* config/alpha/tm-alpha.h: Move alpha_software_single_step
[deliverable/binutils-gdb.git] / gdb / rs6000-tdep.c
CommitLineData
c906108c 1/* Target-dependent code for GDB, the GNU debugger.
b6ba6518 2 Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
2a873819 3 1998, 1999, 2000, 2001, 2002
c906108c
SS
4 Free Software Foundation, Inc.
5
c5aa993b 6 This file is part of GDB.
c906108c 7
c5aa993b
JM
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
c906108c 12
c5aa993b
JM
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
c906108c 17
c5aa993b
JM
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
c906108c
SS
22
23#include "defs.h"
24#include "frame.h"
25#include "inferior.h"
26#include "symtab.h"
27#include "target.h"
28#include "gdbcore.h"
29#include "gdbcmd.h"
30#include "symfile.h"
31#include "objfiles.h"
7a78ae4e 32#include "arch-utils.h"
4e052eda 33#include "regcache.h"
d16aafd8 34#include "doublest.h"
fd0407d6 35#include "value.h"
1fcc0bb8 36#include "parser-defs.h"
7a78ae4e 37
2fccf04a 38#include "libbfd.h" /* for bfd_default_set_arch_mach */
7a78ae4e 39#include "coff/internal.h" /* for libcoff.h */
2fccf04a 40#include "libcoff.h" /* for xcoff_data */
7a78ae4e 41
9aa1e687 42#include "elf-bfd.h"
7a78ae4e 43
6ded7999 44#include "solib-svr4.h"
9aa1e687 45#include "ppc-tdep.h"
7a78ae4e
ND
46
47/* If the kernel has to deliver a signal, it pushes a sigcontext
48 structure on the stack and then calls the signal handler, passing
49 the address of the sigcontext in an argument register. Usually
50 the signal handler doesn't save this register, so we have to
51 access the sigcontext structure via an offset from the signal handler
52 frame.
53 The following constants were determined by experimentation on AIX 3.2. */
54#define SIG_FRAME_PC_OFFSET 96
55#define SIG_FRAME_LR_OFFSET 108
56#define SIG_FRAME_FP_OFFSET 284
57
7a78ae4e
ND
58/* To be used by skip_prologue. */
59
60struct rs6000_framedata
61 {
62 int offset; /* total size of frame --- the distance
63 by which we decrement sp to allocate
64 the frame */
65 int saved_gpr; /* smallest # of saved gpr */
66 int saved_fpr; /* smallest # of saved fpr */
6be8bc0c 67 int saved_vr; /* smallest # of saved vr */
7a78ae4e
ND
68 int alloca_reg; /* alloca register number (frame ptr) */
69 char frameless; /* true if frameless functions. */
70 char nosavedpc; /* true if pc not saved. */
71 int gpr_offset; /* offset of saved gprs from prev sp */
72 int fpr_offset; /* offset of saved fprs from prev sp */
6be8bc0c 73 int vr_offset; /* offset of saved vrs from prev sp */
7a78ae4e
ND
74 int lr_offset; /* offset of saved lr */
75 int cr_offset; /* offset of saved cr */
6be8bc0c 76 int vrsave_offset; /* offset of saved vrsave register */
7a78ae4e
ND
77 };
78
79/* Description of a single register. */
80
81struct reg
82 {
83 char *name; /* name of register */
84 unsigned char sz32; /* size on 32-bit arch, 0 if nonextant */
85 unsigned char sz64; /* size on 64-bit arch, 0 if nonextant */
86 unsigned char fpr; /* whether register is floating-point */
87 };
88
7a78ae4e
ND
89/* Return the current architecture's gdbarch_tdep structure. */
90
91#define TDEP gdbarch_tdep (current_gdbarch)
c906108c
SS
92
93/* Breakpoint shadows for the single step instructions will be kept here. */
94
c5aa993b
JM
95static struct sstep_breaks
96 {
97 /* Address, or 0 if this is not in use. */
98 CORE_ADDR address;
99 /* Shadow contents. */
100 char data[4];
101 }
102stepBreaks[2];
c906108c
SS
103
104/* Hook for determining the TOC address when calling functions in the
105 inferior under AIX. The initialization code in rs6000-nat.c sets
106 this hook to point to find_toc_address. */
107
7a78ae4e
ND
108CORE_ADDR (*rs6000_find_toc_address_hook) (CORE_ADDR) = NULL;
109
110/* Hook to set the current architecture when starting a child process.
111 rs6000-nat.c sets this. */
112
113void (*rs6000_set_host_arch_hook) (int) = NULL;
c906108c
SS
114
115/* Static function prototypes */
116
a14ed312
KB
117static CORE_ADDR branch_dest (int opcode, int instr, CORE_ADDR pc,
118 CORE_ADDR safety);
077276e8
KB
119static CORE_ADDR skip_prologue (CORE_ADDR, CORE_ADDR,
120 struct rs6000_framedata *);
7a78ae4e
ND
121static void frame_get_saved_regs (struct frame_info * fi,
122 struct rs6000_framedata * fdatap);
123static CORE_ADDR frame_initial_stack_address (struct frame_info *);
c906108c 124
7a78ae4e 125/* Read a LEN-byte address from debugged memory address MEMADDR. */
c906108c 126
7a78ae4e
ND
127static CORE_ADDR
128read_memory_addr (CORE_ADDR memaddr, int len)
129{
130 return read_memory_unsigned_integer (memaddr, len);
131}
c906108c 132
7a78ae4e
ND
133static CORE_ADDR
134rs6000_skip_prologue (CORE_ADDR pc)
b83266a0
SS
135{
136 struct rs6000_framedata frame;
077276e8 137 pc = skip_prologue (pc, 0, &frame);
b83266a0
SS
138 return pc;
139}
140
141
c906108c
SS
142/* Fill in fi->saved_regs */
143
144struct frame_extra_info
145{
146 /* Functions calling alloca() change the value of the stack
147 pointer. We need to use initial stack pointer (which is saved in
148 r31 by gcc) in such cases. If a compiler emits traceback table,
149 then we should use the alloca register specified in traceback
150 table. FIXME. */
c5aa993b 151 CORE_ADDR initial_sp; /* initial stack pointer. */
c906108c
SS
152};
153
9aa1e687 154void
7a78ae4e 155rs6000_init_extra_frame_info (int fromleaf, struct frame_info *fi)
c906108c 156{
c5aa993b 157 fi->extra_info = (struct frame_extra_info *)
c906108c
SS
158 frame_obstack_alloc (sizeof (struct frame_extra_info));
159 fi->extra_info->initial_sp = 0;
160 if (fi->next != (CORE_ADDR) 0
161 && fi->pc < TEXT_SEGMENT_BASE)
7a292a7a 162 /* We're in get_prev_frame */
c906108c
SS
163 /* and this is a special signal frame. */
164 /* (fi->pc will be some low address in the kernel, */
165 /* to which the signal handler returns). */
166 fi->signal_handler_caller = 1;
167}
168
7a78ae4e
ND
169/* Put here the code to store, into a struct frame_saved_regs,
170 the addresses of the saved registers of frame described by FRAME_INFO.
171 This includes special registers such as pc and fp saved in special
172 ways in the stack frame. sp is even more special:
173 the address we return for it IS the sp for the next frame. */
c906108c 174
7a78ae4e
ND
175/* In this implementation for RS/6000, we do *not* save sp. I am
176 not sure if it will be needed. The following function takes care of gpr's
177 and fpr's only. */
178
9aa1e687 179void
7a78ae4e 180rs6000_frame_init_saved_regs (struct frame_info *fi)
c906108c
SS
181{
182 frame_get_saved_regs (fi, NULL);
183}
184
7a78ae4e
ND
185static CORE_ADDR
186rs6000_frame_args_address (struct frame_info *fi)
c906108c
SS
187{
188 if (fi->extra_info->initial_sp != 0)
189 return fi->extra_info->initial_sp;
190 else
191 return frame_initial_stack_address (fi);
192}
193
7a78ae4e
ND
194/* Immediately after a function call, return the saved pc.
195 Can't go through the frames for this because on some machines
196 the new frame is not set up until the new function executes
197 some instructions. */
198
199static CORE_ADDR
200rs6000_saved_pc_after_call (struct frame_info *fi)
201{
2188cbdd 202 return read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum);
7a78ae4e 203}
c906108c
SS
204
205/* Calculate the destination of a branch/jump. Return -1 if not a branch. */
206
207static CORE_ADDR
7a78ae4e 208branch_dest (int opcode, int instr, CORE_ADDR pc, CORE_ADDR safety)
c906108c
SS
209{
210 CORE_ADDR dest;
211 int immediate;
212 int absolute;
213 int ext_op;
214
215 absolute = (int) ((instr >> 1) & 1);
216
c5aa993b
JM
217 switch (opcode)
218 {
219 case 18:
220 immediate = ((instr & ~3) << 6) >> 6; /* br unconditional */
221 if (absolute)
222 dest = immediate;
223 else
224 dest = pc + immediate;
225 break;
226
227 case 16:
228 immediate = ((instr & ~3) << 16) >> 16; /* br conditional */
229 if (absolute)
230 dest = immediate;
231 else
232 dest = pc + immediate;
233 break;
234
235 case 19:
236 ext_op = (instr >> 1) & 0x3ff;
237
238 if (ext_op == 16) /* br conditional register */
239 {
2188cbdd 240 dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum) & ~3;
c5aa993b
JM
241
242 /* If we are about to return from a signal handler, dest is
243 something like 0x3c90. The current frame is a signal handler
244 caller frame, upon completion of the sigreturn system call
245 execution will return to the saved PC in the frame. */
246 if (dest < TEXT_SEGMENT_BASE)
247 {
248 struct frame_info *fi;
249
250 fi = get_current_frame ();
251 if (fi != NULL)
7a78ae4e
ND
252 dest = read_memory_addr (fi->frame + SIG_FRAME_PC_OFFSET,
253 TDEP->wordsize);
c5aa993b
JM
254 }
255 }
256
257 else if (ext_op == 528) /* br cond to count reg */
258 {
2188cbdd 259 dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_ctr_regnum) & ~3;
c5aa993b
JM
260
261 /* If we are about to execute a system call, dest is something
262 like 0x22fc or 0x3b00. Upon completion the system call
263 will return to the address in the link register. */
264 if (dest < TEXT_SEGMENT_BASE)
2188cbdd 265 dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum) & ~3;
c5aa993b
JM
266 }
267 else
268 return -1;
269 break;
c906108c 270
c5aa993b
JM
271 default:
272 return -1;
273 }
c906108c
SS
274 return (dest < TEXT_SEGMENT_BASE) ? safety : dest;
275}
276
277
278/* Sequence of bytes for breakpoint instruction. */
279
280#define BIG_BREAKPOINT { 0x7d, 0x82, 0x10, 0x08 }
281#define LITTLE_BREAKPOINT { 0x08, 0x10, 0x82, 0x7d }
282
f4f9705a 283const static unsigned char *
7a78ae4e 284rs6000_breakpoint_from_pc (CORE_ADDR *bp_addr, int *bp_size)
c906108c
SS
285{
286 static unsigned char big_breakpoint[] = BIG_BREAKPOINT;
287 static unsigned char little_breakpoint[] = LITTLE_BREAKPOINT;
288 *bp_size = 4;
d7449b42 289 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
c906108c
SS
290 return big_breakpoint;
291 else
292 return little_breakpoint;
293}
294
295
296/* AIX does not support PT_STEP. Simulate it. */
297
298void
379d08a1
AC
299rs6000_software_single_step (enum target_signal signal,
300 int insert_breakpoints_p)
c906108c 301{
7c40d541
KB
302 CORE_ADDR dummy;
303 int breakp_sz;
f4f9705a 304 const char *breakp = rs6000_breakpoint_from_pc (&dummy, &breakp_sz);
c906108c
SS
305 int ii, insn;
306 CORE_ADDR loc;
307 CORE_ADDR breaks[2];
308 int opcode;
309
c5aa993b
JM
310 if (insert_breakpoints_p)
311 {
c906108c 312
c5aa993b 313 loc = read_pc ();
c906108c 314
c5aa993b 315 insn = read_memory_integer (loc, 4);
c906108c 316
7c40d541 317 breaks[0] = loc + breakp_sz;
c5aa993b
JM
318 opcode = insn >> 26;
319 breaks[1] = branch_dest (opcode, insn, loc, breaks[0]);
c906108c 320
c5aa993b
JM
321 /* Don't put two breakpoints on the same address. */
322 if (breaks[1] == breaks[0])
323 breaks[1] = -1;
c906108c 324
c5aa993b 325 stepBreaks[1].address = 0;
c906108c 326
c5aa993b
JM
327 for (ii = 0; ii < 2; ++ii)
328 {
c906108c 329
c5aa993b
JM
330 /* ignore invalid breakpoint. */
331 if (breaks[ii] == -1)
332 continue;
7c40d541 333 target_insert_breakpoint (breaks[ii], stepBreaks[ii].data);
c5aa993b
JM
334 stepBreaks[ii].address = breaks[ii];
335 }
c906108c 336
c5aa993b
JM
337 }
338 else
339 {
c906108c 340
c5aa993b
JM
341 /* remove step breakpoints. */
342 for (ii = 0; ii < 2; ++ii)
343 if (stepBreaks[ii].address != 0)
7c40d541
KB
344 target_remove_breakpoint (stepBreaks[ii].address,
345 stepBreaks[ii].data);
c5aa993b 346 }
c906108c 347 errno = 0; /* FIXME, don't ignore errors! */
c5aa993b 348 /* What errors? {read,write}_memory call error(). */
c906108c
SS
349}
350
351
352/* return pc value after skipping a function prologue and also return
353 information about a function frame.
354
355 in struct rs6000_framedata fdata:
c5aa993b
JM
356 - frameless is TRUE, if function does not have a frame.
357 - nosavedpc is TRUE, if function does not save %pc value in its frame.
358 - offset is the initial size of this stack frame --- the amount by
359 which we decrement the sp to allocate the frame.
360 - saved_gpr is the number of the first saved gpr.
361 - saved_fpr is the number of the first saved fpr.
6be8bc0c 362 - saved_vr is the number of the first saved vr.
c5aa993b
JM
363 - alloca_reg is the number of the register used for alloca() handling.
364 Otherwise -1.
365 - gpr_offset is the offset of the first saved gpr from the previous frame.
366 - fpr_offset is the offset of the first saved fpr from the previous frame.
6be8bc0c 367 - vr_offset is the offset of the first saved vr from the previous frame.
c5aa993b
JM
368 - lr_offset is the offset of the saved lr
369 - cr_offset is the offset of the saved cr
6be8bc0c 370 - vrsave_offset is the offset of the saved vrsave register
c5aa993b 371 */
c906108c
SS
372
373#define SIGNED_SHORT(x) \
374 ((sizeof (short) == 2) \
375 ? ((int)(short)(x)) \
376 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
377
378#define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
379
55d05f3b
KB
380/* Limit the number of skipped non-prologue instructions, as the examining
381 of the prologue is expensive. */
382static int max_skip_non_prologue_insns = 10;
383
384/* Given PC representing the starting address of a function, and
385 LIM_PC which is the (sloppy) limit to which to scan when looking
386 for a prologue, attempt to further refine this limit by using
387 the line data in the symbol table. If successful, a better guess
388 on where the prologue ends is returned, otherwise the previous
389 value of lim_pc is returned. */
390static CORE_ADDR
391refine_prologue_limit (CORE_ADDR pc, CORE_ADDR lim_pc)
392{
393 struct symtab_and_line prologue_sal;
394
395 prologue_sal = find_pc_line (pc, 0);
396 if (prologue_sal.line != 0)
397 {
398 int i;
399 CORE_ADDR addr = prologue_sal.end;
400
401 /* Handle the case in which compiler's optimizer/scheduler
402 has moved instructions into the prologue. We scan ahead
403 in the function looking for address ranges whose corresponding
404 line number is less than or equal to the first one that we
405 found for the function. (It can be less than when the
406 scheduler puts a body instruction before the first prologue
407 instruction.) */
408 for (i = 2 * max_skip_non_prologue_insns;
409 i > 0 && (lim_pc == 0 || addr < lim_pc);
410 i--)
411 {
412 struct symtab_and_line sal;
413
414 sal = find_pc_line (addr, 0);
415 if (sal.line == 0)
416 break;
417 if (sal.line <= prologue_sal.line
418 && sal.symtab == prologue_sal.symtab)
419 {
420 prologue_sal = sal;
421 }
422 addr = sal.end;
423 }
424
425 if (lim_pc == 0 || prologue_sal.end < lim_pc)
426 lim_pc = prologue_sal.end;
427 }
428 return lim_pc;
429}
430
431
7a78ae4e 432static CORE_ADDR
077276e8 433skip_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct rs6000_framedata *fdata)
c906108c
SS
434{
435 CORE_ADDR orig_pc = pc;
55d05f3b 436 CORE_ADDR last_prologue_pc = pc;
6be8bc0c 437 CORE_ADDR li_found_pc = 0;
c906108c
SS
438 char buf[4];
439 unsigned long op;
440 long offset = 0;
6be8bc0c 441 long vr_saved_offset = 0;
482ca3f5
KB
442 int lr_reg = -1;
443 int cr_reg = -1;
6be8bc0c
EZ
444 int vr_reg = -1;
445 int vrsave_reg = -1;
c906108c
SS
446 int reg;
447 int framep = 0;
448 int minimal_toc_loaded = 0;
ddb20c56 449 int prev_insn_was_prologue_insn = 1;
55d05f3b
KB
450 int num_skip_non_prologue_insns = 0;
451
452 /* Attempt to find the end of the prologue when no limit is specified.
453 Note that refine_prologue_limit() has been written so that it may
454 be used to "refine" the limits of non-zero PC values too, but this
455 is only safe if we 1) trust the line information provided by the
456 compiler and 2) iterate enough to actually find the end of the
457 prologue.
458
459 It may become a good idea at some point (for both performance and
460 accuracy) to unconditionally call refine_prologue_limit(). But,
461 until we can make a clear determination that this is beneficial,
462 we'll play it safe and only use it to obtain a limit when none
463 has been specified. */
464 if (lim_pc == 0)
465 lim_pc = refine_prologue_limit (pc, lim_pc);
c906108c 466
ddb20c56 467 memset (fdata, 0, sizeof (struct rs6000_framedata));
c906108c
SS
468 fdata->saved_gpr = -1;
469 fdata->saved_fpr = -1;
6be8bc0c 470 fdata->saved_vr = -1;
c906108c
SS
471 fdata->alloca_reg = -1;
472 fdata->frameless = 1;
473 fdata->nosavedpc = 1;
474
55d05f3b 475 for (;; pc += 4)
c906108c 476 {
ddb20c56
KB
477 /* Sometimes it isn't clear if an instruction is a prologue
478 instruction or not. When we encounter one of these ambiguous
479 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
480 Otherwise, we'll assume that it really is a prologue instruction. */
481 if (prev_insn_was_prologue_insn)
482 last_prologue_pc = pc;
55d05f3b
KB
483
484 /* Stop scanning if we've hit the limit. */
485 if (lim_pc != 0 && pc >= lim_pc)
486 break;
487
ddb20c56
KB
488 prev_insn_was_prologue_insn = 1;
489
55d05f3b 490 /* Fetch the instruction and convert it to an integer. */
ddb20c56
KB
491 if (target_read_memory (pc, buf, 4))
492 break;
493 op = extract_signed_integer (buf, 4);
c906108c 494
c5aa993b
JM
495 if ((op & 0xfc1fffff) == 0x7c0802a6)
496 { /* mflr Rx */
497 lr_reg = (op & 0x03e00000) | 0x90010000;
498 continue;
c906108c 499
c5aa993b
JM
500 }
501 else if ((op & 0xfc1fffff) == 0x7c000026)
502 { /* mfcr Rx */
503 cr_reg = (op & 0x03e00000) | 0x90010000;
504 continue;
c906108c 505
c906108c 506 }
c5aa993b
JM
507 else if ((op & 0xfc1f0000) == 0xd8010000)
508 { /* stfd Rx,NUM(r1) */
509 reg = GET_SRC_REG (op);
510 if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg)
511 {
512 fdata->saved_fpr = reg;
513 fdata->fpr_offset = SIGNED_SHORT (op) + offset;
514 }
515 continue;
c906108c 516
c5aa993b
JM
517 }
518 else if (((op & 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
7a78ae4e
ND
519 (((op & 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
520 (op & 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
521 (op & 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
c5aa993b
JM
522 {
523
524 reg = GET_SRC_REG (op);
525 if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg)
526 {
527 fdata->saved_gpr = reg;
7a78ae4e
ND
528 if ((op & 0xfc1f0003) == 0xf8010000)
529 op = (op >> 1) << 1;
c5aa993b
JM
530 fdata->gpr_offset = SIGNED_SHORT (op) + offset;
531 }
532 continue;
c906108c 533
ddb20c56
KB
534 }
535 else if ((op & 0xffff0000) == 0x60000000)
536 {
537 /* nop */
538 /* Allow nops in the prologue, but do not consider them to
539 be part of the prologue unless followed by other prologue
540 instructions. */
541 prev_insn_was_prologue_insn = 0;
542 continue;
543
c906108c 544 }
c5aa993b
JM
545 else if ((op & 0xffff0000) == 0x3c000000)
546 { /* addis 0,0,NUM, used
547 for >= 32k frames */
548 fdata->offset = (op & 0x0000ffff) << 16;
549 fdata->frameless = 0;
550 continue;
551
552 }
553 else if ((op & 0xffff0000) == 0x60000000)
554 { /* ori 0,0,NUM, 2nd ha
555 lf of >= 32k frames */
556 fdata->offset |= (op & 0x0000ffff);
557 fdata->frameless = 0;
558 continue;
559
560 }
482ca3f5 561 else if (lr_reg != -1 && (op & 0xffff0000) == lr_reg)
c5aa993b
JM
562 { /* st Rx,NUM(r1)
563 where Rx == lr */
564 fdata->lr_offset = SIGNED_SHORT (op) + offset;
565 fdata->nosavedpc = 0;
566 lr_reg = 0;
567 continue;
568
569 }
482ca3f5 570 else if (cr_reg != -1 && (op & 0xffff0000) == cr_reg)
c5aa993b
JM
571 { /* st Rx,NUM(r1)
572 where Rx == cr */
573 fdata->cr_offset = SIGNED_SHORT (op) + offset;
574 cr_reg = 0;
575 continue;
576
577 }
578 else if (op == 0x48000005)
579 { /* bl .+4 used in
580 -mrelocatable */
581 continue;
582
583 }
584 else if (op == 0x48000004)
585 { /* b .+4 (xlc) */
586 break;
587
c5aa993b 588 }
6be8bc0c
EZ
589 else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
590 in V.4 -mminimal-toc */
c5aa993b
JM
591 (op & 0xffff0000) == 0x3bde0000)
592 { /* addi 30,30,foo@l */
593 continue;
c906108c 594
c5aa993b
JM
595 }
596 else if ((op & 0xfc000001) == 0x48000001)
597 { /* bl foo,
598 to save fprs??? */
c906108c 599
c5aa993b 600 fdata->frameless = 0;
6be8bc0c
EZ
601 /* Don't skip over the subroutine call if it is not within
602 the first three instructions of the prologue. */
c5aa993b
JM
603 if ((pc - orig_pc) > 8)
604 break;
605
606 op = read_memory_integer (pc + 4, 4);
607
6be8bc0c
EZ
608 /* At this point, make sure this is not a trampoline
609 function (a function that simply calls another functions,
610 and nothing else). If the next is not a nop, this branch
611 was part of the function prologue. */
c5aa993b
JM
612
613 if (op == 0x4def7b82 || op == 0) /* crorc 15, 15, 15 */
614 break; /* don't skip over
615 this branch */
616 continue;
617
618 /* update stack pointer */
619 }
7a78ae4e
ND
620 else if ((op & 0xffff0000) == 0x94210000 || /* stu r1,NUM(r1) */
621 (op & 0xffff0003) == 0xf8210001) /* stdu r1,NUM(r1) */
622 {
c5aa993b 623 fdata->frameless = 0;
7a78ae4e
ND
624 if ((op & 0xffff0003) == 0xf8210001)
625 op = (op >> 1) << 1;
c5aa993b
JM
626 fdata->offset = SIGNED_SHORT (op);
627 offset = fdata->offset;
628 continue;
629
630 }
631 else if (op == 0x7c21016e)
632 { /* stwux 1,1,0 */
633 fdata->frameless = 0;
634 offset = fdata->offset;
635 continue;
636
637 /* Load up minimal toc pointer */
638 }
639 else if ((op >> 22) == 0x20f
640 && !minimal_toc_loaded)
641 { /* l r31,... or l r30,... */
642 minimal_toc_loaded = 1;
643 continue;
644
f6077098
KB
645 /* move parameters from argument registers to local variable
646 registers */
647 }
648 else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
649 (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
650 (((op >> 21) & 31) <= 10) &&
651 (((op >> 16) & 31) >= fdata->saved_gpr)) /* Rx: local var reg */
652 {
653 continue;
654
c5aa993b
JM
655 /* store parameters in stack */
656 }
6be8bc0c 657 else if ((op & 0xfc1f0003) == 0xf8010000 || /* std rx,NUM(r1) */
c5aa993b 658 (op & 0xfc1f0000) == 0xd8010000 || /* stfd Rx,NUM(r1) */
7a78ae4e
ND
659 (op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
660 {
c5aa993b 661 continue;
c906108c 662
c5aa993b
JM
663 /* store parameters in stack via frame pointer */
664 }
665 else if (framep &&
666 ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r1) */
667 (op & 0xfc1f0000) == 0xd81f0000 || /* stfd Rx,NUM(r1) */
668 (op & 0xfc1f0000) == 0xfc1f0000))
669 { /* frsp, fp?,NUM(r1) */
670 continue;
671
672 /* Set up frame pointer */
673 }
674 else if (op == 0x603f0000 /* oril r31, r1, 0x0 */
675 || op == 0x7c3f0b78)
676 { /* mr r31, r1 */
677 fdata->frameless = 0;
678 framep = 1;
679 fdata->alloca_reg = 31;
680 continue;
681
682 /* Another way to set up the frame pointer. */
683 }
684 else if ((op & 0xfc1fffff) == 0x38010000)
685 { /* addi rX, r1, 0x0 */
686 fdata->frameless = 0;
687 framep = 1;
688 fdata->alloca_reg = (op & ~0x38010000) >> 21;
689 continue;
c5aa993b 690 }
6be8bc0c
EZ
691 /* AltiVec related instructions. */
692 /* Store the vrsave register (spr 256) in another register for
693 later manipulation, or load a register into the vrsave
694 register. 2 instructions are used: mfvrsave and
695 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
696 and mtspr SPR256, Rn. */
697 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
698 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
699 else if ((op & 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
700 {
701 vrsave_reg = GET_SRC_REG (op);
702 continue;
703 }
704 else if ((op & 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
705 {
706 continue;
707 }
708 /* Store the register where vrsave was saved to onto the stack:
709 rS is the register where vrsave was stored in a previous
710 instruction. */
711 /* 100100 sssss 00001 dddddddd dddddddd */
712 else if ((op & 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
713 {
714 if (vrsave_reg == GET_SRC_REG (op))
715 {
716 fdata->vrsave_offset = SIGNED_SHORT (op) + offset;
717 vrsave_reg = -1;
718 }
719 continue;
720 }
721 /* Compute the new value of vrsave, by modifying the register
722 where vrsave was saved to. */
723 else if (((op & 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
724 || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
725 {
726 continue;
727 }
728 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
729 in a pair of insns to save the vector registers on the
730 stack. */
731 /* 001110 00000 00000 iiii iiii iiii iiii */
732 else if ((op & 0xffff0000) == 0x38000000) /* li r0, SIMM */
733 {
734 li_found_pc = pc;
735 vr_saved_offset = SIGNED_SHORT (op);
736 }
737 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
738 /* 011111 sssss 11111 00000 00111001110 */
739 else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
740 {
741 if (pc == (li_found_pc + 4))
742 {
743 vr_reg = GET_SRC_REG (op);
744 /* If this is the first vector reg to be saved, or if
745 it has a lower number than others previously seen,
746 reupdate the frame info. */
747 if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg)
748 {
749 fdata->saved_vr = vr_reg;
750 fdata->vr_offset = vr_saved_offset + offset;
751 }
752 vr_saved_offset = -1;
753 vr_reg = -1;
754 li_found_pc = 0;
755 }
756 }
757 /* End AltiVec related instructions. */
c5aa993b
JM
758 else
759 {
55d05f3b
KB
760 /* Not a recognized prologue instruction.
761 Handle optimizer code motions into the prologue by continuing
762 the search if we have no valid frame yet or if the return
763 address is not yet saved in the frame. */
764 if (fdata->frameless == 0
765 && (lr_reg == -1 || fdata->nosavedpc == 0))
766 break;
767
768 if (op == 0x4e800020 /* blr */
769 || op == 0x4e800420) /* bctr */
770 /* Do not scan past epilogue in frameless functions or
771 trampolines. */
772 break;
773 if ((op & 0xf4000000) == 0x40000000) /* bxx */
774 /* Never skip branches. */
775 break;
776
777 if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns)
778 /* Do not scan too many insns, scanning insns is expensive with
779 remote targets. */
780 break;
781
782 /* Continue scanning. */
783 prev_insn_was_prologue_insn = 0;
784 continue;
c5aa993b 785 }
c906108c
SS
786 }
787
788#if 0
789/* I have problems with skipping over __main() that I need to address
790 * sometime. Previously, I used to use misc_function_vector which
791 * didn't work as well as I wanted to be. -MGO */
792
793 /* If the first thing after skipping a prolog is a branch to a function,
794 this might be a call to an initializer in main(), introduced by gcc2.
795 We'd like to skip over it as well. Fortunately, xlc does some extra
796 work before calling a function right after a prologue, thus we can
797 single out such gcc2 behaviour. */
c906108c 798
c906108c 799
c5aa993b
JM
800 if ((op & 0xfc000001) == 0x48000001)
801 { /* bl foo, an initializer function? */
802 op = read_memory_integer (pc + 4, 4);
803
804 if (op == 0x4def7b82)
805 { /* cror 0xf, 0xf, 0xf (nop) */
c906108c 806
c5aa993b
JM
807 /* check and see if we are in main. If so, skip over this initializer
808 function as well. */
c906108c 809
c5aa993b 810 tmp = find_pc_misc_function (pc);
51cc5b07 811 if (tmp >= 0 && STREQ (misc_function_vector[tmp].name, main_name ()))
c5aa993b
JM
812 return pc + 8;
813 }
c906108c 814 }
c906108c 815#endif /* 0 */
c5aa993b
JM
816
817 fdata->offset = -fdata->offset;
ddb20c56 818 return last_prologue_pc;
c906108c
SS
819}
820
821
822/*************************************************************************
f6077098 823 Support for creating pushing a dummy frame into the stack, and popping
c906108c
SS
824 frames, etc.
825*************************************************************************/
826
c906108c 827
7a78ae4e 828/* Pop the innermost frame, go back to the caller. */
c5aa993b 829
c906108c 830static void
7a78ae4e 831rs6000_pop_frame (void)
c906108c 832{
470d5666 833 CORE_ADDR pc, lr, sp, prev_sp, addr; /* %pc, %lr, %sp */
c906108c
SS
834 struct rs6000_framedata fdata;
835 struct frame_info *frame = get_current_frame ();
470d5666 836 int ii, wordsize;
c906108c
SS
837
838 pc = read_pc ();
839 sp = FRAME_FP (frame);
840
58223630 841 if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame))
c906108c 842 {
7a78ae4e
ND
843 generic_pop_dummy_frame ();
844 flush_cached_frames ();
845 return;
c906108c
SS
846 }
847
848 /* Make sure that all registers are valid. */
849 read_register_bytes (0, NULL, REGISTER_BYTES);
850
851 /* figure out previous %pc value. If the function is frameless, it is
852 still in the link register, otherwise walk the frames and retrieve the
853 saved %pc value in the previous frame. */
854
855 addr = get_pc_function_start (frame->pc);
077276e8 856 (void) skip_prologue (addr, frame->pc, &fdata);
c906108c 857
7a78ae4e 858 wordsize = TDEP->wordsize;
c906108c
SS
859 if (fdata.frameless)
860 prev_sp = sp;
861 else
7a78ae4e 862 prev_sp = read_memory_addr (sp, wordsize);
c906108c 863 if (fdata.lr_offset == 0)
2188cbdd 864 lr = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum);
c906108c 865 else
7a78ae4e 866 lr = read_memory_addr (prev_sp + fdata.lr_offset, wordsize);
c906108c
SS
867
868 /* reset %pc value. */
869 write_register (PC_REGNUM, lr);
870
871 /* reset register values if any was saved earlier. */
872
873 if (fdata.saved_gpr != -1)
874 {
875 addr = prev_sp + fdata.gpr_offset;
c5aa993b
JM
876 for (ii = fdata.saved_gpr; ii <= 31; ++ii)
877 {
7a78ae4e
ND
878 read_memory (addr, &registers[REGISTER_BYTE (ii)], wordsize);
879 addr += wordsize;
c5aa993b 880 }
c906108c
SS
881 }
882
883 if (fdata.saved_fpr != -1)
884 {
885 addr = prev_sp + fdata.fpr_offset;
c5aa993b
JM
886 for (ii = fdata.saved_fpr; ii <= 31; ++ii)
887 {
888 read_memory (addr, &registers[REGISTER_BYTE (ii + FP0_REGNUM)], 8);
889 addr += 8;
890 }
c906108c
SS
891 }
892
893 write_register (SP_REGNUM, prev_sp);
894 target_store_registers (-1);
895 flush_cached_frames ();
896}
897
7a78ae4e
ND
898/* Fixup the call sequence of a dummy function, with the real function
899 address. Its arguments will be passed by gdb. */
c906108c 900
7a78ae4e
ND
901static void
902rs6000_fix_call_dummy (char *dummyname, CORE_ADDR pc, CORE_ADDR fun,
ea7c478f 903 int nargs, struct value **args, struct type *type,
7a78ae4e 904 int gcc_p)
c906108c 905{
c906108c
SS
906 int ii;
907 CORE_ADDR target_addr;
908
7a78ae4e 909 if (rs6000_find_toc_address_hook != NULL)
f6077098 910 {
7a78ae4e 911 CORE_ADDR tocvalue = (*rs6000_find_toc_address_hook) (fun);
2188cbdd
EZ
912 write_register (gdbarch_tdep (current_gdbarch)->ppc_toc_regnum,
913 tocvalue);
f6077098 914 }
c906108c
SS
915}
916
7a78ae4e 917/* Pass the arguments in either registers, or in the stack. In RS/6000,
c906108c
SS
918 the first eight words of the argument list (that might be less than
919 eight parameters if some parameters occupy more than one word) are
7a78ae4e 920 passed in r3..r10 registers. float and double parameters are
c906108c
SS
921 passed in fpr's, in addition to that. Rest of the parameters if any
922 are passed in user stack. There might be cases in which half of the
923 parameter is copied into registers, the other half is pushed into
924 stack.
925
7a78ae4e
ND
926 Stack must be aligned on 64-bit boundaries when synthesizing
927 function calls.
928
c906108c
SS
929 If the function is returning a structure, then the return address is passed
930 in r3, then the first 7 words of the parameters can be passed in registers,
931 starting from r4. */
932
7a78ae4e 933static CORE_ADDR
ea7c478f 934rs6000_push_arguments (int nargs, struct value **args, CORE_ADDR sp,
7a78ae4e 935 int struct_return, CORE_ADDR struct_addr)
c906108c
SS
936{
937 int ii;
938 int len = 0;
c5aa993b
JM
939 int argno; /* current argument number */
940 int argbytes; /* current argument byte */
941 char tmp_buffer[50];
942 int f_argno = 0; /* current floating point argno */
7a78ae4e 943 int wordsize = TDEP->wordsize;
c906108c 944
ea7c478f 945 struct value *arg = 0;
c906108c
SS
946 struct type *type;
947
948 CORE_ADDR saved_sp;
949
c906108c
SS
950 /* The first eight words of ther arguments are passed in registers. Copy
951 them appropriately.
952
953 If the function is returning a `struct', then the first word (which
954 will be passed in r3) is used for struct return address. In that
955 case we should advance one word and start from r4 register to copy
956 parameters. */
957
c5aa993b 958 ii = struct_return ? 1 : 0;
c906108c
SS
959
960/*
c5aa993b
JM
961 effectively indirect call... gcc does...
962
963 return_val example( float, int);
964
965 eabi:
966 float in fp0, int in r3
967 offset of stack on overflow 8/16
968 for varargs, must go by type.
969 power open:
970 float in r3&r4, int in r5
971 offset of stack on overflow different
972 both:
973 return in r3 or f0. If no float, must study how gcc emulates floats;
974 pay attention to arg promotion.
975 User may have to cast\args to handle promotion correctly
976 since gdb won't know if prototype supplied or not.
977 */
c906108c 978
c5aa993b
JM
979 for (argno = 0, argbytes = 0; argno < nargs && ii < 8; ++ii)
980 {
f6077098 981 int reg_size = REGISTER_RAW_SIZE (ii + 3);
c5aa993b
JM
982
983 arg = args[argno];
984 type = check_typedef (VALUE_TYPE (arg));
985 len = TYPE_LENGTH (type);
986
987 if (TYPE_CODE (type) == TYPE_CODE_FLT)
988 {
989
990 /* floating point arguments are passed in fpr's, as well as gpr's.
991 There are 13 fpr's reserved for passing parameters. At this point
992 there is no way we would run out of them. */
993
994 if (len > 8)
995 printf_unfiltered (
996 "Fatal Error: a floating point parameter #%d with a size > 8 is found!\n", argno);
997
998 memcpy (&registers[REGISTER_BYTE (FP0_REGNUM + 1 + f_argno)],
999 VALUE_CONTENTS (arg),
1000 len);
1001 ++f_argno;
1002 }
1003
f6077098 1004 if (len > reg_size)
c5aa993b
JM
1005 {
1006
1007 /* Argument takes more than one register. */
1008 while (argbytes < len)
1009 {
f6077098 1010 memset (&registers[REGISTER_BYTE (ii + 3)], 0, reg_size);
c5aa993b
JM
1011 memcpy (&registers[REGISTER_BYTE (ii + 3)],
1012 ((char *) VALUE_CONTENTS (arg)) + argbytes,
f6077098
KB
1013 (len - argbytes) > reg_size
1014 ? reg_size : len - argbytes);
1015 ++ii, argbytes += reg_size;
c5aa993b
JM
1016
1017 if (ii >= 8)
1018 goto ran_out_of_registers_for_arguments;
1019 }
1020 argbytes = 0;
1021 --ii;
1022 }
1023 else
1024 { /* Argument can fit in one register. No problem. */
d7449b42 1025 int adj = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? reg_size - len : 0;
f6077098
KB
1026 memset (&registers[REGISTER_BYTE (ii + 3)], 0, reg_size);
1027 memcpy ((char *)&registers[REGISTER_BYTE (ii + 3)] + adj,
1028 VALUE_CONTENTS (arg), len);
c5aa993b
JM
1029 }
1030 ++argno;
c906108c 1031 }
c906108c
SS
1032
1033ran_out_of_registers_for_arguments:
1034
7a78ae4e 1035 saved_sp = read_sp ();
cc9836a8 1036
7a78ae4e
ND
1037 /* location for 8 parameters are always reserved. */
1038 sp -= wordsize * 8;
f6077098 1039
7a78ae4e
ND
1040 /* another six words for back chain, TOC register, link register, etc. */
1041 sp -= wordsize * 6;
f6077098 1042
7a78ae4e
ND
1043 /* stack pointer must be quadword aligned */
1044 sp &= -16;
c906108c 1045
c906108c
SS
1046 /* if there are more arguments, allocate space for them in
1047 the stack, then push them starting from the ninth one. */
1048
c5aa993b
JM
1049 if ((argno < nargs) || argbytes)
1050 {
1051 int space = 0, jj;
c906108c 1052
c5aa993b
JM
1053 if (argbytes)
1054 {
1055 space += ((len - argbytes + 3) & -4);
1056 jj = argno + 1;
1057 }
1058 else
1059 jj = argno;
c906108c 1060
c5aa993b
JM
1061 for (; jj < nargs; ++jj)
1062 {
ea7c478f 1063 struct value *val = args[jj];
c5aa993b
JM
1064 space += ((TYPE_LENGTH (VALUE_TYPE (val))) + 3) & -4;
1065 }
c906108c 1066
c5aa993b 1067 /* add location required for the rest of the parameters */
f6077098 1068 space = (space + 15) & -16;
c5aa993b 1069 sp -= space;
c906108c 1070
c5aa993b
JM
1071 /* This is another instance we need to be concerned about securing our
1072 stack space. If we write anything underneath %sp (r1), we might conflict
1073 with the kernel who thinks he is free to use this area. So, update %sp
1074 first before doing anything else. */
c906108c 1075
c5aa993b 1076 write_register (SP_REGNUM, sp);
c906108c 1077
c5aa993b
JM
1078 /* if the last argument copied into the registers didn't fit there
1079 completely, push the rest of it into stack. */
c906108c 1080
c5aa993b
JM
1081 if (argbytes)
1082 {
1083 write_memory (sp + 24 + (ii * 4),
1084 ((char *) VALUE_CONTENTS (arg)) + argbytes,
1085 len - argbytes);
1086 ++argno;
1087 ii += ((len - argbytes + 3) & -4) / 4;
1088 }
c906108c 1089
c5aa993b
JM
1090 /* push the rest of the arguments into stack. */
1091 for (; argno < nargs; ++argno)
1092 {
c906108c 1093
c5aa993b
JM
1094 arg = args[argno];
1095 type = check_typedef (VALUE_TYPE (arg));
1096 len = TYPE_LENGTH (type);
c906108c
SS
1097
1098
c5aa993b
JM
1099 /* float types should be passed in fpr's, as well as in the stack. */
1100 if (TYPE_CODE (type) == TYPE_CODE_FLT && f_argno < 13)
1101 {
c906108c 1102
c5aa993b
JM
1103 if (len > 8)
1104 printf_unfiltered (
1105 "Fatal Error: a floating point parameter #%d with a size > 8 is found!\n", argno);
c906108c 1106
c5aa993b
JM
1107 memcpy (&registers[REGISTER_BYTE (FP0_REGNUM + 1 + f_argno)],
1108 VALUE_CONTENTS (arg),
1109 len);
1110 ++f_argno;
1111 }
c906108c 1112
c5aa993b
JM
1113 write_memory (sp + 24 + (ii * 4), (char *) VALUE_CONTENTS (arg), len);
1114 ii += ((len + 3) & -4) / 4;
1115 }
c906108c 1116 }
c906108c
SS
1117 else
1118 /* Secure stack areas first, before doing anything else. */
1119 write_register (SP_REGNUM, sp);
1120
c906108c
SS
1121 /* set back chain properly */
1122 store_address (tmp_buffer, 4, saved_sp);
1123 write_memory (sp, tmp_buffer, 4);
1124
1125 target_store_registers (-1);
1126 return sp;
1127}
c906108c
SS
1128
1129/* Function: ppc_push_return_address (pc, sp)
1130 Set up the return address for the inferior function call. */
1131
7a78ae4e
ND
1132static CORE_ADDR
1133ppc_push_return_address (CORE_ADDR pc, CORE_ADDR sp)
c906108c 1134{
2188cbdd
EZ
1135 write_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum,
1136 CALL_DUMMY_ADDRESS ());
c906108c
SS
1137 return sp;
1138}
1139
7a78ae4e
ND
1140/* Extract a function return value of type TYPE from raw register array
1141 REGBUF, and copy that return value into VALBUF in virtual format. */
c906108c 1142
7a78ae4e
ND
1143static void
1144rs6000_extract_return_value (struct type *valtype, char *regbuf, char *valbuf)
c906108c
SS
1145{
1146 int offset = 0;
1147
c5aa993b
JM
1148 if (TYPE_CODE (valtype) == TYPE_CODE_FLT)
1149 {
c906108c 1150
c5aa993b
JM
1151 double dd;
1152 float ff;
1153 /* floats and doubles are returned in fpr1. fpr's have a size of 8 bytes.
1154 We need to truncate the return value into float size (4 byte) if
1155 necessary. */
c906108c 1156
c5aa993b
JM
1157 if (TYPE_LENGTH (valtype) > 4) /* this is a double */
1158 memcpy (valbuf,
1159 &regbuf[REGISTER_BYTE (FP0_REGNUM + 1)],
1160 TYPE_LENGTH (valtype));
1161 else
1162 { /* float */
1163 memcpy (&dd, &regbuf[REGISTER_BYTE (FP0_REGNUM + 1)], 8);
1164 ff = (float) dd;
1165 memcpy (valbuf, &ff, sizeof (float));
1166 }
1167 }
1168 else
1169 {
1170 /* return value is copied starting from r3. */
d7449b42 1171 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
c5aa993b
JM
1172 && TYPE_LENGTH (valtype) < REGISTER_RAW_SIZE (3))
1173 offset = REGISTER_RAW_SIZE (3) - TYPE_LENGTH (valtype);
1174
1175 memcpy (valbuf,
1176 regbuf + REGISTER_BYTE (3) + offset,
c906108c 1177 TYPE_LENGTH (valtype));
c906108c 1178 }
c906108c
SS
1179}
1180
7a78ae4e 1181/* Keep structure return address in this variable.
c906108c
SS
1182 FIXME: This is a horrid kludge which should not be allowed to continue
1183 living. This only allows a single nested call to a structure-returning
1184 function. Come on, guys! -- gnu@cygnus.com, Aug 92 */
1185
7a78ae4e 1186static CORE_ADDR rs6000_struct_return_address;
c906108c 1187
977adac5
ND
1188/* Return whether handle_inferior_event() should proceed through code
1189 starting at PC in function NAME when stepping.
1190
1191 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
1192 handle memory references that are too distant to fit in instructions
1193 generated by the compiler. For example, if 'foo' in the following
1194 instruction:
1195
1196 lwz r9,foo(r2)
1197
1198 is greater than 32767, the linker might replace the lwz with a branch to
1199 somewhere in @FIX1 that does the load in 2 instructions and then branches
1200 back to where execution should continue.
1201
1202 GDB should silently step over @FIX code, just like AIX dbx does.
1203 Unfortunately, the linker uses the "b" instruction for the branches,
1204 meaning that the link register doesn't get set. Therefore, GDB's usual
1205 step_over_function() mechanism won't work.
1206
1207 Instead, use the IN_SOLIB_RETURN_TRAMPOLINE and SKIP_TRAMPOLINE_CODE hooks
1208 in handle_inferior_event() to skip past @FIX code. */
1209
1210int
1211rs6000_in_solib_return_trampoline (CORE_ADDR pc, char *name)
1212{
1213 return name && !strncmp (name, "@FIX", 4);
1214}
1215
1216/* Skip code that the user doesn't want to see when stepping:
1217
1218 1. Indirect function calls use a piece of trampoline code to do context
1219 switching, i.e. to set the new TOC table. Skip such code if we are on
1220 its first instruction (as when we have single-stepped to here).
1221
1222 2. Skip shared library trampoline code (which is different from
c906108c 1223 indirect function call trampolines).
977adac5
ND
1224
1225 3. Skip bigtoc fixup code.
1226
c906108c 1227 Result is desired PC to step until, or NULL if we are not in
977adac5 1228 code that should be skipped. */
c906108c
SS
1229
1230CORE_ADDR
7a78ae4e 1231rs6000_skip_trampoline_code (CORE_ADDR pc)
c906108c
SS
1232{
1233 register unsigned int ii, op;
977adac5 1234 int rel;
c906108c 1235 CORE_ADDR solib_target_pc;
977adac5 1236 struct minimal_symbol *msymbol;
c906108c 1237
c5aa993b
JM
1238 static unsigned trampoline_code[] =
1239 {
1240 0x800b0000, /* l r0,0x0(r11) */
1241 0x90410014, /* st r2,0x14(r1) */
1242 0x7c0903a6, /* mtctr r0 */
1243 0x804b0004, /* l r2,0x4(r11) */
1244 0x816b0008, /* l r11,0x8(r11) */
1245 0x4e800420, /* bctr */
1246 0x4e800020, /* br */
1247 0
c906108c
SS
1248 };
1249
977adac5
ND
1250 /* Check for bigtoc fixup code. */
1251 msymbol = lookup_minimal_symbol_by_pc (pc);
1252 if (msymbol && rs6000_in_solib_return_trampoline (pc, SYMBOL_NAME (msymbol)))
1253 {
1254 /* Double-check that the third instruction from PC is relative "b". */
1255 op = read_memory_integer (pc + 8, 4);
1256 if ((op & 0xfc000003) == 0x48000000)
1257 {
1258 /* Extract bits 6-29 as a signed 24-bit relative word address and
1259 add it to the containing PC. */
1260 rel = ((int)(op << 6) >> 6);
1261 return pc + 8 + rel;
1262 }
1263 }
1264
c906108c
SS
1265 /* If pc is in a shared library trampoline, return its target. */
1266 solib_target_pc = find_solib_trampoline_target (pc);
1267 if (solib_target_pc)
1268 return solib_target_pc;
1269
c5aa993b
JM
1270 for (ii = 0; trampoline_code[ii]; ++ii)
1271 {
1272 op = read_memory_integer (pc + (ii * 4), 4);
1273 if (op != trampoline_code[ii])
1274 return 0;
1275 }
1276 ii = read_register (11); /* r11 holds destination addr */
7a78ae4e 1277 pc = read_memory_addr (ii, TDEP->wordsize); /* (r11) value */
c906108c
SS
1278 return pc;
1279}
1280
1281/* Determines whether the function FI has a frame on the stack or not. */
1282
9aa1e687 1283int
c877c8e6 1284rs6000_frameless_function_invocation (struct frame_info *fi)
c906108c
SS
1285{
1286 CORE_ADDR func_start;
1287 struct rs6000_framedata fdata;
1288
1289 /* Don't even think about framelessness except on the innermost frame
1290 or if the function was interrupted by a signal. */
1291 if (fi->next != NULL && !fi->next->signal_handler_caller)
1292 return 0;
c5aa993b 1293
c906108c
SS
1294 func_start = get_pc_function_start (fi->pc);
1295
1296 /* If we failed to find the start of the function, it is a mistake
1297 to inspect the instructions. */
1298
1299 if (!func_start)
1300 {
1301 /* A frame with a zero PC is usually created by dereferencing a NULL
c5aa993b
JM
1302 function pointer, normally causing an immediate core dump of the
1303 inferior. Mark function as frameless, as the inferior has no chance
1304 of setting up a stack frame. */
c906108c
SS
1305 if (fi->pc == 0)
1306 return 1;
1307 else
1308 return 0;
1309 }
1310
077276e8 1311 (void) skip_prologue (func_start, fi->pc, &fdata);
c906108c
SS
1312 return fdata.frameless;
1313}
1314
1315/* Return the PC saved in a frame */
1316
9aa1e687 1317CORE_ADDR
c877c8e6 1318rs6000_frame_saved_pc (struct frame_info *fi)
c906108c
SS
1319{
1320 CORE_ADDR func_start;
1321 struct rs6000_framedata fdata;
a88376a3
KB
1322 struct gdbarch_tdep *tdep = TDEP;
1323 int wordsize = tdep->wordsize;
c906108c
SS
1324
1325 if (fi->signal_handler_caller)
7a78ae4e 1326 return read_memory_addr (fi->frame + SIG_FRAME_PC_OFFSET, wordsize);
c906108c 1327
7a78ae4e
ND
1328 if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
1329 return generic_read_register_dummy (fi->pc, fi->frame, PC_REGNUM);
c906108c
SS
1330
1331 func_start = get_pc_function_start (fi->pc);
1332
1333 /* If we failed to find the start of the function, it is a mistake
1334 to inspect the instructions. */
1335 if (!func_start)
1336 return 0;
1337
077276e8 1338 (void) skip_prologue (func_start, fi->pc, &fdata);
c906108c
SS
1339
1340 if (fdata.lr_offset == 0 && fi->next != NULL)
1341 {
1342 if (fi->next->signal_handler_caller)
7a78ae4e
ND
1343 return read_memory_addr (fi->next->frame + SIG_FRAME_LR_OFFSET,
1344 wordsize);
c906108c 1345 else
a88376a3 1346 return read_memory_addr (FRAME_CHAIN (fi) + tdep->lr_frame_offset,
7a78ae4e 1347 wordsize);
c906108c
SS
1348 }
1349
1350 if (fdata.lr_offset == 0)
2188cbdd 1351 return read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum);
c906108c 1352
7a78ae4e 1353 return read_memory_addr (FRAME_CHAIN (fi) + fdata.lr_offset, wordsize);
c906108c
SS
1354}
1355
1356/* If saved registers of frame FI are not known yet, read and cache them.
1357 &FDATAP contains rs6000_framedata; TDATAP can be NULL,
1358 in which case the framedata are read. */
1359
1360static void
7a78ae4e 1361frame_get_saved_regs (struct frame_info *fi, struct rs6000_framedata *fdatap)
c906108c 1362{
c5aa993b 1363 CORE_ADDR frame_addr;
c906108c 1364 struct rs6000_framedata work_fdata;
6be8bc0c
EZ
1365 struct gdbarch_tdep * tdep = gdbarch_tdep (current_gdbarch);
1366 int wordsize = tdep->wordsize;
c906108c
SS
1367
1368 if (fi->saved_regs)
1369 return;
c5aa993b 1370
c906108c
SS
1371 if (fdatap == NULL)
1372 {
1373 fdatap = &work_fdata;
077276e8 1374 (void) skip_prologue (get_pc_function_start (fi->pc), fi->pc, fdatap);
c906108c
SS
1375 }
1376
1377 frame_saved_regs_zalloc (fi);
1378
1379 /* If there were any saved registers, figure out parent's stack
1380 pointer. */
1381 /* The following is true only if the frame doesn't have a call to
1382 alloca(), FIXME. */
1383
6be8bc0c
EZ
1384 if (fdatap->saved_fpr == 0
1385 && fdatap->saved_gpr == 0
1386 && fdatap->saved_vr == 0
1387 && fdatap->lr_offset == 0
1388 && fdatap->cr_offset == 0
1389 && fdatap->vr_offset == 0)
c906108c 1390 frame_addr = 0;
c906108c 1391 else
bf75c8c1
AC
1392 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
1393 address of the current frame. Things might be easier if the
1394 ->frame pointed to the outer-most address of the frame. In the
1395 mean time, the address of the prev frame is used as the base
1396 address of this frame. */
1397 frame_addr = FRAME_CHAIN (fi);
c5aa993b 1398
c906108c
SS
1399 /* if != -1, fdatap->saved_fpr is the smallest number of saved_fpr.
1400 All fpr's from saved_fpr to fp31 are saved. */
1401
1402 if (fdatap->saved_fpr >= 0)
1403 {
1404 int i;
7a78ae4e 1405 CORE_ADDR fpr_addr = frame_addr + fdatap->fpr_offset;
c906108c
SS
1406 for (i = fdatap->saved_fpr; i < 32; i++)
1407 {
7a78ae4e
ND
1408 fi->saved_regs[FP0_REGNUM + i] = fpr_addr;
1409 fpr_addr += 8;
c906108c
SS
1410 }
1411 }
1412
1413 /* if != -1, fdatap->saved_gpr is the smallest number of saved_gpr.
1414 All gpr's from saved_gpr to gpr31 are saved. */
1415
1416 if (fdatap->saved_gpr >= 0)
1417 {
1418 int i;
7a78ae4e 1419 CORE_ADDR gpr_addr = frame_addr + fdatap->gpr_offset;
c906108c
SS
1420 for (i = fdatap->saved_gpr; i < 32; i++)
1421 {
7a78ae4e
ND
1422 fi->saved_regs[i] = gpr_addr;
1423 gpr_addr += wordsize;
c906108c
SS
1424 }
1425 }
1426
6be8bc0c
EZ
1427 /* if != -1, fdatap->saved_vr is the smallest number of saved_vr.
1428 All vr's from saved_vr to vr31 are saved. */
1429 if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
1430 {
1431 if (fdatap->saved_vr >= 0)
1432 {
1433 int i;
1434 CORE_ADDR vr_addr = frame_addr + fdatap->vr_offset;
1435 for (i = fdatap->saved_vr; i < 32; i++)
1436 {
1437 fi->saved_regs[tdep->ppc_vr0_regnum + i] = vr_addr;
1438 vr_addr += REGISTER_RAW_SIZE (tdep->ppc_vr0_regnum);
1439 }
1440 }
1441 }
1442
c906108c
SS
1443 /* If != 0, fdatap->cr_offset is the offset from the frame that holds
1444 the CR. */
1445 if (fdatap->cr_offset != 0)
6be8bc0c 1446 fi->saved_regs[tdep->ppc_cr_regnum] = frame_addr + fdatap->cr_offset;
c906108c
SS
1447
1448 /* If != 0, fdatap->lr_offset is the offset from the frame that holds
1449 the LR. */
1450 if (fdatap->lr_offset != 0)
6be8bc0c
EZ
1451 fi->saved_regs[tdep->ppc_lr_regnum] = frame_addr + fdatap->lr_offset;
1452
1453 /* If != 0, fdatap->vrsave_offset is the offset from the frame that holds
1454 the VRSAVE. */
1455 if (fdatap->vrsave_offset != 0)
1456 fi->saved_regs[tdep->ppc_vrsave_regnum] = frame_addr + fdatap->vrsave_offset;
c906108c
SS
1457}
1458
1459/* Return the address of a frame. This is the inital %sp value when the frame
1460 was first allocated. For functions calling alloca(), it might be saved in
1461 an alloca register. */
1462
1463static CORE_ADDR
7a78ae4e 1464frame_initial_stack_address (struct frame_info *fi)
c906108c
SS
1465{
1466 CORE_ADDR tmpaddr;
1467 struct rs6000_framedata fdata;
1468 struct frame_info *callee_fi;
1469
1470 /* if the initial stack pointer (frame address) of this frame is known,
1471 just return it. */
1472
1473 if (fi->extra_info->initial_sp)
1474 return fi->extra_info->initial_sp;
1475
1476 /* find out if this function is using an alloca register.. */
1477
077276e8 1478 (void) skip_prologue (get_pc_function_start (fi->pc), fi->pc, &fdata);
c906108c
SS
1479
1480 /* if saved registers of this frame are not known yet, read and cache them. */
1481
1482 if (!fi->saved_regs)
1483 frame_get_saved_regs (fi, &fdata);
1484
1485 /* If no alloca register used, then fi->frame is the value of the %sp for
1486 this frame, and it is good enough. */
1487
1488 if (fdata.alloca_reg < 0)
1489 {
1490 fi->extra_info->initial_sp = fi->frame;
1491 return fi->extra_info->initial_sp;
1492 }
1493
953836b2
AC
1494 /* There is an alloca register, use its value, in the current frame,
1495 as the initial stack pointer. */
1496 {
1497 char *tmpbuf = alloca (MAX_REGISTER_RAW_SIZE);
1498 if (frame_register_read (fi, fdata.alloca_reg, tmpbuf))
1499 {
1500 fi->extra_info->initial_sp
1501 = extract_unsigned_integer (tmpbuf,
1502 REGISTER_RAW_SIZE (fdata.alloca_reg));
1503 }
1504 else
1505 /* NOTE: cagney/2002-04-17: At present the only time
1506 frame_register_read will fail is when the register isn't
1507 available. If that does happen, use the frame. */
1508 fi->extra_info->initial_sp = fi->frame;
1509 }
c906108c
SS
1510 return fi->extra_info->initial_sp;
1511}
1512
7a78ae4e
ND
1513/* Describe the pointer in each stack frame to the previous stack frame
1514 (its caller). */
1515
1516/* FRAME_CHAIN takes a frame's nominal address
1517 and produces the frame's chain-pointer. */
1518
1519/* In the case of the RS/6000, the frame's nominal address
1520 is the address of a 4-byte word containing the calling frame's address. */
1521
9aa1e687 1522CORE_ADDR
7a78ae4e 1523rs6000_frame_chain (struct frame_info *thisframe)
c906108c 1524{
7a78ae4e
ND
1525 CORE_ADDR fp, fpp, lr;
1526 int wordsize = TDEP->wordsize;
c906108c 1527
7a78ae4e
ND
1528 if (PC_IN_CALL_DUMMY (thisframe->pc, thisframe->frame, thisframe->frame))
1529 return thisframe->frame; /* dummy frame same as caller's frame */
c906108c 1530
c5aa993b 1531 if (inside_entry_file (thisframe->pc) ||
c906108c
SS
1532 thisframe->pc == entry_point_address ())
1533 return 0;
1534
1535 if (thisframe->signal_handler_caller)
7a78ae4e
ND
1536 fp = read_memory_addr (thisframe->frame + SIG_FRAME_FP_OFFSET,
1537 wordsize);
c906108c
SS
1538 else if (thisframe->next != NULL
1539 && thisframe->next->signal_handler_caller
c877c8e6 1540 && FRAMELESS_FUNCTION_INVOCATION (thisframe))
c906108c
SS
1541 /* A frameless function interrupted by a signal did not change the
1542 frame pointer. */
1543 fp = FRAME_FP (thisframe);
1544 else
7a78ae4e 1545 fp = read_memory_addr ((thisframe)->frame, wordsize);
c906108c 1546
2188cbdd 1547 lr = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum);
7a78ae4e
ND
1548 if (lr == entry_point_address ())
1549 if (fp != 0 && (fpp = read_memory_addr (fp, wordsize)) != 0)
1550 if (PC_IN_CALL_DUMMY (lr, fpp, fpp))
1551 return fpp;
1552
1553 return fp;
1554}
1555
1556/* Return the size of register REG when words are WORDSIZE bytes long. If REG
1557 isn't available with that word size, return 0. */
1558
1559static int
1560regsize (const struct reg *reg, int wordsize)
1561{
1562 return wordsize == 8 ? reg->sz64 : reg->sz32;
1563}
1564
1565/* Return the name of register number N, or null if no such register exists
1566 in the current architecture. */
1567
1568static char *
1569rs6000_register_name (int n)
1570{
1571 struct gdbarch_tdep *tdep = TDEP;
1572 const struct reg *reg = tdep->regs + n;
1573
1574 if (!regsize (reg, tdep->wordsize))
1575 return NULL;
1576 return reg->name;
1577}
1578
1579/* Index within `registers' of the first byte of the space for
1580 register N. */
1581
1582static int
1583rs6000_register_byte (int n)
1584{
1585 return TDEP->regoff[n];
1586}
1587
1588/* Return the number of bytes of storage in the actual machine representation
1589 for register N if that register is available, else return 0. */
1590
1591static int
1592rs6000_register_raw_size (int n)
1593{
1594 struct gdbarch_tdep *tdep = TDEP;
1595 const struct reg *reg = tdep->regs + n;
1596 return regsize (reg, tdep->wordsize);
1597}
1598
7a78ae4e
ND
1599/* Return the GDB type object for the "standard" data type
1600 of data in register N. */
1601
1602static struct type *
fba45db2 1603rs6000_register_virtual_type (int n)
7a78ae4e
ND
1604{
1605 struct gdbarch_tdep *tdep = TDEP;
1606 const struct reg *reg = tdep->regs + n;
1607
1fcc0bb8
EZ
1608 if (reg->fpr)
1609 return builtin_type_double;
1610 else
1611 {
1612 int size = regsize (reg, tdep->wordsize);
1613 switch (size)
1614 {
1615 case 8:
1616 return builtin_type_int64;
1617 break;
1618 case 16:
08cf96df 1619 return builtin_type_vec128;
1fcc0bb8
EZ
1620 break;
1621 default:
1622 return builtin_type_int32;
1623 break;
1624 }
1625 }
7a78ae4e
ND
1626}
1627
1628/* For the PowerPC, it appears that the debug info marks float parameters as
1629 floats regardless of whether the function is prototyped, but the actual
1630 values are always passed in as doubles. Tell gdb to always assume that
1631 floats are passed as doubles and then converted in the callee. */
1632
1633static int
1634rs6000_coerce_float_to_double (struct type *formal, struct type *actual)
1635{
1636 return 1;
1637}
1638
1639/* Return whether register N requires conversion when moving from raw format
1640 to virtual format.
1641
1642 The register format for RS/6000 floating point registers is always
1643 double, we need a conversion if the memory format is float. */
1644
1645static int
1646rs6000_register_convertible (int n)
1647{
1648 const struct reg *reg = TDEP->regs + n;
1649 return reg->fpr;
1650}
1651
1652/* Convert data from raw format for register N in buffer FROM
1653 to virtual format with type TYPE in buffer TO. */
1654
1655static void
1656rs6000_register_convert_to_virtual (int n, struct type *type,
1657 char *from, char *to)
1658{
1659 if (TYPE_LENGTH (type) != REGISTER_RAW_SIZE (n))
7a292a7a 1660 {
7a78ae4e
ND
1661 double val = extract_floating (from, REGISTER_RAW_SIZE (n));
1662 store_floating (to, TYPE_LENGTH (type), val);
1663 }
1664 else
1665 memcpy (to, from, REGISTER_RAW_SIZE (n));
1666}
1667
1668/* Convert data from virtual format with type TYPE in buffer FROM
1669 to raw format for register N in buffer TO. */
7a292a7a 1670
7a78ae4e
ND
1671static void
1672rs6000_register_convert_to_raw (struct type *type, int n,
1673 char *from, char *to)
1674{
1675 if (TYPE_LENGTH (type) != REGISTER_RAW_SIZE (n))
1676 {
1677 double val = extract_floating (from, TYPE_LENGTH (type));
1678 store_floating (to, REGISTER_RAW_SIZE (n), val);
7a292a7a 1679 }
7a78ae4e
ND
1680 else
1681 memcpy (to, from, REGISTER_RAW_SIZE (n));
1682}
c906108c 1683
1fcc0bb8
EZ
1684int
1685altivec_register_p (int regno)
1686{
1687 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1688 if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0)
1689 return 0;
1690 else
1691 return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum);
1692}
1693
1694static void
1695rs6000_do_altivec_registers (int regnum)
1696{
1697 int i;
1698 char *raw_buffer = (char*) alloca (MAX_REGISTER_RAW_SIZE);
1699 char *virtual_buffer = (char*) alloca (MAX_REGISTER_VIRTUAL_SIZE);
1700 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1701
1702 for (i = tdep->ppc_vr0_regnum; i <= tdep->ppc_vrsave_regnum; i++)
1703 {
1704 /* If we want just one reg, check that this is the one we want. */
1705 if (regnum != -1 && i != regnum)
1706 continue;
1707
1708 /* If the register name is empty, it is undefined for this
1709 processor, so don't display anything. */
1710 if (REGISTER_NAME (i) == NULL || *(REGISTER_NAME (i)) == '\0')
1711 continue;
1712
1713 fputs_filtered (REGISTER_NAME (i), gdb_stdout);
1714 print_spaces_filtered (15 - strlen (REGISTER_NAME (i)), gdb_stdout);
1715
1716 /* Get the data in raw format. */
cda5a58a 1717 if (!frame_register_read (selected_frame, i, raw_buffer))
1fcc0bb8
EZ
1718 {
1719 printf_filtered ("*value not available*\n");
1720 continue;
1721 }
1722
1723 /* Convert raw data to virtual format if necessary. */
1724 if (REGISTER_CONVERTIBLE (i))
1725 REGISTER_CONVERT_TO_VIRTUAL (i, REGISTER_VIRTUAL_TYPE (i),
1726 raw_buffer, virtual_buffer);
1727 else
1728 memcpy (virtual_buffer, raw_buffer, REGISTER_VIRTUAL_SIZE (i));
1729
1730 /* Print as integer in hex only. */
1731 val_print (REGISTER_VIRTUAL_TYPE (i), virtual_buffer, 0, 0,
1732 gdb_stdout, 'x', 1, 0, Val_pretty_default);
1733 printf_filtered ("\n");
1734 }
1735}
1736
1737static void
1738rs6000_altivec_registers_info (char *addr_exp, int from_tty)
1739{
1740 int regnum, numregs;
1741 register char *end;
1742
1743 if (!target_has_registers)
1744 error ("The program has no registers now.");
1745 if (selected_frame == NULL)
1746 error ("No selected frame.");
1747
1748 if (!addr_exp)
1749 {
1750 rs6000_do_altivec_registers (-1);
1751 return;
1752 }
1753
1754 numregs = NUM_REGS + NUM_PSEUDO_REGS;
1755 do
1756 {
1757 if (addr_exp[0] == '$')
1758 addr_exp++;
1759 end = addr_exp;
1760 while (*end != '\0' && *end != ' ' && *end != '\t')
1761 ++end;
1762
1763 regnum = target_map_name_to_register (addr_exp, end - addr_exp);
1764 if (regnum < 0)
1765 {
1766 regnum = numregs;
1767 if (*addr_exp >= '0' && *addr_exp <= '9')
1768 regnum = atoi (addr_exp); /* Take a number */
1769 if (regnum >= numregs) /* Bad name, or bad number */
1770 error ("%.*s: invalid register", end - addr_exp, addr_exp);
1771 }
1772
1773 rs6000_do_altivec_registers (regnum);
1774
1775 addr_exp = end;
1776 while (*addr_exp == ' ' || *addr_exp == '\t')
1777 ++addr_exp;
1778 }
1779 while (*addr_exp != '\0');
1780}
1781
1782static void
1783rs6000_do_registers_info (int regnum, int fpregs)
1784{
1785 register int i;
1786 int numregs = NUM_REGS + NUM_PSEUDO_REGS;
1787 char *raw_buffer = (char*) alloca (MAX_REGISTER_RAW_SIZE);
1788 char *virtual_buffer = (char*) alloca (MAX_REGISTER_VIRTUAL_SIZE);
1789
1790 for (i = 0; i < numregs; i++)
1791 {
1792 /* Decide between printing all regs, nonfloat regs, or specific reg. */
1793 if (regnum == -1)
1794 {
1795 if ((TYPE_CODE (REGISTER_VIRTUAL_TYPE (i)) == TYPE_CODE_FLT && !fpregs)
1796 || (altivec_register_p (i) && !fpregs))
1797 continue;
1798 }
1799 else
1800 {
1801 if (i != regnum)
1802 continue;
1803 }
1804
1805 /* If the register name is empty, it is undefined for this
1806 processor, so don't display anything. */
1807 if (REGISTER_NAME (i) == NULL || *(REGISTER_NAME (i)) == '\0')
1808 continue;
1809
1810 fputs_filtered (REGISTER_NAME (i), gdb_stdout);
1811 print_spaces_filtered (15 - strlen (REGISTER_NAME (i)), gdb_stdout);
1812
1813 /* Get the data in raw format. */
cda5a58a 1814 if (!frame_register_read (selected_frame, i, raw_buffer))
1fcc0bb8
EZ
1815 {
1816 printf_filtered ("*value not available*\n");
1817 continue;
1818 }
1819
1820 /* Convert raw data to virtual format if necessary. */
1821 if (REGISTER_CONVERTIBLE (i))
1822 REGISTER_CONVERT_TO_VIRTUAL (i, REGISTER_VIRTUAL_TYPE (i),
1823 raw_buffer, virtual_buffer);
1824 else
1825 memcpy (virtual_buffer, raw_buffer, REGISTER_VIRTUAL_SIZE (i));
1826
1827 /* If virtual format is floating, print it that way, and in raw hex. */
1828 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (i)) == TYPE_CODE_FLT)
1829 {
1830 register int j;
1831
75bc7ddf
AC
1832 val_print (REGISTER_VIRTUAL_TYPE (i), virtual_buffer, 0, 0,
1833 gdb_stdout, 0, 1, 0, Val_pretty_default);
1fcc0bb8
EZ
1834
1835 printf_filtered ("\t(raw 0x");
1836 for (j = 0; j < REGISTER_RAW_SIZE (i); j++)
1837 {
a9011d31 1838 register int idx = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? j
1fcc0bb8
EZ
1839 : REGISTER_RAW_SIZE (i) - 1 - j;
1840 printf_filtered ("%02x", (unsigned char) raw_buffer[idx]);
1841 }
1842 printf_filtered (")");
1843 }
1844 else
1845 {
1846 /* Print as integer in hex and in decimal. */
1847 if (!altivec_register_p (i))
1848 {
1849 val_print (REGISTER_VIRTUAL_TYPE (i), virtual_buffer, 0, 0,
1850 gdb_stdout, 'x', 1, 0, Val_pretty_default);
1851 printf_filtered ("\t");
1852 val_print (REGISTER_VIRTUAL_TYPE (i), virtual_buffer, 0, 0,
1853 gdb_stdout, 0, 1, 0, Val_pretty_default);
1854 }
1855 else
1856 /* Print as integer in hex only. */
1857 val_print (REGISTER_VIRTUAL_TYPE (i), virtual_buffer, 0, 0,
1858 gdb_stdout, 'x', 1, 0, Val_pretty_default);
1859 }
1860 printf_filtered ("\n");
1861 }
1862}
1863
2188cbdd
EZ
1864/* Convert a dbx stab register number (from `r' declaration) to a gdb
1865 REGNUM. */
1866static int
1867rs6000_stab_reg_to_regnum (int num)
1868{
1869 int regnum;
1870 switch (num)
1871 {
1872 case 64:
1873 regnum = gdbarch_tdep (current_gdbarch)->ppc_mq_regnum;
1874 break;
1875 case 65:
1876 regnum = gdbarch_tdep (current_gdbarch)->ppc_lr_regnum;
1877 break;
1878 case 66:
1879 regnum = gdbarch_tdep (current_gdbarch)->ppc_ctr_regnum;
1880 break;
1881 case 76:
1882 regnum = gdbarch_tdep (current_gdbarch)->ppc_xer_regnum;
1883 break;
1884 default:
1885 regnum = num;
1886 break;
1887 }
1888 return regnum;
1889}
1890
7a78ae4e
ND
1891/* Store the address of the place in which to copy the structure the
1892 subroutine will return. This is called from call_function.
1893
1894 In RS/6000, struct return addresses are passed as an extra parameter in r3.
1895 In function return, callee is not responsible of returning this address
1896 back. Since gdb needs to find it, we will store in a designated variable
1897 `rs6000_struct_return_address'. */
1898
1899static void
1900rs6000_store_struct_return (CORE_ADDR addr, CORE_ADDR sp)
1901{
1902 write_register (3, addr);
1903 rs6000_struct_return_address = addr;
1904}
1905
1906/* Write into appropriate registers a function return value
1907 of type TYPE, given in virtual format. */
1908
1909static void
1910rs6000_store_return_value (struct type *type, char *valbuf)
1911{
1912 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1913
1914 /* Floating point values are returned starting from FPR1 and up.
1915 Say a double_double_double type could be returned in
1916 FPR1/FPR2/FPR3 triple. */
1917
1918 write_register_bytes (REGISTER_BYTE (FP0_REGNUM + 1), valbuf,
1919 TYPE_LENGTH (type));
1920 else
1921 /* Everything else is returned in GPR3 and up. */
2188cbdd
EZ
1922 write_register_bytes (REGISTER_BYTE (gdbarch_tdep (current_gdbarch)->ppc_gp0_regnum + 3),
1923 valbuf, TYPE_LENGTH (type));
7a78ae4e
ND
1924}
1925
1926/* Extract from an array REGBUF containing the (raw) register state
1927 the address in which a function should return its structure value,
1928 as a CORE_ADDR (or an expression that can be used as one). */
1929
1930static CORE_ADDR
1931rs6000_extract_struct_value_address (char *regbuf)
1932{
1933 return rs6000_struct_return_address;
1934}
1935
1936/* Return whether PC is in a dummy function call.
1937
1938 FIXME: This just checks for the end of the stack, which is broken
1939 for things like stepping through gcc nested function stubs. */
1940
1941static int
1942rs6000_pc_in_call_dummy (CORE_ADDR pc, CORE_ADDR sp, CORE_ADDR fp)
1943{
1944 return sp < pc && pc < fp;
1945}
1946
1947/* Hook called when a new child process is started. */
1948
1949void
1950rs6000_create_inferior (int pid)
1951{
1952 if (rs6000_set_host_arch_hook)
1953 rs6000_set_host_arch_hook (pid);
c906108c
SS
1954}
1955\f
7a78ae4e
ND
1956/* Support for CONVERT_FROM_FUNC_PTR_ADDR(ADDR).
1957
1958 Usually a function pointer's representation is simply the address
1959 of the function. On the RS/6000 however, a function pointer is
1960 represented by a pointer to a TOC entry. This TOC entry contains
1961 three words, the first word is the address of the function, the
1962 second word is the TOC pointer (r2), and the third word is the
1963 static chain value. Throughout GDB it is currently assumed that a
1964 function pointer contains the address of the function, which is not
1965 easy to fix. In addition, the conversion of a function address to
1966 a function pointer would require allocation of a TOC entry in the
1967 inferior's memory space, with all its drawbacks. To be able to
1968 call C++ virtual methods in the inferior (which are called via
f517ea4e 1969 function pointers), find_function_addr uses this function to get the
7a78ae4e
ND
1970 function address from a function pointer. */
1971
f517ea4e
PS
1972/* Return real function address if ADDR (a function pointer) is in the data
1973 space and is therefore a special function pointer. */
c906108c 1974
7a78ae4e
ND
1975CORE_ADDR
1976rs6000_convert_from_func_ptr_addr (CORE_ADDR addr)
c906108c
SS
1977{
1978 struct obj_section *s;
1979
1980 s = find_pc_section (addr);
1981 if (s && s->the_bfd_section->flags & SEC_CODE)
7a78ae4e 1982 return addr;
c906108c 1983
7a78ae4e
ND
1984 /* ADDR is in the data space, so it's a special function pointer. */
1985 return read_memory_addr (addr, TDEP->wordsize);
c906108c 1986}
c906108c 1987\f
c5aa993b 1988
7a78ae4e 1989/* Handling the various POWER/PowerPC variants. */
c906108c
SS
1990
1991
7a78ae4e
ND
1992/* The arrays here called registers_MUMBLE hold information about available
1993 registers.
c906108c
SS
1994
1995 For each family of PPC variants, I've tried to isolate out the
1996 common registers and put them up front, so that as long as you get
1997 the general family right, GDB will correctly identify the registers
1998 common to that family. The common register sets are:
1999
2000 For the 60x family: hid0 hid1 iabr dabr pir
2001
2002 For the 505 and 860 family: eie eid nri
2003
2004 For the 403 and 403GC: icdbdr esr dear evpr cdbcr tsr tcr pit tbhi
c5aa993b
JM
2005 tblo srr2 srr3 dbsr dbcr iac1 iac2 dac1 dac2 dccr iccr pbl1
2006 pbu1 pbl2 pbu2
c906108c
SS
2007
2008 Most of these register groups aren't anything formal. I arrived at
2009 them by looking at the registers that occurred in more than one
7a78ae4e
ND
2010 processor. */
2011
2012/* Convenience macros for populating register arrays. */
2013
2014/* Within another macro, convert S to a string. */
2015
2016#define STR(s) #s
2017
2018/* Return a struct reg defining register NAME that's 32 bits on 32-bit systems
2019 and 64 bits on 64-bit systems. */
2020#define R(name) { STR(name), 4, 8, 0 }
2021
2022/* Return a struct reg defining register NAME that's 32 bits on all
2023 systems. */
2024#define R4(name) { STR(name), 4, 4, 0 }
2025
2026/* Return a struct reg defining register NAME that's 64 bits on all
2027 systems. */
2028#define R8(name) { STR(name), 8, 8, 0 }
2029
1fcc0bb8
EZ
2030/* Return a struct reg defining register NAME that's 128 bits on all
2031 systems. */
2032#define R16(name) { STR(name), 16, 16, 0 }
2033
7a78ae4e
ND
2034/* Return a struct reg defining floating-point register NAME. */
2035#define F(name) { STR(name), 8, 8, 1 }
2036
2037/* Return a struct reg defining register NAME that's 32 bits on 32-bit
2038 systems and that doesn't exist on 64-bit systems. */
2039#define R32(name) { STR(name), 4, 0, 0 }
2040
2041/* Return a struct reg defining register NAME that's 64 bits on 64-bit
2042 systems and that doesn't exist on 32-bit systems. */
2043#define R64(name) { STR(name), 0, 8, 0 }
2044
2045/* Return a struct reg placeholder for a register that doesn't exist. */
2046#define R0 { 0, 0, 0, 0 }
2047
2048/* UISA registers common across all architectures, including POWER. */
2049
2050#define COMMON_UISA_REGS \
2051 /* 0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), \
2052 /* 8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \
2053 /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \
2054 /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \
2055 /* 32 */ F(f0), F(f1), F(f2), F(f3), F(f4), F(f5), F(f6), F(f7), \
2056 /* 40 */ F(f8), F(f9), F(f10),F(f11),F(f12),F(f13),F(f14),F(f15), \
2057 /* 48 */ F(f16),F(f17),F(f18),F(f19),F(f20),F(f21),F(f22),F(f23), \
2058 /* 56 */ F(f24),F(f25),F(f26),F(f27),F(f28),F(f29),F(f30),F(f31), \
2059 /* 64 */ R(pc), R(ps)
2060
ebeac11a
EZ
2061#define COMMON_UISA_NOFP_REGS \
2062 /* 0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), \
2063 /* 8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \
2064 /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \
2065 /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \
2066 /* 32 */ R0, R0, R0, R0, R0, R0, R0, R0, \
2067 /* 40 */ R0, R0, R0, R0, R0, R0, R0, R0, \
2068 /* 48 */ R0, R0, R0, R0, R0, R0, R0, R0, \
2069 /* 56 */ R0, R0, R0, R0, R0, R0, R0, R0, \
2070 /* 64 */ R(pc), R(ps)
2071
7a78ae4e
ND
2072/* UISA-level SPRs for PowerPC. */
2073#define PPC_UISA_SPRS \
e3f36dbd 2074 /* 66 */ R4(cr), R(lr), R(ctr), R4(xer), R4(fpscr)
7a78ae4e
ND
2075
2076/* Segment registers, for PowerPC. */
2077#define PPC_SEGMENT_REGS \
2078 /* 71 */ R32(sr0), R32(sr1), R32(sr2), R32(sr3), \
2079 /* 75 */ R32(sr4), R32(sr5), R32(sr6), R32(sr7), \
2080 /* 79 */ R32(sr8), R32(sr9), R32(sr10), R32(sr11), \
2081 /* 83 */ R32(sr12), R32(sr13), R32(sr14), R32(sr15)
2082
2083/* OEA SPRs for PowerPC. */
2084#define PPC_OEA_SPRS \
2085 /* 87 */ R4(pvr), \
2086 /* 88 */ R(ibat0u), R(ibat0l), R(ibat1u), R(ibat1l), \
2087 /* 92 */ R(ibat2u), R(ibat2l), R(ibat3u), R(ibat3l), \
2088 /* 96 */ R(dbat0u), R(dbat0l), R(dbat1u), R(dbat1l), \
2089 /* 100 */ R(dbat2u), R(dbat2l), R(dbat3u), R(dbat3l), \
2090 /* 104 */ R(sdr1), R64(asr), R(dar), R4(dsisr), \
2091 /* 108 */ R(sprg0), R(sprg1), R(sprg2), R(sprg3), \
2092 /* 112 */ R(srr0), R(srr1), R(tbl), R(tbu), \
2093 /* 116 */ R4(dec), R(dabr), R4(ear)
2094
1fcc0bb8
EZ
2095/* AltiVec registers */
2096#define PPC_ALTIVEC_REGS \
2097 /*119*/R16(vr0), R16(vr1), R16(vr2), R16(vr3), R16(vr4), R16(vr5), R16(vr6), R16(vr7), \
2098 /*127*/R16(vr8), R16(vr9), R16(vr10),R16(vr11),R16(vr12),R16(vr13),R16(vr14),R16(vr15), \
2099 /*135*/R16(vr16),R16(vr17),R16(vr18),R16(vr19),R16(vr20),R16(vr21),R16(vr22),R16(vr23), \
2100 /*143*/R16(vr24),R16(vr25),R16(vr26),R16(vr27),R16(vr28),R16(vr29),R16(vr30),R16(vr31), \
2101 /*151*/R4(vscr), R4(vrsave)
2102
7a78ae4e
ND
2103/* IBM POWER (pre-PowerPC) architecture, user-level view. We only cover
2104 user-level SPR's. */
2105static const struct reg registers_power[] =
c906108c 2106{
7a78ae4e 2107 COMMON_UISA_REGS,
e3f36dbd
KB
2108 /* 66 */ R4(cnd), R(lr), R(cnt), R4(xer), R4(mq),
2109 /* 71 */ R4(fpscr)
c906108c
SS
2110};
2111
7a78ae4e
ND
2112/* PowerPC UISA - a PPC processor as viewed by user-level code. A UISA-only
2113 view of the PowerPC. */
2114static const struct reg registers_powerpc[] =
c906108c 2115{
7a78ae4e 2116 COMMON_UISA_REGS,
1fcc0bb8
EZ
2117 PPC_UISA_SPRS,
2118 PPC_ALTIVEC_REGS
c906108c
SS
2119};
2120
ebeac11a
EZ
2121/* PowerPC UISA - a PPC processor as viewed by user-level
2122 code, but without floating point registers. */
2123static const struct reg registers_powerpc_nofp[] =
2124{
2125 COMMON_UISA_NOFP_REGS,
2126 PPC_UISA_SPRS
2127};
2128
7a78ae4e
ND
2129/* IBM PowerPC 403. */
2130static const struct reg registers_403[] =
c5aa993b 2131{
7a78ae4e
ND
2132 COMMON_UISA_REGS,
2133 PPC_UISA_SPRS,
2134 PPC_SEGMENT_REGS,
2135 PPC_OEA_SPRS,
2136 /* 119 */ R(icdbdr), R(esr), R(dear), R(evpr),
2137 /* 123 */ R(cdbcr), R(tsr), R(tcr), R(pit),
2138 /* 127 */ R(tbhi), R(tblo), R(srr2), R(srr3),
2139 /* 131 */ R(dbsr), R(dbcr), R(iac1), R(iac2),
2140 /* 135 */ R(dac1), R(dac2), R(dccr), R(iccr),
2141 /* 139 */ R(pbl1), R(pbu1), R(pbl2), R(pbu2)
c906108c
SS
2142};
2143
7a78ae4e
ND
2144/* IBM PowerPC 403GC. */
2145static const struct reg registers_403GC[] =
c5aa993b 2146{
7a78ae4e
ND
2147 COMMON_UISA_REGS,
2148 PPC_UISA_SPRS,
2149 PPC_SEGMENT_REGS,
2150 PPC_OEA_SPRS,
2151 /* 119 */ R(icdbdr), R(esr), R(dear), R(evpr),
2152 /* 123 */ R(cdbcr), R(tsr), R(tcr), R(pit),
2153 /* 127 */ R(tbhi), R(tblo), R(srr2), R(srr3),
2154 /* 131 */ R(dbsr), R(dbcr), R(iac1), R(iac2),
2155 /* 135 */ R(dac1), R(dac2), R(dccr), R(iccr),
2156 /* 139 */ R(pbl1), R(pbu1), R(pbl2), R(pbu2),
2157 /* 143 */ R(zpr), R(pid), R(sgr), R(dcwr),
2158 /* 147 */ R(tbhu), R(tblu)
c906108c
SS
2159};
2160
7a78ae4e
ND
2161/* Motorola PowerPC 505. */
2162static const struct reg registers_505[] =
c5aa993b 2163{
7a78ae4e
ND
2164 COMMON_UISA_REGS,
2165 PPC_UISA_SPRS,
2166 PPC_SEGMENT_REGS,
2167 PPC_OEA_SPRS,
2168 /* 119 */ R(eie), R(eid), R(nri)
c906108c
SS
2169};
2170
7a78ae4e
ND
2171/* Motorola PowerPC 860 or 850. */
2172static const struct reg registers_860[] =
c5aa993b 2173{
7a78ae4e
ND
2174 COMMON_UISA_REGS,
2175 PPC_UISA_SPRS,
2176 PPC_SEGMENT_REGS,
2177 PPC_OEA_SPRS,
2178 /* 119 */ R(eie), R(eid), R(nri), R(cmpa),
2179 /* 123 */ R(cmpb), R(cmpc), R(cmpd), R(icr),
2180 /* 127 */ R(der), R(counta), R(countb), R(cmpe),
2181 /* 131 */ R(cmpf), R(cmpg), R(cmph), R(lctrl1),
2182 /* 135 */ R(lctrl2), R(ictrl), R(bar), R(ic_cst),
2183 /* 139 */ R(ic_adr), R(ic_dat), R(dc_cst), R(dc_adr),
2184 /* 143 */ R(dc_dat), R(dpdr), R(dpir), R(immr),
2185 /* 147 */ R(mi_ctr), R(mi_ap), R(mi_epn), R(mi_twc),
2186 /* 151 */ R(mi_rpn), R(md_ctr), R(m_casid), R(md_ap),
2187 /* 155 */ R(md_epn), R(md_twb), R(md_twc), R(md_rpn),
2188 /* 159 */ R(m_tw), R(mi_dbcam), R(mi_dbram0), R(mi_dbram1),
2189 /* 163 */ R(md_dbcam), R(md_dbram0), R(md_dbram1)
c906108c
SS
2190};
2191
7a78ae4e
ND
2192/* Motorola PowerPC 601. Note that the 601 has different register numbers
2193 for reading and writing RTCU and RTCL. However, how one reads and writes a
c906108c 2194 register is the stub's problem. */
7a78ae4e 2195static const struct reg registers_601[] =
c5aa993b 2196{
7a78ae4e
ND
2197 COMMON_UISA_REGS,
2198 PPC_UISA_SPRS,
2199 PPC_SEGMENT_REGS,
2200 PPC_OEA_SPRS,
2201 /* 119 */ R(hid0), R(hid1), R(iabr), R(dabr),
2202 /* 123 */ R(pir), R(mq), R(rtcu), R(rtcl)
c906108c
SS
2203};
2204
7a78ae4e
ND
2205/* Motorola PowerPC 602. */
2206static const struct reg registers_602[] =
c5aa993b 2207{
7a78ae4e
ND
2208 COMMON_UISA_REGS,
2209 PPC_UISA_SPRS,
2210 PPC_SEGMENT_REGS,
2211 PPC_OEA_SPRS,
2212 /* 119 */ R(hid0), R(hid1), R(iabr), R0,
2213 /* 123 */ R0, R(tcr), R(ibr), R(esassr),
2214 /* 127 */ R(sebr), R(ser), R(sp), R(lt)
c906108c
SS
2215};
2216
7a78ae4e
ND
2217/* Motorola/IBM PowerPC 603 or 603e. */
2218static const struct reg registers_603[] =
c5aa993b 2219{
7a78ae4e
ND
2220 COMMON_UISA_REGS,
2221 PPC_UISA_SPRS,
2222 PPC_SEGMENT_REGS,
2223 PPC_OEA_SPRS,
2224 /* 119 */ R(hid0), R(hid1), R(iabr), R0,
2225 /* 123 */ R0, R(dmiss), R(dcmp), R(hash1),
2226 /* 127 */ R(hash2), R(imiss), R(icmp), R(rpa)
c906108c
SS
2227};
2228
7a78ae4e
ND
2229/* Motorola PowerPC 604 or 604e. */
2230static const struct reg registers_604[] =
c5aa993b 2231{
7a78ae4e
ND
2232 COMMON_UISA_REGS,
2233 PPC_UISA_SPRS,
2234 PPC_SEGMENT_REGS,
2235 PPC_OEA_SPRS,
2236 /* 119 */ R(hid0), R(hid1), R(iabr), R(dabr),
2237 /* 123 */ R(pir), R(mmcr0), R(pmc1), R(pmc2),
2238 /* 127 */ R(sia), R(sda)
c906108c
SS
2239};
2240
7a78ae4e
ND
2241/* Motorola/IBM PowerPC 750 or 740. */
2242static const struct reg registers_750[] =
c5aa993b 2243{
7a78ae4e
ND
2244 COMMON_UISA_REGS,
2245 PPC_UISA_SPRS,
2246 PPC_SEGMENT_REGS,
2247 PPC_OEA_SPRS,
2248 /* 119 */ R(hid0), R(hid1), R(iabr), R(dabr),
2249 /* 123 */ R0, R(ummcr0), R(upmc1), R(upmc2),
2250 /* 127 */ R(usia), R(ummcr1), R(upmc3), R(upmc4),
2251 /* 131 */ R(mmcr0), R(pmc1), R(pmc2), R(sia),
2252 /* 135 */ R(mmcr1), R(pmc3), R(pmc4), R(l2cr),
2253 /* 139 */ R(ictc), R(thrm1), R(thrm2), R(thrm3)
c906108c
SS
2254};
2255
2256
1fcc0bb8
EZ
2257/* Motorola PowerPC 7400. */
2258static const struct reg registers_7400[] =
2259{
2260 /* gpr0-gpr31, fpr0-fpr31 */
2261 COMMON_UISA_REGS,
2262 /* ctr, xre, lr, cr */
2263 PPC_UISA_SPRS,
2264 /* sr0-sr15 */
2265 PPC_SEGMENT_REGS,
2266 PPC_OEA_SPRS,
2267 /* vr0-vr31, vrsave, vscr */
2268 PPC_ALTIVEC_REGS
2269 /* FIXME? Add more registers? */
2270};
2271
c906108c 2272/* Information about a particular processor variant. */
7a78ae4e 2273
c906108c 2274struct variant
c5aa993b
JM
2275 {
2276 /* Name of this variant. */
2277 char *name;
c906108c 2278
c5aa993b
JM
2279 /* English description of the variant. */
2280 char *description;
c906108c 2281
7a78ae4e
ND
2282 /* bfd_arch_info.arch corresponding to variant. */
2283 enum bfd_architecture arch;
2284
2285 /* bfd_arch_info.mach corresponding to variant. */
2286 unsigned long mach;
2287
c5aa993b
JM
2288 /* Table of register names; registers[R] is the name of the register
2289 number R. */
7a78ae4e
ND
2290 int nregs;
2291 const struct reg *regs;
c5aa993b 2292 };
c906108c
SS
2293
2294#define num_registers(list) (sizeof (list) / sizeof((list)[0]))
2295
2296
2297/* Information in this table comes from the following web sites:
2298 IBM: http://www.chips.ibm.com:80/products/embedded/
2299 Motorola: http://www.mot.com/SPS/PowerPC/
2300
2301 I'm sure I've got some of the variant descriptions not quite right.
2302 Please report any inaccuracies you find to GDB's maintainer.
2303
2304 If you add entries to this table, please be sure to allow the new
2305 value as an argument to the --with-cpu flag, in configure.in. */
2306
7a78ae4e 2307static const struct variant variants[] =
c906108c 2308{
7a78ae4e
ND
2309 {"powerpc", "PowerPC user-level", bfd_arch_powerpc,
2310 bfd_mach_ppc, num_registers (registers_powerpc), registers_powerpc},
2311 {"power", "POWER user-level", bfd_arch_rs6000,
2312 bfd_mach_rs6k, num_registers (registers_power), registers_power},
2313 {"403", "IBM PowerPC 403", bfd_arch_powerpc,
2314 bfd_mach_ppc_403, num_registers (registers_403), registers_403},
2315 {"601", "Motorola PowerPC 601", bfd_arch_powerpc,
2316 bfd_mach_ppc_601, num_registers (registers_601), registers_601},
2317 {"602", "Motorola PowerPC 602", bfd_arch_powerpc,
2318 bfd_mach_ppc_602, num_registers (registers_602), registers_602},
2319 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc,
2320 bfd_mach_ppc_603, num_registers (registers_603), registers_603},
2321 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc,
2322 604, num_registers (registers_604), registers_604},
2323 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc,
2324 bfd_mach_ppc_403gc, num_registers (registers_403GC), registers_403GC},
2325 {"505", "Motorola PowerPC 505", bfd_arch_powerpc,
2326 bfd_mach_ppc_505, num_registers (registers_505), registers_505},
2327 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc,
2328 bfd_mach_ppc_860, num_registers (registers_860), registers_860},
2329 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc,
2330 bfd_mach_ppc_750, num_registers (registers_750), registers_750},
1fcc0bb8
EZ
2331 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc,
2332 bfd_mach_ppc_7400, num_registers (registers_7400), registers_7400},
7a78ae4e 2333
5d57ee30
KB
2334 /* 64-bit */
2335 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc,
2336 bfd_mach_ppc64, num_registers (registers_powerpc), registers_powerpc},
7a78ae4e
ND
2337 {"620", "Motorola PowerPC 620", bfd_arch_powerpc,
2338 bfd_mach_ppc_620, num_registers (registers_powerpc), registers_powerpc},
5d57ee30
KB
2339 {"630", "Motorola PowerPC 630", bfd_arch_powerpc,
2340 bfd_mach_ppc_630, num_registers (registers_powerpc), registers_powerpc},
7a78ae4e
ND
2341 {"a35", "PowerPC A35", bfd_arch_powerpc,
2342 bfd_mach_ppc_a35, num_registers (registers_powerpc), registers_powerpc},
5d57ee30
KB
2343 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc,
2344 bfd_mach_ppc_rs64ii, num_registers (registers_powerpc), registers_powerpc},
2345 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc,
2346 bfd_mach_ppc_rs64iii, num_registers (registers_powerpc), registers_powerpc},
2347
2348 /* FIXME: I haven't checked the register sets of the following. */
7a78ae4e
ND
2349 {"rs1", "IBM POWER RS1", bfd_arch_rs6000,
2350 bfd_mach_rs6k_rs1, num_registers (registers_power), registers_power},
2351 {"rsc", "IBM POWER RSC", bfd_arch_rs6000,
2352 bfd_mach_rs6k_rsc, num_registers (registers_power), registers_power},
2353 {"rs2", "IBM POWER RS2", bfd_arch_rs6000,
2354 bfd_mach_rs6k_rs2, num_registers (registers_power), registers_power},
2355
c5aa993b 2356 {0, 0, 0, 0}
c906108c
SS
2357};
2358
7a78ae4e 2359#undef num_registers
c906108c 2360
7a78ae4e
ND
2361/* Return the variant corresponding to architecture ARCH and machine number
2362 MACH. If no such variant exists, return null. */
c906108c 2363
7a78ae4e
ND
2364static const struct variant *
2365find_variant_by_arch (enum bfd_architecture arch, unsigned long mach)
c906108c 2366{
7a78ae4e 2367 const struct variant *v;
c5aa993b 2368
7a78ae4e
ND
2369 for (v = variants; v->name; v++)
2370 if (arch == v->arch && mach == v->mach)
2371 return v;
c906108c 2372
7a78ae4e 2373 return NULL;
c906108c
SS
2374}
2375
9aa1e687
KB
2376
2377
2378\f
2379static void
2380process_note_abi_tag_sections (bfd *abfd, asection *sect, void *obj)
2381{
2382 int *os_ident_ptr = obj;
2383 const char *name;
2384 unsigned int sectsize;
2385
2386 name = bfd_get_section_name (abfd, sect);
2387 sectsize = bfd_section_size (abfd, sect);
2388 if (strcmp (name, ".note.ABI-tag") == 0 && sectsize > 0)
2389 {
2390 unsigned int name_length, data_length, note_type;
2391 char *note = alloca (sectsize);
2392
2393 bfd_get_section_contents (abfd, sect, note,
2394 (file_ptr) 0, (bfd_size_type) sectsize);
2395
2396 name_length = bfd_h_get_32 (abfd, note);
2397 data_length = bfd_h_get_32 (abfd, note + 4);
2398 note_type = bfd_h_get_32 (abfd, note + 8);
2399
2400 if (name_length == 4 && data_length == 16 && note_type == 1
2401 && strcmp (note + 12, "GNU") == 0)
2402 {
2403 int os_number = bfd_h_get_32 (abfd, note + 16);
2404
2405 /* The case numbers are from abi-tags in glibc */
2406 switch (os_number)
2407 {
2408 case 0 :
2409 *os_ident_ptr = ELFOSABI_LINUX;
2410 break;
2411 case 1 :
2412 *os_ident_ptr = ELFOSABI_HURD;
2413 break;
2414 case 2 :
2415 *os_ident_ptr = ELFOSABI_SOLARIS;
2416 break;
2417 default :
8e65ff28
AC
2418 internal_error (__FILE__, __LINE__,
2419 "process_note_abi_sections: unknown OS number %d",
2420 os_number);
9aa1e687
KB
2421 break;
2422 }
2423 }
2424 }
2425}
2426
2427/* Return one of the ELFOSABI_ constants for BFDs representing ELF
2428 executables. If it's not an ELF executable or if the OS/ABI couldn't
2429 be determined, simply return -1. */
2430
2431static int
2432get_elfosabi (bfd *abfd)
2433{
2434 int elfosabi = -1;
2435
2436 if (abfd != NULL && bfd_get_flavour (abfd) == bfd_target_elf_flavour)
2437 {
2438 elfosabi = elf_elfheader (abfd)->e_ident[EI_OSABI];
2439
2440 /* When elfosabi is 0 (ELFOSABI_NONE), this is supposed to indicate
2441 that we're on a SYSV system. However, GNU/Linux uses a note section
2442 to record OS/ABI info, but leaves e_ident[EI_OSABI] zero. So we
2443 have to check the note sections too. */
2444 if (elfosabi == 0)
2445 {
2446 bfd_map_over_sections (abfd,
2447 process_note_abi_tag_sections,
2448 &elfosabi);
2449 }
2450 }
2451
2452 return elfosabi;
2453}
2454
7a78ae4e 2455\f
c906108c 2456
7a78ae4e
ND
2457/* Initialize the current architecture based on INFO. If possible, re-use an
2458 architecture from ARCHES, which is a list of architectures already created
2459 during this debugging session.
c906108c 2460
7a78ae4e
ND
2461 Called e.g. at program startup, when reading a core file, and when reading
2462 a binary file. */
c906108c 2463
7a78ae4e
ND
2464static struct gdbarch *
2465rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2466{
2467 struct gdbarch *gdbarch;
2468 struct gdbarch_tdep *tdep;
9aa1e687 2469 int wordsize, from_xcoff_exec, from_elf_exec, power, i, off;
7a78ae4e
ND
2470 struct reg *regs;
2471 const struct variant *v;
2472 enum bfd_architecture arch;
2473 unsigned long mach;
2474 bfd abfd;
9aa1e687 2475 int osabi, sysv_abi;
56a6dfb9 2476 gdbarch_print_insn_ftype *print_insn;
7a78ae4e 2477
9aa1e687 2478 from_xcoff_exec = info.abfd && info.abfd->format == bfd_object &&
7a78ae4e
ND
2479 bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour;
2480
9aa1e687
KB
2481 from_elf_exec = info.abfd && info.abfd->format == bfd_object &&
2482 bfd_get_flavour (info.abfd) == bfd_target_elf_flavour;
2483
2484 sysv_abi = info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour;
2485
2486 osabi = get_elfosabi (info.abfd);
2487
e712c1cf
AC
2488 /* Check word size. If INFO is from a binary file, infer it from
2489 that, else choose a likely default. */
9aa1e687 2490 if (from_xcoff_exec)
c906108c 2491 {
7a78ae4e
ND
2492 if (xcoff_data (info.abfd)->xcoff64)
2493 wordsize = 8;
2494 else
2495 wordsize = 4;
c906108c 2496 }
9aa1e687
KB
2497 else if (from_elf_exec)
2498 {
2499 if (elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
2500 wordsize = 8;
2501 else
2502 wordsize = 4;
2503 }
c906108c 2504 else
7a78ae4e 2505 {
27b15785
KB
2506 if (info.bfd_arch_info != NULL && info.bfd_arch_info->bits_per_word != 0)
2507 wordsize = info.bfd_arch_info->bits_per_word /
2508 info.bfd_arch_info->bits_per_byte;
2509 else
2510 wordsize = 4;
7a78ae4e 2511 }
c906108c 2512
7a78ae4e
ND
2513 /* Find a candidate among extant architectures. */
2514 for (arches = gdbarch_list_lookup_by_info (arches, &info);
2515 arches != NULL;
2516 arches = gdbarch_list_lookup_by_info (arches->next, &info))
2517 {
2518 /* Word size in the various PowerPC bfd_arch_info structs isn't
2519 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
2520 separate word size check. */
2521 tdep = gdbarch_tdep (arches->gdbarch);
9aa1e687 2522 if (tdep && tdep->wordsize == wordsize && tdep->osabi == osabi)
7a78ae4e
ND
2523 return arches->gdbarch;
2524 }
c906108c 2525
7a78ae4e
ND
2526 /* None found, create a new architecture from INFO, whose bfd_arch_info
2527 validity depends on the source:
2528 - executable useless
2529 - rs6000_host_arch() good
2530 - core file good
2531 - "set arch" trust blindly
2532 - GDB startup useless but harmless */
c906108c 2533
9aa1e687 2534 if (!from_xcoff_exec)
c906108c 2535 {
b732d07d 2536 arch = info.bfd_arch_info->arch;
7a78ae4e 2537 mach = info.bfd_arch_info->mach;
c906108c 2538 }
7a78ae4e 2539 else
c906108c 2540 {
7a78ae4e
ND
2541 arch = bfd_arch_powerpc;
2542 mach = 0;
2543 bfd_default_set_arch_mach (&abfd, arch, mach);
2544 info.bfd_arch_info = bfd_get_arch_info (&abfd);
2545 }
2546 tdep = xmalloc (sizeof (struct gdbarch_tdep));
2547 tdep->wordsize = wordsize;
9aa1e687 2548 tdep->osabi = osabi;
7a78ae4e
ND
2549 gdbarch = gdbarch_alloc (&info, tdep);
2550 power = arch == bfd_arch_rs6000;
2551
7a78ae4e
ND
2552 /* Choose variant. */
2553 v = find_variant_by_arch (arch, mach);
2554 if (!v)
dd47e6fd
EZ
2555 return NULL;
2556
7a78ae4e
ND
2557 tdep->regs = v->regs;
2558
2188cbdd
EZ
2559 tdep->ppc_gp0_regnum = 0;
2560 tdep->ppc_gplast_regnum = 31;
2561 tdep->ppc_toc_regnum = 2;
2562 tdep->ppc_ps_regnum = 65;
2563 tdep->ppc_cr_regnum = 66;
2564 tdep->ppc_lr_regnum = 67;
2565 tdep->ppc_ctr_regnum = 68;
2566 tdep->ppc_xer_regnum = 69;
2567 if (v->mach == bfd_mach_ppc_601)
2568 tdep->ppc_mq_regnum = 124;
e3f36dbd 2569 else if (power)
2188cbdd 2570 tdep->ppc_mq_regnum = 70;
e3f36dbd
KB
2571 else
2572 tdep->ppc_mq_regnum = -1;
2573 tdep->ppc_fpscr_regnum = power ? 71 : 70;
2188cbdd 2574
1fcc0bb8
EZ
2575 if (v->arch == bfd_arch_powerpc)
2576 switch (v->mach)
2577 {
2578 case bfd_mach_ppc:
2579 tdep->ppc_vr0_regnum = 71;
2580 tdep->ppc_vrsave_regnum = 104;
2581 break;
2582 case bfd_mach_ppc_7400:
2583 tdep->ppc_vr0_regnum = 119;
2584 tdep->ppc_vrsave_regnum = 153;
2585 break;
2586 default:
2587 tdep->ppc_vr0_regnum = -1;
2588 tdep->ppc_vrsave_regnum = -1;
2589 break;
2590 }
2591
a88376a3
KB
2592 /* Set lr_frame_offset. */
2593 if (wordsize == 8)
2594 tdep->lr_frame_offset = 16;
2595 else if (sysv_abi)
2596 tdep->lr_frame_offset = 4;
2597 else
2598 tdep->lr_frame_offset = 8;
2599
2600 /* Calculate byte offsets in raw register array. */
7a78ae4e
ND
2601 tdep->regoff = xmalloc (v->nregs * sizeof (int));
2602 for (i = off = 0; i < v->nregs; i++)
2603 {
2604 tdep->regoff[i] = off;
2605 off += regsize (v->regs + i, wordsize);
c906108c
SS
2606 }
2607
56a6dfb9
KB
2608 /* Select instruction printer. */
2609 if (arch == power)
2610 print_insn = print_insn_rs6000;
2611 else if (info.byte_order == BFD_ENDIAN_BIG)
2612 print_insn = print_insn_big_powerpc;
2613 else
2614 print_insn = print_insn_little_powerpc;
2615 set_gdbarch_print_insn (gdbarch, print_insn);
7495d1dc 2616
7a78ae4e
ND
2617 set_gdbarch_read_pc (gdbarch, generic_target_read_pc);
2618 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
2619 set_gdbarch_read_fp (gdbarch, generic_target_read_fp);
7a78ae4e
ND
2620 set_gdbarch_read_sp (gdbarch, generic_target_read_sp);
2621 set_gdbarch_write_sp (gdbarch, generic_target_write_sp);
2622
2623 set_gdbarch_num_regs (gdbarch, v->nregs);
2624 set_gdbarch_sp_regnum (gdbarch, 1);
2625 set_gdbarch_fp_regnum (gdbarch, 1);
2626 set_gdbarch_pc_regnum (gdbarch, 64);
2627 set_gdbarch_register_name (gdbarch, rs6000_register_name);
2628 set_gdbarch_register_size (gdbarch, wordsize);
2629 set_gdbarch_register_bytes (gdbarch, off);
2630 set_gdbarch_register_byte (gdbarch, rs6000_register_byte);
2631 set_gdbarch_register_raw_size (gdbarch, rs6000_register_raw_size);
2a873819 2632 set_gdbarch_max_register_raw_size (gdbarch, 16);
0e7c5946 2633 set_gdbarch_register_virtual_size (gdbarch, generic_register_virtual_size);
2a873819 2634 set_gdbarch_max_register_virtual_size (gdbarch, 16);
7a78ae4e 2635 set_gdbarch_register_virtual_type (gdbarch, rs6000_register_virtual_type);
1fcc0bb8 2636 set_gdbarch_do_registers_info (gdbarch, rs6000_do_registers_info);
7a78ae4e
ND
2637
2638 set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
2639 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2640 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2641 set_gdbarch_long_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
2642 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2643 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2644 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2645 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
4e409299 2646 set_gdbarch_char_signed (gdbarch, 0);
7a78ae4e
ND
2647
2648 set_gdbarch_use_generic_dummy_frames (gdbarch, 1);
2649 set_gdbarch_call_dummy_length (gdbarch, 0);
2650 set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT);
2651 set_gdbarch_call_dummy_address (gdbarch, entry_point_address);
2652 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1);
2653 set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0);
2654 set_gdbarch_call_dummy_start_offset (gdbarch, 0);
fe794dc6 2655 set_gdbarch_pc_in_call_dummy (gdbarch, generic_pc_in_call_dummy);
7a78ae4e
ND
2656 set_gdbarch_call_dummy_p (gdbarch, 1);
2657 set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0);
2658 set_gdbarch_get_saved_register (gdbarch, generic_get_saved_register);
2659 set_gdbarch_fix_call_dummy (gdbarch, rs6000_fix_call_dummy);
2660 set_gdbarch_push_dummy_frame (gdbarch, generic_push_dummy_frame);
58223630 2661 set_gdbarch_save_dummy_frame_tos (gdbarch, generic_save_dummy_frame_tos);
7a78ae4e
ND
2662 set_gdbarch_push_return_address (gdbarch, ppc_push_return_address);
2663 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2664 set_gdbarch_coerce_float_to_double (gdbarch, rs6000_coerce_float_to_double);
2665
2666 set_gdbarch_register_convertible (gdbarch, rs6000_register_convertible);
2667 set_gdbarch_register_convert_to_virtual (gdbarch, rs6000_register_convert_to_virtual);
2668 set_gdbarch_register_convert_to_raw (gdbarch, rs6000_register_convert_to_raw);
2188cbdd 2669 set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_stab_reg_to_regnum);
7a78ae4e
ND
2670
2671 set_gdbarch_extract_return_value (gdbarch, rs6000_extract_return_value);
9aa1e687 2672
2ea5f656
KB
2673 /* Note: kevinb/2002-04-12: I'm not convinced that rs6000_push_arguments()
2674 is correct for the SysV ABI when the wordsize is 8, but I'm also
2675 fairly certain that ppc_sysv_abi_push_arguments() will give even
2676 worse results since it only works for 32-bit code. So, for the moment,
2677 we're better off calling rs6000_push_arguments() since it works for
2678 64-bit code. At some point in the future, this matter needs to be
2679 revisited. */
2680 if (sysv_abi && wordsize == 4)
9aa1e687
KB
2681 set_gdbarch_push_arguments (gdbarch, ppc_sysv_abi_push_arguments);
2682 else
2683 set_gdbarch_push_arguments (gdbarch, rs6000_push_arguments);
7a78ae4e
ND
2684
2685 set_gdbarch_store_struct_return (gdbarch, rs6000_store_struct_return);
2686 set_gdbarch_store_return_value (gdbarch, rs6000_store_return_value);
2687 set_gdbarch_extract_struct_value_address (gdbarch, rs6000_extract_struct_value_address);
7a78ae4e
ND
2688 set_gdbarch_pop_frame (gdbarch, rs6000_pop_frame);
2689
2690 set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue);
2691 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2692 set_gdbarch_decr_pc_after_break (gdbarch, 0);
2693 set_gdbarch_function_start_offset (gdbarch, 0);
2694 set_gdbarch_breakpoint_from_pc (gdbarch, rs6000_breakpoint_from_pc);
2695
2696 /* Not sure on this. FIXMEmgo */
2697 set_gdbarch_frame_args_skip (gdbarch, 8);
2698
8e0662df
EZ
2699 /* Until November 2001, gcc was not complying to the SYSV ABI for
2700 returning structures less than or equal to 8 bytes in size. It was
2701 returning everything in memory. When this was corrected, it wasn't
2702 fixed for native platforms. */
2703 if (sysv_abi)
2704 {
2705 if (osabi == ELFOSABI_LINUX
2706 || osabi == ELFOSABI_NETBSD
2707 || osabi == ELFOSABI_FREEBSD)
2708 set_gdbarch_use_struct_convention (gdbarch,
2709 generic_use_struct_convention);
2710 else
2711 set_gdbarch_use_struct_convention (gdbarch,
2712 ppc_sysv_abi_use_struct_convention);
2713 }
2714 else
2715 {
2716 set_gdbarch_use_struct_convention (gdbarch,
2717 generic_use_struct_convention);
2718 }
2719
7a78ae4e 2720 set_gdbarch_frame_chain_valid (gdbarch, file_frame_chain_valid);
2ea5f656
KB
2721 /* Note: kevinb/2002-04-12: See note above regarding *_push_arguments().
2722 The same remarks hold for the methods below. */
2723 if (osabi == ELFOSABI_LINUX && wordsize == 4)
9aa1e687
KB
2724 {
2725 set_gdbarch_frameless_function_invocation (gdbarch,
2726 ppc_linux_frameless_function_invocation);
2727 set_gdbarch_frame_chain (gdbarch, ppc_linux_frame_chain);
2728 set_gdbarch_frame_saved_pc (gdbarch, ppc_linux_frame_saved_pc);
2729
2730 set_gdbarch_frame_init_saved_regs (gdbarch,
2731 ppc_linux_frame_init_saved_regs);
2732 set_gdbarch_init_extra_frame_info (gdbarch,
2733 ppc_linux_init_extra_frame_info);
2734
2735 set_gdbarch_memory_remove_breakpoint (gdbarch,
2736 ppc_linux_memory_remove_breakpoint);
6ded7999
KB
2737 set_solib_svr4_fetch_link_map_offsets
2738 (gdbarch, ppc_linux_svr4_fetch_link_map_offsets);
9aa1e687
KB
2739 }
2740 else
2741 {
2742 set_gdbarch_frameless_function_invocation (gdbarch,
2743 rs6000_frameless_function_invocation);
2744 set_gdbarch_frame_chain (gdbarch, rs6000_frame_chain);
2745 set_gdbarch_frame_saved_pc (gdbarch, rs6000_frame_saved_pc);
2746
2747 set_gdbarch_frame_init_saved_regs (gdbarch, rs6000_frame_init_saved_regs);
2748 set_gdbarch_init_extra_frame_info (gdbarch, rs6000_init_extra_frame_info);
f517ea4e
PS
2749
2750 /* Handle RS/6000 function pointers. */
2751 set_gdbarch_convert_from_func_ptr_addr (gdbarch,
2752 rs6000_convert_from_func_ptr_addr);
9aa1e687 2753 }
7a78ae4e
ND
2754 set_gdbarch_frame_args_address (gdbarch, rs6000_frame_args_address);
2755 set_gdbarch_frame_locals_address (gdbarch, rs6000_frame_args_address);
2756 set_gdbarch_saved_pc_after_call (gdbarch, rs6000_saved_pc_after_call);
2757
2758 /* We can't tell how many args there are
2759 now that the C compiler delays popping them. */
2760 set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown);
2761
2762 return gdbarch;
c906108c
SS
2763}
2764
1fcc0bb8
EZ
2765static struct cmd_list_element *info_powerpc_cmdlist = NULL;
2766
2767static void
2768rs6000_info_powerpc_command (char *args, int from_tty)
2769{
2770 help_list (info_powerpc_cmdlist, "info powerpc ", class_info, gdb_stdout);
2771}
2772
c906108c
SS
2773/* Initialization code. */
2774
2775void
fba45db2 2776_initialize_rs6000_tdep (void)
c906108c 2777{
7a78ae4e
ND
2778 register_gdbarch_init (bfd_arch_rs6000, rs6000_gdbarch_init);
2779 register_gdbarch_init (bfd_arch_powerpc, rs6000_gdbarch_init);
1fcc0bb8
EZ
2780
2781 /* Add root prefix command for "info powerpc" commands */
2782 add_prefix_cmd ("powerpc", class_info, rs6000_info_powerpc_command,
2783 "Various POWERPC info specific commands.",
2784 &info_powerpc_cmdlist, "info powerpc ", 0, &infolist);
2785
2786 add_cmd ("altivec", class_info, rs6000_altivec_registers_info,
2787 "Display the contents of the AltiVec registers.",
2788 &info_powerpc_cmdlist);
2789
c906108c 2790}
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