Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for GDB, the GNU debugger. |
7aea86e6 AC |
2 | |
3 | Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, | |
4 | 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software | |
5 | Foundation, Inc. | |
c906108c | 6 | |
c5aa993b | 7 | This file is part of GDB. |
c906108c | 8 | |
c5aa993b JM |
9 | This program is free software; you can redistribute it and/or modify |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2 of the License, or | |
12 | (at your option) any later version. | |
c906108c | 13 | |
c5aa993b JM |
14 | This program is distributed in the hope that it will be useful, |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
c906108c | 18 | |
c5aa993b JM |
19 | You should have received a copy of the GNU General Public License |
20 | along with this program; if not, write to the Free Software | |
21 | Foundation, Inc., 59 Temple Place - Suite 330, | |
22 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
23 | |
24 | #include "defs.h" | |
25 | #include "frame.h" | |
26 | #include "inferior.h" | |
27 | #include "symtab.h" | |
28 | #include "target.h" | |
29 | #include "gdbcore.h" | |
30 | #include "gdbcmd.h" | |
31 | #include "symfile.h" | |
32 | #include "objfiles.h" | |
7a78ae4e | 33 | #include "arch-utils.h" |
4e052eda | 34 | #include "regcache.h" |
d16aafd8 | 35 | #include "doublest.h" |
fd0407d6 | 36 | #include "value.h" |
1fcc0bb8 | 37 | #include "parser-defs.h" |
4be87837 | 38 | #include "osabi.h" |
7a78ae4e | 39 | |
2fccf04a | 40 | #include "libbfd.h" /* for bfd_default_set_arch_mach */ |
7a78ae4e | 41 | #include "coff/internal.h" /* for libcoff.h */ |
2fccf04a | 42 | #include "libcoff.h" /* for xcoff_data */ |
11ed25ac KB |
43 | #include "coff/xcoff.h" |
44 | #include "libxcoff.h" | |
7a78ae4e | 45 | |
9aa1e687 | 46 | #include "elf-bfd.h" |
7a78ae4e | 47 | |
6ded7999 | 48 | #include "solib-svr4.h" |
9aa1e687 | 49 | #include "ppc-tdep.h" |
7a78ae4e | 50 | |
338ef23d | 51 | #include "gdb_assert.h" |
a89aa300 | 52 | #include "dis-asm.h" |
338ef23d | 53 | |
7a78ae4e ND |
54 | /* If the kernel has to deliver a signal, it pushes a sigcontext |
55 | structure on the stack and then calls the signal handler, passing | |
56 | the address of the sigcontext in an argument register. Usually | |
57 | the signal handler doesn't save this register, so we have to | |
58 | access the sigcontext structure via an offset from the signal handler | |
59 | frame. | |
60 | The following constants were determined by experimentation on AIX 3.2. */ | |
61 | #define SIG_FRAME_PC_OFFSET 96 | |
62 | #define SIG_FRAME_LR_OFFSET 108 | |
63 | #define SIG_FRAME_FP_OFFSET 284 | |
64 | ||
7a78ae4e ND |
65 | /* To be used by skip_prologue. */ |
66 | ||
67 | struct rs6000_framedata | |
68 | { | |
69 | int offset; /* total size of frame --- the distance | |
70 | by which we decrement sp to allocate | |
71 | the frame */ | |
72 | int saved_gpr; /* smallest # of saved gpr */ | |
73 | int saved_fpr; /* smallest # of saved fpr */ | |
6be8bc0c | 74 | int saved_vr; /* smallest # of saved vr */ |
96ff0de4 | 75 | int saved_ev; /* smallest # of saved ev */ |
7a78ae4e ND |
76 | int alloca_reg; /* alloca register number (frame ptr) */ |
77 | char frameless; /* true if frameless functions. */ | |
78 | char nosavedpc; /* true if pc not saved. */ | |
79 | int gpr_offset; /* offset of saved gprs from prev sp */ | |
80 | int fpr_offset; /* offset of saved fprs from prev sp */ | |
6be8bc0c | 81 | int vr_offset; /* offset of saved vrs from prev sp */ |
96ff0de4 | 82 | int ev_offset; /* offset of saved evs from prev sp */ |
7a78ae4e ND |
83 | int lr_offset; /* offset of saved lr */ |
84 | int cr_offset; /* offset of saved cr */ | |
6be8bc0c | 85 | int vrsave_offset; /* offset of saved vrsave register */ |
7a78ae4e ND |
86 | }; |
87 | ||
88 | /* Description of a single register. */ | |
89 | ||
90 | struct reg | |
91 | { | |
92 | char *name; /* name of register */ | |
93 | unsigned char sz32; /* size on 32-bit arch, 0 if nonextant */ | |
94 | unsigned char sz64; /* size on 64-bit arch, 0 if nonextant */ | |
95 | unsigned char fpr; /* whether register is floating-point */ | |
489461e2 | 96 | unsigned char pseudo; /* whether register is pseudo */ |
7a78ae4e ND |
97 | }; |
98 | ||
c906108c SS |
99 | /* Breakpoint shadows for the single step instructions will be kept here. */ |
100 | ||
c5aa993b JM |
101 | static struct sstep_breaks |
102 | { | |
103 | /* Address, or 0 if this is not in use. */ | |
104 | CORE_ADDR address; | |
105 | /* Shadow contents. */ | |
106 | char data[4]; | |
107 | } | |
108 | stepBreaks[2]; | |
c906108c SS |
109 | |
110 | /* Hook for determining the TOC address when calling functions in the | |
111 | inferior under AIX. The initialization code in rs6000-nat.c sets | |
112 | this hook to point to find_toc_address. */ | |
113 | ||
7a78ae4e ND |
114 | CORE_ADDR (*rs6000_find_toc_address_hook) (CORE_ADDR) = NULL; |
115 | ||
116 | /* Hook to set the current architecture when starting a child process. | |
117 | rs6000-nat.c sets this. */ | |
118 | ||
119 | void (*rs6000_set_host_arch_hook) (int) = NULL; | |
c906108c SS |
120 | |
121 | /* Static function prototypes */ | |
122 | ||
a14ed312 KB |
123 | static CORE_ADDR branch_dest (int opcode, int instr, CORE_ADDR pc, |
124 | CORE_ADDR safety); | |
077276e8 KB |
125 | static CORE_ADDR skip_prologue (CORE_ADDR, CORE_ADDR, |
126 | struct rs6000_framedata *); | |
7a78ae4e ND |
127 | static void frame_get_saved_regs (struct frame_info * fi, |
128 | struct rs6000_framedata * fdatap); | |
129 | static CORE_ADDR frame_initial_stack_address (struct frame_info *); | |
c906108c | 130 | |
64b84175 KB |
131 | /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */ |
132 | int | |
133 | altivec_register_p (int regno) | |
134 | { | |
135 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
136 | if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0) | |
137 | return 0; | |
138 | else | |
139 | return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum); | |
140 | } | |
141 | ||
0a613259 AC |
142 | /* Use the architectures FP registers? */ |
143 | int | |
144 | ppc_floating_point_unit_p (struct gdbarch *gdbarch) | |
145 | { | |
146 | const struct bfd_arch_info *info = gdbarch_bfd_arch_info (gdbarch); | |
147 | if (info->arch == bfd_arch_powerpc) | |
148 | return (info->mach != bfd_mach_ppc_e500); | |
149 | if (info->arch == bfd_arch_rs6000) | |
150 | return 1; | |
151 | return 0; | |
152 | } | |
153 | ||
7a78ae4e | 154 | /* Read a LEN-byte address from debugged memory address MEMADDR. */ |
c906108c | 155 | |
7a78ae4e ND |
156 | static CORE_ADDR |
157 | read_memory_addr (CORE_ADDR memaddr, int len) | |
158 | { | |
159 | return read_memory_unsigned_integer (memaddr, len); | |
160 | } | |
c906108c | 161 | |
7a78ae4e ND |
162 | static CORE_ADDR |
163 | rs6000_skip_prologue (CORE_ADDR pc) | |
b83266a0 SS |
164 | { |
165 | struct rs6000_framedata frame; | |
077276e8 | 166 | pc = skip_prologue (pc, 0, &frame); |
b83266a0 SS |
167 | return pc; |
168 | } | |
169 | ||
170 | ||
c906108c SS |
171 | /* Fill in fi->saved_regs */ |
172 | ||
173 | struct frame_extra_info | |
174 | { | |
175 | /* Functions calling alloca() change the value of the stack | |
176 | pointer. We need to use initial stack pointer (which is saved in | |
177 | r31 by gcc) in such cases. If a compiler emits traceback table, | |
178 | then we should use the alloca register specified in traceback | |
179 | table. FIXME. */ | |
c5aa993b | 180 | CORE_ADDR initial_sp; /* initial stack pointer. */ |
c906108c SS |
181 | }; |
182 | ||
9aa1e687 | 183 | void |
7a78ae4e | 184 | rs6000_init_extra_frame_info (int fromleaf, struct frame_info *fi) |
c906108c | 185 | { |
c9012c71 AC |
186 | struct frame_extra_info *extra_info = |
187 | frame_extra_info_zalloc (fi, sizeof (struct frame_extra_info)); | |
188 | extra_info->initial_sp = 0; | |
bdd78e62 AC |
189 | if (get_next_frame (fi) != NULL |
190 | && get_frame_pc (fi) < TEXT_SEGMENT_BASE) | |
7a292a7a | 191 | /* We're in get_prev_frame */ |
c906108c SS |
192 | /* and this is a special signal frame. */ |
193 | /* (fi->pc will be some low address in the kernel, */ | |
194 | /* to which the signal handler returns). */ | |
5a203e44 | 195 | deprecated_set_frame_type (fi, SIGTRAMP_FRAME); |
c906108c SS |
196 | } |
197 | ||
7a78ae4e ND |
198 | /* Put here the code to store, into a struct frame_saved_regs, |
199 | the addresses of the saved registers of frame described by FRAME_INFO. | |
200 | This includes special registers such as pc and fp saved in special | |
201 | ways in the stack frame. sp is even more special: | |
202 | the address we return for it IS the sp for the next frame. */ | |
c906108c | 203 | |
7a78ae4e ND |
204 | /* In this implementation for RS/6000, we do *not* save sp. I am |
205 | not sure if it will be needed. The following function takes care of gpr's | |
206 | and fpr's only. */ | |
207 | ||
9aa1e687 | 208 | void |
7a78ae4e | 209 | rs6000_frame_init_saved_regs (struct frame_info *fi) |
c906108c SS |
210 | { |
211 | frame_get_saved_regs (fi, NULL); | |
212 | } | |
213 | ||
7a78ae4e ND |
214 | static CORE_ADDR |
215 | rs6000_frame_args_address (struct frame_info *fi) | |
c906108c | 216 | { |
c9012c71 AC |
217 | struct frame_extra_info *extra_info = get_frame_extra_info (fi); |
218 | if (extra_info->initial_sp != 0) | |
219 | return extra_info->initial_sp; | |
c906108c SS |
220 | else |
221 | return frame_initial_stack_address (fi); | |
222 | } | |
223 | ||
7a78ae4e ND |
224 | /* Immediately after a function call, return the saved pc. |
225 | Can't go through the frames for this because on some machines | |
226 | the new frame is not set up until the new function executes | |
227 | some instructions. */ | |
228 | ||
229 | static CORE_ADDR | |
230 | rs6000_saved_pc_after_call (struct frame_info *fi) | |
231 | { | |
2188cbdd | 232 | return read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum); |
7a78ae4e | 233 | } |
c906108c | 234 | |
143985b7 | 235 | /* Get the ith function argument for the current function. */ |
b9362cc7 | 236 | static CORE_ADDR |
143985b7 AF |
237 | rs6000_fetch_pointer_argument (struct frame_info *frame, int argi, |
238 | struct type *type) | |
239 | { | |
240 | CORE_ADDR addr; | |
7f5f525d | 241 | get_frame_register (frame, 3 + argi, &addr); |
143985b7 AF |
242 | return addr; |
243 | } | |
244 | ||
c906108c SS |
245 | /* Calculate the destination of a branch/jump. Return -1 if not a branch. */ |
246 | ||
247 | static CORE_ADDR | |
7a78ae4e | 248 | branch_dest (int opcode, int instr, CORE_ADDR pc, CORE_ADDR safety) |
c906108c SS |
249 | { |
250 | CORE_ADDR dest; | |
251 | int immediate; | |
252 | int absolute; | |
253 | int ext_op; | |
254 | ||
255 | absolute = (int) ((instr >> 1) & 1); | |
256 | ||
c5aa993b JM |
257 | switch (opcode) |
258 | { | |
259 | case 18: | |
260 | immediate = ((instr & ~3) << 6) >> 6; /* br unconditional */ | |
261 | if (absolute) | |
262 | dest = immediate; | |
263 | else | |
264 | dest = pc + immediate; | |
265 | break; | |
266 | ||
267 | case 16: | |
268 | immediate = ((instr & ~3) << 16) >> 16; /* br conditional */ | |
269 | if (absolute) | |
270 | dest = immediate; | |
271 | else | |
272 | dest = pc + immediate; | |
273 | break; | |
274 | ||
275 | case 19: | |
276 | ext_op = (instr >> 1) & 0x3ff; | |
277 | ||
278 | if (ext_op == 16) /* br conditional register */ | |
279 | { | |
2188cbdd | 280 | dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum) & ~3; |
c5aa993b JM |
281 | |
282 | /* If we are about to return from a signal handler, dest is | |
283 | something like 0x3c90. The current frame is a signal handler | |
284 | caller frame, upon completion of the sigreturn system call | |
285 | execution will return to the saved PC in the frame. */ | |
286 | if (dest < TEXT_SEGMENT_BASE) | |
287 | { | |
288 | struct frame_info *fi; | |
289 | ||
290 | fi = get_current_frame (); | |
291 | if (fi != NULL) | |
8b36eed8 | 292 | dest = read_memory_addr (get_frame_base (fi) + SIG_FRAME_PC_OFFSET, |
21283beb | 293 | gdbarch_tdep (current_gdbarch)->wordsize); |
c5aa993b JM |
294 | } |
295 | } | |
296 | ||
297 | else if (ext_op == 528) /* br cond to count reg */ | |
298 | { | |
2188cbdd | 299 | dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_ctr_regnum) & ~3; |
c5aa993b JM |
300 | |
301 | /* If we are about to execute a system call, dest is something | |
302 | like 0x22fc or 0x3b00. Upon completion the system call | |
303 | will return to the address in the link register. */ | |
304 | if (dest < TEXT_SEGMENT_BASE) | |
2188cbdd | 305 | dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum) & ~3; |
c5aa993b JM |
306 | } |
307 | else | |
308 | return -1; | |
309 | break; | |
c906108c | 310 | |
c5aa993b JM |
311 | default: |
312 | return -1; | |
313 | } | |
c906108c SS |
314 | return (dest < TEXT_SEGMENT_BASE) ? safety : dest; |
315 | } | |
316 | ||
317 | ||
318 | /* Sequence of bytes for breakpoint instruction. */ | |
319 | ||
f4f9705a | 320 | const static unsigned char * |
7a78ae4e | 321 | rs6000_breakpoint_from_pc (CORE_ADDR *bp_addr, int *bp_size) |
c906108c | 322 | { |
aaab4dba AC |
323 | static unsigned char big_breakpoint[] = { 0x7d, 0x82, 0x10, 0x08 }; |
324 | static unsigned char little_breakpoint[] = { 0x08, 0x10, 0x82, 0x7d }; | |
c906108c | 325 | *bp_size = 4; |
d7449b42 | 326 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
327 | return big_breakpoint; |
328 | else | |
329 | return little_breakpoint; | |
330 | } | |
331 | ||
332 | ||
333 | /* AIX does not support PT_STEP. Simulate it. */ | |
334 | ||
335 | void | |
379d08a1 AC |
336 | rs6000_software_single_step (enum target_signal signal, |
337 | int insert_breakpoints_p) | |
c906108c | 338 | { |
7c40d541 KB |
339 | CORE_ADDR dummy; |
340 | int breakp_sz; | |
f4f9705a | 341 | const char *breakp = rs6000_breakpoint_from_pc (&dummy, &breakp_sz); |
c906108c SS |
342 | int ii, insn; |
343 | CORE_ADDR loc; | |
344 | CORE_ADDR breaks[2]; | |
345 | int opcode; | |
346 | ||
c5aa993b JM |
347 | if (insert_breakpoints_p) |
348 | { | |
c906108c | 349 | |
c5aa993b | 350 | loc = read_pc (); |
c906108c | 351 | |
c5aa993b | 352 | insn = read_memory_integer (loc, 4); |
c906108c | 353 | |
7c40d541 | 354 | breaks[0] = loc + breakp_sz; |
c5aa993b JM |
355 | opcode = insn >> 26; |
356 | breaks[1] = branch_dest (opcode, insn, loc, breaks[0]); | |
c906108c | 357 | |
c5aa993b JM |
358 | /* Don't put two breakpoints on the same address. */ |
359 | if (breaks[1] == breaks[0]) | |
360 | breaks[1] = -1; | |
c906108c | 361 | |
c5aa993b | 362 | stepBreaks[1].address = 0; |
c906108c | 363 | |
c5aa993b JM |
364 | for (ii = 0; ii < 2; ++ii) |
365 | { | |
c906108c | 366 | |
c5aa993b JM |
367 | /* ignore invalid breakpoint. */ |
368 | if (breaks[ii] == -1) | |
369 | continue; | |
7c40d541 | 370 | target_insert_breakpoint (breaks[ii], stepBreaks[ii].data); |
c5aa993b JM |
371 | stepBreaks[ii].address = breaks[ii]; |
372 | } | |
c906108c | 373 | |
c5aa993b JM |
374 | } |
375 | else | |
376 | { | |
c906108c | 377 | |
c5aa993b JM |
378 | /* remove step breakpoints. */ |
379 | for (ii = 0; ii < 2; ++ii) | |
380 | if (stepBreaks[ii].address != 0) | |
7c40d541 KB |
381 | target_remove_breakpoint (stepBreaks[ii].address, |
382 | stepBreaks[ii].data); | |
c5aa993b | 383 | } |
c906108c | 384 | errno = 0; /* FIXME, don't ignore errors! */ |
c5aa993b | 385 | /* What errors? {read,write}_memory call error(). */ |
c906108c SS |
386 | } |
387 | ||
388 | ||
389 | /* return pc value after skipping a function prologue and also return | |
390 | information about a function frame. | |
391 | ||
392 | in struct rs6000_framedata fdata: | |
c5aa993b JM |
393 | - frameless is TRUE, if function does not have a frame. |
394 | - nosavedpc is TRUE, if function does not save %pc value in its frame. | |
395 | - offset is the initial size of this stack frame --- the amount by | |
396 | which we decrement the sp to allocate the frame. | |
397 | - saved_gpr is the number of the first saved gpr. | |
398 | - saved_fpr is the number of the first saved fpr. | |
6be8bc0c | 399 | - saved_vr is the number of the first saved vr. |
96ff0de4 | 400 | - saved_ev is the number of the first saved ev. |
c5aa993b JM |
401 | - alloca_reg is the number of the register used for alloca() handling. |
402 | Otherwise -1. | |
403 | - gpr_offset is the offset of the first saved gpr from the previous frame. | |
404 | - fpr_offset is the offset of the first saved fpr from the previous frame. | |
6be8bc0c | 405 | - vr_offset is the offset of the first saved vr from the previous frame. |
96ff0de4 | 406 | - ev_offset is the offset of the first saved ev from the previous frame. |
c5aa993b JM |
407 | - lr_offset is the offset of the saved lr |
408 | - cr_offset is the offset of the saved cr | |
6be8bc0c | 409 | - vrsave_offset is the offset of the saved vrsave register |
c5aa993b | 410 | */ |
c906108c SS |
411 | |
412 | #define SIGNED_SHORT(x) \ | |
413 | ((sizeof (short) == 2) \ | |
414 | ? ((int)(short)(x)) \ | |
415 | : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000))) | |
416 | ||
417 | #define GET_SRC_REG(x) (((x) >> 21) & 0x1f) | |
418 | ||
55d05f3b KB |
419 | /* Limit the number of skipped non-prologue instructions, as the examining |
420 | of the prologue is expensive. */ | |
421 | static int max_skip_non_prologue_insns = 10; | |
422 | ||
423 | /* Given PC representing the starting address of a function, and | |
424 | LIM_PC which is the (sloppy) limit to which to scan when looking | |
425 | for a prologue, attempt to further refine this limit by using | |
426 | the line data in the symbol table. If successful, a better guess | |
427 | on where the prologue ends is returned, otherwise the previous | |
428 | value of lim_pc is returned. */ | |
429 | static CORE_ADDR | |
430 | refine_prologue_limit (CORE_ADDR pc, CORE_ADDR lim_pc) | |
431 | { | |
432 | struct symtab_and_line prologue_sal; | |
433 | ||
434 | prologue_sal = find_pc_line (pc, 0); | |
435 | if (prologue_sal.line != 0) | |
436 | { | |
437 | int i; | |
438 | CORE_ADDR addr = prologue_sal.end; | |
439 | ||
440 | /* Handle the case in which compiler's optimizer/scheduler | |
441 | has moved instructions into the prologue. We scan ahead | |
442 | in the function looking for address ranges whose corresponding | |
443 | line number is less than or equal to the first one that we | |
444 | found for the function. (It can be less than when the | |
445 | scheduler puts a body instruction before the first prologue | |
446 | instruction.) */ | |
447 | for (i = 2 * max_skip_non_prologue_insns; | |
448 | i > 0 && (lim_pc == 0 || addr < lim_pc); | |
449 | i--) | |
450 | { | |
451 | struct symtab_and_line sal; | |
452 | ||
453 | sal = find_pc_line (addr, 0); | |
454 | if (sal.line == 0) | |
455 | break; | |
456 | if (sal.line <= prologue_sal.line | |
457 | && sal.symtab == prologue_sal.symtab) | |
458 | { | |
459 | prologue_sal = sal; | |
460 | } | |
461 | addr = sal.end; | |
462 | } | |
463 | ||
464 | if (lim_pc == 0 || prologue_sal.end < lim_pc) | |
465 | lim_pc = prologue_sal.end; | |
466 | } | |
467 | return lim_pc; | |
468 | } | |
469 | ||
470 | ||
7a78ae4e | 471 | static CORE_ADDR |
077276e8 | 472 | skip_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct rs6000_framedata *fdata) |
c906108c SS |
473 | { |
474 | CORE_ADDR orig_pc = pc; | |
55d05f3b | 475 | CORE_ADDR last_prologue_pc = pc; |
6be8bc0c | 476 | CORE_ADDR li_found_pc = 0; |
c906108c SS |
477 | char buf[4]; |
478 | unsigned long op; | |
479 | long offset = 0; | |
6be8bc0c | 480 | long vr_saved_offset = 0; |
482ca3f5 KB |
481 | int lr_reg = -1; |
482 | int cr_reg = -1; | |
6be8bc0c | 483 | int vr_reg = -1; |
96ff0de4 EZ |
484 | int ev_reg = -1; |
485 | long ev_offset = 0; | |
6be8bc0c | 486 | int vrsave_reg = -1; |
c906108c SS |
487 | int reg; |
488 | int framep = 0; | |
489 | int minimal_toc_loaded = 0; | |
ddb20c56 | 490 | int prev_insn_was_prologue_insn = 1; |
55d05f3b | 491 | int num_skip_non_prologue_insns = 0; |
96ff0de4 | 492 | const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (current_gdbarch); |
6f99cb26 | 493 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
96ff0de4 | 494 | |
55d05f3b KB |
495 | /* Attempt to find the end of the prologue when no limit is specified. |
496 | Note that refine_prologue_limit() has been written so that it may | |
497 | be used to "refine" the limits of non-zero PC values too, but this | |
498 | is only safe if we 1) trust the line information provided by the | |
499 | compiler and 2) iterate enough to actually find the end of the | |
500 | prologue. | |
501 | ||
502 | It may become a good idea at some point (for both performance and | |
503 | accuracy) to unconditionally call refine_prologue_limit(). But, | |
504 | until we can make a clear determination that this is beneficial, | |
505 | we'll play it safe and only use it to obtain a limit when none | |
506 | has been specified. */ | |
507 | if (lim_pc == 0) | |
508 | lim_pc = refine_prologue_limit (pc, lim_pc); | |
c906108c | 509 | |
ddb20c56 | 510 | memset (fdata, 0, sizeof (struct rs6000_framedata)); |
c906108c SS |
511 | fdata->saved_gpr = -1; |
512 | fdata->saved_fpr = -1; | |
6be8bc0c | 513 | fdata->saved_vr = -1; |
96ff0de4 | 514 | fdata->saved_ev = -1; |
c906108c SS |
515 | fdata->alloca_reg = -1; |
516 | fdata->frameless = 1; | |
517 | fdata->nosavedpc = 1; | |
518 | ||
55d05f3b | 519 | for (;; pc += 4) |
c906108c | 520 | { |
ddb20c56 KB |
521 | /* Sometimes it isn't clear if an instruction is a prologue |
522 | instruction or not. When we encounter one of these ambiguous | |
523 | cases, we'll set prev_insn_was_prologue_insn to 0 (false). | |
524 | Otherwise, we'll assume that it really is a prologue instruction. */ | |
525 | if (prev_insn_was_prologue_insn) | |
526 | last_prologue_pc = pc; | |
55d05f3b KB |
527 | |
528 | /* Stop scanning if we've hit the limit. */ | |
529 | if (lim_pc != 0 && pc >= lim_pc) | |
530 | break; | |
531 | ||
ddb20c56 KB |
532 | prev_insn_was_prologue_insn = 1; |
533 | ||
55d05f3b | 534 | /* Fetch the instruction and convert it to an integer. */ |
ddb20c56 KB |
535 | if (target_read_memory (pc, buf, 4)) |
536 | break; | |
537 | op = extract_signed_integer (buf, 4); | |
c906108c | 538 | |
c5aa993b JM |
539 | if ((op & 0xfc1fffff) == 0x7c0802a6) |
540 | { /* mflr Rx */ | |
98f08d3d | 541 | lr_reg = (op & 0x03e00000); |
c5aa993b | 542 | continue; |
c906108c | 543 | |
c5aa993b JM |
544 | } |
545 | else if ((op & 0xfc1fffff) == 0x7c000026) | |
546 | { /* mfcr Rx */ | |
98f08d3d | 547 | cr_reg = (op & 0x03e00000); |
c5aa993b | 548 | continue; |
c906108c | 549 | |
c906108c | 550 | } |
c5aa993b JM |
551 | else if ((op & 0xfc1f0000) == 0xd8010000) |
552 | { /* stfd Rx,NUM(r1) */ | |
553 | reg = GET_SRC_REG (op); | |
554 | if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg) | |
555 | { | |
556 | fdata->saved_fpr = reg; | |
557 | fdata->fpr_offset = SIGNED_SHORT (op) + offset; | |
558 | } | |
559 | continue; | |
c906108c | 560 | |
c5aa993b JM |
561 | } |
562 | else if (((op & 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */ | |
7a78ae4e ND |
563 | (((op & 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */ |
564 | (op & 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */ | |
565 | (op & 0x03e00000) >= 0x01a00000)) /* rx >= r13 */ | |
c5aa993b JM |
566 | { |
567 | ||
568 | reg = GET_SRC_REG (op); | |
569 | if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg) | |
570 | { | |
571 | fdata->saved_gpr = reg; | |
7a78ae4e | 572 | if ((op & 0xfc1f0003) == 0xf8010000) |
98f08d3d | 573 | op &= ~3UL; |
c5aa993b JM |
574 | fdata->gpr_offset = SIGNED_SHORT (op) + offset; |
575 | } | |
576 | continue; | |
c906108c | 577 | |
ddb20c56 KB |
578 | } |
579 | else if ((op & 0xffff0000) == 0x60000000) | |
580 | { | |
96ff0de4 | 581 | /* nop */ |
ddb20c56 KB |
582 | /* Allow nops in the prologue, but do not consider them to |
583 | be part of the prologue unless followed by other prologue | |
584 | instructions. */ | |
585 | prev_insn_was_prologue_insn = 0; | |
586 | continue; | |
587 | ||
c906108c | 588 | } |
c5aa993b JM |
589 | else if ((op & 0xffff0000) == 0x3c000000) |
590 | { /* addis 0,0,NUM, used | |
591 | for >= 32k frames */ | |
592 | fdata->offset = (op & 0x0000ffff) << 16; | |
593 | fdata->frameless = 0; | |
594 | continue; | |
595 | ||
596 | } | |
597 | else if ((op & 0xffff0000) == 0x60000000) | |
598 | { /* ori 0,0,NUM, 2nd ha | |
599 | lf of >= 32k frames */ | |
600 | fdata->offset |= (op & 0x0000ffff); | |
601 | fdata->frameless = 0; | |
602 | continue; | |
603 | ||
604 | } | |
98f08d3d KB |
605 | else if (lr_reg != -1 && |
606 | /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */ | |
607 | (((op & 0xffff0000) == (lr_reg | 0xf8010000)) || | |
608 | /* stw Rx, NUM(r1) */ | |
609 | ((op & 0xffff0000) == (lr_reg | 0x90010000)) || | |
610 | /* stwu Rx, NUM(r1) */ | |
611 | ((op & 0xffff0000) == (lr_reg | 0x94010000)))) | |
612 | { /* where Rx == lr */ | |
613 | fdata->lr_offset = offset; | |
c5aa993b JM |
614 | fdata->nosavedpc = 0; |
615 | lr_reg = 0; | |
98f08d3d KB |
616 | if ((op & 0xfc000003) == 0xf8000000 || /* std */ |
617 | (op & 0xfc000000) == 0x90000000) /* stw */ | |
618 | { | |
619 | /* Does not update r1, so add displacement to lr_offset. */ | |
620 | fdata->lr_offset += SIGNED_SHORT (op); | |
621 | } | |
c5aa993b JM |
622 | continue; |
623 | ||
624 | } | |
98f08d3d KB |
625 | else if (cr_reg != -1 && |
626 | /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */ | |
627 | (((op & 0xffff0000) == (cr_reg | 0xf8010000)) || | |
628 | /* stw Rx, NUM(r1) */ | |
629 | ((op & 0xffff0000) == (cr_reg | 0x90010000)) || | |
630 | /* stwu Rx, NUM(r1) */ | |
631 | ((op & 0xffff0000) == (cr_reg | 0x94010000)))) | |
632 | { /* where Rx == cr */ | |
633 | fdata->cr_offset = offset; | |
c5aa993b | 634 | cr_reg = 0; |
98f08d3d KB |
635 | if ((op & 0xfc000003) == 0xf8000000 || |
636 | (op & 0xfc000000) == 0x90000000) | |
637 | { | |
638 | /* Does not update r1, so add displacement to cr_offset. */ | |
639 | fdata->cr_offset += SIGNED_SHORT (op); | |
640 | } | |
c5aa993b JM |
641 | continue; |
642 | ||
643 | } | |
644 | else if (op == 0x48000005) | |
645 | { /* bl .+4 used in | |
646 | -mrelocatable */ | |
647 | continue; | |
648 | ||
649 | } | |
650 | else if (op == 0x48000004) | |
651 | { /* b .+4 (xlc) */ | |
652 | break; | |
653 | ||
c5aa993b | 654 | } |
6be8bc0c EZ |
655 | else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used |
656 | in V.4 -mminimal-toc */ | |
c5aa993b JM |
657 | (op & 0xffff0000) == 0x3bde0000) |
658 | { /* addi 30,30,foo@l */ | |
659 | continue; | |
c906108c | 660 | |
c5aa993b JM |
661 | } |
662 | else if ((op & 0xfc000001) == 0x48000001) | |
663 | { /* bl foo, | |
664 | to save fprs??? */ | |
c906108c | 665 | |
c5aa993b | 666 | fdata->frameless = 0; |
6be8bc0c EZ |
667 | /* Don't skip over the subroutine call if it is not within |
668 | the first three instructions of the prologue. */ | |
c5aa993b JM |
669 | if ((pc - orig_pc) > 8) |
670 | break; | |
671 | ||
672 | op = read_memory_integer (pc + 4, 4); | |
673 | ||
6be8bc0c EZ |
674 | /* At this point, make sure this is not a trampoline |
675 | function (a function that simply calls another functions, | |
676 | and nothing else). If the next is not a nop, this branch | |
677 | was part of the function prologue. */ | |
c5aa993b JM |
678 | |
679 | if (op == 0x4def7b82 || op == 0) /* crorc 15, 15, 15 */ | |
680 | break; /* don't skip over | |
681 | this branch */ | |
682 | continue; | |
683 | ||
c5aa993b | 684 | } |
98f08d3d KB |
685 | /* update stack pointer */ |
686 | else if ((op & 0xfc1f0000) == 0x94010000) | |
687 | { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */ | |
c5aa993b JM |
688 | fdata->frameless = 0; |
689 | fdata->offset = SIGNED_SHORT (op); | |
690 | offset = fdata->offset; | |
691 | continue; | |
c5aa993b | 692 | } |
98f08d3d KB |
693 | else if ((op & 0xfc1f016a) == 0x7c01016e) |
694 | { /* stwux rX,r1,rY */ | |
695 | /* no way to figure out what r1 is going to be */ | |
696 | fdata->frameless = 0; | |
697 | offset = fdata->offset; | |
698 | continue; | |
699 | } | |
700 | else if ((op & 0xfc1f0003) == 0xf8010001) | |
701 | { /* stdu rX,NUM(r1) */ | |
702 | fdata->frameless = 0; | |
703 | fdata->offset = SIGNED_SHORT (op & ~3UL); | |
704 | offset = fdata->offset; | |
705 | continue; | |
706 | } | |
707 | else if ((op & 0xfc1f016a) == 0x7c01016a) | |
708 | { /* stdux rX,r1,rY */ | |
709 | /* no way to figure out what r1 is going to be */ | |
c5aa993b JM |
710 | fdata->frameless = 0; |
711 | offset = fdata->offset; | |
712 | continue; | |
c5aa993b | 713 | } |
98f08d3d KB |
714 | /* Load up minimal toc pointer */ |
715 | else if (((op >> 22) == 0x20f || /* l r31,... or l r30,... */ | |
716 | (op >> 22) == 0x3af) /* ld r31,... or ld r30,... */ | |
c5aa993b | 717 | && !minimal_toc_loaded) |
98f08d3d | 718 | { |
c5aa993b JM |
719 | minimal_toc_loaded = 1; |
720 | continue; | |
721 | ||
f6077098 KB |
722 | /* move parameters from argument registers to local variable |
723 | registers */ | |
724 | } | |
725 | else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */ | |
726 | (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */ | |
727 | (((op >> 21) & 31) <= 10) && | |
96ff0de4 | 728 | ((long) ((op >> 16) & 31) >= fdata->saved_gpr)) /* Rx: local var reg */ |
f6077098 KB |
729 | { |
730 | continue; | |
731 | ||
c5aa993b JM |
732 | /* store parameters in stack */ |
733 | } | |
6be8bc0c | 734 | else if ((op & 0xfc1f0003) == 0xf8010000 || /* std rx,NUM(r1) */ |
c5aa993b | 735 | (op & 0xfc1f0000) == 0xd8010000 || /* stfd Rx,NUM(r1) */ |
7a78ae4e ND |
736 | (op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */ |
737 | { | |
c5aa993b | 738 | continue; |
c906108c | 739 | |
c5aa993b JM |
740 | /* store parameters in stack via frame pointer */ |
741 | } | |
742 | else if (framep && | |
743 | ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r1) */ | |
744 | (op & 0xfc1f0000) == 0xd81f0000 || /* stfd Rx,NUM(r1) */ | |
745 | (op & 0xfc1f0000) == 0xfc1f0000)) | |
746 | { /* frsp, fp?,NUM(r1) */ | |
747 | continue; | |
748 | ||
749 | /* Set up frame pointer */ | |
750 | } | |
751 | else if (op == 0x603f0000 /* oril r31, r1, 0x0 */ | |
752 | || op == 0x7c3f0b78) | |
753 | { /* mr r31, r1 */ | |
754 | fdata->frameless = 0; | |
755 | framep = 1; | |
6f99cb26 | 756 | fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31); |
c5aa993b JM |
757 | continue; |
758 | ||
759 | /* Another way to set up the frame pointer. */ | |
760 | } | |
761 | else if ((op & 0xfc1fffff) == 0x38010000) | |
762 | { /* addi rX, r1, 0x0 */ | |
763 | fdata->frameless = 0; | |
764 | framep = 1; | |
6f99cb26 AC |
765 | fdata->alloca_reg = (tdep->ppc_gp0_regnum |
766 | + ((op & ~0x38010000) >> 21)); | |
c5aa993b | 767 | continue; |
c5aa993b | 768 | } |
6be8bc0c EZ |
769 | /* AltiVec related instructions. */ |
770 | /* Store the vrsave register (spr 256) in another register for | |
771 | later manipulation, or load a register into the vrsave | |
772 | register. 2 instructions are used: mfvrsave and | |
773 | mtvrsave. They are shorthand notation for mfspr Rn, SPR256 | |
774 | and mtspr SPR256, Rn. */ | |
775 | /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110 | |
776 | mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */ | |
777 | else if ((op & 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */ | |
778 | { | |
779 | vrsave_reg = GET_SRC_REG (op); | |
780 | continue; | |
781 | } | |
782 | else if ((op & 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */ | |
783 | { | |
784 | continue; | |
785 | } | |
786 | /* Store the register where vrsave was saved to onto the stack: | |
787 | rS is the register where vrsave was stored in a previous | |
788 | instruction. */ | |
789 | /* 100100 sssss 00001 dddddddd dddddddd */ | |
790 | else if ((op & 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */ | |
791 | { | |
792 | if (vrsave_reg == GET_SRC_REG (op)) | |
793 | { | |
794 | fdata->vrsave_offset = SIGNED_SHORT (op) + offset; | |
795 | vrsave_reg = -1; | |
796 | } | |
797 | continue; | |
798 | } | |
799 | /* Compute the new value of vrsave, by modifying the register | |
800 | where vrsave was saved to. */ | |
801 | else if (((op & 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */ | |
802 | || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */ | |
803 | { | |
804 | continue; | |
805 | } | |
806 | /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first | |
807 | in a pair of insns to save the vector registers on the | |
808 | stack. */ | |
809 | /* 001110 00000 00000 iiii iiii iiii iiii */ | |
96ff0de4 EZ |
810 | /* 001110 01110 00000 iiii iiii iiii iiii */ |
811 | else if ((op & 0xffff0000) == 0x38000000 /* li r0, SIMM */ | |
812 | || (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */ | |
6be8bc0c EZ |
813 | { |
814 | li_found_pc = pc; | |
815 | vr_saved_offset = SIGNED_SHORT (op); | |
816 | } | |
817 | /* Store vector register S at (r31+r0) aligned to 16 bytes. */ | |
818 | /* 011111 sssss 11111 00000 00111001110 */ | |
819 | else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */ | |
820 | { | |
821 | if (pc == (li_found_pc + 4)) | |
822 | { | |
823 | vr_reg = GET_SRC_REG (op); | |
824 | /* If this is the first vector reg to be saved, or if | |
825 | it has a lower number than others previously seen, | |
826 | reupdate the frame info. */ | |
827 | if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg) | |
828 | { | |
829 | fdata->saved_vr = vr_reg; | |
830 | fdata->vr_offset = vr_saved_offset + offset; | |
831 | } | |
832 | vr_saved_offset = -1; | |
833 | vr_reg = -1; | |
834 | li_found_pc = 0; | |
835 | } | |
836 | } | |
837 | /* End AltiVec related instructions. */ | |
96ff0de4 EZ |
838 | |
839 | /* Start BookE related instructions. */ | |
840 | /* Store gen register S at (r31+uimm). | |
841 | Any register less than r13 is volatile, so we don't care. */ | |
842 | /* 000100 sssss 11111 iiiii 01100100001 */ | |
843 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
844 | && (op & 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */ | |
845 | { | |
846 | if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */ | |
847 | { | |
848 | unsigned int imm; | |
849 | ev_reg = GET_SRC_REG (op); | |
850 | imm = (op >> 11) & 0x1f; | |
851 | ev_offset = imm * 8; | |
852 | /* If this is the first vector reg to be saved, or if | |
853 | it has a lower number than others previously seen, | |
854 | reupdate the frame info. */ | |
855 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) | |
856 | { | |
857 | fdata->saved_ev = ev_reg; | |
858 | fdata->ev_offset = ev_offset + offset; | |
859 | } | |
860 | } | |
861 | continue; | |
862 | } | |
863 | /* Store gen register rS at (r1+rB). */ | |
864 | /* 000100 sssss 00001 bbbbb 01100100000 */ | |
865 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
866 | && (op & 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */ | |
867 | { | |
868 | if (pc == (li_found_pc + 4)) | |
869 | { | |
870 | ev_reg = GET_SRC_REG (op); | |
871 | /* If this is the first vector reg to be saved, or if | |
872 | it has a lower number than others previously seen, | |
873 | reupdate the frame info. */ | |
874 | /* We know the contents of rB from the previous instruction. */ | |
875 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) | |
876 | { | |
877 | fdata->saved_ev = ev_reg; | |
878 | fdata->ev_offset = vr_saved_offset + offset; | |
879 | } | |
880 | vr_saved_offset = -1; | |
881 | ev_reg = -1; | |
882 | li_found_pc = 0; | |
883 | } | |
884 | continue; | |
885 | } | |
886 | /* Store gen register r31 at (rA+uimm). */ | |
887 | /* 000100 11111 aaaaa iiiii 01100100001 */ | |
888 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
889 | && (op & 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */ | |
890 | { | |
891 | /* Wwe know that the source register is 31 already, but | |
892 | it can't hurt to compute it. */ | |
893 | ev_reg = GET_SRC_REG (op); | |
894 | ev_offset = ((op >> 11) & 0x1f) * 8; | |
895 | /* If this is the first vector reg to be saved, or if | |
896 | it has a lower number than others previously seen, | |
897 | reupdate the frame info. */ | |
898 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) | |
899 | { | |
900 | fdata->saved_ev = ev_reg; | |
901 | fdata->ev_offset = ev_offset + offset; | |
902 | } | |
903 | ||
904 | continue; | |
905 | } | |
906 | /* Store gen register S at (r31+r0). | |
907 | Store param on stack when offset from SP bigger than 4 bytes. */ | |
908 | /* 000100 sssss 11111 00000 01100100000 */ | |
909 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
910 | && (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */ | |
911 | { | |
912 | if (pc == (li_found_pc + 4)) | |
913 | { | |
914 | if ((op & 0x03e00000) >= 0x01a00000) | |
915 | { | |
916 | ev_reg = GET_SRC_REG (op); | |
917 | /* If this is the first vector reg to be saved, or if | |
918 | it has a lower number than others previously seen, | |
919 | reupdate the frame info. */ | |
920 | /* We know the contents of r0 from the previous | |
921 | instruction. */ | |
922 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) | |
923 | { | |
924 | fdata->saved_ev = ev_reg; | |
925 | fdata->ev_offset = vr_saved_offset + offset; | |
926 | } | |
927 | ev_reg = -1; | |
928 | } | |
929 | vr_saved_offset = -1; | |
930 | li_found_pc = 0; | |
931 | continue; | |
932 | } | |
933 | } | |
934 | /* End BookE related instructions. */ | |
935 | ||
c5aa993b JM |
936 | else |
937 | { | |
55d05f3b KB |
938 | /* Not a recognized prologue instruction. |
939 | Handle optimizer code motions into the prologue by continuing | |
940 | the search if we have no valid frame yet or if the return | |
941 | address is not yet saved in the frame. */ | |
942 | if (fdata->frameless == 0 | |
943 | && (lr_reg == -1 || fdata->nosavedpc == 0)) | |
944 | break; | |
945 | ||
946 | if (op == 0x4e800020 /* blr */ | |
947 | || op == 0x4e800420) /* bctr */ | |
948 | /* Do not scan past epilogue in frameless functions or | |
949 | trampolines. */ | |
950 | break; | |
951 | if ((op & 0xf4000000) == 0x40000000) /* bxx */ | |
64366f1c | 952 | /* Never skip branches. */ |
55d05f3b KB |
953 | break; |
954 | ||
955 | if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns) | |
956 | /* Do not scan too many insns, scanning insns is expensive with | |
957 | remote targets. */ | |
958 | break; | |
959 | ||
960 | /* Continue scanning. */ | |
961 | prev_insn_was_prologue_insn = 0; | |
962 | continue; | |
c5aa993b | 963 | } |
c906108c SS |
964 | } |
965 | ||
966 | #if 0 | |
967 | /* I have problems with skipping over __main() that I need to address | |
968 | * sometime. Previously, I used to use misc_function_vector which | |
969 | * didn't work as well as I wanted to be. -MGO */ | |
970 | ||
971 | /* If the first thing after skipping a prolog is a branch to a function, | |
972 | this might be a call to an initializer in main(), introduced by gcc2. | |
64366f1c | 973 | We'd like to skip over it as well. Fortunately, xlc does some extra |
c906108c | 974 | work before calling a function right after a prologue, thus we can |
64366f1c | 975 | single out such gcc2 behaviour. */ |
c906108c | 976 | |
c906108c | 977 | |
c5aa993b JM |
978 | if ((op & 0xfc000001) == 0x48000001) |
979 | { /* bl foo, an initializer function? */ | |
980 | op = read_memory_integer (pc + 4, 4); | |
981 | ||
982 | if (op == 0x4def7b82) | |
983 | { /* cror 0xf, 0xf, 0xf (nop) */ | |
c906108c | 984 | |
64366f1c EZ |
985 | /* Check and see if we are in main. If so, skip over this |
986 | initializer function as well. */ | |
c906108c | 987 | |
c5aa993b | 988 | tmp = find_pc_misc_function (pc); |
6314a349 AC |
989 | if (tmp >= 0 |
990 | && strcmp (misc_function_vector[tmp].name, main_name ()) == 0) | |
c5aa993b JM |
991 | return pc + 8; |
992 | } | |
c906108c | 993 | } |
c906108c | 994 | #endif /* 0 */ |
c5aa993b JM |
995 | |
996 | fdata->offset = -fdata->offset; | |
ddb20c56 | 997 | return last_prologue_pc; |
c906108c SS |
998 | } |
999 | ||
1000 | ||
1001 | /************************************************************************* | |
f6077098 | 1002 | Support for creating pushing a dummy frame into the stack, and popping |
c906108c SS |
1003 | frames, etc. |
1004 | *************************************************************************/ | |
1005 | ||
c906108c | 1006 | |
64366f1c | 1007 | /* Pop the innermost frame, go back to the caller. */ |
c5aa993b | 1008 | |
c906108c | 1009 | static void |
7a78ae4e | 1010 | rs6000_pop_frame (void) |
c906108c | 1011 | { |
470d5666 | 1012 | CORE_ADDR pc, lr, sp, prev_sp, addr; /* %pc, %lr, %sp */ |
c906108c SS |
1013 | struct rs6000_framedata fdata; |
1014 | struct frame_info *frame = get_current_frame (); | |
470d5666 | 1015 | int ii, wordsize; |
c906108c SS |
1016 | |
1017 | pc = read_pc (); | |
c193f6ac | 1018 | sp = get_frame_base (frame); |
c906108c | 1019 | |
bdd78e62 | 1020 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), |
8b36eed8 AC |
1021 | get_frame_base (frame), |
1022 | get_frame_base (frame))) | |
c906108c | 1023 | { |
7a78ae4e ND |
1024 | generic_pop_dummy_frame (); |
1025 | flush_cached_frames (); | |
1026 | return; | |
c906108c SS |
1027 | } |
1028 | ||
1029 | /* Make sure that all registers are valid. */ | |
b8b527c5 | 1030 | deprecated_read_register_bytes (0, NULL, DEPRECATED_REGISTER_BYTES); |
c906108c | 1031 | |
64366f1c | 1032 | /* Figure out previous %pc value. If the function is frameless, it is |
c906108c | 1033 | still in the link register, otherwise walk the frames and retrieve the |
64366f1c | 1034 | saved %pc value in the previous frame. */ |
c906108c | 1035 | |
be41e9f4 | 1036 | addr = get_frame_func (frame); |
bdd78e62 | 1037 | (void) skip_prologue (addr, get_frame_pc (frame), &fdata); |
c906108c | 1038 | |
21283beb | 1039 | wordsize = gdbarch_tdep (current_gdbarch)->wordsize; |
c906108c SS |
1040 | if (fdata.frameless) |
1041 | prev_sp = sp; | |
1042 | else | |
7a78ae4e | 1043 | prev_sp = read_memory_addr (sp, wordsize); |
c906108c | 1044 | if (fdata.lr_offset == 0) |
2188cbdd | 1045 | lr = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum); |
c906108c | 1046 | else |
7a78ae4e | 1047 | lr = read_memory_addr (prev_sp + fdata.lr_offset, wordsize); |
c906108c SS |
1048 | |
1049 | /* reset %pc value. */ | |
1050 | write_register (PC_REGNUM, lr); | |
1051 | ||
64366f1c | 1052 | /* reset register values if any was saved earlier. */ |
c906108c SS |
1053 | |
1054 | if (fdata.saved_gpr != -1) | |
1055 | { | |
1056 | addr = prev_sp + fdata.gpr_offset; | |
c5aa993b JM |
1057 | for (ii = fdata.saved_gpr; ii <= 31; ++ii) |
1058 | { | |
62700349 | 1059 | read_memory (addr, &deprecated_registers[DEPRECATED_REGISTER_BYTE (ii)], |
524d7c18 | 1060 | wordsize); |
7a78ae4e | 1061 | addr += wordsize; |
c5aa993b | 1062 | } |
c906108c SS |
1063 | } |
1064 | ||
1065 | if (fdata.saved_fpr != -1) | |
1066 | { | |
1067 | addr = prev_sp + fdata.fpr_offset; | |
c5aa993b JM |
1068 | for (ii = fdata.saved_fpr; ii <= 31; ++ii) |
1069 | { | |
62700349 | 1070 | read_memory (addr, &deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + FP0_REGNUM)], 8); |
c5aa993b JM |
1071 | addr += 8; |
1072 | } | |
c906108c SS |
1073 | } |
1074 | ||
1075 | write_register (SP_REGNUM, prev_sp); | |
1076 | target_store_registers (-1); | |
1077 | flush_cached_frames (); | |
1078 | } | |
1079 | ||
11269d7e AC |
1080 | /* All the ABI's require 16 byte alignment. */ |
1081 | static CORE_ADDR | |
1082 | rs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
1083 | { | |
1084 | return (addr & -16); | |
1085 | } | |
1086 | ||
7a78ae4e | 1087 | /* Pass the arguments in either registers, or in the stack. In RS/6000, |
c906108c SS |
1088 | the first eight words of the argument list (that might be less than |
1089 | eight parameters if some parameters occupy more than one word) are | |
7a78ae4e | 1090 | passed in r3..r10 registers. float and double parameters are |
64366f1c EZ |
1091 | passed in fpr's, in addition to that. Rest of the parameters if any |
1092 | are passed in user stack. There might be cases in which half of the | |
c906108c SS |
1093 | parameter is copied into registers, the other half is pushed into |
1094 | stack. | |
1095 | ||
7a78ae4e ND |
1096 | Stack must be aligned on 64-bit boundaries when synthesizing |
1097 | function calls. | |
1098 | ||
c906108c SS |
1099 | If the function is returning a structure, then the return address is passed |
1100 | in r3, then the first 7 words of the parameters can be passed in registers, | |
64366f1c | 1101 | starting from r4. */ |
c906108c | 1102 | |
7a78ae4e | 1103 | static CORE_ADDR |
77b2b6d4 AC |
1104 | rs6000_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
1105 | struct regcache *regcache, CORE_ADDR bp_addr, | |
1106 | int nargs, struct value **args, CORE_ADDR sp, | |
1107 | int struct_return, CORE_ADDR struct_addr) | |
c906108c | 1108 | { |
7a41266b | 1109 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c SS |
1110 | int ii; |
1111 | int len = 0; | |
c5aa993b JM |
1112 | int argno; /* current argument number */ |
1113 | int argbytes; /* current argument byte */ | |
1114 | char tmp_buffer[50]; | |
1115 | int f_argno = 0; /* current floating point argno */ | |
21283beb | 1116 | int wordsize = gdbarch_tdep (current_gdbarch)->wordsize; |
c906108c | 1117 | |
ea7c478f | 1118 | struct value *arg = 0; |
c906108c SS |
1119 | struct type *type; |
1120 | ||
1121 | CORE_ADDR saved_sp; | |
1122 | ||
64366f1c | 1123 | /* The first eight words of ther arguments are passed in registers. |
7a41266b AC |
1124 | Copy them appropriately. */ |
1125 | ii = 0; | |
1126 | ||
1127 | /* If the function is returning a `struct', then the first word | |
1128 | (which will be passed in r3) is used for struct return address. | |
1129 | In that case we should advance one word and start from r4 | |
1130 | register to copy parameters. */ | |
1131 | if (struct_return) | |
1132 | { | |
1133 | regcache_raw_write_unsigned (regcache, tdep->ppc_gp0_regnum + 3, | |
1134 | struct_addr); | |
1135 | ii++; | |
1136 | } | |
c906108c SS |
1137 | |
1138 | /* | |
c5aa993b JM |
1139 | effectively indirect call... gcc does... |
1140 | ||
1141 | return_val example( float, int); | |
1142 | ||
1143 | eabi: | |
1144 | float in fp0, int in r3 | |
1145 | offset of stack on overflow 8/16 | |
1146 | for varargs, must go by type. | |
1147 | power open: | |
1148 | float in r3&r4, int in r5 | |
1149 | offset of stack on overflow different | |
1150 | both: | |
1151 | return in r3 or f0. If no float, must study how gcc emulates floats; | |
1152 | pay attention to arg promotion. | |
1153 | User may have to cast\args to handle promotion correctly | |
1154 | since gdb won't know if prototype supplied or not. | |
1155 | */ | |
c906108c | 1156 | |
c5aa993b JM |
1157 | for (argno = 0, argbytes = 0; argno < nargs && ii < 8; ++ii) |
1158 | { | |
12c266ea | 1159 | int reg_size = DEPRECATED_REGISTER_RAW_SIZE (ii + 3); |
c5aa993b JM |
1160 | |
1161 | arg = args[argno]; | |
1162 | type = check_typedef (VALUE_TYPE (arg)); | |
1163 | len = TYPE_LENGTH (type); | |
1164 | ||
1165 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
1166 | { | |
1167 | ||
64366f1c | 1168 | /* Floating point arguments are passed in fpr's, as well as gpr's. |
c5aa993b | 1169 | There are 13 fpr's reserved for passing parameters. At this point |
64366f1c | 1170 | there is no way we would run out of them. */ |
c5aa993b JM |
1171 | |
1172 | if (len > 8) | |
1173 | printf_unfiltered ( | |
1174 | "Fatal Error: a floating point parameter #%d with a size > 8 is found!\n", argno); | |
1175 | ||
62700349 | 1176 | memcpy (&deprecated_registers[DEPRECATED_REGISTER_BYTE (FP0_REGNUM + 1 + f_argno)], |
c5aa993b JM |
1177 | VALUE_CONTENTS (arg), |
1178 | len); | |
1179 | ++f_argno; | |
1180 | } | |
1181 | ||
f6077098 | 1182 | if (len > reg_size) |
c5aa993b JM |
1183 | { |
1184 | ||
64366f1c | 1185 | /* Argument takes more than one register. */ |
c5aa993b JM |
1186 | while (argbytes < len) |
1187 | { | |
62700349 | 1188 | memset (&deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + 3)], 0, |
524d7c18 | 1189 | reg_size); |
62700349 | 1190 | memcpy (&deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + 3)], |
c5aa993b | 1191 | ((char *) VALUE_CONTENTS (arg)) + argbytes, |
f6077098 KB |
1192 | (len - argbytes) > reg_size |
1193 | ? reg_size : len - argbytes); | |
1194 | ++ii, argbytes += reg_size; | |
c5aa993b JM |
1195 | |
1196 | if (ii >= 8) | |
1197 | goto ran_out_of_registers_for_arguments; | |
1198 | } | |
1199 | argbytes = 0; | |
1200 | --ii; | |
1201 | } | |
1202 | else | |
64366f1c EZ |
1203 | { |
1204 | /* Argument can fit in one register. No problem. */ | |
d7449b42 | 1205 | int adj = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? reg_size - len : 0; |
62700349 AC |
1206 | memset (&deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + 3)], 0, reg_size); |
1207 | memcpy ((char *)&deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + 3)] + adj, | |
f6077098 | 1208 | VALUE_CONTENTS (arg), len); |
c5aa993b JM |
1209 | } |
1210 | ++argno; | |
c906108c | 1211 | } |
c906108c SS |
1212 | |
1213 | ran_out_of_registers_for_arguments: | |
1214 | ||
7a78ae4e | 1215 | saved_sp = read_sp (); |
cc9836a8 | 1216 | |
64366f1c | 1217 | /* Location for 8 parameters are always reserved. */ |
7a78ae4e | 1218 | sp -= wordsize * 8; |
f6077098 | 1219 | |
64366f1c | 1220 | /* Another six words for back chain, TOC register, link register, etc. */ |
7a78ae4e | 1221 | sp -= wordsize * 6; |
f6077098 | 1222 | |
64366f1c | 1223 | /* Stack pointer must be quadword aligned. */ |
7a78ae4e | 1224 | sp &= -16; |
c906108c | 1225 | |
64366f1c EZ |
1226 | /* If there are more arguments, allocate space for them in |
1227 | the stack, then push them starting from the ninth one. */ | |
c906108c | 1228 | |
c5aa993b JM |
1229 | if ((argno < nargs) || argbytes) |
1230 | { | |
1231 | int space = 0, jj; | |
c906108c | 1232 | |
c5aa993b JM |
1233 | if (argbytes) |
1234 | { | |
1235 | space += ((len - argbytes + 3) & -4); | |
1236 | jj = argno + 1; | |
1237 | } | |
1238 | else | |
1239 | jj = argno; | |
c906108c | 1240 | |
c5aa993b JM |
1241 | for (; jj < nargs; ++jj) |
1242 | { | |
ea7c478f | 1243 | struct value *val = args[jj]; |
c5aa993b JM |
1244 | space += ((TYPE_LENGTH (VALUE_TYPE (val))) + 3) & -4; |
1245 | } | |
c906108c | 1246 | |
64366f1c | 1247 | /* Add location required for the rest of the parameters. */ |
f6077098 | 1248 | space = (space + 15) & -16; |
c5aa993b | 1249 | sp -= space; |
c906108c | 1250 | |
7aea86e6 AC |
1251 | /* This is another instance we need to be concerned about |
1252 | securing our stack space. If we write anything underneath %sp | |
1253 | (r1), we might conflict with the kernel who thinks he is free | |
1254 | to use this area. So, update %sp first before doing anything | |
1255 | else. */ | |
1256 | ||
1257 | regcache_raw_write_signed (regcache, SP_REGNUM, sp); | |
1258 | ||
64366f1c EZ |
1259 | /* If the last argument copied into the registers didn't fit there |
1260 | completely, push the rest of it into stack. */ | |
c906108c | 1261 | |
c5aa993b JM |
1262 | if (argbytes) |
1263 | { | |
1264 | write_memory (sp + 24 + (ii * 4), | |
1265 | ((char *) VALUE_CONTENTS (arg)) + argbytes, | |
1266 | len - argbytes); | |
1267 | ++argno; | |
1268 | ii += ((len - argbytes + 3) & -4) / 4; | |
1269 | } | |
c906108c | 1270 | |
64366f1c | 1271 | /* Push the rest of the arguments into stack. */ |
c5aa993b JM |
1272 | for (; argno < nargs; ++argno) |
1273 | { | |
c906108c | 1274 | |
c5aa993b JM |
1275 | arg = args[argno]; |
1276 | type = check_typedef (VALUE_TYPE (arg)); | |
1277 | len = TYPE_LENGTH (type); | |
c906108c SS |
1278 | |
1279 | ||
64366f1c EZ |
1280 | /* Float types should be passed in fpr's, as well as in the |
1281 | stack. */ | |
c5aa993b JM |
1282 | if (TYPE_CODE (type) == TYPE_CODE_FLT && f_argno < 13) |
1283 | { | |
c906108c | 1284 | |
c5aa993b JM |
1285 | if (len > 8) |
1286 | printf_unfiltered ( | |
1287 | "Fatal Error: a floating point parameter #%d with a size > 8 is found!\n", argno); | |
c906108c | 1288 | |
62700349 | 1289 | memcpy (&deprecated_registers[DEPRECATED_REGISTER_BYTE (FP0_REGNUM + 1 + f_argno)], |
c5aa993b JM |
1290 | VALUE_CONTENTS (arg), |
1291 | len); | |
1292 | ++f_argno; | |
1293 | } | |
c906108c | 1294 | |
c5aa993b JM |
1295 | write_memory (sp + 24 + (ii * 4), (char *) VALUE_CONTENTS (arg), len); |
1296 | ii += ((len + 3) & -4) / 4; | |
1297 | } | |
c906108c | 1298 | } |
c906108c | 1299 | |
69517000 | 1300 | /* Set the stack pointer. According to the ABI, the SP is meant to |
7aea86e6 AC |
1301 | be set _before_ the corresponding stack space is used. On AIX, |
1302 | this even applies when the target has been completely stopped! | |
1303 | Not doing this can lead to conflicts with the kernel which thinks | |
1304 | that it still has control over this not-yet-allocated stack | |
1305 | region. */ | |
33a7c2fc AC |
1306 | regcache_raw_write_signed (regcache, SP_REGNUM, sp); |
1307 | ||
7aea86e6 AC |
1308 | /* Set back chain properly. */ |
1309 | store_unsigned_integer (tmp_buffer, 4, saved_sp); | |
1310 | write_memory (sp, tmp_buffer, 4); | |
1311 | ||
e56a0ecc AC |
1312 | /* Point the inferior function call's return address at the dummy's |
1313 | breakpoint. */ | |
1314 | regcache_raw_write_signed (regcache, tdep->ppc_lr_regnum, bp_addr); | |
1315 | ||
794a477a AC |
1316 | /* Set the TOC register, get the value from the objfile reader |
1317 | which, in turn, gets it from the VMAP table. */ | |
1318 | if (rs6000_find_toc_address_hook != NULL) | |
1319 | { | |
1320 | CORE_ADDR tocvalue = (*rs6000_find_toc_address_hook) (func_addr); | |
1321 | regcache_raw_write_signed (regcache, tdep->ppc_toc_regnum, tocvalue); | |
1322 | } | |
1323 | ||
c906108c SS |
1324 | target_store_registers (-1); |
1325 | return sp; | |
1326 | } | |
c906108c | 1327 | |
b9ff3018 AC |
1328 | /* PowerOpen always puts structures in memory. Vectors, which were |
1329 | added later, do get returned in a register though. */ | |
1330 | ||
1331 | static int | |
1332 | rs6000_use_struct_convention (int gcc_p, struct type *value_type) | |
1333 | { | |
1334 | if ((TYPE_LENGTH (value_type) == 16 || TYPE_LENGTH (value_type) == 8) | |
1335 | && TYPE_VECTOR (value_type)) | |
1336 | return 0; | |
1337 | return 1; | |
1338 | } | |
1339 | ||
7a78ae4e ND |
1340 | static void |
1341 | rs6000_extract_return_value (struct type *valtype, char *regbuf, char *valbuf) | |
c906108c SS |
1342 | { |
1343 | int offset = 0; | |
ace1378a | 1344 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c | 1345 | |
c5aa993b JM |
1346 | if (TYPE_CODE (valtype) == TYPE_CODE_FLT) |
1347 | { | |
c906108c | 1348 | |
c5aa993b JM |
1349 | double dd; |
1350 | float ff; | |
1351 | /* floats and doubles are returned in fpr1. fpr's have a size of 8 bytes. | |
1352 | We need to truncate the return value into float size (4 byte) if | |
64366f1c | 1353 | necessary. */ |
c906108c | 1354 | |
c5aa993b JM |
1355 | if (TYPE_LENGTH (valtype) > 4) /* this is a double */ |
1356 | memcpy (valbuf, | |
62700349 | 1357 | ®buf[DEPRECATED_REGISTER_BYTE (FP0_REGNUM + 1)], |
c5aa993b JM |
1358 | TYPE_LENGTH (valtype)); |
1359 | else | |
1360 | { /* float */ | |
62700349 | 1361 | memcpy (&dd, ®buf[DEPRECATED_REGISTER_BYTE (FP0_REGNUM + 1)], 8); |
c5aa993b JM |
1362 | ff = (float) dd; |
1363 | memcpy (valbuf, &ff, sizeof (float)); | |
1364 | } | |
1365 | } | |
ace1378a EZ |
1366 | else if (TYPE_CODE (valtype) == TYPE_CODE_ARRAY |
1367 | && TYPE_LENGTH (valtype) == 16 | |
1368 | && TYPE_VECTOR (valtype)) | |
1369 | { | |
62700349 | 1370 | memcpy (valbuf, regbuf + DEPRECATED_REGISTER_BYTE (tdep->ppc_vr0_regnum + 2), |
ace1378a EZ |
1371 | TYPE_LENGTH (valtype)); |
1372 | } | |
c5aa993b JM |
1373 | else |
1374 | { | |
1375 | /* return value is copied starting from r3. */ | |
d7449b42 | 1376 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
12c266ea AC |
1377 | && TYPE_LENGTH (valtype) < DEPRECATED_REGISTER_RAW_SIZE (3)) |
1378 | offset = DEPRECATED_REGISTER_RAW_SIZE (3) - TYPE_LENGTH (valtype); | |
c5aa993b JM |
1379 | |
1380 | memcpy (valbuf, | |
62700349 | 1381 | regbuf + DEPRECATED_REGISTER_BYTE (3) + offset, |
c906108c | 1382 | TYPE_LENGTH (valtype)); |
c906108c | 1383 | } |
c906108c SS |
1384 | } |
1385 | ||
977adac5 ND |
1386 | /* Return whether handle_inferior_event() should proceed through code |
1387 | starting at PC in function NAME when stepping. | |
1388 | ||
1389 | The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to | |
1390 | handle memory references that are too distant to fit in instructions | |
1391 | generated by the compiler. For example, if 'foo' in the following | |
1392 | instruction: | |
1393 | ||
1394 | lwz r9,foo(r2) | |
1395 | ||
1396 | is greater than 32767, the linker might replace the lwz with a branch to | |
1397 | somewhere in @FIX1 that does the load in 2 instructions and then branches | |
1398 | back to where execution should continue. | |
1399 | ||
1400 | GDB should silently step over @FIX code, just like AIX dbx does. | |
1401 | Unfortunately, the linker uses the "b" instruction for the branches, | |
1402 | meaning that the link register doesn't get set. Therefore, GDB's usual | |
1403 | step_over_function() mechanism won't work. | |
1404 | ||
1405 | Instead, use the IN_SOLIB_RETURN_TRAMPOLINE and SKIP_TRAMPOLINE_CODE hooks | |
1406 | in handle_inferior_event() to skip past @FIX code. */ | |
1407 | ||
1408 | int | |
1409 | rs6000_in_solib_return_trampoline (CORE_ADDR pc, char *name) | |
1410 | { | |
1411 | return name && !strncmp (name, "@FIX", 4); | |
1412 | } | |
1413 | ||
1414 | /* Skip code that the user doesn't want to see when stepping: | |
1415 | ||
1416 | 1. Indirect function calls use a piece of trampoline code to do context | |
1417 | switching, i.e. to set the new TOC table. Skip such code if we are on | |
1418 | its first instruction (as when we have single-stepped to here). | |
1419 | ||
1420 | 2. Skip shared library trampoline code (which is different from | |
c906108c | 1421 | indirect function call trampolines). |
977adac5 ND |
1422 | |
1423 | 3. Skip bigtoc fixup code. | |
1424 | ||
c906108c | 1425 | Result is desired PC to step until, or NULL if we are not in |
977adac5 | 1426 | code that should be skipped. */ |
c906108c SS |
1427 | |
1428 | CORE_ADDR | |
7a78ae4e | 1429 | rs6000_skip_trampoline_code (CORE_ADDR pc) |
c906108c | 1430 | { |
52f0bd74 | 1431 | unsigned int ii, op; |
977adac5 | 1432 | int rel; |
c906108c | 1433 | CORE_ADDR solib_target_pc; |
977adac5 | 1434 | struct minimal_symbol *msymbol; |
c906108c | 1435 | |
c5aa993b JM |
1436 | static unsigned trampoline_code[] = |
1437 | { | |
1438 | 0x800b0000, /* l r0,0x0(r11) */ | |
1439 | 0x90410014, /* st r2,0x14(r1) */ | |
1440 | 0x7c0903a6, /* mtctr r0 */ | |
1441 | 0x804b0004, /* l r2,0x4(r11) */ | |
1442 | 0x816b0008, /* l r11,0x8(r11) */ | |
1443 | 0x4e800420, /* bctr */ | |
1444 | 0x4e800020, /* br */ | |
1445 | 0 | |
c906108c SS |
1446 | }; |
1447 | ||
977adac5 ND |
1448 | /* Check for bigtoc fixup code. */ |
1449 | msymbol = lookup_minimal_symbol_by_pc (pc); | |
22abf04a | 1450 | if (msymbol && rs6000_in_solib_return_trampoline (pc, DEPRECATED_SYMBOL_NAME (msymbol))) |
977adac5 ND |
1451 | { |
1452 | /* Double-check that the third instruction from PC is relative "b". */ | |
1453 | op = read_memory_integer (pc + 8, 4); | |
1454 | if ((op & 0xfc000003) == 0x48000000) | |
1455 | { | |
1456 | /* Extract bits 6-29 as a signed 24-bit relative word address and | |
1457 | add it to the containing PC. */ | |
1458 | rel = ((int)(op << 6) >> 6); | |
1459 | return pc + 8 + rel; | |
1460 | } | |
1461 | } | |
1462 | ||
c906108c SS |
1463 | /* If pc is in a shared library trampoline, return its target. */ |
1464 | solib_target_pc = find_solib_trampoline_target (pc); | |
1465 | if (solib_target_pc) | |
1466 | return solib_target_pc; | |
1467 | ||
c5aa993b JM |
1468 | for (ii = 0; trampoline_code[ii]; ++ii) |
1469 | { | |
1470 | op = read_memory_integer (pc + (ii * 4), 4); | |
1471 | if (op != trampoline_code[ii]) | |
1472 | return 0; | |
1473 | } | |
1474 | ii = read_register (11); /* r11 holds destination addr */ | |
21283beb | 1475 | pc = read_memory_addr (ii, gdbarch_tdep (current_gdbarch)->wordsize); /* (r11) value */ |
c906108c SS |
1476 | return pc; |
1477 | } | |
1478 | ||
1479 | /* Determines whether the function FI has a frame on the stack or not. */ | |
1480 | ||
9aa1e687 | 1481 | int |
c877c8e6 | 1482 | rs6000_frameless_function_invocation (struct frame_info *fi) |
c906108c SS |
1483 | { |
1484 | CORE_ADDR func_start; | |
1485 | struct rs6000_framedata fdata; | |
1486 | ||
1487 | /* Don't even think about framelessness except on the innermost frame | |
1488 | or if the function was interrupted by a signal. */ | |
75e3c1f9 AC |
1489 | if (get_next_frame (fi) != NULL |
1490 | && !(get_frame_type (get_next_frame (fi)) == SIGTRAMP_FRAME)) | |
c906108c | 1491 | return 0; |
c5aa993b | 1492 | |
be41e9f4 | 1493 | func_start = get_frame_func (fi); |
c906108c SS |
1494 | |
1495 | /* If we failed to find the start of the function, it is a mistake | |
64366f1c | 1496 | to inspect the instructions. */ |
c906108c SS |
1497 | |
1498 | if (!func_start) | |
1499 | { | |
1500 | /* A frame with a zero PC is usually created by dereferencing a NULL | |
c5aa993b | 1501 | function pointer, normally causing an immediate core dump of the |
64366f1c | 1502 | inferior. Mark function as frameless, as the inferior has no chance |
c5aa993b | 1503 | of setting up a stack frame. */ |
bdd78e62 | 1504 | if (get_frame_pc (fi) == 0) |
c906108c SS |
1505 | return 1; |
1506 | else | |
1507 | return 0; | |
1508 | } | |
1509 | ||
bdd78e62 | 1510 | (void) skip_prologue (func_start, get_frame_pc (fi), &fdata); |
c906108c SS |
1511 | return fdata.frameless; |
1512 | } | |
1513 | ||
64366f1c | 1514 | /* Return the PC saved in a frame. */ |
c906108c | 1515 | |
9aa1e687 | 1516 | CORE_ADDR |
c877c8e6 | 1517 | rs6000_frame_saved_pc (struct frame_info *fi) |
c906108c SS |
1518 | { |
1519 | CORE_ADDR func_start; | |
1520 | struct rs6000_framedata fdata; | |
21283beb | 1521 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
a88376a3 | 1522 | int wordsize = tdep->wordsize; |
c906108c | 1523 | |
5a203e44 | 1524 | if ((get_frame_type (fi) == SIGTRAMP_FRAME)) |
8b36eed8 AC |
1525 | return read_memory_addr (get_frame_base (fi) + SIG_FRAME_PC_OFFSET, |
1526 | wordsize); | |
c906108c | 1527 | |
bdd78e62 | 1528 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), |
8b36eed8 AC |
1529 | get_frame_base (fi), |
1530 | get_frame_base (fi))) | |
bdd78e62 | 1531 | return deprecated_read_register_dummy (get_frame_pc (fi), |
8b36eed8 | 1532 | get_frame_base (fi), PC_REGNUM); |
c906108c | 1533 | |
be41e9f4 | 1534 | func_start = get_frame_func (fi); |
c906108c SS |
1535 | |
1536 | /* If we failed to find the start of the function, it is a mistake | |
64366f1c | 1537 | to inspect the instructions. */ |
c906108c SS |
1538 | if (!func_start) |
1539 | return 0; | |
1540 | ||
bdd78e62 | 1541 | (void) skip_prologue (func_start, get_frame_pc (fi), &fdata); |
c906108c | 1542 | |
75e3c1f9 | 1543 | if (fdata.lr_offset == 0 && get_next_frame (fi) != NULL) |
c906108c | 1544 | { |
75e3c1f9 | 1545 | if ((get_frame_type (get_next_frame (fi)) == SIGTRAMP_FRAME)) |
8b36eed8 AC |
1546 | return read_memory_addr ((get_frame_base (get_next_frame (fi)) |
1547 | + SIG_FRAME_LR_OFFSET), | |
7a78ae4e | 1548 | wordsize); |
bdd78e62 | 1549 | else if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (get_next_frame (fi)), 0, 0)) |
8b69000d AC |
1550 | /* The link register wasn't saved by this frame and the next |
1551 | (inner, newer) frame is a dummy. Get the link register | |
1552 | value by unwinding it from that [dummy] frame. */ | |
1553 | { | |
1554 | ULONGEST lr; | |
1555 | frame_unwind_unsigned_register (get_next_frame (fi), | |
1556 | tdep->ppc_lr_regnum, &lr); | |
1557 | return lr; | |
1558 | } | |
c906108c | 1559 | else |
618ce49f AC |
1560 | return read_memory_addr (DEPRECATED_FRAME_CHAIN (fi) |
1561 | + tdep->lr_frame_offset, | |
7a78ae4e | 1562 | wordsize); |
c906108c SS |
1563 | } |
1564 | ||
1565 | if (fdata.lr_offset == 0) | |
2188cbdd | 1566 | return read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum); |
c906108c | 1567 | |
618ce49f AC |
1568 | return read_memory_addr (DEPRECATED_FRAME_CHAIN (fi) + fdata.lr_offset, |
1569 | wordsize); | |
c906108c SS |
1570 | } |
1571 | ||
1572 | /* If saved registers of frame FI are not known yet, read and cache them. | |
1573 | &FDATAP contains rs6000_framedata; TDATAP can be NULL, | |
1574 | in which case the framedata are read. */ | |
1575 | ||
1576 | static void | |
7a78ae4e | 1577 | frame_get_saved_regs (struct frame_info *fi, struct rs6000_framedata *fdatap) |
c906108c | 1578 | { |
c5aa993b | 1579 | CORE_ADDR frame_addr; |
c906108c | 1580 | struct rs6000_framedata work_fdata; |
6be8bc0c EZ |
1581 | struct gdbarch_tdep * tdep = gdbarch_tdep (current_gdbarch); |
1582 | int wordsize = tdep->wordsize; | |
c906108c | 1583 | |
1b1d3794 | 1584 | if (deprecated_get_frame_saved_regs (fi)) |
c906108c | 1585 | return; |
c5aa993b | 1586 | |
c906108c SS |
1587 | if (fdatap == NULL) |
1588 | { | |
1589 | fdatap = &work_fdata; | |
be41e9f4 | 1590 | (void) skip_prologue (get_frame_func (fi), get_frame_pc (fi), fdatap); |
c906108c SS |
1591 | } |
1592 | ||
1593 | frame_saved_regs_zalloc (fi); | |
1594 | ||
1595 | /* If there were any saved registers, figure out parent's stack | |
64366f1c | 1596 | pointer. */ |
c906108c | 1597 | /* The following is true only if the frame doesn't have a call to |
64366f1c | 1598 | alloca(), FIXME. */ |
c906108c | 1599 | |
6be8bc0c EZ |
1600 | if (fdatap->saved_fpr == 0 |
1601 | && fdatap->saved_gpr == 0 | |
1602 | && fdatap->saved_vr == 0 | |
96ff0de4 | 1603 | && fdatap->saved_ev == 0 |
6be8bc0c EZ |
1604 | && fdatap->lr_offset == 0 |
1605 | && fdatap->cr_offset == 0 | |
96ff0de4 EZ |
1606 | && fdatap->vr_offset == 0 |
1607 | && fdatap->ev_offset == 0) | |
c906108c | 1608 | frame_addr = 0; |
c906108c | 1609 | else |
bf75c8c1 AC |
1610 | /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most |
1611 | address of the current frame. Things might be easier if the | |
1612 | ->frame pointed to the outer-most address of the frame. In the | |
1613 | mean time, the address of the prev frame is used as the base | |
1614 | address of this frame. */ | |
618ce49f | 1615 | frame_addr = DEPRECATED_FRAME_CHAIN (fi); |
c5aa993b | 1616 | |
c906108c SS |
1617 | /* if != -1, fdatap->saved_fpr is the smallest number of saved_fpr. |
1618 | All fpr's from saved_fpr to fp31 are saved. */ | |
1619 | ||
1620 | if (fdatap->saved_fpr >= 0) | |
1621 | { | |
1622 | int i; | |
7a78ae4e | 1623 | CORE_ADDR fpr_addr = frame_addr + fdatap->fpr_offset; |
c906108c SS |
1624 | for (i = fdatap->saved_fpr; i < 32; i++) |
1625 | { | |
1b1d3794 | 1626 | deprecated_get_frame_saved_regs (fi)[FP0_REGNUM + i] = fpr_addr; |
7a78ae4e | 1627 | fpr_addr += 8; |
c906108c SS |
1628 | } |
1629 | } | |
1630 | ||
1631 | /* if != -1, fdatap->saved_gpr is the smallest number of saved_gpr. | |
1632 | All gpr's from saved_gpr to gpr31 are saved. */ | |
1633 | ||
1634 | if (fdatap->saved_gpr >= 0) | |
1635 | { | |
1636 | int i; | |
7a78ae4e | 1637 | CORE_ADDR gpr_addr = frame_addr + fdatap->gpr_offset; |
c906108c SS |
1638 | for (i = fdatap->saved_gpr; i < 32; i++) |
1639 | { | |
1b1d3794 | 1640 | deprecated_get_frame_saved_regs (fi)[tdep->ppc_gp0_regnum + i] = gpr_addr; |
7a78ae4e | 1641 | gpr_addr += wordsize; |
c906108c SS |
1642 | } |
1643 | } | |
1644 | ||
6be8bc0c EZ |
1645 | /* if != -1, fdatap->saved_vr is the smallest number of saved_vr. |
1646 | All vr's from saved_vr to vr31 are saved. */ | |
1647 | if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) | |
1648 | { | |
1649 | if (fdatap->saved_vr >= 0) | |
1650 | { | |
1651 | int i; | |
1652 | CORE_ADDR vr_addr = frame_addr + fdatap->vr_offset; | |
1653 | for (i = fdatap->saved_vr; i < 32; i++) | |
1654 | { | |
1b1d3794 | 1655 | deprecated_get_frame_saved_regs (fi)[tdep->ppc_vr0_regnum + i] = vr_addr; |
12c266ea | 1656 | vr_addr += DEPRECATED_REGISTER_RAW_SIZE (tdep->ppc_vr0_regnum); |
6be8bc0c EZ |
1657 | } |
1658 | } | |
1659 | } | |
1660 | ||
96ff0de4 EZ |
1661 | /* if != -1, fdatap->saved_ev is the smallest number of saved_ev. |
1662 | All vr's from saved_ev to ev31 are saved. ????? */ | |
1663 | if (tdep->ppc_ev0_regnum != -1 && tdep->ppc_ev31_regnum != -1) | |
1664 | { | |
1665 | if (fdatap->saved_ev >= 0) | |
1666 | { | |
1667 | int i; | |
1668 | CORE_ADDR ev_addr = frame_addr + fdatap->ev_offset; | |
1669 | for (i = fdatap->saved_ev; i < 32; i++) | |
1670 | { | |
1b1d3794 AC |
1671 | deprecated_get_frame_saved_regs (fi)[tdep->ppc_ev0_regnum + i] = ev_addr; |
1672 | deprecated_get_frame_saved_regs (fi)[tdep->ppc_gp0_regnum + i] = ev_addr + 4; | |
12c266ea | 1673 | ev_addr += DEPRECATED_REGISTER_RAW_SIZE (tdep->ppc_ev0_regnum); |
96ff0de4 EZ |
1674 | } |
1675 | } | |
1676 | } | |
1677 | ||
c906108c SS |
1678 | /* If != 0, fdatap->cr_offset is the offset from the frame that holds |
1679 | the CR. */ | |
1680 | if (fdatap->cr_offset != 0) | |
1b1d3794 | 1681 | deprecated_get_frame_saved_regs (fi)[tdep->ppc_cr_regnum] = frame_addr + fdatap->cr_offset; |
c906108c SS |
1682 | |
1683 | /* If != 0, fdatap->lr_offset is the offset from the frame that holds | |
1684 | the LR. */ | |
1685 | if (fdatap->lr_offset != 0) | |
1b1d3794 | 1686 | deprecated_get_frame_saved_regs (fi)[tdep->ppc_lr_regnum] = frame_addr + fdatap->lr_offset; |
6be8bc0c EZ |
1687 | |
1688 | /* If != 0, fdatap->vrsave_offset is the offset from the frame that holds | |
1689 | the VRSAVE. */ | |
1690 | if (fdatap->vrsave_offset != 0) | |
1b1d3794 | 1691 | deprecated_get_frame_saved_regs (fi)[tdep->ppc_vrsave_regnum] = frame_addr + fdatap->vrsave_offset; |
c906108c SS |
1692 | } |
1693 | ||
1694 | /* Return the address of a frame. This is the inital %sp value when the frame | |
64366f1c EZ |
1695 | was first allocated. For functions calling alloca(), it might be saved in |
1696 | an alloca register. */ | |
c906108c SS |
1697 | |
1698 | static CORE_ADDR | |
7a78ae4e | 1699 | frame_initial_stack_address (struct frame_info *fi) |
c906108c SS |
1700 | { |
1701 | CORE_ADDR tmpaddr; | |
1702 | struct rs6000_framedata fdata; | |
1703 | struct frame_info *callee_fi; | |
1704 | ||
64366f1c EZ |
1705 | /* If the initial stack pointer (frame address) of this frame is known, |
1706 | just return it. */ | |
c906108c | 1707 | |
c9012c71 AC |
1708 | if (get_frame_extra_info (fi)->initial_sp) |
1709 | return get_frame_extra_info (fi)->initial_sp; | |
c906108c | 1710 | |
64366f1c | 1711 | /* Find out if this function is using an alloca register. */ |
c906108c | 1712 | |
be41e9f4 | 1713 | (void) skip_prologue (get_frame_func (fi), get_frame_pc (fi), &fdata); |
c906108c | 1714 | |
64366f1c EZ |
1715 | /* If saved registers of this frame are not known yet, read and |
1716 | cache them. */ | |
c906108c | 1717 | |
1b1d3794 | 1718 | if (!deprecated_get_frame_saved_regs (fi)) |
c906108c SS |
1719 | frame_get_saved_regs (fi, &fdata); |
1720 | ||
1721 | /* If no alloca register used, then fi->frame is the value of the %sp for | |
64366f1c | 1722 | this frame, and it is good enough. */ |
c906108c SS |
1723 | |
1724 | if (fdata.alloca_reg < 0) | |
1725 | { | |
c9012c71 AC |
1726 | get_frame_extra_info (fi)->initial_sp = get_frame_base (fi); |
1727 | return get_frame_extra_info (fi)->initial_sp; | |
c906108c SS |
1728 | } |
1729 | ||
953836b2 AC |
1730 | /* There is an alloca register, use its value, in the current frame, |
1731 | as the initial stack pointer. */ | |
1732 | { | |
d9d9c31f | 1733 | char tmpbuf[MAX_REGISTER_SIZE]; |
953836b2 AC |
1734 | if (frame_register_read (fi, fdata.alloca_reg, tmpbuf)) |
1735 | { | |
c9012c71 | 1736 | get_frame_extra_info (fi)->initial_sp |
953836b2 | 1737 | = extract_unsigned_integer (tmpbuf, |
12c266ea | 1738 | DEPRECATED_REGISTER_RAW_SIZE (fdata.alloca_reg)); |
953836b2 AC |
1739 | } |
1740 | else | |
1741 | /* NOTE: cagney/2002-04-17: At present the only time | |
1742 | frame_register_read will fail is when the register isn't | |
1743 | available. If that does happen, use the frame. */ | |
c9012c71 | 1744 | get_frame_extra_info (fi)->initial_sp = get_frame_base (fi); |
953836b2 | 1745 | } |
c9012c71 | 1746 | return get_frame_extra_info (fi)->initial_sp; |
c906108c SS |
1747 | } |
1748 | ||
7a78ae4e ND |
1749 | /* Describe the pointer in each stack frame to the previous stack frame |
1750 | (its caller). */ | |
1751 | ||
618ce49f AC |
1752 | /* DEPRECATED_FRAME_CHAIN takes a frame's nominal address and produces |
1753 | the frame's chain-pointer. */ | |
7a78ae4e ND |
1754 | |
1755 | /* In the case of the RS/6000, the frame's nominal address | |
1756 | is the address of a 4-byte word containing the calling frame's address. */ | |
1757 | ||
9aa1e687 | 1758 | CORE_ADDR |
7a78ae4e | 1759 | rs6000_frame_chain (struct frame_info *thisframe) |
c906108c | 1760 | { |
7a78ae4e | 1761 | CORE_ADDR fp, fpp, lr; |
21283beb | 1762 | int wordsize = gdbarch_tdep (current_gdbarch)->wordsize; |
c906108c | 1763 | |
bdd78e62 | 1764 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (thisframe), |
8b36eed8 AC |
1765 | get_frame_base (thisframe), |
1766 | get_frame_base (thisframe))) | |
9f3b7f07 AC |
1767 | /* A dummy frame always correctly chains back to the previous |
1768 | frame. */ | |
8b36eed8 | 1769 | return read_memory_addr (get_frame_base (thisframe), wordsize); |
c906108c | 1770 | |
627b3ba2 | 1771 | if (deprecated_inside_entry_file (get_frame_pc (thisframe)) |
bdd78e62 | 1772 | || get_frame_pc (thisframe) == entry_point_address ()) |
c906108c SS |
1773 | return 0; |
1774 | ||
5a203e44 | 1775 | if ((get_frame_type (thisframe) == SIGTRAMP_FRAME)) |
8b36eed8 AC |
1776 | fp = read_memory_addr (get_frame_base (thisframe) + SIG_FRAME_FP_OFFSET, |
1777 | wordsize); | |
75e3c1f9 AC |
1778 | else if (get_next_frame (thisframe) != NULL |
1779 | && (get_frame_type (get_next_frame (thisframe)) == SIGTRAMP_FRAME) | |
c877c8e6 | 1780 | && FRAMELESS_FUNCTION_INVOCATION (thisframe)) |
c906108c SS |
1781 | /* A frameless function interrupted by a signal did not change the |
1782 | frame pointer. */ | |
c193f6ac | 1783 | fp = get_frame_base (thisframe); |
c906108c | 1784 | else |
8b36eed8 | 1785 | fp = read_memory_addr (get_frame_base (thisframe), wordsize); |
7a78ae4e ND |
1786 | return fp; |
1787 | } | |
1788 | ||
1789 | /* Return the size of register REG when words are WORDSIZE bytes long. If REG | |
64366f1c | 1790 | isn't available with that word size, return 0. */ |
7a78ae4e ND |
1791 | |
1792 | static int | |
1793 | regsize (const struct reg *reg, int wordsize) | |
1794 | { | |
1795 | return wordsize == 8 ? reg->sz64 : reg->sz32; | |
1796 | } | |
1797 | ||
1798 | /* Return the name of register number N, or null if no such register exists | |
64366f1c | 1799 | in the current architecture. */ |
7a78ae4e | 1800 | |
fa88f677 | 1801 | static const char * |
7a78ae4e ND |
1802 | rs6000_register_name (int n) |
1803 | { | |
21283beb | 1804 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
7a78ae4e ND |
1805 | const struct reg *reg = tdep->regs + n; |
1806 | ||
1807 | if (!regsize (reg, tdep->wordsize)) | |
1808 | return NULL; | |
1809 | return reg->name; | |
1810 | } | |
1811 | ||
1812 | /* Index within `registers' of the first byte of the space for | |
1813 | register N. */ | |
1814 | ||
1815 | static int | |
1816 | rs6000_register_byte (int n) | |
1817 | { | |
21283beb | 1818 | return gdbarch_tdep (current_gdbarch)->regoff[n]; |
7a78ae4e ND |
1819 | } |
1820 | ||
1821 | /* Return the number of bytes of storage in the actual machine representation | |
64366f1c | 1822 | for register N if that register is available, else return 0. */ |
7a78ae4e ND |
1823 | |
1824 | static int | |
1825 | rs6000_register_raw_size (int n) | |
1826 | { | |
21283beb | 1827 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
7a78ae4e ND |
1828 | const struct reg *reg = tdep->regs + n; |
1829 | return regsize (reg, tdep->wordsize); | |
1830 | } | |
1831 | ||
7a78ae4e ND |
1832 | /* Return the GDB type object for the "standard" data type |
1833 | of data in register N. */ | |
1834 | ||
1835 | static struct type * | |
fba45db2 | 1836 | rs6000_register_virtual_type (int n) |
7a78ae4e | 1837 | { |
21283beb | 1838 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
7a78ae4e ND |
1839 | const struct reg *reg = tdep->regs + n; |
1840 | ||
1fcc0bb8 EZ |
1841 | if (reg->fpr) |
1842 | return builtin_type_double; | |
1843 | else | |
1844 | { | |
1845 | int size = regsize (reg, tdep->wordsize); | |
1846 | switch (size) | |
1847 | { | |
449a5da4 AC |
1848 | case 0: |
1849 | return builtin_type_int0; | |
1850 | case 4: | |
1851 | return builtin_type_int32; | |
1fcc0bb8 | 1852 | case 8: |
c8001721 EZ |
1853 | if (tdep->ppc_ev0_regnum <= n && n <= tdep->ppc_ev31_regnum) |
1854 | return builtin_type_vec64; | |
1855 | else | |
1856 | return builtin_type_int64; | |
1fcc0bb8 EZ |
1857 | break; |
1858 | case 16: | |
08cf96df | 1859 | return builtin_type_vec128; |
1fcc0bb8 EZ |
1860 | break; |
1861 | default: | |
449a5da4 AC |
1862 | internal_error (__FILE__, __LINE__, "Register %d size %d unknown", |
1863 | n, size); | |
1fcc0bb8 EZ |
1864 | } |
1865 | } | |
7a78ae4e ND |
1866 | } |
1867 | ||
7a78ae4e ND |
1868 | /* Return whether register N requires conversion when moving from raw format |
1869 | to virtual format. | |
1870 | ||
1871 | The register format for RS/6000 floating point registers is always | |
64366f1c | 1872 | double, we need a conversion if the memory format is float. */ |
7a78ae4e ND |
1873 | |
1874 | static int | |
1875 | rs6000_register_convertible (int n) | |
1876 | { | |
21283beb | 1877 | const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + n; |
7a78ae4e ND |
1878 | return reg->fpr; |
1879 | } | |
1880 | ||
1881 | /* Convert data from raw format for register N in buffer FROM | |
64366f1c | 1882 | to virtual format with type TYPE in buffer TO. */ |
7a78ae4e ND |
1883 | |
1884 | static void | |
1885 | rs6000_register_convert_to_virtual (int n, struct type *type, | |
1886 | char *from, char *to) | |
1887 | { | |
12c266ea | 1888 | if (TYPE_LENGTH (type) != DEPRECATED_REGISTER_RAW_SIZE (n)) |
7a292a7a | 1889 | { |
12c266ea | 1890 | double val = deprecated_extract_floating (from, DEPRECATED_REGISTER_RAW_SIZE (n)); |
f1908289 | 1891 | deprecated_store_floating (to, TYPE_LENGTH (type), val); |
7a78ae4e ND |
1892 | } |
1893 | else | |
12c266ea | 1894 | memcpy (to, from, DEPRECATED_REGISTER_RAW_SIZE (n)); |
7a78ae4e ND |
1895 | } |
1896 | ||
1897 | /* Convert data from virtual format with type TYPE in buffer FROM | |
64366f1c | 1898 | to raw format for register N in buffer TO. */ |
7a292a7a | 1899 | |
7a78ae4e ND |
1900 | static void |
1901 | rs6000_register_convert_to_raw (struct type *type, int n, | |
781a750d | 1902 | const char *from, char *to) |
7a78ae4e | 1903 | { |
12c266ea | 1904 | if (TYPE_LENGTH (type) != DEPRECATED_REGISTER_RAW_SIZE (n)) |
7a78ae4e | 1905 | { |
f1908289 | 1906 | double val = deprecated_extract_floating (from, TYPE_LENGTH (type)); |
12c266ea | 1907 | deprecated_store_floating (to, DEPRECATED_REGISTER_RAW_SIZE (n), val); |
7a292a7a | 1908 | } |
7a78ae4e | 1909 | else |
12c266ea | 1910 | memcpy (to, from, DEPRECATED_REGISTER_RAW_SIZE (n)); |
7a78ae4e | 1911 | } |
c906108c | 1912 | |
c8001721 EZ |
1913 | static void |
1914 | e500_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
1915 | int reg_nr, void *buffer) | |
1916 | { | |
1917 | int base_regnum; | |
1918 | int offset = 0; | |
d9d9c31f | 1919 | char temp_buffer[MAX_REGISTER_SIZE]; |
c8001721 EZ |
1920 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1921 | ||
1922 | if (reg_nr >= tdep->ppc_gp0_regnum | |
1923 | && reg_nr <= tdep->ppc_gplast_regnum) | |
1924 | { | |
1925 | base_regnum = reg_nr - tdep->ppc_gp0_regnum + tdep->ppc_ev0_regnum; | |
1926 | ||
1927 | /* Build the value in the provided buffer. */ | |
1928 | /* Read the raw register of which this one is the lower portion. */ | |
1929 | regcache_raw_read (regcache, base_regnum, temp_buffer); | |
1930 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
1931 | offset = 4; | |
1932 | memcpy ((char *) buffer, temp_buffer + offset, 4); | |
1933 | } | |
1934 | } | |
1935 | ||
1936 | static void | |
1937 | e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
1938 | int reg_nr, const void *buffer) | |
1939 | { | |
1940 | int base_regnum; | |
1941 | int offset = 0; | |
d9d9c31f | 1942 | char temp_buffer[MAX_REGISTER_SIZE]; |
c8001721 EZ |
1943 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1944 | ||
1945 | if (reg_nr >= tdep->ppc_gp0_regnum | |
1946 | && reg_nr <= tdep->ppc_gplast_regnum) | |
1947 | { | |
1948 | base_regnum = reg_nr - tdep->ppc_gp0_regnum + tdep->ppc_ev0_regnum; | |
1949 | /* reg_nr is 32 bit here, and base_regnum is 64 bits. */ | |
1950 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
1951 | offset = 4; | |
1952 | ||
1953 | /* Let's read the value of the base register into a temporary | |
1954 | buffer, so that overwriting the last four bytes with the new | |
1955 | value of the pseudo will leave the upper 4 bytes unchanged. */ | |
1956 | regcache_raw_read (regcache, base_regnum, temp_buffer); | |
1957 | ||
1958 | /* Write as an 8 byte quantity. */ | |
1959 | memcpy (temp_buffer + offset, (char *) buffer, 4); | |
1960 | regcache_raw_write (regcache, base_regnum, temp_buffer); | |
1961 | } | |
1962 | } | |
1963 | ||
1964 | /* Convert a dwarf2 register number to a gdb REGNUM. */ | |
1965 | static int | |
1966 | e500_dwarf2_reg_to_regnum (int num) | |
1967 | { | |
1968 | int regnum; | |
1969 | if (0 <= num && num <= 31) | |
1970 | return num + gdbarch_tdep (current_gdbarch)->ppc_gp0_regnum; | |
1971 | else | |
1972 | return num; | |
1973 | } | |
1974 | ||
2188cbdd | 1975 | /* Convert a dbx stab register number (from `r' declaration) to a gdb |
64366f1c | 1976 | REGNUM. */ |
2188cbdd EZ |
1977 | static int |
1978 | rs6000_stab_reg_to_regnum (int num) | |
1979 | { | |
1980 | int regnum; | |
1981 | switch (num) | |
1982 | { | |
1983 | case 64: | |
1984 | regnum = gdbarch_tdep (current_gdbarch)->ppc_mq_regnum; | |
1985 | break; | |
1986 | case 65: | |
1987 | regnum = gdbarch_tdep (current_gdbarch)->ppc_lr_regnum; | |
1988 | break; | |
1989 | case 66: | |
1990 | regnum = gdbarch_tdep (current_gdbarch)->ppc_ctr_regnum; | |
1991 | break; | |
1992 | case 76: | |
1993 | regnum = gdbarch_tdep (current_gdbarch)->ppc_xer_regnum; | |
1994 | break; | |
1995 | default: | |
1996 | regnum = num; | |
1997 | break; | |
1998 | } | |
1999 | return regnum; | |
2000 | } | |
2001 | ||
7a78ae4e ND |
2002 | static void |
2003 | rs6000_store_return_value (struct type *type, char *valbuf) | |
2004 | { | |
ace1378a EZ |
2005 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2006 | ||
7a78ae4e ND |
2007 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
2008 | ||
2009 | /* Floating point values are returned starting from FPR1 and up. | |
2010 | Say a double_double_double type could be returned in | |
64366f1c | 2011 | FPR1/FPR2/FPR3 triple. */ |
7a78ae4e | 2012 | |
62700349 | 2013 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (FP0_REGNUM + 1), valbuf, |
73937e03 | 2014 | TYPE_LENGTH (type)); |
ace1378a EZ |
2015 | else if (TYPE_CODE (type) == TYPE_CODE_ARRAY) |
2016 | { | |
2017 | if (TYPE_LENGTH (type) == 16 | |
2018 | && TYPE_VECTOR (type)) | |
62700349 | 2019 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (tdep->ppc_vr0_regnum + 2), |
73937e03 | 2020 | valbuf, TYPE_LENGTH (type)); |
ace1378a | 2021 | } |
7a78ae4e | 2022 | else |
64366f1c | 2023 | /* Everything else is returned in GPR3 and up. */ |
62700349 | 2024 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (gdbarch_tdep (current_gdbarch)->ppc_gp0_regnum + 3), |
73937e03 | 2025 | valbuf, TYPE_LENGTH (type)); |
7a78ae4e ND |
2026 | } |
2027 | ||
2028 | /* Extract from an array REGBUF containing the (raw) register state | |
2029 | the address in which a function should return its structure value, | |
2030 | as a CORE_ADDR (or an expression that can be used as one). */ | |
2031 | ||
2032 | static CORE_ADDR | |
11269d7e AC |
2033 | rs6000_extract_struct_value_address (struct regcache *regcache) |
2034 | { | |
2035 | /* FIXME: cagney/2002-09-26: PR gdb/724: When making an inferior | |
2036 | function call GDB knows the address of the struct return value | |
2037 | and hence, should not need to call this function. Unfortunately, | |
e8a8712a AC |
2038 | the current call_function_by_hand() code only saves the most |
2039 | recent struct address leading to occasional calls. The code | |
2040 | should instead maintain a stack of such addresses (in the dummy | |
2041 | frame object). */ | |
11269d7e AC |
2042 | /* NOTE: cagney/2002-09-26: Return 0 which indicates that we've |
2043 | really got no idea where the return value is being stored. While | |
2044 | r3, on function entry, contained the address it will have since | |
2045 | been reused (scratch) and hence wouldn't be valid */ | |
2046 | return 0; | |
7a78ae4e ND |
2047 | } |
2048 | ||
2049 | /* Return whether PC is in a dummy function call. | |
2050 | ||
2051 | FIXME: This just checks for the end of the stack, which is broken | |
64366f1c | 2052 | for things like stepping through gcc nested function stubs. */ |
7a78ae4e ND |
2053 | |
2054 | static int | |
2055 | rs6000_pc_in_call_dummy (CORE_ADDR pc, CORE_ADDR sp, CORE_ADDR fp) | |
2056 | { | |
2057 | return sp < pc && pc < fp; | |
2058 | } | |
2059 | ||
64366f1c | 2060 | /* Hook called when a new child process is started. */ |
7a78ae4e ND |
2061 | |
2062 | void | |
2063 | rs6000_create_inferior (int pid) | |
2064 | { | |
2065 | if (rs6000_set_host_arch_hook) | |
2066 | rs6000_set_host_arch_hook (pid); | |
c906108c SS |
2067 | } |
2068 | \f | |
e2d0e7eb | 2069 | /* Support for CONVERT_FROM_FUNC_PTR_ADDR (ARCH, ADDR, TARG). |
7a78ae4e ND |
2070 | |
2071 | Usually a function pointer's representation is simply the address | |
2072 | of the function. On the RS/6000 however, a function pointer is | |
2073 | represented by a pointer to a TOC entry. This TOC entry contains | |
2074 | three words, the first word is the address of the function, the | |
2075 | second word is the TOC pointer (r2), and the third word is the | |
2076 | static chain value. Throughout GDB it is currently assumed that a | |
2077 | function pointer contains the address of the function, which is not | |
2078 | easy to fix. In addition, the conversion of a function address to | |
2079 | a function pointer would require allocation of a TOC entry in the | |
2080 | inferior's memory space, with all its drawbacks. To be able to | |
2081 | call C++ virtual methods in the inferior (which are called via | |
f517ea4e | 2082 | function pointers), find_function_addr uses this function to get the |
7a78ae4e ND |
2083 | function address from a function pointer. */ |
2084 | ||
f517ea4e PS |
2085 | /* Return real function address if ADDR (a function pointer) is in the data |
2086 | space and is therefore a special function pointer. */ | |
c906108c | 2087 | |
b9362cc7 | 2088 | static CORE_ADDR |
e2d0e7eb AC |
2089 | rs6000_convert_from_func_ptr_addr (struct gdbarch *gdbarch, |
2090 | CORE_ADDR addr, | |
2091 | struct target_ops *targ) | |
c906108c SS |
2092 | { |
2093 | struct obj_section *s; | |
2094 | ||
2095 | s = find_pc_section (addr); | |
2096 | if (s && s->the_bfd_section->flags & SEC_CODE) | |
7a78ae4e | 2097 | return addr; |
c906108c | 2098 | |
7a78ae4e | 2099 | /* ADDR is in the data space, so it's a special function pointer. */ |
21283beb | 2100 | return read_memory_addr (addr, gdbarch_tdep (current_gdbarch)->wordsize); |
c906108c | 2101 | } |
c906108c | 2102 | \f |
c5aa993b | 2103 | |
7a78ae4e | 2104 | /* Handling the various POWER/PowerPC variants. */ |
c906108c SS |
2105 | |
2106 | ||
7a78ae4e ND |
2107 | /* The arrays here called registers_MUMBLE hold information about available |
2108 | registers. | |
c906108c SS |
2109 | |
2110 | For each family of PPC variants, I've tried to isolate out the | |
2111 | common registers and put them up front, so that as long as you get | |
2112 | the general family right, GDB will correctly identify the registers | |
2113 | common to that family. The common register sets are: | |
2114 | ||
2115 | For the 60x family: hid0 hid1 iabr dabr pir | |
2116 | ||
2117 | For the 505 and 860 family: eie eid nri | |
2118 | ||
2119 | For the 403 and 403GC: icdbdr esr dear evpr cdbcr tsr tcr pit tbhi | |
c5aa993b JM |
2120 | tblo srr2 srr3 dbsr dbcr iac1 iac2 dac1 dac2 dccr iccr pbl1 |
2121 | pbu1 pbl2 pbu2 | |
c906108c SS |
2122 | |
2123 | Most of these register groups aren't anything formal. I arrived at | |
2124 | them by looking at the registers that occurred in more than one | |
6f5987a6 KB |
2125 | processor. |
2126 | ||
2127 | Note: kevinb/2002-04-30: Support for the fpscr register was added | |
2128 | during April, 2002. Slot 70 is being used for PowerPC and slot 71 | |
2129 | for Power. For PowerPC, slot 70 was unused and was already in the | |
2130 | PPC_UISA_SPRS which is ideally where fpscr should go. For Power, | |
2131 | slot 70 was being used for "mq", so the next available slot (71) | |
2132 | was chosen. It would have been nice to be able to make the | |
2133 | register numbers the same across processor cores, but this wasn't | |
2134 | possible without either 1) renumbering some registers for some | |
2135 | processors or 2) assigning fpscr to a really high slot that's | |
2136 | larger than any current register number. Doing (1) is bad because | |
2137 | existing stubs would break. Doing (2) is undesirable because it | |
2138 | would introduce a really large gap between fpscr and the rest of | |
2139 | the registers for most processors. */ | |
7a78ae4e | 2140 | |
64366f1c | 2141 | /* Convenience macros for populating register arrays. */ |
7a78ae4e | 2142 | |
64366f1c | 2143 | /* Within another macro, convert S to a string. */ |
7a78ae4e ND |
2144 | |
2145 | #define STR(s) #s | |
2146 | ||
2147 | /* Return a struct reg defining register NAME that's 32 bits on 32-bit systems | |
64366f1c | 2148 | and 64 bits on 64-bit systems. */ |
489461e2 | 2149 | #define R(name) { STR(name), 4, 8, 0, 0 } |
7a78ae4e ND |
2150 | |
2151 | /* Return a struct reg defining register NAME that's 32 bits on all | |
64366f1c | 2152 | systems. */ |
489461e2 | 2153 | #define R4(name) { STR(name), 4, 4, 0, 0 } |
7a78ae4e ND |
2154 | |
2155 | /* Return a struct reg defining register NAME that's 64 bits on all | |
64366f1c | 2156 | systems. */ |
489461e2 | 2157 | #define R8(name) { STR(name), 8, 8, 0, 0 } |
7a78ae4e | 2158 | |
1fcc0bb8 | 2159 | /* Return a struct reg defining register NAME that's 128 bits on all |
64366f1c | 2160 | systems. */ |
489461e2 | 2161 | #define R16(name) { STR(name), 16, 16, 0, 0 } |
1fcc0bb8 | 2162 | |
64366f1c | 2163 | /* Return a struct reg defining floating-point register NAME. */ |
489461e2 EZ |
2164 | #define F(name) { STR(name), 8, 8, 1, 0 } |
2165 | ||
64366f1c | 2166 | /* Return a struct reg defining a pseudo register NAME. */ |
489461e2 | 2167 | #define P(name) { STR(name), 4, 8, 0, 1} |
7a78ae4e ND |
2168 | |
2169 | /* Return a struct reg defining register NAME that's 32 bits on 32-bit | |
64366f1c | 2170 | systems and that doesn't exist on 64-bit systems. */ |
489461e2 | 2171 | #define R32(name) { STR(name), 4, 0, 0, 0 } |
7a78ae4e ND |
2172 | |
2173 | /* Return a struct reg defining register NAME that's 64 bits on 64-bit | |
64366f1c | 2174 | systems and that doesn't exist on 32-bit systems. */ |
489461e2 | 2175 | #define R64(name) { STR(name), 0, 8, 0, 0 } |
7a78ae4e | 2176 | |
64366f1c | 2177 | /* Return a struct reg placeholder for a register that doesn't exist. */ |
489461e2 | 2178 | #define R0 { 0, 0, 0, 0, 0 } |
7a78ae4e ND |
2179 | |
2180 | /* UISA registers common across all architectures, including POWER. */ | |
2181 | ||
2182 | #define COMMON_UISA_REGS \ | |
2183 | /* 0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), \ | |
2184 | /* 8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \ | |
2185 | /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \ | |
2186 | /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \ | |
2187 | /* 32 */ F(f0), F(f1), F(f2), F(f3), F(f4), F(f5), F(f6), F(f7), \ | |
2188 | /* 40 */ F(f8), F(f9), F(f10),F(f11),F(f12),F(f13),F(f14),F(f15), \ | |
2189 | /* 48 */ F(f16),F(f17),F(f18),F(f19),F(f20),F(f21),F(f22),F(f23), \ | |
2190 | /* 56 */ F(f24),F(f25),F(f26),F(f27),F(f28),F(f29),F(f30),F(f31), \ | |
2191 | /* 64 */ R(pc), R(ps) | |
2192 | ||
ebeac11a EZ |
2193 | #define COMMON_UISA_NOFP_REGS \ |
2194 | /* 0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), \ | |
2195 | /* 8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \ | |
2196 | /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \ | |
2197 | /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \ | |
2198 | /* 32 */ R0, R0, R0, R0, R0, R0, R0, R0, \ | |
2199 | /* 40 */ R0, R0, R0, R0, R0, R0, R0, R0, \ | |
2200 | /* 48 */ R0, R0, R0, R0, R0, R0, R0, R0, \ | |
2201 | /* 56 */ R0, R0, R0, R0, R0, R0, R0, R0, \ | |
2202 | /* 64 */ R(pc), R(ps) | |
2203 | ||
7a78ae4e ND |
2204 | /* UISA-level SPRs for PowerPC. */ |
2205 | #define PPC_UISA_SPRS \ | |
e3f36dbd | 2206 | /* 66 */ R4(cr), R(lr), R(ctr), R4(xer), R4(fpscr) |
7a78ae4e | 2207 | |
c8001721 EZ |
2208 | /* UISA-level SPRs for PowerPC without floating point support. */ |
2209 | #define PPC_UISA_NOFP_SPRS \ | |
2210 | /* 66 */ R4(cr), R(lr), R(ctr), R4(xer), R0 | |
2211 | ||
7a78ae4e ND |
2212 | /* Segment registers, for PowerPC. */ |
2213 | #define PPC_SEGMENT_REGS \ | |
2214 | /* 71 */ R32(sr0), R32(sr1), R32(sr2), R32(sr3), \ | |
2215 | /* 75 */ R32(sr4), R32(sr5), R32(sr6), R32(sr7), \ | |
2216 | /* 79 */ R32(sr8), R32(sr9), R32(sr10), R32(sr11), \ | |
2217 | /* 83 */ R32(sr12), R32(sr13), R32(sr14), R32(sr15) | |
2218 | ||
2219 | /* OEA SPRs for PowerPC. */ | |
2220 | #define PPC_OEA_SPRS \ | |
2221 | /* 87 */ R4(pvr), \ | |
2222 | /* 88 */ R(ibat0u), R(ibat0l), R(ibat1u), R(ibat1l), \ | |
2223 | /* 92 */ R(ibat2u), R(ibat2l), R(ibat3u), R(ibat3l), \ | |
2224 | /* 96 */ R(dbat0u), R(dbat0l), R(dbat1u), R(dbat1l), \ | |
2225 | /* 100 */ R(dbat2u), R(dbat2l), R(dbat3u), R(dbat3l), \ | |
2226 | /* 104 */ R(sdr1), R64(asr), R(dar), R4(dsisr), \ | |
2227 | /* 108 */ R(sprg0), R(sprg1), R(sprg2), R(sprg3), \ | |
2228 | /* 112 */ R(srr0), R(srr1), R(tbl), R(tbu), \ | |
2229 | /* 116 */ R4(dec), R(dabr), R4(ear) | |
2230 | ||
64366f1c | 2231 | /* AltiVec registers. */ |
1fcc0bb8 EZ |
2232 | #define PPC_ALTIVEC_REGS \ |
2233 | /*119*/R16(vr0), R16(vr1), R16(vr2), R16(vr3), R16(vr4), R16(vr5), R16(vr6), R16(vr7), \ | |
2234 | /*127*/R16(vr8), R16(vr9), R16(vr10),R16(vr11),R16(vr12),R16(vr13),R16(vr14),R16(vr15), \ | |
2235 | /*135*/R16(vr16),R16(vr17),R16(vr18),R16(vr19),R16(vr20),R16(vr21),R16(vr22),R16(vr23), \ | |
2236 | /*143*/R16(vr24),R16(vr25),R16(vr26),R16(vr27),R16(vr28),R16(vr29),R16(vr30),R16(vr31), \ | |
2237 | /*151*/R4(vscr), R4(vrsave) | |
2238 | ||
c8001721 EZ |
2239 | /* Vectors of hi-lo general purpose registers. */ |
2240 | #define PPC_EV_REGS \ | |
2241 | /* 0*/R8(ev0), R8(ev1), R8(ev2), R8(ev3), R8(ev4), R8(ev5), R8(ev6), R8(ev7), \ | |
2242 | /* 8*/R8(ev8), R8(ev9), R8(ev10),R8(ev11),R8(ev12),R8(ev13),R8(ev14),R8(ev15), \ | |
2243 | /*16*/R8(ev16),R8(ev17),R8(ev18),R8(ev19),R8(ev20),R8(ev21),R8(ev22),R8(ev23), \ | |
2244 | /*24*/R8(ev24),R8(ev25),R8(ev26),R8(ev27),R8(ev28),R8(ev29),R8(ev30),R8(ev31) | |
2245 | ||
2246 | /* Lower half of the EV registers. */ | |
2247 | #define PPC_GPRS_PSEUDO_REGS \ | |
2248 | /* 0 */ P(r0), P(r1), P(r2), P(r3), P(r4), P(r5), P(r6), P(r7), \ | |
2249 | /* 8 */ P(r8), P(r9), P(r10),P(r11),P(r12),P(r13),P(r14),P(r15), \ | |
2250 | /* 16 */ P(r16),P(r17),P(r18),P(r19),P(r20),P(r21),P(r22),P(r23), \ | |
338ef23d | 2251 | /* 24 */ P(r24),P(r25),P(r26),P(r27),P(r28),P(r29),P(r30),P(r31) |
c8001721 | 2252 | |
7a78ae4e | 2253 | /* IBM POWER (pre-PowerPC) architecture, user-level view. We only cover |
64366f1c | 2254 | user-level SPR's. */ |
7a78ae4e | 2255 | static const struct reg registers_power[] = |
c906108c | 2256 | { |
7a78ae4e | 2257 | COMMON_UISA_REGS, |
e3f36dbd KB |
2258 | /* 66 */ R4(cnd), R(lr), R(cnt), R4(xer), R4(mq), |
2259 | /* 71 */ R4(fpscr) | |
c906108c SS |
2260 | }; |
2261 | ||
7a78ae4e | 2262 | /* PowerPC UISA - a PPC processor as viewed by user-level code. A UISA-only |
64366f1c | 2263 | view of the PowerPC. */ |
7a78ae4e | 2264 | static const struct reg registers_powerpc[] = |
c906108c | 2265 | { |
7a78ae4e | 2266 | COMMON_UISA_REGS, |
1fcc0bb8 EZ |
2267 | PPC_UISA_SPRS, |
2268 | PPC_ALTIVEC_REGS | |
c906108c SS |
2269 | }; |
2270 | ||
ebeac11a EZ |
2271 | /* PowerPC UISA - a PPC processor as viewed by user-level |
2272 | code, but without floating point registers. */ | |
2273 | static const struct reg registers_powerpc_nofp[] = | |
2274 | { | |
2275 | COMMON_UISA_NOFP_REGS, | |
2276 | PPC_UISA_SPRS | |
2277 | }; | |
2278 | ||
64366f1c | 2279 | /* IBM PowerPC 403. */ |
7a78ae4e | 2280 | static const struct reg registers_403[] = |
c5aa993b | 2281 | { |
7a78ae4e ND |
2282 | COMMON_UISA_REGS, |
2283 | PPC_UISA_SPRS, | |
2284 | PPC_SEGMENT_REGS, | |
2285 | PPC_OEA_SPRS, | |
2286 | /* 119 */ R(icdbdr), R(esr), R(dear), R(evpr), | |
2287 | /* 123 */ R(cdbcr), R(tsr), R(tcr), R(pit), | |
2288 | /* 127 */ R(tbhi), R(tblo), R(srr2), R(srr3), | |
2289 | /* 131 */ R(dbsr), R(dbcr), R(iac1), R(iac2), | |
2290 | /* 135 */ R(dac1), R(dac2), R(dccr), R(iccr), | |
2291 | /* 139 */ R(pbl1), R(pbu1), R(pbl2), R(pbu2) | |
c906108c SS |
2292 | }; |
2293 | ||
64366f1c | 2294 | /* IBM PowerPC 403GC. */ |
7a78ae4e | 2295 | static const struct reg registers_403GC[] = |
c5aa993b | 2296 | { |
7a78ae4e ND |
2297 | COMMON_UISA_REGS, |
2298 | PPC_UISA_SPRS, | |
2299 | PPC_SEGMENT_REGS, | |
2300 | PPC_OEA_SPRS, | |
2301 | /* 119 */ R(icdbdr), R(esr), R(dear), R(evpr), | |
2302 | /* 123 */ R(cdbcr), R(tsr), R(tcr), R(pit), | |
2303 | /* 127 */ R(tbhi), R(tblo), R(srr2), R(srr3), | |
2304 | /* 131 */ R(dbsr), R(dbcr), R(iac1), R(iac2), | |
2305 | /* 135 */ R(dac1), R(dac2), R(dccr), R(iccr), | |
2306 | /* 139 */ R(pbl1), R(pbu1), R(pbl2), R(pbu2), | |
2307 | /* 143 */ R(zpr), R(pid), R(sgr), R(dcwr), | |
2308 | /* 147 */ R(tbhu), R(tblu) | |
c906108c SS |
2309 | }; |
2310 | ||
64366f1c | 2311 | /* Motorola PowerPC 505. */ |
7a78ae4e | 2312 | static const struct reg registers_505[] = |
c5aa993b | 2313 | { |
7a78ae4e ND |
2314 | COMMON_UISA_REGS, |
2315 | PPC_UISA_SPRS, | |
2316 | PPC_SEGMENT_REGS, | |
2317 | PPC_OEA_SPRS, | |
2318 | /* 119 */ R(eie), R(eid), R(nri) | |
c906108c SS |
2319 | }; |
2320 | ||
64366f1c | 2321 | /* Motorola PowerPC 860 or 850. */ |
7a78ae4e | 2322 | static const struct reg registers_860[] = |
c5aa993b | 2323 | { |
7a78ae4e ND |
2324 | COMMON_UISA_REGS, |
2325 | PPC_UISA_SPRS, | |
2326 | PPC_SEGMENT_REGS, | |
2327 | PPC_OEA_SPRS, | |
2328 | /* 119 */ R(eie), R(eid), R(nri), R(cmpa), | |
2329 | /* 123 */ R(cmpb), R(cmpc), R(cmpd), R(icr), | |
2330 | /* 127 */ R(der), R(counta), R(countb), R(cmpe), | |
2331 | /* 131 */ R(cmpf), R(cmpg), R(cmph), R(lctrl1), | |
2332 | /* 135 */ R(lctrl2), R(ictrl), R(bar), R(ic_cst), | |
2333 | /* 139 */ R(ic_adr), R(ic_dat), R(dc_cst), R(dc_adr), | |
2334 | /* 143 */ R(dc_dat), R(dpdr), R(dpir), R(immr), | |
2335 | /* 147 */ R(mi_ctr), R(mi_ap), R(mi_epn), R(mi_twc), | |
2336 | /* 151 */ R(mi_rpn), R(md_ctr), R(m_casid), R(md_ap), | |
2337 | /* 155 */ R(md_epn), R(md_twb), R(md_twc), R(md_rpn), | |
2338 | /* 159 */ R(m_tw), R(mi_dbcam), R(mi_dbram0), R(mi_dbram1), | |
2339 | /* 163 */ R(md_dbcam), R(md_dbram0), R(md_dbram1) | |
c906108c SS |
2340 | }; |
2341 | ||
7a78ae4e ND |
2342 | /* Motorola PowerPC 601. Note that the 601 has different register numbers |
2343 | for reading and writing RTCU and RTCL. However, how one reads and writes a | |
c906108c | 2344 | register is the stub's problem. */ |
7a78ae4e | 2345 | static const struct reg registers_601[] = |
c5aa993b | 2346 | { |
7a78ae4e ND |
2347 | COMMON_UISA_REGS, |
2348 | PPC_UISA_SPRS, | |
2349 | PPC_SEGMENT_REGS, | |
2350 | PPC_OEA_SPRS, | |
2351 | /* 119 */ R(hid0), R(hid1), R(iabr), R(dabr), | |
2352 | /* 123 */ R(pir), R(mq), R(rtcu), R(rtcl) | |
c906108c SS |
2353 | }; |
2354 | ||
64366f1c | 2355 | /* Motorola PowerPC 602. */ |
7a78ae4e | 2356 | static const struct reg registers_602[] = |
c5aa993b | 2357 | { |
7a78ae4e ND |
2358 | COMMON_UISA_REGS, |
2359 | PPC_UISA_SPRS, | |
2360 | PPC_SEGMENT_REGS, | |
2361 | PPC_OEA_SPRS, | |
2362 | /* 119 */ R(hid0), R(hid1), R(iabr), R0, | |
2363 | /* 123 */ R0, R(tcr), R(ibr), R(esassr), | |
2364 | /* 127 */ R(sebr), R(ser), R(sp), R(lt) | |
c906108c SS |
2365 | }; |
2366 | ||
64366f1c | 2367 | /* Motorola/IBM PowerPC 603 or 603e. */ |
7a78ae4e | 2368 | static const struct reg registers_603[] = |
c5aa993b | 2369 | { |
7a78ae4e ND |
2370 | COMMON_UISA_REGS, |
2371 | PPC_UISA_SPRS, | |
2372 | PPC_SEGMENT_REGS, | |
2373 | PPC_OEA_SPRS, | |
2374 | /* 119 */ R(hid0), R(hid1), R(iabr), R0, | |
2375 | /* 123 */ R0, R(dmiss), R(dcmp), R(hash1), | |
2376 | /* 127 */ R(hash2), R(imiss), R(icmp), R(rpa) | |
c906108c SS |
2377 | }; |
2378 | ||
64366f1c | 2379 | /* Motorola PowerPC 604 or 604e. */ |
7a78ae4e | 2380 | static const struct reg registers_604[] = |
c5aa993b | 2381 | { |
7a78ae4e ND |
2382 | COMMON_UISA_REGS, |
2383 | PPC_UISA_SPRS, | |
2384 | PPC_SEGMENT_REGS, | |
2385 | PPC_OEA_SPRS, | |
2386 | /* 119 */ R(hid0), R(hid1), R(iabr), R(dabr), | |
2387 | /* 123 */ R(pir), R(mmcr0), R(pmc1), R(pmc2), | |
2388 | /* 127 */ R(sia), R(sda) | |
c906108c SS |
2389 | }; |
2390 | ||
64366f1c | 2391 | /* Motorola/IBM PowerPC 750 or 740. */ |
7a78ae4e | 2392 | static const struct reg registers_750[] = |
c5aa993b | 2393 | { |
7a78ae4e ND |
2394 | COMMON_UISA_REGS, |
2395 | PPC_UISA_SPRS, | |
2396 | PPC_SEGMENT_REGS, | |
2397 | PPC_OEA_SPRS, | |
2398 | /* 119 */ R(hid0), R(hid1), R(iabr), R(dabr), | |
2399 | /* 123 */ R0, R(ummcr0), R(upmc1), R(upmc2), | |
2400 | /* 127 */ R(usia), R(ummcr1), R(upmc3), R(upmc4), | |
2401 | /* 131 */ R(mmcr0), R(pmc1), R(pmc2), R(sia), | |
2402 | /* 135 */ R(mmcr1), R(pmc3), R(pmc4), R(l2cr), | |
2403 | /* 139 */ R(ictc), R(thrm1), R(thrm2), R(thrm3) | |
c906108c SS |
2404 | }; |
2405 | ||
2406 | ||
64366f1c | 2407 | /* Motorola PowerPC 7400. */ |
1fcc0bb8 EZ |
2408 | static const struct reg registers_7400[] = |
2409 | { | |
2410 | /* gpr0-gpr31, fpr0-fpr31 */ | |
2411 | COMMON_UISA_REGS, | |
2412 | /* ctr, xre, lr, cr */ | |
2413 | PPC_UISA_SPRS, | |
2414 | /* sr0-sr15 */ | |
2415 | PPC_SEGMENT_REGS, | |
2416 | PPC_OEA_SPRS, | |
2417 | /* vr0-vr31, vrsave, vscr */ | |
2418 | PPC_ALTIVEC_REGS | |
2419 | /* FIXME? Add more registers? */ | |
2420 | }; | |
2421 | ||
c8001721 EZ |
2422 | /* Motorola e500. */ |
2423 | static const struct reg registers_e500[] = | |
2424 | { | |
2425 | R(pc), R(ps), | |
2426 | /* cr, lr, ctr, xer, "" */ | |
2427 | PPC_UISA_NOFP_SPRS, | |
2428 | /* 7...38 */ | |
2429 | PPC_EV_REGS, | |
338ef23d AC |
2430 | R8(acc), R(spefscr), |
2431 | /* NOTE: Add new registers here the end of the raw register | |
2432 | list and just before the first pseudo register. */ | |
c8001721 EZ |
2433 | /* 39...70 */ |
2434 | PPC_GPRS_PSEUDO_REGS | |
2435 | }; | |
2436 | ||
c906108c | 2437 | /* Information about a particular processor variant. */ |
7a78ae4e | 2438 | |
c906108c | 2439 | struct variant |
c5aa993b JM |
2440 | { |
2441 | /* Name of this variant. */ | |
2442 | char *name; | |
c906108c | 2443 | |
c5aa993b JM |
2444 | /* English description of the variant. */ |
2445 | char *description; | |
c906108c | 2446 | |
64366f1c | 2447 | /* bfd_arch_info.arch corresponding to variant. */ |
7a78ae4e ND |
2448 | enum bfd_architecture arch; |
2449 | ||
64366f1c | 2450 | /* bfd_arch_info.mach corresponding to variant. */ |
7a78ae4e ND |
2451 | unsigned long mach; |
2452 | ||
489461e2 EZ |
2453 | /* Number of real registers. */ |
2454 | int nregs; | |
2455 | ||
2456 | /* Number of pseudo registers. */ | |
2457 | int npregs; | |
2458 | ||
2459 | /* Number of total registers (the sum of nregs and npregs). */ | |
2460 | int num_tot_regs; | |
2461 | ||
c5aa993b JM |
2462 | /* Table of register names; registers[R] is the name of the register |
2463 | number R. */ | |
7a78ae4e | 2464 | const struct reg *regs; |
c5aa993b | 2465 | }; |
c906108c | 2466 | |
489461e2 EZ |
2467 | #define tot_num_registers(list) (sizeof (list) / sizeof((list)[0])) |
2468 | ||
2469 | static int | |
2470 | num_registers (const struct reg *reg_list, int num_tot_regs) | |
2471 | { | |
2472 | int i; | |
2473 | int nregs = 0; | |
2474 | ||
2475 | for (i = 0; i < num_tot_regs; i++) | |
2476 | if (!reg_list[i].pseudo) | |
2477 | nregs++; | |
2478 | ||
2479 | return nregs; | |
2480 | } | |
2481 | ||
2482 | static int | |
2483 | num_pseudo_registers (const struct reg *reg_list, int num_tot_regs) | |
2484 | { | |
2485 | int i; | |
2486 | int npregs = 0; | |
2487 | ||
2488 | for (i = 0; i < num_tot_regs; i++) | |
2489 | if (reg_list[i].pseudo) | |
2490 | npregs ++; | |
2491 | ||
2492 | return npregs; | |
2493 | } | |
c906108c | 2494 | |
c906108c SS |
2495 | /* Information in this table comes from the following web sites: |
2496 | IBM: http://www.chips.ibm.com:80/products/embedded/ | |
2497 | Motorola: http://www.mot.com/SPS/PowerPC/ | |
2498 | ||
2499 | I'm sure I've got some of the variant descriptions not quite right. | |
2500 | Please report any inaccuracies you find to GDB's maintainer. | |
2501 | ||
2502 | If you add entries to this table, please be sure to allow the new | |
2503 | value as an argument to the --with-cpu flag, in configure.in. */ | |
2504 | ||
489461e2 | 2505 | static struct variant variants[] = |
c906108c | 2506 | { |
489461e2 | 2507 | |
7a78ae4e | 2508 | {"powerpc", "PowerPC user-level", bfd_arch_powerpc, |
489461e2 EZ |
2509 | bfd_mach_ppc, -1, -1, tot_num_registers (registers_powerpc), |
2510 | registers_powerpc}, | |
7a78ae4e | 2511 | {"power", "POWER user-level", bfd_arch_rs6000, |
489461e2 EZ |
2512 | bfd_mach_rs6k, -1, -1, tot_num_registers (registers_power), |
2513 | registers_power}, | |
7a78ae4e | 2514 | {"403", "IBM PowerPC 403", bfd_arch_powerpc, |
489461e2 EZ |
2515 | bfd_mach_ppc_403, -1, -1, tot_num_registers (registers_403), |
2516 | registers_403}, | |
7a78ae4e | 2517 | {"601", "Motorola PowerPC 601", bfd_arch_powerpc, |
489461e2 EZ |
2518 | bfd_mach_ppc_601, -1, -1, tot_num_registers (registers_601), |
2519 | registers_601}, | |
7a78ae4e | 2520 | {"602", "Motorola PowerPC 602", bfd_arch_powerpc, |
489461e2 EZ |
2521 | bfd_mach_ppc_602, -1, -1, tot_num_registers (registers_602), |
2522 | registers_602}, | |
7a78ae4e | 2523 | {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc, |
489461e2 EZ |
2524 | bfd_mach_ppc_603, -1, -1, tot_num_registers (registers_603), |
2525 | registers_603}, | |
7a78ae4e | 2526 | {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc, |
489461e2 EZ |
2527 | 604, -1, -1, tot_num_registers (registers_604), |
2528 | registers_604}, | |
7a78ae4e | 2529 | {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc, |
489461e2 EZ |
2530 | bfd_mach_ppc_403gc, -1, -1, tot_num_registers (registers_403GC), |
2531 | registers_403GC}, | |
7a78ae4e | 2532 | {"505", "Motorola PowerPC 505", bfd_arch_powerpc, |
489461e2 EZ |
2533 | bfd_mach_ppc_505, -1, -1, tot_num_registers (registers_505), |
2534 | registers_505}, | |
7a78ae4e | 2535 | {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc, |
489461e2 EZ |
2536 | bfd_mach_ppc_860, -1, -1, tot_num_registers (registers_860), |
2537 | registers_860}, | |
7a78ae4e | 2538 | {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc, |
489461e2 EZ |
2539 | bfd_mach_ppc_750, -1, -1, tot_num_registers (registers_750), |
2540 | registers_750}, | |
1fcc0bb8 | 2541 | {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc, |
489461e2 EZ |
2542 | bfd_mach_ppc_7400, -1, -1, tot_num_registers (registers_7400), |
2543 | registers_7400}, | |
c8001721 EZ |
2544 | {"e500", "Motorola PowerPC e500", bfd_arch_powerpc, |
2545 | bfd_mach_ppc_e500, -1, -1, tot_num_registers (registers_e500), | |
2546 | registers_e500}, | |
7a78ae4e | 2547 | |
5d57ee30 KB |
2548 | /* 64-bit */ |
2549 | {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc, | |
489461e2 EZ |
2550 | bfd_mach_ppc64, -1, -1, tot_num_registers (registers_powerpc), |
2551 | registers_powerpc}, | |
7a78ae4e | 2552 | {"620", "Motorola PowerPC 620", bfd_arch_powerpc, |
489461e2 EZ |
2553 | bfd_mach_ppc_620, -1, -1, tot_num_registers (registers_powerpc), |
2554 | registers_powerpc}, | |
5d57ee30 | 2555 | {"630", "Motorola PowerPC 630", bfd_arch_powerpc, |
489461e2 EZ |
2556 | bfd_mach_ppc_630, -1, -1, tot_num_registers (registers_powerpc), |
2557 | registers_powerpc}, | |
7a78ae4e | 2558 | {"a35", "PowerPC A35", bfd_arch_powerpc, |
489461e2 EZ |
2559 | bfd_mach_ppc_a35, -1, -1, tot_num_registers (registers_powerpc), |
2560 | registers_powerpc}, | |
5d57ee30 | 2561 | {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc, |
489461e2 EZ |
2562 | bfd_mach_ppc_rs64ii, -1, -1, tot_num_registers (registers_powerpc), |
2563 | registers_powerpc}, | |
5d57ee30 | 2564 | {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc, |
489461e2 EZ |
2565 | bfd_mach_ppc_rs64iii, -1, -1, tot_num_registers (registers_powerpc), |
2566 | registers_powerpc}, | |
5d57ee30 | 2567 | |
64366f1c | 2568 | /* FIXME: I haven't checked the register sets of the following. */ |
7a78ae4e | 2569 | {"rs1", "IBM POWER RS1", bfd_arch_rs6000, |
489461e2 EZ |
2570 | bfd_mach_rs6k_rs1, -1, -1, tot_num_registers (registers_power), |
2571 | registers_power}, | |
7a78ae4e | 2572 | {"rsc", "IBM POWER RSC", bfd_arch_rs6000, |
489461e2 EZ |
2573 | bfd_mach_rs6k_rsc, -1, -1, tot_num_registers (registers_power), |
2574 | registers_power}, | |
7a78ae4e | 2575 | {"rs2", "IBM POWER RS2", bfd_arch_rs6000, |
489461e2 EZ |
2576 | bfd_mach_rs6k_rs2, -1, -1, tot_num_registers (registers_power), |
2577 | registers_power}, | |
7a78ae4e | 2578 | |
489461e2 | 2579 | {0, 0, 0, 0, 0, 0, 0, 0} |
c906108c SS |
2580 | }; |
2581 | ||
64366f1c | 2582 | /* Initialize the number of registers and pseudo registers in each variant. */ |
489461e2 EZ |
2583 | |
2584 | static void | |
2585 | init_variants (void) | |
2586 | { | |
2587 | struct variant *v; | |
2588 | ||
2589 | for (v = variants; v->name; v++) | |
2590 | { | |
2591 | if (v->nregs == -1) | |
2592 | v->nregs = num_registers (v->regs, v->num_tot_regs); | |
2593 | if (v->npregs == -1) | |
2594 | v->npregs = num_pseudo_registers (v->regs, v->num_tot_regs); | |
2595 | } | |
2596 | } | |
c906108c | 2597 | |
7a78ae4e | 2598 | /* Return the variant corresponding to architecture ARCH and machine number |
64366f1c | 2599 | MACH. If no such variant exists, return null. */ |
c906108c | 2600 | |
7a78ae4e ND |
2601 | static const struct variant * |
2602 | find_variant_by_arch (enum bfd_architecture arch, unsigned long mach) | |
c906108c | 2603 | { |
7a78ae4e | 2604 | const struct variant *v; |
c5aa993b | 2605 | |
7a78ae4e ND |
2606 | for (v = variants; v->name; v++) |
2607 | if (arch == v->arch && mach == v->mach) | |
2608 | return v; | |
c906108c | 2609 | |
7a78ae4e | 2610 | return NULL; |
c906108c | 2611 | } |
9364a0ef EZ |
2612 | |
2613 | static int | |
2614 | gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info) | |
2615 | { | |
2616 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
2617 | return print_insn_big_powerpc (memaddr, info); | |
2618 | else | |
2619 | return print_insn_little_powerpc (memaddr, info); | |
2620 | } | |
7a78ae4e | 2621 | \f |
7a78ae4e ND |
2622 | /* Initialize the current architecture based on INFO. If possible, re-use an |
2623 | architecture from ARCHES, which is a list of architectures already created | |
2624 | during this debugging session. | |
c906108c | 2625 | |
7a78ae4e | 2626 | Called e.g. at program startup, when reading a core file, and when reading |
64366f1c | 2627 | a binary file. */ |
c906108c | 2628 | |
7a78ae4e ND |
2629 | static struct gdbarch * |
2630 | rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
2631 | { | |
2632 | struct gdbarch *gdbarch; | |
2633 | struct gdbarch_tdep *tdep; | |
9aa1e687 | 2634 | int wordsize, from_xcoff_exec, from_elf_exec, power, i, off; |
7a78ae4e ND |
2635 | struct reg *regs; |
2636 | const struct variant *v; | |
2637 | enum bfd_architecture arch; | |
2638 | unsigned long mach; | |
2639 | bfd abfd; | |
7b112f9c | 2640 | int sysv_abi; |
5bf1c677 | 2641 | asection *sect; |
7a78ae4e | 2642 | |
9aa1e687 | 2643 | from_xcoff_exec = info.abfd && info.abfd->format == bfd_object && |
7a78ae4e ND |
2644 | bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour; |
2645 | ||
9aa1e687 KB |
2646 | from_elf_exec = info.abfd && info.abfd->format == bfd_object && |
2647 | bfd_get_flavour (info.abfd) == bfd_target_elf_flavour; | |
2648 | ||
2649 | sysv_abi = info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour; | |
2650 | ||
e712c1cf | 2651 | /* Check word size. If INFO is from a binary file, infer it from |
64366f1c | 2652 | that, else choose a likely default. */ |
9aa1e687 | 2653 | if (from_xcoff_exec) |
c906108c | 2654 | { |
11ed25ac | 2655 | if (bfd_xcoff_is_xcoff64 (info.abfd)) |
7a78ae4e ND |
2656 | wordsize = 8; |
2657 | else | |
2658 | wordsize = 4; | |
c906108c | 2659 | } |
9aa1e687 KB |
2660 | else if (from_elf_exec) |
2661 | { | |
2662 | if (elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
2663 | wordsize = 8; | |
2664 | else | |
2665 | wordsize = 4; | |
2666 | } | |
c906108c | 2667 | else |
7a78ae4e | 2668 | { |
27b15785 KB |
2669 | if (info.bfd_arch_info != NULL && info.bfd_arch_info->bits_per_word != 0) |
2670 | wordsize = info.bfd_arch_info->bits_per_word / | |
2671 | info.bfd_arch_info->bits_per_byte; | |
2672 | else | |
2673 | wordsize = 4; | |
7a78ae4e | 2674 | } |
c906108c | 2675 | |
64366f1c | 2676 | /* Find a candidate among extant architectures. */ |
7a78ae4e ND |
2677 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
2678 | arches != NULL; | |
2679 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
2680 | { | |
2681 | /* Word size in the various PowerPC bfd_arch_info structs isn't | |
2682 | meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform | |
64366f1c | 2683 | separate word size check. */ |
7a78ae4e | 2684 | tdep = gdbarch_tdep (arches->gdbarch); |
4be87837 | 2685 | if (tdep && tdep->wordsize == wordsize) |
7a78ae4e ND |
2686 | return arches->gdbarch; |
2687 | } | |
c906108c | 2688 | |
7a78ae4e ND |
2689 | /* None found, create a new architecture from INFO, whose bfd_arch_info |
2690 | validity depends on the source: | |
2691 | - executable useless | |
2692 | - rs6000_host_arch() good | |
2693 | - core file good | |
2694 | - "set arch" trust blindly | |
2695 | - GDB startup useless but harmless */ | |
c906108c | 2696 | |
9aa1e687 | 2697 | if (!from_xcoff_exec) |
c906108c | 2698 | { |
b732d07d | 2699 | arch = info.bfd_arch_info->arch; |
7a78ae4e | 2700 | mach = info.bfd_arch_info->mach; |
c906108c | 2701 | } |
7a78ae4e | 2702 | else |
c906108c | 2703 | { |
7a78ae4e | 2704 | arch = bfd_arch_powerpc; |
35cec841 | 2705 | bfd_default_set_arch_mach (&abfd, arch, 0); |
7a78ae4e | 2706 | info.bfd_arch_info = bfd_get_arch_info (&abfd); |
35cec841 | 2707 | mach = info.bfd_arch_info->mach; |
7a78ae4e ND |
2708 | } |
2709 | tdep = xmalloc (sizeof (struct gdbarch_tdep)); | |
2710 | tdep->wordsize = wordsize; | |
5bf1c677 EZ |
2711 | |
2712 | /* For e500 executables, the apuinfo section is of help here. Such | |
2713 | section contains the identifier and revision number of each | |
2714 | Application-specific Processing Unit that is present on the | |
2715 | chip. The content of the section is determined by the assembler | |
2716 | which looks at each instruction and determines which unit (and | |
2717 | which version of it) can execute it. In our case we just look for | |
2718 | the existance of the section. */ | |
2719 | ||
2720 | if (info.abfd) | |
2721 | { | |
2722 | sect = bfd_get_section_by_name (info.abfd, ".PPC.EMB.apuinfo"); | |
2723 | if (sect) | |
2724 | { | |
2725 | arch = info.bfd_arch_info->arch; | |
2726 | mach = bfd_mach_ppc_e500; | |
2727 | bfd_default_set_arch_mach (&abfd, arch, mach); | |
2728 | info.bfd_arch_info = bfd_get_arch_info (&abfd); | |
2729 | } | |
2730 | } | |
2731 | ||
7a78ae4e ND |
2732 | gdbarch = gdbarch_alloc (&info, tdep); |
2733 | power = arch == bfd_arch_rs6000; | |
2734 | ||
489461e2 EZ |
2735 | /* Initialize the number of real and pseudo registers in each variant. */ |
2736 | init_variants (); | |
2737 | ||
64366f1c | 2738 | /* Choose variant. */ |
7a78ae4e ND |
2739 | v = find_variant_by_arch (arch, mach); |
2740 | if (!v) | |
dd47e6fd EZ |
2741 | return NULL; |
2742 | ||
7a78ae4e ND |
2743 | tdep->regs = v->regs; |
2744 | ||
2188cbdd EZ |
2745 | tdep->ppc_gp0_regnum = 0; |
2746 | tdep->ppc_gplast_regnum = 31; | |
2747 | tdep->ppc_toc_regnum = 2; | |
2748 | tdep->ppc_ps_regnum = 65; | |
2749 | tdep->ppc_cr_regnum = 66; | |
2750 | tdep->ppc_lr_regnum = 67; | |
2751 | tdep->ppc_ctr_regnum = 68; | |
2752 | tdep->ppc_xer_regnum = 69; | |
2753 | if (v->mach == bfd_mach_ppc_601) | |
2754 | tdep->ppc_mq_regnum = 124; | |
e3f36dbd | 2755 | else if (power) |
2188cbdd | 2756 | tdep->ppc_mq_regnum = 70; |
e3f36dbd KB |
2757 | else |
2758 | tdep->ppc_mq_regnum = -1; | |
2759 | tdep->ppc_fpscr_regnum = power ? 71 : 70; | |
2188cbdd | 2760 | |
c8001721 EZ |
2761 | set_gdbarch_pc_regnum (gdbarch, 64); |
2762 | set_gdbarch_sp_regnum (gdbarch, 1); | |
0ba6dca9 | 2763 | set_gdbarch_deprecated_fp_regnum (gdbarch, 1); |
afd48b75 | 2764 | if (sysv_abi && wordsize == 8) |
05580c65 | 2765 | set_gdbarch_return_value (gdbarch, ppc64_sysv_abi_return_value); |
e754ae69 | 2766 | else if (sysv_abi && wordsize == 4) |
05580c65 | 2767 | set_gdbarch_return_value (gdbarch, ppc_sysv_abi_return_value); |
afd48b75 AC |
2768 | else |
2769 | { | |
2770 | set_gdbarch_deprecated_extract_return_value (gdbarch, rs6000_extract_return_value); | |
2771 | set_gdbarch_deprecated_store_return_value (gdbarch, rs6000_store_return_value); | |
2772 | } | |
c8001721 | 2773 | |
1fcc0bb8 EZ |
2774 | if (v->arch == bfd_arch_powerpc) |
2775 | switch (v->mach) | |
2776 | { | |
2777 | case bfd_mach_ppc: | |
2778 | tdep->ppc_vr0_regnum = 71; | |
2779 | tdep->ppc_vrsave_regnum = 104; | |
c8001721 EZ |
2780 | tdep->ppc_ev0_regnum = -1; |
2781 | tdep->ppc_ev31_regnum = -1; | |
1fcc0bb8 EZ |
2782 | break; |
2783 | case bfd_mach_ppc_7400: | |
2784 | tdep->ppc_vr0_regnum = 119; | |
54c2a1e6 | 2785 | tdep->ppc_vrsave_regnum = 152; |
c8001721 EZ |
2786 | tdep->ppc_ev0_regnum = -1; |
2787 | tdep->ppc_ev31_regnum = -1; | |
2788 | break; | |
2789 | case bfd_mach_ppc_e500: | |
338ef23d AC |
2790 | tdep->ppc_gp0_regnum = 41; |
2791 | tdep->ppc_gplast_regnum = tdep->ppc_gp0_regnum + 32 - 1; | |
c8001721 EZ |
2792 | tdep->ppc_toc_regnum = -1; |
2793 | tdep->ppc_ps_regnum = 1; | |
2794 | tdep->ppc_cr_regnum = 2; | |
2795 | tdep->ppc_lr_regnum = 3; | |
2796 | tdep->ppc_ctr_regnum = 4; | |
2797 | tdep->ppc_xer_regnum = 5; | |
2798 | tdep->ppc_ev0_regnum = 7; | |
2799 | tdep->ppc_ev31_regnum = 38; | |
2800 | set_gdbarch_pc_regnum (gdbarch, 0); | |
338ef23d | 2801 | set_gdbarch_sp_regnum (gdbarch, tdep->ppc_gp0_regnum + 1); |
0ba6dca9 | 2802 | set_gdbarch_deprecated_fp_regnum (gdbarch, tdep->ppc_gp0_regnum + 1); |
c8001721 EZ |
2803 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, e500_dwarf2_reg_to_regnum); |
2804 | set_gdbarch_pseudo_register_read (gdbarch, e500_pseudo_register_read); | |
2805 | set_gdbarch_pseudo_register_write (gdbarch, e500_pseudo_register_write); | |
1fcc0bb8 EZ |
2806 | break; |
2807 | default: | |
2808 | tdep->ppc_vr0_regnum = -1; | |
2809 | tdep->ppc_vrsave_regnum = -1; | |
c8001721 EZ |
2810 | tdep->ppc_ev0_regnum = -1; |
2811 | tdep->ppc_ev31_regnum = -1; | |
1fcc0bb8 EZ |
2812 | break; |
2813 | } | |
2814 | ||
338ef23d AC |
2815 | /* Sanity check on registers. */ |
2816 | gdb_assert (strcmp (tdep->regs[tdep->ppc_gp0_regnum].name, "r0") == 0); | |
2817 | ||
a88376a3 KB |
2818 | /* Set lr_frame_offset. */ |
2819 | if (wordsize == 8) | |
2820 | tdep->lr_frame_offset = 16; | |
2821 | else if (sysv_abi) | |
2822 | tdep->lr_frame_offset = 4; | |
2823 | else | |
2824 | tdep->lr_frame_offset = 8; | |
2825 | ||
2826 | /* Calculate byte offsets in raw register array. */ | |
489461e2 EZ |
2827 | tdep->regoff = xmalloc (v->num_tot_regs * sizeof (int)); |
2828 | for (i = off = 0; i < v->num_tot_regs; i++) | |
7a78ae4e ND |
2829 | { |
2830 | tdep->regoff[i] = off; | |
2831 | off += regsize (v->regs + i, wordsize); | |
c906108c SS |
2832 | } |
2833 | ||
56a6dfb9 KB |
2834 | /* Select instruction printer. */ |
2835 | if (arch == power) | |
9364a0ef | 2836 | set_gdbarch_print_insn (gdbarch, print_insn_rs6000); |
56a6dfb9 | 2837 | else |
9364a0ef | 2838 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_powerpc); |
7495d1dc | 2839 | |
7a78ae4e | 2840 | set_gdbarch_write_pc (gdbarch, generic_target_write_pc); |
7a78ae4e ND |
2841 | |
2842 | set_gdbarch_num_regs (gdbarch, v->nregs); | |
c8001721 | 2843 | set_gdbarch_num_pseudo_regs (gdbarch, v->npregs); |
7a78ae4e | 2844 | set_gdbarch_register_name (gdbarch, rs6000_register_name); |
b1e29e33 | 2845 | set_gdbarch_deprecated_register_size (gdbarch, wordsize); |
b8b527c5 | 2846 | set_gdbarch_deprecated_register_bytes (gdbarch, off); |
9c04cab7 AC |
2847 | set_gdbarch_deprecated_register_byte (gdbarch, rs6000_register_byte); |
2848 | set_gdbarch_deprecated_register_raw_size (gdbarch, rs6000_register_raw_size); | |
9c04cab7 | 2849 | set_gdbarch_deprecated_register_virtual_type (gdbarch, rs6000_register_virtual_type); |
7a78ae4e ND |
2850 | |
2851 | set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT); | |
2852 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); | |
2853 | set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
2854 | set_gdbarch_long_bit (gdbarch, wordsize * TARGET_CHAR_BIT); | |
2855 | set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
2856 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
2857 | set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
ab9fe00e KB |
2858 | if (sysv_abi) |
2859 | set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT); | |
2860 | else | |
2861 | set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
4e409299 | 2862 | set_gdbarch_char_signed (gdbarch, 0); |
7a78ae4e | 2863 | |
11269d7e | 2864 | set_gdbarch_frame_align (gdbarch, rs6000_frame_align); |
8b148df9 AC |
2865 | if (sysv_abi && wordsize == 8) |
2866 | /* PPC64 SYSV. */ | |
2867 | set_gdbarch_frame_red_zone_size (gdbarch, 288); | |
2868 | else if (!sysv_abi && wordsize == 4) | |
5bffac25 AC |
2869 | /* PowerOpen / AIX 32 bit. The saved area or red zone consists of |
2870 | 19 4 byte GPRS + 18 8 byte FPRs giving a total of 220 bytes. | |
2871 | Problem is, 220 isn't frame (16 byte) aligned. Round it up to | |
2872 | 224. */ | |
2873 | set_gdbarch_frame_red_zone_size (gdbarch, 224); | |
a59fe496 | 2874 | set_gdbarch_deprecated_save_dummy_frame_tos (gdbarch, generic_save_dummy_frame_tos); |
7a78ae4e | 2875 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); |
7a78ae4e | 2876 | |
781a750d AC |
2877 | set_gdbarch_deprecated_register_convertible (gdbarch, rs6000_register_convertible); |
2878 | set_gdbarch_deprecated_register_convert_to_virtual (gdbarch, rs6000_register_convert_to_virtual); | |
2879 | set_gdbarch_deprecated_register_convert_to_raw (gdbarch, rs6000_register_convert_to_raw); | |
2188cbdd | 2880 | set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_stab_reg_to_regnum); |
2ea5f656 KB |
2881 | /* Note: kevinb/2002-04-12: I'm not convinced that rs6000_push_arguments() |
2882 | is correct for the SysV ABI when the wordsize is 8, but I'm also | |
2883 | fairly certain that ppc_sysv_abi_push_arguments() will give even | |
2884 | worse results since it only works for 32-bit code. So, for the moment, | |
2885 | we're better off calling rs6000_push_arguments() since it works for | |
2886 | 64-bit code. At some point in the future, this matter needs to be | |
2887 | revisited. */ | |
2888 | if (sysv_abi && wordsize == 4) | |
77b2b6d4 | 2889 | set_gdbarch_push_dummy_call (gdbarch, ppc_sysv_abi_push_dummy_call); |
8be9034a AC |
2890 | else if (sysv_abi && wordsize == 8) |
2891 | set_gdbarch_push_dummy_call (gdbarch, ppc64_sysv_abi_push_dummy_call); | |
9aa1e687 | 2892 | else |
77b2b6d4 | 2893 | set_gdbarch_push_dummy_call (gdbarch, rs6000_push_dummy_call); |
7a78ae4e | 2894 | |
11269d7e | 2895 | set_gdbarch_extract_struct_value_address (gdbarch, rs6000_extract_struct_value_address); |
749b82f6 | 2896 | set_gdbarch_deprecated_pop_frame (gdbarch, rs6000_pop_frame); |
7a78ae4e ND |
2897 | |
2898 | set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue); | |
2899 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
7a78ae4e ND |
2900 | set_gdbarch_breakpoint_from_pc (gdbarch, rs6000_breakpoint_from_pc); |
2901 | ||
6066c3de AC |
2902 | /* Handle the 64-bit SVR4 minimal-symbol convention of using "FN" |
2903 | for the descriptor and ".FN" for the entry-point -- a user | |
2904 | specifying "break FN" will unexpectedly end up with a breakpoint | |
2905 | on the descriptor and not the function. This architecture method | |
2906 | transforms any breakpoints on descriptors into breakpoints on the | |
2907 | corresponding entry point. */ | |
2908 | if (sysv_abi && wordsize == 8) | |
2909 | set_gdbarch_adjust_breakpoint_address (gdbarch, ppc64_sysv_abi_adjust_breakpoint_address); | |
2910 | ||
7a78ae4e ND |
2911 | /* Not sure on this. FIXMEmgo */ |
2912 | set_gdbarch_frame_args_skip (gdbarch, 8); | |
2913 | ||
05580c65 | 2914 | if (!sysv_abi) |
7b112f9c | 2915 | set_gdbarch_use_struct_convention (gdbarch, |
b9ff3018 | 2916 | rs6000_use_struct_convention); |
8e0662df | 2917 | |
7b112f9c JT |
2918 | set_gdbarch_frameless_function_invocation (gdbarch, |
2919 | rs6000_frameless_function_invocation); | |
618ce49f | 2920 | set_gdbarch_deprecated_frame_chain (gdbarch, rs6000_frame_chain); |
8bedc050 | 2921 | set_gdbarch_deprecated_frame_saved_pc (gdbarch, rs6000_frame_saved_pc); |
7b112f9c | 2922 | |
f30ee0bc | 2923 | set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, rs6000_frame_init_saved_regs); |
e9582e71 | 2924 | set_gdbarch_deprecated_init_extra_frame_info (gdbarch, rs6000_init_extra_frame_info); |
7b112f9c | 2925 | |
15813d3f AC |
2926 | if (!sysv_abi) |
2927 | { | |
2928 | /* Handle RS/6000 function pointers (which are really function | |
2929 | descriptors). */ | |
f517ea4e PS |
2930 | set_gdbarch_convert_from_func_ptr_addr (gdbarch, |
2931 | rs6000_convert_from_func_ptr_addr); | |
9aa1e687 | 2932 | } |
42efa47a AC |
2933 | set_gdbarch_deprecated_frame_args_address (gdbarch, rs6000_frame_args_address); |
2934 | set_gdbarch_deprecated_frame_locals_address (gdbarch, rs6000_frame_args_address); | |
6913c89a | 2935 | set_gdbarch_deprecated_saved_pc_after_call (gdbarch, rs6000_saved_pc_after_call); |
7a78ae4e | 2936 | |
143985b7 AF |
2937 | /* Helpers for function argument information. */ |
2938 | set_gdbarch_fetch_pointer_argument (gdbarch, rs6000_fetch_pointer_argument); | |
2939 | ||
7b112f9c | 2940 | /* Hook in ABI-specific overrides, if they have been registered. */ |
4be87837 | 2941 | gdbarch_init_osabi (info, gdbarch); |
7b112f9c | 2942 | |
ef5200c1 AC |
2943 | if (from_xcoff_exec) |
2944 | { | |
2945 | /* NOTE: jimix/2003-06-09: This test should really check for | |
2946 | GDB_OSABI_AIX when that is defined and becomes | |
2947 | available. (Actually, once things are properly split apart, | |
2948 | the test goes away.) */ | |
2949 | /* RS6000/AIX does not support PT_STEP. Has to be simulated. */ | |
2950 | set_gdbarch_software_single_step (gdbarch, rs6000_software_single_step); | |
2951 | } | |
2952 | ||
7a78ae4e | 2953 | return gdbarch; |
c906108c SS |
2954 | } |
2955 | ||
7b112f9c JT |
2956 | static void |
2957 | rs6000_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
2958 | { | |
2959 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2960 | ||
2961 | if (tdep == NULL) | |
2962 | return; | |
2963 | ||
4be87837 | 2964 | /* FIXME: Dump gdbarch_tdep. */ |
7b112f9c JT |
2965 | } |
2966 | ||
1fcc0bb8 EZ |
2967 | static struct cmd_list_element *info_powerpc_cmdlist = NULL; |
2968 | ||
2969 | static void | |
2970 | rs6000_info_powerpc_command (char *args, int from_tty) | |
2971 | { | |
2972 | help_list (info_powerpc_cmdlist, "info powerpc ", class_info, gdb_stdout); | |
2973 | } | |
2974 | ||
c906108c SS |
2975 | /* Initialization code. */ |
2976 | ||
a78f21af | 2977 | extern initialize_file_ftype _initialize_rs6000_tdep; /* -Wmissing-prototypes */ |
b9362cc7 | 2978 | |
c906108c | 2979 | void |
fba45db2 | 2980 | _initialize_rs6000_tdep (void) |
c906108c | 2981 | { |
7b112f9c JT |
2982 | gdbarch_register (bfd_arch_rs6000, rs6000_gdbarch_init, rs6000_dump_tdep); |
2983 | gdbarch_register (bfd_arch_powerpc, rs6000_gdbarch_init, rs6000_dump_tdep); | |
1fcc0bb8 EZ |
2984 | |
2985 | /* Add root prefix command for "info powerpc" commands */ | |
2986 | add_prefix_cmd ("powerpc", class_info, rs6000_info_powerpc_command, | |
2987 | "Various POWERPC info specific commands.", | |
2988 | &info_powerpc_cmdlist, "info powerpc ", 0, &infolist); | |
c906108c | 2989 | } |