Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for GDB, the GNU debugger. |
7aea86e6 AC |
2 | |
3 | Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, | |
4 | 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software | |
5 | Foundation, Inc. | |
c906108c | 6 | |
c5aa993b | 7 | This file is part of GDB. |
c906108c | 8 | |
c5aa993b JM |
9 | This program is free software; you can redistribute it and/or modify |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2 of the License, or | |
12 | (at your option) any later version. | |
c906108c | 13 | |
c5aa993b JM |
14 | This program is distributed in the hope that it will be useful, |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
c906108c | 18 | |
c5aa993b JM |
19 | You should have received a copy of the GNU General Public License |
20 | along with this program; if not, write to the Free Software | |
21 | Foundation, Inc., 59 Temple Place - Suite 330, | |
22 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
23 | |
24 | #include "defs.h" | |
25 | #include "frame.h" | |
26 | #include "inferior.h" | |
27 | #include "symtab.h" | |
28 | #include "target.h" | |
29 | #include "gdbcore.h" | |
30 | #include "gdbcmd.h" | |
c906108c | 31 | #include "objfiles.h" |
7a78ae4e | 32 | #include "arch-utils.h" |
4e052eda | 33 | #include "regcache.h" |
d195bc9f | 34 | #include "regset.h" |
d16aafd8 | 35 | #include "doublest.h" |
fd0407d6 | 36 | #include "value.h" |
1fcc0bb8 | 37 | #include "parser-defs.h" |
4be87837 | 38 | #include "osabi.h" |
7a78ae4e | 39 | |
2fccf04a | 40 | #include "libbfd.h" /* for bfd_default_set_arch_mach */ |
7a78ae4e | 41 | #include "coff/internal.h" /* for libcoff.h */ |
2fccf04a | 42 | #include "libcoff.h" /* for xcoff_data */ |
11ed25ac KB |
43 | #include "coff/xcoff.h" |
44 | #include "libxcoff.h" | |
7a78ae4e | 45 | |
9aa1e687 | 46 | #include "elf-bfd.h" |
7a78ae4e | 47 | |
6ded7999 | 48 | #include "solib-svr4.h" |
9aa1e687 | 49 | #include "ppc-tdep.h" |
7a78ae4e | 50 | |
338ef23d | 51 | #include "gdb_assert.h" |
a89aa300 | 52 | #include "dis-asm.h" |
338ef23d | 53 | |
61a65099 KB |
54 | #include "trad-frame.h" |
55 | #include "frame-unwind.h" | |
56 | #include "frame-base.h" | |
57 | ||
7a78ae4e ND |
58 | /* If the kernel has to deliver a signal, it pushes a sigcontext |
59 | structure on the stack and then calls the signal handler, passing | |
60 | the address of the sigcontext in an argument register. Usually | |
61 | the signal handler doesn't save this register, so we have to | |
62 | access the sigcontext structure via an offset from the signal handler | |
63 | frame. | |
64 | The following constants were determined by experimentation on AIX 3.2. */ | |
65 | #define SIG_FRAME_PC_OFFSET 96 | |
66 | #define SIG_FRAME_LR_OFFSET 108 | |
67 | #define SIG_FRAME_FP_OFFSET 284 | |
68 | ||
7a78ae4e ND |
69 | /* To be used by skip_prologue. */ |
70 | ||
71 | struct rs6000_framedata | |
72 | { | |
73 | int offset; /* total size of frame --- the distance | |
74 | by which we decrement sp to allocate | |
75 | the frame */ | |
76 | int saved_gpr; /* smallest # of saved gpr */ | |
77 | int saved_fpr; /* smallest # of saved fpr */ | |
6be8bc0c | 78 | int saved_vr; /* smallest # of saved vr */ |
96ff0de4 | 79 | int saved_ev; /* smallest # of saved ev */ |
7a78ae4e ND |
80 | int alloca_reg; /* alloca register number (frame ptr) */ |
81 | char frameless; /* true if frameless functions. */ | |
82 | char nosavedpc; /* true if pc not saved. */ | |
83 | int gpr_offset; /* offset of saved gprs from prev sp */ | |
84 | int fpr_offset; /* offset of saved fprs from prev sp */ | |
6be8bc0c | 85 | int vr_offset; /* offset of saved vrs from prev sp */ |
96ff0de4 | 86 | int ev_offset; /* offset of saved evs from prev sp */ |
7a78ae4e ND |
87 | int lr_offset; /* offset of saved lr */ |
88 | int cr_offset; /* offset of saved cr */ | |
6be8bc0c | 89 | int vrsave_offset; /* offset of saved vrsave register */ |
7a78ae4e ND |
90 | }; |
91 | ||
92 | /* Description of a single register. */ | |
93 | ||
94 | struct reg | |
95 | { | |
96 | char *name; /* name of register */ | |
97 | unsigned char sz32; /* size on 32-bit arch, 0 if nonextant */ | |
98 | unsigned char sz64; /* size on 64-bit arch, 0 if nonextant */ | |
99 | unsigned char fpr; /* whether register is floating-point */ | |
489461e2 | 100 | unsigned char pseudo; /* whether register is pseudo */ |
7a78ae4e ND |
101 | }; |
102 | ||
c906108c SS |
103 | /* Breakpoint shadows for the single step instructions will be kept here. */ |
104 | ||
c5aa993b JM |
105 | static struct sstep_breaks |
106 | { | |
107 | /* Address, or 0 if this is not in use. */ | |
108 | CORE_ADDR address; | |
109 | /* Shadow contents. */ | |
110 | char data[4]; | |
111 | } | |
112 | stepBreaks[2]; | |
c906108c SS |
113 | |
114 | /* Hook for determining the TOC address when calling functions in the | |
115 | inferior under AIX. The initialization code in rs6000-nat.c sets | |
116 | this hook to point to find_toc_address. */ | |
117 | ||
7a78ae4e ND |
118 | CORE_ADDR (*rs6000_find_toc_address_hook) (CORE_ADDR) = NULL; |
119 | ||
120 | /* Hook to set the current architecture when starting a child process. | |
121 | rs6000-nat.c sets this. */ | |
122 | ||
123 | void (*rs6000_set_host_arch_hook) (int) = NULL; | |
c906108c SS |
124 | |
125 | /* Static function prototypes */ | |
126 | ||
a14ed312 KB |
127 | static CORE_ADDR branch_dest (int opcode, int instr, CORE_ADDR pc, |
128 | CORE_ADDR safety); | |
077276e8 KB |
129 | static CORE_ADDR skip_prologue (CORE_ADDR, CORE_ADDR, |
130 | struct rs6000_framedata *); | |
c906108c | 131 | |
64b84175 KB |
132 | /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */ |
133 | int | |
134 | altivec_register_p (int regno) | |
135 | { | |
136 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
137 | if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0) | |
138 | return 0; | |
139 | else | |
140 | return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum); | |
141 | } | |
142 | ||
383f0f5b JB |
143 | |
144 | /* Return non-zero if the architecture described by GDBARCH has | |
145 | floating-point registers (f0 --- f31 and fpscr). */ | |
0a613259 AC |
146 | int |
147 | ppc_floating_point_unit_p (struct gdbarch *gdbarch) | |
148 | { | |
383f0f5b JB |
149 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
150 | ||
151 | return (tdep->ppc_fp0_regnum >= 0 | |
152 | && tdep->ppc_fpscr_regnum >= 0); | |
0a613259 | 153 | } |
d195bc9f MK |
154 | \f |
155 | ||
156 | /* Register set support functions. */ | |
157 | ||
158 | static void | |
159 | ppc_supply_reg (struct regcache *regcache, int regnum, | |
160 | const char *regs, size_t offset) | |
161 | { | |
162 | if (regnum != -1 && offset != -1) | |
163 | regcache_raw_supply (regcache, regnum, regs + offset); | |
164 | } | |
165 | ||
166 | static void | |
167 | ppc_collect_reg (const struct regcache *regcache, int regnum, | |
168 | char *regs, size_t offset) | |
169 | { | |
170 | if (regnum != -1 && offset != -1) | |
171 | regcache_raw_collect (regcache, regnum, regs + offset); | |
172 | } | |
173 | ||
174 | /* Supply register REGNUM in the general-purpose register set REGSET | |
175 | from the buffer specified by GREGS and LEN to register cache | |
176 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
177 | ||
178 | void | |
179 | ppc_supply_gregset (const struct regset *regset, struct regcache *regcache, | |
180 | int regnum, const void *gregs, size_t len) | |
181 | { | |
182 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
183 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
184 | const struct ppc_reg_offsets *offsets = regset->descr; | |
185 | size_t offset; | |
186 | int i; | |
187 | ||
188 | for (i = 0, offset = offsets->r0_offset; i < 32; i++, offset += 4) | |
189 | { | |
190 | if (regnum == -1 || regnum == i) | |
191 | ppc_supply_reg (regcache, i, gregs, offset); | |
192 | } | |
193 | ||
194 | if (regnum == -1 || regnum == PC_REGNUM) | |
195 | ppc_supply_reg (regcache, PC_REGNUM, gregs, offsets->pc_offset); | |
196 | if (regnum == -1 || regnum == tdep->ppc_ps_regnum) | |
197 | ppc_supply_reg (regcache, tdep->ppc_ps_regnum, | |
198 | gregs, offsets->ps_offset); | |
199 | if (regnum == -1 || regnum == tdep->ppc_cr_regnum) | |
200 | ppc_supply_reg (regcache, tdep->ppc_cr_regnum, | |
201 | gregs, offsets->cr_offset); | |
202 | if (regnum == -1 || regnum == tdep->ppc_lr_regnum) | |
203 | ppc_supply_reg (regcache, tdep->ppc_lr_regnum, | |
204 | gregs, offsets->lr_offset); | |
205 | if (regnum == -1 || regnum == tdep->ppc_ctr_regnum) | |
206 | ppc_supply_reg (regcache, tdep->ppc_ctr_regnum, | |
207 | gregs, offsets->ctr_offset); | |
208 | if (regnum == -1 || regnum == tdep->ppc_xer_regnum) | |
209 | ppc_supply_reg (regcache, tdep->ppc_xer_regnum, | |
210 | gregs, offsets->cr_offset); | |
211 | if (regnum == -1 || regnum == tdep->ppc_mq_regnum) | |
212 | ppc_supply_reg (regcache, tdep->ppc_mq_regnum, gregs, offsets->mq_offset); | |
213 | } | |
214 | ||
215 | /* Supply register REGNUM in the floating-point register set REGSET | |
216 | from the buffer specified by FPREGS and LEN to register cache | |
217 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
218 | ||
219 | void | |
220 | ppc_supply_fpregset (const struct regset *regset, struct regcache *regcache, | |
221 | int regnum, const void *fpregs, size_t len) | |
222 | { | |
223 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
224 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
225 | const struct ppc_reg_offsets *offsets = regset->descr; | |
226 | size_t offset; | |
227 | int i; | |
228 | ||
383f0f5b JB |
229 | gdb_assert (ppc_floating_point_unit_p (gdbarch)); |
230 | ||
d195bc9f | 231 | offset = offsets->f0_offset; |
366f009f JB |
232 | for (i = tdep->ppc_fp0_regnum; |
233 | i < tdep->ppc_fp0_regnum + ppc_num_fprs; | |
234 | i++, offset += 4) | |
d195bc9f MK |
235 | { |
236 | if (regnum == -1 || regnum == i) | |
237 | ppc_supply_reg (regcache, i, fpregs, offset); | |
238 | } | |
239 | ||
240 | if (regnum == -1 || regnum == tdep->ppc_fpscr_regnum) | |
241 | ppc_supply_reg (regcache, tdep->ppc_fpscr_regnum, | |
242 | fpregs, offsets->fpscr_offset); | |
243 | } | |
244 | ||
245 | /* Collect register REGNUM in the general-purpose register set | |
246 | REGSET. from register cache REGCACHE into the buffer specified by | |
247 | GREGS and LEN. If REGNUM is -1, do this for all registers in | |
248 | REGSET. */ | |
249 | ||
250 | void | |
251 | ppc_collect_gregset (const struct regset *regset, | |
252 | const struct regcache *regcache, | |
253 | int regnum, void *gregs, size_t len) | |
254 | { | |
255 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
256 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
257 | const struct ppc_reg_offsets *offsets = regset->descr; | |
258 | size_t offset; | |
259 | int i; | |
260 | ||
261 | offset = offsets->r0_offset; | |
26c0b942 | 262 | for (i = 0; i < 32; i++, offset += 4) |
d195bc9f MK |
263 | { |
264 | if (regnum == -1 || regnum == i) | |
2e56e9c1 | 265 | ppc_collect_reg (regcache, i, gregs, offset); |
d195bc9f MK |
266 | } |
267 | ||
268 | if (regnum == -1 || regnum == PC_REGNUM) | |
269 | ppc_collect_reg (regcache, PC_REGNUM, gregs, offsets->pc_offset); | |
270 | if (regnum == -1 || regnum == tdep->ppc_ps_regnum) | |
271 | ppc_collect_reg (regcache, tdep->ppc_ps_regnum, | |
272 | gregs, offsets->ps_offset); | |
273 | if (regnum == -1 || regnum == tdep->ppc_cr_regnum) | |
274 | ppc_collect_reg (regcache, tdep->ppc_cr_regnum, | |
275 | gregs, offsets->cr_offset); | |
276 | if (regnum == -1 || regnum == tdep->ppc_lr_regnum) | |
277 | ppc_collect_reg (regcache, tdep->ppc_lr_regnum, | |
278 | gregs, offsets->lr_offset); | |
279 | if (regnum == -1 || regnum == tdep->ppc_ctr_regnum) | |
280 | ppc_collect_reg (regcache, tdep->ppc_ctr_regnum, | |
281 | gregs, offsets->ctr_offset); | |
282 | if (regnum == -1 || regnum == tdep->ppc_xer_regnum) | |
283 | ppc_collect_reg (regcache, tdep->ppc_xer_regnum, | |
284 | gregs, offsets->xer_offset); | |
285 | if (regnum == -1 || regnum == tdep->ppc_mq_regnum) | |
286 | ppc_collect_reg (regcache, tdep->ppc_mq_regnum, | |
287 | gregs, offsets->mq_offset); | |
288 | } | |
289 | ||
290 | /* Collect register REGNUM in the floating-point register set | |
291 | REGSET. from register cache REGCACHE into the buffer specified by | |
292 | FPREGS and LEN. If REGNUM is -1, do this for all registers in | |
293 | REGSET. */ | |
294 | ||
295 | void | |
296 | ppc_collect_fpregset (const struct regset *regset, | |
297 | const struct regcache *regcache, | |
298 | int regnum, void *fpregs, size_t len) | |
299 | { | |
300 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
301 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
302 | const struct ppc_reg_offsets *offsets = regset->descr; | |
303 | size_t offset; | |
304 | int i; | |
305 | ||
383f0f5b JB |
306 | gdb_assert (ppc_floating_point_unit_p (gdbarch)); |
307 | ||
d195bc9f | 308 | offset = offsets->f0_offset; |
366f009f JB |
309 | for (i = tdep->ppc_fp0_regnum; |
310 | i <= tdep->ppc_fp0_regnum + ppc_num_fprs; | |
311 | i++, offset += 4) | |
d195bc9f MK |
312 | { |
313 | if (regnum == -1 || regnum == i) | |
314 | ppc_collect_reg (regcache, regnum, fpregs, offset); | |
315 | } | |
316 | ||
317 | if (regnum == -1 || regnum == tdep->ppc_fpscr_regnum) | |
318 | ppc_collect_reg (regcache, tdep->ppc_fpscr_regnum, | |
319 | fpregs, offsets->fpscr_offset); | |
320 | } | |
321 | \f | |
0a613259 | 322 | |
7a78ae4e | 323 | /* Read a LEN-byte address from debugged memory address MEMADDR. */ |
c906108c | 324 | |
7a78ae4e ND |
325 | static CORE_ADDR |
326 | read_memory_addr (CORE_ADDR memaddr, int len) | |
327 | { | |
328 | return read_memory_unsigned_integer (memaddr, len); | |
329 | } | |
c906108c | 330 | |
7a78ae4e ND |
331 | static CORE_ADDR |
332 | rs6000_skip_prologue (CORE_ADDR pc) | |
b83266a0 SS |
333 | { |
334 | struct rs6000_framedata frame; | |
077276e8 | 335 | pc = skip_prologue (pc, 0, &frame); |
b83266a0 SS |
336 | return pc; |
337 | } | |
338 | ||
339 | ||
c906108c SS |
340 | /* Fill in fi->saved_regs */ |
341 | ||
342 | struct frame_extra_info | |
343 | { | |
344 | /* Functions calling alloca() change the value of the stack | |
345 | pointer. We need to use initial stack pointer (which is saved in | |
346 | r31 by gcc) in such cases. If a compiler emits traceback table, | |
347 | then we should use the alloca register specified in traceback | |
348 | table. FIXME. */ | |
c5aa993b | 349 | CORE_ADDR initial_sp; /* initial stack pointer. */ |
c906108c SS |
350 | }; |
351 | ||
143985b7 | 352 | /* Get the ith function argument for the current function. */ |
b9362cc7 | 353 | static CORE_ADDR |
143985b7 AF |
354 | rs6000_fetch_pointer_argument (struct frame_info *frame, int argi, |
355 | struct type *type) | |
356 | { | |
357 | CORE_ADDR addr; | |
7f5f525d | 358 | get_frame_register (frame, 3 + argi, &addr); |
143985b7 AF |
359 | return addr; |
360 | } | |
361 | ||
c906108c SS |
362 | /* Calculate the destination of a branch/jump. Return -1 if not a branch. */ |
363 | ||
364 | static CORE_ADDR | |
7a78ae4e | 365 | branch_dest (int opcode, int instr, CORE_ADDR pc, CORE_ADDR safety) |
c906108c SS |
366 | { |
367 | CORE_ADDR dest; | |
368 | int immediate; | |
369 | int absolute; | |
370 | int ext_op; | |
371 | ||
372 | absolute = (int) ((instr >> 1) & 1); | |
373 | ||
c5aa993b JM |
374 | switch (opcode) |
375 | { | |
376 | case 18: | |
377 | immediate = ((instr & ~3) << 6) >> 6; /* br unconditional */ | |
378 | if (absolute) | |
379 | dest = immediate; | |
380 | else | |
381 | dest = pc + immediate; | |
382 | break; | |
383 | ||
384 | case 16: | |
385 | immediate = ((instr & ~3) << 16) >> 16; /* br conditional */ | |
386 | if (absolute) | |
387 | dest = immediate; | |
388 | else | |
389 | dest = pc + immediate; | |
390 | break; | |
391 | ||
392 | case 19: | |
393 | ext_op = (instr >> 1) & 0x3ff; | |
394 | ||
395 | if (ext_op == 16) /* br conditional register */ | |
396 | { | |
2188cbdd | 397 | dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum) & ~3; |
c5aa993b JM |
398 | |
399 | /* If we are about to return from a signal handler, dest is | |
400 | something like 0x3c90. The current frame is a signal handler | |
401 | caller frame, upon completion of the sigreturn system call | |
402 | execution will return to the saved PC in the frame. */ | |
403 | if (dest < TEXT_SEGMENT_BASE) | |
404 | { | |
405 | struct frame_info *fi; | |
406 | ||
407 | fi = get_current_frame (); | |
408 | if (fi != NULL) | |
8b36eed8 | 409 | dest = read_memory_addr (get_frame_base (fi) + SIG_FRAME_PC_OFFSET, |
21283beb | 410 | gdbarch_tdep (current_gdbarch)->wordsize); |
c5aa993b JM |
411 | } |
412 | } | |
413 | ||
414 | else if (ext_op == 528) /* br cond to count reg */ | |
415 | { | |
2188cbdd | 416 | dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_ctr_regnum) & ~3; |
c5aa993b JM |
417 | |
418 | /* If we are about to execute a system call, dest is something | |
419 | like 0x22fc or 0x3b00. Upon completion the system call | |
420 | will return to the address in the link register. */ | |
421 | if (dest < TEXT_SEGMENT_BASE) | |
2188cbdd | 422 | dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum) & ~3; |
c5aa993b JM |
423 | } |
424 | else | |
425 | return -1; | |
426 | break; | |
c906108c | 427 | |
c5aa993b JM |
428 | default: |
429 | return -1; | |
430 | } | |
c906108c SS |
431 | return (dest < TEXT_SEGMENT_BASE) ? safety : dest; |
432 | } | |
433 | ||
434 | ||
435 | /* Sequence of bytes for breakpoint instruction. */ | |
436 | ||
f4f9705a | 437 | const static unsigned char * |
7a78ae4e | 438 | rs6000_breakpoint_from_pc (CORE_ADDR *bp_addr, int *bp_size) |
c906108c | 439 | { |
aaab4dba AC |
440 | static unsigned char big_breakpoint[] = { 0x7d, 0x82, 0x10, 0x08 }; |
441 | static unsigned char little_breakpoint[] = { 0x08, 0x10, 0x82, 0x7d }; | |
c906108c | 442 | *bp_size = 4; |
d7449b42 | 443 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
444 | return big_breakpoint; |
445 | else | |
446 | return little_breakpoint; | |
447 | } | |
448 | ||
449 | ||
450 | /* AIX does not support PT_STEP. Simulate it. */ | |
451 | ||
452 | void | |
379d08a1 AC |
453 | rs6000_software_single_step (enum target_signal signal, |
454 | int insert_breakpoints_p) | |
c906108c | 455 | { |
7c40d541 KB |
456 | CORE_ADDR dummy; |
457 | int breakp_sz; | |
f4f9705a | 458 | const char *breakp = rs6000_breakpoint_from_pc (&dummy, &breakp_sz); |
c906108c SS |
459 | int ii, insn; |
460 | CORE_ADDR loc; | |
461 | CORE_ADDR breaks[2]; | |
462 | int opcode; | |
463 | ||
c5aa993b JM |
464 | if (insert_breakpoints_p) |
465 | { | |
c906108c | 466 | |
c5aa993b | 467 | loc = read_pc (); |
c906108c | 468 | |
c5aa993b | 469 | insn = read_memory_integer (loc, 4); |
c906108c | 470 | |
7c40d541 | 471 | breaks[0] = loc + breakp_sz; |
c5aa993b JM |
472 | opcode = insn >> 26; |
473 | breaks[1] = branch_dest (opcode, insn, loc, breaks[0]); | |
c906108c | 474 | |
c5aa993b JM |
475 | /* Don't put two breakpoints on the same address. */ |
476 | if (breaks[1] == breaks[0]) | |
477 | breaks[1] = -1; | |
c906108c | 478 | |
c5aa993b | 479 | stepBreaks[1].address = 0; |
c906108c | 480 | |
c5aa993b JM |
481 | for (ii = 0; ii < 2; ++ii) |
482 | { | |
c906108c | 483 | |
c5aa993b JM |
484 | /* ignore invalid breakpoint. */ |
485 | if (breaks[ii] == -1) | |
486 | continue; | |
7c40d541 | 487 | target_insert_breakpoint (breaks[ii], stepBreaks[ii].data); |
c5aa993b JM |
488 | stepBreaks[ii].address = breaks[ii]; |
489 | } | |
c906108c | 490 | |
c5aa993b JM |
491 | } |
492 | else | |
493 | { | |
c906108c | 494 | |
c5aa993b JM |
495 | /* remove step breakpoints. */ |
496 | for (ii = 0; ii < 2; ++ii) | |
497 | if (stepBreaks[ii].address != 0) | |
7c40d541 KB |
498 | target_remove_breakpoint (stepBreaks[ii].address, |
499 | stepBreaks[ii].data); | |
c5aa993b | 500 | } |
c906108c | 501 | errno = 0; /* FIXME, don't ignore errors! */ |
c5aa993b | 502 | /* What errors? {read,write}_memory call error(). */ |
c906108c SS |
503 | } |
504 | ||
505 | ||
506 | /* return pc value after skipping a function prologue and also return | |
507 | information about a function frame. | |
508 | ||
509 | in struct rs6000_framedata fdata: | |
c5aa993b JM |
510 | - frameless is TRUE, if function does not have a frame. |
511 | - nosavedpc is TRUE, if function does not save %pc value in its frame. | |
512 | - offset is the initial size of this stack frame --- the amount by | |
513 | which we decrement the sp to allocate the frame. | |
514 | - saved_gpr is the number of the first saved gpr. | |
515 | - saved_fpr is the number of the first saved fpr. | |
6be8bc0c | 516 | - saved_vr is the number of the first saved vr. |
96ff0de4 | 517 | - saved_ev is the number of the first saved ev. |
c5aa993b JM |
518 | - alloca_reg is the number of the register used for alloca() handling. |
519 | Otherwise -1. | |
520 | - gpr_offset is the offset of the first saved gpr from the previous frame. | |
521 | - fpr_offset is the offset of the first saved fpr from the previous frame. | |
6be8bc0c | 522 | - vr_offset is the offset of the first saved vr from the previous frame. |
96ff0de4 | 523 | - ev_offset is the offset of the first saved ev from the previous frame. |
c5aa993b JM |
524 | - lr_offset is the offset of the saved lr |
525 | - cr_offset is the offset of the saved cr | |
6be8bc0c | 526 | - vrsave_offset is the offset of the saved vrsave register |
c5aa993b | 527 | */ |
c906108c SS |
528 | |
529 | #define SIGNED_SHORT(x) \ | |
530 | ((sizeof (short) == 2) \ | |
531 | ? ((int)(short)(x)) \ | |
532 | : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000))) | |
533 | ||
534 | #define GET_SRC_REG(x) (((x) >> 21) & 0x1f) | |
535 | ||
55d05f3b KB |
536 | /* Limit the number of skipped non-prologue instructions, as the examining |
537 | of the prologue is expensive. */ | |
538 | static int max_skip_non_prologue_insns = 10; | |
539 | ||
540 | /* Given PC representing the starting address of a function, and | |
541 | LIM_PC which is the (sloppy) limit to which to scan when looking | |
542 | for a prologue, attempt to further refine this limit by using | |
543 | the line data in the symbol table. If successful, a better guess | |
544 | on where the prologue ends is returned, otherwise the previous | |
545 | value of lim_pc is returned. */ | |
634aa483 AC |
546 | |
547 | /* FIXME: cagney/2004-02-14: This function and logic have largely been | |
548 | superseded by skip_prologue_using_sal. */ | |
549 | ||
55d05f3b KB |
550 | static CORE_ADDR |
551 | refine_prologue_limit (CORE_ADDR pc, CORE_ADDR lim_pc) | |
552 | { | |
553 | struct symtab_and_line prologue_sal; | |
554 | ||
555 | prologue_sal = find_pc_line (pc, 0); | |
556 | if (prologue_sal.line != 0) | |
557 | { | |
558 | int i; | |
559 | CORE_ADDR addr = prologue_sal.end; | |
560 | ||
561 | /* Handle the case in which compiler's optimizer/scheduler | |
562 | has moved instructions into the prologue. We scan ahead | |
563 | in the function looking for address ranges whose corresponding | |
564 | line number is less than or equal to the first one that we | |
565 | found for the function. (It can be less than when the | |
566 | scheduler puts a body instruction before the first prologue | |
567 | instruction.) */ | |
568 | for (i = 2 * max_skip_non_prologue_insns; | |
569 | i > 0 && (lim_pc == 0 || addr < lim_pc); | |
570 | i--) | |
571 | { | |
572 | struct symtab_and_line sal; | |
573 | ||
574 | sal = find_pc_line (addr, 0); | |
575 | if (sal.line == 0) | |
576 | break; | |
577 | if (sal.line <= prologue_sal.line | |
578 | && sal.symtab == prologue_sal.symtab) | |
579 | { | |
580 | prologue_sal = sal; | |
581 | } | |
582 | addr = sal.end; | |
583 | } | |
584 | ||
585 | if (lim_pc == 0 || prologue_sal.end < lim_pc) | |
586 | lim_pc = prologue_sal.end; | |
587 | } | |
588 | return lim_pc; | |
589 | } | |
590 | ||
591 | ||
7a78ae4e | 592 | static CORE_ADDR |
077276e8 | 593 | skip_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct rs6000_framedata *fdata) |
c906108c SS |
594 | { |
595 | CORE_ADDR orig_pc = pc; | |
55d05f3b | 596 | CORE_ADDR last_prologue_pc = pc; |
6be8bc0c | 597 | CORE_ADDR li_found_pc = 0; |
c906108c SS |
598 | char buf[4]; |
599 | unsigned long op; | |
600 | long offset = 0; | |
6be8bc0c | 601 | long vr_saved_offset = 0; |
482ca3f5 KB |
602 | int lr_reg = -1; |
603 | int cr_reg = -1; | |
6be8bc0c | 604 | int vr_reg = -1; |
96ff0de4 EZ |
605 | int ev_reg = -1; |
606 | long ev_offset = 0; | |
6be8bc0c | 607 | int vrsave_reg = -1; |
c906108c SS |
608 | int reg; |
609 | int framep = 0; | |
610 | int minimal_toc_loaded = 0; | |
ddb20c56 | 611 | int prev_insn_was_prologue_insn = 1; |
55d05f3b | 612 | int num_skip_non_prologue_insns = 0; |
96ff0de4 | 613 | const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (current_gdbarch); |
6f99cb26 | 614 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
96ff0de4 | 615 | |
55d05f3b KB |
616 | /* Attempt to find the end of the prologue when no limit is specified. |
617 | Note that refine_prologue_limit() has been written so that it may | |
618 | be used to "refine" the limits of non-zero PC values too, but this | |
619 | is only safe if we 1) trust the line information provided by the | |
620 | compiler and 2) iterate enough to actually find the end of the | |
621 | prologue. | |
622 | ||
623 | It may become a good idea at some point (for both performance and | |
624 | accuracy) to unconditionally call refine_prologue_limit(). But, | |
625 | until we can make a clear determination that this is beneficial, | |
626 | we'll play it safe and only use it to obtain a limit when none | |
627 | has been specified. */ | |
628 | if (lim_pc == 0) | |
629 | lim_pc = refine_prologue_limit (pc, lim_pc); | |
c906108c | 630 | |
ddb20c56 | 631 | memset (fdata, 0, sizeof (struct rs6000_framedata)); |
c906108c SS |
632 | fdata->saved_gpr = -1; |
633 | fdata->saved_fpr = -1; | |
6be8bc0c | 634 | fdata->saved_vr = -1; |
96ff0de4 | 635 | fdata->saved_ev = -1; |
c906108c SS |
636 | fdata->alloca_reg = -1; |
637 | fdata->frameless = 1; | |
638 | fdata->nosavedpc = 1; | |
639 | ||
55d05f3b | 640 | for (;; pc += 4) |
c906108c | 641 | { |
ddb20c56 KB |
642 | /* Sometimes it isn't clear if an instruction is a prologue |
643 | instruction or not. When we encounter one of these ambiguous | |
644 | cases, we'll set prev_insn_was_prologue_insn to 0 (false). | |
645 | Otherwise, we'll assume that it really is a prologue instruction. */ | |
646 | if (prev_insn_was_prologue_insn) | |
647 | last_prologue_pc = pc; | |
55d05f3b KB |
648 | |
649 | /* Stop scanning if we've hit the limit. */ | |
650 | if (lim_pc != 0 && pc >= lim_pc) | |
651 | break; | |
652 | ||
ddb20c56 KB |
653 | prev_insn_was_prologue_insn = 1; |
654 | ||
55d05f3b | 655 | /* Fetch the instruction and convert it to an integer. */ |
ddb20c56 KB |
656 | if (target_read_memory (pc, buf, 4)) |
657 | break; | |
658 | op = extract_signed_integer (buf, 4); | |
c906108c | 659 | |
c5aa993b JM |
660 | if ((op & 0xfc1fffff) == 0x7c0802a6) |
661 | { /* mflr Rx */ | |
43b1ab88 AC |
662 | /* Since shared library / PIC code, which needs to get its |
663 | address at runtime, can appear to save more than one link | |
664 | register vis: | |
665 | ||
666 | *INDENT-OFF* | |
667 | stwu r1,-304(r1) | |
668 | mflr r3 | |
669 | bl 0xff570d0 (blrl) | |
670 | stw r30,296(r1) | |
671 | mflr r30 | |
672 | stw r31,300(r1) | |
673 | stw r3,308(r1); | |
674 | ... | |
675 | *INDENT-ON* | |
676 | ||
677 | remember just the first one, but skip over additional | |
678 | ones. */ | |
679 | if (lr_reg < 0) | |
680 | lr_reg = (op & 0x03e00000); | |
c5aa993b | 681 | continue; |
c5aa993b JM |
682 | } |
683 | else if ((op & 0xfc1fffff) == 0x7c000026) | |
684 | { /* mfcr Rx */ | |
98f08d3d | 685 | cr_reg = (op & 0x03e00000); |
c5aa993b | 686 | continue; |
c906108c | 687 | |
c906108c | 688 | } |
c5aa993b JM |
689 | else if ((op & 0xfc1f0000) == 0xd8010000) |
690 | { /* stfd Rx,NUM(r1) */ | |
691 | reg = GET_SRC_REG (op); | |
692 | if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg) | |
693 | { | |
694 | fdata->saved_fpr = reg; | |
695 | fdata->fpr_offset = SIGNED_SHORT (op) + offset; | |
696 | } | |
697 | continue; | |
c906108c | 698 | |
c5aa993b JM |
699 | } |
700 | else if (((op & 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */ | |
7a78ae4e ND |
701 | (((op & 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */ |
702 | (op & 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */ | |
703 | (op & 0x03e00000) >= 0x01a00000)) /* rx >= r13 */ | |
c5aa993b JM |
704 | { |
705 | ||
706 | reg = GET_SRC_REG (op); | |
707 | if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg) | |
708 | { | |
709 | fdata->saved_gpr = reg; | |
7a78ae4e | 710 | if ((op & 0xfc1f0003) == 0xf8010000) |
98f08d3d | 711 | op &= ~3UL; |
c5aa993b JM |
712 | fdata->gpr_offset = SIGNED_SHORT (op) + offset; |
713 | } | |
714 | continue; | |
c906108c | 715 | |
ddb20c56 KB |
716 | } |
717 | else if ((op & 0xffff0000) == 0x60000000) | |
718 | { | |
96ff0de4 | 719 | /* nop */ |
ddb20c56 KB |
720 | /* Allow nops in the prologue, but do not consider them to |
721 | be part of the prologue unless followed by other prologue | |
722 | instructions. */ | |
723 | prev_insn_was_prologue_insn = 0; | |
724 | continue; | |
725 | ||
c906108c | 726 | } |
c5aa993b JM |
727 | else if ((op & 0xffff0000) == 0x3c000000) |
728 | { /* addis 0,0,NUM, used | |
729 | for >= 32k frames */ | |
730 | fdata->offset = (op & 0x0000ffff) << 16; | |
731 | fdata->frameless = 0; | |
732 | continue; | |
733 | ||
734 | } | |
735 | else if ((op & 0xffff0000) == 0x60000000) | |
736 | { /* ori 0,0,NUM, 2nd ha | |
737 | lf of >= 32k frames */ | |
738 | fdata->offset |= (op & 0x0000ffff); | |
739 | fdata->frameless = 0; | |
740 | continue; | |
741 | ||
742 | } | |
98f08d3d KB |
743 | else if (lr_reg != -1 && |
744 | /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */ | |
745 | (((op & 0xffff0000) == (lr_reg | 0xf8010000)) || | |
746 | /* stw Rx, NUM(r1) */ | |
747 | ((op & 0xffff0000) == (lr_reg | 0x90010000)) || | |
748 | /* stwu Rx, NUM(r1) */ | |
749 | ((op & 0xffff0000) == (lr_reg | 0x94010000)))) | |
750 | { /* where Rx == lr */ | |
751 | fdata->lr_offset = offset; | |
c5aa993b JM |
752 | fdata->nosavedpc = 0; |
753 | lr_reg = 0; | |
98f08d3d KB |
754 | if ((op & 0xfc000003) == 0xf8000000 || /* std */ |
755 | (op & 0xfc000000) == 0x90000000) /* stw */ | |
756 | { | |
757 | /* Does not update r1, so add displacement to lr_offset. */ | |
758 | fdata->lr_offset += SIGNED_SHORT (op); | |
759 | } | |
c5aa993b JM |
760 | continue; |
761 | ||
762 | } | |
98f08d3d KB |
763 | else if (cr_reg != -1 && |
764 | /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */ | |
765 | (((op & 0xffff0000) == (cr_reg | 0xf8010000)) || | |
766 | /* stw Rx, NUM(r1) */ | |
767 | ((op & 0xffff0000) == (cr_reg | 0x90010000)) || | |
768 | /* stwu Rx, NUM(r1) */ | |
769 | ((op & 0xffff0000) == (cr_reg | 0x94010000)))) | |
770 | { /* where Rx == cr */ | |
771 | fdata->cr_offset = offset; | |
c5aa993b | 772 | cr_reg = 0; |
98f08d3d KB |
773 | if ((op & 0xfc000003) == 0xf8000000 || |
774 | (op & 0xfc000000) == 0x90000000) | |
775 | { | |
776 | /* Does not update r1, so add displacement to cr_offset. */ | |
777 | fdata->cr_offset += SIGNED_SHORT (op); | |
778 | } | |
c5aa993b JM |
779 | continue; |
780 | ||
781 | } | |
782 | else if (op == 0x48000005) | |
783 | { /* bl .+4 used in | |
784 | -mrelocatable */ | |
785 | continue; | |
786 | ||
787 | } | |
788 | else if (op == 0x48000004) | |
789 | { /* b .+4 (xlc) */ | |
790 | break; | |
791 | ||
c5aa993b | 792 | } |
6be8bc0c EZ |
793 | else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used |
794 | in V.4 -mminimal-toc */ | |
c5aa993b JM |
795 | (op & 0xffff0000) == 0x3bde0000) |
796 | { /* addi 30,30,foo@l */ | |
797 | continue; | |
c906108c | 798 | |
c5aa993b JM |
799 | } |
800 | else if ((op & 0xfc000001) == 0x48000001) | |
801 | { /* bl foo, | |
802 | to save fprs??? */ | |
c906108c | 803 | |
c5aa993b | 804 | fdata->frameless = 0; |
6be8bc0c EZ |
805 | /* Don't skip over the subroutine call if it is not within |
806 | the first three instructions of the prologue. */ | |
c5aa993b JM |
807 | if ((pc - orig_pc) > 8) |
808 | break; | |
809 | ||
810 | op = read_memory_integer (pc + 4, 4); | |
811 | ||
6be8bc0c EZ |
812 | /* At this point, make sure this is not a trampoline |
813 | function (a function that simply calls another functions, | |
814 | and nothing else). If the next is not a nop, this branch | |
815 | was part of the function prologue. */ | |
c5aa993b JM |
816 | |
817 | if (op == 0x4def7b82 || op == 0) /* crorc 15, 15, 15 */ | |
818 | break; /* don't skip over | |
819 | this branch */ | |
820 | continue; | |
821 | ||
c5aa993b | 822 | } |
98f08d3d KB |
823 | /* update stack pointer */ |
824 | else if ((op & 0xfc1f0000) == 0x94010000) | |
825 | { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */ | |
c5aa993b JM |
826 | fdata->frameless = 0; |
827 | fdata->offset = SIGNED_SHORT (op); | |
828 | offset = fdata->offset; | |
829 | continue; | |
c5aa993b | 830 | } |
98f08d3d KB |
831 | else if ((op & 0xfc1f016a) == 0x7c01016e) |
832 | { /* stwux rX,r1,rY */ | |
833 | /* no way to figure out what r1 is going to be */ | |
834 | fdata->frameless = 0; | |
835 | offset = fdata->offset; | |
836 | continue; | |
837 | } | |
838 | else if ((op & 0xfc1f0003) == 0xf8010001) | |
839 | { /* stdu rX,NUM(r1) */ | |
840 | fdata->frameless = 0; | |
841 | fdata->offset = SIGNED_SHORT (op & ~3UL); | |
842 | offset = fdata->offset; | |
843 | continue; | |
844 | } | |
845 | else if ((op & 0xfc1f016a) == 0x7c01016a) | |
846 | { /* stdux rX,r1,rY */ | |
847 | /* no way to figure out what r1 is going to be */ | |
c5aa993b JM |
848 | fdata->frameless = 0; |
849 | offset = fdata->offset; | |
850 | continue; | |
c5aa993b | 851 | } |
98f08d3d KB |
852 | /* Load up minimal toc pointer */ |
853 | else if (((op >> 22) == 0x20f || /* l r31,... or l r30,... */ | |
854 | (op >> 22) == 0x3af) /* ld r31,... or ld r30,... */ | |
c5aa993b | 855 | && !minimal_toc_loaded) |
98f08d3d | 856 | { |
c5aa993b JM |
857 | minimal_toc_loaded = 1; |
858 | continue; | |
859 | ||
f6077098 KB |
860 | /* move parameters from argument registers to local variable |
861 | registers */ | |
862 | } | |
863 | else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */ | |
864 | (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */ | |
865 | (((op >> 21) & 31) <= 10) && | |
96ff0de4 | 866 | ((long) ((op >> 16) & 31) >= fdata->saved_gpr)) /* Rx: local var reg */ |
f6077098 KB |
867 | { |
868 | continue; | |
869 | ||
c5aa993b JM |
870 | /* store parameters in stack */ |
871 | } | |
e802b915 JB |
872 | /* Move parameters from argument registers to temporary register. */ |
873 | else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */ | |
874 | (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */ | |
875 | (((op >> 21) & 31) <= 10) && | |
876 | (((op >> 16) & 31) == 0)) /* Rx: scratch register r0 */ | |
877 | { | |
878 | continue; | |
879 | } | |
6be8bc0c | 880 | else if ((op & 0xfc1f0003) == 0xf8010000 || /* std rx,NUM(r1) */ |
c5aa993b | 881 | (op & 0xfc1f0000) == 0xd8010000 || /* stfd Rx,NUM(r1) */ |
7a78ae4e ND |
882 | (op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */ |
883 | { | |
c5aa993b | 884 | continue; |
c906108c | 885 | |
c5aa993b JM |
886 | /* store parameters in stack via frame pointer */ |
887 | } | |
888 | else if (framep && | |
e802b915 JB |
889 | ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */ |
890 | (op & 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */ | |
891 | (op & 0xfc1f0000) == 0xd81f0000 || /* stfd Rx,NUM(r31) */ | |
892 | (op & 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */ | |
893 | { | |
c5aa993b JM |
894 | continue; |
895 | ||
896 | /* Set up frame pointer */ | |
897 | } | |
898 | else if (op == 0x603f0000 /* oril r31, r1, 0x0 */ | |
899 | || op == 0x7c3f0b78) | |
900 | { /* mr r31, r1 */ | |
901 | fdata->frameless = 0; | |
902 | framep = 1; | |
6f99cb26 | 903 | fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31); |
c5aa993b JM |
904 | continue; |
905 | ||
906 | /* Another way to set up the frame pointer. */ | |
907 | } | |
908 | else if ((op & 0xfc1fffff) == 0x38010000) | |
909 | { /* addi rX, r1, 0x0 */ | |
910 | fdata->frameless = 0; | |
911 | framep = 1; | |
6f99cb26 AC |
912 | fdata->alloca_reg = (tdep->ppc_gp0_regnum |
913 | + ((op & ~0x38010000) >> 21)); | |
c5aa993b | 914 | continue; |
c5aa993b | 915 | } |
6be8bc0c EZ |
916 | /* AltiVec related instructions. */ |
917 | /* Store the vrsave register (spr 256) in another register for | |
918 | later manipulation, or load a register into the vrsave | |
919 | register. 2 instructions are used: mfvrsave and | |
920 | mtvrsave. They are shorthand notation for mfspr Rn, SPR256 | |
921 | and mtspr SPR256, Rn. */ | |
922 | /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110 | |
923 | mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */ | |
924 | else if ((op & 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */ | |
925 | { | |
926 | vrsave_reg = GET_SRC_REG (op); | |
927 | continue; | |
928 | } | |
929 | else if ((op & 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */ | |
930 | { | |
931 | continue; | |
932 | } | |
933 | /* Store the register where vrsave was saved to onto the stack: | |
934 | rS is the register where vrsave was stored in a previous | |
935 | instruction. */ | |
936 | /* 100100 sssss 00001 dddddddd dddddddd */ | |
937 | else if ((op & 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */ | |
938 | { | |
939 | if (vrsave_reg == GET_SRC_REG (op)) | |
940 | { | |
941 | fdata->vrsave_offset = SIGNED_SHORT (op) + offset; | |
942 | vrsave_reg = -1; | |
943 | } | |
944 | continue; | |
945 | } | |
946 | /* Compute the new value of vrsave, by modifying the register | |
947 | where vrsave was saved to. */ | |
948 | else if (((op & 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */ | |
949 | || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */ | |
950 | { | |
951 | continue; | |
952 | } | |
953 | /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first | |
954 | in a pair of insns to save the vector registers on the | |
955 | stack. */ | |
956 | /* 001110 00000 00000 iiii iiii iiii iiii */ | |
96ff0de4 EZ |
957 | /* 001110 01110 00000 iiii iiii iiii iiii */ |
958 | else if ((op & 0xffff0000) == 0x38000000 /* li r0, SIMM */ | |
959 | || (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */ | |
6be8bc0c EZ |
960 | { |
961 | li_found_pc = pc; | |
962 | vr_saved_offset = SIGNED_SHORT (op); | |
963 | } | |
964 | /* Store vector register S at (r31+r0) aligned to 16 bytes. */ | |
965 | /* 011111 sssss 11111 00000 00111001110 */ | |
966 | else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */ | |
967 | { | |
968 | if (pc == (li_found_pc + 4)) | |
969 | { | |
970 | vr_reg = GET_SRC_REG (op); | |
971 | /* If this is the first vector reg to be saved, or if | |
972 | it has a lower number than others previously seen, | |
973 | reupdate the frame info. */ | |
974 | if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg) | |
975 | { | |
976 | fdata->saved_vr = vr_reg; | |
977 | fdata->vr_offset = vr_saved_offset + offset; | |
978 | } | |
979 | vr_saved_offset = -1; | |
980 | vr_reg = -1; | |
981 | li_found_pc = 0; | |
982 | } | |
983 | } | |
984 | /* End AltiVec related instructions. */ | |
96ff0de4 EZ |
985 | |
986 | /* Start BookE related instructions. */ | |
987 | /* Store gen register S at (r31+uimm). | |
988 | Any register less than r13 is volatile, so we don't care. */ | |
989 | /* 000100 sssss 11111 iiiii 01100100001 */ | |
990 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
991 | && (op & 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */ | |
992 | { | |
993 | if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */ | |
994 | { | |
995 | unsigned int imm; | |
996 | ev_reg = GET_SRC_REG (op); | |
997 | imm = (op >> 11) & 0x1f; | |
998 | ev_offset = imm * 8; | |
999 | /* If this is the first vector reg to be saved, or if | |
1000 | it has a lower number than others previously seen, | |
1001 | reupdate the frame info. */ | |
1002 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) | |
1003 | { | |
1004 | fdata->saved_ev = ev_reg; | |
1005 | fdata->ev_offset = ev_offset + offset; | |
1006 | } | |
1007 | } | |
1008 | continue; | |
1009 | } | |
1010 | /* Store gen register rS at (r1+rB). */ | |
1011 | /* 000100 sssss 00001 bbbbb 01100100000 */ | |
1012 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
1013 | && (op & 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */ | |
1014 | { | |
1015 | if (pc == (li_found_pc + 4)) | |
1016 | { | |
1017 | ev_reg = GET_SRC_REG (op); | |
1018 | /* If this is the first vector reg to be saved, or if | |
1019 | it has a lower number than others previously seen, | |
1020 | reupdate the frame info. */ | |
1021 | /* We know the contents of rB from the previous instruction. */ | |
1022 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) | |
1023 | { | |
1024 | fdata->saved_ev = ev_reg; | |
1025 | fdata->ev_offset = vr_saved_offset + offset; | |
1026 | } | |
1027 | vr_saved_offset = -1; | |
1028 | ev_reg = -1; | |
1029 | li_found_pc = 0; | |
1030 | } | |
1031 | continue; | |
1032 | } | |
1033 | /* Store gen register r31 at (rA+uimm). */ | |
1034 | /* 000100 11111 aaaaa iiiii 01100100001 */ | |
1035 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
1036 | && (op & 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */ | |
1037 | { | |
1038 | /* Wwe know that the source register is 31 already, but | |
1039 | it can't hurt to compute it. */ | |
1040 | ev_reg = GET_SRC_REG (op); | |
1041 | ev_offset = ((op >> 11) & 0x1f) * 8; | |
1042 | /* If this is the first vector reg to be saved, or if | |
1043 | it has a lower number than others previously seen, | |
1044 | reupdate the frame info. */ | |
1045 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) | |
1046 | { | |
1047 | fdata->saved_ev = ev_reg; | |
1048 | fdata->ev_offset = ev_offset + offset; | |
1049 | } | |
1050 | ||
1051 | continue; | |
1052 | } | |
1053 | /* Store gen register S at (r31+r0). | |
1054 | Store param on stack when offset from SP bigger than 4 bytes. */ | |
1055 | /* 000100 sssss 11111 00000 01100100000 */ | |
1056 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
1057 | && (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */ | |
1058 | { | |
1059 | if (pc == (li_found_pc + 4)) | |
1060 | { | |
1061 | if ((op & 0x03e00000) >= 0x01a00000) | |
1062 | { | |
1063 | ev_reg = GET_SRC_REG (op); | |
1064 | /* If this is the first vector reg to be saved, or if | |
1065 | it has a lower number than others previously seen, | |
1066 | reupdate the frame info. */ | |
1067 | /* We know the contents of r0 from the previous | |
1068 | instruction. */ | |
1069 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) | |
1070 | { | |
1071 | fdata->saved_ev = ev_reg; | |
1072 | fdata->ev_offset = vr_saved_offset + offset; | |
1073 | } | |
1074 | ev_reg = -1; | |
1075 | } | |
1076 | vr_saved_offset = -1; | |
1077 | li_found_pc = 0; | |
1078 | continue; | |
1079 | } | |
1080 | } | |
1081 | /* End BookE related instructions. */ | |
1082 | ||
c5aa993b JM |
1083 | else |
1084 | { | |
55d05f3b KB |
1085 | /* Not a recognized prologue instruction. |
1086 | Handle optimizer code motions into the prologue by continuing | |
1087 | the search if we have no valid frame yet or if the return | |
1088 | address is not yet saved in the frame. */ | |
1089 | if (fdata->frameless == 0 | |
1090 | && (lr_reg == -1 || fdata->nosavedpc == 0)) | |
1091 | break; | |
1092 | ||
1093 | if (op == 0x4e800020 /* blr */ | |
1094 | || op == 0x4e800420) /* bctr */ | |
1095 | /* Do not scan past epilogue in frameless functions or | |
1096 | trampolines. */ | |
1097 | break; | |
1098 | if ((op & 0xf4000000) == 0x40000000) /* bxx */ | |
64366f1c | 1099 | /* Never skip branches. */ |
55d05f3b KB |
1100 | break; |
1101 | ||
1102 | if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns) | |
1103 | /* Do not scan too many insns, scanning insns is expensive with | |
1104 | remote targets. */ | |
1105 | break; | |
1106 | ||
1107 | /* Continue scanning. */ | |
1108 | prev_insn_was_prologue_insn = 0; | |
1109 | continue; | |
c5aa993b | 1110 | } |
c906108c SS |
1111 | } |
1112 | ||
1113 | #if 0 | |
1114 | /* I have problems with skipping over __main() that I need to address | |
1115 | * sometime. Previously, I used to use misc_function_vector which | |
1116 | * didn't work as well as I wanted to be. -MGO */ | |
1117 | ||
1118 | /* If the first thing after skipping a prolog is a branch to a function, | |
1119 | this might be a call to an initializer in main(), introduced by gcc2. | |
64366f1c | 1120 | We'd like to skip over it as well. Fortunately, xlc does some extra |
c906108c | 1121 | work before calling a function right after a prologue, thus we can |
64366f1c | 1122 | single out such gcc2 behaviour. */ |
c906108c | 1123 | |
c906108c | 1124 | |
c5aa993b JM |
1125 | if ((op & 0xfc000001) == 0x48000001) |
1126 | { /* bl foo, an initializer function? */ | |
1127 | op = read_memory_integer (pc + 4, 4); | |
1128 | ||
1129 | if (op == 0x4def7b82) | |
1130 | { /* cror 0xf, 0xf, 0xf (nop) */ | |
c906108c | 1131 | |
64366f1c EZ |
1132 | /* Check and see if we are in main. If so, skip over this |
1133 | initializer function as well. */ | |
c906108c | 1134 | |
c5aa993b | 1135 | tmp = find_pc_misc_function (pc); |
6314a349 AC |
1136 | if (tmp >= 0 |
1137 | && strcmp (misc_function_vector[tmp].name, main_name ()) == 0) | |
c5aa993b JM |
1138 | return pc + 8; |
1139 | } | |
c906108c | 1140 | } |
c906108c | 1141 | #endif /* 0 */ |
c5aa993b JM |
1142 | |
1143 | fdata->offset = -fdata->offset; | |
ddb20c56 | 1144 | return last_prologue_pc; |
c906108c SS |
1145 | } |
1146 | ||
1147 | ||
1148 | /************************************************************************* | |
f6077098 | 1149 | Support for creating pushing a dummy frame into the stack, and popping |
c906108c SS |
1150 | frames, etc. |
1151 | *************************************************************************/ | |
1152 | ||
c906108c | 1153 | |
11269d7e AC |
1154 | /* All the ABI's require 16 byte alignment. */ |
1155 | static CORE_ADDR | |
1156 | rs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
1157 | { | |
1158 | return (addr & -16); | |
1159 | } | |
1160 | ||
7a78ae4e | 1161 | /* Pass the arguments in either registers, or in the stack. In RS/6000, |
c906108c SS |
1162 | the first eight words of the argument list (that might be less than |
1163 | eight parameters if some parameters occupy more than one word) are | |
7a78ae4e | 1164 | passed in r3..r10 registers. float and double parameters are |
64366f1c EZ |
1165 | passed in fpr's, in addition to that. Rest of the parameters if any |
1166 | are passed in user stack. There might be cases in which half of the | |
c906108c SS |
1167 | parameter is copied into registers, the other half is pushed into |
1168 | stack. | |
1169 | ||
7a78ae4e ND |
1170 | Stack must be aligned on 64-bit boundaries when synthesizing |
1171 | function calls. | |
1172 | ||
c906108c SS |
1173 | If the function is returning a structure, then the return address is passed |
1174 | in r3, then the first 7 words of the parameters can be passed in registers, | |
64366f1c | 1175 | starting from r4. */ |
c906108c | 1176 | |
7a78ae4e | 1177 | static CORE_ADDR |
77b2b6d4 AC |
1178 | rs6000_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
1179 | struct regcache *regcache, CORE_ADDR bp_addr, | |
1180 | int nargs, struct value **args, CORE_ADDR sp, | |
1181 | int struct_return, CORE_ADDR struct_addr) | |
c906108c | 1182 | { |
7a41266b | 1183 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c SS |
1184 | int ii; |
1185 | int len = 0; | |
c5aa993b JM |
1186 | int argno; /* current argument number */ |
1187 | int argbytes; /* current argument byte */ | |
1188 | char tmp_buffer[50]; | |
1189 | int f_argno = 0; /* current floating point argno */ | |
21283beb | 1190 | int wordsize = gdbarch_tdep (current_gdbarch)->wordsize; |
c906108c | 1191 | |
ea7c478f | 1192 | struct value *arg = 0; |
c906108c SS |
1193 | struct type *type; |
1194 | ||
1195 | CORE_ADDR saved_sp; | |
1196 | ||
383f0f5b JB |
1197 | /* The calling convention this function implements assumes the |
1198 | processor has floating-point registers. We shouldn't be using it | |
1199 | on PPC variants that lack them. */ | |
1200 | gdb_assert (ppc_floating_point_unit_p (current_gdbarch)); | |
1201 | ||
64366f1c | 1202 | /* The first eight words of ther arguments are passed in registers. |
7a41266b AC |
1203 | Copy them appropriately. */ |
1204 | ii = 0; | |
1205 | ||
1206 | /* If the function is returning a `struct', then the first word | |
1207 | (which will be passed in r3) is used for struct return address. | |
1208 | In that case we should advance one word and start from r4 | |
1209 | register to copy parameters. */ | |
1210 | if (struct_return) | |
1211 | { | |
1212 | regcache_raw_write_unsigned (regcache, tdep->ppc_gp0_regnum + 3, | |
1213 | struct_addr); | |
1214 | ii++; | |
1215 | } | |
c906108c SS |
1216 | |
1217 | /* | |
c5aa993b JM |
1218 | effectively indirect call... gcc does... |
1219 | ||
1220 | return_val example( float, int); | |
1221 | ||
1222 | eabi: | |
1223 | float in fp0, int in r3 | |
1224 | offset of stack on overflow 8/16 | |
1225 | for varargs, must go by type. | |
1226 | power open: | |
1227 | float in r3&r4, int in r5 | |
1228 | offset of stack on overflow different | |
1229 | both: | |
1230 | return in r3 or f0. If no float, must study how gcc emulates floats; | |
1231 | pay attention to arg promotion. | |
1232 | User may have to cast\args to handle promotion correctly | |
1233 | since gdb won't know if prototype supplied or not. | |
1234 | */ | |
c906108c | 1235 | |
c5aa993b JM |
1236 | for (argno = 0, argbytes = 0; argno < nargs && ii < 8; ++ii) |
1237 | { | |
12c266ea | 1238 | int reg_size = DEPRECATED_REGISTER_RAW_SIZE (ii + 3); |
c5aa993b JM |
1239 | |
1240 | arg = args[argno]; | |
1241 | type = check_typedef (VALUE_TYPE (arg)); | |
1242 | len = TYPE_LENGTH (type); | |
1243 | ||
1244 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
1245 | { | |
1246 | ||
64366f1c | 1247 | /* Floating point arguments are passed in fpr's, as well as gpr's. |
c5aa993b | 1248 | There are 13 fpr's reserved for passing parameters. At this point |
64366f1c | 1249 | there is no way we would run out of them. */ |
c5aa993b JM |
1250 | |
1251 | if (len > 8) | |
1252 | printf_unfiltered ( | |
1253 | "Fatal Error: a floating point parameter #%d with a size > 8 is found!\n", argno); | |
1254 | ||
366f009f JB |
1255 | memcpy (&deprecated_registers[DEPRECATED_REGISTER_BYTE |
1256 | (tdep->ppc_fp0_regnum + 1 + f_argno)], | |
c5aa993b JM |
1257 | VALUE_CONTENTS (arg), |
1258 | len); | |
1259 | ++f_argno; | |
1260 | } | |
1261 | ||
f6077098 | 1262 | if (len > reg_size) |
c5aa993b JM |
1263 | { |
1264 | ||
64366f1c | 1265 | /* Argument takes more than one register. */ |
c5aa993b JM |
1266 | while (argbytes < len) |
1267 | { | |
62700349 | 1268 | memset (&deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + 3)], 0, |
524d7c18 | 1269 | reg_size); |
62700349 | 1270 | memcpy (&deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + 3)], |
c5aa993b | 1271 | ((char *) VALUE_CONTENTS (arg)) + argbytes, |
f6077098 KB |
1272 | (len - argbytes) > reg_size |
1273 | ? reg_size : len - argbytes); | |
1274 | ++ii, argbytes += reg_size; | |
c5aa993b JM |
1275 | |
1276 | if (ii >= 8) | |
1277 | goto ran_out_of_registers_for_arguments; | |
1278 | } | |
1279 | argbytes = 0; | |
1280 | --ii; | |
1281 | } | |
1282 | else | |
64366f1c EZ |
1283 | { |
1284 | /* Argument can fit in one register. No problem. */ | |
d7449b42 | 1285 | int adj = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? reg_size - len : 0; |
62700349 AC |
1286 | memset (&deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + 3)], 0, reg_size); |
1287 | memcpy ((char *)&deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + 3)] + adj, | |
f6077098 | 1288 | VALUE_CONTENTS (arg), len); |
c5aa993b JM |
1289 | } |
1290 | ++argno; | |
c906108c | 1291 | } |
c906108c SS |
1292 | |
1293 | ran_out_of_registers_for_arguments: | |
1294 | ||
7a78ae4e | 1295 | saved_sp = read_sp (); |
cc9836a8 | 1296 | |
64366f1c | 1297 | /* Location for 8 parameters are always reserved. */ |
7a78ae4e | 1298 | sp -= wordsize * 8; |
f6077098 | 1299 | |
64366f1c | 1300 | /* Another six words for back chain, TOC register, link register, etc. */ |
7a78ae4e | 1301 | sp -= wordsize * 6; |
f6077098 | 1302 | |
64366f1c | 1303 | /* Stack pointer must be quadword aligned. */ |
7a78ae4e | 1304 | sp &= -16; |
c906108c | 1305 | |
64366f1c EZ |
1306 | /* If there are more arguments, allocate space for them in |
1307 | the stack, then push them starting from the ninth one. */ | |
c906108c | 1308 | |
c5aa993b JM |
1309 | if ((argno < nargs) || argbytes) |
1310 | { | |
1311 | int space = 0, jj; | |
c906108c | 1312 | |
c5aa993b JM |
1313 | if (argbytes) |
1314 | { | |
1315 | space += ((len - argbytes + 3) & -4); | |
1316 | jj = argno + 1; | |
1317 | } | |
1318 | else | |
1319 | jj = argno; | |
c906108c | 1320 | |
c5aa993b JM |
1321 | for (; jj < nargs; ++jj) |
1322 | { | |
ea7c478f | 1323 | struct value *val = args[jj]; |
c5aa993b JM |
1324 | space += ((TYPE_LENGTH (VALUE_TYPE (val))) + 3) & -4; |
1325 | } | |
c906108c | 1326 | |
64366f1c | 1327 | /* Add location required for the rest of the parameters. */ |
f6077098 | 1328 | space = (space + 15) & -16; |
c5aa993b | 1329 | sp -= space; |
c906108c | 1330 | |
7aea86e6 AC |
1331 | /* This is another instance we need to be concerned about |
1332 | securing our stack space. If we write anything underneath %sp | |
1333 | (r1), we might conflict with the kernel who thinks he is free | |
1334 | to use this area. So, update %sp first before doing anything | |
1335 | else. */ | |
1336 | ||
1337 | regcache_raw_write_signed (regcache, SP_REGNUM, sp); | |
1338 | ||
64366f1c EZ |
1339 | /* If the last argument copied into the registers didn't fit there |
1340 | completely, push the rest of it into stack. */ | |
c906108c | 1341 | |
c5aa993b JM |
1342 | if (argbytes) |
1343 | { | |
1344 | write_memory (sp + 24 + (ii * 4), | |
1345 | ((char *) VALUE_CONTENTS (arg)) + argbytes, | |
1346 | len - argbytes); | |
1347 | ++argno; | |
1348 | ii += ((len - argbytes + 3) & -4) / 4; | |
1349 | } | |
c906108c | 1350 | |
64366f1c | 1351 | /* Push the rest of the arguments into stack. */ |
c5aa993b JM |
1352 | for (; argno < nargs; ++argno) |
1353 | { | |
c906108c | 1354 | |
c5aa993b JM |
1355 | arg = args[argno]; |
1356 | type = check_typedef (VALUE_TYPE (arg)); | |
1357 | len = TYPE_LENGTH (type); | |
c906108c SS |
1358 | |
1359 | ||
64366f1c EZ |
1360 | /* Float types should be passed in fpr's, as well as in the |
1361 | stack. */ | |
c5aa993b JM |
1362 | if (TYPE_CODE (type) == TYPE_CODE_FLT && f_argno < 13) |
1363 | { | |
c906108c | 1364 | |
c5aa993b JM |
1365 | if (len > 8) |
1366 | printf_unfiltered ( | |
1367 | "Fatal Error: a floating point parameter #%d with a size > 8 is found!\n", argno); | |
c906108c | 1368 | |
366f009f JB |
1369 | memcpy (&(deprecated_registers |
1370 | [DEPRECATED_REGISTER_BYTE | |
1371 | (tdep->ppc_fp0_regnum + 1 + f_argno)]), | |
c5aa993b JM |
1372 | VALUE_CONTENTS (arg), |
1373 | len); | |
1374 | ++f_argno; | |
1375 | } | |
c906108c | 1376 | |
c5aa993b JM |
1377 | write_memory (sp + 24 + (ii * 4), (char *) VALUE_CONTENTS (arg), len); |
1378 | ii += ((len + 3) & -4) / 4; | |
1379 | } | |
c906108c | 1380 | } |
c906108c | 1381 | |
69517000 | 1382 | /* Set the stack pointer. According to the ABI, the SP is meant to |
7aea86e6 AC |
1383 | be set _before_ the corresponding stack space is used. On AIX, |
1384 | this even applies when the target has been completely stopped! | |
1385 | Not doing this can lead to conflicts with the kernel which thinks | |
1386 | that it still has control over this not-yet-allocated stack | |
1387 | region. */ | |
33a7c2fc AC |
1388 | regcache_raw_write_signed (regcache, SP_REGNUM, sp); |
1389 | ||
7aea86e6 AC |
1390 | /* Set back chain properly. */ |
1391 | store_unsigned_integer (tmp_buffer, 4, saved_sp); | |
1392 | write_memory (sp, tmp_buffer, 4); | |
1393 | ||
e56a0ecc AC |
1394 | /* Point the inferior function call's return address at the dummy's |
1395 | breakpoint. */ | |
1396 | regcache_raw_write_signed (regcache, tdep->ppc_lr_regnum, bp_addr); | |
1397 | ||
794a477a AC |
1398 | /* Set the TOC register, get the value from the objfile reader |
1399 | which, in turn, gets it from the VMAP table. */ | |
1400 | if (rs6000_find_toc_address_hook != NULL) | |
1401 | { | |
1402 | CORE_ADDR tocvalue = (*rs6000_find_toc_address_hook) (func_addr); | |
1403 | regcache_raw_write_signed (regcache, tdep->ppc_toc_regnum, tocvalue); | |
1404 | } | |
1405 | ||
c906108c SS |
1406 | target_store_registers (-1); |
1407 | return sp; | |
1408 | } | |
c906108c | 1409 | |
b9ff3018 AC |
1410 | /* PowerOpen always puts structures in memory. Vectors, which were |
1411 | added later, do get returned in a register though. */ | |
1412 | ||
1413 | static int | |
1414 | rs6000_use_struct_convention (int gcc_p, struct type *value_type) | |
1415 | { | |
1416 | if ((TYPE_LENGTH (value_type) == 16 || TYPE_LENGTH (value_type) == 8) | |
1417 | && TYPE_VECTOR (value_type)) | |
1418 | return 0; | |
1419 | return 1; | |
1420 | } | |
1421 | ||
7a78ae4e ND |
1422 | static void |
1423 | rs6000_extract_return_value (struct type *valtype, char *regbuf, char *valbuf) | |
c906108c SS |
1424 | { |
1425 | int offset = 0; | |
ace1378a | 1426 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c | 1427 | |
383f0f5b JB |
1428 | /* The calling convention this function implements assumes the |
1429 | processor has floating-point registers. We shouldn't be using it | |
1430 | on PPC variants that lack them. */ | |
1431 | gdb_assert (ppc_floating_point_unit_p (current_gdbarch)); | |
1432 | ||
c5aa993b JM |
1433 | if (TYPE_CODE (valtype) == TYPE_CODE_FLT) |
1434 | { | |
c906108c | 1435 | |
c5aa993b JM |
1436 | /* floats and doubles are returned in fpr1. fpr's have a size of 8 bytes. |
1437 | We need to truncate the return value into float size (4 byte) if | |
64366f1c | 1438 | necessary. */ |
c906108c | 1439 | |
65951cd9 | 1440 | convert_typed_floating (®buf[DEPRECATED_REGISTER_BYTE |
366f009f | 1441 | (tdep->ppc_fp0_regnum + 1)], |
65951cd9 JG |
1442 | builtin_type_double, |
1443 | valbuf, | |
1444 | valtype); | |
c5aa993b | 1445 | } |
ace1378a EZ |
1446 | else if (TYPE_CODE (valtype) == TYPE_CODE_ARRAY |
1447 | && TYPE_LENGTH (valtype) == 16 | |
1448 | && TYPE_VECTOR (valtype)) | |
1449 | { | |
62700349 | 1450 | memcpy (valbuf, regbuf + DEPRECATED_REGISTER_BYTE (tdep->ppc_vr0_regnum + 2), |
ace1378a EZ |
1451 | TYPE_LENGTH (valtype)); |
1452 | } | |
c5aa993b JM |
1453 | else |
1454 | { | |
1455 | /* return value is copied starting from r3. */ | |
d7449b42 | 1456 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
12c266ea AC |
1457 | && TYPE_LENGTH (valtype) < DEPRECATED_REGISTER_RAW_SIZE (3)) |
1458 | offset = DEPRECATED_REGISTER_RAW_SIZE (3) - TYPE_LENGTH (valtype); | |
c5aa993b JM |
1459 | |
1460 | memcpy (valbuf, | |
62700349 | 1461 | regbuf + DEPRECATED_REGISTER_BYTE (3) + offset, |
c906108c | 1462 | TYPE_LENGTH (valtype)); |
c906108c | 1463 | } |
c906108c SS |
1464 | } |
1465 | ||
977adac5 ND |
1466 | /* Return whether handle_inferior_event() should proceed through code |
1467 | starting at PC in function NAME when stepping. | |
1468 | ||
1469 | The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to | |
1470 | handle memory references that are too distant to fit in instructions | |
1471 | generated by the compiler. For example, if 'foo' in the following | |
1472 | instruction: | |
1473 | ||
1474 | lwz r9,foo(r2) | |
1475 | ||
1476 | is greater than 32767, the linker might replace the lwz with a branch to | |
1477 | somewhere in @FIX1 that does the load in 2 instructions and then branches | |
1478 | back to where execution should continue. | |
1479 | ||
1480 | GDB should silently step over @FIX code, just like AIX dbx does. | |
1481 | Unfortunately, the linker uses the "b" instruction for the branches, | |
1482 | meaning that the link register doesn't get set. Therefore, GDB's usual | |
1483 | step_over_function() mechanism won't work. | |
1484 | ||
1485 | Instead, use the IN_SOLIB_RETURN_TRAMPOLINE and SKIP_TRAMPOLINE_CODE hooks | |
1486 | in handle_inferior_event() to skip past @FIX code. */ | |
1487 | ||
1488 | int | |
1489 | rs6000_in_solib_return_trampoline (CORE_ADDR pc, char *name) | |
1490 | { | |
1491 | return name && !strncmp (name, "@FIX", 4); | |
1492 | } | |
1493 | ||
1494 | /* Skip code that the user doesn't want to see when stepping: | |
1495 | ||
1496 | 1. Indirect function calls use a piece of trampoline code to do context | |
1497 | switching, i.e. to set the new TOC table. Skip such code if we are on | |
1498 | its first instruction (as when we have single-stepped to here). | |
1499 | ||
1500 | 2. Skip shared library trampoline code (which is different from | |
c906108c | 1501 | indirect function call trampolines). |
977adac5 ND |
1502 | |
1503 | 3. Skip bigtoc fixup code. | |
1504 | ||
c906108c | 1505 | Result is desired PC to step until, or NULL if we are not in |
977adac5 | 1506 | code that should be skipped. */ |
c906108c SS |
1507 | |
1508 | CORE_ADDR | |
7a78ae4e | 1509 | rs6000_skip_trampoline_code (CORE_ADDR pc) |
c906108c | 1510 | { |
52f0bd74 | 1511 | unsigned int ii, op; |
977adac5 | 1512 | int rel; |
c906108c | 1513 | CORE_ADDR solib_target_pc; |
977adac5 | 1514 | struct minimal_symbol *msymbol; |
c906108c | 1515 | |
c5aa993b JM |
1516 | static unsigned trampoline_code[] = |
1517 | { | |
1518 | 0x800b0000, /* l r0,0x0(r11) */ | |
1519 | 0x90410014, /* st r2,0x14(r1) */ | |
1520 | 0x7c0903a6, /* mtctr r0 */ | |
1521 | 0x804b0004, /* l r2,0x4(r11) */ | |
1522 | 0x816b0008, /* l r11,0x8(r11) */ | |
1523 | 0x4e800420, /* bctr */ | |
1524 | 0x4e800020, /* br */ | |
1525 | 0 | |
c906108c SS |
1526 | }; |
1527 | ||
977adac5 ND |
1528 | /* Check for bigtoc fixup code. */ |
1529 | msymbol = lookup_minimal_symbol_by_pc (pc); | |
22abf04a | 1530 | if (msymbol && rs6000_in_solib_return_trampoline (pc, DEPRECATED_SYMBOL_NAME (msymbol))) |
977adac5 ND |
1531 | { |
1532 | /* Double-check that the third instruction from PC is relative "b". */ | |
1533 | op = read_memory_integer (pc + 8, 4); | |
1534 | if ((op & 0xfc000003) == 0x48000000) | |
1535 | { | |
1536 | /* Extract bits 6-29 as a signed 24-bit relative word address and | |
1537 | add it to the containing PC. */ | |
1538 | rel = ((int)(op << 6) >> 6); | |
1539 | return pc + 8 + rel; | |
1540 | } | |
1541 | } | |
1542 | ||
c906108c SS |
1543 | /* If pc is in a shared library trampoline, return its target. */ |
1544 | solib_target_pc = find_solib_trampoline_target (pc); | |
1545 | if (solib_target_pc) | |
1546 | return solib_target_pc; | |
1547 | ||
c5aa993b JM |
1548 | for (ii = 0; trampoline_code[ii]; ++ii) |
1549 | { | |
1550 | op = read_memory_integer (pc + (ii * 4), 4); | |
1551 | if (op != trampoline_code[ii]) | |
1552 | return 0; | |
1553 | } | |
1554 | ii = read_register (11); /* r11 holds destination addr */ | |
21283beb | 1555 | pc = read_memory_addr (ii, gdbarch_tdep (current_gdbarch)->wordsize); /* (r11) value */ |
c906108c SS |
1556 | return pc; |
1557 | } | |
1558 | ||
7a78ae4e | 1559 | /* Return the size of register REG when words are WORDSIZE bytes long. If REG |
64366f1c | 1560 | isn't available with that word size, return 0. */ |
7a78ae4e ND |
1561 | |
1562 | static int | |
1563 | regsize (const struct reg *reg, int wordsize) | |
1564 | { | |
1565 | return wordsize == 8 ? reg->sz64 : reg->sz32; | |
1566 | } | |
1567 | ||
1568 | /* Return the name of register number N, or null if no such register exists | |
64366f1c | 1569 | in the current architecture. */ |
7a78ae4e | 1570 | |
fa88f677 | 1571 | static const char * |
7a78ae4e ND |
1572 | rs6000_register_name (int n) |
1573 | { | |
21283beb | 1574 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
7a78ae4e ND |
1575 | const struct reg *reg = tdep->regs + n; |
1576 | ||
1577 | if (!regsize (reg, tdep->wordsize)) | |
1578 | return NULL; | |
1579 | return reg->name; | |
1580 | } | |
1581 | ||
1582 | /* Index within `registers' of the first byte of the space for | |
1583 | register N. */ | |
1584 | ||
1585 | static int | |
1586 | rs6000_register_byte (int n) | |
1587 | { | |
21283beb | 1588 | return gdbarch_tdep (current_gdbarch)->regoff[n]; |
7a78ae4e ND |
1589 | } |
1590 | ||
1591 | /* Return the number of bytes of storage in the actual machine representation | |
64366f1c | 1592 | for register N if that register is available, else return 0. */ |
7a78ae4e ND |
1593 | |
1594 | static int | |
1595 | rs6000_register_raw_size (int n) | |
1596 | { | |
21283beb | 1597 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
7a78ae4e ND |
1598 | const struct reg *reg = tdep->regs + n; |
1599 | return regsize (reg, tdep->wordsize); | |
1600 | } | |
1601 | ||
7a78ae4e ND |
1602 | /* Return the GDB type object for the "standard" data type |
1603 | of data in register N. */ | |
1604 | ||
1605 | static struct type * | |
fba45db2 | 1606 | rs6000_register_virtual_type (int n) |
7a78ae4e | 1607 | { |
21283beb | 1608 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
7a78ae4e ND |
1609 | const struct reg *reg = tdep->regs + n; |
1610 | ||
1fcc0bb8 EZ |
1611 | if (reg->fpr) |
1612 | return builtin_type_double; | |
1613 | else | |
1614 | { | |
1615 | int size = regsize (reg, tdep->wordsize); | |
1616 | switch (size) | |
1617 | { | |
449a5da4 AC |
1618 | case 0: |
1619 | return builtin_type_int0; | |
1620 | case 4: | |
ed6edd9b | 1621 | return builtin_type_uint32; |
1fcc0bb8 | 1622 | case 8: |
c8001721 EZ |
1623 | if (tdep->ppc_ev0_regnum <= n && n <= tdep->ppc_ev31_regnum) |
1624 | return builtin_type_vec64; | |
1625 | else | |
ed6edd9b | 1626 | return builtin_type_uint64; |
1fcc0bb8 EZ |
1627 | break; |
1628 | case 16: | |
08cf96df | 1629 | return builtin_type_vec128; |
1fcc0bb8 EZ |
1630 | break; |
1631 | default: | |
449a5da4 AC |
1632 | internal_error (__FILE__, __LINE__, "Register %d size %d unknown", |
1633 | n, size); | |
1fcc0bb8 EZ |
1634 | } |
1635 | } | |
7a78ae4e ND |
1636 | } |
1637 | ||
7a78ae4e ND |
1638 | /* Return whether register N requires conversion when moving from raw format |
1639 | to virtual format. | |
1640 | ||
1641 | The register format for RS/6000 floating point registers is always | |
64366f1c | 1642 | double, we need a conversion if the memory format is float. */ |
7a78ae4e ND |
1643 | |
1644 | static int | |
1645 | rs6000_register_convertible (int n) | |
1646 | { | |
21283beb | 1647 | const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + n; |
7a78ae4e ND |
1648 | return reg->fpr; |
1649 | } | |
1650 | ||
1651 | /* Convert data from raw format for register N in buffer FROM | |
64366f1c | 1652 | to virtual format with type TYPE in buffer TO. */ |
7a78ae4e ND |
1653 | |
1654 | static void | |
1655 | rs6000_register_convert_to_virtual (int n, struct type *type, | |
1656 | char *from, char *to) | |
1657 | { | |
12c266ea | 1658 | if (TYPE_LENGTH (type) != DEPRECATED_REGISTER_RAW_SIZE (n)) |
7a292a7a | 1659 | { |
12c266ea | 1660 | double val = deprecated_extract_floating (from, DEPRECATED_REGISTER_RAW_SIZE (n)); |
f1908289 | 1661 | deprecated_store_floating (to, TYPE_LENGTH (type), val); |
7a78ae4e ND |
1662 | } |
1663 | else | |
12c266ea | 1664 | memcpy (to, from, DEPRECATED_REGISTER_RAW_SIZE (n)); |
7a78ae4e ND |
1665 | } |
1666 | ||
1667 | /* Convert data from virtual format with type TYPE in buffer FROM | |
64366f1c | 1668 | to raw format for register N in buffer TO. */ |
7a292a7a | 1669 | |
7a78ae4e ND |
1670 | static void |
1671 | rs6000_register_convert_to_raw (struct type *type, int n, | |
781a750d | 1672 | const char *from, char *to) |
7a78ae4e | 1673 | { |
12c266ea | 1674 | if (TYPE_LENGTH (type) != DEPRECATED_REGISTER_RAW_SIZE (n)) |
7a78ae4e | 1675 | { |
f1908289 | 1676 | double val = deprecated_extract_floating (from, TYPE_LENGTH (type)); |
12c266ea | 1677 | deprecated_store_floating (to, DEPRECATED_REGISTER_RAW_SIZE (n), val); |
7a292a7a | 1678 | } |
7a78ae4e | 1679 | else |
12c266ea | 1680 | memcpy (to, from, DEPRECATED_REGISTER_RAW_SIZE (n)); |
7a78ae4e | 1681 | } |
c906108c | 1682 | |
c8001721 EZ |
1683 | static void |
1684 | e500_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
1685 | int reg_nr, void *buffer) | |
1686 | { | |
1687 | int base_regnum; | |
1688 | int offset = 0; | |
d9d9c31f | 1689 | char temp_buffer[MAX_REGISTER_SIZE]; |
c8001721 EZ |
1690 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1691 | ||
1692 | if (reg_nr >= tdep->ppc_gp0_regnum | |
8bf659e8 | 1693 | && reg_nr < tdep->ppc_gp0_regnum + ppc_num_gprs) |
c8001721 EZ |
1694 | { |
1695 | base_regnum = reg_nr - tdep->ppc_gp0_regnum + tdep->ppc_ev0_regnum; | |
1696 | ||
1697 | /* Build the value in the provided buffer. */ | |
1698 | /* Read the raw register of which this one is the lower portion. */ | |
1699 | regcache_raw_read (regcache, base_regnum, temp_buffer); | |
1700 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
1701 | offset = 4; | |
1702 | memcpy ((char *) buffer, temp_buffer + offset, 4); | |
1703 | } | |
1704 | } | |
1705 | ||
1706 | static void | |
1707 | e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
1708 | int reg_nr, const void *buffer) | |
1709 | { | |
1710 | int base_regnum; | |
1711 | int offset = 0; | |
d9d9c31f | 1712 | char temp_buffer[MAX_REGISTER_SIZE]; |
c8001721 EZ |
1713 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1714 | ||
1715 | if (reg_nr >= tdep->ppc_gp0_regnum | |
8bf659e8 | 1716 | && reg_nr < tdep->ppc_gp0_regnum + ppc_num_gprs) |
c8001721 EZ |
1717 | { |
1718 | base_regnum = reg_nr - tdep->ppc_gp0_regnum + tdep->ppc_ev0_regnum; | |
1719 | /* reg_nr is 32 bit here, and base_regnum is 64 bits. */ | |
1720 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
1721 | offset = 4; | |
1722 | ||
1723 | /* Let's read the value of the base register into a temporary | |
1724 | buffer, so that overwriting the last four bytes with the new | |
1725 | value of the pseudo will leave the upper 4 bytes unchanged. */ | |
1726 | regcache_raw_read (regcache, base_regnum, temp_buffer); | |
1727 | ||
1728 | /* Write as an 8 byte quantity. */ | |
1729 | memcpy (temp_buffer + offset, (char *) buffer, 4); | |
1730 | regcache_raw_write (regcache, base_regnum, temp_buffer); | |
1731 | } | |
1732 | } | |
1733 | ||
9f744501 JB |
1734 | /* Convert a dbx stab or Dwarf 2 register number (from `r' |
1735 | declaration) to a gdb REGNUM. */ | |
c8001721 | 1736 | static int |
9f744501 | 1737 | rs6000_dwarf2_stab_reg_to_regnum (int num) |
c8001721 | 1738 | { |
9f744501 | 1739 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c8001721 | 1740 | |
9f744501 JB |
1741 | if (0 <= num && num <= 31) |
1742 | return tdep->ppc_gp0_regnum + num; | |
1743 | else if (32 <= num && num <= 63) | |
383f0f5b JB |
1744 | /* FIXME: jimb/2004-05-05: What should we do when the debug info |
1745 | specifies registers the architecture doesn't have? Our | |
1746 | callers don't check the value we return. */ | |
366f009f | 1747 | return tdep->ppc_fp0_regnum + (num - 32); |
9f744501 JB |
1748 | else if (1200 <= num && num < 1200 + 32) |
1749 | return tdep->ppc_ev0_regnum + (num - 1200); | |
1750 | else | |
1751 | switch (num) | |
1752 | { | |
1753 | case 64: | |
1754 | return tdep->ppc_mq_regnum; | |
1755 | case 65: | |
1756 | return tdep->ppc_lr_regnum; | |
1757 | case 66: | |
1758 | return tdep->ppc_ctr_regnum; | |
1759 | case 76: | |
1760 | return tdep->ppc_xer_regnum; | |
1761 | case 109: | |
1762 | return tdep->ppc_vrsave_regnum; | |
1763 | default: | |
1764 | return num; | |
1765 | } | |
1766 | ||
1767 | /* FIXME: jimb/2004-03-28: Doesn't something need to be done here | |
1768 | for the Altivec registers, too? | |
1769 | ||
1770 | Looking at GCC, the headers in config/rs6000 never define a | |
1771 | DBX_REGISTER_NUMBER macro, so the debug info uses the same | |
1772 | numbers GCC does internally. Then, looking at the REGISTER_NAMES | |
1773 | macro defined in config/rs6000/rs6000.h, it seems that GCC gives | |
1774 | v0 -- v31 the numbers 77 -- 108. But we number them 119 -- 150. | |
1775 | ||
1776 | I don't have a way to test this ready to hand, but I noticed it | |
1777 | and thought I should include a note. */ | |
2188cbdd EZ |
1778 | } |
1779 | ||
7a78ae4e ND |
1780 | static void |
1781 | rs6000_store_return_value (struct type *type, char *valbuf) | |
1782 | { | |
ace1378a EZ |
1783 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
1784 | ||
383f0f5b JB |
1785 | /* The calling convention this function implements assumes the |
1786 | processor has floating-point registers. We shouldn't be using it | |
1787 | on PPC variants that lack them. */ | |
1788 | gdb_assert (ppc_floating_point_unit_p (current_gdbarch)); | |
1789 | ||
7a78ae4e ND |
1790 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
1791 | ||
1792 | /* Floating point values are returned starting from FPR1 and up. | |
1793 | Say a double_double_double type could be returned in | |
64366f1c | 1794 | FPR1/FPR2/FPR3 triple. */ |
7a78ae4e | 1795 | |
366f009f JB |
1796 | deprecated_write_register_bytes |
1797 | (DEPRECATED_REGISTER_BYTE (tdep->ppc_fp0_regnum + 1), | |
1798 | valbuf, | |
1799 | TYPE_LENGTH (type)); | |
ace1378a EZ |
1800 | else if (TYPE_CODE (type) == TYPE_CODE_ARRAY) |
1801 | { | |
1802 | if (TYPE_LENGTH (type) == 16 | |
1803 | && TYPE_VECTOR (type)) | |
62700349 | 1804 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (tdep->ppc_vr0_regnum + 2), |
73937e03 | 1805 | valbuf, TYPE_LENGTH (type)); |
ace1378a | 1806 | } |
7a78ae4e | 1807 | else |
64366f1c | 1808 | /* Everything else is returned in GPR3 and up. */ |
62700349 | 1809 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (gdbarch_tdep (current_gdbarch)->ppc_gp0_regnum + 3), |
73937e03 | 1810 | valbuf, TYPE_LENGTH (type)); |
7a78ae4e ND |
1811 | } |
1812 | ||
1813 | /* Extract from an array REGBUF containing the (raw) register state | |
1814 | the address in which a function should return its structure value, | |
1815 | as a CORE_ADDR (or an expression that can be used as one). */ | |
1816 | ||
1817 | static CORE_ADDR | |
11269d7e AC |
1818 | rs6000_extract_struct_value_address (struct regcache *regcache) |
1819 | { | |
1820 | /* FIXME: cagney/2002-09-26: PR gdb/724: When making an inferior | |
1821 | function call GDB knows the address of the struct return value | |
1822 | and hence, should not need to call this function. Unfortunately, | |
e8a8712a AC |
1823 | the current call_function_by_hand() code only saves the most |
1824 | recent struct address leading to occasional calls. The code | |
1825 | should instead maintain a stack of such addresses (in the dummy | |
1826 | frame object). */ | |
11269d7e AC |
1827 | /* NOTE: cagney/2002-09-26: Return 0 which indicates that we've |
1828 | really got no idea where the return value is being stored. While | |
1829 | r3, on function entry, contained the address it will have since | |
1830 | been reused (scratch) and hence wouldn't be valid */ | |
1831 | return 0; | |
7a78ae4e ND |
1832 | } |
1833 | ||
64366f1c | 1834 | /* Hook called when a new child process is started. */ |
7a78ae4e ND |
1835 | |
1836 | void | |
1837 | rs6000_create_inferior (int pid) | |
1838 | { | |
1839 | if (rs6000_set_host_arch_hook) | |
1840 | rs6000_set_host_arch_hook (pid); | |
c906108c SS |
1841 | } |
1842 | \f | |
e2d0e7eb | 1843 | /* Support for CONVERT_FROM_FUNC_PTR_ADDR (ARCH, ADDR, TARG). |
7a78ae4e ND |
1844 | |
1845 | Usually a function pointer's representation is simply the address | |
1846 | of the function. On the RS/6000 however, a function pointer is | |
1847 | represented by a pointer to a TOC entry. This TOC entry contains | |
1848 | three words, the first word is the address of the function, the | |
1849 | second word is the TOC pointer (r2), and the third word is the | |
1850 | static chain value. Throughout GDB it is currently assumed that a | |
1851 | function pointer contains the address of the function, which is not | |
1852 | easy to fix. In addition, the conversion of a function address to | |
1853 | a function pointer would require allocation of a TOC entry in the | |
1854 | inferior's memory space, with all its drawbacks. To be able to | |
1855 | call C++ virtual methods in the inferior (which are called via | |
f517ea4e | 1856 | function pointers), find_function_addr uses this function to get the |
7a78ae4e ND |
1857 | function address from a function pointer. */ |
1858 | ||
f517ea4e PS |
1859 | /* Return real function address if ADDR (a function pointer) is in the data |
1860 | space and is therefore a special function pointer. */ | |
c906108c | 1861 | |
b9362cc7 | 1862 | static CORE_ADDR |
e2d0e7eb AC |
1863 | rs6000_convert_from_func_ptr_addr (struct gdbarch *gdbarch, |
1864 | CORE_ADDR addr, | |
1865 | struct target_ops *targ) | |
c906108c SS |
1866 | { |
1867 | struct obj_section *s; | |
1868 | ||
1869 | s = find_pc_section (addr); | |
1870 | if (s && s->the_bfd_section->flags & SEC_CODE) | |
7a78ae4e | 1871 | return addr; |
c906108c | 1872 | |
7a78ae4e | 1873 | /* ADDR is in the data space, so it's a special function pointer. */ |
21283beb | 1874 | return read_memory_addr (addr, gdbarch_tdep (current_gdbarch)->wordsize); |
c906108c | 1875 | } |
c906108c | 1876 | \f |
c5aa993b | 1877 | |
7a78ae4e | 1878 | /* Handling the various POWER/PowerPC variants. */ |
c906108c SS |
1879 | |
1880 | ||
7a78ae4e ND |
1881 | /* The arrays here called registers_MUMBLE hold information about available |
1882 | registers. | |
c906108c SS |
1883 | |
1884 | For each family of PPC variants, I've tried to isolate out the | |
1885 | common registers and put them up front, so that as long as you get | |
1886 | the general family right, GDB will correctly identify the registers | |
1887 | common to that family. The common register sets are: | |
1888 | ||
1889 | For the 60x family: hid0 hid1 iabr dabr pir | |
1890 | ||
1891 | For the 505 and 860 family: eie eid nri | |
1892 | ||
1893 | For the 403 and 403GC: icdbdr esr dear evpr cdbcr tsr tcr pit tbhi | |
c5aa993b JM |
1894 | tblo srr2 srr3 dbsr dbcr iac1 iac2 dac1 dac2 dccr iccr pbl1 |
1895 | pbu1 pbl2 pbu2 | |
c906108c SS |
1896 | |
1897 | Most of these register groups aren't anything formal. I arrived at | |
1898 | them by looking at the registers that occurred in more than one | |
6f5987a6 KB |
1899 | processor. |
1900 | ||
1901 | Note: kevinb/2002-04-30: Support for the fpscr register was added | |
1902 | during April, 2002. Slot 70 is being used for PowerPC and slot 71 | |
1903 | for Power. For PowerPC, slot 70 was unused and was already in the | |
1904 | PPC_UISA_SPRS which is ideally where fpscr should go. For Power, | |
1905 | slot 70 was being used for "mq", so the next available slot (71) | |
1906 | was chosen. It would have been nice to be able to make the | |
1907 | register numbers the same across processor cores, but this wasn't | |
1908 | possible without either 1) renumbering some registers for some | |
1909 | processors or 2) assigning fpscr to a really high slot that's | |
1910 | larger than any current register number. Doing (1) is bad because | |
1911 | existing stubs would break. Doing (2) is undesirable because it | |
1912 | would introduce a really large gap between fpscr and the rest of | |
1913 | the registers for most processors. */ | |
7a78ae4e | 1914 | |
64366f1c | 1915 | /* Convenience macros for populating register arrays. */ |
7a78ae4e | 1916 | |
64366f1c | 1917 | /* Within another macro, convert S to a string. */ |
7a78ae4e ND |
1918 | |
1919 | #define STR(s) #s | |
1920 | ||
1921 | /* Return a struct reg defining register NAME that's 32 bits on 32-bit systems | |
64366f1c | 1922 | and 64 bits on 64-bit systems. */ |
489461e2 | 1923 | #define R(name) { STR(name), 4, 8, 0, 0 } |
7a78ae4e ND |
1924 | |
1925 | /* Return a struct reg defining register NAME that's 32 bits on all | |
64366f1c | 1926 | systems. */ |
489461e2 | 1927 | #define R4(name) { STR(name), 4, 4, 0, 0 } |
7a78ae4e ND |
1928 | |
1929 | /* Return a struct reg defining register NAME that's 64 bits on all | |
64366f1c | 1930 | systems. */ |
489461e2 | 1931 | #define R8(name) { STR(name), 8, 8, 0, 0 } |
7a78ae4e | 1932 | |
1fcc0bb8 | 1933 | /* Return a struct reg defining register NAME that's 128 bits on all |
64366f1c | 1934 | systems. */ |
489461e2 | 1935 | #define R16(name) { STR(name), 16, 16, 0, 0 } |
1fcc0bb8 | 1936 | |
64366f1c | 1937 | /* Return a struct reg defining floating-point register NAME. */ |
489461e2 EZ |
1938 | #define F(name) { STR(name), 8, 8, 1, 0 } |
1939 | ||
64366f1c | 1940 | /* Return a struct reg defining a pseudo register NAME. */ |
489461e2 | 1941 | #define P(name) { STR(name), 4, 8, 0, 1} |
7a78ae4e ND |
1942 | |
1943 | /* Return a struct reg defining register NAME that's 32 bits on 32-bit | |
64366f1c | 1944 | systems and that doesn't exist on 64-bit systems. */ |
489461e2 | 1945 | #define R32(name) { STR(name), 4, 0, 0, 0 } |
7a78ae4e ND |
1946 | |
1947 | /* Return a struct reg defining register NAME that's 64 bits on 64-bit | |
64366f1c | 1948 | systems and that doesn't exist on 32-bit systems. */ |
489461e2 | 1949 | #define R64(name) { STR(name), 0, 8, 0, 0 } |
7a78ae4e | 1950 | |
64366f1c | 1951 | /* Return a struct reg placeholder for a register that doesn't exist. */ |
489461e2 | 1952 | #define R0 { 0, 0, 0, 0, 0 } |
7a78ae4e ND |
1953 | |
1954 | /* UISA registers common across all architectures, including POWER. */ | |
1955 | ||
1956 | #define COMMON_UISA_REGS \ | |
1957 | /* 0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), \ | |
1958 | /* 8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \ | |
1959 | /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \ | |
1960 | /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \ | |
1961 | /* 32 */ F(f0), F(f1), F(f2), F(f3), F(f4), F(f5), F(f6), F(f7), \ | |
1962 | /* 40 */ F(f8), F(f9), F(f10),F(f11),F(f12),F(f13),F(f14),F(f15), \ | |
1963 | /* 48 */ F(f16),F(f17),F(f18),F(f19),F(f20),F(f21),F(f22),F(f23), \ | |
1964 | /* 56 */ F(f24),F(f25),F(f26),F(f27),F(f28),F(f29),F(f30),F(f31), \ | |
1965 | /* 64 */ R(pc), R(ps) | |
1966 | ||
ebeac11a EZ |
1967 | #define COMMON_UISA_NOFP_REGS \ |
1968 | /* 0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), \ | |
1969 | /* 8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \ | |
1970 | /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \ | |
1971 | /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \ | |
1972 | /* 32 */ R0, R0, R0, R0, R0, R0, R0, R0, \ | |
1973 | /* 40 */ R0, R0, R0, R0, R0, R0, R0, R0, \ | |
1974 | /* 48 */ R0, R0, R0, R0, R0, R0, R0, R0, \ | |
1975 | /* 56 */ R0, R0, R0, R0, R0, R0, R0, R0, \ | |
1976 | /* 64 */ R(pc), R(ps) | |
1977 | ||
7a78ae4e ND |
1978 | /* UISA-level SPRs for PowerPC. */ |
1979 | #define PPC_UISA_SPRS \ | |
e3f36dbd | 1980 | /* 66 */ R4(cr), R(lr), R(ctr), R4(xer), R4(fpscr) |
7a78ae4e | 1981 | |
c8001721 EZ |
1982 | /* UISA-level SPRs for PowerPC without floating point support. */ |
1983 | #define PPC_UISA_NOFP_SPRS \ | |
1984 | /* 66 */ R4(cr), R(lr), R(ctr), R4(xer), R0 | |
1985 | ||
7a78ae4e ND |
1986 | /* Segment registers, for PowerPC. */ |
1987 | #define PPC_SEGMENT_REGS \ | |
1988 | /* 71 */ R32(sr0), R32(sr1), R32(sr2), R32(sr3), \ | |
1989 | /* 75 */ R32(sr4), R32(sr5), R32(sr6), R32(sr7), \ | |
1990 | /* 79 */ R32(sr8), R32(sr9), R32(sr10), R32(sr11), \ | |
1991 | /* 83 */ R32(sr12), R32(sr13), R32(sr14), R32(sr15) | |
1992 | ||
1993 | /* OEA SPRs for PowerPC. */ | |
1994 | #define PPC_OEA_SPRS \ | |
1995 | /* 87 */ R4(pvr), \ | |
1996 | /* 88 */ R(ibat0u), R(ibat0l), R(ibat1u), R(ibat1l), \ | |
1997 | /* 92 */ R(ibat2u), R(ibat2l), R(ibat3u), R(ibat3l), \ | |
1998 | /* 96 */ R(dbat0u), R(dbat0l), R(dbat1u), R(dbat1l), \ | |
1999 | /* 100 */ R(dbat2u), R(dbat2l), R(dbat3u), R(dbat3l), \ | |
2000 | /* 104 */ R(sdr1), R64(asr), R(dar), R4(dsisr), \ | |
2001 | /* 108 */ R(sprg0), R(sprg1), R(sprg2), R(sprg3), \ | |
2002 | /* 112 */ R(srr0), R(srr1), R(tbl), R(tbu), \ | |
2003 | /* 116 */ R4(dec), R(dabr), R4(ear) | |
2004 | ||
64366f1c | 2005 | /* AltiVec registers. */ |
1fcc0bb8 EZ |
2006 | #define PPC_ALTIVEC_REGS \ |
2007 | /*119*/R16(vr0), R16(vr1), R16(vr2), R16(vr3), R16(vr4), R16(vr5), R16(vr6), R16(vr7), \ | |
2008 | /*127*/R16(vr8), R16(vr9), R16(vr10),R16(vr11),R16(vr12),R16(vr13),R16(vr14),R16(vr15), \ | |
2009 | /*135*/R16(vr16),R16(vr17),R16(vr18),R16(vr19),R16(vr20),R16(vr21),R16(vr22),R16(vr23), \ | |
2010 | /*143*/R16(vr24),R16(vr25),R16(vr26),R16(vr27),R16(vr28),R16(vr29),R16(vr30),R16(vr31), \ | |
2011 | /*151*/R4(vscr), R4(vrsave) | |
2012 | ||
c8001721 EZ |
2013 | /* Vectors of hi-lo general purpose registers. */ |
2014 | #define PPC_EV_REGS \ | |
2015 | /* 0*/R8(ev0), R8(ev1), R8(ev2), R8(ev3), R8(ev4), R8(ev5), R8(ev6), R8(ev7), \ | |
2016 | /* 8*/R8(ev8), R8(ev9), R8(ev10),R8(ev11),R8(ev12),R8(ev13),R8(ev14),R8(ev15), \ | |
2017 | /*16*/R8(ev16),R8(ev17),R8(ev18),R8(ev19),R8(ev20),R8(ev21),R8(ev22),R8(ev23), \ | |
2018 | /*24*/R8(ev24),R8(ev25),R8(ev26),R8(ev27),R8(ev28),R8(ev29),R8(ev30),R8(ev31) | |
2019 | ||
2020 | /* Lower half of the EV registers. */ | |
2021 | #define PPC_GPRS_PSEUDO_REGS \ | |
2022 | /* 0 */ P(r0), P(r1), P(r2), P(r3), P(r4), P(r5), P(r6), P(r7), \ | |
2023 | /* 8 */ P(r8), P(r9), P(r10),P(r11),P(r12),P(r13),P(r14),P(r15), \ | |
2024 | /* 16 */ P(r16),P(r17),P(r18),P(r19),P(r20),P(r21),P(r22),P(r23), \ | |
338ef23d | 2025 | /* 24 */ P(r24),P(r25),P(r26),P(r27),P(r28),P(r29),P(r30),P(r31) |
c8001721 | 2026 | |
7a78ae4e | 2027 | /* IBM POWER (pre-PowerPC) architecture, user-level view. We only cover |
64366f1c | 2028 | user-level SPR's. */ |
7a78ae4e | 2029 | static const struct reg registers_power[] = |
c906108c | 2030 | { |
7a78ae4e | 2031 | COMMON_UISA_REGS, |
e3f36dbd KB |
2032 | /* 66 */ R4(cnd), R(lr), R(cnt), R4(xer), R4(mq), |
2033 | /* 71 */ R4(fpscr) | |
c906108c SS |
2034 | }; |
2035 | ||
7a78ae4e | 2036 | /* PowerPC UISA - a PPC processor as viewed by user-level code. A UISA-only |
64366f1c | 2037 | view of the PowerPC. */ |
7a78ae4e | 2038 | static const struct reg registers_powerpc[] = |
c906108c | 2039 | { |
7a78ae4e | 2040 | COMMON_UISA_REGS, |
1fcc0bb8 EZ |
2041 | PPC_UISA_SPRS, |
2042 | PPC_ALTIVEC_REGS | |
c906108c SS |
2043 | }; |
2044 | ||
ebeac11a EZ |
2045 | /* PowerPC UISA - a PPC processor as viewed by user-level |
2046 | code, but without floating point registers. */ | |
2047 | static const struct reg registers_powerpc_nofp[] = | |
2048 | { | |
2049 | COMMON_UISA_NOFP_REGS, | |
2050 | PPC_UISA_SPRS | |
2051 | }; | |
2052 | ||
64366f1c | 2053 | /* IBM PowerPC 403. */ |
7a78ae4e | 2054 | static const struct reg registers_403[] = |
c5aa993b | 2055 | { |
7a78ae4e ND |
2056 | COMMON_UISA_REGS, |
2057 | PPC_UISA_SPRS, | |
2058 | PPC_SEGMENT_REGS, | |
2059 | PPC_OEA_SPRS, | |
2060 | /* 119 */ R(icdbdr), R(esr), R(dear), R(evpr), | |
2061 | /* 123 */ R(cdbcr), R(tsr), R(tcr), R(pit), | |
2062 | /* 127 */ R(tbhi), R(tblo), R(srr2), R(srr3), | |
2063 | /* 131 */ R(dbsr), R(dbcr), R(iac1), R(iac2), | |
2064 | /* 135 */ R(dac1), R(dac2), R(dccr), R(iccr), | |
2065 | /* 139 */ R(pbl1), R(pbu1), R(pbl2), R(pbu2) | |
c906108c SS |
2066 | }; |
2067 | ||
64366f1c | 2068 | /* IBM PowerPC 403GC. */ |
7a78ae4e | 2069 | static const struct reg registers_403GC[] = |
c5aa993b | 2070 | { |
7a78ae4e ND |
2071 | COMMON_UISA_REGS, |
2072 | PPC_UISA_SPRS, | |
2073 | PPC_SEGMENT_REGS, | |
2074 | PPC_OEA_SPRS, | |
2075 | /* 119 */ R(icdbdr), R(esr), R(dear), R(evpr), | |
2076 | /* 123 */ R(cdbcr), R(tsr), R(tcr), R(pit), | |
2077 | /* 127 */ R(tbhi), R(tblo), R(srr2), R(srr3), | |
2078 | /* 131 */ R(dbsr), R(dbcr), R(iac1), R(iac2), | |
2079 | /* 135 */ R(dac1), R(dac2), R(dccr), R(iccr), | |
2080 | /* 139 */ R(pbl1), R(pbu1), R(pbl2), R(pbu2), | |
2081 | /* 143 */ R(zpr), R(pid), R(sgr), R(dcwr), | |
2082 | /* 147 */ R(tbhu), R(tblu) | |
c906108c SS |
2083 | }; |
2084 | ||
64366f1c | 2085 | /* Motorola PowerPC 505. */ |
7a78ae4e | 2086 | static const struct reg registers_505[] = |
c5aa993b | 2087 | { |
7a78ae4e ND |
2088 | COMMON_UISA_REGS, |
2089 | PPC_UISA_SPRS, | |
2090 | PPC_SEGMENT_REGS, | |
2091 | PPC_OEA_SPRS, | |
2092 | /* 119 */ R(eie), R(eid), R(nri) | |
c906108c SS |
2093 | }; |
2094 | ||
64366f1c | 2095 | /* Motorola PowerPC 860 or 850. */ |
7a78ae4e | 2096 | static const struct reg registers_860[] = |
c5aa993b | 2097 | { |
7a78ae4e ND |
2098 | COMMON_UISA_REGS, |
2099 | PPC_UISA_SPRS, | |
2100 | PPC_SEGMENT_REGS, | |
2101 | PPC_OEA_SPRS, | |
2102 | /* 119 */ R(eie), R(eid), R(nri), R(cmpa), | |
2103 | /* 123 */ R(cmpb), R(cmpc), R(cmpd), R(icr), | |
2104 | /* 127 */ R(der), R(counta), R(countb), R(cmpe), | |
2105 | /* 131 */ R(cmpf), R(cmpg), R(cmph), R(lctrl1), | |
2106 | /* 135 */ R(lctrl2), R(ictrl), R(bar), R(ic_cst), | |
2107 | /* 139 */ R(ic_adr), R(ic_dat), R(dc_cst), R(dc_adr), | |
2108 | /* 143 */ R(dc_dat), R(dpdr), R(dpir), R(immr), | |
2109 | /* 147 */ R(mi_ctr), R(mi_ap), R(mi_epn), R(mi_twc), | |
2110 | /* 151 */ R(mi_rpn), R(md_ctr), R(m_casid), R(md_ap), | |
2111 | /* 155 */ R(md_epn), R(md_twb), R(md_twc), R(md_rpn), | |
2112 | /* 159 */ R(m_tw), R(mi_dbcam), R(mi_dbram0), R(mi_dbram1), | |
2113 | /* 163 */ R(md_dbcam), R(md_dbram0), R(md_dbram1) | |
c906108c SS |
2114 | }; |
2115 | ||
7a78ae4e ND |
2116 | /* Motorola PowerPC 601. Note that the 601 has different register numbers |
2117 | for reading and writing RTCU and RTCL. However, how one reads and writes a | |
c906108c | 2118 | register is the stub's problem. */ |
7a78ae4e | 2119 | static const struct reg registers_601[] = |
c5aa993b | 2120 | { |
7a78ae4e ND |
2121 | COMMON_UISA_REGS, |
2122 | PPC_UISA_SPRS, | |
2123 | PPC_SEGMENT_REGS, | |
2124 | PPC_OEA_SPRS, | |
2125 | /* 119 */ R(hid0), R(hid1), R(iabr), R(dabr), | |
2126 | /* 123 */ R(pir), R(mq), R(rtcu), R(rtcl) | |
c906108c SS |
2127 | }; |
2128 | ||
64366f1c | 2129 | /* Motorola PowerPC 602. */ |
7a78ae4e | 2130 | static const struct reg registers_602[] = |
c5aa993b | 2131 | { |
7a78ae4e ND |
2132 | COMMON_UISA_REGS, |
2133 | PPC_UISA_SPRS, | |
2134 | PPC_SEGMENT_REGS, | |
2135 | PPC_OEA_SPRS, | |
2136 | /* 119 */ R(hid0), R(hid1), R(iabr), R0, | |
2137 | /* 123 */ R0, R(tcr), R(ibr), R(esassr), | |
2138 | /* 127 */ R(sebr), R(ser), R(sp), R(lt) | |
c906108c SS |
2139 | }; |
2140 | ||
64366f1c | 2141 | /* Motorola/IBM PowerPC 603 or 603e. */ |
7a78ae4e | 2142 | static const struct reg registers_603[] = |
c5aa993b | 2143 | { |
7a78ae4e ND |
2144 | COMMON_UISA_REGS, |
2145 | PPC_UISA_SPRS, | |
2146 | PPC_SEGMENT_REGS, | |
2147 | PPC_OEA_SPRS, | |
2148 | /* 119 */ R(hid0), R(hid1), R(iabr), R0, | |
2149 | /* 123 */ R0, R(dmiss), R(dcmp), R(hash1), | |
2150 | /* 127 */ R(hash2), R(imiss), R(icmp), R(rpa) | |
c906108c SS |
2151 | }; |
2152 | ||
64366f1c | 2153 | /* Motorola PowerPC 604 or 604e. */ |
7a78ae4e | 2154 | static const struct reg registers_604[] = |
c5aa993b | 2155 | { |
7a78ae4e ND |
2156 | COMMON_UISA_REGS, |
2157 | PPC_UISA_SPRS, | |
2158 | PPC_SEGMENT_REGS, | |
2159 | PPC_OEA_SPRS, | |
2160 | /* 119 */ R(hid0), R(hid1), R(iabr), R(dabr), | |
2161 | /* 123 */ R(pir), R(mmcr0), R(pmc1), R(pmc2), | |
2162 | /* 127 */ R(sia), R(sda) | |
c906108c SS |
2163 | }; |
2164 | ||
64366f1c | 2165 | /* Motorola/IBM PowerPC 750 or 740. */ |
7a78ae4e | 2166 | static const struct reg registers_750[] = |
c5aa993b | 2167 | { |
7a78ae4e ND |
2168 | COMMON_UISA_REGS, |
2169 | PPC_UISA_SPRS, | |
2170 | PPC_SEGMENT_REGS, | |
2171 | PPC_OEA_SPRS, | |
2172 | /* 119 */ R(hid0), R(hid1), R(iabr), R(dabr), | |
2173 | /* 123 */ R0, R(ummcr0), R(upmc1), R(upmc2), | |
2174 | /* 127 */ R(usia), R(ummcr1), R(upmc3), R(upmc4), | |
2175 | /* 131 */ R(mmcr0), R(pmc1), R(pmc2), R(sia), | |
2176 | /* 135 */ R(mmcr1), R(pmc3), R(pmc4), R(l2cr), | |
2177 | /* 139 */ R(ictc), R(thrm1), R(thrm2), R(thrm3) | |
c906108c SS |
2178 | }; |
2179 | ||
2180 | ||
64366f1c | 2181 | /* Motorola PowerPC 7400. */ |
1fcc0bb8 EZ |
2182 | static const struct reg registers_7400[] = |
2183 | { | |
2184 | /* gpr0-gpr31, fpr0-fpr31 */ | |
2185 | COMMON_UISA_REGS, | |
13c7b1ca | 2186 | /* cr, lr, ctr, xer, fpscr */ |
1fcc0bb8 EZ |
2187 | PPC_UISA_SPRS, |
2188 | /* sr0-sr15 */ | |
2189 | PPC_SEGMENT_REGS, | |
2190 | PPC_OEA_SPRS, | |
2191 | /* vr0-vr31, vrsave, vscr */ | |
2192 | PPC_ALTIVEC_REGS | |
2193 | /* FIXME? Add more registers? */ | |
2194 | }; | |
2195 | ||
c8001721 EZ |
2196 | /* Motorola e500. */ |
2197 | static const struct reg registers_e500[] = | |
2198 | { | |
2199 | R(pc), R(ps), | |
2200 | /* cr, lr, ctr, xer, "" */ | |
2201 | PPC_UISA_NOFP_SPRS, | |
2202 | /* 7...38 */ | |
2203 | PPC_EV_REGS, | |
338ef23d AC |
2204 | R8(acc), R(spefscr), |
2205 | /* NOTE: Add new registers here the end of the raw register | |
2206 | list and just before the first pseudo register. */ | |
13c7b1ca | 2207 | /* 41...72 */ |
c8001721 EZ |
2208 | PPC_GPRS_PSEUDO_REGS |
2209 | }; | |
2210 | ||
c906108c | 2211 | /* Information about a particular processor variant. */ |
7a78ae4e | 2212 | |
c906108c | 2213 | struct variant |
c5aa993b JM |
2214 | { |
2215 | /* Name of this variant. */ | |
2216 | char *name; | |
c906108c | 2217 | |
c5aa993b JM |
2218 | /* English description of the variant. */ |
2219 | char *description; | |
c906108c | 2220 | |
64366f1c | 2221 | /* bfd_arch_info.arch corresponding to variant. */ |
7a78ae4e ND |
2222 | enum bfd_architecture arch; |
2223 | ||
64366f1c | 2224 | /* bfd_arch_info.mach corresponding to variant. */ |
7a78ae4e ND |
2225 | unsigned long mach; |
2226 | ||
489461e2 EZ |
2227 | /* Number of real registers. */ |
2228 | int nregs; | |
2229 | ||
2230 | /* Number of pseudo registers. */ | |
2231 | int npregs; | |
2232 | ||
2233 | /* Number of total registers (the sum of nregs and npregs). */ | |
2234 | int num_tot_regs; | |
2235 | ||
c5aa993b JM |
2236 | /* Table of register names; registers[R] is the name of the register |
2237 | number R. */ | |
7a78ae4e | 2238 | const struct reg *regs; |
c5aa993b | 2239 | }; |
c906108c | 2240 | |
489461e2 EZ |
2241 | #define tot_num_registers(list) (sizeof (list) / sizeof((list)[0])) |
2242 | ||
2243 | static int | |
2244 | num_registers (const struct reg *reg_list, int num_tot_regs) | |
2245 | { | |
2246 | int i; | |
2247 | int nregs = 0; | |
2248 | ||
2249 | for (i = 0; i < num_tot_regs; i++) | |
2250 | if (!reg_list[i].pseudo) | |
2251 | nregs++; | |
2252 | ||
2253 | return nregs; | |
2254 | } | |
2255 | ||
2256 | static int | |
2257 | num_pseudo_registers (const struct reg *reg_list, int num_tot_regs) | |
2258 | { | |
2259 | int i; | |
2260 | int npregs = 0; | |
2261 | ||
2262 | for (i = 0; i < num_tot_regs; i++) | |
2263 | if (reg_list[i].pseudo) | |
2264 | npregs ++; | |
2265 | ||
2266 | return npregs; | |
2267 | } | |
c906108c | 2268 | |
c906108c SS |
2269 | /* Information in this table comes from the following web sites: |
2270 | IBM: http://www.chips.ibm.com:80/products/embedded/ | |
2271 | Motorola: http://www.mot.com/SPS/PowerPC/ | |
2272 | ||
2273 | I'm sure I've got some of the variant descriptions not quite right. | |
2274 | Please report any inaccuracies you find to GDB's maintainer. | |
2275 | ||
2276 | If you add entries to this table, please be sure to allow the new | |
2277 | value as an argument to the --with-cpu flag, in configure.in. */ | |
2278 | ||
489461e2 | 2279 | static struct variant variants[] = |
c906108c | 2280 | { |
489461e2 | 2281 | |
7a78ae4e | 2282 | {"powerpc", "PowerPC user-level", bfd_arch_powerpc, |
489461e2 EZ |
2283 | bfd_mach_ppc, -1, -1, tot_num_registers (registers_powerpc), |
2284 | registers_powerpc}, | |
7a78ae4e | 2285 | {"power", "POWER user-level", bfd_arch_rs6000, |
489461e2 EZ |
2286 | bfd_mach_rs6k, -1, -1, tot_num_registers (registers_power), |
2287 | registers_power}, | |
7a78ae4e | 2288 | {"403", "IBM PowerPC 403", bfd_arch_powerpc, |
489461e2 EZ |
2289 | bfd_mach_ppc_403, -1, -1, tot_num_registers (registers_403), |
2290 | registers_403}, | |
7a78ae4e | 2291 | {"601", "Motorola PowerPC 601", bfd_arch_powerpc, |
489461e2 EZ |
2292 | bfd_mach_ppc_601, -1, -1, tot_num_registers (registers_601), |
2293 | registers_601}, | |
7a78ae4e | 2294 | {"602", "Motorola PowerPC 602", bfd_arch_powerpc, |
489461e2 EZ |
2295 | bfd_mach_ppc_602, -1, -1, tot_num_registers (registers_602), |
2296 | registers_602}, | |
7a78ae4e | 2297 | {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc, |
489461e2 EZ |
2298 | bfd_mach_ppc_603, -1, -1, tot_num_registers (registers_603), |
2299 | registers_603}, | |
7a78ae4e | 2300 | {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc, |
489461e2 EZ |
2301 | 604, -1, -1, tot_num_registers (registers_604), |
2302 | registers_604}, | |
7a78ae4e | 2303 | {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc, |
489461e2 EZ |
2304 | bfd_mach_ppc_403gc, -1, -1, tot_num_registers (registers_403GC), |
2305 | registers_403GC}, | |
7a78ae4e | 2306 | {"505", "Motorola PowerPC 505", bfd_arch_powerpc, |
489461e2 EZ |
2307 | bfd_mach_ppc_505, -1, -1, tot_num_registers (registers_505), |
2308 | registers_505}, | |
7a78ae4e | 2309 | {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc, |
489461e2 EZ |
2310 | bfd_mach_ppc_860, -1, -1, tot_num_registers (registers_860), |
2311 | registers_860}, | |
7a78ae4e | 2312 | {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc, |
489461e2 EZ |
2313 | bfd_mach_ppc_750, -1, -1, tot_num_registers (registers_750), |
2314 | registers_750}, | |
1fcc0bb8 | 2315 | {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc, |
489461e2 EZ |
2316 | bfd_mach_ppc_7400, -1, -1, tot_num_registers (registers_7400), |
2317 | registers_7400}, | |
c8001721 EZ |
2318 | {"e500", "Motorola PowerPC e500", bfd_arch_powerpc, |
2319 | bfd_mach_ppc_e500, -1, -1, tot_num_registers (registers_e500), | |
2320 | registers_e500}, | |
7a78ae4e | 2321 | |
5d57ee30 KB |
2322 | /* 64-bit */ |
2323 | {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc, | |
489461e2 EZ |
2324 | bfd_mach_ppc64, -1, -1, tot_num_registers (registers_powerpc), |
2325 | registers_powerpc}, | |
7a78ae4e | 2326 | {"620", "Motorola PowerPC 620", bfd_arch_powerpc, |
489461e2 EZ |
2327 | bfd_mach_ppc_620, -1, -1, tot_num_registers (registers_powerpc), |
2328 | registers_powerpc}, | |
5d57ee30 | 2329 | {"630", "Motorola PowerPC 630", bfd_arch_powerpc, |
489461e2 EZ |
2330 | bfd_mach_ppc_630, -1, -1, tot_num_registers (registers_powerpc), |
2331 | registers_powerpc}, | |
7a78ae4e | 2332 | {"a35", "PowerPC A35", bfd_arch_powerpc, |
489461e2 EZ |
2333 | bfd_mach_ppc_a35, -1, -1, tot_num_registers (registers_powerpc), |
2334 | registers_powerpc}, | |
5d57ee30 | 2335 | {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc, |
489461e2 EZ |
2336 | bfd_mach_ppc_rs64ii, -1, -1, tot_num_registers (registers_powerpc), |
2337 | registers_powerpc}, | |
5d57ee30 | 2338 | {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc, |
489461e2 EZ |
2339 | bfd_mach_ppc_rs64iii, -1, -1, tot_num_registers (registers_powerpc), |
2340 | registers_powerpc}, | |
5d57ee30 | 2341 | |
64366f1c | 2342 | /* FIXME: I haven't checked the register sets of the following. */ |
7a78ae4e | 2343 | {"rs1", "IBM POWER RS1", bfd_arch_rs6000, |
489461e2 EZ |
2344 | bfd_mach_rs6k_rs1, -1, -1, tot_num_registers (registers_power), |
2345 | registers_power}, | |
7a78ae4e | 2346 | {"rsc", "IBM POWER RSC", bfd_arch_rs6000, |
489461e2 EZ |
2347 | bfd_mach_rs6k_rsc, -1, -1, tot_num_registers (registers_power), |
2348 | registers_power}, | |
7a78ae4e | 2349 | {"rs2", "IBM POWER RS2", bfd_arch_rs6000, |
489461e2 EZ |
2350 | bfd_mach_rs6k_rs2, -1, -1, tot_num_registers (registers_power), |
2351 | registers_power}, | |
7a78ae4e | 2352 | |
489461e2 | 2353 | {0, 0, 0, 0, 0, 0, 0, 0} |
c906108c SS |
2354 | }; |
2355 | ||
64366f1c | 2356 | /* Initialize the number of registers and pseudo registers in each variant. */ |
489461e2 EZ |
2357 | |
2358 | static void | |
2359 | init_variants (void) | |
2360 | { | |
2361 | struct variant *v; | |
2362 | ||
2363 | for (v = variants; v->name; v++) | |
2364 | { | |
2365 | if (v->nregs == -1) | |
2366 | v->nregs = num_registers (v->regs, v->num_tot_regs); | |
2367 | if (v->npregs == -1) | |
2368 | v->npregs = num_pseudo_registers (v->regs, v->num_tot_regs); | |
2369 | } | |
2370 | } | |
c906108c | 2371 | |
7a78ae4e | 2372 | /* Return the variant corresponding to architecture ARCH and machine number |
64366f1c | 2373 | MACH. If no such variant exists, return null. */ |
c906108c | 2374 | |
7a78ae4e ND |
2375 | static const struct variant * |
2376 | find_variant_by_arch (enum bfd_architecture arch, unsigned long mach) | |
c906108c | 2377 | { |
7a78ae4e | 2378 | const struct variant *v; |
c5aa993b | 2379 | |
7a78ae4e ND |
2380 | for (v = variants; v->name; v++) |
2381 | if (arch == v->arch && mach == v->mach) | |
2382 | return v; | |
c906108c | 2383 | |
7a78ae4e | 2384 | return NULL; |
c906108c | 2385 | } |
9364a0ef EZ |
2386 | |
2387 | static int | |
2388 | gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info) | |
2389 | { | |
2390 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
2391 | return print_insn_big_powerpc (memaddr, info); | |
2392 | else | |
2393 | return print_insn_little_powerpc (memaddr, info); | |
2394 | } | |
7a78ae4e | 2395 | \f |
61a65099 KB |
2396 | static CORE_ADDR |
2397 | rs6000_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
2398 | { | |
2399 | return frame_unwind_register_unsigned (next_frame, PC_REGNUM); | |
2400 | } | |
2401 | ||
2402 | static struct frame_id | |
2403 | rs6000_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
2404 | { | |
2405 | return frame_id_build (frame_unwind_register_unsigned (next_frame, | |
2406 | SP_REGNUM), | |
2407 | frame_pc_unwind (next_frame)); | |
2408 | } | |
2409 | ||
2410 | struct rs6000_frame_cache | |
2411 | { | |
2412 | CORE_ADDR base; | |
2413 | CORE_ADDR initial_sp; | |
2414 | struct trad_frame_saved_reg *saved_regs; | |
2415 | }; | |
2416 | ||
2417 | static struct rs6000_frame_cache * | |
2418 | rs6000_frame_cache (struct frame_info *next_frame, void **this_cache) | |
2419 | { | |
2420 | struct rs6000_frame_cache *cache; | |
2421 | struct gdbarch *gdbarch = get_frame_arch (next_frame); | |
2422 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2423 | struct rs6000_framedata fdata; | |
2424 | int wordsize = tdep->wordsize; | |
2425 | ||
2426 | if ((*this_cache) != NULL) | |
2427 | return (*this_cache); | |
2428 | cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache); | |
2429 | (*this_cache) = cache; | |
2430 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
2431 | ||
2432 | skip_prologue (frame_func_unwind (next_frame), frame_pc_unwind (next_frame), | |
2433 | &fdata); | |
2434 | ||
2435 | /* If there were any saved registers, figure out parent's stack | |
2436 | pointer. */ | |
2437 | /* The following is true only if the frame doesn't have a call to | |
2438 | alloca(), FIXME. */ | |
2439 | ||
2440 | if (fdata.saved_fpr == 0 | |
2441 | && fdata.saved_gpr == 0 | |
2442 | && fdata.saved_vr == 0 | |
2443 | && fdata.saved_ev == 0 | |
2444 | && fdata.lr_offset == 0 | |
2445 | && fdata.cr_offset == 0 | |
2446 | && fdata.vr_offset == 0 | |
2447 | && fdata.ev_offset == 0) | |
2448 | cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM); | |
2449 | else | |
2450 | { | |
2451 | /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most | |
2452 | address of the current frame. Things might be easier if the | |
2453 | ->frame pointed to the outer-most address of the frame. In | |
2454 | the mean time, the address of the prev frame is used as the | |
2455 | base address of this frame. */ | |
2456 | cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM); | |
2457 | if (!fdata.frameless) | |
2458 | /* Frameless really means stackless. */ | |
2459 | cache->base = read_memory_addr (cache->base, wordsize); | |
2460 | } | |
2461 | trad_frame_set_value (cache->saved_regs, SP_REGNUM, cache->base); | |
2462 | ||
2463 | /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr. | |
2464 | All fpr's from saved_fpr to fp31 are saved. */ | |
2465 | ||
2466 | if (fdata.saved_fpr >= 0) | |
2467 | { | |
2468 | int i; | |
2469 | CORE_ADDR fpr_addr = cache->base + fdata.fpr_offset; | |
383f0f5b JB |
2470 | |
2471 | /* If skip_prologue says floating-point registers were saved, | |
2472 | but the current architecture has no floating-point registers, | |
2473 | then that's strange. But we have no indices to even record | |
2474 | the addresses under, so we just ignore it. */ | |
2475 | if (ppc_floating_point_unit_p (gdbarch)) | |
2476 | for (i = fdata.saved_fpr; i < 32; i++) | |
2477 | { | |
2478 | cache->saved_regs[tdep->ppc_fp0_regnum + i].addr = fpr_addr; | |
2479 | fpr_addr += 8; | |
2480 | } | |
61a65099 KB |
2481 | } |
2482 | ||
2483 | /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr. | |
2484 | All gpr's from saved_gpr to gpr31 are saved. */ | |
2485 | ||
2486 | if (fdata.saved_gpr >= 0) | |
2487 | { | |
2488 | int i; | |
2489 | CORE_ADDR gpr_addr = cache->base + fdata.gpr_offset; | |
2490 | for (i = fdata.saved_gpr; i < 32; i++) | |
2491 | { | |
2492 | cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = gpr_addr; | |
2493 | gpr_addr += wordsize; | |
2494 | } | |
2495 | } | |
2496 | ||
2497 | /* if != -1, fdata.saved_vr is the smallest number of saved_vr. | |
2498 | All vr's from saved_vr to vr31 are saved. */ | |
2499 | if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) | |
2500 | { | |
2501 | if (fdata.saved_vr >= 0) | |
2502 | { | |
2503 | int i; | |
2504 | CORE_ADDR vr_addr = cache->base + fdata.vr_offset; | |
2505 | for (i = fdata.saved_vr; i < 32; i++) | |
2506 | { | |
2507 | cache->saved_regs[tdep->ppc_vr0_regnum + i].addr = vr_addr; | |
2508 | vr_addr += register_size (gdbarch, tdep->ppc_vr0_regnum); | |
2509 | } | |
2510 | } | |
2511 | } | |
2512 | ||
2513 | /* if != -1, fdata.saved_ev is the smallest number of saved_ev. | |
2514 | All vr's from saved_ev to ev31 are saved. ????? */ | |
2515 | if (tdep->ppc_ev0_regnum != -1 && tdep->ppc_ev31_regnum != -1) | |
2516 | { | |
2517 | if (fdata.saved_ev >= 0) | |
2518 | { | |
2519 | int i; | |
2520 | CORE_ADDR ev_addr = cache->base + fdata.ev_offset; | |
2521 | for (i = fdata.saved_ev; i < 32; i++) | |
2522 | { | |
2523 | cache->saved_regs[tdep->ppc_ev0_regnum + i].addr = ev_addr; | |
2524 | cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + 4; | |
2525 | ev_addr += register_size (gdbarch, tdep->ppc_ev0_regnum); | |
2526 | } | |
2527 | } | |
2528 | } | |
2529 | ||
2530 | /* If != 0, fdata.cr_offset is the offset from the frame that | |
2531 | holds the CR. */ | |
2532 | if (fdata.cr_offset != 0) | |
2533 | cache->saved_regs[tdep->ppc_cr_regnum].addr = cache->base + fdata.cr_offset; | |
2534 | ||
2535 | /* If != 0, fdata.lr_offset is the offset from the frame that | |
2536 | holds the LR. */ | |
2537 | if (fdata.lr_offset != 0) | |
2538 | cache->saved_regs[tdep->ppc_lr_regnum].addr = cache->base + fdata.lr_offset; | |
2539 | /* The PC is found in the link register. */ | |
2540 | cache->saved_regs[PC_REGNUM] = cache->saved_regs[tdep->ppc_lr_regnum]; | |
2541 | ||
2542 | /* If != 0, fdata.vrsave_offset is the offset from the frame that | |
2543 | holds the VRSAVE. */ | |
2544 | if (fdata.vrsave_offset != 0) | |
2545 | cache->saved_regs[tdep->ppc_vrsave_regnum].addr = cache->base + fdata.vrsave_offset; | |
2546 | ||
2547 | if (fdata.alloca_reg < 0) | |
2548 | /* If no alloca register used, then fi->frame is the value of the | |
2549 | %sp for this frame, and it is good enough. */ | |
2550 | cache->initial_sp = frame_unwind_register_unsigned (next_frame, SP_REGNUM); | |
2551 | else | |
2552 | cache->initial_sp = frame_unwind_register_unsigned (next_frame, | |
2553 | fdata.alloca_reg); | |
2554 | ||
2555 | return cache; | |
2556 | } | |
2557 | ||
2558 | static void | |
2559 | rs6000_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
2560 | struct frame_id *this_id) | |
2561 | { | |
2562 | struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame, | |
2563 | this_cache); | |
2564 | (*this_id) = frame_id_build (info->base, frame_func_unwind (next_frame)); | |
2565 | } | |
2566 | ||
2567 | static void | |
2568 | rs6000_frame_prev_register (struct frame_info *next_frame, | |
2569 | void **this_cache, | |
2570 | int regnum, int *optimizedp, | |
2571 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
2572 | int *realnump, void *valuep) | |
2573 | { | |
2574 | struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame, | |
2575 | this_cache); | |
2576 | trad_frame_prev_register (next_frame, info->saved_regs, regnum, | |
2577 | optimizedp, lvalp, addrp, realnump, valuep); | |
2578 | } | |
2579 | ||
2580 | static const struct frame_unwind rs6000_frame_unwind = | |
2581 | { | |
2582 | NORMAL_FRAME, | |
2583 | rs6000_frame_this_id, | |
2584 | rs6000_frame_prev_register | |
2585 | }; | |
2586 | ||
2587 | static const struct frame_unwind * | |
2588 | rs6000_frame_sniffer (struct frame_info *next_frame) | |
2589 | { | |
2590 | return &rs6000_frame_unwind; | |
2591 | } | |
2592 | ||
2593 | \f | |
2594 | ||
2595 | static CORE_ADDR | |
2596 | rs6000_frame_base_address (struct frame_info *next_frame, | |
2597 | void **this_cache) | |
2598 | { | |
2599 | struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame, | |
2600 | this_cache); | |
2601 | return info->initial_sp; | |
2602 | } | |
2603 | ||
2604 | static const struct frame_base rs6000_frame_base = { | |
2605 | &rs6000_frame_unwind, | |
2606 | rs6000_frame_base_address, | |
2607 | rs6000_frame_base_address, | |
2608 | rs6000_frame_base_address | |
2609 | }; | |
2610 | ||
2611 | static const struct frame_base * | |
2612 | rs6000_frame_base_sniffer (struct frame_info *next_frame) | |
2613 | { | |
2614 | return &rs6000_frame_base; | |
2615 | } | |
2616 | ||
7a78ae4e ND |
2617 | /* Initialize the current architecture based on INFO. If possible, re-use an |
2618 | architecture from ARCHES, which is a list of architectures already created | |
2619 | during this debugging session. | |
c906108c | 2620 | |
7a78ae4e | 2621 | Called e.g. at program startup, when reading a core file, and when reading |
64366f1c | 2622 | a binary file. */ |
c906108c | 2623 | |
7a78ae4e ND |
2624 | static struct gdbarch * |
2625 | rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
2626 | { | |
2627 | struct gdbarch *gdbarch; | |
2628 | struct gdbarch_tdep *tdep; | |
9aa1e687 | 2629 | int wordsize, from_xcoff_exec, from_elf_exec, power, i, off; |
7a78ae4e ND |
2630 | struct reg *regs; |
2631 | const struct variant *v; | |
2632 | enum bfd_architecture arch; | |
2633 | unsigned long mach; | |
2634 | bfd abfd; | |
7b112f9c | 2635 | int sysv_abi; |
5bf1c677 | 2636 | asection *sect; |
7a78ae4e | 2637 | |
9aa1e687 | 2638 | from_xcoff_exec = info.abfd && info.abfd->format == bfd_object && |
7a78ae4e ND |
2639 | bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour; |
2640 | ||
9aa1e687 KB |
2641 | from_elf_exec = info.abfd && info.abfd->format == bfd_object && |
2642 | bfd_get_flavour (info.abfd) == bfd_target_elf_flavour; | |
2643 | ||
2644 | sysv_abi = info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour; | |
2645 | ||
e712c1cf | 2646 | /* Check word size. If INFO is from a binary file, infer it from |
64366f1c | 2647 | that, else choose a likely default. */ |
9aa1e687 | 2648 | if (from_xcoff_exec) |
c906108c | 2649 | { |
11ed25ac | 2650 | if (bfd_xcoff_is_xcoff64 (info.abfd)) |
7a78ae4e ND |
2651 | wordsize = 8; |
2652 | else | |
2653 | wordsize = 4; | |
c906108c | 2654 | } |
9aa1e687 KB |
2655 | else if (from_elf_exec) |
2656 | { | |
2657 | if (elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
2658 | wordsize = 8; | |
2659 | else | |
2660 | wordsize = 4; | |
2661 | } | |
c906108c | 2662 | else |
7a78ae4e | 2663 | { |
27b15785 KB |
2664 | if (info.bfd_arch_info != NULL && info.bfd_arch_info->bits_per_word != 0) |
2665 | wordsize = info.bfd_arch_info->bits_per_word / | |
2666 | info.bfd_arch_info->bits_per_byte; | |
2667 | else | |
2668 | wordsize = 4; | |
7a78ae4e | 2669 | } |
c906108c | 2670 | |
64366f1c | 2671 | /* Find a candidate among extant architectures. */ |
7a78ae4e ND |
2672 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
2673 | arches != NULL; | |
2674 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
2675 | { | |
2676 | /* Word size in the various PowerPC bfd_arch_info structs isn't | |
2677 | meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform | |
64366f1c | 2678 | separate word size check. */ |
7a78ae4e | 2679 | tdep = gdbarch_tdep (arches->gdbarch); |
4be87837 | 2680 | if (tdep && tdep->wordsize == wordsize) |
7a78ae4e ND |
2681 | return arches->gdbarch; |
2682 | } | |
c906108c | 2683 | |
7a78ae4e ND |
2684 | /* None found, create a new architecture from INFO, whose bfd_arch_info |
2685 | validity depends on the source: | |
2686 | - executable useless | |
2687 | - rs6000_host_arch() good | |
2688 | - core file good | |
2689 | - "set arch" trust blindly | |
2690 | - GDB startup useless but harmless */ | |
c906108c | 2691 | |
9aa1e687 | 2692 | if (!from_xcoff_exec) |
c906108c | 2693 | { |
b732d07d | 2694 | arch = info.bfd_arch_info->arch; |
7a78ae4e | 2695 | mach = info.bfd_arch_info->mach; |
c906108c | 2696 | } |
7a78ae4e | 2697 | else |
c906108c | 2698 | { |
7a78ae4e | 2699 | arch = bfd_arch_powerpc; |
35cec841 | 2700 | bfd_default_set_arch_mach (&abfd, arch, 0); |
7a78ae4e | 2701 | info.bfd_arch_info = bfd_get_arch_info (&abfd); |
35cec841 | 2702 | mach = info.bfd_arch_info->mach; |
7a78ae4e ND |
2703 | } |
2704 | tdep = xmalloc (sizeof (struct gdbarch_tdep)); | |
2705 | tdep->wordsize = wordsize; | |
5bf1c677 EZ |
2706 | |
2707 | /* For e500 executables, the apuinfo section is of help here. Such | |
2708 | section contains the identifier and revision number of each | |
2709 | Application-specific Processing Unit that is present on the | |
2710 | chip. The content of the section is determined by the assembler | |
2711 | which looks at each instruction and determines which unit (and | |
2712 | which version of it) can execute it. In our case we just look for | |
2713 | the existance of the section. */ | |
2714 | ||
2715 | if (info.abfd) | |
2716 | { | |
2717 | sect = bfd_get_section_by_name (info.abfd, ".PPC.EMB.apuinfo"); | |
2718 | if (sect) | |
2719 | { | |
2720 | arch = info.bfd_arch_info->arch; | |
2721 | mach = bfd_mach_ppc_e500; | |
2722 | bfd_default_set_arch_mach (&abfd, arch, mach); | |
2723 | info.bfd_arch_info = bfd_get_arch_info (&abfd); | |
2724 | } | |
2725 | } | |
2726 | ||
7a78ae4e ND |
2727 | gdbarch = gdbarch_alloc (&info, tdep); |
2728 | power = arch == bfd_arch_rs6000; | |
2729 | ||
489461e2 EZ |
2730 | /* Initialize the number of real and pseudo registers in each variant. */ |
2731 | init_variants (); | |
2732 | ||
64366f1c | 2733 | /* Choose variant. */ |
7a78ae4e ND |
2734 | v = find_variant_by_arch (arch, mach); |
2735 | if (!v) | |
dd47e6fd EZ |
2736 | return NULL; |
2737 | ||
7a78ae4e ND |
2738 | tdep->regs = v->regs; |
2739 | ||
2188cbdd | 2740 | tdep->ppc_gp0_regnum = 0; |
2188cbdd EZ |
2741 | tdep->ppc_toc_regnum = 2; |
2742 | tdep->ppc_ps_regnum = 65; | |
2743 | tdep->ppc_cr_regnum = 66; | |
2744 | tdep->ppc_lr_regnum = 67; | |
2745 | tdep->ppc_ctr_regnum = 68; | |
2746 | tdep->ppc_xer_regnum = 69; | |
2747 | if (v->mach == bfd_mach_ppc_601) | |
2748 | tdep->ppc_mq_regnum = 124; | |
e3f36dbd | 2749 | else if (power) |
2188cbdd | 2750 | tdep->ppc_mq_regnum = 70; |
e3f36dbd KB |
2751 | else |
2752 | tdep->ppc_mq_regnum = -1; | |
366f009f | 2753 | tdep->ppc_fp0_regnum = 32; |
e3f36dbd | 2754 | tdep->ppc_fpscr_regnum = power ? 71 : 70; |
2188cbdd | 2755 | |
c8001721 EZ |
2756 | set_gdbarch_pc_regnum (gdbarch, 64); |
2757 | set_gdbarch_sp_regnum (gdbarch, 1); | |
0ba6dca9 | 2758 | set_gdbarch_deprecated_fp_regnum (gdbarch, 1); |
afd48b75 | 2759 | if (sysv_abi && wordsize == 8) |
05580c65 | 2760 | set_gdbarch_return_value (gdbarch, ppc64_sysv_abi_return_value); |
e754ae69 | 2761 | else if (sysv_abi && wordsize == 4) |
05580c65 | 2762 | set_gdbarch_return_value (gdbarch, ppc_sysv_abi_return_value); |
afd48b75 AC |
2763 | else |
2764 | { | |
2765 | set_gdbarch_deprecated_extract_return_value (gdbarch, rs6000_extract_return_value); | |
2766 | set_gdbarch_deprecated_store_return_value (gdbarch, rs6000_store_return_value); | |
2767 | } | |
c8001721 | 2768 | |
1fcc0bb8 EZ |
2769 | if (v->arch == bfd_arch_powerpc) |
2770 | switch (v->mach) | |
2771 | { | |
2772 | case bfd_mach_ppc: | |
2773 | tdep->ppc_vr0_regnum = 71; | |
2774 | tdep->ppc_vrsave_regnum = 104; | |
c8001721 EZ |
2775 | tdep->ppc_ev0_regnum = -1; |
2776 | tdep->ppc_ev31_regnum = -1; | |
1fcc0bb8 EZ |
2777 | break; |
2778 | case bfd_mach_ppc_7400: | |
2779 | tdep->ppc_vr0_regnum = 119; | |
54c2a1e6 | 2780 | tdep->ppc_vrsave_regnum = 152; |
c8001721 EZ |
2781 | tdep->ppc_ev0_regnum = -1; |
2782 | tdep->ppc_ev31_regnum = -1; | |
2783 | break; | |
2784 | case bfd_mach_ppc_e500: | |
338ef23d | 2785 | tdep->ppc_gp0_regnum = 41; |
c8001721 EZ |
2786 | tdep->ppc_toc_regnum = -1; |
2787 | tdep->ppc_ps_regnum = 1; | |
2788 | tdep->ppc_cr_regnum = 2; | |
2789 | tdep->ppc_lr_regnum = 3; | |
2790 | tdep->ppc_ctr_regnum = 4; | |
2791 | tdep->ppc_xer_regnum = 5; | |
2792 | tdep->ppc_ev0_regnum = 7; | |
2793 | tdep->ppc_ev31_regnum = 38; | |
383f0f5b JB |
2794 | tdep->ppc_fp0_regnum = -1; |
2795 | tdep->ppc_fpscr_regnum = -1; | |
c8001721 | 2796 | set_gdbarch_pc_regnum (gdbarch, 0); |
338ef23d | 2797 | set_gdbarch_sp_regnum (gdbarch, tdep->ppc_gp0_regnum + 1); |
0ba6dca9 | 2798 | set_gdbarch_deprecated_fp_regnum (gdbarch, tdep->ppc_gp0_regnum + 1); |
c8001721 EZ |
2799 | set_gdbarch_pseudo_register_read (gdbarch, e500_pseudo_register_read); |
2800 | set_gdbarch_pseudo_register_write (gdbarch, e500_pseudo_register_write); | |
1fcc0bb8 EZ |
2801 | break; |
2802 | default: | |
2803 | tdep->ppc_vr0_regnum = -1; | |
2804 | tdep->ppc_vrsave_regnum = -1; | |
c8001721 EZ |
2805 | tdep->ppc_ev0_regnum = -1; |
2806 | tdep->ppc_ev31_regnum = -1; | |
1fcc0bb8 EZ |
2807 | break; |
2808 | } | |
2809 | ||
338ef23d AC |
2810 | /* Sanity check on registers. */ |
2811 | gdb_assert (strcmp (tdep->regs[tdep->ppc_gp0_regnum].name, "r0") == 0); | |
2812 | ||
a88376a3 KB |
2813 | /* Set lr_frame_offset. */ |
2814 | if (wordsize == 8) | |
2815 | tdep->lr_frame_offset = 16; | |
2816 | else if (sysv_abi) | |
2817 | tdep->lr_frame_offset = 4; | |
2818 | else | |
2819 | tdep->lr_frame_offset = 8; | |
2820 | ||
2821 | /* Calculate byte offsets in raw register array. */ | |
489461e2 EZ |
2822 | tdep->regoff = xmalloc (v->num_tot_regs * sizeof (int)); |
2823 | for (i = off = 0; i < v->num_tot_regs; i++) | |
7a78ae4e ND |
2824 | { |
2825 | tdep->regoff[i] = off; | |
2826 | off += regsize (v->regs + i, wordsize); | |
c906108c SS |
2827 | } |
2828 | ||
56a6dfb9 KB |
2829 | /* Select instruction printer. */ |
2830 | if (arch == power) | |
9364a0ef | 2831 | set_gdbarch_print_insn (gdbarch, print_insn_rs6000); |
56a6dfb9 | 2832 | else |
9364a0ef | 2833 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_powerpc); |
7495d1dc | 2834 | |
7a78ae4e | 2835 | set_gdbarch_write_pc (gdbarch, generic_target_write_pc); |
7a78ae4e ND |
2836 | |
2837 | set_gdbarch_num_regs (gdbarch, v->nregs); | |
c8001721 | 2838 | set_gdbarch_num_pseudo_regs (gdbarch, v->npregs); |
7a78ae4e | 2839 | set_gdbarch_register_name (gdbarch, rs6000_register_name); |
b1e29e33 | 2840 | set_gdbarch_deprecated_register_size (gdbarch, wordsize); |
b8b527c5 | 2841 | set_gdbarch_deprecated_register_bytes (gdbarch, off); |
9c04cab7 AC |
2842 | set_gdbarch_deprecated_register_byte (gdbarch, rs6000_register_byte); |
2843 | set_gdbarch_deprecated_register_raw_size (gdbarch, rs6000_register_raw_size); | |
9c04cab7 | 2844 | set_gdbarch_deprecated_register_virtual_type (gdbarch, rs6000_register_virtual_type); |
7a78ae4e ND |
2845 | |
2846 | set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT); | |
2847 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); | |
2848 | set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
2849 | set_gdbarch_long_bit (gdbarch, wordsize * TARGET_CHAR_BIT); | |
2850 | set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
2851 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
2852 | set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
ab9fe00e KB |
2853 | if (sysv_abi) |
2854 | set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT); | |
2855 | else | |
2856 | set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
4e409299 | 2857 | set_gdbarch_char_signed (gdbarch, 0); |
7a78ae4e | 2858 | |
11269d7e | 2859 | set_gdbarch_frame_align (gdbarch, rs6000_frame_align); |
8b148df9 AC |
2860 | if (sysv_abi && wordsize == 8) |
2861 | /* PPC64 SYSV. */ | |
2862 | set_gdbarch_frame_red_zone_size (gdbarch, 288); | |
2863 | else if (!sysv_abi && wordsize == 4) | |
5bffac25 AC |
2864 | /* PowerOpen / AIX 32 bit. The saved area or red zone consists of |
2865 | 19 4 byte GPRS + 18 8 byte FPRs giving a total of 220 bytes. | |
2866 | Problem is, 220 isn't frame (16 byte) aligned. Round it up to | |
2867 | 224. */ | |
2868 | set_gdbarch_frame_red_zone_size (gdbarch, 224); | |
7a78ae4e | 2869 | |
781a750d AC |
2870 | set_gdbarch_deprecated_register_convertible (gdbarch, rs6000_register_convertible); |
2871 | set_gdbarch_deprecated_register_convert_to_virtual (gdbarch, rs6000_register_convert_to_virtual); | |
2872 | set_gdbarch_deprecated_register_convert_to_raw (gdbarch, rs6000_register_convert_to_raw); | |
9f744501 JB |
2873 | set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_dwarf2_stab_reg_to_regnum); |
2874 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rs6000_dwarf2_stab_reg_to_regnum); | |
2ea5f656 KB |
2875 | /* Note: kevinb/2002-04-12: I'm not convinced that rs6000_push_arguments() |
2876 | is correct for the SysV ABI when the wordsize is 8, but I'm also | |
2877 | fairly certain that ppc_sysv_abi_push_arguments() will give even | |
2878 | worse results since it only works for 32-bit code. So, for the moment, | |
2879 | we're better off calling rs6000_push_arguments() since it works for | |
2880 | 64-bit code. At some point in the future, this matter needs to be | |
2881 | revisited. */ | |
2882 | if (sysv_abi && wordsize == 4) | |
77b2b6d4 | 2883 | set_gdbarch_push_dummy_call (gdbarch, ppc_sysv_abi_push_dummy_call); |
8be9034a AC |
2884 | else if (sysv_abi && wordsize == 8) |
2885 | set_gdbarch_push_dummy_call (gdbarch, ppc64_sysv_abi_push_dummy_call); | |
9aa1e687 | 2886 | else |
77b2b6d4 | 2887 | set_gdbarch_push_dummy_call (gdbarch, rs6000_push_dummy_call); |
7a78ae4e | 2888 | |
74055713 | 2889 | set_gdbarch_deprecated_extract_struct_value_address (gdbarch, rs6000_extract_struct_value_address); |
7a78ae4e ND |
2890 | |
2891 | set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue); | |
2892 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
7a78ae4e ND |
2893 | set_gdbarch_breakpoint_from_pc (gdbarch, rs6000_breakpoint_from_pc); |
2894 | ||
6066c3de AC |
2895 | /* Handle the 64-bit SVR4 minimal-symbol convention of using "FN" |
2896 | for the descriptor and ".FN" for the entry-point -- a user | |
2897 | specifying "break FN" will unexpectedly end up with a breakpoint | |
2898 | on the descriptor and not the function. This architecture method | |
2899 | transforms any breakpoints on descriptors into breakpoints on the | |
2900 | corresponding entry point. */ | |
2901 | if (sysv_abi && wordsize == 8) | |
2902 | set_gdbarch_adjust_breakpoint_address (gdbarch, ppc64_sysv_abi_adjust_breakpoint_address); | |
2903 | ||
7a78ae4e ND |
2904 | /* Not sure on this. FIXMEmgo */ |
2905 | set_gdbarch_frame_args_skip (gdbarch, 8); | |
2906 | ||
05580c65 | 2907 | if (!sysv_abi) |
7b112f9c | 2908 | set_gdbarch_use_struct_convention (gdbarch, |
b9ff3018 | 2909 | rs6000_use_struct_convention); |
8e0662df | 2910 | |
15813d3f AC |
2911 | if (!sysv_abi) |
2912 | { | |
2913 | /* Handle RS/6000 function pointers (which are really function | |
2914 | descriptors). */ | |
f517ea4e PS |
2915 | set_gdbarch_convert_from_func_ptr_addr (gdbarch, |
2916 | rs6000_convert_from_func_ptr_addr); | |
9aa1e687 | 2917 | } |
7a78ae4e | 2918 | |
143985b7 AF |
2919 | /* Helpers for function argument information. */ |
2920 | set_gdbarch_fetch_pointer_argument (gdbarch, rs6000_fetch_pointer_argument); | |
2921 | ||
7b112f9c | 2922 | /* Hook in ABI-specific overrides, if they have been registered. */ |
4be87837 | 2923 | gdbarch_init_osabi (info, gdbarch); |
7b112f9c | 2924 | |
61a65099 KB |
2925 | switch (info.osabi) |
2926 | { | |
2927 | case GDB_OSABI_NETBSD_AOUT: | |
2928 | case GDB_OSABI_NETBSD_ELF: | |
2929 | case GDB_OSABI_UNKNOWN: | |
2930 | case GDB_OSABI_LINUX: | |
2931 | set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc); | |
2932 | frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer); | |
2933 | set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id); | |
2934 | frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer); | |
2935 | break; | |
2936 | default: | |
61a65099 | 2937 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); |
81332287 KB |
2938 | |
2939 | set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc); | |
2940 | frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer); | |
2941 | set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id); | |
2942 | frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer); | |
61a65099 KB |
2943 | } |
2944 | ||
ef5200c1 AC |
2945 | if (from_xcoff_exec) |
2946 | { | |
2947 | /* NOTE: jimix/2003-06-09: This test should really check for | |
2948 | GDB_OSABI_AIX when that is defined and becomes | |
2949 | available. (Actually, once things are properly split apart, | |
2950 | the test goes away.) */ | |
2951 | /* RS6000/AIX does not support PT_STEP. Has to be simulated. */ | |
2952 | set_gdbarch_software_single_step (gdbarch, rs6000_software_single_step); | |
2953 | } | |
2954 | ||
7a78ae4e | 2955 | return gdbarch; |
c906108c SS |
2956 | } |
2957 | ||
7b112f9c JT |
2958 | static void |
2959 | rs6000_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
2960 | { | |
2961 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2962 | ||
2963 | if (tdep == NULL) | |
2964 | return; | |
2965 | ||
4be87837 | 2966 | /* FIXME: Dump gdbarch_tdep. */ |
7b112f9c JT |
2967 | } |
2968 | ||
1fcc0bb8 EZ |
2969 | static struct cmd_list_element *info_powerpc_cmdlist = NULL; |
2970 | ||
2971 | static void | |
2972 | rs6000_info_powerpc_command (char *args, int from_tty) | |
2973 | { | |
2974 | help_list (info_powerpc_cmdlist, "info powerpc ", class_info, gdb_stdout); | |
2975 | } | |
2976 | ||
c906108c SS |
2977 | /* Initialization code. */ |
2978 | ||
a78f21af | 2979 | extern initialize_file_ftype _initialize_rs6000_tdep; /* -Wmissing-prototypes */ |
b9362cc7 | 2980 | |
c906108c | 2981 | void |
fba45db2 | 2982 | _initialize_rs6000_tdep (void) |
c906108c | 2983 | { |
7b112f9c JT |
2984 | gdbarch_register (bfd_arch_rs6000, rs6000_gdbarch_init, rs6000_dump_tdep); |
2985 | gdbarch_register (bfd_arch_powerpc, rs6000_gdbarch_init, rs6000_dump_tdep); | |
1fcc0bb8 EZ |
2986 | |
2987 | /* Add root prefix command for "info powerpc" commands */ | |
2988 | add_prefix_cmd ("powerpc", class_info, rs6000_info_powerpc_command, | |
2989 | "Various POWERPC info specific commands.", | |
2990 | &info_powerpc_cmdlist, "info powerpc ", 0, &infolist); | |
c906108c | 2991 | } |