Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for GDB, the GNU debugger. |
7aea86e6 | 2 | |
61baf725 | 3 | Copyright (C) 1986-2017 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 10 | (at your option) any later version. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b | 17 | You should have received a copy of the GNU General Public License |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
19 | |
20 | #include "defs.h" | |
21 | #include "frame.h" | |
22 | #include "inferior.h" | |
45741a9c | 23 | #include "infrun.h" |
c906108c SS |
24 | #include "symtab.h" |
25 | #include "target.h" | |
26 | #include "gdbcore.h" | |
27 | #include "gdbcmd.h" | |
c906108c | 28 | #include "objfiles.h" |
7a78ae4e | 29 | #include "arch-utils.h" |
4e052eda | 30 | #include "regcache.h" |
d195bc9f | 31 | #include "regset.h" |
3b2ca824 | 32 | #include "target-float.h" |
fd0407d6 | 33 | #include "value.h" |
1fcc0bb8 | 34 | #include "parser-defs.h" |
4be87837 | 35 | #include "osabi.h" |
7d9b040b | 36 | #include "infcall.h" |
9f643768 JB |
37 | #include "sim-regno.h" |
38 | #include "gdb/sim-ppc.h" | |
6ced10dd | 39 | #include "reggroups.h" |
4fc771b8 | 40 | #include "dwarf2-frame.h" |
7cc46491 DJ |
41 | #include "target-descriptions.h" |
42 | #include "user-regs.h" | |
b4cdae6f WW |
43 | #include "record-full.h" |
44 | #include "auxv.h" | |
7a78ae4e | 45 | |
7a78ae4e | 46 | #include "coff/internal.h" /* for libcoff.h */ |
2fccf04a | 47 | #include "libcoff.h" /* for xcoff_data */ |
11ed25ac KB |
48 | #include "coff/xcoff.h" |
49 | #include "libxcoff.h" | |
7a78ae4e | 50 | |
9aa1e687 | 51 | #include "elf-bfd.h" |
55eddb0f | 52 | #include "elf/ppc.h" |
cd453cd0 | 53 | #include "elf/ppc64.h" |
7a78ae4e | 54 | |
6ded7999 | 55 | #include "solib-svr4.h" |
9aa1e687 | 56 | #include "ppc-tdep.h" |
debb1f09 | 57 | #include "ppc-ravenscar-thread.h" |
7a78ae4e | 58 | |
a89aa300 | 59 | #include "dis-asm.h" |
338ef23d | 60 | |
61a65099 KB |
61 | #include "trad-frame.h" |
62 | #include "frame-unwind.h" | |
63 | #include "frame-base.h" | |
64 | ||
a67914de MK |
65 | #include "ax.h" |
66 | #include "ax-gdb.h" | |
325fac50 | 67 | #include <algorithm> |
a67914de | 68 | |
7cc46491 | 69 | #include "features/rs6000/powerpc-32.c" |
7284e1be | 70 | #include "features/rs6000/powerpc-altivec32.c" |
604c2f83 | 71 | #include "features/rs6000/powerpc-vsx32.c" |
7cc46491 DJ |
72 | #include "features/rs6000/powerpc-403.c" |
73 | #include "features/rs6000/powerpc-403gc.c" | |
4d09ffea | 74 | #include "features/rs6000/powerpc-405.c" |
7cc46491 DJ |
75 | #include "features/rs6000/powerpc-505.c" |
76 | #include "features/rs6000/powerpc-601.c" | |
77 | #include "features/rs6000/powerpc-602.c" | |
78 | #include "features/rs6000/powerpc-603.c" | |
79 | #include "features/rs6000/powerpc-604.c" | |
80 | #include "features/rs6000/powerpc-64.c" | |
7284e1be | 81 | #include "features/rs6000/powerpc-altivec64.c" |
604c2f83 | 82 | #include "features/rs6000/powerpc-vsx64.c" |
7cc46491 DJ |
83 | #include "features/rs6000/powerpc-7400.c" |
84 | #include "features/rs6000/powerpc-750.c" | |
85 | #include "features/rs6000/powerpc-860.c" | |
86 | #include "features/rs6000/powerpc-e500.c" | |
87 | #include "features/rs6000/rs6000.c" | |
88 | ||
5a9e69ba TJB |
89 | /* Determine if regnum is an SPE pseudo-register. */ |
90 | #define IS_SPE_PSEUDOREG(tdep, regnum) ((tdep)->ppc_ev0_regnum >= 0 \ | |
91 | && (regnum) >= (tdep)->ppc_ev0_regnum \ | |
92 | && (regnum) < (tdep)->ppc_ev0_regnum + 32) | |
93 | ||
f949c649 TJB |
94 | /* Determine if regnum is a decimal float pseudo-register. */ |
95 | #define IS_DFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_dl0_regnum >= 0 \ | |
96 | && (regnum) >= (tdep)->ppc_dl0_regnum \ | |
97 | && (regnum) < (tdep)->ppc_dl0_regnum + 16) | |
98 | ||
604c2f83 LM |
99 | /* Determine if regnum is a POWER7 VSX register. */ |
100 | #define IS_VSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_vsr0_regnum >= 0 \ | |
101 | && (regnum) >= (tdep)->ppc_vsr0_regnum \ | |
102 | && (regnum) < (tdep)->ppc_vsr0_regnum + ppc_num_vsrs) | |
103 | ||
104 | /* Determine if regnum is a POWER7 Extended FP register. */ | |
105 | #define IS_EFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_efpr0_regnum >= 0 \ | |
106 | && (regnum) >= (tdep)->ppc_efpr0_regnum \ | |
d9492458 | 107 | && (regnum) < (tdep)->ppc_efpr0_regnum + ppc_num_efprs) |
604c2f83 | 108 | |
65b48a81 PB |
109 | /* Holds the current set of options to be passed to the disassembler. */ |
110 | static char *powerpc_disassembler_options; | |
111 | ||
55eddb0f DJ |
112 | /* The list of available "set powerpc ..." and "show powerpc ..." |
113 | commands. */ | |
114 | static struct cmd_list_element *setpowerpccmdlist = NULL; | |
115 | static struct cmd_list_element *showpowerpccmdlist = NULL; | |
116 | ||
117 | static enum auto_boolean powerpc_soft_float_global = AUTO_BOOLEAN_AUTO; | |
118 | ||
119 | /* The vector ABI to use. Keep this in sync with powerpc_vector_abi. */ | |
40478521 | 120 | static const char *const powerpc_vector_strings[] = |
55eddb0f DJ |
121 | { |
122 | "auto", | |
123 | "generic", | |
124 | "altivec", | |
125 | "spe", | |
126 | NULL | |
127 | }; | |
128 | ||
129 | /* A variable that can be configured by the user. */ | |
130 | static enum powerpc_vector_abi powerpc_vector_abi_global = POWERPC_VEC_AUTO; | |
131 | static const char *powerpc_vector_abi_string = "auto"; | |
132 | ||
0df8b418 | 133 | /* To be used by skip_prologue. */ |
7a78ae4e ND |
134 | |
135 | struct rs6000_framedata | |
136 | { | |
137 | int offset; /* total size of frame --- the distance | |
138 | by which we decrement sp to allocate | |
139 | the frame */ | |
140 | int saved_gpr; /* smallest # of saved gpr */ | |
46a9b8ed | 141 | unsigned int gpr_mask; /* Each bit is an individual saved GPR. */ |
7a78ae4e | 142 | int saved_fpr; /* smallest # of saved fpr */ |
6be8bc0c | 143 | int saved_vr; /* smallest # of saved vr */ |
96ff0de4 | 144 | int saved_ev; /* smallest # of saved ev */ |
7a78ae4e | 145 | int alloca_reg; /* alloca register number (frame ptr) */ |
0df8b418 MS |
146 | char frameless; /* true if frameless functions. */ |
147 | char nosavedpc; /* true if pc not saved. */ | |
46a9b8ed | 148 | char used_bl; /* true if link register clobbered */ |
7a78ae4e ND |
149 | int gpr_offset; /* offset of saved gprs from prev sp */ |
150 | int fpr_offset; /* offset of saved fprs from prev sp */ | |
6be8bc0c | 151 | int vr_offset; /* offset of saved vrs from prev sp */ |
96ff0de4 | 152 | int ev_offset; /* offset of saved evs from prev sp */ |
7a78ae4e | 153 | int lr_offset; /* offset of saved lr */ |
46a9b8ed | 154 | int lr_register; /* register of saved lr, if trustworthy */ |
7a78ae4e | 155 | int cr_offset; /* offset of saved cr */ |
6be8bc0c | 156 | int vrsave_offset; /* offset of saved vrsave register */ |
7a78ae4e ND |
157 | }; |
158 | ||
c906108c | 159 | |
604c2f83 LM |
160 | /* Is REGNO a VSX register? Return 1 if so, 0 otherwise. */ |
161 | int | |
162 | vsx_register_p (struct gdbarch *gdbarch, int regno) | |
163 | { | |
164 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
165 | if (tdep->ppc_vsr0_regnum < 0) | |
166 | return 0; | |
167 | else | |
168 | return (regno >= tdep->ppc_vsr0_upper_regnum && regno | |
169 | <= tdep->ppc_vsr0_upper_regnum + 31); | |
170 | } | |
171 | ||
64b84175 KB |
172 | /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */ |
173 | int | |
be8626e0 | 174 | altivec_register_p (struct gdbarch *gdbarch, int regno) |
64b84175 | 175 | { |
be8626e0 | 176 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
64b84175 KB |
177 | if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0) |
178 | return 0; | |
179 | else | |
180 | return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum); | |
181 | } | |
182 | ||
383f0f5b | 183 | |
867e2dc5 JB |
184 | /* Return true if REGNO is an SPE register, false otherwise. */ |
185 | int | |
be8626e0 | 186 | spe_register_p (struct gdbarch *gdbarch, int regno) |
867e2dc5 | 187 | { |
be8626e0 | 188 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
867e2dc5 JB |
189 | |
190 | /* Is it a reference to EV0 -- EV31, and do we have those? */ | |
5a9e69ba | 191 | if (IS_SPE_PSEUDOREG (tdep, regno)) |
867e2dc5 JB |
192 | return 1; |
193 | ||
6ced10dd JB |
194 | /* Is it a reference to one of the raw upper GPR halves? */ |
195 | if (tdep->ppc_ev0_upper_regnum >= 0 | |
196 | && tdep->ppc_ev0_upper_regnum <= regno | |
197 | && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) | |
198 | return 1; | |
199 | ||
867e2dc5 JB |
200 | /* Is it a reference to the 64-bit accumulator, and do we have that? */ |
201 | if (tdep->ppc_acc_regnum >= 0 | |
202 | && tdep->ppc_acc_regnum == regno) | |
203 | return 1; | |
204 | ||
205 | /* Is it a reference to the SPE floating-point status and control register, | |
206 | and do we have that? */ | |
207 | if (tdep->ppc_spefscr_regnum >= 0 | |
208 | && tdep->ppc_spefscr_regnum == regno) | |
209 | return 1; | |
210 | ||
211 | return 0; | |
212 | } | |
213 | ||
214 | ||
383f0f5b JB |
215 | /* Return non-zero if the architecture described by GDBARCH has |
216 | floating-point registers (f0 --- f31 and fpscr). */ | |
0a613259 AC |
217 | int |
218 | ppc_floating_point_unit_p (struct gdbarch *gdbarch) | |
219 | { | |
383f0f5b JB |
220 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
221 | ||
222 | return (tdep->ppc_fp0_regnum >= 0 | |
223 | && tdep->ppc_fpscr_regnum >= 0); | |
0a613259 | 224 | } |
9f643768 | 225 | |
604c2f83 LM |
226 | /* Return non-zero if the architecture described by GDBARCH has |
227 | VSX registers (vsr0 --- vsr63). */ | |
63807e1d | 228 | static int |
604c2f83 LM |
229 | ppc_vsx_support_p (struct gdbarch *gdbarch) |
230 | { | |
231 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
232 | ||
233 | return tdep->ppc_vsr0_regnum >= 0; | |
234 | } | |
235 | ||
06caf7d2 CES |
236 | /* Return non-zero if the architecture described by GDBARCH has |
237 | Altivec registers (vr0 --- vr31, vrsave and vscr). */ | |
238 | int | |
239 | ppc_altivec_support_p (struct gdbarch *gdbarch) | |
240 | { | |
241 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
242 | ||
243 | return (tdep->ppc_vr0_regnum >= 0 | |
244 | && tdep->ppc_vrsave_regnum >= 0); | |
245 | } | |
09991fa0 JB |
246 | |
247 | /* Check that TABLE[GDB_REGNO] is not already initialized, and then | |
248 | set it to SIM_REGNO. | |
249 | ||
250 | This is a helper function for init_sim_regno_table, constructing | |
251 | the table mapping GDB register numbers to sim register numbers; we | |
252 | initialize every element in that table to -1 before we start | |
253 | filling it in. */ | |
9f643768 JB |
254 | static void |
255 | set_sim_regno (int *table, int gdb_regno, int sim_regno) | |
256 | { | |
257 | /* Make sure we don't try to assign any given GDB register a sim | |
258 | register number more than once. */ | |
259 | gdb_assert (table[gdb_regno] == -1); | |
260 | table[gdb_regno] = sim_regno; | |
261 | } | |
262 | ||
09991fa0 JB |
263 | |
264 | /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register | |
265 | numbers to simulator register numbers, based on the values placed | |
266 | in the ARCH->tdep->ppc_foo_regnum members. */ | |
9f643768 JB |
267 | static void |
268 | init_sim_regno_table (struct gdbarch *arch) | |
269 | { | |
270 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); | |
7cc46491 | 271 | int total_regs = gdbarch_num_regs (arch); |
9f643768 JB |
272 | int *sim_regno = GDBARCH_OBSTACK_CALLOC (arch, total_regs, int); |
273 | int i; | |
7cc46491 DJ |
274 | static const char *const segment_regs[] = { |
275 | "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7", | |
276 | "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15" | |
277 | }; | |
9f643768 JB |
278 | |
279 | /* Presume that all registers not explicitly mentioned below are | |
280 | unavailable from the sim. */ | |
281 | for (i = 0; i < total_regs; i++) | |
282 | sim_regno[i] = -1; | |
283 | ||
284 | /* General-purpose registers. */ | |
285 | for (i = 0; i < ppc_num_gprs; i++) | |
286 | set_sim_regno (sim_regno, tdep->ppc_gp0_regnum + i, sim_ppc_r0_regnum + i); | |
287 | ||
288 | /* Floating-point registers. */ | |
289 | if (tdep->ppc_fp0_regnum >= 0) | |
290 | for (i = 0; i < ppc_num_fprs; i++) | |
291 | set_sim_regno (sim_regno, | |
292 | tdep->ppc_fp0_regnum + i, | |
293 | sim_ppc_f0_regnum + i); | |
294 | if (tdep->ppc_fpscr_regnum >= 0) | |
295 | set_sim_regno (sim_regno, tdep->ppc_fpscr_regnum, sim_ppc_fpscr_regnum); | |
296 | ||
297 | set_sim_regno (sim_regno, gdbarch_pc_regnum (arch), sim_ppc_pc_regnum); | |
298 | set_sim_regno (sim_regno, tdep->ppc_ps_regnum, sim_ppc_ps_regnum); | |
299 | set_sim_regno (sim_regno, tdep->ppc_cr_regnum, sim_ppc_cr_regnum); | |
300 | ||
301 | /* Segment registers. */ | |
7cc46491 DJ |
302 | for (i = 0; i < ppc_num_srs; i++) |
303 | { | |
304 | int gdb_regno; | |
305 | ||
306 | gdb_regno = user_reg_map_name_to_regnum (arch, segment_regs[i], -1); | |
307 | if (gdb_regno >= 0) | |
308 | set_sim_regno (sim_regno, gdb_regno, sim_ppc_sr0_regnum + i); | |
309 | } | |
9f643768 JB |
310 | |
311 | /* Altivec registers. */ | |
312 | if (tdep->ppc_vr0_regnum >= 0) | |
313 | { | |
314 | for (i = 0; i < ppc_num_vrs; i++) | |
315 | set_sim_regno (sim_regno, | |
316 | tdep->ppc_vr0_regnum + i, | |
317 | sim_ppc_vr0_regnum + i); | |
318 | ||
319 | /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum, | |
320 | we can treat this more like the other cases. */ | |
321 | set_sim_regno (sim_regno, | |
322 | tdep->ppc_vr0_regnum + ppc_num_vrs, | |
323 | sim_ppc_vscr_regnum); | |
324 | } | |
325 | /* vsave is a special-purpose register, so the code below handles it. */ | |
326 | ||
327 | /* SPE APU (E500) registers. */ | |
6ced10dd JB |
328 | if (tdep->ppc_ev0_upper_regnum >= 0) |
329 | for (i = 0; i < ppc_num_gprs; i++) | |
330 | set_sim_regno (sim_regno, | |
331 | tdep->ppc_ev0_upper_regnum + i, | |
332 | sim_ppc_rh0_regnum + i); | |
9f643768 JB |
333 | if (tdep->ppc_acc_regnum >= 0) |
334 | set_sim_regno (sim_regno, tdep->ppc_acc_regnum, sim_ppc_acc_regnum); | |
335 | /* spefscr is a special-purpose register, so the code below handles it. */ | |
336 | ||
976102cd | 337 | #ifdef WITH_PPC_SIM |
9f643768 JB |
338 | /* Now handle all special-purpose registers. Verify that they |
339 | haven't mistakenly been assigned numbers by any of the above | |
7cc46491 DJ |
340 | code. */ |
341 | for (i = 0; i < sim_ppc_num_sprs; i++) | |
342 | { | |
343 | const char *spr_name = sim_spr_register_name (i); | |
344 | int gdb_regno = -1; | |
345 | ||
346 | if (spr_name != NULL) | |
347 | gdb_regno = user_reg_map_name_to_regnum (arch, spr_name, -1); | |
348 | ||
349 | if (gdb_regno != -1) | |
350 | set_sim_regno (sim_regno, gdb_regno, sim_ppc_spr0_regnum + i); | |
351 | } | |
352 | #endif | |
9f643768 JB |
353 | |
354 | /* Drop the initialized array into place. */ | |
355 | tdep->sim_regno = sim_regno; | |
356 | } | |
357 | ||
09991fa0 JB |
358 | |
359 | /* Given a GDB register number REG, return the corresponding SIM | |
360 | register number. */ | |
9f643768 | 361 | static int |
e7faf938 | 362 | rs6000_register_sim_regno (struct gdbarch *gdbarch, int reg) |
9f643768 | 363 | { |
e7faf938 | 364 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
9f643768 JB |
365 | int sim_regno; |
366 | ||
7cc46491 | 367 | if (tdep->sim_regno == NULL) |
e7faf938 | 368 | init_sim_regno_table (gdbarch); |
7cc46491 | 369 | |
f57d151a | 370 | gdb_assert (0 <= reg |
e7faf938 MD |
371 | && reg <= gdbarch_num_regs (gdbarch) |
372 | + gdbarch_num_pseudo_regs (gdbarch)); | |
9f643768 JB |
373 | sim_regno = tdep->sim_regno[reg]; |
374 | ||
375 | if (sim_regno >= 0) | |
376 | return sim_regno; | |
377 | else | |
378 | return LEGACY_SIM_REGNO_IGNORE; | |
379 | } | |
380 | ||
d195bc9f MK |
381 | \f |
382 | ||
383 | /* Register set support functions. */ | |
384 | ||
f2db237a AM |
385 | /* REGS + OFFSET contains register REGNUM in a field REGSIZE wide. |
386 | Write the register to REGCACHE. */ | |
387 | ||
7284e1be | 388 | void |
d195bc9f | 389 | ppc_supply_reg (struct regcache *regcache, int regnum, |
f2db237a | 390 | const gdb_byte *regs, size_t offset, int regsize) |
d195bc9f MK |
391 | { |
392 | if (regnum != -1 && offset != -1) | |
f2db237a AM |
393 | { |
394 | if (regsize > 4) | |
395 | { | |
ac7936df | 396 | struct gdbarch *gdbarch = regcache->arch (); |
f2db237a AM |
397 | int gdb_regsize = register_size (gdbarch, regnum); |
398 | if (gdb_regsize < regsize | |
399 | && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
400 | offset += regsize - gdb_regsize; | |
401 | } | |
402 | regcache_raw_supply (regcache, regnum, regs + offset); | |
403 | } | |
d195bc9f MK |
404 | } |
405 | ||
f2db237a AM |
406 | /* Read register REGNUM from REGCACHE and store to REGS + OFFSET |
407 | in a field REGSIZE wide. Zero pad as necessary. */ | |
408 | ||
7284e1be | 409 | void |
d195bc9f | 410 | ppc_collect_reg (const struct regcache *regcache, int regnum, |
f2db237a | 411 | gdb_byte *regs, size_t offset, int regsize) |
d195bc9f MK |
412 | { |
413 | if (regnum != -1 && offset != -1) | |
f2db237a AM |
414 | { |
415 | if (regsize > 4) | |
416 | { | |
ac7936df | 417 | struct gdbarch *gdbarch = regcache->arch (); |
f2db237a AM |
418 | int gdb_regsize = register_size (gdbarch, regnum); |
419 | if (gdb_regsize < regsize) | |
420 | { | |
421 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
422 | { | |
423 | memset (regs + offset, 0, regsize - gdb_regsize); | |
424 | offset += regsize - gdb_regsize; | |
425 | } | |
426 | else | |
427 | memset (regs + offset + regsize - gdb_regsize, 0, | |
428 | regsize - gdb_regsize); | |
429 | } | |
430 | } | |
431 | regcache_raw_collect (regcache, regnum, regs + offset); | |
432 | } | |
d195bc9f MK |
433 | } |
434 | ||
f2db237a AM |
435 | static int |
436 | ppc_greg_offset (struct gdbarch *gdbarch, | |
437 | struct gdbarch_tdep *tdep, | |
438 | const struct ppc_reg_offsets *offsets, | |
439 | int regnum, | |
440 | int *regsize) | |
441 | { | |
442 | *regsize = offsets->gpr_size; | |
443 | if (regnum >= tdep->ppc_gp0_regnum | |
444 | && regnum < tdep->ppc_gp0_regnum + ppc_num_gprs) | |
445 | return (offsets->r0_offset | |
446 | + (regnum - tdep->ppc_gp0_regnum) * offsets->gpr_size); | |
447 | ||
448 | if (regnum == gdbarch_pc_regnum (gdbarch)) | |
449 | return offsets->pc_offset; | |
450 | ||
451 | if (regnum == tdep->ppc_ps_regnum) | |
452 | return offsets->ps_offset; | |
453 | ||
454 | if (regnum == tdep->ppc_lr_regnum) | |
455 | return offsets->lr_offset; | |
456 | ||
457 | if (regnum == tdep->ppc_ctr_regnum) | |
458 | return offsets->ctr_offset; | |
459 | ||
460 | *regsize = offsets->xr_size; | |
461 | if (regnum == tdep->ppc_cr_regnum) | |
462 | return offsets->cr_offset; | |
463 | ||
464 | if (regnum == tdep->ppc_xer_regnum) | |
465 | return offsets->xer_offset; | |
466 | ||
467 | if (regnum == tdep->ppc_mq_regnum) | |
468 | return offsets->mq_offset; | |
469 | ||
470 | return -1; | |
471 | } | |
472 | ||
473 | static int | |
474 | ppc_fpreg_offset (struct gdbarch_tdep *tdep, | |
475 | const struct ppc_reg_offsets *offsets, | |
476 | int regnum) | |
477 | { | |
478 | if (regnum >= tdep->ppc_fp0_regnum | |
479 | && regnum < tdep->ppc_fp0_regnum + ppc_num_fprs) | |
480 | return offsets->f0_offset + (regnum - tdep->ppc_fp0_regnum) * 8; | |
481 | ||
482 | if (regnum == tdep->ppc_fpscr_regnum) | |
483 | return offsets->fpscr_offset; | |
484 | ||
485 | return -1; | |
486 | } | |
487 | ||
06caf7d2 CES |
488 | static int |
489 | ppc_vrreg_offset (struct gdbarch_tdep *tdep, | |
490 | const struct ppc_reg_offsets *offsets, | |
491 | int regnum) | |
492 | { | |
493 | if (regnum >= tdep->ppc_vr0_regnum | |
494 | && regnum < tdep->ppc_vr0_regnum + ppc_num_vrs) | |
495 | return offsets->vr0_offset + (regnum - tdep->ppc_vr0_regnum) * 16; | |
496 | ||
497 | if (regnum == tdep->ppc_vrsave_regnum - 1) | |
498 | return offsets->vscr_offset; | |
499 | ||
500 | if (regnum == tdep->ppc_vrsave_regnum) | |
501 | return offsets->vrsave_offset; | |
502 | ||
503 | return -1; | |
504 | } | |
505 | ||
d195bc9f MK |
506 | /* Supply register REGNUM in the general-purpose register set REGSET |
507 | from the buffer specified by GREGS and LEN to register cache | |
508 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
509 | ||
510 | void | |
511 | ppc_supply_gregset (const struct regset *regset, struct regcache *regcache, | |
512 | int regnum, const void *gregs, size_t len) | |
513 | { | |
ac7936df | 514 | struct gdbarch *gdbarch = regcache->arch (); |
d195bc9f | 515 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
19ba03f4 SM |
516 | const struct ppc_reg_offsets *offsets |
517 | = (const struct ppc_reg_offsets *) regset->regmap; | |
d195bc9f | 518 | size_t offset; |
f2db237a | 519 | int regsize; |
d195bc9f | 520 | |
f2db237a | 521 | if (regnum == -1) |
d195bc9f | 522 | { |
f2db237a AM |
523 | int i; |
524 | int gpr_size = offsets->gpr_size; | |
525 | ||
526 | for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset; | |
527 | i < tdep->ppc_gp0_regnum + ppc_num_gprs; | |
528 | i++, offset += gpr_size) | |
19ba03f4 SM |
529 | ppc_supply_reg (regcache, i, (const gdb_byte *) gregs, offset, |
530 | gpr_size); | |
f2db237a AM |
531 | |
532 | ppc_supply_reg (regcache, gdbarch_pc_regnum (gdbarch), | |
19ba03f4 | 533 | (const gdb_byte *) gregs, offsets->pc_offset, gpr_size); |
f2db237a | 534 | ppc_supply_reg (regcache, tdep->ppc_ps_regnum, |
19ba03f4 | 535 | (const gdb_byte *) gregs, offsets->ps_offset, gpr_size); |
f2db237a | 536 | ppc_supply_reg (regcache, tdep->ppc_lr_regnum, |
19ba03f4 | 537 | (const gdb_byte *) gregs, offsets->lr_offset, gpr_size); |
f2db237a | 538 | ppc_supply_reg (regcache, tdep->ppc_ctr_regnum, |
19ba03f4 | 539 | (const gdb_byte *) gregs, offsets->ctr_offset, gpr_size); |
f2db237a | 540 | ppc_supply_reg (regcache, tdep->ppc_cr_regnum, |
19ba03f4 SM |
541 | (const gdb_byte *) gregs, offsets->cr_offset, |
542 | offsets->xr_size); | |
f2db237a | 543 | ppc_supply_reg (regcache, tdep->ppc_xer_regnum, |
19ba03f4 SM |
544 | (const gdb_byte *) gregs, offsets->xer_offset, |
545 | offsets->xr_size); | |
f2db237a | 546 | ppc_supply_reg (regcache, tdep->ppc_mq_regnum, |
19ba03f4 SM |
547 | (const gdb_byte *) gregs, offsets->mq_offset, |
548 | offsets->xr_size); | |
f2db237a | 549 | return; |
d195bc9f MK |
550 | } |
551 | ||
f2db237a | 552 | offset = ppc_greg_offset (gdbarch, tdep, offsets, regnum, ®size); |
19ba03f4 | 553 | ppc_supply_reg (regcache, regnum, (const gdb_byte *) gregs, offset, regsize); |
d195bc9f MK |
554 | } |
555 | ||
556 | /* Supply register REGNUM in the floating-point register set REGSET | |
557 | from the buffer specified by FPREGS and LEN to register cache | |
558 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
559 | ||
560 | void | |
561 | ppc_supply_fpregset (const struct regset *regset, struct regcache *regcache, | |
562 | int regnum, const void *fpregs, size_t len) | |
563 | { | |
ac7936df | 564 | struct gdbarch *gdbarch = regcache->arch (); |
f2db237a AM |
565 | struct gdbarch_tdep *tdep; |
566 | const struct ppc_reg_offsets *offsets; | |
d195bc9f | 567 | size_t offset; |
d195bc9f | 568 | |
f2db237a AM |
569 | if (!ppc_floating_point_unit_p (gdbarch)) |
570 | return; | |
383f0f5b | 571 | |
f2db237a | 572 | tdep = gdbarch_tdep (gdbarch); |
19ba03f4 | 573 | offsets = (const struct ppc_reg_offsets *) regset->regmap; |
f2db237a | 574 | if (regnum == -1) |
d195bc9f | 575 | { |
f2db237a AM |
576 | int i; |
577 | ||
578 | for (i = tdep->ppc_fp0_regnum, offset = offsets->f0_offset; | |
579 | i < tdep->ppc_fp0_regnum + ppc_num_fprs; | |
580 | i++, offset += 8) | |
19ba03f4 | 581 | ppc_supply_reg (regcache, i, (const gdb_byte *) fpregs, offset, 8); |
f2db237a AM |
582 | |
583 | ppc_supply_reg (regcache, tdep->ppc_fpscr_regnum, | |
19ba03f4 SM |
584 | (const gdb_byte *) fpregs, offsets->fpscr_offset, |
585 | offsets->fpscr_size); | |
f2db237a | 586 | return; |
d195bc9f MK |
587 | } |
588 | ||
f2db237a | 589 | offset = ppc_fpreg_offset (tdep, offsets, regnum); |
19ba03f4 | 590 | ppc_supply_reg (regcache, regnum, (const gdb_byte *) fpregs, offset, |
f2db237a | 591 | regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8); |
d195bc9f MK |
592 | } |
593 | ||
604c2f83 LM |
594 | /* Supply register REGNUM in the VSX register set REGSET |
595 | from the buffer specified by VSXREGS and LEN to register cache | |
596 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
597 | ||
598 | void | |
599 | ppc_supply_vsxregset (const struct regset *regset, struct regcache *regcache, | |
600 | int regnum, const void *vsxregs, size_t len) | |
601 | { | |
ac7936df | 602 | struct gdbarch *gdbarch = regcache->arch (); |
604c2f83 LM |
603 | struct gdbarch_tdep *tdep; |
604 | ||
605 | if (!ppc_vsx_support_p (gdbarch)) | |
606 | return; | |
607 | ||
608 | tdep = gdbarch_tdep (gdbarch); | |
609 | ||
610 | if (regnum == -1) | |
611 | { | |
612 | int i; | |
613 | ||
614 | for (i = tdep->ppc_vsr0_upper_regnum; | |
615 | i < tdep->ppc_vsr0_upper_regnum + 32; | |
616 | i++) | |
19ba03f4 | 617 | ppc_supply_reg (regcache, i, (const gdb_byte *) vsxregs, 0, 8); |
604c2f83 LM |
618 | |
619 | return; | |
620 | } | |
621 | else | |
19ba03f4 | 622 | ppc_supply_reg (regcache, regnum, (const gdb_byte *) vsxregs, 0, 8); |
604c2f83 LM |
623 | } |
624 | ||
06caf7d2 CES |
625 | /* Supply register REGNUM in the Altivec register set REGSET |
626 | from the buffer specified by VRREGS and LEN to register cache | |
627 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
628 | ||
629 | void | |
630 | ppc_supply_vrregset (const struct regset *regset, struct regcache *regcache, | |
631 | int regnum, const void *vrregs, size_t len) | |
632 | { | |
ac7936df | 633 | struct gdbarch *gdbarch = regcache->arch (); |
06caf7d2 CES |
634 | struct gdbarch_tdep *tdep; |
635 | const struct ppc_reg_offsets *offsets; | |
636 | size_t offset; | |
637 | ||
638 | if (!ppc_altivec_support_p (gdbarch)) | |
639 | return; | |
640 | ||
641 | tdep = gdbarch_tdep (gdbarch); | |
19ba03f4 | 642 | offsets = (const struct ppc_reg_offsets *) regset->regmap; |
06caf7d2 CES |
643 | if (regnum == -1) |
644 | { | |
645 | int i; | |
646 | ||
647 | for (i = tdep->ppc_vr0_regnum, offset = offsets->vr0_offset; | |
648 | i < tdep->ppc_vr0_regnum + ppc_num_vrs; | |
649 | i++, offset += 16) | |
19ba03f4 | 650 | ppc_supply_reg (regcache, i, (const gdb_byte *) vrregs, offset, 16); |
06caf7d2 CES |
651 | |
652 | ppc_supply_reg (regcache, (tdep->ppc_vrsave_regnum - 1), | |
19ba03f4 | 653 | (const gdb_byte *) vrregs, offsets->vscr_offset, 4); |
06caf7d2 CES |
654 | |
655 | ppc_supply_reg (regcache, tdep->ppc_vrsave_regnum, | |
19ba03f4 | 656 | (const gdb_byte *) vrregs, offsets->vrsave_offset, 4); |
06caf7d2 CES |
657 | return; |
658 | } | |
659 | ||
660 | offset = ppc_vrreg_offset (tdep, offsets, regnum); | |
661 | if (regnum != tdep->ppc_vrsave_regnum | |
662 | && regnum != tdep->ppc_vrsave_regnum - 1) | |
19ba03f4 | 663 | ppc_supply_reg (regcache, regnum, (const gdb_byte *) vrregs, offset, 16); |
06caf7d2 CES |
664 | else |
665 | ppc_supply_reg (regcache, regnum, | |
19ba03f4 | 666 | (const gdb_byte *) vrregs, offset, 4); |
06caf7d2 CES |
667 | } |
668 | ||
d195bc9f | 669 | /* Collect register REGNUM in the general-purpose register set |
f2db237a | 670 | REGSET from register cache REGCACHE into the buffer specified by |
d195bc9f MK |
671 | GREGS and LEN. If REGNUM is -1, do this for all registers in |
672 | REGSET. */ | |
673 | ||
674 | void | |
675 | ppc_collect_gregset (const struct regset *regset, | |
676 | const struct regcache *regcache, | |
677 | int regnum, void *gregs, size_t len) | |
678 | { | |
ac7936df | 679 | struct gdbarch *gdbarch = regcache->arch (); |
d195bc9f | 680 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
19ba03f4 SM |
681 | const struct ppc_reg_offsets *offsets |
682 | = (const struct ppc_reg_offsets *) regset->regmap; | |
d195bc9f | 683 | size_t offset; |
f2db237a | 684 | int regsize; |
d195bc9f | 685 | |
f2db237a | 686 | if (regnum == -1) |
d195bc9f | 687 | { |
f2db237a AM |
688 | int i; |
689 | int gpr_size = offsets->gpr_size; | |
690 | ||
691 | for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset; | |
692 | i < tdep->ppc_gp0_regnum + ppc_num_gprs; | |
693 | i++, offset += gpr_size) | |
19ba03f4 | 694 | ppc_collect_reg (regcache, i, (gdb_byte *) gregs, offset, gpr_size); |
f2db237a AM |
695 | |
696 | ppc_collect_reg (regcache, gdbarch_pc_regnum (gdbarch), | |
19ba03f4 | 697 | (gdb_byte *) gregs, offsets->pc_offset, gpr_size); |
f2db237a | 698 | ppc_collect_reg (regcache, tdep->ppc_ps_regnum, |
19ba03f4 | 699 | (gdb_byte *) gregs, offsets->ps_offset, gpr_size); |
f2db237a | 700 | ppc_collect_reg (regcache, tdep->ppc_lr_regnum, |
19ba03f4 | 701 | (gdb_byte *) gregs, offsets->lr_offset, gpr_size); |
f2db237a | 702 | ppc_collect_reg (regcache, tdep->ppc_ctr_regnum, |
19ba03f4 | 703 | (gdb_byte *) gregs, offsets->ctr_offset, gpr_size); |
f2db237a | 704 | ppc_collect_reg (regcache, tdep->ppc_cr_regnum, |
19ba03f4 SM |
705 | (gdb_byte *) gregs, offsets->cr_offset, |
706 | offsets->xr_size); | |
f2db237a | 707 | ppc_collect_reg (regcache, tdep->ppc_xer_regnum, |
19ba03f4 SM |
708 | (gdb_byte *) gregs, offsets->xer_offset, |
709 | offsets->xr_size); | |
f2db237a | 710 | ppc_collect_reg (regcache, tdep->ppc_mq_regnum, |
19ba03f4 SM |
711 | (gdb_byte *) gregs, offsets->mq_offset, |
712 | offsets->xr_size); | |
f2db237a | 713 | return; |
d195bc9f MK |
714 | } |
715 | ||
f2db237a | 716 | offset = ppc_greg_offset (gdbarch, tdep, offsets, regnum, ®size); |
19ba03f4 | 717 | ppc_collect_reg (regcache, regnum, (gdb_byte *) gregs, offset, regsize); |
d195bc9f MK |
718 | } |
719 | ||
720 | /* Collect register REGNUM in the floating-point register set | |
f2db237a | 721 | REGSET from register cache REGCACHE into the buffer specified by |
d195bc9f MK |
722 | FPREGS and LEN. If REGNUM is -1, do this for all registers in |
723 | REGSET. */ | |
724 | ||
725 | void | |
726 | ppc_collect_fpregset (const struct regset *regset, | |
727 | const struct regcache *regcache, | |
728 | int regnum, void *fpregs, size_t len) | |
729 | { | |
ac7936df | 730 | struct gdbarch *gdbarch = regcache->arch (); |
f2db237a AM |
731 | struct gdbarch_tdep *tdep; |
732 | const struct ppc_reg_offsets *offsets; | |
d195bc9f | 733 | size_t offset; |
d195bc9f | 734 | |
f2db237a AM |
735 | if (!ppc_floating_point_unit_p (gdbarch)) |
736 | return; | |
383f0f5b | 737 | |
f2db237a | 738 | tdep = gdbarch_tdep (gdbarch); |
19ba03f4 | 739 | offsets = (const struct ppc_reg_offsets *) regset->regmap; |
f2db237a | 740 | if (regnum == -1) |
d195bc9f | 741 | { |
f2db237a AM |
742 | int i; |
743 | ||
744 | for (i = tdep->ppc_fp0_regnum, offset = offsets->f0_offset; | |
745 | i < tdep->ppc_fp0_regnum + ppc_num_fprs; | |
746 | i++, offset += 8) | |
19ba03f4 | 747 | ppc_collect_reg (regcache, i, (gdb_byte *) fpregs, offset, 8); |
f2db237a AM |
748 | |
749 | ppc_collect_reg (regcache, tdep->ppc_fpscr_regnum, | |
19ba03f4 SM |
750 | (gdb_byte *) fpregs, offsets->fpscr_offset, |
751 | offsets->fpscr_size); | |
f2db237a | 752 | return; |
d195bc9f MK |
753 | } |
754 | ||
f2db237a | 755 | offset = ppc_fpreg_offset (tdep, offsets, regnum); |
19ba03f4 | 756 | ppc_collect_reg (regcache, regnum, (gdb_byte *) fpregs, offset, |
f2db237a | 757 | regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8); |
d195bc9f | 758 | } |
06caf7d2 | 759 | |
604c2f83 LM |
760 | /* Collect register REGNUM in the VSX register set |
761 | REGSET from register cache REGCACHE into the buffer specified by | |
762 | VSXREGS and LEN. If REGNUM is -1, do this for all registers in | |
763 | REGSET. */ | |
764 | ||
765 | void | |
766 | ppc_collect_vsxregset (const struct regset *regset, | |
767 | const struct regcache *regcache, | |
768 | int regnum, void *vsxregs, size_t len) | |
769 | { | |
ac7936df | 770 | struct gdbarch *gdbarch = regcache->arch (); |
604c2f83 LM |
771 | struct gdbarch_tdep *tdep; |
772 | ||
773 | if (!ppc_vsx_support_p (gdbarch)) | |
774 | return; | |
775 | ||
776 | tdep = gdbarch_tdep (gdbarch); | |
777 | ||
778 | if (regnum == -1) | |
779 | { | |
780 | int i; | |
781 | ||
782 | for (i = tdep->ppc_vsr0_upper_regnum; | |
783 | i < tdep->ppc_vsr0_upper_regnum + 32; | |
784 | i++) | |
19ba03f4 | 785 | ppc_collect_reg (regcache, i, (gdb_byte *) vsxregs, 0, 8); |
604c2f83 LM |
786 | |
787 | return; | |
788 | } | |
789 | else | |
19ba03f4 | 790 | ppc_collect_reg (regcache, regnum, (gdb_byte *) vsxregs, 0, 8); |
604c2f83 LM |
791 | } |
792 | ||
793 | ||
06caf7d2 CES |
794 | /* Collect register REGNUM in the Altivec register set |
795 | REGSET from register cache REGCACHE into the buffer specified by | |
796 | VRREGS and LEN. If REGNUM is -1, do this for all registers in | |
797 | REGSET. */ | |
798 | ||
799 | void | |
800 | ppc_collect_vrregset (const struct regset *regset, | |
801 | const struct regcache *regcache, | |
802 | int regnum, void *vrregs, size_t len) | |
803 | { | |
ac7936df | 804 | struct gdbarch *gdbarch = regcache->arch (); |
06caf7d2 CES |
805 | struct gdbarch_tdep *tdep; |
806 | const struct ppc_reg_offsets *offsets; | |
807 | size_t offset; | |
808 | ||
809 | if (!ppc_altivec_support_p (gdbarch)) | |
810 | return; | |
811 | ||
812 | tdep = gdbarch_tdep (gdbarch); | |
19ba03f4 | 813 | offsets = (const struct ppc_reg_offsets *) regset->regmap; |
06caf7d2 CES |
814 | if (regnum == -1) |
815 | { | |
816 | int i; | |
817 | ||
818 | for (i = tdep->ppc_vr0_regnum, offset = offsets->vr0_offset; | |
819 | i < tdep->ppc_vr0_regnum + ppc_num_vrs; | |
820 | i++, offset += 16) | |
19ba03f4 | 821 | ppc_collect_reg (regcache, i, (gdb_byte *) vrregs, offset, 16); |
06caf7d2 CES |
822 | |
823 | ppc_collect_reg (regcache, (tdep->ppc_vrsave_regnum - 1), | |
19ba03f4 | 824 | (gdb_byte *) vrregs, offsets->vscr_offset, 4); |
06caf7d2 CES |
825 | |
826 | ppc_collect_reg (regcache, tdep->ppc_vrsave_regnum, | |
19ba03f4 | 827 | (gdb_byte *) vrregs, offsets->vrsave_offset, 4); |
06caf7d2 CES |
828 | return; |
829 | } | |
830 | ||
831 | offset = ppc_vrreg_offset (tdep, offsets, regnum); | |
832 | if (regnum != tdep->ppc_vrsave_regnum | |
833 | && regnum != tdep->ppc_vrsave_regnum - 1) | |
19ba03f4 | 834 | ppc_collect_reg (regcache, regnum, (gdb_byte *) vrregs, offset, 16); |
06caf7d2 CES |
835 | else |
836 | ppc_collect_reg (regcache, regnum, | |
19ba03f4 | 837 | (gdb_byte *) vrregs, offset, 4); |
06caf7d2 | 838 | } |
d195bc9f | 839 | \f |
0a613259 | 840 | |
0d1243d9 PG |
841 | static int |
842 | insn_changes_sp_or_jumps (unsigned long insn) | |
843 | { | |
844 | int opcode = (insn >> 26) & 0x03f; | |
845 | int sd = (insn >> 21) & 0x01f; | |
846 | int a = (insn >> 16) & 0x01f; | |
847 | int subcode = (insn >> 1) & 0x3ff; | |
848 | ||
849 | /* Changes the stack pointer. */ | |
850 | ||
851 | /* NOTE: There are many ways to change the value of a given register. | |
852 | The ways below are those used when the register is R1, the SP, | |
853 | in a funtion's epilogue. */ | |
854 | ||
855 | if (opcode == 31 && subcode == 444 && a == 1) | |
856 | return 1; /* mr R1,Rn */ | |
857 | if (opcode == 14 && sd == 1) | |
858 | return 1; /* addi R1,Rn,simm */ | |
859 | if (opcode == 58 && sd == 1) | |
860 | return 1; /* ld R1,ds(Rn) */ | |
861 | ||
862 | /* Transfers control. */ | |
863 | ||
864 | if (opcode == 18) | |
865 | return 1; /* b */ | |
866 | if (opcode == 16) | |
867 | return 1; /* bc */ | |
868 | if (opcode == 19 && subcode == 16) | |
869 | return 1; /* bclr */ | |
870 | if (opcode == 19 && subcode == 528) | |
871 | return 1; /* bcctr */ | |
872 | ||
873 | return 0; | |
874 | } | |
875 | ||
876 | /* Return true if we are in the function's epilogue, i.e. after the | |
877 | instruction that destroyed the function's stack frame. | |
878 | ||
879 | 1) scan forward from the point of execution: | |
880 | a) If you find an instruction that modifies the stack pointer | |
881 | or transfers control (except a return), execution is not in | |
882 | an epilogue, return. | |
883 | b) Stop scanning if you find a return instruction or reach the | |
884 | end of the function or reach the hard limit for the size of | |
885 | an epilogue. | |
886 | 2) scan backward from the point of execution: | |
887 | a) If you find an instruction that modifies the stack pointer, | |
888 | execution *is* in an epilogue, return. | |
889 | b) Stop scanning if you reach an instruction that transfers | |
890 | control or the beginning of the function or reach the hard | |
891 | limit for the size of an epilogue. */ | |
892 | ||
893 | static int | |
2608dbf8 WW |
894 | rs6000_in_function_epilogue_frame_p (struct frame_info *curfrm, |
895 | struct gdbarch *gdbarch, CORE_ADDR pc) | |
0d1243d9 | 896 | { |
46a9b8ed | 897 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
e17a4113 | 898 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
0d1243d9 PG |
899 | bfd_byte insn_buf[PPC_INSN_SIZE]; |
900 | CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end; | |
901 | unsigned long insn; | |
0d1243d9 PG |
902 | |
903 | /* Find the search limits based on function boundaries and hard limit. */ | |
904 | ||
905 | if (!find_pc_partial_function (pc, NULL, &func_start, &func_end)) | |
906 | return 0; | |
907 | ||
908 | epilogue_start = pc - PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE; | |
909 | if (epilogue_start < func_start) epilogue_start = func_start; | |
910 | ||
911 | epilogue_end = pc + PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE; | |
912 | if (epilogue_end > func_end) epilogue_end = func_end; | |
913 | ||
0d1243d9 PG |
914 | /* Scan forward until next 'blr'. */ |
915 | ||
916 | for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += PPC_INSN_SIZE) | |
917 | { | |
918 | if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE)) | |
919 | return 0; | |
e17a4113 | 920 | insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE, byte_order); |
0d1243d9 PG |
921 | if (insn == 0x4e800020) |
922 | break; | |
46a9b8ed DJ |
923 | /* Assume a bctr is a tail call unless it points strictly within |
924 | this function. */ | |
925 | if (insn == 0x4e800420) | |
926 | { | |
927 | CORE_ADDR ctr = get_frame_register_unsigned (curfrm, | |
928 | tdep->ppc_ctr_regnum); | |
929 | if (ctr > func_start && ctr < func_end) | |
930 | return 0; | |
931 | else | |
932 | break; | |
933 | } | |
0d1243d9 PG |
934 | if (insn_changes_sp_or_jumps (insn)) |
935 | return 0; | |
936 | } | |
937 | ||
938 | /* Scan backward until adjustment to stack pointer (R1). */ | |
939 | ||
940 | for (scan_pc = pc - PPC_INSN_SIZE; | |
941 | scan_pc >= epilogue_start; | |
942 | scan_pc -= PPC_INSN_SIZE) | |
943 | { | |
944 | if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE)) | |
945 | return 0; | |
e17a4113 | 946 | insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE, byte_order); |
0d1243d9 PG |
947 | if (insn_changes_sp_or_jumps (insn)) |
948 | return 1; | |
949 | } | |
950 | ||
951 | return 0; | |
952 | } | |
953 | ||
c9cf6e20 | 954 | /* Implement the stack_frame_destroyed_p gdbarch method. */ |
2608dbf8 WW |
955 | |
956 | static int | |
c9cf6e20 | 957 | rs6000_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
2608dbf8 WW |
958 | { |
959 | return rs6000_in_function_epilogue_frame_p (get_current_frame (), | |
960 | gdbarch, pc); | |
961 | } | |
962 | ||
143985b7 | 963 | /* Get the ith function argument for the current function. */ |
b9362cc7 | 964 | static CORE_ADDR |
143985b7 AF |
965 | rs6000_fetch_pointer_argument (struct frame_info *frame, int argi, |
966 | struct type *type) | |
967 | { | |
50fd1280 | 968 | return get_frame_register_unsigned (frame, 3 + argi); |
143985b7 AF |
969 | } |
970 | ||
c906108c SS |
971 | /* Sequence of bytes for breakpoint instruction. */ |
972 | ||
04180708 YQ |
973 | constexpr gdb_byte big_breakpoint[] = { 0x7d, 0x82, 0x10, 0x08 }; |
974 | constexpr gdb_byte little_breakpoint[] = { 0x08, 0x10, 0x82, 0x7d }; | |
d19280ad | 975 | |
04180708 YQ |
976 | typedef BP_MANIPULATION_ENDIAN (little_breakpoint, big_breakpoint) |
977 | rs6000_breakpoint; | |
c906108c | 978 | |
f74c6cad LM |
979 | /* Instruction masks for displaced stepping. */ |
980 | #define BRANCH_MASK 0xfc000000 | |
981 | #define BP_MASK 0xFC0007FE | |
982 | #define B_INSN 0x48000000 | |
983 | #define BC_INSN 0x40000000 | |
984 | #define BXL_INSN 0x4c000000 | |
985 | #define BP_INSN 0x7C000008 | |
986 | ||
7f03bd92 PA |
987 | /* Instruction masks used during single-stepping of atomic |
988 | sequences. */ | |
2039d74e | 989 | #define LOAD_AND_RESERVE_MASK 0xfc0007fe |
7f03bd92 PA |
990 | #define LWARX_INSTRUCTION 0x7c000028 |
991 | #define LDARX_INSTRUCTION 0x7c0000A8 | |
2039d74e EBM |
992 | #define LBARX_INSTRUCTION 0x7c000068 |
993 | #define LHARX_INSTRUCTION 0x7c0000e8 | |
994 | #define LQARX_INSTRUCTION 0x7c000228 | |
995 | #define STORE_CONDITIONAL_MASK 0xfc0007ff | |
7f03bd92 PA |
996 | #define STWCX_INSTRUCTION 0x7c00012d |
997 | #define STDCX_INSTRUCTION 0x7c0001ad | |
2039d74e EBM |
998 | #define STBCX_INSTRUCTION 0x7c00056d |
999 | #define STHCX_INSTRUCTION 0x7c0005ad | |
1000 | #define STQCX_INSTRUCTION 0x7c00016d | |
1001 | ||
1002 | /* Check if insn is one of the Load And Reserve instructions used for atomic | |
1003 | sequences. */ | |
1004 | #define IS_LOAD_AND_RESERVE_INSN(insn) ((insn & LOAD_AND_RESERVE_MASK) == LWARX_INSTRUCTION \ | |
1005 | || (insn & LOAD_AND_RESERVE_MASK) == LDARX_INSTRUCTION \ | |
1006 | || (insn & LOAD_AND_RESERVE_MASK) == LBARX_INSTRUCTION \ | |
1007 | || (insn & LOAD_AND_RESERVE_MASK) == LHARX_INSTRUCTION \ | |
1008 | || (insn & LOAD_AND_RESERVE_MASK) == LQARX_INSTRUCTION) | |
1009 | /* Check if insn is one of the Store Conditional instructions used for atomic | |
1010 | sequences. */ | |
1011 | #define IS_STORE_CONDITIONAL_INSN(insn) ((insn & STORE_CONDITIONAL_MASK) == STWCX_INSTRUCTION \ | |
1012 | || (insn & STORE_CONDITIONAL_MASK) == STDCX_INSTRUCTION \ | |
1013 | || (insn & STORE_CONDITIONAL_MASK) == STBCX_INSTRUCTION \ | |
1014 | || (insn & STORE_CONDITIONAL_MASK) == STHCX_INSTRUCTION \ | |
1015 | || (insn & STORE_CONDITIONAL_MASK) == STQCX_INSTRUCTION) | |
7f03bd92 | 1016 | |
cfba9872 SM |
1017 | typedef buf_displaced_step_closure ppc_displaced_step_closure; |
1018 | ||
c2508e90 | 1019 | /* We can't displaced step atomic sequences. */ |
7f03bd92 PA |
1020 | |
1021 | static struct displaced_step_closure * | |
1022 | ppc_displaced_step_copy_insn (struct gdbarch *gdbarch, | |
1023 | CORE_ADDR from, CORE_ADDR to, | |
1024 | struct regcache *regs) | |
1025 | { | |
1026 | size_t len = gdbarch_max_insn_length (gdbarch); | |
cfba9872 SM |
1027 | std::unique_ptr<ppc_displaced_step_closure> closure |
1028 | (new ppc_displaced_step_closure (len)); | |
1029 | gdb_byte *buf = closure->buf.data (); | |
7f03bd92 PA |
1030 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1031 | int insn; | |
1032 | ||
1033 | read_memory (from, buf, len); | |
1034 | ||
1035 | insn = extract_signed_integer (buf, PPC_INSN_SIZE, byte_order); | |
1036 | ||
2039d74e EBM |
1037 | /* Assume all atomic sequences start with a Load and Reserve instruction. */ |
1038 | if (IS_LOAD_AND_RESERVE_INSN (insn)) | |
7f03bd92 PA |
1039 | { |
1040 | if (debug_displaced) | |
1041 | { | |
1042 | fprintf_unfiltered (gdb_stdlog, | |
1043 | "displaced: can't displaced step " | |
1044 | "atomic sequence at %s\n", | |
1045 | paddress (gdbarch, from)); | |
1046 | } | |
cfba9872 | 1047 | |
7f03bd92 PA |
1048 | return NULL; |
1049 | } | |
1050 | ||
1051 | write_memory (to, buf, len); | |
1052 | ||
1053 | if (debug_displaced) | |
1054 | { | |
1055 | fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ", | |
1056 | paddress (gdbarch, from), paddress (gdbarch, to)); | |
1057 | displaced_step_dump_bytes (gdb_stdlog, buf, len); | |
1058 | } | |
1059 | ||
cfba9872 | 1060 | return closure.release (); |
7f03bd92 PA |
1061 | } |
1062 | ||
f74c6cad LM |
1063 | /* Fix up the state of registers and memory after having single-stepped |
1064 | a displaced instruction. */ | |
63807e1d | 1065 | static void |
f74c6cad | 1066 | ppc_displaced_step_fixup (struct gdbarch *gdbarch, |
cfba9872 | 1067 | struct displaced_step_closure *closure_, |
63807e1d PA |
1068 | CORE_ADDR from, CORE_ADDR to, |
1069 | struct regcache *regs) | |
f74c6cad | 1070 | { |
e17a4113 | 1071 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7f03bd92 | 1072 | /* Our closure is a copy of the instruction. */ |
cfba9872 SM |
1073 | ppc_displaced_step_closure *closure = (ppc_displaced_step_closure *) closure_; |
1074 | ULONGEST insn = extract_unsigned_integer (closure->buf.data (), | |
1075 | PPC_INSN_SIZE, byte_order); | |
f74c6cad LM |
1076 | ULONGEST opcode = 0; |
1077 | /* Offset for non PC-relative instructions. */ | |
1078 | LONGEST offset = PPC_INSN_SIZE; | |
1079 | ||
1080 | opcode = insn & BRANCH_MASK; | |
1081 | ||
1082 | if (debug_displaced) | |
1083 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 UW |
1084 | "displaced: (ppc) fixup (%s, %s)\n", |
1085 | paddress (gdbarch, from), paddress (gdbarch, to)); | |
f74c6cad LM |
1086 | |
1087 | ||
1088 | /* Handle PC-relative branch instructions. */ | |
1089 | if (opcode == B_INSN || opcode == BC_INSN || opcode == BXL_INSN) | |
1090 | { | |
a4fafde3 | 1091 | ULONGEST current_pc; |
f74c6cad LM |
1092 | |
1093 | /* Read the current PC value after the instruction has been executed | |
1094 | in a displaced location. Calculate the offset to be applied to the | |
1095 | original PC value before the displaced stepping. */ | |
1096 | regcache_cooked_read_unsigned (regs, gdbarch_pc_regnum (gdbarch), | |
1097 | ¤t_pc); | |
1098 | offset = current_pc - to; | |
1099 | ||
1100 | if (opcode != BXL_INSN) | |
1101 | { | |
1102 | /* Check for AA bit indicating whether this is an absolute | |
1103 | addressing or PC-relative (1: absolute, 0: relative). */ | |
1104 | if (!(insn & 0x2)) | |
1105 | { | |
1106 | /* PC-relative addressing is being used in the branch. */ | |
1107 | if (debug_displaced) | |
1108 | fprintf_unfiltered | |
1109 | (gdb_stdlog, | |
5af949e3 UW |
1110 | "displaced: (ppc) branch instruction: %s\n" |
1111 | "displaced: (ppc) adjusted PC from %s to %s\n", | |
1112 | paddress (gdbarch, insn), paddress (gdbarch, current_pc), | |
1113 | paddress (gdbarch, from + offset)); | |
f74c6cad | 1114 | |
0df8b418 MS |
1115 | regcache_cooked_write_unsigned (regs, |
1116 | gdbarch_pc_regnum (gdbarch), | |
f74c6cad LM |
1117 | from + offset); |
1118 | } | |
1119 | } | |
1120 | else | |
1121 | { | |
1122 | /* If we're here, it means we have a branch to LR or CTR. If the | |
1123 | branch was taken, the offset is probably greater than 4 (the next | |
1124 | instruction), so it's safe to assume that an offset of 4 means we | |
1125 | did not take the branch. */ | |
1126 | if (offset == PPC_INSN_SIZE) | |
1127 | regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch), | |
1128 | from + PPC_INSN_SIZE); | |
1129 | } | |
1130 | ||
1131 | /* Check for LK bit indicating whether we should set the link | |
1132 | register to point to the next instruction | |
1133 | (1: Set, 0: Don't set). */ | |
1134 | if (insn & 0x1) | |
1135 | { | |
1136 | /* Link register needs to be set to the next instruction's PC. */ | |
1137 | regcache_cooked_write_unsigned (regs, | |
1138 | gdbarch_tdep (gdbarch)->ppc_lr_regnum, | |
1139 | from + PPC_INSN_SIZE); | |
1140 | if (debug_displaced) | |
1141 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 UW |
1142 | "displaced: (ppc) adjusted LR to %s\n", |
1143 | paddress (gdbarch, from + PPC_INSN_SIZE)); | |
f74c6cad LM |
1144 | |
1145 | } | |
1146 | } | |
1147 | /* Check for breakpoints in the inferior. If we've found one, place the PC | |
1148 | right at the breakpoint instruction. */ | |
1149 | else if ((insn & BP_MASK) == BP_INSN) | |
1150 | regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch), from); | |
1151 | else | |
1152 | /* Handle any other instructions that do not fit in the categories above. */ | |
1153 | regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch), | |
1154 | from + offset); | |
1155 | } | |
c906108c | 1156 | |
99e40580 UW |
1157 | /* Always use hardware single-stepping to execute the |
1158 | displaced instruction. */ | |
1159 | static int | |
1160 | ppc_displaced_step_hw_singlestep (struct gdbarch *gdbarch, | |
1161 | struct displaced_step_closure *closure) | |
1162 | { | |
1163 | return 1; | |
1164 | } | |
1165 | ||
2039d74e EBM |
1166 | /* Checks for an atomic sequence of instructions beginning with a |
1167 | Load And Reserve instruction and ending with a Store Conditional | |
1168 | instruction. If such a sequence is found, attempt to step through it. | |
1169 | A breakpoint is placed at the end of the sequence. */ | |
a0ff9e1a | 1170 | std::vector<CORE_ADDR> |
f5ea389a | 1171 | ppc_deal_with_atomic_sequence (struct regcache *regcache) |
ce5eab59 | 1172 | { |
ac7936df | 1173 | struct gdbarch *gdbarch = regcache->arch (); |
e17a4113 | 1174 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
41e26ad3 | 1175 | CORE_ADDR pc = regcache_read_pc (regcache); |
ce5eab59 UW |
1176 | CORE_ADDR breaks[2] = {-1, -1}; |
1177 | CORE_ADDR loc = pc; | |
24d45690 | 1178 | CORE_ADDR closing_insn; /* Instruction that closes the atomic sequence. */ |
e17a4113 | 1179 | int insn = read_memory_integer (loc, PPC_INSN_SIZE, byte_order); |
ce5eab59 UW |
1180 | int insn_count; |
1181 | int index; | |
1182 | int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ | |
1183 | const int atomic_sequence_length = 16; /* Instruction sequence length. */ | |
ce5eab59 UW |
1184 | int bc_insn_count = 0; /* Conditional branch instruction count. */ |
1185 | ||
2039d74e EBM |
1186 | /* Assume all atomic sequences start with a Load And Reserve instruction. */ |
1187 | if (!IS_LOAD_AND_RESERVE_INSN (insn)) | |
a0ff9e1a | 1188 | return {}; |
ce5eab59 UW |
1189 | |
1190 | /* Assume that no atomic sequence is longer than "atomic_sequence_length" | |
1191 | instructions. */ | |
1192 | for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) | |
1193 | { | |
1194 | loc += PPC_INSN_SIZE; | |
e17a4113 | 1195 | insn = read_memory_integer (loc, PPC_INSN_SIZE, byte_order); |
ce5eab59 UW |
1196 | |
1197 | /* Assume that there is at most one conditional branch in the atomic | |
1198 | sequence. If a conditional branch is found, put a breakpoint in | |
1199 | its destination address. */ | |
f74c6cad | 1200 | if ((insn & BRANCH_MASK) == BC_INSN) |
ce5eab59 | 1201 | { |
a3769e0c AM |
1202 | int immediate = ((insn & 0xfffc) ^ 0x8000) - 0x8000; |
1203 | int absolute = insn & 2; | |
4a7622d1 | 1204 | |
ce5eab59 | 1205 | if (bc_insn_count >= 1) |
a0ff9e1a SM |
1206 | return {}; /* More than one conditional branch found, fallback |
1207 | to the standard single-step code. */ | |
4a7622d1 UW |
1208 | |
1209 | if (absolute) | |
1210 | breaks[1] = immediate; | |
1211 | else | |
a3769e0c | 1212 | breaks[1] = loc + immediate; |
4a7622d1 UW |
1213 | |
1214 | bc_insn_count++; | |
1215 | last_breakpoint++; | |
ce5eab59 UW |
1216 | } |
1217 | ||
2039d74e | 1218 | if (IS_STORE_CONDITIONAL_INSN (insn)) |
ce5eab59 UW |
1219 | break; |
1220 | } | |
1221 | ||
2039d74e EBM |
1222 | /* Assume that the atomic sequence ends with a Store Conditional |
1223 | instruction. */ | |
1224 | if (!IS_STORE_CONDITIONAL_INSN (insn)) | |
a0ff9e1a | 1225 | return {}; |
ce5eab59 | 1226 | |
24d45690 | 1227 | closing_insn = loc; |
ce5eab59 | 1228 | loc += PPC_INSN_SIZE; |
e17a4113 | 1229 | insn = read_memory_integer (loc, PPC_INSN_SIZE, byte_order); |
ce5eab59 UW |
1230 | |
1231 | /* Insert a breakpoint right after the end of the atomic sequence. */ | |
1232 | breaks[0] = loc; | |
1233 | ||
24d45690 | 1234 | /* Check for duplicated breakpoints. Check also for a breakpoint |
a3769e0c AM |
1235 | placed (branch instruction's destination) anywhere in sequence. */ |
1236 | if (last_breakpoint | |
1237 | && (breaks[1] == breaks[0] | |
1238 | || (breaks[1] >= pc && breaks[1] <= closing_insn))) | |
ce5eab59 UW |
1239 | last_breakpoint = 0; |
1240 | ||
a0ff9e1a SM |
1241 | std::vector<CORE_ADDR> next_pcs; |
1242 | ||
ce5eab59 | 1243 | for (index = 0; index <= last_breakpoint; index++) |
a0ff9e1a | 1244 | next_pcs.push_back (breaks[index]); |
ce5eab59 | 1245 | |
93f9a11f | 1246 | return next_pcs; |
ce5eab59 UW |
1247 | } |
1248 | ||
c906108c | 1249 | |
c906108c SS |
1250 | #define SIGNED_SHORT(x) \ |
1251 | ((sizeof (short) == 2) \ | |
1252 | ? ((int)(short)(x)) \ | |
1253 | : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000))) | |
1254 | ||
1255 | #define GET_SRC_REG(x) (((x) >> 21) & 0x1f) | |
1256 | ||
55d05f3b KB |
1257 | /* Limit the number of skipped non-prologue instructions, as the examining |
1258 | of the prologue is expensive. */ | |
1259 | static int max_skip_non_prologue_insns = 10; | |
1260 | ||
773df3e5 JB |
1261 | /* Return nonzero if the given instruction OP can be part of the prologue |
1262 | of a function and saves a parameter on the stack. FRAMEP should be | |
1263 | set if one of the previous instructions in the function has set the | |
1264 | Frame Pointer. */ | |
1265 | ||
1266 | static int | |
1267 | store_param_on_stack_p (unsigned long op, int framep, int *r0_contains_arg) | |
1268 | { | |
1269 | /* Move parameters from argument registers to temporary register. */ | |
1270 | if ((op & 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */ | |
1271 | { | |
1272 | /* Rx must be scratch register r0. */ | |
1273 | const int rx_regno = (op >> 16) & 31; | |
1274 | /* Ry: Only r3 - r10 are used for parameter passing. */ | |
1275 | const int ry_regno = GET_SRC_REG (op); | |
1276 | ||
1277 | if (rx_regno == 0 && ry_regno >= 3 && ry_regno <= 10) | |
1278 | { | |
1279 | *r0_contains_arg = 1; | |
1280 | return 1; | |
1281 | } | |
1282 | else | |
1283 | return 0; | |
1284 | } | |
1285 | ||
1286 | /* Save a General Purpose Register on stack. */ | |
1287 | ||
1288 | if ((op & 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */ | |
1289 | (op & 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */ | |
1290 | { | |
1291 | /* Rx: Only r3 - r10 are used for parameter passing. */ | |
1292 | const int rx_regno = GET_SRC_REG (op); | |
1293 | ||
1294 | return (rx_regno >= 3 && rx_regno <= 10); | |
1295 | } | |
1296 | ||
1297 | /* Save a General Purpose Register on stack via the Frame Pointer. */ | |
1298 | ||
1299 | if (framep && | |
1300 | ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */ | |
1301 | (op & 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */ | |
1302 | (op & 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */ | |
1303 | { | |
1304 | /* Rx: Usually, only r3 - r10 are used for parameter passing. | |
1305 | However, the compiler sometimes uses r0 to hold an argument. */ | |
1306 | const int rx_regno = GET_SRC_REG (op); | |
1307 | ||
1308 | return ((rx_regno >= 3 && rx_regno <= 10) | |
1309 | || (rx_regno == 0 && *r0_contains_arg)); | |
1310 | } | |
1311 | ||
1312 | if ((op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */ | |
1313 | { | |
1314 | /* Only f2 - f8 are used for parameter passing. */ | |
1315 | const int src_regno = GET_SRC_REG (op); | |
1316 | ||
1317 | return (src_regno >= 2 && src_regno <= 8); | |
1318 | } | |
1319 | ||
1320 | if (framep && ((op & 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */ | |
1321 | { | |
1322 | /* Only f2 - f8 are used for parameter passing. */ | |
1323 | const int src_regno = GET_SRC_REG (op); | |
1324 | ||
1325 | return (src_regno >= 2 && src_regno <= 8); | |
1326 | } | |
1327 | ||
1328 | /* Not an insn that saves a parameter on stack. */ | |
1329 | return 0; | |
1330 | } | |
55d05f3b | 1331 | |
3c77c82a DJ |
1332 | /* Assuming that INSN is a "bl" instruction located at PC, return |
1333 | nonzero if the destination of the branch is a "blrl" instruction. | |
1334 | ||
1335 | This sequence is sometimes found in certain function prologues. | |
1336 | It allows the function to load the LR register with a value that | |
1337 | they can use to access PIC data using PC-relative offsets. */ | |
1338 | ||
1339 | static int | |
e17a4113 | 1340 | bl_to_blrl_insn_p (CORE_ADDR pc, int insn, enum bfd_endian byte_order) |
3c77c82a | 1341 | { |
0b1b3e42 UW |
1342 | CORE_ADDR dest; |
1343 | int immediate; | |
1344 | int absolute; | |
3c77c82a DJ |
1345 | int dest_insn; |
1346 | ||
0b1b3e42 UW |
1347 | absolute = (int) ((insn >> 1) & 1); |
1348 | immediate = ((insn & ~3) << 6) >> 6; | |
1349 | if (absolute) | |
1350 | dest = immediate; | |
1351 | else | |
1352 | dest = pc + immediate; | |
1353 | ||
e17a4113 | 1354 | dest_insn = read_memory_integer (dest, 4, byte_order); |
3c77c82a DJ |
1355 | if ((dest_insn & 0xfc00ffff) == 0x4c000021) /* blrl */ |
1356 | return 1; | |
1357 | ||
1358 | return 0; | |
1359 | } | |
1360 | ||
0df8b418 | 1361 | /* Masks for decoding a branch-and-link (bl) instruction. |
8ab3d180 KB |
1362 | |
1363 | BL_MASK and BL_INSTRUCTION are used in combination with each other. | |
1364 | The former is anded with the opcode in question; if the result of | |
1365 | this masking operation is equal to BL_INSTRUCTION, then the opcode in | |
1366 | question is a ``bl'' instruction. | |
1367 | ||
1368 | BL_DISPLACMENT_MASK is anded with the opcode in order to extract | |
1369 | the branch displacement. */ | |
1370 | ||
1371 | #define BL_MASK 0xfc000001 | |
1372 | #define BL_INSTRUCTION 0x48000001 | |
1373 | #define BL_DISPLACEMENT_MASK 0x03fffffc | |
1374 | ||
de9f48f0 | 1375 | static unsigned long |
e17a4113 | 1376 | rs6000_fetch_instruction (struct gdbarch *gdbarch, const CORE_ADDR pc) |
de9f48f0 | 1377 | { |
e17a4113 | 1378 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
de9f48f0 JG |
1379 | gdb_byte buf[4]; |
1380 | unsigned long op; | |
1381 | ||
1382 | /* Fetch the instruction and convert it to an integer. */ | |
1383 | if (target_read_memory (pc, buf, 4)) | |
1384 | return 0; | |
e17a4113 | 1385 | op = extract_unsigned_integer (buf, 4, byte_order); |
de9f48f0 JG |
1386 | |
1387 | return op; | |
1388 | } | |
1389 | ||
1390 | /* GCC generates several well-known sequences of instructions at the begining | |
1391 | of each function prologue when compiling with -fstack-check. If one of | |
1392 | such sequences starts at START_PC, then return the address of the | |
1393 | instruction immediately past this sequence. Otherwise, return START_PC. */ | |
1394 | ||
1395 | static CORE_ADDR | |
e17a4113 | 1396 | rs6000_skip_stack_check (struct gdbarch *gdbarch, const CORE_ADDR start_pc) |
de9f48f0 JG |
1397 | { |
1398 | CORE_ADDR pc = start_pc; | |
e17a4113 | 1399 | unsigned long op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 JG |
1400 | |
1401 | /* First possible sequence: A small number of probes. | |
1402 | stw 0, -<some immediate>(1) | |
0df8b418 | 1403 | [repeat this instruction any (small) number of times]. */ |
de9f48f0 JG |
1404 | |
1405 | if ((op & 0xffff0000) == 0x90010000) | |
1406 | { | |
1407 | while ((op & 0xffff0000) == 0x90010000) | |
1408 | { | |
1409 | pc = pc + 4; | |
e17a4113 | 1410 | op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 JG |
1411 | } |
1412 | return pc; | |
1413 | } | |
1414 | ||
1415 | /* Second sequence: A probing loop. | |
1416 | addi 12,1,-<some immediate> | |
1417 | lis 0,-<some immediate> | |
1418 | [possibly ori 0,0,<some immediate>] | |
1419 | add 0,12,0 | |
1420 | cmpw 0,12,0 | |
1421 | beq 0,<disp> | |
1422 | addi 12,12,-<some immediate> | |
1423 | stw 0,0(12) | |
1424 | b <disp> | |
0df8b418 | 1425 | [possibly one last probe: stw 0,<some immediate>(12)]. */ |
de9f48f0 JG |
1426 | |
1427 | while (1) | |
1428 | { | |
1429 | /* addi 12,1,-<some immediate> */ | |
1430 | if ((op & 0xffff0000) != 0x39810000) | |
1431 | break; | |
1432 | ||
1433 | /* lis 0,-<some immediate> */ | |
1434 | pc = pc + 4; | |
e17a4113 | 1435 | op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 JG |
1436 | if ((op & 0xffff0000) != 0x3c000000) |
1437 | break; | |
1438 | ||
1439 | pc = pc + 4; | |
e17a4113 | 1440 | op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 JG |
1441 | /* [possibly ori 0,0,<some immediate>] */ |
1442 | if ((op & 0xffff0000) == 0x60000000) | |
1443 | { | |
1444 | pc = pc + 4; | |
e17a4113 | 1445 | op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 JG |
1446 | } |
1447 | /* add 0,12,0 */ | |
1448 | if (op != 0x7c0c0214) | |
1449 | break; | |
1450 | ||
1451 | /* cmpw 0,12,0 */ | |
1452 | pc = pc + 4; | |
e17a4113 | 1453 | op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 JG |
1454 | if (op != 0x7c0c0000) |
1455 | break; | |
1456 | ||
1457 | /* beq 0,<disp> */ | |
1458 | pc = pc + 4; | |
e17a4113 | 1459 | op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 JG |
1460 | if ((op & 0xff9f0001) != 0x41820000) |
1461 | break; | |
1462 | ||
1463 | /* addi 12,12,-<some immediate> */ | |
1464 | pc = pc + 4; | |
e17a4113 | 1465 | op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 JG |
1466 | if ((op & 0xffff0000) != 0x398c0000) |
1467 | break; | |
1468 | ||
1469 | /* stw 0,0(12) */ | |
1470 | pc = pc + 4; | |
e17a4113 | 1471 | op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 JG |
1472 | if (op != 0x900c0000) |
1473 | break; | |
1474 | ||
1475 | /* b <disp> */ | |
1476 | pc = pc + 4; | |
e17a4113 | 1477 | op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 JG |
1478 | if ((op & 0xfc000001) != 0x48000000) |
1479 | break; | |
1480 | ||
0df8b418 | 1481 | /* [possibly one last probe: stw 0,<some immediate>(12)]. */ |
de9f48f0 | 1482 | pc = pc + 4; |
e17a4113 | 1483 | op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 JG |
1484 | if ((op & 0xffff0000) == 0x900c0000) |
1485 | { | |
1486 | pc = pc + 4; | |
e17a4113 | 1487 | op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 JG |
1488 | } |
1489 | ||
1490 | /* We found a valid stack-check sequence, return the new PC. */ | |
1491 | return pc; | |
1492 | } | |
1493 | ||
1494 | /* Third sequence: No probe; instead, a comparizon between the stack size | |
1495 | limit (saved in a run-time global variable) and the current stack | |
1496 | pointer: | |
1497 | ||
1498 | addi 0,1,-<some immediate> | |
1499 | lis 12,__gnat_stack_limit@ha | |
1500 | lwz 12,__gnat_stack_limit@l(12) | |
1501 | twllt 0,12 | |
1502 | ||
1503 | or, with a small variant in the case of a bigger stack frame: | |
1504 | addis 0,1,<some immediate> | |
1505 | addic 0,0,-<some immediate> | |
1506 | lis 12,__gnat_stack_limit@ha | |
1507 | lwz 12,__gnat_stack_limit@l(12) | |
1508 | twllt 0,12 | |
1509 | */ | |
1510 | while (1) | |
1511 | { | |
1512 | /* addi 0,1,-<some immediate> */ | |
1513 | if ((op & 0xffff0000) != 0x38010000) | |
1514 | { | |
1515 | /* small stack frame variant not recognized; try the | |
1516 | big stack frame variant: */ | |
1517 | ||
1518 | /* addis 0,1,<some immediate> */ | |
1519 | if ((op & 0xffff0000) != 0x3c010000) | |
1520 | break; | |
1521 | ||
1522 | /* addic 0,0,-<some immediate> */ | |
1523 | pc = pc + 4; | |
e17a4113 | 1524 | op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 JG |
1525 | if ((op & 0xffff0000) != 0x30000000) |
1526 | break; | |
1527 | } | |
1528 | ||
1529 | /* lis 12,<some immediate> */ | |
1530 | pc = pc + 4; | |
e17a4113 | 1531 | op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 JG |
1532 | if ((op & 0xffff0000) != 0x3d800000) |
1533 | break; | |
1534 | ||
1535 | /* lwz 12,<some immediate>(12) */ | |
1536 | pc = pc + 4; | |
e17a4113 | 1537 | op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 JG |
1538 | if ((op & 0xffff0000) != 0x818c0000) |
1539 | break; | |
1540 | ||
1541 | /* twllt 0,12 */ | |
1542 | pc = pc + 4; | |
e17a4113 | 1543 | op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 JG |
1544 | if ((op & 0xfffffffe) != 0x7c406008) |
1545 | break; | |
1546 | ||
1547 | /* We found a valid stack-check sequence, return the new PC. */ | |
1548 | return pc; | |
1549 | } | |
1550 | ||
1551 | /* No stack check code in our prologue, return the start_pc. */ | |
1552 | return start_pc; | |
1553 | } | |
1554 | ||
6a16c029 TJB |
1555 | /* return pc value after skipping a function prologue and also return |
1556 | information about a function frame. | |
1557 | ||
1558 | in struct rs6000_framedata fdata: | |
1559 | - frameless is TRUE, if function does not have a frame. | |
1560 | - nosavedpc is TRUE, if function does not save %pc value in its frame. | |
1561 | - offset is the initial size of this stack frame --- the amount by | |
1562 | which we decrement the sp to allocate the frame. | |
1563 | - saved_gpr is the number of the first saved gpr. | |
1564 | - saved_fpr is the number of the first saved fpr. | |
1565 | - saved_vr is the number of the first saved vr. | |
1566 | - saved_ev is the number of the first saved ev. | |
1567 | - alloca_reg is the number of the register used for alloca() handling. | |
1568 | Otherwise -1. | |
1569 | - gpr_offset is the offset of the first saved gpr from the previous frame. | |
1570 | - fpr_offset is the offset of the first saved fpr from the previous frame. | |
1571 | - vr_offset is the offset of the first saved vr from the previous frame. | |
1572 | - ev_offset is the offset of the first saved ev from the previous frame. | |
1573 | - lr_offset is the offset of the saved lr | |
1574 | - cr_offset is the offset of the saved cr | |
0df8b418 | 1575 | - vrsave_offset is the offset of the saved vrsave register. */ |
6a16c029 | 1576 | |
7a78ae4e | 1577 | static CORE_ADDR |
be8626e0 MD |
1578 | skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, CORE_ADDR lim_pc, |
1579 | struct rs6000_framedata *fdata) | |
c906108c SS |
1580 | { |
1581 | CORE_ADDR orig_pc = pc; | |
55d05f3b | 1582 | CORE_ADDR last_prologue_pc = pc; |
6be8bc0c | 1583 | CORE_ADDR li_found_pc = 0; |
50fd1280 | 1584 | gdb_byte buf[4]; |
c906108c SS |
1585 | unsigned long op; |
1586 | long offset = 0; | |
6be8bc0c | 1587 | long vr_saved_offset = 0; |
482ca3f5 KB |
1588 | int lr_reg = -1; |
1589 | int cr_reg = -1; | |
6be8bc0c | 1590 | int vr_reg = -1; |
96ff0de4 EZ |
1591 | int ev_reg = -1; |
1592 | long ev_offset = 0; | |
6be8bc0c | 1593 | int vrsave_reg = -1; |
c906108c SS |
1594 | int reg; |
1595 | int framep = 0; | |
1596 | int minimal_toc_loaded = 0; | |
ddb20c56 | 1597 | int prev_insn_was_prologue_insn = 1; |
55d05f3b | 1598 | int num_skip_non_prologue_insns = 0; |
773df3e5 | 1599 | int r0_contains_arg = 0; |
be8626e0 MD |
1600 | const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (gdbarch); |
1601 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
e17a4113 | 1602 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
c906108c | 1603 | |
ddb20c56 | 1604 | memset (fdata, 0, sizeof (struct rs6000_framedata)); |
c906108c SS |
1605 | fdata->saved_gpr = -1; |
1606 | fdata->saved_fpr = -1; | |
6be8bc0c | 1607 | fdata->saved_vr = -1; |
96ff0de4 | 1608 | fdata->saved_ev = -1; |
c906108c SS |
1609 | fdata->alloca_reg = -1; |
1610 | fdata->frameless = 1; | |
1611 | fdata->nosavedpc = 1; | |
46a9b8ed | 1612 | fdata->lr_register = -1; |
c906108c | 1613 | |
e17a4113 | 1614 | pc = rs6000_skip_stack_check (gdbarch, pc); |
de9f48f0 JG |
1615 | if (pc >= lim_pc) |
1616 | pc = lim_pc; | |
1617 | ||
55d05f3b | 1618 | for (;; pc += 4) |
c906108c | 1619 | { |
ddb20c56 KB |
1620 | /* Sometimes it isn't clear if an instruction is a prologue |
1621 | instruction or not. When we encounter one of these ambiguous | |
1622 | cases, we'll set prev_insn_was_prologue_insn to 0 (false). | |
0df8b418 | 1623 | Otherwise, we'll assume that it really is a prologue instruction. */ |
ddb20c56 KB |
1624 | if (prev_insn_was_prologue_insn) |
1625 | last_prologue_pc = pc; | |
55d05f3b KB |
1626 | |
1627 | /* Stop scanning if we've hit the limit. */ | |
4e463ff5 | 1628 | if (pc >= lim_pc) |
55d05f3b KB |
1629 | break; |
1630 | ||
ddb20c56 KB |
1631 | prev_insn_was_prologue_insn = 1; |
1632 | ||
55d05f3b | 1633 | /* Fetch the instruction and convert it to an integer. */ |
ddb20c56 KB |
1634 | if (target_read_memory (pc, buf, 4)) |
1635 | break; | |
e17a4113 | 1636 | op = extract_unsigned_integer (buf, 4, byte_order); |
c906108c | 1637 | |
c5aa993b JM |
1638 | if ((op & 0xfc1fffff) == 0x7c0802a6) |
1639 | { /* mflr Rx */ | |
43b1ab88 AC |
1640 | /* Since shared library / PIC code, which needs to get its |
1641 | address at runtime, can appear to save more than one link | |
1642 | register vis: | |
1643 | ||
1644 | *INDENT-OFF* | |
1645 | stwu r1,-304(r1) | |
1646 | mflr r3 | |
1647 | bl 0xff570d0 (blrl) | |
1648 | stw r30,296(r1) | |
1649 | mflr r30 | |
1650 | stw r31,300(r1) | |
1651 | stw r3,308(r1); | |
1652 | ... | |
1653 | *INDENT-ON* | |
1654 | ||
1655 | remember just the first one, but skip over additional | |
1656 | ones. */ | |
721d14ba | 1657 | if (lr_reg == -1) |
46a9b8ed | 1658 | lr_reg = (op & 0x03e00000) >> 21; |
773df3e5 JB |
1659 | if (lr_reg == 0) |
1660 | r0_contains_arg = 0; | |
c5aa993b | 1661 | continue; |
c5aa993b JM |
1662 | } |
1663 | else if ((op & 0xfc1fffff) == 0x7c000026) | |
1664 | { /* mfcr Rx */ | |
98f08d3d | 1665 | cr_reg = (op & 0x03e00000); |
773df3e5 JB |
1666 | if (cr_reg == 0) |
1667 | r0_contains_arg = 0; | |
c5aa993b | 1668 | continue; |
c906108c | 1669 | |
c906108c | 1670 | } |
c5aa993b JM |
1671 | else if ((op & 0xfc1f0000) == 0xd8010000) |
1672 | { /* stfd Rx,NUM(r1) */ | |
1673 | reg = GET_SRC_REG (op); | |
1674 | if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg) | |
1675 | { | |
1676 | fdata->saved_fpr = reg; | |
1677 | fdata->fpr_offset = SIGNED_SHORT (op) + offset; | |
1678 | } | |
1679 | continue; | |
c906108c | 1680 | |
c5aa993b JM |
1681 | } |
1682 | else if (((op & 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */ | |
7a78ae4e ND |
1683 | (((op & 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */ |
1684 | (op & 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */ | |
1685 | (op & 0x03e00000) >= 0x01a00000)) /* rx >= r13 */ | |
c5aa993b JM |
1686 | { |
1687 | ||
1688 | reg = GET_SRC_REG (op); | |
46a9b8ed DJ |
1689 | if ((op & 0xfc1f0000) == 0xbc010000) |
1690 | fdata->gpr_mask |= ~((1U << reg) - 1); | |
1691 | else | |
1692 | fdata->gpr_mask |= 1U << reg; | |
c5aa993b JM |
1693 | if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg) |
1694 | { | |
1695 | fdata->saved_gpr = reg; | |
7a78ae4e | 1696 | if ((op & 0xfc1f0003) == 0xf8010000) |
98f08d3d | 1697 | op &= ~3UL; |
c5aa993b JM |
1698 | fdata->gpr_offset = SIGNED_SHORT (op) + offset; |
1699 | } | |
1700 | continue; | |
c906108c | 1701 | |
ddb20c56 | 1702 | } |
ef1bc9e7 AM |
1703 | else if ((op & 0xffff0000) == 0x3c4c0000 |
1704 | || (op & 0xffff0000) == 0x3c400000 | |
1705 | || (op & 0xffff0000) == 0x38420000) | |
1706 | { | |
1707 | /* . 0: addis 2,12,.TOC.-0b@ha | |
1708 | . addi 2,2,.TOC.-0b@l | |
1709 | or | |
1710 | . lis 2,.TOC.@ha | |
1711 | . addi 2,2,.TOC.@l | |
1712 | used by ELFv2 global entry points to set up r2. */ | |
1713 | continue; | |
1714 | } | |
1715 | else if (op == 0x60000000) | |
ddb20c56 | 1716 | { |
96ff0de4 | 1717 | /* nop */ |
ddb20c56 KB |
1718 | /* Allow nops in the prologue, but do not consider them to |
1719 | be part of the prologue unless followed by other prologue | |
0df8b418 | 1720 | instructions. */ |
ddb20c56 KB |
1721 | prev_insn_was_prologue_insn = 0; |
1722 | continue; | |
1723 | ||
c906108c | 1724 | } |
c5aa993b | 1725 | else if ((op & 0xffff0000) == 0x3c000000) |
ef1bc9e7 | 1726 | { /* addis 0,0,NUM, used for >= 32k frames */ |
c5aa993b JM |
1727 | fdata->offset = (op & 0x0000ffff) << 16; |
1728 | fdata->frameless = 0; | |
773df3e5 | 1729 | r0_contains_arg = 0; |
c5aa993b JM |
1730 | continue; |
1731 | ||
1732 | } | |
1733 | else if ((op & 0xffff0000) == 0x60000000) | |
ef1bc9e7 | 1734 | { /* ori 0,0,NUM, 2nd half of >= 32k frames */ |
c5aa993b JM |
1735 | fdata->offset |= (op & 0x0000ffff); |
1736 | fdata->frameless = 0; | |
773df3e5 | 1737 | r0_contains_arg = 0; |
c5aa993b JM |
1738 | continue; |
1739 | ||
1740 | } | |
be723e22 | 1741 | else if (lr_reg >= 0 && |
98f08d3d KB |
1742 | /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */ |
1743 | (((op & 0xffff0000) == (lr_reg | 0xf8010000)) || | |
1744 | /* stw Rx, NUM(r1) */ | |
1745 | ((op & 0xffff0000) == (lr_reg | 0x90010000)) || | |
1746 | /* stwu Rx, NUM(r1) */ | |
1747 | ((op & 0xffff0000) == (lr_reg | 0x94010000)))) | |
1748 | { /* where Rx == lr */ | |
1749 | fdata->lr_offset = offset; | |
c5aa993b | 1750 | fdata->nosavedpc = 0; |
be723e22 MS |
1751 | /* Invalidate lr_reg, but don't set it to -1. |
1752 | That would mean that it had never been set. */ | |
1753 | lr_reg = -2; | |
98f08d3d KB |
1754 | if ((op & 0xfc000003) == 0xf8000000 || /* std */ |
1755 | (op & 0xfc000000) == 0x90000000) /* stw */ | |
1756 | { | |
1757 | /* Does not update r1, so add displacement to lr_offset. */ | |
1758 | fdata->lr_offset += SIGNED_SHORT (op); | |
1759 | } | |
c5aa993b JM |
1760 | continue; |
1761 | ||
1762 | } | |
be723e22 | 1763 | else if (cr_reg >= 0 && |
98f08d3d KB |
1764 | /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */ |
1765 | (((op & 0xffff0000) == (cr_reg | 0xf8010000)) || | |
1766 | /* stw Rx, NUM(r1) */ | |
1767 | ((op & 0xffff0000) == (cr_reg | 0x90010000)) || | |
1768 | /* stwu Rx, NUM(r1) */ | |
1769 | ((op & 0xffff0000) == (cr_reg | 0x94010000)))) | |
1770 | { /* where Rx == cr */ | |
1771 | fdata->cr_offset = offset; | |
be723e22 MS |
1772 | /* Invalidate cr_reg, but don't set it to -1. |
1773 | That would mean that it had never been set. */ | |
1774 | cr_reg = -2; | |
98f08d3d KB |
1775 | if ((op & 0xfc000003) == 0xf8000000 || |
1776 | (op & 0xfc000000) == 0x90000000) | |
1777 | { | |
1778 | /* Does not update r1, so add displacement to cr_offset. */ | |
1779 | fdata->cr_offset += SIGNED_SHORT (op); | |
1780 | } | |
c5aa993b JM |
1781 | continue; |
1782 | ||
1783 | } | |
721d14ba DJ |
1784 | else if ((op & 0xfe80ffff) == 0x42800005 && lr_reg != -1) |
1785 | { | |
1786 | /* bcl 20,xx,.+4 is used to get the current PC, with or without | |
1787 | prediction bits. If the LR has already been saved, we can | |
1788 | skip it. */ | |
1789 | continue; | |
1790 | } | |
c5aa993b JM |
1791 | else if (op == 0x48000005) |
1792 | { /* bl .+4 used in | |
1793 | -mrelocatable */ | |
46a9b8ed | 1794 | fdata->used_bl = 1; |
c5aa993b JM |
1795 | continue; |
1796 | ||
1797 | } | |
1798 | else if (op == 0x48000004) | |
1799 | { /* b .+4 (xlc) */ | |
1800 | break; | |
1801 | ||
c5aa993b | 1802 | } |
6be8bc0c EZ |
1803 | else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used |
1804 | in V.4 -mminimal-toc */ | |
c5aa993b JM |
1805 | (op & 0xffff0000) == 0x3bde0000) |
1806 | { /* addi 30,30,foo@l */ | |
1807 | continue; | |
c906108c | 1808 | |
c5aa993b JM |
1809 | } |
1810 | else if ((op & 0xfc000001) == 0x48000001) | |
1811 | { /* bl foo, | |
0df8b418 | 1812 | to save fprs??? */ |
c906108c | 1813 | |
c5aa993b | 1814 | fdata->frameless = 0; |
3c77c82a DJ |
1815 | |
1816 | /* If the return address has already been saved, we can skip | |
1817 | calls to blrl (for PIC). */ | |
e17a4113 | 1818 | if (lr_reg != -1 && bl_to_blrl_insn_p (pc, op, byte_order)) |
46a9b8ed DJ |
1819 | { |
1820 | fdata->used_bl = 1; | |
1821 | continue; | |
1822 | } | |
3c77c82a | 1823 | |
6be8bc0c | 1824 | /* Don't skip over the subroutine call if it is not within |
ebd98106 FF |
1825 | the first three instructions of the prologue and either |
1826 | we have no line table information or the line info tells | |
1827 | us that the subroutine call is not part of the line | |
1828 | associated with the prologue. */ | |
c5aa993b | 1829 | if ((pc - orig_pc) > 8) |
ebd98106 FF |
1830 | { |
1831 | struct symtab_and_line prologue_sal = find_pc_line (orig_pc, 0); | |
1832 | struct symtab_and_line this_sal = find_pc_line (pc, 0); | |
1833 | ||
0df8b418 MS |
1834 | if ((prologue_sal.line == 0) |
1835 | || (prologue_sal.line != this_sal.line)) | |
ebd98106 FF |
1836 | break; |
1837 | } | |
c5aa993b | 1838 | |
e17a4113 | 1839 | op = read_memory_integer (pc + 4, 4, byte_order); |
c5aa993b | 1840 | |
6be8bc0c EZ |
1841 | /* At this point, make sure this is not a trampoline |
1842 | function (a function that simply calls another functions, | |
1843 | and nothing else). If the next is not a nop, this branch | |
0df8b418 | 1844 | was part of the function prologue. */ |
c5aa993b JM |
1845 | |
1846 | if (op == 0x4def7b82 || op == 0) /* crorc 15, 15, 15 */ | |
0df8b418 MS |
1847 | break; /* Don't skip over |
1848 | this branch. */ | |
c5aa993b | 1849 | |
46a9b8ed DJ |
1850 | fdata->used_bl = 1; |
1851 | continue; | |
c5aa993b | 1852 | } |
98f08d3d KB |
1853 | /* update stack pointer */ |
1854 | else if ((op & 0xfc1f0000) == 0x94010000) | |
1855 | { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */ | |
c5aa993b JM |
1856 | fdata->frameless = 0; |
1857 | fdata->offset = SIGNED_SHORT (op); | |
1858 | offset = fdata->offset; | |
1859 | continue; | |
c5aa993b | 1860 | } |
98f08d3d KB |
1861 | else if ((op & 0xfc1f016a) == 0x7c01016e) |
1862 | { /* stwux rX,r1,rY */ | |
0df8b418 | 1863 | /* No way to figure out what r1 is going to be. */ |
98f08d3d KB |
1864 | fdata->frameless = 0; |
1865 | offset = fdata->offset; | |
1866 | continue; | |
1867 | } | |
1868 | else if ((op & 0xfc1f0003) == 0xf8010001) | |
1869 | { /* stdu rX,NUM(r1) */ | |
1870 | fdata->frameless = 0; | |
1871 | fdata->offset = SIGNED_SHORT (op & ~3UL); | |
1872 | offset = fdata->offset; | |
1873 | continue; | |
1874 | } | |
1875 | else if ((op & 0xfc1f016a) == 0x7c01016a) | |
1876 | { /* stdux rX,r1,rY */ | |
0df8b418 | 1877 | /* No way to figure out what r1 is going to be. */ |
c5aa993b JM |
1878 | fdata->frameless = 0; |
1879 | offset = fdata->offset; | |
1880 | continue; | |
c5aa993b | 1881 | } |
7313566f FF |
1882 | else if ((op & 0xffff0000) == 0x38210000) |
1883 | { /* addi r1,r1,SIMM */ | |
1884 | fdata->frameless = 0; | |
1885 | fdata->offset += SIGNED_SHORT (op); | |
1886 | offset = fdata->offset; | |
1887 | continue; | |
1888 | } | |
4e463ff5 DJ |
1889 | /* Load up minimal toc pointer. Do not treat an epilogue restore |
1890 | of r31 as a minimal TOC load. */ | |
0df8b418 MS |
1891 | else if (((op >> 22) == 0x20f || /* l r31,... or l r30,... */ |
1892 | (op >> 22) == 0x3af) /* ld r31,... or ld r30,... */ | |
4e463ff5 | 1893 | && !framep |
c5aa993b | 1894 | && !minimal_toc_loaded) |
98f08d3d | 1895 | { |
c5aa993b JM |
1896 | minimal_toc_loaded = 1; |
1897 | continue; | |
1898 | ||
f6077098 KB |
1899 | /* move parameters from argument registers to local variable |
1900 | registers */ | |
1901 | } | |
1902 | else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */ | |
1903 | (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */ | |
1904 | (((op >> 21) & 31) <= 10) && | |
0df8b418 MS |
1905 | ((long) ((op >> 16) & 31) |
1906 | >= fdata->saved_gpr)) /* Rx: local var reg */ | |
f6077098 KB |
1907 | { |
1908 | continue; | |
1909 | ||
c5aa993b JM |
1910 | /* store parameters in stack */ |
1911 | } | |
e802b915 | 1912 | /* Move parameters from argument registers to temporary register. */ |
773df3e5 | 1913 | else if (store_param_on_stack_p (op, framep, &r0_contains_arg)) |
e802b915 | 1914 | { |
c5aa993b JM |
1915 | continue; |
1916 | ||
1917 | /* Set up frame pointer */ | |
1918 | } | |
76219d77 JB |
1919 | else if (op == 0x603d0000) /* oril r29, r1, 0x0 */ |
1920 | { | |
1921 | fdata->frameless = 0; | |
1922 | framep = 1; | |
1923 | fdata->alloca_reg = (tdep->ppc_gp0_regnum + 29); | |
1924 | continue; | |
1925 | ||
1926 | /* Another way to set up the frame pointer. */ | |
1927 | } | |
c5aa993b JM |
1928 | else if (op == 0x603f0000 /* oril r31, r1, 0x0 */ |
1929 | || op == 0x7c3f0b78) | |
1930 | { /* mr r31, r1 */ | |
1931 | fdata->frameless = 0; | |
1932 | framep = 1; | |
6f99cb26 | 1933 | fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31); |
c5aa993b JM |
1934 | continue; |
1935 | ||
1936 | /* Another way to set up the frame pointer. */ | |
1937 | } | |
1938 | else if ((op & 0xfc1fffff) == 0x38010000) | |
1939 | { /* addi rX, r1, 0x0 */ | |
1940 | fdata->frameless = 0; | |
1941 | framep = 1; | |
6f99cb26 AC |
1942 | fdata->alloca_reg = (tdep->ppc_gp0_regnum |
1943 | + ((op & ~0x38010000) >> 21)); | |
c5aa993b | 1944 | continue; |
c5aa993b | 1945 | } |
6be8bc0c EZ |
1946 | /* AltiVec related instructions. */ |
1947 | /* Store the vrsave register (spr 256) in another register for | |
1948 | later manipulation, or load a register into the vrsave | |
1949 | register. 2 instructions are used: mfvrsave and | |
1950 | mtvrsave. They are shorthand notation for mfspr Rn, SPR256 | |
1951 | and mtspr SPR256, Rn. */ | |
1952 | /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110 | |
1953 | mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */ | |
1954 | else if ((op & 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */ | |
1955 | { | |
1956 | vrsave_reg = GET_SRC_REG (op); | |
1957 | continue; | |
1958 | } | |
1959 | else if ((op & 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */ | |
1960 | { | |
1961 | continue; | |
1962 | } | |
1963 | /* Store the register where vrsave was saved to onto the stack: | |
1964 | rS is the register where vrsave was stored in a previous | |
1965 | instruction. */ | |
1966 | /* 100100 sssss 00001 dddddddd dddddddd */ | |
1967 | else if ((op & 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */ | |
1968 | { | |
1969 | if (vrsave_reg == GET_SRC_REG (op)) | |
1970 | { | |
1971 | fdata->vrsave_offset = SIGNED_SHORT (op) + offset; | |
1972 | vrsave_reg = -1; | |
1973 | } | |
1974 | continue; | |
1975 | } | |
1976 | /* Compute the new value of vrsave, by modifying the register | |
1977 | where vrsave was saved to. */ | |
1978 | else if (((op & 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */ | |
1979 | || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */ | |
1980 | { | |
1981 | continue; | |
1982 | } | |
1983 | /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first | |
1984 | in a pair of insns to save the vector registers on the | |
1985 | stack. */ | |
1986 | /* 001110 00000 00000 iiii iiii iiii iiii */ | |
96ff0de4 EZ |
1987 | /* 001110 01110 00000 iiii iiii iiii iiii */ |
1988 | else if ((op & 0xffff0000) == 0x38000000 /* li r0, SIMM */ | |
1989 | || (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */ | |
6be8bc0c | 1990 | { |
773df3e5 JB |
1991 | if ((op & 0xffff0000) == 0x38000000) |
1992 | r0_contains_arg = 0; | |
6be8bc0c EZ |
1993 | li_found_pc = pc; |
1994 | vr_saved_offset = SIGNED_SHORT (op); | |
773df3e5 JB |
1995 | |
1996 | /* This insn by itself is not part of the prologue, unless | |
0df8b418 | 1997 | if part of the pair of insns mentioned above. So do not |
773df3e5 JB |
1998 | record this insn as part of the prologue yet. */ |
1999 | prev_insn_was_prologue_insn = 0; | |
6be8bc0c EZ |
2000 | } |
2001 | /* Store vector register S at (r31+r0) aligned to 16 bytes. */ | |
2002 | /* 011111 sssss 11111 00000 00111001110 */ | |
2003 | else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */ | |
2004 | { | |
2005 | if (pc == (li_found_pc + 4)) | |
2006 | { | |
2007 | vr_reg = GET_SRC_REG (op); | |
2008 | /* If this is the first vector reg to be saved, or if | |
2009 | it has a lower number than others previously seen, | |
2010 | reupdate the frame info. */ | |
2011 | if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg) | |
2012 | { | |
2013 | fdata->saved_vr = vr_reg; | |
2014 | fdata->vr_offset = vr_saved_offset + offset; | |
2015 | } | |
2016 | vr_saved_offset = -1; | |
2017 | vr_reg = -1; | |
2018 | li_found_pc = 0; | |
2019 | } | |
2020 | } | |
2021 | /* End AltiVec related instructions. */ | |
96ff0de4 EZ |
2022 | |
2023 | /* Start BookE related instructions. */ | |
2024 | /* Store gen register S at (r31+uimm). | |
2025 | Any register less than r13 is volatile, so we don't care. */ | |
2026 | /* 000100 sssss 11111 iiiii 01100100001 */ | |
2027 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
2028 | && (op & 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */ | |
2029 | { | |
2030 | if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */ | |
2031 | { | |
2032 | unsigned int imm; | |
2033 | ev_reg = GET_SRC_REG (op); | |
2034 | imm = (op >> 11) & 0x1f; | |
2035 | ev_offset = imm * 8; | |
2036 | /* If this is the first vector reg to be saved, or if | |
2037 | it has a lower number than others previously seen, | |
2038 | reupdate the frame info. */ | |
2039 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) | |
2040 | { | |
2041 | fdata->saved_ev = ev_reg; | |
2042 | fdata->ev_offset = ev_offset + offset; | |
2043 | } | |
2044 | } | |
2045 | continue; | |
2046 | } | |
2047 | /* Store gen register rS at (r1+rB). */ | |
2048 | /* 000100 sssss 00001 bbbbb 01100100000 */ | |
2049 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
2050 | && (op & 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */ | |
2051 | { | |
2052 | if (pc == (li_found_pc + 4)) | |
2053 | { | |
2054 | ev_reg = GET_SRC_REG (op); | |
2055 | /* If this is the first vector reg to be saved, or if | |
2056 | it has a lower number than others previously seen, | |
2057 | reupdate the frame info. */ | |
2058 | /* We know the contents of rB from the previous instruction. */ | |
2059 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) | |
2060 | { | |
2061 | fdata->saved_ev = ev_reg; | |
2062 | fdata->ev_offset = vr_saved_offset + offset; | |
2063 | } | |
2064 | vr_saved_offset = -1; | |
2065 | ev_reg = -1; | |
2066 | li_found_pc = 0; | |
2067 | } | |
2068 | continue; | |
2069 | } | |
2070 | /* Store gen register r31 at (rA+uimm). */ | |
2071 | /* 000100 11111 aaaaa iiiii 01100100001 */ | |
2072 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
2073 | && (op & 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */ | |
2074 | { | |
2075 | /* Wwe know that the source register is 31 already, but | |
2076 | it can't hurt to compute it. */ | |
2077 | ev_reg = GET_SRC_REG (op); | |
2078 | ev_offset = ((op >> 11) & 0x1f) * 8; | |
2079 | /* If this is the first vector reg to be saved, or if | |
2080 | it has a lower number than others previously seen, | |
2081 | reupdate the frame info. */ | |
2082 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) | |
2083 | { | |
2084 | fdata->saved_ev = ev_reg; | |
2085 | fdata->ev_offset = ev_offset + offset; | |
2086 | } | |
2087 | ||
2088 | continue; | |
2089 | } | |
2090 | /* Store gen register S at (r31+r0). | |
2091 | Store param on stack when offset from SP bigger than 4 bytes. */ | |
2092 | /* 000100 sssss 11111 00000 01100100000 */ | |
2093 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
2094 | && (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */ | |
2095 | { | |
2096 | if (pc == (li_found_pc + 4)) | |
2097 | { | |
2098 | if ((op & 0x03e00000) >= 0x01a00000) | |
2099 | { | |
2100 | ev_reg = GET_SRC_REG (op); | |
2101 | /* If this is the first vector reg to be saved, or if | |
2102 | it has a lower number than others previously seen, | |
2103 | reupdate the frame info. */ | |
2104 | /* We know the contents of r0 from the previous | |
2105 | instruction. */ | |
2106 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) | |
2107 | { | |
2108 | fdata->saved_ev = ev_reg; | |
2109 | fdata->ev_offset = vr_saved_offset + offset; | |
2110 | } | |
2111 | ev_reg = -1; | |
2112 | } | |
2113 | vr_saved_offset = -1; | |
2114 | li_found_pc = 0; | |
2115 | continue; | |
2116 | } | |
2117 | } | |
2118 | /* End BookE related instructions. */ | |
2119 | ||
c5aa993b JM |
2120 | else |
2121 | { | |
46a9b8ed DJ |
2122 | unsigned int all_mask = ~((1U << fdata->saved_gpr) - 1); |
2123 | ||
55d05f3b KB |
2124 | /* Not a recognized prologue instruction. |
2125 | Handle optimizer code motions into the prologue by continuing | |
2126 | the search if we have no valid frame yet or if the return | |
46a9b8ed DJ |
2127 | address is not yet saved in the frame. Also skip instructions |
2128 | if some of the GPRs expected to be saved are not yet saved. */ | |
2129 | if (fdata->frameless == 0 && fdata->nosavedpc == 0 | |
2130 | && (fdata->gpr_mask & all_mask) == all_mask) | |
55d05f3b KB |
2131 | break; |
2132 | ||
2133 | if (op == 0x4e800020 /* blr */ | |
2134 | || op == 0x4e800420) /* bctr */ | |
2135 | /* Do not scan past epilogue in frameless functions or | |
2136 | trampolines. */ | |
2137 | break; | |
2138 | if ((op & 0xf4000000) == 0x40000000) /* bxx */ | |
64366f1c | 2139 | /* Never skip branches. */ |
55d05f3b KB |
2140 | break; |
2141 | ||
2142 | if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns) | |
2143 | /* Do not scan too many insns, scanning insns is expensive with | |
2144 | remote targets. */ | |
2145 | break; | |
2146 | ||
2147 | /* Continue scanning. */ | |
2148 | prev_insn_was_prologue_insn = 0; | |
2149 | continue; | |
c5aa993b | 2150 | } |
c906108c SS |
2151 | } |
2152 | ||
2153 | #if 0 | |
2154 | /* I have problems with skipping over __main() that I need to address | |
0df8b418 | 2155 | * sometime. Previously, I used to use misc_function_vector which |
c906108c SS |
2156 | * didn't work as well as I wanted to be. -MGO */ |
2157 | ||
2158 | /* If the first thing after skipping a prolog is a branch to a function, | |
2159 | this might be a call to an initializer in main(), introduced by gcc2. | |
64366f1c | 2160 | We'd like to skip over it as well. Fortunately, xlc does some extra |
c906108c | 2161 | work before calling a function right after a prologue, thus we can |
64366f1c | 2162 | single out such gcc2 behaviour. */ |
c906108c | 2163 | |
c906108c | 2164 | |
c5aa993b | 2165 | if ((op & 0xfc000001) == 0x48000001) |
0df8b418 | 2166 | { /* bl foo, an initializer function? */ |
e17a4113 | 2167 | op = read_memory_integer (pc + 4, 4, byte_order); |
c5aa993b JM |
2168 | |
2169 | if (op == 0x4def7b82) | |
2170 | { /* cror 0xf, 0xf, 0xf (nop) */ | |
c906108c | 2171 | |
64366f1c EZ |
2172 | /* Check and see if we are in main. If so, skip over this |
2173 | initializer function as well. */ | |
c906108c | 2174 | |
c5aa993b | 2175 | tmp = find_pc_misc_function (pc); |
6314a349 AC |
2176 | if (tmp >= 0 |
2177 | && strcmp (misc_function_vector[tmp].name, main_name ()) == 0) | |
c5aa993b JM |
2178 | return pc + 8; |
2179 | } | |
c906108c | 2180 | } |
c906108c | 2181 | #endif /* 0 */ |
c5aa993b | 2182 | |
46a9b8ed DJ |
2183 | if (pc == lim_pc && lr_reg >= 0) |
2184 | fdata->lr_register = lr_reg; | |
2185 | ||
c5aa993b | 2186 | fdata->offset = -fdata->offset; |
ddb20c56 | 2187 | return last_prologue_pc; |
c906108c SS |
2188 | } |
2189 | ||
7a78ae4e | 2190 | static CORE_ADDR |
4a7622d1 | 2191 | rs6000_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
c906108c | 2192 | { |
4a7622d1 | 2193 | struct rs6000_framedata frame; |
e3acb115 | 2194 | CORE_ADDR limit_pc, func_addr, func_end_addr = 0; |
c906108c | 2195 | |
4a7622d1 UW |
2196 | /* See if we can determine the end of the prologue via the symbol table. |
2197 | If so, then return either PC, or the PC after the prologue, whichever | |
2198 | is greater. */ | |
e3acb115 | 2199 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end_addr)) |
c5aa993b | 2200 | { |
d80b854b UW |
2201 | CORE_ADDR post_prologue_pc |
2202 | = skip_prologue_using_sal (gdbarch, func_addr); | |
4a7622d1 | 2203 | if (post_prologue_pc != 0) |
325fac50 | 2204 | return std::max (pc, post_prologue_pc); |
c906108c | 2205 | } |
c906108c | 2206 | |
4a7622d1 UW |
2207 | /* Can't determine prologue from the symbol table, need to examine |
2208 | instructions. */ | |
c906108c | 2209 | |
4a7622d1 UW |
2210 | /* Find an upper limit on the function prologue using the debug |
2211 | information. If the debug information could not be used to provide | |
2212 | that bound, then use an arbitrary large number as the upper bound. */ | |
d80b854b | 2213 | limit_pc = skip_prologue_using_sal (gdbarch, pc); |
4a7622d1 UW |
2214 | if (limit_pc == 0) |
2215 | limit_pc = pc + 100; /* Magic. */ | |
794a477a | 2216 | |
e3acb115 JB |
2217 | /* Do not allow limit_pc to be past the function end, if we know |
2218 | where that end is... */ | |
2219 | if (func_end_addr && limit_pc > func_end_addr) | |
2220 | limit_pc = func_end_addr; | |
2221 | ||
4a7622d1 UW |
2222 | pc = skip_prologue (gdbarch, pc, limit_pc, &frame); |
2223 | return pc; | |
c906108c | 2224 | } |
c906108c | 2225 | |
8ab3d180 KB |
2226 | /* When compiling for EABI, some versions of GCC emit a call to __eabi |
2227 | in the prologue of main(). | |
2228 | ||
2229 | The function below examines the code pointed at by PC and checks to | |
2230 | see if it corresponds to a call to __eabi. If so, it returns the | |
2231 | address of the instruction following that call. Otherwise, it simply | |
2232 | returns PC. */ | |
2233 | ||
63807e1d | 2234 | static CORE_ADDR |
8ab3d180 KB |
2235 | rs6000_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
2236 | { | |
e17a4113 | 2237 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
8ab3d180 KB |
2238 | gdb_byte buf[4]; |
2239 | unsigned long op; | |
2240 | ||
2241 | if (target_read_memory (pc, buf, 4)) | |
2242 | return pc; | |
e17a4113 | 2243 | op = extract_unsigned_integer (buf, 4, byte_order); |
8ab3d180 KB |
2244 | |
2245 | if ((op & BL_MASK) == BL_INSTRUCTION) | |
2246 | { | |
2247 | CORE_ADDR displ = op & BL_DISPLACEMENT_MASK; | |
2248 | CORE_ADDR call_dest = pc + 4 + displ; | |
7cbd4a93 | 2249 | struct bound_minimal_symbol s = lookup_minimal_symbol_by_pc (call_dest); |
8ab3d180 KB |
2250 | |
2251 | /* We check for ___eabi (three leading underscores) in addition | |
2252 | to __eabi in case the GCC option "-fleading-underscore" was | |
2253 | used to compile the program. */ | |
7cbd4a93 | 2254 | if (s.minsym != NULL |
efd66ac6 TT |
2255 | && MSYMBOL_LINKAGE_NAME (s.minsym) != NULL |
2256 | && (strcmp (MSYMBOL_LINKAGE_NAME (s.minsym), "__eabi") == 0 | |
2257 | || strcmp (MSYMBOL_LINKAGE_NAME (s.minsym), "___eabi") == 0)) | |
8ab3d180 KB |
2258 | pc += 4; |
2259 | } | |
2260 | return pc; | |
2261 | } | |
383f0f5b | 2262 | |
4a7622d1 UW |
2263 | /* All the ABI's require 16 byte alignment. */ |
2264 | static CORE_ADDR | |
2265 | rs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
2266 | { | |
2267 | return (addr & -16); | |
c906108c SS |
2268 | } |
2269 | ||
977adac5 ND |
2270 | /* Return whether handle_inferior_event() should proceed through code |
2271 | starting at PC in function NAME when stepping. | |
2272 | ||
2273 | The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to | |
2274 | handle memory references that are too distant to fit in instructions | |
2275 | generated by the compiler. For example, if 'foo' in the following | |
2276 | instruction: | |
2277 | ||
2278 | lwz r9,foo(r2) | |
2279 | ||
2280 | is greater than 32767, the linker might replace the lwz with a branch to | |
2281 | somewhere in @FIX1 that does the load in 2 instructions and then branches | |
2282 | back to where execution should continue. | |
2283 | ||
2284 | GDB should silently step over @FIX code, just like AIX dbx does. | |
2ec664f5 MS |
2285 | Unfortunately, the linker uses the "b" instruction for the |
2286 | branches, meaning that the link register doesn't get set. | |
2287 | Therefore, GDB's usual step_over_function () mechanism won't work. | |
977adac5 | 2288 | |
e76f05fa UW |
2289 | Instead, use the gdbarch_skip_trampoline_code and |
2290 | gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past | |
2ec664f5 | 2291 | @FIX code. */ |
977adac5 | 2292 | |
63807e1d | 2293 | static int |
e17a4113 | 2294 | rs6000_in_solib_return_trampoline (struct gdbarch *gdbarch, |
2c02bd72 | 2295 | CORE_ADDR pc, const char *name) |
977adac5 | 2296 | { |
61012eef | 2297 | return name && startswith (name, "@FIX"); |
977adac5 ND |
2298 | } |
2299 | ||
2300 | /* Skip code that the user doesn't want to see when stepping: | |
2301 | ||
2302 | 1. Indirect function calls use a piece of trampoline code to do context | |
2303 | switching, i.e. to set the new TOC table. Skip such code if we are on | |
2304 | its first instruction (as when we have single-stepped to here). | |
2305 | ||
2306 | 2. Skip shared library trampoline code (which is different from | |
c906108c | 2307 | indirect function call trampolines). |
977adac5 ND |
2308 | |
2309 | 3. Skip bigtoc fixup code. | |
2310 | ||
c906108c | 2311 | Result is desired PC to step until, or NULL if we are not in |
977adac5 | 2312 | code that should be skipped. */ |
c906108c | 2313 | |
63807e1d | 2314 | static CORE_ADDR |
52f729a7 | 2315 | rs6000_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 2316 | { |
e17a4113 UW |
2317 | struct gdbarch *gdbarch = get_frame_arch (frame); |
2318 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2319 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
52f0bd74 | 2320 | unsigned int ii, op; |
977adac5 | 2321 | int rel; |
c906108c | 2322 | CORE_ADDR solib_target_pc; |
7cbd4a93 | 2323 | struct bound_minimal_symbol msymbol; |
c906108c | 2324 | |
c5aa993b JM |
2325 | static unsigned trampoline_code[] = |
2326 | { | |
2327 | 0x800b0000, /* l r0,0x0(r11) */ | |
2328 | 0x90410014, /* st r2,0x14(r1) */ | |
2329 | 0x7c0903a6, /* mtctr r0 */ | |
2330 | 0x804b0004, /* l r2,0x4(r11) */ | |
2331 | 0x816b0008, /* l r11,0x8(r11) */ | |
2332 | 0x4e800420, /* bctr */ | |
2333 | 0x4e800020, /* br */ | |
2334 | 0 | |
c906108c SS |
2335 | }; |
2336 | ||
977adac5 ND |
2337 | /* Check for bigtoc fixup code. */ |
2338 | msymbol = lookup_minimal_symbol_by_pc (pc); | |
7cbd4a93 | 2339 | if (msymbol.minsym |
e17a4113 | 2340 | && rs6000_in_solib_return_trampoline (gdbarch, pc, |
efd66ac6 | 2341 | MSYMBOL_LINKAGE_NAME (msymbol.minsym))) |
977adac5 ND |
2342 | { |
2343 | /* Double-check that the third instruction from PC is relative "b". */ | |
e17a4113 | 2344 | op = read_memory_integer (pc + 8, 4, byte_order); |
977adac5 ND |
2345 | if ((op & 0xfc000003) == 0x48000000) |
2346 | { | |
2347 | /* Extract bits 6-29 as a signed 24-bit relative word address and | |
2348 | add it to the containing PC. */ | |
2349 | rel = ((int)(op << 6) >> 6); | |
2350 | return pc + 8 + rel; | |
2351 | } | |
2352 | } | |
2353 | ||
c906108c | 2354 | /* If pc is in a shared library trampoline, return its target. */ |
52f729a7 | 2355 | solib_target_pc = find_solib_trampoline_target (frame, pc); |
c906108c SS |
2356 | if (solib_target_pc) |
2357 | return solib_target_pc; | |
2358 | ||
c5aa993b JM |
2359 | for (ii = 0; trampoline_code[ii]; ++ii) |
2360 | { | |
e17a4113 | 2361 | op = read_memory_integer (pc + (ii * 4), 4, byte_order); |
c5aa993b JM |
2362 | if (op != trampoline_code[ii]) |
2363 | return 0; | |
2364 | } | |
0df8b418 MS |
2365 | ii = get_frame_register_unsigned (frame, 11); /* r11 holds destination |
2366 | addr. */ | |
e17a4113 | 2367 | pc = read_memory_unsigned_integer (ii, tdep->wordsize, byte_order); |
c906108c SS |
2368 | return pc; |
2369 | } | |
2370 | ||
794ac428 UW |
2371 | /* ISA-specific vector types. */ |
2372 | ||
2373 | static struct type * | |
2374 | rs6000_builtin_type_vec64 (struct gdbarch *gdbarch) | |
2375 | { | |
2376 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2377 | ||
2378 | if (!tdep->ppc_builtin_type_vec64) | |
2379 | { | |
df4df182 UW |
2380 | const struct builtin_type *bt = builtin_type (gdbarch); |
2381 | ||
794ac428 UW |
2382 | /* The type we're building is this: */ |
2383 | #if 0 | |
2384 | union __gdb_builtin_type_vec64 | |
2385 | { | |
2386 | int64_t uint64; | |
2387 | float v2_float[2]; | |
2388 | int32_t v2_int32[2]; | |
2389 | int16_t v4_int16[4]; | |
2390 | int8_t v8_int8[8]; | |
2391 | }; | |
2392 | #endif | |
2393 | ||
2394 | struct type *t; | |
2395 | ||
e9bb382b UW |
2396 | t = arch_composite_type (gdbarch, |
2397 | "__ppc_builtin_type_vec64", TYPE_CODE_UNION); | |
df4df182 | 2398 | append_composite_type_field (t, "uint64", bt->builtin_int64); |
794ac428 | 2399 | append_composite_type_field (t, "v2_float", |
df4df182 | 2400 | init_vector_type (bt->builtin_float, 2)); |
794ac428 | 2401 | append_composite_type_field (t, "v2_int32", |
df4df182 | 2402 | init_vector_type (bt->builtin_int32, 2)); |
794ac428 | 2403 | append_composite_type_field (t, "v4_int16", |
df4df182 | 2404 | init_vector_type (bt->builtin_int16, 4)); |
794ac428 | 2405 | append_composite_type_field (t, "v8_int8", |
df4df182 | 2406 | init_vector_type (bt->builtin_int8, 8)); |
794ac428 | 2407 | |
876cecd0 | 2408 | TYPE_VECTOR (t) = 1; |
794ac428 UW |
2409 | TYPE_NAME (t) = "ppc_builtin_type_vec64"; |
2410 | tdep->ppc_builtin_type_vec64 = t; | |
2411 | } | |
2412 | ||
2413 | return tdep->ppc_builtin_type_vec64; | |
2414 | } | |
2415 | ||
604c2f83 LM |
2416 | /* Vector 128 type. */ |
2417 | ||
2418 | static struct type * | |
2419 | rs6000_builtin_type_vec128 (struct gdbarch *gdbarch) | |
2420 | { | |
2421 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2422 | ||
2423 | if (!tdep->ppc_builtin_type_vec128) | |
2424 | { | |
df4df182 UW |
2425 | const struct builtin_type *bt = builtin_type (gdbarch); |
2426 | ||
604c2f83 LM |
2427 | /* The type we're building is this |
2428 | ||
2429 | type = union __ppc_builtin_type_vec128 { | |
2430 | uint128_t uint128; | |
db9f5df8 | 2431 | double v2_double[2]; |
604c2f83 LM |
2432 | float v4_float[4]; |
2433 | int32_t v4_int32[4]; | |
2434 | int16_t v8_int16[8]; | |
2435 | int8_t v16_int8[16]; | |
2436 | } | |
2437 | */ | |
2438 | ||
2439 | struct type *t; | |
2440 | ||
e9bb382b UW |
2441 | t = arch_composite_type (gdbarch, |
2442 | "__ppc_builtin_type_vec128", TYPE_CODE_UNION); | |
df4df182 | 2443 | append_composite_type_field (t, "uint128", bt->builtin_uint128); |
db9f5df8 UW |
2444 | append_composite_type_field (t, "v2_double", |
2445 | init_vector_type (bt->builtin_double, 2)); | |
604c2f83 | 2446 | append_composite_type_field (t, "v4_float", |
df4df182 | 2447 | init_vector_type (bt->builtin_float, 4)); |
604c2f83 | 2448 | append_composite_type_field (t, "v4_int32", |
df4df182 | 2449 | init_vector_type (bt->builtin_int32, 4)); |
604c2f83 | 2450 | append_composite_type_field (t, "v8_int16", |
df4df182 | 2451 | init_vector_type (bt->builtin_int16, 8)); |
604c2f83 | 2452 | append_composite_type_field (t, "v16_int8", |
df4df182 | 2453 | init_vector_type (bt->builtin_int8, 16)); |
604c2f83 | 2454 | |
803e1097 | 2455 | TYPE_VECTOR (t) = 1; |
604c2f83 LM |
2456 | TYPE_NAME (t) = "ppc_builtin_type_vec128"; |
2457 | tdep->ppc_builtin_type_vec128 = t; | |
2458 | } | |
2459 | ||
2460 | return tdep->ppc_builtin_type_vec128; | |
2461 | } | |
2462 | ||
7cc46491 DJ |
2463 | /* Return the name of register number REGNO, or the empty string if it |
2464 | is an anonymous register. */ | |
7a78ae4e | 2465 | |
fa88f677 | 2466 | static const char * |
d93859e2 | 2467 | rs6000_register_name (struct gdbarch *gdbarch, int regno) |
7a78ae4e | 2468 | { |
d93859e2 | 2469 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7a78ae4e | 2470 | |
7cc46491 DJ |
2471 | /* The upper half "registers" have names in the XML description, |
2472 | but we present only the low GPRs and the full 64-bit registers | |
2473 | to the user. */ | |
2474 | if (tdep->ppc_ev0_upper_regnum >= 0 | |
2475 | && tdep->ppc_ev0_upper_regnum <= regno | |
2476 | && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) | |
2477 | return ""; | |
2478 | ||
604c2f83 LM |
2479 | /* Hide the upper halves of the vs0~vs31 registers. */ |
2480 | if (tdep->ppc_vsr0_regnum >= 0 | |
2481 | && tdep->ppc_vsr0_upper_regnum <= regno | |
2482 | && regno < tdep->ppc_vsr0_upper_regnum + ppc_num_gprs) | |
2483 | return ""; | |
2484 | ||
7cc46491 | 2485 | /* Check if the SPE pseudo registers are available. */ |
5a9e69ba | 2486 | if (IS_SPE_PSEUDOREG (tdep, regno)) |
7cc46491 DJ |
2487 | { |
2488 | static const char *const spe_regnames[] = { | |
2489 | "ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7", | |
2490 | "ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15", | |
2491 | "ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23", | |
2492 | "ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31", | |
2493 | }; | |
2494 | return spe_regnames[regno - tdep->ppc_ev0_regnum]; | |
2495 | } | |
2496 | ||
f949c649 TJB |
2497 | /* Check if the decimal128 pseudo-registers are available. */ |
2498 | if (IS_DFP_PSEUDOREG (tdep, regno)) | |
2499 | { | |
2500 | static const char *const dfp128_regnames[] = { | |
2501 | "dl0", "dl1", "dl2", "dl3", | |
2502 | "dl4", "dl5", "dl6", "dl7", | |
2503 | "dl8", "dl9", "dl10", "dl11", | |
2504 | "dl12", "dl13", "dl14", "dl15" | |
2505 | }; | |
2506 | return dfp128_regnames[regno - tdep->ppc_dl0_regnum]; | |
2507 | } | |
2508 | ||
604c2f83 LM |
2509 | /* Check if this is a VSX pseudo-register. */ |
2510 | if (IS_VSX_PSEUDOREG (tdep, regno)) | |
2511 | { | |
2512 | static const char *const vsx_regnames[] = { | |
2513 | "vs0", "vs1", "vs2", "vs3", "vs4", "vs5", "vs6", "vs7", | |
2514 | "vs8", "vs9", "vs10", "vs11", "vs12", "vs13", "vs14", | |
2515 | "vs15", "vs16", "vs17", "vs18", "vs19", "vs20", "vs21", | |
2516 | "vs22", "vs23", "vs24", "vs25", "vs26", "vs27", "vs28", | |
2517 | "vs29", "vs30", "vs31", "vs32", "vs33", "vs34", "vs35", | |
2518 | "vs36", "vs37", "vs38", "vs39", "vs40", "vs41", "vs42", | |
2519 | "vs43", "vs44", "vs45", "vs46", "vs47", "vs48", "vs49", | |
2520 | "vs50", "vs51", "vs52", "vs53", "vs54", "vs55", "vs56", | |
2521 | "vs57", "vs58", "vs59", "vs60", "vs61", "vs62", "vs63" | |
2522 | }; | |
2523 | return vsx_regnames[regno - tdep->ppc_vsr0_regnum]; | |
2524 | } | |
2525 | ||
2526 | /* Check if the this is a Extended FP pseudo-register. */ | |
2527 | if (IS_EFP_PSEUDOREG (tdep, regno)) | |
2528 | { | |
2529 | static const char *const efpr_regnames[] = { | |
2530 | "f32", "f33", "f34", "f35", "f36", "f37", "f38", | |
2531 | "f39", "f40", "f41", "f42", "f43", "f44", "f45", | |
2532 | "f46", "f47", "f48", "f49", "f50", "f51", | |
2533 | "f52", "f53", "f54", "f55", "f56", "f57", | |
2534 | "f58", "f59", "f60", "f61", "f62", "f63" | |
2535 | }; | |
2536 | return efpr_regnames[regno - tdep->ppc_efpr0_regnum]; | |
2537 | } | |
2538 | ||
d93859e2 | 2539 | return tdesc_register_name (gdbarch, regno); |
7a78ae4e ND |
2540 | } |
2541 | ||
7cc46491 DJ |
2542 | /* Return the GDB type object for the "standard" data type of data in |
2543 | register N. */ | |
7a78ae4e ND |
2544 | |
2545 | static struct type * | |
7cc46491 | 2546 | rs6000_pseudo_register_type (struct gdbarch *gdbarch, int regnum) |
7a78ae4e | 2547 | { |
691d145a | 2548 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7a78ae4e | 2549 | |
7cc46491 | 2550 | /* These are the only pseudo-registers we support. */ |
f949c649 | 2551 | gdb_assert (IS_SPE_PSEUDOREG (tdep, regnum) |
604c2f83 LM |
2552 | || IS_DFP_PSEUDOREG (tdep, regnum) |
2553 | || IS_VSX_PSEUDOREG (tdep, regnum) | |
2554 | || IS_EFP_PSEUDOREG (tdep, regnum)); | |
7cc46491 | 2555 | |
f949c649 TJB |
2556 | /* These are the e500 pseudo-registers. */ |
2557 | if (IS_SPE_PSEUDOREG (tdep, regnum)) | |
2558 | return rs6000_builtin_type_vec64 (gdbarch); | |
604c2f83 LM |
2559 | else if (IS_DFP_PSEUDOREG (tdep, regnum)) |
2560 | /* PPC decimal128 pseudo-registers. */ | |
f949c649 | 2561 | return builtin_type (gdbarch)->builtin_declong; |
604c2f83 LM |
2562 | else if (IS_VSX_PSEUDOREG (tdep, regnum)) |
2563 | /* POWER7 VSX pseudo-registers. */ | |
2564 | return rs6000_builtin_type_vec128 (gdbarch); | |
2565 | else | |
2566 | /* POWER7 Extended FP pseudo-registers. */ | |
2567 | return builtin_type (gdbarch)->builtin_double; | |
7a78ae4e ND |
2568 | } |
2569 | ||
c44ca51c AC |
2570 | /* Is REGNUM a member of REGGROUP? */ |
2571 | static int | |
7cc46491 DJ |
2572 | rs6000_pseudo_register_reggroup_p (struct gdbarch *gdbarch, int regnum, |
2573 | struct reggroup *group) | |
c44ca51c AC |
2574 | { |
2575 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
c44ca51c | 2576 | |
7cc46491 | 2577 | /* These are the only pseudo-registers we support. */ |
f949c649 | 2578 | gdb_assert (IS_SPE_PSEUDOREG (tdep, regnum) |
604c2f83 LM |
2579 | || IS_DFP_PSEUDOREG (tdep, regnum) |
2580 | || IS_VSX_PSEUDOREG (tdep, regnum) | |
2581 | || IS_EFP_PSEUDOREG (tdep, regnum)); | |
c44ca51c | 2582 | |
604c2f83 LM |
2583 | /* These are the e500 pseudo-registers or the POWER7 VSX registers. */ |
2584 | if (IS_SPE_PSEUDOREG (tdep, regnum) || IS_VSX_PSEUDOREG (tdep, regnum)) | |
f949c649 | 2585 | return group == all_reggroup || group == vector_reggroup; |
7cc46491 | 2586 | else |
604c2f83 | 2587 | /* PPC decimal128 or Extended FP pseudo-registers. */ |
f949c649 | 2588 | return group == all_reggroup || group == float_reggroup; |
c44ca51c AC |
2589 | } |
2590 | ||
691d145a | 2591 | /* The register format for RS/6000 floating point registers is always |
64366f1c | 2592 | double, we need a conversion if the memory format is float. */ |
7a78ae4e ND |
2593 | |
2594 | static int | |
0abe36f5 MD |
2595 | rs6000_convert_register_p (struct gdbarch *gdbarch, int regnum, |
2596 | struct type *type) | |
7a78ae4e | 2597 | { |
0abe36f5 | 2598 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7cc46491 DJ |
2599 | |
2600 | return (tdep->ppc_fp0_regnum >= 0 | |
2601 | && regnum >= tdep->ppc_fp0_regnum | |
2602 | && regnum < tdep->ppc_fp0_regnum + ppc_num_fprs | |
2603 | && TYPE_CODE (type) == TYPE_CODE_FLT | |
0dfff4cb UW |
2604 | && TYPE_LENGTH (type) |
2605 | != TYPE_LENGTH (builtin_type (gdbarch)->builtin_double)); | |
7a78ae4e ND |
2606 | } |
2607 | ||
8dccd430 | 2608 | static int |
691d145a JB |
2609 | rs6000_register_to_value (struct frame_info *frame, |
2610 | int regnum, | |
2611 | struct type *type, | |
8dccd430 PA |
2612 | gdb_byte *to, |
2613 | int *optimizedp, int *unavailablep) | |
7a78ae4e | 2614 | { |
0dfff4cb | 2615 | struct gdbarch *gdbarch = get_frame_arch (frame); |
0f068fb5 | 2616 | gdb_byte from[PPC_MAX_REGISTER_SIZE]; |
691d145a | 2617 | |
691d145a | 2618 | gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT); |
7a78ae4e | 2619 | |
8dccd430 PA |
2620 | if (!get_frame_register_bytes (frame, regnum, 0, |
2621 | register_size (gdbarch, regnum), | |
2622 | from, optimizedp, unavailablep)) | |
2623 | return 0; | |
2624 | ||
3b2ca824 UW |
2625 | target_float_convert (from, builtin_type (gdbarch)->builtin_double, |
2626 | to, type); | |
8dccd430 PA |
2627 | *optimizedp = *unavailablep = 0; |
2628 | return 1; | |
691d145a | 2629 | } |
7a292a7a | 2630 | |
7a78ae4e | 2631 | static void |
691d145a JB |
2632 | rs6000_value_to_register (struct frame_info *frame, |
2633 | int regnum, | |
2634 | struct type *type, | |
50fd1280 | 2635 | const gdb_byte *from) |
7a78ae4e | 2636 | { |
0dfff4cb | 2637 | struct gdbarch *gdbarch = get_frame_arch (frame); |
0f068fb5 | 2638 | gdb_byte to[PPC_MAX_REGISTER_SIZE]; |
691d145a | 2639 | |
691d145a JB |
2640 | gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT); |
2641 | ||
3b2ca824 UW |
2642 | target_float_convert (from, type, |
2643 | to, builtin_type (gdbarch)->builtin_double); | |
691d145a | 2644 | put_frame_register (frame, regnum, to); |
7a78ae4e | 2645 | } |
c906108c | 2646 | |
05d1431c PA |
2647 | /* The type of a function that moves the value of REG between CACHE |
2648 | or BUF --- in either direction. */ | |
2649 | typedef enum register_status (*move_ev_register_func) (struct regcache *, | |
2650 | int, void *); | |
2651 | ||
6ced10dd JB |
2652 | /* Move SPE vector register values between a 64-bit buffer and the two |
2653 | 32-bit raw register halves in a regcache. This function handles | |
2654 | both splitting a 64-bit value into two 32-bit halves, and joining | |
2655 | two halves into a whole 64-bit value, depending on the function | |
2656 | passed as the MOVE argument. | |
2657 | ||
2658 | EV_REG must be the number of an SPE evN vector register --- a | |
2659 | pseudoregister. REGCACHE must be a regcache, and BUFFER must be a | |
2660 | 64-bit buffer. | |
2661 | ||
2662 | Call MOVE once for each 32-bit half of that register, passing | |
2663 | REGCACHE, the number of the raw register corresponding to that | |
2664 | half, and the address of the appropriate half of BUFFER. | |
2665 | ||
2666 | For example, passing 'regcache_raw_read' as the MOVE function will | |
2667 | fill BUFFER with the full 64-bit contents of EV_REG. Or, passing | |
2668 | 'regcache_raw_supply' will supply the contents of BUFFER to the | |
2669 | appropriate pair of raw registers in REGCACHE. | |
2670 | ||
2671 | You may need to cast away some 'const' qualifiers when passing | |
2672 | MOVE, since this function can't tell at compile-time which of | |
2673 | REGCACHE or BUFFER is acting as the source of the data. If C had | |
2674 | co-variant type qualifiers, ... */ | |
05d1431c PA |
2675 | |
2676 | static enum register_status | |
2677 | e500_move_ev_register (move_ev_register_func move, | |
2678 | struct regcache *regcache, int ev_reg, void *buffer) | |
6ced10dd | 2679 | { |
ac7936df | 2680 | struct gdbarch *arch = regcache->arch (); |
6ced10dd JB |
2681 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); |
2682 | int reg_index; | |
19ba03f4 | 2683 | gdb_byte *byte_buffer = (gdb_byte *) buffer; |
05d1431c | 2684 | enum register_status status; |
6ced10dd | 2685 | |
5a9e69ba | 2686 | gdb_assert (IS_SPE_PSEUDOREG (tdep, ev_reg)); |
6ced10dd JB |
2687 | |
2688 | reg_index = ev_reg - tdep->ppc_ev0_regnum; | |
2689 | ||
8b164abb | 2690 | if (gdbarch_byte_order (arch) == BFD_ENDIAN_BIG) |
6ced10dd | 2691 | { |
05d1431c PA |
2692 | status = move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, |
2693 | byte_buffer); | |
2694 | if (status == REG_VALID) | |
2695 | status = move (regcache, tdep->ppc_gp0_regnum + reg_index, | |
2696 | byte_buffer + 4); | |
6ced10dd JB |
2697 | } |
2698 | else | |
2699 | { | |
05d1431c PA |
2700 | status = move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer); |
2701 | if (status == REG_VALID) | |
2702 | status = move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, | |
2703 | byte_buffer + 4); | |
6ced10dd | 2704 | } |
05d1431c PA |
2705 | |
2706 | return status; | |
6ced10dd JB |
2707 | } |
2708 | ||
05d1431c PA |
2709 | static enum register_status |
2710 | do_regcache_raw_read (struct regcache *regcache, int regnum, void *buffer) | |
2711 | { | |
19ba03f4 | 2712 | return regcache_raw_read (regcache, regnum, (gdb_byte *) buffer); |
05d1431c PA |
2713 | } |
2714 | ||
2715 | static enum register_status | |
2716 | do_regcache_raw_write (struct regcache *regcache, int regnum, void *buffer) | |
2717 | { | |
19ba03f4 | 2718 | regcache_raw_write (regcache, regnum, (const gdb_byte *) buffer); |
05d1431c PA |
2719 | |
2720 | return REG_VALID; | |
2721 | } | |
2722 | ||
2723 | static enum register_status | |
c8001721 | 2724 | e500_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, |
50fd1280 | 2725 | int reg_nr, gdb_byte *buffer) |
f949c649 | 2726 | { |
05d1431c | 2727 | return e500_move_ev_register (do_regcache_raw_read, regcache, reg_nr, buffer); |
f949c649 TJB |
2728 | } |
2729 | ||
2730 | static void | |
2731 | e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
2732 | int reg_nr, const gdb_byte *buffer) | |
2733 | { | |
05d1431c PA |
2734 | e500_move_ev_register (do_regcache_raw_write, regcache, |
2735 | reg_nr, (void *) buffer); | |
f949c649 TJB |
2736 | } |
2737 | ||
604c2f83 | 2738 | /* Read method for DFP pseudo-registers. */ |
05d1431c | 2739 | static enum register_status |
604c2f83 | 2740 | dfp_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, |
f949c649 TJB |
2741 | int reg_nr, gdb_byte *buffer) |
2742 | { | |
2743 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2744 | int reg_index = reg_nr - tdep->ppc_dl0_regnum; | |
05d1431c | 2745 | enum register_status status; |
f949c649 TJB |
2746 | |
2747 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
2748 | { | |
2749 | /* Read two FP registers to form a whole dl register. */ | |
05d1431c PA |
2750 | status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum + |
2751 | 2 * reg_index, buffer); | |
2752 | if (status == REG_VALID) | |
2753 | status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum + | |
2754 | 2 * reg_index + 1, buffer + 8); | |
f949c649 TJB |
2755 | } |
2756 | else | |
2757 | { | |
05d1431c | 2758 | status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum + |
0ff3e01f | 2759 | 2 * reg_index + 1, buffer); |
05d1431c PA |
2760 | if (status == REG_VALID) |
2761 | status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum + | |
0ff3e01f | 2762 | 2 * reg_index, buffer + 8); |
f949c649 | 2763 | } |
05d1431c PA |
2764 | |
2765 | return status; | |
f949c649 TJB |
2766 | } |
2767 | ||
604c2f83 | 2768 | /* Write method for DFP pseudo-registers. */ |
f949c649 | 2769 | static void |
604c2f83 | 2770 | dfp_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, |
f949c649 TJB |
2771 | int reg_nr, const gdb_byte *buffer) |
2772 | { | |
2773 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2774 | int reg_index = reg_nr - tdep->ppc_dl0_regnum; | |
2775 | ||
2776 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
2777 | { | |
2778 | /* Write each half of the dl register into a separate | |
2779 | FP register. */ | |
2780 | regcache_raw_write (regcache, tdep->ppc_fp0_regnum + | |
2781 | 2 * reg_index, buffer); | |
2782 | regcache_raw_write (regcache, tdep->ppc_fp0_regnum + | |
2783 | 2 * reg_index + 1, buffer + 8); | |
2784 | } | |
2785 | else | |
2786 | { | |
2787 | regcache_raw_write (regcache, tdep->ppc_fp0_regnum + | |
0ff3e01f | 2788 | 2 * reg_index + 1, buffer); |
f949c649 | 2789 | regcache_raw_write (regcache, tdep->ppc_fp0_regnum + |
0ff3e01f | 2790 | 2 * reg_index, buffer + 8); |
f949c649 TJB |
2791 | } |
2792 | } | |
2793 | ||
604c2f83 | 2794 | /* Read method for POWER7 VSX pseudo-registers. */ |
05d1431c | 2795 | static enum register_status |
604c2f83 LM |
2796 | vsx_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, |
2797 | int reg_nr, gdb_byte *buffer) | |
2798 | { | |
2799 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2800 | int reg_index = reg_nr - tdep->ppc_vsr0_regnum; | |
05d1431c | 2801 | enum register_status status; |
604c2f83 LM |
2802 | |
2803 | /* Read the portion that overlaps the VMX registers. */ | |
2804 | if (reg_index > 31) | |
05d1431c PA |
2805 | status = regcache_raw_read (regcache, tdep->ppc_vr0_regnum + |
2806 | reg_index - 32, buffer); | |
604c2f83 LM |
2807 | else |
2808 | /* Read the portion that overlaps the FPR registers. */ | |
2809 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
2810 | { | |
05d1431c PA |
2811 | status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum + |
2812 | reg_index, buffer); | |
2813 | if (status == REG_VALID) | |
2814 | status = regcache_raw_read (regcache, tdep->ppc_vsr0_upper_regnum + | |
2815 | reg_index, buffer + 8); | |
604c2f83 LM |
2816 | } |
2817 | else | |
2818 | { | |
05d1431c PA |
2819 | status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum + |
2820 | reg_index, buffer + 8); | |
2821 | if (status == REG_VALID) | |
2822 | status = regcache_raw_read (regcache, tdep->ppc_vsr0_upper_regnum + | |
2823 | reg_index, buffer); | |
604c2f83 | 2824 | } |
05d1431c PA |
2825 | |
2826 | return status; | |
604c2f83 LM |
2827 | } |
2828 | ||
2829 | /* Write method for POWER7 VSX pseudo-registers. */ | |
2830 | static void | |
2831 | vsx_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
2832 | int reg_nr, const gdb_byte *buffer) | |
2833 | { | |
2834 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2835 | int reg_index = reg_nr - tdep->ppc_vsr0_regnum; | |
2836 | ||
2837 | /* Write the portion that overlaps the VMX registers. */ | |
2838 | if (reg_index > 31) | |
2839 | regcache_raw_write (regcache, tdep->ppc_vr0_regnum + | |
2840 | reg_index - 32, buffer); | |
2841 | else | |
2842 | /* Write the portion that overlaps the FPR registers. */ | |
2843 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
2844 | { | |
2845 | regcache_raw_write (regcache, tdep->ppc_fp0_regnum + | |
2846 | reg_index, buffer); | |
2847 | regcache_raw_write (regcache, tdep->ppc_vsr0_upper_regnum + | |
2848 | reg_index, buffer + 8); | |
2849 | } | |
2850 | else | |
2851 | { | |
2852 | regcache_raw_write (regcache, tdep->ppc_fp0_regnum + | |
2853 | reg_index, buffer + 8); | |
2854 | regcache_raw_write (regcache, tdep->ppc_vsr0_upper_regnum + | |
2855 | reg_index, buffer); | |
2856 | } | |
2857 | } | |
2858 | ||
2859 | /* Read method for POWER7 Extended FP pseudo-registers. */ | |
05d1431c | 2860 | static enum register_status |
604c2f83 LM |
2861 | efpr_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, |
2862 | int reg_nr, gdb_byte *buffer) | |
2863 | { | |
2864 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2865 | int reg_index = reg_nr - tdep->ppc_efpr0_regnum; | |
084ee545 | 2866 | int offset = gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG ? 0 : 8; |
604c2f83 | 2867 | |
d9492458 | 2868 | /* Read the portion that overlaps the VMX register. */ |
084ee545 UW |
2869 | return regcache_raw_read_part (regcache, tdep->ppc_vr0_regnum + reg_index, |
2870 | offset, register_size (gdbarch, reg_nr), | |
2871 | buffer); | |
604c2f83 LM |
2872 | } |
2873 | ||
2874 | /* Write method for POWER7 Extended FP pseudo-registers. */ | |
2875 | static void | |
2876 | efpr_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
2877 | int reg_nr, const gdb_byte *buffer) | |
2878 | { | |
2879 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2880 | int reg_index = reg_nr - tdep->ppc_efpr0_regnum; | |
084ee545 | 2881 | int offset = gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG ? 0 : 8; |
604c2f83 | 2882 | |
d9492458 | 2883 | /* Write the portion that overlaps the VMX register. */ |
084ee545 UW |
2884 | regcache_raw_write_part (regcache, tdep->ppc_vr0_regnum + reg_index, |
2885 | offset, register_size (gdbarch, reg_nr), | |
2886 | buffer); | |
604c2f83 LM |
2887 | } |
2888 | ||
05d1431c | 2889 | static enum register_status |
0df8b418 MS |
2890 | rs6000_pseudo_register_read (struct gdbarch *gdbarch, |
2891 | struct regcache *regcache, | |
f949c649 | 2892 | int reg_nr, gdb_byte *buffer) |
c8001721 | 2893 | { |
ac7936df | 2894 | struct gdbarch *regcache_arch = regcache->arch (); |
c8001721 EZ |
2895 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2896 | ||
6ced10dd | 2897 | gdb_assert (regcache_arch == gdbarch); |
f949c649 | 2898 | |
5a9e69ba | 2899 | if (IS_SPE_PSEUDOREG (tdep, reg_nr)) |
05d1431c | 2900 | return e500_pseudo_register_read (gdbarch, regcache, reg_nr, buffer); |
f949c649 | 2901 | else if (IS_DFP_PSEUDOREG (tdep, reg_nr)) |
05d1431c | 2902 | return dfp_pseudo_register_read (gdbarch, regcache, reg_nr, buffer); |
604c2f83 | 2903 | else if (IS_VSX_PSEUDOREG (tdep, reg_nr)) |
05d1431c | 2904 | return vsx_pseudo_register_read (gdbarch, regcache, reg_nr, buffer); |
604c2f83 | 2905 | else if (IS_EFP_PSEUDOREG (tdep, reg_nr)) |
05d1431c | 2906 | return efpr_pseudo_register_read (gdbarch, regcache, reg_nr, buffer); |
6ced10dd | 2907 | else |
a44bddec | 2908 | internal_error (__FILE__, __LINE__, |
f949c649 TJB |
2909 | _("rs6000_pseudo_register_read: " |
2910 | "called on unexpected register '%s' (%d)"), | |
2911 | gdbarch_register_name (gdbarch, reg_nr), reg_nr); | |
c8001721 EZ |
2912 | } |
2913 | ||
2914 | static void | |
f949c649 TJB |
2915 | rs6000_pseudo_register_write (struct gdbarch *gdbarch, |
2916 | struct regcache *regcache, | |
2917 | int reg_nr, const gdb_byte *buffer) | |
c8001721 | 2918 | { |
ac7936df | 2919 | struct gdbarch *regcache_arch = regcache->arch (); |
c8001721 EZ |
2920 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2921 | ||
6ced10dd | 2922 | gdb_assert (regcache_arch == gdbarch); |
f949c649 | 2923 | |
5a9e69ba | 2924 | if (IS_SPE_PSEUDOREG (tdep, reg_nr)) |
f949c649 TJB |
2925 | e500_pseudo_register_write (gdbarch, regcache, reg_nr, buffer); |
2926 | else if (IS_DFP_PSEUDOREG (tdep, reg_nr)) | |
604c2f83 LM |
2927 | dfp_pseudo_register_write (gdbarch, regcache, reg_nr, buffer); |
2928 | else if (IS_VSX_PSEUDOREG (tdep, reg_nr)) | |
2929 | vsx_pseudo_register_write (gdbarch, regcache, reg_nr, buffer); | |
2930 | else if (IS_EFP_PSEUDOREG (tdep, reg_nr)) | |
2931 | efpr_pseudo_register_write (gdbarch, regcache, reg_nr, buffer); | |
6ced10dd | 2932 | else |
a44bddec | 2933 | internal_error (__FILE__, __LINE__, |
f949c649 TJB |
2934 | _("rs6000_pseudo_register_write: " |
2935 | "called on unexpected register '%s' (%d)"), | |
2936 | gdbarch_register_name (gdbarch, reg_nr), reg_nr); | |
6ced10dd JB |
2937 | } |
2938 | ||
2a2fa07b MK |
2939 | static int |
2940 | rs6000_ax_pseudo_register_collect (struct gdbarch *gdbarch, | |
2941 | struct agent_expr *ax, int reg_nr) | |
2942 | { | |
2943 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2944 | if (IS_SPE_PSEUDOREG (tdep, reg_nr)) | |
2945 | { | |
2946 | int reg_index = reg_nr - tdep->ppc_ev0_regnum; | |
2947 | ax_reg_mask (ax, tdep->ppc_gp0_regnum + reg_index); | |
2948 | ax_reg_mask (ax, tdep->ppc_ev0_upper_regnum + reg_index); | |
2949 | } | |
2950 | else if (IS_DFP_PSEUDOREG (tdep, reg_nr)) | |
2951 | { | |
2952 | int reg_index = reg_nr - tdep->ppc_dl0_regnum; | |
2953 | ax_reg_mask (ax, tdep->ppc_fp0_regnum + 2 * reg_index); | |
2954 | ax_reg_mask (ax, tdep->ppc_fp0_regnum + 2 * reg_index + 1); | |
2955 | } | |
2956 | else if (IS_VSX_PSEUDOREG (tdep, reg_nr)) | |
2957 | { | |
2958 | int reg_index = reg_nr - tdep->ppc_vsr0_regnum; | |
2959 | if (reg_index > 31) | |
2960 | { | |
2961 | ax_reg_mask (ax, tdep->ppc_vr0_regnum + reg_index - 32); | |
2962 | } | |
2963 | else | |
2964 | { | |
2965 | ax_reg_mask (ax, tdep->ppc_fp0_regnum + reg_index); | |
2966 | ax_reg_mask (ax, tdep->ppc_vsr0_upper_regnum + reg_index); | |
2967 | } | |
2968 | } | |
2969 | else if (IS_EFP_PSEUDOREG (tdep, reg_nr)) | |
2970 | { | |
2971 | int reg_index = reg_nr - tdep->ppc_efpr0_regnum; | |
2972 | ax_reg_mask (ax, tdep->ppc_vr0_regnum + reg_index); | |
2973 | } | |
2974 | else | |
2975 | internal_error (__FILE__, __LINE__, | |
2976 | _("rs6000_pseudo_register_collect: " | |
2977 | "called on unexpected register '%s' (%d)"), | |
2978 | gdbarch_register_name (gdbarch, reg_nr), reg_nr); | |
2979 | return 0; | |
2980 | } | |
2981 | ||
2982 | ||
a67914de MK |
2983 | static void |
2984 | rs6000_gen_return_address (struct gdbarch *gdbarch, | |
2985 | struct agent_expr *ax, struct axs_value *value, | |
2986 | CORE_ADDR scope) | |
2987 | { | |
2988 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2989 | value->type = register_type (gdbarch, tdep->ppc_lr_regnum); | |
2990 | value->kind = axs_lvalue_register; | |
2991 | value->u.reg = tdep->ppc_lr_regnum; | |
2992 | } | |
2993 | ||
2994 | ||
18ed0c4e | 2995 | /* Convert a DBX STABS register number to a GDB register number. */ |
c8001721 | 2996 | static int |
d3f73121 | 2997 | rs6000_stab_reg_to_regnum (struct gdbarch *gdbarch, int num) |
c8001721 | 2998 | { |
d3f73121 | 2999 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
c8001721 | 3000 | |
9f744501 JB |
3001 | if (0 <= num && num <= 31) |
3002 | return tdep->ppc_gp0_regnum + num; | |
3003 | else if (32 <= num && num <= 63) | |
383f0f5b JB |
3004 | /* FIXME: jimb/2004-05-05: What should we do when the debug info |
3005 | specifies registers the architecture doesn't have? Our | |
3006 | callers don't check the value we return. */ | |
366f009f | 3007 | return tdep->ppc_fp0_regnum + (num - 32); |
18ed0c4e JB |
3008 | else if (77 <= num && num <= 108) |
3009 | return tdep->ppc_vr0_regnum + (num - 77); | |
9f744501 | 3010 | else if (1200 <= num && num < 1200 + 32) |
e1ec1b42 | 3011 | return tdep->ppc_ev0_upper_regnum + (num - 1200); |
9f744501 JB |
3012 | else |
3013 | switch (num) | |
3014 | { | |
3015 | case 64: | |
3016 | return tdep->ppc_mq_regnum; | |
3017 | case 65: | |
3018 | return tdep->ppc_lr_regnum; | |
3019 | case 66: | |
3020 | return tdep->ppc_ctr_regnum; | |
3021 | case 76: | |
3022 | return tdep->ppc_xer_regnum; | |
3023 | case 109: | |
3024 | return tdep->ppc_vrsave_regnum; | |
18ed0c4e JB |
3025 | case 110: |
3026 | return tdep->ppc_vrsave_regnum - 1; /* vscr */ | |
867e2dc5 | 3027 | case 111: |
18ed0c4e | 3028 | return tdep->ppc_acc_regnum; |
867e2dc5 | 3029 | case 112: |
18ed0c4e | 3030 | return tdep->ppc_spefscr_regnum; |
9f744501 JB |
3031 | default: |
3032 | return num; | |
3033 | } | |
18ed0c4e | 3034 | } |
9f744501 | 3035 | |
9f744501 | 3036 | |
18ed0c4e JB |
3037 | /* Convert a Dwarf 2 register number to a GDB register number. */ |
3038 | static int | |
d3f73121 | 3039 | rs6000_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int num) |
18ed0c4e | 3040 | { |
d3f73121 | 3041 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
9f744501 | 3042 | |
18ed0c4e JB |
3043 | if (0 <= num && num <= 31) |
3044 | return tdep->ppc_gp0_regnum + num; | |
3045 | else if (32 <= num && num <= 63) | |
3046 | /* FIXME: jimb/2004-05-05: What should we do when the debug info | |
3047 | specifies registers the architecture doesn't have? Our | |
3048 | callers don't check the value we return. */ | |
3049 | return tdep->ppc_fp0_regnum + (num - 32); | |
3050 | else if (1124 <= num && num < 1124 + 32) | |
3051 | return tdep->ppc_vr0_regnum + (num - 1124); | |
3052 | else if (1200 <= num && num < 1200 + 32) | |
e1ec1b42 | 3053 | return tdep->ppc_ev0_upper_regnum + (num - 1200); |
18ed0c4e JB |
3054 | else |
3055 | switch (num) | |
3056 | { | |
a489f789 AS |
3057 | case 64: |
3058 | return tdep->ppc_cr_regnum; | |
18ed0c4e JB |
3059 | case 67: |
3060 | return tdep->ppc_vrsave_regnum - 1; /* vscr */ | |
3061 | case 99: | |
3062 | return tdep->ppc_acc_regnum; | |
3063 | case 100: | |
3064 | return tdep->ppc_mq_regnum; | |
3065 | case 101: | |
3066 | return tdep->ppc_xer_regnum; | |
3067 | case 108: | |
3068 | return tdep->ppc_lr_regnum; | |
3069 | case 109: | |
3070 | return tdep->ppc_ctr_regnum; | |
3071 | case 356: | |
3072 | return tdep->ppc_vrsave_regnum; | |
3073 | case 612: | |
3074 | return tdep->ppc_spefscr_regnum; | |
3075 | default: | |
3076 | return num; | |
3077 | } | |
2188cbdd EZ |
3078 | } |
3079 | ||
4fc771b8 DJ |
3080 | /* Translate a .eh_frame register to DWARF register, or adjust a |
3081 | .debug_frame register. */ | |
3082 | ||
3083 | static int | |
3084 | rs6000_adjust_frame_regnum (struct gdbarch *gdbarch, int num, int eh_frame_p) | |
3085 | { | |
3086 | /* GCC releases before 3.4 use GCC internal register numbering in | |
3087 | .debug_frame (and .debug_info, et cetera). The numbering is | |
3088 | different from the standard SysV numbering for everything except | |
3089 | for GPRs and FPRs. We can not detect this problem in most cases | |
3090 | - to get accurate debug info for variables living in lr, ctr, v0, | |
3091 | et cetera, use a newer version of GCC. But we must detect | |
3092 | one important case - lr is in column 65 in .debug_frame output, | |
3093 | instead of 108. | |
3094 | ||
3095 | GCC 3.4, and the "hammer" branch, have a related problem. They | |
3096 | record lr register saves in .debug_frame as 108, but still record | |
3097 | the return column as 65. We fix that up too. | |
3098 | ||
3099 | We can do this because 65 is assigned to fpsr, and GCC never | |
3100 | generates debug info referring to it. To add support for | |
3101 | handwritten debug info that restores fpsr, we would need to add a | |
3102 | producer version check to this. */ | |
3103 | if (!eh_frame_p) | |
3104 | { | |
3105 | if (num == 65) | |
3106 | return 108; | |
3107 | else | |
3108 | return num; | |
3109 | } | |
3110 | ||
3111 | /* .eh_frame is GCC specific. For binary compatibility, it uses GCC | |
3112 | internal register numbering; translate that to the standard DWARF2 | |
3113 | register numbering. */ | |
3114 | if (0 <= num && num <= 63) /* r0-r31,fp0-fp31 */ | |
3115 | return num; | |
3116 | else if (68 <= num && num <= 75) /* cr0-cr8 */ | |
3117 | return num - 68 + 86; | |
3118 | else if (77 <= num && num <= 108) /* vr0-vr31 */ | |
3119 | return num - 77 + 1124; | |
3120 | else | |
3121 | switch (num) | |
3122 | { | |
3123 | case 64: /* mq */ | |
3124 | return 100; | |
3125 | case 65: /* lr */ | |
3126 | return 108; | |
3127 | case 66: /* ctr */ | |
3128 | return 109; | |
3129 | case 76: /* xer */ | |
3130 | return 101; | |
3131 | case 109: /* vrsave */ | |
3132 | return 356; | |
3133 | case 110: /* vscr */ | |
3134 | return 67; | |
3135 | case 111: /* spe_acc */ | |
3136 | return 99; | |
3137 | case 112: /* spefscr */ | |
3138 | return 612; | |
3139 | default: | |
3140 | return num; | |
3141 | } | |
3142 | } | |
c906108c | 3143 | \f |
c5aa993b | 3144 | |
7a78ae4e | 3145 | /* Handling the various POWER/PowerPC variants. */ |
c906108c | 3146 | |
c906108c | 3147 | /* Information about a particular processor variant. */ |
7a78ae4e | 3148 | |
c906108c | 3149 | struct variant |
c5aa993b JM |
3150 | { |
3151 | /* Name of this variant. */ | |
a121b7c1 | 3152 | const char *name; |
c906108c | 3153 | |
c5aa993b | 3154 | /* English description of the variant. */ |
a121b7c1 | 3155 | const char *description; |
c906108c | 3156 | |
64366f1c | 3157 | /* bfd_arch_info.arch corresponding to variant. */ |
7a78ae4e ND |
3158 | enum bfd_architecture arch; |
3159 | ||
64366f1c | 3160 | /* bfd_arch_info.mach corresponding to variant. */ |
7a78ae4e ND |
3161 | unsigned long mach; |
3162 | ||
7cc46491 DJ |
3163 | /* Target description for this variant. */ |
3164 | struct target_desc **tdesc; | |
c5aa993b | 3165 | }; |
c906108c | 3166 | |
489461e2 | 3167 | static struct variant variants[] = |
c906108c | 3168 | { |
7a78ae4e | 3169 | {"powerpc", "PowerPC user-level", bfd_arch_powerpc, |
7284e1be | 3170 | bfd_mach_ppc, &tdesc_powerpc_altivec32}, |
7a78ae4e | 3171 | {"power", "POWER user-level", bfd_arch_rs6000, |
7cc46491 | 3172 | bfd_mach_rs6k, &tdesc_rs6000}, |
7a78ae4e | 3173 | {"403", "IBM PowerPC 403", bfd_arch_powerpc, |
7cc46491 | 3174 | bfd_mach_ppc_403, &tdesc_powerpc_403}, |
4d09ffea MS |
3175 | {"405", "IBM PowerPC 405", bfd_arch_powerpc, |
3176 | bfd_mach_ppc_405, &tdesc_powerpc_405}, | |
7a78ae4e | 3177 | {"601", "Motorola PowerPC 601", bfd_arch_powerpc, |
7cc46491 | 3178 | bfd_mach_ppc_601, &tdesc_powerpc_601}, |
7a78ae4e | 3179 | {"602", "Motorola PowerPC 602", bfd_arch_powerpc, |
7cc46491 | 3180 | bfd_mach_ppc_602, &tdesc_powerpc_602}, |
7a78ae4e | 3181 | {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc, |
7cc46491 | 3182 | bfd_mach_ppc_603, &tdesc_powerpc_603}, |
7a78ae4e | 3183 | {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc, |
7cc46491 | 3184 | 604, &tdesc_powerpc_604}, |
7a78ae4e | 3185 | {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc, |
7cc46491 | 3186 | bfd_mach_ppc_403gc, &tdesc_powerpc_403gc}, |
7a78ae4e | 3187 | {"505", "Motorola PowerPC 505", bfd_arch_powerpc, |
7cc46491 | 3188 | bfd_mach_ppc_505, &tdesc_powerpc_505}, |
7a78ae4e | 3189 | {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc, |
7cc46491 | 3190 | bfd_mach_ppc_860, &tdesc_powerpc_860}, |
7a78ae4e | 3191 | {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc, |
7cc46491 | 3192 | bfd_mach_ppc_750, &tdesc_powerpc_750}, |
1fcc0bb8 | 3193 | {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc, |
7cc46491 | 3194 | bfd_mach_ppc_7400, &tdesc_powerpc_7400}, |
c8001721 | 3195 | {"e500", "Motorola PowerPC e500", bfd_arch_powerpc, |
7cc46491 | 3196 | bfd_mach_ppc_e500, &tdesc_powerpc_e500}, |
7a78ae4e | 3197 | |
5d57ee30 KB |
3198 | /* 64-bit */ |
3199 | {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc, | |
7284e1be | 3200 | bfd_mach_ppc64, &tdesc_powerpc_altivec64}, |
7a78ae4e | 3201 | {"620", "Motorola PowerPC 620", bfd_arch_powerpc, |
7cc46491 | 3202 | bfd_mach_ppc_620, &tdesc_powerpc_64}, |
5d57ee30 | 3203 | {"630", "Motorola PowerPC 630", bfd_arch_powerpc, |
7cc46491 | 3204 | bfd_mach_ppc_630, &tdesc_powerpc_64}, |
7a78ae4e | 3205 | {"a35", "PowerPC A35", bfd_arch_powerpc, |
7cc46491 | 3206 | bfd_mach_ppc_a35, &tdesc_powerpc_64}, |
5d57ee30 | 3207 | {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc, |
7cc46491 | 3208 | bfd_mach_ppc_rs64ii, &tdesc_powerpc_64}, |
5d57ee30 | 3209 | {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc, |
7cc46491 | 3210 | bfd_mach_ppc_rs64iii, &tdesc_powerpc_64}, |
5d57ee30 | 3211 | |
64366f1c | 3212 | /* FIXME: I haven't checked the register sets of the following. */ |
7a78ae4e | 3213 | {"rs1", "IBM POWER RS1", bfd_arch_rs6000, |
7cc46491 | 3214 | bfd_mach_rs6k_rs1, &tdesc_rs6000}, |
7a78ae4e | 3215 | {"rsc", "IBM POWER RSC", bfd_arch_rs6000, |
7cc46491 | 3216 | bfd_mach_rs6k_rsc, &tdesc_rs6000}, |
7a78ae4e | 3217 | {"rs2", "IBM POWER RS2", bfd_arch_rs6000, |
7cc46491 | 3218 | bfd_mach_rs6k_rs2, &tdesc_rs6000}, |
7a78ae4e | 3219 | |
3e45d68b | 3220 | {0, 0, (enum bfd_architecture) 0, 0, 0} |
c906108c SS |
3221 | }; |
3222 | ||
7a78ae4e | 3223 | /* Return the variant corresponding to architecture ARCH and machine number |
64366f1c | 3224 | MACH. If no such variant exists, return null. */ |
c906108c | 3225 | |
7a78ae4e ND |
3226 | static const struct variant * |
3227 | find_variant_by_arch (enum bfd_architecture arch, unsigned long mach) | |
c906108c | 3228 | { |
7a78ae4e | 3229 | const struct variant *v; |
c5aa993b | 3230 | |
7a78ae4e ND |
3231 | for (v = variants; v->name; v++) |
3232 | if (arch == v->arch && mach == v->mach) | |
3233 | return v; | |
c906108c | 3234 | |
7a78ae4e | 3235 | return NULL; |
c906108c | 3236 | } |
9364a0ef | 3237 | |
7a78ae4e | 3238 | \f |
61a65099 KB |
3239 | static CORE_ADDR |
3240 | rs6000_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
3241 | { | |
3e8c568d | 3242 | return frame_unwind_register_unsigned (next_frame, |
8b164abb | 3243 | gdbarch_pc_regnum (gdbarch)); |
61a65099 KB |
3244 | } |
3245 | ||
3246 | static struct frame_id | |
1af5d7ce | 3247 | rs6000_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
61a65099 | 3248 | { |
1af5d7ce UW |
3249 | return frame_id_build (get_frame_register_unsigned |
3250 | (this_frame, gdbarch_sp_regnum (gdbarch)), | |
3251 | get_frame_pc (this_frame)); | |
61a65099 KB |
3252 | } |
3253 | ||
3254 | struct rs6000_frame_cache | |
3255 | { | |
3256 | CORE_ADDR base; | |
3257 | CORE_ADDR initial_sp; | |
3258 | struct trad_frame_saved_reg *saved_regs; | |
50ae56ec WW |
3259 | |
3260 | /* Set BASE_P to true if this frame cache is properly initialized. | |
3261 | Otherwise set to false because some registers or memory cannot | |
3262 | collected. */ | |
3263 | int base_p; | |
3264 | /* Cache PC for building unavailable frame. */ | |
3265 | CORE_ADDR pc; | |
61a65099 KB |
3266 | }; |
3267 | ||
3268 | static struct rs6000_frame_cache * | |
1af5d7ce | 3269 | rs6000_frame_cache (struct frame_info *this_frame, void **this_cache) |
61a65099 KB |
3270 | { |
3271 | struct rs6000_frame_cache *cache; | |
1af5d7ce | 3272 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
61a65099 | 3273 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
e17a4113 | 3274 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
61a65099 KB |
3275 | struct rs6000_framedata fdata; |
3276 | int wordsize = tdep->wordsize; | |
338435ef | 3277 | CORE_ADDR func = 0, pc = 0; |
61a65099 KB |
3278 | |
3279 | if ((*this_cache) != NULL) | |
19ba03f4 | 3280 | return (struct rs6000_frame_cache *) (*this_cache); |
61a65099 KB |
3281 | cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache); |
3282 | (*this_cache) = cache; | |
50ae56ec | 3283 | cache->pc = 0; |
1af5d7ce | 3284 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
61a65099 | 3285 | |
50ae56ec WW |
3286 | TRY |
3287 | { | |
3288 | func = get_frame_func (this_frame); | |
3289 | cache->pc = func; | |
3290 | pc = get_frame_pc (this_frame); | |
3291 | skip_prologue (gdbarch, func, pc, &fdata); | |
3292 | ||
3293 | /* Figure out the parent's stack pointer. */ | |
3294 | ||
3295 | /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most | |
3296 | address of the current frame. Things might be easier if the | |
3297 | ->frame pointed to the outer-most address of the frame. In | |
3298 | the mean time, the address of the prev frame is used as the | |
3299 | base address of this frame. */ | |
3300 | cache->base = get_frame_register_unsigned | |
3301 | (this_frame, gdbarch_sp_regnum (gdbarch)); | |
3302 | } | |
3303 | CATCH (ex, RETURN_MASK_ERROR) | |
3304 | { | |
3305 | if (ex.error != NOT_AVAILABLE_ERROR) | |
3306 | throw_exception (ex); | |
1ed0c2a4 | 3307 | return (struct rs6000_frame_cache *) (*this_cache); |
50ae56ec WW |
3308 | } |
3309 | END_CATCH | |
e10b1c4c DJ |
3310 | |
3311 | /* If the function appears to be frameless, check a couple of likely | |
3312 | indicators that we have simply failed to find the frame setup. | |
3313 | Two common cases of this are missing symbols (i.e. | |
ef02daa9 | 3314 | get_frame_func returns the wrong address or 0), and assembly |
e10b1c4c DJ |
3315 | stubs which have a fast exit path but set up a frame on the slow |
3316 | path. | |
3317 | ||
3318 | If the LR appears to return to this function, then presume that | |
3319 | we have an ABI compliant frame that we failed to find. */ | |
3320 | if (fdata.frameless && fdata.lr_offset == 0) | |
61a65099 | 3321 | { |
e10b1c4c DJ |
3322 | CORE_ADDR saved_lr; |
3323 | int make_frame = 0; | |
3324 | ||
1af5d7ce | 3325 | saved_lr = get_frame_register_unsigned (this_frame, tdep->ppc_lr_regnum); |
e10b1c4c DJ |
3326 | if (func == 0 && saved_lr == pc) |
3327 | make_frame = 1; | |
3328 | else if (func != 0) | |
3329 | { | |
3330 | CORE_ADDR saved_func = get_pc_function_start (saved_lr); | |
3331 | if (func == saved_func) | |
3332 | make_frame = 1; | |
3333 | } | |
3334 | ||
3335 | if (make_frame) | |
3336 | { | |
3337 | fdata.frameless = 0; | |
de6a76fd | 3338 | fdata.lr_offset = tdep->lr_frame_offset; |
e10b1c4c | 3339 | } |
61a65099 | 3340 | } |
e10b1c4c DJ |
3341 | |
3342 | if (!fdata.frameless) | |
9d9bf2df EBM |
3343 | { |
3344 | /* Frameless really means stackless. */ | |
cc2c4da8 | 3345 | ULONGEST backchain; |
9d9bf2df | 3346 | |
cc2c4da8 MK |
3347 | if (safe_read_memory_unsigned_integer (cache->base, wordsize, |
3348 | byte_order, &backchain)) | |
9d9bf2df EBM |
3349 | cache->base = (CORE_ADDR) backchain; |
3350 | } | |
e10b1c4c | 3351 | |
3e8c568d | 3352 | trad_frame_set_value (cache->saved_regs, |
8b164abb | 3353 | gdbarch_sp_regnum (gdbarch), cache->base); |
61a65099 KB |
3354 | |
3355 | /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr. | |
3356 | All fpr's from saved_fpr to fp31 are saved. */ | |
3357 | ||
3358 | if (fdata.saved_fpr >= 0) | |
3359 | { | |
3360 | int i; | |
3361 | CORE_ADDR fpr_addr = cache->base + fdata.fpr_offset; | |
383f0f5b JB |
3362 | |
3363 | /* If skip_prologue says floating-point registers were saved, | |
3364 | but the current architecture has no floating-point registers, | |
3365 | then that's strange. But we have no indices to even record | |
3366 | the addresses under, so we just ignore it. */ | |
3367 | if (ppc_floating_point_unit_p (gdbarch)) | |
063715bf | 3368 | for (i = fdata.saved_fpr; i < ppc_num_fprs; i++) |
383f0f5b JB |
3369 | { |
3370 | cache->saved_regs[tdep->ppc_fp0_regnum + i].addr = fpr_addr; | |
3371 | fpr_addr += 8; | |
3372 | } | |
61a65099 KB |
3373 | } |
3374 | ||
3375 | /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr. | |
46a9b8ed DJ |
3376 | All gpr's from saved_gpr to gpr31 are saved (except during the |
3377 | prologue). */ | |
61a65099 KB |
3378 | |
3379 | if (fdata.saved_gpr >= 0) | |
3380 | { | |
3381 | int i; | |
3382 | CORE_ADDR gpr_addr = cache->base + fdata.gpr_offset; | |
063715bf | 3383 | for (i = fdata.saved_gpr; i < ppc_num_gprs; i++) |
61a65099 | 3384 | { |
46a9b8ed DJ |
3385 | if (fdata.gpr_mask & (1U << i)) |
3386 | cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = gpr_addr; | |
61a65099 KB |
3387 | gpr_addr += wordsize; |
3388 | } | |
3389 | } | |
3390 | ||
3391 | /* if != -1, fdata.saved_vr is the smallest number of saved_vr. | |
3392 | All vr's from saved_vr to vr31 are saved. */ | |
3393 | if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) | |
3394 | { | |
3395 | if (fdata.saved_vr >= 0) | |
3396 | { | |
3397 | int i; | |
3398 | CORE_ADDR vr_addr = cache->base + fdata.vr_offset; | |
3399 | for (i = fdata.saved_vr; i < 32; i++) | |
3400 | { | |
3401 | cache->saved_regs[tdep->ppc_vr0_regnum + i].addr = vr_addr; | |
3402 | vr_addr += register_size (gdbarch, tdep->ppc_vr0_regnum); | |
3403 | } | |
3404 | } | |
3405 | } | |
3406 | ||
3407 | /* if != -1, fdata.saved_ev is the smallest number of saved_ev. | |
0df8b418 | 3408 | All vr's from saved_ev to ev31 are saved. ????? */ |
5a9e69ba | 3409 | if (tdep->ppc_ev0_regnum != -1) |
61a65099 KB |
3410 | { |
3411 | if (fdata.saved_ev >= 0) | |
3412 | { | |
3413 | int i; | |
3414 | CORE_ADDR ev_addr = cache->base + fdata.ev_offset; | |
dea80df0 MR |
3415 | CORE_ADDR off = (byte_order == BFD_ENDIAN_BIG ? 4 : 0); |
3416 | ||
063715bf | 3417 | for (i = fdata.saved_ev; i < ppc_num_gprs; i++) |
61a65099 KB |
3418 | { |
3419 | cache->saved_regs[tdep->ppc_ev0_regnum + i].addr = ev_addr; | |
dea80df0 | 3420 | cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + off; |
61a65099 | 3421 | ev_addr += register_size (gdbarch, tdep->ppc_ev0_regnum); |
dea80df0 | 3422 | } |
61a65099 KB |
3423 | } |
3424 | } | |
3425 | ||
3426 | /* If != 0, fdata.cr_offset is the offset from the frame that | |
3427 | holds the CR. */ | |
3428 | if (fdata.cr_offset != 0) | |
0df8b418 MS |
3429 | cache->saved_regs[tdep->ppc_cr_regnum].addr |
3430 | = cache->base + fdata.cr_offset; | |
61a65099 KB |
3431 | |
3432 | /* If != 0, fdata.lr_offset is the offset from the frame that | |
3433 | holds the LR. */ | |
3434 | if (fdata.lr_offset != 0) | |
0df8b418 MS |
3435 | cache->saved_regs[tdep->ppc_lr_regnum].addr |
3436 | = cache->base + fdata.lr_offset; | |
46a9b8ed DJ |
3437 | else if (fdata.lr_register != -1) |
3438 | cache->saved_regs[tdep->ppc_lr_regnum].realreg = fdata.lr_register; | |
61a65099 | 3439 | /* The PC is found in the link register. */ |
8b164abb | 3440 | cache->saved_regs[gdbarch_pc_regnum (gdbarch)] = |
3e8c568d | 3441 | cache->saved_regs[tdep->ppc_lr_regnum]; |
61a65099 KB |
3442 | |
3443 | /* If != 0, fdata.vrsave_offset is the offset from the frame that | |
3444 | holds the VRSAVE. */ | |
3445 | if (fdata.vrsave_offset != 0) | |
0df8b418 MS |
3446 | cache->saved_regs[tdep->ppc_vrsave_regnum].addr |
3447 | = cache->base + fdata.vrsave_offset; | |
61a65099 KB |
3448 | |
3449 | if (fdata.alloca_reg < 0) | |
3450 | /* If no alloca register used, then fi->frame is the value of the | |
3451 | %sp for this frame, and it is good enough. */ | |
1af5d7ce UW |
3452 | cache->initial_sp |
3453 | = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch)); | |
61a65099 | 3454 | else |
1af5d7ce UW |
3455 | cache->initial_sp |
3456 | = get_frame_register_unsigned (this_frame, fdata.alloca_reg); | |
61a65099 | 3457 | |
50ae56ec | 3458 | cache->base_p = 1; |
61a65099 KB |
3459 | return cache; |
3460 | } | |
3461 | ||
3462 | static void | |
1af5d7ce | 3463 | rs6000_frame_this_id (struct frame_info *this_frame, void **this_cache, |
61a65099 KB |
3464 | struct frame_id *this_id) |
3465 | { | |
1af5d7ce | 3466 | struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame, |
61a65099 | 3467 | this_cache); |
50ae56ec WW |
3468 | |
3469 | if (!info->base_p) | |
3470 | { | |
3471 | (*this_id) = frame_id_build_unavailable_stack (info->pc); | |
3472 | return; | |
3473 | } | |
3474 | ||
5b197912 UW |
3475 | /* This marks the outermost frame. */ |
3476 | if (info->base == 0) | |
3477 | return; | |
3478 | ||
1af5d7ce | 3479 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); |
61a65099 KB |
3480 | } |
3481 | ||
1af5d7ce UW |
3482 | static struct value * |
3483 | rs6000_frame_prev_register (struct frame_info *this_frame, | |
3484 | void **this_cache, int regnum) | |
61a65099 | 3485 | { |
1af5d7ce | 3486 | struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame, |
61a65099 | 3487 | this_cache); |
1af5d7ce | 3488 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
61a65099 KB |
3489 | } |
3490 | ||
3491 | static const struct frame_unwind rs6000_frame_unwind = | |
3492 | { | |
3493 | NORMAL_FRAME, | |
8fbca658 | 3494 | default_frame_unwind_stop_reason, |
61a65099 | 3495 | rs6000_frame_this_id, |
1af5d7ce UW |
3496 | rs6000_frame_prev_register, |
3497 | NULL, | |
3498 | default_frame_sniffer | |
61a65099 | 3499 | }; |
2608dbf8 | 3500 | |
ddeca1df WW |
3501 | /* Allocate and initialize a frame cache for an epilogue frame. |
3502 | SP is restored and prev-PC is stored in LR. */ | |
3503 | ||
2608dbf8 WW |
3504 | static struct rs6000_frame_cache * |
3505 | rs6000_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache) | |
3506 | { | |
2608dbf8 WW |
3507 | struct rs6000_frame_cache *cache; |
3508 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
3509 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2608dbf8 WW |
3510 | |
3511 | if (*this_cache) | |
19ba03f4 | 3512 | return (struct rs6000_frame_cache *) *this_cache; |
2608dbf8 WW |
3513 | |
3514 | cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache); | |
3515 | (*this_cache) = cache; | |
3516 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); | |
3517 | ||
492d29ea | 3518 | TRY |
2608dbf8 WW |
3519 | { |
3520 | /* At this point the stack looks as if we just entered the | |
3521 | function, and the return address is stored in LR. */ | |
3522 | CORE_ADDR sp, lr; | |
3523 | ||
3524 | sp = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch)); | |
3525 | lr = get_frame_register_unsigned (this_frame, tdep->ppc_lr_regnum); | |
3526 | ||
3527 | cache->base = sp; | |
3528 | cache->initial_sp = sp; | |
3529 | ||
3530 | trad_frame_set_value (cache->saved_regs, | |
3531 | gdbarch_pc_regnum (gdbarch), lr); | |
3532 | } | |
492d29ea | 3533 | CATCH (ex, RETURN_MASK_ERROR) |
7556d4a4 PA |
3534 | { |
3535 | if (ex.error != NOT_AVAILABLE_ERROR) | |
3536 | throw_exception (ex); | |
3537 | } | |
492d29ea | 3538 | END_CATCH |
2608dbf8 WW |
3539 | |
3540 | return cache; | |
3541 | } | |
3542 | ||
ddeca1df WW |
3543 | /* Implementation of frame_unwind.this_id, as defined in frame_unwind.h. |
3544 | Return the frame ID of an epilogue frame. */ | |
3545 | ||
2608dbf8 WW |
3546 | static void |
3547 | rs6000_epilogue_frame_this_id (struct frame_info *this_frame, | |
3548 | void **this_cache, struct frame_id *this_id) | |
3549 | { | |
3550 | CORE_ADDR pc; | |
3551 | struct rs6000_frame_cache *info = | |
3552 | rs6000_epilogue_frame_cache (this_frame, this_cache); | |
3553 | ||
3554 | pc = get_frame_func (this_frame); | |
3555 | if (info->base == 0) | |
3556 | (*this_id) = frame_id_build_unavailable_stack (pc); | |
3557 | else | |
3558 | (*this_id) = frame_id_build (info->base, pc); | |
3559 | } | |
3560 | ||
ddeca1df WW |
3561 | /* Implementation of frame_unwind.prev_register, as defined in frame_unwind.h. |
3562 | Return the register value of REGNUM in previous frame. */ | |
3563 | ||
2608dbf8 WW |
3564 | static struct value * |
3565 | rs6000_epilogue_frame_prev_register (struct frame_info *this_frame, | |
3566 | void **this_cache, int regnum) | |
3567 | { | |
3568 | struct rs6000_frame_cache *info = | |
3569 | rs6000_epilogue_frame_cache (this_frame, this_cache); | |
3570 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); | |
3571 | } | |
3572 | ||
ddeca1df WW |
3573 | /* Implementation of frame_unwind.sniffer, as defined in frame_unwind.h. |
3574 | Check whether this an epilogue frame. */ | |
3575 | ||
2608dbf8 WW |
3576 | static int |
3577 | rs6000_epilogue_frame_sniffer (const struct frame_unwind *self, | |
3578 | struct frame_info *this_frame, | |
3579 | void **this_prologue_cache) | |
3580 | { | |
3581 | if (frame_relative_level (this_frame) == 0) | |
3582 | return rs6000_in_function_epilogue_frame_p (this_frame, | |
3583 | get_frame_arch (this_frame), | |
3584 | get_frame_pc (this_frame)); | |
3585 | else | |
3586 | return 0; | |
3587 | } | |
3588 | ||
ddeca1df WW |
3589 | /* Frame unwinder for epilogue frame. This is required for reverse step-over |
3590 | a function without debug information. */ | |
3591 | ||
2608dbf8 WW |
3592 | static const struct frame_unwind rs6000_epilogue_frame_unwind = |
3593 | { | |
3594 | NORMAL_FRAME, | |
3595 | default_frame_unwind_stop_reason, | |
3596 | rs6000_epilogue_frame_this_id, rs6000_epilogue_frame_prev_register, | |
3597 | NULL, | |
3598 | rs6000_epilogue_frame_sniffer | |
3599 | }; | |
61a65099 KB |
3600 | \f |
3601 | ||
3602 | static CORE_ADDR | |
1af5d7ce | 3603 | rs6000_frame_base_address (struct frame_info *this_frame, void **this_cache) |
61a65099 | 3604 | { |
1af5d7ce | 3605 | struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame, |
61a65099 KB |
3606 | this_cache); |
3607 | return info->initial_sp; | |
3608 | } | |
3609 | ||
3610 | static const struct frame_base rs6000_frame_base = { | |
3611 | &rs6000_frame_unwind, | |
3612 | rs6000_frame_base_address, | |
3613 | rs6000_frame_base_address, | |
3614 | rs6000_frame_base_address | |
3615 | }; | |
3616 | ||
3617 | static const struct frame_base * | |
1af5d7ce | 3618 | rs6000_frame_base_sniffer (struct frame_info *this_frame) |
61a65099 KB |
3619 | { |
3620 | return &rs6000_frame_base; | |
3621 | } | |
3622 | ||
9274a07c LM |
3623 | /* DWARF-2 frame support. Used to handle the detection of |
3624 | clobbered registers during function calls. */ | |
3625 | ||
3626 | static void | |
3627 | ppc_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
3628 | struct dwarf2_frame_state_reg *reg, | |
4a4e5149 | 3629 | struct frame_info *this_frame) |
9274a07c LM |
3630 | { |
3631 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3632 | ||
3633 | /* PPC32 and PPC64 ABI's are the same regarding volatile and | |
3634 | non-volatile registers. We will use the same code for both. */ | |
3635 | ||
3636 | /* Call-saved GP registers. */ | |
3637 | if ((regnum >= tdep->ppc_gp0_regnum + 14 | |
3638 | && regnum <= tdep->ppc_gp0_regnum + 31) | |
3639 | || (regnum == tdep->ppc_gp0_regnum + 1)) | |
3640 | reg->how = DWARF2_FRAME_REG_SAME_VALUE; | |
3641 | ||
3642 | /* Call-clobbered GP registers. */ | |
3643 | if ((regnum >= tdep->ppc_gp0_regnum + 3 | |
3644 | && regnum <= tdep->ppc_gp0_regnum + 12) | |
3645 | || (regnum == tdep->ppc_gp0_regnum)) | |
3646 | reg->how = DWARF2_FRAME_REG_UNDEFINED; | |
3647 | ||
3648 | /* Deal with FP registers, if supported. */ | |
3649 | if (tdep->ppc_fp0_regnum >= 0) | |
3650 | { | |
3651 | /* Call-saved FP registers. */ | |
3652 | if ((regnum >= tdep->ppc_fp0_regnum + 14 | |
3653 | && regnum <= tdep->ppc_fp0_regnum + 31)) | |
3654 | reg->how = DWARF2_FRAME_REG_SAME_VALUE; | |
3655 | ||
3656 | /* Call-clobbered FP registers. */ | |
3657 | if ((regnum >= tdep->ppc_fp0_regnum | |
3658 | && regnum <= tdep->ppc_fp0_regnum + 13)) | |
3659 | reg->how = DWARF2_FRAME_REG_UNDEFINED; | |
3660 | } | |
3661 | ||
3662 | /* Deal with ALTIVEC registers, if supported. */ | |
3663 | if (tdep->ppc_vr0_regnum > 0 && tdep->ppc_vrsave_regnum > 0) | |
3664 | { | |
3665 | /* Call-saved Altivec registers. */ | |
3666 | if ((regnum >= tdep->ppc_vr0_regnum + 20 | |
3667 | && regnum <= tdep->ppc_vr0_regnum + 31) | |
3668 | || regnum == tdep->ppc_vrsave_regnum) | |
3669 | reg->how = DWARF2_FRAME_REG_SAME_VALUE; | |
3670 | ||
3671 | /* Call-clobbered Altivec registers. */ | |
3672 | if ((regnum >= tdep->ppc_vr0_regnum | |
3673 | && regnum <= tdep->ppc_vr0_regnum + 19)) | |
3674 | reg->how = DWARF2_FRAME_REG_UNDEFINED; | |
3675 | } | |
3676 | ||
3677 | /* Handle PC register and Stack Pointer correctly. */ | |
40a6adc1 | 3678 | if (regnum == gdbarch_pc_regnum (gdbarch)) |
9274a07c | 3679 | reg->how = DWARF2_FRAME_REG_RA; |
40a6adc1 | 3680 | else if (regnum == gdbarch_sp_regnum (gdbarch)) |
9274a07c LM |
3681 | reg->how = DWARF2_FRAME_REG_CFA; |
3682 | } | |
3683 | ||
3684 | ||
74af9197 NF |
3685 | /* Return true if a .gnu_attributes section exists in BFD and it |
3686 | indicates we are using SPE extensions OR if a .PPC.EMB.apuinfo | |
3687 | section exists in BFD and it indicates that SPE extensions are in | |
3688 | use. Check the .gnu.attributes section first, as the binary might be | |
3689 | compiled for SPE, but not actually using SPE instructions. */ | |
3690 | ||
3691 | static int | |
3692 | bfd_uses_spe_extensions (bfd *abfd) | |
3693 | { | |
3694 | asection *sect; | |
3695 | gdb_byte *contents = NULL; | |
3696 | bfd_size_type size; | |
3697 | gdb_byte *ptr; | |
3698 | int success = 0; | |
3699 | int vector_abi; | |
3700 | ||
3701 | if (!abfd) | |
3702 | return 0; | |
3703 | ||
50a99728 | 3704 | #ifdef HAVE_ELF |
74af9197 NF |
3705 | /* Using Tag_GNU_Power_ABI_Vector here is a bit of a hack, as the user |
3706 | could be using the SPE vector abi without actually using any spe | |
3707 | bits whatsoever. But it's close enough for now. */ | |
3708 | vector_abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_GNU, | |
3709 | Tag_GNU_Power_ABI_Vector); | |
3710 | if (vector_abi == 3) | |
3711 | return 1; | |
50a99728 | 3712 | #endif |
74af9197 NF |
3713 | |
3714 | sect = bfd_get_section_by_name (abfd, ".PPC.EMB.apuinfo"); | |
3715 | if (!sect) | |
3716 | return 0; | |
3717 | ||
3718 | size = bfd_get_section_size (sect); | |
224c3ddb | 3719 | contents = (gdb_byte *) xmalloc (size); |
74af9197 NF |
3720 | if (!bfd_get_section_contents (abfd, sect, contents, 0, size)) |
3721 | { | |
3722 | xfree (contents); | |
3723 | return 0; | |
3724 | } | |
3725 | ||
3726 | /* Parse the .PPC.EMB.apuinfo section. The layout is as follows: | |
3727 | ||
3728 | struct { | |
3729 | uint32 name_len; | |
3730 | uint32 data_len; | |
3731 | uint32 type; | |
3732 | char name[name_len rounded up to 4-byte alignment]; | |
3733 | char data[data_len]; | |
3734 | }; | |
3735 | ||
3736 | Technically, there's only supposed to be one such structure in a | |
3737 | given apuinfo section, but the linker is not always vigilant about | |
3738 | merging apuinfo sections from input files. Just go ahead and parse | |
3739 | them all, exiting early when we discover the binary uses SPE | |
3740 | insns. | |
3741 | ||
3742 | It's not specified in what endianness the information in this | |
3743 | section is stored. Assume that it's the endianness of the BFD. */ | |
3744 | ptr = contents; | |
3745 | while (1) | |
3746 | { | |
3747 | unsigned int name_len; | |
3748 | unsigned int data_len; | |
3749 | unsigned int type; | |
3750 | ||
3751 | /* If we can't read the first three fields, we're done. */ | |
3752 | if (size < 12) | |
3753 | break; | |
3754 | ||
3755 | name_len = bfd_get_32 (abfd, ptr); | |
3756 | name_len = (name_len + 3) & ~3U; /* Round to 4 bytes. */ | |
3757 | data_len = bfd_get_32 (abfd, ptr + 4); | |
3758 | type = bfd_get_32 (abfd, ptr + 8); | |
3759 | ptr += 12; | |
3760 | ||
3761 | /* The name must be "APUinfo\0". */ | |
3762 | if (name_len != 8 | |
3763 | && strcmp ((const char *) ptr, "APUinfo") != 0) | |
3764 | break; | |
3765 | ptr += name_len; | |
3766 | ||
3767 | /* The type must be 2. */ | |
3768 | if (type != 2) | |
3769 | break; | |
3770 | ||
3771 | /* The data is stored as a series of uint32. The upper half of | |
3772 | each uint32 indicates the particular APU used and the lower | |
3773 | half indicates the revision of that APU. We just care about | |
3774 | the upper half. */ | |
3775 | ||
3776 | /* Not 4-byte quantities. */ | |
3777 | if (data_len & 3U) | |
3778 | break; | |
3779 | ||
3780 | while (data_len) | |
3781 | { | |
3782 | unsigned int apuinfo = bfd_get_32 (abfd, ptr); | |
3783 | unsigned int apu = apuinfo >> 16; | |
3784 | ptr += 4; | |
3785 | data_len -= 4; | |
3786 | ||
3787 | /* The SPE APU is 0x100; the SPEFP APU is 0x101. Accept | |
3788 | either. */ | |
3789 | if (apu == 0x100 || apu == 0x101) | |
3790 | { | |
3791 | success = 1; | |
3792 | data_len = 0; | |
3793 | } | |
3794 | } | |
3795 | ||
3796 | if (success) | |
3797 | break; | |
3798 | } | |
3799 | ||
3800 | xfree (contents); | |
3801 | return success; | |
3802 | } | |
3803 | ||
b4cdae6f WW |
3804 | /* These are macros for parsing instruction fields (I.1.6.28) */ |
3805 | ||
3806 | #define PPC_FIELD(value, from, len) \ | |
3807 | (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1)) | |
3808 | #define PPC_SEXT(v, bs) \ | |
3809 | ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \ | |
3810 | ^ ((CORE_ADDR) 1 << ((bs) - 1))) \ | |
3811 | - ((CORE_ADDR) 1 << ((bs) - 1))) | |
3812 | #define PPC_OP6(insn) PPC_FIELD (insn, 0, 6) | |
3813 | #define PPC_EXTOP(insn) PPC_FIELD (insn, 21, 10) | |
3814 | #define PPC_RT(insn) PPC_FIELD (insn, 6, 5) | |
3815 | #define PPC_RS(insn) PPC_FIELD (insn, 6, 5) | |
3816 | #define PPC_RA(insn) PPC_FIELD (insn, 11, 5) | |
3817 | #define PPC_RB(insn) PPC_FIELD (insn, 16, 5) | |
3818 | #define PPC_NB(insn) PPC_FIELD (insn, 16, 5) | |
3819 | #define PPC_VRT(insn) PPC_FIELD (insn, 6, 5) | |
3820 | #define PPC_FRT(insn) PPC_FIELD (insn, 6, 5) | |
3821 | #define PPC_SPR(insn) (PPC_FIELD (insn, 11, 5) \ | |
3822 | | (PPC_FIELD (insn, 16, 5) << 5)) | |
3823 | #define PPC_BO(insn) PPC_FIELD (insn, 6, 5) | |
3824 | #define PPC_T(insn) PPC_FIELD (insn, 6, 5) | |
3825 | #define PPC_D(insn) PPC_SEXT (PPC_FIELD (insn, 16, 16), 16) | |
3826 | #define PPC_DS(insn) PPC_SEXT (PPC_FIELD (insn, 16, 14), 14) | |
6ec2b213 | 3827 | #define PPC_DQ(insn) PPC_SEXT (PPC_FIELD (insn, 16, 12), 12) |
b4cdae6f WW |
3828 | #define PPC_BIT(insn,n) ((insn & (1 << (31 - (n)))) ? 1 : 0) |
3829 | #define PPC_OE(insn) PPC_BIT (insn, 21) | |
3830 | #define PPC_RC(insn) PPC_BIT (insn, 31) | |
3831 | #define PPC_Rc(insn) PPC_BIT (insn, 21) | |
3832 | #define PPC_LK(insn) PPC_BIT (insn, 31) | |
3833 | #define PPC_TX(insn) PPC_BIT (insn, 31) | |
3834 | #define PPC_LEV(insn) PPC_FIELD (insn, 20, 7) | |
3835 | ||
3836 | #define PPC_XT(insn) ((PPC_TX (insn) << 5) | PPC_T (insn)) | |
3837 | #define PPC_XER_NB(xer) (xer & 0x7f) | |
3838 | ||
ddeca1df WW |
3839 | /* Record Vector-Scalar Registers. |
3840 | For VSR less than 32, it's represented by an FPR and an VSR-upper register. | |
3841 | Otherwise, it's just a VR register. Record them accordingly. */ | |
b4cdae6f WW |
3842 | |
3843 | static int | |
3844 | ppc_record_vsr (struct regcache *regcache, struct gdbarch_tdep *tdep, int vsr) | |
3845 | { | |
3846 | if (vsr < 0 || vsr >= 64) | |
3847 | return -1; | |
3848 | ||
3849 | if (vsr >= 32) | |
3850 | { | |
3851 | if (tdep->ppc_vr0_regnum >= 0) | |
3852 | record_full_arch_list_add_reg (regcache, tdep->ppc_vr0_regnum + vsr - 32); | |
3853 | } | |
3854 | else | |
3855 | { | |
3856 | if (tdep->ppc_fp0_regnum >= 0) | |
3857 | record_full_arch_list_add_reg (regcache, tdep->ppc_fp0_regnum + vsr); | |
3858 | if (tdep->ppc_vsr0_upper_regnum >= 0) | |
3859 | record_full_arch_list_add_reg (regcache, | |
3860 | tdep->ppc_vsr0_upper_regnum + vsr); | |
3861 | } | |
3862 | ||
3863 | return 0; | |
3864 | } | |
3865 | ||
ddeca1df WW |
3866 | /* Parse and record instructions primary opcode-4 at ADDR. |
3867 | Return 0 if successful. */ | |
b4cdae6f WW |
3868 | |
3869 | static int | |
3870 | ppc_process_record_op4 (struct gdbarch *gdbarch, struct regcache *regcache, | |
ddeca1df | 3871 | CORE_ADDR addr, uint32_t insn) |
b4cdae6f WW |
3872 | { |
3873 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3874 | int ext = PPC_FIELD (insn, 21, 11); | |
6ec2b213 | 3875 | int vra = PPC_FIELD (insn, 11, 5); |
b4cdae6f WW |
3876 | |
3877 | switch (ext & 0x3f) | |
3878 | { | |
3879 | case 32: /* Vector Multiply-High-Add Signed Halfword Saturate */ | |
3880 | case 33: /* Vector Multiply-High-Round-Add Signed Halfword Saturate */ | |
3881 | case 39: /* Vector Multiply-Sum Unsigned Halfword Saturate */ | |
3882 | case 41: /* Vector Multiply-Sum Signed Halfword Saturate */ | |
3883 | record_full_arch_list_add_reg (regcache, PPC_VSCR_REGNUM); | |
3884 | /* FALL-THROUGH */ | |
3885 | case 42: /* Vector Select */ | |
3886 | case 43: /* Vector Permute */ | |
6ec2b213 | 3887 | case 59: /* Vector Permute Right-indexed */ |
b4cdae6f WW |
3888 | case 44: /* Vector Shift Left Double by Octet Immediate */ |
3889 | case 45: /* Vector Permute and Exclusive-OR */ | |
3890 | case 60: /* Vector Add Extended Unsigned Quadword Modulo */ | |
3891 | case 61: /* Vector Add Extended & write Carry Unsigned Quadword */ | |
3892 | case 62: /* Vector Subtract Extended Unsigned Quadword Modulo */ | |
3893 | case 63: /* Vector Subtract Extended & write Carry Unsigned Quadword */ | |
3894 | case 34: /* Vector Multiply-Low-Add Unsigned Halfword Modulo */ | |
6ec2b213 | 3895 | case 35: /* Vector Multiply-Sum Unsigned Doubleword Modulo */ |
b4cdae6f WW |
3896 | case 36: /* Vector Multiply-Sum Unsigned Byte Modulo */ |
3897 | case 37: /* Vector Multiply-Sum Mixed Byte Modulo */ | |
3898 | case 38: /* Vector Multiply-Sum Unsigned Halfword Modulo */ | |
3899 | case 40: /* Vector Multiply-Sum Signed Halfword Modulo */ | |
3900 | case 46: /* Vector Multiply-Add Single-Precision */ | |
3901 | case 47: /* Vector Negative Multiply-Subtract Single-Precision */ | |
3902 | record_full_arch_list_add_reg (regcache, | |
3903 | tdep->ppc_vr0_regnum + PPC_VRT (insn)); | |
3904 | return 0; | |
6ec2b213 EBM |
3905 | |
3906 | case 48: /* Multiply-Add High Doubleword */ | |
3907 | case 49: /* Multiply-Add High Doubleword Unsigned */ | |
3908 | case 51: /* Multiply-Add Low Doubleword */ | |
3909 | record_full_arch_list_add_reg (regcache, | |
3910 | tdep->ppc_gp0_regnum + PPC_RT (insn)); | |
3911 | return 0; | |
b4cdae6f WW |
3912 | } |
3913 | ||
3914 | switch ((ext & 0x1ff)) | |
3915 | { | |
6ec2b213 EBM |
3916 | case 385: |
3917 | if (vra != 0 /* Decimal Convert To Signed Quadword */ | |
3918 | && vra != 2 /* Decimal Convert From Signed Quadword */ | |
3919 | && vra != 4 /* Decimal Convert To Zoned */ | |
3920 | && vra != 5 /* Decimal Convert To National */ | |
3921 | && vra != 6 /* Decimal Convert From Zoned */ | |
3922 | && vra != 7 /* Decimal Convert From National */ | |
3923 | && vra != 31) /* Decimal Set Sign */ | |
3924 | break; | |
b4cdae6f WW |
3925 | /* 5.16 Decimal Integer Arithmetic Instructions */ |
3926 | case 1: /* Decimal Add Modulo */ | |
3927 | case 65: /* Decimal Subtract Modulo */ | |
3928 | ||
6ec2b213 EBM |
3929 | case 193: /* Decimal Shift */ |
3930 | case 129: /* Decimal Unsigned Shift */ | |
3931 | case 449: /* Decimal Shift and Round */ | |
3932 | ||
3933 | case 257: /* Decimal Truncate */ | |
3934 | case 321: /* Decimal Unsigned Truncate */ | |
3935 | ||
b4cdae6f WW |
3936 | /* Bit-21 should be set. */ |
3937 | if (!PPC_BIT (insn, 21)) | |
3938 | break; | |
3939 | ||
3940 | record_full_arch_list_add_reg (regcache, | |
3941 | tdep->ppc_vr0_regnum + PPC_VRT (insn)); | |
3942 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
3943 | return 0; | |
3944 | } | |
3945 | ||
3946 | /* Bit-21 is used for RC */ | |
3947 | switch (ext & 0x3ff) | |
3948 | { | |
3949 | case 6: /* Vector Compare Equal To Unsigned Byte */ | |
3950 | case 70: /* Vector Compare Equal To Unsigned Halfword */ | |
3951 | case 134: /* Vector Compare Equal To Unsigned Word */ | |
3952 | case 199: /* Vector Compare Equal To Unsigned Doubleword */ | |
3953 | case 774: /* Vector Compare Greater Than Signed Byte */ | |
3954 | case 838: /* Vector Compare Greater Than Signed Halfword */ | |
3955 | case 902: /* Vector Compare Greater Than Signed Word */ | |
3956 | case 967: /* Vector Compare Greater Than Signed Doubleword */ | |
3957 | case 518: /* Vector Compare Greater Than Unsigned Byte */ | |
3958 | case 646: /* Vector Compare Greater Than Unsigned Word */ | |
3959 | case 582: /* Vector Compare Greater Than Unsigned Halfword */ | |
3960 | case 711: /* Vector Compare Greater Than Unsigned Doubleword */ | |
3961 | case 966: /* Vector Compare Bounds Single-Precision */ | |
3962 | case 198: /* Vector Compare Equal To Single-Precision */ | |
3963 | case 454: /* Vector Compare Greater Than or Equal To Single-Precision */ | |
3964 | case 710: /* Vector Compare Greater Than Single-Precision */ | |
6ec2b213 EBM |
3965 | case 7: /* Vector Compare Not Equal Byte */ |
3966 | case 71: /* Vector Compare Not Equal Halfword */ | |
3967 | case 135: /* Vector Compare Not Equal Word */ | |
3968 | case 263: /* Vector Compare Not Equal or Zero Byte */ | |
3969 | case 327: /* Vector Compare Not Equal or Zero Halfword */ | |
3970 | case 391: /* Vector Compare Not Equal or Zero Word */ | |
b4cdae6f WW |
3971 | if (PPC_Rc (insn)) |
3972 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
3973 | record_full_arch_list_add_reg (regcache, | |
3974 | tdep->ppc_vr0_regnum + PPC_VRT (insn)); | |
3975 | return 0; | |
3976 | } | |
3977 | ||
6ec2b213 EBM |
3978 | if (ext == 1538) |
3979 | { | |
3980 | switch (vra) | |
3981 | { | |
3982 | case 0: /* Vector Count Leading Zero Least-Significant Bits | |
3983 | Byte */ | |
3984 | case 1: /* Vector Count Trailing Zero Least-Significant Bits | |
3985 | Byte */ | |
3986 | record_full_arch_list_add_reg (regcache, | |
3987 | tdep->ppc_gp0_regnum + PPC_RT (insn)); | |
3988 | return 0; | |
3989 | ||
3990 | case 6: /* Vector Negate Word */ | |
3991 | case 7: /* Vector Negate Doubleword */ | |
3992 | case 8: /* Vector Parity Byte Word */ | |
3993 | case 9: /* Vector Parity Byte Doubleword */ | |
3994 | case 10: /* Vector Parity Byte Quadword */ | |
3995 | case 16: /* Vector Extend Sign Byte To Word */ | |
3996 | case 17: /* Vector Extend Sign Halfword To Word */ | |
3997 | case 24: /* Vector Extend Sign Byte To Doubleword */ | |
3998 | case 25: /* Vector Extend Sign Halfword To Doubleword */ | |
3999 | case 26: /* Vector Extend Sign Word To Doubleword */ | |
4000 | case 28: /* Vector Count Trailing Zeros Byte */ | |
4001 | case 29: /* Vector Count Trailing Zeros Halfword */ | |
4002 | case 30: /* Vector Count Trailing Zeros Word */ | |
4003 | case 31: /* Vector Count Trailing Zeros Doubleword */ | |
4004 | record_full_arch_list_add_reg (regcache, | |
4005 | tdep->ppc_vr0_regnum + PPC_VRT (insn)); | |
4006 | return 0; | |
4007 | } | |
4008 | } | |
4009 | ||
b4cdae6f WW |
4010 | switch (ext) |
4011 | { | |
4012 | case 142: /* Vector Pack Unsigned Halfword Unsigned Saturate */ | |
4013 | case 206: /* Vector Pack Unsigned Word Unsigned Saturate */ | |
4014 | case 270: /* Vector Pack Signed Halfword Unsigned Saturate */ | |
4015 | case 334: /* Vector Pack Signed Word Unsigned Saturate */ | |
4016 | case 398: /* Vector Pack Signed Halfword Signed Saturate */ | |
4017 | case 462: /* Vector Pack Signed Word Signed Saturate */ | |
4018 | case 1230: /* Vector Pack Unsigned Doubleword Unsigned Saturate */ | |
4019 | case 1358: /* Vector Pack Signed Doubleword Unsigned Saturate */ | |
4020 | case 1486: /* Vector Pack Signed Doubleword Signed Saturate */ | |
4021 | case 512: /* Vector Add Unsigned Byte Saturate */ | |
4022 | case 576: /* Vector Add Unsigned Halfword Saturate */ | |
4023 | case 640: /* Vector Add Unsigned Word Saturate */ | |
4024 | case 768: /* Vector Add Signed Byte Saturate */ | |
4025 | case 832: /* Vector Add Signed Halfword Saturate */ | |
4026 | case 896: /* Vector Add Signed Word Saturate */ | |
4027 | case 1536: /* Vector Subtract Unsigned Byte Saturate */ | |
4028 | case 1600: /* Vector Subtract Unsigned Halfword Saturate */ | |
4029 | case 1664: /* Vector Subtract Unsigned Word Saturate */ | |
4030 | case 1792: /* Vector Subtract Signed Byte Saturate */ | |
4031 | case 1856: /* Vector Subtract Signed Halfword Saturate */ | |
4032 | case 1920: /* Vector Subtract Signed Word Saturate */ | |
4033 | ||
4034 | case 1544: /* Vector Sum across Quarter Unsigned Byte Saturate */ | |
4035 | case 1800: /* Vector Sum across Quarter Signed Byte Saturate */ | |
4036 | case 1608: /* Vector Sum across Quarter Signed Halfword Saturate */ | |
4037 | case 1672: /* Vector Sum across Half Signed Word Saturate */ | |
4038 | case 1928: /* Vector Sum across Signed Word Saturate */ | |
4039 | case 970: /* Vector Convert To Signed Fixed-Point Word Saturate */ | |
4040 | case 906: /* Vector Convert To Unsigned Fixed-Point Word Saturate */ | |
4041 | record_full_arch_list_add_reg (regcache, PPC_VSCR_REGNUM); | |
4042 | /* FALL-THROUGH */ | |
4043 | case 12: /* Vector Merge High Byte */ | |
4044 | case 14: /* Vector Pack Unsigned Halfword Unsigned Modulo */ | |
4045 | case 76: /* Vector Merge High Halfword */ | |
4046 | case 78: /* Vector Pack Unsigned Word Unsigned Modulo */ | |
4047 | case 140: /* Vector Merge High Word */ | |
4048 | case 268: /* Vector Merge Low Byte */ | |
4049 | case 332: /* Vector Merge Low Halfword */ | |
4050 | case 396: /* Vector Merge Low Word */ | |
4051 | case 526: /* Vector Unpack High Signed Byte */ | |
4052 | case 590: /* Vector Unpack High Signed Halfword */ | |
4053 | case 654: /* Vector Unpack Low Signed Byte */ | |
4054 | case 718: /* Vector Unpack Low Signed Halfword */ | |
4055 | case 782: /* Vector Pack Pixel */ | |
4056 | case 846: /* Vector Unpack High Pixel */ | |
4057 | case 974: /* Vector Unpack Low Pixel */ | |
4058 | case 1102: /* Vector Pack Unsigned Doubleword Unsigned Modulo */ | |
4059 | case 1614: /* Vector Unpack High Signed Word */ | |
4060 | case 1676: /* Vector Merge Odd Word */ | |
4061 | case 1742: /* Vector Unpack Low Signed Word */ | |
4062 | case 1932: /* Vector Merge Even Word */ | |
4063 | case 524: /* Vector Splat Byte */ | |
4064 | case 588: /* Vector Splat Halfword */ | |
4065 | case 652: /* Vector Splat Word */ | |
4066 | case 780: /* Vector Splat Immediate Signed Byte */ | |
4067 | case 844: /* Vector Splat Immediate Signed Halfword */ | |
4068 | case 908: /* Vector Splat Immediate Signed Word */ | |
4069 | case 452: /* Vector Shift Left */ | |
4070 | case 708: /* Vector Shift Right */ | |
4071 | case 1036: /* Vector Shift Left by Octet */ | |
4072 | case 1100: /* Vector Shift Right by Octet */ | |
4073 | case 0: /* Vector Add Unsigned Byte Modulo */ | |
4074 | case 64: /* Vector Add Unsigned Halfword Modulo */ | |
4075 | case 128: /* Vector Add Unsigned Word Modulo */ | |
4076 | case 192: /* Vector Add Unsigned Doubleword Modulo */ | |
4077 | case 256: /* Vector Add Unsigned Quadword Modulo */ | |
4078 | case 320: /* Vector Add & write Carry Unsigned Quadword */ | |
4079 | case 384: /* Vector Add and Write Carry-Out Unsigned Word */ | |
4080 | case 8: /* Vector Multiply Odd Unsigned Byte */ | |
4081 | case 72: /* Vector Multiply Odd Unsigned Halfword */ | |
4082 | case 136: /* Vector Multiply Odd Unsigned Word */ | |
4083 | case 264: /* Vector Multiply Odd Signed Byte */ | |
4084 | case 328: /* Vector Multiply Odd Signed Halfword */ | |
4085 | case 392: /* Vector Multiply Odd Signed Word */ | |
4086 | case 520: /* Vector Multiply Even Unsigned Byte */ | |
4087 | case 584: /* Vector Multiply Even Unsigned Halfword */ | |
4088 | case 648: /* Vector Multiply Even Unsigned Word */ | |
4089 | case 776: /* Vector Multiply Even Signed Byte */ | |
4090 | case 840: /* Vector Multiply Even Signed Halfword */ | |
4091 | case 904: /* Vector Multiply Even Signed Word */ | |
4092 | case 137: /* Vector Multiply Unsigned Word Modulo */ | |
4093 | case 1024: /* Vector Subtract Unsigned Byte Modulo */ | |
4094 | case 1088: /* Vector Subtract Unsigned Halfword Modulo */ | |
4095 | case 1152: /* Vector Subtract Unsigned Word Modulo */ | |
4096 | case 1216: /* Vector Subtract Unsigned Doubleword Modulo */ | |
4097 | case 1280: /* Vector Subtract Unsigned Quadword Modulo */ | |
4098 | case 1344: /* Vector Subtract & write Carry Unsigned Quadword */ | |
4099 | case 1408: /* Vector Subtract and Write Carry-Out Unsigned Word */ | |
4100 | case 1282: /* Vector Average Signed Byte */ | |
4101 | case 1346: /* Vector Average Signed Halfword */ | |
4102 | case 1410: /* Vector Average Signed Word */ | |
4103 | case 1026: /* Vector Average Unsigned Byte */ | |
4104 | case 1090: /* Vector Average Unsigned Halfword */ | |
4105 | case 1154: /* Vector Average Unsigned Word */ | |
4106 | case 258: /* Vector Maximum Signed Byte */ | |
4107 | case 322: /* Vector Maximum Signed Halfword */ | |
4108 | case 386: /* Vector Maximum Signed Word */ | |
4109 | case 450: /* Vector Maximum Signed Doubleword */ | |
4110 | case 2: /* Vector Maximum Unsigned Byte */ | |
4111 | case 66: /* Vector Maximum Unsigned Halfword */ | |
4112 | case 130: /* Vector Maximum Unsigned Word */ | |
4113 | case 194: /* Vector Maximum Unsigned Doubleword */ | |
4114 | case 770: /* Vector Minimum Signed Byte */ | |
4115 | case 834: /* Vector Minimum Signed Halfword */ | |
4116 | case 898: /* Vector Minimum Signed Word */ | |
4117 | case 962: /* Vector Minimum Signed Doubleword */ | |
4118 | case 514: /* Vector Minimum Unsigned Byte */ | |
4119 | case 578: /* Vector Minimum Unsigned Halfword */ | |
4120 | case 642: /* Vector Minimum Unsigned Word */ | |
4121 | case 706: /* Vector Minimum Unsigned Doubleword */ | |
4122 | case 1028: /* Vector Logical AND */ | |
4123 | case 1668: /* Vector Logical Equivalent */ | |
4124 | case 1092: /* Vector Logical AND with Complement */ | |
4125 | case 1412: /* Vector Logical NAND */ | |
4126 | case 1348: /* Vector Logical OR with Complement */ | |
4127 | case 1156: /* Vector Logical OR */ | |
4128 | case 1284: /* Vector Logical NOR */ | |
4129 | case 1220: /* Vector Logical XOR */ | |
4130 | case 4: /* Vector Rotate Left Byte */ | |
4131 | case 132: /* Vector Rotate Left Word VX-form */ | |
4132 | case 68: /* Vector Rotate Left Halfword */ | |
4133 | case 196: /* Vector Rotate Left Doubleword */ | |
4134 | case 260: /* Vector Shift Left Byte */ | |
4135 | case 388: /* Vector Shift Left Word */ | |
4136 | case 324: /* Vector Shift Left Halfword */ | |
4137 | case 1476: /* Vector Shift Left Doubleword */ | |
4138 | case 516: /* Vector Shift Right Byte */ | |
4139 | case 644: /* Vector Shift Right Word */ | |
4140 | case 580: /* Vector Shift Right Halfword */ | |
4141 | case 1732: /* Vector Shift Right Doubleword */ | |
4142 | case 772: /* Vector Shift Right Algebraic Byte */ | |
4143 | case 900: /* Vector Shift Right Algebraic Word */ | |
4144 | case 836: /* Vector Shift Right Algebraic Halfword */ | |
4145 | case 964: /* Vector Shift Right Algebraic Doubleword */ | |
4146 | case 10: /* Vector Add Single-Precision */ | |
4147 | case 74: /* Vector Subtract Single-Precision */ | |
4148 | case 1034: /* Vector Maximum Single-Precision */ | |
4149 | case 1098: /* Vector Minimum Single-Precision */ | |
4150 | case 842: /* Vector Convert From Signed Fixed-Point Word */ | |
4151 | case 778: /* Vector Convert From Unsigned Fixed-Point Word */ | |
4152 | case 714: /* Vector Round to Single-Precision Integer toward -Infinity */ | |
4153 | case 522: /* Vector Round to Single-Precision Integer Nearest */ | |
4154 | case 650: /* Vector Round to Single-Precision Integer toward +Infinity */ | |
4155 | case 586: /* Vector Round to Single-Precision Integer toward Zero */ | |
4156 | case 394: /* Vector 2 Raised to the Exponent Estimate Floating-Point */ | |
4157 | case 458: /* Vector Log Base 2 Estimate Floating-Point */ | |
4158 | case 266: /* Vector Reciprocal Estimate Single-Precision */ | |
4159 | case 330: /* Vector Reciprocal Square Root Estimate Single-Precision */ | |
4160 | case 1288: /* Vector AES Cipher */ | |
4161 | case 1289: /* Vector AES Cipher Last */ | |
4162 | case 1352: /* Vector AES Inverse Cipher */ | |
4163 | case 1353: /* Vector AES Inverse Cipher Last */ | |
4164 | case 1480: /* Vector AES SubBytes */ | |
4165 | case 1730: /* Vector SHA-512 Sigma Doubleword */ | |
4166 | case 1666: /* Vector SHA-256 Sigma Word */ | |
4167 | case 1032: /* Vector Polynomial Multiply-Sum Byte */ | |
4168 | case 1160: /* Vector Polynomial Multiply-Sum Word */ | |
4169 | case 1096: /* Vector Polynomial Multiply-Sum Halfword */ | |
4170 | case 1224: /* Vector Polynomial Multiply-Sum Doubleword */ | |
4171 | case 1292: /* Vector Gather Bits by Bytes by Doubleword */ | |
4172 | case 1794: /* Vector Count Leading Zeros Byte */ | |
4173 | case 1858: /* Vector Count Leading Zeros Halfword */ | |
4174 | case 1922: /* Vector Count Leading Zeros Word */ | |
4175 | case 1986: /* Vector Count Leading Zeros Doubleword */ | |
4176 | case 1795: /* Vector Population Count Byte */ | |
4177 | case 1859: /* Vector Population Count Halfword */ | |
4178 | case 1923: /* Vector Population Count Word */ | |
4179 | case 1987: /* Vector Population Count Doubleword */ | |
4180 | case 1356: /* Vector Bit Permute Quadword */ | |
6ec2b213 EBM |
4181 | case 1484: /* Vector Bit Permute Doubleword */ |
4182 | case 513: /* Vector Multiply-by-10 Unsigned Quadword */ | |
4183 | case 1: /* Vector Multiply-by-10 & write Carry Unsigned | |
4184 | Quadword */ | |
4185 | case 577: /* Vector Multiply-by-10 Extended Unsigned Quadword */ | |
4186 | case 65: /* Vector Multiply-by-10 Extended & write Carry | |
4187 | Unsigned Quadword */ | |
4188 | case 1027: /* Vector Absolute Difference Unsigned Byte */ | |
4189 | case 1091: /* Vector Absolute Difference Unsigned Halfword */ | |
4190 | case 1155: /* Vector Absolute Difference Unsigned Word */ | |
4191 | case 1796: /* Vector Shift Right Variable */ | |
4192 | case 1860: /* Vector Shift Left Variable */ | |
4193 | case 133: /* Vector Rotate Left Word then Mask Insert */ | |
4194 | case 197: /* Vector Rotate Left Doubleword then Mask Insert */ | |
4195 | case 389: /* Vector Rotate Left Word then AND with Mask */ | |
4196 | case 453: /* Vector Rotate Left Doubleword then AND with Mask */ | |
4197 | case 525: /* Vector Extract Unsigned Byte */ | |
4198 | case 589: /* Vector Extract Unsigned Halfword */ | |
4199 | case 653: /* Vector Extract Unsigned Word */ | |
4200 | case 717: /* Vector Extract Doubleword */ | |
4201 | case 781: /* Vector Insert Byte */ | |
4202 | case 845: /* Vector Insert Halfword */ | |
4203 | case 909: /* Vector Insert Word */ | |
4204 | case 973: /* Vector Insert Doubleword */ | |
b4cdae6f WW |
4205 | record_full_arch_list_add_reg (regcache, |
4206 | tdep->ppc_vr0_regnum + PPC_VRT (insn)); | |
4207 | return 0; | |
4208 | ||
6ec2b213 EBM |
4209 | case 1549: /* Vector Extract Unsigned Byte Left-Indexed */ |
4210 | case 1613: /* Vector Extract Unsigned Halfword Left-Indexed */ | |
4211 | case 1677: /* Vector Extract Unsigned Word Left-Indexed */ | |
4212 | case 1805: /* Vector Extract Unsigned Byte Right-Indexed */ | |
4213 | case 1869: /* Vector Extract Unsigned Halfword Right-Indexed */ | |
4214 | case 1933: /* Vector Extract Unsigned Word Right-Indexed */ | |
4215 | record_full_arch_list_add_reg (regcache, | |
4216 | tdep->ppc_gp0_regnum + PPC_RT (insn)); | |
4217 | return 0; | |
4218 | ||
b4cdae6f WW |
4219 | case 1604: /* Move To Vector Status and Control Register */ |
4220 | record_full_arch_list_add_reg (regcache, PPC_VSCR_REGNUM); | |
4221 | return 0; | |
4222 | case 1540: /* Move From Vector Status and Control Register */ | |
4223 | record_full_arch_list_add_reg (regcache, | |
4224 | tdep->ppc_vr0_regnum + PPC_VRT (insn)); | |
4225 | return 0; | |
6ec2b213 EBM |
4226 | case 833: /* Decimal Copy Sign */ |
4227 | record_full_arch_list_add_reg (regcache, | |
4228 | tdep->ppc_vr0_regnum + PPC_VRT (insn)); | |
4229 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
4230 | return 0; | |
b4cdae6f WW |
4231 | } |
4232 | ||
810c1026 WW |
4233 | fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x " |
4234 | "at %s, 4-%d.\n", insn, paddress (gdbarch, addr), ext); | |
b4cdae6f WW |
4235 | return -1; |
4236 | } | |
4237 | ||
ddeca1df WW |
4238 | /* Parse and record instructions of primary opcode-19 at ADDR. |
4239 | Return 0 if successful. */ | |
b4cdae6f WW |
4240 | |
4241 | static int | |
4242 | ppc_process_record_op19 (struct gdbarch *gdbarch, struct regcache *regcache, | |
4243 | CORE_ADDR addr, uint32_t insn) | |
4244 | { | |
4245 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
4246 | int ext = PPC_EXTOP (insn); | |
4247 | ||
6ec2b213 EBM |
4248 | switch (ext & 0x01f) |
4249 | { | |
4250 | case 2: /* Add PC Immediate Shifted */ | |
4251 | record_full_arch_list_add_reg (regcache, | |
4252 | tdep->ppc_gp0_regnum + PPC_RT (insn)); | |
4253 | return 0; | |
4254 | } | |
4255 | ||
b4cdae6f WW |
4256 | switch (ext) |
4257 | { | |
4258 | case 0: /* Move Condition Register Field */ | |
4259 | case 33: /* Condition Register NOR */ | |
4260 | case 129: /* Condition Register AND with Complement */ | |
4261 | case 193: /* Condition Register XOR */ | |
4262 | case 225: /* Condition Register NAND */ | |
4263 | case 257: /* Condition Register AND */ | |
4264 | case 289: /* Condition Register Equivalent */ | |
4265 | case 417: /* Condition Register OR with Complement */ | |
4266 | case 449: /* Condition Register OR */ | |
4267 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
4268 | return 0; | |
4269 | ||
4270 | case 16: /* Branch Conditional */ | |
4271 | case 560: /* Branch Conditional to Branch Target Address Register */ | |
4272 | if ((PPC_BO (insn) & 0x4) == 0) | |
4273 | record_full_arch_list_add_reg (regcache, tdep->ppc_ctr_regnum); | |
4274 | /* FALL-THROUGH */ | |
4275 | case 528: /* Branch Conditional to Count Register */ | |
4276 | if (PPC_LK (insn)) | |
4277 | record_full_arch_list_add_reg (regcache, tdep->ppc_lr_regnum); | |
4278 | return 0; | |
4279 | ||
4280 | case 150: /* Instruction Synchronize */ | |
4281 | /* Do nothing. */ | |
4282 | return 0; | |
4283 | } | |
4284 | ||
810c1026 WW |
4285 | fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x " |
4286 | "at %s, 19-%d.\n", insn, paddress (gdbarch, addr), ext); | |
b4cdae6f WW |
4287 | return -1; |
4288 | } | |
4289 | ||
ddeca1df WW |
4290 | /* Parse and record instructions of primary opcode-31 at ADDR. |
4291 | Return 0 if successful. */ | |
b4cdae6f WW |
4292 | |
4293 | static int | |
4294 | ppc_process_record_op31 (struct gdbarch *gdbarch, struct regcache *regcache, | |
4295 | CORE_ADDR addr, uint32_t insn) | |
4296 | { | |
4297 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
4298 | int ext = PPC_EXTOP (insn); | |
4299 | int tmp, nr, nb, i; | |
4300 | CORE_ADDR at_dcsz, ea = 0; | |
4301 | ULONGEST rb, ra, xer; | |
4302 | int size = 0; | |
4303 | ||
4304 | /* These instructions have OE bit. */ | |
4305 | switch (ext & 0x1ff) | |
4306 | { | |
4307 | /* These write RT and XER. Update CR if RC is set. */ | |
4308 | case 8: /* Subtract from carrying */ | |
4309 | case 10: /* Add carrying */ | |
4310 | case 136: /* Subtract from extended */ | |
4311 | case 138: /* Add extended */ | |
4312 | case 200: /* Subtract from zero extended */ | |
4313 | case 202: /* Add to zero extended */ | |
4314 | case 232: /* Subtract from minus one extended */ | |
4315 | case 234: /* Add to minus one extended */ | |
4316 | /* CA is always altered, but SO/OV are only altered when OE=1. | |
4317 | In any case, XER is always altered. */ | |
4318 | record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum); | |
4319 | if (PPC_RC (insn)) | |
4320 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
4321 | record_full_arch_list_add_reg (regcache, | |
4322 | tdep->ppc_gp0_regnum + PPC_RT (insn)); | |
4323 | return 0; | |
4324 | ||
4325 | /* These write RT. Update CR if RC is set and update XER if OE is set. */ | |
4326 | case 40: /* Subtract from */ | |
4327 | case 104: /* Negate */ | |
4328 | case 233: /* Multiply low doubleword */ | |
4329 | case 235: /* Multiply low word */ | |
4330 | case 266: /* Add */ | |
4331 | case 393: /* Divide Doubleword Extended Unsigned */ | |
4332 | case 395: /* Divide Word Extended Unsigned */ | |
4333 | case 425: /* Divide Doubleword Extended */ | |
4334 | case 427: /* Divide Word Extended */ | |
4335 | case 457: /* Divide Doubleword Unsigned */ | |
4336 | case 459: /* Divide Word Unsigned */ | |
4337 | case 489: /* Divide Doubleword */ | |
4338 | case 491: /* Divide Word */ | |
4339 | if (PPC_OE (insn)) | |
4340 | record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum); | |
4341 | /* FALL-THROUGH */ | |
4342 | case 9: /* Multiply High Doubleword Unsigned */ | |
4343 | case 11: /* Multiply High Word Unsigned */ | |
4344 | case 73: /* Multiply High Doubleword */ | |
4345 | case 75: /* Multiply High Word */ | |
4346 | if (PPC_RC (insn)) | |
4347 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
4348 | record_full_arch_list_add_reg (regcache, | |
4349 | tdep->ppc_gp0_regnum + PPC_RT (insn)); | |
4350 | return 0; | |
4351 | } | |
4352 | ||
4353 | if ((ext & 0x1f) == 15) | |
4354 | { | |
4355 | /* Integer Select. bit[16:20] is used for BC. */ | |
4356 | record_full_arch_list_add_reg (regcache, | |
4357 | tdep->ppc_gp0_regnum + PPC_RT (insn)); | |
4358 | return 0; | |
4359 | } | |
4360 | ||
6ec2b213 EBM |
4361 | if ((ext & 0xff) == 170) |
4362 | { | |
4363 | /* Add Extended using alternate carry bits */ | |
4364 | record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum); | |
4365 | record_full_arch_list_add_reg (regcache, | |
4366 | tdep->ppc_gp0_regnum + PPC_RT (insn)); | |
4367 | return 0; | |
4368 | } | |
4369 | ||
b4cdae6f WW |
4370 | switch (ext) |
4371 | { | |
4372 | case 78: /* Determine Leftmost Zero Byte */ | |
4373 | if (PPC_RC (insn)) | |
4374 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
4375 | record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum); | |
4376 | record_full_arch_list_add_reg (regcache, | |
4377 | tdep->ppc_gp0_regnum + PPC_RT (insn)); | |
4378 | return 0; | |
4379 | ||
4380 | /* These only write RT. */ | |
4381 | case 19: /* Move from condition register */ | |
4382 | /* Move From One Condition Register Field */ | |
4383 | case 74: /* Add and Generate Sixes */ | |
4384 | case 74 | 0x200: /* Add and Generate Sixes (bit-21 dont-care) */ | |
4385 | case 302: /* Move From Branch History Rolling Buffer */ | |
4386 | case 339: /* Move From Special Purpose Register */ | |
4387 | case 371: /* Move From Time Base [Phased-Out] */ | |
6ec2b213 EBM |
4388 | case 309: /* Load Doubleword Monitored Indexed */ |
4389 | case 128: /* Set Boolean */ | |
4390 | case 755: /* Deliver A Random Number */ | |
b4cdae6f WW |
4391 | record_full_arch_list_add_reg (regcache, |
4392 | tdep->ppc_gp0_regnum + PPC_RT (insn)); | |
4393 | return 0; | |
4394 | ||
4395 | /* These only write to RA. */ | |
4396 | case 51: /* Move From VSR Doubleword */ | |
4397 | case 115: /* Move From VSR Word and Zero */ | |
4398 | case 122: /* Population count bytes */ | |
4399 | case 378: /* Population count words */ | |
4400 | case 506: /* Population count doublewords */ | |
4401 | case 154: /* Parity Word */ | |
4402 | case 186: /* Parity Doubleword */ | |
4403 | case 252: /* Bit Permute Doubleword */ | |
4404 | case 282: /* Convert Declets To Binary Coded Decimal */ | |
4405 | case 314: /* Convert Binary Coded Decimal To Declets */ | |
4406 | case 508: /* Compare bytes */ | |
6ec2b213 | 4407 | case 307: /* Move From VSR Lower Doubleword */ |
b4cdae6f WW |
4408 | record_full_arch_list_add_reg (regcache, |
4409 | tdep->ppc_gp0_regnum + PPC_RA (insn)); | |
4410 | return 0; | |
4411 | ||
4412 | /* These write CR and optional RA. */ | |
4413 | case 792: /* Shift Right Algebraic Word */ | |
4414 | case 794: /* Shift Right Algebraic Doubleword */ | |
4415 | case 824: /* Shift Right Algebraic Word Immediate */ | |
4416 | case 826: /* Shift Right Algebraic Doubleword Immediate (413) */ | |
4417 | case 826 | 1: /* Shift Right Algebraic Doubleword Immediate (413) */ | |
4418 | record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum); | |
4419 | record_full_arch_list_add_reg (regcache, | |
4420 | tdep->ppc_gp0_regnum + PPC_RA (insn)); | |
4421 | /* FALL-THROUGH */ | |
4422 | case 0: /* Compare */ | |
4423 | case 32: /* Compare logical */ | |
4424 | case 144: /* Move To Condition Register Fields */ | |
4425 | /* Move To One Condition Register Field */ | |
6ec2b213 EBM |
4426 | case 192: /* Compare Ranged Byte */ |
4427 | case 224: /* Compare Equal Byte */ | |
4428 | case 576: /* Move XER to CR Extended */ | |
4429 | case 902: /* Paste (should always fail due to single-stepping and | |
4430 | the memory location might not be accessible, so | |
4431 | record only CR) */ | |
b4cdae6f WW |
4432 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); |
4433 | return 0; | |
4434 | ||
4435 | /* These write to RT. Update RA if 'update indexed.' */ | |
4436 | case 53: /* Load Doubleword with Update Indexed */ | |
4437 | case 119: /* Load Byte and Zero with Update Indexed */ | |
4438 | case 311: /* Load Halfword and Zero with Update Indexed */ | |
4439 | case 55: /* Load Word and Zero with Update Indexed */ | |
4440 | case 375: /* Load Halfword Algebraic with Update Indexed */ | |
4441 | case 373: /* Load Word Algebraic with Update Indexed */ | |
4442 | record_full_arch_list_add_reg (regcache, | |
4443 | tdep->ppc_gp0_regnum + PPC_RA (insn)); | |
4444 | /* FALL-THROUGH */ | |
4445 | case 21: /* Load Doubleword Indexed */ | |
4446 | case 52: /* Load Byte And Reserve Indexed */ | |
4447 | case 116: /* Load Halfword And Reserve Indexed */ | |
4448 | case 20: /* Load Word And Reserve Indexed */ | |
4449 | case 84: /* Load Doubleword And Reserve Indexed */ | |
4450 | case 87: /* Load Byte and Zero Indexed */ | |
4451 | case 279: /* Load Halfword and Zero Indexed */ | |
4452 | case 23: /* Load Word and Zero Indexed */ | |
4453 | case 343: /* Load Halfword Algebraic Indexed */ | |
4454 | case 341: /* Load Word Algebraic Indexed */ | |
4455 | case 790: /* Load Halfword Byte-Reverse Indexed */ | |
4456 | case 534: /* Load Word Byte-Reverse Indexed */ | |
4457 | case 532: /* Load Doubleword Byte-Reverse Indexed */ | |
6ec2b213 EBM |
4458 | case 582: /* Load Word Atomic */ |
4459 | case 614: /* Load Doubleword Atomic */ | |
4460 | case 265: /* Modulo Unsigned Doubleword */ | |
4461 | case 777: /* Modulo Signed Doubleword */ | |
4462 | case 267: /* Modulo Unsigned Word */ | |
4463 | case 779: /* Modulo Signed Word */ | |
b4cdae6f WW |
4464 | record_full_arch_list_add_reg (regcache, |
4465 | tdep->ppc_gp0_regnum + PPC_RT (insn)); | |
4466 | return 0; | |
4467 | ||
4468 | case 597: /* Load String Word Immediate */ | |
4469 | case 533: /* Load String Word Indexed */ | |
4470 | if (ext == 597) | |
4471 | { | |
4472 | nr = PPC_NB (insn); | |
4473 | if (nr == 0) | |
4474 | nr = 32; | |
4475 | } | |
4476 | else | |
4477 | { | |
4478 | regcache_raw_read_unsigned (regcache, tdep->ppc_xer_regnum, &xer); | |
4479 | nr = PPC_XER_NB (xer); | |
4480 | } | |
4481 | ||
4482 | nr = (nr + 3) >> 2; | |
4483 | ||
4484 | /* If n=0, the contents of register RT are undefined. */ | |
4485 | if (nr == 0) | |
4486 | nr = 1; | |
4487 | ||
4488 | for (i = 0; i < nr; i++) | |
4489 | record_full_arch_list_add_reg (regcache, | |
4490 | tdep->ppc_gp0_regnum | |
4491 | + ((PPC_RT (insn) + i) & 0x1f)); | |
4492 | return 0; | |
4493 | ||
4494 | case 276: /* Load Quadword And Reserve Indexed */ | |
4495 | tmp = tdep->ppc_gp0_regnum + (PPC_RT (insn) & ~1); | |
4496 | record_full_arch_list_add_reg (regcache, tmp); | |
4497 | record_full_arch_list_add_reg (regcache, tmp + 1); | |
4498 | return 0; | |
4499 | ||
4500 | /* These write VRT. */ | |
4501 | case 6: /* Load Vector for Shift Left Indexed */ | |
4502 | case 38: /* Load Vector for Shift Right Indexed */ | |
4503 | case 7: /* Load Vector Element Byte Indexed */ | |
4504 | case 39: /* Load Vector Element Halfword Indexed */ | |
4505 | case 71: /* Load Vector Element Word Indexed */ | |
4506 | case 103: /* Load Vector Indexed */ | |
4507 | case 359: /* Load Vector Indexed LRU */ | |
4508 | record_full_arch_list_add_reg (regcache, | |
4509 | tdep->ppc_vr0_regnum + PPC_VRT (insn)); | |
4510 | return 0; | |
4511 | ||
4512 | /* These write FRT. Update RA if 'update indexed.' */ | |
4513 | case 567: /* Load Floating-Point Single with Update Indexed */ | |
4514 | case 631: /* Load Floating-Point Double with Update Indexed */ | |
4515 | record_full_arch_list_add_reg (regcache, | |
4516 | tdep->ppc_gp0_regnum + PPC_RA (insn)); | |
4517 | /* FALL-THROUGH */ | |
4518 | case 535: /* Load Floating-Point Single Indexed */ | |
4519 | case 599: /* Load Floating-Point Double Indexed */ | |
4520 | case 855: /* Load Floating-Point as Integer Word Algebraic Indexed */ | |
4521 | case 887: /* Load Floating-Point as Integer Word and Zero Indexed */ | |
4522 | record_full_arch_list_add_reg (regcache, | |
4523 | tdep->ppc_fp0_regnum + PPC_FRT (insn)); | |
4524 | return 0; | |
4525 | ||
4526 | case 791: /* Load Floating-Point Double Pair Indexed */ | |
4527 | tmp = tdep->ppc_fp0_regnum + (PPC_FRT (insn) & ~1); | |
4528 | record_full_arch_list_add_reg (regcache, tmp); | |
4529 | record_full_arch_list_add_reg (regcache, tmp + 1); | |
4530 | return 0; | |
4531 | ||
4532 | case 179: /* Move To VSR Doubleword */ | |
4533 | case 211: /* Move To VSR Word Algebraic */ | |
4534 | case 243: /* Move To VSR Word and Zero */ | |
4535 | case 588: /* Load VSX Scalar Doubleword Indexed */ | |
4536 | case 524: /* Load VSX Scalar Single-Precision Indexed */ | |
4537 | case 76: /* Load VSX Scalar as Integer Word Algebraic Indexed */ | |
4538 | case 12: /* Load VSX Scalar as Integer Word and Zero Indexed */ | |
4539 | case 844: /* Load VSX Vector Doubleword*2 Indexed */ | |
4540 | case 332: /* Load VSX Vector Doubleword & Splat Indexed */ | |
4541 | case 780: /* Load VSX Vector Word*4 Indexed */ | |
6ec2b213 EBM |
4542 | case 268: /* Load VSX Vector Indexed */ |
4543 | case 364: /* Load VSX Vector Word & Splat Indexed */ | |
4544 | case 812: /* Load VSX Vector Halfword*8 Indexed */ | |
4545 | case 876: /* Load VSX Vector Byte*16 Indexed */ | |
4546 | case 269: /* Load VSX Vector with Length */ | |
4547 | case 301: /* Load VSX Vector Left-justified with Length */ | |
4548 | case 781: /* Load VSX Scalar as Integer Byte & Zero Indexed */ | |
4549 | case 813: /* Load VSX Scalar as Integer Halfword & Zero Indexed */ | |
4550 | case 403: /* Move To VSR Word & Splat */ | |
4551 | case 435: /* Move To VSR Double Doubleword */ | |
b4cdae6f WW |
4552 | ppc_record_vsr (regcache, tdep, PPC_XT (insn)); |
4553 | return 0; | |
4554 | ||
4555 | /* These write RA. Update CR if RC is set. */ | |
4556 | case 24: /* Shift Left Word */ | |
4557 | case 26: /* Count Leading Zeros Word */ | |
4558 | case 27: /* Shift Left Doubleword */ | |
4559 | case 28: /* AND */ | |
4560 | case 58: /* Count Leading Zeros Doubleword */ | |
4561 | case 60: /* AND with Complement */ | |
4562 | case 124: /* NOR */ | |
4563 | case 284: /* Equivalent */ | |
4564 | case 316: /* XOR */ | |
4565 | case 476: /* NAND */ | |
4566 | case 412: /* OR with Complement */ | |
4567 | case 444: /* OR */ | |
4568 | case 536: /* Shift Right Word */ | |
4569 | case 539: /* Shift Right Doubleword */ | |
4570 | case 922: /* Extend Sign Halfword */ | |
4571 | case 954: /* Extend Sign Byte */ | |
4572 | case 986: /* Extend Sign Word */ | |
6ec2b213 EBM |
4573 | case 538: /* Count Trailing Zeros Word */ |
4574 | case 570: /* Count Trailing Zeros Doubleword */ | |
4575 | case 890: /* Extend-Sign Word and Shift Left Immediate (445) */ | |
4576 | case 890 | 1: /* Extend-Sign Word and Shift Left Immediate (445) */ | |
b4cdae6f WW |
4577 | if (PPC_RC (insn)) |
4578 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
4579 | record_full_arch_list_add_reg (regcache, | |
4580 | tdep->ppc_gp0_regnum + PPC_RA (insn)); | |
4581 | return 0; | |
4582 | ||
4583 | /* Store memory. */ | |
4584 | case 181: /* Store Doubleword with Update Indexed */ | |
4585 | case 183: /* Store Word with Update Indexed */ | |
4586 | case 247: /* Store Byte with Update Indexed */ | |
4587 | case 439: /* Store Half Word with Update Indexed */ | |
4588 | case 695: /* Store Floating-Point Single with Update Indexed */ | |
4589 | case 759: /* Store Floating-Point Double with Update Indexed */ | |
4590 | record_full_arch_list_add_reg (regcache, | |
4591 | tdep->ppc_gp0_regnum + PPC_RA (insn)); | |
4592 | /* FALL-THROUGH */ | |
4593 | case 135: /* Store Vector Element Byte Indexed */ | |
4594 | case 167: /* Store Vector Element Halfword Indexed */ | |
4595 | case 199: /* Store Vector Element Word Indexed */ | |
4596 | case 231: /* Store Vector Indexed */ | |
4597 | case 487: /* Store Vector Indexed LRU */ | |
4598 | case 716: /* Store VSX Scalar Doubleword Indexed */ | |
4599 | case 140: /* Store VSX Scalar as Integer Word Indexed */ | |
4600 | case 652: /* Store VSX Scalar Single-Precision Indexed */ | |
4601 | case 972: /* Store VSX Vector Doubleword*2 Indexed */ | |
4602 | case 908: /* Store VSX Vector Word*4 Indexed */ | |
4603 | case 149: /* Store Doubleword Indexed */ | |
4604 | case 151: /* Store Word Indexed */ | |
4605 | case 215: /* Store Byte Indexed */ | |
4606 | case 407: /* Store Half Word Indexed */ | |
4607 | case 694: /* Store Byte Conditional Indexed */ | |
4608 | case 726: /* Store Halfword Conditional Indexed */ | |
4609 | case 150: /* Store Word Conditional Indexed */ | |
4610 | case 214: /* Store Doubleword Conditional Indexed */ | |
4611 | case 182: /* Store Quadword Conditional Indexed */ | |
4612 | case 662: /* Store Word Byte-Reverse Indexed */ | |
4613 | case 918: /* Store Halfword Byte-Reverse Indexed */ | |
4614 | case 660: /* Store Doubleword Byte-Reverse Indexed */ | |
4615 | case 663: /* Store Floating-Point Single Indexed */ | |
4616 | case 727: /* Store Floating-Point Double Indexed */ | |
4617 | case 919: /* Store Floating-Point Double Pair Indexed */ | |
4618 | case 983: /* Store Floating-Point as Integer Word Indexed */ | |
6ec2b213 EBM |
4619 | case 396: /* Store VSX Vector Indexed */ |
4620 | case 940: /* Store VSX Vector Halfword*8 Indexed */ | |
4621 | case 1004: /* Store VSX Vector Byte*16 Indexed */ | |
4622 | case 909: /* Store VSX Scalar as Integer Byte Indexed */ | |
4623 | case 941: /* Store VSX Scalar as Integer Halfword Indexed */ | |
b4cdae6f WW |
4624 | if (ext == 694 || ext == 726 || ext == 150 || ext == 214 || ext == 182) |
4625 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
4626 | ||
4627 | ra = 0; | |
4628 | if (PPC_RA (insn) != 0) | |
4629 | regcache_raw_read_unsigned (regcache, | |
4630 | tdep->ppc_gp0_regnum + PPC_RA (insn), &ra); | |
4631 | regcache_raw_read_unsigned (regcache, | |
4632 | tdep->ppc_gp0_regnum + PPC_RB (insn), &rb); | |
4633 | ea = ra + rb; | |
4634 | ||
4635 | switch (ext) | |
4636 | { | |
4637 | case 183: /* Store Word with Update Indexed */ | |
4638 | case 199: /* Store Vector Element Word Indexed */ | |
4639 | case 140: /* Store VSX Scalar as Integer Word Indexed */ | |
4640 | case 652: /* Store VSX Scalar Single-Precision Indexed */ | |
4641 | case 151: /* Store Word Indexed */ | |
4642 | case 150: /* Store Word Conditional Indexed */ | |
4643 | case 662: /* Store Word Byte-Reverse Indexed */ | |
4644 | case 663: /* Store Floating-Point Single Indexed */ | |
4645 | case 695: /* Store Floating-Point Single with Update Indexed */ | |
4646 | case 983: /* Store Floating-Point as Integer Word Indexed */ | |
4647 | size = 4; | |
4648 | break; | |
4649 | case 247: /* Store Byte with Update Indexed */ | |
4650 | case 135: /* Store Vector Element Byte Indexed */ | |
4651 | case 215: /* Store Byte Indexed */ | |
4652 | case 694: /* Store Byte Conditional Indexed */ | |
6ec2b213 | 4653 | case 909: /* Store VSX Scalar as Integer Byte Indexed */ |
b4cdae6f WW |
4654 | size = 1; |
4655 | break; | |
4656 | case 439: /* Store Halfword with Update Indexed */ | |
4657 | case 167: /* Store Vector Element Halfword Indexed */ | |
4658 | case 407: /* Store Halfword Indexed */ | |
4659 | case 726: /* Store Halfword Conditional Indexed */ | |
4660 | case 918: /* Store Halfword Byte-Reverse Indexed */ | |
6ec2b213 | 4661 | case 941: /* Store VSX Scalar as Integer Halfword Indexed */ |
b4cdae6f WW |
4662 | size = 2; |
4663 | break; | |
4664 | case 181: /* Store Doubleword with Update Indexed */ | |
4665 | case 716: /* Store VSX Scalar Doubleword Indexed */ | |
4666 | case 149: /* Store Doubleword Indexed */ | |
4667 | case 214: /* Store Doubleword Conditional Indexed */ | |
4668 | case 660: /* Store Doubleword Byte-Reverse Indexed */ | |
4669 | case 727: /* Store Floating-Point Double Indexed */ | |
4670 | case 759: /* Store Floating-Point Double with Update Indexed */ | |
4671 | size = 8; | |
4672 | break; | |
4673 | case 972: /* Store VSX Vector Doubleword*2 Indexed */ | |
4674 | case 908: /* Store VSX Vector Word*4 Indexed */ | |
4675 | case 182: /* Store Quadword Conditional Indexed */ | |
4676 | case 231: /* Store Vector Indexed */ | |
4677 | case 487: /* Store Vector Indexed LRU */ | |
4678 | case 919: /* Store Floating-Point Double Pair Indexed */ | |
6ec2b213 EBM |
4679 | case 396: /* Store VSX Vector Indexed */ |
4680 | case 940: /* Store VSX Vector Halfword*8 Indexed */ | |
4681 | case 1004: /* Store VSX Vector Byte*16 Indexed */ | |
b4cdae6f WW |
4682 | size = 16; |
4683 | break; | |
4684 | default: | |
4685 | gdb_assert (0); | |
4686 | } | |
4687 | ||
4688 | /* Align address for Store Vector instructions. */ | |
4689 | switch (ext) | |
4690 | { | |
4691 | case 167: /* Store Vector Element Halfword Indexed */ | |
4692 | addr = addr & ~0x1ULL; | |
4693 | break; | |
4694 | ||
4695 | case 199: /* Store Vector Element Word Indexed */ | |
4696 | addr = addr & ~0x3ULL; | |
4697 | break; | |
4698 | ||
4699 | case 231: /* Store Vector Indexed */ | |
4700 | case 487: /* Store Vector Indexed LRU */ | |
4701 | addr = addr & ~0xfULL; | |
4702 | break; | |
4703 | } | |
4704 | ||
4705 | record_full_arch_list_add_mem (addr, size); | |
4706 | return 0; | |
4707 | ||
6ec2b213 EBM |
4708 | case 397: /* Store VSX Vector with Length */ |
4709 | case 429: /* Store VSX Vector Left-justified with Length */ | |
de678454 | 4710 | ra = 0; |
6ec2b213 EBM |
4711 | if (PPC_RA (insn) != 0) |
4712 | regcache_raw_read_unsigned (regcache, | |
de678454 EBM |
4713 | tdep->ppc_gp0_regnum + PPC_RA (insn), &ra); |
4714 | ea = ra; | |
6ec2b213 EBM |
4715 | regcache_raw_read_unsigned (regcache, |
4716 | tdep->ppc_gp0_regnum + PPC_RB (insn), &rb); | |
4717 | /* Store up to 16 bytes. */ | |
4718 | nb = (rb & 0xff) > 16 ? 16 : (rb & 0xff); | |
4719 | if (nb > 0) | |
4720 | record_full_arch_list_add_mem (ea, nb); | |
4721 | return 0; | |
4722 | ||
4723 | case 710: /* Store Word Atomic */ | |
4724 | case 742: /* Store Doubleword Atomic */ | |
de678454 | 4725 | ra = 0; |
6ec2b213 EBM |
4726 | if (PPC_RA (insn) != 0) |
4727 | regcache_raw_read_unsigned (regcache, | |
de678454 EBM |
4728 | tdep->ppc_gp0_regnum + PPC_RA (insn), &ra); |
4729 | ea = ra; | |
6ec2b213 EBM |
4730 | switch (ext) |
4731 | { | |
4732 | case 710: /* Store Word Atomic */ | |
4733 | size = 8; | |
4734 | break; | |
4735 | case 742: /* Store Doubleword Atomic */ | |
4736 | size = 16; | |
4737 | break; | |
4738 | default: | |
4739 | gdb_assert (0); | |
4740 | } | |
4741 | record_full_arch_list_add_mem (ea, size); | |
4742 | return 0; | |
4743 | ||
b4cdae6f WW |
4744 | case 725: /* Store String Word Immediate */ |
4745 | ra = 0; | |
4746 | if (PPC_RA (insn) != 0) | |
9f7efd5b EBM |
4747 | regcache_raw_read_unsigned (regcache, |
4748 | tdep->ppc_gp0_regnum + PPC_RA (insn), &ra); | |
b4cdae6f WW |
4749 | ea += ra; |
4750 | ||
4751 | nb = PPC_NB (insn); | |
4752 | if (nb == 0) | |
4753 | nb = 32; | |
4754 | ||
4755 | record_full_arch_list_add_mem (ea, nb); | |
4756 | ||
4757 | return 0; | |
4758 | ||
4759 | case 661: /* Store String Word Indexed */ | |
4760 | ra = 0; | |
4761 | if (PPC_RA (insn) != 0) | |
9f7efd5b EBM |
4762 | regcache_raw_read_unsigned (regcache, |
4763 | tdep->ppc_gp0_regnum + PPC_RA (insn), &ra); | |
b4cdae6f WW |
4764 | ea += ra; |
4765 | ||
4766 | regcache_raw_read_unsigned (regcache, tdep->ppc_xer_regnum, &xer); | |
4767 | nb = PPC_XER_NB (xer); | |
4768 | ||
4769 | if (nb != 0) | |
4770 | { | |
9f7efd5b EBM |
4771 | regcache_raw_read_unsigned (regcache, |
4772 | tdep->ppc_gp0_regnum + PPC_RB (insn), | |
4773 | &rb); | |
b4cdae6f WW |
4774 | ea += rb; |
4775 | record_full_arch_list_add_mem (ea, nb); | |
4776 | } | |
4777 | ||
4778 | return 0; | |
4779 | ||
4780 | case 467: /* Move To Special Purpose Register */ | |
4781 | switch (PPC_SPR (insn)) | |
4782 | { | |
4783 | case 1: /* XER */ | |
4784 | record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum); | |
4785 | return 0; | |
4786 | case 8: /* LR */ | |
4787 | record_full_arch_list_add_reg (regcache, tdep->ppc_lr_regnum); | |
4788 | return 0; | |
4789 | case 9: /* CTR */ | |
4790 | record_full_arch_list_add_reg (regcache, tdep->ppc_ctr_regnum); | |
4791 | return 0; | |
4792 | case 256: /* VRSAVE */ | |
4793 | record_full_arch_list_add_reg (regcache, tdep->ppc_vrsave_regnum); | |
4794 | return 0; | |
4795 | } | |
4796 | ||
4797 | goto UNKNOWN_OP; | |
4798 | ||
4799 | case 147: /* Move To Split Little Endian */ | |
4800 | record_full_arch_list_add_reg (regcache, tdep->ppc_ps_regnum); | |
4801 | return 0; | |
4802 | ||
4803 | case 512: /* Move to Condition Register from XER */ | |
4804 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
4805 | record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum); | |
4806 | return 0; | |
4807 | ||
4808 | case 4: /* Trap Word */ | |
4809 | case 68: /* Trap Doubleword */ | |
4810 | case 430: /* Clear BHRB */ | |
4811 | case 598: /* Synchronize */ | |
4812 | case 62: /* Wait for Interrupt */ | |
6ec2b213 | 4813 | case 30: /* Wait */ |
b4cdae6f WW |
4814 | case 22: /* Instruction Cache Block Touch */ |
4815 | case 854: /* Enforce In-order Execution of I/O */ | |
4816 | case 246: /* Data Cache Block Touch for Store */ | |
4817 | case 54: /* Data Cache Block Store */ | |
4818 | case 86: /* Data Cache Block Flush */ | |
4819 | case 278: /* Data Cache Block Touch */ | |
4820 | case 758: /* Data Cache Block Allocate */ | |
4821 | case 982: /* Instruction Cache Block Invalidate */ | |
6ec2b213 EBM |
4822 | case 774: /* Copy */ |
4823 | case 838: /* CP_Abort */ | |
b4cdae6f WW |
4824 | return 0; |
4825 | ||
4826 | case 654: /* Transaction Begin */ | |
4827 | case 686: /* Transaction End */ | |
b4cdae6f WW |
4828 | case 750: /* Transaction Suspend or Resume */ |
4829 | case 782: /* Transaction Abort Word Conditional */ | |
4830 | case 814: /* Transaction Abort Doubleword Conditional */ | |
4831 | case 846: /* Transaction Abort Word Conditional Immediate */ | |
4832 | case 878: /* Transaction Abort Doubleword Conditional Immediate */ | |
4833 | case 910: /* Transaction Abort */ | |
d44c67f3 EBM |
4834 | record_full_arch_list_add_reg (regcache, tdep->ppc_ps_regnum); |
4835 | /* FALL-THROUGH */ | |
4836 | case 718: /* Transaction Check */ | |
4837 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
4838 | return 0; | |
b4cdae6f WW |
4839 | |
4840 | case 1014: /* Data Cache Block set to Zero */ | |
4841 | if (target_auxv_search (¤t_target, AT_DCACHEBSIZE, &at_dcsz) <= 0 | |
4842 | || at_dcsz == 0) | |
4843 | at_dcsz = 128; /* Assume 128-byte cache line size (POWER8) */ | |
4844 | ||
bec734b2 | 4845 | ra = 0; |
b4cdae6f WW |
4846 | if (PPC_RA (insn) != 0) |
4847 | regcache_raw_read_unsigned (regcache, | |
4848 | tdep->ppc_gp0_regnum + PPC_RA (insn), &ra); | |
4849 | regcache_raw_read_unsigned (regcache, | |
4850 | tdep->ppc_gp0_regnum + PPC_RB (insn), &rb); | |
4851 | ea = (ra + rb) & ~((ULONGEST) (at_dcsz - 1)); | |
4852 | record_full_arch_list_add_mem (ea, at_dcsz); | |
4853 | return 0; | |
4854 | } | |
4855 | ||
4856 | UNKNOWN_OP: | |
810c1026 WW |
4857 | fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x " |
4858 | "at %s, 31-%d.\n", insn, paddress (gdbarch, addr), ext); | |
b4cdae6f WW |
4859 | return -1; |
4860 | } | |
4861 | ||
ddeca1df WW |
4862 | /* Parse and record instructions of primary opcode-59 at ADDR. |
4863 | Return 0 if successful. */ | |
b4cdae6f WW |
4864 | |
4865 | static int | |
4866 | ppc_process_record_op59 (struct gdbarch *gdbarch, struct regcache *regcache, | |
4867 | CORE_ADDR addr, uint32_t insn) | |
4868 | { | |
4869 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
4870 | int ext = PPC_EXTOP (insn); | |
4871 | ||
4872 | switch (ext & 0x1f) | |
4873 | { | |
4874 | case 18: /* Floating Divide */ | |
4875 | case 20: /* Floating Subtract */ | |
4876 | case 21: /* Floating Add */ | |
4877 | case 22: /* Floating Square Root */ | |
4878 | case 24: /* Floating Reciprocal Estimate */ | |
4879 | case 25: /* Floating Multiply */ | |
4880 | case 26: /* Floating Reciprocal Square Root Estimate */ | |
4881 | case 28: /* Floating Multiply-Subtract */ | |
4882 | case 29: /* Floating Multiply-Add */ | |
4883 | case 30: /* Floating Negative Multiply-Subtract */ | |
4884 | case 31: /* Floating Negative Multiply-Add */ | |
4885 | record_full_arch_list_add_reg (regcache, | |
4886 | tdep->ppc_fp0_regnum + PPC_FRT (insn)); | |
4887 | if (PPC_RC (insn)) | |
4888 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
4889 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
4890 | ||
4891 | return 0; | |
4892 | } | |
4893 | ||
4894 | switch (ext) | |
4895 | { | |
4896 | case 2: /* DFP Add */ | |
4897 | case 3: /* DFP Quantize */ | |
4898 | case 34: /* DFP Multiply */ | |
4899 | case 35: /* DFP Reround */ | |
4900 | case 67: /* DFP Quantize Immediate */ | |
4901 | case 99: /* DFP Round To FP Integer With Inexact */ | |
4902 | case 227: /* DFP Round To FP Integer Without Inexact */ | |
4903 | case 258: /* DFP Convert To DFP Long! */ | |
4904 | case 290: /* DFP Convert To Fixed */ | |
4905 | case 514: /* DFP Subtract */ | |
4906 | case 546: /* DFP Divide */ | |
4907 | case 770: /* DFP Round To DFP Short! */ | |
4908 | case 802: /* DFP Convert From Fixed */ | |
4909 | case 834: /* DFP Encode BCD To DPD */ | |
4910 | if (PPC_RC (insn)) | |
4911 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
4912 | record_full_arch_list_add_reg (regcache, | |
4913 | tdep->ppc_fp0_regnum + PPC_FRT (insn)); | |
4914 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
4915 | return 0; | |
4916 | ||
4917 | case 130: /* DFP Compare Ordered */ | |
4918 | case 162: /* DFP Test Exponent */ | |
4919 | case 194: /* DFP Test Data Class */ | |
4920 | case 226: /* DFP Test Data Group */ | |
4921 | case 642: /* DFP Compare Unordered */ | |
4922 | case 674: /* DFP Test Significance */ | |
6ec2b213 | 4923 | case 675: /* DFP Test Significance Immediate */ |
b4cdae6f WW |
4924 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); |
4925 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
4926 | return 0; | |
4927 | ||
4928 | case 66: /* DFP Shift Significand Left Immediate */ | |
4929 | case 98: /* DFP Shift Significand Right Immediate */ | |
4930 | case 322: /* DFP Decode DPD To BCD */ | |
4931 | case 354: /* DFP Extract Biased Exponent */ | |
4932 | case 866: /* DFP Insert Biased Exponent */ | |
4933 | record_full_arch_list_add_reg (regcache, | |
4934 | tdep->ppc_fp0_regnum + PPC_FRT (insn)); | |
4935 | if (PPC_RC (insn)) | |
4936 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
4937 | return 0; | |
4938 | ||
4939 | case 846: /* Floating Convert From Integer Doubleword Single */ | |
4940 | case 974: /* Floating Convert From Integer Doubleword Unsigned | |
4941 | Single */ | |
4942 | record_full_arch_list_add_reg (regcache, | |
4943 | tdep->ppc_fp0_regnum + PPC_FRT (insn)); | |
4944 | if (PPC_RC (insn)) | |
4945 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
4946 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
4947 | ||
4948 | return 0; | |
4949 | } | |
4950 | ||
810c1026 WW |
4951 | fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x " |
4952 | "at %s, 59-%d.\n", insn, paddress (gdbarch, addr), ext); | |
b4cdae6f WW |
4953 | return -1; |
4954 | } | |
4955 | ||
ddeca1df WW |
4956 | /* Parse and record instructions of primary opcode-60 at ADDR. |
4957 | Return 0 if successful. */ | |
b4cdae6f WW |
4958 | |
4959 | static int | |
4960 | ppc_process_record_op60 (struct gdbarch *gdbarch, struct regcache *regcache, | |
4961 | CORE_ADDR addr, uint32_t insn) | |
4962 | { | |
4963 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
4964 | int ext = PPC_EXTOP (insn); | |
b4cdae6f WW |
4965 | |
4966 | switch (ext >> 2) | |
4967 | { | |
4968 | case 0: /* VSX Scalar Add Single-Precision */ | |
4969 | case 32: /* VSX Scalar Add Double-Precision */ | |
4970 | case 24: /* VSX Scalar Divide Single-Precision */ | |
4971 | case 56: /* VSX Scalar Divide Double-Precision */ | |
4972 | case 176: /* VSX Scalar Copy Sign Double-Precision */ | |
4973 | case 33: /* VSX Scalar Multiply-Add Double-Precision */ | |
4974 | case 41: /* ditto */ | |
4975 | case 1: /* VSX Scalar Multiply-Add Single-Precision */ | |
4976 | case 9: /* ditto */ | |
4977 | case 160: /* VSX Scalar Maximum Double-Precision */ | |
4978 | case 168: /* VSX Scalar Minimum Double-Precision */ | |
4979 | case 49: /* VSX Scalar Multiply-Subtract Double-Precision */ | |
4980 | case 57: /* ditto */ | |
4981 | case 17: /* VSX Scalar Multiply-Subtract Single-Precision */ | |
4982 | case 25: /* ditto */ | |
4983 | case 48: /* VSX Scalar Multiply Double-Precision */ | |
4984 | case 16: /* VSX Scalar Multiply Single-Precision */ | |
4985 | case 161: /* VSX Scalar Negative Multiply-Add Double-Precision */ | |
4986 | case 169: /* ditto */ | |
4987 | case 129: /* VSX Scalar Negative Multiply-Add Single-Precision */ | |
4988 | case 137: /* ditto */ | |
4989 | case 177: /* VSX Scalar Negative Multiply-Subtract Double-Precision */ | |
4990 | case 185: /* ditto */ | |
4991 | case 145: /* VSX Scalar Negative Multiply-Subtract Single-Precision */ | |
4992 | case 153: /* ditto */ | |
4993 | case 40: /* VSX Scalar Subtract Double-Precision */ | |
4994 | case 8: /* VSX Scalar Subtract Single-Precision */ | |
4995 | case 96: /* VSX Vector Add Double-Precision */ | |
4996 | case 64: /* VSX Vector Add Single-Precision */ | |
4997 | case 120: /* VSX Vector Divide Double-Precision */ | |
4998 | case 88: /* VSX Vector Divide Single-Precision */ | |
4999 | case 97: /* VSX Vector Multiply-Add Double-Precision */ | |
5000 | case 105: /* ditto */ | |
5001 | case 65: /* VSX Vector Multiply-Add Single-Precision */ | |
5002 | case 73: /* ditto */ | |
5003 | case 224: /* VSX Vector Maximum Double-Precision */ | |
5004 | case 192: /* VSX Vector Maximum Single-Precision */ | |
5005 | case 232: /* VSX Vector Minimum Double-Precision */ | |
5006 | case 200: /* VSX Vector Minimum Single-Precision */ | |
5007 | case 113: /* VSX Vector Multiply-Subtract Double-Precision */ | |
5008 | case 121: /* ditto */ | |
5009 | case 81: /* VSX Vector Multiply-Subtract Single-Precision */ | |
5010 | case 89: /* ditto */ | |
5011 | case 112: /* VSX Vector Multiply Double-Precision */ | |
5012 | case 80: /* VSX Vector Multiply Single-Precision */ | |
5013 | case 225: /* VSX Vector Negative Multiply-Add Double-Precision */ | |
5014 | case 233: /* ditto */ | |
5015 | case 193: /* VSX Vector Negative Multiply-Add Single-Precision */ | |
5016 | case 201: /* ditto */ | |
5017 | case 241: /* VSX Vector Negative Multiply-Subtract Double-Precision */ | |
5018 | case 249: /* ditto */ | |
5019 | case 209: /* VSX Vector Negative Multiply-Subtract Single-Precision */ | |
5020 | case 217: /* ditto */ | |
5021 | case 104: /* VSX Vector Subtract Double-Precision */ | |
5022 | case 72: /* VSX Vector Subtract Single-Precision */ | |
6ec2b213 EBM |
5023 | case 128: /* VSX Scalar Maximum Type-C Double-Precision */ |
5024 | case 136: /* VSX Scalar Minimum Type-C Double-Precision */ | |
5025 | case 144: /* VSX Scalar Maximum Type-J Double-Precision */ | |
5026 | case 152: /* VSX Scalar Minimum Type-J Double-Precision */ | |
5027 | case 3: /* VSX Scalar Compare Equal Double-Precision */ | |
5028 | case 11: /* VSX Scalar Compare Greater Than Double-Precision */ | |
5029 | case 19: /* VSX Scalar Compare Greater Than or Equal | |
5030 | Double-Precision */ | |
b4cdae6f | 5031 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); |
6ec2b213 | 5032 | /* FALL-THROUGH */ |
b4cdae6f WW |
5033 | case 240: /* VSX Vector Copy Sign Double-Precision */ |
5034 | case 208: /* VSX Vector Copy Sign Single-Precision */ | |
5035 | case 130: /* VSX Logical AND */ | |
5036 | case 138: /* VSX Logical AND with Complement */ | |
5037 | case 186: /* VSX Logical Equivalence */ | |
5038 | case 178: /* VSX Logical NAND */ | |
5039 | case 170: /* VSX Logical OR with Complement */ | |
5040 | case 162: /* VSX Logical NOR */ | |
5041 | case 146: /* VSX Logical OR */ | |
5042 | case 154: /* VSX Logical XOR */ | |
5043 | case 18: /* VSX Merge High Word */ | |
5044 | case 50: /* VSX Merge Low Word */ | |
5045 | case 10: /* VSX Permute Doubleword Immediate (DM=0) */ | |
5046 | case 10 | 0x20: /* VSX Permute Doubleword Immediate (DM=1) */ | |
5047 | case 10 | 0x40: /* VSX Permute Doubleword Immediate (DM=2) */ | |
5048 | case 10 | 0x60: /* VSX Permute Doubleword Immediate (DM=3) */ | |
5049 | case 2: /* VSX Shift Left Double by Word Immediate (SHW=0) */ | |
5050 | case 2 | 0x20: /* VSX Shift Left Double by Word Immediate (SHW=1) */ | |
5051 | case 2 | 0x40: /* VSX Shift Left Double by Word Immediate (SHW=2) */ | |
5052 | case 2 | 0x60: /* VSX Shift Left Double by Word Immediate (SHW=3) */ | |
6ec2b213 EBM |
5053 | case 216: /* VSX Vector Insert Exponent Single-Precision */ |
5054 | case 248: /* VSX Vector Insert Exponent Double-Precision */ | |
5055 | case 26: /* VSX Vector Permute */ | |
5056 | case 58: /* VSX Vector Permute Right-indexed */ | |
5057 | case 213: /* VSX Vector Test Data Class Single-Precision (DC=0) */ | |
5058 | case 213 | 0x8: /* VSX Vector Test Data Class Single-Precision (DC=1) */ | |
5059 | case 245: /* VSX Vector Test Data Class Double-Precision (DC=0) */ | |
5060 | case 245 | 0x8: /* VSX Vector Test Data Class Double-Precision (DC=1) */ | |
b4cdae6f WW |
5061 | ppc_record_vsr (regcache, tdep, PPC_XT (insn)); |
5062 | return 0; | |
5063 | ||
5064 | case 61: /* VSX Scalar Test for software Divide Double-Precision */ | |
5065 | case 125: /* VSX Vector Test for software Divide Double-Precision */ | |
5066 | case 93: /* VSX Vector Test for software Divide Single-Precision */ | |
5067 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
5068 | return 0; | |
5069 | ||
5070 | case 35: /* VSX Scalar Compare Unordered Double-Precision */ | |
5071 | case 43: /* VSX Scalar Compare Ordered Double-Precision */ | |
6ec2b213 | 5072 | case 59: /* VSX Scalar Compare Exponents Double-Precision */ |
b4cdae6f WW |
5073 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); |
5074 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
5075 | return 0; | |
5076 | } | |
5077 | ||
5078 | switch ((ext >> 2) & 0x7f) /* Mask out Rc-bit. */ | |
5079 | { | |
5080 | case 99: /* VSX Vector Compare Equal To Double-Precision */ | |
5081 | case 67: /* VSX Vector Compare Equal To Single-Precision */ | |
5082 | case 115: /* VSX Vector Compare Greater Than or | |
5083 | Equal To Double-Precision */ | |
5084 | case 83: /* VSX Vector Compare Greater Than or | |
5085 | Equal To Single-Precision */ | |
5086 | case 107: /* VSX Vector Compare Greater Than Double-Precision */ | |
5087 | case 75: /* VSX Vector Compare Greater Than Single-Precision */ | |
5088 | if (PPC_Rc (insn)) | |
5089 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
5090 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
5091 | ppc_record_vsr (regcache, tdep, PPC_XT (insn)); | |
5092 | return 0; | |
5093 | } | |
5094 | ||
5095 | switch (ext >> 1) | |
5096 | { | |
5097 | case 265: /* VSX Scalar round Double-Precision to | |
5098 | Single-Precision and Convert to | |
5099 | Single-Precision format */ | |
5100 | case 344: /* VSX Scalar truncate Double-Precision to | |
5101 | Integer and Convert to Signed Integer | |
5102 | Doubleword format with Saturate */ | |
5103 | case 88: /* VSX Scalar truncate Double-Precision to | |
5104 | Integer and Convert to Signed Integer Word | |
5105 | Format with Saturate */ | |
5106 | case 328: /* VSX Scalar truncate Double-Precision integer | |
5107 | and Convert to Unsigned Integer Doubleword | |
5108 | Format with Saturate */ | |
5109 | case 72: /* VSX Scalar truncate Double-Precision to | |
5110 | Integer and Convert to Unsigned Integer Word | |
5111 | Format with Saturate */ | |
5112 | case 329: /* VSX Scalar Convert Single-Precision to | |
5113 | Double-Precision format */ | |
5114 | case 376: /* VSX Scalar Convert Signed Integer | |
5115 | Doubleword to floating-point format and | |
5116 | Round to Double-Precision format */ | |
5117 | case 312: /* VSX Scalar Convert Signed Integer | |
5118 | Doubleword to floating-point format and | |
5119 | round to Single-Precision */ | |
5120 | case 360: /* VSX Scalar Convert Unsigned Integer | |
5121 | Doubleword to floating-point format and | |
5122 | Round to Double-Precision format */ | |
5123 | case 296: /* VSX Scalar Convert Unsigned Integer | |
5124 | Doubleword to floating-point format and | |
5125 | Round to Single-Precision */ | |
5126 | case 73: /* VSX Scalar Round to Double-Precision Integer | |
5127 | Using Round to Nearest Away */ | |
5128 | case 107: /* VSX Scalar Round to Double-Precision Integer | |
5129 | Exact using Current rounding mode */ | |
5130 | case 121: /* VSX Scalar Round to Double-Precision Integer | |
5131 | Using Round toward -Infinity */ | |
5132 | case 105: /* VSX Scalar Round to Double-Precision Integer | |
5133 | Using Round toward +Infinity */ | |
5134 | case 89: /* VSX Scalar Round to Double-Precision Integer | |
5135 | Using Round toward Zero */ | |
5136 | case 90: /* VSX Scalar Reciprocal Estimate Double-Precision */ | |
5137 | case 26: /* VSX Scalar Reciprocal Estimate Single-Precision */ | |
5138 | case 281: /* VSX Scalar Round to Single-Precision */ | |
5139 | case 74: /* VSX Scalar Reciprocal Square Root Estimate | |
5140 | Double-Precision */ | |
5141 | case 10: /* VSX Scalar Reciprocal Square Root Estimate | |
5142 | Single-Precision */ | |
5143 | case 75: /* VSX Scalar Square Root Double-Precision */ | |
5144 | case 11: /* VSX Scalar Square Root Single-Precision */ | |
5145 | case 393: /* VSX Vector round Double-Precision to | |
5146 | Single-Precision and Convert to | |
5147 | Single-Precision format */ | |
5148 | case 472: /* VSX Vector truncate Double-Precision to | |
5149 | Integer and Convert to Signed Integer | |
5150 | Doubleword format with Saturate */ | |
5151 | case 216: /* VSX Vector truncate Double-Precision to | |
5152 | Integer and Convert to Signed Integer Word | |
5153 | Format with Saturate */ | |
5154 | case 456: /* VSX Vector truncate Double-Precision to | |
5155 | Integer and Convert to Unsigned Integer | |
5156 | Doubleword format with Saturate */ | |
5157 | case 200: /* VSX Vector truncate Double-Precision to | |
5158 | Integer and Convert to Unsigned Integer Word | |
5159 | Format with Saturate */ | |
5160 | case 457: /* VSX Vector Convert Single-Precision to | |
5161 | Double-Precision format */ | |
5162 | case 408: /* VSX Vector truncate Single-Precision to | |
5163 | Integer and Convert to Signed Integer | |
5164 | Doubleword format with Saturate */ | |
5165 | case 152: /* VSX Vector truncate Single-Precision to | |
5166 | Integer and Convert to Signed Integer Word | |
5167 | Format with Saturate */ | |
5168 | case 392: /* VSX Vector truncate Single-Precision to | |
5169 | Integer and Convert to Unsigned Integer | |
5170 | Doubleword format with Saturate */ | |
5171 | case 136: /* VSX Vector truncate Single-Precision to | |
5172 | Integer and Convert to Unsigned Integer Word | |
5173 | Format with Saturate */ | |
5174 | case 504: /* VSX Vector Convert and round Signed Integer | |
5175 | Doubleword to Double-Precision format */ | |
5176 | case 440: /* VSX Vector Convert and round Signed Integer | |
5177 | Doubleword to Single-Precision format */ | |
5178 | case 248: /* VSX Vector Convert Signed Integer Word to | |
5179 | Double-Precision format */ | |
5180 | case 184: /* VSX Vector Convert and round Signed Integer | |
5181 | Word to Single-Precision format */ | |
5182 | case 488: /* VSX Vector Convert and round Unsigned | |
5183 | Integer Doubleword to Double-Precision format */ | |
5184 | case 424: /* VSX Vector Convert and round Unsigned | |
5185 | Integer Doubleword to Single-Precision format */ | |
5186 | case 232: /* VSX Vector Convert and round Unsigned | |
5187 | Integer Word to Double-Precision format */ | |
5188 | case 168: /* VSX Vector Convert and round Unsigned | |
5189 | Integer Word to Single-Precision format */ | |
5190 | case 201: /* VSX Vector Round to Double-Precision | |
5191 | Integer using round to Nearest Away */ | |
5192 | case 235: /* VSX Vector Round to Double-Precision | |
5193 | Integer Exact using Current rounding mode */ | |
5194 | case 249: /* VSX Vector Round to Double-Precision | |
5195 | Integer using round toward -Infinity */ | |
5196 | case 233: /* VSX Vector Round to Double-Precision | |
5197 | Integer using round toward +Infinity */ | |
5198 | case 217: /* VSX Vector Round to Double-Precision | |
5199 | Integer using round toward Zero */ | |
5200 | case 218: /* VSX Vector Reciprocal Estimate Double-Precision */ | |
5201 | case 154: /* VSX Vector Reciprocal Estimate Single-Precision */ | |
5202 | case 137: /* VSX Vector Round to Single-Precision Integer | |
5203 | Using Round to Nearest Away */ | |
5204 | case 171: /* VSX Vector Round to Single-Precision Integer | |
5205 | Exact Using Current rounding mode */ | |
5206 | case 185: /* VSX Vector Round to Single-Precision Integer | |
5207 | Using Round toward -Infinity */ | |
5208 | case 169: /* VSX Vector Round to Single-Precision Integer | |
5209 | Using Round toward +Infinity */ | |
5210 | case 153: /* VSX Vector Round to Single-Precision Integer | |
5211 | Using round toward Zero */ | |
5212 | case 202: /* VSX Vector Reciprocal Square Root Estimate | |
5213 | Double-Precision */ | |
5214 | case 138: /* VSX Vector Reciprocal Square Root Estimate | |
5215 | Single-Precision */ | |
5216 | case 203: /* VSX Vector Square Root Double-Precision */ | |
5217 | case 139: /* VSX Vector Square Root Single-Precision */ | |
5218 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
6ec2b213 | 5219 | /* FALL-THROUGH */ |
b4cdae6f WW |
5220 | case 345: /* VSX Scalar Absolute Value Double-Precision */ |
5221 | case 267: /* VSX Scalar Convert Scalar Single-Precision to | |
5222 | Vector Single-Precision format Non-signalling */ | |
5223 | case 331: /* VSX Scalar Convert Single-Precision to | |
5224 | Double-Precision format Non-signalling */ | |
5225 | case 361: /* VSX Scalar Negative Absolute Value Double-Precision */ | |
5226 | case 377: /* VSX Scalar Negate Double-Precision */ | |
5227 | case 473: /* VSX Vector Absolute Value Double-Precision */ | |
5228 | case 409: /* VSX Vector Absolute Value Single-Precision */ | |
5229 | case 489: /* VSX Vector Negative Absolute Value Double-Precision */ | |
5230 | case 425: /* VSX Vector Negative Absolute Value Single-Precision */ | |
5231 | case 505: /* VSX Vector Negate Double-Precision */ | |
5232 | case 441: /* VSX Vector Negate Single-Precision */ | |
5233 | case 164: /* VSX Splat Word */ | |
6ec2b213 EBM |
5234 | case 165: /* VSX Vector Extract Unsigned Word */ |
5235 | case 181: /* VSX Vector Insert Word */ | |
b4cdae6f WW |
5236 | ppc_record_vsr (regcache, tdep, PPC_XT (insn)); |
5237 | return 0; | |
5238 | ||
6ec2b213 EBM |
5239 | case 298: /* VSX Scalar Test Data Class Single-Precision */ |
5240 | case 362: /* VSX Scalar Test Data Class Double-Precision */ | |
5241 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
5242 | /* FALL-THROUGH */ | |
b4cdae6f WW |
5243 | case 106: /* VSX Scalar Test for software Square Root |
5244 | Double-Precision */ | |
5245 | case 234: /* VSX Vector Test for software Square Root | |
5246 | Double-Precision */ | |
5247 | case 170: /* VSX Vector Test for software Square Root | |
5248 | Single-Precision */ | |
5249 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
5250 | return 0; | |
6ec2b213 EBM |
5251 | |
5252 | case 347: | |
5253 | switch (PPC_FIELD (insn, 11, 5)) | |
5254 | { | |
5255 | case 0: /* VSX Scalar Extract Exponent Double-Precision */ | |
5256 | case 1: /* VSX Scalar Extract Significand Double-Precision */ | |
5257 | record_full_arch_list_add_reg (regcache, | |
5258 | tdep->ppc_gp0_regnum + PPC_RT (insn)); | |
5259 | return 0; | |
5260 | case 16: /* VSX Scalar Convert Half-Precision format to | |
5261 | Double-Precision format */ | |
5262 | case 17: /* VSX Scalar round & Convert Double-Precision format | |
5263 | to Half-Precision format */ | |
5264 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
5265 | ppc_record_vsr (regcache, tdep, PPC_XT (insn)); | |
5266 | return 0; | |
5267 | } | |
5268 | break; | |
5269 | ||
5270 | case 475: | |
5271 | switch (PPC_FIELD (insn, 11, 5)) | |
5272 | { | |
5273 | case 24: /* VSX Vector Convert Half-Precision format to | |
5274 | Single-Precision format */ | |
5275 | case 25: /* VSX Vector round and Convert Single-Precision format | |
5276 | to Half-Precision format */ | |
5277 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
5278 | /* FALL-THROUGH */ | |
5279 | case 0: /* VSX Vector Extract Exponent Double-Precision */ | |
5280 | case 1: /* VSX Vector Extract Significand Double-Precision */ | |
5281 | case 7: /* VSX Vector Byte-Reverse Halfword */ | |
5282 | case 8: /* VSX Vector Extract Exponent Single-Precision */ | |
5283 | case 9: /* VSX Vector Extract Significand Single-Precision */ | |
5284 | case 15: /* VSX Vector Byte-Reverse Word */ | |
5285 | case 23: /* VSX Vector Byte-Reverse Doubleword */ | |
5286 | case 31: /* VSX Vector Byte-Reverse Quadword */ | |
5287 | ppc_record_vsr (regcache, tdep, PPC_XT (insn)); | |
5288 | return 0; | |
5289 | } | |
5290 | break; | |
5291 | } | |
5292 | ||
5293 | switch (ext) | |
5294 | { | |
5295 | case 360: /* VSX Vector Splat Immediate Byte */ | |
5296 | if (PPC_FIELD (insn, 11, 2) == 0) | |
5297 | { | |
5298 | ppc_record_vsr (regcache, tdep, PPC_XT (insn)); | |
5299 | return 0; | |
5300 | } | |
5301 | break; | |
5302 | case 918: /* VSX Scalar Insert Exponent Double-Precision */ | |
5303 | ppc_record_vsr (regcache, tdep, PPC_XT (insn)); | |
5304 | return 0; | |
b4cdae6f WW |
5305 | } |
5306 | ||
5307 | if (((ext >> 3) & 0x3) == 3) /* VSX Select */ | |
5308 | { | |
5309 | ppc_record_vsr (regcache, tdep, PPC_XT (insn)); | |
5310 | return 0; | |
5311 | } | |
5312 | ||
810c1026 WW |
5313 | fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x " |
5314 | "at %s, 60-%d.\n", insn, paddress (gdbarch, addr), ext); | |
b4cdae6f WW |
5315 | return -1; |
5316 | } | |
5317 | ||
6ec2b213 EBM |
5318 | /* Parse and record instructions of primary opcode-61 at ADDR. |
5319 | Return 0 if successful. */ | |
5320 | ||
5321 | static int | |
5322 | ppc_process_record_op61 (struct gdbarch *gdbarch, struct regcache *regcache, | |
5323 | CORE_ADDR addr, uint32_t insn) | |
5324 | { | |
5325 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
5326 | ULONGEST ea = 0; | |
5327 | int size; | |
5328 | ||
5329 | switch (insn & 0x3) | |
5330 | { | |
5331 | case 0: /* Store Floating-Point Double Pair */ | |
5332 | case 2: /* Store VSX Scalar Doubleword */ | |
5333 | case 3: /* Store VSX Scalar Single */ | |
5334 | if (PPC_RA (insn) != 0) | |
5335 | regcache_raw_read_unsigned (regcache, | |
5336 | tdep->ppc_gp0_regnum + PPC_RA (insn), | |
5337 | &ea); | |
5338 | ea += PPC_DS (insn) << 2; | |
5339 | switch (insn & 0x3) | |
5340 | { | |
5341 | case 0: /* Store Floating-Point Double Pair */ | |
5342 | size = 16; | |
5343 | break; | |
5344 | case 2: /* Store VSX Scalar Doubleword */ | |
5345 | size = 8; | |
5346 | break; | |
5347 | case 3: /* Store VSX Scalar Single */ | |
5348 | size = 4; | |
5349 | break; | |
5350 | default: | |
5351 | gdb_assert (0); | |
5352 | } | |
5353 | record_full_arch_list_add_mem (ea, size); | |
5354 | return 0; | |
5355 | } | |
5356 | ||
5357 | switch (insn & 0x7) | |
5358 | { | |
5359 | case 1: /* Load VSX Vector */ | |
5360 | ppc_record_vsr (regcache, tdep, PPC_XT (insn)); | |
5361 | return 0; | |
5362 | case 5: /* Store VSX Vector */ | |
5363 | if (PPC_RA (insn) != 0) | |
5364 | regcache_raw_read_unsigned (regcache, | |
5365 | tdep->ppc_gp0_regnum + PPC_RA (insn), | |
5366 | &ea); | |
5367 | ea += PPC_DQ (insn) << 4; | |
5368 | record_full_arch_list_add_mem (ea, 16); | |
5369 | return 0; | |
5370 | } | |
5371 | ||
5372 | fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x " | |
5373 | "at %s.\n", insn, paddress (gdbarch, addr)); | |
5374 | return -1; | |
5375 | } | |
5376 | ||
ddeca1df WW |
5377 | /* Parse and record instructions of primary opcode-63 at ADDR. |
5378 | Return 0 if successful. */ | |
b4cdae6f WW |
5379 | |
5380 | static int | |
5381 | ppc_process_record_op63 (struct gdbarch *gdbarch, struct regcache *regcache, | |
5382 | CORE_ADDR addr, uint32_t insn) | |
5383 | { | |
5384 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
5385 | int ext = PPC_EXTOP (insn); | |
5386 | int tmp; | |
5387 | ||
5388 | switch (ext & 0x1f) | |
5389 | { | |
5390 | case 18: /* Floating Divide */ | |
5391 | case 20: /* Floating Subtract */ | |
5392 | case 21: /* Floating Add */ | |
5393 | case 22: /* Floating Square Root */ | |
5394 | case 24: /* Floating Reciprocal Estimate */ | |
5395 | case 25: /* Floating Multiply */ | |
5396 | case 26: /* Floating Reciprocal Square Root Estimate */ | |
5397 | case 28: /* Floating Multiply-Subtract */ | |
5398 | case 29: /* Floating Multiply-Add */ | |
5399 | case 30: /* Floating Negative Multiply-Subtract */ | |
5400 | case 31: /* Floating Negative Multiply-Add */ | |
5401 | record_full_arch_list_add_reg (regcache, | |
5402 | tdep->ppc_fp0_regnum + PPC_FRT (insn)); | |
5403 | if (PPC_RC (insn)) | |
5404 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
5405 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
5406 | return 0; | |
5407 | ||
5408 | case 23: /* Floating Select */ | |
5409 | record_full_arch_list_add_reg (regcache, | |
5410 | tdep->ppc_fp0_regnum + PPC_FRT (insn)); | |
5411 | if (PPC_RC (insn)) | |
5412 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
8aabe2e2 | 5413 | return 0; |
b4cdae6f WW |
5414 | } |
5415 | ||
6ec2b213 EBM |
5416 | switch (ext & 0xff) |
5417 | { | |
5418 | case 5: /* VSX Scalar Round to Quad-Precision Integer */ | |
5419 | case 37: /* VSX Scalar Round Quad-Precision to Double-Extended | |
5420 | Precision */ | |
5421 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
5422 | ppc_record_vsr (regcache, tdep, PPC_VRT (insn) + 32); | |
5423 | return 0; | |
5424 | } | |
5425 | ||
b4cdae6f WW |
5426 | switch (ext) |
5427 | { | |
5428 | case 2: /* DFP Add Quad */ | |
5429 | case 3: /* DFP Quantize Quad */ | |
5430 | case 34: /* DFP Multiply Quad */ | |
5431 | case 35: /* DFP Reround Quad */ | |
5432 | case 67: /* DFP Quantize Immediate Quad */ | |
5433 | case 99: /* DFP Round To FP Integer With Inexact Quad */ | |
5434 | case 227: /* DFP Round To FP Integer Without Inexact Quad */ | |
5435 | case 258: /* DFP Convert To DFP Extended Quad */ | |
5436 | case 514: /* DFP Subtract Quad */ | |
5437 | case 546: /* DFP Divide Quad */ | |
5438 | case 770: /* DFP Round To DFP Long Quad */ | |
5439 | case 802: /* DFP Convert From Fixed Quad */ | |
5440 | case 834: /* DFP Encode BCD To DPD Quad */ | |
5441 | if (PPC_RC (insn)) | |
5442 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
5443 | tmp = tdep->ppc_fp0_regnum + (PPC_FRT (insn) & ~1); | |
5444 | record_full_arch_list_add_reg (regcache, tmp); | |
5445 | record_full_arch_list_add_reg (regcache, tmp + 1); | |
5446 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
5447 | return 0; | |
5448 | ||
5449 | case 130: /* DFP Compare Ordered Quad */ | |
5450 | case 162: /* DFP Test Exponent Quad */ | |
5451 | case 194: /* DFP Test Data Class Quad */ | |
5452 | case 226: /* DFP Test Data Group Quad */ | |
5453 | case 642: /* DFP Compare Unordered Quad */ | |
5454 | case 674: /* DFP Test Significance Quad */ | |
6ec2b213 | 5455 | case 675: /* DFP Test Significance Immediate Quad */ |
b4cdae6f WW |
5456 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); |
5457 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
5458 | return 0; | |
5459 | ||
5460 | case 66: /* DFP Shift Significand Left Immediate Quad */ | |
5461 | case 98: /* DFP Shift Significand Right Immediate Quad */ | |
5462 | case 322: /* DFP Decode DPD To BCD Quad */ | |
5463 | case 866: /* DFP Insert Biased Exponent Quad */ | |
5464 | tmp = tdep->ppc_fp0_regnum + (PPC_FRT (insn) & ~1); | |
5465 | record_full_arch_list_add_reg (regcache, tmp); | |
5466 | record_full_arch_list_add_reg (regcache, tmp + 1); | |
5467 | if (PPC_RC (insn)) | |
5468 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
5469 | return 0; | |
5470 | ||
5471 | case 290: /* DFP Convert To Fixed Quad */ | |
5472 | record_full_arch_list_add_reg (regcache, | |
5473 | tdep->ppc_fp0_regnum + PPC_FRT (insn)); | |
5474 | if (PPC_RC (insn)) | |
5475 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
5476 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
8aabe2e2 | 5477 | return 0; |
b4cdae6f WW |
5478 | |
5479 | case 354: /* DFP Extract Biased Exponent Quad */ | |
5480 | record_full_arch_list_add_reg (regcache, | |
5481 | tdep->ppc_fp0_regnum + PPC_FRT (insn)); | |
5482 | if (PPC_RC (insn)) | |
5483 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
5484 | return 0; | |
5485 | ||
5486 | case 12: /* Floating Round to Single-Precision */ | |
5487 | case 14: /* Floating Convert To Integer Word */ | |
5488 | case 15: /* Floating Convert To Integer Word | |
5489 | with round toward Zero */ | |
5490 | case 142: /* Floating Convert To Integer Word Unsigned */ | |
5491 | case 143: /* Floating Convert To Integer Word Unsigned | |
5492 | with round toward Zero */ | |
5493 | case 392: /* Floating Round to Integer Nearest */ | |
5494 | case 424: /* Floating Round to Integer Toward Zero */ | |
5495 | case 456: /* Floating Round to Integer Plus */ | |
5496 | case 488: /* Floating Round to Integer Minus */ | |
5497 | case 814: /* Floating Convert To Integer Doubleword */ | |
5498 | case 815: /* Floating Convert To Integer Doubleword | |
5499 | with round toward Zero */ | |
5500 | case 846: /* Floating Convert From Integer Doubleword */ | |
5501 | case 942: /* Floating Convert To Integer Doubleword Unsigned */ | |
5502 | case 943: /* Floating Convert To Integer Doubleword Unsigned | |
5503 | with round toward Zero */ | |
5504 | case 974: /* Floating Convert From Integer Doubleword Unsigned */ | |
5505 | record_full_arch_list_add_reg (regcache, | |
5506 | tdep->ppc_fp0_regnum + PPC_FRT (insn)); | |
5507 | if (PPC_RC (insn)) | |
5508 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
5509 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
5510 | return 0; | |
5511 | ||
6ec2b213 EBM |
5512 | case 583: |
5513 | switch (PPC_FIELD (insn, 11, 5)) | |
5514 | { | |
5515 | case 1: /* Move From FPSCR & Clear Enables */ | |
5516 | case 20: /* Move From FPSCR Control & set DRN */ | |
5517 | case 21: /* Move From FPSCR Control & set DRN Immediate */ | |
5518 | case 22: /* Move From FPSCR Control & set RN */ | |
5519 | case 23: /* Move From FPSCR Control & set RN Immediate */ | |
5520 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
5521 | case 0: /* Move From FPSCR */ | |
5522 | case 24: /* Move From FPSCR Lightweight */ | |
5523 | if (PPC_FIELD (insn, 11, 5) == 0 && PPC_RC (insn)) | |
5524 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
5525 | record_full_arch_list_add_reg (regcache, | |
5526 | tdep->ppc_fp0_regnum | |
5527 | + PPC_FRT (insn)); | |
5528 | return 0; | |
5529 | } | |
5530 | break; | |
5531 | ||
b4cdae6f WW |
5532 | case 8: /* Floating Copy Sign */ |
5533 | case 40: /* Floating Negate */ | |
5534 | case 72: /* Floating Move Register */ | |
5535 | case 136: /* Floating Negative Absolute Value */ | |
5536 | case 264: /* Floating Absolute Value */ | |
5537 | record_full_arch_list_add_reg (regcache, | |
5538 | tdep->ppc_fp0_regnum + PPC_FRT (insn)); | |
5539 | if (PPC_RC (insn)) | |
5540 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
5541 | return 0; | |
5542 | ||
5543 | case 838: /* Floating Merge Odd Word */ | |
5544 | case 966: /* Floating Merge Even Word */ | |
5545 | record_full_arch_list_add_reg (regcache, | |
5546 | tdep->ppc_fp0_regnum + PPC_FRT (insn)); | |
5547 | return 0; | |
5548 | ||
5549 | case 38: /* Move To FPSCR Bit 1 */ | |
5550 | case 70: /* Move To FPSCR Bit 0 */ | |
5551 | case 134: /* Move To FPSCR Field Immediate */ | |
5552 | case 711: /* Move To FPSCR Fields */ | |
5553 | if (PPC_RC (insn)) | |
5554 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
5555 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
8aabe2e2 | 5556 | return 0; |
b4cdae6f WW |
5557 | |
5558 | case 0: /* Floating Compare Unordered */ | |
5559 | case 32: /* Floating Compare Ordered */ | |
5560 | case 64: /* Move to Condition Register from FPSCR */ | |
6ec2b213 EBM |
5561 | case 132: /* VSX Scalar Compare Ordered Quad-Precision */ |
5562 | case 164: /* VSX Scalar Compare Exponents Quad-Precision */ | |
5563 | case 644: /* VSX Scalar Compare Unordered Quad-Precision */ | |
5564 | case 708: /* VSX Scalar Test Data Class Quad-Precision */ | |
b4cdae6f WW |
5565 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); |
5566 | /* FALL-THROUGH */ | |
5567 | case 128: /* Floating Test for software Divide */ | |
5568 | case 160: /* Floating Test for software Square Root */ | |
5569 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
5570 | return 0; | |
5571 | ||
6ec2b213 EBM |
5572 | case 4: /* VSX Scalar Add Quad-Precision */ |
5573 | case 36: /* VSX Scalar Multiply Quad-Precision */ | |
5574 | case 388: /* VSX Scalar Multiply-Add Quad-Precision */ | |
5575 | case 420: /* VSX Scalar Multiply-Subtract Quad-Precision */ | |
5576 | case 452: /* VSX Scalar Negative Multiply-Add Quad-Precision */ | |
5577 | case 484: /* VSX Scalar Negative Multiply-Subtract | |
5578 | Quad-Precision */ | |
5579 | case 516: /* VSX Scalar Subtract Quad-Precision */ | |
5580 | case 548: /* VSX Scalar Divide Quad-Precision */ | |
5581 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
5582 | /* FALL-THROUGH */ | |
5583 | case 100: /* VSX Scalar Copy Sign Quad-Precision */ | |
5584 | case 868: /* VSX Scalar Insert Exponent Quad-Precision */ | |
5585 | ppc_record_vsr (regcache, tdep, PPC_VRT (insn) + 32); | |
5586 | return 0; | |
5587 | ||
5588 | case 804: | |
5589 | switch (PPC_FIELD (insn, 11, 5)) | |
5590 | { | |
5591 | case 27: /* VSX Scalar Square Root Quad-Precision */ | |
5592 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
5593 | /* FALL-THROUGH */ | |
5594 | case 0: /* VSX Scalar Absolute Quad-Precision */ | |
5595 | case 2: /* VSX Scalar Extract Exponent Quad-Precision */ | |
5596 | case 8: /* VSX Scalar Negative Absolute Quad-Precision */ | |
5597 | case 16: /* VSX Scalar Negate Quad-Precision */ | |
5598 | case 18: /* VSX Scalar Extract Significand Quad-Precision */ | |
5599 | ppc_record_vsr (regcache, tdep, PPC_VRT (insn) + 32); | |
5600 | return 0; | |
5601 | } | |
5602 | break; | |
5603 | ||
5604 | case 836: | |
5605 | switch (PPC_FIELD (insn, 11, 5)) | |
5606 | { | |
5607 | case 1: /* VSX Scalar truncate & Convert Quad-Precision format | |
5608 | to Unsigned Word format */ | |
5609 | case 2: /* VSX Scalar Convert Unsigned Doubleword format to | |
5610 | Quad-Precision format */ | |
5611 | case 9: /* VSX Scalar truncate & Convert Quad-Precision format | |
5612 | to Signed Word format */ | |
5613 | case 10: /* VSX Scalar Convert Signed Doubleword format to | |
5614 | Quad-Precision format */ | |
5615 | case 17: /* VSX Scalar truncate & Convert Quad-Precision format | |
5616 | to Unsigned Doubleword format */ | |
5617 | case 20: /* VSX Scalar round & Convert Quad-Precision format to | |
5618 | Double-Precision format */ | |
5619 | case 22: /* VSX Scalar Convert Double-Precision format to | |
5620 | Quad-Precision format */ | |
5621 | case 25: /* VSX Scalar truncate & Convert Quad-Precision format | |
5622 | to Signed Doubleword format */ | |
5623 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
5624 | ppc_record_vsr (regcache, tdep, PPC_VRT (insn) + 32); | |
5625 | return 0; | |
5626 | } | |
b4cdae6f WW |
5627 | } |
5628 | ||
810c1026 | 5629 | fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x " |
6ec2b213 | 5630 | "at %s, 63-%d.\n", insn, paddress (gdbarch, addr), ext); |
b4cdae6f WW |
5631 | return -1; |
5632 | } | |
5633 | ||
5634 | /* Parse the current instruction and record the values of the registers and | |
5635 | memory that will be changed in current instruction to "record_arch_list". | |
5636 | Return -1 if something wrong. */ | |
5637 | ||
5638 | int | |
5639 | ppc_process_record (struct gdbarch *gdbarch, struct regcache *regcache, | |
5640 | CORE_ADDR addr) | |
5641 | { | |
5642 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
5643 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
5644 | uint32_t insn; | |
5645 | int op6, tmp, i; | |
5646 | ||
5647 | insn = read_memory_unsigned_integer (addr, 4, byte_order); | |
5648 | op6 = PPC_OP6 (insn); | |
5649 | ||
5650 | switch (op6) | |
5651 | { | |
5652 | case 2: /* Trap Doubleword Immediate */ | |
5653 | case 3: /* Trap Word Immediate */ | |
5654 | /* Do nothing. */ | |
5655 | break; | |
5656 | ||
5657 | case 4: | |
5658 | if (ppc_process_record_op4 (gdbarch, regcache, addr, insn) != 0) | |
5659 | return -1; | |
5660 | break; | |
5661 | ||
5662 | case 17: /* System call */ | |
5663 | if (PPC_LEV (insn) != 0) | |
5664 | goto UNKNOWN_OP; | |
5665 | ||
5666 | if (tdep->ppc_syscall_record != NULL) | |
5667 | { | |
5668 | if (tdep->ppc_syscall_record (regcache) != 0) | |
5669 | return -1; | |
5670 | } | |
5671 | else | |
5672 | { | |
5673 | printf_unfiltered (_("no syscall record support\n")); | |
5674 | return -1; | |
5675 | } | |
5676 | break; | |
5677 | ||
5678 | case 7: /* Multiply Low Immediate */ | |
5679 | record_full_arch_list_add_reg (regcache, | |
5680 | tdep->ppc_gp0_regnum + PPC_RT (insn)); | |
5681 | break; | |
5682 | ||
5683 | case 8: /* Subtract From Immediate Carrying */ | |
5684 | record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum); | |
5685 | record_full_arch_list_add_reg (regcache, | |
5686 | tdep->ppc_gp0_regnum + PPC_RT (insn)); | |
5687 | break; | |
5688 | ||
5689 | case 10: /* Compare Logical Immediate */ | |
5690 | case 11: /* Compare Immediate */ | |
5691 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
5692 | break; | |
5693 | ||
5694 | case 13: /* Add Immediate Carrying and Record */ | |
5695 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
5696 | /* FALL-THROUGH */ | |
5697 | case 12: /* Add Immediate Carrying */ | |
5698 | record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum); | |
5699 | /* FALL-THROUGH */ | |
5700 | case 14: /* Add Immediate */ | |
5701 | case 15: /* Add Immediate Shifted */ | |
5702 | record_full_arch_list_add_reg (regcache, | |
5703 | tdep->ppc_gp0_regnum + PPC_RT (insn)); | |
5704 | break; | |
5705 | ||
5706 | case 16: /* Branch Conditional */ | |
5707 | if ((PPC_BO (insn) & 0x4) == 0) | |
5708 | record_full_arch_list_add_reg (regcache, tdep->ppc_ctr_regnum); | |
5709 | /* FALL-THROUGH */ | |
5710 | case 18: /* Branch */ | |
5711 | if (PPC_LK (insn)) | |
5712 | record_full_arch_list_add_reg (regcache, tdep->ppc_lr_regnum); | |
5713 | break; | |
5714 | ||
5715 | case 19: | |
5716 | if (ppc_process_record_op19 (gdbarch, regcache, addr, insn) != 0) | |
5717 | return -1; | |
5718 | break; | |
5719 | ||
5720 | case 20: /* Rotate Left Word Immediate then Mask Insert */ | |
5721 | case 21: /* Rotate Left Word Immediate then AND with Mask */ | |
5722 | case 23: /* Rotate Left Word then AND with Mask */ | |
5723 | case 30: /* Rotate Left Doubleword Immediate then Clear Left */ | |
5724 | /* Rotate Left Doubleword Immediate then Clear Right */ | |
5725 | /* Rotate Left Doubleword Immediate then Clear */ | |
5726 | /* Rotate Left Doubleword then Clear Left */ | |
5727 | /* Rotate Left Doubleword then Clear Right */ | |
5728 | /* Rotate Left Doubleword Immediate then Mask Insert */ | |
5729 | if (PPC_RC (insn)) | |
5730 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
5731 | record_full_arch_list_add_reg (regcache, | |
5732 | tdep->ppc_gp0_regnum + PPC_RA (insn)); | |
5733 | break; | |
5734 | ||
5735 | case 28: /* AND Immediate */ | |
5736 | case 29: /* AND Immediate Shifted */ | |
5737 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
5738 | /* FALL-THROUGH */ | |
5739 | case 24: /* OR Immediate */ | |
5740 | case 25: /* OR Immediate Shifted */ | |
5741 | case 26: /* XOR Immediate */ | |
5742 | case 27: /* XOR Immediate Shifted */ | |
5743 | record_full_arch_list_add_reg (regcache, | |
5744 | tdep->ppc_gp0_regnum + PPC_RA (insn)); | |
5745 | break; | |
5746 | ||
5747 | case 31: | |
5748 | if (ppc_process_record_op31 (gdbarch, regcache, addr, insn) != 0) | |
5749 | return -1; | |
5750 | break; | |
5751 | ||
5752 | case 33: /* Load Word and Zero with Update */ | |
5753 | case 35: /* Load Byte and Zero with Update */ | |
5754 | case 41: /* Load Halfword and Zero with Update */ | |
5755 | case 43: /* Load Halfword Algebraic with Update */ | |
5756 | record_full_arch_list_add_reg (regcache, | |
5757 | tdep->ppc_gp0_regnum + PPC_RA (insn)); | |
5758 | /* FALL-THROUGH */ | |
5759 | case 32: /* Load Word and Zero */ | |
5760 | case 34: /* Load Byte and Zero */ | |
5761 | case 40: /* Load Halfword and Zero */ | |
5762 | case 42: /* Load Halfword Algebraic */ | |
5763 | record_full_arch_list_add_reg (regcache, | |
5764 | tdep->ppc_gp0_regnum + PPC_RT (insn)); | |
5765 | break; | |
5766 | ||
5767 | case 46: /* Load Multiple Word */ | |
5768 | for (i = PPC_RT (insn); i < 32; i++) | |
5769 | record_full_arch_list_add_reg (regcache, tdep->ppc_gp0_regnum + i); | |
5770 | break; | |
5771 | ||
5772 | case 56: /* Load Quadword */ | |
5773 | tmp = tdep->ppc_gp0_regnum + (PPC_RT (insn) & ~1); | |
5774 | record_full_arch_list_add_reg (regcache, tmp); | |
5775 | record_full_arch_list_add_reg (regcache, tmp + 1); | |
5776 | break; | |
5777 | ||
5778 | case 49: /* Load Floating-Point Single with Update */ | |
5779 | case 51: /* Load Floating-Point Double with Update */ | |
5780 | record_full_arch_list_add_reg (regcache, | |
5781 | tdep->ppc_gp0_regnum + PPC_RA (insn)); | |
5782 | /* FALL-THROUGH */ | |
5783 | case 48: /* Load Floating-Point Single */ | |
5784 | case 50: /* Load Floating-Point Double */ | |
5785 | record_full_arch_list_add_reg (regcache, | |
5786 | tdep->ppc_fp0_regnum + PPC_FRT (insn)); | |
5787 | break; | |
5788 | ||
5789 | case 47: /* Store Multiple Word */ | |
5790 | { | |
5791 | ULONGEST addr = 0; | |
5792 | ||
5793 | if (PPC_RA (insn) != 0) | |
5794 | regcache_raw_read_unsigned (regcache, | |
5795 | tdep->ppc_gp0_regnum + PPC_RA (insn), | |
5796 | &addr); | |
5797 | ||
5798 | addr += PPC_D (insn); | |
5799 | record_full_arch_list_add_mem (addr, 4 * (32 - PPC_RS (insn))); | |
5800 | } | |
5801 | break; | |
5802 | ||
5803 | case 37: /* Store Word with Update */ | |
5804 | case 39: /* Store Byte with Update */ | |
5805 | case 45: /* Store Halfword with Update */ | |
5806 | case 53: /* Store Floating-Point Single with Update */ | |
5807 | case 55: /* Store Floating-Point Double with Update */ | |
5808 | record_full_arch_list_add_reg (regcache, | |
5809 | tdep->ppc_gp0_regnum + PPC_RA (insn)); | |
5810 | /* FALL-THROUGH */ | |
5811 | case 36: /* Store Word */ | |
5812 | case 38: /* Store Byte */ | |
5813 | case 44: /* Store Halfword */ | |
5814 | case 52: /* Store Floating-Point Single */ | |
5815 | case 54: /* Store Floating-Point Double */ | |
5816 | { | |
5817 | ULONGEST addr = 0; | |
5818 | int size = -1; | |
5819 | ||
5820 | if (PPC_RA (insn) != 0) | |
5821 | regcache_raw_read_unsigned (regcache, | |
5822 | tdep->ppc_gp0_regnum + PPC_RA (insn), | |
5823 | &addr); | |
5824 | addr += PPC_D (insn); | |
5825 | ||
5826 | if (op6 == 36 || op6 == 37 || op6 == 52 || op6 == 53) | |
5827 | size = 4; | |
5828 | else if (op6 == 54 || op6 == 55) | |
5829 | size = 8; | |
5830 | else if (op6 == 44 || op6 == 45) | |
5831 | size = 2; | |
5832 | else if (op6 == 38 || op6 == 39) | |
5833 | size = 1; | |
5834 | else | |
5835 | gdb_assert (0); | |
5836 | ||
5837 | record_full_arch_list_add_mem (addr, size); | |
5838 | } | |
5839 | break; | |
5840 | ||
6ec2b213 EBM |
5841 | case 57: |
5842 | switch (insn & 0x3) | |
5843 | { | |
5844 | case 0: /* Load Floating-Point Double Pair */ | |
5845 | tmp = tdep->ppc_fp0_regnum + (PPC_RT (insn) & ~1); | |
5846 | record_full_arch_list_add_reg (regcache, tmp); | |
5847 | record_full_arch_list_add_reg (regcache, tmp + 1); | |
5848 | break; | |
5849 | case 2: /* Load VSX Scalar Doubleword */ | |
5850 | case 3: /* Load VSX Scalar Single */ | |
5851 | ppc_record_vsr (regcache, tdep, PPC_VRT (insn) + 32); | |
5852 | break; | |
5853 | default: | |
5854 | goto UNKNOWN_OP; | |
5855 | } | |
b4cdae6f WW |
5856 | break; |
5857 | ||
5858 | case 58: /* Load Doubleword */ | |
5859 | /* Load Doubleword with Update */ | |
5860 | /* Load Word Algebraic */ | |
5861 | if (PPC_FIELD (insn, 30, 2) > 2) | |
5862 | goto UNKNOWN_OP; | |
5863 | ||
5864 | record_full_arch_list_add_reg (regcache, | |
5865 | tdep->ppc_gp0_regnum + PPC_RT (insn)); | |
5866 | if (PPC_BIT (insn, 31)) | |
5867 | record_full_arch_list_add_reg (regcache, | |
5868 | tdep->ppc_gp0_regnum + PPC_RA (insn)); | |
5869 | break; | |
5870 | ||
5871 | case 59: | |
5872 | if (ppc_process_record_op59 (gdbarch, regcache, addr, insn) != 0) | |
5873 | return -1; | |
5874 | break; | |
5875 | ||
5876 | case 60: | |
5877 | if (ppc_process_record_op60 (gdbarch, regcache, addr, insn) != 0) | |
5878 | return -1; | |
5879 | break; | |
5880 | ||
6ec2b213 EBM |
5881 | case 61: |
5882 | if (ppc_process_record_op61 (gdbarch, regcache, addr, insn) != 0) | |
5883 | return -1; | |
5884 | break; | |
5885 | ||
b4cdae6f WW |
5886 | case 62: /* Store Doubleword */ |
5887 | /* Store Doubleword with Update */ | |
5888 | /* Store Quadword with Update */ | |
5889 | { | |
5890 | ULONGEST addr = 0; | |
5891 | int size; | |
5892 | int sub2 = PPC_FIELD (insn, 30, 2); | |
5893 | ||
6ec2b213 | 5894 | if (sub2 > 2) |
b4cdae6f WW |
5895 | goto UNKNOWN_OP; |
5896 | ||
5897 | if (PPC_RA (insn) != 0) | |
5898 | regcache_raw_read_unsigned (regcache, | |
5899 | tdep->ppc_gp0_regnum + PPC_RA (insn), | |
5900 | &addr); | |
5901 | ||
6ec2b213 | 5902 | size = (sub2 == 2) ? 16 : 8; |
b4cdae6f WW |
5903 | |
5904 | addr += PPC_DS (insn) << 2; | |
5905 | record_full_arch_list_add_mem (addr, size); | |
5906 | ||
5907 | if (op6 == 62 && sub2 == 1) | |
5908 | record_full_arch_list_add_reg (regcache, | |
5909 | tdep->ppc_gp0_regnum + | |
5910 | PPC_RA (insn)); | |
5911 | ||
5912 | break; | |
5913 | } | |
5914 | ||
5915 | case 63: | |
5916 | if (ppc_process_record_op63 (gdbarch, regcache, addr, insn) != 0) | |
5917 | return -1; | |
5918 | break; | |
5919 | ||
5920 | default: | |
5921 | UNKNOWN_OP: | |
810c1026 WW |
5922 | fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x " |
5923 | "at %s, %d.\n", insn, paddress (gdbarch, addr), op6); | |
b4cdae6f WW |
5924 | return -1; |
5925 | } | |
5926 | ||
5927 | if (record_full_arch_list_add_reg (regcache, PPC_PC_REGNUM)) | |
5928 | return -1; | |
5929 | if (record_full_arch_list_add_end ()) | |
5930 | return -1; | |
5931 | return 0; | |
5932 | } | |
5933 | ||
7a78ae4e ND |
5934 | /* Initialize the current architecture based on INFO. If possible, re-use an |
5935 | architecture from ARCHES, which is a list of architectures already created | |
5936 | during this debugging session. | |
c906108c | 5937 | |
7a78ae4e | 5938 | Called e.g. at program startup, when reading a core file, and when reading |
64366f1c | 5939 | a binary file. */ |
c906108c | 5940 | |
7a78ae4e ND |
5941 | static struct gdbarch * |
5942 | rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
5943 | { | |
5944 | struct gdbarch *gdbarch; | |
5945 | struct gdbarch_tdep *tdep; | |
7cc46491 | 5946 | int wordsize, from_xcoff_exec, from_elf_exec; |
7a78ae4e ND |
5947 | enum bfd_architecture arch; |
5948 | unsigned long mach; | |
5949 | bfd abfd; | |
55eddb0f DJ |
5950 | enum auto_boolean soft_float_flag = powerpc_soft_float_global; |
5951 | int soft_float; | |
5952 | enum powerpc_vector_abi vector_abi = powerpc_vector_abi_global; | |
cd453cd0 | 5953 | enum powerpc_elf_abi elf_abi = POWERPC_ELF_AUTO; |
604c2f83 LM |
5954 | int have_fpu = 1, have_spe = 0, have_mq = 0, have_altivec = 0, have_dfp = 0, |
5955 | have_vsx = 0; | |
7cc46491 DJ |
5956 | int tdesc_wordsize = -1; |
5957 | const struct target_desc *tdesc = info.target_desc; | |
5958 | struct tdesc_arch_data *tdesc_data = NULL; | |
f949c649 | 5959 | int num_pseudoregs = 0; |
604c2f83 | 5960 | int cur_reg; |
7a78ae4e | 5961 | |
f4d9bade UW |
5962 | /* INFO may refer to a binary that is not of the PowerPC architecture, |
5963 | e.g. when debugging a stand-alone SPE executable on a Cell/B.E. system. | |
5964 | In this case, we must not attempt to infer properties of the (PowerPC | |
5965 | side) of the target system from properties of that executable. Trust | |
5966 | the target description instead. */ | |
5967 | if (info.abfd | |
5968 | && bfd_get_arch (info.abfd) != bfd_arch_powerpc | |
5969 | && bfd_get_arch (info.abfd) != bfd_arch_rs6000) | |
5970 | info.abfd = NULL; | |
5971 | ||
9aa1e687 | 5972 | from_xcoff_exec = info.abfd && info.abfd->format == bfd_object && |
7a78ae4e ND |
5973 | bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour; |
5974 | ||
9aa1e687 KB |
5975 | from_elf_exec = info.abfd && info.abfd->format == bfd_object && |
5976 | bfd_get_flavour (info.abfd) == bfd_target_elf_flavour; | |
5977 | ||
e712c1cf | 5978 | /* Check word size. If INFO is from a binary file, infer it from |
64366f1c | 5979 | that, else choose a likely default. */ |
9aa1e687 | 5980 | if (from_xcoff_exec) |
c906108c | 5981 | { |
11ed25ac | 5982 | if (bfd_xcoff_is_xcoff64 (info.abfd)) |
7a78ae4e ND |
5983 | wordsize = 8; |
5984 | else | |
5985 | wordsize = 4; | |
c906108c | 5986 | } |
9aa1e687 KB |
5987 | else if (from_elf_exec) |
5988 | { | |
5989 | if (elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
5990 | wordsize = 8; | |
5991 | else | |
5992 | wordsize = 4; | |
5993 | } | |
7cc46491 DJ |
5994 | else if (tdesc_has_registers (tdesc)) |
5995 | wordsize = -1; | |
c906108c | 5996 | else |
7a78ae4e | 5997 | { |
27b15785 | 5998 | if (info.bfd_arch_info != NULL && info.bfd_arch_info->bits_per_word != 0) |
16d8013c JB |
5999 | wordsize = (info.bfd_arch_info->bits_per_word |
6000 | / info.bfd_arch_info->bits_per_byte); | |
27b15785 KB |
6001 | else |
6002 | wordsize = 4; | |
7a78ae4e | 6003 | } |
c906108c | 6004 | |
475bbd17 JB |
6005 | /* Get the architecture and machine from the BFD. */ |
6006 | arch = info.bfd_arch_info->arch; | |
6007 | mach = info.bfd_arch_info->mach; | |
5bf1c677 EZ |
6008 | |
6009 | /* For e500 executables, the apuinfo section is of help here. Such | |
6010 | section contains the identifier and revision number of each | |
6011 | Application-specific Processing Unit that is present on the | |
6012 | chip. The content of the section is determined by the assembler | |
6013 | which looks at each instruction and determines which unit (and | |
74af9197 NF |
6014 | which version of it) can execute it. Grovel through the section |
6015 | looking for relevant e500 APUs. */ | |
5bf1c677 | 6016 | |
74af9197 | 6017 | if (bfd_uses_spe_extensions (info.abfd)) |
5bf1c677 | 6018 | { |
74af9197 NF |
6019 | arch = info.bfd_arch_info->arch; |
6020 | mach = bfd_mach_ppc_e500; | |
6021 | bfd_default_set_arch_mach (&abfd, arch, mach); | |
6022 | info.bfd_arch_info = bfd_get_arch_info (&abfd); | |
5bf1c677 EZ |
6023 | } |
6024 | ||
7cc46491 DJ |
6025 | /* Find a default target description which describes our register |
6026 | layout, if we do not already have one. */ | |
6027 | if (! tdesc_has_registers (tdesc)) | |
6028 | { | |
6029 | const struct variant *v; | |
6030 | ||
6031 | /* Choose variant. */ | |
6032 | v = find_variant_by_arch (arch, mach); | |
6033 | if (!v) | |
6034 | return NULL; | |
6035 | ||
6036 | tdesc = *v->tdesc; | |
6037 | } | |
6038 | ||
6039 | gdb_assert (tdesc_has_registers (tdesc)); | |
6040 | ||
6041 | /* Check any target description for validity. */ | |
6042 | if (tdesc_has_registers (tdesc)) | |
6043 | { | |
6044 | static const char *const gprs[] = { | |
6045 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
6046 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
6047 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
6048 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" | |
6049 | }; | |
7cc46491 DJ |
6050 | const struct tdesc_feature *feature; |
6051 | int i, valid_p; | |
6052 | static const char *const msr_names[] = { "msr", "ps" }; | |
6053 | static const char *const cr_names[] = { "cr", "cnd" }; | |
6054 | static const char *const ctr_names[] = { "ctr", "cnt" }; | |
6055 | ||
6056 | feature = tdesc_find_feature (tdesc, | |
6057 | "org.gnu.gdb.power.core"); | |
6058 | if (feature == NULL) | |
6059 | return NULL; | |
6060 | ||
6061 | tdesc_data = tdesc_data_alloc (); | |
6062 | ||
6063 | valid_p = 1; | |
6064 | for (i = 0; i < ppc_num_gprs; i++) | |
6065 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, gprs[i]); | |
6066 | valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_PC_REGNUM, | |
6067 | "pc"); | |
6068 | valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_LR_REGNUM, | |
6069 | "lr"); | |
6070 | valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_XER_REGNUM, | |
6071 | "xer"); | |
6072 | ||
6073 | /* Allow alternate names for these registers, to accomodate GDB's | |
6074 | historic naming. */ | |
6075 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data, | |
6076 | PPC_MSR_REGNUM, msr_names); | |
6077 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data, | |
6078 | PPC_CR_REGNUM, cr_names); | |
6079 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data, | |
6080 | PPC_CTR_REGNUM, ctr_names); | |
6081 | ||
6082 | if (!valid_p) | |
6083 | { | |
6084 | tdesc_data_cleanup (tdesc_data); | |
6085 | return NULL; | |
6086 | } | |
6087 | ||
6088 | have_mq = tdesc_numbered_register (feature, tdesc_data, PPC_MQ_REGNUM, | |
6089 | "mq"); | |
6090 | ||
6091 | tdesc_wordsize = tdesc_register_size (feature, "pc") / 8; | |
6092 | if (wordsize == -1) | |
6093 | wordsize = tdesc_wordsize; | |
6094 | ||
6095 | feature = tdesc_find_feature (tdesc, | |
6096 | "org.gnu.gdb.power.fpu"); | |
6097 | if (feature != NULL) | |
6098 | { | |
6099 | static const char *const fprs[] = { | |
6100 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
6101 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
6102 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
6103 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31" | |
6104 | }; | |
6105 | valid_p = 1; | |
6106 | for (i = 0; i < ppc_num_fprs; i++) | |
6107 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
6108 | PPC_F0_REGNUM + i, fprs[i]); | |
6109 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
6110 | PPC_FPSCR_REGNUM, "fpscr"); | |
6111 | ||
6112 | if (!valid_p) | |
6113 | { | |
6114 | tdesc_data_cleanup (tdesc_data); | |
6115 | return NULL; | |
6116 | } | |
6117 | have_fpu = 1; | |
6118 | } | |
6119 | else | |
6120 | have_fpu = 0; | |
6121 | ||
f949c649 TJB |
6122 | /* The DFP pseudo-registers will be available when there are floating |
6123 | point registers. */ | |
6124 | have_dfp = have_fpu; | |
6125 | ||
7cc46491 DJ |
6126 | feature = tdesc_find_feature (tdesc, |
6127 | "org.gnu.gdb.power.altivec"); | |
6128 | if (feature != NULL) | |
6129 | { | |
6130 | static const char *const vector_regs[] = { | |
6131 | "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7", | |
6132 | "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15", | |
6133 | "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23", | |
6134 | "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31" | |
6135 | }; | |
6136 | ||
6137 | valid_p = 1; | |
6138 | for (i = 0; i < ppc_num_gprs; i++) | |
6139 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
6140 | PPC_VR0_REGNUM + i, | |
6141 | vector_regs[i]); | |
6142 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
6143 | PPC_VSCR_REGNUM, "vscr"); | |
6144 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
6145 | PPC_VRSAVE_REGNUM, "vrsave"); | |
6146 | ||
6147 | if (have_spe || !valid_p) | |
6148 | { | |
6149 | tdesc_data_cleanup (tdesc_data); | |
6150 | return NULL; | |
6151 | } | |
6152 | have_altivec = 1; | |
6153 | } | |
6154 | else | |
6155 | have_altivec = 0; | |
6156 | ||
604c2f83 LM |
6157 | /* Check for POWER7 VSX registers support. */ |
6158 | feature = tdesc_find_feature (tdesc, | |
6159 | "org.gnu.gdb.power.vsx"); | |
6160 | ||
6161 | if (feature != NULL) | |
6162 | { | |
6163 | static const char *const vsx_regs[] = { | |
6164 | "vs0h", "vs1h", "vs2h", "vs3h", "vs4h", "vs5h", | |
6165 | "vs6h", "vs7h", "vs8h", "vs9h", "vs10h", "vs11h", | |
6166 | "vs12h", "vs13h", "vs14h", "vs15h", "vs16h", "vs17h", | |
6167 | "vs18h", "vs19h", "vs20h", "vs21h", "vs22h", "vs23h", | |
6168 | "vs24h", "vs25h", "vs26h", "vs27h", "vs28h", "vs29h", | |
6169 | "vs30h", "vs31h" | |
6170 | }; | |
6171 | ||
6172 | valid_p = 1; | |
6173 | ||
6174 | for (i = 0; i < ppc_num_vshrs; i++) | |
6175 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
6176 | PPC_VSR0_UPPER_REGNUM + i, | |
6177 | vsx_regs[i]); | |
6178 | if (!valid_p) | |
6179 | { | |
6180 | tdesc_data_cleanup (tdesc_data); | |
6181 | return NULL; | |
6182 | } | |
6183 | ||
6184 | have_vsx = 1; | |
6185 | } | |
6186 | else | |
6187 | have_vsx = 0; | |
6188 | ||
7cc46491 DJ |
6189 | /* On machines supporting the SPE APU, the general-purpose registers |
6190 | are 64 bits long. There are SIMD vector instructions to treat them | |
6191 | as pairs of floats, but the rest of the instruction set treats them | |
6192 | as 32-bit registers, and only operates on their lower halves. | |
6193 | ||
6194 | In the GDB regcache, we treat their high and low halves as separate | |
6195 | registers. The low halves we present as the general-purpose | |
6196 | registers, and then we have pseudo-registers that stitch together | |
6197 | the upper and lower halves and present them as pseudo-registers. | |
6198 | ||
6199 | Thus, the target description is expected to supply the upper | |
6200 | halves separately. */ | |
6201 | ||
6202 | feature = tdesc_find_feature (tdesc, | |
6203 | "org.gnu.gdb.power.spe"); | |
6204 | if (feature != NULL) | |
6205 | { | |
6206 | static const char *const upper_spe[] = { | |
6207 | "ev0h", "ev1h", "ev2h", "ev3h", | |
6208 | "ev4h", "ev5h", "ev6h", "ev7h", | |
6209 | "ev8h", "ev9h", "ev10h", "ev11h", | |
6210 | "ev12h", "ev13h", "ev14h", "ev15h", | |
6211 | "ev16h", "ev17h", "ev18h", "ev19h", | |
6212 | "ev20h", "ev21h", "ev22h", "ev23h", | |
6213 | "ev24h", "ev25h", "ev26h", "ev27h", | |
6214 | "ev28h", "ev29h", "ev30h", "ev31h" | |
6215 | }; | |
6216 | ||
6217 | valid_p = 1; | |
6218 | for (i = 0; i < ppc_num_gprs; i++) | |
6219 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
6220 | PPC_SPE_UPPER_GP0_REGNUM + i, | |
6221 | upper_spe[i]); | |
6222 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
6223 | PPC_SPE_ACC_REGNUM, "acc"); | |
6224 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
6225 | PPC_SPE_FSCR_REGNUM, "spefscr"); | |
6226 | ||
6227 | if (have_mq || have_fpu || !valid_p) | |
6228 | { | |
6229 | tdesc_data_cleanup (tdesc_data); | |
6230 | return NULL; | |
6231 | } | |
6232 | have_spe = 1; | |
6233 | } | |
6234 | else | |
6235 | have_spe = 0; | |
6236 | } | |
6237 | ||
6238 | /* If we have a 64-bit binary on a 32-bit target, complain. Also | |
6239 | complain for a 32-bit binary on a 64-bit target; we do not yet | |
6240 | support that. For instance, the 32-bit ABI routines expect | |
6241 | 32-bit GPRs. | |
6242 | ||
6243 | As long as there isn't an explicit target description, we'll | |
6244 | choose one based on the BFD architecture and get a word size | |
6245 | matching the binary (probably powerpc:common or | |
6246 | powerpc:common64). So there is only trouble if a 64-bit target | |
6247 | supplies a 64-bit description while debugging a 32-bit | |
6248 | binary. */ | |
6249 | if (tdesc_wordsize != -1 && tdesc_wordsize != wordsize) | |
6250 | { | |
6251 | tdesc_data_cleanup (tdesc_data); | |
6252 | return NULL; | |
6253 | } | |
6254 | ||
55eddb0f | 6255 | #ifdef HAVE_ELF |
cd453cd0 UW |
6256 | if (from_elf_exec) |
6257 | { | |
6258 | switch (elf_elfheader (info.abfd)->e_flags & EF_PPC64_ABI) | |
6259 | { | |
6260 | case 1: | |
6261 | elf_abi = POWERPC_ELF_V1; | |
6262 | break; | |
6263 | case 2: | |
6264 | elf_abi = POWERPC_ELF_V2; | |
6265 | break; | |
6266 | default: | |
6267 | break; | |
6268 | } | |
6269 | } | |
6270 | ||
55eddb0f DJ |
6271 | if (soft_float_flag == AUTO_BOOLEAN_AUTO && from_elf_exec) |
6272 | { | |
6273 | switch (bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU, | |
6274 | Tag_GNU_Power_ABI_FP)) | |
6275 | { | |
6276 | case 1: | |
6277 | soft_float_flag = AUTO_BOOLEAN_FALSE; | |
6278 | break; | |
6279 | case 2: | |
6280 | soft_float_flag = AUTO_BOOLEAN_TRUE; | |
6281 | break; | |
6282 | default: | |
6283 | break; | |
6284 | } | |
6285 | } | |
6286 | ||
6287 | if (vector_abi == POWERPC_VEC_AUTO && from_elf_exec) | |
6288 | { | |
6289 | switch (bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU, | |
6290 | Tag_GNU_Power_ABI_Vector)) | |
6291 | { | |
6292 | case 1: | |
6293 | vector_abi = POWERPC_VEC_GENERIC; | |
6294 | break; | |
6295 | case 2: | |
6296 | vector_abi = POWERPC_VEC_ALTIVEC; | |
6297 | break; | |
6298 | case 3: | |
6299 | vector_abi = POWERPC_VEC_SPE; | |
6300 | break; | |
6301 | default: | |
6302 | break; | |
6303 | } | |
6304 | } | |
6305 | #endif | |
6306 | ||
cd453cd0 UW |
6307 | /* At this point, the only supported ELF-based 64-bit little-endian |
6308 | operating system is GNU/Linux, and this uses the ELFv2 ABI by | |
6309 | default. All other supported ELF-based operating systems use the | |
6310 | ELFv1 ABI by default. Therefore, if the ABI marker is missing, | |
6311 | e.g. because we run a legacy binary, or have attached to a process | |
6312 | and have not found any associated binary file, set the default | |
6313 | according to this heuristic. */ | |
6314 | if (elf_abi == POWERPC_ELF_AUTO) | |
6315 | { | |
6316 | if (wordsize == 8 && info.byte_order == BFD_ENDIAN_LITTLE) | |
6317 | elf_abi = POWERPC_ELF_V2; | |
6318 | else | |
6319 | elf_abi = POWERPC_ELF_V1; | |
6320 | } | |
6321 | ||
55eddb0f DJ |
6322 | if (soft_float_flag == AUTO_BOOLEAN_TRUE) |
6323 | soft_float = 1; | |
6324 | else if (soft_float_flag == AUTO_BOOLEAN_FALSE) | |
6325 | soft_float = 0; | |
6326 | else | |
6327 | soft_float = !have_fpu; | |
6328 | ||
6329 | /* If we have a hard float binary or setting but no floating point | |
6330 | registers, downgrade to soft float anyway. We're still somewhat | |
6331 | useful in this scenario. */ | |
6332 | if (!soft_float && !have_fpu) | |
6333 | soft_float = 1; | |
6334 | ||
6335 | /* Similarly for vector registers. */ | |
6336 | if (vector_abi == POWERPC_VEC_ALTIVEC && !have_altivec) | |
6337 | vector_abi = POWERPC_VEC_GENERIC; | |
6338 | ||
6339 | if (vector_abi == POWERPC_VEC_SPE && !have_spe) | |
6340 | vector_abi = POWERPC_VEC_GENERIC; | |
6341 | ||
6342 | if (vector_abi == POWERPC_VEC_AUTO) | |
6343 | { | |
6344 | if (have_altivec) | |
6345 | vector_abi = POWERPC_VEC_ALTIVEC; | |
6346 | else if (have_spe) | |
6347 | vector_abi = POWERPC_VEC_SPE; | |
6348 | else | |
6349 | vector_abi = POWERPC_VEC_GENERIC; | |
6350 | } | |
6351 | ||
6352 | /* Do not limit the vector ABI based on available hardware, since we | |
6353 | do not yet know what hardware we'll decide we have. Yuck! FIXME! */ | |
6354 | ||
7cc46491 DJ |
6355 | /* Find a candidate among extant architectures. */ |
6356 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
6357 | arches != NULL; | |
6358 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
6359 | { | |
6360 | /* Word size in the various PowerPC bfd_arch_info structs isn't | |
6361 | meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform | |
6362 | separate word size check. */ | |
6363 | tdep = gdbarch_tdep (arches->gdbarch); | |
cd453cd0 UW |
6364 | if (tdep && tdep->elf_abi != elf_abi) |
6365 | continue; | |
55eddb0f DJ |
6366 | if (tdep && tdep->soft_float != soft_float) |
6367 | continue; | |
6368 | if (tdep && tdep->vector_abi != vector_abi) | |
6369 | continue; | |
7cc46491 DJ |
6370 | if (tdep && tdep->wordsize == wordsize) |
6371 | { | |
6372 | if (tdesc_data != NULL) | |
6373 | tdesc_data_cleanup (tdesc_data); | |
6374 | return arches->gdbarch; | |
6375 | } | |
6376 | } | |
6377 | ||
6378 | /* None found, create a new architecture from INFO, whose bfd_arch_info | |
6379 | validity depends on the source: | |
6380 | - executable useless | |
6381 | - rs6000_host_arch() good | |
6382 | - core file good | |
6383 | - "set arch" trust blindly | |
6384 | - GDB startup useless but harmless */ | |
6385 | ||
fc270c35 | 6386 | tdep = XCNEW (struct gdbarch_tdep); |
7cc46491 | 6387 | tdep->wordsize = wordsize; |
cd453cd0 | 6388 | tdep->elf_abi = elf_abi; |
55eddb0f DJ |
6389 | tdep->soft_float = soft_float; |
6390 | tdep->vector_abi = vector_abi; | |
7cc46491 | 6391 | |
7a78ae4e | 6392 | gdbarch = gdbarch_alloc (&info, tdep); |
7a78ae4e | 6393 | |
7cc46491 DJ |
6394 | tdep->ppc_gp0_regnum = PPC_R0_REGNUM; |
6395 | tdep->ppc_toc_regnum = PPC_R0_REGNUM + 2; | |
6396 | tdep->ppc_ps_regnum = PPC_MSR_REGNUM; | |
6397 | tdep->ppc_cr_regnum = PPC_CR_REGNUM; | |
6398 | tdep->ppc_lr_regnum = PPC_LR_REGNUM; | |
6399 | tdep->ppc_ctr_regnum = PPC_CTR_REGNUM; | |
6400 | tdep->ppc_xer_regnum = PPC_XER_REGNUM; | |
6401 | tdep->ppc_mq_regnum = have_mq ? PPC_MQ_REGNUM : -1; | |
6402 | ||
6403 | tdep->ppc_fp0_regnum = have_fpu ? PPC_F0_REGNUM : -1; | |
6404 | tdep->ppc_fpscr_regnum = have_fpu ? PPC_FPSCR_REGNUM : -1; | |
604c2f83 | 6405 | tdep->ppc_vsr0_upper_regnum = have_vsx ? PPC_VSR0_UPPER_REGNUM : -1; |
7cc46491 DJ |
6406 | tdep->ppc_vr0_regnum = have_altivec ? PPC_VR0_REGNUM : -1; |
6407 | tdep->ppc_vrsave_regnum = have_altivec ? PPC_VRSAVE_REGNUM : -1; | |
6408 | tdep->ppc_ev0_upper_regnum = have_spe ? PPC_SPE_UPPER_GP0_REGNUM : -1; | |
6409 | tdep->ppc_acc_regnum = have_spe ? PPC_SPE_ACC_REGNUM : -1; | |
6410 | tdep->ppc_spefscr_regnum = have_spe ? PPC_SPE_FSCR_REGNUM : -1; | |
6411 | ||
6412 | set_gdbarch_pc_regnum (gdbarch, PPC_PC_REGNUM); | |
6413 | set_gdbarch_sp_regnum (gdbarch, PPC_R0_REGNUM + 1); | |
7cc46491 | 6414 | set_gdbarch_fp0_regnum (gdbarch, tdep->ppc_fp0_regnum); |
9f643768 | 6415 | set_gdbarch_register_sim_regno (gdbarch, rs6000_register_sim_regno); |
7cc46491 DJ |
6416 | |
6417 | /* The XML specification for PowerPC sensibly calls the MSR "msr". | |
6418 | GDB traditionally called it "ps", though, so let GDB add an | |
6419 | alias. */ | |
6420 | set_gdbarch_ps_regnum (gdbarch, tdep->ppc_ps_regnum); | |
6421 | ||
4a7622d1 | 6422 | if (wordsize == 8) |
05580c65 | 6423 | set_gdbarch_return_value (gdbarch, ppc64_sysv_abi_return_value); |
afd48b75 | 6424 | else |
4a7622d1 | 6425 | set_gdbarch_return_value (gdbarch, ppc_sysv_abi_return_value); |
c8001721 | 6426 | |
baffbae0 JB |
6427 | /* Set lr_frame_offset. */ |
6428 | if (wordsize == 8) | |
6429 | tdep->lr_frame_offset = 16; | |
baffbae0 | 6430 | else |
4a7622d1 | 6431 | tdep->lr_frame_offset = 4; |
baffbae0 | 6432 | |
604c2f83 | 6433 | if (have_spe || have_dfp || have_vsx) |
7cc46491 | 6434 | { |
f949c649 | 6435 | set_gdbarch_pseudo_register_read (gdbarch, rs6000_pseudo_register_read); |
0df8b418 MS |
6436 | set_gdbarch_pseudo_register_write (gdbarch, |
6437 | rs6000_pseudo_register_write); | |
2a2fa07b MK |
6438 | set_gdbarch_ax_pseudo_register_collect (gdbarch, |
6439 | rs6000_ax_pseudo_register_collect); | |
7cc46491 | 6440 | } |
1fcc0bb8 | 6441 | |
a67914de MK |
6442 | set_gdbarch_gen_return_address (gdbarch, rs6000_gen_return_address); |
6443 | ||
e0d24f8d WZ |
6444 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); |
6445 | ||
5a9e69ba | 6446 | set_gdbarch_num_regs (gdbarch, PPC_NUM_REGS); |
f949c649 TJB |
6447 | |
6448 | if (have_spe) | |
6449 | num_pseudoregs += 32; | |
6450 | if (have_dfp) | |
6451 | num_pseudoregs += 16; | |
604c2f83 LM |
6452 | if (have_vsx) |
6453 | /* Include both VSX and Extended FP registers. */ | |
6454 | num_pseudoregs += 96; | |
f949c649 TJB |
6455 | |
6456 | set_gdbarch_num_pseudo_regs (gdbarch, num_pseudoregs); | |
7a78ae4e ND |
6457 | |
6458 | set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT); | |
6459 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); | |
6460 | set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
6461 | set_gdbarch_long_bit (gdbarch, wordsize * TARGET_CHAR_BIT); | |
6462 | set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
6463 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
6464 | set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
4a7622d1 | 6465 | set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT); |
4e409299 | 6466 | set_gdbarch_char_signed (gdbarch, 0); |
7a78ae4e | 6467 | |
11269d7e | 6468 | set_gdbarch_frame_align (gdbarch, rs6000_frame_align); |
4a7622d1 | 6469 | if (wordsize == 8) |
8b148df9 AC |
6470 | /* PPC64 SYSV. */ |
6471 | set_gdbarch_frame_red_zone_size (gdbarch, 288); | |
7a78ae4e | 6472 | |
691d145a JB |
6473 | set_gdbarch_convert_register_p (gdbarch, rs6000_convert_register_p); |
6474 | set_gdbarch_register_to_value (gdbarch, rs6000_register_to_value); | |
6475 | set_gdbarch_value_to_register (gdbarch, rs6000_value_to_register); | |
6476 | ||
18ed0c4e JB |
6477 | set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_stab_reg_to_regnum); |
6478 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rs6000_dwarf2_reg_to_regnum); | |
d217aaed | 6479 | |
4a7622d1 | 6480 | if (wordsize == 4) |
77b2b6d4 | 6481 | set_gdbarch_push_dummy_call (gdbarch, ppc_sysv_abi_push_dummy_call); |
4a7622d1 | 6482 | else if (wordsize == 8) |
8be9034a | 6483 | set_gdbarch_push_dummy_call (gdbarch, ppc64_sysv_abi_push_dummy_call); |
7a78ae4e | 6484 | |
7a78ae4e | 6485 | set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue); |
c9cf6e20 | 6486 | set_gdbarch_stack_frame_destroyed_p (gdbarch, rs6000_stack_frame_destroyed_p); |
8ab3d180 | 6487 | set_gdbarch_skip_main_prologue (gdbarch, rs6000_skip_main_prologue); |
0d1243d9 | 6488 | |
7a78ae4e | 6489 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
04180708 YQ |
6490 | |
6491 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, | |
6492 | rs6000_breakpoint::kind_from_pc); | |
6493 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, | |
6494 | rs6000_breakpoint::bp_from_kind); | |
7a78ae4e | 6495 | |
203c3895 | 6496 | /* The value of symbols of type N_SO and N_FUN maybe null when |
0df8b418 | 6497 | it shouldn't be. */ |
203c3895 UW |
6498 | set_gdbarch_sofun_address_maybe_missing (gdbarch, 1); |
6499 | ||
ce5eab59 | 6500 | /* Handles single stepping of atomic sequences. */ |
4a7622d1 | 6501 | set_gdbarch_software_single_step (gdbarch, ppc_deal_with_atomic_sequence); |
ce5eab59 | 6502 | |
0df8b418 | 6503 | /* Not sure on this. FIXMEmgo */ |
7a78ae4e ND |
6504 | set_gdbarch_frame_args_skip (gdbarch, 8); |
6505 | ||
143985b7 AF |
6506 | /* Helpers for function argument information. */ |
6507 | set_gdbarch_fetch_pointer_argument (gdbarch, rs6000_fetch_pointer_argument); | |
6508 | ||
6f7f3f0d UW |
6509 | /* Trampoline. */ |
6510 | set_gdbarch_in_solib_return_trampoline | |
6511 | (gdbarch, rs6000_in_solib_return_trampoline); | |
6512 | set_gdbarch_skip_trampoline_code (gdbarch, rs6000_skip_trampoline_code); | |
6513 | ||
4fc771b8 | 6514 | /* Hook in the DWARF CFI frame unwinder. */ |
1af5d7ce | 6515 | dwarf2_append_unwinders (gdbarch); |
4fc771b8 DJ |
6516 | dwarf2_frame_set_adjust_regnum (gdbarch, rs6000_adjust_frame_regnum); |
6517 | ||
9274a07c LM |
6518 | /* Frame handling. */ |
6519 | dwarf2_frame_set_init_reg (gdbarch, ppc_dwarf2_frame_init_reg); | |
6520 | ||
2454a024 UW |
6521 | /* Setup displaced stepping. */ |
6522 | set_gdbarch_displaced_step_copy_insn (gdbarch, | |
7f03bd92 | 6523 | ppc_displaced_step_copy_insn); |
99e40580 UW |
6524 | set_gdbarch_displaced_step_hw_singlestep (gdbarch, |
6525 | ppc_displaced_step_hw_singlestep); | |
2454a024 | 6526 | set_gdbarch_displaced_step_fixup (gdbarch, ppc_displaced_step_fixup); |
2454a024 UW |
6527 | set_gdbarch_displaced_step_location (gdbarch, |
6528 | displaced_step_at_entry_point); | |
6529 | ||
6530 | set_gdbarch_max_insn_length (gdbarch, PPC_INSN_SIZE); | |
6531 | ||
7b112f9c | 6532 | /* Hook in ABI-specific overrides, if they have been registered. */ |
8a4c2d24 | 6533 | info.target_desc = tdesc; |
0dba2a6c | 6534 | info.tdesc_data = tdesc_data; |
4be87837 | 6535 | gdbarch_init_osabi (info, gdbarch); |
7b112f9c | 6536 | |
61a65099 KB |
6537 | switch (info.osabi) |
6538 | { | |
f5aecab8 | 6539 | case GDB_OSABI_LINUX: |
1736a7bd | 6540 | case GDB_OSABI_NETBSD: |
61a65099 | 6541 | case GDB_OSABI_UNKNOWN: |
61a65099 | 6542 | set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc); |
2608dbf8 | 6543 | frame_unwind_append_unwinder (gdbarch, &rs6000_epilogue_frame_unwind); |
1af5d7ce UW |
6544 | frame_unwind_append_unwinder (gdbarch, &rs6000_frame_unwind); |
6545 | set_gdbarch_dummy_id (gdbarch, rs6000_dummy_id); | |
61a65099 KB |
6546 | frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer); |
6547 | break; | |
6548 | default: | |
61a65099 | 6549 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); |
81332287 KB |
6550 | |
6551 | set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc); | |
2608dbf8 | 6552 | frame_unwind_append_unwinder (gdbarch, &rs6000_epilogue_frame_unwind); |
1af5d7ce UW |
6553 | frame_unwind_append_unwinder (gdbarch, &rs6000_frame_unwind); |
6554 | set_gdbarch_dummy_id (gdbarch, rs6000_dummy_id); | |
81332287 | 6555 | frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer); |
61a65099 KB |
6556 | } |
6557 | ||
7cc46491 DJ |
6558 | set_tdesc_pseudo_register_type (gdbarch, rs6000_pseudo_register_type); |
6559 | set_tdesc_pseudo_register_reggroup_p (gdbarch, | |
6560 | rs6000_pseudo_register_reggroup_p); | |
6561 | tdesc_use_registers (gdbarch, tdesc, tdesc_data); | |
6562 | ||
6563 | /* Override the normal target description method to make the SPE upper | |
6564 | halves anonymous. */ | |
6565 | set_gdbarch_register_name (gdbarch, rs6000_register_name); | |
6566 | ||
604c2f83 LM |
6567 | /* Choose register numbers for all supported pseudo-registers. */ |
6568 | tdep->ppc_ev0_regnum = -1; | |
6569 | tdep->ppc_dl0_regnum = -1; | |
6570 | tdep->ppc_vsr0_regnum = -1; | |
6571 | tdep->ppc_efpr0_regnum = -1; | |
9f643768 | 6572 | |
604c2f83 LM |
6573 | cur_reg = gdbarch_num_regs (gdbarch); |
6574 | ||
6575 | if (have_spe) | |
6576 | { | |
6577 | tdep->ppc_ev0_regnum = cur_reg; | |
6578 | cur_reg += 32; | |
6579 | } | |
6580 | if (have_dfp) | |
6581 | { | |
6582 | tdep->ppc_dl0_regnum = cur_reg; | |
6583 | cur_reg += 16; | |
6584 | } | |
6585 | if (have_vsx) | |
6586 | { | |
6587 | tdep->ppc_vsr0_regnum = cur_reg; | |
6588 | cur_reg += 64; | |
6589 | tdep->ppc_efpr0_regnum = cur_reg; | |
6590 | cur_reg += 32; | |
6591 | } | |
f949c649 | 6592 | |
604c2f83 LM |
6593 | gdb_assert (gdbarch_num_regs (gdbarch) |
6594 | + gdbarch_num_pseudo_regs (gdbarch) == cur_reg); | |
f949c649 | 6595 | |
debb1f09 JB |
6596 | /* Register the ravenscar_arch_ops. */ |
6597 | if (mach == bfd_mach_ppc_e500) | |
6598 | register_e500_ravenscar_ops (gdbarch); | |
6599 | else | |
6600 | register_ppc_ravenscar_ops (gdbarch); | |
6601 | ||
65b48a81 PB |
6602 | set_gdbarch_disassembler_options (gdbarch, &powerpc_disassembler_options); |
6603 | set_gdbarch_valid_disassembler_options (gdbarch, | |
6604 | disassembler_options_powerpc ()); | |
6605 | ||
7a78ae4e | 6606 | return gdbarch; |
c906108c SS |
6607 | } |
6608 | ||
7b112f9c | 6609 | static void |
8b164abb | 6610 | rs6000_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
7b112f9c | 6611 | { |
8b164abb | 6612 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7b112f9c JT |
6613 | |
6614 | if (tdep == NULL) | |
6615 | return; | |
6616 | ||
4be87837 | 6617 | /* FIXME: Dump gdbarch_tdep. */ |
7b112f9c JT |
6618 | } |
6619 | ||
55eddb0f DJ |
6620 | /* PowerPC-specific commands. */ |
6621 | ||
6622 | static void | |
981a3fb3 | 6623 | set_powerpc_command (const char *args, int from_tty) |
55eddb0f DJ |
6624 | { |
6625 | printf_unfiltered (_("\ | |
6626 | \"set powerpc\" must be followed by an appropriate subcommand.\n")); | |
6627 | help_list (setpowerpccmdlist, "set powerpc ", all_commands, gdb_stdout); | |
6628 | } | |
6629 | ||
6630 | static void | |
981a3fb3 | 6631 | show_powerpc_command (const char *args, int from_tty) |
55eddb0f DJ |
6632 | { |
6633 | cmd_show_list (showpowerpccmdlist, from_tty, ""); | |
6634 | } | |
6635 | ||
6636 | static void | |
eb4c3f4a | 6637 | powerpc_set_soft_float (const char *args, int from_tty, |
55eddb0f DJ |
6638 | struct cmd_list_element *c) |
6639 | { | |
6640 | struct gdbarch_info info; | |
6641 | ||
6642 | /* Update the architecture. */ | |
6643 | gdbarch_info_init (&info); | |
6644 | if (!gdbarch_update_p (info)) | |
9b20d036 | 6645 | internal_error (__FILE__, __LINE__, _("could not update architecture")); |
55eddb0f DJ |
6646 | } |
6647 | ||
6648 | static void | |
eb4c3f4a | 6649 | powerpc_set_vector_abi (const char *args, int from_tty, |
55eddb0f DJ |
6650 | struct cmd_list_element *c) |
6651 | { | |
6652 | struct gdbarch_info info; | |
570dc176 | 6653 | int vector_abi; |
55eddb0f DJ |
6654 | |
6655 | for (vector_abi = POWERPC_VEC_AUTO; | |
6656 | vector_abi != POWERPC_VEC_LAST; | |
6657 | vector_abi++) | |
6658 | if (strcmp (powerpc_vector_abi_string, | |
6659 | powerpc_vector_strings[vector_abi]) == 0) | |
6660 | { | |
aead7601 | 6661 | powerpc_vector_abi_global = (enum powerpc_vector_abi) vector_abi; |
55eddb0f DJ |
6662 | break; |
6663 | } | |
6664 | ||
6665 | if (vector_abi == POWERPC_VEC_LAST) | |
6666 | internal_error (__FILE__, __LINE__, _("Invalid vector ABI accepted: %s."), | |
6667 | powerpc_vector_abi_string); | |
6668 | ||
6669 | /* Update the architecture. */ | |
6670 | gdbarch_info_init (&info); | |
6671 | if (!gdbarch_update_p (info)) | |
9b20d036 | 6672 | internal_error (__FILE__, __LINE__, _("could not update architecture")); |
55eddb0f DJ |
6673 | } |
6674 | ||
e09342b5 TJB |
6675 | /* Show the current setting of the exact watchpoints flag. */ |
6676 | ||
6677 | static void | |
6678 | show_powerpc_exact_watchpoints (struct ui_file *file, int from_tty, | |
6679 | struct cmd_list_element *c, | |
6680 | const char *value) | |
6681 | { | |
6682 | fprintf_filtered (file, _("Use of exact watchpoints is %s.\n"), value); | |
6683 | } | |
6684 | ||
845d4708 | 6685 | /* Read a PPC instruction from memory. */ |
d78489bf AT |
6686 | |
6687 | static unsigned int | |
845d4708 | 6688 | read_insn (struct frame_info *frame, CORE_ADDR pc) |
d78489bf | 6689 | { |
845d4708 AM |
6690 | struct gdbarch *gdbarch = get_frame_arch (frame); |
6691 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
6692 | ||
6693 | return read_memory_unsigned_integer (pc, 4, byte_order); | |
d78489bf AT |
6694 | } |
6695 | ||
6696 | /* Return non-zero if the instructions at PC match the series | |
6697 | described in PATTERN, or zero otherwise. PATTERN is an array of | |
6698 | 'struct ppc_insn_pattern' objects, terminated by an entry whose | |
6699 | mask is zero. | |
6700 | ||
6701 | When the match is successful, fill INSN[i] with what PATTERN[i] | |
6702 | matched. If PATTERN[i] is optional, and the instruction wasn't | |
6703 | present, set INSN[i] to 0 (which is not a valid PPC instruction). | |
6704 | INSN should have as many elements as PATTERN. Note that, if | |
6705 | PATTERN contains optional instructions which aren't present in | |
6706 | memory, then INSN will have holes, so INSN[i] isn't necessarily the | |
6707 | i'th instruction in memory. */ | |
6708 | ||
6709 | int | |
845d4708 AM |
6710 | ppc_insns_match_pattern (struct frame_info *frame, CORE_ADDR pc, |
6711 | struct ppc_insn_pattern *pattern, | |
6712 | unsigned int *insns) | |
d78489bf AT |
6713 | { |
6714 | int i; | |
845d4708 | 6715 | unsigned int insn; |
d78489bf | 6716 | |
845d4708 | 6717 | for (i = 0, insn = 0; pattern[i].mask; i++) |
d78489bf | 6718 | { |
845d4708 AM |
6719 | if (insn == 0) |
6720 | insn = read_insn (frame, pc); | |
6721 | insns[i] = 0; | |
6722 | if ((insn & pattern[i].mask) == pattern[i].data) | |
6723 | { | |
6724 | insns[i] = insn; | |
6725 | pc += 4; | |
6726 | insn = 0; | |
6727 | } | |
6728 | else if (!pattern[i].optional) | |
d78489bf AT |
6729 | return 0; |
6730 | } | |
6731 | ||
6732 | return 1; | |
6733 | } | |
6734 | ||
6735 | /* Return the 'd' field of the d-form instruction INSN, properly | |
6736 | sign-extended. */ | |
6737 | ||
6738 | CORE_ADDR | |
6739 | ppc_insn_d_field (unsigned int insn) | |
6740 | { | |
6741 | return ((((CORE_ADDR) insn & 0xffff) ^ 0x8000) - 0x8000); | |
6742 | } | |
6743 | ||
6744 | /* Return the 'ds' field of the ds-form instruction INSN, with the two | |
6745 | zero bits concatenated at the right, and properly | |
6746 | sign-extended. */ | |
6747 | ||
6748 | CORE_ADDR | |
6749 | ppc_insn_ds_field (unsigned int insn) | |
6750 | { | |
6751 | return ((((CORE_ADDR) insn & 0xfffc) ^ 0x8000) - 0x8000); | |
6752 | } | |
6753 | ||
c906108c SS |
6754 | /* Initialization code. */ |
6755 | ||
6756 | void | |
fba45db2 | 6757 | _initialize_rs6000_tdep (void) |
c906108c | 6758 | { |
7b112f9c JT |
6759 | gdbarch_register (bfd_arch_rs6000, rs6000_gdbarch_init, rs6000_dump_tdep); |
6760 | gdbarch_register (bfd_arch_powerpc, rs6000_gdbarch_init, rs6000_dump_tdep); | |
7cc46491 DJ |
6761 | |
6762 | /* Initialize the standard target descriptions. */ | |
6763 | initialize_tdesc_powerpc_32 (); | |
7284e1be | 6764 | initialize_tdesc_powerpc_altivec32 (); |
604c2f83 | 6765 | initialize_tdesc_powerpc_vsx32 (); |
7cc46491 DJ |
6766 | initialize_tdesc_powerpc_403 (); |
6767 | initialize_tdesc_powerpc_403gc (); | |
4d09ffea | 6768 | initialize_tdesc_powerpc_405 (); |
7cc46491 DJ |
6769 | initialize_tdesc_powerpc_505 (); |
6770 | initialize_tdesc_powerpc_601 (); | |
6771 | initialize_tdesc_powerpc_602 (); | |
6772 | initialize_tdesc_powerpc_603 (); | |
6773 | initialize_tdesc_powerpc_604 (); | |
6774 | initialize_tdesc_powerpc_64 (); | |
7284e1be | 6775 | initialize_tdesc_powerpc_altivec64 (); |
604c2f83 | 6776 | initialize_tdesc_powerpc_vsx64 (); |
7cc46491 DJ |
6777 | initialize_tdesc_powerpc_7400 (); |
6778 | initialize_tdesc_powerpc_750 (); | |
6779 | initialize_tdesc_powerpc_860 (); | |
6780 | initialize_tdesc_powerpc_e500 (); | |
6781 | initialize_tdesc_rs6000 (); | |
55eddb0f DJ |
6782 | |
6783 | /* Add root prefix command for all "set powerpc"/"show powerpc" | |
6784 | commands. */ | |
6785 | add_prefix_cmd ("powerpc", no_class, set_powerpc_command, | |
6786 | _("Various PowerPC-specific commands."), | |
6787 | &setpowerpccmdlist, "set powerpc ", 0, &setlist); | |
6788 | ||
6789 | add_prefix_cmd ("powerpc", no_class, show_powerpc_command, | |
6790 | _("Various PowerPC-specific commands."), | |
6791 | &showpowerpccmdlist, "show powerpc ", 0, &showlist); | |
6792 | ||
6793 | /* Add a command to allow the user to force the ABI. */ | |
6794 | add_setshow_auto_boolean_cmd ("soft-float", class_support, | |
6795 | &powerpc_soft_float_global, | |
6796 | _("Set whether to use a soft-float ABI."), | |
6797 | _("Show whether to use a soft-float ABI."), | |
6798 | NULL, | |
6799 | powerpc_set_soft_float, NULL, | |
6800 | &setpowerpccmdlist, &showpowerpccmdlist); | |
6801 | ||
6802 | add_setshow_enum_cmd ("vector-abi", class_support, powerpc_vector_strings, | |
6803 | &powerpc_vector_abi_string, | |
6804 | _("Set the vector ABI."), | |
6805 | _("Show the vector ABI."), | |
6806 | NULL, powerpc_set_vector_abi, NULL, | |
6807 | &setpowerpccmdlist, &showpowerpccmdlist); | |
e09342b5 TJB |
6808 | |
6809 | add_setshow_boolean_cmd ("exact-watchpoints", class_support, | |
6810 | &target_exact_watchpoints, | |
6811 | _("\ | |
6812 | Set whether to use just one debug register for watchpoints on scalars."), | |
6813 | _("\ | |
6814 | Show whether to use just one debug register for watchpoints on scalars."), | |
6815 | _("\ | |
6816 | If true, GDB will use only one debug register when watching a variable of\n\ | |
6817 | scalar type, thus assuming that the variable is accessed through the address\n\ | |
6818 | of its first byte."), | |
6819 | NULL, show_powerpc_exact_watchpoints, | |
6820 | &setpowerpccmdlist, &showpowerpccmdlist); | |
c906108c | 6821 | } |