Commit | Line | Data |
---|---|---|
c906108c | 1 | /* Target-dependent code for GDB, the GNU debugger. |
b6ba6518 | 2 | Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, |
1e698235 | 3 | 1998, 1999, 2000, 2001, 2002, 2003 |
c906108c SS |
4 | Free Software Foundation, Inc. |
5 | ||
c5aa993b | 6 | This file is part of GDB. |
c906108c | 7 | |
c5aa993b JM |
8 | This program is free software; you can redistribute it and/or modify |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2 of the License, or | |
11 | (at your option) any later version. | |
c906108c | 12 | |
c5aa993b JM |
13 | This program is distributed in the hope that it will be useful, |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
c906108c | 17 | |
c5aa993b JM |
18 | You should have received a copy of the GNU General Public License |
19 | along with this program; if not, write to the Free Software | |
20 | Foundation, Inc., 59 Temple Place - Suite 330, | |
21 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
22 | |
23 | #include "defs.h" | |
24 | #include "frame.h" | |
25 | #include "inferior.h" | |
26 | #include "symtab.h" | |
27 | #include "target.h" | |
28 | #include "gdbcore.h" | |
29 | #include "gdbcmd.h" | |
30 | #include "symfile.h" | |
31 | #include "objfiles.h" | |
7a78ae4e | 32 | #include "arch-utils.h" |
4e052eda | 33 | #include "regcache.h" |
d16aafd8 | 34 | #include "doublest.h" |
fd0407d6 | 35 | #include "value.h" |
1fcc0bb8 | 36 | #include "parser-defs.h" |
4be87837 | 37 | #include "osabi.h" |
7a78ae4e | 38 | |
2fccf04a | 39 | #include "libbfd.h" /* for bfd_default_set_arch_mach */ |
7a78ae4e | 40 | #include "coff/internal.h" /* for libcoff.h */ |
2fccf04a | 41 | #include "libcoff.h" /* for xcoff_data */ |
11ed25ac KB |
42 | #include "coff/xcoff.h" |
43 | #include "libxcoff.h" | |
7a78ae4e | 44 | |
9aa1e687 | 45 | #include "elf-bfd.h" |
7a78ae4e | 46 | |
6ded7999 | 47 | #include "solib-svr4.h" |
9aa1e687 | 48 | #include "ppc-tdep.h" |
7a78ae4e ND |
49 | |
50 | /* If the kernel has to deliver a signal, it pushes a sigcontext | |
51 | structure on the stack and then calls the signal handler, passing | |
52 | the address of the sigcontext in an argument register. Usually | |
53 | the signal handler doesn't save this register, so we have to | |
54 | access the sigcontext structure via an offset from the signal handler | |
55 | frame. | |
56 | The following constants were determined by experimentation on AIX 3.2. */ | |
57 | #define SIG_FRAME_PC_OFFSET 96 | |
58 | #define SIG_FRAME_LR_OFFSET 108 | |
59 | #define SIG_FRAME_FP_OFFSET 284 | |
60 | ||
7a78ae4e ND |
61 | /* To be used by skip_prologue. */ |
62 | ||
63 | struct rs6000_framedata | |
64 | { | |
65 | int offset; /* total size of frame --- the distance | |
66 | by which we decrement sp to allocate | |
67 | the frame */ | |
68 | int saved_gpr; /* smallest # of saved gpr */ | |
69 | int saved_fpr; /* smallest # of saved fpr */ | |
6be8bc0c | 70 | int saved_vr; /* smallest # of saved vr */ |
96ff0de4 | 71 | int saved_ev; /* smallest # of saved ev */ |
7a78ae4e ND |
72 | int alloca_reg; /* alloca register number (frame ptr) */ |
73 | char frameless; /* true if frameless functions. */ | |
74 | char nosavedpc; /* true if pc not saved. */ | |
75 | int gpr_offset; /* offset of saved gprs from prev sp */ | |
76 | int fpr_offset; /* offset of saved fprs from prev sp */ | |
6be8bc0c | 77 | int vr_offset; /* offset of saved vrs from prev sp */ |
96ff0de4 | 78 | int ev_offset; /* offset of saved evs from prev sp */ |
7a78ae4e ND |
79 | int lr_offset; /* offset of saved lr */ |
80 | int cr_offset; /* offset of saved cr */ | |
6be8bc0c | 81 | int vrsave_offset; /* offset of saved vrsave register */ |
7a78ae4e ND |
82 | }; |
83 | ||
84 | /* Description of a single register. */ | |
85 | ||
86 | struct reg | |
87 | { | |
88 | char *name; /* name of register */ | |
89 | unsigned char sz32; /* size on 32-bit arch, 0 if nonextant */ | |
90 | unsigned char sz64; /* size on 64-bit arch, 0 if nonextant */ | |
91 | unsigned char fpr; /* whether register is floating-point */ | |
489461e2 | 92 | unsigned char pseudo; /* whether register is pseudo */ |
7a78ae4e ND |
93 | }; |
94 | ||
c906108c SS |
95 | /* Breakpoint shadows for the single step instructions will be kept here. */ |
96 | ||
c5aa993b JM |
97 | static struct sstep_breaks |
98 | { | |
99 | /* Address, or 0 if this is not in use. */ | |
100 | CORE_ADDR address; | |
101 | /* Shadow contents. */ | |
102 | char data[4]; | |
103 | } | |
104 | stepBreaks[2]; | |
c906108c SS |
105 | |
106 | /* Hook for determining the TOC address when calling functions in the | |
107 | inferior under AIX. The initialization code in rs6000-nat.c sets | |
108 | this hook to point to find_toc_address. */ | |
109 | ||
7a78ae4e ND |
110 | CORE_ADDR (*rs6000_find_toc_address_hook) (CORE_ADDR) = NULL; |
111 | ||
112 | /* Hook to set the current architecture when starting a child process. | |
113 | rs6000-nat.c sets this. */ | |
114 | ||
115 | void (*rs6000_set_host_arch_hook) (int) = NULL; | |
c906108c SS |
116 | |
117 | /* Static function prototypes */ | |
118 | ||
a14ed312 KB |
119 | static CORE_ADDR branch_dest (int opcode, int instr, CORE_ADDR pc, |
120 | CORE_ADDR safety); | |
077276e8 KB |
121 | static CORE_ADDR skip_prologue (CORE_ADDR, CORE_ADDR, |
122 | struct rs6000_framedata *); | |
7a78ae4e ND |
123 | static void frame_get_saved_regs (struct frame_info * fi, |
124 | struct rs6000_framedata * fdatap); | |
125 | static CORE_ADDR frame_initial_stack_address (struct frame_info *); | |
c906108c | 126 | |
64b84175 KB |
127 | /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */ |
128 | int | |
129 | altivec_register_p (int regno) | |
130 | { | |
131 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
132 | if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0) | |
133 | return 0; | |
134 | else | |
135 | return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum); | |
136 | } | |
137 | ||
7a78ae4e | 138 | /* Read a LEN-byte address from debugged memory address MEMADDR. */ |
c906108c | 139 | |
7a78ae4e ND |
140 | static CORE_ADDR |
141 | read_memory_addr (CORE_ADDR memaddr, int len) | |
142 | { | |
143 | return read_memory_unsigned_integer (memaddr, len); | |
144 | } | |
c906108c | 145 | |
7a78ae4e ND |
146 | static CORE_ADDR |
147 | rs6000_skip_prologue (CORE_ADDR pc) | |
b83266a0 SS |
148 | { |
149 | struct rs6000_framedata frame; | |
077276e8 | 150 | pc = skip_prologue (pc, 0, &frame); |
b83266a0 SS |
151 | return pc; |
152 | } | |
153 | ||
154 | ||
c906108c SS |
155 | /* Fill in fi->saved_regs */ |
156 | ||
157 | struct frame_extra_info | |
158 | { | |
159 | /* Functions calling alloca() change the value of the stack | |
160 | pointer. We need to use initial stack pointer (which is saved in | |
161 | r31 by gcc) in such cases. If a compiler emits traceback table, | |
162 | then we should use the alloca register specified in traceback | |
163 | table. FIXME. */ | |
c5aa993b | 164 | CORE_ADDR initial_sp; /* initial stack pointer. */ |
c906108c SS |
165 | }; |
166 | ||
9aa1e687 | 167 | void |
7a78ae4e | 168 | rs6000_init_extra_frame_info (int fromleaf, struct frame_info *fi) |
c906108c | 169 | { |
c9012c71 AC |
170 | struct frame_extra_info *extra_info = |
171 | frame_extra_info_zalloc (fi, sizeof (struct frame_extra_info)); | |
172 | extra_info->initial_sp = 0; | |
bdd78e62 AC |
173 | if (get_next_frame (fi) != NULL |
174 | && get_frame_pc (fi) < TEXT_SEGMENT_BASE) | |
7a292a7a | 175 | /* We're in get_prev_frame */ |
c906108c SS |
176 | /* and this is a special signal frame. */ |
177 | /* (fi->pc will be some low address in the kernel, */ | |
178 | /* to which the signal handler returns). */ | |
5a203e44 | 179 | deprecated_set_frame_type (fi, SIGTRAMP_FRAME); |
c906108c SS |
180 | } |
181 | ||
7a78ae4e ND |
182 | /* Put here the code to store, into a struct frame_saved_regs, |
183 | the addresses of the saved registers of frame described by FRAME_INFO. | |
184 | This includes special registers such as pc and fp saved in special | |
185 | ways in the stack frame. sp is even more special: | |
186 | the address we return for it IS the sp for the next frame. */ | |
c906108c | 187 | |
7a78ae4e ND |
188 | /* In this implementation for RS/6000, we do *not* save sp. I am |
189 | not sure if it will be needed. The following function takes care of gpr's | |
190 | and fpr's only. */ | |
191 | ||
9aa1e687 | 192 | void |
7a78ae4e | 193 | rs6000_frame_init_saved_regs (struct frame_info *fi) |
c906108c SS |
194 | { |
195 | frame_get_saved_regs (fi, NULL); | |
196 | } | |
197 | ||
7a78ae4e ND |
198 | static CORE_ADDR |
199 | rs6000_frame_args_address (struct frame_info *fi) | |
c906108c | 200 | { |
c9012c71 AC |
201 | struct frame_extra_info *extra_info = get_frame_extra_info (fi); |
202 | if (extra_info->initial_sp != 0) | |
203 | return extra_info->initial_sp; | |
c906108c SS |
204 | else |
205 | return frame_initial_stack_address (fi); | |
206 | } | |
207 | ||
7a78ae4e ND |
208 | /* Immediately after a function call, return the saved pc. |
209 | Can't go through the frames for this because on some machines | |
210 | the new frame is not set up until the new function executes | |
211 | some instructions. */ | |
212 | ||
213 | static CORE_ADDR | |
214 | rs6000_saved_pc_after_call (struct frame_info *fi) | |
215 | { | |
2188cbdd | 216 | return read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum); |
7a78ae4e | 217 | } |
c906108c SS |
218 | |
219 | /* Calculate the destination of a branch/jump. Return -1 if not a branch. */ | |
220 | ||
221 | static CORE_ADDR | |
7a78ae4e | 222 | branch_dest (int opcode, int instr, CORE_ADDR pc, CORE_ADDR safety) |
c906108c SS |
223 | { |
224 | CORE_ADDR dest; | |
225 | int immediate; | |
226 | int absolute; | |
227 | int ext_op; | |
228 | ||
229 | absolute = (int) ((instr >> 1) & 1); | |
230 | ||
c5aa993b JM |
231 | switch (opcode) |
232 | { | |
233 | case 18: | |
234 | immediate = ((instr & ~3) << 6) >> 6; /* br unconditional */ | |
235 | if (absolute) | |
236 | dest = immediate; | |
237 | else | |
238 | dest = pc + immediate; | |
239 | break; | |
240 | ||
241 | case 16: | |
242 | immediate = ((instr & ~3) << 16) >> 16; /* br conditional */ | |
243 | if (absolute) | |
244 | dest = immediate; | |
245 | else | |
246 | dest = pc + immediate; | |
247 | break; | |
248 | ||
249 | case 19: | |
250 | ext_op = (instr >> 1) & 0x3ff; | |
251 | ||
252 | if (ext_op == 16) /* br conditional register */ | |
253 | { | |
2188cbdd | 254 | dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum) & ~3; |
c5aa993b JM |
255 | |
256 | /* If we are about to return from a signal handler, dest is | |
257 | something like 0x3c90. The current frame is a signal handler | |
258 | caller frame, upon completion of the sigreturn system call | |
259 | execution will return to the saved PC in the frame. */ | |
260 | if (dest < TEXT_SEGMENT_BASE) | |
261 | { | |
262 | struct frame_info *fi; | |
263 | ||
264 | fi = get_current_frame (); | |
265 | if (fi != NULL) | |
8b36eed8 | 266 | dest = read_memory_addr (get_frame_base (fi) + SIG_FRAME_PC_OFFSET, |
21283beb | 267 | gdbarch_tdep (current_gdbarch)->wordsize); |
c5aa993b JM |
268 | } |
269 | } | |
270 | ||
271 | else if (ext_op == 528) /* br cond to count reg */ | |
272 | { | |
2188cbdd | 273 | dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_ctr_regnum) & ~3; |
c5aa993b JM |
274 | |
275 | /* If we are about to execute a system call, dest is something | |
276 | like 0x22fc or 0x3b00. Upon completion the system call | |
277 | will return to the address in the link register. */ | |
278 | if (dest < TEXT_SEGMENT_BASE) | |
2188cbdd | 279 | dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum) & ~3; |
c5aa993b JM |
280 | } |
281 | else | |
282 | return -1; | |
283 | break; | |
c906108c | 284 | |
c5aa993b JM |
285 | default: |
286 | return -1; | |
287 | } | |
c906108c SS |
288 | return (dest < TEXT_SEGMENT_BASE) ? safety : dest; |
289 | } | |
290 | ||
291 | ||
292 | /* Sequence of bytes for breakpoint instruction. */ | |
293 | ||
294 | #define BIG_BREAKPOINT { 0x7d, 0x82, 0x10, 0x08 } | |
295 | #define LITTLE_BREAKPOINT { 0x08, 0x10, 0x82, 0x7d } | |
296 | ||
f4f9705a | 297 | const static unsigned char * |
7a78ae4e | 298 | rs6000_breakpoint_from_pc (CORE_ADDR *bp_addr, int *bp_size) |
c906108c SS |
299 | { |
300 | static unsigned char big_breakpoint[] = BIG_BREAKPOINT; | |
301 | static unsigned char little_breakpoint[] = LITTLE_BREAKPOINT; | |
302 | *bp_size = 4; | |
d7449b42 | 303 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
304 | return big_breakpoint; |
305 | else | |
306 | return little_breakpoint; | |
307 | } | |
308 | ||
309 | ||
310 | /* AIX does not support PT_STEP. Simulate it. */ | |
311 | ||
312 | void | |
379d08a1 AC |
313 | rs6000_software_single_step (enum target_signal signal, |
314 | int insert_breakpoints_p) | |
c906108c | 315 | { |
7c40d541 KB |
316 | CORE_ADDR dummy; |
317 | int breakp_sz; | |
f4f9705a | 318 | const char *breakp = rs6000_breakpoint_from_pc (&dummy, &breakp_sz); |
c906108c SS |
319 | int ii, insn; |
320 | CORE_ADDR loc; | |
321 | CORE_ADDR breaks[2]; | |
322 | int opcode; | |
323 | ||
c5aa993b JM |
324 | if (insert_breakpoints_p) |
325 | { | |
c906108c | 326 | |
c5aa993b | 327 | loc = read_pc (); |
c906108c | 328 | |
c5aa993b | 329 | insn = read_memory_integer (loc, 4); |
c906108c | 330 | |
7c40d541 | 331 | breaks[0] = loc + breakp_sz; |
c5aa993b JM |
332 | opcode = insn >> 26; |
333 | breaks[1] = branch_dest (opcode, insn, loc, breaks[0]); | |
c906108c | 334 | |
c5aa993b JM |
335 | /* Don't put two breakpoints on the same address. */ |
336 | if (breaks[1] == breaks[0]) | |
337 | breaks[1] = -1; | |
c906108c | 338 | |
c5aa993b | 339 | stepBreaks[1].address = 0; |
c906108c | 340 | |
c5aa993b JM |
341 | for (ii = 0; ii < 2; ++ii) |
342 | { | |
c906108c | 343 | |
c5aa993b JM |
344 | /* ignore invalid breakpoint. */ |
345 | if (breaks[ii] == -1) | |
346 | continue; | |
7c40d541 | 347 | target_insert_breakpoint (breaks[ii], stepBreaks[ii].data); |
c5aa993b JM |
348 | stepBreaks[ii].address = breaks[ii]; |
349 | } | |
c906108c | 350 | |
c5aa993b JM |
351 | } |
352 | else | |
353 | { | |
c906108c | 354 | |
c5aa993b JM |
355 | /* remove step breakpoints. */ |
356 | for (ii = 0; ii < 2; ++ii) | |
357 | if (stepBreaks[ii].address != 0) | |
7c40d541 KB |
358 | target_remove_breakpoint (stepBreaks[ii].address, |
359 | stepBreaks[ii].data); | |
c5aa993b | 360 | } |
c906108c | 361 | errno = 0; /* FIXME, don't ignore errors! */ |
c5aa993b | 362 | /* What errors? {read,write}_memory call error(). */ |
c906108c SS |
363 | } |
364 | ||
365 | ||
366 | /* return pc value after skipping a function prologue and also return | |
367 | information about a function frame. | |
368 | ||
369 | in struct rs6000_framedata fdata: | |
c5aa993b JM |
370 | - frameless is TRUE, if function does not have a frame. |
371 | - nosavedpc is TRUE, if function does not save %pc value in its frame. | |
372 | - offset is the initial size of this stack frame --- the amount by | |
373 | which we decrement the sp to allocate the frame. | |
374 | - saved_gpr is the number of the first saved gpr. | |
375 | - saved_fpr is the number of the first saved fpr. | |
6be8bc0c | 376 | - saved_vr is the number of the first saved vr. |
96ff0de4 | 377 | - saved_ev is the number of the first saved ev. |
c5aa993b JM |
378 | - alloca_reg is the number of the register used for alloca() handling. |
379 | Otherwise -1. | |
380 | - gpr_offset is the offset of the first saved gpr from the previous frame. | |
381 | - fpr_offset is the offset of the first saved fpr from the previous frame. | |
6be8bc0c | 382 | - vr_offset is the offset of the first saved vr from the previous frame. |
96ff0de4 | 383 | - ev_offset is the offset of the first saved ev from the previous frame. |
c5aa993b JM |
384 | - lr_offset is the offset of the saved lr |
385 | - cr_offset is the offset of the saved cr | |
6be8bc0c | 386 | - vrsave_offset is the offset of the saved vrsave register |
c5aa993b | 387 | */ |
c906108c SS |
388 | |
389 | #define SIGNED_SHORT(x) \ | |
390 | ((sizeof (short) == 2) \ | |
391 | ? ((int)(short)(x)) \ | |
392 | : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000))) | |
393 | ||
394 | #define GET_SRC_REG(x) (((x) >> 21) & 0x1f) | |
395 | ||
55d05f3b KB |
396 | /* Limit the number of skipped non-prologue instructions, as the examining |
397 | of the prologue is expensive. */ | |
398 | static int max_skip_non_prologue_insns = 10; | |
399 | ||
400 | /* Given PC representing the starting address of a function, and | |
401 | LIM_PC which is the (sloppy) limit to which to scan when looking | |
402 | for a prologue, attempt to further refine this limit by using | |
403 | the line data in the symbol table. If successful, a better guess | |
404 | on where the prologue ends is returned, otherwise the previous | |
405 | value of lim_pc is returned. */ | |
406 | static CORE_ADDR | |
407 | refine_prologue_limit (CORE_ADDR pc, CORE_ADDR lim_pc) | |
408 | { | |
409 | struct symtab_and_line prologue_sal; | |
410 | ||
411 | prologue_sal = find_pc_line (pc, 0); | |
412 | if (prologue_sal.line != 0) | |
413 | { | |
414 | int i; | |
415 | CORE_ADDR addr = prologue_sal.end; | |
416 | ||
417 | /* Handle the case in which compiler's optimizer/scheduler | |
418 | has moved instructions into the prologue. We scan ahead | |
419 | in the function looking for address ranges whose corresponding | |
420 | line number is less than or equal to the first one that we | |
421 | found for the function. (It can be less than when the | |
422 | scheduler puts a body instruction before the first prologue | |
423 | instruction.) */ | |
424 | for (i = 2 * max_skip_non_prologue_insns; | |
425 | i > 0 && (lim_pc == 0 || addr < lim_pc); | |
426 | i--) | |
427 | { | |
428 | struct symtab_and_line sal; | |
429 | ||
430 | sal = find_pc_line (addr, 0); | |
431 | if (sal.line == 0) | |
432 | break; | |
433 | if (sal.line <= prologue_sal.line | |
434 | && sal.symtab == prologue_sal.symtab) | |
435 | { | |
436 | prologue_sal = sal; | |
437 | } | |
438 | addr = sal.end; | |
439 | } | |
440 | ||
441 | if (lim_pc == 0 || prologue_sal.end < lim_pc) | |
442 | lim_pc = prologue_sal.end; | |
443 | } | |
444 | return lim_pc; | |
445 | } | |
446 | ||
447 | ||
7a78ae4e | 448 | static CORE_ADDR |
077276e8 | 449 | skip_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct rs6000_framedata *fdata) |
c906108c SS |
450 | { |
451 | CORE_ADDR orig_pc = pc; | |
55d05f3b | 452 | CORE_ADDR last_prologue_pc = pc; |
6be8bc0c | 453 | CORE_ADDR li_found_pc = 0; |
c906108c SS |
454 | char buf[4]; |
455 | unsigned long op; | |
456 | long offset = 0; | |
6be8bc0c | 457 | long vr_saved_offset = 0; |
482ca3f5 KB |
458 | int lr_reg = -1; |
459 | int cr_reg = -1; | |
6be8bc0c | 460 | int vr_reg = -1; |
96ff0de4 EZ |
461 | int ev_reg = -1; |
462 | long ev_offset = 0; | |
6be8bc0c | 463 | int vrsave_reg = -1; |
c906108c SS |
464 | int reg; |
465 | int framep = 0; | |
466 | int minimal_toc_loaded = 0; | |
ddb20c56 | 467 | int prev_insn_was_prologue_insn = 1; |
55d05f3b | 468 | int num_skip_non_prologue_insns = 0; |
96ff0de4 | 469 | const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (current_gdbarch); |
6f99cb26 | 470 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
96ff0de4 | 471 | |
55d05f3b KB |
472 | /* Attempt to find the end of the prologue when no limit is specified. |
473 | Note that refine_prologue_limit() has been written so that it may | |
474 | be used to "refine" the limits of non-zero PC values too, but this | |
475 | is only safe if we 1) trust the line information provided by the | |
476 | compiler and 2) iterate enough to actually find the end of the | |
477 | prologue. | |
478 | ||
479 | It may become a good idea at some point (for both performance and | |
480 | accuracy) to unconditionally call refine_prologue_limit(). But, | |
481 | until we can make a clear determination that this is beneficial, | |
482 | we'll play it safe and only use it to obtain a limit when none | |
483 | has been specified. */ | |
484 | if (lim_pc == 0) | |
485 | lim_pc = refine_prologue_limit (pc, lim_pc); | |
c906108c | 486 | |
ddb20c56 | 487 | memset (fdata, 0, sizeof (struct rs6000_framedata)); |
c906108c SS |
488 | fdata->saved_gpr = -1; |
489 | fdata->saved_fpr = -1; | |
6be8bc0c | 490 | fdata->saved_vr = -1; |
96ff0de4 | 491 | fdata->saved_ev = -1; |
c906108c SS |
492 | fdata->alloca_reg = -1; |
493 | fdata->frameless = 1; | |
494 | fdata->nosavedpc = 1; | |
495 | ||
55d05f3b | 496 | for (;; pc += 4) |
c906108c | 497 | { |
ddb20c56 KB |
498 | /* Sometimes it isn't clear if an instruction is a prologue |
499 | instruction or not. When we encounter one of these ambiguous | |
500 | cases, we'll set prev_insn_was_prologue_insn to 0 (false). | |
501 | Otherwise, we'll assume that it really is a prologue instruction. */ | |
502 | if (prev_insn_was_prologue_insn) | |
503 | last_prologue_pc = pc; | |
55d05f3b KB |
504 | |
505 | /* Stop scanning if we've hit the limit. */ | |
506 | if (lim_pc != 0 && pc >= lim_pc) | |
507 | break; | |
508 | ||
ddb20c56 KB |
509 | prev_insn_was_prologue_insn = 1; |
510 | ||
55d05f3b | 511 | /* Fetch the instruction and convert it to an integer. */ |
ddb20c56 KB |
512 | if (target_read_memory (pc, buf, 4)) |
513 | break; | |
514 | op = extract_signed_integer (buf, 4); | |
c906108c | 515 | |
c5aa993b JM |
516 | if ((op & 0xfc1fffff) == 0x7c0802a6) |
517 | { /* mflr Rx */ | |
518 | lr_reg = (op & 0x03e00000) | 0x90010000; | |
519 | continue; | |
c906108c | 520 | |
c5aa993b JM |
521 | } |
522 | else if ((op & 0xfc1fffff) == 0x7c000026) | |
523 | { /* mfcr Rx */ | |
524 | cr_reg = (op & 0x03e00000) | 0x90010000; | |
525 | continue; | |
c906108c | 526 | |
c906108c | 527 | } |
c5aa993b JM |
528 | else if ((op & 0xfc1f0000) == 0xd8010000) |
529 | { /* stfd Rx,NUM(r1) */ | |
530 | reg = GET_SRC_REG (op); | |
531 | if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg) | |
532 | { | |
533 | fdata->saved_fpr = reg; | |
534 | fdata->fpr_offset = SIGNED_SHORT (op) + offset; | |
535 | } | |
536 | continue; | |
c906108c | 537 | |
c5aa993b JM |
538 | } |
539 | else if (((op & 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */ | |
7a78ae4e ND |
540 | (((op & 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */ |
541 | (op & 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */ | |
542 | (op & 0x03e00000) >= 0x01a00000)) /* rx >= r13 */ | |
c5aa993b JM |
543 | { |
544 | ||
545 | reg = GET_SRC_REG (op); | |
546 | if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg) | |
547 | { | |
548 | fdata->saved_gpr = reg; | |
7a78ae4e ND |
549 | if ((op & 0xfc1f0003) == 0xf8010000) |
550 | op = (op >> 1) << 1; | |
c5aa993b JM |
551 | fdata->gpr_offset = SIGNED_SHORT (op) + offset; |
552 | } | |
553 | continue; | |
c906108c | 554 | |
ddb20c56 KB |
555 | } |
556 | else if ((op & 0xffff0000) == 0x60000000) | |
557 | { | |
96ff0de4 | 558 | /* nop */ |
ddb20c56 KB |
559 | /* Allow nops in the prologue, but do not consider them to |
560 | be part of the prologue unless followed by other prologue | |
561 | instructions. */ | |
562 | prev_insn_was_prologue_insn = 0; | |
563 | continue; | |
564 | ||
c906108c | 565 | } |
c5aa993b JM |
566 | else if ((op & 0xffff0000) == 0x3c000000) |
567 | { /* addis 0,0,NUM, used | |
568 | for >= 32k frames */ | |
569 | fdata->offset = (op & 0x0000ffff) << 16; | |
570 | fdata->frameless = 0; | |
571 | continue; | |
572 | ||
573 | } | |
574 | else if ((op & 0xffff0000) == 0x60000000) | |
575 | { /* ori 0,0,NUM, 2nd ha | |
576 | lf of >= 32k frames */ | |
577 | fdata->offset |= (op & 0x0000ffff); | |
578 | fdata->frameless = 0; | |
579 | continue; | |
580 | ||
581 | } | |
482ca3f5 | 582 | else if (lr_reg != -1 && (op & 0xffff0000) == lr_reg) |
c5aa993b JM |
583 | { /* st Rx,NUM(r1) |
584 | where Rx == lr */ | |
585 | fdata->lr_offset = SIGNED_SHORT (op) + offset; | |
586 | fdata->nosavedpc = 0; | |
587 | lr_reg = 0; | |
588 | continue; | |
589 | ||
590 | } | |
482ca3f5 | 591 | else if (cr_reg != -1 && (op & 0xffff0000) == cr_reg) |
c5aa993b JM |
592 | { /* st Rx,NUM(r1) |
593 | where Rx == cr */ | |
594 | fdata->cr_offset = SIGNED_SHORT (op) + offset; | |
595 | cr_reg = 0; | |
596 | continue; | |
597 | ||
598 | } | |
599 | else if (op == 0x48000005) | |
600 | { /* bl .+4 used in | |
601 | -mrelocatable */ | |
602 | continue; | |
603 | ||
604 | } | |
605 | else if (op == 0x48000004) | |
606 | { /* b .+4 (xlc) */ | |
607 | break; | |
608 | ||
c5aa993b | 609 | } |
6be8bc0c EZ |
610 | else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used |
611 | in V.4 -mminimal-toc */ | |
c5aa993b JM |
612 | (op & 0xffff0000) == 0x3bde0000) |
613 | { /* addi 30,30,foo@l */ | |
614 | continue; | |
c906108c | 615 | |
c5aa993b JM |
616 | } |
617 | else if ((op & 0xfc000001) == 0x48000001) | |
618 | { /* bl foo, | |
619 | to save fprs??? */ | |
c906108c | 620 | |
c5aa993b | 621 | fdata->frameless = 0; |
6be8bc0c EZ |
622 | /* Don't skip over the subroutine call if it is not within |
623 | the first three instructions of the prologue. */ | |
c5aa993b JM |
624 | if ((pc - orig_pc) > 8) |
625 | break; | |
626 | ||
627 | op = read_memory_integer (pc + 4, 4); | |
628 | ||
6be8bc0c EZ |
629 | /* At this point, make sure this is not a trampoline |
630 | function (a function that simply calls another functions, | |
631 | and nothing else). If the next is not a nop, this branch | |
632 | was part of the function prologue. */ | |
c5aa993b JM |
633 | |
634 | if (op == 0x4def7b82 || op == 0) /* crorc 15, 15, 15 */ | |
635 | break; /* don't skip over | |
636 | this branch */ | |
637 | continue; | |
638 | ||
639 | /* update stack pointer */ | |
640 | } | |
7a78ae4e ND |
641 | else if ((op & 0xffff0000) == 0x94210000 || /* stu r1,NUM(r1) */ |
642 | (op & 0xffff0003) == 0xf8210001) /* stdu r1,NUM(r1) */ | |
643 | { | |
c5aa993b | 644 | fdata->frameless = 0; |
7a78ae4e ND |
645 | if ((op & 0xffff0003) == 0xf8210001) |
646 | op = (op >> 1) << 1; | |
c5aa993b JM |
647 | fdata->offset = SIGNED_SHORT (op); |
648 | offset = fdata->offset; | |
649 | continue; | |
650 | ||
651 | } | |
652 | else if (op == 0x7c21016e) | |
653 | { /* stwux 1,1,0 */ | |
654 | fdata->frameless = 0; | |
655 | offset = fdata->offset; | |
656 | continue; | |
657 | ||
658 | /* Load up minimal toc pointer */ | |
659 | } | |
660 | else if ((op >> 22) == 0x20f | |
661 | && !minimal_toc_loaded) | |
662 | { /* l r31,... or l r30,... */ | |
663 | minimal_toc_loaded = 1; | |
664 | continue; | |
665 | ||
f6077098 KB |
666 | /* move parameters from argument registers to local variable |
667 | registers */ | |
668 | } | |
669 | else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */ | |
670 | (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */ | |
671 | (((op >> 21) & 31) <= 10) && | |
96ff0de4 | 672 | ((long) ((op >> 16) & 31) >= fdata->saved_gpr)) /* Rx: local var reg */ |
f6077098 KB |
673 | { |
674 | continue; | |
675 | ||
c5aa993b JM |
676 | /* store parameters in stack */ |
677 | } | |
6be8bc0c | 678 | else if ((op & 0xfc1f0003) == 0xf8010000 || /* std rx,NUM(r1) */ |
c5aa993b | 679 | (op & 0xfc1f0000) == 0xd8010000 || /* stfd Rx,NUM(r1) */ |
7a78ae4e ND |
680 | (op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */ |
681 | { | |
c5aa993b | 682 | continue; |
c906108c | 683 | |
c5aa993b JM |
684 | /* store parameters in stack via frame pointer */ |
685 | } | |
686 | else if (framep && | |
687 | ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r1) */ | |
688 | (op & 0xfc1f0000) == 0xd81f0000 || /* stfd Rx,NUM(r1) */ | |
689 | (op & 0xfc1f0000) == 0xfc1f0000)) | |
690 | { /* frsp, fp?,NUM(r1) */ | |
691 | continue; | |
692 | ||
693 | /* Set up frame pointer */ | |
694 | } | |
695 | else if (op == 0x603f0000 /* oril r31, r1, 0x0 */ | |
696 | || op == 0x7c3f0b78) | |
697 | { /* mr r31, r1 */ | |
698 | fdata->frameless = 0; | |
699 | framep = 1; | |
6f99cb26 | 700 | fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31); |
c5aa993b JM |
701 | continue; |
702 | ||
703 | /* Another way to set up the frame pointer. */ | |
704 | } | |
705 | else if ((op & 0xfc1fffff) == 0x38010000) | |
706 | { /* addi rX, r1, 0x0 */ | |
707 | fdata->frameless = 0; | |
708 | framep = 1; | |
6f99cb26 AC |
709 | fdata->alloca_reg = (tdep->ppc_gp0_regnum |
710 | + ((op & ~0x38010000) >> 21)); | |
c5aa993b | 711 | continue; |
c5aa993b | 712 | } |
6be8bc0c EZ |
713 | /* AltiVec related instructions. */ |
714 | /* Store the vrsave register (spr 256) in another register for | |
715 | later manipulation, or load a register into the vrsave | |
716 | register. 2 instructions are used: mfvrsave and | |
717 | mtvrsave. They are shorthand notation for mfspr Rn, SPR256 | |
718 | and mtspr SPR256, Rn. */ | |
719 | /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110 | |
720 | mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */ | |
721 | else if ((op & 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */ | |
722 | { | |
723 | vrsave_reg = GET_SRC_REG (op); | |
724 | continue; | |
725 | } | |
726 | else if ((op & 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */ | |
727 | { | |
728 | continue; | |
729 | } | |
730 | /* Store the register where vrsave was saved to onto the stack: | |
731 | rS is the register where vrsave was stored in a previous | |
732 | instruction. */ | |
733 | /* 100100 sssss 00001 dddddddd dddddddd */ | |
734 | else if ((op & 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */ | |
735 | { | |
736 | if (vrsave_reg == GET_SRC_REG (op)) | |
737 | { | |
738 | fdata->vrsave_offset = SIGNED_SHORT (op) + offset; | |
739 | vrsave_reg = -1; | |
740 | } | |
741 | continue; | |
742 | } | |
743 | /* Compute the new value of vrsave, by modifying the register | |
744 | where vrsave was saved to. */ | |
745 | else if (((op & 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */ | |
746 | || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */ | |
747 | { | |
748 | continue; | |
749 | } | |
750 | /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first | |
751 | in a pair of insns to save the vector registers on the | |
752 | stack. */ | |
753 | /* 001110 00000 00000 iiii iiii iiii iiii */ | |
96ff0de4 EZ |
754 | /* 001110 01110 00000 iiii iiii iiii iiii */ |
755 | else if ((op & 0xffff0000) == 0x38000000 /* li r0, SIMM */ | |
756 | || (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */ | |
6be8bc0c EZ |
757 | { |
758 | li_found_pc = pc; | |
759 | vr_saved_offset = SIGNED_SHORT (op); | |
760 | } | |
761 | /* Store vector register S at (r31+r0) aligned to 16 bytes. */ | |
762 | /* 011111 sssss 11111 00000 00111001110 */ | |
763 | else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */ | |
764 | { | |
765 | if (pc == (li_found_pc + 4)) | |
766 | { | |
767 | vr_reg = GET_SRC_REG (op); | |
768 | /* If this is the first vector reg to be saved, or if | |
769 | it has a lower number than others previously seen, | |
770 | reupdate the frame info. */ | |
771 | if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg) | |
772 | { | |
773 | fdata->saved_vr = vr_reg; | |
774 | fdata->vr_offset = vr_saved_offset + offset; | |
775 | } | |
776 | vr_saved_offset = -1; | |
777 | vr_reg = -1; | |
778 | li_found_pc = 0; | |
779 | } | |
780 | } | |
781 | /* End AltiVec related instructions. */ | |
96ff0de4 EZ |
782 | |
783 | /* Start BookE related instructions. */ | |
784 | /* Store gen register S at (r31+uimm). | |
785 | Any register less than r13 is volatile, so we don't care. */ | |
786 | /* 000100 sssss 11111 iiiii 01100100001 */ | |
787 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
788 | && (op & 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */ | |
789 | { | |
790 | if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */ | |
791 | { | |
792 | unsigned int imm; | |
793 | ev_reg = GET_SRC_REG (op); | |
794 | imm = (op >> 11) & 0x1f; | |
795 | ev_offset = imm * 8; | |
796 | /* If this is the first vector reg to be saved, or if | |
797 | it has a lower number than others previously seen, | |
798 | reupdate the frame info. */ | |
799 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) | |
800 | { | |
801 | fdata->saved_ev = ev_reg; | |
802 | fdata->ev_offset = ev_offset + offset; | |
803 | } | |
804 | } | |
805 | continue; | |
806 | } | |
807 | /* Store gen register rS at (r1+rB). */ | |
808 | /* 000100 sssss 00001 bbbbb 01100100000 */ | |
809 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
810 | && (op & 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */ | |
811 | { | |
812 | if (pc == (li_found_pc + 4)) | |
813 | { | |
814 | ev_reg = GET_SRC_REG (op); | |
815 | /* If this is the first vector reg to be saved, or if | |
816 | it has a lower number than others previously seen, | |
817 | reupdate the frame info. */ | |
818 | /* We know the contents of rB from the previous instruction. */ | |
819 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) | |
820 | { | |
821 | fdata->saved_ev = ev_reg; | |
822 | fdata->ev_offset = vr_saved_offset + offset; | |
823 | } | |
824 | vr_saved_offset = -1; | |
825 | ev_reg = -1; | |
826 | li_found_pc = 0; | |
827 | } | |
828 | continue; | |
829 | } | |
830 | /* Store gen register r31 at (rA+uimm). */ | |
831 | /* 000100 11111 aaaaa iiiii 01100100001 */ | |
832 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
833 | && (op & 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */ | |
834 | { | |
835 | /* Wwe know that the source register is 31 already, but | |
836 | it can't hurt to compute it. */ | |
837 | ev_reg = GET_SRC_REG (op); | |
838 | ev_offset = ((op >> 11) & 0x1f) * 8; | |
839 | /* If this is the first vector reg to be saved, or if | |
840 | it has a lower number than others previously seen, | |
841 | reupdate the frame info. */ | |
842 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) | |
843 | { | |
844 | fdata->saved_ev = ev_reg; | |
845 | fdata->ev_offset = ev_offset + offset; | |
846 | } | |
847 | ||
848 | continue; | |
849 | } | |
850 | /* Store gen register S at (r31+r0). | |
851 | Store param on stack when offset from SP bigger than 4 bytes. */ | |
852 | /* 000100 sssss 11111 00000 01100100000 */ | |
853 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
854 | && (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */ | |
855 | { | |
856 | if (pc == (li_found_pc + 4)) | |
857 | { | |
858 | if ((op & 0x03e00000) >= 0x01a00000) | |
859 | { | |
860 | ev_reg = GET_SRC_REG (op); | |
861 | /* If this is the first vector reg to be saved, or if | |
862 | it has a lower number than others previously seen, | |
863 | reupdate the frame info. */ | |
864 | /* We know the contents of r0 from the previous | |
865 | instruction. */ | |
866 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) | |
867 | { | |
868 | fdata->saved_ev = ev_reg; | |
869 | fdata->ev_offset = vr_saved_offset + offset; | |
870 | } | |
871 | ev_reg = -1; | |
872 | } | |
873 | vr_saved_offset = -1; | |
874 | li_found_pc = 0; | |
875 | continue; | |
876 | } | |
877 | } | |
878 | /* End BookE related instructions. */ | |
879 | ||
c5aa993b JM |
880 | else |
881 | { | |
55d05f3b KB |
882 | /* Not a recognized prologue instruction. |
883 | Handle optimizer code motions into the prologue by continuing | |
884 | the search if we have no valid frame yet or if the return | |
885 | address is not yet saved in the frame. */ | |
886 | if (fdata->frameless == 0 | |
887 | && (lr_reg == -1 || fdata->nosavedpc == 0)) | |
888 | break; | |
889 | ||
890 | if (op == 0x4e800020 /* blr */ | |
891 | || op == 0x4e800420) /* bctr */ | |
892 | /* Do not scan past epilogue in frameless functions or | |
893 | trampolines. */ | |
894 | break; | |
895 | if ((op & 0xf4000000) == 0x40000000) /* bxx */ | |
64366f1c | 896 | /* Never skip branches. */ |
55d05f3b KB |
897 | break; |
898 | ||
899 | if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns) | |
900 | /* Do not scan too many insns, scanning insns is expensive with | |
901 | remote targets. */ | |
902 | break; | |
903 | ||
904 | /* Continue scanning. */ | |
905 | prev_insn_was_prologue_insn = 0; | |
906 | continue; | |
c5aa993b | 907 | } |
c906108c SS |
908 | } |
909 | ||
910 | #if 0 | |
911 | /* I have problems with skipping over __main() that I need to address | |
912 | * sometime. Previously, I used to use misc_function_vector which | |
913 | * didn't work as well as I wanted to be. -MGO */ | |
914 | ||
915 | /* If the first thing after skipping a prolog is a branch to a function, | |
916 | this might be a call to an initializer in main(), introduced by gcc2. | |
64366f1c | 917 | We'd like to skip over it as well. Fortunately, xlc does some extra |
c906108c | 918 | work before calling a function right after a prologue, thus we can |
64366f1c | 919 | single out such gcc2 behaviour. */ |
c906108c | 920 | |
c906108c | 921 | |
c5aa993b JM |
922 | if ((op & 0xfc000001) == 0x48000001) |
923 | { /* bl foo, an initializer function? */ | |
924 | op = read_memory_integer (pc + 4, 4); | |
925 | ||
926 | if (op == 0x4def7b82) | |
927 | { /* cror 0xf, 0xf, 0xf (nop) */ | |
c906108c | 928 | |
64366f1c EZ |
929 | /* Check and see if we are in main. If so, skip over this |
930 | initializer function as well. */ | |
c906108c | 931 | |
c5aa993b | 932 | tmp = find_pc_misc_function (pc); |
51cc5b07 | 933 | if (tmp >= 0 && STREQ (misc_function_vector[tmp].name, main_name ())) |
c5aa993b JM |
934 | return pc + 8; |
935 | } | |
c906108c | 936 | } |
c906108c | 937 | #endif /* 0 */ |
c5aa993b JM |
938 | |
939 | fdata->offset = -fdata->offset; | |
ddb20c56 | 940 | return last_prologue_pc; |
c906108c SS |
941 | } |
942 | ||
943 | ||
944 | /************************************************************************* | |
f6077098 | 945 | Support for creating pushing a dummy frame into the stack, and popping |
c906108c SS |
946 | frames, etc. |
947 | *************************************************************************/ | |
948 | ||
c906108c | 949 | |
64366f1c | 950 | /* Pop the innermost frame, go back to the caller. */ |
c5aa993b | 951 | |
c906108c | 952 | static void |
7a78ae4e | 953 | rs6000_pop_frame (void) |
c906108c | 954 | { |
470d5666 | 955 | CORE_ADDR pc, lr, sp, prev_sp, addr; /* %pc, %lr, %sp */ |
c906108c SS |
956 | struct rs6000_framedata fdata; |
957 | struct frame_info *frame = get_current_frame (); | |
470d5666 | 958 | int ii, wordsize; |
c906108c SS |
959 | |
960 | pc = read_pc (); | |
c193f6ac | 961 | sp = get_frame_base (frame); |
c906108c | 962 | |
bdd78e62 | 963 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), |
8b36eed8 AC |
964 | get_frame_base (frame), |
965 | get_frame_base (frame))) | |
c906108c | 966 | { |
7a78ae4e ND |
967 | generic_pop_dummy_frame (); |
968 | flush_cached_frames (); | |
969 | return; | |
c906108c SS |
970 | } |
971 | ||
972 | /* Make sure that all registers are valid. */ | |
73937e03 | 973 | deprecated_read_register_bytes (0, NULL, REGISTER_BYTES); |
c906108c | 974 | |
64366f1c | 975 | /* Figure out previous %pc value. If the function is frameless, it is |
c906108c | 976 | still in the link register, otherwise walk the frames and retrieve the |
64366f1c | 977 | saved %pc value in the previous frame. */ |
c906108c | 978 | |
bdd78e62 AC |
979 | addr = get_pc_function_start (get_frame_pc (frame)); |
980 | (void) skip_prologue (addr, get_frame_pc (frame), &fdata); | |
c906108c | 981 | |
21283beb | 982 | wordsize = gdbarch_tdep (current_gdbarch)->wordsize; |
c906108c SS |
983 | if (fdata.frameless) |
984 | prev_sp = sp; | |
985 | else | |
7a78ae4e | 986 | prev_sp = read_memory_addr (sp, wordsize); |
c906108c | 987 | if (fdata.lr_offset == 0) |
2188cbdd | 988 | lr = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum); |
c906108c | 989 | else |
7a78ae4e | 990 | lr = read_memory_addr (prev_sp + fdata.lr_offset, wordsize); |
c906108c SS |
991 | |
992 | /* reset %pc value. */ | |
993 | write_register (PC_REGNUM, lr); | |
994 | ||
64366f1c | 995 | /* reset register values if any was saved earlier. */ |
c906108c SS |
996 | |
997 | if (fdata.saved_gpr != -1) | |
998 | { | |
999 | addr = prev_sp + fdata.gpr_offset; | |
c5aa993b JM |
1000 | for (ii = fdata.saved_gpr; ii <= 31; ++ii) |
1001 | { | |
524d7c18 AC |
1002 | read_memory (addr, &deprecated_registers[REGISTER_BYTE (ii)], |
1003 | wordsize); | |
7a78ae4e | 1004 | addr += wordsize; |
c5aa993b | 1005 | } |
c906108c SS |
1006 | } |
1007 | ||
1008 | if (fdata.saved_fpr != -1) | |
1009 | { | |
1010 | addr = prev_sp + fdata.fpr_offset; | |
c5aa993b JM |
1011 | for (ii = fdata.saved_fpr; ii <= 31; ++ii) |
1012 | { | |
524d7c18 | 1013 | read_memory (addr, &deprecated_registers[REGISTER_BYTE (ii + FP0_REGNUM)], 8); |
c5aa993b JM |
1014 | addr += 8; |
1015 | } | |
c906108c SS |
1016 | } |
1017 | ||
1018 | write_register (SP_REGNUM, prev_sp); | |
1019 | target_store_registers (-1); | |
1020 | flush_cached_frames (); | |
1021 | } | |
1022 | ||
7a78ae4e | 1023 | /* Fixup the call sequence of a dummy function, with the real function |
64366f1c | 1024 | address. Its arguments will be passed by gdb. */ |
c906108c | 1025 | |
7a78ae4e ND |
1026 | static void |
1027 | rs6000_fix_call_dummy (char *dummyname, CORE_ADDR pc, CORE_ADDR fun, | |
ea7c478f | 1028 | int nargs, struct value **args, struct type *type, |
7a78ae4e | 1029 | int gcc_p) |
c906108c | 1030 | { |
c906108c SS |
1031 | int ii; |
1032 | CORE_ADDR target_addr; | |
1033 | ||
7a78ae4e | 1034 | if (rs6000_find_toc_address_hook != NULL) |
f6077098 | 1035 | { |
7a78ae4e | 1036 | CORE_ADDR tocvalue = (*rs6000_find_toc_address_hook) (fun); |
2188cbdd EZ |
1037 | write_register (gdbarch_tdep (current_gdbarch)->ppc_toc_regnum, |
1038 | tocvalue); | |
f6077098 | 1039 | } |
c906108c SS |
1040 | } |
1041 | ||
11269d7e AC |
1042 | /* All the ABI's require 16 byte alignment. */ |
1043 | static CORE_ADDR | |
1044 | rs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
1045 | { | |
1046 | return (addr & -16); | |
1047 | } | |
1048 | ||
7a78ae4e | 1049 | /* Pass the arguments in either registers, or in the stack. In RS/6000, |
c906108c SS |
1050 | the first eight words of the argument list (that might be less than |
1051 | eight parameters if some parameters occupy more than one word) are | |
7a78ae4e | 1052 | passed in r3..r10 registers. float and double parameters are |
64366f1c EZ |
1053 | passed in fpr's, in addition to that. Rest of the parameters if any |
1054 | are passed in user stack. There might be cases in which half of the | |
c906108c SS |
1055 | parameter is copied into registers, the other half is pushed into |
1056 | stack. | |
1057 | ||
7a78ae4e ND |
1058 | Stack must be aligned on 64-bit boundaries when synthesizing |
1059 | function calls. | |
1060 | ||
c906108c SS |
1061 | If the function is returning a structure, then the return address is passed |
1062 | in r3, then the first 7 words of the parameters can be passed in registers, | |
64366f1c | 1063 | starting from r4. */ |
c906108c | 1064 | |
7a78ae4e | 1065 | static CORE_ADDR |
ea7c478f | 1066 | rs6000_push_arguments (int nargs, struct value **args, CORE_ADDR sp, |
7a78ae4e | 1067 | int struct_return, CORE_ADDR struct_addr) |
c906108c SS |
1068 | { |
1069 | int ii; | |
1070 | int len = 0; | |
c5aa993b JM |
1071 | int argno; /* current argument number */ |
1072 | int argbytes; /* current argument byte */ | |
1073 | char tmp_buffer[50]; | |
1074 | int f_argno = 0; /* current floating point argno */ | |
21283beb | 1075 | int wordsize = gdbarch_tdep (current_gdbarch)->wordsize; |
c906108c | 1076 | |
ea7c478f | 1077 | struct value *arg = 0; |
c906108c SS |
1078 | struct type *type; |
1079 | ||
1080 | CORE_ADDR saved_sp; | |
1081 | ||
64366f1c EZ |
1082 | /* The first eight words of ther arguments are passed in registers. |
1083 | Copy them appropriately. | |
c906108c SS |
1084 | |
1085 | If the function is returning a `struct', then the first word (which | |
64366f1c | 1086 | will be passed in r3) is used for struct return address. In that |
c906108c | 1087 | case we should advance one word and start from r4 register to copy |
64366f1c | 1088 | parameters. */ |
c906108c | 1089 | |
c5aa993b | 1090 | ii = struct_return ? 1 : 0; |
c906108c SS |
1091 | |
1092 | /* | |
c5aa993b JM |
1093 | effectively indirect call... gcc does... |
1094 | ||
1095 | return_val example( float, int); | |
1096 | ||
1097 | eabi: | |
1098 | float in fp0, int in r3 | |
1099 | offset of stack on overflow 8/16 | |
1100 | for varargs, must go by type. | |
1101 | power open: | |
1102 | float in r3&r4, int in r5 | |
1103 | offset of stack on overflow different | |
1104 | both: | |
1105 | return in r3 or f0. If no float, must study how gcc emulates floats; | |
1106 | pay attention to arg promotion. | |
1107 | User may have to cast\args to handle promotion correctly | |
1108 | since gdb won't know if prototype supplied or not. | |
1109 | */ | |
c906108c | 1110 | |
c5aa993b JM |
1111 | for (argno = 0, argbytes = 0; argno < nargs && ii < 8; ++ii) |
1112 | { | |
f6077098 | 1113 | int reg_size = REGISTER_RAW_SIZE (ii + 3); |
c5aa993b JM |
1114 | |
1115 | arg = args[argno]; | |
1116 | type = check_typedef (VALUE_TYPE (arg)); | |
1117 | len = TYPE_LENGTH (type); | |
1118 | ||
1119 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
1120 | { | |
1121 | ||
64366f1c | 1122 | /* Floating point arguments are passed in fpr's, as well as gpr's. |
c5aa993b | 1123 | There are 13 fpr's reserved for passing parameters. At this point |
64366f1c | 1124 | there is no way we would run out of them. */ |
c5aa993b JM |
1125 | |
1126 | if (len > 8) | |
1127 | printf_unfiltered ( | |
1128 | "Fatal Error: a floating point parameter #%d with a size > 8 is found!\n", argno); | |
1129 | ||
524d7c18 | 1130 | memcpy (&deprecated_registers[REGISTER_BYTE (FP0_REGNUM + 1 + f_argno)], |
c5aa993b JM |
1131 | VALUE_CONTENTS (arg), |
1132 | len); | |
1133 | ++f_argno; | |
1134 | } | |
1135 | ||
f6077098 | 1136 | if (len > reg_size) |
c5aa993b JM |
1137 | { |
1138 | ||
64366f1c | 1139 | /* Argument takes more than one register. */ |
c5aa993b JM |
1140 | while (argbytes < len) |
1141 | { | |
524d7c18 AC |
1142 | memset (&deprecated_registers[REGISTER_BYTE (ii + 3)], 0, |
1143 | reg_size); | |
1144 | memcpy (&deprecated_registers[REGISTER_BYTE (ii + 3)], | |
c5aa993b | 1145 | ((char *) VALUE_CONTENTS (arg)) + argbytes, |
f6077098 KB |
1146 | (len - argbytes) > reg_size |
1147 | ? reg_size : len - argbytes); | |
1148 | ++ii, argbytes += reg_size; | |
c5aa993b JM |
1149 | |
1150 | if (ii >= 8) | |
1151 | goto ran_out_of_registers_for_arguments; | |
1152 | } | |
1153 | argbytes = 0; | |
1154 | --ii; | |
1155 | } | |
1156 | else | |
64366f1c EZ |
1157 | { |
1158 | /* Argument can fit in one register. No problem. */ | |
d7449b42 | 1159 | int adj = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? reg_size - len : 0; |
524d7c18 AC |
1160 | memset (&deprecated_registers[REGISTER_BYTE (ii + 3)], 0, reg_size); |
1161 | memcpy ((char *)&deprecated_registers[REGISTER_BYTE (ii + 3)] + adj, | |
f6077098 | 1162 | VALUE_CONTENTS (arg), len); |
c5aa993b JM |
1163 | } |
1164 | ++argno; | |
c906108c | 1165 | } |
c906108c SS |
1166 | |
1167 | ran_out_of_registers_for_arguments: | |
1168 | ||
7a78ae4e | 1169 | saved_sp = read_sp (); |
cc9836a8 | 1170 | |
64366f1c | 1171 | /* Location for 8 parameters are always reserved. */ |
7a78ae4e | 1172 | sp -= wordsize * 8; |
f6077098 | 1173 | |
64366f1c | 1174 | /* Another six words for back chain, TOC register, link register, etc. */ |
7a78ae4e | 1175 | sp -= wordsize * 6; |
f6077098 | 1176 | |
64366f1c | 1177 | /* Stack pointer must be quadword aligned. */ |
7a78ae4e | 1178 | sp &= -16; |
c906108c | 1179 | |
64366f1c EZ |
1180 | /* If there are more arguments, allocate space for them in |
1181 | the stack, then push them starting from the ninth one. */ | |
c906108c | 1182 | |
c5aa993b JM |
1183 | if ((argno < nargs) || argbytes) |
1184 | { | |
1185 | int space = 0, jj; | |
c906108c | 1186 | |
c5aa993b JM |
1187 | if (argbytes) |
1188 | { | |
1189 | space += ((len - argbytes + 3) & -4); | |
1190 | jj = argno + 1; | |
1191 | } | |
1192 | else | |
1193 | jj = argno; | |
c906108c | 1194 | |
c5aa993b JM |
1195 | for (; jj < nargs; ++jj) |
1196 | { | |
ea7c478f | 1197 | struct value *val = args[jj]; |
c5aa993b JM |
1198 | space += ((TYPE_LENGTH (VALUE_TYPE (val))) + 3) & -4; |
1199 | } | |
c906108c | 1200 | |
64366f1c | 1201 | /* Add location required for the rest of the parameters. */ |
f6077098 | 1202 | space = (space + 15) & -16; |
c5aa993b | 1203 | sp -= space; |
c906108c | 1204 | |
64366f1c EZ |
1205 | /* This is another instance we need to be concerned about |
1206 | securing our stack space. If we write anything underneath %sp | |
1207 | (r1), we might conflict with the kernel who thinks he is free | |
1208 | to use this area. So, update %sp first before doing anything | |
1209 | else. */ | |
c906108c | 1210 | |
c5aa993b | 1211 | write_register (SP_REGNUM, sp); |
c906108c | 1212 | |
64366f1c EZ |
1213 | /* If the last argument copied into the registers didn't fit there |
1214 | completely, push the rest of it into stack. */ | |
c906108c | 1215 | |
c5aa993b JM |
1216 | if (argbytes) |
1217 | { | |
1218 | write_memory (sp + 24 + (ii * 4), | |
1219 | ((char *) VALUE_CONTENTS (arg)) + argbytes, | |
1220 | len - argbytes); | |
1221 | ++argno; | |
1222 | ii += ((len - argbytes + 3) & -4) / 4; | |
1223 | } | |
c906108c | 1224 | |
64366f1c | 1225 | /* Push the rest of the arguments into stack. */ |
c5aa993b JM |
1226 | for (; argno < nargs; ++argno) |
1227 | { | |
c906108c | 1228 | |
c5aa993b JM |
1229 | arg = args[argno]; |
1230 | type = check_typedef (VALUE_TYPE (arg)); | |
1231 | len = TYPE_LENGTH (type); | |
c906108c SS |
1232 | |
1233 | ||
64366f1c EZ |
1234 | /* Float types should be passed in fpr's, as well as in the |
1235 | stack. */ | |
c5aa993b JM |
1236 | if (TYPE_CODE (type) == TYPE_CODE_FLT && f_argno < 13) |
1237 | { | |
c906108c | 1238 | |
c5aa993b JM |
1239 | if (len > 8) |
1240 | printf_unfiltered ( | |
1241 | "Fatal Error: a floating point parameter #%d with a size > 8 is found!\n", argno); | |
c906108c | 1242 | |
524d7c18 | 1243 | memcpy (&deprecated_registers[REGISTER_BYTE (FP0_REGNUM + 1 + f_argno)], |
c5aa993b JM |
1244 | VALUE_CONTENTS (arg), |
1245 | len); | |
1246 | ++f_argno; | |
1247 | } | |
c906108c | 1248 | |
c5aa993b JM |
1249 | write_memory (sp + 24 + (ii * 4), (char *) VALUE_CONTENTS (arg), len); |
1250 | ii += ((len + 3) & -4) / 4; | |
1251 | } | |
c906108c | 1252 | } |
c906108c | 1253 | else |
64366f1c | 1254 | /* Secure stack areas first, before doing anything else. */ |
c906108c SS |
1255 | write_register (SP_REGNUM, sp); |
1256 | ||
c906108c SS |
1257 | /* set back chain properly */ |
1258 | store_address (tmp_buffer, 4, saved_sp); | |
1259 | write_memory (sp, tmp_buffer, 4); | |
1260 | ||
1261 | target_store_registers (-1); | |
1262 | return sp; | |
1263 | } | |
c906108c SS |
1264 | |
1265 | /* Function: ppc_push_return_address (pc, sp) | |
64366f1c | 1266 | Set up the return address for the inferior function call. */ |
c906108c | 1267 | |
7a78ae4e ND |
1268 | static CORE_ADDR |
1269 | ppc_push_return_address (CORE_ADDR pc, CORE_ADDR sp) | |
c906108c | 1270 | { |
2188cbdd EZ |
1271 | write_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum, |
1272 | CALL_DUMMY_ADDRESS ()); | |
c906108c SS |
1273 | return sp; |
1274 | } | |
1275 | ||
7a78ae4e | 1276 | /* Extract a function return value of type TYPE from raw register array |
64366f1c | 1277 | REGBUF, and copy that return value into VALBUF in virtual format. */ |
96ff0de4 | 1278 | static void |
46d79c04 | 1279 | e500_extract_return_value (struct type *valtype, struct regcache *regbuf, void *valbuf) |
96ff0de4 EZ |
1280 | { |
1281 | int offset = 0; | |
1282 | int vallen = TYPE_LENGTH (valtype); | |
1283 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
1284 | ||
1285 | if (TYPE_CODE (valtype) == TYPE_CODE_ARRAY | |
1286 | && vallen == 8 | |
1287 | && TYPE_VECTOR (valtype)) | |
1288 | { | |
1289 | regcache_raw_read (regbuf, tdep->ppc_ev0_regnum + 3, valbuf); | |
1290 | } | |
1291 | else | |
1292 | { | |
1293 | /* Return value is copied starting from r3. Note that r3 for us | |
1294 | is a pseudo register. */ | |
1295 | int offset = 0; | |
1296 | int return_regnum = tdep->ppc_gp0_regnum + 3; | |
1297 | int reg_size = REGISTER_RAW_SIZE (return_regnum); | |
1298 | int reg_part_size; | |
1299 | char *val_buffer; | |
1300 | int copied = 0; | |
1301 | int i = 0; | |
1302 | ||
1303 | /* Compute where we will start storing the value from. */ | |
1304 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
1305 | { | |
1306 | if (vallen <= reg_size) | |
1307 | offset = reg_size - vallen; | |
1308 | else | |
1309 | offset = reg_size + (reg_size - vallen); | |
1310 | } | |
1311 | ||
1312 | /* How big does the local buffer need to be? */ | |
1313 | if (vallen <= reg_size) | |
1314 | val_buffer = alloca (reg_size); | |
1315 | else | |
1316 | val_buffer = alloca (vallen); | |
1317 | ||
1318 | /* Read all we need into our private buffer. We copy it in | |
1319 | chunks that are as long as one register, never shorter, even | |
1320 | if the value is smaller than the register. */ | |
1321 | while (copied < vallen) | |
1322 | { | |
1323 | reg_part_size = REGISTER_RAW_SIZE (return_regnum + i); | |
1324 | /* It is a pseudo/cooked register. */ | |
1325 | regcache_cooked_read (regbuf, return_regnum + i, | |
1326 | val_buffer + copied); | |
1327 | copied += reg_part_size; | |
1328 | i++; | |
1329 | } | |
1330 | /* Put the stuff in the return buffer. */ | |
1331 | memcpy (valbuf, val_buffer + offset, vallen); | |
1332 | } | |
1333 | } | |
c906108c | 1334 | |
7a78ae4e ND |
1335 | static void |
1336 | rs6000_extract_return_value (struct type *valtype, char *regbuf, char *valbuf) | |
c906108c SS |
1337 | { |
1338 | int offset = 0; | |
ace1378a | 1339 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c | 1340 | |
c5aa993b JM |
1341 | if (TYPE_CODE (valtype) == TYPE_CODE_FLT) |
1342 | { | |
c906108c | 1343 | |
c5aa993b JM |
1344 | double dd; |
1345 | float ff; | |
1346 | /* floats and doubles are returned in fpr1. fpr's have a size of 8 bytes. | |
1347 | We need to truncate the return value into float size (4 byte) if | |
64366f1c | 1348 | necessary. */ |
c906108c | 1349 | |
c5aa993b JM |
1350 | if (TYPE_LENGTH (valtype) > 4) /* this is a double */ |
1351 | memcpy (valbuf, | |
1352 | ®buf[REGISTER_BYTE (FP0_REGNUM + 1)], | |
1353 | TYPE_LENGTH (valtype)); | |
1354 | else | |
1355 | { /* float */ | |
1356 | memcpy (&dd, ®buf[REGISTER_BYTE (FP0_REGNUM + 1)], 8); | |
1357 | ff = (float) dd; | |
1358 | memcpy (valbuf, &ff, sizeof (float)); | |
1359 | } | |
1360 | } | |
ace1378a EZ |
1361 | else if (TYPE_CODE (valtype) == TYPE_CODE_ARRAY |
1362 | && TYPE_LENGTH (valtype) == 16 | |
1363 | && TYPE_VECTOR (valtype)) | |
1364 | { | |
1365 | memcpy (valbuf, regbuf + REGISTER_BYTE (tdep->ppc_vr0_regnum + 2), | |
1366 | TYPE_LENGTH (valtype)); | |
1367 | } | |
c5aa993b JM |
1368 | else |
1369 | { | |
1370 | /* return value is copied starting from r3. */ | |
d7449b42 | 1371 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
c5aa993b JM |
1372 | && TYPE_LENGTH (valtype) < REGISTER_RAW_SIZE (3)) |
1373 | offset = REGISTER_RAW_SIZE (3) - TYPE_LENGTH (valtype); | |
1374 | ||
1375 | memcpy (valbuf, | |
1376 | regbuf + REGISTER_BYTE (3) + offset, | |
c906108c | 1377 | TYPE_LENGTH (valtype)); |
c906108c | 1378 | } |
c906108c SS |
1379 | } |
1380 | ||
977adac5 ND |
1381 | /* Return whether handle_inferior_event() should proceed through code |
1382 | starting at PC in function NAME when stepping. | |
1383 | ||
1384 | The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to | |
1385 | handle memory references that are too distant to fit in instructions | |
1386 | generated by the compiler. For example, if 'foo' in the following | |
1387 | instruction: | |
1388 | ||
1389 | lwz r9,foo(r2) | |
1390 | ||
1391 | is greater than 32767, the linker might replace the lwz with a branch to | |
1392 | somewhere in @FIX1 that does the load in 2 instructions and then branches | |
1393 | back to where execution should continue. | |
1394 | ||
1395 | GDB should silently step over @FIX code, just like AIX dbx does. | |
1396 | Unfortunately, the linker uses the "b" instruction for the branches, | |
1397 | meaning that the link register doesn't get set. Therefore, GDB's usual | |
1398 | step_over_function() mechanism won't work. | |
1399 | ||
1400 | Instead, use the IN_SOLIB_RETURN_TRAMPOLINE and SKIP_TRAMPOLINE_CODE hooks | |
1401 | in handle_inferior_event() to skip past @FIX code. */ | |
1402 | ||
1403 | int | |
1404 | rs6000_in_solib_return_trampoline (CORE_ADDR pc, char *name) | |
1405 | { | |
1406 | return name && !strncmp (name, "@FIX", 4); | |
1407 | } | |
1408 | ||
1409 | /* Skip code that the user doesn't want to see when stepping: | |
1410 | ||
1411 | 1. Indirect function calls use a piece of trampoline code to do context | |
1412 | switching, i.e. to set the new TOC table. Skip such code if we are on | |
1413 | its first instruction (as when we have single-stepped to here). | |
1414 | ||
1415 | 2. Skip shared library trampoline code (which is different from | |
c906108c | 1416 | indirect function call trampolines). |
977adac5 ND |
1417 | |
1418 | 3. Skip bigtoc fixup code. | |
1419 | ||
c906108c | 1420 | Result is desired PC to step until, or NULL if we are not in |
977adac5 | 1421 | code that should be skipped. */ |
c906108c SS |
1422 | |
1423 | CORE_ADDR | |
7a78ae4e | 1424 | rs6000_skip_trampoline_code (CORE_ADDR pc) |
c906108c SS |
1425 | { |
1426 | register unsigned int ii, op; | |
977adac5 | 1427 | int rel; |
c906108c | 1428 | CORE_ADDR solib_target_pc; |
977adac5 | 1429 | struct minimal_symbol *msymbol; |
c906108c | 1430 | |
c5aa993b JM |
1431 | static unsigned trampoline_code[] = |
1432 | { | |
1433 | 0x800b0000, /* l r0,0x0(r11) */ | |
1434 | 0x90410014, /* st r2,0x14(r1) */ | |
1435 | 0x7c0903a6, /* mtctr r0 */ | |
1436 | 0x804b0004, /* l r2,0x4(r11) */ | |
1437 | 0x816b0008, /* l r11,0x8(r11) */ | |
1438 | 0x4e800420, /* bctr */ | |
1439 | 0x4e800020, /* br */ | |
1440 | 0 | |
c906108c SS |
1441 | }; |
1442 | ||
977adac5 ND |
1443 | /* Check for bigtoc fixup code. */ |
1444 | msymbol = lookup_minimal_symbol_by_pc (pc); | |
1445 | if (msymbol && rs6000_in_solib_return_trampoline (pc, SYMBOL_NAME (msymbol))) | |
1446 | { | |
1447 | /* Double-check that the third instruction from PC is relative "b". */ | |
1448 | op = read_memory_integer (pc + 8, 4); | |
1449 | if ((op & 0xfc000003) == 0x48000000) | |
1450 | { | |
1451 | /* Extract bits 6-29 as a signed 24-bit relative word address and | |
1452 | add it to the containing PC. */ | |
1453 | rel = ((int)(op << 6) >> 6); | |
1454 | return pc + 8 + rel; | |
1455 | } | |
1456 | } | |
1457 | ||
c906108c SS |
1458 | /* If pc is in a shared library trampoline, return its target. */ |
1459 | solib_target_pc = find_solib_trampoline_target (pc); | |
1460 | if (solib_target_pc) | |
1461 | return solib_target_pc; | |
1462 | ||
c5aa993b JM |
1463 | for (ii = 0; trampoline_code[ii]; ++ii) |
1464 | { | |
1465 | op = read_memory_integer (pc + (ii * 4), 4); | |
1466 | if (op != trampoline_code[ii]) | |
1467 | return 0; | |
1468 | } | |
1469 | ii = read_register (11); /* r11 holds destination addr */ | |
21283beb | 1470 | pc = read_memory_addr (ii, gdbarch_tdep (current_gdbarch)->wordsize); /* (r11) value */ |
c906108c SS |
1471 | return pc; |
1472 | } | |
1473 | ||
1474 | /* Determines whether the function FI has a frame on the stack or not. */ | |
1475 | ||
9aa1e687 | 1476 | int |
c877c8e6 | 1477 | rs6000_frameless_function_invocation (struct frame_info *fi) |
c906108c SS |
1478 | { |
1479 | CORE_ADDR func_start; | |
1480 | struct rs6000_framedata fdata; | |
1481 | ||
1482 | /* Don't even think about framelessness except on the innermost frame | |
1483 | or if the function was interrupted by a signal. */ | |
75e3c1f9 AC |
1484 | if (get_next_frame (fi) != NULL |
1485 | && !(get_frame_type (get_next_frame (fi)) == SIGTRAMP_FRAME)) | |
c906108c | 1486 | return 0; |
c5aa993b | 1487 | |
bdd78e62 | 1488 | func_start = get_pc_function_start (get_frame_pc (fi)); |
c906108c SS |
1489 | |
1490 | /* If we failed to find the start of the function, it is a mistake | |
64366f1c | 1491 | to inspect the instructions. */ |
c906108c SS |
1492 | |
1493 | if (!func_start) | |
1494 | { | |
1495 | /* A frame with a zero PC is usually created by dereferencing a NULL | |
c5aa993b | 1496 | function pointer, normally causing an immediate core dump of the |
64366f1c | 1497 | inferior. Mark function as frameless, as the inferior has no chance |
c5aa993b | 1498 | of setting up a stack frame. */ |
bdd78e62 | 1499 | if (get_frame_pc (fi) == 0) |
c906108c SS |
1500 | return 1; |
1501 | else | |
1502 | return 0; | |
1503 | } | |
1504 | ||
bdd78e62 | 1505 | (void) skip_prologue (func_start, get_frame_pc (fi), &fdata); |
c906108c SS |
1506 | return fdata.frameless; |
1507 | } | |
1508 | ||
64366f1c | 1509 | /* Return the PC saved in a frame. */ |
c906108c | 1510 | |
9aa1e687 | 1511 | CORE_ADDR |
c877c8e6 | 1512 | rs6000_frame_saved_pc (struct frame_info *fi) |
c906108c SS |
1513 | { |
1514 | CORE_ADDR func_start; | |
1515 | struct rs6000_framedata fdata; | |
21283beb | 1516 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
a88376a3 | 1517 | int wordsize = tdep->wordsize; |
c906108c | 1518 | |
5a203e44 | 1519 | if ((get_frame_type (fi) == SIGTRAMP_FRAME)) |
8b36eed8 AC |
1520 | return read_memory_addr (get_frame_base (fi) + SIG_FRAME_PC_OFFSET, |
1521 | wordsize); | |
c906108c | 1522 | |
bdd78e62 | 1523 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), |
8b36eed8 AC |
1524 | get_frame_base (fi), |
1525 | get_frame_base (fi))) | |
bdd78e62 | 1526 | return deprecated_read_register_dummy (get_frame_pc (fi), |
8b36eed8 | 1527 | get_frame_base (fi), PC_REGNUM); |
c906108c | 1528 | |
bdd78e62 | 1529 | func_start = get_pc_function_start (get_frame_pc (fi)); |
c906108c SS |
1530 | |
1531 | /* If we failed to find the start of the function, it is a mistake | |
64366f1c | 1532 | to inspect the instructions. */ |
c906108c SS |
1533 | if (!func_start) |
1534 | return 0; | |
1535 | ||
bdd78e62 | 1536 | (void) skip_prologue (func_start, get_frame_pc (fi), &fdata); |
c906108c | 1537 | |
75e3c1f9 | 1538 | if (fdata.lr_offset == 0 && get_next_frame (fi) != NULL) |
c906108c | 1539 | { |
75e3c1f9 | 1540 | if ((get_frame_type (get_next_frame (fi)) == SIGTRAMP_FRAME)) |
8b36eed8 AC |
1541 | return read_memory_addr ((get_frame_base (get_next_frame (fi)) |
1542 | + SIG_FRAME_LR_OFFSET), | |
7a78ae4e | 1543 | wordsize); |
bdd78e62 | 1544 | else if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (get_next_frame (fi)), 0, 0)) |
8b69000d AC |
1545 | /* The link register wasn't saved by this frame and the next |
1546 | (inner, newer) frame is a dummy. Get the link register | |
1547 | value by unwinding it from that [dummy] frame. */ | |
1548 | { | |
1549 | ULONGEST lr; | |
1550 | frame_unwind_unsigned_register (get_next_frame (fi), | |
1551 | tdep->ppc_lr_regnum, &lr); | |
1552 | return lr; | |
1553 | } | |
c906108c | 1554 | else |
a88376a3 | 1555 | return read_memory_addr (FRAME_CHAIN (fi) + tdep->lr_frame_offset, |
7a78ae4e | 1556 | wordsize); |
c906108c SS |
1557 | } |
1558 | ||
1559 | if (fdata.lr_offset == 0) | |
2188cbdd | 1560 | return read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum); |
c906108c | 1561 | |
7a78ae4e | 1562 | return read_memory_addr (FRAME_CHAIN (fi) + fdata.lr_offset, wordsize); |
c906108c SS |
1563 | } |
1564 | ||
1565 | /* If saved registers of frame FI are not known yet, read and cache them. | |
1566 | &FDATAP contains rs6000_framedata; TDATAP can be NULL, | |
1567 | in which case the framedata are read. */ | |
1568 | ||
1569 | static void | |
7a78ae4e | 1570 | frame_get_saved_regs (struct frame_info *fi, struct rs6000_framedata *fdatap) |
c906108c | 1571 | { |
c5aa993b | 1572 | CORE_ADDR frame_addr; |
c906108c | 1573 | struct rs6000_framedata work_fdata; |
6be8bc0c EZ |
1574 | struct gdbarch_tdep * tdep = gdbarch_tdep (current_gdbarch); |
1575 | int wordsize = tdep->wordsize; | |
c906108c | 1576 | |
c9012c71 | 1577 | if (get_frame_saved_regs (fi)) |
c906108c | 1578 | return; |
c5aa993b | 1579 | |
c906108c SS |
1580 | if (fdatap == NULL) |
1581 | { | |
1582 | fdatap = &work_fdata; | |
bdd78e62 AC |
1583 | (void) skip_prologue (get_pc_function_start (get_frame_pc (fi)), |
1584 | get_frame_pc (fi), fdatap); | |
c906108c SS |
1585 | } |
1586 | ||
1587 | frame_saved_regs_zalloc (fi); | |
1588 | ||
1589 | /* If there were any saved registers, figure out parent's stack | |
64366f1c | 1590 | pointer. */ |
c906108c | 1591 | /* The following is true only if the frame doesn't have a call to |
64366f1c | 1592 | alloca(), FIXME. */ |
c906108c | 1593 | |
6be8bc0c EZ |
1594 | if (fdatap->saved_fpr == 0 |
1595 | && fdatap->saved_gpr == 0 | |
1596 | && fdatap->saved_vr == 0 | |
96ff0de4 | 1597 | && fdatap->saved_ev == 0 |
6be8bc0c EZ |
1598 | && fdatap->lr_offset == 0 |
1599 | && fdatap->cr_offset == 0 | |
96ff0de4 EZ |
1600 | && fdatap->vr_offset == 0 |
1601 | && fdatap->ev_offset == 0) | |
c906108c | 1602 | frame_addr = 0; |
c906108c | 1603 | else |
bf75c8c1 AC |
1604 | /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most |
1605 | address of the current frame. Things might be easier if the | |
1606 | ->frame pointed to the outer-most address of the frame. In the | |
1607 | mean time, the address of the prev frame is used as the base | |
1608 | address of this frame. */ | |
1609 | frame_addr = FRAME_CHAIN (fi); | |
c5aa993b | 1610 | |
c906108c SS |
1611 | /* if != -1, fdatap->saved_fpr is the smallest number of saved_fpr. |
1612 | All fpr's from saved_fpr to fp31 are saved. */ | |
1613 | ||
1614 | if (fdatap->saved_fpr >= 0) | |
1615 | { | |
1616 | int i; | |
7a78ae4e | 1617 | CORE_ADDR fpr_addr = frame_addr + fdatap->fpr_offset; |
c906108c SS |
1618 | for (i = fdatap->saved_fpr; i < 32; i++) |
1619 | { | |
c9012c71 | 1620 | get_frame_saved_regs (fi)[FP0_REGNUM + i] = fpr_addr; |
7a78ae4e | 1621 | fpr_addr += 8; |
c906108c SS |
1622 | } |
1623 | } | |
1624 | ||
1625 | /* if != -1, fdatap->saved_gpr is the smallest number of saved_gpr. | |
1626 | All gpr's from saved_gpr to gpr31 are saved. */ | |
1627 | ||
1628 | if (fdatap->saved_gpr >= 0) | |
1629 | { | |
1630 | int i; | |
7a78ae4e | 1631 | CORE_ADDR gpr_addr = frame_addr + fdatap->gpr_offset; |
c906108c SS |
1632 | for (i = fdatap->saved_gpr; i < 32; i++) |
1633 | { | |
c9012c71 | 1634 | get_frame_saved_regs (fi)[i] = gpr_addr; |
7a78ae4e | 1635 | gpr_addr += wordsize; |
c906108c SS |
1636 | } |
1637 | } | |
1638 | ||
6be8bc0c EZ |
1639 | /* if != -1, fdatap->saved_vr is the smallest number of saved_vr. |
1640 | All vr's from saved_vr to vr31 are saved. */ | |
1641 | if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) | |
1642 | { | |
1643 | if (fdatap->saved_vr >= 0) | |
1644 | { | |
1645 | int i; | |
1646 | CORE_ADDR vr_addr = frame_addr + fdatap->vr_offset; | |
1647 | for (i = fdatap->saved_vr; i < 32; i++) | |
1648 | { | |
c9012c71 | 1649 | get_frame_saved_regs (fi)[tdep->ppc_vr0_regnum + i] = vr_addr; |
6be8bc0c EZ |
1650 | vr_addr += REGISTER_RAW_SIZE (tdep->ppc_vr0_regnum); |
1651 | } | |
1652 | } | |
1653 | } | |
1654 | ||
96ff0de4 EZ |
1655 | /* if != -1, fdatap->saved_ev is the smallest number of saved_ev. |
1656 | All vr's from saved_ev to ev31 are saved. ????? */ | |
1657 | if (tdep->ppc_ev0_regnum != -1 && tdep->ppc_ev31_regnum != -1) | |
1658 | { | |
1659 | if (fdatap->saved_ev >= 0) | |
1660 | { | |
1661 | int i; | |
1662 | CORE_ADDR ev_addr = frame_addr + fdatap->ev_offset; | |
1663 | for (i = fdatap->saved_ev; i < 32; i++) | |
1664 | { | |
c9012c71 AC |
1665 | get_frame_saved_regs (fi)[tdep->ppc_ev0_regnum + i] = ev_addr; |
1666 | get_frame_saved_regs (fi)[tdep->ppc_gp0_regnum + i] = ev_addr + 4; | |
96ff0de4 EZ |
1667 | ev_addr += REGISTER_RAW_SIZE (tdep->ppc_ev0_regnum); |
1668 | } | |
1669 | } | |
1670 | } | |
1671 | ||
c906108c SS |
1672 | /* If != 0, fdatap->cr_offset is the offset from the frame that holds |
1673 | the CR. */ | |
1674 | if (fdatap->cr_offset != 0) | |
c9012c71 | 1675 | get_frame_saved_regs (fi)[tdep->ppc_cr_regnum] = frame_addr + fdatap->cr_offset; |
c906108c SS |
1676 | |
1677 | /* If != 0, fdatap->lr_offset is the offset from the frame that holds | |
1678 | the LR. */ | |
1679 | if (fdatap->lr_offset != 0) | |
c9012c71 | 1680 | get_frame_saved_regs (fi)[tdep->ppc_lr_regnum] = frame_addr + fdatap->lr_offset; |
6be8bc0c EZ |
1681 | |
1682 | /* If != 0, fdatap->vrsave_offset is the offset from the frame that holds | |
1683 | the VRSAVE. */ | |
1684 | if (fdatap->vrsave_offset != 0) | |
c9012c71 | 1685 | get_frame_saved_regs (fi)[tdep->ppc_vrsave_regnum] = frame_addr + fdatap->vrsave_offset; |
c906108c SS |
1686 | } |
1687 | ||
1688 | /* Return the address of a frame. This is the inital %sp value when the frame | |
64366f1c EZ |
1689 | was first allocated. For functions calling alloca(), it might be saved in |
1690 | an alloca register. */ | |
c906108c SS |
1691 | |
1692 | static CORE_ADDR | |
7a78ae4e | 1693 | frame_initial_stack_address (struct frame_info *fi) |
c906108c SS |
1694 | { |
1695 | CORE_ADDR tmpaddr; | |
1696 | struct rs6000_framedata fdata; | |
1697 | struct frame_info *callee_fi; | |
1698 | ||
64366f1c EZ |
1699 | /* If the initial stack pointer (frame address) of this frame is known, |
1700 | just return it. */ | |
c906108c | 1701 | |
c9012c71 AC |
1702 | if (get_frame_extra_info (fi)->initial_sp) |
1703 | return get_frame_extra_info (fi)->initial_sp; | |
c906108c | 1704 | |
64366f1c | 1705 | /* Find out if this function is using an alloca register. */ |
c906108c | 1706 | |
bdd78e62 AC |
1707 | (void) skip_prologue (get_pc_function_start (get_frame_pc (fi)), |
1708 | get_frame_pc (fi), &fdata); | |
c906108c | 1709 | |
64366f1c EZ |
1710 | /* If saved registers of this frame are not known yet, read and |
1711 | cache them. */ | |
c906108c | 1712 | |
c9012c71 | 1713 | if (!get_frame_saved_regs (fi)) |
c906108c SS |
1714 | frame_get_saved_regs (fi, &fdata); |
1715 | ||
1716 | /* If no alloca register used, then fi->frame is the value of the %sp for | |
64366f1c | 1717 | this frame, and it is good enough. */ |
c906108c SS |
1718 | |
1719 | if (fdata.alloca_reg < 0) | |
1720 | { | |
c9012c71 AC |
1721 | get_frame_extra_info (fi)->initial_sp = get_frame_base (fi); |
1722 | return get_frame_extra_info (fi)->initial_sp; | |
c906108c SS |
1723 | } |
1724 | ||
953836b2 AC |
1725 | /* There is an alloca register, use its value, in the current frame, |
1726 | as the initial stack pointer. */ | |
1727 | { | |
1728 | char *tmpbuf = alloca (MAX_REGISTER_RAW_SIZE); | |
1729 | if (frame_register_read (fi, fdata.alloca_reg, tmpbuf)) | |
1730 | { | |
c9012c71 | 1731 | get_frame_extra_info (fi)->initial_sp |
953836b2 AC |
1732 | = extract_unsigned_integer (tmpbuf, |
1733 | REGISTER_RAW_SIZE (fdata.alloca_reg)); | |
1734 | } | |
1735 | else | |
1736 | /* NOTE: cagney/2002-04-17: At present the only time | |
1737 | frame_register_read will fail is when the register isn't | |
1738 | available. If that does happen, use the frame. */ | |
c9012c71 | 1739 | get_frame_extra_info (fi)->initial_sp = get_frame_base (fi); |
953836b2 | 1740 | } |
c9012c71 | 1741 | return get_frame_extra_info (fi)->initial_sp; |
c906108c SS |
1742 | } |
1743 | ||
7a78ae4e ND |
1744 | /* Describe the pointer in each stack frame to the previous stack frame |
1745 | (its caller). */ | |
1746 | ||
1747 | /* FRAME_CHAIN takes a frame's nominal address | |
64366f1c | 1748 | and produces the frame's chain-pointer. */ |
7a78ae4e ND |
1749 | |
1750 | /* In the case of the RS/6000, the frame's nominal address | |
1751 | is the address of a 4-byte word containing the calling frame's address. */ | |
1752 | ||
9aa1e687 | 1753 | CORE_ADDR |
7a78ae4e | 1754 | rs6000_frame_chain (struct frame_info *thisframe) |
c906108c | 1755 | { |
7a78ae4e | 1756 | CORE_ADDR fp, fpp, lr; |
21283beb | 1757 | int wordsize = gdbarch_tdep (current_gdbarch)->wordsize; |
c906108c | 1758 | |
bdd78e62 | 1759 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (thisframe), |
8b36eed8 AC |
1760 | get_frame_base (thisframe), |
1761 | get_frame_base (thisframe))) | |
9f3b7f07 AC |
1762 | /* A dummy frame always correctly chains back to the previous |
1763 | frame. */ | |
8b36eed8 | 1764 | return read_memory_addr (get_frame_base (thisframe), wordsize); |
c906108c | 1765 | |
bdd78e62 AC |
1766 | if (inside_entry_file (get_frame_pc (thisframe)) |
1767 | || get_frame_pc (thisframe) == entry_point_address ()) | |
c906108c SS |
1768 | return 0; |
1769 | ||
5a203e44 | 1770 | if ((get_frame_type (thisframe) == SIGTRAMP_FRAME)) |
8b36eed8 AC |
1771 | fp = read_memory_addr (get_frame_base (thisframe) + SIG_FRAME_FP_OFFSET, |
1772 | wordsize); | |
75e3c1f9 AC |
1773 | else if (get_next_frame (thisframe) != NULL |
1774 | && (get_frame_type (get_next_frame (thisframe)) == SIGTRAMP_FRAME) | |
c877c8e6 | 1775 | && FRAMELESS_FUNCTION_INVOCATION (thisframe)) |
c906108c SS |
1776 | /* A frameless function interrupted by a signal did not change the |
1777 | frame pointer. */ | |
c193f6ac | 1778 | fp = get_frame_base (thisframe); |
c906108c | 1779 | else |
8b36eed8 | 1780 | fp = read_memory_addr (get_frame_base (thisframe), wordsize); |
7a78ae4e ND |
1781 | return fp; |
1782 | } | |
1783 | ||
1784 | /* Return the size of register REG when words are WORDSIZE bytes long. If REG | |
64366f1c | 1785 | isn't available with that word size, return 0. */ |
7a78ae4e ND |
1786 | |
1787 | static int | |
1788 | regsize (const struct reg *reg, int wordsize) | |
1789 | { | |
1790 | return wordsize == 8 ? reg->sz64 : reg->sz32; | |
1791 | } | |
1792 | ||
1793 | /* Return the name of register number N, or null if no such register exists | |
64366f1c | 1794 | in the current architecture. */ |
7a78ae4e | 1795 | |
fa88f677 | 1796 | static const char * |
7a78ae4e ND |
1797 | rs6000_register_name (int n) |
1798 | { | |
21283beb | 1799 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
7a78ae4e ND |
1800 | const struct reg *reg = tdep->regs + n; |
1801 | ||
1802 | if (!regsize (reg, tdep->wordsize)) | |
1803 | return NULL; | |
1804 | return reg->name; | |
1805 | } | |
1806 | ||
1807 | /* Index within `registers' of the first byte of the space for | |
1808 | register N. */ | |
1809 | ||
1810 | static int | |
1811 | rs6000_register_byte (int n) | |
1812 | { | |
21283beb | 1813 | return gdbarch_tdep (current_gdbarch)->regoff[n]; |
7a78ae4e ND |
1814 | } |
1815 | ||
1816 | /* Return the number of bytes of storage in the actual machine representation | |
64366f1c | 1817 | for register N if that register is available, else return 0. */ |
7a78ae4e ND |
1818 | |
1819 | static int | |
1820 | rs6000_register_raw_size (int n) | |
1821 | { | |
21283beb | 1822 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
7a78ae4e ND |
1823 | const struct reg *reg = tdep->regs + n; |
1824 | return regsize (reg, tdep->wordsize); | |
1825 | } | |
1826 | ||
7a78ae4e ND |
1827 | /* Return the GDB type object for the "standard" data type |
1828 | of data in register N. */ | |
1829 | ||
1830 | static struct type * | |
fba45db2 | 1831 | rs6000_register_virtual_type (int n) |
7a78ae4e | 1832 | { |
21283beb | 1833 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
7a78ae4e ND |
1834 | const struct reg *reg = tdep->regs + n; |
1835 | ||
1fcc0bb8 EZ |
1836 | if (reg->fpr) |
1837 | return builtin_type_double; | |
1838 | else | |
1839 | { | |
1840 | int size = regsize (reg, tdep->wordsize); | |
1841 | switch (size) | |
1842 | { | |
1843 | case 8: | |
c8001721 EZ |
1844 | if (tdep->ppc_ev0_regnum <= n && n <= tdep->ppc_ev31_regnum) |
1845 | return builtin_type_vec64; | |
1846 | else | |
1847 | return builtin_type_int64; | |
1fcc0bb8 EZ |
1848 | break; |
1849 | case 16: | |
08cf96df | 1850 | return builtin_type_vec128; |
1fcc0bb8 EZ |
1851 | break; |
1852 | default: | |
1853 | return builtin_type_int32; | |
1854 | break; | |
1855 | } | |
1856 | } | |
7a78ae4e ND |
1857 | } |
1858 | ||
7a78ae4e ND |
1859 | /* Return whether register N requires conversion when moving from raw format |
1860 | to virtual format. | |
1861 | ||
1862 | The register format for RS/6000 floating point registers is always | |
64366f1c | 1863 | double, we need a conversion if the memory format is float. */ |
7a78ae4e ND |
1864 | |
1865 | static int | |
1866 | rs6000_register_convertible (int n) | |
1867 | { | |
21283beb | 1868 | const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + n; |
7a78ae4e ND |
1869 | return reg->fpr; |
1870 | } | |
1871 | ||
1872 | /* Convert data from raw format for register N in buffer FROM | |
64366f1c | 1873 | to virtual format with type TYPE in buffer TO. */ |
7a78ae4e ND |
1874 | |
1875 | static void | |
1876 | rs6000_register_convert_to_virtual (int n, struct type *type, | |
1877 | char *from, char *to) | |
1878 | { | |
1879 | if (TYPE_LENGTH (type) != REGISTER_RAW_SIZE (n)) | |
7a292a7a | 1880 | { |
7a78ae4e ND |
1881 | double val = extract_floating (from, REGISTER_RAW_SIZE (n)); |
1882 | store_floating (to, TYPE_LENGTH (type), val); | |
1883 | } | |
1884 | else | |
1885 | memcpy (to, from, REGISTER_RAW_SIZE (n)); | |
1886 | } | |
1887 | ||
1888 | /* Convert data from virtual format with type TYPE in buffer FROM | |
64366f1c | 1889 | to raw format for register N in buffer TO. */ |
7a292a7a | 1890 | |
7a78ae4e ND |
1891 | static void |
1892 | rs6000_register_convert_to_raw (struct type *type, int n, | |
1893 | char *from, char *to) | |
1894 | { | |
1895 | if (TYPE_LENGTH (type) != REGISTER_RAW_SIZE (n)) | |
1896 | { | |
1897 | double val = extract_floating (from, TYPE_LENGTH (type)); | |
1898 | store_floating (to, REGISTER_RAW_SIZE (n), val); | |
7a292a7a | 1899 | } |
7a78ae4e ND |
1900 | else |
1901 | memcpy (to, from, REGISTER_RAW_SIZE (n)); | |
1902 | } | |
c906108c | 1903 | |
c8001721 EZ |
1904 | static void |
1905 | e500_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
1906 | int reg_nr, void *buffer) | |
1907 | { | |
1908 | int base_regnum; | |
1909 | int offset = 0; | |
1910 | char *temp_buffer = (char*) alloca (MAX_REGISTER_RAW_SIZE); | |
1911 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1912 | ||
1913 | if (reg_nr >= tdep->ppc_gp0_regnum | |
1914 | && reg_nr <= tdep->ppc_gplast_regnum) | |
1915 | { | |
1916 | base_regnum = reg_nr - tdep->ppc_gp0_regnum + tdep->ppc_ev0_regnum; | |
1917 | ||
1918 | /* Build the value in the provided buffer. */ | |
1919 | /* Read the raw register of which this one is the lower portion. */ | |
1920 | regcache_raw_read (regcache, base_regnum, temp_buffer); | |
1921 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
1922 | offset = 4; | |
1923 | memcpy ((char *) buffer, temp_buffer + offset, 4); | |
1924 | } | |
1925 | } | |
1926 | ||
1927 | static void | |
1928 | e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
1929 | int reg_nr, const void *buffer) | |
1930 | { | |
1931 | int base_regnum; | |
1932 | int offset = 0; | |
1933 | char *temp_buffer = (char*) alloca (MAX_REGISTER_RAW_SIZE); | |
1934 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1935 | ||
1936 | if (reg_nr >= tdep->ppc_gp0_regnum | |
1937 | && reg_nr <= tdep->ppc_gplast_regnum) | |
1938 | { | |
1939 | base_regnum = reg_nr - tdep->ppc_gp0_regnum + tdep->ppc_ev0_regnum; | |
1940 | /* reg_nr is 32 bit here, and base_regnum is 64 bits. */ | |
1941 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
1942 | offset = 4; | |
1943 | ||
1944 | /* Let's read the value of the base register into a temporary | |
1945 | buffer, so that overwriting the last four bytes with the new | |
1946 | value of the pseudo will leave the upper 4 bytes unchanged. */ | |
1947 | regcache_raw_read (regcache, base_regnum, temp_buffer); | |
1948 | ||
1949 | /* Write as an 8 byte quantity. */ | |
1950 | memcpy (temp_buffer + offset, (char *) buffer, 4); | |
1951 | regcache_raw_write (regcache, base_regnum, temp_buffer); | |
1952 | } | |
1953 | } | |
1954 | ||
1955 | /* Convert a dwarf2 register number to a gdb REGNUM. */ | |
1956 | static int | |
1957 | e500_dwarf2_reg_to_regnum (int num) | |
1958 | { | |
1959 | int regnum; | |
1960 | if (0 <= num && num <= 31) | |
1961 | return num + gdbarch_tdep (current_gdbarch)->ppc_gp0_regnum; | |
1962 | else | |
1963 | return num; | |
1964 | } | |
1965 | ||
2188cbdd | 1966 | /* Convert a dbx stab register number (from `r' declaration) to a gdb |
64366f1c | 1967 | REGNUM. */ |
2188cbdd EZ |
1968 | static int |
1969 | rs6000_stab_reg_to_regnum (int num) | |
1970 | { | |
1971 | int regnum; | |
1972 | switch (num) | |
1973 | { | |
1974 | case 64: | |
1975 | regnum = gdbarch_tdep (current_gdbarch)->ppc_mq_regnum; | |
1976 | break; | |
1977 | case 65: | |
1978 | regnum = gdbarch_tdep (current_gdbarch)->ppc_lr_regnum; | |
1979 | break; | |
1980 | case 66: | |
1981 | regnum = gdbarch_tdep (current_gdbarch)->ppc_ctr_regnum; | |
1982 | break; | |
1983 | case 76: | |
1984 | regnum = gdbarch_tdep (current_gdbarch)->ppc_xer_regnum; | |
1985 | break; | |
1986 | default: | |
1987 | regnum = num; | |
1988 | break; | |
1989 | } | |
1990 | return regnum; | |
1991 | } | |
1992 | ||
7a78ae4e | 1993 | /* Store the address of the place in which to copy the structure the |
11269d7e | 1994 | subroutine will return. */ |
7a78ae4e ND |
1995 | |
1996 | static void | |
1997 | rs6000_store_struct_return (CORE_ADDR addr, CORE_ADDR sp) | |
1998 | { | |
da3eff49 AC |
1999 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2000 | write_register (tdep->ppc_gp0_regnum + 3, addr); | |
7a78ae4e ND |
2001 | } |
2002 | ||
2003 | /* Write into appropriate registers a function return value | |
2004 | of type TYPE, given in virtual format. */ | |
96ff0de4 EZ |
2005 | static void |
2006 | e500_store_return_value (struct type *type, char *valbuf) | |
2007 | { | |
2008 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2009 | ||
2010 | /* Everything is returned in GPR3 and up. */ | |
2011 | int copied = 0; | |
2012 | int i = 0; | |
2013 | int len = TYPE_LENGTH (type); | |
2014 | while (copied < len) | |
2015 | { | |
2016 | int regnum = gdbarch_tdep (current_gdbarch)->ppc_gp0_regnum + 3 + i; | |
2017 | int reg_size = REGISTER_RAW_SIZE (regnum); | |
2018 | char *reg_val_buf = alloca (reg_size); | |
2019 | ||
2020 | memcpy (reg_val_buf, valbuf + copied, reg_size); | |
2021 | copied += reg_size; | |
4caf0990 | 2022 | deprecated_write_register_gen (regnum, reg_val_buf); |
96ff0de4 EZ |
2023 | i++; |
2024 | } | |
2025 | } | |
7a78ae4e ND |
2026 | |
2027 | static void | |
2028 | rs6000_store_return_value (struct type *type, char *valbuf) | |
2029 | { | |
ace1378a EZ |
2030 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2031 | ||
7a78ae4e ND |
2032 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
2033 | ||
2034 | /* Floating point values are returned starting from FPR1 and up. | |
2035 | Say a double_double_double type could be returned in | |
64366f1c | 2036 | FPR1/FPR2/FPR3 triple. */ |
7a78ae4e | 2037 | |
73937e03 AC |
2038 | deprecated_write_register_bytes (REGISTER_BYTE (FP0_REGNUM + 1), valbuf, |
2039 | TYPE_LENGTH (type)); | |
ace1378a EZ |
2040 | else if (TYPE_CODE (type) == TYPE_CODE_ARRAY) |
2041 | { | |
2042 | if (TYPE_LENGTH (type) == 16 | |
2043 | && TYPE_VECTOR (type)) | |
73937e03 AC |
2044 | deprecated_write_register_bytes (REGISTER_BYTE (tdep->ppc_vr0_regnum + 2), |
2045 | valbuf, TYPE_LENGTH (type)); | |
ace1378a | 2046 | } |
7a78ae4e | 2047 | else |
64366f1c | 2048 | /* Everything else is returned in GPR3 and up. */ |
73937e03 AC |
2049 | deprecated_write_register_bytes (REGISTER_BYTE (gdbarch_tdep (current_gdbarch)->ppc_gp0_regnum + 3), |
2050 | valbuf, TYPE_LENGTH (type)); | |
7a78ae4e ND |
2051 | } |
2052 | ||
2053 | /* Extract from an array REGBUF containing the (raw) register state | |
2054 | the address in which a function should return its structure value, | |
2055 | as a CORE_ADDR (or an expression that can be used as one). */ | |
2056 | ||
2057 | static CORE_ADDR | |
11269d7e AC |
2058 | rs6000_extract_struct_value_address (struct regcache *regcache) |
2059 | { | |
2060 | /* FIXME: cagney/2002-09-26: PR gdb/724: When making an inferior | |
2061 | function call GDB knows the address of the struct return value | |
2062 | and hence, should not need to call this function. Unfortunately, | |
2063 | the current hand_function_call() code only saves the most recent | |
2064 | struct address leading to occasional calls. The code should | |
2065 | instead maintain a stack of such addresses (in the dummy frame | |
2066 | object). */ | |
2067 | /* NOTE: cagney/2002-09-26: Return 0 which indicates that we've | |
2068 | really got no idea where the return value is being stored. While | |
2069 | r3, on function entry, contained the address it will have since | |
2070 | been reused (scratch) and hence wouldn't be valid */ | |
2071 | return 0; | |
7a78ae4e ND |
2072 | } |
2073 | ||
2074 | /* Return whether PC is in a dummy function call. | |
2075 | ||
2076 | FIXME: This just checks for the end of the stack, which is broken | |
64366f1c | 2077 | for things like stepping through gcc nested function stubs. */ |
7a78ae4e ND |
2078 | |
2079 | static int | |
2080 | rs6000_pc_in_call_dummy (CORE_ADDR pc, CORE_ADDR sp, CORE_ADDR fp) | |
2081 | { | |
2082 | return sp < pc && pc < fp; | |
2083 | } | |
2084 | ||
64366f1c | 2085 | /* Hook called when a new child process is started. */ |
7a78ae4e ND |
2086 | |
2087 | void | |
2088 | rs6000_create_inferior (int pid) | |
2089 | { | |
2090 | if (rs6000_set_host_arch_hook) | |
2091 | rs6000_set_host_arch_hook (pid); | |
c906108c SS |
2092 | } |
2093 | \f | |
7a78ae4e ND |
2094 | /* Support for CONVERT_FROM_FUNC_PTR_ADDR(ADDR). |
2095 | ||
2096 | Usually a function pointer's representation is simply the address | |
2097 | of the function. On the RS/6000 however, a function pointer is | |
2098 | represented by a pointer to a TOC entry. This TOC entry contains | |
2099 | three words, the first word is the address of the function, the | |
2100 | second word is the TOC pointer (r2), and the third word is the | |
2101 | static chain value. Throughout GDB it is currently assumed that a | |
2102 | function pointer contains the address of the function, which is not | |
2103 | easy to fix. In addition, the conversion of a function address to | |
2104 | a function pointer would require allocation of a TOC entry in the | |
2105 | inferior's memory space, with all its drawbacks. To be able to | |
2106 | call C++ virtual methods in the inferior (which are called via | |
f517ea4e | 2107 | function pointers), find_function_addr uses this function to get the |
7a78ae4e ND |
2108 | function address from a function pointer. */ |
2109 | ||
f517ea4e PS |
2110 | /* Return real function address if ADDR (a function pointer) is in the data |
2111 | space and is therefore a special function pointer. */ | |
c906108c | 2112 | |
7a78ae4e ND |
2113 | CORE_ADDR |
2114 | rs6000_convert_from_func_ptr_addr (CORE_ADDR addr) | |
c906108c SS |
2115 | { |
2116 | struct obj_section *s; | |
2117 | ||
2118 | s = find_pc_section (addr); | |
2119 | if (s && s->the_bfd_section->flags & SEC_CODE) | |
7a78ae4e | 2120 | return addr; |
c906108c | 2121 | |
7a78ae4e | 2122 | /* ADDR is in the data space, so it's a special function pointer. */ |
21283beb | 2123 | return read_memory_addr (addr, gdbarch_tdep (current_gdbarch)->wordsize); |
c906108c | 2124 | } |
c906108c | 2125 | \f |
c5aa993b | 2126 | |
7a78ae4e | 2127 | /* Handling the various POWER/PowerPC variants. */ |
c906108c SS |
2128 | |
2129 | ||
7a78ae4e ND |
2130 | /* The arrays here called registers_MUMBLE hold information about available |
2131 | registers. | |
c906108c SS |
2132 | |
2133 | For each family of PPC variants, I've tried to isolate out the | |
2134 | common registers and put them up front, so that as long as you get | |
2135 | the general family right, GDB will correctly identify the registers | |
2136 | common to that family. The common register sets are: | |
2137 | ||
2138 | For the 60x family: hid0 hid1 iabr dabr pir | |
2139 | ||
2140 | For the 505 and 860 family: eie eid nri | |
2141 | ||
2142 | For the 403 and 403GC: icdbdr esr dear evpr cdbcr tsr tcr pit tbhi | |
c5aa993b JM |
2143 | tblo srr2 srr3 dbsr dbcr iac1 iac2 dac1 dac2 dccr iccr pbl1 |
2144 | pbu1 pbl2 pbu2 | |
c906108c SS |
2145 | |
2146 | Most of these register groups aren't anything formal. I arrived at | |
2147 | them by looking at the registers that occurred in more than one | |
6f5987a6 KB |
2148 | processor. |
2149 | ||
2150 | Note: kevinb/2002-04-30: Support for the fpscr register was added | |
2151 | during April, 2002. Slot 70 is being used for PowerPC and slot 71 | |
2152 | for Power. For PowerPC, slot 70 was unused and was already in the | |
2153 | PPC_UISA_SPRS which is ideally where fpscr should go. For Power, | |
2154 | slot 70 was being used for "mq", so the next available slot (71) | |
2155 | was chosen. It would have been nice to be able to make the | |
2156 | register numbers the same across processor cores, but this wasn't | |
2157 | possible without either 1) renumbering some registers for some | |
2158 | processors or 2) assigning fpscr to a really high slot that's | |
2159 | larger than any current register number. Doing (1) is bad because | |
2160 | existing stubs would break. Doing (2) is undesirable because it | |
2161 | would introduce a really large gap between fpscr and the rest of | |
2162 | the registers for most processors. */ | |
7a78ae4e | 2163 | |
64366f1c | 2164 | /* Convenience macros for populating register arrays. */ |
7a78ae4e | 2165 | |
64366f1c | 2166 | /* Within another macro, convert S to a string. */ |
7a78ae4e ND |
2167 | |
2168 | #define STR(s) #s | |
2169 | ||
2170 | /* Return a struct reg defining register NAME that's 32 bits on 32-bit systems | |
64366f1c | 2171 | and 64 bits on 64-bit systems. */ |
489461e2 | 2172 | #define R(name) { STR(name), 4, 8, 0, 0 } |
7a78ae4e ND |
2173 | |
2174 | /* Return a struct reg defining register NAME that's 32 bits on all | |
64366f1c | 2175 | systems. */ |
489461e2 | 2176 | #define R4(name) { STR(name), 4, 4, 0, 0 } |
7a78ae4e ND |
2177 | |
2178 | /* Return a struct reg defining register NAME that's 64 bits on all | |
64366f1c | 2179 | systems. */ |
489461e2 | 2180 | #define R8(name) { STR(name), 8, 8, 0, 0 } |
7a78ae4e | 2181 | |
1fcc0bb8 | 2182 | /* Return a struct reg defining register NAME that's 128 bits on all |
64366f1c | 2183 | systems. */ |
489461e2 | 2184 | #define R16(name) { STR(name), 16, 16, 0, 0 } |
1fcc0bb8 | 2185 | |
64366f1c | 2186 | /* Return a struct reg defining floating-point register NAME. */ |
489461e2 EZ |
2187 | #define F(name) { STR(name), 8, 8, 1, 0 } |
2188 | ||
64366f1c | 2189 | /* Return a struct reg defining a pseudo register NAME. */ |
489461e2 | 2190 | #define P(name) { STR(name), 4, 8, 0, 1} |
7a78ae4e ND |
2191 | |
2192 | /* Return a struct reg defining register NAME that's 32 bits on 32-bit | |
64366f1c | 2193 | systems and that doesn't exist on 64-bit systems. */ |
489461e2 | 2194 | #define R32(name) { STR(name), 4, 0, 0, 0 } |
7a78ae4e ND |
2195 | |
2196 | /* Return a struct reg defining register NAME that's 64 bits on 64-bit | |
64366f1c | 2197 | systems and that doesn't exist on 32-bit systems. */ |
489461e2 | 2198 | #define R64(name) { STR(name), 0, 8, 0, 0 } |
7a78ae4e | 2199 | |
64366f1c | 2200 | /* Return a struct reg placeholder for a register that doesn't exist. */ |
489461e2 | 2201 | #define R0 { 0, 0, 0, 0, 0 } |
7a78ae4e ND |
2202 | |
2203 | /* UISA registers common across all architectures, including POWER. */ | |
2204 | ||
2205 | #define COMMON_UISA_REGS \ | |
2206 | /* 0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), \ | |
2207 | /* 8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \ | |
2208 | /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \ | |
2209 | /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \ | |
2210 | /* 32 */ F(f0), F(f1), F(f2), F(f3), F(f4), F(f5), F(f6), F(f7), \ | |
2211 | /* 40 */ F(f8), F(f9), F(f10),F(f11),F(f12),F(f13),F(f14),F(f15), \ | |
2212 | /* 48 */ F(f16),F(f17),F(f18),F(f19),F(f20),F(f21),F(f22),F(f23), \ | |
2213 | /* 56 */ F(f24),F(f25),F(f26),F(f27),F(f28),F(f29),F(f30),F(f31), \ | |
2214 | /* 64 */ R(pc), R(ps) | |
2215 | ||
ebeac11a EZ |
2216 | #define COMMON_UISA_NOFP_REGS \ |
2217 | /* 0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), \ | |
2218 | /* 8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \ | |
2219 | /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \ | |
2220 | /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \ | |
2221 | /* 32 */ R0, R0, R0, R0, R0, R0, R0, R0, \ | |
2222 | /* 40 */ R0, R0, R0, R0, R0, R0, R0, R0, \ | |
2223 | /* 48 */ R0, R0, R0, R0, R0, R0, R0, R0, \ | |
2224 | /* 56 */ R0, R0, R0, R0, R0, R0, R0, R0, \ | |
2225 | /* 64 */ R(pc), R(ps) | |
2226 | ||
7a78ae4e ND |
2227 | /* UISA-level SPRs for PowerPC. */ |
2228 | #define PPC_UISA_SPRS \ | |
e3f36dbd | 2229 | /* 66 */ R4(cr), R(lr), R(ctr), R4(xer), R4(fpscr) |
7a78ae4e | 2230 | |
c8001721 EZ |
2231 | /* UISA-level SPRs for PowerPC without floating point support. */ |
2232 | #define PPC_UISA_NOFP_SPRS \ | |
2233 | /* 66 */ R4(cr), R(lr), R(ctr), R4(xer), R0 | |
2234 | ||
7a78ae4e ND |
2235 | /* Segment registers, for PowerPC. */ |
2236 | #define PPC_SEGMENT_REGS \ | |
2237 | /* 71 */ R32(sr0), R32(sr1), R32(sr2), R32(sr3), \ | |
2238 | /* 75 */ R32(sr4), R32(sr5), R32(sr6), R32(sr7), \ | |
2239 | /* 79 */ R32(sr8), R32(sr9), R32(sr10), R32(sr11), \ | |
2240 | /* 83 */ R32(sr12), R32(sr13), R32(sr14), R32(sr15) | |
2241 | ||
2242 | /* OEA SPRs for PowerPC. */ | |
2243 | #define PPC_OEA_SPRS \ | |
2244 | /* 87 */ R4(pvr), \ | |
2245 | /* 88 */ R(ibat0u), R(ibat0l), R(ibat1u), R(ibat1l), \ | |
2246 | /* 92 */ R(ibat2u), R(ibat2l), R(ibat3u), R(ibat3l), \ | |
2247 | /* 96 */ R(dbat0u), R(dbat0l), R(dbat1u), R(dbat1l), \ | |
2248 | /* 100 */ R(dbat2u), R(dbat2l), R(dbat3u), R(dbat3l), \ | |
2249 | /* 104 */ R(sdr1), R64(asr), R(dar), R4(dsisr), \ | |
2250 | /* 108 */ R(sprg0), R(sprg1), R(sprg2), R(sprg3), \ | |
2251 | /* 112 */ R(srr0), R(srr1), R(tbl), R(tbu), \ | |
2252 | /* 116 */ R4(dec), R(dabr), R4(ear) | |
2253 | ||
64366f1c | 2254 | /* AltiVec registers. */ |
1fcc0bb8 EZ |
2255 | #define PPC_ALTIVEC_REGS \ |
2256 | /*119*/R16(vr0), R16(vr1), R16(vr2), R16(vr3), R16(vr4), R16(vr5), R16(vr6), R16(vr7), \ | |
2257 | /*127*/R16(vr8), R16(vr9), R16(vr10),R16(vr11),R16(vr12),R16(vr13),R16(vr14),R16(vr15), \ | |
2258 | /*135*/R16(vr16),R16(vr17),R16(vr18),R16(vr19),R16(vr20),R16(vr21),R16(vr22),R16(vr23), \ | |
2259 | /*143*/R16(vr24),R16(vr25),R16(vr26),R16(vr27),R16(vr28),R16(vr29),R16(vr30),R16(vr31), \ | |
2260 | /*151*/R4(vscr), R4(vrsave) | |
2261 | ||
c8001721 EZ |
2262 | /* Vectors of hi-lo general purpose registers. */ |
2263 | #define PPC_EV_REGS \ | |
2264 | /* 0*/R8(ev0), R8(ev1), R8(ev2), R8(ev3), R8(ev4), R8(ev5), R8(ev6), R8(ev7), \ | |
2265 | /* 8*/R8(ev8), R8(ev9), R8(ev10),R8(ev11),R8(ev12),R8(ev13),R8(ev14),R8(ev15), \ | |
2266 | /*16*/R8(ev16),R8(ev17),R8(ev18),R8(ev19),R8(ev20),R8(ev21),R8(ev22),R8(ev23), \ | |
2267 | /*24*/R8(ev24),R8(ev25),R8(ev26),R8(ev27),R8(ev28),R8(ev29),R8(ev30),R8(ev31) | |
2268 | ||
2269 | /* Lower half of the EV registers. */ | |
2270 | #define PPC_GPRS_PSEUDO_REGS \ | |
2271 | /* 0 */ P(r0), P(r1), P(r2), P(r3), P(r4), P(r5), P(r6), P(r7), \ | |
2272 | /* 8 */ P(r8), P(r9), P(r10),P(r11),P(r12),P(r13),P(r14),P(r15), \ | |
2273 | /* 16 */ P(r16),P(r17),P(r18),P(r19),P(r20),P(r21),P(r22),P(r23), \ | |
2274 | /* 24 */ P(r24),P(r25),P(r26),P(r27),P(r28),P(r29),P(r30),P(r31), \ | |
2275 | ||
7a78ae4e | 2276 | /* IBM POWER (pre-PowerPC) architecture, user-level view. We only cover |
64366f1c | 2277 | user-level SPR's. */ |
7a78ae4e | 2278 | static const struct reg registers_power[] = |
c906108c | 2279 | { |
7a78ae4e | 2280 | COMMON_UISA_REGS, |
e3f36dbd KB |
2281 | /* 66 */ R4(cnd), R(lr), R(cnt), R4(xer), R4(mq), |
2282 | /* 71 */ R4(fpscr) | |
c906108c SS |
2283 | }; |
2284 | ||
7a78ae4e | 2285 | /* PowerPC UISA - a PPC processor as viewed by user-level code. A UISA-only |
64366f1c | 2286 | view of the PowerPC. */ |
7a78ae4e | 2287 | static const struct reg registers_powerpc[] = |
c906108c | 2288 | { |
7a78ae4e | 2289 | COMMON_UISA_REGS, |
1fcc0bb8 EZ |
2290 | PPC_UISA_SPRS, |
2291 | PPC_ALTIVEC_REGS | |
c906108c SS |
2292 | }; |
2293 | ||
ebeac11a EZ |
2294 | /* PowerPC UISA - a PPC processor as viewed by user-level |
2295 | code, but without floating point registers. */ | |
2296 | static const struct reg registers_powerpc_nofp[] = | |
2297 | { | |
2298 | COMMON_UISA_NOFP_REGS, | |
2299 | PPC_UISA_SPRS | |
2300 | }; | |
2301 | ||
64366f1c | 2302 | /* IBM PowerPC 403. */ |
7a78ae4e | 2303 | static const struct reg registers_403[] = |
c5aa993b | 2304 | { |
7a78ae4e ND |
2305 | COMMON_UISA_REGS, |
2306 | PPC_UISA_SPRS, | |
2307 | PPC_SEGMENT_REGS, | |
2308 | PPC_OEA_SPRS, | |
2309 | /* 119 */ R(icdbdr), R(esr), R(dear), R(evpr), | |
2310 | /* 123 */ R(cdbcr), R(tsr), R(tcr), R(pit), | |
2311 | /* 127 */ R(tbhi), R(tblo), R(srr2), R(srr3), | |
2312 | /* 131 */ R(dbsr), R(dbcr), R(iac1), R(iac2), | |
2313 | /* 135 */ R(dac1), R(dac2), R(dccr), R(iccr), | |
2314 | /* 139 */ R(pbl1), R(pbu1), R(pbl2), R(pbu2) | |
c906108c SS |
2315 | }; |
2316 | ||
64366f1c | 2317 | /* IBM PowerPC 403GC. */ |
7a78ae4e | 2318 | static const struct reg registers_403GC[] = |
c5aa993b | 2319 | { |
7a78ae4e ND |
2320 | COMMON_UISA_REGS, |
2321 | PPC_UISA_SPRS, | |
2322 | PPC_SEGMENT_REGS, | |
2323 | PPC_OEA_SPRS, | |
2324 | /* 119 */ R(icdbdr), R(esr), R(dear), R(evpr), | |
2325 | /* 123 */ R(cdbcr), R(tsr), R(tcr), R(pit), | |
2326 | /* 127 */ R(tbhi), R(tblo), R(srr2), R(srr3), | |
2327 | /* 131 */ R(dbsr), R(dbcr), R(iac1), R(iac2), | |
2328 | /* 135 */ R(dac1), R(dac2), R(dccr), R(iccr), | |
2329 | /* 139 */ R(pbl1), R(pbu1), R(pbl2), R(pbu2), | |
2330 | /* 143 */ R(zpr), R(pid), R(sgr), R(dcwr), | |
2331 | /* 147 */ R(tbhu), R(tblu) | |
c906108c SS |
2332 | }; |
2333 | ||
64366f1c | 2334 | /* Motorola PowerPC 505. */ |
7a78ae4e | 2335 | static const struct reg registers_505[] = |
c5aa993b | 2336 | { |
7a78ae4e ND |
2337 | COMMON_UISA_REGS, |
2338 | PPC_UISA_SPRS, | |
2339 | PPC_SEGMENT_REGS, | |
2340 | PPC_OEA_SPRS, | |
2341 | /* 119 */ R(eie), R(eid), R(nri) | |
c906108c SS |
2342 | }; |
2343 | ||
64366f1c | 2344 | /* Motorola PowerPC 860 or 850. */ |
7a78ae4e | 2345 | static const struct reg registers_860[] = |
c5aa993b | 2346 | { |
7a78ae4e ND |
2347 | COMMON_UISA_REGS, |
2348 | PPC_UISA_SPRS, | |
2349 | PPC_SEGMENT_REGS, | |
2350 | PPC_OEA_SPRS, | |
2351 | /* 119 */ R(eie), R(eid), R(nri), R(cmpa), | |
2352 | /* 123 */ R(cmpb), R(cmpc), R(cmpd), R(icr), | |
2353 | /* 127 */ R(der), R(counta), R(countb), R(cmpe), | |
2354 | /* 131 */ R(cmpf), R(cmpg), R(cmph), R(lctrl1), | |
2355 | /* 135 */ R(lctrl2), R(ictrl), R(bar), R(ic_cst), | |
2356 | /* 139 */ R(ic_adr), R(ic_dat), R(dc_cst), R(dc_adr), | |
2357 | /* 143 */ R(dc_dat), R(dpdr), R(dpir), R(immr), | |
2358 | /* 147 */ R(mi_ctr), R(mi_ap), R(mi_epn), R(mi_twc), | |
2359 | /* 151 */ R(mi_rpn), R(md_ctr), R(m_casid), R(md_ap), | |
2360 | /* 155 */ R(md_epn), R(md_twb), R(md_twc), R(md_rpn), | |
2361 | /* 159 */ R(m_tw), R(mi_dbcam), R(mi_dbram0), R(mi_dbram1), | |
2362 | /* 163 */ R(md_dbcam), R(md_dbram0), R(md_dbram1) | |
c906108c SS |
2363 | }; |
2364 | ||
7a78ae4e ND |
2365 | /* Motorola PowerPC 601. Note that the 601 has different register numbers |
2366 | for reading and writing RTCU and RTCL. However, how one reads and writes a | |
c906108c | 2367 | register is the stub's problem. */ |
7a78ae4e | 2368 | static const struct reg registers_601[] = |
c5aa993b | 2369 | { |
7a78ae4e ND |
2370 | COMMON_UISA_REGS, |
2371 | PPC_UISA_SPRS, | |
2372 | PPC_SEGMENT_REGS, | |
2373 | PPC_OEA_SPRS, | |
2374 | /* 119 */ R(hid0), R(hid1), R(iabr), R(dabr), | |
2375 | /* 123 */ R(pir), R(mq), R(rtcu), R(rtcl) | |
c906108c SS |
2376 | }; |
2377 | ||
64366f1c | 2378 | /* Motorola PowerPC 602. */ |
7a78ae4e | 2379 | static const struct reg registers_602[] = |
c5aa993b | 2380 | { |
7a78ae4e ND |
2381 | COMMON_UISA_REGS, |
2382 | PPC_UISA_SPRS, | |
2383 | PPC_SEGMENT_REGS, | |
2384 | PPC_OEA_SPRS, | |
2385 | /* 119 */ R(hid0), R(hid1), R(iabr), R0, | |
2386 | /* 123 */ R0, R(tcr), R(ibr), R(esassr), | |
2387 | /* 127 */ R(sebr), R(ser), R(sp), R(lt) | |
c906108c SS |
2388 | }; |
2389 | ||
64366f1c | 2390 | /* Motorola/IBM PowerPC 603 or 603e. */ |
7a78ae4e | 2391 | static const struct reg registers_603[] = |
c5aa993b | 2392 | { |
7a78ae4e ND |
2393 | COMMON_UISA_REGS, |
2394 | PPC_UISA_SPRS, | |
2395 | PPC_SEGMENT_REGS, | |
2396 | PPC_OEA_SPRS, | |
2397 | /* 119 */ R(hid0), R(hid1), R(iabr), R0, | |
2398 | /* 123 */ R0, R(dmiss), R(dcmp), R(hash1), | |
2399 | /* 127 */ R(hash2), R(imiss), R(icmp), R(rpa) | |
c906108c SS |
2400 | }; |
2401 | ||
64366f1c | 2402 | /* Motorola PowerPC 604 or 604e. */ |
7a78ae4e | 2403 | static const struct reg registers_604[] = |
c5aa993b | 2404 | { |
7a78ae4e ND |
2405 | COMMON_UISA_REGS, |
2406 | PPC_UISA_SPRS, | |
2407 | PPC_SEGMENT_REGS, | |
2408 | PPC_OEA_SPRS, | |
2409 | /* 119 */ R(hid0), R(hid1), R(iabr), R(dabr), | |
2410 | /* 123 */ R(pir), R(mmcr0), R(pmc1), R(pmc2), | |
2411 | /* 127 */ R(sia), R(sda) | |
c906108c SS |
2412 | }; |
2413 | ||
64366f1c | 2414 | /* Motorola/IBM PowerPC 750 or 740. */ |
7a78ae4e | 2415 | static const struct reg registers_750[] = |
c5aa993b | 2416 | { |
7a78ae4e ND |
2417 | COMMON_UISA_REGS, |
2418 | PPC_UISA_SPRS, | |
2419 | PPC_SEGMENT_REGS, | |
2420 | PPC_OEA_SPRS, | |
2421 | /* 119 */ R(hid0), R(hid1), R(iabr), R(dabr), | |
2422 | /* 123 */ R0, R(ummcr0), R(upmc1), R(upmc2), | |
2423 | /* 127 */ R(usia), R(ummcr1), R(upmc3), R(upmc4), | |
2424 | /* 131 */ R(mmcr0), R(pmc1), R(pmc2), R(sia), | |
2425 | /* 135 */ R(mmcr1), R(pmc3), R(pmc4), R(l2cr), | |
2426 | /* 139 */ R(ictc), R(thrm1), R(thrm2), R(thrm3) | |
c906108c SS |
2427 | }; |
2428 | ||
2429 | ||
64366f1c | 2430 | /* Motorola PowerPC 7400. */ |
1fcc0bb8 EZ |
2431 | static const struct reg registers_7400[] = |
2432 | { | |
2433 | /* gpr0-gpr31, fpr0-fpr31 */ | |
2434 | COMMON_UISA_REGS, | |
2435 | /* ctr, xre, lr, cr */ | |
2436 | PPC_UISA_SPRS, | |
2437 | /* sr0-sr15 */ | |
2438 | PPC_SEGMENT_REGS, | |
2439 | PPC_OEA_SPRS, | |
2440 | /* vr0-vr31, vrsave, vscr */ | |
2441 | PPC_ALTIVEC_REGS | |
2442 | /* FIXME? Add more registers? */ | |
2443 | }; | |
2444 | ||
c8001721 EZ |
2445 | /* Motorola e500. */ |
2446 | static const struct reg registers_e500[] = | |
2447 | { | |
2448 | R(pc), R(ps), | |
2449 | /* cr, lr, ctr, xer, "" */ | |
2450 | PPC_UISA_NOFP_SPRS, | |
2451 | /* 7...38 */ | |
2452 | PPC_EV_REGS, | |
2453 | /* 39...70 */ | |
2454 | PPC_GPRS_PSEUDO_REGS | |
2455 | }; | |
2456 | ||
c906108c | 2457 | /* Information about a particular processor variant. */ |
7a78ae4e | 2458 | |
c906108c | 2459 | struct variant |
c5aa993b JM |
2460 | { |
2461 | /* Name of this variant. */ | |
2462 | char *name; | |
c906108c | 2463 | |
c5aa993b JM |
2464 | /* English description of the variant. */ |
2465 | char *description; | |
c906108c | 2466 | |
64366f1c | 2467 | /* bfd_arch_info.arch corresponding to variant. */ |
7a78ae4e ND |
2468 | enum bfd_architecture arch; |
2469 | ||
64366f1c | 2470 | /* bfd_arch_info.mach corresponding to variant. */ |
7a78ae4e ND |
2471 | unsigned long mach; |
2472 | ||
489461e2 EZ |
2473 | /* Number of real registers. */ |
2474 | int nregs; | |
2475 | ||
2476 | /* Number of pseudo registers. */ | |
2477 | int npregs; | |
2478 | ||
2479 | /* Number of total registers (the sum of nregs and npregs). */ | |
2480 | int num_tot_regs; | |
2481 | ||
c5aa993b JM |
2482 | /* Table of register names; registers[R] is the name of the register |
2483 | number R. */ | |
7a78ae4e | 2484 | const struct reg *regs; |
c5aa993b | 2485 | }; |
c906108c | 2486 | |
489461e2 EZ |
2487 | #define tot_num_registers(list) (sizeof (list) / sizeof((list)[0])) |
2488 | ||
2489 | static int | |
2490 | num_registers (const struct reg *reg_list, int num_tot_regs) | |
2491 | { | |
2492 | int i; | |
2493 | int nregs = 0; | |
2494 | ||
2495 | for (i = 0; i < num_tot_regs; i++) | |
2496 | if (!reg_list[i].pseudo) | |
2497 | nregs++; | |
2498 | ||
2499 | return nregs; | |
2500 | } | |
2501 | ||
2502 | static int | |
2503 | num_pseudo_registers (const struct reg *reg_list, int num_tot_regs) | |
2504 | { | |
2505 | int i; | |
2506 | int npregs = 0; | |
2507 | ||
2508 | for (i = 0; i < num_tot_regs; i++) | |
2509 | if (reg_list[i].pseudo) | |
2510 | npregs ++; | |
2511 | ||
2512 | return npregs; | |
2513 | } | |
c906108c | 2514 | |
c906108c SS |
2515 | /* Information in this table comes from the following web sites: |
2516 | IBM: http://www.chips.ibm.com:80/products/embedded/ | |
2517 | Motorola: http://www.mot.com/SPS/PowerPC/ | |
2518 | ||
2519 | I'm sure I've got some of the variant descriptions not quite right. | |
2520 | Please report any inaccuracies you find to GDB's maintainer. | |
2521 | ||
2522 | If you add entries to this table, please be sure to allow the new | |
2523 | value as an argument to the --with-cpu flag, in configure.in. */ | |
2524 | ||
489461e2 | 2525 | static struct variant variants[] = |
c906108c | 2526 | { |
489461e2 | 2527 | |
7a78ae4e | 2528 | {"powerpc", "PowerPC user-level", bfd_arch_powerpc, |
489461e2 EZ |
2529 | bfd_mach_ppc, -1, -1, tot_num_registers (registers_powerpc), |
2530 | registers_powerpc}, | |
7a78ae4e | 2531 | {"power", "POWER user-level", bfd_arch_rs6000, |
489461e2 EZ |
2532 | bfd_mach_rs6k, -1, -1, tot_num_registers (registers_power), |
2533 | registers_power}, | |
7a78ae4e | 2534 | {"403", "IBM PowerPC 403", bfd_arch_powerpc, |
489461e2 EZ |
2535 | bfd_mach_ppc_403, -1, -1, tot_num_registers (registers_403), |
2536 | registers_403}, | |
7a78ae4e | 2537 | {"601", "Motorola PowerPC 601", bfd_arch_powerpc, |
489461e2 EZ |
2538 | bfd_mach_ppc_601, -1, -1, tot_num_registers (registers_601), |
2539 | registers_601}, | |
7a78ae4e | 2540 | {"602", "Motorola PowerPC 602", bfd_arch_powerpc, |
489461e2 EZ |
2541 | bfd_mach_ppc_602, -1, -1, tot_num_registers (registers_602), |
2542 | registers_602}, | |
7a78ae4e | 2543 | {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc, |
489461e2 EZ |
2544 | bfd_mach_ppc_603, -1, -1, tot_num_registers (registers_603), |
2545 | registers_603}, | |
7a78ae4e | 2546 | {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc, |
489461e2 EZ |
2547 | 604, -1, -1, tot_num_registers (registers_604), |
2548 | registers_604}, | |
7a78ae4e | 2549 | {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc, |
489461e2 EZ |
2550 | bfd_mach_ppc_403gc, -1, -1, tot_num_registers (registers_403GC), |
2551 | registers_403GC}, | |
7a78ae4e | 2552 | {"505", "Motorola PowerPC 505", bfd_arch_powerpc, |
489461e2 EZ |
2553 | bfd_mach_ppc_505, -1, -1, tot_num_registers (registers_505), |
2554 | registers_505}, | |
7a78ae4e | 2555 | {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc, |
489461e2 EZ |
2556 | bfd_mach_ppc_860, -1, -1, tot_num_registers (registers_860), |
2557 | registers_860}, | |
7a78ae4e | 2558 | {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc, |
489461e2 EZ |
2559 | bfd_mach_ppc_750, -1, -1, tot_num_registers (registers_750), |
2560 | registers_750}, | |
1fcc0bb8 | 2561 | {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc, |
489461e2 EZ |
2562 | bfd_mach_ppc_7400, -1, -1, tot_num_registers (registers_7400), |
2563 | registers_7400}, | |
c8001721 EZ |
2564 | {"e500", "Motorola PowerPC e500", bfd_arch_powerpc, |
2565 | bfd_mach_ppc_e500, -1, -1, tot_num_registers (registers_e500), | |
2566 | registers_e500}, | |
7a78ae4e | 2567 | |
5d57ee30 KB |
2568 | /* 64-bit */ |
2569 | {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc, | |
489461e2 EZ |
2570 | bfd_mach_ppc64, -1, -1, tot_num_registers (registers_powerpc), |
2571 | registers_powerpc}, | |
7a78ae4e | 2572 | {"620", "Motorola PowerPC 620", bfd_arch_powerpc, |
489461e2 EZ |
2573 | bfd_mach_ppc_620, -1, -1, tot_num_registers (registers_powerpc), |
2574 | registers_powerpc}, | |
5d57ee30 | 2575 | {"630", "Motorola PowerPC 630", bfd_arch_powerpc, |
489461e2 EZ |
2576 | bfd_mach_ppc_630, -1, -1, tot_num_registers (registers_powerpc), |
2577 | registers_powerpc}, | |
7a78ae4e | 2578 | {"a35", "PowerPC A35", bfd_arch_powerpc, |
489461e2 EZ |
2579 | bfd_mach_ppc_a35, -1, -1, tot_num_registers (registers_powerpc), |
2580 | registers_powerpc}, | |
5d57ee30 | 2581 | {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc, |
489461e2 EZ |
2582 | bfd_mach_ppc_rs64ii, -1, -1, tot_num_registers (registers_powerpc), |
2583 | registers_powerpc}, | |
5d57ee30 | 2584 | {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc, |
489461e2 EZ |
2585 | bfd_mach_ppc_rs64iii, -1, -1, tot_num_registers (registers_powerpc), |
2586 | registers_powerpc}, | |
5d57ee30 | 2587 | |
64366f1c | 2588 | /* FIXME: I haven't checked the register sets of the following. */ |
7a78ae4e | 2589 | {"rs1", "IBM POWER RS1", bfd_arch_rs6000, |
489461e2 EZ |
2590 | bfd_mach_rs6k_rs1, -1, -1, tot_num_registers (registers_power), |
2591 | registers_power}, | |
7a78ae4e | 2592 | {"rsc", "IBM POWER RSC", bfd_arch_rs6000, |
489461e2 EZ |
2593 | bfd_mach_rs6k_rsc, -1, -1, tot_num_registers (registers_power), |
2594 | registers_power}, | |
7a78ae4e | 2595 | {"rs2", "IBM POWER RS2", bfd_arch_rs6000, |
489461e2 EZ |
2596 | bfd_mach_rs6k_rs2, -1, -1, tot_num_registers (registers_power), |
2597 | registers_power}, | |
7a78ae4e | 2598 | |
489461e2 | 2599 | {0, 0, 0, 0, 0, 0, 0, 0} |
c906108c SS |
2600 | }; |
2601 | ||
64366f1c | 2602 | /* Initialize the number of registers and pseudo registers in each variant. */ |
489461e2 EZ |
2603 | |
2604 | static void | |
2605 | init_variants (void) | |
2606 | { | |
2607 | struct variant *v; | |
2608 | ||
2609 | for (v = variants; v->name; v++) | |
2610 | { | |
2611 | if (v->nregs == -1) | |
2612 | v->nregs = num_registers (v->regs, v->num_tot_regs); | |
2613 | if (v->npregs == -1) | |
2614 | v->npregs = num_pseudo_registers (v->regs, v->num_tot_regs); | |
2615 | } | |
2616 | } | |
c906108c | 2617 | |
7a78ae4e | 2618 | /* Return the variant corresponding to architecture ARCH and machine number |
64366f1c | 2619 | MACH. If no such variant exists, return null. */ |
c906108c | 2620 | |
7a78ae4e ND |
2621 | static const struct variant * |
2622 | find_variant_by_arch (enum bfd_architecture arch, unsigned long mach) | |
c906108c | 2623 | { |
7a78ae4e | 2624 | const struct variant *v; |
c5aa993b | 2625 | |
7a78ae4e ND |
2626 | for (v = variants; v->name; v++) |
2627 | if (arch == v->arch && mach == v->mach) | |
2628 | return v; | |
c906108c | 2629 | |
7a78ae4e | 2630 | return NULL; |
c906108c | 2631 | } |
9364a0ef EZ |
2632 | |
2633 | static int | |
2634 | gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info) | |
2635 | { | |
2636 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
2637 | return print_insn_big_powerpc (memaddr, info); | |
2638 | else | |
2639 | return print_insn_little_powerpc (memaddr, info); | |
2640 | } | |
7a78ae4e | 2641 | \f |
7a78ae4e ND |
2642 | /* Initialize the current architecture based on INFO. If possible, re-use an |
2643 | architecture from ARCHES, which is a list of architectures already created | |
2644 | during this debugging session. | |
c906108c | 2645 | |
7a78ae4e | 2646 | Called e.g. at program startup, when reading a core file, and when reading |
64366f1c | 2647 | a binary file. */ |
c906108c | 2648 | |
7a78ae4e ND |
2649 | static struct gdbarch * |
2650 | rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
2651 | { | |
2652 | struct gdbarch *gdbarch; | |
2653 | struct gdbarch_tdep *tdep; | |
9aa1e687 | 2654 | int wordsize, from_xcoff_exec, from_elf_exec, power, i, off; |
7a78ae4e ND |
2655 | struct reg *regs; |
2656 | const struct variant *v; | |
2657 | enum bfd_architecture arch; | |
2658 | unsigned long mach; | |
2659 | bfd abfd; | |
7b112f9c | 2660 | int sysv_abi; |
5bf1c677 | 2661 | asection *sect; |
7a78ae4e | 2662 | |
9aa1e687 | 2663 | from_xcoff_exec = info.abfd && info.abfd->format == bfd_object && |
7a78ae4e ND |
2664 | bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour; |
2665 | ||
9aa1e687 KB |
2666 | from_elf_exec = info.abfd && info.abfd->format == bfd_object && |
2667 | bfd_get_flavour (info.abfd) == bfd_target_elf_flavour; | |
2668 | ||
2669 | sysv_abi = info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour; | |
2670 | ||
e712c1cf | 2671 | /* Check word size. If INFO is from a binary file, infer it from |
64366f1c | 2672 | that, else choose a likely default. */ |
9aa1e687 | 2673 | if (from_xcoff_exec) |
c906108c | 2674 | { |
11ed25ac | 2675 | if (bfd_xcoff_is_xcoff64 (info.abfd)) |
7a78ae4e ND |
2676 | wordsize = 8; |
2677 | else | |
2678 | wordsize = 4; | |
c906108c | 2679 | } |
9aa1e687 KB |
2680 | else if (from_elf_exec) |
2681 | { | |
2682 | if (elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
2683 | wordsize = 8; | |
2684 | else | |
2685 | wordsize = 4; | |
2686 | } | |
c906108c | 2687 | else |
7a78ae4e | 2688 | { |
27b15785 KB |
2689 | if (info.bfd_arch_info != NULL && info.bfd_arch_info->bits_per_word != 0) |
2690 | wordsize = info.bfd_arch_info->bits_per_word / | |
2691 | info.bfd_arch_info->bits_per_byte; | |
2692 | else | |
2693 | wordsize = 4; | |
7a78ae4e | 2694 | } |
c906108c | 2695 | |
64366f1c | 2696 | /* Find a candidate among extant architectures. */ |
7a78ae4e ND |
2697 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
2698 | arches != NULL; | |
2699 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
2700 | { | |
2701 | /* Word size in the various PowerPC bfd_arch_info structs isn't | |
2702 | meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform | |
64366f1c | 2703 | separate word size check. */ |
7a78ae4e | 2704 | tdep = gdbarch_tdep (arches->gdbarch); |
4be87837 | 2705 | if (tdep && tdep->wordsize == wordsize) |
7a78ae4e ND |
2706 | return arches->gdbarch; |
2707 | } | |
c906108c | 2708 | |
7a78ae4e ND |
2709 | /* None found, create a new architecture from INFO, whose bfd_arch_info |
2710 | validity depends on the source: | |
2711 | - executable useless | |
2712 | - rs6000_host_arch() good | |
2713 | - core file good | |
2714 | - "set arch" trust blindly | |
2715 | - GDB startup useless but harmless */ | |
c906108c | 2716 | |
9aa1e687 | 2717 | if (!from_xcoff_exec) |
c906108c | 2718 | { |
b732d07d | 2719 | arch = info.bfd_arch_info->arch; |
7a78ae4e | 2720 | mach = info.bfd_arch_info->mach; |
c906108c | 2721 | } |
7a78ae4e | 2722 | else |
c906108c | 2723 | { |
7a78ae4e ND |
2724 | arch = bfd_arch_powerpc; |
2725 | mach = 0; | |
2726 | bfd_default_set_arch_mach (&abfd, arch, mach); | |
2727 | info.bfd_arch_info = bfd_get_arch_info (&abfd); | |
2728 | } | |
2729 | tdep = xmalloc (sizeof (struct gdbarch_tdep)); | |
2730 | tdep->wordsize = wordsize; | |
5bf1c677 EZ |
2731 | |
2732 | /* For e500 executables, the apuinfo section is of help here. Such | |
2733 | section contains the identifier and revision number of each | |
2734 | Application-specific Processing Unit that is present on the | |
2735 | chip. The content of the section is determined by the assembler | |
2736 | which looks at each instruction and determines which unit (and | |
2737 | which version of it) can execute it. In our case we just look for | |
2738 | the existance of the section. */ | |
2739 | ||
2740 | if (info.abfd) | |
2741 | { | |
2742 | sect = bfd_get_section_by_name (info.abfd, ".PPC.EMB.apuinfo"); | |
2743 | if (sect) | |
2744 | { | |
2745 | arch = info.bfd_arch_info->arch; | |
2746 | mach = bfd_mach_ppc_e500; | |
2747 | bfd_default_set_arch_mach (&abfd, arch, mach); | |
2748 | info.bfd_arch_info = bfd_get_arch_info (&abfd); | |
2749 | } | |
2750 | } | |
2751 | ||
7a78ae4e ND |
2752 | gdbarch = gdbarch_alloc (&info, tdep); |
2753 | power = arch == bfd_arch_rs6000; | |
2754 | ||
489461e2 EZ |
2755 | /* Initialize the number of real and pseudo registers in each variant. */ |
2756 | init_variants (); | |
2757 | ||
64366f1c | 2758 | /* Choose variant. */ |
7a78ae4e ND |
2759 | v = find_variant_by_arch (arch, mach); |
2760 | if (!v) | |
dd47e6fd EZ |
2761 | return NULL; |
2762 | ||
7a78ae4e ND |
2763 | tdep->regs = v->regs; |
2764 | ||
2188cbdd EZ |
2765 | tdep->ppc_gp0_regnum = 0; |
2766 | tdep->ppc_gplast_regnum = 31; | |
2767 | tdep->ppc_toc_regnum = 2; | |
2768 | tdep->ppc_ps_regnum = 65; | |
2769 | tdep->ppc_cr_regnum = 66; | |
2770 | tdep->ppc_lr_regnum = 67; | |
2771 | tdep->ppc_ctr_regnum = 68; | |
2772 | tdep->ppc_xer_regnum = 69; | |
2773 | if (v->mach == bfd_mach_ppc_601) | |
2774 | tdep->ppc_mq_regnum = 124; | |
e3f36dbd | 2775 | else if (power) |
2188cbdd | 2776 | tdep->ppc_mq_regnum = 70; |
e3f36dbd KB |
2777 | else |
2778 | tdep->ppc_mq_regnum = -1; | |
2779 | tdep->ppc_fpscr_regnum = power ? 71 : 70; | |
2188cbdd | 2780 | |
c8001721 EZ |
2781 | set_gdbarch_pc_regnum (gdbarch, 64); |
2782 | set_gdbarch_sp_regnum (gdbarch, 1); | |
2783 | set_gdbarch_fp_regnum (gdbarch, 1); | |
96ff0de4 EZ |
2784 | set_gdbarch_deprecated_extract_return_value (gdbarch, |
2785 | rs6000_extract_return_value); | |
46d79c04 | 2786 | set_gdbarch_deprecated_store_return_value (gdbarch, rs6000_store_return_value); |
c8001721 | 2787 | |
1fcc0bb8 EZ |
2788 | if (v->arch == bfd_arch_powerpc) |
2789 | switch (v->mach) | |
2790 | { | |
2791 | case bfd_mach_ppc: | |
2792 | tdep->ppc_vr0_regnum = 71; | |
2793 | tdep->ppc_vrsave_regnum = 104; | |
c8001721 EZ |
2794 | tdep->ppc_ev0_regnum = -1; |
2795 | tdep->ppc_ev31_regnum = -1; | |
1fcc0bb8 EZ |
2796 | break; |
2797 | case bfd_mach_ppc_7400: | |
2798 | tdep->ppc_vr0_regnum = 119; | |
54c2a1e6 | 2799 | tdep->ppc_vrsave_regnum = 152; |
c8001721 EZ |
2800 | tdep->ppc_ev0_regnum = -1; |
2801 | tdep->ppc_ev31_regnum = -1; | |
2802 | break; | |
2803 | case bfd_mach_ppc_e500: | |
2804 | tdep->ppc_gp0_regnum = 39; | |
2805 | tdep->ppc_gplast_regnum = 70; | |
2806 | tdep->ppc_toc_regnum = -1; | |
2807 | tdep->ppc_ps_regnum = 1; | |
2808 | tdep->ppc_cr_regnum = 2; | |
2809 | tdep->ppc_lr_regnum = 3; | |
2810 | tdep->ppc_ctr_regnum = 4; | |
2811 | tdep->ppc_xer_regnum = 5; | |
2812 | tdep->ppc_ev0_regnum = 7; | |
2813 | tdep->ppc_ev31_regnum = 38; | |
2814 | set_gdbarch_pc_regnum (gdbarch, 0); | |
2815 | set_gdbarch_sp_regnum (gdbarch, 40); | |
2816 | set_gdbarch_fp_regnum (gdbarch, 40); | |
2817 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, e500_dwarf2_reg_to_regnum); | |
2818 | set_gdbarch_pseudo_register_read (gdbarch, e500_pseudo_register_read); | |
2819 | set_gdbarch_pseudo_register_write (gdbarch, e500_pseudo_register_write); | |
96ff0de4 | 2820 | set_gdbarch_extract_return_value (gdbarch, e500_extract_return_value); |
46d79c04 | 2821 | set_gdbarch_deprecated_store_return_value (gdbarch, e500_store_return_value); |
1fcc0bb8 EZ |
2822 | break; |
2823 | default: | |
2824 | tdep->ppc_vr0_regnum = -1; | |
2825 | tdep->ppc_vrsave_regnum = -1; | |
c8001721 EZ |
2826 | tdep->ppc_ev0_regnum = -1; |
2827 | tdep->ppc_ev31_regnum = -1; | |
1fcc0bb8 EZ |
2828 | break; |
2829 | } | |
2830 | ||
a88376a3 KB |
2831 | /* Set lr_frame_offset. */ |
2832 | if (wordsize == 8) | |
2833 | tdep->lr_frame_offset = 16; | |
2834 | else if (sysv_abi) | |
2835 | tdep->lr_frame_offset = 4; | |
2836 | else | |
2837 | tdep->lr_frame_offset = 8; | |
2838 | ||
2839 | /* Calculate byte offsets in raw register array. */ | |
489461e2 EZ |
2840 | tdep->regoff = xmalloc (v->num_tot_regs * sizeof (int)); |
2841 | for (i = off = 0; i < v->num_tot_regs; i++) | |
7a78ae4e ND |
2842 | { |
2843 | tdep->regoff[i] = off; | |
2844 | off += regsize (v->regs + i, wordsize); | |
c906108c SS |
2845 | } |
2846 | ||
56a6dfb9 KB |
2847 | /* Select instruction printer. */ |
2848 | if (arch == power) | |
9364a0ef | 2849 | set_gdbarch_print_insn (gdbarch, print_insn_rs6000); |
56a6dfb9 | 2850 | else |
9364a0ef | 2851 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_powerpc); |
7495d1dc | 2852 | |
7a78ae4e ND |
2853 | set_gdbarch_read_pc (gdbarch, generic_target_read_pc); |
2854 | set_gdbarch_write_pc (gdbarch, generic_target_write_pc); | |
2855 | set_gdbarch_read_fp (gdbarch, generic_target_read_fp); | |
7a78ae4e ND |
2856 | set_gdbarch_read_sp (gdbarch, generic_target_read_sp); |
2857 | set_gdbarch_write_sp (gdbarch, generic_target_write_sp); | |
2858 | ||
2859 | set_gdbarch_num_regs (gdbarch, v->nregs); | |
c8001721 | 2860 | set_gdbarch_num_pseudo_regs (gdbarch, v->npregs); |
7a78ae4e ND |
2861 | set_gdbarch_register_name (gdbarch, rs6000_register_name); |
2862 | set_gdbarch_register_size (gdbarch, wordsize); | |
2863 | set_gdbarch_register_bytes (gdbarch, off); | |
2864 | set_gdbarch_register_byte (gdbarch, rs6000_register_byte); | |
2865 | set_gdbarch_register_raw_size (gdbarch, rs6000_register_raw_size); | |
2a873819 | 2866 | set_gdbarch_max_register_raw_size (gdbarch, 16); |
b2e75d78 | 2867 | set_gdbarch_register_virtual_size (gdbarch, generic_register_size); |
2a873819 | 2868 | set_gdbarch_max_register_virtual_size (gdbarch, 16); |
7a78ae4e ND |
2869 | set_gdbarch_register_virtual_type (gdbarch, rs6000_register_virtual_type); |
2870 | ||
2871 | set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT); | |
2872 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); | |
2873 | set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
2874 | set_gdbarch_long_bit (gdbarch, wordsize * TARGET_CHAR_BIT); | |
2875 | set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
2876 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
2877 | set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
2878 | set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
4e409299 | 2879 | set_gdbarch_char_signed (gdbarch, 0); |
7a78ae4e | 2880 | |
7a78ae4e | 2881 | set_gdbarch_call_dummy_length (gdbarch, 0); |
7a78ae4e ND |
2882 | set_gdbarch_call_dummy_address (gdbarch, entry_point_address); |
2883 | set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1); | |
2884 | set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0); | |
2885 | set_gdbarch_call_dummy_start_offset (gdbarch, 0); | |
7a78ae4e ND |
2886 | set_gdbarch_call_dummy_p (gdbarch, 1); |
2887 | set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0); | |
7a78ae4e | 2888 | set_gdbarch_fix_call_dummy (gdbarch, rs6000_fix_call_dummy); |
11269d7e | 2889 | set_gdbarch_frame_align (gdbarch, rs6000_frame_align); |
7a78ae4e | 2890 | set_gdbarch_push_dummy_frame (gdbarch, generic_push_dummy_frame); |
58223630 | 2891 | set_gdbarch_save_dummy_frame_tos (gdbarch, generic_save_dummy_frame_tos); |
7a78ae4e ND |
2892 | set_gdbarch_push_return_address (gdbarch, ppc_push_return_address); |
2893 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); | |
7a78ae4e ND |
2894 | |
2895 | set_gdbarch_register_convertible (gdbarch, rs6000_register_convertible); | |
2896 | set_gdbarch_register_convert_to_virtual (gdbarch, rs6000_register_convert_to_virtual); | |
2897 | set_gdbarch_register_convert_to_raw (gdbarch, rs6000_register_convert_to_raw); | |
2188cbdd | 2898 | set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_stab_reg_to_regnum); |
2ea5f656 KB |
2899 | /* Note: kevinb/2002-04-12: I'm not convinced that rs6000_push_arguments() |
2900 | is correct for the SysV ABI when the wordsize is 8, but I'm also | |
2901 | fairly certain that ppc_sysv_abi_push_arguments() will give even | |
2902 | worse results since it only works for 32-bit code. So, for the moment, | |
2903 | we're better off calling rs6000_push_arguments() since it works for | |
2904 | 64-bit code. At some point in the future, this matter needs to be | |
2905 | revisited. */ | |
2906 | if (sysv_abi && wordsize == 4) | |
9aa1e687 KB |
2907 | set_gdbarch_push_arguments (gdbarch, ppc_sysv_abi_push_arguments); |
2908 | else | |
2909 | set_gdbarch_push_arguments (gdbarch, rs6000_push_arguments); | |
7a78ae4e | 2910 | |
d0403e00 | 2911 | set_gdbarch_store_struct_return (gdbarch, rs6000_store_struct_return); |
11269d7e | 2912 | set_gdbarch_extract_struct_value_address (gdbarch, rs6000_extract_struct_value_address); |
7a78ae4e ND |
2913 | set_gdbarch_pop_frame (gdbarch, rs6000_pop_frame); |
2914 | ||
2915 | set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue); | |
2916 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
2917 | set_gdbarch_decr_pc_after_break (gdbarch, 0); | |
2918 | set_gdbarch_function_start_offset (gdbarch, 0); | |
2919 | set_gdbarch_breakpoint_from_pc (gdbarch, rs6000_breakpoint_from_pc); | |
2920 | ||
2921 | /* Not sure on this. FIXMEmgo */ | |
2922 | set_gdbarch_frame_args_skip (gdbarch, 8); | |
2923 | ||
8e0662df | 2924 | if (sysv_abi) |
7b112f9c JT |
2925 | set_gdbarch_use_struct_convention (gdbarch, |
2926 | ppc_sysv_abi_use_struct_convention); | |
8e0662df | 2927 | else |
7b112f9c JT |
2928 | set_gdbarch_use_struct_convention (gdbarch, |
2929 | generic_use_struct_convention); | |
8e0662df | 2930 | |
7b112f9c JT |
2931 | set_gdbarch_frameless_function_invocation (gdbarch, |
2932 | rs6000_frameless_function_invocation); | |
2933 | set_gdbarch_frame_chain (gdbarch, rs6000_frame_chain); | |
2934 | set_gdbarch_frame_saved_pc (gdbarch, rs6000_frame_saved_pc); | |
2935 | ||
2936 | set_gdbarch_frame_init_saved_regs (gdbarch, rs6000_frame_init_saved_regs); | |
2937 | set_gdbarch_init_extra_frame_info (gdbarch, rs6000_init_extra_frame_info); | |
2938 | ||
15813d3f AC |
2939 | if (!sysv_abi) |
2940 | { | |
2941 | /* Handle RS/6000 function pointers (which are really function | |
2942 | descriptors). */ | |
f517ea4e PS |
2943 | set_gdbarch_convert_from_func_ptr_addr (gdbarch, |
2944 | rs6000_convert_from_func_ptr_addr); | |
9aa1e687 | 2945 | } |
7a78ae4e ND |
2946 | set_gdbarch_frame_args_address (gdbarch, rs6000_frame_args_address); |
2947 | set_gdbarch_frame_locals_address (gdbarch, rs6000_frame_args_address); | |
2948 | set_gdbarch_saved_pc_after_call (gdbarch, rs6000_saved_pc_after_call); | |
2949 | ||
2950 | /* We can't tell how many args there are | |
2951 | now that the C compiler delays popping them. */ | |
2952 | set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown); | |
2953 | ||
7b112f9c | 2954 | /* Hook in ABI-specific overrides, if they have been registered. */ |
4be87837 | 2955 | gdbarch_init_osabi (info, gdbarch); |
7b112f9c | 2956 | |
7a78ae4e | 2957 | return gdbarch; |
c906108c SS |
2958 | } |
2959 | ||
7b112f9c JT |
2960 | static void |
2961 | rs6000_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
2962 | { | |
2963 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2964 | ||
2965 | if (tdep == NULL) | |
2966 | return; | |
2967 | ||
4be87837 | 2968 | /* FIXME: Dump gdbarch_tdep. */ |
7b112f9c JT |
2969 | } |
2970 | ||
1fcc0bb8 EZ |
2971 | static struct cmd_list_element *info_powerpc_cmdlist = NULL; |
2972 | ||
2973 | static void | |
2974 | rs6000_info_powerpc_command (char *args, int from_tty) | |
2975 | { | |
2976 | help_list (info_powerpc_cmdlist, "info powerpc ", class_info, gdb_stdout); | |
2977 | } | |
2978 | ||
c906108c SS |
2979 | /* Initialization code. */ |
2980 | ||
2981 | void | |
fba45db2 | 2982 | _initialize_rs6000_tdep (void) |
c906108c | 2983 | { |
7b112f9c JT |
2984 | gdbarch_register (bfd_arch_rs6000, rs6000_gdbarch_init, rs6000_dump_tdep); |
2985 | gdbarch_register (bfd_arch_powerpc, rs6000_gdbarch_init, rs6000_dump_tdep); | |
1fcc0bb8 EZ |
2986 | |
2987 | /* Add root prefix command for "info powerpc" commands */ | |
2988 | add_prefix_cmd ("powerpc", class_info, rs6000_info_powerpc_command, | |
2989 | "Various POWERPC info specific commands.", | |
2990 | &info_powerpc_cmdlist, "info powerpc ", 0, &infolist); | |
c906108c | 2991 | } |