Commit | Line | Data |
---|---|---|
c906108c | 1 | /* Target-dependent code for GDB, the GNU debugger. |
7aea86e6 AC |
2 | |
3 | Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, | |
4 | 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software | |
5 | Foundation, Inc. | |
c906108c | 6 | |
c5aa993b | 7 | This file is part of GDB. |
c906108c | 8 | |
c5aa993b JM |
9 | This program is free software; you can redistribute it and/or modify |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2 of the License, or | |
12 | (at your option) any later version. | |
c906108c | 13 | |
c5aa993b JM |
14 | This program is distributed in the hope that it will be useful, |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
c906108c | 18 | |
c5aa993b JM |
19 | You should have received a copy of the GNU General Public License |
20 | along with this program; if not, write to the Free Software | |
21 | Foundation, Inc., 59 Temple Place - Suite 330, | |
22 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
23 | |
24 | #include "defs.h" | |
25 | #include "frame.h" | |
26 | #include "inferior.h" | |
27 | #include "symtab.h" | |
28 | #include "target.h" | |
29 | #include "gdbcore.h" | |
30 | #include "gdbcmd.h" | |
c906108c | 31 | #include "objfiles.h" |
7a78ae4e | 32 | #include "arch-utils.h" |
4e052eda | 33 | #include "regcache.h" |
d16aafd8 | 34 | #include "doublest.h" |
fd0407d6 | 35 | #include "value.h" |
1fcc0bb8 | 36 | #include "parser-defs.h" |
4be87837 | 37 | #include "osabi.h" |
7a78ae4e | 38 | |
2fccf04a | 39 | #include "libbfd.h" /* for bfd_default_set_arch_mach */ |
7a78ae4e | 40 | #include "coff/internal.h" /* for libcoff.h */ |
2fccf04a | 41 | #include "libcoff.h" /* for xcoff_data */ |
11ed25ac KB |
42 | #include "coff/xcoff.h" |
43 | #include "libxcoff.h" | |
7a78ae4e | 44 | |
9aa1e687 | 45 | #include "elf-bfd.h" |
7a78ae4e | 46 | |
6ded7999 | 47 | #include "solib-svr4.h" |
9aa1e687 | 48 | #include "ppc-tdep.h" |
7a78ae4e | 49 | |
338ef23d | 50 | #include "gdb_assert.h" |
a89aa300 | 51 | #include "dis-asm.h" |
338ef23d | 52 | |
61a65099 KB |
53 | #include "trad-frame.h" |
54 | #include "frame-unwind.h" | |
55 | #include "frame-base.h" | |
56 | ||
7a78ae4e ND |
57 | /* If the kernel has to deliver a signal, it pushes a sigcontext |
58 | structure on the stack and then calls the signal handler, passing | |
59 | the address of the sigcontext in an argument register. Usually | |
60 | the signal handler doesn't save this register, so we have to | |
61 | access the sigcontext structure via an offset from the signal handler | |
62 | frame. | |
63 | The following constants were determined by experimentation on AIX 3.2. */ | |
64 | #define SIG_FRAME_PC_OFFSET 96 | |
65 | #define SIG_FRAME_LR_OFFSET 108 | |
66 | #define SIG_FRAME_FP_OFFSET 284 | |
67 | ||
7a78ae4e ND |
68 | /* To be used by skip_prologue. */ |
69 | ||
70 | struct rs6000_framedata | |
71 | { | |
72 | int offset; /* total size of frame --- the distance | |
73 | by which we decrement sp to allocate | |
74 | the frame */ | |
75 | int saved_gpr; /* smallest # of saved gpr */ | |
76 | int saved_fpr; /* smallest # of saved fpr */ | |
6be8bc0c | 77 | int saved_vr; /* smallest # of saved vr */ |
96ff0de4 | 78 | int saved_ev; /* smallest # of saved ev */ |
7a78ae4e ND |
79 | int alloca_reg; /* alloca register number (frame ptr) */ |
80 | char frameless; /* true if frameless functions. */ | |
81 | char nosavedpc; /* true if pc not saved. */ | |
82 | int gpr_offset; /* offset of saved gprs from prev sp */ | |
83 | int fpr_offset; /* offset of saved fprs from prev sp */ | |
6be8bc0c | 84 | int vr_offset; /* offset of saved vrs from prev sp */ |
96ff0de4 | 85 | int ev_offset; /* offset of saved evs from prev sp */ |
7a78ae4e ND |
86 | int lr_offset; /* offset of saved lr */ |
87 | int cr_offset; /* offset of saved cr */ | |
6be8bc0c | 88 | int vrsave_offset; /* offset of saved vrsave register */ |
7a78ae4e ND |
89 | }; |
90 | ||
91 | /* Description of a single register. */ | |
92 | ||
93 | struct reg | |
94 | { | |
95 | char *name; /* name of register */ | |
96 | unsigned char sz32; /* size on 32-bit arch, 0 if nonextant */ | |
97 | unsigned char sz64; /* size on 64-bit arch, 0 if nonextant */ | |
98 | unsigned char fpr; /* whether register is floating-point */ | |
489461e2 | 99 | unsigned char pseudo; /* whether register is pseudo */ |
7a78ae4e ND |
100 | }; |
101 | ||
c906108c SS |
102 | /* Breakpoint shadows for the single step instructions will be kept here. */ |
103 | ||
c5aa993b JM |
104 | static struct sstep_breaks |
105 | { | |
106 | /* Address, or 0 if this is not in use. */ | |
107 | CORE_ADDR address; | |
108 | /* Shadow contents. */ | |
109 | char data[4]; | |
110 | } | |
111 | stepBreaks[2]; | |
c906108c SS |
112 | |
113 | /* Hook for determining the TOC address when calling functions in the | |
114 | inferior under AIX. The initialization code in rs6000-nat.c sets | |
115 | this hook to point to find_toc_address. */ | |
116 | ||
7a78ae4e ND |
117 | CORE_ADDR (*rs6000_find_toc_address_hook) (CORE_ADDR) = NULL; |
118 | ||
119 | /* Hook to set the current architecture when starting a child process. | |
120 | rs6000-nat.c sets this. */ | |
121 | ||
122 | void (*rs6000_set_host_arch_hook) (int) = NULL; | |
c906108c SS |
123 | |
124 | /* Static function prototypes */ | |
125 | ||
a14ed312 KB |
126 | static CORE_ADDR branch_dest (int opcode, int instr, CORE_ADDR pc, |
127 | CORE_ADDR safety); | |
077276e8 KB |
128 | static CORE_ADDR skip_prologue (CORE_ADDR, CORE_ADDR, |
129 | struct rs6000_framedata *); | |
7a78ae4e ND |
130 | static void frame_get_saved_regs (struct frame_info * fi, |
131 | struct rs6000_framedata * fdatap); | |
132 | static CORE_ADDR frame_initial_stack_address (struct frame_info *); | |
c906108c | 133 | |
64b84175 KB |
134 | /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */ |
135 | int | |
136 | altivec_register_p (int regno) | |
137 | { | |
138 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
139 | if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0) | |
140 | return 0; | |
141 | else | |
142 | return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum); | |
143 | } | |
144 | ||
0a613259 AC |
145 | /* Use the architectures FP registers? */ |
146 | int | |
147 | ppc_floating_point_unit_p (struct gdbarch *gdbarch) | |
148 | { | |
149 | const struct bfd_arch_info *info = gdbarch_bfd_arch_info (gdbarch); | |
150 | if (info->arch == bfd_arch_powerpc) | |
151 | return (info->mach != bfd_mach_ppc_e500); | |
152 | if (info->arch == bfd_arch_rs6000) | |
153 | return 1; | |
154 | return 0; | |
155 | } | |
156 | ||
7a78ae4e | 157 | /* Read a LEN-byte address from debugged memory address MEMADDR. */ |
c906108c | 158 | |
7a78ae4e ND |
159 | static CORE_ADDR |
160 | read_memory_addr (CORE_ADDR memaddr, int len) | |
161 | { | |
162 | return read_memory_unsigned_integer (memaddr, len); | |
163 | } | |
c906108c | 164 | |
7a78ae4e ND |
165 | static CORE_ADDR |
166 | rs6000_skip_prologue (CORE_ADDR pc) | |
b83266a0 SS |
167 | { |
168 | struct rs6000_framedata frame; | |
077276e8 | 169 | pc = skip_prologue (pc, 0, &frame); |
b83266a0 SS |
170 | return pc; |
171 | } | |
172 | ||
173 | ||
c906108c SS |
174 | /* Fill in fi->saved_regs */ |
175 | ||
176 | struct frame_extra_info | |
177 | { | |
178 | /* Functions calling alloca() change the value of the stack | |
179 | pointer. We need to use initial stack pointer (which is saved in | |
180 | r31 by gcc) in such cases. If a compiler emits traceback table, | |
181 | then we should use the alloca register specified in traceback | |
182 | table. FIXME. */ | |
c5aa993b | 183 | CORE_ADDR initial_sp; /* initial stack pointer. */ |
c906108c SS |
184 | }; |
185 | ||
143985b7 | 186 | /* Get the ith function argument for the current function. */ |
b9362cc7 | 187 | static CORE_ADDR |
143985b7 AF |
188 | rs6000_fetch_pointer_argument (struct frame_info *frame, int argi, |
189 | struct type *type) | |
190 | { | |
191 | CORE_ADDR addr; | |
7f5f525d | 192 | get_frame_register (frame, 3 + argi, &addr); |
143985b7 AF |
193 | return addr; |
194 | } | |
195 | ||
c906108c SS |
196 | /* Calculate the destination of a branch/jump. Return -1 if not a branch. */ |
197 | ||
198 | static CORE_ADDR | |
7a78ae4e | 199 | branch_dest (int opcode, int instr, CORE_ADDR pc, CORE_ADDR safety) |
c906108c SS |
200 | { |
201 | CORE_ADDR dest; | |
202 | int immediate; | |
203 | int absolute; | |
204 | int ext_op; | |
205 | ||
206 | absolute = (int) ((instr >> 1) & 1); | |
207 | ||
c5aa993b JM |
208 | switch (opcode) |
209 | { | |
210 | case 18: | |
211 | immediate = ((instr & ~3) << 6) >> 6; /* br unconditional */ | |
212 | if (absolute) | |
213 | dest = immediate; | |
214 | else | |
215 | dest = pc + immediate; | |
216 | break; | |
217 | ||
218 | case 16: | |
219 | immediate = ((instr & ~3) << 16) >> 16; /* br conditional */ | |
220 | if (absolute) | |
221 | dest = immediate; | |
222 | else | |
223 | dest = pc + immediate; | |
224 | break; | |
225 | ||
226 | case 19: | |
227 | ext_op = (instr >> 1) & 0x3ff; | |
228 | ||
229 | if (ext_op == 16) /* br conditional register */ | |
230 | { | |
2188cbdd | 231 | dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum) & ~3; |
c5aa993b JM |
232 | |
233 | /* If we are about to return from a signal handler, dest is | |
234 | something like 0x3c90. The current frame is a signal handler | |
235 | caller frame, upon completion of the sigreturn system call | |
236 | execution will return to the saved PC in the frame. */ | |
237 | if (dest < TEXT_SEGMENT_BASE) | |
238 | { | |
239 | struct frame_info *fi; | |
240 | ||
241 | fi = get_current_frame (); | |
242 | if (fi != NULL) | |
8b36eed8 | 243 | dest = read_memory_addr (get_frame_base (fi) + SIG_FRAME_PC_OFFSET, |
21283beb | 244 | gdbarch_tdep (current_gdbarch)->wordsize); |
c5aa993b JM |
245 | } |
246 | } | |
247 | ||
248 | else if (ext_op == 528) /* br cond to count reg */ | |
249 | { | |
2188cbdd | 250 | dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_ctr_regnum) & ~3; |
c5aa993b JM |
251 | |
252 | /* If we are about to execute a system call, dest is something | |
253 | like 0x22fc or 0x3b00. Upon completion the system call | |
254 | will return to the address in the link register. */ | |
255 | if (dest < TEXT_SEGMENT_BASE) | |
2188cbdd | 256 | dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum) & ~3; |
c5aa993b JM |
257 | } |
258 | else | |
259 | return -1; | |
260 | break; | |
c906108c | 261 | |
c5aa993b JM |
262 | default: |
263 | return -1; | |
264 | } | |
c906108c SS |
265 | return (dest < TEXT_SEGMENT_BASE) ? safety : dest; |
266 | } | |
267 | ||
268 | ||
269 | /* Sequence of bytes for breakpoint instruction. */ | |
270 | ||
f4f9705a | 271 | const static unsigned char * |
7a78ae4e | 272 | rs6000_breakpoint_from_pc (CORE_ADDR *bp_addr, int *bp_size) |
c906108c | 273 | { |
aaab4dba AC |
274 | static unsigned char big_breakpoint[] = { 0x7d, 0x82, 0x10, 0x08 }; |
275 | static unsigned char little_breakpoint[] = { 0x08, 0x10, 0x82, 0x7d }; | |
c906108c | 276 | *bp_size = 4; |
d7449b42 | 277 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
278 | return big_breakpoint; |
279 | else | |
280 | return little_breakpoint; | |
281 | } | |
282 | ||
283 | ||
284 | /* AIX does not support PT_STEP. Simulate it. */ | |
285 | ||
286 | void | |
379d08a1 AC |
287 | rs6000_software_single_step (enum target_signal signal, |
288 | int insert_breakpoints_p) | |
c906108c | 289 | { |
7c40d541 KB |
290 | CORE_ADDR dummy; |
291 | int breakp_sz; | |
f4f9705a | 292 | const char *breakp = rs6000_breakpoint_from_pc (&dummy, &breakp_sz); |
c906108c SS |
293 | int ii, insn; |
294 | CORE_ADDR loc; | |
295 | CORE_ADDR breaks[2]; | |
296 | int opcode; | |
297 | ||
c5aa993b JM |
298 | if (insert_breakpoints_p) |
299 | { | |
c906108c | 300 | |
c5aa993b | 301 | loc = read_pc (); |
c906108c | 302 | |
c5aa993b | 303 | insn = read_memory_integer (loc, 4); |
c906108c | 304 | |
7c40d541 | 305 | breaks[0] = loc + breakp_sz; |
c5aa993b JM |
306 | opcode = insn >> 26; |
307 | breaks[1] = branch_dest (opcode, insn, loc, breaks[0]); | |
c906108c | 308 | |
c5aa993b JM |
309 | /* Don't put two breakpoints on the same address. */ |
310 | if (breaks[1] == breaks[0]) | |
311 | breaks[1] = -1; | |
c906108c | 312 | |
c5aa993b | 313 | stepBreaks[1].address = 0; |
c906108c | 314 | |
c5aa993b JM |
315 | for (ii = 0; ii < 2; ++ii) |
316 | { | |
c906108c | 317 | |
c5aa993b JM |
318 | /* ignore invalid breakpoint. */ |
319 | if (breaks[ii] == -1) | |
320 | continue; | |
7c40d541 | 321 | target_insert_breakpoint (breaks[ii], stepBreaks[ii].data); |
c5aa993b JM |
322 | stepBreaks[ii].address = breaks[ii]; |
323 | } | |
c906108c | 324 | |
c5aa993b JM |
325 | } |
326 | else | |
327 | { | |
c906108c | 328 | |
c5aa993b JM |
329 | /* remove step breakpoints. */ |
330 | for (ii = 0; ii < 2; ++ii) | |
331 | if (stepBreaks[ii].address != 0) | |
7c40d541 KB |
332 | target_remove_breakpoint (stepBreaks[ii].address, |
333 | stepBreaks[ii].data); | |
c5aa993b | 334 | } |
c906108c | 335 | errno = 0; /* FIXME, don't ignore errors! */ |
c5aa993b | 336 | /* What errors? {read,write}_memory call error(). */ |
c906108c SS |
337 | } |
338 | ||
339 | ||
340 | /* return pc value after skipping a function prologue and also return | |
341 | information about a function frame. | |
342 | ||
343 | in struct rs6000_framedata fdata: | |
c5aa993b JM |
344 | - frameless is TRUE, if function does not have a frame. |
345 | - nosavedpc is TRUE, if function does not save %pc value in its frame. | |
346 | - offset is the initial size of this stack frame --- the amount by | |
347 | which we decrement the sp to allocate the frame. | |
348 | - saved_gpr is the number of the first saved gpr. | |
349 | - saved_fpr is the number of the first saved fpr. | |
6be8bc0c | 350 | - saved_vr is the number of the first saved vr. |
96ff0de4 | 351 | - saved_ev is the number of the first saved ev. |
c5aa993b JM |
352 | - alloca_reg is the number of the register used for alloca() handling. |
353 | Otherwise -1. | |
354 | - gpr_offset is the offset of the first saved gpr from the previous frame. | |
355 | - fpr_offset is the offset of the first saved fpr from the previous frame. | |
6be8bc0c | 356 | - vr_offset is the offset of the first saved vr from the previous frame. |
96ff0de4 | 357 | - ev_offset is the offset of the first saved ev from the previous frame. |
c5aa993b JM |
358 | - lr_offset is the offset of the saved lr |
359 | - cr_offset is the offset of the saved cr | |
6be8bc0c | 360 | - vrsave_offset is the offset of the saved vrsave register |
c5aa993b | 361 | */ |
c906108c SS |
362 | |
363 | #define SIGNED_SHORT(x) \ | |
364 | ((sizeof (short) == 2) \ | |
365 | ? ((int)(short)(x)) \ | |
366 | : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000))) | |
367 | ||
368 | #define GET_SRC_REG(x) (((x) >> 21) & 0x1f) | |
369 | ||
55d05f3b KB |
370 | /* Limit the number of skipped non-prologue instructions, as the examining |
371 | of the prologue is expensive. */ | |
372 | static int max_skip_non_prologue_insns = 10; | |
373 | ||
374 | /* Given PC representing the starting address of a function, and | |
375 | LIM_PC which is the (sloppy) limit to which to scan when looking | |
376 | for a prologue, attempt to further refine this limit by using | |
377 | the line data in the symbol table. If successful, a better guess | |
378 | on where the prologue ends is returned, otherwise the previous | |
379 | value of lim_pc is returned. */ | |
634aa483 AC |
380 | |
381 | /* FIXME: cagney/2004-02-14: This function and logic have largely been | |
382 | superseded by skip_prologue_using_sal. */ | |
383 | ||
55d05f3b KB |
384 | static CORE_ADDR |
385 | refine_prologue_limit (CORE_ADDR pc, CORE_ADDR lim_pc) | |
386 | { | |
387 | struct symtab_and_line prologue_sal; | |
388 | ||
389 | prologue_sal = find_pc_line (pc, 0); | |
390 | if (prologue_sal.line != 0) | |
391 | { | |
392 | int i; | |
393 | CORE_ADDR addr = prologue_sal.end; | |
394 | ||
395 | /* Handle the case in which compiler's optimizer/scheduler | |
396 | has moved instructions into the prologue. We scan ahead | |
397 | in the function looking for address ranges whose corresponding | |
398 | line number is less than or equal to the first one that we | |
399 | found for the function. (It can be less than when the | |
400 | scheduler puts a body instruction before the first prologue | |
401 | instruction.) */ | |
402 | for (i = 2 * max_skip_non_prologue_insns; | |
403 | i > 0 && (lim_pc == 0 || addr < lim_pc); | |
404 | i--) | |
405 | { | |
406 | struct symtab_and_line sal; | |
407 | ||
408 | sal = find_pc_line (addr, 0); | |
409 | if (sal.line == 0) | |
410 | break; | |
411 | if (sal.line <= prologue_sal.line | |
412 | && sal.symtab == prologue_sal.symtab) | |
413 | { | |
414 | prologue_sal = sal; | |
415 | } | |
416 | addr = sal.end; | |
417 | } | |
418 | ||
419 | if (lim_pc == 0 || prologue_sal.end < lim_pc) | |
420 | lim_pc = prologue_sal.end; | |
421 | } | |
422 | return lim_pc; | |
423 | } | |
424 | ||
425 | ||
7a78ae4e | 426 | static CORE_ADDR |
077276e8 | 427 | skip_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct rs6000_framedata *fdata) |
c906108c SS |
428 | { |
429 | CORE_ADDR orig_pc = pc; | |
55d05f3b | 430 | CORE_ADDR last_prologue_pc = pc; |
6be8bc0c | 431 | CORE_ADDR li_found_pc = 0; |
c906108c SS |
432 | char buf[4]; |
433 | unsigned long op; | |
434 | long offset = 0; | |
6be8bc0c | 435 | long vr_saved_offset = 0; |
482ca3f5 KB |
436 | int lr_reg = -1; |
437 | int cr_reg = -1; | |
6be8bc0c | 438 | int vr_reg = -1; |
96ff0de4 EZ |
439 | int ev_reg = -1; |
440 | long ev_offset = 0; | |
6be8bc0c | 441 | int vrsave_reg = -1; |
c906108c SS |
442 | int reg; |
443 | int framep = 0; | |
444 | int minimal_toc_loaded = 0; | |
ddb20c56 | 445 | int prev_insn_was_prologue_insn = 1; |
55d05f3b | 446 | int num_skip_non_prologue_insns = 0; |
96ff0de4 | 447 | const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (current_gdbarch); |
6f99cb26 | 448 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
96ff0de4 | 449 | |
55d05f3b KB |
450 | /* Attempt to find the end of the prologue when no limit is specified. |
451 | Note that refine_prologue_limit() has been written so that it may | |
452 | be used to "refine" the limits of non-zero PC values too, but this | |
453 | is only safe if we 1) trust the line information provided by the | |
454 | compiler and 2) iterate enough to actually find the end of the | |
455 | prologue. | |
456 | ||
457 | It may become a good idea at some point (for both performance and | |
458 | accuracy) to unconditionally call refine_prologue_limit(). But, | |
459 | until we can make a clear determination that this is beneficial, | |
460 | we'll play it safe and only use it to obtain a limit when none | |
461 | has been specified. */ | |
462 | if (lim_pc == 0) | |
463 | lim_pc = refine_prologue_limit (pc, lim_pc); | |
c906108c | 464 | |
ddb20c56 | 465 | memset (fdata, 0, sizeof (struct rs6000_framedata)); |
c906108c SS |
466 | fdata->saved_gpr = -1; |
467 | fdata->saved_fpr = -1; | |
6be8bc0c | 468 | fdata->saved_vr = -1; |
96ff0de4 | 469 | fdata->saved_ev = -1; |
c906108c SS |
470 | fdata->alloca_reg = -1; |
471 | fdata->frameless = 1; | |
472 | fdata->nosavedpc = 1; | |
473 | ||
55d05f3b | 474 | for (;; pc += 4) |
c906108c | 475 | { |
ddb20c56 KB |
476 | /* Sometimes it isn't clear if an instruction is a prologue |
477 | instruction or not. When we encounter one of these ambiguous | |
478 | cases, we'll set prev_insn_was_prologue_insn to 0 (false). | |
479 | Otherwise, we'll assume that it really is a prologue instruction. */ | |
480 | if (prev_insn_was_prologue_insn) | |
481 | last_prologue_pc = pc; | |
55d05f3b KB |
482 | |
483 | /* Stop scanning if we've hit the limit. */ | |
484 | if (lim_pc != 0 && pc >= lim_pc) | |
485 | break; | |
486 | ||
ddb20c56 KB |
487 | prev_insn_was_prologue_insn = 1; |
488 | ||
55d05f3b | 489 | /* Fetch the instruction and convert it to an integer. */ |
ddb20c56 KB |
490 | if (target_read_memory (pc, buf, 4)) |
491 | break; | |
492 | op = extract_signed_integer (buf, 4); | |
c906108c | 493 | |
c5aa993b JM |
494 | if ((op & 0xfc1fffff) == 0x7c0802a6) |
495 | { /* mflr Rx */ | |
43b1ab88 AC |
496 | /* Since shared library / PIC code, which needs to get its |
497 | address at runtime, can appear to save more than one link | |
498 | register vis: | |
499 | ||
500 | *INDENT-OFF* | |
501 | stwu r1,-304(r1) | |
502 | mflr r3 | |
503 | bl 0xff570d0 (blrl) | |
504 | stw r30,296(r1) | |
505 | mflr r30 | |
506 | stw r31,300(r1) | |
507 | stw r3,308(r1); | |
508 | ... | |
509 | *INDENT-ON* | |
510 | ||
511 | remember just the first one, but skip over additional | |
512 | ones. */ | |
513 | if (lr_reg < 0) | |
514 | lr_reg = (op & 0x03e00000); | |
c5aa993b | 515 | continue; |
c5aa993b JM |
516 | } |
517 | else if ((op & 0xfc1fffff) == 0x7c000026) | |
518 | { /* mfcr Rx */ | |
98f08d3d | 519 | cr_reg = (op & 0x03e00000); |
c5aa993b | 520 | continue; |
c906108c | 521 | |
c906108c | 522 | } |
c5aa993b JM |
523 | else if ((op & 0xfc1f0000) == 0xd8010000) |
524 | { /* stfd Rx,NUM(r1) */ | |
525 | reg = GET_SRC_REG (op); | |
526 | if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg) | |
527 | { | |
528 | fdata->saved_fpr = reg; | |
529 | fdata->fpr_offset = SIGNED_SHORT (op) + offset; | |
530 | } | |
531 | continue; | |
c906108c | 532 | |
c5aa993b JM |
533 | } |
534 | else if (((op & 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */ | |
7a78ae4e ND |
535 | (((op & 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */ |
536 | (op & 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */ | |
537 | (op & 0x03e00000) >= 0x01a00000)) /* rx >= r13 */ | |
c5aa993b JM |
538 | { |
539 | ||
540 | reg = GET_SRC_REG (op); | |
541 | if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg) | |
542 | { | |
543 | fdata->saved_gpr = reg; | |
7a78ae4e | 544 | if ((op & 0xfc1f0003) == 0xf8010000) |
98f08d3d | 545 | op &= ~3UL; |
c5aa993b JM |
546 | fdata->gpr_offset = SIGNED_SHORT (op) + offset; |
547 | } | |
548 | continue; | |
c906108c | 549 | |
ddb20c56 KB |
550 | } |
551 | else if ((op & 0xffff0000) == 0x60000000) | |
552 | { | |
96ff0de4 | 553 | /* nop */ |
ddb20c56 KB |
554 | /* Allow nops in the prologue, but do not consider them to |
555 | be part of the prologue unless followed by other prologue | |
556 | instructions. */ | |
557 | prev_insn_was_prologue_insn = 0; | |
558 | continue; | |
559 | ||
c906108c | 560 | } |
c5aa993b JM |
561 | else if ((op & 0xffff0000) == 0x3c000000) |
562 | { /* addis 0,0,NUM, used | |
563 | for >= 32k frames */ | |
564 | fdata->offset = (op & 0x0000ffff) << 16; | |
565 | fdata->frameless = 0; | |
566 | continue; | |
567 | ||
568 | } | |
569 | else if ((op & 0xffff0000) == 0x60000000) | |
570 | { /* ori 0,0,NUM, 2nd ha | |
571 | lf of >= 32k frames */ | |
572 | fdata->offset |= (op & 0x0000ffff); | |
573 | fdata->frameless = 0; | |
574 | continue; | |
575 | ||
576 | } | |
98f08d3d KB |
577 | else if (lr_reg != -1 && |
578 | /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */ | |
579 | (((op & 0xffff0000) == (lr_reg | 0xf8010000)) || | |
580 | /* stw Rx, NUM(r1) */ | |
581 | ((op & 0xffff0000) == (lr_reg | 0x90010000)) || | |
582 | /* stwu Rx, NUM(r1) */ | |
583 | ((op & 0xffff0000) == (lr_reg | 0x94010000)))) | |
584 | { /* where Rx == lr */ | |
585 | fdata->lr_offset = offset; | |
c5aa993b JM |
586 | fdata->nosavedpc = 0; |
587 | lr_reg = 0; | |
98f08d3d KB |
588 | if ((op & 0xfc000003) == 0xf8000000 || /* std */ |
589 | (op & 0xfc000000) == 0x90000000) /* stw */ | |
590 | { | |
591 | /* Does not update r1, so add displacement to lr_offset. */ | |
592 | fdata->lr_offset += SIGNED_SHORT (op); | |
593 | } | |
c5aa993b JM |
594 | continue; |
595 | ||
596 | } | |
98f08d3d KB |
597 | else if (cr_reg != -1 && |
598 | /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */ | |
599 | (((op & 0xffff0000) == (cr_reg | 0xf8010000)) || | |
600 | /* stw Rx, NUM(r1) */ | |
601 | ((op & 0xffff0000) == (cr_reg | 0x90010000)) || | |
602 | /* stwu Rx, NUM(r1) */ | |
603 | ((op & 0xffff0000) == (cr_reg | 0x94010000)))) | |
604 | { /* where Rx == cr */ | |
605 | fdata->cr_offset = offset; | |
c5aa993b | 606 | cr_reg = 0; |
98f08d3d KB |
607 | if ((op & 0xfc000003) == 0xf8000000 || |
608 | (op & 0xfc000000) == 0x90000000) | |
609 | { | |
610 | /* Does not update r1, so add displacement to cr_offset. */ | |
611 | fdata->cr_offset += SIGNED_SHORT (op); | |
612 | } | |
c5aa993b JM |
613 | continue; |
614 | ||
615 | } | |
616 | else if (op == 0x48000005) | |
617 | { /* bl .+4 used in | |
618 | -mrelocatable */ | |
619 | continue; | |
620 | ||
621 | } | |
622 | else if (op == 0x48000004) | |
623 | { /* b .+4 (xlc) */ | |
624 | break; | |
625 | ||
c5aa993b | 626 | } |
6be8bc0c EZ |
627 | else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used |
628 | in V.4 -mminimal-toc */ | |
c5aa993b JM |
629 | (op & 0xffff0000) == 0x3bde0000) |
630 | { /* addi 30,30,foo@l */ | |
631 | continue; | |
c906108c | 632 | |
c5aa993b JM |
633 | } |
634 | else if ((op & 0xfc000001) == 0x48000001) | |
635 | { /* bl foo, | |
636 | to save fprs??? */ | |
c906108c | 637 | |
c5aa993b | 638 | fdata->frameless = 0; |
6be8bc0c EZ |
639 | /* Don't skip over the subroutine call if it is not within |
640 | the first three instructions of the prologue. */ | |
c5aa993b JM |
641 | if ((pc - orig_pc) > 8) |
642 | break; | |
643 | ||
644 | op = read_memory_integer (pc + 4, 4); | |
645 | ||
6be8bc0c EZ |
646 | /* At this point, make sure this is not a trampoline |
647 | function (a function that simply calls another functions, | |
648 | and nothing else). If the next is not a nop, this branch | |
649 | was part of the function prologue. */ | |
c5aa993b JM |
650 | |
651 | if (op == 0x4def7b82 || op == 0) /* crorc 15, 15, 15 */ | |
652 | break; /* don't skip over | |
653 | this branch */ | |
654 | continue; | |
655 | ||
c5aa993b | 656 | } |
98f08d3d KB |
657 | /* update stack pointer */ |
658 | else if ((op & 0xfc1f0000) == 0x94010000) | |
659 | { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */ | |
c5aa993b JM |
660 | fdata->frameless = 0; |
661 | fdata->offset = SIGNED_SHORT (op); | |
662 | offset = fdata->offset; | |
663 | continue; | |
c5aa993b | 664 | } |
98f08d3d KB |
665 | else if ((op & 0xfc1f016a) == 0x7c01016e) |
666 | { /* stwux rX,r1,rY */ | |
667 | /* no way to figure out what r1 is going to be */ | |
668 | fdata->frameless = 0; | |
669 | offset = fdata->offset; | |
670 | continue; | |
671 | } | |
672 | else if ((op & 0xfc1f0003) == 0xf8010001) | |
673 | { /* stdu rX,NUM(r1) */ | |
674 | fdata->frameless = 0; | |
675 | fdata->offset = SIGNED_SHORT (op & ~3UL); | |
676 | offset = fdata->offset; | |
677 | continue; | |
678 | } | |
679 | else if ((op & 0xfc1f016a) == 0x7c01016a) | |
680 | { /* stdux rX,r1,rY */ | |
681 | /* no way to figure out what r1 is going to be */ | |
c5aa993b JM |
682 | fdata->frameless = 0; |
683 | offset = fdata->offset; | |
684 | continue; | |
c5aa993b | 685 | } |
98f08d3d KB |
686 | /* Load up minimal toc pointer */ |
687 | else if (((op >> 22) == 0x20f || /* l r31,... or l r30,... */ | |
688 | (op >> 22) == 0x3af) /* ld r31,... or ld r30,... */ | |
c5aa993b | 689 | && !minimal_toc_loaded) |
98f08d3d | 690 | { |
c5aa993b JM |
691 | minimal_toc_loaded = 1; |
692 | continue; | |
693 | ||
f6077098 KB |
694 | /* move parameters from argument registers to local variable |
695 | registers */ | |
696 | } | |
697 | else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */ | |
698 | (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */ | |
699 | (((op >> 21) & 31) <= 10) && | |
96ff0de4 | 700 | ((long) ((op >> 16) & 31) >= fdata->saved_gpr)) /* Rx: local var reg */ |
f6077098 KB |
701 | { |
702 | continue; | |
703 | ||
c5aa993b JM |
704 | /* store parameters in stack */ |
705 | } | |
6be8bc0c | 706 | else if ((op & 0xfc1f0003) == 0xf8010000 || /* std rx,NUM(r1) */ |
c5aa993b | 707 | (op & 0xfc1f0000) == 0xd8010000 || /* stfd Rx,NUM(r1) */ |
7a78ae4e ND |
708 | (op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */ |
709 | { | |
c5aa993b | 710 | continue; |
c906108c | 711 | |
c5aa993b JM |
712 | /* store parameters in stack via frame pointer */ |
713 | } | |
714 | else if (framep && | |
715 | ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r1) */ | |
716 | (op & 0xfc1f0000) == 0xd81f0000 || /* stfd Rx,NUM(r1) */ | |
717 | (op & 0xfc1f0000) == 0xfc1f0000)) | |
718 | { /* frsp, fp?,NUM(r1) */ | |
719 | continue; | |
720 | ||
721 | /* Set up frame pointer */ | |
722 | } | |
723 | else if (op == 0x603f0000 /* oril r31, r1, 0x0 */ | |
724 | || op == 0x7c3f0b78) | |
725 | { /* mr r31, r1 */ | |
726 | fdata->frameless = 0; | |
727 | framep = 1; | |
6f99cb26 | 728 | fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31); |
c5aa993b JM |
729 | continue; |
730 | ||
731 | /* Another way to set up the frame pointer. */ | |
732 | } | |
733 | else if ((op & 0xfc1fffff) == 0x38010000) | |
734 | { /* addi rX, r1, 0x0 */ | |
735 | fdata->frameless = 0; | |
736 | framep = 1; | |
6f99cb26 AC |
737 | fdata->alloca_reg = (tdep->ppc_gp0_regnum |
738 | + ((op & ~0x38010000) >> 21)); | |
c5aa993b | 739 | continue; |
c5aa993b | 740 | } |
6be8bc0c EZ |
741 | /* AltiVec related instructions. */ |
742 | /* Store the vrsave register (spr 256) in another register for | |
743 | later manipulation, or load a register into the vrsave | |
744 | register. 2 instructions are used: mfvrsave and | |
745 | mtvrsave. They are shorthand notation for mfspr Rn, SPR256 | |
746 | and mtspr SPR256, Rn. */ | |
747 | /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110 | |
748 | mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */ | |
749 | else if ((op & 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */ | |
750 | { | |
751 | vrsave_reg = GET_SRC_REG (op); | |
752 | continue; | |
753 | } | |
754 | else if ((op & 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */ | |
755 | { | |
756 | continue; | |
757 | } | |
758 | /* Store the register where vrsave was saved to onto the stack: | |
759 | rS is the register where vrsave was stored in a previous | |
760 | instruction. */ | |
761 | /* 100100 sssss 00001 dddddddd dddddddd */ | |
762 | else if ((op & 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */ | |
763 | { | |
764 | if (vrsave_reg == GET_SRC_REG (op)) | |
765 | { | |
766 | fdata->vrsave_offset = SIGNED_SHORT (op) + offset; | |
767 | vrsave_reg = -1; | |
768 | } | |
769 | continue; | |
770 | } | |
771 | /* Compute the new value of vrsave, by modifying the register | |
772 | where vrsave was saved to. */ | |
773 | else if (((op & 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */ | |
774 | || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */ | |
775 | { | |
776 | continue; | |
777 | } | |
778 | /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first | |
779 | in a pair of insns to save the vector registers on the | |
780 | stack. */ | |
781 | /* 001110 00000 00000 iiii iiii iiii iiii */ | |
96ff0de4 EZ |
782 | /* 001110 01110 00000 iiii iiii iiii iiii */ |
783 | else if ((op & 0xffff0000) == 0x38000000 /* li r0, SIMM */ | |
784 | || (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */ | |
6be8bc0c EZ |
785 | { |
786 | li_found_pc = pc; | |
787 | vr_saved_offset = SIGNED_SHORT (op); | |
788 | } | |
789 | /* Store vector register S at (r31+r0) aligned to 16 bytes. */ | |
790 | /* 011111 sssss 11111 00000 00111001110 */ | |
791 | else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */ | |
792 | { | |
793 | if (pc == (li_found_pc + 4)) | |
794 | { | |
795 | vr_reg = GET_SRC_REG (op); | |
796 | /* If this is the first vector reg to be saved, or if | |
797 | it has a lower number than others previously seen, | |
798 | reupdate the frame info. */ | |
799 | if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg) | |
800 | { | |
801 | fdata->saved_vr = vr_reg; | |
802 | fdata->vr_offset = vr_saved_offset + offset; | |
803 | } | |
804 | vr_saved_offset = -1; | |
805 | vr_reg = -1; | |
806 | li_found_pc = 0; | |
807 | } | |
808 | } | |
809 | /* End AltiVec related instructions. */ | |
96ff0de4 EZ |
810 | |
811 | /* Start BookE related instructions. */ | |
812 | /* Store gen register S at (r31+uimm). | |
813 | Any register less than r13 is volatile, so we don't care. */ | |
814 | /* 000100 sssss 11111 iiiii 01100100001 */ | |
815 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
816 | && (op & 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */ | |
817 | { | |
818 | if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */ | |
819 | { | |
820 | unsigned int imm; | |
821 | ev_reg = GET_SRC_REG (op); | |
822 | imm = (op >> 11) & 0x1f; | |
823 | ev_offset = imm * 8; | |
824 | /* If this is the first vector reg to be saved, or if | |
825 | it has a lower number than others previously seen, | |
826 | reupdate the frame info. */ | |
827 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) | |
828 | { | |
829 | fdata->saved_ev = ev_reg; | |
830 | fdata->ev_offset = ev_offset + offset; | |
831 | } | |
832 | } | |
833 | continue; | |
834 | } | |
835 | /* Store gen register rS at (r1+rB). */ | |
836 | /* 000100 sssss 00001 bbbbb 01100100000 */ | |
837 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
838 | && (op & 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */ | |
839 | { | |
840 | if (pc == (li_found_pc + 4)) | |
841 | { | |
842 | ev_reg = GET_SRC_REG (op); | |
843 | /* If this is the first vector reg to be saved, or if | |
844 | it has a lower number than others previously seen, | |
845 | reupdate the frame info. */ | |
846 | /* We know the contents of rB from the previous instruction. */ | |
847 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) | |
848 | { | |
849 | fdata->saved_ev = ev_reg; | |
850 | fdata->ev_offset = vr_saved_offset + offset; | |
851 | } | |
852 | vr_saved_offset = -1; | |
853 | ev_reg = -1; | |
854 | li_found_pc = 0; | |
855 | } | |
856 | continue; | |
857 | } | |
858 | /* Store gen register r31 at (rA+uimm). */ | |
859 | /* 000100 11111 aaaaa iiiii 01100100001 */ | |
860 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
861 | && (op & 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */ | |
862 | { | |
863 | /* Wwe know that the source register is 31 already, but | |
864 | it can't hurt to compute it. */ | |
865 | ev_reg = GET_SRC_REG (op); | |
866 | ev_offset = ((op >> 11) & 0x1f) * 8; | |
867 | /* If this is the first vector reg to be saved, or if | |
868 | it has a lower number than others previously seen, | |
869 | reupdate the frame info. */ | |
870 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) | |
871 | { | |
872 | fdata->saved_ev = ev_reg; | |
873 | fdata->ev_offset = ev_offset + offset; | |
874 | } | |
875 | ||
876 | continue; | |
877 | } | |
878 | /* Store gen register S at (r31+r0). | |
879 | Store param on stack when offset from SP bigger than 4 bytes. */ | |
880 | /* 000100 sssss 11111 00000 01100100000 */ | |
881 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
882 | && (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */ | |
883 | { | |
884 | if (pc == (li_found_pc + 4)) | |
885 | { | |
886 | if ((op & 0x03e00000) >= 0x01a00000) | |
887 | { | |
888 | ev_reg = GET_SRC_REG (op); | |
889 | /* If this is the first vector reg to be saved, or if | |
890 | it has a lower number than others previously seen, | |
891 | reupdate the frame info. */ | |
892 | /* We know the contents of r0 from the previous | |
893 | instruction. */ | |
894 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) | |
895 | { | |
896 | fdata->saved_ev = ev_reg; | |
897 | fdata->ev_offset = vr_saved_offset + offset; | |
898 | } | |
899 | ev_reg = -1; | |
900 | } | |
901 | vr_saved_offset = -1; | |
902 | li_found_pc = 0; | |
903 | continue; | |
904 | } | |
905 | } | |
906 | /* End BookE related instructions. */ | |
907 | ||
c5aa993b JM |
908 | else |
909 | { | |
55d05f3b KB |
910 | /* Not a recognized prologue instruction. |
911 | Handle optimizer code motions into the prologue by continuing | |
912 | the search if we have no valid frame yet or if the return | |
913 | address is not yet saved in the frame. */ | |
914 | if (fdata->frameless == 0 | |
915 | && (lr_reg == -1 || fdata->nosavedpc == 0)) | |
916 | break; | |
917 | ||
918 | if (op == 0x4e800020 /* blr */ | |
919 | || op == 0x4e800420) /* bctr */ | |
920 | /* Do not scan past epilogue in frameless functions or | |
921 | trampolines. */ | |
922 | break; | |
923 | if ((op & 0xf4000000) == 0x40000000) /* bxx */ | |
64366f1c | 924 | /* Never skip branches. */ |
55d05f3b KB |
925 | break; |
926 | ||
927 | if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns) | |
928 | /* Do not scan too many insns, scanning insns is expensive with | |
929 | remote targets. */ | |
930 | break; | |
931 | ||
932 | /* Continue scanning. */ | |
933 | prev_insn_was_prologue_insn = 0; | |
934 | continue; | |
c5aa993b | 935 | } |
c906108c SS |
936 | } |
937 | ||
938 | #if 0 | |
939 | /* I have problems with skipping over __main() that I need to address | |
940 | * sometime. Previously, I used to use misc_function_vector which | |
941 | * didn't work as well as I wanted to be. -MGO */ | |
942 | ||
943 | /* If the first thing after skipping a prolog is a branch to a function, | |
944 | this might be a call to an initializer in main(), introduced by gcc2. | |
64366f1c | 945 | We'd like to skip over it as well. Fortunately, xlc does some extra |
c906108c | 946 | work before calling a function right after a prologue, thus we can |
64366f1c | 947 | single out such gcc2 behaviour. */ |
c906108c | 948 | |
c906108c | 949 | |
c5aa993b JM |
950 | if ((op & 0xfc000001) == 0x48000001) |
951 | { /* bl foo, an initializer function? */ | |
952 | op = read_memory_integer (pc + 4, 4); | |
953 | ||
954 | if (op == 0x4def7b82) | |
955 | { /* cror 0xf, 0xf, 0xf (nop) */ | |
c906108c | 956 | |
64366f1c EZ |
957 | /* Check and see if we are in main. If so, skip over this |
958 | initializer function as well. */ | |
c906108c | 959 | |
c5aa993b | 960 | tmp = find_pc_misc_function (pc); |
6314a349 AC |
961 | if (tmp >= 0 |
962 | && strcmp (misc_function_vector[tmp].name, main_name ()) == 0) | |
c5aa993b JM |
963 | return pc + 8; |
964 | } | |
c906108c | 965 | } |
c906108c | 966 | #endif /* 0 */ |
c5aa993b JM |
967 | |
968 | fdata->offset = -fdata->offset; | |
ddb20c56 | 969 | return last_prologue_pc; |
c906108c SS |
970 | } |
971 | ||
972 | ||
973 | /************************************************************************* | |
f6077098 | 974 | Support for creating pushing a dummy frame into the stack, and popping |
c906108c SS |
975 | frames, etc. |
976 | *************************************************************************/ | |
977 | ||
c906108c | 978 | |
11269d7e AC |
979 | /* All the ABI's require 16 byte alignment. */ |
980 | static CORE_ADDR | |
981 | rs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
982 | { | |
983 | return (addr & -16); | |
984 | } | |
985 | ||
7a78ae4e | 986 | /* Pass the arguments in either registers, or in the stack. In RS/6000, |
c906108c SS |
987 | the first eight words of the argument list (that might be less than |
988 | eight parameters if some parameters occupy more than one word) are | |
7a78ae4e | 989 | passed in r3..r10 registers. float and double parameters are |
64366f1c EZ |
990 | passed in fpr's, in addition to that. Rest of the parameters if any |
991 | are passed in user stack. There might be cases in which half of the | |
c906108c SS |
992 | parameter is copied into registers, the other half is pushed into |
993 | stack. | |
994 | ||
7a78ae4e ND |
995 | Stack must be aligned on 64-bit boundaries when synthesizing |
996 | function calls. | |
997 | ||
c906108c SS |
998 | If the function is returning a structure, then the return address is passed |
999 | in r3, then the first 7 words of the parameters can be passed in registers, | |
64366f1c | 1000 | starting from r4. */ |
c906108c | 1001 | |
7a78ae4e | 1002 | static CORE_ADDR |
77b2b6d4 AC |
1003 | rs6000_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, |
1004 | struct regcache *regcache, CORE_ADDR bp_addr, | |
1005 | int nargs, struct value **args, CORE_ADDR sp, | |
1006 | int struct_return, CORE_ADDR struct_addr) | |
c906108c | 1007 | { |
7a41266b | 1008 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c SS |
1009 | int ii; |
1010 | int len = 0; | |
c5aa993b JM |
1011 | int argno; /* current argument number */ |
1012 | int argbytes; /* current argument byte */ | |
1013 | char tmp_buffer[50]; | |
1014 | int f_argno = 0; /* current floating point argno */ | |
21283beb | 1015 | int wordsize = gdbarch_tdep (current_gdbarch)->wordsize; |
c906108c | 1016 | |
ea7c478f | 1017 | struct value *arg = 0; |
c906108c SS |
1018 | struct type *type; |
1019 | ||
1020 | CORE_ADDR saved_sp; | |
1021 | ||
64366f1c | 1022 | /* The first eight words of ther arguments are passed in registers. |
7a41266b AC |
1023 | Copy them appropriately. */ |
1024 | ii = 0; | |
1025 | ||
1026 | /* If the function is returning a `struct', then the first word | |
1027 | (which will be passed in r3) is used for struct return address. | |
1028 | In that case we should advance one word and start from r4 | |
1029 | register to copy parameters. */ | |
1030 | if (struct_return) | |
1031 | { | |
1032 | regcache_raw_write_unsigned (regcache, tdep->ppc_gp0_regnum + 3, | |
1033 | struct_addr); | |
1034 | ii++; | |
1035 | } | |
c906108c SS |
1036 | |
1037 | /* | |
c5aa993b JM |
1038 | effectively indirect call... gcc does... |
1039 | ||
1040 | return_val example( float, int); | |
1041 | ||
1042 | eabi: | |
1043 | float in fp0, int in r3 | |
1044 | offset of stack on overflow 8/16 | |
1045 | for varargs, must go by type. | |
1046 | power open: | |
1047 | float in r3&r4, int in r5 | |
1048 | offset of stack on overflow different | |
1049 | both: | |
1050 | return in r3 or f0. If no float, must study how gcc emulates floats; | |
1051 | pay attention to arg promotion. | |
1052 | User may have to cast\args to handle promotion correctly | |
1053 | since gdb won't know if prototype supplied or not. | |
1054 | */ | |
c906108c | 1055 | |
c5aa993b JM |
1056 | for (argno = 0, argbytes = 0; argno < nargs && ii < 8; ++ii) |
1057 | { | |
12c266ea | 1058 | int reg_size = DEPRECATED_REGISTER_RAW_SIZE (ii + 3); |
c5aa993b JM |
1059 | |
1060 | arg = args[argno]; | |
1061 | type = check_typedef (VALUE_TYPE (arg)); | |
1062 | len = TYPE_LENGTH (type); | |
1063 | ||
1064 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
1065 | { | |
1066 | ||
64366f1c | 1067 | /* Floating point arguments are passed in fpr's, as well as gpr's. |
c5aa993b | 1068 | There are 13 fpr's reserved for passing parameters. At this point |
64366f1c | 1069 | there is no way we would run out of them. */ |
c5aa993b JM |
1070 | |
1071 | if (len > 8) | |
1072 | printf_unfiltered ( | |
1073 | "Fatal Error: a floating point parameter #%d with a size > 8 is found!\n", argno); | |
1074 | ||
62700349 | 1075 | memcpy (&deprecated_registers[DEPRECATED_REGISTER_BYTE (FP0_REGNUM + 1 + f_argno)], |
c5aa993b JM |
1076 | VALUE_CONTENTS (arg), |
1077 | len); | |
1078 | ++f_argno; | |
1079 | } | |
1080 | ||
f6077098 | 1081 | if (len > reg_size) |
c5aa993b JM |
1082 | { |
1083 | ||
64366f1c | 1084 | /* Argument takes more than one register. */ |
c5aa993b JM |
1085 | while (argbytes < len) |
1086 | { | |
62700349 | 1087 | memset (&deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + 3)], 0, |
524d7c18 | 1088 | reg_size); |
62700349 | 1089 | memcpy (&deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + 3)], |
c5aa993b | 1090 | ((char *) VALUE_CONTENTS (arg)) + argbytes, |
f6077098 KB |
1091 | (len - argbytes) > reg_size |
1092 | ? reg_size : len - argbytes); | |
1093 | ++ii, argbytes += reg_size; | |
c5aa993b JM |
1094 | |
1095 | if (ii >= 8) | |
1096 | goto ran_out_of_registers_for_arguments; | |
1097 | } | |
1098 | argbytes = 0; | |
1099 | --ii; | |
1100 | } | |
1101 | else | |
64366f1c EZ |
1102 | { |
1103 | /* Argument can fit in one register. No problem. */ | |
d7449b42 | 1104 | int adj = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? reg_size - len : 0; |
62700349 AC |
1105 | memset (&deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + 3)], 0, reg_size); |
1106 | memcpy ((char *)&deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + 3)] + adj, | |
f6077098 | 1107 | VALUE_CONTENTS (arg), len); |
c5aa993b JM |
1108 | } |
1109 | ++argno; | |
c906108c | 1110 | } |
c906108c SS |
1111 | |
1112 | ran_out_of_registers_for_arguments: | |
1113 | ||
7a78ae4e | 1114 | saved_sp = read_sp (); |
cc9836a8 | 1115 | |
64366f1c | 1116 | /* Location for 8 parameters are always reserved. */ |
7a78ae4e | 1117 | sp -= wordsize * 8; |
f6077098 | 1118 | |
64366f1c | 1119 | /* Another six words for back chain, TOC register, link register, etc. */ |
7a78ae4e | 1120 | sp -= wordsize * 6; |
f6077098 | 1121 | |
64366f1c | 1122 | /* Stack pointer must be quadword aligned. */ |
7a78ae4e | 1123 | sp &= -16; |
c906108c | 1124 | |
64366f1c EZ |
1125 | /* If there are more arguments, allocate space for them in |
1126 | the stack, then push them starting from the ninth one. */ | |
c906108c | 1127 | |
c5aa993b JM |
1128 | if ((argno < nargs) || argbytes) |
1129 | { | |
1130 | int space = 0, jj; | |
c906108c | 1131 | |
c5aa993b JM |
1132 | if (argbytes) |
1133 | { | |
1134 | space += ((len - argbytes + 3) & -4); | |
1135 | jj = argno + 1; | |
1136 | } | |
1137 | else | |
1138 | jj = argno; | |
c906108c | 1139 | |
c5aa993b JM |
1140 | for (; jj < nargs; ++jj) |
1141 | { | |
ea7c478f | 1142 | struct value *val = args[jj]; |
c5aa993b JM |
1143 | space += ((TYPE_LENGTH (VALUE_TYPE (val))) + 3) & -4; |
1144 | } | |
c906108c | 1145 | |
64366f1c | 1146 | /* Add location required for the rest of the parameters. */ |
f6077098 | 1147 | space = (space + 15) & -16; |
c5aa993b | 1148 | sp -= space; |
c906108c | 1149 | |
7aea86e6 AC |
1150 | /* This is another instance we need to be concerned about |
1151 | securing our stack space. If we write anything underneath %sp | |
1152 | (r1), we might conflict with the kernel who thinks he is free | |
1153 | to use this area. So, update %sp first before doing anything | |
1154 | else. */ | |
1155 | ||
1156 | regcache_raw_write_signed (regcache, SP_REGNUM, sp); | |
1157 | ||
64366f1c EZ |
1158 | /* If the last argument copied into the registers didn't fit there |
1159 | completely, push the rest of it into stack. */ | |
c906108c | 1160 | |
c5aa993b JM |
1161 | if (argbytes) |
1162 | { | |
1163 | write_memory (sp + 24 + (ii * 4), | |
1164 | ((char *) VALUE_CONTENTS (arg)) + argbytes, | |
1165 | len - argbytes); | |
1166 | ++argno; | |
1167 | ii += ((len - argbytes + 3) & -4) / 4; | |
1168 | } | |
c906108c | 1169 | |
64366f1c | 1170 | /* Push the rest of the arguments into stack. */ |
c5aa993b JM |
1171 | for (; argno < nargs; ++argno) |
1172 | { | |
c906108c | 1173 | |
c5aa993b JM |
1174 | arg = args[argno]; |
1175 | type = check_typedef (VALUE_TYPE (arg)); | |
1176 | len = TYPE_LENGTH (type); | |
c906108c SS |
1177 | |
1178 | ||
64366f1c EZ |
1179 | /* Float types should be passed in fpr's, as well as in the |
1180 | stack. */ | |
c5aa993b JM |
1181 | if (TYPE_CODE (type) == TYPE_CODE_FLT && f_argno < 13) |
1182 | { | |
c906108c | 1183 | |
c5aa993b JM |
1184 | if (len > 8) |
1185 | printf_unfiltered ( | |
1186 | "Fatal Error: a floating point parameter #%d with a size > 8 is found!\n", argno); | |
c906108c | 1187 | |
62700349 | 1188 | memcpy (&deprecated_registers[DEPRECATED_REGISTER_BYTE (FP0_REGNUM + 1 + f_argno)], |
c5aa993b JM |
1189 | VALUE_CONTENTS (arg), |
1190 | len); | |
1191 | ++f_argno; | |
1192 | } | |
c906108c | 1193 | |
c5aa993b JM |
1194 | write_memory (sp + 24 + (ii * 4), (char *) VALUE_CONTENTS (arg), len); |
1195 | ii += ((len + 3) & -4) / 4; | |
1196 | } | |
c906108c | 1197 | } |
c906108c | 1198 | |
69517000 | 1199 | /* Set the stack pointer. According to the ABI, the SP is meant to |
7aea86e6 AC |
1200 | be set _before_ the corresponding stack space is used. On AIX, |
1201 | this even applies when the target has been completely stopped! | |
1202 | Not doing this can lead to conflicts with the kernel which thinks | |
1203 | that it still has control over this not-yet-allocated stack | |
1204 | region. */ | |
33a7c2fc AC |
1205 | regcache_raw_write_signed (regcache, SP_REGNUM, sp); |
1206 | ||
7aea86e6 AC |
1207 | /* Set back chain properly. */ |
1208 | store_unsigned_integer (tmp_buffer, 4, saved_sp); | |
1209 | write_memory (sp, tmp_buffer, 4); | |
1210 | ||
e56a0ecc AC |
1211 | /* Point the inferior function call's return address at the dummy's |
1212 | breakpoint. */ | |
1213 | regcache_raw_write_signed (regcache, tdep->ppc_lr_regnum, bp_addr); | |
1214 | ||
794a477a AC |
1215 | /* Set the TOC register, get the value from the objfile reader |
1216 | which, in turn, gets it from the VMAP table. */ | |
1217 | if (rs6000_find_toc_address_hook != NULL) | |
1218 | { | |
1219 | CORE_ADDR tocvalue = (*rs6000_find_toc_address_hook) (func_addr); | |
1220 | regcache_raw_write_signed (regcache, tdep->ppc_toc_regnum, tocvalue); | |
1221 | } | |
1222 | ||
c906108c SS |
1223 | target_store_registers (-1); |
1224 | return sp; | |
1225 | } | |
c906108c | 1226 | |
b9ff3018 AC |
1227 | /* PowerOpen always puts structures in memory. Vectors, which were |
1228 | added later, do get returned in a register though. */ | |
1229 | ||
1230 | static int | |
1231 | rs6000_use_struct_convention (int gcc_p, struct type *value_type) | |
1232 | { | |
1233 | if ((TYPE_LENGTH (value_type) == 16 || TYPE_LENGTH (value_type) == 8) | |
1234 | && TYPE_VECTOR (value_type)) | |
1235 | return 0; | |
1236 | return 1; | |
1237 | } | |
1238 | ||
7a78ae4e ND |
1239 | static void |
1240 | rs6000_extract_return_value (struct type *valtype, char *regbuf, char *valbuf) | |
c906108c SS |
1241 | { |
1242 | int offset = 0; | |
ace1378a | 1243 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c | 1244 | |
c5aa993b JM |
1245 | if (TYPE_CODE (valtype) == TYPE_CODE_FLT) |
1246 | { | |
c906108c | 1247 | |
c5aa993b JM |
1248 | double dd; |
1249 | float ff; | |
1250 | /* floats and doubles are returned in fpr1. fpr's have a size of 8 bytes. | |
1251 | We need to truncate the return value into float size (4 byte) if | |
64366f1c | 1252 | necessary. */ |
c906108c | 1253 | |
c5aa993b JM |
1254 | if (TYPE_LENGTH (valtype) > 4) /* this is a double */ |
1255 | memcpy (valbuf, | |
62700349 | 1256 | ®buf[DEPRECATED_REGISTER_BYTE (FP0_REGNUM + 1)], |
c5aa993b JM |
1257 | TYPE_LENGTH (valtype)); |
1258 | else | |
1259 | { /* float */ | |
62700349 | 1260 | memcpy (&dd, ®buf[DEPRECATED_REGISTER_BYTE (FP0_REGNUM + 1)], 8); |
c5aa993b JM |
1261 | ff = (float) dd; |
1262 | memcpy (valbuf, &ff, sizeof (float)); | |
1263 | } | |
1264 | } | |
ace1378a EZ |
1265 | else if (TYPE_CODE (valtype) == TYPE_CODE_ARRAY |
1266 | && TYPE_LENGTH (valtype) == 16 | |
1267 | && TYPE_VECTOR (valtype)) | |
1268 | { | |
62700349 | 1269 | memcpy (valbuf, regbuf + DEPRECATED_REGISTER_BYTE (tdep->ppc_vr0_regnum + 2), |
ace1378a EZ |
1270 | TYPE_LENGTH (valtype)); |
1271 | } | |
c5aa993b JM |
1272 | else |
1273 | { | |
1274 | /* return value is copied starting from r3. */ | |
d7449b42 | 1275 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
12c266ea AC |
1276 | && TYPE_LENGTH (valtype) < DEPRECATED_REGISTER_RAW_SIZE (3)) |
1277 | offset = DEPRECATED_REGISTER_RAW_SIZE (3) - TYPE_LENGTH (valtype); | |
c5aa993b JM |
1278 | |
1279 | memcpy (valbuf, | |
62700349 | 1280 | regbuf + DEPRECATED_REGISTER_BYTE (3) + offset, |
c906108c | 1281 | TYPE_LENGTH (valtype)); |
c906108c | 1282 | } |
c906108c SS |
1283 | } |
1284 | ||
977adac5 ND |
1285 | /* Return whether handle_inferior_event() should proceed through code |
1286 | starting at PC in function NAME when stepping. | |
1287 | ||
1288 | The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to | |
1289 | handle memory references that are too distant to fit in instructions | |
1290 | generated by the compiler. For example, if 'foo' in the following | |
1291 | instruction: | |
1292 | ||
1293 | lwz r9,foo(r2) | |
1294 | ||
1295 | is greater than 32767, the linker might replace the lwz with a branch to | |
1296 | somewhere in @FIX1 that does the load in 2 instructions and then branches | |
1297 | back to where execution should continue. | |
1298 | ||
1299 | GDB should silently step over @FIX code, just like AIX dbx does. | |
1300 | Unfortunately, the linker uses the "b" instruction for the branches, | |
1301 | meaning that the link register doesn't get set. Therefore, GDB's usual | |
1302 | step_over_function() mechanism won't work. | |
1303 | ||
1304 | Instead, use the IN_SOLIB_RETURN_TRAMPOLINE and SKIP_TRAMPOLINE_CODE hooks | |
1305 | in handle_inferior_event() to skip past @FIX code. */ | |
1306 | ||
1307 | int | |
1308 | rs6000_in_solib_return_trampoline (CORE_ADDR pc, char *name) | |
1309 | { | |
1310 | return name && !strncmp (name, "@FIX", 4); | |
1311 | } | |
1312 | ||
1313 | /* Skip code that the user doesn't want to see when stepping: | |
1314 | ||
1315 | 1. Indirect function calls use a piece of trampoline code to do context | |
1316 | switching, i.e. to set the new TOC table. Skip such code if we are on | |
1317 | its first instruction (as when we have single-stepped to here). | |
1318 | ||
1319 | 2. Skip shared library trampoline code (which is different from | |
c906108c | 1320 | indirect function call trampolines). |
977adac5 ND |
1321 | |
1322 | 3. Skip bigtoc fixup code. | |
1323 | ||
c906108c | 1324 | Result is desired PC to step until, or NULL if we are not in |
977adac5 | 1325 | code that should be skipped. */ |
c906108c SS |
1326 | |
1327 | CORE_ADDR | |
7a78ae4e | 1328 | rs6000_skip_trampoline_code (CORE_ADDR pc) |
c906108c | 1329 | { |
52f0bd74 | 1330 | unsigned int ii, op; |
977adac5 | 1331 | int rel; |
c906108c | 1332 | CORE_ADDR solib_target_pc; |
977adac5 | 1333 | struct minimal_symbol *msymbol; |
c906108c | 1334 | |
c5aa993b JM |
1335 | static unsigned trampoline_code[] = |
1336 | { | |
1337 | 0x800b0000, /* l r0,0x0(r11) */ | |
1338 | 0x90410014, /* st r2,0x14(r1) */ | |
1339 | 0x7c0903a6, /* mtctr r0 */ | |
1340 | 0x804b0004, /* l r2,0x4(r11) */ | |
1341 | 0x816b0008, /* l r11,0x8(r11) */ | |
1342 | 0x4e800420, /* bctr */ | |
1343 | 0x4e800020, /* br */ | |
1344 | 0 | |
c906108c SS |
1345 | }; |
1346 | ||
977adac5 ND |
1347 | /* Check for bigtoc fixup code. */ |
1348 | msymbol = lookup_minimal_symbol_by_pc (pc); | |
22abf04a | 1349 | if (msymbol && rs6000_in_solib_return_trampoline (pc, DEPRECATED_SYMBOL_NAME (msymbol))) |
977adac5 ND |
1350 | { |
1351 | /* Double-check that the third instruction from PC is relative "b". */ | |
1352 | op = read_memory_integer (pc + 8, 4); | |
1353 | if ((op & 0xfc000003) == 0x48000000) | |
1354 | { | |
1355 | /* Extract bits 6-29 as a signed 24-bit relative word address and | |
1356 | add it to the containing PC. */ | |
1357 | rel = ((int)(op << 6) >> 6); | |
1358 | return pc + 8 + rel; | |
1359 | } | |
1360 | } | |
1361 | ||
c906108c SS |
1362 | /* If pc is in a shared library trampoline, return its target. */ |
1363 | solib_target_pc = find_solib_trampoline_target (pc); | |
1364 | if (solib_target_pc) | |
1365 | return solib_target_pc; | |
1366 | ||
c5aa993b JM |
1367 | for (ii = 0; trampoline_code[ii]; ++ii) |
1368 | { | |
1369 | op = read_memory_integer (pc + (ii * 4), 4); | |
1370 | if (op != trampoline_code[ii]) | |
1371 | return 0; | |
1372 | } | |
1373 | ii = read_register (11); /* r11 holds destination addr */ | |
21283beb | 1374 | pc = read_memory_addr (ii, gdbarch_tdep (current_gdbarch)->wordsize); /* (r11) value */ |
c906108c SS |
1375 | return pc; |
1376 | } | |
1377 | ||
c906108c SS |
1378 | /* If saved registers of frame FI are not known yet, read and cache them. |
1379 | &FDATAP contains rs6000_framedata; TDATAP can be NULL, | |
1380 | in which case the framedata are read. */ | |
1381 | ||
1382 | static void | |
7a78ae4e | 1383 | frame_get_saved_regs (struct frame_info *fi, struct rs6000_framedata *fdatap) |
c906108c | 1384 | { |
c5aa993b | 1385 | CORE_ADDR frame_addr; |
c906108c | 1386 | struct rs6000_framedata work_fdata; |
6be8bc0c EZ |
1387 | struct gdbarch_tdep * tdep = gdbarch_tdep (current_gdbarch); |
1388 | int wordsize = tdep->wordsize; | |
c906108c | 1389 | |
1b1d3794 | 1390 | if (deprecated_get_frame_saved_regs (fi)) |
c906108c | 1391 | return; |
c5aa993b | 1392 | |
c906108c SS |
1393 | if (fdatap == NULL) |
1394 | { | |
1395 | fdatap = &work_fdata; | |
be41e9f4 | 1396 | (void) skip_prologue (get_frame_func (fi), get_frame_pc (fi), fdatap); |
c906108c SS |
1397 | } |
1398 | ||
1399 | frame_saved_regs_zalloc (fi); | |
1400 | ||
1401 | /* If there were any saved registers, figure out parent's stack | |
64366f1c | 1402 | pointer. */ |
c906108c | 1403 | /* The following is true only if the frame doesn't have a call to |
64366f1c | 1404 | alloca(), FIXME. */ |
c906108c | 1405 | |
6be8bc0c EZ |
1406 | if (fdatap->saved_fpr == 0 |
1407 | && fdatap->saved_gpr == 0 | |
1408 | && fdatap->saved_vr == 0 | |
96ff0de4 | 1409 | && fdatap->saved_ev == 0 |
6be8bc0c EZ |
1410 | && fdatap->lr_offset == 0 |
1411 | && fdatap->cr_offset == 0 | |
96ff0de4 EZ |
1412 | && fdatap->vr_offset == 0 |
1413 | && fdatap->ev_offset == 0) | |
c906108c | 1414 | frame_addr = 0; |
c906108c | 1415 | else |
bf75c8c1 AC |
1416 | /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most |
1417 | address of the current frame. Things might be easier if the | |
1418 | ->frame pointed to the outer-most address of the frame. In the | |
1419 | mean time, the address of the prev frame is used as the base | |
1420 | address of this frame. */ | |
618ce49f | 1421 | frame_addr = DEPRECATED_FRAME_CHAIN (fi); |
c5aa993b | 1422 | |
c906108c SS |
1423 | /* if != -1, fdatap->saved_fpr is the smallest number of saved_fpr. |
1424 | All fpr's from saved_fpr to fp31 are saved. */ | |
1425 | ||
1426 | if (fdatap->saved_fpr >= 0) | |
1427 | { | |
1428 | int i; | |
7a78ae4e | 1429 | CORE_ADDR fpr_addr = frame_addr + fdatap->fpr_offset; |
c906108c SS |
1430 | for (i = fdatap->saved_fpr; i < 32; i++) |
1431 | { | |
1b1d3794 | 1432 | deprecated_get_frame_saved_regs (fi)[FP0_REGNUM + i] = fpr_addr; |
7a78ae4e | 1433 | fpr_addr += 8; |
c906108c SS |
1434 | } |
1435 | } | |
1436 | ||
1437 | /* if != -1, fdatap->saved_gpr is the smallest number of saved_gpr. | |
1438 | All gpr's from saved_gpr to gpr31 are saved. */ | |
1439 | ||
1440 | if (fdatap->saved_gpr >= 0) | |
1441 | { | |
1442 | int i; | |
7a78ae4e | 1443 | CORE_ADDR gpr_addr = frame_addr + fdatap->gpr_offset; |
c906108c SS |
1444 | for (i = fdatap->saved_gpr; i < 32; i++) |
1445 | { | |
1b1d3794 | 1446 | deprecated_get_frame_saved_regs (fi)[tdep->ppc_gp0_regnum + i] = gpr_addr; |
7a78ae4e | 1447 | gpr_addr += wordsize; |
c906108c SS |
1448 | } |
1449 | } | |
1450 | ||
6be8bc0c EZ |
1451 | /* if != -1, fdatap->saved_vr is the smallest number of saved_vr. |
1452 | All vr's from saved_vr to vr31 are saved. */ | |
1453 | if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) | |
1454 | { | |
1455 | if (fdatap->saved_vr >= 0) | |
1456 | { | |
1457 | int i; | |
1458 | CORE_ADDR vr_addr = frame_addr + fdatap->vr_offset; | |
1459 | for (i = fdatap->saved_vr; i < 32; i++) | |
1460 | { | |
1b1d3794 | 1461 | deprecated_get_frame_saved_regs (fi)[tdep->ppc_vr0_regnum + i] = vr_addr; |
12c266ea | 1462 | vr_addr += DEPRECATED_REGISTER_RAW_SIZE (tdep->ppc_vr0_regnum); |
6be8bc0c EZ |
1463 | } |
1464 | } | |
1465 | } | |
1466 | ||
96ff0de4 EZ |
1467 | /* if != -1, fdatap->saved_ev is the smallest number of saved_ev. |
1468 | All vr's from saved_ev to ev31 are saved. ????? */ | |
1469 | if (tdep->ppc_ev0_regnum != -1 && tdep->ppc_ev31_regnum != -1) | |
1470 | { | |
1471 | if (fdatap->saved_ev >= 0) | |
1472 | { | |
1473 | int i; | |
1474 | CORE_ADDR ev_addr = frame_addr + fdatap->ev_offset; | |
1475 | for (i = fdatap->saved_ev; i < 32; i++) | |
1476 | { | |
1b1d3794 AC |
1477 | deprecated_get_frame_saved_regs (fi)[tdep->ppc_ev0_regnum + i] = ev_addr; |
1478 | deprecated_get_frame_saved_regs (fi)[tdep->ppc_gp0_regnum + i] = ev_addr + 4; | |
12c266ea | 1479 | ev_addr += DEPRECATED_REGISTER_RAW_SIZE (tdep->ppc_ev0_regnum); |
96ff0de4 EZ |
1480 | } |
1481 | } | |
1482 | } | |
1483 | ||
c906108c SS |
1484 | /* If != 0, fdatap->cr_offset is the offset from the frame that holds |
1485 | the CR. */ | |
1486 | if (fdatap->cr_offset != 0) | |
1b1d3794 | 1487 | deprecated_get_frame_saved_regs (fi)[tdep->ppc_cr_regnum] = frame_addr + fdatap->cr_offset; |
c906108c SS |
1488 | |
1489 | /* If != 0, fdatap->lr_offset is the offset from the frame that holds | |
1490 | the LR. */ | |
1491 | if (fdatap->lr_offset != 0) | |
1b1d3794 | 1492 | deprecated_get_frame_saved_regs (fi)[tdep->ppc_lr_regnum] = frame_addr + fdatap->lr_offset; |
6be8bc0c EZ |
1493 | |
1494 | /* If != 0, fdatap->vrsave_offset is the offset from the frame that holds | |
1495 | the VRSAVE. */ | |
1496 | if (fdatap->vrsave_offset != 0) | |
1b1d3794 | 1497 | deprecated_get_frame_saved_regs (fi)[tdep->ppc_vrsave_regnum] = frame_addr + fdatap->vrsave_offset; |
c906108c SS |
1498 | } |
1499 | ||
1500 | /* Return the address of a frame. This is the inital %sp value when the frame | |
64366f1c EZ |
1501 | was first allocated. For functions calling alloca(), it might be saved in |
1502 | an alloca register. */ | |
c906108c SS |
1503 | |
1504 | static CORE_ADDR | |
7a78ae4e | 1505 | frame_initial_stack_address (struct frame_info *fi) |
c906108c SS |
1506 | { |
1507 | CORE_ADDR tmpaddr; | |
1508 | struct rs6000_framedata fdata; | |
1509 | struct frame_info *callee_fi; | |
1510 | ||
64366f1c EZ |
1511 | /* If the initial stack pointer (frame address) of this frame is known, |
1512 | just return it. */ | |
c906108c | 1513 | |
c9012c71 AC |
1514 | if (get_frame_extra_info (fi)->initial_sp) |
1515 | return get_frame_extra_info (fi)->initial_sp; | |
c906108c | 1516 | |
64366f1c | 1517 | /* Find out if this function is using an alloca register. */ |
c906108c | 1518 | |
be41e9f4 | 1519 | (void) skip_prologue (get_frame_func (fi), get_frame_pc (fi), &fdata); |
c906108c | 1520 | |
64366f1c EZ |
1521 | /* If saved registers of this frame are not known yet, read and |
1522 | cache them. */ | |
c906108c | 1523 | |
1b1d3794 | 1524 | if (!deprecated_get_frame_saved_regs (fi)) |
c906108c SS |
1525 | frame_get_saved_regs (fi, &fdata); |
1526 | ||
1527 | /* If no alloca register used, then fi->frame is the value of the %sp for | |
64366f1c | 1528 | this frame, and it is good enough. */ |
c906108c SS |
1529 | |
1530 | if (fdata.alloca_reg < 0) | |
1531 | { | |
c9012c71 AC |
1532 | get_frame_extra_info (fi)->initial_sp = get_frame_base (fi); |
1533 | return get_frame_extra_info (fi)->initial_sp; | |
c906108c SS |
1534 | } |
1535 | ||
953836b2 AC |
1536 | /* There is an alloca register, use its value, in the current frame, |
1537 | as the initial stack pointer. */ | |
1538 | { | |
d9d9c31f | 1539 | char tmpbuf[MAX_REGISTER_SIZE]; |
953836b2 AC |
1540 | if (frame_register_read (fi, fdata.alloca_reg, tmpbuf)) |
1541 | { | |
c9012c71 | 1542 | get_frame_extra_info (fi)->initial_sp |
953836b2 | 1543 | = extract_unsigned_integer (tmpbuf, |
12c266ea | 1544 | DEPRECATED_REGISTER_RAW_SIZE (fdata.alloca_reg)); |
953836b2 AC |
1545 | } |
1546 | else | |
1547 | /* NOTE: cagney/2002-04-17: At present the only time | |
1548 | frame_register_read will fail is when the register isn't | |
1549 | available. If that does happen, use the frame. */ | |
c9012c71 | 1550 | get_frame_extra_info (fi)->initial_sp = get_frame_base (fi); |
953836b2 | 1551 | } |
c9012c71 | 1552 | return get_frame_extra_info (fi)->initial_sp; |
c906108c SS |
1553 | } |
1554 | ||
7a78ae4e | 1555 | /* Return the size of register REG when words are WORDSIZE bytes long. If REG |
64366f1c | 1556 | isn't available with that word size, return 0. */ |
7a78ae4e ND |
1557 | |
1558 | static int | |
1559 | regsize (const struct reg *reg, int wordsize) | |
1560 | { | |
1561 | return wordsize == 8 ? reg->sz64 : reg->sz32; | |
1562 | } | |
1563 | ||
1564 | /* Return the name of register number N, or null if no such register exists | |
64366f1c | 1565 | in the current architecture. */ |
7a78ae4e | 1566 | |
fa88f677 | 1567 | static const char * |
7a78ae4e ND |
1568 | rs6000_register_name (int n) |
1569 | { | |
21283beb | 1570 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
7a78ae4e ND |
1571 | const struct reg *reg = tdep->regs + n; |
1572 | ||
1573 | if (!regsize (reg, tdep->wordsize)) | |
1574 | return NULL; | |
1575 | return reg->name; | |
1576 | } | |
1577 | ||
1578 | /* Index within `registers' of the first byte of the space for | |
1579 | register N. */ | |
1580 | ||
1581 | static int | |
1582 | rs6000_register_byte (int n) | |
1583 | { | |
21283beb | 1584 | return gdbarch_tdep (current_gdbarch)->regoff[n]; |
7a78ae4e ND |
1585 | } |
1586 | ||
1587 | /* Return the number of bytes of storage in the actual machine representation | |
64366f1c | 1588 | for register N if that register is available, else return 0. */ |
7a78ae4e ND |
1589 | |
1590 | static int | |
1591 | rs6000_register_raw_size (int n) | |
1592 | { | |
21283beb | 1593 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
7a78ae4e ND |
1594 | const struct reg *reg = tdep->regs + n; |
1595 | return regsize (reg, tdep->wordsize); | |
1596 | } | |
1597 | ||
7a78ae4e ND |
1598 | /* Return the GDB type object for the "standard" data type |
1599 | of data in register N. */ | |
1600 | ||
1601 | static struct type * | |
fba45db2 | 1602 | rs6000_register_virtual_type (int n) |
7a78ae4e | 1603 | { |
21283beb | 1604 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
7a78ae4e ND |
1605 | const struct reg *reg = tdep->regs + n; |
1606 | ||
1fcc0bb8 EZ |
1607 | if (reg->fpr) |
1608 | return builtin_type_double; | |
1609 | else | |
1610 | { | |
1611 | int size = regsize (reg, tdep->wordsize); | |
1612 | switch (size) | |
1613 | { | |
449a5da4 AC |
1614 | case 0: |
1615 | return builtin_type_int0; | |
1616 | case 4: | |
ed6edd9b | 1617 | return builtin_type_uint32; |
1fcc0bb8 | 1618 | case 8: |
c8001721 EZ |
1619 | if (tdep->ppc_ev0_regnum <= n && n <= tdep->ppc_ev31_regnum) |
1620 | return builtin_type_vec64; | |
1621 | else | |
ed6edd9b | 1622 | return builtin_type_uint64; |
1fcc0bb8 EZ |
1623 | break; |
1624 | case 16: | |
08cf96df | 1625 | return builtin_type_vec128; |
1fcc0bb8 EZ |
1626 | break; |
1627 | default: | |
449a5da4 AC |
1628 | internal_error (__FILE__, __LINE__, "Register %d size %d unknown", |
1629 | n, size); | |
1fcc0bb8 EZ |
1630 | } |
1631 | } | |
7a78ae4e ND |
1632 | } |
1633 | ||
7a78ae4e ND |
1634 | /* Return whether register N requires conversion when moving from raw format |
1635 | to virtual format. | |
1636 | ||
1637 | The register format for RS/6000 floating point registers is always | |
64366f1c | 1638 | double, we need a conversion if the memory format is float. */ |
7a78ae4e ND |
1639 | |
1640 | static int | |
1641 | rs6000_register_convertible (int n) | |
1642 | { | |
21283beb | 1643 | const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + n; |
7a78ae4e ND |
1644 | return reg->fpr; |
1645 | } | |
1646 | ||
1647 | /* Convert data from raw format for register N in buffer FROM | |
64366f1c | 1648 | to virtual format with type TYPE in buffer TO. */ |
7a78ae4e ND |
1649 | |
1650 | static void | |
1651 | rs6000_register_convert_to_virtual (int n, struct type *type, | |
1652 | char *from, char *to) | |
1653 | { | |
12c266ea | 1654 | if (TYPE_LENGTH (type) != DEPRECATED_REGISTER_RAW_SIZE (n)) |
7a292a7a | 1655 | { |
12c266ea | 1656 | double val = deprecated_extract_floating (from, DEPRECATED_REGISTER_RAW_SIZE (n)); |
f1908289 | 1657 | deprecated_store_floating (to, TYPE_LENGTH (type), val); |
7a78ae4e ND |
1658 | } |
1659 | else | |
12c266ea | 1660 | memcpy (to, from, DEPRECATED_REGISTER_RAW_SIZE (n)); |
7a78ae4e ND |
1661 | } |
1662 | ||
1663 | /* Convert data from virtual format with type TYPE in buffer FROM | |
64366f1c | 1664 | to raw format for register N in buffer TO. */ |
7a292a7a | 1665 | |
7a78ae4e ND |
1666 | static void |
1667 | rs6000_register_convert_to_raw (struct type *type, int n, | |
781a750d | 1668 | const char *from, char *to) |
7a78ae4e | 1669 | { |
12c266ea | 1670 | if (TYPE_LENGTH (type) != DEPRECATED_REGISTER_RAW_SIZE (n)) |
7a78ae4e | 1671 | { |
f1908289 | 1672 | double val = deprecated_extract_floating (from, TYPE_LENGTH (type)); |
12c266ea | 1673 | deprecated_store_floating (to, DEPRECATED_REGISTER_RAW_SIZE (n), val); |
7a292a7a | 1674 | } |
7a78ae4e | 1675 | else |
12c266ea | 1676 | memcpy (to, from, DEPRECATED_REGISTER_RAW_SIZE (n)); |
7a78ae4e | 1677 | } |
c906108c | 1678 | |
c8001721 EZ |
1679 | static void |
1680 | e500_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
1681 | int reg_nr, void *buffer) | |
1682 | { | |
1683 | int base_regnum; | |
1684 | int offset = 0; | |
d9d9c31f | 1685 | char temp_buffer[MAX_REGISTER_SIZE]; |
c8001721 EZ |
1686 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1687 | ||
1688 | if (reg_nr >= tdep->ppc_gp0_regnum | |
1689 | && reg_nr <= tdep->ppc_gplast_regnum) | |
1690 | { | |
1691 | base_regnum = reg_nr - tdep->ppc_gp0_regnum + tdep->ppc_ev0_regnum; | |
1692 | ||
1693 | /* Build the value in the provided buffer. */ | |
1694 | /* Read the raw register of which this one is the lower portion. */ | |
1695 | regcache_raw_read (regcache, base_regnum, temp_buffer); | |
1696 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
1697 | offset = 4; | |
1698 | memcpy ((char *) buffer, temp_buffer + offset, 4); | |
1699 | } | |
1700 | } | |
1701 | ||
1702 | static void | |
1703 | e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
1704 | int reg_nr, const void *buffer) | |
1705 | { | |
1706 | int base_regnum; | |
1707 | int offset = 0; | |
d9d9c31f | 1708 | char temp_buffer[MAX_REGISTER_SIZE]; |
c8001721 EZ |
1709 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
1710 | ||
1711 | if (reg_nr >= tdep->ppc_gp0_regnum | |
1712 | && reg_nr <= tdep->ppc_gplast_regnum) | |
1713 | { | |
1714 | base_regnum = reg_nr - tdep->ppc_gp0_regnum + tdep->ppc_ev0_regnum; | |
1715 | /* reg_nr is 32 bit here, and base_regnum is 64 bits. */ | |
1716 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
1717 | offset = 4; | |
1718 | ||
1719 | /* Let's read the value of the base register into a temporary | |
1720 | buffer, so that overwriting the last four bytes with the new | |
1721 | value of the pseudo will leave the upper 4 bytes unchanged. */ | |
1722 | regcache_raw_read (regcache, base_regnum, temp_buffer); | |
1723 | ||
1724 | /* Write as an 8 byte quantity. */ | |
1725 | memcpy (temp_buffer + offset, (char *) buffer, 4); | |
1726 | regcache_raw_write (regcache, base_regnum, temp_buffer); | |
1727 | } | |
1728 | } | |
1729 | ||
1730 | /* Convert a dwarf2 register number to a gdb REGNUM. */ | |
1731 | static int | |
1732 | e500_dwarf2_reg_to_regnum (int num) | |
1733 | { | |
1734 | int regnum; | |
1735 | if (0 <= num && num <= 31) | |
1736 | return num + gdbarch_tdep (current_gdbarch)->ppc_gp0_regnum; | |
1737 | else | |
1738 | return num; | |
1739 | } | |
1740 | ||
2188cbdd | 1741 | /* Convert a dbx stab register number (from `r' declaration) to a gdb |
64366f1c | 1742 | REGNUM. */ |
2188cbdd EZ |
1743 | static int |
1744 | rs6000_stab_reg_to_regnum (int num) | |
1745 | { | |
1746 | int regnum; | |
1747 | switch (num) | |
1748 | { | |
1749 | case 64: | |
1750 | regnum = gdbarch_tdep (current_gdbarch)->ppc_mq_regnum; | |
1751 | break; | |
1752 | case 65: | |
1753 | regnum = gdbarch_tdep (current_gdbarch)->ppc_lr_regnum; | |
1754 | break; | |
1755 | case 66: | |
1756 | regnum = gdbarch_tdep (current_gdbarch)->ppc_ctr_regnum; | |
1757 | break; | |
1758 | case 76: | |
1759 | regnum = gdbarch_tdep (current_gdbarch)->ppc_xer_regnum; | |
1760 | break; | |
1761 | default: | |
1762 | regnum = num; | |
1763 | break; | |
1764 | } | |
1765 | return regnum; | |
1766 | } | |
1767 | ||
7a78ae4e ND |
1768 | static void |
1769 | rs6000_store_return_value (struct type *type, char *valbuf) | |
1770 | { | |
ace1378a EZ |
1771 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
1772 | ||
7a78ae4e ND |
1773 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
1774 | ||
1775 | /* Floating point values are returned starting from FPR1 and up. | |
1776 | Say a double_double_double type could be returned in | |
64366f1c | 1777 | FPR1/FPR2/FPR3 triple. */ |
7a78ae4e | 1778 | |
62700349 | 1779 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (FP0_REGNUM + 1), valbuf, |
73937e03 | 1780 | TYPE_LENGTH (type)); |
ace1378a EZ |
1781 | else if (TYPE_CODE (type) == TYPE_CODE_ARRAY) |
1782 | { | |
1783 | if (TYPE_LENGTH (type) == 16 | |
1784 | && TYPE_VECTOR (type)) | |
62700349 | 1785 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (tdep->ppc_vr0_regnum + 2), |
73937e03 | 1786 | valbuf, TYPE_LENGTH (type)); |
ace1378a | 1787 | } |
7a78ae4e | 1788 | else |
64366f1c | 1789 | /* Everything else is returned in GPR3 and up. */ |
62700349 | 1790 | deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (gdbarch_tdep (current_gdbarch)->ppc_gp0_regnum + 3), |
73937e03 | 1791 | valbuf, TYPE_LENGTH (type)); |
7a78ae4e ND |
1792 | } |
1793 | ||
1794 | /* Extract from an array REGBUF containing the (raw) register state | |
1795 | the address in which a function should return its structure value, | |
1796 | as a CORE_ADDR (or an expression that can be used as one). */ | |
1797 | ||
1798 | static CORE_ADDR | |
11269d7e AC |
1799 | rs6000_extract_struct_value_address (struct regcache *regcache) |
1800 | { | |
1801 | /* FIXME: cagney/2002-09-26: PR gdb/724: When making an inferior | |
1802 | function call GDB knows the address of the struct return value | |
1803 | and hence, should not need to call this function. Unfortunately, | |
e8a8712a AC |
1804 | the current call_function_by_hand() code only saves the most |
1805 | recent struct address leading to occasional calls. The code | |
1806 | should instead maintain a stack of such addresses (in the dummy | |
1807 | frame object). */ | |
11269d7e AC |
1808 | /* NOTE: cagney/2002-09-26: Return 0 which indicates that we've |
1809 | really got no idea where the return value is being stored. While | |
1810 | r3, on function entry, contained the address it will have since | |
1811 | been reused (scratch) and hence wouldn't be valid */ | |
1812 | return 0; | |
7a78ae4e ND |
1813 | } |
1814 | ||
64366f1c | 1815 | /* Hook called when a new child process is started. */ |
7a78ae4e ND |
1816 | |
1817 | void | |
1818 | rs6000_create_inferior (int pid) | |
1819 | { | |
1820 | if (rs6000_set_host_arch_hook) | |
1821 | rs6000_set_host_arch_hook (pid); | |
c906108c SS |
1822 | } |
1823 | \f | |
e2d0e7eb | 1824 | /* Support for CONVERT_FROM_FUNC_PTR_ADDR (ARCH, ADDR, TARG). |
7a78ae4e ND |
1825 | |
1826 | Usually a function pointer's representation is simply the address | |
1827 | of the function. On the RS/6000 however, a function pointer is | |
1828 | represented by a pointer to a TOC entry. This TOC entry contains | |
1829 | three words, the first word is the address of the function, the | |
1830 | second word is the TOC pointer (r2), and the third word is the | |
1831 | static chain value. Throughout GDB it is currently assumed that a | |
1832 | function pointer contains the address of the function, which is not | |
1833 | easy to fix. In addition, the conversion of a function address to | |
1834 | a function pointer would require allocation of a TOC entry in the | |
1835 | inferior's memory space, with all its drawbacks. To be able to | |
1836 | call C++ virtual methods in the inferior (which are called via | |
f517ea4e | 1837 | function pointers), find_function_addr uses this function to get the |
7a78ae4e ND |
1838 | function address from a function pointer. */ |
1839 | ||
f517ea4e PS |
1840 | /* Return real function address if ADDR (a function pointer) is in the data |
1841 | space and is therefore a special function pointer. */ | |
c906108c | 1842 | |
b9362cc7 | 1843 | static CORE_ADDR |
e2d0e7eb AC |
1844 | rs6000_convert_from_func_ptr_addr (struct gdbarch *gdbarch, |
1845 | CORE_ADDR addr, | |
1846 | struct target_ops *targ) | |
c906108c SS |
1847 | { |
1848 | struct obj_section *s; | |
1849 | ||
1850 | s = find_pc_section (addr); | |
1851 | if (s && s->the_bfd_section->flags & SEC_CODE) | |
7a78ae4e | 1852 | return addr; |
c906108c | 1853 | |
7a78ae4e | 1854 | /* ADDR is in the data space, so it's a special function pointer. */ |
21283beb | 1855 | return read_memory_addr (addr, gdbarch_tdep (current_gdbarch)->wordsize); |
c906108c | 1856 | } |
c906108c | 1857 | \f |
c5aa993b | 1858 | |
7a78ae4e | 1859 | /* Handling the various POWER/PowerPC variants. */ |
c906108c SS |
1860 | |
1861 | ||
7a78ae4e ND |
1862 | /* The arrays here called registers_MUMBLE hold information about available |
1863 | registers. | |
c906108c SS |
1864 | |
1865 | For each family of PPC variants, I've tried to isolate out the | |
1866 | common registers and put them up front, so that as long as you get | |
1867 | the general family right, GDB will correctly identify the registers | |
1868 | common to that family. The common register sets are: | |
1869 | ||
1870 | For the 60x family: hid0 hid1 iabr dabr pir | |
1871 | ||
1872 | For the 505 and 860 family: eie eid nri | |
1873 | ||
1874 | For the 403 and 403GC: icdbdr esr dear evpr cdbcr tsr tcr pit tbhi | |
c5aa993b JM |
1875 | tblo srr2 srr3 dbsr dbcr iac1 iac2 dac1 dac2 dccr iccr pbl1 |
1876 | pbu1 pbl2 pbu2 | |
c906108c SS |
1877 | |
1878 | Most of these register groups aren't anything formal. I arrived at | |
1879 | them by looking at the registers that occurred in more than one | |
6f5987a6 KB |
1880 | processor. |
1881 | ||
1882 | Note: kevinb/2002-04-30: Support for the fpscr register was added | |
1883 | during April, 2002. Slot 70 is being used for PowerPC and slot 71 | |
1884 | for Power. For PowerPC, slot 70 was unused and was already in the | |
1885 | PPC_UISA_SPRS which is ideally where fpscr should go. For Power, | |
1886 | slot 70 was being used for "mq", so the next available slot (71) | |
1887 | was chosen. It would have been nice to be able to make the | |
1888 | register numbers the same across processor cores, but this wasn't | |
1889 | possible without either 1) renumbering some registers for some | |
1890 | processors or 2) assigning fpscr to a really high slot that's | |
1891 | larger than any current register number. Doing (1) is bad because | |
1892 | existing stubs would break. Doing (2) is undesirable because it | |
1893 | would introduce a really large gap between fpscr and the rest of | |
1894 | the registers for most processors. */ | |
7a78ae4e | 1895 | |
64366f1c | 1896 | /* Convenience macros for populating register arrays. */ |
7a78ae4e | 1897 | |
64366f1c | 1898 | /* Within another macro, convert S to a string. */ |
7a78ae4e ND |
1899 | |
1900 | #define STR(s) #s | |
1901 | ||
1902 | /* Return a struct reg defining register NAME that's 32 bits on 32-bit systems | |
64366f1c | 1903 | and 64 bits on 64-bit systems. */ |
489461e2 | 1904 | #define R(name) { STR(name), 4, 8, 0, 0 } |
7a78ae4e ND |
1905 | |
1906 | /* Return a struct reg defining register NAME that's 32 bits on all | |
64366f1c | 1907 | systems. */ |
489461e2 | 1908 | #define R4(name) { STR(name), 4, 4, 0, 0 } |
7a78ae4e ND |
1909 | |
1910 | /* Return a struct reg defining register NAME that's 64 bits on all | |
64366f1c | 1911 | systems. */ |
489461e2 | 1912 | #define R8(name) { STR(name), 8, 8, 0, 0 } |
7a78ae4e | 1913 | |
1fcc0bb8 | 1914 | /* Return a struct reg defining register NAME that's 128 bits on all |
64366f1c | 1915 | systems. */ |
489461e2 | 1916 | #define R16(name) { STR(name), 16, 16, 0, 0 } |
1fcc0bb8 | 1917 | |
64366f1c | 1918 | /* Return a struct reg defining floating-point register NAME. */ |
489461e2 EZ |
1919 | #define F(name) { STR(name), 8, 8, 1, 0 } |
1920 | ||
64366f1c | 1921 | /* Return a struct reg defining a pseudo register NAME. */ |
489461e2 | 1922 | #define P(name) { STR(name), 4, 8, 0, 1} |
7a78ae4e ND |
1923 | |
1924 | /* Return a struct reg defining register NAME that's 32 bits on 32-bit | |
64366f1c | 1925 | systems and that doesn't exist on 64-bit systems. */ |
489461e2 | 1926 | #define R32(name) { STR(name), 4, 0, 0, 0 } |
7a78ae4e ND |
1927 | |
1928 | /* Return a struct reg defining register NAME that's 64 bits on 64-bit | |
64366f1c | 1929 | systems and that doesn't exist on 32-bit systems. */ |
489461e2 | 1930 | #define R64(name) { STR(name), 0, 8, 0, 0 } |
7a78ae4e | 1931 | |
64366f1c | 1932 | /* Return a struct reg placeholder for a register that doesn't exist. */ |
489461e2 | 1933 | #define R0 { 0, 0, 0, 0, 0 } |
7a78ae4e ND |
1934 | |
1935 | /* UISA registers common across all architectures, including POWER. */ | |
1936 | ||
1937 | #define COMMON_UISA_REGS \ | |
1938 | /* 0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), \ | |
1939 | /* 8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \ | |
1940 | /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \ | |
1941 | /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \ | |
1942 | /* 32 */ F(f0), F(f1), F(f2), F(f3), F(f4), F(f5), F(f6), F(f7), \ | |
1943 | /* 40 */ F(f8), F(f9), F(f10),F(f11),F(f12),F(f13),F(f14),F(f15), \ | |
1944 | /* 48 */ F(f16),F(f17),F(f18),F(f19),F(f20),F(f21),F(f22),F(f23), \ | |
1945 | /* 56 */ F(f24),F(f25),F(f26),F(f27),F(f28),F(f29),F(f30),F(f31), \ | |
1946 | /* 64 */ R(pc), R(ps) | |
1947 | ||
ebeac11a EZ |
1948 | #define COMMON_UISA_NOFP_REGS \ |
1949 | /* 0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), \ | |
1950 | /* 8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \ | |
1951 | /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \ | |
1952 | /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \ | |
1953 | /* 32 */ R0, R0, R0, R0, R0, R0, R0, R0, \ | |
1954 | /* 40 */ R0, R0, R0, R0, R0, R0, R0, R0, \ | |
1955 | /* 48 */ R0, R0, R0, R0, R0, R0, R0, R0, \ | |
1956 | /* 56 */ R0, R0, R0, R0, R0, R0, R0, R0, \ | |
1957 | /* 64 */ R(pc), R(ps) | |
1958 | ||
7a78ae4e ND |
1959 | /* UISA-level SPRs for PowerPC. */ |
1960 | #define PPC_UISA_SPRS \ | |
e3f36dbd | 1961 | /* 66 */ R4(cr), R(lr), R(ctr), R4(xer), R4(fpscr) |
7a78ae4e | 1962 | |
c8001721 EZ |
1963 | /* UISA-level SPRs for PowerPC without floating point support. */ |
1964 | #define PPC_UISA_NOFP_SPRS \ | |
1965 | /* 66 */ R4(cr), R(lr), R(ctr), R4(xer), R0 | |
1966 | ||
7a78ae4e ND |
1967 | /* Segment registers, for PowerPC. */ |
1968 | #define PPC_SEGMENT_REGS \ | |
1969 | /* 71 */ R32(sr0), R32(sr1), R32(sr2), R32(sr3), \ | |
1970 | /* 75 */ R32(sr4), R32(sr5), R32(sr6), R32(sr7), \ | |
1971 | /* 79 */ R32(sr8), R32(sr9), R32(sr10), R32(sr11), \ | |
1972 | /* 83 */ R32(sr12), R32(sr13), R32(sr14), R32(sr15) | |
1973 | ||
1974 | /* OEA SPRs for PowerPC. */ | |
1975 | #define PPC_OEA_SPRS \ | |
1976 | /* 87 */ R4(pvr), \ | |
1977 | /* 88 */ R(ibat0u), R(ibat0l), R(ibat1u), R(ibat1l), \ | |
1978 | /* 92 */ R(ibat2u), R(ibat2l), R(ibat3u), R(ibat3l), \ | |
1979 | /* 96 */ R(dbat0u), R(dbat0l), R(dbat1u), R(dbat1l), \ | |
1980 | /* 100 */ R(dbat2u), R(dbat2l), R(dbat3u), R(dbat3l), \ | |
1981 | /* 104 */ R(sdr1), R64(asr), R(dar), R4(dsisr), \ | |
1982 | /* 108 */ R(sprg0), R(sprg1), R(sprg2), R(sprg3), \ | |
1983 | /* 112 */ R(srr0), R(srr1), R(tbl), R(tbu), \ | |
1984 | /* 116 */ R4(dec), R(dabr), R4(ear) | |
1985 | ||
64366f1c | 1986 | /* AltiVec registers. */ |
1fcc0bb8 EZ |
1987 | #define PPC_ALTIVEC_REGS \ |
1988 | /*119*/R16(vr0), R16(vr1), R16(vr2), R16(vr3), R16(vr4), R16(vr5), R16(vr6), R16(vr7), \ | |
1989 | /*127*/R16(vr8), R16(vr9), R16(vr10),R16(vr11),R16(vr12),R16(vr13),R16(vr14),R16(vr15), \ | |
1990 | /*135*/R16(vr16),R16(vr17),R16(vr18),R16(vr19),R16(vr20),R16(vr21),R16(vr22),R16(vr23), \ | |
1991 | /*143*/R16(vr24),R16(vr25),R16(vr26),R16(vr27),R16(vr28),R16(vr29),R16(vr30),R16(vr31), \ | |
1992 | /*151*/R4(vscr), R4(vrsave) | |
1993 | ||
c8001721 EZ |
1994 | /* Vectors of hi-lo general purpose registers. */ |
1995 | #define PPC_EV_REGS \ | |
1996 | /* 0*/R8(ev0), R8(ev1), R8(ev2), R8(ev3), R8(ev4), R8(ev5), R8(ev6), R8(ev7), \ | |
1997 | /* 8*/R8(ev8), R8(ev9), R8(ev10),R8(ev11),R8(ev12),R8(ev13),R8(ev14),R8(ev15), \ | |
1998 | /*16*/R8(ev16),R8(ev17),R8(ev18),R8(ev19),R8(ev20),R8(ev21),R8(ev22),R8(ev23), \ | |
1999 | /*24*/R8(ev24),R8(ev25),R8(ev26),R8(ev27),R8(ev28),R8(ev29),R8(ev30),R8(ev31) | |
2000 | ||
2001 | /* Lower half of the EV registers. */ | |
2002 | #define PPC_GPRS_PSEUDO_REGS \ | |
2003 | /* 0 */ P(r0), P(r1), P(r2), P(r3), P(r4), P(r5), P(r6), P(r7), \ | |
2004 | /* 8 */ P(r8), P(r9), P(r10),P(r11),P(r12),P(r13),P(r14),P(r15), \ | |
2005 | /* 16 */ P(r16),P(r17),P(r18),P(r19),P(r20),P(r21),P(r22),P(r23), \ | |
338ef23d | 2006 | /* 24 */ P(r24),P(r25),P(r26),P(r27),P(r28),P(r29),P(r30),P(r31) |
c8001721 | 2007 | |
7a78ae4e | 2008 | /* IBM POWER (pre-PowerPC) architecture, user-level view. We only cover |
64366f1c | 2009 | user-level SPR's. */ |
7a78ae4e | 2010 | static const struct reg registers_power[] = |
c906108c | 2011 | { |
7a78ae4e | 2012 | COMMON_UISA_REGS, |
e3f36dbd KB |
2013 | /* 66 */ R4(cnd), R(lr), R(cnt), R4(xer), R4(mq), |
2014 | /* 71 */ R4(fpscr) | |
c906108c SS |
2015 | }; |
2016 | ||
7a78ae4e | 2017 | /* PowerPC UISA - a PPC processor as viewed by user-level code. A UISA-only |
64366f1c | 2018 | view of the PowerPC. */ |
7a78ae4e | 2019 | static const struct reg registers_powerpc[] = |
c906108c | 2020 | { |
7a78ae4e | 2021 | COMMON_UISA_REGS, |
1fcc0bb8 EZ |
2022 | PPC_UISA_SPRS, |
2023 | PPC_ALTIVEC_REGS | |
c906108c SS |
2024 | }; |
2025 | ||
ebeac11a EZ |
2026 | /* PowerPC UISA - a PPC processor as viewed by user-level |
2027 | code, but without floating point registers. */ | |
2028 | static const struct reg registers_powerpc_nofp[] = | |
2029 | { | |
2030 | COMMON_UISA_NOFP_REGS, | |
2031 | PPC_UISA_SPRS | |
2032 | }; | |
2033 | ||
64366f1c | 2034 | /* IBM PowerPC 403. */ |
7a78ae4e | 2035 | static const struct reg registers_403[] = |
c5aa993b | 2036 | { |
7a78ae4e ND |
2037 | COMMON_UISA_REGS, |
2038 | PPC_UISA_SPRS, | |
2039 | PPC_SEGMENT_REGS, | |
2040 | PPC_OEA_SPRS, | |
2041 | /* 119 */ R(icdbdr), R(esr), R(dear), R(evpr), | |
2042 | /* 123 */ R(cdbcr), R(tsr), R(tcr), R(pit), | |
2043 | /* 127 */ R(tbhi), R(tblo), R(srr2), R(srr3), | |
2044 | /* 131 */ R(dbsr), R(dbcr), R(iac1), R(iac2), | |
2045 | /* 135 */ R(dac1), R(dac2), R(dccr), R(iccr), | |
2046 | /* 139 */ R(pbl1), R(pbu1), R(pbl2), R(pbu2) | |
c906108c SS |
2047 | }; |
2048 | ||
64366f1c | 2049 | /* IBM PowerPC 403GC. */ |
7a78ae4e | 2050 | static const struct reg registers_403GC[] = |
c5aa993b | 2051 | { |
7a78ae4e ND |
2052 | COMMON_UISA_REGS, |
2053 | PPC_UISA_SPRS, | |
2054 | PPC_SEGMENT_REGS, | |
2055 | PPC_OEA_SPRS, | |
2056 | /* 119 */ R(icdbdr), R(esr), R(dear), R(evpr), | |
2057 | /* 123 */ R(cdbcr), R(tsr), R(tcr), R(pit), | |
2058 | /* 127 */ R(tbhi), R(tblo), R(srr2), R(srr3), | |
2059 | /* 131 */ R(dbsr), R(dbcr), R(iac1), R(iac2), | |
2060 | /* 135 */ R(dac1), R(dac2), R(dccr), R(iccr), | |
2061 | /* 139 */ R(pbl1), R(pbu1), R(pbl2), R(pbu2), | |
2062 | /* 143 */ R(zpr), R(pid), R(sgr), R(dcwr), | |
2063 | /* 147 */ R(tbhu), R(tblu) | |
c906108c SS |
2064 | }; |
2065 | ||
64366f1c | 2066 | /* Motorola PowerPC 505. */ |
7a78ae4e | 2067 | static const struct reg registers_505[] = |
c5aa993b | 2068 | { |
7a78ae4e ND |
2069 | COMMON_UISA_REGS, |
2070 | PPC_UISA_SPRS, | |
2071 | PPC_SEGMENT_REGS, | |
2072 | PPC_OEA_SPRS, | |
2073 | /* 119 */ R(eie), R(eid), R(nri) | |
c906108c SS |
2074 | }; |
2075 | ||
64366f1c | 2076 | /* Motorola PowerPC 860 or 850. */ |
7a78ae4e | 2077 | static const struct reg registers_860[] = |
c5aa993b | 2078 | { |
7a78ae4e ND |
2079 | COMMON_UISA_REGS, |
2080 | PPC_UISA_SPRS, | |
2081 | PPC_SEGMENT_REGS, | |
2082 | PPC_OEA_SPRS, | |
2083 | /* 119 */ R(eie), R(eid), R(nri), R(cmpa), | |
2084 | /* 123 */ R(cmpb), R(cmpc), R(cmpd), R(icr), | |
2085 | /* 127 */ R(der), R(counta), R(countb), R(cmpe), | |
2086 | /* 131 */ R(cmpf), R(cmpg), R(cmph), R(lctrl1), | |
2087 | /* 135 */ R(lctrl2), R(ictrl), R(bar), R(ic_cst), | |
2088 | /* 139 */ R(ic_adr), R(ic_dat), R(dc_cst), R(dc_adr), | |
2089 | /* 143 */ R(dc_dat), R(dpdr), R(dpir), R(immr), | |
2090 | /* 147 */ R(mi_ctr), R(mi_ap), R(mi_epn), R(mi_twc), | |
2091 | /* 151 */ R(mi_rpn), R(md_ctr), R(m_casid), R(md_ap), | |
2092 | /* 155 */ R(md_epn), R(md_twb), R(md_twc), R(md_rpn), | |
2093 | /* 159 */ R(m_tw), R(mi_dbcam), R(mi_dbram0), R(mi_dbram1), | |
2094 | /* 163 */ R(md_dbcam), R(md_dbram0), R(md_dbram1) | |
c906108c SS |
2095 | }; |
2096 | ||
7a78ae4e ND |
2097 | /* Motorola PowerPC 601. Note that the 601 has different register numbers |
2098 | for reading and writing RTCU and RTCL. However, how one reads and writes a | |
c906108c | 2099 | register is the stub's problem. */ |
7a78ae4e | 2100 | static const struct reg registers_601[] = |
c5aa993b | 2101 | { |
7a78ae4e ND |
2102 | COMMON_UISA_REGS, |
2103 | PPC_UISA_SPRS, | |
2104 | PPC_SEGMENT_REGS, | |
2105 | PPC_OEA_SPRS, | |
2106 | /* 119 */ R(hid0), R(hid1), R(iabr), R(dabr), | |
2107 | /* 123 */ R(pir), R(mq), R(rtcu), R(rtcl) | |
c906108c SS |
2108 | }; |
2109 | ||
64366f1c | 2110 | /* Motorola PowerPC 602. */ |
7a78ae4e | 2111 | static const struct reg registers_602[] = |
c5aa993b | 2112 | { |
7a78ae4e ND |
2113 | COMMON_UISA_REGS, |
2114 | PPC_UISA_SPRS, | |
2115 | PPC_SEGMENT_REGS, | |
2116 | PPC_OEA_SPRS, | |
2117 | /* 119 */ R(hid0), R(hid1), R(iabr), R0, | |
2118 | /* 123 */ R0, R(tcr), R(ibr), R(esassr), | |
2119 | /* 127 */ R(sebr), R(ser), R(sp), R(lt) | |
c906108c SS |
2120 | }; |
2121 | ||
64366f1c | 2122 | /* Motorola/IBM PowerPC 603 or 603e. */ |
7a78ae4e | 2123 | static const struct reg registers_603[] = |
c5aa993b | 2124 | { |
7a78ae4e ND |
2125 | COMMON_UISA_REGS, |
2126 | PPC_UISA_SPRS, | |
2127 | PPC_SEGMENT_REGS, | |
2128 | PPC_OEA_SPRS, | |
2129 | /* 119 */ R(hid0), R(hid1), R(iabr), R0, | |
2130 | /* 123 */ R0, R(dmiss), R(dcmp), R(hash1), | |
2131 | /* 127 */ R(hash2), R(imiss), R(icmp), R(rpa) | |
c906108c SS |
2132 | }; |
2133 | ||
64366f1c | 2134 | /* Motorola PowerPC 604 or 604e. */ |
7a78ae4e | 2135 | static const struct reg registers_604[] = |
c5aa993b | 2136 | { |
7a78ae4e ND |
2137 | COMMON_UISA_REGS, |
2138 | PPC_UISA_SPRS, | |
2139 | PPC_SEGMENT_REGS, | |
2140 | PPC_OEA_SPRS, | |
2141 | /* 119 */ R(hid0), R(hid1), R(iabr), R(dabr), | |
2142 | /* 123 */ R(pir), R(mmcr0), R(pmc1), R(pmc2), | |
2143 | /* 127 */ R(sia), R(sda) | |
c906108c SS |
2144 | }; |
2145 | ||
64366f1c | 2146 | /* Motorola/IBM PowerPC 750 or 740. */ |
7a78ae4e | 2147 | static const struct reg registers_750[] = |
c5aa993b | 2148 | { |
7a78ae4e ND |
2149 | COMMON_UISA_REGS, |
2150 | PPC_UISA_SPRS, | |
2151 | PPC_SEGMENT_REGS, | |
2152 | PPC_OEA_SPRS, | |
2153 | /* 119 */ R(hid0), R(hid1), R(iabr), R(dabr), | |
2154 | /* 123 */ R0, R(ummcr0), R(upmc1), R(upmc2), | |
2155 | /* 127 */ R(usia), R(ummcr1), R(upmc3), R(upmc4), | |
2156 | /* 131 */ R(mmcr0), R(pmc1), R(pmc2), R(sia), | |
2157 | /* 135 */ R(mmcr1), R(pmc3), R(pmc4), R(l2cr), | |
2158 | /* 139 */ R(ictc), R(thrm1), R(thrm2), R(thrm3) | |
c906108c SS |
2159 | }; |
2160 | ||
2161 | ||
64366f1c | 2162 | /* Motorola PowerPC 7400. */ |
1fcc0bb8 EZ |
2163 | static const struct reg registers_7400[] = |
2164 | { | |
2165 | /* gpr0-gpr31, fpr0-fpr31 */ | |
2166 | COMMON_UISA_REGS, | |
2167 | /* ctr, xre, lr, cr */ | |
2168 | PPC_UISA_SPRS, | |
2169 | /* sr0-sr15 */ | |
2170 | PPC_SEGMENT_REGS, | |
2171 | PPC_OEA_SPRS, | |
2172 | /* vr0-vr31, vrsave, vscr */ | |
2173 | PPC_ALTIVEC_REGS | |
2174 | /* FIXME? Add more registers? */ | |
2175 | }; | |
2176 | ||
c8001721 EZ |
2177 | /* Motorola e500. */ |
2178 | static const struct reg registers_e500[] = | |
2179 | { | |
2180 | R(pc), R(ps), | |
2181 | /* cr, lr, ctr, xer, "" */ | |
2182 | PPC_UISA_NOFP_SPRS, | |
2183 | /* 7...38 */ | |
2184 | PPC_EV_REGS, | |
338ef23d AC |
2185 | R8(acc), R(spefscr), |
2186 | /* NOTE: Add new registers here the end of the raw register | |
2187 | list and just before the first pseudo register. */ | |
c8001721 EZ |
2188 | /* 39...70 */ |
2189 | PPC_GPRS_PSEUDO_REGS | |
2190 | }; | |
2191 | ||
c906108c | 2192 | /* Information about a particular processor variant. */ |
7a78ae4e | 2193 | |
c906108c | 2194 | struct variant |
c5aa993b JM |
2195 | { |
2196 | /* Name of this variant. */ | |
2197 | char *name; | |
c906108c | 2198 | |
c5aa993b JM |
2199 | /* English description of the variant. */ |
2200 | char *description; | |
c906108c | 2201 | |
64366f1c | 2202 | /* bfd_arch_info.arch corresponding to variant. */ |
7a78ae4e ND |
2203 | enum bfd_architecture arch; |
2204 | ||
64366f1c | 2205 | /* bfd_arch_info.mach corresponding to variant. */ |
7a78ae4e ND |
2206 | unsigned long mach; |
2207 | ||
489461e2 EZ |
2208 | /* Number of real registers. */ |
2209 | int nregs; | |
2210 | ||
2211 | /* Number of pseudo registers. */ | |
2212 | int npregs; | |
2213 | ||
2214 | /* Number of total registers (the sum of nregs and npregs). */ | |
2215 | int num_tot_regs; | |
2216 | ||
c5aa993b JM |
2217 | /* Table of register names; registers[R] is the name of the register |
2218 | number R. */ | |
7a78ae4e | 2219 | const struct reg *regs; |
c5aa993b | 2220 | }; |
c906108c | 2221 | |
489461e2 EZ |
2222 | #define tot_num_registers(list) (sizeof (list) / sizeof((list)[0])) |
2223 | ||
2224 | static int | |
2225 | num_registers (const struct reg *reg_list, int num_tot_regs) | |
2226 | { | |
2227 | int i; | |
2228 | int nregs = 0; | |
2229 | ||
2230 | for (i = 0; i < num_tot_regs; i++) | |
2231 | if (!reg_list[i].pseudo) | |
2232 | nregs++; | |
2233 | ||
2234 | return nregs; | |
2235 | } | |
2236 | ||
2237 | static int | |
2238 | num_pseudo_registers (const struct reg *reg_list, int num_tot_regs) | |
2239 | { | |
2240 | int i; | |
2241 | int npregs = 0; | |
2242 | ||
2243 | for (i = 0; i < num_tot_regs; i++) | |
2244 | if (reg_list[i].pseudo) | |
2245 | npregs ++; | |
2246 | ||
2247 | return npregs; | |
2248 | } | |
c906108c | 2249 | |
c906108c SS |
2250 | /* Information in this table comes from the following web sites: |
2251 | IBM: http://www.chips.ibm.com:80/products/embedded/ | |
2252 | Motorola: http://www.mot.com/SPS/PowerPC/ | |
2253 | ||
2254 | I'm sure I've got some of the variant descriptions not quite right. | |
2255 | Please report any inaccuracies you find to GDB's maintainer. | |
2256 | ||
2257 | If you add entries to this table, please be sure to allow the new | |
2258 | value as an argument to the --with-cpu flag, in configure.in. */ | |
2259 | ||
489461e2 | 2260 | static struct variant variants[] = |
c906108c | 2261 | { |
489461e2 | 2262 | |
7a78ae4e | 2263 | {"powerpc", "PowerPC user-level", bfd_arch_powerpc, |
489461e2 EZ |
2264 | bfd_mach_ppc, -1, -1, tot_num_registers (registers_powerpc), |
2265 | registers_powerpc}, | |
7a78ae4e | 2266 | {"power", "POWER user-level", bfd_arch_rs6000, |
489461e2 EZ |
2267 | bfd_mach_rs6k, -1, -1, tot_num_registers (registers_power), |
2268 | registers_power}, | |
7a78ae4e | 2269 | {"403", "IBM PowerPC 403", bfd_arch_powerpc, |
489461e2 EZ |
2270 | bfd_mach_ppc_403, -1, -1, tot_num_registers (registers_403), |
2271 | registers_403}, | |
7a78ae4e | 2272 | {"601", "Motorola PowerPC 601", bfd_arch_powerpc, |
489461e2 EZ |
2273 | bfd_mach_ppc_601, -1, -1, tot_num_registers (registers_601), |
2274 | registers_601}, | |
7a78ae4e | 2275 | {"602", "Motorola PowerPC 602", bfd_arch_powerpc, |
489461e2 EZ |
2276 | bfd_mach_ppc_602, -1, -1, tot_num_registers (registers_602), |
2277 | registers_602}, | |
7a78ae4e | 2278 | {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc, |
489461e2 EZ |
2279 | bfd_mach_ppc_603, -1, -1, tot_num_registers (registers_603), |
2280 | registers_603}, | |
7a78ae4e | 2281 | {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc, |
489461e2 EZ |
2282 | 604, -1, -1, tot_num_registers (registers_604), |
2283 | registers_604}, | |
7a78ae4e | 2284 | {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc, |
489461e2 EZ |
2285 | bfd_mach_ppc_403gc, -1, -1, tot_num_registers (registers_403GC), |
2286 | registers_403GC}, | |
7a78ae4e | 2287 | {"505", "Motorola PowerPC 505", bfd_arch_powerpc, |
489461e2 EZ |
2288 | bfd_mach_ppc_505, -1, -1, tot_num_registers (registers_505), |
2289 | registers_505}, | |
7a78ae4e | 2290 | {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc, |
489461e2 EZ |
2291 | bfd_mach_ppc_860, -1, -1, tot_num_registers (registers_860), |
2292 | registers_860}, | |
7a78ae4e | 2293 | {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc, |
489461e2 EZ |
2294 | bfd_mach_ppc_750, -1, -1, tot_num_registers (registers_750), |
2295 | registers_750}, | |
1fcc0bb8 | 2296 | {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc, |
489461e2 EZ |
2297 | bfd_mach_ppc_7400, -1, -1, tot_num_registers (registers_7400), |
2298 | registers_7400}, | |
c8001721 EZ |
2299 | {"e500", "Motorola PowerPC e500", bfd_arch_powerpc, |
2300 | bfd_mach_ppc_e500, -1, -1, tot_num_registers (registers_e500), | |
2301 | registers_e500}, | |
7a78ae4e | 2302 | |
5d57ee30 KB |
2303 | /* 64-bit */ |
2304 | {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc, | |
489461e2 EZ |
2305 | bfd_mach_ppc64, -1, -1, tot_num_registers (registers_powerpc), |
2306 | registers_powerpc}, | |
7a78ae4e | 2307 | {"620", "Motorola PowerPC 620", bfd_arch_powerpc, |
489461e2 EZ |
2308 | bfd_mach_ppc_620, -1, -1, tot_num_registers (registers_powerpc), |
2309 | registers_powerpc}, | |
5d57ee30 | 2310 | {"630", "Motorola PowerPC 630", bfd_arch_powerpc, |
489461e2 EZ |
2311 | bfd_mach_ppc_630, -1, -1, tot_num_registers (registers_powerpc), |
2312 | registers_powerpc}, | |
7a78ae4e | 2313 | {"a35", "PowerPC A35", bfd_arch_powerpc, |
489461e2 EZ |
2314 | bfd_mach_ppc_a35, -1, -1, tot_num_registers (registers_powerpc), |
2315 | registers_powerpc}, | |
5d57ee30 | 2316 | {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc, |
489461e2 EZ |
2317 | bfd_mach_ppc_rs64ii, -1, -1, tot_num_registers (registers_powerpc), |
2318 | registers_powerpc}, | |
5d57ee30 | 2319 | {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc, |
489461e2 EZ |
2320 | bfd_mach_ppc_rs64iii, -1, -1, tot_num_registers (registers_powerpc), |
2321 | registers_powerpc}, | |
5d57ee30 | 2322 | |
64366f1c | 2323 | /* FIXME: I haven't checked the register sets of the following. */ |
7a78ae4e | 2324 | {"rs1", "IBM POWER RS1", bfd_arch_rs6000, |
489461e2 EZ |
2325 | bfd_mach_rs6k_rs1, -1, -1, tot_num_registers (registers_power), |
2326 | registers_power}, | |
7a78ae4e | 2327 | {"rsc", "IBM POWER RSC", bfd_arch_rs6000, |
489461e2 EZ |
2328 | bfd_mach_rs6k_rsc, -1, -1, tot_num_registers (registers_power), |
2329 | registers_power}, | |
7a78ae4e | 2330 | {"rs2", "IBM POWER RS2", bfd_arch_rs6000, |
489461e2 EZ |
2331 | bfd_mach_rs6k_rs2, -1, -1, tot_num_registers (registers_power), |
2332 | registers_power}, | |
7a78ae4e | 2333 | |
489461e2 | 2334 | {0, 0, 0, 0, 0, 0, 0, 0} |
c906108c SS |
2335 | }; |
2336 | ||
64366f1c | 2337 | /* Initialize the number of registers and pseudo registers in each variant. */ |
489461e2 EZ |
2338 | |
2339 | static void | |
2340 | init_variants (void) | |
2341 | { | |
2342 | struct variant *v; | |
2343 | ||
2344 | for (v = variants; v->name; v++) | |
2345 | { | |
2346 | if (v->nregs == -1) | |
2347 | v->nregs = num_registers (v->regs, v->num_tot_regs); | |
2348 | if (v->npregs == -1) | |
2349 | v->npregs = num_pseudo_registers (v->regs, v->num_tot_regs); | |
2350 | } | |
2351 | } | |
c906108c | 2352 | |
7a78ae4e | 2353 | /* Return the variant corresponding to architecture ARCH and machine number |
64366f1c | 2354 | MACH. If no such variant exists, return null. */ |
c906108c | 2355 | |
7a78ae4e ND |
2356 | static const struct variant * |
2357 | find_variant_by_arch (enum bfd_architecture arch, unsigned long mach) | |
c906108c | 2358 | { |
7a78ae4e | 2359 | const struct variant *v; |
c5aa993b | 2360 | |
7a78ae4e ND |
2361 | for (v = variants; v->name; v++) |
2362 | if (arch == v->arch && mach == v->mach) | |
2363 | return v; | |
c906108c | 2364 | |
7a78ae4e | 2365 | return NULL; |
c906108c | 2366 | } |
9364a0ef EZ |
2367 | |
2368 | static int | |
2369 | gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info) | |
2370 | { | |
2371 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
2372 | return print_insn_big_powerpc (memaddr, info); | |
2373 | else | |
2374 | return print_insn_little_powerpc (memaddr, info); | |
2375 | } | |
7a78ae4e | 2376 | \f |
61a65099 KB |
2377 | static CORE_ADDR |
2378 | rs6000_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
2379 | { | |
2380 | return frame_unwind_register_unsigned (next_frame, PC_REGNUM); | |
2381 | } | |
2382 | ||
2383 | static struct frame_id | |
2384 | rs6000_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
2385 | { | |
2386 | return frame_id_build (frame_unwind_register_unsigned (next_frame, | |
2387 | SP_REGNUM), | |
2388 | frame_pc_unwind (next_frame)); | |
2389 | } | |
2390 | ||
2391 | struct rs6000_frame_cache | |
2392 | { | |
2393 | CORE_ADDR base; | |
2394 | CORE_ADDR initial_sp; | |
2395 | struct trad_frame_saved_reg *saved_regs; | |
2396 | }; | |
2397 | ||
2398 | static struct rs6000_frame_cache * | |
2399 | rs6000_frame_cache (struct frame_info *next_frame, void **this_cache) | |
2400 | { | |
2401 | struct rs6000_frame_cache *cache; | |
2402 | struct gdbarch *gdbarch = get_frame_arch (next_frame); | |
2403 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2404 | struct rs6000_framedata fdata; | |
2405 | int wordsize = tdep->wordsize; | |
2406 | ||
2407 | if ((*this_cache) != NULL) | |
2408 | return (*this_cache); | |
2409 | cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache); | |
2410 | (*this_cache) = cache; | |
2411 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
2412 | ||
2413 | skip_prologue (frame_func_unwind (next_frame), frame_pc_unwind (next_frame), | |
2414 | &fdata); | |
2415 | ||
2416 | /* If there were any saved registers, figure out parent's stack | |
2417 | pointer. */ | |
2418 | /* The following is true only if the frame doesn't have a call to | |
2419 | alloca(), FIXME. */ | |
2420 | ||
2421 | if (fdata.saved_fpr == 0 | |
2422 | && fdata.saved_gpr == 0 | |
2423 | && fdata.saved_vr == 0 | |
2424 | && fdata.saved_ev == 0 | |
2425 | && fdata.lr_offset == 0 | |
2426 | && fdata.cr_offset == 0 | |
2427 | && fdata.vr_offset == 0 | |
2428 | && fdata.ev_offset == 0) | |
2429 | cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM); | |
2430 | else | |
2431 | { | |
2432 | /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most | |
2433 | address of the current frame. Things might be easier if the | |
2434 | ->frame pointed to the outer-most address of the frame. In | |
2435 | the mean time, the address of the prev frame is used as the | |
2436 | base address of this frame. */ | |
2437 | cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM); | |
2438 | if (!fdata.frameless) | |
2439 | /* Frameless really means stackless. */ | |
2440 | cache->base = read_memory_addr (cache->base, wordsize); | |
2441 | } | |
2442 | trad_frame_set_value (cache->saved_regs, SP_REGNUM, cache->base); | |
2443 | ||
2444 | /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr. | |
2445 | All fpr's from saved_fpr to fp31 are saved. */ | |
2446 | ||
2447 | if (fdata.saved_fpr >= 0) | |
2448 | { | |
2449 | int i; | |
2450 | CORE_ADDR fpr_addr = cache->base + fdata.fpr_offset; | |
2451 | for (i = fdata.saved_fpr; i < 32; i++) | |
2452 | { | |
2453 | cache->saved_regs[FP0_REGNUM + i].addr = fpr_addr; | |
2454 | fpr_addr += 8; | |
2455 | } | |
2456 | } | |
2457 | ||
2458 | /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr. | |
2459 | All gpr's from saved_gpr to gpr31 are saved. */ | |
2460 | ||
2461 | if (fdata.saved_gpr >= 0) | |
2462 | { | |
2463 | int i; | |
2464 | CORE_ADDR gpr_addr = cache->base + fdata.gpr_offset; | |
2465 | for (i = fdata.saved_gpr; i < 32; i++) | |
2466 | { | |
2467 | cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = gpr_addr; | |
2468 | gpr_addr += wordsize; | |
2469 | } | |
2470 | } | |
2471 | ||
2472 | /* if != -1, fdata.saved_vr is the smallest number of saved_vr. | |
2473 | All vr's from saved_vr to vr31 are saved. */ | |
2474 | if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) | |
2475 | { | |
2476 | if (fdata.saved_vr >= 0) | |
2477 | { | |
2478 | int i; | |
2479 | CORE_ADDR vr_addr = cache->base + fdata.vr_offset; | |
2480 | for (i = fdata.saved_vr; i < 32; i++) | |
2481 | { | |
2482 | cache->saved_regs[tdep->ppc_vr0_regnum + i].addr = vr_addr; | |
2483 | vr_addr += register_size (gdbarch, tdep->ppc_vr0_regnum); | |
2484 | } | |
2485 | } | |
2486 | } | |
2487 | ||
2488 | /* if != -1, fdata.saved_ev is the smallest number of saved_ev. | |
2489 | All vr's from saved_ev to ev31 are saved. ????? */ | |
2490 | if (tdep->ppc_ev0_regnum != -1 && tdep->ppc_ev31_regnum != -1) | |
2491 | { | |
2492 | if (fdata.saved_ev >= 0) | |
2493 | { | |
2494 | int i; | |
2495 | CORE_ADDR ev_addr = cache->base + fdata.ev_offset; | |
2496 | for (i = fdata.saved_ev; i < 32; i++) | |
2497 | { | |
2498 | cache->saved_regs[tdep->ppc_ev0_regnum + i].addr = ev_addr; | |
2499 | cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + 4; | |
2500 | ev_addr += register_size (gdbarch, tdep->ppc_ev0_regnum); | |
2501 | } | |
2502 | } | |
2503 | } | |
2504 | ||
2505 | /* If != 0, fdata.cr_offset is the offset from the frame that | |
2506 | holds the CR. */ | |
2507 | if (fdata.cr_offset != 0) | |
2508 | cache->saved_regs[tdep->ppc_cr_regnum].addr = cache->base + fdata.cr_offset; | |
2509 | ||
2510 | /* If != 0, fdata.lr_offset is the offset from the frame that | |
2511 | holds the LR. */ | |
2512 | if (fdata.lr_offset != 0) | |
2513 | cache->saved_regs[tdep->ppc_lr_regnum].addr = cache->base + fdata.lr_offset; | |
2514 | /* The PC is found in the link register. */ | |
2515 | cache->saved_regs[PC_REGNUM] = cache->saved_regs[tdep->ppc_lr_regnum]; | |
2516 | ||
2517 | /* If != 0, fdata.vrsave_offset is the offset from the frame that | |
2518 | holds the VRSAVE. */ | |
2519 | if (fdata.vrsave_offset != 0) | |
2520 | cache->saved_regs[tdep->ppc_vrsave_regnum].addr = cache->base + fdata.vrsave_offset; | |
2521 | ||
2522 | if (fdata.alloca_reg < 0) | |
2523 | /* If no alloca register used, then fi->frame is the value of the | |
2524 | %sp for this frame, and it is good enough. */ | |
2525 | cache->initial_sp = frame_unwind_register_unsigned (next_frame, SP_REGNUM); | |
2526 | else | |
2527 | cache->initial_sp = frame_unwind_register_unsigned (next_frame, | |
2528 | fdata.alloca_reg); | |
2529 | ||
2530 | return cache; | |
2531 | } | |
2532 | ||
2533 | static void | |
2534 | rs6000_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
2535 | struct frame_id *this_id) | |
2536 | { | |
2537 | struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame, | |
2538 | this_cache); | |
2539 | (*this_id) = frame_id_build (info->base, frame_func_unwind (next_frame)); | |
2540 | } | |
2541 | ||
2542 | static void | |
2543 | rs6000_frame_prev_register (struct frame_info *next_frame, | |
2544 | void **this_cache, | |
2545 | int regnum, int *optimizedp, | |
2546 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
2547 | int *realnump, void *valuep) | |
2548 | { | |
2549 | struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame, | |
2550 | this_cache); | |
2551 | trad_frame_prev_register (next_frame, info->saved_regs, regnum, | |
2552 | optimizedp, lvalp, addrp, realnump, valuep); | |
2553 | } | |
2554 | ||
2555 | static const struct frame_unwind rs6000_frame_unwind = | |
2556 | { | |
2557 | NORMAL_FRAME, | |
2558 | rs6000_frame_this_id, | |
2559 | rs6000_frame_prev_register | |
2560 | }; | |
2561 | ||
2562 | static const struct frame_unwind * | |
2563 | rs6000_frame_sniffer (struct frame_info *next_frame) | |
2564 | { | |
2565 | return &rs6000_frame_unwind; | |
2566 | } | |
2567 | ||
2568 | \f | |
2569 | ||
2570 | static CORE_ADDR | |
2571 | rs6000_frame_base_address (struct frame_info *next_frame, | |
2572 | void **this_cache) | |
2573 | { | |
2574 | struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame, | |
2575 | this_cache); | |
2576 | return info->initial_sp; | |
2577 | } | |
2578 | ||
2579 | static const struct frame_base rs6000_frame_base = { | |
2580 | &rs6000_frame_unwind, | |
2581 | rs6000_frame_base_address, | |
2582 | rs6000_frame_base_address, | |
2583 | rs6000_frame_base_address | |
2584 | }; | |
2585 | ||
2586 | static const struct frame_base * | |
2587 | rs6000_frame_base_sniffer (struct frame_info *next_frame) | |
2588 | { | |
2589 | return &rs6000_frame_base; | |
2590 | } | |
2591 | ||
7a78ae4e ND |
2592 | /* Initialize the current architecture based on INFO. If possible, re-use an |
2593 | architecture from ARCHES, which is a list of architectures already created | |
2594 | during this debugging session. | |
c906108c | 2595 | |
7a78ae4e | 2596 | Called e.g. at program startup, when reading a core file, and when reading |
64366f1c | 2597 | a binary file. */ |
c906108c | 2598 | |
7a78ae4e ND |
2599 | static struct gdbarch * |
2600 | rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
2601 | { | |
2602 | struct gdbarch *gdbarch; | |
2603 | struct gdbarch_tdep *tdep; | |
9aa1e687 | 2604 | int wordsize, from_xcoff_exec, from_elf_exec, power, i, off; |
7a78ae4e ND |
2605 | struct reg *regs; |
2606 | const struct variant *v; | |
2607 | enum bfd_architecture arch; | |
2608 | unsigned long mach; | |
2609 | bfd abfd; | |
7b112f9c | 2610 | int sysv_abi; |
5bf1c677 | 2611 | asection *sect; |
7a78ae4e | 2612 | |
9aa1e687 | 2613 | from_xcoff_exec = info.abfd && info.abfd->format == bfd_object && |
7a78ae4e ND |
2614 | bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour; |
2615 | ||
9aa1e687 KB |
2616 | from_elf_exec = info.abfd && info.abfd->format == bfd_object && |
2617 | bfd_get_flavour (info.abfd) == bfd_target_elf_flavour; | |
2618 | ||
2619 | sysv_abi = info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour; | |
2620 | ||
e712c1cf | 2621 | /* Check word size. If INFO is from a binary file, infer it from |
64366f1c | 2622 | that, else choose a likely default. */ |
9aa1e687 | 2623 | if (from_xcoff_exec) |
c906108c | 2624 | { |
11ed25ac | 2625 | if (bfd_xcoff_is_xcoff64 (info.abfd)) |
7a78ae4e ND |
2626 | wordsize = 8; |
2627 | else | |
2628 | wordsize = 4; | |
c906108c | 2629 | } |
9aa1e687 KB |
2630 | else if (from_elf_exec) |
2631 | { | |
2632 | if (elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
2633 | wordsize = 8; | |
2634 | else | |
2635 | wordsize = 4; | |
2636 | } | |
c906108c | 2637 | else |
7a78ae4e | 2638 | { |
27b15785 KB |
2639 | if (info.bfd_arch_info != NULL && info.bfd_arch_info->bits_per_word != 0) |
2640 | wordsize = info.bfd_arch_info->bits_per_word / | |
2641 | info.bfd_arch_info->bits_per_byte; | |
2642 | else | |
2643 | wordsize = 4; | |
7a78ae4e | 2644 | } |
c906108c | 2645 | |
64366f1c | 2646 | /* Find a candidate among extant architectures. */ |
7a78ae4e ND |
2647 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
2648 | arches != NULL; | |
2649 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
2650 | { | |
2651 | /* Word size in the various PowerPC bfd_arch_info structs isn't | |
2652 | meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform | |
64366f1c | 2653 | separate word size check. */ |
7a78ae4e | 2654 | tdep = gdbarch_tdep (arches->gdbarch); |
4be87837 | 2655 | if (tdep && tdep->wordsize == wordsize) |
7a78ae4e ND |
2656 | return arches->gdbarch; |
2657 | } | |
c906108c | 2658 | |
7a78ae4e ND |
2659 | /* None found, create a new architecture from INFO, whose bfd_arch_info |
2660 | validity depends on the source: | |
2661 | - executable useless | |
2662 | - rs6000_host_arch() good | |
2663 | - core file good | |
2664 | - "set arch" trust blindly | |
2665 | - GDB startup useless but harmless */ | |
c906108c | 2666 | |
9aa1e687 | 2667 | if (!from_xcoff_exec) |
c906108c | 2668 | { |
b732d07d | 2669 | arch = info.bfd_arch_info->arch; |
7a78ae4e | 2670 | mach = info.bfd_arch_info->mach; |
c906108c | 2671 | } |
7a78ae4e | 2672 | else |
c906108c | 2673 | { |
7a78ae4e | 2674 | arch = bfd_arch_powerpc; |
35cec841 | 2675 | bfd_default_set_arch_mach (&abfd, arch, 0); |
7a78ae4e | 2676 | info.bfd_arch_info = bfd_get_arch_info (&abfd); |
35cec841 | 2677 | mach = info.bfd_arch_info->mach; |
7a78ae4e ND |
2678 | } |
2679 | tdep = xmalloc (sizeof (struct gdbarch_tdep)); | |
2680 | tdep->wordsize = wordsize; | |
5bf1c677 EZ |
2681 | |
2682 | /* For e500 executables, the apuinfo section is of help here. Such | |
2683 | section contains the identifier and revision number of each | |
2684 | Application-specific Processing Unit that is present on the | |
2685 | chip. The content of the section is determined by the assembler | |
2686 | which looks at each instruction and determines which unit (and | |
2687 | which version of it) can execute it. In our case we just look for | |
2688 | the existance of the section. */ | |
2689 | ||
2690 | if (info.abfd) | |
2691 | { | |
2692 | sect = bfd_get_section_by_name (info.abfd, ".PPC.EMB.apuinfo"); | |
2693 | if (sect) | |
2694 | { | |
2695 | arch = info.bfd_arch_info->arch; | |
2696 | mach = bfd_mach_ppc_e500; | |
2697 | bfd_default_set_arch_mach (&abfd, arch, mach); | |
2698 | info.bfd_arch_info = bfd_get_arch_info (&abfd); | |
2699 | } | |
2700 | } | |
2701 | ||
7a78ae4e ND |
2702 | gdbarch = gdbarch_alloc (&info, tdep); |
2703 | power = arch == bfd_arch_rs6000; | |
2704 | ||
489461e2 EZ |
2705 | /* Initialize the number of real and pseudo registers in each variant. */ |
2706 | init_variants (); | |
2707 | ||
64366f1c | 2708 | /* Choose variant. */ |
7a78ae4e ND |
2709 | v = find_variant_by_arch (arch, mach); |
2710 | if (!v) | |
dd47e6fd EZ |
2711 | return NULL; |
2712 | ||
7a78ae4e ND |
2713 | tdep->regs = v->regs; |
2714 | ||
2188cbdd EZ |
2715 | tdep->ppc_gp0_regnum = 0; |
2716 | tdep->ppc_gplast_regnum = 31; | |
2717 | tdep->ppc_toc_regnum = 2; | |
2718 | tdep->ppc_ps_regnum = 65; | |
2719 | tdep->ppc_cr_regnum = 66; | |
2720 | tdep->ppc_lr_regnum = 67; | |
2721 | tdep->ppc_ctr_regnum = 68; | |
2722 | tdep->ppc_xer_regnum = 69; | |
2723 | if (v->mach == bfd_mach_ppc_601) | |
2724 | tdep->ppc_mq_regnum = 124; | |
e3f36dbd | 2725 | else if (power) |
2188cbdd | 2726 | tdep->ppc_mq_regnum = 70; |
e3f36dbd KB |
2727 | else |
2728 | tdep->ppc_mq_regnum = -1; | |
2729 | tdep->ppc_fpscr_regnum = power ? 71 : 70; | |
2188cbdd | 2730 | |
c8001721 EZ |
2731 | set_gdbarch_pc_regnum (gdbarch, 64); |
2732 | set_gdbarch_sp_regnum (gdbarch, 1); | |
0ba6dca9 | 2733 | set_gdbarch_deprecated_fp_regnum (gdbarch, 1); |
afd48b75 | 2734 | if (sysv_abi && wordsize == 8) |
05580c65 | 2735 | set_gdbarch_return_value (gdbarch, ppc64_sysv_abi_return_value); |
e754ae69 | 2736 | else if (sysv_abi && wordsize == 4) |
05580c65 | 2737 | set_gdbarch_return_value (gdbarch, ppc_sysv_abi_return_value); |
afd48b75 AC |
2738 | else |
2739 | { | |
2740 | set_gdbarch_deprecated_extract_return_value (gdbarch, rs6000_extract_return_value); | |
2741 | set_gdbarch_deprecated_store_return_value (gdbarch, rs6000_store_return_value); | |
2742 | } | |
c8001721 | 2743 | |
1fcc0bb8 EZ |
2744 | if (v->arch == bfd_arch_powerpc) |
2745 | switch (v->mach) | |
2746 | { | |
2747 | case bfd_mach_ppc: | |
2748 | tdep->ppc_vr0_regnum = 71; | |
2749 | tdep->ppc_vrsave_regnum = 104; | |
c8001721 EZ |
2750 | tdep->ppc_ev0_regnum = -1; |
2751 | tdep->ppc_ev31_regnum = -1; | |
1fcc0bb8 EZ |
2752 | break; |
2753 | case bfd_mach_ppc_7400: | |
2754 | tdep->ppc_vr0_regnum = 119; | |
54c2a1e6 | 2755 | tdep->ppc_vrsave_regnum = 152; |
c8001721 EZ |
2756 | tdep->ppc_ev0_regnum = -1; |
2757 | tdep->ppc_ev31_regnum = -1; | |
2758 | break; | |
2759 | case bfd_mach_ppc_e500: | |
338ef23d AC |
2760 | tdep->ppc_gp0_regnum = 41; |
2761 | tdep->ppc_gplast_regnum = tdep->ppc_gp0_regnum + 32 - 1; | |
c8001721 EZ |
2762 | tdep->ppc_toc_regnum = -1; |
2763 | tdep->ppc_ps_regnum = 1; | |
2764 | tdep->ppc_cr_regnum = 2; | |
2765 | tdep->ppc_lr_regnum = 3; | |
2766 | tdep->ppc_ctr_regnum = 4; | |
2767 | tdep->ppc_xer_regnum = 5; | |
2768 | tdep->ppc_ev0_regnum = 7; | |
2769 | tdep->ppc_ev31_regnum = 38; | |
2770 | set_gdbarch_pc_regnum (gdbarch, 0); | |
338ef23d | 2771 | set_gdbarch_sp_regnum (gdbarch, tdep->ppc_gp0_regnum + 1); |
0ba6dca9 | 2772 | set_gdbarch_deprecated_fp_regnum (gdbarch, tdep->ppc_gp0_regnum + 1); |
c8001721 EZ |
2773 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, e500_dwarf2_reg_to_regnum); |
2774 | set_gdbarch_pseudo_register_read (gdbarch, e500_pseudo_register_read); | |
2775 | set_gdbarch_pseudo_register_write (gdbarch, e500_pseudo_register_write); | |
1fcc0bb8 EZ |
2776 | break; |
2777 | default: | |
2778 | tdep->ppc_vr0_regnum = -1; | |
2779 | tdep->ppc_vrsave_regnum = -1; | |
c8001721 EZ |
2780 | tdep->ppc_ev0_regnum = -1; |
2781 | tdep->ppc_ev31_regnum = -1; | |
1fcc0bb8 EZ |
2782 | break; |
2783 | } | |
2784 | ||
338ef23d AC |
2785 | /* Sanity check on registers. */ |
2786 | gdb_assert (strcmp (tdep->regs[tdep->ppc_gp0_regnum].name, "r0") == 0); | |
2787 | ||
a88376a3 KB |
2788 | /* Set lr_frame_offset. */ |
2789 | if (wordsize == 8) | |
2790 | tdep->lr_frame_offset = 16; | |
2791 | else if (sysv_abi) | |
2792 | tdep->lr_frame_offset = 4; | |
2793 | else | |
2794 | tdep->lr_frame_offset = 8; | |
2795 | ||
2796 | /* Calculate byte offsets in raw register array. */ | |
489461e2 EZ |
2797 | tdep->regoff = xmalloc (v->num_tot_regs * sizeof (int)); |
2798 | for (i = off = 0; i < v->num_tot_regs; i++) | |
7a78ae4e ND |
2799 | { |
2800 | tdep->regoff[i] = off; | |
2801 | off += regsize (v->regs + i, wordsize); | |
c906108c SS |
2802 | } |
2803 | ||
56a6dfb9 KB |
2804 | /* Select instruction printer. */ |
2805 | if (arch == power) | |
9364a0ef | 2806 | set_gdbarch_print_insn (gdbarch, print_insn_rs6000); |
56a6dfb9 | 2807 | else |
9364a0ef | 2808 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_powerpc); |
7495d1dc | 2809 | |
7a78ae4e | 2810 | set_gdbarch_write_pc (gdbarch, generic_target_write_pc); |
7a78ae4e ND |
2811 | |
2812 | set_gdbarch_num_regs (gdbarch, v->nregs); | |
c8001721 | 2813 | set_gdbarch_num_pseudo_regs (gdbarch, v->npregs); |
7a78ae4e | 2814 | set_gdbarch_register_name (gdbarch, rs6000_register_name); |
b1e29e33 | 2815 | set_gdbarch_deprecated_register_size (gdbarch, wordsize); |
b8b527c5 | 2816 | set_gdbarch_deprecated_register_bytes (gdbarch, off); |
9c04cab7 AC |
2817 | set_gdbarch_deprecated_register_byte (gdbarch, rs6000_register_byte); |
2818 | set_gdbarch_deprecated_register_raw_size (gdbarch, rs6000_register_raw_size); | |
9c04cab7 | 2819 | set_gdbarch_deprecated_register_virtual_type (gdbarch, rs6000_register_virtual_type); |
7a78ae4e ND |
2820 | |
2821 | set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT); | |
2822 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); | |
2823 | set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
2824 | set_gdbarch_long_bit (gdbarch, wordsize * TARGET_CHAR_BIT); | |
2825 | set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
2826 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
2827 | set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
ab9fe00e KB |
2828 | if (sysv_abi) |
2829 | set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT); | |
2830 | else | |
2831 | set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
4e409299 | 2832 | set_gdbarch_char_signed (gdbarch, 0); |
7a78ae4e | 2833 | |
11269d7e | 2834 | set_gdbarch_frame_align (gdbarch, rs6000_frame_align); |
8b148df9 AC |
2835 | if (sysv_abi && wordsize == 8) |
2836 | /* PPC64 SYSV. */ | |
2837 | set_gdbarch_frame_red_zone_size (gdbarch, 288); | |
2838 | else if (!sysv_abi && wordsize == 4) | |
5bffac25 AC |
2839 | /* PowerOpen / AIX 32 bit. The saved area or red zone consists of |
2840 | 19 4 byte GPRS + 18 8 byte FPRs giving a total of 220 bytes. | |
2841 | Problem is, 220 isn't frame (16 byte) aligned. Round it up to | |
2842 | 224. */ | |
2843 | set_gdbarch_frame_red_zone_size (gdbarch, 224); | |
7a78ae4e | 2844 | |
781a750d AC |
2845 | set_gdbarch_deprecated_register_convertible (gdbarch, rs6000_register_convertible); |
2846 | set_gdbarch_deprecated_register_convert_to_virtual (gdbarch, rs6000_register_convert_to_virtual); | |
2847 | set_gdbarch_deprecated_register_convert_to_raw (gdbarch, rs6000_register_convert_to_raw); | |
2188cbdd | 2848 | set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_stab_reg_to_regnum); |
2ea5f656 KB |
2849 | /* Note: kevinb/2002-04-12: I'm not convinced that rs6000_push_arguments() |
2850 | is correct for the SysV ABI when the wordsize is 8, but I'm also | |
2851 | fairly certain that ppc_sysv_abi_push_arguments() will give even | |
2852 | worse results since it only works for 32-bit code. So, for the moment, | |
2853 | we're better off calling rs6000_push_arguments() since it works for | |
2854 | 64-bit code. At some point in the future, this matter needs to be | |
2855 | revisited. */ | |
2856 | if (sysv_abi && wordsize == 4) | |
77b2b6d4 | 2857 | set_gdbarch_push_dummy_call (gdbarch, ppc_sysv_abi_push_dummy_call); |
8be9034a AC |
2858 | else if (sysv_abi && wordsize == 8) |
2859 | set_gdbarch_push_dummy_call (gdbarch, ppc64_sysv_abi_push_dummy_call); | |
9aa1e687 | 2860 | else |
77b2b6d4 | 2861 | set_gdbarch_push_dummy_call (gdbarch, rs6000_push_dummy_call); |
7a78ae4e | 2862 | |
74055713 | 2863 | set_gdbarch_deprecated_extract_struct_value_address (gdbarch, rs6000_extract_struct_value_address); |
7a78ae4e ND |
2864 | |
2865 | set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue); | |
2866 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
7a78ae4e ND |
2867 | set_gdbarch_breakpoint_from_pc (gdbarch, rs6000_breakpoint_from_pc); |
2868 | ||
6066c3de AC |
2869 | /* Handle the 64-bit SVR4 minimal-symbol convention of using "FN" |
2870 | for the descriptor and ".FN" for the entry-point -- a user | |
2871 | specifying "break FN" will unexpectedly end up with a breakpoint | |
2872 | on the descriptor and not the function. This architecture method | |
2873 | transforms any breakpoints on descriptors into breakpoints on the | |
2874 | corresponding entry point. */ | |
2875 | if (sysv_abi && wordsize == 8) | |
2876 | set_gdbarch_adjust_breakpoint_address (gdbarch, ppc64_sysv_abi_adjust_breakpoint_address); | |
2877 | ||
7a78ae4e ND |
2878 | /* Not sure on this. FIXMEmgo */ |
2879 | set_gdbarch_frame_args_skip (gdbarch, 8); | |
2880 | ||
05580c65 | 2881 | if (!sysv_abi) |
7b112f9c | 2882 | set_gdbarch_use_struct_convention (gdbarch, |
b9ff3018 | 2883 | rs6000_use_struct_convention); |
8e0662df | 2884 | |
15813d3f AC |
2885 | if (!sysv_abi) |
2886 | { | |
2887 | /* Handle RS/6000 function pointers (which are really function | |
2888 | descriptors). */ | |
f517ea4e PS |
2889 | set_gdbarch_convert_from_func_ptr_addr (gdbarch, |
2890 | rs6000_convert_from_func_ptr_addr); | |
9aa1e687 | 2891 | } |
7a78ae4e | 2892 | |
143985b7 AF |
2893 | /* Helpers for function argument information. */ |
2894 | set_gdbarch_fetch_pointer_argument (gdbarch, rs6000_fetch_pointer_argument); | |
2895 | ||
7b112f9c | 2896 | /* Hook in ABI-specific overrides, if they have been registered. */ |
4be87837 | 2897 | gdbarch_init_osabi (info, gdbarch); |
7b112f9c | 2898 | |
61a65099 KB |
2899 | switch (info.osabi) |
2900 | { | |
2901 | case GDB_OSABI_NETBSD_AOUT: | |
2902 | case GDB_OSABI_NETBSD_ELF: | |
2903 | case GDB_OSABI_UNKNOWN: | |
2904 | case GDB_OSABI_LINUX: | |
2905 | set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc); | |
2906 | frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer); | |
2907 | set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id); | |
2908 | frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer); | |
2909 | break; | |
2910 | default: | |
2911 | set_gdbarch_deprecated_save_dummy_frame_tos (gdbarch, generic_save_dummy_frame_tos); | |
2912 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); | |
81332287 KB |
2913 | |
2914 | set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc); | |
2915 | frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer); | |
2916 | set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id); | |
2917 | frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer); | |
61a65099 KB |
2918 | } |
2919 | ||
ef5200c1 AC |
2920 | if (from_xcoff_exec) |
2921 | { | |
2922 | /* NOTE: jimix/2003-06-09: This test should really check for | |
2923 | GDB_OSABI_AIX when that is defined and becomes | |
2924 | available. (Actually, once things are properly split apart, | |
2925 | the test goes away.) */ | |
2926 | /* RS6000/AIX does not support PT_STEP. Has to be simulated. */ | |
2927 | set_gdbarch_software_single_step (gdbarch, rs6000_software_single_step); | |
2928 | } | |
2929 | ||
7a78ae4e | 2930 | return gdbarch; |
c906108c SS |
2931 | } |
2932 | ||
7b112f9c JT |
2933 | static void |
2934 | rs6000_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
2935 | { | |
2936 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2937 | ||
2938 | if (tdep == NULL) | |
2939 | return; | |
2940 | ||
4be87837 | 2941 | /* FIXME: Dump gdbarch_tdep. */ |
7b112f9c JT |
2942 | } |
2943 | ||
1fcc0bb8 EZ |
2944 | static struct cmd_list_element *info_powerpc_cmdlist = NULL; |
2945 | ||
2946 | static void | |
2947 | rs6000_info_powerpc_command (char *args, int from_tty) | |
2948 | { | |
2949 | help_list (info_powerpc_cmdlist, "info powerpc ", class_info, gdb_stdout); | |
2950 | } | |
2951 | ||
c906108c SS |
2952 | /* Initialization code. */ |
2953 | ||
a78f21af | 2954 | extern initialize_file_ftype _initialize_rs6000_tdep; /* -Wmissing-prototypes */ |
b9362cc7 | 2955 | |
c906108c | 2956 | void |
fba45db2 | 2957 | _initialize_rs6000_tdep (void) |
c906108c | 2958 | { |
7b112f9c JT |
2959 | gdbarch_register (bfd_arch_rs6000, rs6000_gdbarch_init, rs6000_dump_tdep); |
2960 | gdbarch_register (bfd_arch_powerpc, rs6000_gdbarch_init, rs6000_dump_tdep); | |
1fcc0bb8 EZ |
2961 | |
2962 | /* Add root prefix command for "info powerpc" commands */ | |
2963 | add_prefix_cmd ("powerpc", class_info, rs6000_info_powerpc_command, | |
2964 | "Various POWERPC info specific commands.", | |
2965 | &info_powerpc_cmdlist, "info powerpc ", 0, &infolist); | |
c906108c | 2966 | } |