Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for GDB, the GNU debugger. |
7aea86e6 | 2 | |
6aba47ca DJ |
3 | Copyright (C) 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, |
4 | 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 | |
721d14ba | 5 | Free Software Foundation, Inc. |
c906108c | 6 | |
c5aa993b | 7 | This file is part of GDB. |
c906108c | 8 | |
c5aa993b JM |
9 | This program is free software; you can redistribute it and/or modify |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2 of the License, or | |
12 | (at your option) any later version. | |
c906108c | 13 | |
c5aa993b JM |
14 | This program is distributed in the hope that it will be useful, |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
c906108c | 18 | |
c5aa993b JM |
19 | You should have received a copy of the GNU General Public License |
20 | along with this program; if not, write to the Free Software | |
197e01b6 EZ |
21 | Foundation, Inc., 51 Franklin Street, Fifth Floor, |
22 | Boston, MA 02110-1301, USA. */ | |
c906108c SS |
23 | |
24 | #include "defs.h" | |
25 | #include "frame.h" | |
26 | #include "inferior.h" | |
27 | #include "symtab.h" | |
28 | #include "target.h" | |
29 | #include "gdbcore.h" | |
30 | #include "gdbcmd.h" | |
c906108c | 31 | #include "objfiles.h" |
7a78ae4e | 32 | #include "arch-utils.h" |
4e052eda | 33 | #include "regcache.h" |
d195bc9f | 34 | #include "regset.h" |
d16aafd8 | 35 | #include "doublest.h" |
fd0407d6 | 36 | #include "value.h" |
1fcc0bb8 | 37 | #include "parser-defs.h" |
4be87837 | 38 | #include "osabi.h" |
7d9b040b | 39 | #include "infcall.h" |
9f643768 JB |
40 | #include "sim-regno.h" |
41 | #include "gdb/sim-ppc.h" | |
6ced10dd | 42 | #include "reggroups.h" |
4fc771b8 | 43 | #include "dwarf2-frame.h" |
7a78ae4e | 44 | |
2fccf04a | 45 | #include "libbfd.h" /* for bfd_default_set_arch_mach */ |
7a78ae4e | 46 | #include "coff/internal.h" /* for libcoff.h */ |
2fccf04a | 47 | #include "libcoff.h" /* for xcoff_data */ |
11ed25ac KB |
48 | #include "coff/xcoff.h" |
49 | #include "libxcoff.h" | |
7a78ae4e | 50 | |
9aa1e687 | 51 | #include "elf-bfd.h" |
7a78ae4e | 52 | |
6ded7999 | 53 | #include "solib-svr4.h" |
9aa1e687 | 54 | #include "ppc-tdep.h" |
7a78ae4e | 55 | |
338ef23d | 56 | #include "gdb_assert.h" |
a89aa300 | 57 | #include "dis-asm.h" |
338ef23d | 58 | |
61a65099 KB |
59 | #include "trad-frame.h" |
60 | #include "frame-unwind.h" | |
61 | #include "frame-base.h" | |
62 | ||
1f82754b | 63 | #include "rs6000-tdep.h" |
c44ca51c | 64 | |
7a78ae4e ND |
65 | /* If the kernel has to deliver a signal, it pushes a sigcontext |
66 | structure on the stack and then calls the signal handler, passing | |
67 | the address of the sigcontext in an argument register. Usually | |
68 | the signal handler doesn't save this register, so we have to | |
69 | access the sigcontext structure via an offset from the signal handler | |
70 | frame. | |
71 | The following constants were determined by experimentation on AIX 3.2. */ | |
72 | #define SIG_FRAME_PC_OFFSET 96 | |
73 | #define SIG_FRAME_LR_OFFSET 108 | |
74 | #define SIG_FRAME_FP_OFFSET 284 | |
75 | ||
7a78ae4e ND |
76 | /* To be used by skip_prologue. */ |
77 | ||
78 | struct rs6000_framedata | |
79 | { | |
80 | int offset; /* total size of frame --- the distance | |
81 | by which we decrement sp to allocate | |
82 | the frame */ | |
83 | int saved_gpr; /* smallest # of saved gpr */ | |
84 | int saved_fpr; /* smallest # of saved fpr */ | |
6be8bc0c | 85 | int saved_vr; /* smallest # of saved vr */ |
96ff0de4 | 86 | int saved_ev; /* smallest # of saved ev */ |
7a78ae4e ND |
87 | int alloca_reg; /* alloca register number (frame ptr) */ |
88 | char frameless; /* true if frameless functions. */ | |
89 | char nosavedpc; /* true if pc not saved. */ | |
90 | int gpr_offset; /* offset of saved gprs from prev sp */ | |
91 | int fpr_offset; /* offset of saved fprs from prev sp */ | |
6be8bc0c | 92 | int vr_offset; /* offset of saved vrs from prev sp */ |
96ff0de4 | 93 | int ev_offset; /* offset of saved evs from prev sp */ |
7a78ae4e ND |
94 | int lr_offset; /* offset of saved lr */ |
95 | int cr_offset; /* offset of saved cr */ | |
6be8bc0c | 96 | int vrsave_offset; /* offset of saved vrsave register */ |
7a78ae4e ND |
97 | }; |
98 | ||
99 | /* Description of a single register. */ | |
100 | ||
101 | struct reg | |
102 | { | |
103 | char *name; /* name of register */ | |
0bcc32ae JB |
104 | unsigned char sz32; /* size on 32-bit arch, 0 if nonexistent */ |
105 | unsigned char sz64; /* size on 64-bit arch, 0 if nonexistent */ | |
7a78ae4e | 106 | unsigned char fpr; /* whether register is floating-point */ |
489461e2 | 107 | unsigned char pseudo; /* whether register is pseudo */ |
13ac140c JB |
108 | int spr_num; /* PowerPC SPR number, or -1 if not an SPR. |
109 | This is an ISA SPR number, not a GDB | |
110 | register number. */ | |
7a78ae4e ND |
111 | }; |
112 | ||
c906108c SS |
113 | /* Hook for determining the TOC address when calling functions in the |
114 | inferior under AIX. The initialization code in rs6000-nat.c sets | |
115 | this hook to point to find_toc_address. */ | |
116 | ||
7a78ae4e ND |
117 | CORE_ADDR (*rs6000_find_toc_address_hook) (CORE_ADDR) = NULL; |
118 | ||
c906108c SS |
119 | /* Static function prototypes */ |
120 | ||
0b1b3e42 UW |
121 | static CORE_ADDR branch_dest (struct frame_info *frame, int opcode, |
122 | int instr, CORE_ADDR pc, CORE_ADDR safety); | |
077276e8 KB |
123 | static CORE_ADDR skip_prologue (CORE_ADDR, CORE_ADDR, |
124 | struct rs6000_framedata *); | |
c906108c | 125 | |
64b84175 KB |
126 | /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */ |
127 | int | |
128 | altivec_register_p (int regno) | |
129 | { | |
130 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
131 | if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0) | |
132 | return 0; | |
133 | else | |
134 | return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum); | |
135 | } | |
136 | ||
383f0f5b | 137 | |
867e2dc5 JB |
138 | /* Return true if REGNO is an SPE register, false otherwise. */ |
139 | int | |
140 | spe_register_p (int regno) | |
141 | { | |
142 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
143 | ||
144 | /* Is it a reference to EV0 -- EV31, and do we have those? */ | |
145 | if (tdep->ppc_ev0_regnum >= 0 | |
146 | && tdep->ppc_ev31_regnum >= 0 | |
147 | && tdep->ppc_ev0_regnum <= regno && regno <= tdep->ppc_ev31_regnum) | |
148 | return 1; | |
149 | ||
6ced10dd JB |
150 | /* Is it a reference to one of the raw upper GPR halves? */ |
151 | if (tdep->ppc_ev0_upper_regnum >= 0 | |
152 | && tdep->ppc_ev0_upper_regnum <= regno | |
153 | && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) | |
154 | return 1; | |
155 | ||
867e2dc5 JB |
156 | /* Is it a reference to the 64-bit accumulator, and do we have that? */ |
157 | if (tdep->ppc_acc_regnum >= 0 | |
158 | && tdep->ppc_acc_regnum == regno) | |
159 | return 1; | |
160 | ||
161 | /* Is it a reference to the SPE floating-point status and control register, | |
162 | and do we have that? */ | |
163 | if (tdep->ppc_spefscr_regnum >= 0 | |
164 | && tdep->ppc_spefscr_regnum == regno) | |
165 | return 1; | |
166 | ||
167 | return 0; | |
168 | } | |
169 | ||
170 | ||
383f0f5b JB |
171 | /* Return non-zero if the architecture described by GDBARCH has |
172 | floating-point registers (f0 --- f31 and fpscr). */ | |
0a613259 AC |
173 | int |
174 | ppc_floating_point_unit_p (struct gdbarch *gdbarch) | |
175 | { | |
383f0f5b JB |
176 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
177 | ||
178 | return (tdep->ppc_fp0_regnum >= 0 | |
179 | && tdep->ppc_fpscr_regnum >= 0); | |
0a613259 | 180 | } |
9f643768 | 181 | |
09991fa0 JB |
182 | |
183 | /* Check that TABLE[GDB_REGNO] is not already initialized, and then | |
184 | set it to SIM_REGNO. | |
185 | ||
186 | This is a helper function for init_sim_regno_table, constructing | |
187 | the table mapping GDB register numbers to sim register numbers; we | |
188 | initialize every element in that table to -1 before we start | |
189 | filling it in. */ | |
9f643768 JB |
190 | static void |
191 | set_sim_regno (int *table, int gdb_regno, int sim_regno) | |
192 | { | |
193 | /* Make sure we don't try to assign any given GDB register a sim | |
194 | register number more than once. */ | |
195 | gdb_assert (table[gdb_regno] == -1); | |
196 | table[gdb_regno] = sim_regno; | |
197 | } | |
198 | ||
09991fa0 JB |
199 | |
200 | /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register | |
201 | numbers to simulator register numbers, based on the values placed | |
202 | in the ARCH->tdep->ppc_foo_regnum members. */ | |
9f643768 JB |
203 | static void |
204 | init_sim_regno_table (struct gdbarch *arch) | |
205 | { | |
206 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); | |
207 | int total_regs = gdbarch_num_regs (arch) + gdbarch_num_pseudo_regs (arch); | |
208 | const struct reg *regs = tdep->regs; | |
209 | int *sim_regno = GDBARCH_OBSTACK_CALLOC (arch, total_regs, int); | |
210 | int i; | |
211 | ||
212 | /* Presume that all registers not explicitly mentioned below are | |
213 | unavailable from the sim. */ | |
214 | for (i = 0; i < total_regs; i++) | |
215 | sim_regno[i] = -1; | |
216 | ||
217 | /* General-purpose registers. */ | |
218 | for (i = 0; i < ppc_num_gprs; i++) | |
219 | set_sim_regno (sim_regno, tdep->ppc_gp0_regnum + i, sim_ppc_r0_regnum + i); | |
220 | ||
221 | /* Floating-point registers. */ | |
222 | if (tdep->ppc_fp0_regnum >= 0) | |
223 | for (i = 0; i < ppc_num_fprs; i++) | |
224 | set_sim_regno (sim_regno, | |
225 | tdep->ppc_fp0_regnum + i, | |
226 | sim_ppc_f0_regnum + i); | |
227 | if (tdep->ppc_fpscr_regnum >= 0) | |
228 | set_sim_regno (sim_regno, tdep->ppc_fpscr_regnum, sim_ppc_fpscr_regnum); | |
229 | ||
230 | set_sim_regno (sim_regno, gdbarch_pc_regnum (arch), sim_ppc_pc_regnum); | |
231 | set_sim_regno (sim_regno, tdep->ppc_ps_regnum, sim_ppc_ps_regnum); | |
232 | set_sim_regno (sim_regno, tdep->ppc_cr_regnum, sim_ppc_cr_regnum); | |
233 | ||
234 | /* Segment registers. */ | |
235 | if (tdep->ppc_sr0_regnum >= 0) | |
236 | for (i = 0; i < ppc_num_srs; i++) | |
237 | set_sim_regno (sim_regno, | |
238 | tdep->ppc_sr0_regnum + i, | |
239 | sim_ppc_sr0_regnum + i); | |
240 | ||
241 | /* Altivec registers. */ | |
242 | if (tdep->ppc_vr0_regnum >= 0) | |
243 | { | |
244 | for (i = 0; i < ppc_num_vrs; i++) | |
245 | set_sim_regno (sim_regno, | |
246 | tdep->ppc_vr0_regnum + i, | |
247 | sim_ppc_vr0_regnum + i); | |
248 | ||
249 | /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum, | |
250 | we can treat this more like the other cases. */ | |
251 | set_sim_regno (sim_regno, | |
252 | tdep->ppc_vr0_regnum + ppc_num_vrs, | |
253 | sim_ppc_vscr_regnum); | |
254 | } | |
255 | /* vsave is a special-purpose register, so the code below handles it. */ | |
256 | ||
257 | /* SPE APU (E500) registers. */ | |
258 | if (tdep->ppc_ev0_regnum >= 0) | |
259 | for (i = 0; i < ppc_num_gprs; i++) | |
260 | set_sim_regno (sim_regno, | |
261 | tdep->ppc_ev0_regnum + i, | |
262 | sim_ppc_ev0_regnum + i); | |
6ced10dd JB |
263 | if (tdep->ppc_ev0_upper_regnum >= 0) |
264 | for (i = 0; i < ppc_num_gprs; i++) | |
265 | set_sim_regno (sim_regno, | |
266 | tdep->ppc_ev0_upper_regnum + i, | |
267 | sim_ppc_rh0_regnum + i); | |
9f643768 JB |
268 | if (tdep->ppc_acc_regnum >= 0) |
269 | set_sim_regno (sim_regno, tdep->ppc_acc_regnum, sim_ppc_acc_regnum); | |
270 | /* spefscr is a special-purpose register, so the code below handles it. */ | |
271 | ||
272 | /* Now handle all special-purpose registers. Verify that they | |
273 | haven't mistakenly been assigned numbers by any of the above | |
274 | code). */ | |
275 | for (i = 0; i < total_regs; i++) | |
276 | if (regs[i].spr_num >= 0) | |
277 | set_sim_regno (sim_regno, i, regs[i].spr_num + sim_ppc_spr0_regnum); | |
278 | ||
279 | /* Drop the initialized array into place. */ | |
280 | tdep->sim_regno = sim_regno; | |
281 | } | |
282 | ||
09991fa0 JB |
283 | |
284 | /* Given a GDB register number REG, return the corresponding SIM | |
285 | register number. */ | |
9f643768 JB |
286 | static int |
287 | rs6000_register_sim_regno (int reg) | |
288 | { | |
289 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
290 | int sim_regno; | |
291 | ||
f57d151a UW |
292 | gdb_assert (0 <= reg |
293 | && reg <= gdbarch_num_regs (current_gdbarch) | |
294 | + gdbarch_num_pseudo_regs (current_gdbarch)); | |
9f643768 JB |
295 | sim_regno = tdep->sim_regno[reg]; |
296 | ||
297 | if (sim_regno >= 0) | |
298 | return sim_regno; | |
299 | else | |
300 | return LEGACY_SIM_REGNO_IGNORE; | |
301 | } | |
302 | ||
d195bc9f MK |
303 | \f |
304 | ||
305 | /* Register set support functions. */ | |
306 | ||
307 | static void | |
308 | ppc_supply_reg (struct regcache *regcache, int regnum, | |
50fd1280 | 309 | const gdb_byte *regs, size_t offset) |
d195bc9f MK |
310 | { |
311 | if (regnum != -1 && offset != -1) | |
312 | regcache_raw_supply (regcache, regnum, regs + offset); | |
313 | } | |
314 | ||
315 | static void | |
316 | ppc_collect_reg (const struct regcache *regcache, int regnum, | |
50fd1280 | 317 | gdb_byte *regs, size_t offset) |
d195bc9f MK |
318 | { |
319 | if (regnum != -1 && offset != -1) | |
320 | regcache_raw_collect (regcache, regnum, regs + offset); | |
321 | } | |
322 | ||
323 | /* Supply register REGNUM in the general-purpose register set REGSET | |
324 | from the buffer specified by GREGS and LEN to register cache | |
325 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
326 | ||
327 | void | |
328 | ppc_supply_gregset (const struct regset *regset, struct regcache *regcache, | |
329 | int regnum, const void *gregs, size_t len) | |
330 | { | |
331 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
332 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
333 | const struct ppc_reg_offsets *offsets = regset->descr; | |
334 | size_t offset; | |
335 | int i; | |
336 | ||
cdf2c5f5 | 337 | for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset; |
063715bf | 338 | i < tdep->ppc_gp0_regnum + ppc_num_gprs; |
cdf2c5f5 | 339 | i++, offset += 4) |
d195bc9f MK |
340 | { |
341 | if (regnum == -1 || regnum == i) | |
342 | ppc_supply_reg (regcache, i, gregs, offset); | |
343 | } | |
344 | ||
3e8c568d UW |
345 | if (regnum == -1 || regnum == gdbarch_pc_regnum (current_gdbarch)) |
346 | ppc_supply_reg (regcache, gdbarch_pc_regnum (current_gdbarch), | |
347 | gregs, offsets->pc_offset); | |
d195bc9f MK |
348 | if (regnum == -1 || regnum == tdep->ppc_ps_regnum) |
349 | ppc_supply_reg (regcache, tdep->ppc_ps_regnum, | |
350 | gregs, offsets->ps_offset); | |
351 | if (regnum == -1 || regnum == tdep->ppc_cr_regnum) | |
352 | ppc_supply_reg (regcache, tdep->ppc_cr_regnum, | |
353 | gregs, offsets->cr_offset); | |
354 | if (regnum == -1 || regnum == tdep->ppc_lr_regnum) | |
355 | ppc_supply_reg (regcache, tdep->ppc_lr_regnum, | |
356 | gregs, offsets->lr_offset); | |
357 | if (regnum == -1 || regnum == tdep->ppc_ctr_regnum) | |
358 | ppc_supply_reg (regcache, tdep->ppc_ctr_regnum, | |
359 | gregs, offsets->ctr_offset); | |
360 | if (regnum == -1 || regnum == tdep->ppc_xer_regnum) | |
361 | ppc_supply_reg (regcache, tdep->ppc_xer_regnum, | |
362 | gregs, offsets->cr_offset); | |
363 | if (regnum == -1 || regnum == tdep->ppc_mq_regnum) | |
364 | ppc_supply_reg (regcache, tdep->ppc_mq_regnum, gregs, offsets->mq_offset); | |
365 | } | |
366 | ||
367 | /* Supply register REGNUM in the floating-point register set REGSET | |
368 | from the buffer specified by FPREGS and LEN to register cache | |
369 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
370 | ||
371 | void | |
372 | ppc_supply_fpregset (const struct regset *regset, struct regcache *regcache, | |
373 | int regnum, const void *fpregs, size_t len) | |
374 | { | |
375 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
376 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
377 | const struct ppc_reg_offsets *offsets = regset->descr; | |
378 | size_t offset; | |
379 | int i; | |
380 | ||
383f0f5b JB |
381 | gdb_assert (ppc_floating_point_unit_p (gdbarch)); |
382 | ||
d195bc9f | 383 | offset = offsets->f0_offset; |
366f009f JB |
384 | for (i = tdep->ppc_fp0_regnum; |
385 | i < tdep->ppc_fp0_regnum + ppc_num_fprs; | |
bdbcb8b4 | 386 | i++, offset += 8) |
d195bc9f MK |
387 | { |
388 | if (regnum == -1 || regnum == i) | |
389 | ppc_supply_reg (regcache, i, fpregs, offset); | |
390 | } | |
391 | ||
392 | if (regnum == -1 || regnum == tdep->ppc_fpscr_regnum) | |
393 | ppc_supply_reg (regcache, tdep->ppc_fpscr_regnum, | |
394 | fpregs, offsets->fpscr_offset); | |
395 | } | |
396 | ||
397 | /* Collect register REGNUM in the general-purpose register set | |
398 | REGSET. from register cache REGCACHE into the buffer specified by | |
399 | GREGS and LEN. If REGNUM is -1, do this for all registers in | |
400 | REGSET. */ | |
401 | ||
402 | void | |
403 | ppc_collect_gregset (const struct regset *regset, | |
404 | const struct regcache *regcache, | |
405 | int regnum, void *gregs, size_t len) | |
406 | { | |
407 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
408 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
409 | const struct ppc_reg_offsets *offsets = regset->descr; | |
410 | size_t offset; | |
411 | int i; | |
412 | ||
413 | offset = offsets->r0_offset; | |
cdf2c5f5 | 414 | for (i = tdep->ppc_gp0_regnum; |
063715bf | 415 | i < tdep->ppc_gp0_regnum + ppc_num_gprs; |
cdf2c5f5 | 416 | i++, offset += 4) |
d195bc9f MK |
417 | { |
418 | if (regnum == -1 || regnum == i) | |
2e56e9c1 | 419 | ppc_collect_reg (regcache, i, gregs, offset); |
d195bc9f MK |
420 | } |
421 | ||
3e8c568d UW |
422 | if (regnum == -1 || regnum == gdbarch_pc_regnum (current_gdbarch)) |
423 | ppc_collect_reg (regcache, gdbarch_pc_regnum (current_gdbarch), | |
424 | gregs, offsets->pc_offset); | |
d195bc9f MK |
425 | if (regnum == -1 || regnum == tdep->ppc_ps_regnum) |
426 | ppc_collect_reg (regcache, tdep->ppc_ps_regnum, | |
427 | gregs, offsets->ps_offset); | |
428 | if (regnum == -1 || regnum == tdep->ppc_cr_regnum) | |
429 | ppc_collect_reg (regcache, tdep->ppc_cr_regnum, | |
430 | gregs, offsets->cr_offset); | |
431 | if (regnum == -1 || regnum == tdep->ppc_lr_regnum) | |
432 | ppc_collect_reg (regcache, tdep->ppc_lr_regnum, | |
433 | gregs, offsets->lr_offset); | |
434 | if (regnum == -1 || regnum == tdep->ppc_ctr_regnum) | |
435 | ppc_collect_reg (regcache, tdep->ppc_ctr_regnum, | |
436 | gregs, offsets->ctr_offset); | |
437 | if (regnum == -1 || regnum == tdep->ppc_xer_regnum) | |
438 | ppc_collect_reg (regcache, tdep->ppc_xer_regnum, | |
439 | gregs, offsets->xer_offset); | |
440 | if (regnum == -1 || regnum == tdep->ppc_mq_regnum) | |
441 | ppc_collect_reg (regcache, tdep->ppc_mq_regnum, | |
442 | gregs, offsets->mq_offset); | |
443 | } | |
444 | ||
445 | /* Collect register REGNUM in the floating-point register set | |
446 | REGSET. from register cache REGCACHE into the buffer specified by | |
447 | FPREGS and LEN. If REGNUM is -1, do this for all registers in | |
448 | REGSET. */ | |
449 | ||
450 | void | |
451 | ppc_collect_fpregset (const struct regset *regset, | |
452 | const struct regcache *regcache, | |
453 | int regnum, void *fpregs, size_t len) | |
454 | { | |
455 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
456 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
457 | const struct ppc_reg_offsets *offsets = regset->descr; | |
458 | size_t offset; | |
459 | int i; | |
460 | ||
383f0f5b JB |
461 | gdb_assert (ppc_floating_point_unit_p (gdbarch)); |
462 | ||
d195bc9f | 463 | offset = offsets->f0_offset; |
366f009f JB |
464 | for (i = tdep->ppc_fp0_regnum; |
465 | i <= tdep->ppc_fp0_regnum + ppc_num_fprs; | |
bdbcb8b4 | 466 | i++, offset += 8) |
d195bc9f MK |
467 | { |
468 | if (regnum == -1 || regnum == i) | |
bdbcb8b4 | 469 | ppc_collect_reg (regcache, i, fpregs, offset); |
d195bc9f MK |
470 | } |
471 | ||
472 | if (regnum == -1 || regnum == tdep->ppc_fpscr_regnum) | |
473 | ppc_collect_reg (regcache, tdep->ppc_fpscr_regnum, | |
474 | fpregs, offsets->fpscr_offset); | |
475 | } | |
476 | \f | |
0a613259 | 477 | |
7a78ae4e | 478 | /* Read a LEN-byte address from debugged memory address MEMADDR. */ |
c906108c | 479 | |
7a78ae4e ND |
480 | static CORE_ADDR |
481 | read_memory_addr (CORE_ADDR memaddr, int len) | |
482 | { | |
483 | return read_memory_unsigned_integer (memaddr, len); | |
484 | } | |
c906108c | 485 | |
7a78ae4e ND |
486 | static CORE_ADDR |
487 | rs6000_skip_prologue (CORE_ADDR pc) | |
b83266a0 SS |
488 | { |
489 | struct rs6000_framedata frame; | |
4e463ff5 DJ |
490 | CORE_ADDR limit_pc, func_addr; |
491 | ||
492 | /* See if we can determine the end of the prologue via the symbol table. | |
493 | If so, then return either PC, or the PC after the prologue, whichever | |
494 | is greater. */ | |
495 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) | |
496 | { | |
497 | CORE_ADDR post_prologue_pc = skip_prologue_using_sal (func_addr); | |
498 | if (post_prologue_pc != 0) | |
499 | return max (pc, post_prologue_pc); | |
500 | } | |
501 | ||
502 | /* Can't determine prologue from the symbol table, need to examine | |
503 | instructions. */ | |
504 | ||
505 | /* Find an upper limit on the function prologue using the debug | |
506 | information. If the debug information could not be used to provide | |
507 | that bound, then use an arbitrary large number as the upper bound. */ | |
508 | limit_pc = skip_prologue_using_sal (pc); | |
509 | if (limit_pc == 0) | |
510 | limit_pc = pc + 100; /* Magic. */ | |
511 | ||
512 | pc = skip_prologue (pc, limit_pc, &frame); | |
b83266a0 SS |
513 | return pc; |
514 | } | |
515 | ||
0d1243d9 PG |
516 | static int |
517 | insn_changes_sp_or_jumps (unsigned long insn) | |
518 | { | |
519 | int opcode = (insn >> 26) & 0x03f; | |
520 | int sd = (insn >> 21) & 0x01f; | |
521 | int a = (insn >> 16) & 0x01f; | |
522 | int subcode = (insn >> 1) & 0x3ff; | |
523 | ||
524 | /* Changes the stack pointer. */ | |
525 | ||
526 | /* NOTE: There are many ways to change the value of a given register. | |
527 | The ways below are those used when the register is R1, the SP, | |
528 | in a funtion's epilogue. */ | |
529 | ||
530 | if (opcode == 31 && subcode == 444 && a == 1) | |
531 | return 1; /* mr R1,Rn */ | |
532 | if (opcode == 14 && sd == 1) | |
533 | return 1; /* addi R1,Rn,simm */ | |
534 | if (opcode == 58 && sd == 1) | |
535 | return 1; /* ld R1,ds(Rn) */ | |
536 | ||
537 | /* Transfers control. */ | |
538 | ||
539 | if (opcode == 18) | |
540 | return 1; /* b */ | |
541 | if (opcode == 16) | |
542 | return 1; /* bc */ | |
543 | if (opcode == 19 && subcode == 16) | |
544 | return 1; /* bclr */ | |
545 | if (opcode == 19 && subcode == 528) | |
546 | return 1; /* bcctr */ | |
547 | ||
548 | return 0; | |
549 | } | |
550 | ||
551 | /* Return true if we are in the function's epilogue, i.e. after the | |
552 | instruction that destroyed the function's stack frame. | |
553 | ||
554 | 1) scan forward from the point of execution: | |
555 | a) If you find an instruction that modifies the stack pointer | |
556 | or transfers control (except a return), execution is not in | |
557 | an epilogue, return. | |
558 | b) Stop scanning if you find a return instruction or reach the | |
559 | end of the function or reach the hard limit for the size of | |
560 | an epilogue. | |
561 | 2) scan backward from the point of execution: | |
562 | a) If you find an instruction that modifies the stack pointer, | |
563 | execution *is* in an epilogue, return. | |
564 | b) Stop scanning if you reach an instruction that transfers | |
565 | control or the beginning of the function or reach the hard | |
566 | limit for the size of an epilogue. */ | |
567 | ||
568 | static int | |
569 | rs6000_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
570 | { | |
571 | bfd_byte insn_buf[PPC_INSN_SIZE]; | |
572 | CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end; | |
573 | unsigned long insn; | |
574 | struct frame_info *curfrm; | |
575 | ||
576 | /* Find the search limits based on function boundaries and hard limit. */ | |
577 | ||
578 | if (!find_pc_partial_function (pc, NULL, &func_start, &func_end)) | |
579 | return 0; | |
580 | ||
581 | epilogue_start = pc - PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE; | |
582 | if (epilogue_start < func_start) epilogue_start = func_start; | |
583 | ||
584 | epilogue_end = pc + PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE; | |
585 | if (epilogue_end > func_end) epilogue_end = func_end; | |
586 | ||
587 | curfrm = get_current_frame (); | |
588 | ||
589 | /* Scan forward until next 'blr'. */ | |
590 | ||
591 | for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += PPC_INSN_SIZE) | |
592 | { | |
593 | if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE)) | |
594 | return 0; | |
4e463ff5 | 595 | insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE); |
0d1243d9 PG |
596 | if (insn == 0x4e800020) |
597 | break; | |
598 | if (insn_changes_sp_or_jumps (insn)) | |
599 | return 0; | |
600 | } | |
601 | ||
602 | /* Scan backward until adjustment to stack pointer (R1). */ | |
603 | ||
604 | for (scan_pc = pc - PPC_INSN_SIZE; | |
605 | scan_pc >= epilogue_start; | |
606 | scan_pc -= PPC_INSN_SIZE) | |
607 | { | |
608 | if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE)) | |
609 | return 0; | |
4e463ff5 | 610 | insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE); |
0d1243d9 PG |
611 | if (insn_changes_sp_or_jumps (insn)) |
612 | return 1; | |
613 | } | |
614 | ||
615 | return 0; | |
616 | } | |
617 | ||
143985b7 | 618 | /* Get the ith function argument for the current function. */ |
b9362cc7 | 619 | static CORE_ADDR |
143985b7 AF |
620 | rs6000_fetch_pointer_argument (struct frame_info *frame, int argi, |
621 | struct type *type) | |
622 | { | |
50fd1280 | 623 | return get_frame_register_unsigned (frame, 3 + argi); |
143985b7 AF |
624 | } |
625 | ||
c906108c SS |
626 | /* Calculate the destination of a branch/jump. Return -1 if not a branch. */ |
627 | ||
628 | static CORE_ADDR | |
0b1b3e42 UW |
629 | branch_dest (struct frame_info *frame, int opcode, int instr, |
630 | CORE_ADDR pc, CORE_ADDR safety) | |
c906108c | 631 | { |
0b1b3e42 | 632 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (frame)); |
c906108c SS |
633 | CORE_ADDR dest; |
634 | int immediate; | |
635 | int absolute; | |
636 | int ext_op; | |
637 | ||
638 | absolute = (int) ((instr >> 1) & 1); | |
639 | ||
c5aa993b JM |
640 | switch (opcode) |
641 | { | |
642 | case 18: | |
643 | immediate = ((instr & ~3) << 6) >> 6; /* br unconditional */ | |
644 | if (absolute) | |
645 | dest = immediate; | |
646 | else | |
647 | dest = pc + immediate; | |
648 | break; | |
649 | ||
650 | case 16: | |
651 | immediate = ((instr & ~3) << 16) >> 16; /* br conditional */ | |
652 | if (absolute) | |
653 | dest = immediate; | |
654 | else | |
655 | dest = pc + immediate; | |
656 | break; | |
657 | ||
658 | case 19: | |
659 | ext_op = (instr >> 1) & 0x3ff; | |
660 | ||
661 | if (ext_op == 16) /* br conditional register */ | |
662 | { | |
0b1b3e42 | 663 | dest = get_frame_register_unsigned (frame, tdep->ppc_lr_regnum) & ~3; |
c5aa993b JM |
664 | |
665 | /* If we are about to return from a signal handler, dest is | |
666 | something like 0x3c90. The current frame is a signal handler | |
667 | caller frame, upon completion of the sigreturn system call | |
668 | execution will return to the saved PC in the frame. */ | |
0b1b3e42 UW |
669 | if (dest < tdep->text_segment_base) |
670 | dest = read_memory_addr (get_frame_base (frame) + SIG_FRAME_PC_OFFSET, | |
671 | tdep->wordsize); | |
c5aa993b JM |
672 | } |
673 | ||
674 | else if (ext_op == 528) /* br cond to count reg */ | |
675 | { | |
0b1b3e42 | 676 | dest = get_frame_register_unsigned (frame, tdep->ppc_ctr_regnum) & ~3; |
c5aa993b JM |
677 | |
678 | /* If we are about to execute a system call, dest is something | |
679 | like 0x22fc or 0x3b00. Upon completion the system call | |
680 | will return to the address in the link register. */ | |
0b1b3e42 UW |
681 | if (dest < tdep->text_segment_base) |
682 | dest = get_frame_register_unsigned (frame, tdep->ppc_lr_regnum) & ~3; | |
c5aa993b JM |
683 | } |
684 | else | |
685 | return -1; | |
686 | break; | |
c906108c | 687 | |
c5aa993b JM |
688 | default: |
689 | return -1; | |
690 | } | |
0b1b3e42 | 691 | return (dest < tdep->text_segment_base) ? safety : dest; |
c906108c SS |
692 | } |
693 | ||
694 | ||
695 | /* Sequence of bytes for breakpoint instruction. */ | |
696 | ||
f4f9705a | 697 | const static unsigned char * |
7a78ae4e | 698 | rs6000_breakpoint_from_pc (CORE_ADDR *bp_addr, int *bp_size) |
c906108c | 699 | { |
aaab4dba AC |
700 | static unsigned char big_breakpoint[] = { 0x7d, 0x82, 0x10, 0x08 }; |
701 | static unsigned char little_breakpoint[] = { 0x08, 0x10, 0x82, 0x7d }; | |
c906108c | 702 | *bp_size = 4; |
4c6b5505 | 703 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
c906108c SS |
704 | return big_breakpoint; |
705 | else | |
706 | return little_breakpoint; | |
707 | } | |
708 | ||
709 | ||
ce5eab59 UW |
710 | /* Instruction masks used during single-stepping of atomic sequences. */ |
711 | #define LWARX_MASK 0xfc0007fe | |
712 | #define LWARX_INSTRUCTION 0x7c000028 | |
713 | #define LDARX_INSTRUCTION 0x7c0000A8 | |
714 | #define STWCX_MASK 0xfc0007ff | |
715 | #define STWCX_INSTRUCTION 0x7c00012d | |
716 | #define STDCX_INSTRUCTION 0x7c0001ad | |
717 | #define BC_MASK 0xfc000000 | |
718 | #define BC_INSTRUCTION 0x40000000 | |
719 | ||
720 | /* Checks for an atomic sequence of instructions beginning with a LWARX/LDARX | |
721 | instruction and ending with a STWCX/STDCX instruction. If such a sequence | |
722 | is found, attempt to step through it. A breakpoint is placed at the end of | |
723 | the sequence. */ | |
724 | ||
725 | static int | |
0b1b3e42 | 726 | deal_with_atomic_sequence (struct frame_info *frame) |
ce5eab59 | 727 | { |
0b1b3e42 | 728 | CORE_ADDR pc = get_frame_pc (frame); |
ce5eab59 UW |
729 | CORE_ADDR breaks[2] = {-1, -1}; |
730 | CORE_ADDR loc = pc; | |
731 | CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */ | |
24d45690 | 732 | CORE_ADDR closing_insn; /* Instruction that closes the atomic sequence. */ |
ce5eab59 UW |
733 | int insn = read_memory_integer (loc, PPC_INSN_SIZE); |
734 | int insn_count; | |
735 | int index; | |
736 | int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ | |
737 | const int atomic_sequence_length = 16; /* Instruction sequence length. */ | |
24d45690 | 738 | int opcode; /* Branch instruction's OPcode. */ |
ce5eab59 UW |
739 | int bc_insn_count = 0; /* Conditional branch instruction count. */ |
740 | ||
741 | /* Assume all atomic sequences start with a lwarx/ldarx instruction. */ | |
742 | if ((insn & LWARX_MASK) != LWARX_INSTRUCTION | |
743 | && (insn & LWARX_MASK) != LDARX_INSTRUCTION) | |
744 | return 0; | |
745 | ||
746 | /* Assume that no atomic sequence is longer than "atomic_sequence_length" | |
747 | instructions. */ | |
748 | for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) | |
749 | { | |
750 | loc += PPC_INSN_SIZE; | |
751 | insn = read_memory_integer (loc, PPC_INSN_SIZE); | |
752 | ||
753 | /* Assume that there is at most one conditional branch in the atomic | |
754 | sequence. If a conditional branch is found, put a breakpoint in | |
755 | its destination address. */ | |
756 | if ((insn & BC_MASK) == BC_INSTRUCTION) | |
757 | { | |
758 | if (bc_insn_count >= 1) | |
759 | return 0; /* More than one conditional branch found, fallback | |
760 | to the standard single-step code. */ | |
761 | ||
24d45690 | 762 | opcode = insn >> 26; |
0b1b3e42 | 763 | branch_bp = branch_dest (frame, opcode, insn, pc, breaks[0]); |
ce5eab59 UW |
764 | |
765 | if (branch_bp != -1) | |
766 | { | |
767 | breaks[1] = branch_bp; | |
768 | bc_insn_count++; | |
769 | last_breakpoint++; | |
770 | } | |
771 | } | |
772 | ||
773 | if ((insn & STWCX_MASK) == STWCX_INSTRUCTION | |
774 | || (insn & STWCX_MASK) == STDCX_INSTRUCTION) | |
775 | break; | |
776 | } | |
777 | ||
778 | /* Assume that the atomic sequence ends with a stwcx/stdcx instruction. */ | |
779 | if ((insn & STWCX_MASK) != STWCX_INSTRUCTION | |
780 | && (insn & STWCX_MASK) != STDCX_INSTRUCTION) | |
781 | return 0; | |
782 | ||
24d45690 | 783 | closing_insn = loc; |
ce5eab59 UW |
784 | loc += PPC_INSN_SIZE; |
785 | insn = read_memory_integer (loc, PPC_INSN_SIZE); | |
786 | ||
787 | /* Insert a breakpoint right after the end of the atomic sequence. */ | |
788 | breaks[0] = loc; | |
789 | ||
24d45690 UW |
790 | /* Check for duplicated breakpoints. Check also for a breakpoint |
791 | placed (branch instruction's destination) at the stwcx/stdcx | |
792 | instruction, this resets the reservation and take us back to the | |
793 | lwarx/ldarx instruction at the beginning of the atomic sequence. */ | |
794 | if (last_breakpoint && ((breaks[1] == breaks[0]) | |
795 | || (breaks[1] == closing_insn))) | |
ce5eab59 UW |
796 | last_breakpoint = 0; |
797 | ||
798 | /* Effectively inserts the breakpoints. */ | |
799 | for (index = 0; index <= last_breakpoint; index++) | |
800 | insert_single_step_breakpoint (breaks[index]); | |
801 | ||
802 | return 1; | |
803 | } | |
804 | ||
805 | /* AIX does not support PT_STEP. Simulate it. */ | |
c906108c | 806 | |
e6590a1b | 807 | int |
0b1b3e42 | 808 | rs6000_software_single_step (struct frame_info *frame) |
c906108c | 809 | { |
7c40d541 KB |
810 | CORE_ADDR dummy; |
811 | int breakp_sz; | |
50fd1280 | 812 | const gdb_byte *breakp = rs6000_breakpoint_from_pc (&dummy, &breakp_sz); |
c906108c SS |
813 | int ii, insn; |
814 | CORE_ADDR loc; | |
815 | CORE_ADDR breaks[2]; | |
816 | int opcode; | |
817 | ||
0b1b3e42 | 818 | loc = get_frame_pc (frame); |
c906108c | 819 | |
e0cd558a | 820 | insn = read_memory_integer (loc, 4); |
c906108c | 821 | |
0b1b3e42 | 822 | if (deal_with_atomic_sequence (frame)) |
ce5eab59 UW |
823 | return 1; |
824 | ||
e0cd558a UW |
825 | breaks[0] = loc + breakp_sz; |
826 | opcode = insn >> 26; | |
0b1b3e42 | 827 | breaks[1] = branch_dest (frame, opcode, insn, loc, breaks[0]); |
c906108c | 828 | |
e0cd558a UW |
829 | /* Don't put two breakpoints on the same address. */ |
830 | if (breaks[1] == breaks[0]) | |
831 | breaks[1] = -1; | |
c906108c | 832 | |
e0cd558a UW |
833 | for (ii = 0; ii < 2; ++ii) |
834 | { | |
835 | /* ignore invalid breakpoint. */ | |
836 | if (breaks[ii] == -1) | |
837 | continue; | |
838 | insert_single_step_breakpoint (breaks[ii]); | |
c5aa993b | 839 | } |
c906108c | 840 | |
c906108c | 841 | errno = 0; /* FIXME, don't ignore errors! */ |
c5aa993b | 842 | /* What errors? {read,write}_memory call error(). */ |
e6590a1b | 843 | return 1; |
c906108c SS |
844 | } |
845 | ||
846 | ||
847 | /* return pc value after skipping a function prologue and also return | |
848 | information about a function frame. | |
849 | ||
850 | in struct rs6000_framedata fdata: | |
c5aa993b JM |
851 | - frameless is TRUE, if function does not have a frame. |
852 | - nosavedpc is TRUE, if function does not save %pc value in its frame. | |
853 | - offset is the initial size of this stack frame --- the amount by | |
854 | which we decrement the sp to allocate the frame. | |
855 | - saved_gpr is the number of the first saved gpr. | |
856 | - saved_fpr is the number of the first saved fpr. | |
6be8bc0c | 857 | - saved_vr is the number of the first saved vr. |
96ff0de4 | 858 | - saved_ev is the number of the first saved ev. |
c5aa993b JM |
859 | - alloca_reg is the number of the register used for alloca() handling. |
860 | Otherwise -1. | |
861 | - gpr_offset is the offset of the first saved gpr from the previous frame. | |
862 | - fpr_offset is the offset of the first saved fpr from the previous frame. | |
6be8bc0c | 863 | - vr_offset is the offset of the first saved vr from the previous frame. |
96ff0de4 | 864 | - ev_offset is the offset of the first saved ev from the previous frame. |
c5aa993b JM |
865 | - lr_offset is the offset of the saved lr |
866 | - cr_offset is the offset of the saved cr | |
6be8bc0c | 867 | - vrsave_offset is the offset of the saved vrsave register |
c5aa993b | 868 | */ |
c906108c SS |
869 | |
870 | #define SIGNED_SHORT(x) \ | |
871 | ((sizeof (short) == 2) \ | |
872 | ? ((int)(short)(x)) \ | |
873 | : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000))) | |
874 | ||
875 | #define GET_SRC_REG(x) (((x) >> 21) & 0x1f) | |
876 | ||
55d05f3b KB |
877 | /* Limit the number of skipped non-prologue instructions, as the examining |
878 | of the prologue is expensive. */ | |
879 | static int max_skip_non_prologue_insns = 10; | |
880 | ||
773df3e5 JB |
881 | /* Return nonzero if the given instruction OP can be part of the prologue |
882 | of a function and saves a parameter on the stack. FRAMEP should be | |
883 | set if one of the previous instructions in the function has set the | |
884 | Frame Pointer. */ | |
885 | ||
886 | static int | |
887 | store_param_on_stack_p (unsigned long op, int framep, int *r0_contains_arg) | |
888 | { | |
889 | /* Move parameters from argument registers to temporary register. */ | |
890 | if ((op & 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */ | |
891 | { | |
892 | /* Rx must be scratch register r0. */ | |
893 | const int rx_regno = (op >> 16) & 31; | |
894 | /* Ry: Only r3 - r10 are used for parameter passing. */ | |
895 | const int ry_regno = GET_SRC_REG (op); | |
896 | ||
897 | if (rx_regno == 0 && ry_regno >= 3 && ry_regno <= 10) | |
898 | { | |
899 | *r0_contains_arg = 1; | |
900 | return 1; | |
901 | } | |
902 | else | |
903 | return 0; | |
904 | } | |
905 | ||
906 | /* Save a General Purpose Register on stack. */ | |
907 | ||
908 | if ((op & 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */ | |
909 | (op & 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */ | |
910 | { | |
911 | /* Rx: Only r3 - r10 are used for parameter passing. */ | |
912 | const int rx_regno = GET_SRC_REG (op); | |
913 | ||
914 | return (rx_regno >= 3 && rx_regno <= 10); | |
915 | } | |
916 | ||
917 | /* Save a General Purpose Register on stack via the Frame Pointer. */ | |
918 | ||
919 | if (framep && | |
920 | ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */ | |
921 | (op & 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */ | |
922 | (op & 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */ | |
923 | { | |
924 | /* Rx: Usually, only r3 - r10 are used for parameter passing. | |
925 | However, the compiler sometimes uses r0 to hold an argument. */ | |
926 | const int rx_regno = GET_SRC_REG (op); | |
927 | ||
928 | return ((rx_regno >= 3 && rx_regno <= 10) | |
929 | || (rx_regno == 0 && *r0_contains_arg)); | |
930 | } | |
931 | ||
932 | if ((op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */ | |
933 | { | |
934 | /* Only f2 - f8 are used for parameter passing. */ | |
935 | const int src_regno = GET_SRC_REG (op); | |
936 | ||
937 | return (src_regno >= 2 && src_regno <= 8); | |
938 | } | |
939 | ||
940 | if (framep && ((op & 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */ | |
941 | { | |
942 | /* Only f2 - f8 are used for parameter passing. */ | |
943 | const int src_regno = GET_SRC_REG (op); | |
944 | ||
945 | return (src_regno >= 2 && src_regno <= 8); | |
946 | } | |
947 | ||
948 | /* Not an insn that saves a parameter on stack. */ | |
949 | return 0; | |
950 | } | |
55d05f3b | 951 | |
3c77c82a DJ |
952 | /* Assuming that INSN is a "bl" instruction located at PC, return |
953 | nonzero if the destination of the branch is a "blrl" instruction. | |
954 | ||
955 | This sequence is sometimes found in certain function prologues. | |
956 | It allows the function to load the LR register with a value that | |
957 | they can use to access PIC data using PC-relative offsets. */ | |
958 | ||
959 | static int | |
960 | bl_to_blrl_insn_p (CORE_ADDR pc, int insn) | |
961 | { | |
0b1b3e42 UW |
962 | CORE_ADDR dest; |
963 | int immediate; | |
964 | int absolute; | |
3c77c82a DJ |
965 | int dest_insn; |
966 | ||
0b1b3e42 UW |
967 | absolute = (int) ((insn >> 1) & 1); |
968 | immediate = ((insn & ~3) << 6) >> 6; | |
969 | if (absolute) | |
970 | dest = immediate; | |
971 | else | |
972 | dest = pc + immediate; | |
973 | ||
3c77c82a DJ |
974 | dest_insn = read_memory_integer (dest, 4); |
975 | if ((dest_insn & 0xfc00ffff) == 0x4c000021) /* blrl */ | |
976 | return 1; | |
977 | ||
978 | return 0; | |
979 | } | |
980 | ||
7a78ae4e | 981 | static CORE_ADDR |
077276e8 | 982 | skip_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct rs6000_framedata *fdata) |
c906108c SS |
983 | { |
984 | CORE_ADDR orig_pc = pc; | |
55d05f3b | 985 | CORE_ADDR last_prologue_pc = pc; |
6be8bc0c | 986 | CORE_ADDR li_found_pc = 0; |
50fd1280 | 987 | gdb_byte buf[4]; |
c906108c SS |
988 | unsigned long op; |
989 | long offset = 0; | |
6be8bc0c | 990 | long vr_saved_offset = 0; |
482ca3f5 KB |
991 | int lr_reg = -1; |
992 | int cr_reg = -1; | |
6be8bc0c | 993 | int vr_reg = -1; |
96ff0de4 EZ |
994 | int ev_reg = -1; |
995 | long ev_offset = 0; | |
6be8bc0c | 996 | int vrsave_reg = -1; |
c906108c SS |
997 | int reg; |
998 | int framep = 0; | |
999 | int minimal_toc_loaded = 0; | |
ddb20c56 | 1000 | int prev_insn_was_prologue_insn = 1; |
55d05f3b | 1001 | int num_skip_non_prologue_insns = 0; |
773df3e5 | 1002 | int r0_contains_arg = 0; |
96ff0de4 | 1003 | const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (current_gdbarch); |
6f99cb26 | 1004 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c | 1005 | |
ddb20c56 | 1006 | memset (fdata, 0, sizeof (struct rs6000_framedata)); |
c906108c SS |
1007 | fdata->saved_gpr = -1; |
1008 | fdata->saved_fpr = -1; | |
6be8bc0c | 1009 | fdata->saved_vr = -1; |
96ff0de4 | 1010 | fdata->saved_ev = -1; |
c906108c SS |
1011 | fdata->alloca_reg = -1; |
1012 | fdata->frameless = 1; | |
1013 | fdata->nosavedpc = 1; | |
1014 | ||
55d05f3b | 1015 | for (;; pc += 4) |
c906108c | 1016 | { |
ddb20c56 KB |
1017 | /* Sometimes it isn't clear if an instruction is a prologue |
1018 | instruction or not. When we encounter one of these ambiguous | |
1019 | cases, we'll set prev_insn_was_prologue_insn to 0 (false). | |
1020 | Otherwise, we'll assume that it really is a prologue instruction. */ | |
1021 | if (prev_insn_was_prologue_insn) | |
1022 | last_prologue_pc = pc; | |
55d05f3b KB |
1023 | |
1024 | /* Stop scanning if we've hit the limit. */ | |
4e463ff5 | 1025 | if (pc >= lim_pc) |
55d05f3b KB |
1026 | break; |
1027 | ||
ddb20c56 KB |
1028 | prev_insn_was_prologue_insn = 1; |
1029 | ||
55d05f3b | 1030 | /* Fetch the instruction and convert it to an integer. */ |
ddb20c56 KB |
1031 | if (target_read_memory (pc, buf, 4)) |
1032 | break; | |
4e463ff5 | 1033 | op = extract_unsigned_integer (buf, 4); |
c906108c | 1034 | |
c5aa993b JM |
1035 | if ((op & 0xfc1fffff) == 0x7c0802a6) |
1036 | { /* mflr Rx */ | |
43b1ab88 AC |
1037 | /* Since shared library / PIC code, which needs to get its |
1038 | address at runtime, can appear to save more than one link | |
1039 | register vis: | |
1040 | ||
1041 | *INDENT-OFF* | |
1042 | stwu r1,-304(r1) | |
1043 | mflr r3 | |
1044 | bl 0xff570d0 (blrl) | |
1045 | stw r30,296(r1) | |
1046 | mflr r30 | |
1047 | stw r31,300(r1) | |
1048 | stw r3,308(r1); | |
1049 | ... | |
1050 | *INDENT-ON* | |
1051 | ||
1052 | remember just the first one, but skip over additional | |
1053 | ones. */ | |
721d14ba | 1054 | if (lr_reg == -1) |
43b1ab88 | 1055 | lr_reg = (op & 0x03e00000); |
773df3e5 JB |
1056 | if (lr_reg == 0) |
1057 | r0_contains_arg = 0; | |
c5aa993b | 1058 | continue; |
c5aa993b JM |
1059 | } |
1060 | else if ((op & 0xfc1fffff) == 0x7c000026) | |
1061 | { /* mfcr Rx */ | |
98f08d3d | 1062 | cr_reg = (op & 0x03e00000); |
773df3e5 JB |
1063 | if (cr_reg == 0) |
1064 | r0_contains_arg = 0; | |
c5aa993b | 1065 | continue; |
c906108c | 1066 | |
c906108c | 1067 | } |
c5aa993b JM |
1068 | else if ((op & 0xfc1f0000) == 0xd8010000) |
1069 | { /* stfd Rx,NUM(r1) */ | |
1070 | reg = GET_SRC_REG (op); | |
1071 | if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg) | |
1072 | { | |
1073 | fdata->saved_fpr = reg; | |
1074 | fdata->fpr_offset = SIGNED_SHORT (op) + offset; | |
1075 | } | |
1076 | continue; | |
c906108c | 1077 | |
c5aa993b JM |
1078 | } |
1079 | else if (((op & 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */ | |
7a78ae4e ND |
1080 | (((op & 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */ |
1081 | (op & 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */ | |
1082 | (op & 0x03e00000) >= 0x01a00000)) /* rx >= r13 */ | |
c5aa993b JM |
1083 | { |
1084 | ||
1085 | reg = GET_SRC_REG (op); | |
1086 | if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg) | |
1087 | { | |
1088 | fdata->saved_gpr = reg; | |
7a78ae4e | 1089 | if ((op & 0xfc1f0003) == 0xf8010000) |
98f08d3d | 1090 | op &= ~3UL; |
c5aa993b JM |
1091 | fdata->gpr_offset = SIGNED_SHORT (op) + offset; |
1092 | } | |
1093 | continue; | |
c906108c | 1094 | |
ddb20c56 KB |
1095 | } |
1096 | else if ((op & 0xffff0000) == 0x60000000) | |
1097 | { | |
96ff0de4 | 1098 | /* nop */ |
ddb20c56 KB |
1099 | /* Allow nops in the prologue, but do not consider them to |
1100 | be part of the prologue unless followed by other prologue | |
1101 | instructions. */ | |
1102 | prev_insn_was_prologue_insn = 0; | |
1103 | continue; | |
1104 | ||
c906108c | 1105 | } |
c5aa993b JM |
1106 | else if ((op & 0xffff0000) == 0x3c000000) |
1107 | { /* addis 0,0,NUM, used | |
1108 | for >= 32k frames */ | |
1109 | fdata->offset = (op & 0x0000ffff) << 16; | |
1110 | fdata->frameless = 0; | |
773df3e5 | 1111 | r0_contains_arg = 0; |
c5aa993b JM |
1112 | continue; |
1113 | ||
1114 | } | |
1115 | else if ((op & 0xffff0000) == 0x60000000) | |
1116 | { /* ori 0,0,NUM, 2nd ha | |
1117 | lf of >= 32k frames */ | |
1118 | fdata->offset |= (op & 0x0000ffff); | |
1119 | fdata->frameless = 0; | |
773df3e5 | 1120 | r0_contains_arg = 0; |
c5aa993b JM |
1121 | continue; |
1122 | ||
1123 | } | |
be723e22 | 1124 | else if (lr_reg >= 0 && |
98f08d3d KB |
1125 | /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */ |
1126 | (((op & 0xffff0000) == (lr_reg | 0xf8010000)) || | |
1127 | /* stw Rx, NUM(r1) */ | |
1128 | ((op & 0xffff0000) == (lr_reg | 0x90010000)) || | |
1129 | /* stwu Rx, NUM(r1) */ | |
1130 | ((op & 0xffff0000) == (lr_reg | 0x94010000)))) | |
1131 | { /* where Rx == lr */ | |
1132 | fdata->lr_offset = offset; | |
c5aa993b | 1133 | fdata->nosavedpc = 0; |
be723e22 MS |
1134 | /* Invalidate lr_reg, but don't set it to -1. |
1135 | That would mean that it had never been set. */ | |
1136 | lr_reg = -2; | |
98f08d3d KB |
1137 | if ((op & 0xfc000003) == 0xf8000000 || /* std */ |
1138 | (op & 0xfc000000) == 0x90000000) /* stw */ | |
1139 | { | |
1140 | /* Does not update r1, so add displacement to lr_offset. */ | |
1141 | fdata->lr_offset += SIGNED_SHORT (op); | |
1142 | } | |
c5aa993b JM |
1143 | continue; |
1144 | ||
1145 | } | |
be723e22 | 1146 | else if (cr_reg >= 0 && |
98f08d3d KB |
1147 | /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */ |
1148 | (((op & 0xffff0000) == (cr_reg | 0xf8010000)) || | |
1149 | /* stw Rx, NUM(r1) */ | |
1150 | ((op & 0xffff0000) == (cr_reg | 0x90010000)) || | |
1151 | /* stwu Rx, NUM(r1) */ | |
1152 | ((op & 0xffff0000) == (cr_reg | 0x94010000)))) | |
1153 | { /* where Rx == cr */ | |
1154 | fdata->cr_offset = offset; | |
be723e22 MS |
1155 | /* Invalidate cr_reg, but don't set it to -1. |
1156 | That would mean that it had never been set. */ | |
1157 | cr_reg = -2; | |
98f08d3d KB |
1158 | if ((op & 0xfc000003) == 0xf8000000 || |
1159 | (op & 0xfc000000) == 0x90000000) | |
1160 | { | |
1161 | /* Does not update r1, so add displacement to cr_offset. */ | |
1162 | fdata->cr_offset += SIGNED_SHORT (op); | |
1163 | } | |
c5aa993b JM |
1164 | continue; |
1165 | ||
1166 | } | |
721d14ba DJ |
1167 | else if ((op & 0xfe80ffff) == 0x42800005 && lr_reg != -1) |
1168 | { | |
1169 | /* bcl 20,xx,.+4 is used to get the current PC, with or without | |
1170 | prediction bits. If the LR has already been saved, we can | |
1171 | skip it. */ | |
1172 | continue; | |
1173 | } | |
c5aa993b JM |
1174 | else if (op == 0x48000005) |
1175 | { /* bl .+4 used in | |
1176 | -mrelocatable */ | |
1177 | continue; | |
1178 | ||
1179 | } | |
1180 | else if (op == 0x48000004) | |
1181 | { /* b .+4 (xlc) */ | |
1182 | break; | |
1183 | ||
c5aa993b | 1184 | } |
6be8bc0c EZ |
1185 | else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used |
1186 | in V.4 -mminimal-toc */ | |
c5aa993b JM |
1187 | (op & 0xffff0000) == 0x3bde0000) |
1188 | { /* addi 30,30,foo@l */ | |
1189 | continue; | |
c906108c | 1190 | |
c5aa993b JM |
1191 | } |
1192 | else if ((op & 0xfc000001) == 0x48000001) | |
1193 | { /* bl foo, | |
1194 | to save fprs??? */ | |
c906108c | 1195 | |
c5aa993b | 1196 | fdata->frameless = 0; |
3c77c82a DJ |
1197 | |
1198 | /* If the return address has already been saved, we can skip | |
1199 | calls to blrl (for PIC). */ | |
1200 | if (lr_reg != -1 && bl_to_blrl_insn_p (pc, op)) | |
1201 | continue; | |
1202 | ||
6be8bc0c | 1203 | /* Don't skip over the subroutine call if it is not within |
ebd98106 FF |
1204 | the first three instructions of the prologue and either |
1205 | we have no line table information or the line info tells | |
1206 | us that the subroutine call is not part of the line | |
1207 | associated with the prologue. */ | |
c5aa993b | 1208 | if ((pc - orig_pc) > 8) |
ebd98106 FF |
1209 | { |
1210 | struct symtab_and_line prologue_sal = find_pc_line (orig_pc, 0); | |
1211 | struct symtab_and_line this_sal = find_pc_line (pc, 0); | |
1212 | ||
1213 | if ((prologue_sal.line == 0) || (prologue_sal.line != this_sal.line)) | |
1214 | break; | |
1215 | } | |
c5aa993b JM |
1216 | |
1217 | op = read_memory_integer (pc + 4, 4); | |
1218 | ||
6be8bc0c EZ |
1219 | /* At this point, make sure this is not a trampoline |
1220 | function (a function that simply calls another functions, | |
1221 | and nothing else). If the next is not a nop, this branch | |
1222 | was part of the function prologue. */ | |
c5aa993b JM |
1223 | |
1224 | if (op == 0x4def7b82 || op == 0) /* crorc 15, 15, 15 */ | |
1225 | break; /* don't skip over | |
1226 | this branch */ | |
1227 | continue; | |
1228 | ||
c5aa993b | 1229 | } |
98f08d3d KB |
1230 | /* update stack pointer */ |
1231 | else if ((op & 0xfc1f0000) == 0x94010000) | |
1232 | { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */ | |
c5aa993b JM |
1233 | fdata->frameless = 0; |
1234 | fdata->offset = SIGNED_SHORT (op); | |
1235 | offset = fdata->offset; | |
1236 | continue; | |
c5aa993b | 1237 | } |
98f08d3d KB |
1238 | else if ((op & 0xfc1f016a) == 0x7c01016e) |
1239 | { /* stwux rX,r1,rY */ | |
1240 | /* no way to figure out what r1 is going to be */ | |
1241 | fdata->frameless = 0; | |
1242 | offset = fdata->offset; | |
1243 | continue; | |
1244 | } | |
1245 | else if ((op & 0xfc1f0003) == 0xf8010001) | |
1246 | { /* stdu rX,NUM(r1) */ | |
1247 | fdata->frameless = 0; | |
1248 | fdata->offset = SIGNED_SHORT (op & ~3UL); | |
1249 | offset = fdata->offset; | |
1250 | continue; | |
1251 | } | |
1252 | else if ((op & 0xfc1f016a) == 0x7c01016a) | |
1253 | { /* stdux rX,r1,rY */ | |
1254 | /* no way to figure out what r1 is going to be */ | |
c5aa993b JM |
1255 | fdata->frameless = 0; |
1256 | offset = fdata->offset; | |
1257 | continue; | |
c5aa993b | 1258 | } |
7313566f FF |
1259 | else if ((op & 0xffff0000) == 0x38210000) |
1260 | { /* addi r1,r1,SIMM */ | |
1261 | fdata->frameless = 0; | |
1262 | fdata->offset += SIGNED_SHORT (op); | |
1263 | offset = fdata->offset; | |
1264 | continue; | |
1265 | } | |
4e463ff5 DJ |
1266 | /* Load up minimal toc pointer. Do not treat an epilogue restore |
1267 | of r31 as a minimal TOC load. */ | |
98f08d3d KB |
1268 | else if (((op >> 22) == 0x20f || /* l r31,... or l r30,... */ |
1269 | (op >> 22) == 0x3af) /* ld r31,... or ld r30,... */ | |
4e463ff5 | 1270 | && !framep |
c5aa993b | 1271 | && !minimal_toc_loaded) |
98f08d3d | 1272 | { |
c5aa993b JM |
1273 | minimal_toc_loaded = 1; |
1274 | continue; | |
1275 | ||
f6077098 KB |
1276 | /* move parameters from argument registers to local variable |
1277 | registers */ | |
1278 | } | |
1279 | else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */ | |
1280 | (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */ | |
1281 | (((op >> 21) & 31) <= 10) && | |
96ff0de4 | 1282 | ((long) ((op >> 16) & 31) >= fdata->saved_gpr)) /* Rx: local var reg */ |
f6077098 KB |
1283 | { |
1284 | continue; | |
1285 | ||
c5aa993b JM |
1286 | /* store parameters in stack */ |
1287 | } | |
e802b915 | 1288 | /* Move parameters from argument registers to temporary register. */ |
773df3e5 | 1289 | else if (store_param_on_stack_p (op, framep, &r0_contains_arg)) |
e802b915 | 1290 | { |
c5aa993b JM |
1291 | continue; |
1292 | ||
1293 | /* Set up frame pointer */ | |
1294 | } | |
1295 | else if (op == 0x603f0000 /* oril r31, r1, 0x0 */ | |
1296 | || op == 0x7c3f0b78) | |
1297 | { /* mr r31, r1 */ | |
1298 | fdata->frameless = 0; | |
1299 | framep = 1; | |
6f99cb26 | 1300 | fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31); |
c5aa993b JM |
1301 | continue; |
1302 | ||
1303 | /* Another way to set up the frame pointer. */ | |
1304 | } | |
1305 | else if ((op & 0xfc1fffff) == 0x38010000) | |
1306 | { /* addi rX, r1, 0x0 */ | |
1307 | fdata->frameless = 0; | |
1308 | framep = 1; | |
6f99cb26 AC |
1309 | fdata->alloca_reg = (tdep->ppc_gp0_regnum |
1310 | + ((op & ~0x38010000) >> 21)); | |
c5aa993b | 1311 | continue; |
c5aa993b | 1312 | } |
6be8bc0c EZ |
1313 | /* AltiVec related instructions. */ |
1314 | /* Store the vrsave register (spr 256) in another register for | |
1315 | later manipulation, or load a register into the vrsave | |
1316 | register. 2 instructions are used: mfvrsave and | |
1317 | mtvrsave. They are shorthand notation for mfspr Rn, SPR256 | |
1318 | and mtspr SPR256, Rn. */ | |
1319 | /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110 | |
1320 | mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */ | |
1321 | else if ((op & 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */ | |
1322 | { | |
1323 | vrsave_reg = GET_SRC_REG (op); | |
1324 | continue; | |
1325 | } | |
1326 | else if ((op & 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */ | |
1327 | { | |
1328 | continue; | |
1329 | } | |
1330 | /* Store the register where vrsave was saved to onto the stack: | |
1331 | rS is the register where vrsave was stored in a previous | |
1332 | instruction. */ | |
1333 | /* 100100 sssss 00001 dddddddd dddddddd */ | |
1334 | else if ((op & 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */ | |
1335 | { | |
1336 | if (vrsave_reg == GET_SRC_REG (op)) | |
1337 | { | |
1338 | fdata->vrsave_offset = SIGNED_SHORT (op) + offset; | |
1339 | vrsave_reg = -1; | |
1340 | } | |
1341 | continue; | |
1342 | } | |
1343 | /* Compute the new value of vrsave, by modifying the register | |
1344 | where vrsave was saved to. */ | |
1345 | else if (((op & 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */ | |
1346 | || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */ | |
1347 | { | |
1348 | continue; | |
1349 | } | |
1350 | /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first | |
1351 | in a pair of insns to save the vector registers on the | |
1352 | stack. */ | |
1353 | /* 001110 00000 00000 iiii iiii iiii iiii */ | |
96ff0de4 EZ |
1354 | /* 001110 01110 00000 iiii iiii iiii iiii */ |
1355 | else if ((op & 0xffff0000) == 0x38000000 /* li r0, SIMM */ | |
1356 | || (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */ | |
6be8bc0c | 1357 | { |
773df3e5 JB |
1358 | if ((op & 0xffff0000) == 0x38000000) |
1359 | r0_contains_arg = 0; | |
6be8bc0c EZ |
1360 | li_found_pc = pc; |
1361 | vr_saved_offset = SIGNED_SHORT (op); | |
773df3e5 JB |
1362 | |
1363 | /* This insn by itself is not part of the prologue, unless | |
1364 | if part of the pair of insns mentioned above. So do not | |
1365 | record this insn as part of the prologue yet. */ | |
1366 | prev_insn_was_prologue_insn = 0; | |
6be8bc0c EZ |
1367 | } |
1368 | /* Store vector register S at (r31+r0) aligned to 16 bytes. */ | |
1369 | /* 011111 sssss 11111 00000 00111001110 */ | |
1370 | else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */ | |
1371 | { | |
1372 | if (pc == (li_found_pc + 4)) | |
1373 | { | |
1374 | vr_reg = GET_SRC_REG (op); | |
1375 | /* If this is the first vector reg to be saved, or if | |
1376 | it has a lower number than others previously seen, | |
1377 | reupdate the frame info. */ | |
1378 | if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg) | |
1379 | { | |
1380 | fdata->saved_vr = vr_reg; | |
1381 | fdata->vr_offset = vr_saved_offset + offset; | |
1382 | } | |
1383 | vr_saved_offset = -1; | |
1384 | vr_reg = -1; | |
1385 | li_found_pc = 0; | |
1386 | } | |
1387 | } | |
1388 | /* End AltiVec related instructions. */ | |
96ff0de4 EZ |
1389 | |
1390 | /* Start BookE related instructions. */ | |
1391 | /* Store gen register S at (r31+uimm). | |
1392 | Any register less than r13 is volatile, so we don't care. */ | |
1393 | /* 000100 sssss 11111 iiiii 01100100001 */ | |
1394 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
1395 | && (op & 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */ | |
1396 | { | |
1397 | if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */ | |
1398 | { | |
1399 | unsigned int imm; | |
1400 | ev_reg = GET_SRC_REG (op); | |
1401 | imm = (op >> 11) & 0x1f; | |
1402 | ev_offset = imm * 8; | |
1403 | /* If this is the first vector reg to be saved, or if | |
1404 | it has a lower number than others previously seen, | |
1405 | reupdate the frame info. */ | |
1406 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) | |
1407 | { | |
1408 | fdata->saved_ev = ev_reg; | |
1409 | fdata->ev_offset = ev_offset + offset; | |
1410 | } | |
1411 | } | |
1412 | continue; | |
1413 | } | |
1414 | /* Store gen register rS at (r1+rB). */ | |
1415 | /* 000100 sssss 00001 bbbbb 01100100000 */ | |
1416 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
1417 | && (op & 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */ | |
1418 | { | |
1419 | if (pc == (li_found_pc + 4)) | |
1420 | { | |
1421 | ev_reg = GET_SRC_REG (op); | |
1422 | /* If this is the first vector reg to be saved, or if | |
1423 | it has a lower number than others previously seen, | |
1424 | reupdate the frame info. */ | |
1425 | /* We know the contents of rB from the previous instruction. */ | |
1426 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) | |
1427 | { | |
1428 | fdata->saved_ev = ev_reg; | |
1429 | fdata->ev_offset = vr_saved_offset + offset; | |
1430 | } | |
1431 | vr_saved_offset = -1; | |
1432 | ev_reg = -1; | |
1433 | li_found_pc = 0; | |
1434 | } | |
1435 | continue; | |
1436 | } | |
1437 | /* Store gen register r31 at (rA+uimm). */ | |
1438 | /* 000100 11111 aaaaa iiiii 01100100001 */ | |
1439 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
1440 | && (op & 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */ | |
1441 | { | |
1442 | /* Wwe know that the source register is 31 already, but | |
1443 | it can't hurt to compute it. */ | |
1444 | ev_reg = GET_SRC_REG (op); | |
1445 | ev_offset = ((op >> 11) & 0x1f) * 8; | |
1446 | /* If this is the first vector reg to be saved, or if | |
1447 | it has a lower number than others previously seen, | |
1448 | reupdate the frame info. */ | |
1449 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) | |
1450 | { | |
1451 | fdata->saved_ev = ev_reg; | |
1452 | fdata->ev_offset = ev_offset + offset; | |
1453 | } | |
1454 | ||
1455 | continue; | |
1456 | } | |
1457 | /* Store gen register S at (r31+r0). | |
1458 | Store param on stack when offset from SP bigger than 4 bytes. */ | |
1459 | /* 000100 sssss 11111 00000 01100100000 */ | |
1460 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
1461 | && (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */ | |
1462 | { | |
1463 | if (pc == (li_found_pc + 4)) | |
1464 | { | |
1465 | if ((op & 0x03e00000) >= 0x01a00000) | |
1466 | { | |
1467 | ev_reg = GET_SRC_REG (op); | |
1468 | /* If this is the first vector reg to be saved, or if | |
1469 | it has a lower number than others previously seen, | |
1470 | reupdate the frame info. */ | |
1471 | /* We know the contents of r0 from the previous | |
1472 | instruction. */ | |
1473 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) | |
1474 | { | |
1475 | fdata->saved_ev = ev_reg; | |
1476 | fdata->ev_offset = vr_saved_offset + offset; | |
1477 | } | |
1478 | ev_reg = -1; | |
1479 | } | |
1480 | vr_saved_offset = -1; | |
1481 | li_found_pc = 0; | |
1482 | continue; | |
1483 | } | |
1484 | } | |
1485 | /* End BookE related instructions. */ | |
1486 | ||
c5aa993b JM |
1487 | else |
1488 | { | |
55d05f3b KB |
1489 | /* Not a recognized prologue instruction. |
1490 | Handle optimizer code motions into the prologue by continuing | |
1491 | the search if we have no valid frame yet or if the return | |
1492 | address is not yet saved in the frame. */ | |
4e463ff5 | 1493 | if (fdata->frameless == 0 && fdata->nosavedpc == 0) |
55d05f3b KB |
1494 | break; |
1495 | ||
1496 | if (op == 0x4e800020 /* blr */ | |
1497 | || op == 0x4e800420) /* bctr */ | |
1498 | /* Do not scan past epilogue in frameless functions or | |
1499 | trampolines. */ | |
1500 | break; | |
1501 | if ((op & 0xf4000000) == 0x40000000) /* bxx */ | |
64366f1c | 1502 | /* Never skip branches. */ |
55d05f3b KB |
1503 | break; |
1504 | ||
1505 | if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns) | |
1506 | /* Do not scan too many insns, scanning insns is expensive with | |
1507 | remote targets. */ | |
1508 | break; | |
1509 | ||
1510 | /* Continue scanning. */ | |
1511 | prev_insn_was_prologue_insn = 0; | |
1512 | continue; | |
c5aa993b | 1513 | } |
c906108c SS |
1514 | } |
1515 | ||
1516 | #if 0 | |
1517 | /* I have problems with skipping over __main() that I need to address | |
1518 | * sometime. Previously, I used to use misc_function_vector which | |
1519 | * didn't work as well as I wanted to be. -MGO */ | |
1520 | ||
1521 | /* If the first thing after skipping a prolog is a branch to a function, | |
1522 | this might be a call to an initializer in main(), introduced by gcc2. | |
64366f1c | 1523 | We'd like to skip over it as well. Fortunately, xlc does some extra |
c906108c | 1524 | work before calling a function right after a prologue, thus we can |
64366f1c | 1525 | single out such gcc2 behaviour. */ |
c906108c | 1526 | |
c906108c | 1527 | |
c5aa993b JM |
1528 | if ((op & 0xfc000001) == 0x48000001) |
1529 | { /* bl foo, an initializer function? */ | |
1530 | op = read_memory_integer (pc + 4, 4); | |
1531 | ||
1532 | if (op == 0x4def7b82) | |
1533 | { /* cror 0xf, 0xf, 0xf (nop) */ | |
c906108c | 1534 | |
64366f1c EZ |
1535 | /* Check and see if we are in main. If so, skip over this |
1536 | initializer function as well. */ | |
c906108c | 1537 | |
c5aa993b | 1538 | tmp = find_pc_misc_function (pc); |
6314a349 AC |
1539 | if (tmp >= 0 |
1540 | && strcmp (misc_function_vector[tmp].name, main_name ()) == 0) | |
c5aa993b JM |
1541 | return pc + 8; |
1542 | } | |
c906108c | 1543 | } |
c906108c | 1544 | #endif /* 0 */ |
c5aa993b JM |
1545 | |
1546 | fdata->offset = -fdata->offset; | |
ddb20c56 | 1547 | return last_prologue_pc; |
c906108c SS |
1548 | } |
1549 | ||
1550 | ||
1551 | /************************************************************************* | |
f6077098 | 1552 | Support for creating pushing a dummy frame into the stack, and popping |
c906108c SS |
1553 | frames, etc. |
1554 | *************************************************************************/ | |
1555 | ||
c906108c | 1556 | |
11269d7e AC |
1557 | /* All the ABI's require 16 byte alignment. */ |
1558 | static CORE_ADDR | |
1559 | rs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
1560 | { | |
1561 | return (addr & -16); | |
1562 | } | |
1563 | ||
7a78ae4e | 1564 | /* Pass the arguments in either registers, or in the stack. In RS/6000, |
c906108c SS |
1565 | the first eight words of the argument list (that might be less than |
1566 | eight parameters if some parameters occupy more than one word) are | |
7a78ae4e | 1567 | passed in r3..r10 registers. float and double parameters are |
64366f1c EZ |
1568 | passed in fpr's, in addition to that. Rest of the parameters if any |
1569 | are passed in user stack. There might be cases in which half of the | |
c906108c SS |
1570 | parameter is copied into registers, the other half is pushed into |
1571 | stack. | |
1572 | ||
7a78ae4e ND |
1573 | Stack must be aligned on 64-bit boundaries when synthesizing |
1574 | function calls. | |
1575 | ||
c906108c SS |
1576 | If the function is returning a structure, then the return address is passed |
1577 | in r3, then the first 7 words of the parameters can be passed in registers, | |
64366f1c | 1578 | starting from r4. */ |
c906108c | 1579 | |
7a78ae4e | 1580 | static CORE_ADDR |
7d9b040b | 1581 | rs6000_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
77b2b6d4 AC |
1582 | struct regcache *regcache, CORE_ADDR bp_addr, |
1583 | int nargs, struct value **args, CORE_ADDR sp, | |
1584 | int struct_return, CORE_ADDR struct_addr) | |
c906108c | 1585 | { |
7a41266b | 1586 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c SS |
1587 | int ii; |
1588 | int len = 0; | |
c5aa993b JM |
1589 | int argno; /* current argument number */ |
1590 | int argbytes; /* current argument byte */ | |
50fd1280 | 1591 | gdb_byte tmp_buffer[50]; |
c5aa993b | 1592 | int f_argno = 0; /* current floating point argno */ |
21283beb | 1593 | int wordsize = gdbarch_tdep (current_gdbarch)->wordsize; |
7d9b040b | 1594 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
c906108c | 1595 | |
ea7c478f | 1596 | struct value *arg = 0; |
c906108c SS |
1597 | struct type *type; |
1598 | ||
fb4443d8 | 1599 | ULONGEST saved_sp; |
c906108c | 1600 | |
383f0f5b JB |
1601 | /* The calling convention this function implements assumes the |
1602 | processor has floating-point registers. We shouldn't be using it | |
1603 | on PPC variants that lack them. */ | |
1604 | gdb_assert (ppc_floating_point_unit_p (current_gdbarch)); | |
1605 | ||
64366f1c | 1606 | /* The first eight words of ther arguments are passed in registers. |
7a41266b AC |
1607 | Copy them appropriately. */ |
1608 | ii = 0; | |
1609 | ||
1610 | /* If the function is returning a `struct', then the first word | |
1611 | (which will be passed in r3) is used for struct return address. | |
1612 | In that case we should advance one word and start from r4 | |
1613 | register to copy parameters. */ | |
1614 | if (struct_return) | |
1615 | { | |
1616 | regcache_raw_write_unsigned (regcache, tdep->ppc_gp0_regnum + 3, | |
1617 | struct_addr); | |
1618 | ii++; | |
1619 | } | |
c906108c SS |
1620 | |
1621 | /* | |
c5aa993b JM |
1622 | effectively indirect call... gcc does... |
1623 | ||
1624 | return_val example( float, int); | |
1625 | ||
1626 | eabi: | |
1627 | float in fp0, int in r3 | |
1628 | offset of stack on overflow 8/16 | |
1629 | for varargs, must go by type. | |
1630 | power open: | |
1631 | float in r3&r4, int in r5 | |
1632 | offset of stack on overflow different | |
1633 | both: | |
1634 | return in r3 or f0. If no float, must study how gcc emulates floats; | |
1635 | pay attention to arg promotion. | |
1636 | User may have to cast\args to handle promotion correctly | |
1637 | since gdb won't know if prototype supplied or not. | |
1638 | */ | |
c906108c | 1639 | |
c5aa993b JM |
1640 | for (argno = 0, argbytes = 0; argno < nargs && ii < 8; ++ii) |
1641 | { | |
3acba339 | 1642 | int reg_size = register_size (current_gdbarch, ii + 3); |
c5aa993b JM |
1643 | |
1644 | arg = args[argno]; | |
df407dfe | 1645 | type = check_typedef (value_type (arg)); |
c5aa993b JM |
1646 | len = TYPE_LENGTH (type); |
1647 | ||
1648 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
1649 | { | |
1650 | ||
64366f1c | 1651 | /* Floating point arguments are passed in fpr's, as well as gpr's. |
c5aa993b | 1652 | There are 13 fpr's reserved for passing parameters. At this point |
64366f1c | 1653 | there is no way we would run out of them. */ |
c5aa993b | 1654 | |
9f335945 KB |
1655 | gdb_assert (len <= 8); |
1656 | ||
1657 | regcache_cooked_write (regcache, | |
1658 | tdep->ppc_fp0_regnum + 1 + f_argno, | |
0fd88904 | 1659 | value_contents (arg)); |
c5aa993b JM |
1660 | ++f_argno; |
1661 | } | |
1662 | ||
f6077098 | 1663 | if (len > reg_size) |
c5aa993b JM |
1664 | { |
1665 | ||
64366f1c | 1666 | /* Argument takes more than one register. */ |
c5aa993b JM |
1667 | while (argbytes < len) |
1668 | { | |
50fd1280 | 1669 | gdb_byte word[MAX_REGISTER_SIZE]; |
9f335945 KB |
1670 | memset (word, 0, reg_size); |
1671 | memcpy (word, | |
0fd88904 | 1672 | ((char *) value_contents (arg)) + argbytes, |
f6077098 KB |
1673 | (len - argbytes) > reg_size |
1674 | ? reg_size : len - argbytes); | |
9f335945 KB |
1675 | regcache_cooked_write (regcache, |
1676 | tdep->ppc_gp0_regnum + 3 + ii, | |
1677 | word); | |
f6077098 | 1678 | ++ii, argbytes += reg_size; |
c5aa993b JM |
1679 | |
1680 | if (ii >= 8) | |
1681 | goto ran_out_of_registers_for_arguments; | |
1682 | } | |
1683 | argbytes = 0; | |
1684 | --ii; | |
1685 | } | |
1686 | else | |
64366f1c EZ |
1687 | { |
1688 | /* Argument can fit in one register. No problem. */ | |
4c6b5505 UW |
1689 | int adj = gdbarch_byte_order (current_gdbarch) |
1690 | == BFD_ENDIAN_BIG ? reg_size - len : 0; | |
50fd1280 | 1691 | gdb_byte word[MAX_REGISTER_SIZE]; |
9f335945 KB |
1692 | |
1693 | memset (word, 0, reg_size); | |
0fd88904 | 1694 | memcpy (word, value_contents (arg), len); |
9f335945 | 1695 | regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 3 +ii, word); |
c5aa993b JM |
1696 | } |
1697 | ++argno; | |
c906108c | 1698 | } |
c906108c SS |
1699 | |
1700 | ran_out_of_registers_for_arguments: | |
1701 | ||
3e8c568d UW |
1702 | regcache_cooked_read_unsigned (regcache, |
1703 | gdbarch_sp_regnum (current_gdbarch), | |
1704 | &saved_sp); | |
cc9836a8 | 1705 | |
64366f1c | 1706 | /* Location for 8 parameters are always reserved. */ |
7a78ae4e | 1707 | sp -= wordsize * 8; |
f6077098 | 1708 | |
64366f1c | 1709 | /* Another six words for back chain, TOC register, link register, etc. */ |
7a78ae4e | 1710 | sp -= wordsize * 6; |
f6077098 | 1711 | |
64366f1c | 1712 | /* Stack pointer must be quadword aligned. */ |
7a78ae4e | 1713 | sp &= -16; |
c906108c | 1714 | |
64366f1c EZ |
1715 | /* If there are more arguments, allocate space for them in |
1716 | the stack, then push them starting from the ninth one. */ | |
c906108c | 1717 | |
c5aa993b JM |
1718 | if ((argno < nargs) || argbytes) |
1719 | { | |
1720 | int space = 0, jj; | |
c906108c | 1721 | |
c5aa993b JM |
1722 | if (argbytes) |
1723 | { | |
1724 | space += ((len - argbytes + 3) & -4); | |
1725 | jj = argno + 1; | |
1726 | } | |
1727 | else | |
1728 | jj = argno; | |
c906108c | 1729 | |
c5aa993b JM |
1730 | for (; jj < nargs; ++jj) |
1731 | { | |
ea7c478f | 1732 | struct value *val = args[jj]; |
df407dfe | 1733 | space += ((TYPE_LENGTH (value_type (val))) + 3) & -4; |
c5aa993b | 1734 | } |
c906108c | 1735 | |
64366f1c | 1736 | /* Add location required for the rest of the parameters. */ |
f6077098 | 1737 | space = (space + 15) & -16; |
c5aa993b | 1738 | sp -= space; |
c906108c | 1739 | |
7aea86e6 AC |
1740 | /* This is another instance we need to be concerned about |
1741 | securing our stack space. If we write anything underneath %sp | |
1742 | (r1), we might conflict with the kernel who thinks he is free | |
1743 | to use this area. So, update %sp first before doing anything | |
1744 | else. */ | |
1745 | ||
3e8c568d UW |
1746 | regcache_raw_write_signed (regcache, |
1747 | gdbarch_sp_regnum (current_gdbarch), sp); | |
7aea86e6 | 1748 | |
64366f1c EZ |
1749 | /* If the last argument copied into the registers didn't fit there |
1750 | completely, push the rest of it into stack. */ | |
c906108c | 1751 | |
c5aa993b JM |
1752 | if (argbytes) |
1753 | { | |
1754 | write_memory (sp + 24 + (ii * 4), | |
50fd1280 | 1755 | value_contents (arg) + argbytes, |
c5aa993b JM |
1756 | len - argbytes); |
1757 | ++argno; | |
1758 | ii += ((len - argbytes + 3) & -4) / 4; | |
1759 | } | |
c906108c | 1760 | |
64366f1c | 1761 | /* Push the rest of the arguments into stack. */ |
c5aa993b JM |
1762 | for (; argno < nargs; ++argno) |
1763 | { | |
c906108c | 1764 | |
c5aa993b | 1765 | arg = args[argno]; |
df407dfe | 1766 | type = check_typedef (value_type (arg)); |
c5aa993b | 1767 | len = TYPE_LENGTH (type); |
c906108c SS |
1768 | |
1769 | ||
64366f1c EZ |
1770 | /* Float types should be passed in fpr's, as well as in the |
1771 | stack. */ | |
c5aa993b JM |
1772 | if (TYPE_CODE (type) == TYPE_CODE_FLT && f_argno < 13) |
1773 | { | |
c906108c | 1774 | |
9f335945 | 1775 | gdb_assert (len <= 8); |
c906108c | 1776 | |
9f335945 KB |
1777 | regcache_cooked_write (regcache, |
1778 | tdep->ppc_fp0_regnum + 1 + f_argno, | |
0fd88904 | 1779 | value_contents (arg)); |
c5aa993b JM |
1780 | ++f_argno; |
1781 | } | |
c906108c | 1782 | |
50fd1280 | 1783 | write_memory (sp + 24 + (ii * 4), value_contents (arg), len); |
c5aa993b JM |
1784 | ii += ((len + 3) & -4) / 4; |
1785 | } | |
c906108c | 1786 | } |
c906108c | 1787 | |
69517000 | 1788 | /* Set the stack pointer. According to the ABI, the SP is meant to |
7aea86e6 AC |
1789 | be set _before_ the corresponding stack space is used. On AIX, |
1790 | this even applies when the target has been completely stopped! | |
1791 | Not doing this can lead to conflicts with the kernel which thinks | |
1792 | that it still has control over this not-yet-allocated stack | |
1793 | region. */ | |
3e8c568d | 1794 | regcache_raw_write_signed (regcache, gdbarch_sp_regnum (current_gdbarch), sp); |
33a7c2fc | 1795 | |
7aea86e6 | 1796 | /* Set back chain properly. */ |
8ba0209f AM |
1797 | store_unsigned_integer (tmp_buffer, wordsize, saved_sp); |
1798 | write_memory (sp, tmp_buffer, wordsize); | |
7aea86e6 | 1799 | |
e56a0ecc AC |
1800 | /* Point the inferior function call's return address at the dummy's |
1801 | breakpoint. */ | |
1802 | regcache_raw_write_signed (regcache, tdep->ppc_lr_regnum, bp_addr); | |
1803 | ||
794a477a AC |
1804 | /* Set the TOC register, get the value from the objfile reader |
1805 | which, in turn, gets it from the VMAP table. */ | |
1806 | if (rs6000_find_toc_address_hook != NULL) | |
1807 | { | |
1808 | CORE_ADDR tocvalue = (*rs6000_find_toc_address_hook) (func_addr); | |
1809 | regcache_raw_write_signed (regcache, tdep->ppc_toc_regnum, tocvalue); | |
1810 | } | |
1811 | ||
56be3814 | 1812 | target_store_registers (regcache, -1); |
c906108c SS |
1813 | return sp; |
1814 | } | |
c906108c | 1815 | |
d217aaed MK |
1816 | static enum return_value_convention |
1817 | rs6000_return_value (struct gdbarch *gdbarch, struct type *valtype, | |
1818 | struct regcache *regcache, gdb_byte *readbuf, | |
1819 | const gdb_byte *writebuf) | |
c906108c | 1820 | { |
ace1378a | 1821 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
d217aaed | 1822 | gdb_byte buf[8]; |
c906108c | 1823 | |
383f0f5b JB |
1824 | /* The calling convention this function implements assumes the |
1825 | processor has floating-point registers. We shouldn't be using it | |
d217aaed | 1826 | on PowerPC variants that lack them. */ |
383f0f5b JB |
1827 | gdb_assert (ppc_floating_point_unit_p (current_gdbarch)); |
1828 | ||
d217aaed MK |
1829 | /* AltiVec extension: Functions that declare a vector data type as a |
1830 | return value place that return value in VR2. */ | |
1831 | if (TYPE_CODE (valtype) == TYPE_CODE_ARRAY && TYPE_VECTOR (valtype) | |
1832 | && TYPE_LENGTH (valtype) == 16) | |
c5aa993b | 1833 | { |
d217aaed MK |
1834 | if (readbuf) |
1835 | regcache_cooked_read (regcache, tdep->ppc_vr0_regnum + 2, readbuf); | |
1836 | if (writebuf) | |
1837 | regcache_cooked_write (regcache, tdep->ppc_vr0_regnum + 2, writebuf); | |
c906108c | 1838 | |
d217aaed | 1839 | return RETURN_VALUE_REGISTER_CONVENTION; |
c5aa993b | 1840 | } |
d217aaed MK |
1841 | |
1842 | /* If the called subprogram returns an aggregate, there exists an | |
1843 | implicit first argument, whose value is the address of a caller- | |
1844 | allocated buffer into which the callee is assumed to store its | |
1845 | return value. All explicit parameters are appropriately | |
1846 | relabeled. */ | |
1847 | if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT | |
1848 | || TYPE_CODE (valtype) == TYPE_CODE_UNION | |
1849 | || TYPE_CODE (valtype) == TYPE_CODE_ARRAY) | |
1850 | return RETURN_VALUE_STRUCT_CONVENTION; | |
1851 | ||
1852 | /* Scalar floating-point values are returned in FPR1 for float or | |
1853 | double, and in FPR1:FPR2 for quadword precision. Fortran | |
1854 | complex*8 and complex*16 are returned in FPR1:FPR2, and | |
1855 | complex*32 is returned in FPR1:FPR4. */ | |
1856 | if (TYPE_CODE (valtype) == TYPE_CODE_FLT | |
1857 | && (TYPE_LENGTH (valtype) == 4 || TYPE_LENGTH (valtype) == 8)) | |
1858 | { | |
1859 | struct type *regtype = register_type (gdbarch, tdep->ppc_fp0_regnum); | |
1860 | gdb_byte regval[8]; | |
1861 | ||
1862 | /* FIXME: kettenis/2007-01-01: Add support for quadword | |
1863 | precision and complex. */ | |
1864 | ||
1865 | if (readbuf) | |
1866 | { | |
1867 | regcache_cooked_read (regcache, tdep->ppc_fp0_regnum + 1, regval); | |
1868 | convert_typed_floating (regval, regtype, readbuf, valtype); | |
1869 | } | |
1870 | if (writebuf) | |
1871 | { | |
1872 | convert_typed_floating (writebuf, valtype, regval, regtype); | |
1873 | regcache_cooked_write (regcache, tdep->ppc_fp0_regnum + 1, regval); | |
1874 | } | |
1875 | ||
1876 | return RETURN_VALUE_REGISTER_CONVENTION; | |
1877 | } | |
1878 | ||
1879 | /* Values of the types int, long, short, pointer, and char (length | |
1880 | is less than or equal to four bytes), as well as bit values of | |
1881 | lengths less than or equal to 32 bits, must be returned right | |
1882 | justified in GPR3 with signed values sign extended and unsigned | |
1883 | values zero extended, as necessary. */ | |
1884 | if (TYPE_LENGTH (valtype) <= tdep->wordsize) | |
ace1378a | 1885 | { |
d217aaed MK |
1886 | if (readbuf) |
1887 | { | |
1888 | ULONGEST regval; | |
1889 | ||
1890 | /* For reading we don't have to worry about sign extension. */ | |
1891 | regcache_cooked_read_unsigned (regcache, tdep->ppc_gp0_regnum + 3, | |
1892 | ®val); | |
1893 | store_unsigned_integer (readbuf, TYPE_LENGTH (valtype), regval); | |
1894 | } | |
1895 | if (writebuf) | |
1896 | { | |
1897 | /* For writing, use unpack_long since that should handle any | |
1898 | required sign extension. */ | |
1899 | regcache_cooked_write_unsigned (regcache, tdep->ppc_gp0_regnum + 3, | |
1900 | unpack_long (valtype, writebuf)); | |
1901 | } | |
1902 | ||
1903 | return RETURN_VALUE_REGISTER_CONVENTION; | |
ace1378a | 1904 | } |
d217aaed MK |
1905 | |
1906 | /* Eight-byte non-floating-point scalar values must be returned in | |
1907 | GPR3:GPR4. */ | |
1908 | ||
1909 | if (TYPE_LENGTH (valtype) == 8) | |
c5aa993b | 1910 | { |
d217aaed MK |
1911 | gdb_assert (TYPE_CODE (valtype) != TYPE_CODE_FLT); |
1912 | gdb_assert (tdep->wordsize == 4); | |
1913 | ||
1914 | if (readbuf) | |
1915 | { | |
1916 | gdb_byte regval[8]; | |
1917 | ||
1918 | regcache_cooked_read (regcache, tdep->ppc_gp0_regnum + 3, regval); | |
1919 | regcache_cooked_read (regcache, tdep->ppc_gp0_regnum + 4, | |
1920 | regval + 4); | |
1921 | memcpy (readbuf, regval, 8); | |
1922 | } | |
1923 | if (writebuf) | |
1924 | { | |
1925 | regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 3, writebuf); | |
1926 | regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 4, | |
1927 | writebuf + 4); | |
1928 | } | |
1929 | ||
1930 | return RETURN_VALUE_REGISTER_CONVENTION; | |
c906108c | 1931 | } |
d217aaed MK |
1932 | |
1933 | return RETURN_VALUE_STRUCT_CONVENTION; | |
c906108c SS |
1934 | } |
1935 | ||
977adac5 ND |
1936 | /* Return whether handle_inferior_event() should proceed through code |
1937 | starting at PC in function NAME when stepping. | |
1938 | ||
1939 | The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to | |
1940 | handle memory references that are too distant to fit in instructions | |
1941 | generated by the compiler. For example, if 'foo' in the following | |
1942 | instruction: | |
1943 | ||
1944 | lwz r9,foo(r2) | |
1945 | ||
1946 | is greater than 32767, the linker might replace the lwz with a branch to | |
1947 | somewhere in @FIX1 that does the load in 2 instructions and then branches | |
1948 | back to where execution should continue. | |
1949 | ||
1950 | GDB should silently step over @FIX code, just like AIX dbx does. | |
2ec664f5 MS |
1951 | Unfortunately, the linker uses the "b" instruction for the |
1952 | branches, meaning that the link register doesn't get set. | |
1953 | Therefore, GDB's usual step_over_function () mechanism won't work. | |
977adac5 | 1954 | |
e76f05fa UW |
1955 | Instead, use the gdbarch_skip_trampoline_code and |
1956 | gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past | |
2ec664f5 | 1957 | @FIX code. */ |
977adac5 ND |
1958 | |
1959 | int | |
1960 | rs6000_in_solib_return_trampoline (CORE_ADDR pc, char *name) | |
1961 | { | |
1962 | return name && !strncmp (name, "@FIX", 4); | |
1963 | } | |
1964 | ||
1965 | /* Skip code that the user doesn't want to see when stepping: | |
1966 | ||
1967 | 1. Indirect function calls use a piece of trampoline code to do context | |
1968 | switching, i.e. to set the new TOC table. Skip such code if we are on | |
1969 | its first instruction (as when we have single-stepped to here). | |
1970 | ||
1971 | 2. Skip shared library trampoline code (which is different from | |
c906108c | 1972 | indirect function call trampolines). |
977adac5 ND |
1973 | |
1974 | 3. Skip bigtoc fixup code. | |
1975 | ||
c906108c | 1976 | Result is desired PC to step until, or NULL if we are not in |
977adac5 | 1977 | code that should be skipped. */ |
c906108c SS |
1978 | |
1979 | CORE_ADDR | |
52f729a7 | 1980 | rs6000_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 1981 | { |
52f0bd74 | 1982 | unsigned int ii, op; |
977adac5 | 1983 | int rel; |
c906108c | 1984 | CORE_ADDR solib_target_pc; |
977adac5 | 1985 | struct minimal_symbol *msymbol; |
c906108c | 1986 | |
c5aa993b JM |
1987 | static unsigned trampoline_code[] = |
1988 | { | |
1989 | 0x800b0000, /* l r0,0x0(r11) */ | |
1990 | 0x90410014, /* st r2,0x14(r1) */ | |
1991 | 0x7c0903a6, /* mtctr r0 */ | |
1992 | 0x804b0004, /* l r2,0x4(r11) */ | |
1993 | 0x816b0008, /* l r11,0x8(r11) */ | |
1994 | 0x4e800420, /* bctr */ | |
1995 | 0x4e800020, /* br */ | |
1996 | 0 | |
c906108c SS |
1997 | }; |
1998 | ||
977adac5 ND |
1999 | /* Check for bigtoc fixup code. */ |
2000 | msymbol = lookup_minimal_symbol_by_pc (pc); | |
2ec664f5 MS |
2001 | if (msymbol |
2002 | && rs6000_in_solib_return_trampoline (pc, | |
2003 | DEPRECATED_SYMBOL_NAME (msymbol))) | |
977adac5 ND |
2004 | { |
2005 | /* Double-check that the third instruction from PC is relative "b". */ | |
2006 | op = read_memory_integer (pc + 8, 4); | |
2007 | if ((op & 0xfc000003) == 0x48000000) | |
2008 | { | |
2009 | /* Extract bits 6-29 as a signed 24-bit relative word address and | |
2010 | add it to the containing PC. */ | |
2011 | rel = ((int)(op << 6) >> 6); | |
2012 | return pc + 8 + rel; | |
2013 | } | |
2014 | } | |
2015 | ||
c906108c | 2016 | /* If pc is in a shared library trampoline, return its target. */ |
52f729a7 | 2017 | solib_target_pc = find_solib_trampoline_target (frame, pc); |
c906108c SS |
2018 | if (solib_target_pc) |
2019 | return solib_target_pc; | |
2020 | ||
c5aa993b JM |
2021 | for (ii = 0; trampoline_code[ii]; ++ii) |
2022 | { | |
2023 | op = read_memory_integer (pc + (ii * 4), 4); | |
2024 | if (op != trampoline_code[ii]) | |
2025 | return 0; | |
2026 | } | |
52f729a7 | 2027 | ii = get_frame_register_unsigned (frame, 11); /* r11 holds destination addr */ |
21283beb | 2028 | pc = read_memory_addr (ii, gdbarch_tdep (current_gdbarch)->wordsize); /* (r11) value */ |
c906108c SS |
2029 | return pc; |
2030 | } | |
2031 | ||
794ac428 UW |
2032 | /* ISA-specific vector types. */ |
2033 | ||
2034 | static struct type * | |
2035 | rs6000_builtin_type_vec64 (struct gdbarch *gdbarch) | |
2036 | { | |
2037 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2038 | ||
2039 | if (!tdep->ppc_builtin_type_vec64) | |
2040 | { | |
2041 | /* The type we're building is this: */ | |
2042 | #if 0 | |
2043 | union __gdb_builtin_type_vec64 | |
2044 | { | |
2045 | int64_t uint64; | |
2046 | float v2_float[2]; | |
2047 | int32_t v2_int32[2]; | |
2048 | int16_t v4_int16[4]; | |
2049 | int8_t v8_int8[8]; | |
2050 | }; | |
2051 | #endif | |
2052 | ||
2053 | struct type *t; | |
2054 | ||
2055 | t = init_composite_type ("__ppc_builtin_type_vec64", TYPE_CODE_UNION); | |
2056 | append_composite_type_field (t, "uint64", builtin_type_int64); | |
2057 | append_composite_type_field (t, "v2_float", | |
2058 | init_vector_type (builtin_type_float, 2)); | |
2059 | append_composite_type_field (t, "v2_int32", | |
2060 | init_vector_type (builtin_type_int32, 2)); | |
2061 | append_composite_type_field (t, "v4_int16", | |
2062 | init_vector_type (builtin_type_int16, 4)); | |
2063 | append_composite_type_field (t, "v8_int8", | |
2064 | init_vector_type (builtin_type_int8, 8)); | |
2065 | ||
2066 | TYPE_FLAGS (t) |= TYPE_FLAG_VECTOR; | |
2067 | TYPE_NAME (t) = "ppc_builtin_type_vec64"; | |
2068 | tdep->ppc_builtin_type_vec64 = t; | |
2069 | } | |
2070 | ||
2071 | return tdep->ppc_builtin_type_vec64; | |
2072 | } | |
2073 | ||
2074 | static struct type * | |
2075 | rs6000_builtin_type_vec128 (struct gdbarch *gdbarch) | |
2076 | { | |
2077 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2078 | ||
2079 | if (!tdep->ppc_builtin_type_vec128) | |
2080 | { | |
2081 | /* The type we're building is this: */ | |
2082 | #if 0 | |
2083 | union __gdb_builtin_type_vec128 | |
2084 | { | |
2085 | int128_t uint128; | |
2086 | float v4_float[4]; | |
2087 | int32_t v4_int32[4]; | |
2088 | int16_t v8_int16[8]; | |
2089 | int8_t v16_int8[16]; | |
2090 | }; | |
2091 | #endif | |
2092 | ||
2093 | struct type *t; | |
2094 | ||
2095 | t = init_composite_type ("__ppc_builtin_type_vec128", TYPE_CODE_UNION); | |
2096 | append_composite_type_field (t, "uint128", builtin_type_int128); | |
2097 | append_composite_type_field (t, "v4_float", | |
2098 | init_vector_type (builtin_type_float, 4)); | |
2099 | append_composite_type_field (t, "v4_int32", | |
2100 | init_vector_type (builtin_type_int32, 4)); | |
2101 | append_composite_type_field (t, "v8_int16", | |
2102 | init_vector_type (builtin_type_int16, 8)); | |
2103 | append_composite_type_field (t, "v16_int8", | |
2104 | init_vector_type (builtin_type_int8, 16)); | |
2105 | ||
2106 | TYPE_FLAGS (t) |= TYPE_FLAG_VECTOR; | |
2107 | TYPE_NAME (t) = "ppc_builtin_type_vec128"; | |
2108 | tdep->ppc_builtin_type_vec128 = t; | |
2109 | } | |
2110 | ||
2111 | return tdep->ppc_builtin_type_vec128; | |
2112 | } | |
2113 | ||
7a78ae4e | 2114 | /* Return the size of register REG when words are WORDSIZE bytes long. If REG |
64366f1c | 2115 | isn't available with that word size, return 0. */ |
7a78ae4e ND |
2116 | |
2117 | static int | |
2118 | regsize (const struct reg *reg, int wordsize) | |
2119 | { | |
2120 | return wordsize == 8 ? reg->sz64 : reg->sz32; | |
2121 | } | |
2122 | ||
2123 | /* Return the name of register number N, or null if no such register exists | |
64366f1c | 2124 | in the current architecture. */ |
7a78ae4e | 2125 | |
fa88f677 | 2126 | static const char * |
7a78ae4e ND |
2127 | rs6000_register_name (int n) |
2128 | { | |
21283beb | 2129 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
7a78ae4e ND |
2130 | const struct reg *reg = tdep->regs + n; |
2131 | ||
2132 | if (!regsize (reg, tdep->wordsize)) | |
2133 | return NULL; | |
2134 | return reg->name; | |
2135 | } | |
2136 | ||
7a78ae4e ND |
2137 | /* Return the GDB type object for the "standard" data type |
2138 | of data in register N. */ | |
2139 | ||
2140 | static struct type * | |
691d145a | 2141 | rs6000_register_type (struct gdbarch *gdbarch, int n) |
7a78ae4e | 2142 | { |
691d145a | 2143 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7a78ae4e ND |
2144 | const struct reg *reg = tdep->regs + n; |
2145 | ||
1fcc0bb8 EZ |
2146 | if (reg->fpr) |
2147 | return builtin_type_double; | |
2148 | else | |
2149 | { | |
2150 | int size = regsize (reg, tdep->wordsize); | |
2151 | switch (size) | |
2152 | { | |
449a5da4 AC |
2153 | case 0: |
2154 | return builtin_type_int0; | |
2155 | case 4: | |
ed6edd9b | 2156 | return builtin_type_uint32; |
1fcc0bb8 | 2157 | case 8: |
c8001721 | 2158 | if (tdep->ppc_ev0_regnum <= n && n <= tdep->ppc_ev31_regnum) |
794ac428 | 2159 | return rs6000_builtin_type_vec64 (gdbarch); |
c8001721 | 2160 | else |
ed6edd9b | 2161 | return builtin_type_uint64; |
1fcc0bb8 EZ |
2162 | break; |
2163 | case 16: | |
794ac428 | 2164 | return rs6000_builtin_type_vec128 (gdbarch); |
1fcc0bb8 EZ |
2165 | break; |
2166 | default: | |
e2e0b3e5 | 2167 | internal_error (__FILE__, __LINE__, _("Register %d size %d unknown"), |
449a5da4 | 2168 | n, size); |
1fcc0bb8 EZ |
2169 | } |
2170 | } | |
7a78ae4e ND |
2171 | } |
2172 | ||
c44ca51c AC |
2173 | /* Is REGNUM a member of REGGROUP? */ |
2174 | static int | |
2175 | rs6000_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
2176 | struct reggroup *group) | |
2177 | { | |
2178 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2179 | int float_p; | |
2180 | int vector_p; | |
2181 | int general_p; | |
2182 | ||
c9f4d572 UW |
2183 | if (gdbarch_register_name (current_gdbarch, regnum) == NULL |
2184 | || *gdbarch_register_name (current_gdbarch, regnum) == '\0') | |
c44ca51c AC |
2185 | return 0; |
2186 | if (group == all_reggroup) | |
2187 | return 1; | |
2188 | ||
2189 | float_p = (regnum == tdep->ppc_fpscr_regnum | |
2190 | || (regnum >= tdep->ppc_fp0_regnum | |
2191 | && regnum < tdep->ppc_fp0_regnum + 32)); | |
2192 | if (group == float_reggroup) | |
2193 | return float_p; | |
2194 | ||
826d5376 PG |
2195 | vector_p = ((tdep->ppc_vr0_regnum >= 0 |
2196 | && regnum >= tdep->ppc_vr0_regnum | |
c44ca51c | 2197 | && regnum < tdep->ppc_vr0_regnum + 32) |
826d5376 PG |
2198 | || (tdep->ppc_ev0_regnum >= 0 |
2199 | && regnum >= tdep->ppc_ev0_regnum | |
c44ca51c | 2200 | && regnum < tdep->ppc_ev0_regnum + 32) |
3bf49e1b | 2201 | || regnum == tdep->ppc_vrsave_regnum - 1 /* vscr */ |
c44ca51c AC |
2202 | || regnum == tdep->ppc_vrsave_regnum |
2203 | || regnum == tdep->ppc_acc_regnum | |
2204 | || regnum == tdep->ppc_spefscr_regnum); | |
2205 | if (group == vector_reggroup) | |
2206 | return vector_p; | |
2207 | ||
2208 | /* Note that PS aka MSR isn't included - it's a system register (and | |
2209 | besides, due to GCC's CFI foobar you do not want to restore | |
2210 | it). */ | |
2211 | general_p = ((regnum >= tdep->ppc_gp0_regnum | |
2212 | && regnum < tdep->ppc_gp0_regnum + 32) | |
2213 | || regnum == tdep->ppc_toc_regnum | |
2214 | || regnum == tdep->ppc_cr_regnum | |
2215 | || regnum == tdep->ppc_lr_regnum | |
2216 | || regnum == tdep->ppc_ctr_regnum | |
2217 | || regnum == tdep->ppc_xer_regnum | |
3e8c568d | 2218 | || regnum == gdbarch_pc_regnum (current_gdbarch)); |
c44ca51c AC |
2219 | if (group == general_reggroup) |
2220 | return general_p; | |
2221 | ||
2222 | if (group == save_reggroup || group == restore_reggroup) | |
2223 | return general_p || vector_p || float_p; | |
2224 | ||
2225 | return 0; | |
2226 | } | |
2227 | ||
691d145a | 2228 | /* The register format for RS/6000 floating point registers is always |
64366f1c | 2229 | double, we need a conversion if the memory format is float. */ |
7a78ae4e ND |
2230 | |
2231 | static int | |
691d145a | 2232 | rs6000_convert_register_p (int regnum, struct type *type) |
7a78ae4e | 2233 | { |
691d145a JB |
2234 | const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum; |
2235 | ||
2236 | return (reg->fpr | |
2237 | && TYPE_CODE (type) == TYPE_CODE_FLT | |
2238 | && TYPE_LENGTH (type) != TYPE_LENGTH (builtin_type_double)); | |
7a78ae4e ND |
2239 | } |
2240 | ||
7a78ae4e | 2241 | static void |
691d145a JB |
2242 | rs6000_register_to_value (struct frame_info *frame, |
2243 | int regnum, | |
2244 | struct type *type, | |
50fd1280 | 2245 | gdb_byte *to) |
7a78ae4e | 2246 | { |
691d145a | 2247 | const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum; |
50fd1280 | 2248 | gdb_byte from[MAX_REGISTER_SIZE]; |
691d145a JB |
2249 | |
2250 | gdb_assert (reg->fpr); | |
2251 | gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT); | |
7a78ae4e | 2252 | |
691d145a JB |
2253 | get_frame_register (frame, regnum, from); |
2254 | convert_typed_floating (from, builtin_type_double, to, type); | |
2255 | } | |
7a292a7a | 2256 | |
7a78ae4e | 2257 | static void |
691d145a JB |
2258 | rs6000_value_to_register (struct frame_info *frame, |
2259 | int regnum, | |
2260 | struct type *type, | |
50fd1280 | 2261 | const gdb_byte *from) |
7a78ae4e | 2262 | { |
691d145a | 2263 | const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum; |
50fd1280 | 2264 | gdb_byte to[MAX_REGISTER_SIZE]; |
691d145a JB |
2265 | |
2266 | gdb_assert (reg->fpr); | |
2267 | gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT); | |
2268 | ||
2269 | convert_typed_floating (from, type, to, builtin_type_double); | |
2270 | put_frame_register (frame, regnum, to); | |
7a78ae4e | 2271 | } |
c906108c | 2272 | |
6ced10dd JB |
2273 | /* Move SPE vector register values between a 64-bit buffer and the two |
2274 | 32-bit raw register halves in a regcache. This function handles | |
2275 | both splitting a 64-bit value into two 32-bit halves, and joining | |
2276 | two halves into a whole 64-bit value, depending on the function | |
2277 | passed as the MOVE argument. | |
2278 | ||
2279 | EV_REG must be the number of an SPE evN vector register --- a | |
2280 | pseudoregister. REGCACHE must be a regcache, and BUFFER must be a | |
2281 | 64-bit buffer. | |
2282 | ||
2283 | Call MOVE once for each 32-bit half of that register, passing | |
2284 | REGCACHE, the number of the raw register corresponding to that | |
2285 | half, and the address of the appropriate half of BUFFER. | |
2286 | ||
2287 | For example, passing 'regcache_raw_read' as the MOVE function will | |
2288 | fill BUFFER with the full 64-bit contents of EV_REG. Or, passing | |
2289 | 'regcache_raw_supply' will supply the contents of BUFFER to the | |
2290 | appropriate pair of raw registers in REGCACHE. | |
2291 | ||
2292 | You may need to cast away some 'const' qualifiers when passing | |
2293 | MOVE, since this function can't tell at compile-time which of | |
2294 | REGCACHE or BUFFER is acting as the source of the data. If C had | |
2295 | co-variant type qualifiers, ... */ | |
2296 | static void | |
2297 | e500_move_ev_register (void (*move) (struct regcache *regcache, | |
50fd1280 | 2298 | int regnum, gdb_byte *buf), |
6ced10dd | 2299 | struct regcache *regcache, int ev_reg, |
50fd1280 | 2300 | gdb_byte *buffer) |
6ced10dd JB |
2301 | { |
2302 | struct gdbarch *arch = get_regcache_arch (regcache); | |
2303 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); | |
2304 | int reg_index; | |
50fd1280 | 2305 | gdb_byte *byte_buffer = buffer; |
6ced10dd JB |
2306 | |
2307 | gdb_assert (tdep->ppc_ev0_regnum <= ev_reg | |
2308 | && ev_reg < tdep->ppc_ev0_regnum + ppc_num_gprs); | |
2309 | ||
2310 | reg_index = ev_reg - tdep->ppc_ev0_regnum; | |
2311 | ||
4c6b5505 | 2312 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
6ced10dd JB |
2313 | { |
2314 | move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer); | |
2315 | move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer + 4); | |
2316 | } | |
2317 | else | |
2318 | { | |
2319 | move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer); | |
2320 | move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer + 4); | |
2321 | } | |
2322 | } | |
2323 | ||
c8001721 EZ |
2324 | static void |
2325 | e500_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
50fd1280 | 2326 | int reg_nr, gdb_byte *buffer) |
c8001721 | 2327 | { |
6ced10dd | 2328 | struct gdbarch *regcache_arch = get_regcache_arch (regcache); |
c8001721 EZ |
2329 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2330 | ||
6ced10dd JB |
2331 | gdb_assert (regcache_arch == gdbarch); |
2332 | ||
2333 | if (tdep->ppc_ev0_regnum <= reg_nr | |
2334 | && reg_nr < tdep->ppc_ev0_regnum + ppc_num_gprs) | |
2335 | e500_move_ev_register (regcache_raw_read, regcache, reg_nr, buffer); | |
2336 | else | |
a44bddec | 2337 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 AC |
2338 | _("e500_pseudo_register_read: " |
2339 | "called on unexpected register '%s' (%d)"), | |
a44bddec | 2340 | gdbarch_register_name (gdbarch, reg_nr), reg_nr); |
c8001721 EZ |
2341 | } |
2342 | ||
2343 | static void | |
2344 | e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
50fd1280 | 2345 | int reg_nr, const gdb_byte *buffer) |
c8001721 | 2346 | { |
6ced10dd | 2347 | struct gdbarch *regcache_arch = get_regcache_arch (regcache); |
c8001721 EZ |
2348 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2349 | ||
6ced10dd JB |
2350 | gdb_assert (regcache_arch == gdbarch); |
2351 | ||
2352 | if (tdep->ppc_ev0_regnum <= reg_nr | |
2353 | && reg_nr < tdep->ppc_ev0_regnum + ppc_num_gprs) | |
50fd1280 | 2354 | e500_move_ev_register ((void (*) (struct regcache *, int, gdb_byte *)) |
6ced10dd | 2355 | regcache_raw_write, |
50fd1280 | 2356 | regcache, reg_nr, (gdb_byte *) buffer); |
6ced10dd | 2357 | else |
a44bddec | 2358 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 AC |
2359 | _("e500_pseudo_register_read: " |
2360 | "called on unexpected register '%s' (%d)"), | |
a44bddec | 2361 | gdbarch_register_name (gdbarch, reg_nr), reg_nr); |
6ced10dd JB |
2362 | } |
2363 | ||
2364 | /* The E500 needs a custom reggroup function: it has anonymous raw | |
2365 | registers, and default_register_reggroup_p assumes that anonymous | |
2366 | registers are not members of any reggroup. */ | |
2367 | static int | |
2368 | e500_register_reggroup_p (struct gdbarch *gdbarch, | |
2369 | int regnum, | |
2370 | struct reggroup *group) | |
2371 | { | |
2372 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2373 | ||
2374 | /* The save and restore register groups need to include the | |
2375 | upper-half registers, even though they're anonymous. */ | |
2376 | if ((group == save_reggroup | |
2377 | || group == restore_reggroup) | |
2378 | && (tdep->ppc_ev0_upper_regnum <= regnum | |
2379 | && regnum < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)) | |
2380 | return 1; | |
2381 | ||
2382 | /* In all other regards, the default reggroup definition is fine. */ | |
2383 | return default_register_reggroup_p (gdbarch, regnum, group); | |
c8001721 EZ |
2384 | } |
2385 | ||
18ed0c4e | 2386 | /* Convert a DBX STABS register number to a GDB register number. */ |
c8001721 | 2387 | static int |
18ed0c4e | 2388 | rs6000_stab_reg_to_regnum (int num) |
c8001721 | 2389 | { |
9f744501 | 2390 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c8001721 | 2391 | |
9f744501 JB |
2392 | if (0 <= num && num <= 31) |
2393 | return tdep->ppc_gp0_regnum + num; | |
2394 | else if (32 <= num && num <= 63) | |
383f0f5b JB |
2395 | /* FIXME: jimb/2004-05-05: What should we do when the debug info |
2396 | specifies registers the architecture doesn't have? Our | |
2397 | callers don't check the value we return. */ | |
366f009f | 2398 | return tdep->ppc_fp0_regnum + (num - 32); |
18ed0c4e JB |
2399 | else if (77 <= num && num <= 108) |
2400 | return tdep->ppc_vr0_regnum + (num - 77); | |
9f744501 JB |
2401 | else if (1200 <= num && num < 1200 + 32) |
2402 | return tdep->ppc_ev0_regnum + (num - 1200); | |
2403 | else | |
2404 | switch (num) | |
2405 | { | |
2406 | case 64: | |
2407 | return tdep->ppc_mq_regnum; | |
2408 | case 65: | |
2409 | return tdep->ppc_lr_regnum; | |
2410 | case 66: | |
2411 | return tdep->ppc_ctr_regnum; | |
2412 | case 76: | |
2413 | return tdep->ppc_xer_regnum; | |
2414 | case 109: | |
2415 | return tdep->ppc_vrsave_regnum; | |
18ed0c4e JB |
2416 | case 110: |
2417 | return tdep->ppc_vrsave_regnum - 1; /* vscr */ | |
867e2dc5 | 2418 | case 111: |
18ed0c4e | 2419 | return tdep->ppc_acc_regnum; |
867e2dc5 | 2420 | case 112: |
18ed0c4e | 2421 | return tdep->ppc_spefscr_regnum; |
9f744501 JB |
2422 | default: |
2423 | return num; | |
2424 | } | |
18ed0c4e | 2425 | } |
9f744501 | 2426 | |
9f744501 | 2427 | |
18ed0c4e JB |
2428 | /* Convert a Dwarf 2 register number to a GDB register number. */ |
2429 | static int | |
2430 | rs6000_dwarf2_reg_to_regnum (int num) | |
2431 | { | |
2432 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
9f744501 | 2433 | |
18ed0c4e JB |
2434 | if (0 <= num && num <= 31) |
2435 | return tdep->ppc_gp0_regnum + num; | |
2436 | else if (32 <= num && num <= 63) | |
2437 | /* FIXME: jimb/2004-05-05: What should we do when the debug info | |
2438 | specifies registers the architecture doesn't have? Our | |
2439 | callers don't check the value we return. */ | |
2440 | return tdep->ppc_fp0_regnum + (num - 32); | |
2441 | else if (1124 <= num && num < 1124 + 32) | |
2442 | return tdep->ppc_vr0_regnum + (num - 1124); | |
2443 | else if (1200 <= num && num < 1200 + 32) | |
2444 | return tdep->ppc_ev0_regnum + (num - 1200); | |
2445 | else | |
2446 | switch (num) | |
2447 | { | |
a489f789 AS |
2448 | case 64: |
2449 | return tdep->ppc_cr_regnum; | |
18ed0c4e JB |
2450 | case 67: |
2451 | return tdep->ppc_vrsave_regnum - 1; /* vscr */ | |
2452 | case 99: | |
2453 | return tdep->ppc_acc_regnum; | |
2454 | case 100: | |
2455 | return tdep->ppc_mq_regnum; | |
2456 | case 101: | |
2457 | return tdep->ppc_xer_regnum; | |
2458 | case 108: | |
2459 | return tdep->ppc_lr_regnum; | |
2460 | case 109: | |
2461 | return tdep->ppc_ctr_regnum; | |
2462 | case 356: | |
2463 | return tdep->ppc_vrsave_regnum; | |
2464 | case 612: | |
2465 | return tdep->ppc_spefscr_regnum; | |
2466 | default: | |
2467 | return num; | |
2468 | } | |
2188cbdd EZ |
2469 | } |
2470 | ||
4fc771b8 DJ |
2471 | /* Translate a .eh_frame register to DWARF register, or adjust a |
2472 | .debug_frame register. */ | |
2473 | ||
2474 | static int | |
2475 | rs6000_adjust_frame_regnum (struct gdbarch *gdbarch, int num, int eh_frame_p) | |
2476 | { | |
2477 | /* GCC releases before 3.4 use GCC internal register numbering in | |
2478 | .debug_frame (and .debug_info, et cetera). The numbering is | |
2479 | different from the standard SysV numbering for everything except | |
2480 | for GPRs and FPRs. We can not detect this problem in most cases | |
2481 | - to get accurate debug info for variables living in lr, ctr, v0, | |
2482 | et cetera, use a newer version of GCC. But we must detect | |
2483 | one important case - lr is in column 65 in .debug_frame output, | |
2484 | instead of 108. | |
2485 | ||
2486 | GCC 3.4, and the "hammer" branch, have a related problem. They | |
2487 | record lr register saves in .debug_frame as 108, but still record | |
2488 | the return column as 65. We fix that up too. | |
2489 | ||
2490 | We can do this because 65 is assigned to fpsr, and GCC never | |
2491 | generates debug info referring to it. To add support for | |
2492 | handwritten debug info that restores fpsr, we would need to add a | |
2493 | producer version check to this. */ | |
2494 | if (!eh_frame_p) | |
2495 | { | |
2496 | if (num == 65) | |
2497 | return 108; | |
2498 | else | |
2499 | return num; | |
2500 | } | |
2501 | ||
2502 | /* .eh_frame is GCC specific. For binary compatibility, it uses GCC | |
2503 | internal register numbering; translate that to the standard DWARF2 | |
2504 | register numbering. */ | |
2505 | if (0 <= num && num <= 63) /* r0-r31,fp0-fp31 */ | |
2506 | return num; | |
2507 | else if (68 <= num && num <= 75) /* cr0-cr8 */ | |
2508 | return num - 68 + 86; | |
2509 | else if (77 <= num && num <= 108) /* vr0-vr31 */ | |
2510 | return num - 77 + 1124; | |
2511 | else | |
2512 | switch (num) | |
2513 | { | |
2514 | case 64: /* mq */ | |
2515 | return 100; | |
2516 | case 65: /* lr */ | |
2517 | return 108; | |
2518 | case 66: /* ctr */ | |
2519 | return 109; | |
2520 | case 76: /* xer */ | |
2521 | return 101; | |
2522 | case 109: /* vrsave */ | |
2523 | return 356; | |
2524 | case 110: /* vscr */ | |
2525 | return 67; | |
2526 | case 111: /* spe_acc */ | |
2527 | return 99; | |
2528 | case 112: /* spefscr */ | |
2529 | return 612; | |
2530 | default: | |
2531 | return num; | |
2532 | } | |
2533 | } | |
c906108c | 2534 | \f |
e2d0e7eb | 2535 | /* Support for CONVERT_FROM_FUNC_PTR_ADDR (ARCH, ADDR, TARG). |
7a78ae4e ND |
2536 | |
2537 | Usually a function pointer's representation is simply the address | |
2538 | of the function. On the RS/6000 however, a function pointer is | |
8ba0209f | 2539 | represented by a pointer to an OPD entry. This OPD entry contains |
7a78ae4e ND |
2540 | three words, the first word is the address of the function, the |
2541 | second word is the TOC pointer (r2), and the third word is the | |
2542 | static chain value. Throughout GDB it is currently assumed that a | |
2543 | function pointer contains the address of the function, which is not | |
2544 | easy to fix. In addition, the conversion of a function address to | |
8ba0209f | 2545 | a function pointer would require allocation of an OPD entry in the |
7a78ae4e ND |
2546 | inferior's memory space, with all its drawbacks. To be able to |
2547 | call C++ virtual methods in the inferior (which are called via | |
f517ea4e | 2548 | function pointers), find_function_addr uses this function to get the |
7a78ae4e ND |
2549 | function address from a function pointer. */ |
2550 | ||
f517ea4e PS |
2551 | /* Return real function address if ADDR (a function pointer) is in the data |
2552 | space and is therefore a special function pointer. */ | |
c906108c | 2553 | |
b9362cc7 | 2554 | static CORE_ADDR |
e2d0e7eb AC |
2555 | rs6000_convert_from_func_ptr_addr (struct gdbarch *gdbarch, |
2556 | CORE_ADDR addr, | |
2557 | struct target_ops *targ) | |
c906108c SS |
2558 | { |
2559 | struct obj_section *s; | |
2560 | ||
2561 | s = find_pc_section (addr); | |
2562 | if (s && s->the_bfd_section->flags & SEC_CODE) | |
7a78ae4e | 2563 | return addr; |
c906108c | 2564 | |
7a78ae4e | 2565 | /* ADDR is in the data space, so it's a special function pointer. */ |
7f68ac27 | 2566 | return read_memory_addr (addr, gdbarch_tdep (gdbarch)->wordsize); |
c906108c | 2567 | } |
c906108c | 2568 | \f |
c5aa993b | 2569 | |
7a78ae4e | 2570 | /* Handling the various POWER/PowerPC variants. */ |
c906108c SS |
2571 | |
2572 | ||
7a78ae4e ND |
2573 | /* The arrays here called registers_MUMBLE hold information about available |
2574 | registers. | |
c906108c SS |
2575 | |
2576 | For each family of PPC variants, I've tried to isolate out the | |
2577 | common registers and put them up front, so that as long as you get | |
2578 | the general family right, GDB will correctly identify the registers | |
2579 | common to that family. The common register sets are: | |
2580 | ||
2581 | For the 60x family: hid0 hid1 iabr dabr pir | |
2582 | ||
2583 | For the 505 and 860 family: eie eid nri | |
2584 | ||
2585 | For the 403 and 403GC: icdbdr esr dear evpr cdbcr tsr tcr pit tbhi | |
c5aa993b JM |
2586 | tblo srr2 srr3 dbsr dbcr iac1 iac2 dac1 dac2 dccr iccr pbl1 |
2587 | pbu1 pbl2 pbu2 | |
c906108c SS |
2588 | |
2589 | Most of these register groups aren't anything formal. I arrived at | |
2590 | them by looking at the registers that occurred in more than one | |
6f5987a6 KB |
2591 | processor. |
2592 | ||
2593 | Note: kevinb/2002-04-30: Support for the fpscr register was added | |
2594 | during April, 2002. Slot 70 is being used for PowerPC and slot 71 | |
2595 | for Power. For PowerPC, slot 70 was unused and was already in the | |
2596 | PPC_UISA_SPRS which is ideally where fpscr should go. For Power, | |
2597 | slot 70 was being used for "mq", so the next available slot (71) | |
2598 | was chosen. It would have been nice to be able to make the | |
2599 | register numbers the same across processor cores, but this wasn't | |
2600 | possible without either 1) renumbering some registers for some | |
2601 | processors or 2) assigning fpscr to a really high slot that's | |
2602 | larger than any current register number. Doing (1) is bad because | |
2603 | existing stubs would break. Doing (2) is undesirable because it | |
2604 | would introduce a really large gap between fpscr and the rest of | |
2605 | the registers for most processors. */ | |
7a78ae4e | 2606 | |
64366f1c | 2607 | /* Convenience macros for populating register arrays. */ |
7a78ae4e | 2608 | |
64366f1c | 2609 | /* Within another macro, convert S to a string. */ |
7a78ae4e ND |
2610 | |
2611 | #define STR(s) #s | |
2612 | ||
2613 | /* Return a struct reg defining register NAME that's 32 bits on 32-bit systems | |
64366f1c | 2614 | and 64 bits on 64-bit systems. */ |
13ac140c | 2615 | #define R(name) { STR(name), 4, 8, 0, 0, -1 } |
7a78ae4e ND |
2616 | |
2617 | /* Return a struct reg defining register NAME that's 32 bits on all | |
64366f1c | 2618 | systems. */ |
13ac140c | 2619 | #define R4(name) { STR(name), 4, 4, 0, 0, -1 } |
7a78ae4e ND |
2620 | |
2621 | /* Return a struct reg defining register NAME that's 64 bits on all | |
64366f1c | 2622 | systems. */ |
13ac140c | 2623 | #define R8(name) { STR(name), 8, 8, 0, 0, -1 } |
7a78ae4e | 2624 | |
1fcc0bb8 | 2625 | /* Return a struct reg defining register NAME that's 128 bits on all |
64366f1c | 2626 | systems. */ |
13ac140c | 2627 | #define R16(name) { STR(name), 16, 16, 0, 0, -1 } |
1fcc0bb8 | 2628 | |
64366f1c | 2629 | /* Return a struct reg defining floating-point register NAME. */ |
13ac140c | 2630 | #define F(name) { STR(name), 8, 8, 1, 0, -1 } |
489461e2 | 2631 | |
6ced10dd JB |
2632 | /* Return a struct reg defining a pseudo register NAME that is 64 bits |
2633 | long on all systems. */ | |
2634 | #define P8(name) { STR(name), 8, 8, 0, 1, -1 } | |
7a78ae4e ND |
2635 | |
2636 | /* Return a struct reg defining register NAME that's 32 bits on 32-bit | |
64366f1c | 2637 | systems and that doesn't exist on 64-bit systems. */ |
13ac140c | 2638 | #define R32(name) { STR(name), 4, 0, 0, 0, -1 } |
7a78ae4e ND |
2639 | |
2640 | /* Return a struct reg defining register NAME that's 64 bits on 64-bit | |
64366f1c | 2641 | systems and that doesn't exist on 32-bit systems. */ |
13ac140c | 2642 | #define R64(name) { STR(name), 0, 8, 0, 0, -1 } |
7a78ae4e | 2643 | |
64366f1c | 2644 | /* Return a struct reg placeholder for a register that doesn't exist. */ |
13ac140c | 2645 | #define R0 { 0, 0, 0, 0, 0, -1 } |
7a78ae4e | 2646 | |
6ced10dd JB |
2647 | /* Return a struct reg defining an anonymous raw register that's 32 |
2648 | bits on all systems. */ | |
2649 | #define A4 { 0, 4, 4, 0, 0, -1 } | |
2650 | ||
13ac140c JB |
2651 | /* Return a struct reg defining an SPR named NAME that is 32 bits on |
2652 | 32-bit systems and 64 bits on 64-bit systems. */ | |
2653 | #define S(name) { STR(name), 4, 8, 0, 0, ppc_spr_ ## name } | |
2654 | ||
2655 | /* Return a struct reg defining an SPR named NAME that is 32 bits on | |
2656 | all systems. */ | |
2657 | #define S4(name) { STR(name), 4, 4, 0, 0, ppc_spr_ ## name } | |
2658 | ||
2659 | /* Return a struct reg defining an SPR named NAME that is 32 bits on | |
2660 | all systems, and whose SPR number is NUMBER. */ | |
2661 | #define SN4(name, number) { STR(name), 4, 4, 0, 0, (number) } | |
2662 | ||
2663 | /* Return a struct reg defining an SPR named NAME that's 64 bits on | |
2664 | 64-bit systems and that doesn't exist on 32-bit systems. */ | |
2665 | #define S64(name) { STR(name), 0, 8, 0, 0, ppc_spr_ ## name } | |
2666 | ||
7a78ae4e ND |
2667 | /* UISA registers common across all architectures, including POWER. */ |
2668 | ||
2669 | #define COMMON_UISA_REGS \ | |
2670 | /* 0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), \ | |
2671 | /* 8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \ | |
2672 | /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \ | |
2673 | /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \ | |
2674 | /* 32 */ F(f0), F(f1), F(f2), F(f3), F(f4), F(f5), F(f6), F(f7), \ | |
2675 | /* 40 */ F(f8), F(f9), F(f10),F(f11),F(f12),F(f13),F(f14),F(f15), \ | |
2676 | /* 48 */ F(f16),F(f17),F(f18),F(f19),F(f20),F(f21),F(f22),F(f23), \ | |
2677 | /* 56 */ F(f24),F(f25),F(f26),F(f27),F(f28),F(f29),F(f30),F(f31), \ | |
2678 | /* 64 */ R(pc), R(ps) | |
2679 | ||
2680 | /* UISA-level SPRs for PowerPC. */ | |
2681 | #define PPC_UISA_SPRS \ | |
13ac140c | 2682 | /* 66 */ R4(cr), S(lr), S(ctr), S4(xer), R4(fpscr) |
7a78ae4e | 2683 | |
c8001721 EZ |
2684 | /* UISA-level SPRs for PowerPC without floating point support. */ |
2685 | #define PPC_UISA_NOFP_SPRS \ | |
13ac140c | 2686 | /* 66 */ R4(cr), S(lr), S(ctr), S4(xer), R0 |
c8001721 | 2687 | |
7a78ae4e ND |
2688 | /* Segment registers, for PowerPC. */ |
2689 | #define PPC_SEGMENT_REGS \ | |
2690 | /* 71 */ R32(sr0), R32(sr1), R32(sr2), R32(sr3), \ | |
2691 | /* 75 */ R32(sr4), R32(sr5), R32(sr6), R32(sr7), \ | |
2692 | /* 79 */ R32(sr8), R32(sr9), R32(sr10), R32(sr11), \ | |
2693 | /* 83 */ R32(sr12), R32(sr13), R32(sr14), R32(sr15) | |
2694 | ||
2695 | /* OEA SPRs for PowerPC. */ | |
2696 | #define PPC_OEA_SPRS \ | |
13ac140c JB |
2697 | /* 87 */ S4(pvr), \ |
2698 | /* 88 */ S(ibat0u), S(ibat0l), S(ibat1u), S(ibat1l), \ | |
2699 | /* 92 */ S(ibat2u), S(ibat2l), S(ibat3u), S(ibat3l), \ | |
2700 | /* 96 */ S(dbat0u), S(dbat0l), S(dbat1u), S(dbat1l), \ | |
2701 | /* 100 */ S(dbat2u), S(dbat2l), S(dbat3u), S(dbat3l), \ | |
2702 | /* 104 */ S(sdr1), S64(asr), S(dar), S4(dsisr), \ | |
2703 | /* 108 */ S(sprg0), S(sprg1), S(sprg2), S(sprg3), \ | |
2704 | /* 112 */ S(srr0), S(srr1), S(tbl), S(tbu), \ | |
2705 | /* 116 */ S4(dec), S(dabr), S4(ear) | |
7a78ae4e | 2706 | |
64366f1c | 2707 | /* AltiVec registers. */ |
1fcc0bb8 EZ |
2708 | #define PPC_ALTIVEC_REGS \ |
2709 | /*119*/R16(vr0), R16(vr1), R16(vr2), R16(vr3), R16(vr4), R16(vr5), R16(vr6), R16(vr7), \ | |
2710 | /*127*/R16(vr8), R16(vr9), R16(vr10),R16(vr11),R16(vr12),R16(vr13),R16(vr14),R16(vr15), \ | |
2711 | /*135*/R16(vr16),R16(vr17),R16(vr18),R16(vr19),R16(vr20),R16(vr21),R16(vr22),R16(vr23), \ | |
2712 | /*143*/R16(vr24),R16(vr25),R16(vr26),R16(vr27),R16(vr28),R16(vr29),R16(vr30),R16(vr31), \ | |
2713 | /*151*/R4(vscr), R4(vrsave) | |
2714 | ||
c8001721 | 2715 | |
6ced10dd JB |
2716 | /* On machines supporting the SPE APU, the general-purpose registers |
2717 | are 64 bits long. There are SIMD vector instructions to treat them | |
2718 | as pairs of floats, but the rest of the instruction set treats them | |
2719 | as 32-bit registers, and only operates on their lower halves. | |
2720 | ||
2721 | In the GDB regcache, we treat their high and low halves as separate | |
2722 | registers. The low halves we present as the general-purpose | |
2723 | registers, and then we have pseudo-registers that stitch together | |
2724 | the upper and lower halves and present them as pseudo-registers. */ | |
2725 | ||
2726 | /* SPE GPR lower halves --- raw registers. */ | |
2727 | #define PPC_SPE_GP_REGS \ | |
2728 | /* 0 */ R4(r0), R4(r1), R4(r2), R4(r3), R4(r4), R4(r5), R4(r6), R4(r7), \ | |
2729 | /* 8 */ R4(r8), R4(r9), R4(r10),R4(r11),R4(r12),R4(r13),R4(r14),R4(r15), \ | |
2730 | /* 16 */ R4(r16),R4(r17),R4(r18),R4(r19),R4(r20),R4(r21),R4(r22),R4(r23), \ | |
2731 | /* 24 */ R4(r24),R4(r25),R4(r26),R4(r27),R4(r28),R4(r29),R4(r30),R4(r31) | |
2732 | ||
2733 | /* SPE GPR upper halves --- anonymous raw registers. */ | |
2734 | #define PPC_SPE_UPPER_GP_REGS \ | |
2735 | /* 0 */ A4, A4, A4, A4, A4, A4, A4, A4, \ | |
2736 | /* 8 */ A4, A4, A4, A4, A4, A4, A4, A4, \ | |
2737 | /* 16 */ A4, A4, A4, A4, A4, A4, A4, A4, \ | |
2738 | /* 24 */ A4, A4, A4, A4, A4, A4, A4, A4 | |
2739 | ||
2740 | /* SPE GPR vector registers --- pseudo registers based on underlying | |
2741 | gprs and the anonymous upper half raw registers. */ | |
2742 | #define PPC_EV_PSEUDO_REGS \ | |
2743 | /* 0*/P8(ev0), P8(ev1), P8(ev2), P8(ev3), P8(ev4), P8(ev5), P8(ev6), P8(ev7), \ | |
2744 | /* 8*/P8(ev8), P8(ev9), P8(ev10),P8(ev11),P8(ev12),P8(ev13),P8(ev14),P8(ev15),\ | |
2745 | /*16*/P8(ev16),P8(ev17),P8(ev18),P8(ev19),P8(ev20),P8(ev21),P8(ev22),P8(ev23),\ | |
2746 | /*24*/P8(ev24),P8(ev25),P8(ev26),P8(ev27),P8(ev28),P8(ev29),P8(ev30),P8(ev31) | |
c8001721 | 2747 | |
7a78ae4e | 2748 | /* IBM POWER (pre-PowerPC) architecture, user-level view. We only cover |
64366f1c | 2749 | user-level SPR's. */ |
7a78ae4e | 2750 | static const struct reg registers_power[] = |
c906108c | 2751 | { |
7a78ae4e | 2752 | COMMON_UISA_REGS, |
13ac140c | 2753 | /* 66 */ R4(cnd), S(lr), S(cnt), S4(xer), S4(mq), |
e3f36dbd | 2754 | /* 71 */ R4(fpscr) |
c906108c SS |
2755 | }; |
2756 | ||
7a78ae4e | 2757 | /* PowerPC UISA - a PPC processor as viewed by user-level code. A UISA-only |
64366f1c | 2758 | view of the PowerPC. */ |
7a78ae4e | 2759 | static const struct reg registers_powerpc[] = |
c906108c | 2760 | { |
7a78ae4e | 2761 | COMMON_UISA_REGS, |
1fcc0bb8 EZ |
2762 | PPC_UISA_SPRS, |
2763 | PPC_ALTIVEC_REGS | |
c906108c SS |
2764 | }; |
2765 | ||
13ac140c JB |
2766 | /* IBM PowerPC 403. |
2767 | ||
2768 | Some notes about the "tcr" special-purpose register: | |
2769 | - On the 403 and 403GC, SPR 986 is named "tcr", and it controls the | |
2770 | 403's programmable interval timer, fixed interval timer, and | |
2771 | watchdog timer. | |
2772 | - On the 602, SPR 984 is named "tcr", and it controls the 602's | |
2773 | watchdog timer, and nothing else. | |
2774 | ||
2775 | Some of the fields are similar between the two, but they're not | |
2776 | compatible with each other. Since the two variants have different | |
2777 | registers, with different numbers, but the same name, we can't | |
2778 | splice the register name to get the SPR number. */ | |
7a78ae4e | 2779 | static const struct reg registers_403[] = |
c5aa993b | 2780 | { |
7a78ae4e ND |
2781 | COMMON_UISA_REGS, |
2782 | PPC_UISA_SPRS, | |
2783 | PPC_SEGMENT_REGS, | |
2784 | PPC_OEA_SPRS, | |
13ac140c JB |
2785 | /* 119 */ S(icdbdr), S(esr), S(dear), S(evpr), |
2786 | /* 123 */ S(cdbcr), S(tsr), SN4(tcr, ppc_spr_403_tcr), S(pit), | |
2787 | /* 127 */ S(tbhi), S(tblo), S(srr2), S(srr3), | |
2788 | /* 131 */ S(dbsr), S(dbcr), S(iac1), S(iac2), | |
2789 | /* 135 */ S(dac1), S(dac2), S(dccr), S(iccr), | |
2790 | /* 139 */ S(pbl1), S(pbu1), S(pbl2), S(pbu2) | |
c906108c SS |
2791 | }; |
2792 | ||
13ac140c JB |
2793 | /* IBM PowerPC 403GC. |
2794 | See the comments about 'tcr' for the 403, above. */ | |
7a78ae4e | 2795 | static const struct reg registers_403GC[] = |
c5aa993b | 2796 | { |
7a78ae4e ND |
2797 | COMMON_UISA_REGS, |
2798 | PPC_UISA_SPRS, | |
2799 | PPC_SEGMENT_REGS, | |
2800 | PPC_OEA_SPRS, | |
13ac140c JB |
2801 | /* 119 */ S(icdbdr), S(esr), S(dear), S(evpr), |
2802 | /* 123 */ S(cdbcr), S(tsr), SN4(tcr, ppc_spr_403_tcr), S(pit), | |
2803 | /* 127 */ S(tbhi), S(tblo), S(srr2), S(srr3), | |
2804 | /* 131 */ S(dbsr), S(dbcr), S(iac1), S(iac2), | |
2805 | /* 135 */ S(dac1), S(dac2), S(dccr), S(iccr), | |
2806 | /* 139 */ S(pbl1), S(pbu1), S(pbl2), S(pbu2), | |
2807 | /* 143 */ S(zpr), S(pid), S(sgr), S(dcwr), | |
2808 | /* 147 */ S(tbhu), S(tblu) | |
c906108c SS |
2809 | }; |
2810 | ||
64366f1c | 2811 | /* Motorola PowerPC 505. */ |
7a78ae4e | 2812 | static const struct reg registers_505[] = |
c5aa993b | 2813 | { |
7a78ae4e ND |
2814 | COMMON_UISA_REGS, |
2815 | PPC_UISA_SPRS, | |
2816 | PPC_SEGMENT_REGS, | |
2817 | PPC_OEA_SPRS, | |
13ac140c | 2818 | /* 119 */ S(eie), S(eid), S(nri) |
c906108c SS |
2819 | }; |
2820 | ||
64366f1c | 2821 | /* Motorola PowerPC 860 or 850. */ |
7a78ae4e | 2822 | static const struct reg registers_860[] = |
c5aa993b | 2823 | { |
7a78ae4e ND |
2824 | COMMON_UISA_REGS, |
2825 | PPC_UISA_SPRS, | |
2826 | PPC_SEGMENT_REGS, | |
2827 | PPC_OEA_SPRS, | |
13ac140c JB |
2828 | /* 119 */ S(eie), S(eid), S(nri), S(cmpa), |
2829 | /* 123 */ S(cmpb), S(cmpc), S(cmpd), S(icr), | |
2830 | /* 127 */ S(der), S(counta), S(countb), S(cmpe), | |
2831 | /* 131 */ S(cmpf), S(cmpg), S(cmph), S(lctrl1), | |
2832 | /* 135 */ S(lctrl2), S(ictrl), S(bar), S(ic_cst), | |
2833 | /* 139 */ S(ic_adr), S(ic_dat), S(dc_cst), S(dc_adr), | |
2834 | /* 143 */ S(dc_dat), S(dpdr), S(dpir), S(immr), | |
2835 | /* 147 */ S(mi_ctr), S(mi_ap), S(mi_epn), S(mi_twc), | |
2836 | /* 151 */ S(mi_rpn), S(md_ctr), S(m_casid), S(md_ap), | |
2837 | /* 155 */ S(md_epn), S(m_twb), S(md_twc), S(md_rpn), | |
2838 | /* 159 */ S(m_tw), S(mi_dbcam), S(mi_dbram0), S(mi_dbram1), | |
2839 | /* 163 */ S(md_dbcam), S(md_dbram0), S(md_dbram1) | |
c906108c SS |
2840 | }; |
2841 | ||
7a78ae4e ND |
2842 | /* Motorola PowerPC 601. Note that the 601 has different register numbers |
2843 | for reading and writing RTCU and RTCL. However, how one reads and writes a | |
c906108c | 2844 | register is the stub's problem. */ |
7a78ae4e | 2845 | static const struct reg registers_601[] = |
c5aa993b | 2846 | { |
7a78ae4e ND |
2847 | COMMON_UISA_REGS, |
2848 | PPC_UISA_SPRS, | |
2849 | PPC_SEGMENT_REGS, | |
2850 | PPC_OEA_SPRS, | |
13ac140c JB |
2851 | /* 119 */ S(hid0), S(hid1), S(iabr), S(dabr), |
2852 | /* 123 */ S(pir), S(mq), S(rtcu), S(rtcl) | |
c906108c SS |
2853 | }; |
2854 | ||
13ac140c JB |
2855 | /* Motorola PowerPC 602. |
2856 | See the notes under the 403 about 'tcr'. */ | |
7a78ae4e | 2857 | static const struct reg registers_602[] = |
c5aa993b | 2858 | { |
7a78ae4e ND |
2859 | COMMON_UISA_REGS, |
2860 | PPC_UISA_SPRS, | |
2861 | PPC_SEGMENT_REGS, | |
2862 | PPC_OEA_SPRS, | |
13ac140c JB |
2863 | /* 119 */ S(hid0), S(hid1), S(iabr), R0, |
2864 | /* 123 */ R0, SN4(tcr, ppc_spr_602_tcr), S(ibr), S(esasrr), | |
2865 | /* 127 */ S(sebr), S(ser), S(sp), S(lt) | |
c906108c SS |
2866 | }; |
2867 | ||
64366f1c | 2868 | /* Motorola/IBM PowerPC 603 or 603e. */ |
7a78ae4e | 2869 | static const struct reg registers_603[] = |
c5aa993b | 2870 | { |
7a78ae4e ND |
2871 | COMMON_UISA_REGS, |
2872 | PPC_UISA_SPRS, | |
2873 | PPC_SEGMENT_REGS, | |
2874 | PPC_OEA_SPRS, | |
13ac140c JB |
2875 | /* 119 */ S(hid0), S(hid1), S(iabr), R0, |
2876 | /* 123 */ R0, S(dmiss), S(dcmp), S(hash1), | |
2877 | /* 127 */ S(hash2), S(imiss), S(icmp), S(rpa) | |
c906108c SS |
2878 | }; |
2879 | ||
64366f1c | 2880 | /* Motorola PowerPC 604 or 604e. */ |
7a78ae4e | 2881 | static const struct reg registers_604[] = |
c5aa993b | 2882 | { |
7a78ae4e ND |
2883 | COMMON_UISA_REGS, |
2884 | PPC_UISA_SPRS, | |
2885 | PPC_SEGMENT_REGS, | |
2886 | PPC_OEA_SPRS, | |
13ac140c JB |
2887 | /* 119 */ S(hid0), S(hid1), S(iabr), S(dabr), |
2888 | /* 123 */ S(pir), S(mmcr0), S(pmc1), S(pmc2), | |
2889 | /* 127 */ S(sia), S(sda) | |
c906108c SS |
2890 | }; |
2891 | ||
64366f1c | 2892 | /* Motorola/IBM PowerPC 750 or 740. */ |
7a78ae4e | 2893 | static const struct reg registers_750[] = |
c5aa993b | 2894 | { |
7a78ae4e ND |
2895 | COMMON_UISA_REGS, |
2896 | PPC_UISA_SPRS, | |
2897 | PPC_SEGMENT_REGS, | |
2898 | PPC_OEA_SPRS, | |
13ac140c JB |
2899 | /* 119 */ S(hid0), S(hid1), S(iabr), S(dabr), |
2900 | /* 123 */ R0, S(ummcr0), S(upmc1), S(upmc2), | |
2901 | /* 127 */ S(usia), S(ummcr1), S(upmc3), S(upmc4), | |
2902 | /* 131 */ S(mmcr0), S(pmc1), S(pmc2), S(sia), | |
2903 | /* 135 */ S(mmcr1), S(pmc3), S(pmc4), S(l2cr), | |
2904 | /* 139 */ S(ictc), S(thrm1), S(thrm2), S(thrm3) | |
c906108c SS |
2905 | }; |
2906 | ||
2907 | ||
64366f1c | 2908 | /* Motorola PowerPC 7400. */ |
1fcc0bb8 EZ |
2909 | static const struct reg registers_7400[] = |
2910 | { | |
2911 | /* gpr0-gpr31, fpr0-fpr31 */ | |
2912 | COMMON_UISA_REGS, | |
13c7b1ca | 2913 | /* cr, lr, ctr, xer, fpscr */ |
1fcc0bb8 EZ |
2914 | PPC_UISA_SPRS, |
2915 | /* sr0-sr15 */ | |
2916 | PPC_SEGMENT_REGS, | |
2917 | PPC_OEA_SPRS, | |
2918 | /* vr0-vr31, vrsave, vscr */ | |
2919 | PPC_ALTIVEC_REGS | |
2920 | /* FIXME? Add more registers? */ | |
2921 | }; | |
2922 | ||
c8001721 EZ |
2923 | /* Motorola e500. */ |
2924 | static const struct reg registers_e500[] = | |
2925 | { | |
6ced10dd JB |
2926 | /* 0 .. 31 */ PPC_SPE_GP_REGS, |
2927 | /* 32 .. 63 */ PPC_SPE_UPPER_GP_REGS, | |
2928 | /* 64 .. 65 */ R(pc), R(ps), | |
2929 | /* 66 .. 70 */ PPC_UISA_NOFP_SPRS, | |
2930 | /* 71 .. 72 */ R8(acc), S4(spefscr), | |
338ef23d AC |
2931 | /* NOTE: Add new registers here the end of the raw register |
2932 | list and just before the first pseudo register. */ | |
6ced10dd | 2933 | /* 73 .. 104 */ PPC_EV_PSEUDO_REGS |
c8001721 EZ |
2934 | }; |
2935 | ||
c906108c | 2936 | /* Information about a particular processor variant. */ |
7a78ae4e | 2937 | |
c906108c | 2938 | struct variant |
c5aa993b JM |
2939 | { |
2940 | /* Name of this variant. */ | |
2941 | char *name; | |
c906108c | 2942 | |
c5aa993b JM |
2943 | /* English description of the variant. */ |
2944 | char *description; | |
c906108c | 2945 | |
64366f1c | 2946 | /* bfd_arch_info.arch corresponding to variant. */ |
7a78ae4e ND |
2947 | enum bfd_architecture arch; |
2948 | ||
64366f1c | 2949 | /* bfd_arch_info.mach corresponding to variant. */ |
7a78ae4e ND |
2950 | unsigned long mach; |
2951 | ||
489461e2 EZ |
2952 | /* Number of real registers. */ |
2953 | int nregs; | |
2954 | ||
2955 | /* Number of pseudo registers. */ | |
2956 | int npregs; | |
2957 | ||
2958 | /* Number of total registers (the sum of nregs and npregs). */ | |
2959 | int num_tot_regs; | |
2960 | ||
c5aa993b JM |
2961 | /* Table of register names; registers[R] is the name of the register |
2962 | number R. */ | |
7a78ae4e | 2963 | const struct reg *regs; |
c5aa993b | 2964 | }; |
c906108c | 2965 | |
489461e2 EZ |
2966 | #define tot_num_registers(list) (sizeof (list) / sizeof((list)[0])) |
2967 | ||
2968 | static int | |
2969 | num_registers (const struct reg *reg_list, int num_tot_regs) | |
2970 | { | |
2971 | int i; | |
2972 | int nregs = 0; | |
2973 | ||
2974 | for (i = 0; i < num_tot_regs; i++) | |
2975 | if (!reg_list[i].pseudo) | |
2976 | nregs++; | |
2977 | ||
2978 | return nregs; | |
2979 | } | |
2980 | ||
2981 | static int | |
2982 | num_pseudo_registers (const struct reg *reg_list, int num_tot_regs) | |
2983 | { | |
2984 | int i; | |
2985 | int npregs = 0; | |
2986 | ||
2987 | for (i = 0; i < num_tot_regs; i++) | |
2988 | if (reg_list[i].pseudo) | |
2989 | npregs ++; | |
2990 | ||
2991 | return npregs; | |
2992 | } | |
c906108c | 2993 | |
c906108c SS |
2994 | /* Information in this table comes from the following web sites: |
2995 | IBM: http://www.chips.ibm.com:80/products/embedded/ | |
2996 | Motorola: http://www.mot.com/SPS/PowerPC/ | |
2997 | ||
2998 | I'm sure I've got some of the variant descriptions not quite right. | |
2999 | Please report any inaccuracies you find to GDB's maintainer. | |
3000 | ||
3001 | If you add entries to this table, please be sure to allow the new | |
3002 | value as an argument to the --with-cpu flag, in configure.in. */ | |
3003 | ||
489461e2 | 3004 | static struct variant variants[] = |
c906108c | 3005 | { |
489461e2 | 3006 | |
7a78ae4e | 3007 | {"powerpc", "PowerPC user-level", bfd_arch_powerpc, |
489461e2 EZ |
3008 | bfd_mach_ppc, -1, -1, tot_num_registers (registers_powerpc), |
3009 | registers_powerpc}, | |
7a78ae4e | 3010 | {"power", "POWER user-level", bfd_arch_rs6000, |
489461e2 EZ |
3011 | bfd_mach_rs6k, -1, -1, tot_num_registers (registers_power), |
3012 | registers_power}, | |
7a78ae4e | 3013 | {"403", "IBM PowerPC 403", bfd_arch_powerpc, |
489461e2 EZ |
3014 | bfd_mach_ppc_403, -1, -1, tot_num_registers (registers_403), |
3015 | registers_403}, | |
7a78ae4e | 3016 | {"601", "Motorola PowerPC 601", bfd_arch_powerpc, |
489461e2 EZ |
3017 | bfd_mach_ppc_601, -1, -1, tot_num_registers (registers_601), |
3018 | registers_601}, | |
7a78ae4e | 3019 | {"602", "Motorola PowerPC 602", bfd_arch_powerpc, |
489461e2 EZ |
3020 | bfd_mach_ppc_602, -1, -1, tot_num_registers (registers_602), |
3021 | registers_602}, | |
7a78ae4e | 3022 | {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc, |
489461e2 EZ |
3023 | bfd_mach_ppc_603, -1, -1, tot_num_registers (registers_603), |
3024 | registers_603}, | |
7a78ae4e | 3025 | {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc, |
489461e2 EZ |
3026 | 604, -1, -1, tot_num_registers (registers_604), |
3027 | registers_604}, | |
7a78ae4e | 3028 | {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc, |
489461e2 EZ |
3029 | bfd_mach_ppc_403gc, -1, -1, tot_num_registers (registers_403GC), |
3030 | registers_403GC}, | |
7a78ae4e | 3031 | {"505", "Motorola PowerPC 505", bfd_arch_powerpc, |
489461e2 EZ |
3032 | bfd_mach_ppc_505, -1, -1, tot_num_registers (registers_505), |
3033 | registers_505}, | |
7a78ae4e | 3034 | {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc, |
489461e2 EZ |
3035 | bfd_mach_ppc_860, -1, -1, tot_num_registers (registers_860), |
3036 | registers_860}, | |
7a78ae4e | 3037 | {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc, |
489461e2 EZ |
3038 | bfd_mach_ppc_750, -1, -1, tot_num_registers (registers_750), |
3039 | registers_750}, | |
1fcc0bb8 | 3040 | {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc, |
489461e2 EZ |
3041 | bfd_mach_ppc_7400, -1, -1, tot_num_registers (registers_7400), |
3042 | registers_7400}, | |
c8001721 EZ |
3043 | {"e500", "Motorola PowerPC e500", bfd_arch_powerpc, |
3044 | bfd_mach_ppc_e500, -1, -1, tot_num_registers (registers_e500), | |
3045 | registers_e500}, | |
7a78ae4e | 3046 | |
5d57ee30 KB |
3047 | /* 64-bit */ |
3048 | {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc, | |
489461e2 EZ |
3049 | bfd_mach_ppc64, -1, -1, tot_num_registers (registers_powerpc), |
3050 | registers_powerpc}, | |
7a78ae4e | 3051 | {"620", "Motorola PowerPC 620", bfd_arch_powerpc, |
489461e2 EZ |
3052 | bfd_mach_ppc_620, -1, -1, tot_num_registers (registers_powerpc), |
3053 | registers_powerpc}, | |
5d57ee30 | 3054 | {"630", "Motorola PowerPC 630", bfd_arch_powerpc, |
489461e2 EZ |
3055 | bfd_mach_ppc_630, -1, -1, tot_num_registers (registers_powerpc), |
3056 | registers_powerpc}, | |
7a78ae4e | 3057 | {"a35", "PowerPC A35", bfd_arch_powerpc, |
489461e2 EZ |
3058 | bfd_mach_ppc_a35, -1, -1, tot_num_registers (registers_powerpc), |
3059 | registers_powerpc}, | |
5d57ee30 | 3060 | {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc, |
489461e2 EZ |
3061 | bfd_mach_ppc_rs64ii, -1, -1, tot_num_registers (registers_powerpc), |
3062 | registers_powerpc}, | |
5d57ee30 | 3063 | {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc, |
489461e2 EZ |
3064 | bfd_mach_ppc_rs64iii, -1, -1, tot_num_registers (registers_powerpc), |
3065 | registers_powerpc}, | |
5d57ee30 | 3066 | |
64366f1c | 3067 | /* FIXME: I haven't checked the register sets of the following. */ |
7a78ae4e | 3068 | {"rs1", "IBM POWER RS1", bfd_arch_rs6000, |
489461e2 EZ |
3069 | bfd_mach_rs6k_rs1, -1, -1, tot_num_registers (registers_power), |
3070 | registers_power}, | |
7a78ae4e | 3071 | {"rsc", "IBM POWER RSC", bfd_arch_rs6000, |
489461e2 EZ |
3072 | bfd_mach_rs6k_rsc, -1, -1, tot_num_registers (registers_power), |
3073 | registers_power}, | |
7a78ae4e | 3074 | {"rs2", "IBM POWER RS2", bfd_arch_rs6000, |
489461e2 EZ |
3075 | bfd_mach_rs6k_rs2, -1, -1, tot_num_registers (registers_power), |
3076 | registers_power}, | |
7a78ae4e | 3077 | |
489461e2 | 3078 | {0, 0, 0, 0, 0, 0, 0, 0} |
c906108c SS |
3079 | }; |
3080 | ||
64366f1c | 3081 | /* Initialize the number of registers and pseudo registers in each variant. */ |
489461e2 EZ |
3082 | |
3083 | static void | |
3084 | init_variants (void) | |
3085 | { | |
3086 | struct variant *v; | |
3087 | ||
3088 | for (v = variants; v->name; v++) | |
3089 | { | |
3090 | if (v->nregs == -1) | |
3091 | v->nregs = num_registers (v->regs, v->num_tot_regs); | |
3092 | if (v->npregs == -1) | |
3093 | v->npregs = num_pseudo_registers (v->regs, v->num_tot_regs); | |
3094 | } | |
3095 | } | |
c906108c | 3096 | |
7a78ae4e | 3097 | /* Return the variant corresponding to architecture ARCH and machine number |
64366f1c | 3098 | MACH. If no such variant exists, return null. */ |
c906108c | 3099 | |
7a78ae4e ND |
3100 | static const struct variant * |
3101 | find_variant_by_arch (enum bfd_architecture arch, unsigned long mach) | |
c906108c | 3102 | { |
7a78ae4e | 3103 | const struct variant *v; |
c5aa993b | 3104 | |
7a78ae4e ND |
3105 | for (v = variants; v->name; v++) |
3106 | if (arch == v->arch && mach == v->mach) | |
3107 | return v; | |
c906108c | 3108 | |
7a78ae4e | 3109 | return NULL; |
c906108c | 3110 | } |
9364a0ef EZ |
3111 | |
3112 | static int | |
3113 | gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info) | |
3114 | { | |
ee4f0f76 DJ |
3115 | if (!info->disassembler_options) |
3116 | info->disassembler_options = "any"; | |
3117 | ||
4c6b5505 | 3118 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
9364a0ef EZ |
3119 | return print_insn_big_powerpc (memaddr, info); |
3120 | else | |
3121 | return print_insn_little_powerpc (memaddr, info); | |
3122 | } | |
7a78ae4e | 3123 | \f |
61a65099 KB |
3124 | static CORE_ADDR |
3125 | rs6000_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
3126 | { | |
3e8c568d UW |
3127 | return frame_unwind_register_unsigned (next_frame, |
3128 | gdbarch_pc_regnum (current_gdbarch)); | |
61a65099 KB |
3129 | } |
3130 | ||
3131 | static struct frame_id | |
3132 | rs6000_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
3133 | { | |
3e8c568d UW |
3134 | return frame_id_build (frame_unwind_register_unsigned |
3135 | (next_frame, gdbarch_sp_regnum (current_gdbarch)), | |
3136 | frame_pc_unwind (next_frame)); | |
61a65099 KB |
3137 | } |
3138 | ||
3139 | struct rs6000_frame_cache | |
3140 | { | |
3141 | CORE_ADDR base; | |
3142 | CORE_ADDR initial_sp; | |
3143 | struct trad_frame_saved_reg *saved_regs; | |
3144 | }; | |
3145 | ||
3146 | static struct rs6000_frame_cache * | |
3147 | rs6000_frame_cache (struct frame_info *next_frame, void **this_cache) | |
3148 | { | |
3149 | struct rs6000_frame_cache *cache; | |
3150 | struct gdbarch *gdbarch = get_frame_arch (next_frame); | |
3151 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3152 | struct rs6000_framedata fdata; | |
3153 | int wordsize = tdep->wordsize; | |
e10b1c4c | 3154 | CORE_ADDR func, pc; |
61a65099 KB |
3155 | |
3156 | if ((*this_cache) != NULL) | |
3157 | return (*this_cache); | |
3158 | cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache); | |
3159 | (*this_cache) = cache; | |
3160 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
3161 | ||
93d42b30 | 3162 | func = frame_func_unwind (next_frame, NORMAL_FRAME); |
e10b1c4c DJ |
3163 | pc = frame_pc_unwind (next_frame); |
3164 | skip_prologue (func, pc, &fdata); | |
3165 | ||
3166 | /* Figure out the parent's stack pointer. */ | |
3167 | ||
3168 | /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most | |
3169 | address of the current frame. Things might be easier if the | |
3170 | ->frame pointed to the outer-most address of the frame. In | |
3171 | the mean time, the address of the prev frame is used as the | |
3172 | base address of this frame. */ | |
3e8c568d UW |
3173 | cache->base = frame_unwind_register_unsigned |
3174 | (next_frame, gdbarch_sp_regnum (current_gdbarch)); | |
e10b1c4c DJ |
3175 | |
3176 | /* If the function appears to be frameless, check a couple of likely | |
3177 | indicators that we have simply failed to find the frame setup. | |
3178 | Two common cases of this are missing symbols (i.e. | |
3179 | frame_func_unwind returns the wrong address or 0), and assembly | |
3180 | stubs which have a fast exit path but set up a frame on the slow | |
3181 | path. | |
3182 | ||
3183 | If the LR appears to return to this function, then presume that | |
3184 | we have an ABI compliant frame that we failed to find. */ | |
3185 | if (fdata.frameless && fdata.lr_offset == 0) | |
61a65099 | 3186 | { |
e10b1c4c DJ |
3187 | CORE_ADDR saved_lr; |
3188 | int make_frame = 0; | |
3189 | ||
3190 | saved_lr = frame_unwind_register_unsigned (next_frame, | |
3191 | tdep->ppc_lr_regnum); | |
3192 | if (func == 0 && saved_lr == pc) | |
3193 | make_frame = 1; | |
3194 | else if (func != 0) | |
3195 | { | |
3196 | CORE_ADDR saved_func = get_pc_function_start (saved_lr); | |
3197 | if (func == saved_func) | |
3198 | make_frame = 1; | |
3199 | } | |
3200 | ||
3201 | if (make_frame) | |
3202 | { | |
3203 | fdata.frameless = 0; | |
de6a76fd | 3204 | fdata.lr_offset = tdep->lr_frame_offset; |
e10b1c4c | 3205 | } |
61a65099 | 3206 | } |
e10b1c4c DJ |
3207 | |
3208 | if (!fdata.frameless) | |
3209 | /* Frameless really means stackless. */ | |
3210 | cache->base = read_memory_addr (cache->base, wordsize); | |
3211 | ||
3e8c568d UW |
3212 | trad_frame_set_value (cache->saved_regs, |
3213 | gdbarch_sp_regnum (current_gdbarch), cache->base); | |
61a65099 KB |
3214 | |
3215 | /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr. | |
3216 | All fpr's from saved_fpr to fp31 are saved. */ | |
3217 | ||
3218 | if (fdata.saved_fpr >= 0) | |
3219 | { | |
3220 | int i; | |
3221 | CORE_ADDR fpr_addr = cache->base + fdata.fpr_offset; | |
383f0f5b JB |
3222 | |
3223 | /* If skip_prologue says floating-point registers were saved, | |
3224 | but the current architecture has no floating-point registers, | |
3225 | then that's strange. But we have no indices to even record | |
3226 | the addresses under, so we just ignore it. */ | |
3227 | if (ppc_floating_point_unit_p (gdbarch)) | |
063715bf | 3228 | for (i = fdata.saved_fpr; i < ppc_num_fprs; i++) |
383f0f5b JB |
3229 | { |
3230 | cache->saved_regs[tdep->ppc_fp0_regnum + i].addr = fpr_addr; | |
3231 | fpr_addr += 8; | |
3232 | } | |
61a65099 KB |
3233 | } |
3234 | ||
3235 | /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr. | |
3236 | All gpr's from saved_gpr to gpr31 are saved. */ | |
3237 | ||
3238 | if (fdata.saved_gpr >= 0) | |
3239 | { | |
3240 | int i; | |
3241 | CORE_ADDR gpr_addr = cache->base + fdata.gpr_offset; | |
063715bf | 3242 | for (i = fdata.saved_gpr; i < ppc_num_gprs; i++) |
61a65099 KB |
3243 | { |
3244 | cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = gpr_addr; | |
3245 | gpr_addr += wordsize; | |
3246 | } | |
3247 | } | |
3248 | ||
3249 | /* if != -1, fdata.saved_vr is the smallest number of saved_vr. | |
3250 | All vr's from saved_vr to vr31 are saved. */ | |
3251 | if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) | |
3252 | { | |
3253 | if (fdata.saved_vr >= 0) | |
3254 | { | |
3255 | int i; | |
3256 | CORE_ADDR vr_addr = cache->base + fdata.vr_offset; | |
3257 | for (i = fdata.saved_vr; i < 32; i++) | |
3258 | { | |
3259 | cache->saved_regs[tdep->ppc_vr0_regnum + i].addr = vr_addr; | |
3260 | vr_addr += register_size (gdbarch, tdep->ppc_vr0_regnum); | |
3261 | } | |
3262 | } | |
3263 | } | |
3264 | ||
3265 | /* if != -1, fdata.saved_ev is the smallest number of saved_ev. | |
3266 | All vr's from saved_ev to ev31 are saved. ????? */ | |
3267 | if (tdep->ppc_ev0_regnum != -1 && tdep->ppc_ev31_regnum != -1) | |
3268 | { | |
3269 | if (fdata.saved_ev >= 0) | |
3270 | { | |
3271 | int i; | |
3272 | CORE_ADDR ev_addr = cache->base + fdata.ev_offset; | |
063715bf | 3273 | for (i = fdata.saved_ev; i < ppc_num_gprs; i++) |
61a65099 KB |
3274 | { |
3275 | cache->saved_regs[tdep->ppc_ev0_regnum + i].addr = ev_addr; | |
3276 | cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + 4; | |
3277 | ev_addr += register_size (gdbarch, tdep->ppc_ev0_regnum); | |
3278 | } | |
3279 | } | |
3280 | } | |
3281 | ||
3282 | /* If != 0, fdata.cr_offset is the offset from the frame that | |
3283 | holds the CR. */ | |
3284 | if (fdata.cr_offset != 0) | |
3285 | cache->saved_regs[tdep->ppc_cr_regnum].addr = cache->base + fdata.cr_offset; | |
3286 | ||
3287 | /* If != 0, fdata.lr_offset is the offset from the frame that | |
3288 | holds the LR. */ | |
3289 | if (fdata.lr_offset != 0) | |
3290 | cache->saved_regs[tdep->ppc_lr_regnum].addr = cache->base + fdata.lr_offset; | |
3291 | /* The PC is found in the link register. */ | |
3e8c568d UW |
3292 | cache->saved_regs[gdbarch_pc_regnum (current_gdbarch)] = |
3293 | cache->saved_regs[tdep->ppc_lr_regnum]; | |
61a65099 KB |
3294 | |
3295 | /* If != 0, fdata.vrsave_offset is the offset from the frame that | |
3296 | holds the VRSAVE. */ | |
3297 | if (fdata.vrsave_offset != 0) | |
3298 | cache->saved_regs[tdep->ppc_vrsave_regnum].addr = cache->base + fdata.vrsave_offset; | |
3299 | ||
3300 | if (fdata.alloca_reg < 0) | |
3301 | /* If no alloca register used, then fi->frame is the value of the | |
3302 | %sp for this frame, and it is good enough. */ | |
3e8c568d UW |
3303 | cache->initial_sp = frame_unwind_register_unsigned |
3304 | (next_frame, gdbarch_sp_regnum (current_gdbarch)); | |
61a65099 KB |
3305 | else |
3306 | cache->initial_sp = frame_unwind_register_unsigned (next_frame, | |
3307 | fdata.alloca_reg); | |
3308 | ||
3309 | return cache; | |
3310 | } | |
3311 | ||
3312 | static void | |
3313 | rs6000_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
3314 | struct frame_id *this_id) | |
3315 | { | |
3316 | struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame, | |
3317 | this_cache); | |
93d42b30 DJ |
3318 | (*this_id) = frame_id_build (info->base, |
3319 | frame_func_unwind (next_frame, NORMAL_FRAME)); | |
61a65099 KB |
3320 | } |
3321 | ||
3322 | static void | |
3323 | rs6000_frame_prev_register (struct frame_info *next_frame, | |
3324 | void **this_cache, | |
3325 | int regnum, int *optimizedp, | |
3326 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
50fd1280 | 3327 | int *realnump, gdb_byte *valuep) |
61a65099 KB |
3328 | { |
3329 | struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame, | |
3330 | this_cache); | |
1f67027d AC |
3331 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, |
3332 | optimizedp, lvalp, addrp, realnump, valuep); | |
61a65099 KB |
3333 | } |
3334 | ||
3335 | static const struct frame_unwind rs6000_frame_unwind = | |
3336 | { | |
3337 | NORMAL_FRAME, | |
3338 | rs6000_frame_this_id, | |
3339 | rs6000_frame_prev_register | |
3340 | }; | |
3341 | ||
3342 | static const struct frame_unwind * | |
3343 | rs6000_frame_sniffer (struct frame_info *next_frame) | |
3344 | { | |
3345 | return &rs6000_frame_unwind; | |
3346 | } | |
3347 | ||
3348 | \f | |
3349 | ||
3350 | static CORE_ADDR | |
3351 | rs6000_frame_base_address (struct frame_info *next_frame, | |
3352 | void **this_cache) | |
3353 | { | |
3354 | struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame, | |
3355 | this_cache); | |
3356 | return info->initial_sp; | |
3357 | } | |
3358 | ||
3359 | static const struct frame_base rs6000_frame_base = { | |
3360 | &rs6000_frame_unwind, | |
3361 | rs6000_frame_base_address, | |
3362 | rs6000_frame_base_address, | |
3363 | rs6000_frame_base_address | |
3364 | }; | |
3365 | ||
3366 | static const struct frame_base * | |
3367 | rs6000_frame_base_sniffer (struct frame_info *next_frame) | |
3368 | { | |
3369 | return &rs6000_frame_base; | |
3370 | } | |
3371 | ||
7a78ae4e ND |
3372 | /* Initialize the current architecture based on INFO. If possible, re-use an |
3373 | architecture from ARCHES, which is a list of architectures already created | |
3374 | during this debugging session. | |
c906108c | 3375 | |
7a78ae4e | 3376 | Called e.g. at program startup, when reading a core file, and when reading |
64366f1c | 3377 | a binary file. */ |
c906108c | 3378 | |
7a78ae4e ND |
3379 | static struct gdbarch * |
3380 | rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
3381 | { | |
3382 | struct gdbarch *gdbarch; | |
3383 | struct gdbarch_tdep *tdep; | |
708ff411 | 3384 | int wordsize, from_xcoff_exec, from_elf_exec, i, off; |
7a78ae4e ND |
3385 | struct reg *regs; |
3386 | const struct variant *v; | |
3387 | enum bfd_architecture arch; | |
3388 | unsigned long mach; | |
3389 | bfd abfd; | |
7b112f9c | 3390 | int sysv_abi; |
5bf1c677 | 3391 | asection *sect; |
7a78ae4e | 3392 | |
9aa1e687 | 3393 | from_xcoff_exec = info.abfd && info.abfd->format == bfd_object && |
7a78ae4e ND |
3394 | bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour; |
3395 | ||
9aa1e687 KB |
3396 | from_elf_exec = info.abfd && info.abfd->format == bfd_object && |
3397 | bfd_get_flavour (info.abfd) == bfd_target_elf_flavour; | |
3398 | ||
3399 | sysv_abi = info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour; | |
3400 | ||
e712c1cf | 3401 | /* Check word size. If INFO is from a binary file, infer it from |
64366f1c | 3402 | that, else choose a likely default. */ |
9aa1e687 | 3403 | if (from_xcoff_exec) |
c906108c | 3404 | { |
11ed25ac | 3405 | if (bfd_xcoff_is_xcoff64 (info.abfd)) |
7a78ae4e ND |
3406 | wordsize = 8; |
3407 | else | |
3408 | wordsize = 4; | |
c906108c | 3409 | } |
9aa1e687 KB |
3410 | else if (from_elf_exec) |
3411 | { | |
3412 | if (elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
3413 | wordsize = 8; | |
3414 | else | |
3415 | wordsize = 4; | |
3416 | } | |
c906108c | 3417 | else |
7a78ae4e | 3418 | { |
27b15785 KB |
3419 | if (info.bfd_arch_info != NULL && info.bfd_arch_info->bits_per_word != 0) |
3420 | wordsize = info.bfd_arch_info->bits_per_word / | |
3421 | info.bfd_arch_info->bits_per_byte; | |
3422 | else | |
3423 | wordsize = 4; | |
7a78ae4e | 3424 | } |
c906108c | 3425 | |
13c0b536 | 3426 | /* Find a candidate among extant architectures. */ |
7a78ae4e ND |
3427 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
3428 | arches != NULL; | |
3429 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
3430 | { | |
3431 | /* Word size in the various PowerPC bfd_arch_info structs isn't | |
3432 | meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform | |
64366f1c | 3433 | separate word size check. */ |
7a78ae4e | 3434 | tdep = gdbarch_tdep (arches->gdbarch); |
4be87837 | 3435 | if (tdep && tdep->wordsize == wordsize) |
7a78ae4e ND |
3436 | return arches->gdbarch; |
3437 | } | |
c906108c | 3438 | |
7a78ae4e ND |
3439 | /* None found, create a new architecture from INFO, whose bfd_arch_info |
3440 | validity depends on the source: | |
3441 | - executable useless | |
3442 | - rs6000_host_arch() good | |
3443 | - core file good | |
3444 | - "set arch" trust blindly | |
3445 | - GDB startup useless but harmless */ | |
c906108c | 3446 | |
9aa1e687 | 3447 | if (!from_xcoff_exec) |
c906108c | 3448 | { |
b732d07d | 3449 | arch = info.bfd_arch_info->arch; |
7a78ae4e | 3450 | mach = info.bfd_arch_info->mach; |
c906108c | 3451 | } |
7a78ae4e | 3452 | else |
c906108c | 3453 | { |
7a78ae4e | 3454 | arch = bfd_arch_powerpc; |
35cec841 | 3455 | bfd_default_set_arch_mach (&abfd, arch, 0); |
7a78ae4e | 3456 | info.bfd_arch_info = bfd_get_arch_info (&abfd); |
35cec841 | 3457 | mach = info.bfd_arch_info->mach; |
7a78ae4e | 3458 | } |
794ac428 | 3459 | tdep = XCALLOC (1, struct gdbarch_tdep); |
7a78ae4e | 3460 | tdep->wordsize = wordsize; |
5bf1c677 EZ |
3461 | |
3462 | /* For e500 executables, the apuinfo section is of help here. Such | |
3463 | section contains the identifier and revision number of each | |
3464 | Application-specific Processing Unit that is present on the | |
3465 | chip. The content of the section is determined by the assembler | |
3466 | which looks at each instruction and determines which unit (and | |
3467 | which version of it) can execute it. In our case we just look for | |
3468 | the existance of the section. */ | |
3469 | ||
3470 | if (info.abfd) | |
3471 | { | |
3472 | sect = bfd_get_section_by_name (info.abfd, ".PPC.EMB.apuinfo"); | |
3473 | if (sect) | |
3474 | { | |
3475 | arch = info.bfd_arch_info->arch; | |
3476 | mach = bfd_mach_ppc_e500; | |
3477 | bfd_default_set_arch_mach (&abfd, arch, mach); | |
3478 | info.bfd_arch_info = bfd_get_arch_info (&abfd); | |
3479 | } | |
3480 | } | |
3481 | ||
7a78ae4e | 3482 | gdbarch = gdbarch_alloc (&info, tdep); |
7a78ae4e | 3483 | |
489461e2 EZ |
3484 | /* Initialize the number of real and pseudo registers in each variant. */ |
3485 | init_variants (); | |
3486 | ||
64366f1c | 3487 | /* Choose variant. */ |
7a78ae4e ND |
3488 | v = find_variant_by_arch (arch, mach); |
3489 | if (!v) | |
dd47e6fd EZ |
3490 | return NULL; |
3491 | ||
7a78ae4e ND |
3492 | tdep->regs = v->regs; |
3493 | ||
2188cbdd | 3494 | tdep->ppc_gp0_regnum = 0; |
2188cbdd EZ |
3495 | tdep->ppc_toc_regnum = 2; |
3496 | tdep->ppc_ps_regnum = 65; | |
3497 | tdep->ppc_cr_regnum = 66; | |
3498 | tdep->ppc_lr_regnum = 67; | |
3499 | tdep->ppc_ctr_regnum = 68; | |
3500 | tdep->ppc_xer_regnum = 69; | |
3501 | if (v->mach == bfd_mach_ppc_601) | |
3502 | tdep->ppc_mq_regnum = 124; | |
708ff411 | 3503 | else if (arch == bfd_arch_rs6000) |
2188cbdd | 3504 | tdep->ppc_mq_regnum = 70; |
e3f36dbd KB |
3505 | else |
3506 | tdep->ppc_mq_regnum = -1; | |
366f009f | 3507 | tdep->ppc_fp0_regnum = 32; |
708ff411 | 3508 | tdep->ppc_fpscr_regnum = (arch == bfd_arch_rs6000) ? 71 : 70; |
f86a7158 | 3509 | tdep->ppc_sr0_regnum = 71; |
baffbae0 JB |
3510 | tdep->ppc_vr0_regnum = -1; |
3511 | tdep->ppc_vrsave_regnum = -1; | |
6ced10dd | 3512 | tdep->ppc_ev0_upper_regnum = -1; |
baffbae0 JB |
3513 | tdep->ppc_ev0_regnum = -1; |
3514 | tdep->ppc_ev31_regnum = -1; | |
867e2dc5 JB |
3515 | tdep->ppc_acc_regnum = -1; |
3516 | tdep->ppc_spefscr_regnum = -1; | |
2188cbdd | 3517 | |
c8001721 EZ |
3518 | set_gdbarch_pc_regnum (gdbarch, 64); |
3519 | set_gdbarch_sp_regnum (gdbarch, 1); | |
0ba6dca9 | 3520 | set_gdbarch_deprecated_fp_regnum (gdbarch, 1); |
6f7f3f0d | 3521 | set_gdbarch_fp0_regnum (gdbarch, 32); |
9f643768 | 3522 | set_gdbarch_register_sim_regno (gdbarch, rs6000_register_sim_regno); |
afd48b75 | 3523 | if (sysv_abi && wordsize == 8) |
05580c65 | 3524 | set_gdbarch_return_value (gdbarch, ppc64_sysv_abi_return_value); |
e754ae69 | 3525 | else if (sysv_abi && wordsize == 4) |
05580c65 | 3526 | set_gdbarch_return_value (gdbarch, ppc_sysv_abi_return_value); |
afd48b75 | 3527 | else |
d217aaed | 3528 | set_gdbarch_return_value (gdbarch, rs6000_return_value); |
c8001721 | 3529 | |
baffbae0 JB |
3530 | /* Set lr_frame_offset. */ |
3531 | if (wordsize == 8) | |
3532 | tdep->lr_frame_offset = 16; | |
3533 | else if (sysv_abi) | |
3534 | tdep->lr_frame_offset = 4; | |
3535 | else | |
3536 | tdep->lr_frame_offset = 8; | |
3537 | ||
f86a7158 JB |
3538 | if (v->arch == bfd_arch_rs6000) |
3539 | tdep->ppc_sr0_regnum = -1; | |
3540 | else if (v->arch == bfd_arch_powerpc) | |
1fcc0bb8 EZ |
3541 | switch (v->mach) |
3542 | { | |
3543 | case bfd_mach_ppc: | |
412b3060 | 3544 | tdep->ppc_sr0_regnum = -1; |
1fcc0bb8 EZ |
3545 | tdep->ppc_vr0_regnum = 71; |
3546 | tdep->ppc_vrsave_regnum = 104; | |
3547 | break; | |
3548 | case bfd_mach_ppc_7400: | |
3549 | tdep->ppc_vr0_regnum = 119; | |
54c2a1e6 | 3550 | tdep->ppc_vrsave_regnum = 152; |
c8001721 EZ |
3551 | break; |
3552 | case bfd_mach_ppc_e500: | |
c8001721 | 3553 | tdep->ppc_toc_regnum = -1; |
6ced10dd JB |
3554 | tdep->ppc_ev0_upper_regnum = 32; |
3555 | tdep->ppc_ev0_regnum = 73; | |
3556 | tdep->ppc_ev31_regnum = 104; | |
3557 | tdep->ppc_acc_regnum = 71; | |
3558 | tdep->ppc_spefscr_regnum = 72; | |
383f0f5b JB |
3559 | tdep->ppc_fp0_regnum = -1; |
3560 | tdep->ppc_fpscr_regnum = -1; | |
f86a7158 | 3561 | tdep->ppc_sr0_regnum = -1; |
c8001721 EZ |
3562 | set_gdbarch_pseudo_register_read (gdbarch, e500_pseudo_register_read); |
3563 | set_gdbarch_pseudo_register_write (gdbarch, e500_pseudo_register_write); | |
6ced10dd | 3564 | set_gdbarch_register_reggroup_p (gdbarch, e500_register_reggroup_p); |
1fcc0bb8 | 3565 | break; |
f86a7158 JB |
3566 | |
3567 | case bfd_mach_ppc64: | |
3568 | case bfd_mach_ppc_620: | |
3569 | case bfd_mach_ppc_630: | |
3570 | case bfd_mach_ppc_a35: | |
3571 | case bfd_mach_ppc_rs64ii: | |
3572 | case bfd_mach_ppc_rs64iii: | |
3573 | /* These processor's register sets don't have segment registers. */ | |
3574 | tdep->ppc_sr0_regnum = -1; | |
3575 | break; | |
1fcc0bb8 | 3576 | } |
f86a7158 JB |
3577 | else |
3578 | internal_error (__FILE__, __LINE__, | |
e2e0b3e5 AC |
3579 | _("rs6000_gdbarch_init: " |
3580 | "received unexpected BFD 'arch' value")); | |
1fcc0bb8 | 3581 | |
e0d24f8d WZ |
3582 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); |
3583 | ||
338ef23d AC |
3584 | /* Sanity check on registers. */ |
3585 | gdb_assert (strcmp (tdep->regs[tdep->ppc_gp0_regnum].name, "r0") == 0); | |
3586 | ||
56a6dfb9 | 3587 | /* Select instruction printer. */ |
708ff411 | 3588 | if (arch == bfd_arch_rs6000) |
9364a0ef | 3589 | set_gdbarch_print_insn (gdbarch, print_insn_rs6000); |
56a6dfb9 | 3590 | else |
9364a0ef | 3591 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_powerpc); |
7495d1dc | 3592 | |
7a78ae4e | 3593 | set_gdbarch_num_regs (gdbarch, v->nregs); |
c8001721 | 3594 | set_gdbarch_num_pseudo_regs (gdbarch, v->npregs); |
7a78ae4e | 3595 | set_gdbarch_register_name (gdbarch, rs6000_register_name); |
691d145a | 3596 | set_gdbarch_register_type (gdbarch, rs6000_register_type); |
c44ca51c | 3597 | set_gdbarch_register_reggroup_p (gdbarch, rs6000_register_reggroup_p); |
7a78ae4e ND |
3598 | |
3599 | set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT); | |
3600 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); | |
3601 | set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
3602 | set_gdbarch_long_bit (gdbarch, wordsize * TARGET_CHAR_BIT); | |
3603 | set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
3604 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
3605 | set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
ab9fe00e KB |
3606 | if (sysv_abi) |
3607 | set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT); | |
3608 | else | |
3609 | set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
4e409299 | 3610 | set_gdbarch_char_signed (gdbarch, 0); |
7a78ae4e | 3611 | |
11269d7e | 3612 | set_gdbarch_frame_align (gdbarch, rs6000_frame_align); |
8b148df9 AC |
3613 | if (sysv_abi && wordsize == 8) |
3614 | /* PPC64 SYSV. */ | |
3615 | set_gdbarch_frame_red_zone_size (gdbarch, 288); | |
3616 | else if (!sysv_abi && wordsize == 4) | |
5bffac25 AC |
3617 | /* PowerOpen / AIX 32 bit. The saved area or red zone consists of |
3618 | 19 4 byte GPRS + 18 8 byte FPRs giving a total of 220 bytes. | |
3619 | Problem is, 220 isn't frame (16 byte) aligned. Round it up to | |
3620 | 224. */ | |
3621 | set_gdbarch_frame_red_zone_size (gdbarch, 224); | |
7a78ae4e | 3622 | |
691d145a JB |
3623 | set_gdbarch_convert_register_p (gdbarch, rs6000_convert_register_p); |
3624 | set_gdbarch_register_to_value (gdbarch, rs6000_register_to_value); | |
3625 | set_gdbarch_value_to_register (gdbarch, rs6000_value_to_register); | |
3626 | ||
18ed0c4e JB |
3627 | set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_stab_reg_to_regnum); |
3628 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rs6000_dwarf2_reg_to_regnum); | |
d217aaed | 3629 | |
2ea5f656 | 3630 | if (sysv_abi && wordsize == 4) |
77b2b6d4 | 3631 | set_gdbarch_push_dummy_call (gdbarch, ppc_sysv_abi_push_dummy_call); |
8be9034a AC |
3632 | else if (sysv_abi && wordsize == 8) |
3633 | set_gdbarch_push_dummy_call (gdbarch, ppc64_sysv_abi_push_dummy_call); | |
9aa1e687 | 3634 | else |
77b2b6d4 | 3635 | set_gdbarch_push_dummy_call (gdbarch, rs6000_push_dummy_call); |
7a78ae4e | 3636 | |
7a78ae4e | 3637 | set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue); |
0d1243d9 PG |
3638 | set_gdbarch_in_function_epilogue_p (gdbarch, rs6000_in_function_epilogue_p); |
3639 | ||
7a78ae4e | 3640 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
7a78ae4e ND |
3641 | set_gdbarch_breakpoint_from_pc (gdbarch, rs6000_breakpoint_from_pc); |
3642 | ||
ce5eab59 UW |
3643 | /* Handles single stepping of atomic sequences. */ |
3644 | set_gdbarch_software_single_step (gdbarch, deal_with_atomic_sequence); | |
3645 | ||
6066c3de AC |
3646 | /* Handle the 64-bit SVR4 minimal-symbol convention of using "FN" |
3647 | for the descriptor and ".FN" for the entry-point -- a user | |
3648 | specifying "break FN" will unexpectedly end up with a breakpoint | |
3649 | on the descriptor and not the function. This architecture method | |
3650 | transforms any breakpoints on descriptors into breakpoints on the | |
3651 | corresponding entry point. */ | |
3652 | if (sysv_abi && wordsize == 8) | |
3653 | set_gdbarch_adjust_breakpoint_address (gdbarch, ppc64_sysv_abi_adjust_breakpoint_address); | |
3654 | ||
7a78ae4e ND |
3655 | /* Not sure on this. FIXMEmgo */ |
3656 | set_gdbarch_frame_args_skip (gdbarch, 8); | |
3657 | ||
15813d3f AC |
3658 | if (!sysv_abi) |
3659 | { | |
3660 | /* Handle RS/6000 function pointers (which are really function | |
3661 | descriptors). */ | |
f517ea4e PS |
3662 | set_gdbarch_convert_from_func_ptr_addr (gdbarch, |
3663 | rs6000_convert_from_func_ptr_addr); | |
9aa1e687 | 3664 | } |
7a78ae4e | 3665 | |
143985b7 AF |
3666 | /* Helpers for function argument information. */ |
3667 | set_gdbarch_fetch_pointer_argument (gdbarch, rs6000_fetch_pointer_argument); | |
3668 | ||
6f7f3f0d UW |
3669 | /* Trampoline. */ |
3670 | set_gdbarch_in_solib_return_trampoline | |
3671 | (gdbarch, rs6000_in_solib_return_trampoline); | |
3672 | set_gdbarch_skip_trampoline_code (gdbarch, rs6000_skip_trampoline_code); | |
3673 | ||
4fc771b8 DJ |
3674 | /* Hook in the DWARF CFI frame unwinder. */ |
3675 | frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer); | |
3676 | dwarf2_frame_set_adjust_regnum (gdbarch, rs6000_adjust_frame_regnum); | |
3677 | ||
7b112f9c | 3678 | /* Hook in ABI-specific overrides, if they have been registered. */ |
4be87837 | 3679 | gdbarch_init_osabi (info, gdbarch); |
7b112f9c | 3680 | |
61a65099 KB |
3681 | switch (info.osabi) |
3682 | { | |
f5aecab8 PG |
3683 | case GDB_OSABI_LINUX: |
3684 | /* FIXME: pgilliam/2005-10-21: Assume all PowerPC 64-bit linux systems | |
3685 | have altivec registers. If not, ptrace will fail the first time it's | |
3686 | called to access one and will not be called again. This wart will | |
3687 | be removed when Daniel Jacobowitz's proposal for autodetecting target | |
3688 | registers is implemented. */ | |
3689 | if ((v->arch == bfd_arch_powerpc) && ((v->mach)== bfd_mach_ppc64)) | |
3690 | { | |
3691 | tdep->ppc_vr0_regnum = 71; | |
3692 | tdep->ppc_vrsave_regnum = 104; | |
3693 | } | |
3694 | /* Fall Thru */ | |
61a65099 KB |
3695 | case GDB_OSABI_NETBSD_AOUT: |
3696 | case GDB_OSABI_NETBSD_ELF: | |
3697 | case GDB_OSABI_UNKNOWN: | |
61a65099 KB |
3698 | set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc); |
3699 | frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer); | |
3700 | set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id); | |
3701 | frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer); | |
3702 | break; | |
3703 | default: | |
61a65099 | 3704 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); |
81332287 KB |
3705 | |
3706 | set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc); | |
3707 | frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer); | |
3708 | set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id); | |
3709 | frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer); | |
61a65099 KB |
3710 | } |
3711 | ||
9f643768 JB |
3712 | init_sim_regno_table (gdbarch); |
3713 | ||
7a78ae4e | 3714 | return gdbarch; |
c906108c SS |
3715 | } |
3716 | ||
7b112f9c JT |
3717 | static void |
3718 | rs6000_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
3719 | { | |
3720 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3721 | ||
3722 | if (tdep == NULL) | |
3723 | return; | |
3724 | ||
4be87837 | 3725 | /* FIXME: Dump gdbarch_tdep. */ |
7b112f9c JT |
3726 | } |
3727 | ||
c906108c SS |
3728 | /* Initialization code. */ |
3729 | ||
a78f21af | 3730 | extern initialize_file_ftype _initialize_rs6000_tdep; /* -Wmissing-prototypes */ |
b9362cc7 | 3731 | |
c906108c | 3732 | void |
fba45db2 | 3733 | _initialize_rs6000_tdep (void) |
c906108c | 3734 | { |
7b112f9c JT |
3735 | gdbarch_register (bfd_arch_rs6000, rs6000_gdbarch_init, rs6000_dump_tdep); |
3736 | gdbarch_register (bfd_arch_powerpc, rs6000_gdbarch_init, rs6000_dump_tdep); | |
c906108c | 3737 | } |