Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for GDB, the GNU debugger. |
7aea86e6 | 2 | |
ecd75fc8 | 3 | Copyright (C) 1986-2014 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 10 | (at your option) any later version. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b | 17 | You should have received a copy of the GNU General Public License |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
19 | |
20 | #include "defs.h" | |
21 | #include "frame.h" | |
22 | #include "inferior.h" | |
45741a9c | 23 | #include "infrun.h" |
c906108c SS |
24 | #include "symtab.h" |
25 | #include "target.h" | |
26 | #include "gdbcore.h" | |
27 | #include "gdbcmd.h" | |
c906108c | 28 | #include "objfiles.h" |
7a78ae4e | 29 | #include "arch-utils.h" |
4e052eda | 30 | #include "regcache.h" |
d195bc9f | 31 | #include "regset.h" |
d16aafd8 | 32 | #include "doublest.h" |
fd0407d6 | 33 | #include "value.h" |
1fcc0bb8 | 34 | #include "parser-defs.h" |
4be87837 | 35 | #include "osabi.h" |
7d9b040b | 36 | #include "infcall.h" |
9f643768 JB |
37 | #include "sim-regno.h" |
38 | #include "gdb/sim-ppc.h" | |
6ced10dd | 39 | #include "reggroups.h" |
4fc771b8 | 40 | #include "dwarf2-frame.h" |
7cc46491 DJ |
41 | #include "target-descriptions.h" |
42 | #include "user-regs.h" | |
7a78ae4e | 43 | |
2fccf04a | 44 | #include "libbfd.h" /* for bfd_default_set_arch_mach */ |
7a78ae4e | 45 | #include "coff/internal.h" /* for libcoff.h */ |
2fccf04a | 46 | #include "libcoff.h" /* for xcoff_data */ |
11ed25ac KB |
47 | #include "coff/xcoff.h" |
48 | #include "libxcoff.h" | |
7a78ae4e | 49 | |
9aa1e687 | 50 | #include "elf-bfd.h" |
55eddb0f | 51 | #include "elf/ppc.h" |
cd453cd0 | 52 | #include "elf/ppc64.h" |
7a78ae4e | 53 | |
6ded7999 | 54 | #include "solib-svr4.h" |
9aa1e687 | 55 | #include "ppc-tdep.h" |
debb1f09 | 56 | #include "ppc-ravenscar-thread.h" |
7a78ae4e | 57 | |
338ef23d | 58 | #include "gdb_assert.h" |
a89aa300 | 59 | #include "dis-asm.h" |
338ef23d | 60 | |
61a65099 KB |
61 | #include "trad-frame.h" |
62 | #include "frame-unwind.h" | |
63 | #include "frame-base.h" | |
64 | ||
7cc46491 | 65 | #include "features/rs6000/powerpc-32.c" |
7284e1be | 66 | #include "features/rs6000/powerpc-altivec32.c" |
604c2f83 | 67 | #include "features/rs6000/powerpc-vsx32.c" |
7cc46491 DJ |
68 | #include "features/rs6000/powerpc-403.c" |
69 | #include "features/rs6000/powerpc-403gc.c" | |
4d09ffea | 70 | #include "features/rs6000/powerpc-405.c" |
7cc46491 DJ |
71 | #include "features/rs6000/powerpc-505.c" |
72 | #include "features/rs6000/powerpc-601.c" | |
73 | #include "features/rs6000/powerpc-602.c" | |
74 | #include "features/rs6000/powerpc-603.c" | |
75 | #include "features/rs6000/powerpc-604.c" | |
76 | #include "features/rs6000/powerpc-64.c" | |
7284e1be | 77 | #include "features/rs6000/powerpc-altivec64.c" |
604c2f83 | 78 | #include "features/rs6000/powerpc-vsx64.c" |
7cc46491 DJ |
79 | #include "features/rs6000/powerpc-7400.c" |
80 | #include "features/rs6000/powerpc-750.c" | |
81 | #include "features/rs6000/powerpc-860.c" | |
82 | #include "features/rs6000/powerpc-e500.c" | |
83 | #include "features/rs6000/rs6000.c" | |
84 | ||
5a9e69ba TJB |
85 | /* Determine if regnum is an SPE pseudo-register. */ |
86 | #define IS_SPE_PSEUDOREG(tdep, regnum) ((tdep)->ppc_ev0_regnum >= 0 \ | |
87 | && (regnum) >= (tdep)->ppc_ev0_regnum \ | |
88 | && (regnum) < (tdep)->ppc_ev0_regnum + 32) | |
89 | ||
f949c649 TJB |
90 | /* Determine if regnum is a decimal float pseudo-register. */ |
91 | #define IS_DFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_dl0_regnum >= 0 \ | |
92 | && (regnum) >= (tdep)->ppc_dl0_regnum \ | |
93 | && (regnum) < (tdep)->ppc_dl0_regnum + 16) | |
94 | ||
604c2f83 LM |
95 | /* Determine if regnum is a POWER7 VSX register. */ |
96 | #define IS_VSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_vsr0_regnum >= 0 \ | |
97 | && (regnum) >= (tdep)->ppc_vsr0_regnum \ | |
98 | && (regnum) < (tdep)->ppc_vsr0_regnum + ppc_num_vsrs) | |
99 | ||
100 | /* Determine if regnum is a POWER7 Extended FP register. */ | |
101 | #define IS_EFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_efpr0_regnum >= 0 \ | |
102 | && (regnum) >= (tdep)->ppc_efpr0_regnum \ | |
d9492458 | 103 | && (regnum) < (tdep)->ppc_efpr0_regnum + ppc_num_efprs) |
604c2f83 | 104 | |
55eddb0f DJ |
105 | /* The list of available "set powerpc ..." and "show powerpc ..." |
106 | commands. */ | |
107 | static struct cmd_list_element *setpowerpccmdlist = NULL; | |
108 | static struct cmd_list_element *showpowerpccmdlist = NULL; | |
109 | ||
110 | static enum auto_boolean powerpc_soft_float_global = AUTO_BOOLEAN_AUTO; | |
111 | ||
112 | /* The vector ABI to use. Keep this in sync with powerpc_vector_abi. */ | |
40478521 | 113 | static const char *const powerpc_vector_strings[] = |
55eddb0f DJ |
114 | { |
115 | "auto", | |
116 | "generic", | |
117 | "altivec", | |
118 | "spe", | |
119 | NULL | |
120 | }; | |
121 | ||
122 | /* A variable that can be configured by the user. */ | |
123 | static enum powerpc_vector_abi powerpc_vector_abi_global = POWERPC_VEC_AUTO; | |
124 | static const char *powerpc_vector_abi_string = "auto"; | |
125 | ||
0df8b418 | 126 | /* To be used by skip_prologue. */ |
7a78ae4e ND |
127 | |
128 | struct rs6000_framedata | |
129 | { | |
130 | int offset; /* total size of frame --- the distance | |
131 | by which we decrement sp to allocate | |
132 | the frame */ | |
133 | int saved_gpr; /* smallest # of saved gpr */ | |
46a9b8ed | 134 | unsigned int gpr_mask; /* Each bit is an individual saved GPR. */ |
7a78ae4e | 135 | int saved_fpr; /* smallest # of saved fpr */ |
6be8bc0c | 136 | int saved_vr; /* smallest # of saved vr */ |
96ff0de4 | 137 | int saved_ev; /* smallest # of saved ev */ |
7a78ae4e | 138 | int alloca_reg; /* alloca register number (frame ptr) */ |
0df8b418 MS |
139 | char frameless; /* true if frameless functions. */ |
140 | char nosavedpc; /* true if pc not saved. */ | |
46a9b8ed | 141 | char used_bl; /* true if link register clobbered */ |
7a78ae4e ND |
142 | int gpr_offset; /* offset of saved gprs from prev sp */ |
143 | int fpr_offset; /* offset of saved fprs from prev sp */ | |
6be8bc0c | 144 | int vr_offset; /* offset of saved vrs from prev sp */ |
96ff0de4 | 145 | int ev_offset; /* offset of saved evs from prev sp */ |
7a78ae4e | 146 | int lr_offset; /* offset of saved lr */ |
46a9b8ed | 147 | int lr_register; /* register of saved lr, if trustworthy */ |
7a78ae4e | 148 | int cr_offset; /* offset of saved cr */ |
6be8bc0c | 149 | int vrsave_offset; /* offset of saved vrsave register */ |
7a78ae4e ND |
150 | }; |
151 | ||
c906108c | 152 | |
604c2f83 LM |
153 | /* Is REGNO a VSX register? Return 1 if so, 0 otherwise. */ |
154 | int | |
155 | vsx_register_p (struct gdbarch *gdbarch, int regno) | |
156 | { | |
157 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
158 | if (tdep->ppc_vsr0_regnum < 0) | |
159 | return 0; | |
160 | else | |
161 | return (regno >= tdep->ppc_vsr0_upper_regnum && regno | |
162 | <= tdep->ppc_vsr0_upper_regnum + 31); | |
163 | } | |
164 | ||
64b84175 KB |
165 | /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */ |
166 | int | |
be8626e0 | 167 | altivec_register_p (struct gdbarch *gdbarch, int regno) |
64b84175 | 168 | { |
be8626e0 | 169 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
64b84175 KB |
170 | if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0) |
171 | return 0; | |
172 | else | |
173 | return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum); | |
174 | } | |
175 | ||
383f0f5b | 176 | |
867e2dc5 JB |
177 | /* Return true if REGNO is an SPE register, false otherwise. */ |
178 | int | |
be8626e0 | 179 | spe_register_p (struct gdbarch *gdbarch, int regno) |
867e2dc5 | 180 | { |
be8626e0 | 181 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
867e2dc5 JB |
182 | |
183 | /* Is it a reference to EV0 -- EV31, and do we have those? */ | |
5a9e69ba | 184 | if (IS_SPE_PSEUDOREG (tdep, regno)) |
867e2dc5 JB |
185 | return 1; |
186 | ||
6ced10dd JB |
187 | /* Is it a reference to one of the raw upper GPR halves? */ |
188 | if (tdep->ppc_ev0_upper_regnum >= 0 | |
189 | && tdep->ppc_ev0_upper_regnum <= regno | |
190 | && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) | |
191 | return 1; | |
192 | ||
867e2dc5 JB |
193 | /* Is it a reference to the 64-bit accumulator, and do we have that? */ |
194 | if (tdep->ppc_acc_regnum >= 0 | |
195 | && tdep->ppc_acc_regnum == regno) | |
196 | return 1; | |
197 | ||
198 | /* Is it a reference to the SPE floating-point status and control register, | |
199 | and do we have that? */ | |
200 | if (tdep->ppc_spefscr_regnum >= 0 | |
201 | && tdep->ppc_spefscr_regnum == regno) | |
202 | return 1; | |
203 | ||
204 | return 0; | |
205 | } | |
206 | ||
207 | ||
383f0f5b JB |
208 | /* Return non-zero if the architecture described by GDBARCH has |
209 | floating-point registers (f0 --- f31 and fpscr). */ | |
0a613259 AC |
210 | int |
211 | ppc_floating_point_unit_p (struct gdbarch *gdbarch) | |
212 | { | |
383f0f5b JB |
213 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
214 | ||
215 | return (tdep->ppc_fp0_regnum >= 0 | |
216 | && tdep->ppc_fpscr_regnum >= 0); | |
0a613259 | 217 | } |
9f643768 | 218 | |
604c2f83 LM |
219 | /* Return non-zero if the architecture described by GDBARCH has |
220 | VSX registers (vsr0 --- vsr63). */ | |
63807e1d | 221 | static int |
604c2f83 LM |
222 | ppc_vsx_support_p (struct gdbarch *gdbarch) |
223 | { | |
224 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
225 | ||
226 | return tdep->ppc_vsr0_regnum >= 0; | |
227 | } | |
228 | ||
06caf7d2 CES |
229 | /* Return non-zero if the architecture described by GDBARCH has |
230 | Altivec registers (vr0 --- vr31, vrsave and vscr). */ | |
231 | int | |
232 | ppc_altivec_support_p (struct gdbarch *gdbarch) | |
233 | { | |
234 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
235 | ||
236 | return (tdep->ppc_vr0_regnum >= 0 | |
237 | && tdep->ppc_vrsave_regnum >= 0); | |
238 | } | |
09991fa0 JB |
239 | |
240 | /* Check that TABLE[GDB_REGNO] is not already initialized, and then | |
241 | set it to SIM_REGNO. | |
242 | ||
243 | This is a helper function for init_sim_regno_table, constructing | |
244 | the table mapping GDB register numbers to sim register numbers; we | |
245 | initialize every element in that table to -1 before we start | |
246 | filling it in. */ | |
9f643768 JB |
247 | static void |
248 | set_sim_regno (int *table, int gdb_regno, int sim_regno) | |
249 | { | |
250 | /* Make sure we don't try to assign any given GDB register a sim | |
251 | register number more than once. */ | |
252 | gdb_assert (table[gdb_regno] == -1); | |
253 | table[gdb_regno] = sim_regno; | |
254 | } | |
255 | ||
09991fa0 JB |
256 | |
257 | /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register | |
258 | numbers to simulator register numbers, based on the values placed | |
259 | in the ARCH->tdep->ppc_foo_regnum members. */ | |
9f643768 JB |
260 | static void |
261 | init_sim_regno_table (struct gdbarch *arch) | |
262 | { | |
263 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); | |
7cc46491 | 264 | int total_regs = gdbarch_num_regs (arch); |
9f643768 JB |
265 | int *sim_regno = GDBARCH_OBSTACK_CALLOC (arch, total_regs, int); |
266 | int i; | |
7cc46491 DJ |
267 | static const char *const segment_regs[] = { |
268 | "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7", | |
269 | "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15" | |
270 | }; | |
9f643768 JB |
271 | |
272 | /* Presume that all registers not explicitly mentioned below are | |
273 | unavailable from the sim. */ | |
274 | for (i = 0; i < total_regs; i++) | |
275 | sim_regno[i] = -1; | |
276 | ||
277 | /* General-purpose registers. */ | |
278 | for (i = 0; i < ppc_num_gprs; i++) | |
279 | set_sim_regno (sim_regno, tdep->ppc_gp0_regnum + i, sim_ppc_r0_regnum + i); | |
280 | ||
281 | /* Floating-point registers. */ | |
282 | if (tdep->ppc_fp0_regnum >= 0) | |
283 | for (i = 0; i < ppc_num_fprs; i++) | |
284 | set_sim_regno (sim_regno, | |
285 | tdep->ppc_fp0_regnum + i, | |
286 | sim_ppc_f0_regnum + i); | |
287 | if (tdep->ppc_fpscr_regnum >= 0) | |
288 | set_sim_regno (sim_regno, tdep->ppc_fpscr_regnum, sim_ppc_fpscr_regnum); | |
289 | ||
290 | set_sim_regno (sim_regno, gdbarch_pc_regnum (arch), sim_ppc_pc_regnum); | |
291 | set_sim_regno (sim_regno, tdep->ppc_ps_regnum, sim_ppc_ps_regnum); | |
292 | set_sim_regno (sim_regno, tdep->ppc_cr_regnum, sim_ppc_cr_regnum); | |
293 | ||
294 | /* Segment registers. */ | |
7cc46491 DJ |
295 | for (i = 0; i < ppc_num_srs; i++) |
296 | { | |
297 | int gdb_regno; | |
298 | ||
299 | gdb_regno = user_reg_map_name_to_regnum (arch, segment_regs[i], -1); | |
300 | if (gdb_regno >= 0) | |
301 | set_sim_regno (sim_regno, gdb_regno, sim_ppc_sr0_regnum + i); | |
302 | } | |
9f643768 JB |
303 | |
304 | /* Altivec registers. */ | |
305 | if (tdep->ppc_vr0_regnum >= 0) | |
306 | { | |
307 | for (i = 0; i < ppc_num_vrs; i++) | |
308 | set_sim_regno (sim_regno, | |
309 | tdep->ppc_vr0_regnum + i, | |
310 | sim_ppc_vr0_regnum + i); | |
311 | ||
312 | /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum, | |
313 | we can treat this more like the other cases. */ | |
314 | set_sim_regno (sim_regno, | |
315 | tdep->ppc_vr0_regnum + ppc_num_vrs, | |
316 | sim_ppc_vscr_regnum); | |
317 | } | |
318 | /* vsave is a special-purpose register, so the code below handles it. */ | |
319 | ||
320 | /* SPE APU (E500) registers. */ | |
6ced10dd JB |
321 | if (tdep->ppc_ev0_upper_regnum >= 0) |
322 | for (i = 0; i < ppc_num_gprs; i++) | |
323 | set_sim_regno (sim_regno, | |
324 | tdep->ppc_ev0_upper_regnum + i, | |
325 | sim_ppc_rh0_regnum + i); | |
9f643768 JB |
326 | if (tdep->ppc_acc_regnum >= 0) |
327 | set_sim_regno (sim_regno, tdep->ppc_acc_regnum, sim_ppc_acc_regnum); | |
328 | /* spefscr is a special-purpose register, so the code below handles it. */ | |
329 | ||
7cc46491 | 330 | #ifdef WITH_SIM |
9f643768 JB |
331 | /* Now handle all special-purpose registers. Verify that they |
332 | haven't mistakenly been assigned numbers by any of the above | |
7cc46491 DJ |
333 | code. */ |
334 | for (i = 0; i < sim_ppc_num_sprs; i++) | |
335 | { | |
336 | const char *spr_name = sim_spr_register_name (i); | |
337 | int gdb_regno = -1; | |
338 | ||
339 | if (spr_name != NULL) | |
340 | gdb_regno = user_reg_map_name_to_regnum (arch, spr_name, -1); | |
341 | ||
342 | if (gdb_regno != -1) | |
343 | set_sim_regno (sim_regno, gdb_regno, sim_ppc_spr0_regnum + i); | |
344 | } | |
345 | #endif | |
9f643768 JB |
346 | |
347 | /* Drop the initialized array into place. */ | |
348 | tdep->sim_regno = sim_regno; | |
349 | } | |
350 | ||
09991fa0 JB |
351 | |
352 | /* Given a GDB register number REG, return the corresponding SIM | |
353 | register number. */ | |
9f643768 | 354 | static int |
e7faf938 | 355 | rs6000_register_sim_regno (struct gdbarch *gdbarch, int reg) |
9f643768 | 356 | { |
e7faf938 | 357 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
9f643768 JB |
358 | int sim_regno; |
359 | ||
7cc46491 | 360 | if (tdep->sim_regno == NULL) |
e7faf938 | 361 | init_sim_regno_table (gdbarch); |
7cc46491 | 362 | |
f57d151a | 363 | gdb_assert (0 <= reg |
e7faf938 MD |
364 | && reg <= gdbarch_num_regs (gdbarch) |
365 | + gdbarch_num_pseudo_regs (gdbarch)); | |
9f643768 JB |
366 | sim_regno = tdep->sim_regno[reg]; |
367 | ||
368 | if (sim_regno >= 0) | |
369 | return sim_regno; | |
370 | else | |
371 | return LEGACY_SIM_REGNO_IGNORE; | |
372 | } | |
373 | ||
d195bc9f MK |
374 | \f |
375 | ||
376 | /* Register set support functions. */ | |
377 | ||
f2db237a AM |
378 | /* REGS + OFFSET contains register REGNUM in a field REGSIZE wide. |
379 | Write the register to REGCACHE. */ | |
380 | ||
7284e1be | 381 | void |
d195bc9f | 382 | ppc_supply_reg (struct regcache *regcache, int regnum, |
f2db237a | 383 | const gdb_byte *regs, size_t offset, int regsize) |
d195bc9f MK |
384 | { |
385 | if (regnum != -1 && offset != -1) | |
f2db237a AM |
386 | { |
387 | if (regsize > 4) | |
388 | { | |
389 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
390 | int gdb_regsize = register_size (gdbarch, regnum); | |
391 | if (gdb_regsize < regsize | |
392 | && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
393 | offset += regsize - gdb_regsize; | |
394 | } | |
395 | regcache_raw_supply (regcache, regnum, regs + offset); | |
396 | } | |
d195bc9f MK |
397 | } |
398 | ||
f2db237a AM |
399 | /* Read register REGNUM from REGCACHE and store to REGS + OFFSET |
400 | in a field REGSIZE wide. Zero pad as necessary. */ | |
401 | ||
7284e1be | 402 | void |
d195bc9f | 403 | ppc_collect_reg (const struct regcache *regcache, int regnum, |
f2db237a | 404 | gdb_byte *regs, size_t offset, int regsize) |
d195bc9f MK |
405 | { |
406 | if (regnum != -1 && offset != -1) | |
f2db237a AM |
407 | { |
408 | if (regsize > 4) | |
409 | { | |
410 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
411 | int gdb_regsize = register_size (gdbarch, regnum); | |
412 | if (gdb_regsize < regsize) | |
413 | { | |
414 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
415 | { | |
416 | memset (regs + offset, 0, regsize - gdb_regsize); | |
417 | offset += regsize - gdb_regsize; | |
418 | } | |
419 | else | |
420 | memset (regs + offset + regsize - gdb_regsize, 0, | |
421 | regsize - gdb_regsize); | |
422 | } | |
423 | } | |
424 | regcache_raw_collect (regcache, regnum, regs + offset); | |
425 | } | |
d195bc9f MK |
426 | } |
427 | ||
f2db237a AM |
428 | static int |
429 | ppc_greg_offset (struct gdbarch *gdbarch, | |
430 | struct gdbarch_tdep *tdep, | |
431 | const struct ppc_reg_offsets *offsets, | |
432 | int regnum, | |
433 | int *regsize) | |
434 | { | |
435 | *regsize = offsets->gpr_size; | |
436 | if (regnum >= tdep->ppc_gp0_regnum | |
437 | && regnum < tdep->ppc_gp0_regnum + ppc_num_gprs) | |
438 | return (offsets->r0_offset | |
439 | + (regnum - tdep->ppc_gp0_regnum) * offsets->gpr_size); | |
440 | ||
441 | if (regnum == gdbarch_pc_regnum (gdbarch)) | |
442 | return offsets->pc_offset; | |
443 | ||
444 | if (regnum == tdep->ppc_ps_regnum) | |
445 | return offsets->ps_offset; | |
446 | ||
447 | if (regnum == tdep->ppc_lr_regnum) | |
448 | return offsets->lr_offset; | |
449 | ||
450 | if (regnum == tdep->ppc_ctr_regnum) | |
451 | return offsets->ctr_offset; | |
452 | ||
453 | *regsize = offsets->xr_size; | |
454 | if (regnum == tdep->ppc_cr_regnum) | |
455 | return offsets->cr_offset; | |
456 | ||
457 | if (regnum == tdep->ppc_xer_regnum) | |
458 | return offsets->xer_offset; | |
459 | ||
460 | if (regnum == tdep->ppc_mq_regnum) | |
461 | return offsets->mq_offset; | |
462 | ||
463 | return -1; | |
464 | } | |
465 | ||
466 | static int | |
467 | ppc_fpreg_offset (struct gdbarch_tdep *tdep, | |
468 | const struct ppc_reg_offsets *offsets, | |
469 | int regnum) | |
470 | { | |
471 | if (regnum >= tdep->ppc_fp0_regnum | |
472 | && regnum < tdep->ppc_fp0_regnum + ppc_num_fprs) | |
473 | return offsets->f0_offset + (regnum - tdep->ppc_fp0_regnum) * 8; | |
474 | ||
475 | if (regnum == tdep->ppc_fpscr_regnum) | |
476 | return offsets->fpscr_offset; | |
477 | ||
478 | return -1; | |
479 | } | |
480 | ||
06caf7d2 CES |
481 | static int |
482 | ppc_vrreg_offset (struct gdbarch_tdep *tdep, | |
483 | const struct ppc_reg_offsets *offsets, | |
484 | int regnum) | |
485 | { | |
486 | if (regnum >= tdep->ppc_vr0_regnum | |
487 | && regnum < tdep->ppc_vr0_regnum + ppc_num_vrs) | |
488 | return offsets->vr0_offset + (regnum - tdep->ppc_vr0_regnum) * 16; | |
489 | ||
490 | if (regnum == tdep->ppc_vrsave_regnum - 1) | |
491 | return offsets->vscr_offset; | |
492 | ||
493 | if (regnum == tdep->ppc_vrsave_regnum) | |
494 | return offsets->vrsave_offset; | |
495 | ||
496 | return -1; | |
497 | } | |
498 | ||
d195bc9f MK |
499 | /* Supply register REGNUM in the general-purpose register set REGSET |
500 | from the buffer specified by GREGS and LEN to register cache | |
501 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
502 | ||
503 | void | |
504 | ppc_supply_gregset (const struct regset *regset, struct regcache *regcache, | |
505 | int regnum, const void *gregs, size_t len) | |
506 | { | |
507 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
508 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
509 | const struct ppc_reg_offsets *offsets = regset->descr; | |
510 | size_t offset; | |
f2db237a | 511 | int regsize; |
d195bc9f | 512 | |
f2db237a | 513 | if (regnum == -1) |
d195bc9f | 514 | { |
f2db237a AM |
515 | int i; |
516 | int gpr_size = offsets->gpr_size; | |
517 | ||
518 | for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset; | |
519 | i < tdep->ppc_gp0_regnum + ppc_num_gprs; | |
520 | i++, offset += gpr_size) | |
521 | ppc_supply_reg (regcache, i, gregs, offset, gpr_size); | |
522 | ||
523 | ppc_supply_reg (regcache, gdbarch_pc_regnum (gdbarch), | |
524 | gregs, offsets->pc_offset, gpr_size); | |
525 | ppc_supply_reg (regcache, tdep->ppc_ps_regnum, | |
526 | gregs, offsets->ps_offset, gpr_size); | |
527 | ppc_supply_reg (regcache, tdep->ppc_lr_regnum, | |
528 | gregs, offsets->lr_offset, gpr_size); | |
529 | ppc_supply_reg (regcache, tdep->ppc_ctr_regnum, | |
530 | gregs, offsets->ctr_offset, gpr_size); | |
531 | ppc_supply_reg (regcache, tdep->ppc_cr_regnum, | |
532 | gregs, offsets->cr_offset, offsets->xr_size); | |
533 | ppc_supply_reg (regcache, tdep->ppc_xer_regnum, | |
534 | gregs, offsets->xer_offset, offsets->xr_size); | |
535 | ppc_supply_reg (regcache, tdep->ppc_mq_regnum, | |
536 | gregs, offsets->mq_offset, offsets->xr_size); | |
537 | return; | |
d195bc9f MK |
538 | } |
539 | ||
f2db237a AM |
540 | offset = ppc_greg_offset (gdbarch, tdep, offsets, regnum, ®size); |
541 | ppc_supply_reg (regcache, regnum, gregs, offset, regsize); | |
d195bc9f MK |
542 | } |
543 | ||
544 | /* Supply register REGNUM in the floating-point register set REGSET | |
545 | from the buffer specified by FPREGS and LEN to register cache | |
546 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
547 | ||
548 | void | |
549 | ppc_supply_fpregset (const struct regset *regset, struct regcache *regcache, | |
550 | int regnum, const void *fpregs, size_t len) | |
551 | { | |
552 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
f2db237a AM |
553 | struct gdbarch_tdep *tdep; |
554 | const struct ppc_reg_offsets *offsets; | |
d195bc9f | 555 | size_t offset; |
d195bc9f | 556 | |
f2db237a AM |
557 | if (!ppc_floating_point_unit_p (gdbarch)) |
558 | return; | |
383f0f5b | 559 | |
f2db237a AM |
560 | tdep = gdbarch_tdep (gdbarch); |
561 | offsets = regset->descr; | |
562 | if (regnum == -1) | |
d195bc9f | 563 | { |
f2db237a AM |
564 | int i; |
565 | ||
566 | for (i = tdep->ppc_fp0_regnum, offset = offsets->f0_offset; | |
567 | i < tdep->ppc_fp0_regnum + ppc_num_fprs; | |
568 | i++, offset += 8) | |
569 | ppc_supply_reg (regcache, i, fpregs, offset, 8); | |
570 | ||
571 | ppc_supply_reg (regcache, tdep->ppc_fpscr_regnum, | |
572 | fpregs, offsets->fpscr_offset, offsets->fpscr_size); | |
573 | return; | |
d195bc9f MK |
574 | } |
575 | ||
f2db237a AM |
576 | offset = ppc_fpreg_offset (tdep, offsets, regnum); |
577 | ppc_supply_reg (regcache, regnum, fpregs, offset, | |
578 | regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8); | |
d195bc9f MK |
579 | } |
580 | ||
604c2f83 LM |
581 | /* Supply register REGNUM in the VSX register set REGSET |
582 | from the buffer specified by VSXREGS and LEN to register cache | |
583 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
584 | ||
585 | void | |
586 | ppc_supply_vsxregset (const struct regset *regset, struct regcache *regcache, | |
587 | int regnum, const void *vsxregs, size_t len) | |
588 | { | |
589 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
590 | struct gdbarch_tdep *tdep; | |
591 | ||
592 | if (!ppc_vsx_support_p (gdbarch)) | |
593 | return; | |
594 | ||
595 | tdep = gdbarch_tdep (gdbarch); | |
596 | ||
597 | if (regnum == -1) | |
598 | { | |
599 | int i; | |
600 | ||
601 | for (i = tdep->ppc_vsr0_upper_regnum; | |
602 | i < tdep->ppc_vsr0_upper_regnum + 32; | |
603 | i++) | |
604 | ppc_supply_reg (regcache, i, vsxregs, 0, 8); | |
605 | ||
606 | return; | |
607 | } | |
608 | else | |
609 | ppc_supply_reg (regcache, regnum, vsxregs, 0, 8); | |
610 | } | |
611 | ||
06caf7d2 CES |
612 | /* Supply register REGNUM in the Altivec register set REGSET |
613 | from the buffer specified by VRREGS and LEN to register cache | |
614 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
615 | ||
616 | void | |
617 | ppc_supply_vrregset (const struct regset *regset, struct regcache *regcache, | |
618 | int regnum, const void *vrregs, size_t len) | |
619 | { | |
620 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
621 | struct gdbarch_tdep *tdep; | |
622 | const struct ppc_reg_offsets *offsets; | |
623 | size_t offset; | |
624 | ||
625 | if (!ppc_altivec_support_p (gdbarch)) | |
626 | return; | |
627 | ||
628 | tdep = gdbarch_tdep (gdbarch); | |
629 | offsets = regset->descr; | |
630 | if (regnum == -1) | |
631 | { | |
632 | int i; | |
633 | ||
634 | for (i = tdep->ppc_vr0_regnum, offset = offsets->vr0_offset; | |
635 | i < tdep->ppc_vr0_regnum + ppc_num_vrs; | |
636 | i++, offset += 16) | |
637 | ppc_supply_reg (regcache, i, vrregs, offset, 16); | |
638 | ||
639 | ppc_supply_reg (regcache, (tdep->ppc_vrsave_regnum - 1), | |
640 | vrregs, offsets->vscr_offset, 4); | |
641 | ||
642 | ppc_supply_reg (regcache, tdep->ppc_vrsave_regnum, | |
643 | vrregs, offsets->vrsave_offset, 4); | |
644 | return; | |
645 | } | |
646 | ||
647 | offset = ppc_vrreg_offset (tdep, offsets, regnum); | |
648 | if (regnum != tdep->ppc_vrsave_regnum | |
649 | && regnum != tdep->ppc_vrsave_regnum - 1) | |
650 | ppc_supply_reg (regcache, regnum, vrregs, offset, 16); | |
651 | else | |
652 | ppc_supply_reg (regcache, regnum, | |
653 | vrregs, offset, 4); | |
654 | } | |
655 | ||
d195bc9f | 656 | /* Collect register REGNUM in the general-purpose register set |
f2db237a | 657 | REGSET from register cache REGCACHE into the buffer specified by |
d195bc9f MK |
658 | GREGS and LEN. If REGNUM is -1, do this for all registers in |
659 | REGSET. */ | |
660 | ||
661 | void | |
662 | ppc_collect_gregset (const struct regset *regset, | |
663 | const struct regcache *regcache, | |
664 | int regnum, void *gregs, size_t len) | |
665 | { | |
666 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
667 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
668 | const struct ppc_reg_offsets *offsets = regset->descr; | |
669 | size_t offset; | |
f2db237a | 670 | int regsize; |
d195bc9f | 671 | |
f2db237a | 672 | if (regnum == -1) |
d195bc9f | 673 | { |
f2db237a AM |
674 | int i; |
675 | int gpr_size = offsets->gpr_size; | |
676 | ||
677 | for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset; | |
678 | i < tdep->ppc_gp0_regnum + ppc_num_gprs; | |
679 | i++, offset += gpr_size) | |
680 | ppc_collect_reg (regcache, i, gregs, offset, gpr_size); | |
681 | ||
682 | ppc_collect_reg (regcache, gdbarch_pc_regnum (gdbarch), | |
683 | gregs, offsets->pc_offset, gpr_size); | |
684 | ppc_collect_reg (regcache, tdep->ppc_ps_regnum, | |
685 | gregs, offsets->ps_offset, gpr_size); | |
686 | ppc_collect_reg (regcache, tdep->ppc_lr_regnum, | |
687 | gregs, offsets->lr_offset, gpr_size); | |
688 | ppc_collect_reg (regcache, tdep->ppc_ctr_regnum, | |
689 | gregs, offsets->ctr_offset, gpr_size); | |
690 | ppc_collect_reg (regcache, tdep->ppc_cr_regnum, | |
691 | gregs, offsets->cr_offset, offsets->xr_size); | |
692 | ppc_collect_reg (regcache, tdep->ppc_xer_regnum, | |
693 | gregs, offsets->xer_offset, offsets->xr_size); | |
694 | ppc_collect_reg (regcache, tdep->ppc_mq_regnum, | |
695 | gregs, offsets->mq_offset, offsets->xr_size); | |
696 | return; | |
d195bc9f MK |
697 | } |
698 | ||
f2db237a AM |
699 | offset = ppc_greg_offset (gdbarch, tdep, offsets, regnum, ®size); |
700 | ppc_collect_reg (regcache, regnum, gregs, offset, regsize); | |
d195bc9f MK |
701 | } |
702 | ||
703 | /* Collect register REGNUM in the floating-point register set | |
f2db237a | 704 | REGSET from register cache REGCACHE into the buffer specified by |
d195bc9f MK |
705 | FPREGS and LEN. If REGNUM is -1, do this for all registers in |
706 | REGSET. */ | |
707 | ||
708 | void | |
709 | ppc_collect_fpregset (const struct regset *regset, | |
710 | const struct regcache *regcache, | |
711 | int regnum, void *fpregs, size_t len) | |
712 | { | |
713 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
f2db237a AM |
714 | struct gdbarch_tdep *tdep; |
715 | const struct ppc_reg_offsets *offsets; | |
d195bc9f | 716 | size_t offset; |
d195bc9f | 717 | |
f2db237a AM |
718 | if (!ppc_floating_point_unit_p (gdbarch)) |
719 | return; | |
383f0f5b | 720 | |
f2db237a AM |
721 | tdep = gdbarch_tdep (gdbarch); |
722 | offsets = regset->descr; | |
723 | if (regnum == -1) | |
d195bc9f | 724 | { |
f2db237a AM |
725 | int i; |
726 | ||
727 | for (i = tdep->ppc_fp0_regnum, offset = offsets->f0_offset; | |
728 | i < tdep->ppc_fp0_regnum + ppc_num_fprs; | |
729 | i++, offset += 8) | |
730 | ppc_collect_reg (regcache, i, fpregs, offset, 8); | |
731 | ||
732 | ppc_collect_reg (regcache, tdep->ppc_fpscr_regnum, | |
733 | fpregs, offsets->fpscr_offset, offsets->fpscr_size); | |
734 | return; | |
d195bc9f MK |
735 | } |
736 | ||
f2db237a AM |
737 | offset = ppc_fpreg_offset (tdep, offsets, regnum); |
738 | ppc_collect_reg (regcache, regnum, fpregs, offset, | |
739 | regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8); | |
d195bc9f | 740 | } |
06caf7d2 | 741 | |
604c2f83 LM |
742 | /* Collect register REGNUM in the VSX register set |
743 | REGSET from register cache REGCACHE into the buffer specified by | |
744 | VSXREGS and LEN. If REGNUM is -1, do this for all registers in | |
745 | REGSET. */ | |
746 | ||
747 | void | |
748 | ppc_collect_vsxregset (const struct regset *regset, | |
749 | const struct regcache *regcache, | |
750 | int regnum, void *vsxregs, size_t len) | |
751 | { | |
752 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
753 | struct gdbarch_tdep *tdep; | |
754 | ||
755 | if (!ppc_vsx_support_p (gdbarch)) | |
756 | return; | |
757 | ||
758 | tdep = gdbarch_tdep (gdbarch); | |
759 | ||
760 | if (regnum == -1) | |
761 | { | |
762 | int i; | |
763 | ||
764 | for (i = tdep->ppc_vsr0_upper_regnum; | |
765 | i < tdep->ppc_vsr0_upper_regnum + 32; | |
766 | i++) | |
767 | ppc_collect_reg (regcache, i, vsxregs, 0, 8); | |
768 | ||
769 | return; | |
770 | } | |
771 | else | |
772 | ppc_collect_reg (regcache, regnum, vsxregs, 0, 8); | |
773 | } | |
774 | ||
775 | ||
06caf7d2 CES |
776 | /* Collect register REGNUM in the Altivec register set |
777 | REGSET from register cache REGCACHE into the buffer specified by | |
778 | VRREGS and LEN. If REGNUM is -1, do this for all registers in | |
779 | REGSET. */ | |
780 | ||
781 | void | |
782 | ppc_collect_vrregset (const struct regset *regset, | |
783 | const struct regcache *regcache, | |
784 | int regnum, void *vrregs, size_t len) | |
785 | { | |
786 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
787 | struct gdbarch_tdep *tdep; | |
788 | const struct ppc_reg_offsets *offsets; | |
789 | size_t offset; | |
790 | ||
791 | if (!ppc_altivec_support_p (gdbarch)) | |
792 | return; | |
793 | ||
794 | tdep = gdbarch_tdep (gdbarch); | |
795 | offsets = regset->descr; | |
796 | if (regnum == -1) | |
797 | { | |
798 | int i; | |
799 | ||
800 | for (i = tdep->ppc_vr0_regnum, offset = offsets->vr0_offset; | |
801 | i < tdep->ppc_vr0_regnum + ppc_num_vrs; | |
802 | i++, offset += 16) | |
803 | ppc_collect_reg (regcache, i, vrregs, offset, 16); | |
804 | ||
805 | ppc_collect_reg (regcache, (tdep->ppc_vrsave_regnum - 1), | |
806 | vrregs, offsets->vscr_offset, 4); | |
807 | ||
808 | ppc_collect_reg (regcache, tdep->ppc_vrsave_regnum, | |
809 | vrregs, offsets->vrsave_offset, 4); | |
810 | return; | |
811 | } | |
812 | ||
813 | offset = ppc_vrreg_offset (tdep, offsets, regnum); | |
814 | if (regnum != tdep->ppc_vrsave_regnum | |
815 | && regnum != tdep->ppc_vrsave_regnum - 1) | |
816 | ppc_collect_reg (regcache, regnum, vrregs, offset, 16); | |
817 | else | |
818 | ppc_collect_reg (regcache, regnum, | |
819 | vrregs, offset, 4); | |
820 | } | |
d195bc9f | 821 | \f |
0a613259 | 822 | |
0d1243d9 PG |
823 | static int |
824 | insn_changes_sp_or_jumps (unsigned long insn) | |
825 | { | |
826 | int opcode = (insn >> 26) & 0x03f; | |
827 | int sd = (insn >> 21) & 0x01f; | |
828 | int a = (insn >> 16) & 0x01f; | |
829 | int subcode = (insn >> 1) & 0x3ff; | |
830 | ||
831 | /* Changes the stack pointer. */ | |
832 | ||
833 | /* NOTE: There are many ways to change the value of a given register. | |
834 | The ways below are those used when the register is R1, the SP, | |
835 | in a funtion's epilogue. */ | |
836 | ||
837 | if (opcode == 31 && subcode == 444 && a == 1) | |
838 | return 1; /* mr R1,Rn */ | |
839 | if (opcode == 14 && sd == 1) | |
840 | return 1; /* addi R1,Rn,simm */ | |
841 | if (opcode == 58 && sd == 1) | |
842 | return 1; /* ld R1,ds(Rn) */ | |
843 | ||
844 | /* Transfers control. */ | |
845 | ||
846 | if (opcode == 18) | |
847 | return 1; /* b */ | |
848 | if (opcode == 16) | |
849 | return 1; /* bc */ | |
850 | if (opcode == 19 && subcode == 16) | |
851 | return 1; /* bclr */ | |
852 | if (opcode == 19 && subcode == 528) | |
853 | return 1; /* bcctr */ | |
854 | ||
855 | return 0; | |
856 | } | |
857 | ||
858 | /* Return true if we are in the function's epilogue, i.e. after the | |
859 | instruction that destroyed the function's stack frame. | |
860 | ||
861 | 1) scan forward from the point of execution: | |
862 | a) If you find an instruction that modifies the stack pointer | |
863 | or transfers control (except a return), execution is not in | |
864 | an epilogue, return. | |
865 | b) Stop scanning if you find a return instruction or reach the | |
866 | end of the function or reach the hard limit for the size of | |
867 | an epilogue. | |
868 | 2) scan backward from the point of execution: | |
869 | a) If you find an instruction that modifies the stack pointer, | |
870 | execution *is* in an epilogue, return. | |
871 | b) Stop scanning if you reach an instruction that transfers | |
872 | control or the beginning of the function or reach the hard | |
873 | limit for the size of an epilogue. */ | |
874 | ||
875 | static int | |
876 | rs6000_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
877 | { | |
46a9b8ed | 878 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
e17a4113 | 879 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
0d1243d9 PG |
880 | bfd_byte insn_buf[PPC_INSN_SIZE]; |
881 | CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end; | |
882 | unsigned long insn; | |
883 | struct frame_info *curfrm; | |
884 | ||
885 | /* Find the search limits based on function boundaries and hard limit. */ | |
886 | ||
887 | if (!find_pc_partial_function (pc, NULL, &func_start, &func_end)) | |
888 | return 0; | |
889 | ||
890 | epilogue_start = pc - PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE; | |
891 | if (epilogue_start < func_start) epilogue_start = func_start; | |
892 | ||
893 | epilogue_end = pc + PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE; | |
894 | if (epilogue_end > func_end) epilogue_end = func_end; | |
895 | ||
896 | curfrm = get_current_frame (); | |
897 | ||
898 | /* Scan forward until next 'blr'. */ | |
899 | ||
900 | for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += PPC_INSN_SIZE) | |
901 | { | |
902 | if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE)) | |
903 | return 0; | |
e17a4113 | 904 | insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE, byte_order); |
0d1243d9 PG |
905 | if (insn == 0x4e800020) |
906 | break; | |
46a9b8ed DJ |
907 | /* Assume a bctr is a tail call unless it points strictly within |
908 | this function. */ | |
909 | if (insn == 0x4e800420) | |
910 | { | |
911 | CORE_ADDR ctr = get_frame_register_unsigned (curfrm, | |
912 | tdep->ppc_ctr_regnum); | |
913 | if (ctr > func_start && ctr < func_end) | |
914 | return 0; | |
915 | else | |
916 | break; | |
917 | } | |
0d1243d9 PG |
918 | if (insn_changes_sp_or_jumps (insn)) |
919 | return 0; | |
920 | } | |
921 | ||
922 | /* Scan backward until adjustment to stack pointer (R1). */ | |
923 | ||
924 | for (scan_pc = pc - PPC_INSN_SIZE; | |
925 | scan_pc >= epilogue_start; | |
926 | scan_pc -= PPC_INSN_SIZE) | |
927 | { | |
928 | if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE)) | |
929 | return 0; | |
e17a4113 | 930 | insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE, byte_order); |
0d1243d9 PG |
931 | if (insn_changes_sp_or_jumps (insn)) |
932 | return 1; | |
933 | } | |
934 | ||
935 | return 0; | |
936 | } | |
937 | ||
143985b7 | 938 | /* Get the ith function argument for the current function. */ |
b9362cc7 | 939 | static CORE_ADDR |
143985b7 AF |
940 | rs6000_fetch_pointer_argument (struct frame_info *frame, int argi, |
941 | struct type *type) | |
942 | { | |
50fd1280 | 943 | return get_frame_register_unsigned (frame, 3 + argi); |
143985b7 AF |
944 | } |
945 | ||
c906108c SS |
946 | /* Sequence of bytes for breakpoint instruction. */ |
947 | ||
44d100c3 | 948 | static const unsigned char * |
67d57894 MD |
949 | rs6000_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *bp_addr, |
950 | int *bp_size) | |
c906108c | 951 | { |
aaab4dba AC |
952 | static unsigned char big_breakpoint[] = { 0x7d, 0x82, 0x10, 0x08 }; |
953 | static unsigned char little_breakpoint[] = { 0x08, 0x10, 0x82, 0x7d }; | |
c906108c | 954 | *bp_size = 4; |
67d57894 | 955 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
c906108c SS |
956 | return big_breakpoint; |
957 | else | |
958 | return little_breakpoint; | |
959 | } | |
960 | ||
f74c6cad LM |
961 | /* Instruction masks for displaced stepping. */ |
962 | #define BRANCH_MASK 0xfc000000 | |
963 | #define BP_MASK 0xFC0007FE | |
964 | #define B_INSN 0x48000000 | |
965 | #define BC_INSN 0x40000000 | |
966 | #define BXL_INSN 0x4c000000 | |
967 | #define BP_INSN 0x7C000008 | |
968 | ||
969 | /* Fix up the state of registers and memory after having single-stepped | |
970 | a displaced instruction. */ | |
63807e1d | 971 | static void |
f74c6cad | 972 | ppc_displaced_step_fixup (struct gdbarch *gdbarch, |
63807e1d PA |
973 | struct displaced_step_closure *closure, |
974 | CORE_ADDR from, CORE_ADDR to, | |
975 | struct regcache *regs) | |
f74c6cad | 976 | { |
e17a4113 | 977 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
f74c6cad LM |
978 | /* Since we use simple_displaced_step_copy_insn, our closure is a |
979 | copy of the instruction. */ | |
980 | ULONGEST insn = extract_unsigned_integer ((gdb_byte *) closure, | |
e17a4113 | 981 | PPC_INSN_SIZE, byte_order); |
f74c6cad LM |
982 | ULONGEST opcode = 0; |
983 | /* Offset for non PC-relative instructions. */ | |
984 | LONGEST offset = PPC_INSN_SIZE; | |
985 | ||
986 | opcode = insn & BRANCH_MASK; | |
987 | ||
988 | if (debug_displaced) | |
989 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 UW |
990 | "displaced: (ppc) fixup (%s, %s)\n", |
991 | paddress (gdbarch, from), paddress (gdbarch, to)); | |
f74c6cad LM |
992 | |
993 | ||
994 | /* Handle PC-relative branch instructions. */ | |
995 | if (opcode == B_INSN || opcode == BC_INSN || opcode == BXL_INSN) | |
996 | { | |
a4fafde3 | 997 | ULONGEST current_pc; |
f74c6cad LM |
998 | |
999 | /* Read the current PC value after the instruction has been executed | |
1000 | in a displaced location. Calculate the offset to be applied to the | |
1001 | original PC value before the displaced stepping. */ | |
1002 | regcache_cooked_read_unsigned (regs, gdbarch_pc_regnum (gdbarch), | |
1003 | ¤t_pc); | |
1004 | offset = current_pc - to; | |
1005 | ||
1006 | if (opcode != BXL_INSN) | |
1007 | { | |
1008 | /* Check for AA bit indicating whether this is an absolute | |
1009 | addressing or PC-relative (1: absolute, 0: relative). */ | |
1010 | if (!(insn & 0x2)) | |
1011 | { | |
1012 | /* PC-relative addressing is being used in the branch. */ | |
1013 | if (debug_displaced) | |
1014 | fprintf_unfiltered | |
1015 | (gdb_stdlog, | |
5af949e3 UW |
1016 | "displaced: (ppc) branch instruction: %s\n" |
1017 | "displaced: (ppc) adjusted PC from %s to %s\n", | |
1018 | paddress (gdbarch, insn), paddress (gdbarch, current_pc), | |
1019 | paddress (gdbarch, from + offset)); | |
f74c6cad | 1020 | |
0df8b418 MS |
1021 | regcache_cooked_write_unsigned (regs, |
1022 | gdbarch_pc_regnum (gdbarch), | |
f74c6cad LM |
1023 | from + offset); |
1024 | } | |
1025 | } | |
1026 | else | |
1027 | { | |
1028 | /* If we're here, it means we have a branch to LR or CTR. If the | |
1029 | branch was taken, the offset is probably greater than 4 (the next | |
1030 | instruction), so it's safe to assume that an offset of 4 means we | |
1031 | did not take the branch. */ | |
1032 | if (offset == PPC_INSN_SIZE) | |
1033 | regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch), | |
1034 | from + PPC_INSN_SIZE); | |
1035 | } | |
1036 | ||
1037 | /* Check for LK bit indicating whether we should set the link | |
1038 | register to point to the next instruction | |
1039 | (1: Set, 0: Don't set). */ | |
1040 | if (insn & 0x1) | |
1041 | { | |
1042 | /* Link register needs to be set to the next instruction's PC. */ | |
1043 | regcache_cooked_write_unsigned (regs, | |
1044 | gdbarch_tdep (gdbarch)->ppc_lr_regnum, | |
1045 | from + PPC_INSN_SIZE); | |
1046 | if (debug_displaced) | |
1047 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 UW |
1048 | "displaced: (ppc) adjusted LR to %s\n", |
1049 | paddress (gdbarch, from + PPC_INSN_SIZE)); | |
f74c6cad LM |
1050 | |
1051 | } | |
1052 | } | |
1053 | /* Check for breakpoints in the inferior. If we've found one, place the PC | |
1054 | right at the breakpoint instruction. */ | |
1055 | else if ((insn & BP_MASK) == BP_INSN) | |
1056 | regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch), from); | |
1057 | else | |
1058 | /* Handle any other instructions that do not fit in the categories above. */ | |
1059 | regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch), | |
1060 | from + offset); | |
1061 | } | |
c906108c | 1062 | |
99e40580 UW |
1063 | /* Always use hardware single-stepping to execute the |
1064 | displaced instruction. */ | |
1065 | static int | |
1066 | ppc_displaced_step_hw_singlestep (struct gdbarch *gdbarch, | |
1067 | struct displaced_step_closure *closure) | |
1068 | { | |
1069 | return 1; | |
1070 | } | |
1071 | ||
ce5eab59 UW |
1072 | /* Instruction masks used during single-stepping of atomic sequences. */ |
1073 | #define LWARX_MASK 0xfc0007fe | |
1074 | #define LWARX_INSTRUCTION 0x7c000028 | |
1075 | #define LDARX_INSTRUCTION 0x7c0000A8 | |
1076 | #define STWCX_MASK 0xfc0007ff | |
1077 | #define STWCX_INSTRUCTION 0x7c00012d | |
1078 | #define STDCX_INSTRUCTION 0x7c0001ad | |
ce5eab59 UW |
1079 | |
1080 | /* Checks for an atomic sequence of instructions beginning with a LWARX/LDARX | |
1081 | instruction and ending with a STWCX/STDCX instruction. If such a sequence | |
1082 | is found, attempt to step through it. A breakpoint is placed at the end of | |
1083 | the sequence. */ | |
1084 | ||
4a7622d1 UW |
1085 | int |
1086 | ppc_deal_with_atomic_sequence (struct frame_info *frame) | |
ce5eab59 | 1087 | { |
a6d9a66e | 1088 | struct gdbarch *gdbarch = get_frame_arch (frame); |
6c95b8df | 1089 | struct address_space *aspace = get_frame_address_space (frame); |
e17a4113 | 1090 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
0b1b3e42 | 1091 | CORE_ADDR pc = get_frame_pc (frame); |
ce5eab59 UW |
1092 | CORE_ADDR breaks[2] = {-1, -1}; |
1093 | CORE_ADDR loc = pc; | |
24d45690 | 1094 | CORE_ADDR closing_insn; /* Instruction that closes the atomic sequence. */ |
e17a4113 | 1095 | int insn = read_memory_integer (loc, PPC_INSN_SIZE, byte_order); |
ce5eab59 UW |
1096 | int insn_count; |
1097 | int index; | |
1098 | int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ | |
1099 | const int atomic_sequence_length = 16; /* Instruction sequence length. */ | |
24d45690 | 1100 | int opcode; /* Branch instruction's OPcode. */ |
ce5eab59 UW |
1101 | int bc_insn_count = 0; /* Conditional branch instruction count. */ |
1102 | ||
1103 | /* Assume all atomic sequences start with a lwarx/ldarx instruction. */ | |
1104 | if ((insn & LWARX_MASK) != LWARX_INSTRUCTION | |
1105 | && (insn & LWARX_MASK) != LDARX_INSTRUCTION) | |
1106 | return 0; | |
1107 | ||
1108 | /* Assume that no atomic sequence is longer than "atomic_sequence_length" | |
1109 | instructions. */ | |
1110 | for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) | |
1111 | { | |
1112 | loc += PPC_INSN_SIZE; | |
e17a4113 | 1113 | insn = read_memory_integer (loc, PPC_INSN_SIZE, byte_order); |
ce5eab59 UW |
1114 | |
1115 | /* Assume that there is at most one conditional branch in the atomic | |
1116 | sequence. If a conditional branch is found, put a breakpoint in | |
1117 | its destination address. */ | |
f74c6cad | 1118 | if ((insn & BRANCH_MASK) == BC_INSN) |
ce5eab59 | 1119 | { |
a3769e0c AM |
1120 | int immediate = ((insn & 0xfffc) ^ 0x8000) - 0x8000; |
1121 | int absolute = insn & 2; | |
4a7622d1 | 1122 | |
ce5eab59 UW |
1123 | if (bc_insn_count >= 1) |
1124 | return 0; /* More than one conditional branch found, fallback | |
1125 | to the standard single-step code. */ | |
4a7622d1 UW |
1126 | |
1127 | if (absolute) | |
1128 | breaks[1] = immediate; | |
1129 | else | |
a3769e0c | 1130 | breaks[1] = loc + immediate; |
4a7622d1 UW |
1131 | |
1132 | bc_insn_count++; | |
1133 | last_breakpoint++; | |
ce5eab59 UW |
1134 | } |
1135 | ||
1136 | if ((insn & STWCX_MASK) == STWCX_INSTRUCTION | |
1137 | || (insn & STWCX_MASK) == STDCX_INSTRUCTION) | |
1138 | break; | |
1139 | } | |
1140 | ||
1141 | /* Assume that the atomic sequence ends with a stwcx/stdcx instruction. */ | |
1142 | if ((insn & STWCX_MASK) != STWCX_INSTRUCTION | |
1143 | && (insn & STWCX_MASK) != STDCX_INSTRUCTION) | |
1144 | return 0; | |
1145 | ||
24d45690 | 1146 | closing_insn = loc; |
ce5eab59 | 1147 | loc += PPC_INSN_SIZE; |
e17a4113 | 1148 | insn = read_memory_integer (loc, PPC_INSN_SIZE, byte_order); |
ce5eab59 UW |
1149 | |
1150 | /* Insert a breakpoint right after the end of the atomic sequence. */ | |
1151 | breaks[0] = loc; | |
1152 | ||
24d45690 | 1153 | /* Check for duplicated breakpoints. Check also for a breakpoint |
a3769e0c AM |
1154 | placed (branch instruction's destination) anywhere in sequence. */ |
1155 | if (last_breakpoint | |
1156 | && (breaks[1] == breaks[0] | |
1157 | || (breaks[1] >= pc && breaks[1] <= closing_insn))) | |
ce5eab59 UW |
1158 | last_breakpoint = 0; |
1159 | ||
1160 | /* Effectively inserts the breakpoints. */ | |
1161 | for (index = 0; index <= last_breakpoint; index++) | |
6c95b8df | 1162 | insert_single_step_breakpoint (gdbarch, aspace, breaks[index]); |
ce5eab59 UW |
1163 | |
1164 | return 1; | |
1165 | } | |
1166 | ||
c906108c | 1167 | |
c906108c SS |
1168 | #define SIGNED_SHORT(x) \ |
1169 | ((sizeof (short) == 2) \ | |
1170 | ? ((int)(short)(x)) \ | |
1171 | : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000))) | |
1172 | ||
1173 | #define GET_SRC_REG(x) (((x) >> 21) & 0x1f) | |
1174 | ||
55d05f3b KB |
1175 | /* Limit the number of skipped non-prologue instructions, as the examining |
1176 | of the prologue is expensive. */ | |
1177 | static int max_skip_non_prologue_insns = 10; | |
1178 | ||
773df3e5 JB |
1179 | /* Return nonzero if the given instruction OP can be part of the prologue |
1180 | of a function and saves a parameter on the stack. FRAMEP should be | |
1181 | set if one of the previous instructions in the function has set the | |
1182 | Frame Pointer. */ | |
1183 | ||
1184 | static int | |
1185 | store_param_on_stack_p (unsigned long op, int framep, int *r0_contains_arg) | |
1186 | { | |
1187 | /* Move parameters from argument registers to temporary register. */ | |
1188 | if ((op & 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */ | |
1189 | { | |
1190 | /* Rx must be scratch register r0. */ | |
1191 | const int rx_regno = (op >> 16) & 31; | |
1192 | /* Ry: Only r3 - r10 are used for parameter passing. */ | |
1193 | const int ry_regno = GET_SRC_REG (op); | |
1194 | ||
1195 | if (rx_regno == 0 && ry_regno >= 3 && ry_regno <= 10) | |
1196 | { | |
1197 | *r0_contains_arg = 1; | |
1198 | return 1; | |
1199 | } | |
1200 | else | |
1201 | return 0; | |
1202 | } | |
1203 | ||
1204 | /* Save a General Purpose Register on stack. */ | |
1205 | ||
1206 | if ((op & 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */ | |
1207 | (op & 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */ | |
1208 | { | |
1209 | /* Rx: Only r3 - r10 are used for parameter passing. */ | |
1210 | const int rx_regno = GET_SRC_REG (op); | |
1211 | ||
1212 | return (rx_regno >= 3 && rx_regno <= 10); | |
1213 | } | |
1214 | ||
1215 | /* Save a General Purpose Register on stack via the Frame Pointer. */ | |
1216 | ||
1217 | if (framep && | |
1218 | ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */ | |
1219 | (op & 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */ | |
1220 | (op & 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */ | |
1221 | { | |
1222 | /* Rx: Usually, only r3 - r10 are used for parameter passing. | |
1223 | However, the compiler sometimes uses r0 to hold an argument. */ | |
1224 | const int rx_regno = GET_SRC_REG (op); | |
1225 | ||
1226 | return ((rx_regno >= 3 && rx_regno <= 10) | |
1227 | || (rx_regno == 0 && *r0_contains_arg)); | |
1228 | } | |
1229 | ||
1230 | if ((op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */ | |
1231 | { | |
1232 | /* Only f2 - f8 are used for parameter passing. */ | |
1233 | const int src_regno = GET_SRC_REG (op); | |
1234 | ||
1235 | return (src_regno >= 2 && src_regno <= 8); | |
1236 | } | |
1237 | ||
1238 | if (framep && ((op & 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */ | |
1239 | { | |
1240 | /* Only f2 - f8 are used for parameter passing. */ | |
1241 | const int src_regno = GET_SRC_REG (op); | |
1242 | ||
1243 | return (src_regno >= 2 && src_regno <= 8); | |
1244 | } | |
1245 | ||
1246 | /* Not an insn that saves a parameter on stack. */ | |
1247 | return 0; | |
1248 | } | |
55d05f3b | 1249 | |
3c77c82a DJ |
1250 | /* Assuming that INSN is a "bl" instruction located at PC, return |
1251 | nonzero if the destination of the branch is a "blrl" instruction. | |
1252 | ||
1253 | This sequence is sometimes found in certain function prologues. | |
1254 | It allows the function to load the LR register with a value that | |
1255 | they can use to access PIC data using PC-relative offsets. */ | |
1256 | ||
1257 | static int | |
e17a4113 | 1258 | bl_to_blrl_insn_p (CORE_ADDR pc, int insn, enum bfd_endian byte_order) |
3c77c82a | 1259 | { |
0b1b3e42 UW |
1260 | CORE_ADDR dest; |
1261 | int immediate; | |
1262 | int absolute; | |
3c77c82a DJ |
1263 | int dest_insn; |
1264 | ||
0b1b3e42 UW |
1265 | absolute = (int) ((insn >> 1) & 1); |
1266 | immediate = ((insn & ~3) << 6) >> 6; | |
1267 | if (absolute) | |
1268 | dest = immediate; | |
1269 | else | |
1270 | dest = pc + immediate; | |
1271 | ||
e17a4113 | 1272 | dest_insn = read_memory_integer (dest, 4, byte_order); |
3c77c82a DJ |
1273 | if ((dest_insn & 0xfc00ffff) == 0x4c000021) /* blrl */ |
1274 | return 1; | |
1275 | ||
1276 | return 0; | |
1277 | } | |
1278 | ||
0df8b418 | 1279 | /* Masks for decoding a branch-and-link (bl) instruction. |
8ab3d180 KB |
1280 | |
1281 | BL_MASK and BL_INSTRUCTION are used in combination with each other. | |
1282 | The former is anded with the opcode in question; if the result of | |
1283 | this masking operation is equal to BL_INSTRUCTION, then the opcode in | |
1284 | question is a ``bl'' instruction. | |
1285 | ||
1286 | BL_DISPLACMENT_MASK is anded with the opcode in order to extract | |
1287 | the branch displacement. */ | |
1288 | ||
1289 | #define BL_MASK 0xfc000001 | |
1290 | #define BL_INSTRUCTION 0x48000001 | |
1291 | #define BL_DISPLACEMENT_MASK 0x03fffffc | |
1292 | ||
de9f48f0 | 1293 | static unsigned long |
e17a4113 | 1294 | rs6000_fetch_instruction (struct gdbarch *gdbarch, const CORE_ADDR pc) |
de9f48f0 | 1295 | { |
e17a4113 | 1296 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
de9f48f0 JG |
1297 | gdb_byte buf[4]; |
1298 | unsigned long op; | |
1299 | ||
1300 | /* Fetch the instruction and convert it to an integer. */ | |
1301 | if (target_read_memory (pc, buf, 4)) | |
1302 | return 0; | |
e17a4113 | 1303 | op = extract_unsigned_integer (buf, 4, byte_order); |
de9f48f0 JG |
1304 | |
1305 | return op; | |
1306 | } | |
1307 | ||
1308 | /* GCC generates several well-known sequences of instructions at the begining | |
1309 | of each function prologue when compiling with -fstack-check. If one of | |
1310 | such sequences starts at START_PC, then return the address of the | |
1311 | instruction immediately past this sequence. Otherwise, return START_PC. */ | |
1312 | ||
1313 | static CORE_ADDR | |
e17a4113 | 1314 | rs6000_skip_stack_check (struct gdbarch *gdbarch, const CORE_ADDR start_pc) |
de9f48f0 JG |
1315 | { |
1316 | CORE_ADDR pc = start_pc; | |
e17a4113 | 1317 | unsigned long op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 JG |
1318 | |
1319 | /* First possible sequence: A small number of probes. | |
1320 | stw 0, -<some immediate>(1) | |
0df8b418 | 1321 | [repeat this instruction any (small) number of times]. */ |
de9f48f0 JG |
1322 | |
1323 | if ((op & 0xffff0000) == 0x90010000) | |
1324 | { | |
1325 | while ((op & 0xffff0000) == 0x90010000) | |
1326 | { | |
1327 | pc = pc + 4; | |
e17a4113 | 1328 | op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 JG |
1329 | } |
1330 | return pc; | |
1331 | } | |
1332 | ||
1333 | /* Second sequence: A probing loop. | |
1334 | addi 12,1,-<some immediate> | |
1335 | lis 0,-<some immediate> | |
1336 | [possibly ori 0,0,<some immediate>] | |
1337 | add 0,12,0 | |
1338 | cmpw 0,12,0 | |
1339 | beq 0,<disp> | |
1340 | addi 12,12,-<some immediate> | |
1341 | stw 0,0(12) | |
1342 | b <disp> | |
0df8b418 | 1343 | [possibly one last probe: stw 0,<some immediate>(12)]. */ |
de9f48f0 JG |
1344 | |
1345 | while (1) | |
1346 | { | |
1347 | /* addi 12,1,-<some immediate> */ | |
1348 | if ((op & 0xffff0000) != 0x39810000) | |
1349 | break; | |
1350 | ||
1351 | /* lis 0,-<some immediate> */ | |
1352 | pc = pc + 4; | |
e17a4113 | 1353 | op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 JG |
1354 | if ((op & 0xffff0000) != 0x3c000000) |
1355 | break; | |
1356 | ||
1357 | pc = pc + 4; | |
e17a4113 | 1358 | op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 JG |
1359 | /* [possibly ori 0,0,<some immediate>] */ |
1360 | if ((op & 0xffff0000) == 0x60000000) | |
1361 | { | |
1362 | pc = pc + 4; | |
e17a4113 | 1363 | op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 JG |
1364 | } |
1365 | /* add 0,12,0 */ | |
1366 | if (op != 0x7c0c0214) | |
1367 | break; | |
1368 | ||
1369 | /* cmpw 0,12,0 */ | |
1370 | pc = pc + 4; | |
e17a4113 | 1371 | op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 JG |
1372 | if (op != 0x7c0c0000) |
1373 | break; | |
1374 | ||
1375 | /* beq 0,<disp> */ | |
1376 | pc = pc + 4; | |
e17a4113 | 1377 | op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 JG |
1378 | if ((op & 0xff9f0001) != 0x41820000) |
1379 | break; | |
1380 | ||
1381 | /* addi 12,12,-<some immediate> */ | |
1382 | pc = pc + 4; | |
e17a4113 | 1383 | op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 JG |
1384 | if ((op & 0xffff0000) != 0x398c0000) |
1385 | break; | |
1386 | ||
1387 | /* stw 0,0(12) */ | |
1388 | pc = pc + 4; | |
e17a4113 | 1389 | op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 JG |
1390 | if (op != 0x900c0000) |
1391 | break; | |
1392 | ||
1393 | /* b <disp> */ | |
1394 | pc = pc + 4; | |
e17a4113 | 1395 | op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 JG |
1396 | if ((op & 0xfc000001) != 0x48000000) |
1397 | break; | |
1398 | ||
0df8b418 | 1399 | /* [possibly one last probe: stw 0,<some immediate>(12)]. */ |
de9f48f0 | 1400 | pc = pc + 4; |
e17a4113 | 1401 | op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 JG |
1402 | if ((op & 0xffff0000) == 0x900c0000) |
1403 | { | |
1404 | pc = pc + 4; | |
e17a4113 | 1405 | op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 JG |
1406 | } |
1407 | ||
1408 | /* We found a valid stack-check sequence, return the new PC. */ | |
1409 | return pc; | |
1410 | } | |
1411 | ||
1412 | /* Third sequence: No probe; instead, a comparizon between the stack size | |
1413 | limit (saved in a run-time global variable) and the current stack | |
1414 | pointer: | |
1415 | ||
1416 | addi 0,1,-<some immediate> | |
1417 | lis 12,__gnat_stack_limit@ha | |
1418 | lwz 12,__gnat_stack_limit@l(12) | |
1419 | twllt 0,12 | |
1420 | ||
1421 | or, with a small variant in the case of a bigger stack frame: | |
1422 | addis 0,1,<some immediate> | |
1423 | addic 0,0,-<some immediate> | |
1424 | lis 12,__gnat_stack_limit@ha | |
1425 | lwz 12,__gnat_stack_limit@l(12) | |
1426 | twllt 0,12 | |
1427 | */ | |
1428 | while (1) | |
1429 | { | |
1430 | /* addi 0,1,-<some immediate> */ | |
1431 | if ((op & 0xffff0000) != 0x38010000) | |
1432 | { | |
1433 | /* small stack frame variant not recognized; try the | |
1434 | big stack frame variant: */ | |
1435 | ||
1436 | /* addis 0,1,<some immediate> */ | |
1437 | if ((op & 0xffff0000) != 0x3c010000) | |
1438 | break; | |
1439 | ||
1440 | /* addic 0,0,-<some immediate> */ | |
1441 | pc = pc + 4; | |
e17a4113 | 1442 | op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 JG |
1443 | if ((op & 0xffff0000) != 0x30000000) |
1444 | break; | |
1445 | } | |
1446 | ||
1447 | /* lis 12,<some immediate> */ | |
1448 | pc = pc + 4; | |
e17a4113 | 1449 | op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 JG |
1450 | if ((op & 0xffff0000) != 0x3d800000) |
1451 | break; | |
1452 | ||
1453 | /* lwz 12,<some immediate>(12) */ | |
1454 | pc = pc + 4; | |
e17a4113 | 1455 | op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 JG |
1456 | if ((op & 0xffff0000) != 0x818c0000) |
1457 | break; | |
1458 | ||
1459 | /* twllt 0,12 */ | |
1460 | pc = pc + 4; | |
e17a4113 | 1461 | op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 JG |
1462 | if ((op & 0xfffffffe) != 0x7c406008) |
1463 | break; | |
1464 | ||
1465 | /* We found a valid stack-check sequence, return the new PC. */ | |
1466 | return pc; | |
1467 | } | |
1468 | ||
1469 | /* No stack check code in our prologue, return the start_pc. */ | |
1470 | return start_pc; | |
1471 | } | |
1472 | ||
6a16c029 TJB |
1473 | /* return pc value after skipping a function prologue and also return |
1474 | information about a function frame. | |
1475 | ||
1476 | in struct rs6000_framedata fdata: | |
1477 | - frameless is TRUE, if function does not have a frame. | |
1478 | - nosavedpc is TRUE, if function does not save %pc value in its frame. | |
1479 | - offset is the initial size of this stack frame --- the amount by | |
1480 | which we decrement the sp to allocate the frame. | |
1481 | - saved_gpr is the number of the first saved gpr. | |
1482 | - saved_fpr is the number of the first saved fpr. | |
1483 | - saved_vr is the number of the first saved vr. | |
1484 | - saved_ev is the number of the first saved ev. | |
1485 | - alloca_reg is the number of the register used for alloca() handling. | |
1486 | Otherwise -1. | |
1487 | - gpr_offset is the offset of the first saved gpr from the previous frame. | |
1488 | - fpr_offset is the offset of the first saved fpr from the previous frame. | |
1489 | - vr_offset is the offset of the first saved vr from the previous frame. | |
1490 | - ev_offset is the offset of the first saved ev from the previous frame. | |
1491 | - lr_offset is the offset of the saved lr | |
1492 | - cr_offset is the offset of the saved cr | |
0df8b418 | 1493 | - vrsave_offset is the offset of the saved vrsave register. */ |
6a16c029 | 1494 | |
7a78ae4e | 1495 | static CORE_ADDR |
be8626e0 MD |
1496 | skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, CORE_ADDR lim_pc, |
1497 | struct rs6000_framedata *fdata) | |
c906108c SS |
1498 | { |
1499 | CORE_ADDR orig_pc = pc; | |
55d05f3b | 1500 | CORE_ADDR last_prologue_pc = pc; |
6be8bc0c | 1501 | CORE_ADDR li_found_pc = 0; |
50fd1280 | 1502 | gdb_byte buf[4]; |
c906108c SS |
1503 | unsigned long op; |
1504 | long offset = 0; | |
6be8bc0c | 1505 | long vr_saved_offset = 0; |
482ca3f5 KB |
1506 | int lr_reg = -1; |
1507 | int cr_reg = -1; | |
6be8bc0c | 1508 | int vr_reg = -1; |
96ff0de4 EZ |
1509 | int ev_reg = -1; |
1510 | long ev_offset = 0; | |
6be8bc0c | 1511 | int vrsave_reg = -1; |
c906108c SS |
1512 | int reg; |
1513 | int framep = 0; | |
1514 | int minimal_toc_loaded = 0; | |
ddb20c56 | 1515 | int prev_insn_was_prologue_insn = 1; |
55d05f3b | 1516 | int num_skip_non_prologue_insns = 0; |
773df3e5 | 1517 | int r0_contains_arg = 0; |
be8626e0 MD |
1518 | const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (gdbarch); |
1519 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
e17a4113 | 1520 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
c906108c | 1521 | |
ddb20c56 | 1522 | memset (fdata, 0, sizeof (struct rs6000_framedata)); |
c906108c SS |
1523 | fdata->saved_gpr = -1; |
1524 | fdata->saved_fpr = -1; | |
6be8bc0c | 1525 | fdata->saved_vr = -1; |
96ff0de4 | 1526 | fdata->saved_ev = -1; |
c906108c SS |
1527 | fdata->alloca_reg = -1; |
1528 | fdata->frameless = 1; | |
1529 | fdata->nosavedpc = 1; | |
46a9b8ed | 1530 | fdata->lr_register = -1; |
c906108c | 1531 | |
e17a4113 | 1532 | pc = rs6000_skip_stack_check (gdbarch, pc); |
de9f48f0 JG |
1533 | if (pc >= lim_pc) |
1534 | pc = lim_pc; | |
1535 | ||
55d05f3b | 1536 | for (;; pc += 4) |
c906108c | 1537 | { |
ddb20c56 KB |
1538 | /* Sometimes it isn't clear if an instruction is a prologue |
1539 | instruction or not. When we encounter one of these ambiguous | |
1540 | cases, we'll set prev_insn_was_prologue_insn to 0 (false). | |
0df8b418 | 1541 | Otherwise, we'll assume that it really is a prologue instruction. */ |
ddb20c56 KB |
1542 | if (prev_insn_was_prologue_insn) |
1543 | last_prologue_pc = pc; | |
55d05f3b KB |
1544 | |
1545 | /* Stop scanning if we've hit the limit. */ | |
4e463ff5 | 1546 | if (pc >= lim_pc) |
55d05f3b KB |
1547 | break; |
1548 | ||
ddb20c56 KB |
1549 | prev_insn_was_prologue_insn = 1; |
1550 | ||
55d05f3b | 1551 | /* Fetch the instruction and convert it to an integer. */ |
ddb20c56 KB |
1552 | if (target_read_memory (pc, buf, 4)) |
1553 | break; | |
e17a4113 | 1554 | op = extract_unsigned_integer (buf, 4, byte_order); |
c906108c | 1555 | |
c5aa993b JM |
1556 | if ((op & 0xfc1fffff) == 0x7c0802a6) |
1557 | { /* mflr Rx */ | |
43b1ab88 AC |
1558 | /* Since shared library / PIC code, which needs to get its |
1559 | address at runtime, can appear to save more than one link | |
1560 | register vis: | |
1561 | ||
1562 | *INDENT-OFF* | |
1563 | stwu r1,-304(r1) | |
1564 | mflr r3 | |
1565 | bl 0xff570d0 (blrl) | |
1566 | stw r30,296(r1) | |
1567 | mflr r30 | |
1568 | stw r31,300(r1) | |
1569 | stw r3,308(r1); | |
1570 | ... | |
1571 | *INDENT-ON* | |
1572 | ||
1573 | remember just the first one, but skip over additional | |
1574 | ones. */ | |
721d14ba | 1575 | if (lr_reg == -1) |
46a9b8ed | 1576 | lr_reg = (op & 0x03e00000) >> 21; |
773df3e5 JB |
1577 | if (lr_reg == 0) |
1578 | r0_contains_arg = 0; | |
c5aa993b | 1579 | continue; |
c5aa993b JM |
1580 | } |
1581 | else if ((op & 0xfc1fffff) == 0x7c000026) | |
1582 | { /* mfcr Rx */ | |
98f08d3d | 1583 | cr_reg = (op & 0x03e00000); |
773df3e5 JB |
1584 | if (cr_reg == 0) |
1585 | r0_contains_arg = 0; | |
c5aa993b | 1586 | continue; |
c906108c | 1587 | |
c906108c | 1588 | } |
c5aa993b JM |
1589 | else if ((op & 0xfc1f0000) == 0xd8010000) |
1590 | { /* stfd Rx,NUM(r1) */ | |
1591 | reg = GET_SRC_REG (op); | |
1592 | if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg) | |
1593 | { | |
1594 | fdata->saved_fpr = reg; | |
1595 | fdata->fpr_offset = SIGNED_SHORT (op) + offset; | |
1596 | } | |
1597 | continue; | |
c906108c | 1598 | |
c5aa993b JM |
1599 | } |
1600 | else if (((op & 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */ | |
7a78ae4e ND |
1601 | (((op & 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */ |
1602 | (op & 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */ | |
1603 | (op & 0x03e00000) >= 0x01a00000)) /* rx >= r13 */ | |
c5aa993b JM |
1604 | { |
1605 | ||
1606 | reg = GET_SRC_REG (op); | |
46a9b8ed DJ |
1607 | if ((op & 0xfc1f0000) == 0xbc010000) |
1608 | fdata->gpr_mask |= ~((1U << reg) - 1); | |
1609 | else | |
1610 | fdata->gpr_mask |= 1U << reg; | |
c5aa993b JM |
1611 | if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg) |
1612 | { | |
1613 | fdata->saved_gpr = reg; | |
7a78ae4e | 1614 | if ((op & 0xfc1f0003) == 0xf8010000) |
98f08d3d | 1615 | op &= ~3UL; |
c5aa993b JM |
1616 | fdata->gpr_offset = SIGNED_SHORT (op) + offset; |
1617 | } | |
1618 | continue; | |
c906108c | 1619 | |
ddb20c56 | 1620 | } |
ef1bc9e7 AM |
1621 | else if ((op & 0xffff0000) == 0x3c4c0000 |
1622 | || (op & 0xffff0000) == 0x3c400000 | |
1623 | || (op & 0xffff0000) == 0x38420000) | |
1624 | { | |
1625 | /* . 0: addis 2,12,.TOC.-0b@ha | |
1626 | . addi 2,2,.TOC.-0b@l | |
1627 | or | |
1628 | . lis 2,.TOC.@ha | |
1629 | . addi 2,2,.TOC.@l | |
1630 | used by ELFv2 global entry points to set up r2. */ | |
1631 | continue; | |
1632 | } | |
1633 | else if (op == 0x60000000) | |
ddb20c56 | 1634 | { |
96ff0de4 | 1635 | /* nop */ |
ddb20c56 KB |
1636 | /* Allow nops in the prologue, but do not consider them to |
1637 | be part of the prologue unless followed by other prologue | |
0df8b418 | 1638 | instructions. */ |
ddb20c56 KB |
1639 | prev_insn_was_prologue_insn = 0; |
1640 | continue; | |
1641 | ||
c906108c | 1642 | } |
c5aa993b | 1643 | else if ((op & 0xffff0000) == 0x3c000000) |
ef1bc9e7 | 1644 | { /* addis 0,0,NUM, used for >= 32k frames */ |
c5aa993b JM |
1645 | fdata->offset = (op & 0x0000ffff) << 16; |
1646 | fdata->frameless = 0; | |
773df3e5 | 1647 | r0_contains_arg = 0; |
c5aa993b JM |
1648 | continue; |
1649 | ||
1650 | } | |
1651 | else if ((op & 0xffff0000) == 0x60000000) | |
ef1bc9e7 | 1652 | { /* ori 0,0,NUM, 2nd half of >= 32k frames */ |
c5aa993b JM |
1653 | fdata->offset |= (op & 0x0000ffff); |
1654 | fdata->frameless = 0; | |
773df3e5 | 1655 | r0_contains_arg = 0; |
c5aa993b JM |
1656 | continue; |
1657 | ||
1658 | } | |
be723e22 | 1659 | else if (lr_reg >= 0 && |
98f08d3d KB |
1660 | /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */ |
1661 | (((op & 0xffff0000) == (lr_reg | 0xf8010000)) || | |
1662 | /* stw Rx, NUM(r1) */ | |
1663 | ((op & 0xffff0000) == (lr_reg | 0x90010000)) || | |
1664 | /* stwu Rx, NUM(r1) */ | |
1665 | ((op & 0xffff0000) == (lr_reg | 0x94010000)))) | |
1666 | { /* where Rx == lr */ | |
1667 | fdata->lr_offset = offset; | |
c5aa993b | 1668 | fdata->nosavedpc = 0; |
be723e22 MS |
1669 | /* Invalidate lr_reg, but don't set it to -1. |
1670 | That would mean that it had never been set. */ | |
1671 | lr_reg = -2; | |
98f08d3d KB |
1672 | if ((op & 0xfc000003) == 0xf8000000 || /* std */ |
1673 | (op & 0xfc000000) == 0x90000000) /* stw */ | |
1674 | { | |
1675 | /* Does not update r1, so add displacement to lr_offset. */ | |
1676 | fdata->lr_offset += SIGNED_SHORT (op); | |
1677 | } | |
c5aa993b JM |
1678 | continue; |
1679 | ||
1680 | } | |
be723e22 | 1681 | else if (cr_reg >= 0 && |
98f08d3d KB |
1682 | /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */ |
1683 | (((op & 0xffff0000) == (cr_reg | 0xf8010000)) || | |
1684 | /* stw Rx, NUM(r1) */ | |
1685 | ((op & 0xffff0000) == (cr_reg | 0x90010000)) || | |
1686 | /* stwu Rx, NUM(r1) */ | |
1687 | ((op & 0xffff0000) == (cr_reg | 0x94010000)))) | |
1688 | { /* where Rx == cr */ | |
1689 | fdata->cr_offset = offset; | |
be723e22 MS |
1690 | /* Invalidate cr_reg, but don't set it to -1. |
1691 | That would mean that it had never been set. */ | |
1692 | cr_reg = -2; | |
98f08d3d KB |
1693 | if ((op & 0xfc000003) == 0xf8000000 || |
1694 | (op & 0xfc000000) == 0x90000000) | |
1695 | { | |
1696 | /* Does not update r1, so add displacement to cr_offset. */ | |
1697 | fdata->cr_offset += SIGNED_SHORT (op); | |
1698 | } | |
c5aa993b JM |
1699 | continue; |
1700 | ||
1701 | } | |
721d14ba DJ |
1702 | else if ((op & 0xfe80ffff) == 0x42800005 && lr_reg != -1) |
1703 | { | |
1704 | /* bcl 20,xx,.+4 is used to get the current PC, with or without | |
1705 | prediction bits. If the LR has already been saved, we can | |
1706 | skip it. */ | |
1707 | continue; | |
1708 | } | |
c5aa993b JM |
1709 | else if (op == 0x48000005) |
1710 | { /* bl .+4 used in | |
1711 | -mrelocatable */ | |
46a9b8ed | 1712 | fdata->used_bl = 1; |
c5aa993b JM |
1713 | continue; |
1714 | ||
1715 | } | |
1716 | else if (op == 0x48000004) | |
1717 | { /* b .+4 (xlc) */ | |
1718 | break; | |
1719 | ||
c5aa993b | 1720 | } |
6be8bc0c EZ |
1721 | else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used |
1722 | in V.4 -mminimal-toc */ | |
c5aa993b JM |
1723 | (op & 0xffff0000) == 0x3bde0000) |
1724 | { /* addi 30,30,foo@l */ | |
1725 | continue; | |
c906108c | 1726 | |
c5aa993b JM |
1727 | } |
1728 | else if ((op & 0xfc000001) == 0x48000001) | |
1729 | { /* bl foo, | |
0df8b418 | 1730 | to save fprs??? */ |
c906108c | 1731 | |
c5aa993b | 1732 | fdata->frameless = 0; |
3c77c82a DJ |
1733 | |
1734 | /* If the return address has already been saved, we can skip | |
1735 | calls to blrl (for PIC). */ | |
e17a4113 | 1736 | if (lr_reg != -1 && bl_to_blrl_insn_p (pc, op, byte_order)) |
46a9b8ed DJ |
1737 | { |
1738 | fdata->used_bl = 1; | |
1739 | continue; | |
1740 | } | |
3c77c82a | 1741 | |
6be8bc0c | 1742 | /* Don't skip over the subroutine call if it is not within |
ebd98106 FF |
1743 | the first three instructions of the prologue and either |
1744 | we have no line table information or the line info tells | |
1745 | us that the subroutine call is not part of the line | |
1746 | associated with the prologue. */ | |
c5aa993b | 1747 | if ((pc - orig_pc) > 8) |
ebd98106 FF |
1748 | { |
1749 | struct symtab_and_line prologue_sal = find_pc_line (orig_pc, 0); | |
1750 | struct symtab_and_line this_sal = find_pc_line (pc, 0); | |
1751 | ||
0df8b418 MS |
1752 | if ((prologue_sal.line == 0) |
1753 | || (prologue_sal.line != this_sal.line)) | |
ebd98106 FF |
1754 | break; |
1755 | } | |
c5aa993b | 1756 | |
e17a4113 | 1757 | op = read_memory_integer (pc + 4, 4, byte_order); |
c5aa993b | 1758 | |
6be8bc0c EZ |
1759 | /* At this point, make sure this is not a trampoline |
1760 | function (a function that simply calls another functions, | |
1761 | and nothing else). If the next is not a nop, this branch | |
0df8b418 | 1762 | was part of the function prologue. */ |
c5aa993b JM |
1763 | |
1764 | if (op == 0x4def7b82 || op == 0) /* crorc 15, 15, 15 */ | |
0df8b418 MS |
1765 | break; /* Don't skip over |
1766 | this branch. */ | |
c5aa993b | 1767 | |
46a9b8ed DJ |
1768 | fdata->used_bl = 1; |
1769 | continue; | |
c5aa993b | 1770 | } |
98f08d3d KB |
1771 | /* update stack pointer */ |
1772 | else if ((op & 0xfc1f0000) == 0x94010000) | |
1773 | { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */ | |
c5aa993b JM |
1774 | fdata->frameless = 0; |
1775 | fdata->offset = SIGNED_SHORT (op); | |
1776 | offset = fdata->offset; | |
1777 | continue; | |
c5aa993b | 1778 | } |
98f08d3d KB |
1779 | else if ((op & 0xfc1f016a) == 0x7c01016e) |
1780 | { /* stwux rX,r1,rY */ | |
0df8b418 | 1781 | /* No way to figure out what r1 is going to be. */ |
98f08d3d KB |
1782 | fdata->frameless = 0; |
1783 | offset = fdata->offset; | |
1784 | continue; | |
1785 | } | |
1786 | else if ((op & 0xfc1f0003) == 0xf8010001) | |
1787 | { /* stdu rX,NUM(r1) */ | |
1788 | fdata->frameless = 0; | |
1789 | fdata->offset = SIGNED_SHORT (op & ~3UL); | |
1790 | offset = fdata->offset; | |
1791 | continue; | |
1792 | } | |
1793 | else if ((op & 0xfc1f016a) == 0x7c01016a) | |
1794 | { /* stdux rX,r1,rY */ | |
0df8b418 | 1795 | /* No way to figure out what r1 is going to be. */ |
c5aa993b JM |
1796 | fdata->frameless = 0; |
1797 | offset = fdata->offset; | |
1798 | continue; | |
c5aa993b | 1799 | } |
7313566f FF |
1800 | else if ((op & 0xffff0000) == 0x38210000) |
1801 | { /* addi r1,r1,SIMM */ | |
1802 | fdata->frameless = 0; | |
1803 | fdata->offset += SIGNED_SHORT (op); | |
1804 | offset = fdata->offset; | |
1805 | continue; | |
1806 | } | |
4e463ff5 DJ |
1807 | /* Load up minimal toc pointer. Do not treat an epilogue restore |
1808 | of r31 as a minimal TOC load. */ | |
0df8b418 MS |
1809 | else if (((op >> 22) == 0x20f || /* l r31,... or l r30,... */ |
1810 | (op >> 22) == 0x3af) /* ld r31,... or ld r30,... */ | |
4e463ff5 | 1811 | && !framep |
c5aa993b | 1812 | && !minimal_toc_loaded) |
98f08d3d | 1813 | { |
c5aa993b JM |
1814 | minimal_toc_loaded = 1; |
1815 | continue; | |
1816 | ||
f6077098 KB |
1817 | /* move parameters from argument registers to local variable |
1818 | registers */ | |
1819 | } | |
1820 | else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */ | |
1821 | (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */ | |
1822 | (((op >> 21) & 31) <= 10) && | |
0df8b418 MS |
1823 | ((long) ((op >> 16) & 31) |
1824 | >= fdata->saved_gpr)) /* Rx: local var reg */ | |
f6077098 KB |
1825 | { |
1826 | continue; | |
1827 | ||
c5aa993b JM |
1828 | /* store parameters in stack */ |
1829 | } | |
e802b915 | 1830 | /* Move parameters from argument registers to temporary register. */ |
773df3e5 | 1831 | else if (store_param_on_stack_p (op, framep, &r0_contains_arg)) |
e802b915 | 1832 | { |
c5aa993b JM |
1833 | continue; |
1834 | ||
1835 | /* Set up frame pointer */ | |
1836 | } | |
76219d77 JB |
1837 | else if (op == 0x603d0000) /* oril r29, r1, 0x0 */ |
1838 | { | |
1839 | fdata->frameless = 0; | |
1840 | framep = 1; | |
1841 | fdata->alloca_reg = (tdep->ppc_gp0_regnum + 29); | |
1842 | continue; | |
1843 | ||
1844 | /* Another way to set up the frame pointer. */ | |
1845 | } | |
c5aa993b JM |
1846 | else if (op == 0x603f0000 /* oril r31, r1, 0x0 */ |
1847 | || op == 0x7c3f0b78) | |
1848 | { /* mr r31, r1 */ | |
1849 | fdata->frameless = 0; | |
1850 | framep = 1; | |
6f99cb26 | 1851 | fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31); |
c5aa993b JM |
1852 | continue; |
1853 | ||
1854 | /* Another way to set up the frame pointer. */ | |
1855 | } | |
1856 | else if ((op & 0xfc1fffff) == 0x38010000) | |
1857 | { /* addi rX, r1, 0x0 */ | |
1858 | fdata->frameless = 0; | |
1859 | framep = 1; | |
6f99cb26 AC |
1860 | fdata->alloca_reg = (tdep->ppc_gp0_regnum |
1861 | + ((op & ~0x38010000) >> 21)); | |
c5aa993b | 1862 | continue; |
c5aa993b | 1863 | } |
6be8bc0c EZ |
1864 | /* AltiVec related instructions. */ |
1865 | /* Store the vrsave register (spr 256) in another register for | |
1866 | later manipulation, or load a register into the vrsave | |
1867 | register. 2 instructions are used: mfvrsave and | |
1868 | mtvrsave. They are shorthand notation for mfspr Rn, SPR256 | |
1869 | and mtspr SPR256, Rn. */ | |
1870 | /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110 | |
1871 | mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */ | |
1872 | else if ((op & 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */ | |
1873 | { | |
1874 | vrsave_reg = GET_SRC_REG (op); | |
1875 | continue; | |
1876 | } | |
1877 | else if ((op & 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */ | |
1878 | { | |
1879 | continue; | |
1880 | } | |
1881 | /* Store the register where vrsave was saved to onto the stack: | |
1882 | rS is the register where vrsave was stored in a previous | |
1883 | instruction. */ | |
1884 | /* 100100 sssss 00001 dddddddd dddddddd */ | |
1885 | else if ((op & 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */ | |
1886 | { | |
1887 | if (vrsave_reg == GET_SRC_REG (op)) | |
1888 | { | |
1889 | fdata->vrsave_offset = SIGNED_SHORT (op) + offset; | |
1890 | vrsave_reg = -1; | |
1891 | } | |
1892 | continue; | |
1893 | } | |
1894 | /* Compute the new value of vrsave, by modifying the register | |
1895 | where vrsave was saved to. */ | |
1896 | else if (((op & 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */ | |
1897 | || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */ | |
1898 | { | |
1899 | continue; | |
1900 | } | |
1901 | /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first | |
1902 | in a pair of insns to save the vector registers on the | |
1903 | stack. */ | |
1904 | /* 001110 00000 00000 iiii iiii iiii iiii */ | |
96ff0de4 EZ |
1905 | /* 001110 01110 00000 iiii iiii iiii iiii */ |
1906 | else if ((op & 0xffff0000) == 0x38000000 /* li r0, SIMM */ | |
1907 | || (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */ | |
6be8bc0c | 1908 | { |
773df3e5 JB |
1909 | if ((op & 0xffff0000) == 0x38000000) |
1910 | r0_contains_arg = 0; | |
6be8bc0c EZ |
1911 | li_found_pc = pc; |
1912 | vr_saved_offset = SIGNED_SHORT (op); | |
773df3e5 JB |
1913 | |
1914 | /* This insn by itself is not part of the prologue, unless | |
0df8b418 | 1915 | if part of the pair of insns mentioned above. So do not |
773df3e5 JB |
1916 | record this insn as part of the prologue yet. */ |
1917 | prev_insn_was_prologue_insn = 0; | |
6be8bc0c EZ |
1918 | } |
1919 | /* Store vector register S at (r31+r0) aligned to 16 bytes. */ | |
1920 | /* 011111 sssss 11111 00000 00111001110 */ | |
1921 | else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */ | |
1922 | { | |
1923 | if (pc == (li_found_pc + 4)) | |
1924 | { | |
1925 | vr_reg = GET_SRC_REG (op); | |
1926 | /* If this is the first vector reg to be saved, or if | |
1927 | it has a lower number than others previously seen, | |
1928 | reupdate the frame info. */ | |
1929 | if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg) | |
1930 | { | |
1931 | fdata->saved_vr = vr_reg; | |
1932 | fdata->vr_offset = vr_saved_offset + offset; | |
1933 | } | |
1934 | vr_saved_offset = -1; | |
1935 | vr_reg = -1; | |
1936 | li_found_pc = 0; | |
1937 | } | |
1938 | } | |
1939 | /* End AltiVec related instructions. */ | |
96ff0de4 EZ |
1940 | |
1941 | /* Start BookE related instructions. */ | |
1942 | /* Store gen register S at (r31+uimm). | |
1943 | Any register less than r13 is volatile, so we don't care. */ | |
1944 | /* 000100 sssss 11111 iiiii 01100100001 */ | |
1945 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
1946 | && (op & 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */ | |
1947 | { | |
1948 | if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */ | |
1949 | { | |
1950 | unsigned int imm; | |
1951 | ev_reg = GET_SRC_REG (op); | |
1952 | imm = (op >> 11) & 0x1f; | |
1953 | ev_offset = imm * 8; | |
1954 | /* If this is the first vector reg to be saved, or if | |
1955 | it has a lower number than others previously seen, | |
1956 | reupdate the frame info. */ | |
1957 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) | |
1958 | { | |
1959 | fdata->saved_ev = ev_reg; | |
1960 | fdata->ev_offset = ev_offset + offset; | |
1961 | } | |
1962 | } | |
1963 | continue; | |
1964 | } | |
1965 | /* Store gen register rS at (r1+rB). */ | |
1966 | /* 000100 sssss 00001 bbbbb 01100100000 */ | |
1967 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
1968 | && (op & 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */ | |
1969 | { | |
1970 | if (pc == (li_found_pc + 4)) | |
1971 | { | |
1972 | ev_reg = GET_SRC_REG (op); | |
1973 | /* If this is the first vector reg to be saved, or if | |
1974 | it has a lower number than others previously seen, | |
1975 | reupdate the frame info. */ | |
1976 | /* We know the contents of rB from the previous instruction. */ | |
1977 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) | |
1978 | { | |
1979 | fdata->saved_ev = ev_reg; | |
1980 | fdata->ev_offset = vr_saved_offset + offset; | |
1981 | } | |
1982 | vr_saved_offset = -1; | |
1983 | ev_reg = -1; | |
1984 | li_found_pc = 0; | |
1985 | } | |
1986 | continue; | |
1987 | } | |
1988 | /* Store gen register r31 at (rA+uimm). */ | |
1989 | /* 000100 11111 aaaaa iiiii 01100100001 */ | |
1990 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
1991 | && (op & 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */ | |
1992 | { | |
1993 | /* Wwe know that the source register is 31 already, but | |
1994 | it can't hurt to compute it. */ | |
1995 | ev_reg = GET_SRC_REG (op); | |
1996 | ev_offset = ((op >> 11) & 0x1f) * 8; | |
1997 | /* If this is the first vector reg to be saved, or if | |
1998 | it has a lower number than others previously seen, | |
1999 | reupdate the frame info. */ | |
2000 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) | |
2001 | { | |
2002 | fdata->saved_ev = ev_reg; | |
2003 | fdata->ev_offset = ev_offset + offset; | |
2004 | } | |
2005 | ||
2006 | continue; | |
2007 | } | |
2008 | /* Store gen register S at (r31+r0). | |
2009 | Store param on stack when offset from SP bigger than 4 bytes. */ | |
2010 | /* 000100 sssss 11111 00000 01100100000 */ | |
2011 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
2012 | && (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */ | |
2013 | { | |
2014 | if (pc == (li_found_pc + 4)) | |
2015 | { | |
2016 | if ((op & 0x03e00000) >= 0x01a00000) | |
2017 | { | |
2018 | ev_reg = GET_SRC_REG (op); | |
2019 | /* If this is the first vector reg to be saved, or if | |
2020 | it has a lower number than others previously seen, | |
2021 | reupdate the frame info. */ | |
2022 | /* We know the contents of r0 from the previous | |
2023 | instruction. */ | |
2024 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) | |
2025 | { | |
2026 | fdata->saved_ev = ev_reg; | |
2027 | fdata->ev_offset = vr_saved_offset + offset; | |
2028 | } | |
2029 | ev_reg = -1; | |
2030 | } | |
2031 | vr_saved_offset = -1; | |
2032 | li_found_pc = 0; | |
2033 | continue; | |
2034 | } | |
2035 | } | |
2036 | /* End BookE related instructions. */ | |
2037 | ||
c5aa993b JM |
2038 | else |
2039 | { | |
46a9b8ed DJ |
2040 | unsigned int all_mask = ~((1U << fdata->saved_gpr) - 1); |
2041 | ||
55d05f3b KB |
2042 | /* Not a recognized prologue instruction. |
2043 | Handle optimizer code motions into the prologue by continuing | |
2044 | the search if we have no valid frame yet or if the return | |
46a9b8ed DJ |
2045 | address is not yet saved in the frame. Also skip instructions |
2046 | if some of the GPRs expected to be saved are not yet saved. */ | |
2047 | if (fdata->frameless == 0 && fdata->nosavedpc == 0 | |
2048 | && (fdata->gpr_mask & all_mask) == all_mask) | |
55d05f3b KB |
2049 | break; |
2050 | ||
2051 | if (op == 0x4e800020 /* blr */ | |
2052 | || op == 0x4e800420) /* bctr */ | |
2053 | /* Do not scan past epilogue in frameless functions or | |
2054 | trampolines. */ | |
2055 | break; | |
2056 | if ((op & 0xf4000000) == 0x40000000) /* bxx */ | |
64366f1c | 2057 | /* Never skip branches. */ |
55d05f3b KB |
2058 | break; |
2059 | ||
2060 | if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns) | |
2061 | /* Do not scan too many insns, scanning insns is expensive with | |
2062 | remote targets. */ | |
2063 | break; | |
2064 | ||
2065 | /* Continue scanning. */ | |
2066 | prev_insn_was_prologue_insn = 0; | |
2067 | continue; | |
c5aa993b | 2068 | } |
c906108c SS |
2069 | } |
2070 | ||
2071 | #if 0 | |
2072 | /* I have problems with skipping over __main() that I need to address | |
0df8b418 | 2073 | * sometime. Previously, I used to use misc_function_vector which |
c906108c SS |
2074 | * didn't work as well as I wanted to be. -MGO */ |
2075 | ||
2076 | /* If the first thing after skipping a prolog is a branch to a function, | |
2077 | this might be a call to an initializer in main(), introduced by gcc2. | |
64366f1c | 2078 | We'd like to skip over it as well. Fortunately, xlc does some extra |
c906108c | 2079 | work before calling a function right after a prologue, thus we can |
64366f1c | 2080 | single out such gcc2 behaviour. */ |
c906108c | 2081 | |
c906108c | 2082 | |
c5aa993b | 2083 | if ((op & 0xfc000001) == 0x48000001) |
0df8b418 | 2084 | { /* bl foo, an initializer function? */ |
e17a4113 | 2085 | op = read_memory_integer (pc + 4, 4, byte_order); |
c5aa993b JM |
2086 | |
2087 | if (op == 0x4def7b82) | |
2088 | { /* cror 0xf, 0xf, 0xf (nop) */ | |
c906108c | 2089 | |
64366f1c EZ |
2090 | /* Check and see if we are in main. If so, skip over this |
2091 | initializer function as well. */ | |
c906108c | 2092 | |
c5aa993b | 2093 | tmp = find_pc_misc_function (pc); |
6314a349 AC |
2094 | if (tmp >= 0 |
2095 | && strcmp (misc_function_vector[tmp].name, main_name ()) == 0) | |
c5aa993b JM |
2096 | return pc + 8; |
2097 | } | |
c906108c | 2098 | } |
c906108c | 2099 | #endif /* 0 */ |
c5aa993b | 2100 | |
46a9b8ed DJ |
2101 | if (pc == lim_pc && lr_reg >= 0) |
2102 | fdata->lr_register = lr_reg; | |
2103 | ||
c5aa993b | 2104 | fdata->offset = -fdata->offset; |
ddb20c56 | 2105 | return last_prologue_pc; |
c906108c SS |
2106 | } |
2107 | ||
7a78ae4e | 2108 | static CORE_ADDR |
4a7622d1 | 2109 | rs6000_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
c906108c | 2110 | { |
4a7622d1 | 2111 | struct rs6000_framedata frame; |
e3acb115 | 2112 | CORE_ADDR limit_pc, func_addr, func_end_addr = 0; |
c906108c | 2113 | |
4a7622d1 UW |
2114 | /* See if we can determine the end of the prologue via the symbol table. |
2115 | If so, then return either PC, or the PC after the prologue, whichever | |
2116 | is greater. */ | |
e3acb115 | 2117 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end_addr)) |
c5aa993b | 2118 | { |
d80b854b UW |
2119 | CORE_ADDR post_prologue_pc |
2120 | = skip_prologue_using_sal (gdbarch, func_addr); | |
4a7622d1 UW |
2121 | if (post_prologue_pc != 0) |
2122 | return max (pc, post_prologue_pc); | |
c906108c | 2123 | } |
c906108c | 2124 | |
4a7622d1 UW |
2125 | /* Can't determine prologue from the symbol table, need to examine |
2126 | instructions. */ | |
c906108c | 2127 | |
4a7622d1 UW |
2128 | /* Find an upper limit on the function prologue using the debug |
2129 | information. If the debug information could not be used to provide | |
2130 | that bound, then use an arbitrary large number as the upper bound. */ | |
d80b854b | 2131 | limit_pc = skip_prologue_using_sal (gdbarch, pc); |
4a7622d1 UW |
2132 | if (limit_pc == 0) |
2133 | limit_pc = pc + 100; /* Magic. */ | |
794a477a | 2134 | |
e3acb115 JB |
2135 | /* Do not allow limit_pc to be past the function end, if we know |
2136 | where that end is... */ | |
2137 | if (func_end_addr && limit_pc > func_end_addr) | |
2138 | limit_pc = func_end_addr; | |
2139 | ||
4a7622d1 UW |
2140 | pc = skip_prologue (gdbarch, pc, limit_pc, &frame); |
2141 | return pc; | |
c906108c | 2142 | } |
c906108c | 2143 | |
8ab3d180 KB |
2144 | /* When compiling for EABI, some versions of GCC emit a call to __eabi |
2145 | in the prologue of main(). | |
2146 | ||
2147 | The function below examines the code pointed at by PC and checks to | |
2148 | see if it corresponds to a call to __eabi. If so, it returns the | |
2149 | address of the instruction following that call. Otherwise, it simply | |
2150 | returns PC. */ | |
2151 | ||
63807e1d | 2152 | static CORE_ADDR |
8ab3d180 KB |
2153 | rs6000_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
2154 | { | |
e17a4113 | 2155 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
8ab3d180 KB |
2156 | gdb_byte buf[4]; |
2157 | unsigned long op; | |
2158 | ||
2159 | if (target_read_memory (pc, buf, 4)) | |
2160 | return pc; | |
e17a4113 | 2161 | op = extract_unsigned_integer (buf, 4, byte_order); |
8ab3d180 KB |
2162 | |
2163 | if ((op & BL_MASK) == BL_INSTRUCTION) | |
2164 | { | |
2165 | CORE_ADDR displ = op & BL_DISPLACEMENT_MASK; | |
2166 | CORE_ADDR call_dest = pc + 4 + displ; | |
7cbd4a93 | 2167 | struct bound_minimal_symbol s = lookup_minimal_symbol_by_pc (call_dest); |
8ab3d180 KB |
2168 | |
2169 | /* We check for ___eabi (three leading underscores) in addition | |
2170 | to __eabi in case the GCC option "-fleading-underscore" was | |
2171 | used to compile the program. */ | |
7cbd4a93 | 2172 | if (s.minsym != NULL |
efd66ac6 TT |
2173 | && MSYMBOL_LINKAGE_NAME (s.minsym) != NULL |
2174 | && (strcmp (MSYMBOL_LINKAGE_NAME (s.minsym), "__eabi") == 0 | |
2175 | || strcmp (MSYMBOL_LINKAGE_NAME (s.minsym), "___eabi") == 0)) | |
8ab3d180 KB |
2176 | pc += 4; |
2177 | } | |
2178 | return pc; | |
2179 | } | |
383f0f5b | 2180 | |
4a7622d1 UW |
2181 | /* All the ABI's require 16 byte alignment. */ |
2182 | static CORE_ADDR | |
2183 | rs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
2184 | { | |
2185 | return (addr & -16); | |
c906108c SS |
2186 | } |
2187 | ||
977adac5 ND |
2188 | /* Return whether handle_inferior_event() should proceed through code |
2189 | starting at PC in function NAME when stepping. | |
2190 | ||
2191 | The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to | |
2192 | handle memory references that are too distant to fit in instructions | |
2193 | generated by the compiler. For example, if 'foo' in the following | |
2194 | instruction: | |
2195 | ||
2196 | lwz r9,foo(r2) | |
2197 | ||
2198 | is greater than 32767, the linker might replace the lwz with a branch to | |
2199 | somewhere in @FIX1 that does the load in 2 instructions and then branches | |
2200 | back to where execution should continue. | |
2201 | ||
2202 | GDB should silently step over @FIX code, just like AIX dbx does. | |
2ec664f5 MS |
2203 | Unfortunately, the linker uses the "b" instruction for the |
2204 | branches, meaning that the link register doesn't get set. | |
2205 | Therefore, GDB's usual step_over_function () mechanism won't work. | |
977adac5 | 2206 | |
e76f05fa UW |
2207 | Instead, use the gdbarch_skip_trampoline_code and |
2208 | gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past | |
2ec664f5 | 2209 | @FIX code. */ |
977adac5 | 2210 | |
63807e1d | 2211 | static int |
e17a4113 | 2212 | rs6000_in_solib_return_trampoline (struct gdbarch *gdbarch, |
2c02bd72 | 2213 | CORE_ADDR pc, const char *name) |
977adac5 ND |
2214 | { |
2215 | return name && !strncmp (name, "@FIX", 4); | |
2216 | } | |
2217 | ||
2218 | /* Skip code that the user doesn't want to see when stepping: | |
2219 | ||
2220 | 1. Indirect function calls use a piece of trampoline code to do context | |
2221 | switching, i.e. to set the new TOC table. Skip such code if we are on | |
2222 | its first instruction (as when we have single-stepped to here). | |
2223 | ||
2224 | 2. Skip shared library trampoline code (which is different from | |
c906108c | 2225 | indirect function call trampolines). |
977adac5 ND |
2226 | |
2227 | 3. Skip bigtoc fixup code. | |
2228 | ||
c906108c | 2229 | Result is desired PC to step until, or NULL if we are not in |
977adac5 | 2230 | code that should be skipped. */ |
c906108c | 2231 | |
63807e1d | 2232 | static CORE_ADDR |
52f729a7 | 2233 | rs6000_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 2234 | { |
e17a4113 UW |
2235 | struct gdbarch *gdbarch = get_frame_arch (frame); |
2236 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2237 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
52f0bd74 | 2238 | unsigned int ii, op; |
977adac5 | 2239 | int rel; |
c906108c | 2240 | CORE_ADDR solib_target_pc; |
7cbd4a93 | 2241 | struct bound_minimal_symbol msymbol; |
c906108c | 2242 | |
c5aa993b JM |
2243 | static unsigned trampoline_code[] = |
2244 | { | |
2245 | 0x800b0000, /* l r0,0x0(r11) */ | |
2246 | 0x90410014, /* st r2,0x14(r1) */ | |
2247 | 0x7c0903a6, /* mtctr r0 */ | |
2248 | 0x804b0004, /* l r2,0x4(r11) */ | |
2249 | 0x816b0008, /* l r11,0x8(r11) */ | |
2250 | 0x4e800420, /* bctr */ | |
2251 | 0x4e800020, /* br */ | |
2252 | 0 | |
c906108c SS |
2253 | }; |
2254 | ||
977adac5 ND |
2255 | /* Check for bigtoc fixup code. */ |
2256 | msymbol = lookup_minimal_symbol_by_pc (pc); | |
7cbd4a93 | 2257 | if (msymbol.minsym |
e17a4113 | 2258 | && rs6000_in_solib_return_trampoline (gdbarch, pc, |
efd66ac6 | 2259 | MSYMBOL_LINKAGE_NAME (msymbol.minsym))) |
977adac5 ND |
2260 | { |
2261 | /* Double-check that the third instruction from PC is relative "b". */ | |
e17a4113 | 2262 | op = read_memory_integer (pc + 8, 4, byte_order); |
977adac5 ND |
2263 | if ((op & 0xfc000003) == 0x48000000) |
2264 | { | |
2265 | /* Extract bits 6-29 as a signed 24-bit relative word address and | |
2266 | add it to the containing PC. */ | |
2267 | rel = ((int)(op << 6) >> 6); | |
2268 | return pc + 8 + rel; | |
2269 | } | |
2270 | } | |
2271 | ||
c906108c | 2272 | /* If pc is in a shared library trampoline, return its target. */ |
52f729a7 | 2273 | solib_target_pc = find_solib_trampoline_target (frame, pc); |
c906108c SS |
2274 | if (solib_target_pc) |
2275 | return solib_target_pc; | |
2276 | ||
c5aa993b JM |
2277 | for (ii = 0; trampoline_code[ii]; ++ii) |
2278 | { | |
e17a4113 | 2279 | op = read_memory_integer (pc + (ii * 4), 4, byte_order); |
c5aa993b JM |
2280 | if (op != trampoline_code[ii]) |
2281 | return 0; | |
2282 | } | |
0df8b418 MS |
2283 | ii = get_frame_register_unsigned (frame, 11); /* r11 holds destination |
2284 | addr. */ | |
e17a4113 | 2285 | pc = read_memory_unsigned_integer (ii, tdep->wordsize, byte_order); |
c906108c SS |
2286 | return pc; |
2287 | } | |
2288 | ||
794ac428 UW |
2289 | /* ISA-specific vector types. */ |
2290 | ||
2291 | static struct type * | |
2292 | rs6000_builtin_type_vec64 (struct gdbarch *gdbarch) | |
2293 | { | |
2294 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2295 | ||
2296 | if (!tdep->ppc_builtin_type_vec64) | |
2297 | { | |
df4df182 UW |
2298 | const struct builtin_type *bt = builtin_type (gdbarch); |
2299 | ||
794ac428 UW |
2300 | /* The type we're building is this: */ |
2301 | #if 0 | |
2302 | union __gdb_builtin_type_vec64 | |
2303 | { | |
2304 | int64_t uint64; | |
2305 | float v2_float[2]; | |
2306 | int32_t v2_int32[2]; | |
2307 | int16_t v4_int16[4]; | |
2308 | int8_t v8_int8[8]; | |
2309 | }; | |
2310 | #endif | |
2311 | ||
2312 | struct type *t; | |
2313 | ||
e9bb382b UW |
2314 | t = arch_composite_type (gdbarch, |
2315 | "__ppc_builtin_type_vec64", TYPE_CODE_UNION); | |
df4df182 | 2316 | append_composite_type_field (t, "uint64", bt->builtin_int64); |
794ac428 | 2317 | append_composite_type_field (t, "v2_float", |
df4df182 | 2318 | init_vector_type (bt->builtin_float, 2)); |
794ac428 | 2319 | append_composite_type_field (t, "v2_int32", |
df4df182 | 2320 | init_vector_type (bt->builtin_int32, 2)); |
794ac428 | 2321 | append_composite_type_field (t, "v4_int16", |
df4df182 | 2322 | init_vector_type (bt->builtin_int16, 4)); |
794ac428 | 2323 | append_composite_type_field (t, "v8_int8", |
df4df182 | 2324 | init_vector_type (bt->builtin_int8, 8)); |
794ac428 | 2325 | |
876cecd0 | 2326 | TYPE_VECTOR (t) = 1; |
794ac428 UW |
2327 | TYPE_NAME (t) = "ppc_builtin_type_vec64"; |
2328 | tdep->ppc_builtin_type_vec64 = t; | |
2329 | } | |
2330 | ||
2331 | return tdep->ppc_builtin_type_vec64; | |
2332 | } | |
2333 | ||
604c2f83 LM |
2334 | /* Vector 128 type. */ |
2335 | ||
2336 | static struct type * | |
2337 | rs6000_builtin_type_vec128 (struct gdbarch *gdbarch) | |
2338 | { | |
2339 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2340 | ||
2341 | if (!tdep->ppc_builtin_type_vec128) | |
2342 | { | |
df4df182 UW |
2343 | const struct builtin_type *bt = builtin_type (gdbarch); |
2344 | ||
604c2f83 LM |
2345 | /* The type we're building is this |
2346 | ||
2347 | type = union __ppc_builtin_type_vec128 { | |
2348 | uint128_t uint128; | |
db9f5df8 | 2349 | double v2_double[2]; |
604c2f83 LM |
2350 | float v4_float[4]; |
2351 | int32_t v4_int32[4]; | |
2352 | int16_t v8_int16[8]; | |
2353 | int8_t v16_int8[16]; | |
2354 | } | |
2355 | */ | |
2356 | ||
2357 | struct type *t; | |
2358 | ||
e9bb382b UW |
2359 | t = arch_composite_type (gdbarch, |
2360 | "__ppc_builtin_type_vec128", TYPE_CODE_UNION); | |
df4df182 | 2361 | append_composite_type_field (t, "uint128", bt->builtin_uint128); |
db9f5df8 UW |
2362 | append_composite_type_field (t, "v2_double", |
2363 | init_vector_type (bt->builtin_double, 2)); | |
604c2f83 | 2364 | append_composite_type_field (t, "v4_float", |
df4df182 | 2365 | init_vector_type (bt->builtin_float, 4)); |
604c2f83 | 2366 | append_composite_type_field (t, "v4_int32", |
df4df182 | 2367 | init_vector_type (bt->builtin_int32, 4)); |
604c2f83 | 2368 | append_composite_type_field (t, "v8_int16", |
df4df182 | 2369 | init_vector_type (bt->builtin_int16, 8)); |
604c2f83 | 2370 | append_composite_type_field (t, "v16_int8", |
df4df182 | 2371 | init_vector_type (bt->builtin_int8, 16)); |
604c2f83 | 2372 | |
803e1097 | 2373 | TYPE_VECTOR (t) = 1; |
604c2f83 LM |
2374 | TYPE_NAME (t) = "ppc_builtin_type_vec128"; |
2375 | tdep->ppc_builtin_type_vec128 = t; | |
2376 | } | |
2377 | ||
2378 | return tdep->ppc_builtin_type_vec128; | |
2379 | } | |
2380 | ||
7cc46491 DJ |
2381 | /* Return the name of register number REGNO, or the empty string if it |
2382 | is an anonymous register. */ | |
7a78ae4e | 2383 | |
fa88f677 | 2384 | static const char * |
d93859e2 | 2385 | rs6000_register_name (struct gdbarch *gdbarch, int regno) |
7a78ae4e | 2386 | { |
d93859e2 | 2387 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7a78ae4e | 2388 | |
7cc46491 DJ |
2389 | /* The upper half "registers" have names in the XML description, |
2390 | but we present only the low GPRs and the full 64-bit registers | |
2391 | to the user. */ | |
2392 | if (tdep->ppc_ev0_upper_regnum >= 0 | |
2393 | && tdep->ppc_ev0_upper_regnum <= regno | |
2394 | && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) | |
2395 | return ""; | |
2396 | ||
604c2f83 LM |
2397 | /* Hide the upper halves of the vs0~vs31 registers. */ |
2398 | if (tdep->ppc_vsr0_regnum >= 0 | |
2399 | && tdep->ppc_vsr0_upper_regnum <= regno | |
2400 | && regno < tdep->ppc_vsr0_upper_regnum + ppc_num_gprs) | |
2401 | return ""; | |
2402 | ||
7cc46491 | 2403 | /* Check if the SPE pseudo registers are available. */ |
5a9e69ba | 2404 | if (IS_SPE_PSEUDOREG (tdep, regno)) |
7cc46491 DJ |
2405 | { |
2406 | static const char *const spe_regnames[] = { | |
2407 | "ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7", | |
2408 | "ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15", | |
2409 | "ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23", | |
2410 | "ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31", | |
2411 | }; | |
2412 | return spe_regnames[regno - tdep->ppc_ev0_regnum]; | |
2413 | } | |
2414 | ||
f949c649 TJB |
2415 | /* Check if the decimal128 pseudo-registers are available. */ |
2416 | if (IS_DFP_PSEUDOREG (tdep, regno)) | |
2417 | { | |
2418 | static const char *const dfp128_regnames[] = { | |
2419 | "dl0", "dl1", "dl2", "dl3", | |
2420 | "dl4", "dl5", "dl6", "dl7", | |
2421 | "dl8", "dl9", "dl10", "dl11", | |
2422 | "dl12", "dl13", "dl14", "dl15" | |
2423 | }; | |
2424 | return dfp128_regnames[regno - tdep->ppc_dl0_regnum]; | |
2425 | } | |
2426 | ||
604c2f83 LM |
2427 | /* Check if this is a VSX pseudo-register. */ |
2428 | if (IS_VSX_PSEUDOREG (tdep, regno)) | |
2429 | { | |
2430 | static const char *const vsx_regnames[] = { | |
2431 | "vs0", "vs1", "vs2", "vs3", "vs4", "vs5", "vs6", "vs7", | |
2432 | "vs8", "vs9", "vs10", "vs11", "vs12", "vs13", "vs14", | |
2433 | "vs15", "vs16", "vs17", "vs18", "vs19", "vs20", "vs21", | |
2434 | "vs22", "vs23", "vs24", "vs25", "vs26", "vs27", "vs28", | |
2435 | "vs29", "vs30", "vs31", "vs32", "vs33", "vs34", "vs35", | |
2436 | "vs36", "vs37", "vs38", "vs39", "vs40", "vs41", "vs42", | |
2437 | "vs43", "vs44", "vs45", "vs46", "vs47", "vs48", "vs49", | |
2438 | "vs50", "vs51", "vs52", "vs53", "vs54", "vs55", "vs56", | |
2439 | "vs57", "vs58", "vs59", "vs60", "vs61", "vs62", "vs63" | |
2440 | }; | |
2441 | return vsx_regnames[regno - tdep->ppc_vsr0_regnum]; | |
2442 | } | |
2443 | ||
2444 | /* Check if the this is a Extended FP pseudo-register. */ | |
2445 | if (IS_EFP_PSEUDOREG (tdep, regno)) | |
2446 | { | |
2447 | static const char *const efpr_regnames[] = { | |
2448 | "f32", "f33", "f34", "f35", "f36", "f37", "f38", | |
2449 | "f39", "f40", "f41", "f42", "f43", "f44", "f45", | |
2450 | "f46", "f47", "f48", "f49", "f50", "f51", | |
2451 | "f52", "f53", "f54", "f55", "f56", "f57", | |
2452 | "f58", "f59", "f60", "f61", "f62", "f63" | |
2453 | }; | |
2454 | return efpr_regnames[regno - tdep->ppc_efpr0_regnum]; | |
2455 | } | |
2456 | ||
d93859e2 | 2457 | return tdesc_register_name (gdbarch, regno); |
7a78ae4e ND |
2458 | } |
2459 | ||
7cc46491 DJ |
2460 | /* Return the GDB type object for the "standard" data type of data in |
2461 | register N. */ | |
7a78ae4e ND |
2462 | |
2463 | static struct type * | |
7cc46491 | 2464 | rs6000_pseudo_register_type (struct gdbarch *gdbarch, int regnum) |
7a78ae4e | 2465 | { |
691d145a | 2466 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7a78ae4e | 2467 | |
7cc46491 | 2468 | /* These are the only pseudo-registers we support. */ |
f949c649 | 2469 | gdb_assert (IS_SPE_PSEUDOREG (tdep, regnum) |
604c2f83 LM |
2470 | || IS_DFP_PSEUDOREG (tdep, regnum) |
2471 | || IS_VSX_PSEUDOREG (tdep, regnum) | |
2472 | || IS_EFP_PSEUDOREG (tdep, regnum)); | |
7cc46491 | 2473 | |
f949c649 TJB |
2474 | /* These are the e500 pseudo-registers. */ |
2475 | if (IS_SPE_PSEUDOREG (tdep, regnum)) | |
2476 | return rs6000_builtin_type_vec64 (gdbarch); | |
604c2f83 LM |
2477 | else if (IS_DFP_PSEUDOREG (tdep, regnum)) |
2478 | /* PPC decimal128 pseudo-registers. */ | |
f949c649 | 2479 | return builtin_type (gdbarch)->builtin_declong; |
604c2f83 LM |
2480 | else if (IS_VSX_PSEUDOREG (tdep, regnum)) |
2481 | /* POWER7 VSX pseudo-registers. */ | |
2482 | return rs6000_builtin_type_vec128 (gdbarch); | |
2483 | else | |
2484 | /* POWER7 Extended FP pseudo-registers. */ | |
2485 | return builtin_type (gdbarch)->builtin_double; | |
7a78ae4e ND |
2486 | } |
2487 | ||
c44ca51c AC |
2488 | /* Is REGNUM a member of REGGROUP? */ |
2489 | static int | |
7cc46491 DJ |
2490 | rs6000_pseudo_register_reggroup_p (struct gdbarch *gdbarch, int regnum, |
2491 | struct reggroup *group) | |
c44ca51c AC |
2492 | { |
2493 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
c44ca51c | 2494 | |
7cc46491 | 2495 | /* These are the only pseudo-registers we support. */ |
f949c649 | 2496 | gdb_assert (IS_SPE_PSEUDOREG (tdep, regnum) |
604c2f83 LM |
2497 | || IS_DFP_PSEUDOREG (tdep, regnum) |
2498 | || IS_VSX_PSEUDOREG (tdep, regnum) | |
2499 | || IS_EFP_PSEUDOREG (tdep, regnum)); | |
c44ca51c | 2500 | |
604c2f83 LM |
2501 | /* These are the e500 pseudo-registers or the POWER7 VSX registers. */ |
2502 | if (IS_SPE_PSEUDOREG (tdep, regnum) || IS_VSX_PSEUDOREG (tdep, regnum)) | |
f949c649 | 2503 | return group == all_reggroup || group == vector_reggroup; |
7cc46491 | 2504 | else |
604c2f83 | 2505 | /* PPC decimal128 or Extended FP pseudo-registers. */ |
f949c649 | 2506 | return group == all_reggroup || group == float_reggroup; |
c44ca51c AC |
2507 | } |
2508 | ||
691d145a | 2509 | /* The register format for RS/6000 floating point registers is always |
64366f1c | 2510 | double, we need a conversion if the memory format is float. */ |
7a78ae4e ND |
2511 | |
2512 | static int | |
0abe36f5 MD |
2513 | rs6000_convert_register_p (struct gdbarch *gdbarch, int regnum, |
2514 | struct type *type) | |
7a78ae4e | 2515 | { |
0abe36f5 | 2516 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7cc46491 DJ |
2517 | |
2518 | return (tdep->ppc_fp0_regnum >= 0 | |
2519 | && regnum >= tdep->ppc_fp0_regnum | |
2520 | && regnum < tdep->ppc_fp0_regnum + ppc_num_fprs | |
2521 | && TYPE_CODE (type) == TYPE_CODE_FLT | |
0dfff4cb UW |
2522 | && TYPE_LENGTH (type) |
2523 | != TYPE_LENGTH (builtin_type (gdbarch)->builtin_double)); | |
7a78ae4e ND |
2524 | } |
2525 | ||
8dccd430 | 2526 | static int |
691d145a JB |
2527 | rs6000_register_to_value (struct frame_info *frame, |
2528 | int regnum, | |
2529 | struct type *type, | |
8dccd430 PA |
2530 | gdb_byte *to, |
2531 | int *optimizedp, int *unavailablep) | |
7a78ae4e | 2532 | { |
0dfff4cb | 2533 | struct gdbarch *gdbarch = get_frame_arch (frame); |
50fd1280 | 2534 | gdb_byte from[MAX_REGISTER_SIZE]; |
691d145a | 2535 | |
691d145a | 2536 | gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT); |
7a78ae4e | 2537 | |
8dccd430 PA |
2538 | if (!get_frame_register_bytes (frame, regnum, 0, |
2539 | register_size (gdbarch, regnum), | |
2540 | from, optimizedp, unavailablep)) | |
2541 | return 0; | |
2542 | ||
0dfff4cb UW |
2543 | convert_typed_floating (from, builtin_type (gdbarch)->builtin_double, |
2544 | to, type); | |
8dccd430 PA |
2545 | *optimizedp = *unavailablep = 0; |
2546 | return 1; | |
691d145a | 2547 | } |
7a292a7a | 2548 | |
7a78ae4e | 2549 | static void |
691d145a JB |
2550 | rs6000_value_to_register (struct frame_info *frame, |
2551 | int regnum, | |
2552 | struct type *type, | |
50fd1280 | 2553 | const gdb_byte *from) |
7a78ae4e | 2554 | { |
0dfff4cb | 2555 | struct gdbarch *gdbarch = get_frame_arch (frame); |
50fd1280 | 2556 | gdb_byte to[MAX_REGISTER_SIZE]; |
691d145a | 2557 | |
691d145a JB |
2558 | gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT); |
2559 | ||
0dfff4cb UW |
2560 | convert_typed_floating (from, type, |
2561 | to, builtin_type (gdbarch)->builtin_double); | |
691d145a | 2562 | put_frame_register (frame, regnum, to); |
7a78ae4e | 2563 | } |
c906108c | 2564 | |
05d1431c PA |
2565 | /* The type of a function that moves the value of REG between CACHE |
2566 | or BUF --- in either direction. */ | |
2567 | typedef enum register_status (*move_ev_register_func) (struct regcache *, | |
2568 | int, void *); | |
2569 | ||
6ced10dd JB |
2570 | /* Move SPE vector register values between a 64-bit buffer and the two |
2571 | 32-bit raw register halves in a regcache. This function handles | |
2572 | both splitting a 64-bit value into two 32-bit halves, and joining | |
2573 | two halves into a whole 64-bit value, depending on the function | |
2574 | passed as the MOVE argument. | |
2575 | ||
2576 | EV_REG must be the number of an SPE evN vector register --- a | |
2577 | pseudoregister. REGCACHE must be a regcache, and BUFFER must be a | |
2578 | 64-bit buffer. | |
2579 | ||
2580 | Call MOVE once for each 32-bit half of that register, passing | |
2581 | REGCACHE, the number of the raw register corresponding to that | |
2582 | half, and the address of the appropriate half of BUFFER. | |
2583 | ||
2584 | For example, passing 'regcache_raw_read' as the MOVE function will | |
2585 | fill BUFFER with the full 64-bit contents of EV_REG. Or, passing | |
2586 | 'regcache_raw_supply' will supply the contents of BUFFER to the | |
2587 | appropriate pair of raw registers in REGCACHE. | |
2588 | ||
2589 | You may need to cast away some 'const' qualifiers when passing | |
2590 | MOVE, since this function can't tell at compile-time which of | |
2591 | REGCACHE or BUFFER is acting as the source of the data. If C had | |
2592 | co-variant type qualifiers, ... */ | |
05d1431c PA |
2593 | |
2594 | static enum register_status | |
2595 | e500_move_ev_register (move_ev_register_func move, | |
2596 | struct regcache *regcache, int ev_reg, void *buffer) | |
6ced10dd JB |
2597 | { |
2598 | struct gdbarch *arch = get_regcache_arch (regcache); | |
2599 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); | |
2600 | int reg_index; | |
50fd1280 | 2601 | gdb_byte *byte_buffer = buffer; |
05d1431c | 2602 | enum register_status status; |
6ced10dd | 2603 | |
5a9e69ba | 2604 | gdb_assert (IS_SPE_PSEUDOREG (tdep, ev_reg)); |
6ced10dd JB |
2605 | |
2606 | reg_index = ev_reg - tdep->ppc_ev0_regnum; | |
2607 | ||
8b164abb | 2608 | if (gdbarch_byte_order (arch) == BFD_ENDIAN_BIG) |
6ced10dd | 2609 | { |
05d1431c PA |
2610 | status = move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, |
2611 | byte_buffer); | |
2612 | if (status == REG_VALID) | |
2613 | status = move (regcache, tdep->ppc_gp0_regnum + reg_index, | |
2614 | byte_buffer + 4); | |
6ced10dd JB |
2615 | } |
2616 | else | |
2617 | { | |
05d1431c PA |
2618 | status = move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer); |
2619 | if (status == REG_VALID) | |
2620 | status = move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, | |
2621 | byte_buffer + 4); | |
6ced10dd | 2622 | } |
05d1431c PA |
2623 | |
2624 | return status; | |
6ced10dd JB |
2625 | } |
2626 | ||
05d1431c PA |
2627 | static enum register_status |
2628 | do_regcache_raw_read (struct regcache *regcache, int regnum, void *buffer) | |
2629 | { | |
2630 | return regcache_raw_read (regcache, regnum, buffer); | |
2631 | } | |
2632 | ||
2633 | static enum register_status | |
2634 | do_regcache_raw_write (struct regcache *regcache, int regnum, void *buffer) | |
2635 | { | |
2636 | regcache_raw_write (regcache, regnum, buffer); | |
2637 | ||
2638 | return REG_VALID; | |
2639 | } | |
2640 | ||
2641 | static enum register_status | |
c8001721 | 2642 | e500_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, |
50fd1280 | 2643 | int reg_nr, gdb_byte *buffer) |
f949c649 | 2644 | { |
05d1431c | 2645 | return e500_move_ev_register (do_regcache_raw_read, regcache, reg_nr, buffer); |
f949c649 TJB |
2646 | } |
2647 | ||
2648 | static void | |
2649 | e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
2650 | int reg_nr, const gdb_byte *buffer) | |
2651 | { | |
05d1431c PA |
2652 | e500_move_ev_register (do_regcache_raw_write, regcache, |
2653 | reg_nr, (void *) buffer); | |
f949c649 TJB |
2654 | } |
2655 | ||
604c2f83 | 2656 | /* Read method for DFP pseudo-registers. */ |
05d1431c | 2657 | static enum register_status |
604c2f83 | 2658 | dfp_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, |
f949c649 TJB |
2659 | int reg_nr, gdb_byte *buffer) |
2660 | { | |
2661 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2662 | int reg_index = reg_nr - tdep->ppc_dl0_regnum; | |
05d1431c | 2663 | enum register_status status; |
f949c649 TJB |
2664 | |
2665 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
2666 | { | |
2667 | /* Read two FP registers to form a whole dl register. */ | |
05d1431c PA |
2668 | status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum + |
2669 | 2 * reg_index, buffer); | |
2670 | if (status == REG_VALID) | |
2671 | status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum + | |
2672 | 2 * reg_index + 1, buffer + 8); | |
f949c649 TJB |
2673 | } |
2674 | else | |
2675 | { | |
05d1431c | 2676 | status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum + |
0ff3e01f | 2677 | 2 * reg_index + 1, buffer); |
05d1431c PA |
2678 | if (status == REG_VALID) |
2679 | status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum + | |
0ff3e01f | 2680 | 2 * reg_index, buffer + 8); |
f949c649 | 2681 | } |
05d1431c PA |
2682 | |
2683 | return status; | |
f949c649 TJB |
2684 | } |
2685 | ||
604c2f83 | 2686 | /* Write method for DFP pseudo-registers. */ |
f949c649 | 2687 | static void |
604c2f83 | 2688 | dfp_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, |
f949c649 TJB |
2689 | int reg_nr, const gdb_byte *buffer) |
2690 | { | |
2691 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2692 | int reg_index = reg_nr - tdep->ppc_dl0_regnum; | |
2693 | ||
2694 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
2695 | { | |
2696 | /* Write each half of the dl register into a separate | |
2697 | FP register. */ | |
2698 | regcache_raw_write (regcache, tdep->ppc_fp0_regnum + | |
2699 | 2 * reg_index, buffer); | |
2700 | regcache_raw_write (regcache, tdep->ppc_fp0_regnum + | |
2701 | 2 * reg_index + 1, buffer + 8); | |
2702 | } | |
2703 | else | |
2704 | { | |
2705 | regcache_raw_write (regcache, tdep->ppc_fp0_regnum + | |
0ff3e01f | 2706 | 2 * reg_index + 1, buffer); |
f949c649 | 2707 | regcache_raw_write (regcache, tdep->ppc_fp0_regnum + |
0ff3e01f | 2708 | 2 * reg_index, buffer + 8); |
f949c649 TJB |
2709 | } |
2710 | } | |
2711 | ||
604c2f83 | 2712 | /* Read method for POWER7 VSX pseudo-registers. */ |
05d1431c | 2713 | static enum register_status |
604c2f83 LM |
2714 | vsx_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, |
2715 | int reg_nr, gdb_byte *buffer) | |
2716 | { | |
2717 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2718 | int reg_index = reg_nr - tdep->ppc_vsr0_regnum; | |
05d1431c | 2719 | enum register_status status; |
604c2f83 LM |
2720 | |
2721 | /* Read the portion that overlaps the VMX registers. */ | |
2722 | if (reg_index > 31) | |
05d1431c PA |
2723 | status = regcache_raw_read (regcache, tdep->ppc_vr0_regnum + |
2724 | reg_index - 32, buffer); | |
604c2f83 LM |
2725 | else |
2726 | /* Read the portion that overlaps the FPR registers. */ | |
2727 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
2728 | { | |
05d1431c PA |
2729 | status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum + |
2730 | reg_index, buffer); | |
2731 | if (status == REG_VALID) | |
2732 | status = regcache_raw_read (regcache, tdep->ppc_vsr0_upper_regnum + | |
2733 | reg_index, buffer + 8); | |
604c2f83 LM |
2734 | } |
2735 | else | |
2736 | { | |
05d1431c PA |
2737 | status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum + |
2738 | reg_index, buffer + 8); | |
2739 | if (status == REG_VALID) | |
2740 | status = regcache_raw_read (regcache, tdep->ppc_vsr0_upper_regnum + | |
2741 | reg_index, buffer); | |
604c2f83 | 2742 | } |
05d1431c PA |
2743 | |
2744 | return status; | |
604c2f83 LM |
2745 | } |
2746 | ||
2747 | /* Write method for POWER7 VSX pseudo-registers. */ | |
2748 | static void | |
2749 | vsx_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
2750 | int reg_nr, const gdb_byte *buffer) | |
2751 | { | |
2752 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2753 | int reg_index = reg_nr - tdep->ppc_vsr0_regnum; | |
2754 | ||
2755 | /* Write the portion that overlaps the VMX registers. */ | |
2756 | if (reg_index > 31) | |
2757 | regcache_raw_write (regcache, tdep->ppc_vr0_regnum + | |
2758 | reg_index - 32, buffer); | |
2759 | else | |
2760 | /* Write the portion that overlaps the FPR registers. */ | |
2761 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
2762 | { | |
2763 | regcache_raw_write (regcache, tdep->ppc_fp0_regnum + | |
2764 | reg_index, buffer); | |
2765 | regcache_raw_write (regcache, tdep->ppc_vsr0_upper_regnum + | |
2766 | reg_index, buffer + 8); | |
2767 | } | |
2768 | else | |
2769 | { | |
2770 | regcache_raw_write (regcache, tdep->ppc_fp0_regnum + | |
2771 | reg_index, buffer + 8); | |
2772 | regcache_raw_write (regcache, tdep->ppc_vsr0_upper_regnum + | |
2773 | reg_index, buffer); | |
2774 | } | |
2775 | } | |
2776 | ||
2777 | /* Read method for POWER7 Extended FP pseudo-registers. */ | |
05d1431c | 2778 | static enum register_status |
604c2f83 LM |
2779 | efpr_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, |
2780 | int reg_nr, gdb_byte *buffer) | |
2781 | { | |
2782 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2783 | int reg_index = reg_nr - tdep->ppc_efpr0_regnum; | |
084ee545 | 2784 | int offset = gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG ? 0 : 8; |
604c2f83 | 2785 | |
d9492458 | 2786 | /* Read the portion that overlaps the VMX register. */ |
084ee545 UW |
2787 | return regcache_raw_read_part (regcache, tdep->ppc_vr0_regnum + reg_index, |
2788 | offset, register_size (gdbarch, reg_nr), | |
2789 | buffer); | |
604c2f83 LM |
2790 | } |
2791 | ||
2792 | /* Write method for POWER7 Extended FP pseudo-registers. */ | |
2793 | static void | |
2794 | efpr_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
2795 | int reg_nr, const gdb_byte *buffer) | |
2796 | { | |
2797 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2798 | int reg_index = reg_nr - tdep->ppc_efpr0_regnum; | |
084ee545 | 2799 | int offset = gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG ? 0 : 8; |
604c2f83 | 2800 | |
d9492458 | 2801 | /* Write the portion that overlaps the VMX register. */ |
084ee545 UW |
2802 | regcache_raw_write_part (regcache, tdep->ppc_vr0_regnum + reg_index, |
2803 | offset, register_size (gdbarch, reg_nr), | |
2804 | buffer); | |
604c2f83 LM |
2805 | } |
2806 | ||
05d1431c | 2807 | static enum register_status |
0df8b418 MS |
2808 | rs6000_pseudo_register_read (struct gdbarch *gdbarch, |
2809 | struct regcache *regcache, | |
f949c649 | 2810 | int reg_nr, gdb_byte *buffer) |
c8001721 | 2811 | { |
6ced10dd | 2812 | struct gdbarch *regcache_arch = get_regcache_arch (regcache); |
c8001721 EZ |
2813 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2814 | ||
6ced10dd | 2815 | gdb_assert (regcache_arch == gdbarch); |
f949c649 | 2816 | |
5a9e69ba | 2817 | if (IS_SPE_PSEUDOREG (tdep, reg_nr)) |
05d1431c | 2818 | return e500_pseudo_register_read (gdbarch, regcache, reg_nr, buffer); |
f949c649 | 2819 | else if (IS_DFP_PSEUDOREG (tdep, reg_nr)) |
05d1431c | 2820 | return dfp_pseudo_register_read (gdbarch, regcache, reg_nr, buffer); |
604c2f83 | 2821 | else if (IS_VSX_PSEUDOREG (tdep, reg_nr)) |
05d1431c | 2822 | return vsx_pseudo_register_read (gdbarch, regcache, reg_nr, buffer); |
604c2f83 | 2823 | else if (IS_EFP_PSEUDOREG (tdep, reg_nr)) |
05d1431c | 2824 | return efpr_pseudo_register_read (gdbarch, regcache, reg_nr, buffer); |
6ced10dd | 2825 | else |
a44bddec | 2826 | internal_error (__FILE__, __LINE__, |
f949c649 TJB |
2827 | _("rs6000_pseudo_register_read: " |
2828 | "called on unexpected register '%s' (%d)"), | |
2829 | gdbarch_register_name (gdbarch, reg_nr), reg_nr); | |
c8001721 EZ |
2830 | } |
2831 | ||
2832 | static void | |
f949c649 TJB |
2833 | rs6000_pseudo_register_write (struct gdbarch *gdbarch, |
2834 | struct regcache *regcache, | |
2835 | int reg_nr, const gdb_byte *buffer) | |
c8001721 | 2836 | { |
6ced10dd | 2837 | struct gdbarch *regcache_arch = get_regcache_arch (regcache); |
c8001721 EZ |
2838 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2839 | ||
6ced10dd | 2840 | gdb_assert (regcache_arch == gdbarch); |
f949c649 | 2841 | |
5a9e69ba | 2842 | if (IS_SPE_PSEUDOREG (tdep, reg_nr)) |
f949c649 TJB |
2843 | e500_pseudo_register_write (gdbarch, regcache, reg_nr, buffer); |
2844 | else if (IS_DFP_PSEUDOREG (tdep, reg_nr)) | |
604c2f83 LM |
2845 | dfp_pseudo_register_write (gdbarch, regcache, reg_nr, buffer); |
2846 | else if (IS_VSX_PSEUDOREG (tdep, reg_nr)) | |
2847 | vsx_pseudo_register_write (gdbarch, regcache, reg_nr, buffer); | |
2848 | else if (IS_EFP_PSEUDOREG (tdep, reg_nr)) | |
2849 | efpr_pseudo_register_write (gdbarch, regcache, reg_nr, buffer); | |
6ced10dd | 2850 | else |
a44bddec | 2851 | internal_error (__FILE__, __LINE__, |
f949c649 TJB |
2852 | _("rs6000_pseudo_register_write: " |
2853 | "called on unexpected register '%s' (%d)"), | |
2854 | gdbarch_register_name (gdbarch, reg_nr), reg_nr); | |
6ced10dd JB |
2855 | } |
2856 | ||
18ed0c4e | 2857 | /* Convert a DBX STABS register number to a GDB register number. */ |
c8001721 | 2858 | static int |
d3f73121 | 2859 | rs6000_stab_reg_to_regnum (struct gdbarch *gdbarch, int num) |
c8001721 | 2860 | { |
d3f73121 | 2861 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
c8001721 | 2862 | |
9f744501 JB |
2863 | if (0 <= num && num <= 31) |
2864 | return tdep->ppc_gp0_regnum + num; | |
2865 | else if (32 <= num && num <= 63) | |
383f0f5b JB |
2866 | /* FIXME: jimb/2004-05-05: What should we do when the debug info |
2867 | specifies registers the architecture doesn't have? Our | |
2868 | callers don't check the value we return. */ | |
366f009f | 2869 | return tdep->ppc_fp0_regnum + (num - 32); |
18ed0c4e JB |
2870 | else if (77 <= num && num <= 108) |
2871 | return tdep->ppc_vr0_regnum + (num - 77); | |
9f744501 | 2872 | else if (1200 <= num && num < 1200 + 32) |
e1ec1b42 | 2873 | return tdep->ppc_ev0_upper_regnum + (num - 1200); |
9f744501 JB |
2874 | else |
2875 | switch (num) | |
2876 | { | |
2877 | case 64: | |
2878 | return tdep->ppc_mq_regnum; | |
2879 | case 65: | |
2880 | return tdep->ppc_lr_regnum; | |
2881 | case 66: | |
2882 | return tdep->ppc_ctr_regnum; | |
2883 | case 76: | |
2884 | return tdep->ppc_xer_regnum; | |
2885 | case 109: | |
2886 | return tdep->ppc_vrsave_regnum; | |
18ed0c4e JB |
2887 | case 110: |
2888 | return tdep->ppc_vrsave_regnum - 1; /* vscr */ | |
867e2dc5 | 2889 | case 111: |
18ed0c4e | 2890 | return tdep->ppc_acc_regnum; |
867e2dc5 | 2891 | case 112: |
18ed0c4e | 2892 | return tdep->ppc_spefscr_regnum; |
9f744501 JB |
2893 | default: |
2894 | return num; | |
2895 | } | |
18ed0c4e | 2896 | } |
9f744501 | 2897 | |
9f744501 | 2898 | |
18ed0c4e JB |
2899 | /* Convert a Dwarf 2 register number to a GDB register number. */ |
2900 | static int | |
d3f73121 | 2901 | rs6000_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int num) |
18ed0c4e | 2902 | { |
d3f73121 | 2903 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
9f744501 | 2904 | |
18ed0c4e JB |
2905 | if (0 <= num && num <= 31) |
2906 | return tdep->ppc_gp0_regnum + num; | |
2907 | else if (32 <= num && num <= 63) | |
2908 | /* FIXME: jimb/2004-05-05: What should we do when the debug info | |
2909 | specifies registers the architecture doesn't have? Our | |
2910 | callers don't check the value we return. */ | |
2911 | return tdep->ppc_fp0_regnum + (num - 32); | |
2912 | else if (1124 <= num && num < 1124 + 32) | |
2913 | return tdep->ppc_vr0_regnum + (num - 1124); | |
2914 | else if (1200 <= num && num < 1200 + 32) | |
e1ec1b42 | 2915 | return tdep->ppc_ev0_upper_regnum + (num - 1200); |
18ed0c4e JB |
2916 | else |
2917 | switch (num) | |
2918 | { | |
a489f789 AS |
2919 | case 64: |
2920 | return tdep->ppc_cr_regnum; | |
18ed0c4e JB |
2921 | case 67: |
2922 | return tdep->ppc_vrsave_regnum - 1; /* vscr */ | |
2923 | case 99: | |
2924 | return tdep->ppc_acc_regnum; | |
2925 | case 100: | |
2926 | return tdep->ppc_mq_regnum; | |
2927 | case 101: | |
2928 | return tdep->ppc_xer_regnum; | |
2929 | case 108: | |
2930 | return tdep->ppc_lr_regnum; | |
2931 | case 109: | |
2932 | return tdep->ppc_ctr_regnum; | |
2933 | case 356: | |
2934 | return tdep->ppc_vrsave_regnum; | |
2935 | case 612: | |
2936 | return tdep->ppc_spefscr_regnum; | |
2937 | default: | |
2938 | return num; | |
2939 | } | |
2188cbdd EZ |
2940 | } |
2941 | ||
4fc771b8 DJ |
2942 | /* Translate a .eh_frame register to DWARF register, or adjust a |
2943 | .debug_frame register. */ | |
2944 | ||
2945 | static int | |
2946 | rs6000_adjust_frame_regnum (struct gdbarch *gdbarch, int num, int eh_frame_p) | |
2947 | { | |
2948 | /* GCC releases before 3.4 use GCC internal register numbering in | |
2949 | .debug_frame (and .debug_info, et cetera). The numbering is | |
2950 | different from the standard SysV numbering for everything except | |
2951 | for GPRs and FPRs. We can not detect this problem in most cases | |
2952 | - to get accurate debug info for variables living in lr, ctr, v0, | |
2953 | et cetera, use a newer version of GCC. But we must detect | |
2954 | one important case - lr is in column 65 in .debug_frame output, | |
2955 | instead of 108. | |
2956 | ||
2957 | GCC 3.4, and the "hammer" branch, have a related problem. They | |
2958 | record lr register saves in .debug_frame as 108, but still record | |
2959 | the return column as 65. We fix that up too. | |
2960 | ||
2961 | We can do this because 65 is assigned to fpsr, and GCC never | |
2962 | generates debug info referring to it. To add support for | |
2963 | handwritten debug info that restores fpsr, we would need to add a | |
2964 | producer version check to this. */ | |
2965 | if (!eh_frame_p) | |
2966 | { | |
2967 | if (num == 65) | |
2968 | return 108; | |
2969 | else | |
2970 | return num; | |
2971 | } | |
2972 | ||
2973 | /* .eh_frame is GCC specific. For binary compatibility, it uses GCC | |
2974 | internal register numbering; translate that to the standard DWARF2 | |
2975 | register numbering. */ | |
2976 | if (0 <= num && num <= 63) /* r0-r31,fp0-fp31 */ | |
2977 | return num; | |
2978 | else if (68 <= num && num <= 75) /* cr0-cr8 */ | |
2979 | return num - 68 + 86; | |
2980 | else if (77 <= num && num <= 108) /* vr0-vr31 */ | |
2981 | return num - 77 + 1124; | |
2982 | else | |
2983 | switch (num) | |
2984 | { | |
2985 | case 64: /* mq */ | |
2986 | return 100; | |
2987 | case 65: /* lr */ | |
2988 | return 108; | |
2989 | case 66: /* ctr */ | |
2990 | return 109; | |
2991 | case 76: /* xer */ | |
2992 | return 101; | |
2993 | case 109: /* vrsave */ | |
2994 | return 356; | |
2995 | case 110: /* vscr */ | |
2996 | return 67; | |
2997 | case 111: /* spe_acc */ | |
2998 | return 99; | |
2999 | case 112: /* spefscr */ | |
3000 | return 612; | |
3001 | default: | |
3002 | return num; | |
3003 | } | |
3004 | } | |
c906108c | 3005 | \f |
c5aa993b | 3006 | |
7a78ae4e | 3007 | /* Handling the various POWER/PowerPC variants. */ |
c906108c | 3008 | |
c906108c | 3009 | /* Information about a particular processor variant. */ |
7a78ae4e | 3010 | |
c906108c | 3011 | struct variant |
c5aa993b JM |
3012 | { |
3013 | /* Name of this variant. */ | |
3014 | char *name; | |
c906108c | 3015 | |
c5aa993b JM |
3016 | /* English description of the variant. */ |
3017 | char *description; | |
c906108c | 3018 | |
64366f1c | 3019 | /* bfd_arch_info.arch corresponding to variant. */ |
7a78ae4e ND |
3020 | enum bfd_architecture arch; |
3021 | ||
64366f1c | 3022 | /* bfd_arch_info.mach corresponding to variant. */ |
7a78ae4e ND |
3023 | unsigned long mach; |
3024 | ||
7cc46491 DJ |
3025 | /* Target description for this variant. */ |
3026 | struct target_desc **tdesc; | |
c5aa993b | 3027 | }; |
c906108c | 3028 | |
489461e2 | 3029 | static struct variant variants[] = |
c906108c | 3030 | { |
7a78ae4e | 3031 | {"powerpc", "PowerPC user-level", bfd_arch_powerpc, |
7284e1be | 3032 | bfd_mach_ppc, &tdesc_powerpc_altivec32}, |
7a78ae4e | 3033 | {"power", "POWER user-level", bfd_arch_rs6000, |
7cc46491 | 3034 | bfd_mach_rs6k, &tdesc_rs6000}, |
7a78ae4e | 3035 | {"403", "IBM PowerPC 403", bfd_arch_powerpc, |
7cc46491 | 3036 | bfd_mach_ppc_403, &tdesc_powerpc_403}, |
4d09ffea MS |
3037 | {"405", "IBM PowerPC 405", bfd_arch_powerpc, |
3038 | bfd_mach_ppc_405, &tdesc_powerpc_405}, | |
7a78ae4e | 3039 | {"601", "Motorola PowerPC 601", bfd_arch_powerpc, |
7cc46491 | 3040 | bfd_mach_ppc_601, &tdesc_powerpc_601}, |
7a78ae4e | 3041 | {"602", "Motorola PowerPC 602", bfd_arch_powerpc, |
7cc46491 | 3042 | bfd_mach_ppc_602, &tdesc_powerpc_602}, |
7a78ae4e | 3043 | {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc, |
7cc46491 | 3044 | bfd_mach_ppc_603, &tdesc_powerpc_603}, |
7a78ae4e | 3045 | {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc, |
7cc46491 | 3046 | 604, &tdesc_powerpc_604}, |
7a78ae4e | 3047 | {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc, |
7cc46491 | 3048 | bfd_mach_ppc_403gc, &tdesc_powerpc_403gc}, |
7a78ae4e | 3049 | {"505", "Motorola PowerPC 505", bfd_arch_powerpc, |
7cc46491 | 3050 | bfd_mach_ppc_505, &tdesc_powerpc_505}, |
7a78ae4e | 3051 | {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc, |
7cc46491 | 3052 | bfd_mach_ppc_860, &tdesc_powerpc_860}, |
7a78ae4e | 3053 | {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc, |
7cc46491 | 3054 | bfd_mach_ppc_750, &tdesc_powerpc_750}, |
1fcc0bb8 | 3055 | {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc, |
7cc46491 | 3056 | bfd_mach_ppc_7400, &tdesc_powerpc_7400}, |
c8001721 | 3057 | {"e500", "Motorola PowerPC e500", bfd_arch_powerpc, |
7cc46491 | 3058 | bfd_mach_ppc_e500, &tdesc_powerpc_e500}, |
7a78ae4e | 3059 | |
5d57ee30 KB |
3060 | /* 64-bit */ |
3061 | {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc, | |
7284e1be | 3062 | bfd_mach_ppc64, &tdesc_powerpc_altivec64}, |
7a78ae4e | 3063 | {"620", "Motorola PowerPC 620", bfd_arch_powerpc, |
7cc46491 | 3064 | bfd_mach_ppc_620, &tdesc_powerpc_64}, |
5d57ee30 | 3065 | {"630", "Motorola PowerPC 630", bfd_arch_powerpc, |
7cc46491 | 3066 | bfd_mach_ppc_630, &tdesc_powerpc_64}, |
7a78ae4e | 3067 | {"a35", "PowerPC A35", bfd_arch_powerpc, |
7cc46491 | 3068 | bfd_mach_ppc_a35, &tdesc_powerpc_64}, |
5d57ee30 | 3069 | {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc, |
7cc46491 | 3070 | bfd_mach_ppc_rs64ii, &tdesc_powerpc_64}, |
5d57ee30 | 3071 | {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc, |
7cc46491 | 3072 | bfd_mach_ppc_rs64iii, &tdesc_powerpc_64}, |
5d57ee30 | 3073 | |
64366f1c | 3074 | /* FIXME: I haven't checked the register sets of the following. */ |
7a78ae4e | 3075 | {"rs1", "IBM POWER RS1", bfd_arch_rs6000, |
7cc46491 | 3076 | bfd_mach_rs6k_rs1, &tdesc_rs6000}, |
7a78ae4e | 3077 | {"rsc", "IBM POWER RSC", bfd_arch_rs6000, |
7cc46491 | 3078 | bfd_mach_rs6k_rsc, &tdesc_rs6000}, |
7a78ae4e | 3079 | {"rs2", "IBM POWER RS2", bfd_arch_rs6000, |
7cc46491 | 3080 | bfd_mach_rs6k_rs2, &tdesc_rs6000}, |
7a78ae4e | 3081 | |
7cc46491 | 3082 | {0, 0, 0, 0, 0} |
c906108c SS |
3083 | }; |
3084 | ||
7a78ae4e | 3085 | /* Return the variant corresponding to architecture ARCH and machine number |
64366f1c | 3086 | MACH. If no such variant exists, return null. */ |
c906108c | 3087 | |
7a78ae4e ND |
3088 | static const struct variant * |
3089 | find_variant_by_arch (enum bfd_architecture arch, unsigned long mach) | |
c906108c | 3090 | { |
7a78ae4e | 3091 | const struct variant *v; |
c5aa993b | 3092 | |
7a78ae4e ND |
3093 | for (v = variants; v->name; v++) |
3094 | if (arch == v->arch && mach == v->mach) | |
3095 | return v; | |
c906108c | 3096 | |
7a78ae4e | 3097 | return NULL; |
c906108c | 3098 | } |
9364a0ef EZ |
3099 | |
3100 | static int | |
3101 | gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info) | |
3102 | { | |
40887e1a | 3103 | if (info->endian == BFD_ENDIAN_BIG) |
9364a0ef EZ |
3104 | return print_insn_big_powerpc (memaddr, info); |
3105 | else | |
3106 | return print_insn_little_powerpc (memaddr, info); | |
3107 | } | |
7a78ae4e | 3108 | \f |
61a65099 KB |
3109 | static CORE_ADDR |
3110 | rs6000_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
3111 | { | |
3e8c568d | 3112 | return frame_unwind_register_unsigned (next_frame, |
8b164abb | 3113 | gdbarch_pc_regnum (gdbarch)); |
61a65099 KB |
3114 | } |
3115 | ||
3116 | static struct frame_id | |
1af5d7ce | 3117 | rs6000_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
61a65099 | 3118 | { |
1af5d7ce UW |
3119 | return frame_id_build (get_frame_register_unsigned |
3120 | (this_frame, gdbarch_sp_regnum (gdbarch)), | |
3121 | get_frame_pc (this_frame)); | |
61a65099 KB |
3122 | } |
3123 | ||
3124 | struct rs6000_frame_cache | |
3125 | { | |
3126 | CORE_ADDR base; | |
3127 | CORE_ADDR initial_sp; | |
3128 | struct trad_frame_saved_reg *saved_regs; | |
3129 | }; | |
3130 | ||
3131 | static struct rs6000_frame_cache * | |
1af5d7ce | 3132 | rs6000_frame_cache (struct frame_info *this_frame, void **this_cache) |
61a65099 KB |
3133 | { |
3134 | struct rs6000_frame_cache *cache; | |
1af5d7ce | 3135 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
61a65099 | 3136 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
e17a4113 | 3137 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
61a65099 KB |
3138 | struct rs6000_framedata fdata; |
3139 | int wordsize = tdep->wordsize; | |
e10b1c4c | 3140 | CORE_ADDR func, pc; |
61a65099 KB |
3141 | |
3142 | if ((*this_cache) != NULL) | |
3143 | return (*this_cache); | |
3144 | cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache); | |
3145 | (*this_cache) = cache; | |
1af5d7ce | 3146 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
61a65099 | 3147 | |
1af5d7ce UW |
3148 | func = get_frame_func (this_frame); |
3149 | pc = get_frame_pc (this_frame); | |
be8626e0 | 3150 | skip_prologue (gdbarch, func, pc, &fdata); |
e10b1c4c DJ |
3151 | |
3152 | /* Figure out the parent's stack pointer. */ | |
3153 | ||
3154 | /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most | |
3155 | address of the current frame. Things might be easier if the | |
3156 | ->frame pointed to the outer-most address of the frame. In | |
3157 | the mean time, the address of the prev frame is used as the | |
3158 | base address of this frame. */ | |
1af5d7ce UW |
3159 | cache->base = get_frame_register_unsigned |
3160 | (this_frame, gdbarch_sp_regnum (gdbarch)); | |
e10b1c4c DJ |
3161 | |
3162 | /* If the function appears to be frameless, check a couple of likely | |
3163 | indicators that we have simply failed to find the frame setup. | |
3164 | Two common cases of this are missing symbols (i.e. | |
ef02daa9 | 3165 | get_frame_func returns the wrong address or 0), and assembly |
e10b1c4c DJ |
3166 | stubs which have a fast exit path but set up a frame on the slow |
3167 | path. | |
3168 | ||
3169 | If the LR appears to return to this function, then presume that | |
3170 | we have an ABI compliant frame that we failed to find. */ | |
3171 | if (fdata.frameless && fdata.lr_offset == 0) | |
61a65099 | 3172 | { |
e10b1c4c DJ |
3173 | CORE_ADDR saved_lr; |
3174 | int make_frame = 0; | |
3175 | ||
1af5d7ce | 3176 | saved_lr = get_frame_register_unsigned (this_frame, tdep->ppc_lr_regnum); |
e10b1c4c DJ |
3177 | if (func == 0 && saved_lr == pc) |
3178 | make_frame = 1; | |
3179 | else if (func != 0) | |
3180 | { | |
3181 | CORE_ADDR saved_func = get_pc_function_start (saved_lr); | |
3182 | if (func == saved_func) | |
3183 | make_frame = 1; | |
3184 | } | |
3185 | ||
3186 | if (make_frame) | |
3187 | { | |
3188 | fdata.frameless = 0; | |
de6a76fd | 3189 | fdata.lr_offset = tdep->lr_frame_offset; |
e10b1c4c | 3190 | } |
61a65099 | 3191 | } |
e10b1c4c DJ |
3192 | |
3193 | if (!fdata.frameless) | |
3194 | /* Frameless really means stackless. */ | |
e17a4113 UW |
3195 | cache->base |
3196 | = read_memory_unsigned_integer (cache->base, wordsize, byte_order); | |
e10b1c4c | 3197 | |
3e8c568d | 3198 | trad_frame_set_value (cache->saved_regs, |
8b164abb | 3199 | gdbarch_sp_regnum (gdbarch), cache->base); |
61a65099 KB |
3200 | |
3201 | /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr. | |
3202 | All fpr's from saved_fpr to fp31 are saved. */ | |
3203 | ||
3204 | if (fdata.saved_fpr >= 0) | |
3205 | { | |
3206 | int i; | |
3207 | CORE_ADDR fpr_addr = cache->base + fdata.fpr_offset; | |
383f0f5b JB |
3208 | |
3209 | /* If skip_prologue says floating-point registers were saved, | |
3210 | but the current architecture has no floating-point registers, | |
3211 | then that's strange. But we have no indices to even record | |
3212 | the addresses under, so we just ignore it. */ | |
3213 | if (ppc_floating_point_unit_p (gdbarch)) | |
063715bf | 3214 | for (i = fdata.saved_fpr; i < ppc_num_fprs; i++) |
383f0f5b JB |
3215 | { |
3216 | cache->saved_regs[tdep->ppc_fp0_regnum + i].addr = fpr_addr; | |
3217 | fpr_addr += 8; | |
3218 | } | |
61a65099 KB |
3219 | } |
3220 | ||
3221 | /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr. | |
46a9b8ed DJ |
3222 | All gpr's from saved_gpr to gpr31 are saved (except during the |
3223 | prologue). */ | |
61a65099 KB |
3224 | |
3225 | if (fdata.saved_gpr >= 0) | |
3226 | { | |
3227 | int i; | |
3228 | CORE_ADDR gpr_addr = cache->base + fdata.gpr_offset; | |
063715bf | 3229 | for (i = fdata.saved_gpr; i < ppc_num_gprs; i++) |
61a65099 | 3230 | { |
46a9b8ed DJ |
3231 | if (fdata.gpr_mask & (1U << i)) |
3232 | cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = gpr_addr; | |
61a65099 KB |
3233 | gpr_addr += wordsize; |
3234 | } | |
3235 | } | |
3236 | ||
3237 | /* if != -1, fdata.saved_vr is the smallest number of saved_vr. | |
3238 | All vr's from saved_vr to vr31 are saved. */ | |
3239 | if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) | |
3240 | { | |
3241 | if (fdata.saved_vr >= 0) | |
3242 | { | |
3243 | int i; | |
3244 | CORE_ADDR vr_addr = cache->base + fdata.vr_offset; | |
3245 | for (i = fdata.saved_vr; i < 32; i++) | |
3246 | { | |
3247 | cache->saved_regs[tdep->ppc_vr0_regnum + i].addr = vr_addr; | |
3248 | vr_addr += register_size (gdbarch, tdep->ppc_vr0_regnum); | |
3249 | } | |
3250 | } | |
3251 | } | |
3252 | ||
3253 | /* if != -1, fdata.saved_ev is the smallest number of saved_ev. | |
0df8b418 | 3254 | All vr's from saved_ev to ev31 are saved. ????? */ |
5a9e69ba | 3255 | if (tdep->ppc_ev0_regnum != -1) |
61a65099 KB |
3256 | { |
3257 | if (fdata.saved_ev >= 0) | |
3258 | { | |
3259 | int i; | |
3260 | CORE_ADDR ev_addr = cache->base + fdata.ev_offset; | |
dea80df0 MR |
3261 | CORE_ADDR off = (byte_order == BFD_ENDIAN_BIG ? 4 : 0); |
3262 | ||
063715bf | 3263 | for (i = fdata.saved_ev; i < ppc_num_gprs; i++) |
61a65099 KB |
3264 | { |
3265 | cache->saved_regs[tdep->ppc_ev0_regnum + i].addr = ev_addr; | |
dea80df0 | 3266 | cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + off; |
61a65099 | 3267 | ev_addr += register_size (gdbarch, tdep->ppc_ev0_regnum); |
dea80df0 | 3268 | } |
61a65099 KB |
3269 | } |
3270 | } | |
3271 | ||
3272 | /* If != 0, fdata.cr_offset is the offset from the frame that | |
3273 | holds the CR. */ | |
3274 | if (fdata.cr_offset != 0) | |
0df8b418 MS |
3275 | cache->saved_regs[tdep->ppc_cr_regnum].addr |
3276 | = cache->base + fdata.cr_offset; | |
61a65099 KB |
3277 | |
3278 | /* If != 0, fdata.lr_offset is the offset from the frame that | |
3279 | holds the LR. */ | |
3280 | if (fdata.lr_offset != 0) | |
0df8b418 MS |
3281 | cache->saved_regs[tdep->ppc_lr_regnum].addr |
3282 | = cache->base + fdata.lr_offset; | |
46a9b8ed DJ |
3283 | else if (fdata.lr_register != -1) |
3284 | cache->saved_regs[tdep->ppc_lr_regnum].realreg = fdata.lr_register; | |
61a65099 | 3285 | /* The PC is found in the link register. */ |
8b164abb | 3286 | cache->saved_regs[gdbarch_pc_regnum (gdbarch)] = |
3e8c568d | 3287 | cache->saved_regs[tdep->ppc_lr_regnum]; |
61a65099 KB |
3288 | |
3289 | /* If != 0, fdata.vrsave_offset is the offset from the frame that | |
3290 | holds the VRSAVE. */ | |
3291 | if (fdata.vrsave_offset != 0) | |
0df8b418 MS |
3292 | cache->saved_regs[tdep->ppc_vrsave_regnum].addr |
3293 | = cache->base + fdata.vrsave_offset; | |
61a65099 KB |
3294 | |
3295 | if (fdata.alloca_reg < 0) | |
3296 | /* If no alloca register used, then fi->frame is the value of the | |
3297 | %sp for this frame, and it is good enough. */ | |
1af5d7ce UW |
3298 | cache->initial_sp |
3299 | = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch)); | |
61a65099 | 3300 | else |
1af5d7ce UW |
3301 | cache->initial_sp |
3302 | = get_frame_register_unsigned (this_frame, fdata.alloca_reg); | |
61a65099 KB |
3303 | |
3304 | return cache; | |
3305 | } | |
3306 | ||
3307 | static void | |
1af5d7ce | 3308 | rs6000_frame_this_id (struct frame_info *this_frame, void **this_cache, |
61a65099 KB |
3309 | struct frame_id *this_id) |
3310 | { | |
1af5d7ce | 3311 | struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame, |
61a65099 | 3312 | this_cache); |
5b197912 UW |
3313 | /* This marks the outermost frame. */ |
3314 | if (info->base == 0) | |
3315 | return; | |
3316 | ||
1af5d7ce | 3317 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); |
61a65099 KB |
3318 | } |
3319 | ||
1af5d7ce UW |
3320 | static struct value * |
3321 | rs6000_frame_prev_register (struct frame_info *this_frame, | |
3322 | void **this_cache, int regnum) | |
61a65099 | 3323 | { |
1af5d7ce | 3324 | struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame, |
61a65099 | 3325 | this_cache); |
1af5d7ce | 3326 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
61a65099 KB |
3327 | } |
3328 | ||
3329 | static const struct frame_unwind rs6000_frame_unwind = | |
3330 | { | |
3331 | NORMAL_FRAME, | |
8fbca658 | 3332 | default_frame_unwind_stop_reason, |
61a65099 | 3333 | rs6000_frame_this_id, |
1af5d7ce UW |
3334 | rs6000_frame_prev_register, |
3335 | NULL, | |
3336 | default_frame_sniffer | |
61a65099 | 3337 | }; |
61a65099 KB |
3338 | \f |
3339 | ||
3340 | static CORE_ADDR | |
1af5d7ce | 3341 | rs6000_frame_base_address (struct frame_info *this_frame, void **this_cache) |
61a65099 | 3342 | { |
1af5d7ce | 3343 | struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame, |
61a65099 KB |
3344 | this_cache); |
3345 | return info->initial_sp; | |
3346 | } | |
3347 | ||
3348 | static const struct frame_base rs6000_frame_base = { | |
3349 | &rs6000_frame_unwind, | |
3350 | rs6000_frame_base_address, | |
3351 | rs6000_frame_base_address, | |
3352 | rs6000_frame_base_address | |
3353 | }; | |
3354 | ||
3355 | static const struct frame_base * | |
1af5d7ce | 3356 | rs6000_frame_base_sniffer (struct frame_info *this_frame) |
61a65099 KB |
3357 | { |
3358 | return &rs6000_frame_base; | |
3359 | } | |
3360 | ||
9274a07c LM |
3361 | /* DWARF-2 frame support. Used to handle the detection of |
3362 | clobbered registers during function calls. */ | |
3363 | ||
3364 | static void | |
3365 | ppc_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
3366 | struct dwarf2_frame_state_reg *reg, | |
4a4e5149 | 3367 | struct frame_info *this_frame) |
9274a07c LM |
3368 | { |
3369 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3370 | ||
3371 | /* PPC32 and PPC64 ABI's are the same regarding volatile and | |
3372 | non-volatile registers. We will use the same code for both. */ | |
3373 | ||
3374 | /* Call-saved GP registers. */ | |
3375 | if ((regnum >= tdep->ppc_gp0_regnum + 14 | |
3376 | && regnum <= tdep->ppc_gp0_regnum + 31) | |
3377 | || (regnum == tdep->ppc_gp0_regnum + 1)) | |
3378 | reg->how = DWARF2_FRAME_REG_SAME_VALUE; | |
3379 | ||
3380 | /* Call-clobbered GP registers. */ | |
3381 | if ((regnum >= tdep->ppc_gp0_regnum + 3 | |
3382 | && regnum <= tdep->ppc_gp0_regnum + 12) | |
3383 | || (regnum == tdep->ppc_gp0_regnum)) | |
3384 | reg->how = DWARF2_FRAME_REG_UNDEFINED; | |
3385 | ||
3386 | /* Deal with FP registers, if supported. */ | |
3387 | if (tdep->ppc_fp0_regnum >= 0) | |
3388 | { | |
3389 | /* Call-saved FP registers. */ | |
3390 | if ((regnum >= tdep->ppc_fp0_regnum + 14 | |
3391 | && regnum <= tdep->ppc_fp0_regnum + 31)) | |
3392 | reg->how = DWARF2_FRAME_REG_SAME_VALUE; | |
3393 | ||
3394 | /* Call-clobbered FP registers. */ | |
3395 | if ((regnum >= tdep->ppc_fp0_regnum | |
3396 | && regnum <= tdep->ppc_fp0_regnum + 13)) | |
3397 | reg->how = DWARF2_FRAME_REG_UNDEFINED; | |
3398 | } | |
3399 | ||
3400 | /* Deal with ALTIVEC registers, if supported. */ | |
3401 | if (tdep->ppc_vr0_regnum > 0 && tdep->ppc_vrsave_regnum > 0) | |
3402 | { | |
3403 | /* Call-saved Altivec registers. */ | |
3404 | if ((regnum >= tdep->ppc_vr0_regnum + 20 | |
3405 | && regnum <= tdep->ppc_vr0_regnum + 31) | |
3406 | || regnum == tdep->ppc_vrsave_regnum) | |
3407 | reg->how = DWARF2_FRAME_REG_SAME_VALUE; | |
3408 | ||
3409 | /* Call-clobbered Altivec registers. */ | |
3410 | if ((regnum >= tdep->ppc_vr0_regnum | |
3411 | && regnum <= tdep->ppc_vr0_regnum + 19)) | |
3412 | reg->how = DWARF2_FRAME_REG_UNDEFINED; | |
3413 | } | |
3414 | ||
3415 | /* Handle PC register and Stack Pointer correctly. */ | |
40a6adc1 | 3416 | if (regnum == gdbarch_pc_regnum (gdbarch)) |
9274a07c | 3417 | reg->how = DWARF2_FRAME_REG_RA; |
40a6adc1 | 3418 | else if (regnum == gdbarch_sp_regnum (gdbarch)) |
9274a07c LM |
3419 | reg->how = DWARF2_FRAME_REG_CFA; |
3420 | } | |
3421 | ||
3422 | ||
74af9197 NF |
3423 | /* Return true if a .gnu_attributes section exists in BFD and it |
3424 | indicates we are using SPE extensions OR if a .PPC.EMB.apuinfo | |
3425 | section exists in BFD and it indicates that SPE extensions are in | |
3426 | use. Check the .gnu.attributes section first, as the binary might be | |
3427 | compiled for SPE, but not actually using SPE instructions. */ | |
3428 | ||
3429 | static int | |
3430 | bfd_uses_spe_extensions (bfd *abfd) | |
3431 | { | |
3432 | asection *sect; | |
3433 | gdb_byte *contents = NULL; | |
3434 | bfd_size_type size; | |
3435 | gdb_byte *ptr; | |
3436 | int success = 0; | |
3437 | int vector_abi; | |
3438 | ||
3439 | if (!abfd) | |
3440 | return 0; | |
3441 | ||
50a99728 | 3442 | #ifdef HAVE_ELF |
74af9197 NF |
3443 | /* Using Tag_GNU_Power_ABI_Vector here is a bit of a hack, as the user |
3444 | could be using the SPE vector abi without actually using any spe | |
3445 | bits whatsoever. But it's close enough for now. */ | |
3446 | vector_abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_GNU, | |
3447 | Tag_GNU_Power_ABI_Vector); | |
3448 | if (vector_abi == 3) | |
3449 | return 1; | |
50a99728 | 3450 | #endif |
74af9197 NF |
3451 | |
3452 | sect = bfd_get_section_by_name (abfd, ".PPC.EMB.apuinfo"); | |
3453 | if (!sect) | |
3454 | return 0; | |
3455 | ||
3456 | size = bfd_get_section_size (sect); | |
3457 | contents = xmalloc (size); | |
3458 | if (!bfd_get_section_contents (abfd, sect, contents, 0, size)) | |
3459 | { | |
3460 | xfree (contents); | |
3461 | return 0; | |
3462 | } | |
3463 | ||
3464 | /* Parse the .PPC.EMB.apuinfo section. The layout is as follows: | |
3465 | ||
3466 | struct { | |
3467 | uint32 name_len; | |
3468 | uint32 data_len; | |
3469 | uint32 type; | |
3470 | char name[name_len rounded up to 4-byte alignment]; | |
3471 | char data[data_len]; | |
3472 | }; | |
3473 | ||
3474 | Technically, there's only supposed to be one such structure in a | |
3475 | given apuinfo section, but the linker is not always vigilant about | |
3476 | merging apuinfo sections from input files. Just go ahead and parse | |
3477 | them all, exiting early when we discover the binary uses SPE | |
3478 | insns. | |
3479 | ||
3480 | It's not specified in what endianness the information in this | |
3481 | section is stored. Assume that it's the endianness of the BFD. */ | |
3482 | ptr = contents; | |
3483 | while (1) | |
3484 | { | |
3485 | unsigned int name_len; | |
3486 | unsigned int data_len; | |
3487 | unsigned int type; | |
3488 | ||
3489 | /* If we can't read the first three fields, we're done. */ | |
3490 | if (size < 12) | |
3491 | break; | |
3492 | ||
3493 | name_len = bfd_get_32 (abfd, ptr); | |
3494 | name_len = (name_len + 3) & ~3U; /* Round to 4 bytes. */ | |
3495 | data_len = bfd_get_32 (abfd, ptr + 4); | |
3496 | type = bfd_get_32 (abfd, ptr + 8); | |
3497 | ptr += 12; | |
3498 | ||
3499 | /* The name must be "APUinfo\0". */ | |
3500 | if (name_len != 8 | |
3501 | && strcmp ((const char *) ptr, "APUinfo") != 0) | |
3502 | break; | |
3503 | ptr += name_len; | |
3504 | ||
3505 | /* The type must be 2. */ | |
3506 | if (type != 2) | |
3507 | break; | |
3508 | ||
3509 | /* The data is stored as a series of uint32. The upper half of | |
3510 | each uint32 indicates the particular APU used and the lower | |
3511 | half indicates the revision of that APU. We just care about | |
3512 | the upper half. */ | |
3513 | ||
3514 | /* Not 4-byte quantities. */ | |
3515 | if (data_len & 3U) | |
3516 | break; | |
3517 | ||
3518 | while (data_len) | |
3519 | { | |
3520 | unsigned int apuinfo = bfd_get_32 (abfd, ptr); | |
3521 | unsigned int apu = apuinfo >> 16; | |
3522 | ptr += 4; | |
3523 | data_len -= 4; | |
3524 | ||
3525 | /* The SPE APU is 0x100; the SPEFP APU is 0x101. Accept | |
3526 | either. */ | |
3527 | if (apu == 0x100 || apu == 0x101) | |
3528 | { | |
3529 | success = 1; | |
3530 | data_len = 0; | |
3531 | } | |
3532 | } | |
3533 | ||
3534 | if (success) | |
3535 | break; | |
3536 | } | |
3537 | ||
3538 | xfree (contents); | |
3539 | return success; | |
3540 | } | |
3541 | ||
7a78ae4e ND |
3542 | /* Initialize the current architecture based on INFO. If possible, re-use an |
3543 | architecture from ARCHES, which is a list of architectures already created | |
3544 | during this debugging session. | |
c906108c | 3545 | |
7a78ae4e | 3546 | Called e.g. at program startup, when reading a core file, and when reading |
64366f1c | 3547 | a binary file. */ |
c906108c | 3548 | |
7a78ae4e ND |
3549 | static struct gdbarch * |
3550 | rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
3551 | { | |
3552 | struct gdbarch *gdbarch; | |
3553 | struct gdbarch_tdep *tdep; | |
7cc46491 | 3554 | int wordsize, from_xcoff_exec, from_elf_exec; |
7a78ae4e ND |
3555 | enum bfd_architecture arch; |
3556 | unsigned long mach; | |
3557 | bfd abfd; | |
55eddb0f DJ |
3558 | enum auto_boolean soft_float_flag = powerpc_soft_float_global; |
3559 | int soft_float; | |
3560 | enum powerpc_vector_abi vector_abi = powerpc_vector_abi_global; | |
cd453cd0 | 3561 | enum powerpc_elf_abi elf_abi = POWERPC_ELF_AUTO; |
604c2f83 LM |
3562 | int have_fpu = 1, have_spe = 0, have_mq = 0, have_altivec = 0, have_dfp = 0, |
3563 | have_vsx = 0; | |
7cc46491 DJ |
3564 | int tdesc_wordsize = -1; |
3565 | const struct target_desc *tdesc = info.target_desc; | |
3566 | struct tdesc_arch_data *tdesc_data = NULL; | |
f949c649 | 3567 | int num_pseudoregs = 0; |
604c2f83 | 3568 | int cur_reg; |
7a78ae4e | 3569 | |
f4d9bade UW |
3570 | /* INFO may refer to a binary that is not of the PowerPC architecture, |
3571 | e.g. when debugging a stand-alone SPE executable on a Cell/B.E. system. | |
3572 | In this case, we must not attempt to infer properties of the (PowerPC | |
3573 | side) of the target system from properties of that executable. Trust | |
3574 | the target description instead. */ | |
3575 | if (info.abfd | |
3576 | && bfd_get_arch (info.abfd) != bfd_arch_powerpc | |
3577 | && bfd_get_arch (info.abfd) != bfd_arch_rs6000) | |
3578 | info.abfd = NULL; | |
3579 | ||
9aa1e687 | 3580 | from_xcoff_exec = info.abfd && info.abfd->format == bfd_object && |
7a78ae4e ND |
3581 | bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour; |
3582 | ||
9aa1e687 KB |
3583 | from_elf_exec = info.abfd && info.abfd->format == bfd_object && |
3584 | bfd_get_flavour (info.abfd) == bfd_target_elf_flavour; | |
3585 | ||
e712c1cf | 3586 | /* Check word size. If INFO is from a binary file, infer it from |
64366f1c | 3587 | that, else choose a likely default. */ |
9aa1e687 | 3588 | if (from_xcoff_exec) |
c906108c | 3589 | { |
11ed25ac | 3590 | if (bfd_xcoff_is_xcoff64 (info.abfd)) |
7a78ae4e ND |
3591 | wordsize = 8; |
3592 | else | |
3593 | wordsize = 4; | |
c906108c | 3594 | } |
9aa1e687 KB |
3595 | else if (from_elf_exec) |
3596 | { | |
3597 | if (elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
3598 | wordsize = 8; | |
3599 | else | |
3600 | wordsize = 4; | |
3601 | } | |
7cc46491 DJ |
3602 | else if (tdesc_has_registers (tdesc)) |
3603 | wordsize = -1; | |
c906108c | 3604 | else |
7a78ae4e | 3605 | { |
27b15785 KB |
3606 | if (info.bfd_arch_info != NULL && info.bfd_arch_info->bits_per_word != 0) |
3607 | wordsize = info.bfd_arch_info->bits_per_word / | |
3608 | info.bfd_arch_info->bits_per_byte; | |
3609 | else | |
3610 | wordsize = 4; | |
7a78ae4e | 3611 | } |
c906108c | 3612 | |
475bbd17 JB |
3613 | /* Get the architecture and machine from the BFD. */ |
3614 | arch = info.bfd_arch_info->arch; | |
3615 | mach = info.bfd_arch_info->mach; | |
5bf1c677 EZ |
3616 | |
3617 | /* For e500 executables, the apuinfo section is of help here. Such | |
3618 | section contains the identifier and revision number of each | |
3619 | Application-specific Processing Unit that is present on the | |
3620 | chip. The content of the section is determined by the assembler | |
3621 | which looks at each instruction and determines which unit (and | |
74af9197 NF |
3622 | which version of it) can execute it. Grovel through the section |
3623 | looking for relevant e500 APUs. */ | |
5bf1c677 | 3624 | |
74af9197 | 3625 | if (bfd_uses_spe_extensions (info.abfd)) |
5bf1c677 | 3626 | { |
74af9197 NF |
3627 | arch = info.bfd_arch_info->arch; |
3628 | mach = bfd_mach_ppc_e500; | |
3629 | bfd_default_set_arch_mach (&abfd, arch, mach); | |
3630 | info.bfd_arch_info = bfd_get_arch_info (&abfd); | |
5bf1c677 EZ |
3631 | } |
3632 | ||
7cc46491 DJ |
3633 | /* Find a default target description which describes our register |
3634 | layout, if we do not already have one. */ | |
3635 | if (! tdesc_has_registers (tdesc)) | |
3636 | { | |
3637 | const struct variant *v; | |
3638 | ||
3639 | /* Choose variant. */ | |
3640 | v = find_variant_by_arch (arch, mach); | |
3641 | if (!v) | |
3642 | return NULL; | |
3643 | ||
3644 | tdesc = *v->tdesc; | |
3645 | } | |
3646 | ||
3647 | gdb_assert (tdesc_has_registers (tdesc)); | |
3648 | ||
3649 | /* Check any target description for validity. */ | |
3650 | if (tdesc_has_registers (tdesc)) | |
3651 | { | |
3652 | static const char *const gprs[] = { | |
3653 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
3654 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
3655 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
3656 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" | |
3657 | }; | |
7cc46491 DJ |
3658 | const struct tdesc_feature *feature; |
3659 | int i, valid_p; | |
3660 | static const char *const msr_names[] = { "msr", "ps" }; | |
3661 | static const char *const cr_names[] = { "cr", "cnd" }; | |
3662 | static const char *const ctr_names[] = { "ctr", "cnt" }; | |
3663 | ||
3664 | feature = tdesc_find_feature (tdesc, | |
3665 | "org.gnu.gdb.power.core"); | |
3666 | if (feature == NULL) | |
3667 | return NULL; | |
3668 | ||
3669 | tdesc_data = tdesc_data_alloc (); | |
3670 | ||
3671 | valid_p = 1; | |
3672 | for (i = 0; i < ppc_num_gprs; i++) | |
3673 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, gprs[i]); | |
3674 | valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_PC_REGNUM, | |
3675 | "pc"); | |
3676 | valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_LR_REGNUM, | |
3677 | "lr"); | |
3678 | valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_XER_REGNUM, | |
3679 | "xer"); | |
3680 | ||
3681 | /* Allow alternate names for these registers, to accomodate GDB's | |
3682 | historic naming. */ | |
3683 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data, | |
3684 | PPC_MSR_REGNUM, msr_names); | |
3685 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data, | |
3686 | PPC_CR_REGNUM, cr_names); | |
3687 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data, | |
3688 | PPC_CTR_REGNUM, ctr_names); | |
3689 | ||
3690 | if (!valid_p) | |
3691 | { | |
3692 | tdesc_data_cleanup (tdesc_data); | |
3693 | return NULL; | |
3694 | } | |
3695 | ||
3696 | have_mq = tdesc_numbered_register (feature, tdesc_data, PPC_MQ_REGNUM, | |
3697 | "mq"); | |
3698 | ||
3699 | tdesc_wordsize = tdesc_register_size (feature, "pc") / 8; | |
3700 | if (wordsize == -1) | |
3701 | wordsize = tdesc_wordsize; | |
3702 | ||
3703 | feature = tdesc_find_feature (tdesc, | |
3704 | "org.gnu.gdb.power.fpu"); | |
3705 | if (feature != NULL) | |
3706 | { | |
3707 | static const char *const fprs[] = { | |
3708 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
3709 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
3710 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
3711 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31" | |
3712 | }; | |
3713 | valid_p = 1; | |
3714 | for (i = 0; i < ppc_num_fprs; i++) | |
3715 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
3716 | PPC_F0_REGNUM + i, fprs[i]); | |
3717 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
3718 | PPC_FPSCR_REGNUM, "fpscr"); | |
3719 | ||
3720 | if (!valid_p) | |
3721 | { | |
3722 | tdesc_data_cleanup (tdesc_data); | |
3723 | return NULL; | |
3724 | } | |
3725 | have_fpu = 1; | |
3726 | } | |
3727 | else | |
3728 | have_fpu = 0; | |
3729 | ||
f949c649 TJB |
3730 | /* The DFP pseudo-registers will be available when there are floating |
3731 | point registers. */ | |
3732 | have_dfp = have_fpu; | |
3733 | ||
7cc46491 DJ |
3734 | feature = tdesc_find_feature (tdesc, |
3735 | "org.gnu.gdb.power.altivec"); | |
3736 | if (feature != NULL) | |
3737 | { | |
3738 | static const char *const vector_regs[] = { | |
3739 | "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7", | |
3740 | "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15", | |
3741 | "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23", | |
3742 | "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31" | |
3743 | }; | |
3744 | ||
3745 | valid_p = 1; | |
3746 | for (i = 0; i < ppc_num_gprs; i++) | |
3747 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
3748 | PPC_VR0_REGNUM + i, | |
3749 | vector_regs[i]); | |
3750 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
3751 | PPC_VSCR_REGNUM, "vscr"); | |
3752 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
3753 | PPC_VRSAVE_REGNUM, "vrsave"); | |
3754 | ||
3755 | if (have_spe || !valid_p) | |
3756 | { | |
3757 | tdesc_data_cleanup (tdesc_data); | |
3758 | return NULL; | |
3759 | } | |
3760 | have_altivec = 1; | |
3761 | } | |
3762 | else | |
3763 | have_altivec = 0; | |
3764 | ||
604c2f83 LM |
3765 | /* Check for POWER7 VSX registers support. */ |
3766 | feature = tdesc_find_feature (tdesc, | |
3767 | "org.gnu.gdb.power.vsx"); | |
3768 | ||
3769 | if (feature != NULL) | |
3770 | { | |
3771 | static const char *const vsx_regs[] = { | |
3772 | "vs0h", "vs1h", "vs2h", "vs3h", "vs4h", "vs5h", | |
3773 | "vs6h", "vs7h", "vs8h", "vs9h", "vs10h", "vs11h", | |
3774 | "vs12h", "vs13h", "vs14h", "vs15h", "vs16h", "vs17h", | |
3775 | "vs18h", "vs19h", "vs20h", "vs21h", "vs22h", "vs23h", | |
3776 | "vs24h", "vs25h", "vs26h", "vs27h", "vs28h", "vs29h", | |
3777 | "vs30h", "vs31h" | |
3778 | }; | |
3779 | ||
3780 | valid_p = 1; | |
3781 | ||
3782 | for (i = 0; i < ppc_num_vshrs; i++) | |
3783 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
3784 | PPC_VSR0_UPPER_REGNUM + i, | |
3785 | vsx_regs[i]); | |
3786 | if (!valid_p) | |
3787 | { | |
3788 | tdesc_data_cleanup (tdesc_data); | |
3789 | return NULL; | |
3790 | } | |
3791 | ||
3792 | have_vsx = 1; | |
3793 | } | |
3794 | else | |
3795 | have_vsx = 0; | |
3796 | ||
7cc46491 DJ |
3797 | /* On machines supporting the SPE APU, the general-purpose registers |
3798 | are 64 bits long. There are SIMD vector instructions to treat them | |
3799 | as pairs of floats, but the rest of the instruction set treats them | |
3800 | as 32-bit registers, and only operates on their lower halves. | |
3801 | ||
3802 | In the GDB regcache, we treat their high and low halves as separate | |
3803 | registers. The low halves we present as the general-purpose | |
3804 | registers, and then we have pseudo-registers that stitch together | |
3805 | the upper and lower halves and present them as pseudo-registers. | |
3806 | ||
3807 | Thus, the target description is expected to supply the upper | |
3808 | halves separately. */ | |
3809 | ||
3810 | feature = tdesc_find_feature (tdesc, | |
3811 | "org.gnu.gdb.power.spe"); | |
3812 | if (feature != NULL) | |
3813 | { | |
3814 | static const char *const upper_spe[] = { | |
3815 | "ev0h", "ev1h", "ev2h", "ev3h", | |
3816 | "ev4h", "ev5h", "ev6h", "ev7h", | |
3817 | "ev8h", "ev9h", "ev10h", "ev11h", | |
3818 | "ev12h", "ev13h", "ev14h", "ev15h", | |
3819 | "ev16h", "ev17h", "ev18h", "ev19h", | |
3820 | "ev20h", "ev21h", "ev22h", "ev23h", | |
3821 | "ev24h", "ev25h", "ev26h", "ev27h", | |
3822 | "ev28h", "ev29h", "ev30h", "ev31h" | |
3823 | }; | |
3824 | ||
3825 | valid_p = 1; | |
3826 | for (i = 0; i < ppc_num_gprs; i++) | |
3827 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
3828 | PPC_SPE_UPPER_GP0_REGNUM + i, | |
3829 | upper_spe[i]); | |
3830 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
3831 | PPC_SPE_ACC_REGNUM, "acc"); | |
3832 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
3833 | PPC_SPE_FSCR_REGNUM, "spefscr"); | |
3834 | ||
3835 | if (have_mq || have_fpu || !valid_p) | |
3836 | { | |
3837 | tdesc_data_cleanup (tdesc_data); | |
3838 | return NULL; | |
3839 | } | |
3840 | have_spe = 1; | |
3841 | } | |
3842 | else | |
3843 | have_spe = 0; | |
3844 | } | |
3845 | ||
3846 | /* If we have a 64-bit binary on a 32-bit target, complain. Also | |
3847 | complain for a 32-bit binary on a 64-bit target; we do not yet | |
3848 | support that. For instance, the 32-bit ABI routines expect | |
3849 | 32-bit GPRs. | |
3850 | ||
3851 | As long as there isn't an explicit target description, we'll | |
3852 | choose one based on the BFD architecture and get a word size | |
3853 | matching the binary (probably powerpc:common or | |
3854 | powerpc:common64). So there is only trouble if a 64-bit target | |
3855 | supplies a 64-bit description while debugging a 32-bit | |
3856 | binary. */ | |
3857 | if (tdesc_wordsize != -1 && tdesc_wordsize != wordsize) | |
3858 | { | |
3859 | tdesc_data_cleanup (tdesc_data); | |
3860 | return NULL; | |
3861 | } | |
3862 | ||
55eddb0f | 3863 | #ifdef HAVE_ELF |
cd453cd0 UW |
3864 | if (from_elf_exec) |
3865 | { | |
3866 | switch (elf_elfheader (info.abfd)->e_flags & EF_PPC64_ABI) | |
3867 | { | |
3868 | case 1: | |
3869 | elf_abi = POWERPC_ELF_V1; | |
3870 | break; | |
3871 | case 2: | |
3872 | elf_abi = POWERPC_ELF_V2; | |
3873 | break; | |
3874 | default: | |
3875 | break; | |
3876 | } | |
3877 | } | |
3878 | ||
55eddb0f DJ |
3879 | if (soft_float_flag == AUTO_BOOLEAN_AUTO && from_elf_exec) |
3880 | { | |
3881 | switch (bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU, | |
3882 | Tag_GNU_Power_ABI_FP)) | |
3883 | { | |
3884 | case 1: | |
3885 | soft_float_flag = AUTO_BOOLEAN_FALSE; | |
3886 | break; | |
3887 | case 2: | |
3888 | soft_float_flag = AUTO_BOOLEAN_TRUE; | |
3889 | break; | |
3890 | default: | |
3891 | break; | |
3892 | } | |
3893 | } | |
3894 | ||
3895 | if (vector_abi == POWERPC_VEC_AUTO && from_elf_exec) | |
3896 | { | |
3897 | switch (bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU, | |
3898 | Tag_GNU_Power_ABI_Vector)) | |
3899 | { | |
3900 | case 1: | |
3901 | vector_abi = POWERPC_VEC_GENERIC; | |
3902 | break; | |
3903 | case 2: | |
3904 | vector_abi = POWERPC_VEC_ALTIVEC; | |
3905 | break; | |
3906 | case 3: | |
3907 | vector_abi = POWERPC_VEC_SPE; | |
3908 | break; | |
3909 | default: | |
3910 | break; | |
3911 | } | |
3912 | } | |
3913 | #endif | |
3914 | ||
cd453cd0 UW |
3915 | /* At this point, the only supported ELF-based 64-bit little-endian |
3916 | operating system is GNU/Linux, and this uses the ELFv2 ABI by | |
3917 | default. All other supported ELF-based operating systems use the | |
3918 | ELFv1 ABI by default. Therefore, if the ABI marker is missing, | |
3919 | e.g. because we run a legacy binary, or have attached to a process | |
3920 | and have not found any associated binary file, set the default | |
3921 | according to this heuristic. */ | |
3922 | if (elf_abi == POWERPC_ELF_AUTO) | |
3923 | { | |
3924 | if (wordsize == 8 && info.byte_order == BFD_ENDIAN_LITTLE) | |
3925 | elf_abi = POWERPC_ELF_V2; | |
3926 | else | |
3927 | elf_abi = POWERPC_ELF_V1; | |
3928 | } | |
3929 | ||
55eddb0f DJ |
3930 | if (soft_float_flag == AUTO_BOOLEAN_TRUE) |
3931 | soft_float = 1; | |
3932 | else if (soft_float_flag == AUTO_BOOLEAN_FALSE) | |
3933 | soft_float = 0; | |
3934 | else | |
3935 | soft_float = !have_fpu; | |
3936 | ||
3937 | /* If we have a hard float binary or setting but no floating point | |
3938 | registers, downgrade to soft float anyway. We're still somewhat | |
3939 | useful in this scenario. */ | |
3940 | if (!soft_float && !have_fpu) | |
3941 | soft_float = 1; | |
3942 | ||
3943 | /* Similarly for vector registers. */ | |
3944 | if (vector_abi == POWERPC_VEC_ALTIVEC && !have_altivec) | |
3945 | vector_abi = POWERPC_VEC_GENERIC; | |
3946 | ||
3947 | if (vector_abi == POWERPC_VEC_SPE && !have_spe) | |
3948 | vector_abi = POWERPC_VEC_GENERIC; | |
3949 | ||
3950 | if (vector_abi == POWERPC_VEC_AUTO) | |
3951 | { | |
3952 | if (have_altivec) | |
3953 | vector_abi = POWERPC_VEC_ALTIVEC; | |
3954 | else if (have_spe) | |
3955 | vector_abi = POWERPC_VEC_SPE; | |
3956 | else | |
3957 | vector_abi = POWERPC_VEC_GENERIC; | |
3958 | } | |
3959 | ||
3960 | /* Do not limit the vector ABI based on available hardware, since we | |
3961 | do not yet know what hardware we'll decide we have. Yuck! FIXME! */ | |
3962 | ||
7cc46491 DJ |
3963 | /* Find a candidate among extant architectures. */ |
3964 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
3965 | arches != NULL; | |
3966 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
3967 | { | |
3968 | /* Word size in the various PowerPC bfd_arch_info structs isn't | |
3969 | meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform | |
3970 | separate word size check. */ | |
3971 | tdep = gdbarch_tdep (arches->gdbarch); | |
cd453cd0 UW |
3972 | if (tdep && tdep->elf_abi != elf_abi) |
3973 | continue; | |
55eddb0f DJ |
3974 | if (tdep && tdep->soft_float != soft_float) |
3975 | continue; | |
3976 | if (tdep && tdep->vector_abi != vector_abi) | |
3977 | continue; | |
7cc46491 DJ |
3978 | if (tdep && tdep->wordsize == wordsize) |
3979 | { | |
3980 | if (tdesc_data != NULL) | |
3981 | tdesc_data_cleanup (tdesc_data); | |
3982 | return arches->gdbarch; | |
3983 | } | |
3984 | } | |
3985 | ||
3986 | /* None found, create a new architecture from INFO, whose bfd_arch_info | |
3987 | validity depends on the source: | |
3988 | - executable useless | |
3989 | - rs6000_host_arch() good | |
3990 | - core file good | |
3991 | - "set arch" trust blindly | |
3992 | - GDB startup useless but harmless */ | |
3993 | ||
fc270c35 | 3994 | tdep = XCNEW (struct gdbarch_tdep); |
7cc46491 | 3995 | tdep->wordsize = wordsize; |
cd453cd0 | 3996 | tdep->elf_abi = elf_abi; |
55eddb0f DJ |
3997 | tdep->soft_float = soft_float; |
3998 | tdep->vector_abi = vector_abi; | |
7cc46491 | 3999 | |
7a78ae4e | 4000 | gdbarch = gdbarch_alloc (&info, tdep); |
7a78ae4e | 4001 | |
7cc46491 DJ |
4002 | tdep->ppc_gp0_regnum = PPC_R0_REGNUM; |
4003 | tdep->ppc_toc_regnum = PPC_R0_REGNUM + 2; | |
4004 | tdep->ppc_ps_regnum = PPC_MSR_REGNUM; | |
4005 | tdep->ppc_cr_regnum = PPC_CR_REGNUM; | |
4006 | tdep->ppc_lr_regnum = PPC_LR_REGNUM; | |
4007 | tdep->ppc_ctr_regnum = PPC_CTR_REGNUM; | |
4008 | tdep->ppc_xer_regnum = PPC_XER_REGNUM; | |
4009 | tdep->ppc_mq_regnum = have_mq ? PPC_MQ_REGNUM : -1; | |
4010 | ||
4011 | tdep->ppc_fp0_regnum = have_fpu ? PPC_F0_REGNUM : -1; | |
4012 | tdep->ppc_fpscr_regnum = have_fpu ? PPC_FPSCR_REGNUM : -1; | |
604c2f83 | 4013 | tdep->ppc_vsr0_upper_regnum = have_vsx ? PPC_VSR0_UPPER_REGNUM : -1; |
7cc46491 DJ |
4014 | tdep->ppc_vr0_regnum = have_altivec ? PPC_VR0_REGNUM : -1; |
4015 | tdep->ppc_vrsave_regnum = have_altivec ? PPC_VRSAVE_REGNUM : -1; | |
4016 | tdep->ppc_ev0_upper_regnum = have_spe ? PPC_SPE_UPPER_GP0_REGNUM : -1; | |
4017 | tdep->ppc_acc_regnum = have_spe ? PPC_SPE_ACC_REGNUM : -1; | |
4018 | tdep->ppc_spefscr_regnum = have_spe ? PPC_SPE_FSCR_REGNUM : -1; | |
4019 | ||
4020 | set_gdbarch_pc_regnum (gdbarch, PPC_PC_REGNUM); | |
4021 | set_gdbarch_sp_regnum (gdbarch, PPC_R0_REGNUM + 1); | |
4022 | set_gdbarch_deprecated_fp_regnum (gdbarch, PPC_R0_REGNUM + 1); | |
4023 | set_gdbarch_fp0_regnum (gdbarch, tdep->ppc_fp0_regnum); | |
9f643768 | 4024 | set_gdbarch_register_sim_regno (gdbarch, rs6000_register_sim_regno); |
7cc46491 DJ |
4025 | |
4026 | /* The XML specification for PowerPC sensibly calls the MSR "msr". | |
4027 | GDB traditionally called it "ps", though, so let GDB add an | |
4028 | alias. */ | |
4029 | set_gdbarch_ps_regnum (gdbarch, tdep->ppc_ps_regnum); | |
4030 | ||
4a7622d1 | 4031 | if (wordsize == 8) |
05580c65 | 4032 | set_gdbarch_return_value (gdbarch, ppc64_sysv_abi_return_value); |
afd48b75 | 4033 | else |
4a7622d1 | 4034 | set_gdbarch_return_value (gdbarch, ppc_sysv_abi_return_value); |
c8001721 | 4035 | |
baffbae0 JB |
4036 | /* Set lr_frame_offset. */ |
4037 | if (wordsize == 8) | |
4038 | tdep->lr_frame_offset = 16; | |
baffbae0 | 4039 | else |
4a7622d1 | 4040 | tdep->lr_frame_offset = 4; |
baffbae0 | 4041 | |
604c2f83 | 4042 | if (have_spe || have_dfp || have_vsx) |
7cc46491 | 4043 | { |
f949c649 | 4044 | set_gdbarch_pseudo_register_read (gdbarch, rs6000_pseudo_register_read); |
0df8b418 MS |
4045 | set_gdbarch_pseudo_register_write (gdbarch, |
4046 | rs6000_pseudo_register_write); | |
7cc46491 | 4047 | } |
1fcc0bb8 | 4048 | |
e0d24f8d WZ |
4049 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); |
4050 | ||
56a6dfb9 | 4051 | /* Select instruction printer. */ |
708ff411 | 4052 | if (arch == bfd_arch_rs6000) |
9364a0ef | 4053 | set_gdbarch_print_insn (gdbarch, print_insn_rs6000); |
56a6dfb9 | 4054 | else |
9364a0ef | 4055 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_powerpc); |
7495d1dc | 4056 | |
5a9e69ba | 4057 | set_gdbarch_num_regs (gdbarch, PPC_NUM_REGS); |
f949c649 TJB |
4058 | |
4059 | if (have_spe) | |
4060 | num_pseudoregs += 32; | |
4061 | if (have_dfp) | |
4062 | num_pseudoregs += 16; | |
604c2f83 LM |
4063 | if (have_vsx) |
4064 | /* Include both VSX and Extended FP registers. */ | |
4065 | num_pseudoregs += 96; | |
f949c649 TJB |
4066 | |
4067 | set_gdbarch_num_pseudo_regs (gdbarch, num_pseudoregs); | |
7a78ae4e ND |
4068 | |
4069 | set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT); | |
4070 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); | |
4071 | set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
4072 | set_gdbarch_long_bit (gdbarch, wordsize * TARGET_CHAR_BIT); | |
4073 | set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
4074 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
4075 | set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
4a7622d1 | 4076 | set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT); |
4e409299 | 4077 | set_gdbarch_char_signed (gdbarch, 0); |
7a78ae4e | 4078 | |
11269d7e | 4079 | set_gdbarch_frame_align (gdbarch, rs6000_frame_align); |
4a7622d1 | 4080 | if (wordsize == 8) |
8b148df9 AC |
4081 | /* PPC64 SYSV. */ |
4082 | set_gdbarch_frame_red_zone_size (gdbarch, 288); | |
7a78ae4e | 4083 | |
691d145a JB |
4084 | set_gdbarch_convert_register_p (gdbarch, rs6000_convert_register_p); |
4085 | set_gdbarch_register_to_value (gdbarch, rs6000_register_to_value); | |
4086 | set_gdbarch_value_to_register (gdbarch, rs6000_value_to_register); | |
4087 | ||
18ed0c4e JB |
4088 | set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_stab_reg_to_regnum); |
4089 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rs6000_dwarf2_reg_to_regnum); | |
d217aaed | 4090 | |
4a7622d1 | 4091 | if (wordsize == 4) |
77b2b6d4 | 4092 | set_gdbarch_push_dummy_call (gdbarch, ppc_sysv_abi_push_dummy_call); |
4a7622d1 | 4093 | else if (wordsize == 8) |
8be9034a | 4094 | set_gdbarch_push_dummy_call (gdbarch, ppc64_sysv_abi_push_dummy_call); |
7a78ae4e | 4095 | |
7a78ae4e | 4096 | set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue); |
0d1243d9 | 4097 | set_gdbarch_in_function_epilogue_p (gdbarch, rs6000_in_function_epilogue_p); |
8ab3d180 | 4098 | set_gdbarch_skip_main_prologue (gdbarch, rs6000_skip_main_prologue); |
0d1243d9 | 4099 | |
7a78ae4e | 4100 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
7a78ae4e ND |
4101 | set_gdbarch_breakpoint_from_pc (gdbarch, rs6000_breakpoint_from_pc); |
4102 | ||
203c3895 | 4103 | /* The value of symbols of type N_SO and N_FUN maybe null when |
0df8b418 | 4104 | it shouldn't be. */ |
203c3895 UW |
4105 | set_gdbarch_sofun_address_maybe_missing (gdbarch, 1); |
4106 | ||
ce5eab59 | 4107 | /* Handles single stepping of atomic sequences. */ |
4a7622d1 | 4108 | set_gdbarch_software_single_step (gdbarch, ppc_deal_with_atomic_sequence); |
ce5eab59 | 4109 | |
0df8b418 | 4110 | /* Not sure on this. FIXMEmgo */ |
7a78ae4e ND |
4111 | set_gdbarch_frame_args_skip (gdbarch, 8); |
4112 | ||
143985b7 AF |
4113 | /* Helpers for function argument information. */ |
4114 | set_gdbarch_fetch_pointer_argument (gdbarch, rs6000_fetch_pointer_argument); | |
4115 | ||
6f7f3f0d UW |
4116 | /* Trampoline. */ |
4117 | set_gdbarch_in_solib_return_trampoline | |
4118 | (gdbarch, rs6000_in_solib_return_trampoline); | |
4119 | set_gdbarch_skip_trampoline_code (gdbarch, rs6000_skip_trampoline_code); | |
4120 | ||
4fc771b8 | 4121 | /* Hook in the DWARF CFI frame unwinder. */ |
1af5d7ce | 4122 | dwarf2_append_unwinders (gdbarch); |
4fc771b8 DJ |
4123 | dwarf2_frame_set_adjust_regnum (gdbarch, rs6000_adjust_frame_regnum); |
4124 | ||
9274a07c LM |
4125 | /* Frame handling. */ |
4126 | dwarf2_frame_set_init_reg (gdbarch, ppc_dwarf2_frame_init_reg); | |
4127 | ||
2454a024 UW |
4128 | /* Setup displaced stepping. */ |
4129 | set_gdbarch_displaced_step_copy_insn (gdbarch, | |
4130 | simple_displaced_step_copy_insn); | |
99e40580 UW |
4131 | set_gdbarch_displaced_step_hw_singlestep (gdbarch, |
4132 | ppc_displaced_step_hw_singlestep); | |
2454a024 UW |
4133 | set_gdbarch_displaced_step_fixup (gdbarch, ppc_displaced_step_fixup); |
4134 | set_gdbarch_displaced_step_free_closure (gdbarch, | |
4135 | simple_displaced_step_free_closure); | |
4136 | set_gdbarch_displaced_step_location (gdbarch, | |
4137 | displaced_step_at_entry_point); | |
4138 | ||
4139 | set_gdbarch_max_insn_length (gdbarch, PPC_INSN_SIZE); | |
4140 | ||
7b112f9c | 4141 | /* Hook in ABI-specific overrides, if they have been registered. */ |
8a4c2d24 UW |
4142 | info.target_desc = tdesc; |
4143 | info.tdep_info = (void *) tdesc_data; | |
4be87837 | 4144 | gdbarch_init_osabi (info, gdbarch); |
7b112f9c | 4145 | |
61a65099 KB |
4146 | switch (info.osabi) |
4147 | { | |
f5aecab8 | 4148 | case GDB_OSABI_LINUX: |
61a65099 KB |
4149 | case GDB_OSABI_NETBSD_AOUT: |
4150 | case GDB_OSABI_NETBSD_ELF: | |
4151 | case GDB_OSABI_UNKNOWN: | |
61a65099 | 4152 | set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc); |
1af5d7ce UW |
4153 | frame_unwind_append_unwinder (gdbarch, &rs6000_frame_unwind); |
4154 | set_gdbarch_dummy_id (gdbarch, rs6000_dummy_id); | |
61a65099 KB |
4155 | frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer); |
4156 | break; | |
4157 | default: | |
61a65099 | 4158 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); |
81332287 KB |
4159 | |
4160 | set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc); | |
1af5d7ce UW |
4161 | frame_unwind_append_unwinder (gdbarch, &rs6000_frame_unwind); |
4162 | set_gdbarch_dummy_id (gdbarch, rs6000_dummy_id); | |
81332287 | 4163 | frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer); |
61a65099 KB |
4164 | } |
4165 | ||
7cc46491 DJ |
4166 | set_tdesc_pseudo_register_type (gdbarch, rs6000_pseudo_register_type); |
4167 | set_tdesc_pseudo_register_reggroup_p (gdbarch, | |
4168 | rs6000_pseudo_register_reggroup_p); | |
4169 | tdesc_use_registers (gdbarch, tdesc, tdesc_data); | |
4170 | ||
4171 | /* Override the normal target description method to make the SPE upper | |
4172 | halves anonymous. */ | |
4173 | set_gdbarch_register_name (gdbarch, rs6000_register_name); | |
4174 | ||
604c2f83 LM |
4175 | /* Choose register numbers for all supported pseudo-registers. */ |
4176 | tdep->ppc_ev0_regnum = -1; | |
4177 | tdep->ppc_dl0_regnum = -1; | |
4178 | tdep->ppc_vsr0_regnum = -1; | |
4179 | tdep->ppc_efpr0_regnum = -1; | |
9f643768 | 4180 | |
604c2f83 LM |
4181 | cur_reg = gdbarch_num_regs (gdbarch); |
4182 | ||
4183 | if (have_spe) | |
4184 | { | |
4185 | tdep->ppc_ev0_regnum = cur_reg; | |
4186 | cur_reg += 32; | |
4187 | } | |
4188 | if (have_dfp) | |
4189 | { | |
4190 | tdep->ppc_dl0_regnum = cur_reg; | |
4191 | cur_reg += 16; | |
4192 | } | |
4193 | if (have_vsx) | |
4194 | { | |
4195 | tdep->ppc_vsr0_regnum = cur_reg; | |
4196 | cur_reg += 64; | |
4197 | tdep->ppc_efpr0_regnum = cur_reg; | |
4198 | cur_reg += 32; | |
4199 | } | |
f949c649 | 4200 | |
604c2f83 LM |
4201 | gdb_assert (gdbarch_num_regs (gdbarch) |
4202 | + gdbarch_num_pseudo_regs (gdbarch) == cur_reg); | |
f949c649 | 4203 | |
debb1f09 JB |
4204 | /* Register the ravenscar_arch_ops. */ |
4205 | if (mach == bfd_mach_ppc_e500) | |
4206 | register_e500_ravenscar_ops (gdbarch); | |
4207 | else | |
4208 | register_ppc_ravenscar_ops (gdbarch); | |
4209 | ||
7a78ae4e | 4210 | return gdbarch; |
c906108c SS |
4211 | } |
4212 | ||
7b112f9c | 4213 | static void |
8b164abb | 4214 | rs6000_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
7b112f9c | 4215 | { |
8b164abb | 4216 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7b112f9c JT |
4217 | |
4218 | if (tdep == NULL) | |
4219 | return; | |
4220 | ||
4be87837 | 4221 | /* FIXME: Dump gdbarch_tdep. */ |
7b112f9c JT |
4222 | } |
4223 | ||
55eddb0f DJ |
4224 | /* PowerPC-specific commands. */ |
4225 | ||
4226 | static void | |
4227 | set_powerpc_command (char *args, int from_tty) | |
4228 | { | |
4229 | printf_unfiltered (_("\ | |
4230 | \"set powerpc\" must be followed by an appropriate subcommand.\n")); | |
4231 | help_list (setpowerpccmdlist, "set powerpc ", all_commands, gdb_stdout); | |
4232 | } | |
4233 | ||
4234 | static void | |
4235 | show_powerpc_command (char *args, int from_tty) | |
4236 | { | |
4237 | cmd_show_list (showpowerpccmdlist, from_tty, ""); | |
4238 | } | |
4239 | ||
4240 | static void | |
4241 | powerpc_set_soft_float (char *args, int from_tty, | |
4242 | struct cmd_list_element *c) | |
4243 | { | |
4244 | struct gdbarch_info info; | |
4245 | ||
4246 | /* Update the architecture. */ | |
4247 | gdbarch_info_init (&info); | |
4248 | if (!gdbarch_update_p (info)) | |
9b20d036 | 4249 | internal_error (__FILE__, __LINE__, _("could not update architecture")); |
55eddb0f DJ |
4250 | } |
4251 | ||
4252 | static void | |
4253 | powerpc_set_vector_abi (char *args, int from_tty, | |
4254 | struct cmd_list_element *c) | |
4255 | { | |
4256 | struct gdbarch_info info; | |
4257 | enum powerpc_vector_abi vector_abi; | |
4258 | ||
4259 | for (vector_abi = POWERPC_VEC_AUTO; | |
4260 | vector_abi != POWERPC_VEC_LAST; | |
4261 | vector_abi++) | |
4262 | if (strcmp (powerpc_vector_abi_string, | |
4263 | powerpc_vector_strings[vector_abi]) == 0) | |
4264 | { | |
4265 | powerpc_vector_abi_global = vector_abi; | |
4266 | break; | |
4267 | } | |
4268 | ||
4269 | if (vector_abi == POWERPC_VEC_LAST) | |
4270 | internal_error (__FILE__, __LINE__, _("Invalid vector ABI accepted: %s."), | |
4271 | powerpc_vector_abi_string); | |
4272 | ||
4273 | /* Update the architecture. */ | |
4274 | gdbarch_info_init (&info); | |
4275 | if (!gdbarch_update_p (info)) | |
9b20d036 | 4276 | internal_error (__FILE__, __LINE__, _("could not update architecture")); |
55eddb0f DJ |
4277 | } |
4278 | ||
e09342b5 TJB |
4279 | /* Show the current setting of the exact watchpoints flag. */ |
4280 | ||
4281 | static void | |
4282 | show_powerpc_exact_watchpoints (struct ui_file *file, int from_tty, | |
4283 | struct cmd_list_element *c, | |
4284 | const char *value) | |
4285 | { | |
4286 | fprintf_filtered (file, _("Use of exact watchpoints is %s.\n"), value); | |
4287 | } | |
4288 | ||
845d4708 | 4289 | /* Read a PPC instruction from memory. */ |
d78489bf AT |
4290 | |
4291 | static unsigned int | |
845d4708 | 4292 | read_insn (struct frame_info *frame, CORE_ADDR pc) |
d78489bf | 4293 | { |
845d4708 AM |
4294 | struct gdbarch *gdbarch = get_frame_arch (frame); |
4295 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
4296 | ||
4297 | return read_memory_unsigned_integer (pc, 4, byte_order); | |
d78489bf AT |
4298 | } |
4299 | ||
4300 | /* Return non-zero if the instructions at PC match the series | |
4301 | described in PATTERN, or zero otherwise. PATTERN is an array of | |
4302 | 'struct ppc_insn_pattern' objects, terminated by an entry whose | |
4303 | mask is zero. | |
4304 | ||
4305 | When the match is successful, fill INSN[i] with what PATTERN[i] | |
4306 | matched. If PATTERN[i] is optional, and the instruction wasn't | |
4307 | present, set INSN[i] to 0 (which is not a valid PPC instruction). | |
4308 | INSN should have as many elements as PATTERN. Note that, if | |
4309 | PATTERN contains optional instructions which aren't present in | |
4310 | memory, then INSN will have holes, so INSN[i] isn't necessarily the | |
4311 | i'th instruction in memory. */ | |
4312 | ||
4313 | int | |
845d4708 AM |
4314 | ppc_insns_match_pattern (struct frame_info *frame, CORE_ADDR pc, |
4315 | struct ppc_insn_pattern *pattern, | |
4316 | unsigned int *insns) | |
d78489bf AT |
4317 | { |
4318 | int i; | |
845d4708 | 4319 | unsigned int insn; |
d78489bf | 4320 | |
845d4708 | 4321 | for (i = 0, insn = 0; pattern[i].mask; i++) |
d78489bf | 4322 | { |
845d4708 AM |
4323 | if (insn == 0) |
4324 | insn = read_insn (frame, pc); | |
4325 | insns[i] = 0; | |
4326 | if ((insn & pattern[i].mask) == pattern[i].data) | |
4327 | { | |
4328 | insns[i] = insn; | |
4329 | pc += 4; | |
4330 | insn = 0; | |
4331 | } | |
4332 | else if (!pattern[i].optional) | |
d78489bf AT |
4333 | return 0; |
4334 | } | |
4335 | ||
4336 | return 1; | |
4337 | } | |
4338 | ||
4339 | /* Return the 'd' field of the d-form instruction INSN, properly | |
4340 | sign-extended. */ | |
4341 | ||
4342 | CORE_ADDR | |
4343 | ppc_insn_d_field (unsigned int insn) | |
4344 | { | |
4345 | return ((((CORE_ADDR) insn & 0xffff) ^ 0x8000) - 0x8000); | |
4346 | } | |
4347 | ||
4348 | /* Return the 'ds' field of the ds-form instruction INSN, with the two | |
4349 | zero bits concatenated at the right, and properly | |
4350 | sign-extended. */ | |
4351 | ||
4352 | CORE_ADDR | |
4353 | ppc_insn_ds_field (unsigned int insn) | |
4354 | { | |
4355 | return ((((CORE_ADDR) insn & 0xfffc) ^ 0x8000) - 0x8000); | |
4356 | } | |
4357 | ||
c906108c SS |
4358 | /* Initialization code. */ |
4359 | ||
0df8b418 MS |
4360 | /* -Wmissing-prototypes */ |
4361 | extern initialize_file_ftype _initialize_rs6000_tdep; | |
b9362cc7 | 4362 | |
c906108c | 4363 | void |
fba45db2 | 4364 | _initialize_rs6000_tdep (void) |
c906108c | 4365 | { |
7b112f9c JT |
4366 | gdbarch_register (bfd_arch_rs6000, rs6000_gdbarch_init, rs6000_dump_tdep); |
4367 | gdbarch_register (bfd_arch_powerpc, rs6000_gdbarch_init, rs6000_dump_tdep); | |
7cc46491 DJ |
4368 | |
4369 | /* Initialize the standard target descriptions. */ | |
4370 | initialize_tdesc_powerpc_32 (); | |
7284e1be | 4371 | initialize_tdesc_powerpc_altivec32 (); |
604c2f83 | 4372 | initialize_tdesc_powerpc_vsx32 (); |
7cc46491 DJ |
4373 | initialize_tdesc_powerpc_403 (); |
4374 | initialize_tdesc_powerpc_403gc (); | |
4d09ffea | 4375 | initialize_tdesc_powerpc_405 (); |
7cc46491 DJ |
4376 | initialize_tdesc_powerpc_505 (); |
4377 | initialize_tdesc_powerpc_601 (); | |
4378 | initialize_tdesc_powerpc_602 (); | |
4379 | initialize_tdesc_powerpc_603 (); | |
4380 | initialize_tdesc_powerpc_604 (); | |
4381 | initialize_tdesc_powerpc_64 (); | |
7284e1be | 4382 | initialize_tdesc_powerpc_altivec64 (); |
604c2f83 | 4383 | initialize_tdesc_powerpc_vsx64 (); |
7cc46491 DJ |
4384 | initialize_tdesc_powerpc_7400 (); |
4385 | initialize_tdesc_powerpc_750 (); | |
4386 | initialize_tdesc_powerpc_860 (); | |
4387 | initialize_tdesc_powerpc_e500 (); | |
4388 | initialize_tdesc_rs6000 (); | |
55eddb0f DJ |
4389 | |
4390 | /* Add root prefix command for all "set powerpc"/"show powerpc" | |
4391 | commands. */ | |
4392 | add_prefix_cmd ("powerpc", no_class, set_powerpc_command, | |
4393 | _("Various PowerPC-specific commands."), | |
4394 | &setpowerpccmdlist, "set powerpc ", 0, &setlist); | |
4395 | ||
4396 | add_prefix_cmd ("powerpc", no_class, show_powerpc_command, | |
4397 | _("Various PowerPC-specific commands."), | |
4398 | &showpowerpccmdlist, "show powerpc ", 0, &showlist); | |
4399 | ||
4400 | /* Add a command to allow the user to force the ABI. */ | |
4401 | add_setshow_auto_boolean_cmd ("soft-float", class_support, | |
4402 | &powerpc_soft_float_global, | |
4403 | _("Set whether to use a soft-float ABI."), | |
4404 | _("Show whether to use a soft-float ABI."), | |
4405 | NULL, | |
4406 | powerpc_set_soft_float, NULL, | |
4407 | &setpowerpccmdlist, &showpowerpccmdlist); | |
4408 | ||
4409 | add_setshow_enum_cmd ("vector-abi", class_support, powerpc_vector_strings, | |
4410 | &powerpc_vector_abi_string, | |
4411 | _("Set the vector ABI."), | |
4412 | _("Show the vector ABI."), | |
4413 | NULL, powerpc_set_vector_abi, NULL, | |
4414 | &setpowerpccmdlist, &showpowerpccmdlist); | |
e09342b5 TJB |
4415 | |
4416 | add_setshow_boolean_cmd ("exact-watchpoints", class_support, | |
4417 | &target_exact_watchpoints, | |
4418 | _("\ | |
4419 | Set whether to use just one debug register for watchpoints on scalars."), | |
4420 | _("\ | |
4421 | Show whether to use just one debug register for watchpoints on scalars."), | |
4422 | _("\ | |
4423 | If true, GDB will use only one debug register when watching a variable of\n\ | |
4424 | scalar type, thus assuming that the variable is accessed through the address\n\ | |
4425 | of its first byte."), | |
4426 | NULL, show_powerpc_exact_watchpoints, | |
4427 | &setpowerpccmdlist, &showpowerpccmdlist); | |
c906108c | 4428 | } |