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[deliverable/binutils-gdb.git] / gdb / rs6000-tdep.c
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c906108c 1/* Target-dependent code for GDB, the GNU debugger.
7aea86e6 2
6aba47ca 3 Copyright (C) 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
0fb0cc75 4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
721d14ba 5 Free Software Foundation, Inc.
c906108c 6
c5aa993b 7 This file is part of GDB.
c906108c 8
c5aa993b
JM		 9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
a9762ec7 11 the Free Software Foundation; either version 3 of the License, or
c5aa993b 12 (at your option) any later version.
c906108c 13
c5aa993b
JM		 14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
c906108c 18
c5aa993b 19 You should have received a copy of the GNU General Public License
a9762ec7 20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
c906108c
SS		 21
22#include "defs.h"
23#include "frame.h"
24#include "inferior.h"
25#include "symtab.h"
26#include "target.h"
27#include "gdbcore.h"
28#include "gdbcmd.h"
c906108c 29#include "objfiles.h"
7a78ae4e 30#include "arch-utils.h"
4e052eda 31#include "regcache.h"
d195bc9f 32#include "regset.h"
d16aafd8 33#include "doublest.h"
fd0407d6 34#include "value.h"
1fcc0bb8 35#include "parser-defs.h"
4be87837 36#include "osabi.h"
7d9b040b 37#include "infcall.h"
9f643768
JB		 38#include "sim-regno.h"
39#include "gdb/sim-ppc.h"
6ced10dd 40#include "reggroups.h"
4fc771b8 41#include "dwarf2-frame.h"
7cc46491
DJ		 42#include "target-descriptions.h"
43#include "user-regs.h"
7a78ae4e 44
2fccf04a 45#include "libbfd.h" /* for bfd_default_set_arch_mach */
7a78ae4e 46#include "coff/internal.h" /* for libcoff.h */
2fccf04a 47#include "libcoff.h" /* for xcoff_data */
11ed25ac
KB		 48#include "coff/xcoff.h"
49#include "libxcoff.h"
7a78ae4e 50
9aa1e687 51#include "elf-bfd.h"
55eddb0f 52#include "elf/ppc.h"
7a78ae4e 53
6ded7999 54#include "solib-svr4.h"
9aa1e687 55#include "ppc-tdep.h"
7a78ae4e 56
338ef23d 57#include "gdb_assert.h"
a89aa300 58#include "dis-asm.h"
338ef23d 59
61a65099
KB		 60#include "trad-frame.h"
61#include "frame-unwind.h"
62#include "frame-base.h"
63
7cc46491 64#include "features/rs6000/powerpc-32.c"
7284e1be 65#include "features/rs6000/powerpc-altivec32.c"
604c2f83 66#include "features/rs6000/powerpc-vsx32.c"
7cc46491
DJ		 67#include "features/rs6000/powerpc-403.c"
68#include "features/rs6000/powerpc-403gc.c"
4d09ffea 69#include "features/rs6000/powerpc-405.c"
7cc46491
DJ		 70#include "features/rs6000/powerpc-505.c"
71#include "features/rs6000/powerpc-601.c"
72#include "features/rs6000/powerpc-602.c"
73#include "features/rs6000/powerpc-603.c"
74#include "features/rs6000/powerpc-604.c"
75#include "features/rs6000/powerpc-64.c"
7284e1be 76#include "features/rs6000/powerpc-altivec64.c"
604c2f83 77#include "features/rs6000/powerpc-vsx64.c"
7cc46491
DJ		 78#include "features/rs6000/powerpc-7400.c"
79#include "features/rs6000/powerpc-750.c"
80#include "features/rs6000/powerpc-860.c"
81#include "features/rs6000/powerpc-e500.c"
82#include "features/rs6000/rs6000.c"
83
5a9e69ba
TJB		 84/* Determine if regnum is an SPE pseudo-register. */
85#define IS_SPE_PSEUDOREG(tdep, regnum) ((tdep)->ppc_ev0_regnum >= 0 \
86 && (regnum) >= (tdep)->ppc_ev0_regnum \
87 && (regnum) < (tdep)->ppc_ev0_regnum + 32)
88
f949c649
TJB		 89/* Determine if regnum is a decimal float pseudo-register. */
90#define IS_DFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_dl0_regnum >= 0 \
91 && (regnum) >= (tdep)->ppc_dl0_regnum \
92 && (regnum) < (tdep)->ppc_dl0_regnum + 16)
93
604c2f83
LM		 94/* Determine if regnum is a POWER7 VSX register. */
95#define IS_VSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_vsr0_regnum >= 0 \
96 && (regnum) >= (tdep)->ppc_vsr0_regnum \
97 && (regnum) < (tdep)->ppc_vsr0_regnum + ppc_num_vsrs)
98
99/* Determine if regnum is a POWER7 Extended FP register. */
100#define IS_EFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_efpr0_regnum >= 0 \
101 && (regnum) >= (tdep)->ppc_efpr0_regnum \
102 && (regnum) < (tdep)->ppc_efpr0_regnum + ppc_num_fprs)
103
55eddb0f
DJ		 104/* The list of available "set powerpc ..." and "show powerpc ..."
105 commands. */
106static struct cmd_list_element *setpowerpccmdlist = NULL;
107static struct cmd_list_element *showpowerpccmdlist = NULL;
108
109static enum auto_boolean powerpc_soft_float_global = AUTO_BOOLEAN_AUTO;
110
111/* The vector ABI to use. Keep this in sync with powerpc_vector_abi. */
112static const char *powerpc_vector_strings[] =
113{
114 "auto",
115 "generic",
116 "altivec",
117 "spe",
118 NULL
119};
120
121/* A variable that can be configured by the user. */
122static enum powerpc_vector_abi powerpc_vector_abi_global = POWERPC_VEC_AUTO;
123static const char *powerpc_vector_abi_string = "auto";
124
7a78ae4e
ND		 125/* To be used by skip_prologue. */
126
127struct rs6000_framedata
128 {
129 int offset; /* total size of frame --- the distance
130 by which we decrement sp to allocate
131 the frame */
132 int saved_gpr; /* smallest # of saved gpr */
46a9b8ed 133 unsigned int gpr_mask; /* Each bit is an individual saved GPR. */
7a78ae4e 134 int saved_fpr; /* smallest # of saved fpr */
6be8bc0c 135 int saved_vr; /* smallest # of saved vr */
96ff0de4 136 int saved_ev; /* smallest # of saved ev */
7a78ae4e
ND		 137 int alloca_reg; /* alloca register number (frame ptr) */
138 char frameless; /* true if frameless functions. */
139 char nosavedpc; /* true if pc not saved. */
46a9b8ed 140 char used_bl; /* true if link register clobbered */
7a78ae4e
ND		 141 int gpr_offset; /* offset of saved gprs from prev sp */
142 int fpr_offset; /* offset of saved fprs from prev sp */
6be8bc0c 143 int vr_offset; /* offset of saved vrs from prev sp */
96ff0de4 144 int ev_offset; /* offset of saved evs from prev sp */
7a78ae4e 145 int lr_offset; /* offset of saved lr */
46a9b8ed 146 int lr_register; /* register of saved lr, if trustworthy */
7a78ae4e 147 int cr_offset; /* offset of saved cr */
6be8bc0c 148 int vrsave_offset; /* offset of saved vrsave register */
7a78ae4e
ND		 149 };
150
c906108c 151
604c2f83
LM		 152/* Is REGNO a VSX register? Return 1 if so, 0 otherwise. */
153int
154vsx_register_p (struct gdbarch *gdbarch, int regno)
155{
156 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
157 if (tdep->ppc_vsr0_regnum < 0)
158 return 0;
159 else
160 return (regno >= tdep->ppc_vsr0_upper_regnum && regno
161 <= tdep->ppc_vsr0_upper_regnum + 31);
162}
163
64b84175
KB		 164/* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
165int
be8626e0 166altivec_register_p (struct gdbarch *gdbarch, int regno)
64b84175 167{
be8626e0 168 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
64b84175
KB		 169 if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0)
170 return 0;
171 else
172 return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum);
173}
174
383f0f5b 175
867e2dc5
JB		 176/* Return true if REGNO is an SPE register, false otherwise. */
177int
be8626e0 178spe_register_p (struct gdbarch *gdbarch, int regno)
867e2dc5 179{
be8626e0 180 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
867e2dc5
JB		 181
182 /* Is it a reference to EV0 -- EV31, and do we have those? */
5a9e69ba 183 if (IS_SPE_PSEUDOREG (tdep, regno))
867e2dc5
JB		 184 return 1;
185
6ced10dd
JB		 186 /* Is it a reference to one of the raw upper GPR halves? */
187 if (tdep->ppc_ev0_upper_regnum >= 0
188 && tdep->ppc_ev0_upper_regnum <= regno
189 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
190 return 1;
191
867e2dc5
JB		 192 /* Is it a reference to the 64-bit accumulator, and do we have that? */
193 if (tdep->ppc_acc_regnum >= 0
194 && tdep->ppc_acc_regnum == regno)
195 return 1;
196
197 /* Is it a reference to the SPE floating-point status and control register,
198 and do we have that? */
199 if (tdep->ppc_spefscr_regnum >= 0
200 && tdep->ppc_spefscr_regnum == regno)
201 return 1;
202
203 return 0;
204}
205
206
383f0f5b
JB		 207/* Return non-zero if the architecture described by GDBARCH has
208 floating-point registers (f0 --- f31 and fpscr). */
0a613259
AC		 209int
210ppc_floating_point_unit_p (struct gdbarch *gdbarch)
211{
383f0f5b
JB		 212 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
213
214 return (tdep->ppc_fp0_regnum >= 0
215 && tdep->ppc_fpscr_regnum >= 0);
0a613259 216}
9f643768 217
604c2f83
LM		 218/* Return non-zero if the architecture described by GDBARCH has
219 VSX registers (vsr0 --- vsr63). */
63807e1d 220static int
604c2f83
LM		 221ppc_vsx_support_p (struct gdbarch *gdbarch)
222{
223 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
224
225 return tdep->ppc_vsr0_regnum >= 0;
226}
227
06caf7d2
CES		 228/* Return non-zero if the architecture described by GDBARCH has
229 Altivec registers (vr0 --- vr31, vrsave and vscr). */
230int
231ppc_altivec_support_p (struct gdbarch *gdbarch)
232{
233 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
234
235 return (tdep->ppc_vr0_regnum >= 0
236 && tdep->ppc_vrsave_regnum >= 0);
237}
09991fa0
JB		 238
239/* Check that TABLE[GDB_REGNO] is not already initialized, and then
240 set it to SIM_REGNO.
241
242 This is a helper function for init_sim_regno_table, constructing
243 the table mapping GDB register numbers to sim register numbers; we
244 initialize every element in that table to -1 before we start
245 filling it in. */
9f643768
JB		 246static void
247set_sim_regno (int *table, int gdb_regno, int sim_regno)
248{
249 /* Make sure we don't try to assign any given GDB register a sim
250 register number more than once. */
251 gdb_assert (table[gdb_regno] == -1);
252 table[gdb_regno] = sim_regno;
253}
254
09991fa0
JB		 255
256/* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
257 numbers to simulator register numbers, based on the values placed
258 in the ARCH->tdep->ppc_foo_regnum members. */
9f643768
JB		 259static void
260init_sim_regno_table (struct gdbarch *arch)
261{
262 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
7cc46491 263 int total_regs = gdbarch_num_regs (arch);
9f643768
JB		 264 int *sim_regno = GDBARCH_OBSTACK_CALLOC (arch, total_regs, int);
265 int i;
7cc46491
DJ		 266 static const char *const segment_regs[] = {
267 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
268 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
269 };
9f643768
JB		 270
271 /* Presume that all registers not explicitly mentioned below are
272 unavailable from the sim. */
273 for (i = 0; i < total_regs; i++)
274 sim_regno[i] = -1;
275
276 /* General-purpose registers. */
277 for (i = 0; i < ppc_num_gprs; i++)
278 set_sim_regno (sim_regno, tdep->ppc_gp0_regnum + i, sim_ppc_r0_regnum + i);
279
280 /* Floating-point registers. */
281 if (tdep->ppc_fp0_regnum >= 0)
282 for (i = 0; i < ppc_num_fprs; i++)
283 set_sim_regno (sim_regno,
284 tdep->ppc_fp0_regnum + i,
285 sim_ppc_f0_regnum + i);
286 if (tdep->ppc_fpscr_regnum >= 0)
287 set_sim_regno (sim_regno, tdep->ppc_fpscr_regnum, sim_ppc_fpscr_regnum);
288
289 set_sim_regno (sim_regno, gdbarch_pc_regnum (arch), sim_ppc_pc_regnum);
290 set_sim_regno (sim_regno, tdep->ppc_ps_regnum, sim_ppc_ps_regnum);
291 set_sim_regno (sim_regno, tdep->ppc_cr_regnum, sim_ppc_cr_regnum);
292
293 /* Segment registers. */
7cc46491
DJ		 294 for (i = 0; i < ppc_num_srs; i++)
295 {
296 int gdb_regno;
297
298 gdb_regno = user_reg_map_name_to_regnum (arch, segment_regs[i], -1);
299 if (gdb_regno >= 0)
300 set_sim_regno (sim_regno, gdb_regno, sim_ppc_sr0_regnum + i);
301 }
9f643768
JB		 302
303 /* Altivec registers. */
304 if (tdep->ppc_vr0_regnum >= 0)
305 {
306 for (i = 0; i < ppc_num_vrs; i++)
307 set_sim_regno (sim_regno,
308 tdep->ppc_vr0_regnum + i,
309 sim_ppc_vr0_regnum + i);
310
311 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
312 we can treat this more like the other cases. */
313 set_sim_regno (sim_regno,
314 tdep->ppc_vr0_regnum + ppc_num_vrs,
315 sim_ppc_vscr_regnum);
316 }
317 /* vsave is a special-purpose register, so the code below handles it. */
318
319 /* SPE APU (E500) registers. */
6ced10dd
JB		 320 if (tdep->ppc_ev0_upper_regnum >= 0)
321 for (i = 0; i < ppc_num_gprs; i++)
322 set_sim_regno (sim_regno,
323 tdep->ppc_ev0_upper_regnum + i,
324 sim_ppc_rh0_regnum + i);
9f643768
JB		 325 if (tdep->ppc_acc_regnum >= 0)
326 set_sim_regno (sim_regno, tdep->ppc_acc_regnum, sim_ppc_acc_regnum);
327 /* spefscr is a special-purpose register, so the code below handles it. */
328
7cc46491 329#ifdef WITH_SIM
9f643768
JB		 330 /* Now handle all special-purpose registers. Verify that they
331 haven't mistakenly been assigned numbers by any of the above
7cc46491
DJ		 332 code. */
333 for (i = 0; i < sim_ppc_num_sprs; i++)
334 {
335 const char *spr_name = sim_spr_register_name (i);
336 int gdb_regno = -1;
337
338 if (spr_name != NULL)
339 gdb_regno = user_reg_map_name_to_regnum (arch, spr_name, -1);
340
341 if (gdb_regno != -1)
342 set_sim_regno (sim_regno, gdb_regno, sim_ppc_spr0_regnum + i);
343 }
344#endif
9f643768
JB		 345
346 /* Drop the initialized array into place. */
347 tdep->sim_regno = sim_regno;
348}
349
09991fa0
JB		 350
351/* Given a GDB register number REG, return the corresponding SIM
352 register number. */
9f643768 353static int
e7faf938 354rs6000_register_sim_regno (struct gdbarch *gdbarch, int reg)
9f643768 355{
e7faf938 356 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
9f643768
JB		 357 int sim_regno;
358
7cc46491 359 if (tdep->sim_regno == NULL)
e7faf938 360 init_sim_regno_table (gdbarch);
7cc46491 361
f57d151a 362 gdb_assert (0 <= reg
e7faf938
MD		 363 && reg <= gdbarch_num_regs (gdbarch)
364 + gdbarch_num_pseudo_regs (gdbarch));
9f643768
JB		 365 sim_regno = tdep->sim_regno[reg];
366
367 if (sim_regno >= 0)
368 return sim_regno;
369 else
370 return LEGACY_SIM_REGNO_IGNORE;
371}
372
d195bc9f
MK		 373\f
374
375/* Register set support functions. */
376
f2db237a
AM		 377/* REGS + OFFSET contains register REGNUM in a field REGSIZE wide.
378 Write the register to REGCACHE. */
379
7284e1be 380void
d195bc9f 381ppc_supply_reg (struct regcache *regcache, int regnum,
f2db237a 382 const gdb_byte *regs, size_t offset, int regsize)
d195bc9f
MK		 383{
384 if (regnum != -1 && offset != -1)
f2db237a
AM		 385 {
386 if (regsize > 4)
387 {
388 struct gdbarch *gdbarch = get_regcache_arch (regcache);
389 int gdb_regsize = register_size (gdbarch, regnum);
390 if (gdb_regsize < regsize
391 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
392 offset += regsize - gdb_regsize;
393 }
394 regcache_raw_supply (regcache, regnum, regs + offset);
395 }
d195bc9f
MK		 396}
397
f2db237a
AM		 398/* Read register REGNUM from REGCACHE and store to REGS + OFFSET
399 in a field REGSIZE wide. Zero pad as necessary. */
400
7284e1be 401void
d195bc9f 402ppc_collect_reg (const struct regcache *regcache, int regnum,
f2db237a 403 gdb_byte *regs, size_t offset, int regsize)
d195bc9f
MK		 404{
405 if (regnum != -1 && offset != -1)
f2db237a
AM		 406 {
407 if (regsize > 4)
408 {
409 struct gdbarch *gdbarch = get_regcache_arch (regcache);
410 int gdb_regsize = register_size (gdbarch, regnum);
411 if (gdb_regsize < regsize)
412 {
413 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
414 {
415 memset (regs + offset, 0, regsize - gdb_regsize);
416 offset += regsize - gdb_regsize;
417 }
418 else
419 memset (regs + offset + regsize - gdb_regsize, 0,
420 regsize - gdb_regsize);
421 }
422 }
423 regcache_raw_collect (regcache, regnum, regs + offset);
424 }
d195bc9f
MK		 425}
426
f2db237a
AM		 427static int
428ppc_greg_offset (struct gdbarch *gdbarch,
429 struct gdbarch_tdep *tdep,
430 const struct ppc_reg_offsets *offsets,
431 int regnum,
432 int *regsize)
433{
434 *regsize = offsets->gpr_size;
435 if (regnum >= tdep->ppc_gp0_regnum
436 && regnum < tdep->ppc_gp0_regnum + ppc_num_gprs)
437 return (offsets->r0_offset
438 + (regnum - tdep->ppc_gp0_regnum) * offsets->gpr_size);
439
440 if (regnum == gdbarch_pc_regnum (gdbarch))
441 return offsets->pc_offset;
442
443 if (regnum == tdep->ppc_ps_regnum)
444 return offsets->ps_offset;
445
446 if (regnum == tdep->ppc_lr_regnum)
447 return offsets->lr_offset;
448
449 if (regnum == tdep->ppc_ctr_regnum)
450 return offsets->ctr_offset;
451
452 *regsize = offsets->xr_size;
453 if (regnum == tdep->ppc_cr_regnum)
454 return offsets->cr_offset;
455
456 if (regnum == tdep->ppc_xer_regnum)
457 return offsets->xer_offset;
458
459 if (regnum == tdep->ppc_mq_regnum)
460 return offsets->mq_offset;
461
462 return -1;
463}
464
465static int
466ppc_fpreg_offset (struct gdbarch_tdep *tdep,
467 const struct ppc_reg_offsets *offsets,
468 int regnum)
469{
470 if (regnum >= tdep->ppc_fp0_regnum
471 && regnum < tdep->ppc_fp0_regnum + ppc_num_fprs)
472 return offsets->f0_offset + (regnum - tdep->ppc_fp0_regnum) * 8;
473
474 if (regnum == tdep->ppc_fpscr_regnum)
475 return offsets->fpscr_offset;
476
477 return -1;
478}
479
06caf7d2
CES		 480static int
481ppc_vrreg_offset (struct gdbarch_tdep *tdep,
482 const struct ppc_reg_offsets *offsets,
483 int regnum)
484{
485 if (regnum >= tdep->ppc_vr0_regnum
486 && regnum < tdep->ppc_vr0_regnum + ppc_num_vrs)
487 return offsets->vr0_offset + (regnum - tdep->ppc_vr0_regnum) * 16;
488
489 if (regnum == tdep->ppc_vrsave_regnum - 1)
490 return offsets->vscr_offset;
491
492 if (regnum == tdep->ppc_vrsave_regnum)
493 return offsets->vrsave_offset;
494
495 return -1;
496}
497
d195bc9f
MK		 498/* Supply register REGNUM in the general-purpose register set REGSET
499 from the buffer specified by GREGS and LEN to register cache
500 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
501
502void
503ppc_supply_gregset (const struct regset *regset, struct regcache *regcache,
504 int regnum, const void *gregs, size_t len)
505{
506 struct gdbarch *gdbarch = get_regcache_arch (regcache);
507 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
508 const struct ppc_reg_offsets *offsets = regset->descr;
509 size_t offset;
f2db237a 510 int regsize;
d195bc9f 511
f2db237a 512 if (regnum == -1)
d195bc9f 513 {
f2db237a
AM		 514 int i;
515 int gpr_size = offsets->gpr_size;
516
517 for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset;
518 i < tdep->ppc_gp0_regnum + ppc_num_gprs;
519 i++, offset += gpr_size)
520 ppc_supply_reg (regcache, i, gregs, offset, gpr_size);
521
522 ppc_supply_reg (regcache, gdbarch_pc_regnum (gdbarch),
523 gregs, offsets->pc_offset, gpr_size);
524 ppc_supply_reg (regcache, tdep->ppc_ps_regnum,
525 gregs, offsets->ps_offset, gpr_size);
526 ppc_supply_reg (regcache, tdep->ppc_lr_regnum,
527 gregs, offsets->lr_offset, gpr_size);
528 ppc_supply_reg (regcache, tdep->ppc_ctr_regnum,
529 gregs, offsets->ctr_offset, gpr_size);
530 ppc_supply_reg (regcache, tdep->ppc_cr_regnum,
531 gregs, offsets->cr_offset, offsets->xr_size);
532 ppc_supply_reg (regcache, tdep->ppc_xer_regnum,
533 gregs, offsets->xer_offset, offsets->xr_size);
534 ppc_supply_reg (regcache, tdep->ppc_mq_regnum,
535 gregs, offsets->mq_offset, offsets->xr_size);
536 return;
d195bc9f
MK		 537 }
538
f2db237a
AM		 539 offset = ppc_greg_offset (gdbarch, tdep, offsets, regnum, &regsize);
540 ppc_supply_reg (regcache, regnum, gregs, offset, regsize);
d195bc9f
MK		 541}
542
543/* Supply register REGNUM in the floating-point register set REGSET
544 from the buffer specified by FPREGS and LEN to register cache
545 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
546
547void
548ppc_supply_fpregset (const struct regset *regset, struct regcache *regcache,
549 int regnum, const void *fpregs, size_t len)
550{
551 struct gdbarch *gdbarch = get_regcache_arch (regcache);
f2db237a
AM		 552 struct gdbarch_tdep *tdep;
553 const struct ppc_reg_offsets *offsets;
d195bc9f 554 size_t offset;
d195bc9f 555
f2db237a
AM		 556 if (!ppc_floating_point_unit_p (gdbarch))
557 return;
383f0f5b 558
f2db237a
AM		 559 tdep = gdbarch_tdep (gdbarch);
560 offsets = regset->descr;
561 if (regnum == -1)
d195bc9f 562 {
f2db237a
AM		 563 int i;
564
565 for (i = tdep->ppc_fp0_regnum, offset = offsets->f0_offset;
566 i < tdep->ppc_fp0_regnum + ppc_num_fprs;
567 i++, offset += 8)
568 ppc_supply_reg (regcache, i, fpregs, offset, 8);
569
570 ppc_supply_reg (regcache, tdep->ppc_fpscr_regnum,
571 fpregs, offsets->fpscr_offset, offsets->fpscr_size);
572 return;
d195bc9f
MK		 573 }
574
f2db237a
AM		 575 offset = ppc_fpreg_offset (tdep, offsets, regnum);
576 ppc_supply_reg (regcache, regnum, fpregs, offset,
577 regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8);
d195bc9f
MK		 578}
579
604c2f83
LM		 580/* Supply register REGNUM in the VSX register set REGSET
581 from the buffer specified by VSXREGS and LEN to register cache
582 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
583
584void
585ppc_supply_vsxregset (const struct regset *regset, struct regcache *regcache,
586 int regnum, const void *vsxregs, size_t len)
587{
588 struct gdbarch *gdbarch = get_regcache_arch (regcache);
589 struct gdbarch_tdep *tdep;
590
591 if (!ppc_vsx_support_p (gdbarch))
592 return;
593
594 tdep = gdbarch_tdep (gdbarch);
595
596 if (regnum == -1)
597 {
598 int i;
599
600 for (i = tdep->ppc_vsr0_upper_regnum;
601 i < tdep->ppc_vsr0_upper_regnum + 32;
602 i++)
603 ppc_supply_reg (regcache, i, vsxregs, 0, 8);
604
605 return;
606 }
607 else
608 ppc_supply_reg (regcache, regnum, vsxregs, 0, 8);
609}
610
06caf7d2
CES		 611/* Supply register REGNUM in the Altivec register set REGSET
612 from the buffer specified by VRREGS and LEN to register cache
613 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
614
615void
616ppc_supply_vrregset (const struct regset *regset, struct regcache *regcache,
617 int regnum, const void *vrregs, size_t len)
618{
619 struct gdbarch *gdbarch = get_regcache_arch (regcache);
620 struct gdbarch_tdep *tdep;
621 const struct ppc_reg_offsets *offsets;
622 size_t offset;
623
624 if (!ppc_altivec_support_p (gdbarch))
625 return;
626
627 tdep = gdbarch_tdep (gdbarch);
628 offsets = regset->descr;
629 if (regnum == -1)
630 {
631 int i;
632
633 for (i = tdep->ppc_vr0_regnum, offset = offsets->vr0_offset;
634 i < tdep->ppc_vr0_regnum + ppc_num_vrs;
635 i++, offset += 16)
636 ppc_supply_reg (regcache, i, vrregs, offset, 16);
637
638 ppc_supply_reg (regcache, (tdep->ppc_vrsave_regnum - 1),
639 vrregs, offsets->vscr_offset, 4);
640
641 ppc_supply_reg (regcache, tdep->ppc_vrsave_regnum,
642 vrregs, offsets->vrsave_offset, 4);
643 return;
644 }
645
646 offset = ppc_vrreg_offset (tdep, offsets, regnum);
647 if (regnum != tdep->ppc_vrsave_regnum
648 && regnum != tdep->ppc_vrsave_regnum - 1)
649 ppc_supply_reg (regcache, regnum, vrregs, offset, 16);
650 else
651 ppc_supply_reg (regcache, regnum,
652 vrregs, offset, 4);
653}
654
d195bc9f 655/* Collect register REGNUM in the general-purpose register set
f2db237a 656 REGSET from register cache REGCACHE into the buffer specified by
d195bc9f
MK		 657 GREGS and LEN. If REGNUM is -1, do this for all registers in
658 REGSET. */
659
660void
661ppc_collect_gregset (const struct regset *regset,
662 const struct regcache *regcache,
663 int regnum, void *gregs, size_t len)
664{
665 struct gdbarch *gdbarch = get_regcache_arch (regcache);
666 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
667 const struct ppc_reg_offsets *offsets = regset->descr;
668 size_t offset;
f2db237a 669 int regsize;
d195bc9f 670
f2db237a 671 if (regnum == -1)
d195bc9f 672 {
f2db237a
AM		 673 int i;
674 int gpr_size = offsets->gpr_size;
675
676 for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset;
677 i < tdep->ppc_gp0_regnum + ppc_num_gprs;
678 i++, offset += gpr_size)
679 ppc_collect_reg (regcache, i, gregs, offset, gpr_size);
680
681 ppc_collect_reg (regcache, gdbarch_pc_regnum (gdbarch),
682 gregs, offsets->pc_offset, gpr_size);
683 ppc_collect_reg (regcache, tdep->ppc_ps_regnum,
684 gregs, offsets->ps_offset, gpr_size);
685 ppc_collect_reg (regcache, tdep->ppc_lr_regnum,
686 gregs, offsets->lr_offset, gpr_size);
687 ppc_collect_reg (regcache, tdep->ppc_ctr_regnum,
688 gregs, offsets->ctr_offset, gpr_size);
689 ppc_collect_reg (regcache, tdep->ppc_cr_regnum,
690 gregs, offsets->cr_offset, offsets->xr_size);
691 ppc_collect_reg (regcache, tdep->ppc_xer_regnum,
692 gregs, offsets->xer_offset, offsets->xr_size);
693 ppc_collect_reg (regcache, tdep->ppc_mq_regnum,
694 gregs, offsets->mq_offset, offsets->xr_size);
695 return;
d195bc9f
MK		 696 }
697
f2db237a
AM		 698 offset = ppc_greg_offset (gdbarch, tdep, offsets, regnum, &regsize);
699 ppc_collect_reg (regcache, regnum, gregs, offset, regsize);
d195bc9f
MK		 700}
701
702/* Collect register REGNUM in the floating-point register set
f2db237a 703 REGSET from register cache REGCACHE into the buffer specified by
d195bc9f
MK		 704 FPREGS and LEN. If REGNUM is -1, do this for all registers in
705 REGSET. */
706
707void
708ppc_collect_fpregset (const struct regset *regset,
709 const struct regcache *regcache,
710 int regnum, void *fpregs, size_t len)
711{
712 struct gdbarch *gdbarch = get_regcache_arch (regcache);
f2db237a
AM		 713 struct gdbarch_tdep *tdep;
714 const struct ppc_reg_offsets *offsets;
d195bc9f 715 size_t offset;
d195bc9f 716
f2db237a
AM		 717 if (!ppc_floating_point_unit_p (gdbarch))
718 return;
383f0f5b 719
f2db237a
AM		 720 tdep = gdbarch_tdep (gdbarch);
721 offsets = regset->descr;
722 if (regnum == -1)
d195bc9f 723 {
f2db237a
AM		 724 int i;
725
726 for (i = tdep->ppc_fp0_regnum, offset = offsets->f0_offset;
727 i < tdep->ppc_fp0_regnum + ppc_num_fprs;
728 i++, offset += 8)
729 ppc_collect_reg (regcache, i, fpregs, offset, 8);
730
731 ppc_collect_reg (regcache, tdep->ppc_fpscr_regnum,
732 fpregs, offsets->fpscr_offset, offsets->fpscr_size);
733 return;
d195bc9f
MK		 734 }
735
f2db237a
AM		 736 offset = ppc_fpreg_offset (tdep, offsets, regnum);
737 ppc_collect_reg (regcache, regnum, fpregs, offset,
738 regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8);
d195bc9f 739}
06caf7d2 740
604c2f83
LM		 741/* Collect register REGNUM in the VSX register set
742 REGSET from register cache REGCACHE into the buffer specified by
743 VSXREGS and LEN. If REGNUM is -1, do this for all registers in
744 REGSET. */
745
746void
747ppc_collect_vsxregset (const struct regset *regset,
748 const struct regcache *regcache,
749 int regnum, void *vsxregs, size_t len)
750{
751 struct gdbarch *gdbarch = get_regcache_arch (regcache);
752 struct gdbarch_tdep *tdep;
753
754 if (!ppc_vsx_support_p (gdbarch))
755 return;
756
757 tdep = gdbarch_tdep (gdbarch);
758
759 if (regnum == -1)
760 {
761 int i;
762
763 for (i = tdep->ppc_vsr0_upper_regnum;
764 i < tdep->ppc_vsr0_upper_regnum + 32;
765 i++)
766 ppc_collect_reg (regcache, i, vsxregs, 0, 8);
767
768 return;
769 }
770 else
771 ppc_collect_reg (regcache, regnum, vsxregs, 0, 8);
772}
773
774
06caf7d2
CES		 775/* Collect register REGNUM in the Altivec register set
776 REGSET from register cache REGCACHE into the buffer specified by
777 VRREGS and LEN. If REGNUM is -1, do this for all registers in
778 REGSET. */
779
780void
781ppc_collect_vrregset (const struct regset *regset,
782 const struct regcache *regcache,
783 int regnum, void *vrregs, size_t len)
784{
785 struct gdbarch *gdbarch = get_regcache_arch (regcache);
786 struct gdbarch_tdep *tdep;
787 const struct ppc_reg_offsets *offsets;
788 size_t offset;
789
790 if (!ppc_altivec_support_p (gdbarch))
791 return;
792
793 tdep = gdbarch_tdep (gdbarch);
794 offsets = regset->descr;
795 if (regnum == -1)
796 {
797 int i;
798
799 for (i = tdep->ppc_vr0_regnum, offset = offsets->vr0_offset;
800 i < tdep->ppc_vr0_regnum + ppc_num_vrs;
801 i++, offset += 16)
802 ppc_collect_reg (regcache, i, vrregs, offset, 16);
803
804 ppc_collect_reg (regcache, (tdep->ppc_vrsave_regnum - 1),
805 vrregs, offsets->vscr_offset, 4);
806
807 ppc_collect_reg (regcache, tdep->ppc_vrsave_regnum,
808 vrregs, offsets->vrsave_offset, 4);
809 return;
810 }
811
812 offset = ppc_vrreg_offset (tdep, offsets, regnum);
813 if (regnum != tdep->ppc_vrsave_regnum
814 && regnum != tdep->ppc_vrsave_regnum - 1)
815 ppc_collect_reg (regcache, regnum, vrregs, offset, 16);
816 else
817 ppc_collect_reg (regcache, regnum,
818 vrregs, offset, 4);
819}
d195bc9f 820\f
0a613259 821
0d1243d9
PG		 822static int
823insn_changes_sp_or_jumps (unsigned long insn)
824{
825 int opcode = (insn >> 26) & 0x03f;
826 int sd = (insn >> 21) & 0x01f;
827 int a = (insn >> 16) & 0x01f;
828 int subcode = (insn >> 1) & 0x3ff;
829
830 /* Changes the stack pointer. */
831
832 /* NOTE: There are many ways to change the value of a given register.
833 The ways below are those used when the register is R1, the SP,
834 in a funtion's epilogue. */
835
836 if (opcode == 31 && subcode == 444 && a == 1)
837 return 1; /* mr R1,Rn */
838 if (opcode == 14 && sd == 1)
839 return 1; /* addi R1,Rn,simm */
840 if (opcode == 58 && sd == 1)
841 return 1; /* ld R1,ds(Rn) */
842
843 /* Transfers control. */
844
845 if (opcode == 18)
846 return 1; /* b */
847 if (opcode == 16)
848 return 1; /* bc */
849 if (opcode == 19 && subcode == 16)
850 return 1; /* bclr */
851 if (opcode == 19 && subcode == 528)
852 return 1; /* bcctr */
853
854 return 0;
855}
856
857/* Return true if we are in the function's epilogue, i.e. after the
858 instruction that destroyed the function's stack frame.
859
860 1) scan forward from the point of execution:
861 a) If you find an instruction that modifies the stack pointer
862 or transfers control (except a return), execution is not in
863 an epilogue, return.
864 b) Stop scanning if you find a return instruction or reach the
865 end of the function or reach the hard limit for the size of
866 an epilogue.
867 2) scan backward from the point of execution:
868 a) If you find an instruction that modifies the stack pointer,
869 execution *is* in an epilogue, return.
870 b) Stop scanning if you reach an instruction that transfers
871 control or the beginning of the function or reach the hard
872 limit for the size of an epilogue. */
873
874static int
875rs6000_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
876{
46a9b8ed 877 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
e17a4113 878 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
0d1243d9
PG		 879 bfd_byte insn_buf[PPC_INSN_SIZE];
880 CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end;
881 unsigned long insn;
882 struct frame_info *curfrm;
883
884 /* Find the search limits based on function boundaries and hard limit. */
885
886 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
887 return 0;
888
889 epilogue_start = pc - PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE;
890 if (epilogue_start < func_start) epilogue_start = func_start;
891
892 epilogue_end = pc + PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE;
893 if (epilogue_end > func_end) epilogue_end = func_end;
894
895 curfrm = get_current_frame ();
896
897 /* Scan forward until next 'blr'. */
898
899 for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += PPC_INSN_SIZE)
900 {
901 if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE))
902 return 0;
e17a4113 903 insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE, byte_order);
0d1243d9
PG		 904 if (insn == 0x4e800020)
905 break;
46a9b8ed
DJ		 906 /* Assume a bctr is a tail call unless it points strictly within
907 this function. */
908 if (insn == 0x4e800420)
909 {
910 CORE_ADDR ctr = get_frame_register_unsigned (curfrm,
911 tdep->ppc_ctr_regnum);
912 if (ctr > func_start && ctr < func_end)
913 return 0;
914 else
915 break;
916 }
0d1243d9
PG		 917 if (insn_changes_sp_or_jumps (insn))
918 return 0;
919 }
920
921 /* Scan backward until adjustment to stack pointer (R1). */
922
923 for (scan_pc = pc - PPC_INSN_SIZE;
924 scan_pc >= epilogue_start;
925 scan_pc -= PPC_INSN_SIZE)
926 {
927 if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE))
928 return 0;
e17a4113 929 insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE, byte_order);
0d1243d9
PG		 930 if (insn_changes_sp_or_jumps (insn))
931 return 1;
932 }
933
934 return 0;
935}
936
143985b7 937/* Get the ith function argument for the current function. */
b9362cc7 938static CORE_ADDR
143985b7
AF		 939rs6000_fetch_pointer_argument (struct frame_info *frame, int argi,
940 struct type *type)
941{
50fd1280 942 return get_frame_register_unsigned (frame, 3 + argi);
143985b7
AF		 943}
944
c906108c
SS		 945/* Sequence of bytes for breakpoint instruction. */
946
f4f9705a 947const static unsigned char *
67d57894
MD		 948rs6000_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *bp_addr,
949 int *bp_size)
c906108c 950{
aaab4dba
AC		 951 static unsigned char big_breakpoint[] = { 0x7d, 0x82, 0x10, 0x08 };
952 static unsigned char little_breakpoint[] = { 0x08, 0x10, 0x82, 0x7d };
c906108c 953 *bp_size = 4;
67d57894 954 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
c906108c
SS		 955 return big_breakpoint;
956 else
957 return little_breakpoint;
958}
959
f74c6cad
LM		 960/* Instruction masks for displaced stepping. */
961#define BRANCH_MASK 0xfc000000
962#define BP_MASK 0xFC0007FE
963#define B_INSN 0x48000000
964#define BC_INSN 0x40000000
965#define BXL_INSN 0x4c000000
966#define BP_INSN 0x7C000008
967
968/* Fix up the state of registers and memory after having single-stepped
969 a displaced instruction. */
63807e1d 970static void
f74c6cad 971ppc_displaced_step_fixup (struct gdbarch *gdbarch,
63807e1d
PA		 972 struct displaced_step_closure *closure,
973 CORE_ADDR from, CORE_ADDR to,
974 struct regcache *regs)
f74c6cad 975{
e17a4113 976 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
f74c6cad
LM		 977 /* Since we use simple_displaced_step_copy_insn, our closure is a
978 copy of the instruction. */
979 ULONGEST insn = extract_unsigned_integer ((gdb_byte *) closure,
e17a4113 980 PPC_INSN_SIZE, byte_order);
f74c6cad
LM		 981 ULONGEST opcode = 0;
982 /* Offset for non PC-relative instructions. */
983 LONGEST offset = PPC_INSN_SIZE;
984
985 opcode = insn & BRANCH_MASK;
986
987 if (debug_displaced)
988 fprintf_unfiltered (gdb_stdlog,
5af949e3
UW		 989 "displaced: (ppc) fixup (%s, %s)\n",
990 paddress (gdbarch, from), paddress (gdbarch, to));
f74c6cad
LM		 991
992
993 /* Handle PC-relative branch instructions. */
994 if (opcode == B_INSN || opcode == BC_INSN || opcode == BXL_INSN)
995 {
a4fafde3 996 ULONGEST current_pc;
f74c6cad
LM		 997
998 /* Read the current PC value after the instruction has been executed
999 in a displaced location. Calculate the offset to be applied to the
1000 original PC value before the displaced stepping. */
1001 regcache_cooked_read_unsigned (regs, gdbarch_pc_regnum (gdbarch),
1002 &current_pc);
1003 offset = current_pc - to;
1004
1005 if (opcode != BXL_INSN)
1006 {
1007 /* Check for AA bit indicating whether this is an absolute
1008 addressing or PC-relative (1: absolute, 0: relative). */
1009 if (!(insn & 0x2))
1010 {
1011 /* PC-relative addressing is being used in the branch. */
1012 if (debug_displaced)
1013 fprintf_unfiltered
1014 (gdb_stdlog,
5af949e3
UW		 1015 "displaced: (ppc) branch instruction: %s\n"
1016 "displaced: (ppc) adjusted PC from %s to %s\n",
1017 paddress (gdbarch, insn), paddress (gdbarch, current_pc),
1018 paddress (gdbarch, from + offset));
f74c6cad
LM		 1019
1020 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch),
1021 from + offset);
1022 }
1023 }
1024 else
1025 {
1026 /* If we're here, it means we have a branch to LR or CTR. If the
1027 branch was taken, the offset is probably greater than 4 (the next
1028 instruction), so it's safe to assume that an offset of 4 means we
1029 did not take the branch. */
1030 if (offset == PPC_INSN_SIZE)
1031 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch),
1032 from + PPC_INSN_SIZE);
1033 }
1034
1035 /* Check for LK bit indicating whether we should set the link
1036 register to point to the next instruction
1037 (1: Set, 0: Don't set). */
1038 if (insn & 0x1)
1039 {
1040 /* Link register needs to be set to the next instruction's PC. */
1041 regcache_cooked_write_unsigned (regs,
1042 gdbarch_tdep (gdbarch)->ppc_lr_regnum,
1043 from + PPC_INSN_SIZE);
1044 if (debug_displaced)
1045 fprintf_unfiltered (gdb_stdlog,
5af949e3
UW		 1046 "displaced: (ppc) adjusted LR to %s\n",
1047 paddress (gdbarch, from + PPC_INSN_SIZE));
f74c6cad
LM		 1048
1049 }
1050 }
1051 /* Check for breakpoints in the inferior. If we've found one, place the PC
1052 right at the breakpoint instruction. */
1053 else if ((insn & BP_MASK) == BP_INSN)
1054 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch), from);
1055 else
1056 /* Handle any other instructions that do not fit in the categories above. */
1057 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch),
1058 from + offset);
1059}
c906108c 1060
ce5eab59
UW		 1061/* Instruction masks used during single-stepping of atomic sequences. */
1062#define LWARX_MASK 0xfc0007fe
1063#define LWARX_INSTRUCTION 0x7c000028
1064#define LDARX_INSTRUCTION 0x7c0000A8
1065#define STWCX_MASK 0xfc0007ff
1066#define STWCX_INSTRUCTION 0x7c00012d
1067#define STDCX_INSTRUCTION 0x7c0001ad
ce5eab59
UW		 1068
1069/* Checks for an atomic sequence of instructions beginning with a LWARX/LDARX
1070 instruction and ending with a STWCX/STDCX instruction. If such a sequence
1071 is found, attempt to step through it. A breakpoint is placed at the end of
1072 the sequence. */
1073
4a7622d1
UW		 1074int
1075ppc_deal_with_atomic_sequence (struct frame_info *frame)
ce5eab59 1076{
a6d9a66e 1077 struct gdbarch *gdbarch = get_frame_arch (frame);
e17a4113 1078 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
0b1b3e42 1079 CORE_ADDR pc = get_frame_pc (frame);
ce5eab59
UW		 1080 CORE_ADDR breaks[2] = {-1, -1};
1081 CORE_ADDR loc = pc;
24d45690 1082 CORE_ADDR closing_insn; /* Instruction that closes the atomic sequence. */
e17a4113 1083 int insn = read_memory_integer (loc, PPC_INSN_SIZE, byte_order);
ce5eab59
UW		 1084 int insn_count;
1085 int index;
1086 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
1087 const int atomic_sequence_length = 16; /* Instruction sequence length. */
24d45690 1088 int opcode; /* Branch instruction's OPcode. */
ce5eab59
UW		 1089 int bc_insn_count = 0; /* Conditional branch instruction count. */
1090
1091 /* Assume all atomic sequences start with a lwarx/ldarx instruction. */
1092 if ((insn & LWARX_MASK) != LWARX_INSTRUCTION
1093 && (insn & LWARX_MASK) != LDARX_INSTRUCTION)
1094 return 0;
1095
1096 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
1097 instructions. */
1098 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
1099 {
1100 loc += PPC_INSN_SIZE;
e17a4113 1101 insn = read_memory_integer (loc, PPC_INSN_SIZE, byte_order);
ce5eab59
UW		 1102
1103 /* Assume that there is at most one conditional branch in the atomic
1104 sequence. If a conditional branch is found, put a breakpoint in
1105 its destination address. */
f74c6cad 1106 if ((insn & BRANCH_MASK) == BC_INSN)
ce5eab59 1107 {
4a7622d1
UW		 1108 int immediate = ((insn & ~3) << 16) >> 16;
1109 int absolute = ((insn >> 1) & 1);
1110
ce5eab59
UW		 1111 if (bc_insn_count >= 1)
1112 return 0; /* More than one conditional branch found, fallback
1113 to the standard single-step code. */
4a7622d1
UW		 1114
1115 if (absolute)
1116 breaks[1] = immediate;
1117 else
1118 breaks[1] = pc + immediate;
1119
1120 bc_insn_count++;
1121 last_breakpoint++;
ce5eab59
UW		 1122 }
1123
1124 if ((insn & STWCX_MASK) == STWCX_INSTRUCTION
1125 || (insn & STWCX_MASK) == STDCX_INSTRUCTION)
1126 break;
1127 }
1128
1129 /* Assume that the atomic sequence ends with a stwcx/stdcx instruction. */
1130 if ((insn & STWCX_MASK) != STWCX_INSTRUCTION
1131 && (insn & STWCX_MASK) != STDCX_INSTRUCTION)
1132 return 0;
1133
24d45690 1134 closing_insn = loc;
ce5eab59 1135 loc += PPC_INSN_SIZE;
e17a4113 1136 insn = read_memory_integer (loc, PPC_INSN_SIZE, byte_order);
ce5eab59
UW		 1137
1138 /* Insert a breakpoint right after the end of the atomic sequence. */
1139 breaks[0] = loc;
1140
24d45690
UW		 1141 /* Check for duplicated breakpoints. Check also for a breakpoint
1142 placed (branch instruction's destination) at the stwcx/stdcx
1143 instruction, this resets the reservation and take us back to the
1144 lwarx/ldarx instruction at the beginning of the atomic sequence. */
1145 if (last_breakpoint && ((breaks[1] == breaks[0])
1146 || (breaks[1] == closing_insn)))
ce5eab59
UW		 1147 last_breakpoint = 0;
1148
1149 /* Effectively inserts the breakpoints. */
1150 for (index = 0; index <= last_breakpoint; index++)
a6d9a66e 1151 insert_single_step_breakpoint (gdbarch, breaks[index]);
ce5eab59
UW		 1152
1153 return 1;
1154}
1155
c906108c 1156
c906108c
SS		 1157#define SIGNED_SHORT(x) \
1158 ((sizeof (short) == 2) \
1159 ? ((int)(short)(x)) \
1160 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
1161
1162#define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
1163
55d05f3b
KB		 1164/* Limit the number of skipped non-prologue instructions, as the examining
1165 of the prologue is expensive. */
1166static int max_skip_non_prologue_insns = 10;
1167
773df3e5
JB		 1168/* Return nonzero if the given instruction OP can be part of the prologue
1169 of a function and saves a parameter on the stack. FRAMEP should be
1170 set if one of the previous instructions in the function has set the
1171 Frame Pointer. */
1172
1173static int
1174store_param_on_stack_p (unsigned long op, int framep, int *r0_contains_arg)
1175{
1176 /* Move parameters from argument registers to temporary register. */
1177 if ((op & 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
1178 {
1179 /* Rx must be scratch register r0. */
1180 const int rx_regno = (op >> 16) & 31;
1181 /* Ry: Only r3 - r10 are used for parameter passing. */
1182 const int ry_regno = GET_SRC_REG (op);
1183
1184 if (rx_regno == 0 && ry_regno >= 3 && ry_regno <= 10)
1185 {
1186 *r0_contains_arg = 1;
1187 return 1;
1188 }
1189 else
1190 return 0;
1191 }
1192
1193 /* Save a General Purpose Register on stack. */
1194
1195 if ((op & 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
1196 (op & 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
1197 {
1198 /* Rx: Only r3 - r10 are used for parameter passing. */
1199 const int rx_regno = GET_SRC_REG (op);
1200
1201 return (rx_regno >= 3 && rx_regno <= 10);
1202 }
1203
1204 /* Save a General Purpose Register on stack via the Frame Pointer. */
1205
1206 if (framep &&
1207 ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
1208 (op & 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
1209 (op & 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
1210 {
1211 /* Rx: Usually, only r3 - r10 are used for parameter passing.
1212 However, the compiler sometimes uses r0 to hold an argument. */
1213 const int rx_regno = GET_SRC_REG (op);
1214
1215 return ((rx_regno >= 3 && rx_regno <= 10)
1216 || (rx_regno == 0 && *r0_contains_arg));
1217 }
1218
1219 if ((op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
1220 {
1221 /* Only f2 - f8 are used for parameter passing. */
1222 const int src_regno = GET_SRC_REG (op);
1223
1224 return (src_regno >= 2 && src_regno <= 8);
1225 }
1226
1227 if (framep && ((op & 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
1228 {
1229 /* Only f2 - f8 are used for parameter passing. */
1230 const int src_regno = GET_SRC_REG (op);
1231
1232 return (src_regno >= 2 && src_regno <= 8);
1233 }
1234
1235 /* Not an insn that saves a parameter on stack. */
1236 return 0;
1237}
55d05f3b 1238
3c77c82a
DJ		 1239/* Assuming that INSN is a "bl" instruction located at PC, return
1240 nonzero if the destination of the branch is a "blrl" instruction.
1241
1242 This sequence is sometimes found in certain function prologues.
1243 It allows the function to load the LR register with a value that
1244 they can use to access PIC data using PC-relative offsets. */
1245
1246static int
e17a4113 1247bl_to_blrl_insn_p (CORE_ADDR pc, int insn, enum bfd_endian byte_order)
3c77c82a 1248{
0b1b3e42
UW		 1249 CORE_ADDR dest;
1250 int immediate;
1251 int absolute;
3c77c82a
DJ		 1252 int dest_insn;
1253
0b1b3e42
UW		 1254 absolute = (int) ((insn >> 1) & 1);
1255 immediate = ((insn & ~3) << 6) >> 6;
1256 if (absolute)
1257 dest = immediate;
1258 else
1259 dest = pc + immediate;
1260
e17a4113 1261 dest_insn = read_memory_integer (dest, 4, byte_order);
3c77c82a
DJ		 1262 if ((dest_insn & 0xfc00ffff) == 0x4c000021) /* blrl */
1263 return 1;
1264
1265 return 0;
1266}
1267
8ab3d180
KB		 1268/* Masks for decoding a branch-and-link (bl) instruction.
1269
1270 BL_MASK and BL_INSTRUCTION are used in combination with each other.
1271 The former is anded with the opcode in question; if the result of
1272 this masking operation is equal to BL_INSTRUCTION, then the opcode in
1273 question is a ``bl'' instruction.
1274
1275 BL_DISPLACMENT_MASK is anded with the opcode in order to extract
1276 the branch displacement. */
1277
1278#define BL_MASK 0xfc000001
1279#define BL_INSTRUCTION 0x48000001
1280#define BL_DISPLACEMENT_MASK 0x03fffffc
1281
de9f48f0 1282static unsigned long
e17a4113 1283rs6000_fetch_instruction (struct gdbarch *gdbarch, const CORE_ADDR pc)
de9f48f0 1284{
e17a4113 1285 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
de9f48f0
JG		 1286 gdb_byte buf[4];
1287 unsigned long op;
1288
1289 /* Fetch the instruction and convert it to an integer. */
1290 if (target_read_memory (pc, buf, 4))
1291 return 0;
e17a4113 1292 op = extract_unsigned_integer (buf, 4, byte_order);
de9f48f0
JG		 1293
1294 return op;
1295}
1296
1297/* GCC generates several well-known sequences of instructions at the begining
1298 of each function prologue when compiling with -fstack-check. If one of
1299 such sequences starts at START_PC, then return the address of the
1300 instruction immediately past this sequence. Otherwise, return START_PC. */
1301
1302static CORE_ADDR
e17a4113 1303rs6000_skip_stack_check (struct gdbarch *gdbarch, const CORE_ADDR start_pc)
de9f48f0
JG		 1304{
1305 CORE_ADDR pc = start_pc;
e17a4113 1306 unsigned long op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1307
1308 /* First possible sequence: A small number of probes.
1309 stw 0, -<some immediate>(1)
1310 [repeat this instruction any (small) number of times]
1311 */
1312
1313 if ((op & 0xffff0000) == 0x90010000)
1314 {
1315 while ((op & 0xffff0000) == 0x90010000)
1316 {
1317 pc = pc + 4;
e17a4113 1318 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1319 }
1320 return pc;
1321 }
1322
1323 /* Second sequence: A probing loop.
1324 addi 12,1,-<some immediate>
1325 lis 0,-<some immediate>
1326 [possibly ori 0,0,<some immediate>]
1327 add 0,12,0
1328 cmpw 0,12,0
1329 beq 0,<disp>
1330 addi 12,12,-<some immediate>
1331 stw 0,0(12)
1332 b <disp>
1333 [possibly one last probe: stw 0,<some immediate>(12)]
1334 */
1335
1336 while (1)
1337 {
1338 /* addi 12,1,-<some immediate> */
1339 if ((op & 0xffff0000) != 0x39810000)
1340 break;
1341
1342 /* lis 0,-<some immediate> */
1343 pc = pc + 4;
e17a4113 1344 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1345 if ((op & 0xffff0000) != 0x3c000000)
1346 break;
1347
1348 pc = pc + 4;
e17a4113 1349 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1350 /* [possibly ori 0,0,<some immediate>] */
1351 if ((op & 0xffff0000) == 0x60000000)
1352 {
1353 pc = pc + 4;
e17a4113 1354 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1355 }
1356 /* add 0,12,0 */
1357 if (op != 0x7c0c0214)
1358 break;
1359
1360 /* cmpw 0,12,0 */
1361 pc = pc + 4;
e17a4113 1362 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1363 if (op != 0x7c0c0000)
1364 break;
1365
1366 /* beq 0,<disp> */
1367 pc = pc + 4;
e17a4113 1368 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1369 if ((op & 0xff9f0001) != 0x41820000)
1370 break;
1371
1372 /* addi 12,12,-<some immediate> */
1373 pc = pc + 4;
e17a4113 1374 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1375 if ((op & 0xffff0000) != 0x398c0000)
1376 break;
1377
1378 /* stw 0,0(12) */
1379 pc = pc + 4;
e17a4113 1380 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1381 if (op != 0x900c0000)
1382 break;
1383
1384 /* b <disp> */
1385 pc = pc + 4;
e17a4113 1386 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1387 if ((op & 0xfc000001) != 0x48000000)
1388 break;
1389
1390 /* [possibly one last probe: stw 0,<some immediate>(12)] */
1391 pc = pc + 4;
e17a4113 1392 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1393 if ((op & 0xffff0000) == 0x900c0000)
1394 {
1395 pc = pc + 4;
e17a4113 1396 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1397 }
1398
1399 /* We found a valid stack-check sequence, return the new PC. */
1400 return pc;
1401 }
1402
1403 /* Third sequence: No probe; instead, a comparizon between the stack size
1404 limit (saved in a run-time global variable) and the current stack
1405 pointer:
1406
1407 addi 0,1,-<some immediate>
1408 lis 12,__gnat_stack_limit@ha
1409 lwz 12,__gnat_stack_limit@l(12)
1410 twllt 0,12
1411
1412 or, with a small variant in the case of a bigger stack frame:
1413 addis 0,1,<some immediate>
1414 addic 0,0,-<some immediate>
1415 lis 12,__gnat_stack_limit@ha
1416 lwz 12,__gnat_stack_limit@l(12)
1417 twllt 0,12
1418 */
1419 while (1)
1420 {
1421 /* addi 0,1,-<some immediate> */
1422 if ((op & 0xffff0000) != 0x38010000)
1423 {
1424 /* small stack frame variant not recognized; try the
1425 big stack frame variant: */
1426
1427 /* addis 0,1,<some immediate> */
1428 if ((op & 0xffff0000) != 0x3c010000)
1429 break;
1430
1431 /* addic 0,0,-<some immediate> */
1432 pc = pc + 4;
e17a4113 1433 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1434 if ((op & 0xffff0000) != 0x30000000)
1435 break;
1436 }
1437
1438 /* lis 12,<some immediate> */
1439 pc = pc + 4;
e17a4113 1440 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1441 if ((op & 0xffff0000) != 0x3d800000)
1442 break;
1443
1444 /* lwz 12,<some immediate>(12) */
1445 pc = pc + 4;
e17a4113 1446 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1447 if ((op & 0xffff0000) != 0x818c0000)
1448 break;
1449
1450 /* twllt 0,12 */
1451 pc = pc + 4;
e17a4113 1452 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1453 if ((op & 0xfffffffe) != 0x7c406008)
1454 break;
1455
1456 /* We found a valid stack-check sequence, return the new PC. */
1457 return pc;
1458 }
1459
1460 /* No stack check code in our prologue, return the start_pc. */
1461 return start_pc;
1462}
1463
6a16c029
TJB		 1464/* return pc value after skipping a function prologue and also return
1465 information about a function frame.
1466
1467 in struct rs6000_framedata fdata:
1468 - frameless is TRUE, if function does not have a frame.
1469 - nosavedpc is TRUE, if function does not save %pc value in its frame.
1470 - offset is the initial size of this stack frame --- the amount by
1471 which we decrement the sp to allocate the frame.
1472 - saved_gpr is the number of the first saved gpr.
1473 - saved_fpr is the number of the first saved fpr.
1474 - saved_vr is the number of the first saved vr.
1475 - saved_ev is the number of the first saved ev.
1476 - alloca_reg is the number of the register used for alloca() handling.
1477 Otherwise -1.
1478 - gpr_offset is the offset of the first saved gpr from the previous frame.
1479 - fpr_offset is the offset of the first saved fpr from the previous frame.
1480 - vr_offset is the offset of the first saved vr from the previous frame.
1481 - ev_offset is the offset of the first saved ev from the previous frame.
1482 - lr_offset is the offset of the saved lr
1483 - cr_offset is the offset of the saved cr
1484 - vrsave_offset is the offset of the saved vrsave register
1485 */
1486
7a78ae4e 1487static CORE_ADDR
be8626e0
MD		 1488skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, CORE_ADDR lim_pc,
1489 struct rs6000_framedata *fdata)
c906108c
SS		 1490{
1491 CORE_ADDR orig_pc = pc;
55d05f3b 1492 CORE_ADDR last_prologue_pc = pc;
6be8bc0c 1493 CORE_ADDR li_found_pc = 0;
50fd1280 1494 gdb_byte buf[4];
c906108c
SS		 1495 unsigned long op;
1496 long offset = 0;
6be8bc0c 1497 long vr_saved_offset = 0;
482ca3f5
KB		 1498 int lr_reg = -1;
1499 int cr_reg = -1;
6be8bc0c 1500 int vr_reg = -1;
96ff0de4
EZ		 1501 int ev_reg = -1;
1502 long ev_offset = 0;
6be8bc0c 1503 int vrsave_reg = -1;
c906108c
SS		 1504 int reg;
1505 int framep = 0;
1506 int minimal_toc_loaded = 0;
ddb20c56 1507 int prev_insn_was_prologue_insn = 1;
55d05f3b 1508 int num_skip_non_prologue_insns = 0;
773df3e5 1509 int r0_contains_arg = 0;
be8626e0
MD		 1510 const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (gdbarch);
1511 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
e17a4113 1512 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
c906108c 1513
ddb20c56 1514 memset (fdata, 0, sizeof (struct rs6000_framedata));
c906108c
SS		 1515 fdata->saved_gpr = -1;
1516 fdata->saved_fpr = -1;
6be8bc0c 1517 fdata->saved_vr = -1;
96ff0de4 1518 fdata->saved_ev = -1;
c906108c
SS		 1519 fdata->alloca_reg = -1;
1520 fdata->frameless = 1;
1521 fdata->nosavedpc = 1;
46a9b8ed 1522 fdata->lr_register = -1;
c906108c 1523
e17a4113 1524 pc = rs6000_skip_stack_check (gdbarch, pc);
de9f48f0
JG		 1525 if (pc >= lim_pc)
1526 pc = lim_pc;
1527
55d05f3b 1528 for (;; pc += 4)
c906108c 1529 {
ddb20c56
KB		 1530 /* Sometimes it isn't clear if an instruction is a prologue
1531 instruction or not. When we encounter one of these ambiguous
1532 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
1533 Otherwise, we'll assume that it really is a prologue instruction. */
1534 if (prev_insn_was_prologue_insn)
1535 last_prologue_pc = pc;
55d05f3b
KB		 1536
1537 /* Stop scanning if we've hit the limit. */
4e463ff5 1538 if (pc >= lim_pc)
55d05f3b
KB		 1539 break;
1540
ddb20c56
KB		 1541 prev_insn_was_prologue_insn = 1;
1542
55d05f3b 1543 /* Fetch the instruction and convert it to an integer. */
ddb20c56
KB		 1544 if (target_read_memory (pc, buf, 4))
1545 break;
e17a4113 1546 op = extract_unsigned_integer (buf, 4, byte_order);
c906108c 1547
c5aa993b
JM		 1548 if ((op & 0xfc1fffff) == 0x7c0802a6)
1549 { /* mflr Rx */
43b1ab88
AC		 1550 /* Since shared library / PIC code, which needs to get its
1551 address at runtime, can appear to save more than one link
1552 register vis:
1553
1554 *INDENT-OFF*
1555 stwu r1,-304(r1)
1556 mflr r3
1557 bl 0xff570d0 (blrl)
1558 stw r30,296(r1)
1559 mflr r30
1560 stw r31,300(r1)
1561 stw r3,308(r1);
1562 ...
1563 *INDENT-ON*
1564
1565 remember just the first one, but skip over additional
1566 ones. */
721d14ba 1567 if (lr_reg == -1)
46a9b8ed 1568 lr_reg = (op & 0x03e00000) >> 21;
773df3e5
JB		 1569 if (lr_reg == 0)
1570 r0_contains_arg = 0;
c5aa993b 1571 continue;
c5aa993b
JM		 1572 }
1573 else if ((op & 0xfc1fffff) == 0x7c000026)
1574 { /* mfcr Rx */
98f08d3d 1575 cr_reg = (op & 0x03e00000);
773df3e5
JB		 1576 if (cr_reg == 0)
1577 r0_contains_arg = 0;
c5aa993b 1578 continue;
c906108c 1579
c906108c 1580 }
c5aa993b
JM		 1581 else if ((op & 0xfc1f0000) == 0xd8010000)
1582 { /* stfd Rx,NUM(r1) */
1583 reg = GET_SRC_REG (op);
1584 if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg)
1585 {
1586 fdata->saved_fpr = reg;
1587 fdata->fpr_offset = SIGNED_SHORT (op) + offset;
1588 }
1589 continue;
c906108c 1590
c5aa993b
JM		 1591 }
1592 else if (((op & 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
7a78ae4e
ND		 1593 (((op & 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
1594 (op & 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
1595 (op & 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
c5aa993b
JM		 1596 {
1597
1598 reg = GET_SRC_REG (op);
46a9b8ed
DJ		 1599 if ((op & 0xfc1f0000) == 0xbc010000)
1600 fdata->gpr_mask |= ~((1U << reg) - 1);
1601 else
1602 fdata->gpr_mask |= 1U << reg;
c5aa993b
JM		 1603 if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg)
1604 {
1605 fdata->saved_gpr = reg;
7a78ae4e 1606 if ((op & 0xfc1f0003) == 0xf8010000)
98f08d3d 1607 op &= ~3UL;
c5aa993b
JM		 1608 fdata->gpr_offset = SIGNED_SHORT (op) + offset;
1609 }
1610 continue;
c906108c 1611
ddb20c56
KB		 1612 }
1613 else if ((op & 0xffff0000) == 0x60000000)
1614 {
96ff0de4 1615 /* nop */
ddb20c56
KB		 1616 /* Allow nops in the prologue, but do not consider them to
1617 be part of the prologue unless followed by other prologue
1618 instructions. */
1619 prev_insn_was_prologue_insn = 0;
1620 continue;
1621
c906108c 1622 }
c5aa993b
JM		 1623 else if ((op & 0xffff0000) == 0x3c000000)
1624 { /* addis 0,0,NUM, used
1625 for >= 32k frames */
1626 fdata->offset = (op & 0x0000ffff) << 16;
1627 fdata->frameless = 0;
773df3e5 1628 r0_contains_arg = 0;
c5aa993b
JM		 1629 continue;
1630
1631 }
1632 else if ((op & 0xffff0000) == 0x60000000)
1633 { /* ori 0,0,NUM, 2nd ha
1634 lf of >= 32k frames */
1635 fdata->offset |= (op & 0x0000ffff);
1636 fdata->frameless = 0;
773df3e5 1637 r0_contains_arg = 0;
c5aa993b
JM		 1638 continue;
1639
1640 }
be723e22 1641 else if (lr_reg >= 0 &&
98f08d3d
KB		 1642 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1643 (((op & 0xffff0000) == (lr_reg | 0xf8010000)) ||
1644 /* stw Rx, NUM(r1) */
1645 ((op & 0xffff0000) == (lr_reg | 0x90010000)) ||
1646 /* stwu Rx, NUM(r1) */
1647 ((op & 0xffff0000) == (lr_reg | 0x94010000))))
1648 { /* where Rx == lr */
1649 fdata->lr_offset = offset;
c5aa993b 1650 fdata->nosavedpc = 0;
be723e22
MS		 1651 /* Invalidate lr_reg, but don't set it to -1.
1652 That would mean that it had never been set. */
1653 lr_reg = -2;
98f08d3d
KB		 1654 if ((op & 0xfc000003) == 0xf8000000 || /* std */
1655 (op & 0xfc000000) == 0x90000000) /* stw */
1656 {
1657 /* Does not update r1, so add displacement to lr_offset. */
1658 fdata->lr_offset += SIGNED_SHORT (op);
1659 }
c5aa993b
JM		 1660 continue;
1661
1662 }
be723e22 1663 else if (cr_reg >= 0 &&
98f08d3d
KB		 1664 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1665 (((op & 0xffff0000) == (cr_reg | 0xf8010000)) ||
1666 /* stw Rx, NUM(r1) */
1667 ((op & 0xffff0000) == (cr_reg | 0x90010000)) ||
1668 /* stwu Rx, NUM(r1) */
1669 ((op & 0xffff0000) == (cr_reg | 0x94010000))))
1670 { /* where Rx == cr */
1671 fdata->cr_offset = offset;
be723e22
MS		 1672 /* Invalidate cr_reg, but don't set it to -1.
1673 That would mean that it had never been set. */
1674 cr_reg = -2;
98f08d3d
KB		 1675 if ((op & 0xfc000003) == 0xf8000000 ||
1676 (op & 0xfc000000) == 0x90000000)
1677 {
1678 /* Does not update r1, so add displacement to cr_offset. */
1679 fdata->cr_offset += SIGNED_SHORT (op);
1680 }
c5aa993b
JM		 1681 continue;
1682
1683 }
721d14ba
DJ		 1684 else if ((op & 0xfe80ffff) == 0x42800005 && lr_reg != -1)
1685 {
1686 /* bcl 20,xx,.+4 is used to get the current PC, with or without
1687 prediction bits. If the LR has already been saved, we can
1688 skip it. */
1689 continue;
1690 }
c5aa993b
JM		 1691 else if (op == 0x48000005)
1692 { /* bl .+4 used in
1693 -mrelocatable */
46a9b8ed 1694 fdata->used_bl = 1;
c5aa993b
JM		 1695 continue;
1696
1697 }
1698 else if (op == 0x48000004)
1699 { /* b .+4 (xlc) */
1700 break;
1701
c5aa993b 1702 }
6be8bc0c
EZ		 1703 else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1704 in V.4 -mminimal-toc */
c5aa993b
JM		 1705 (op & 0xffff0000) == 0x3bde0000)
1706 { /* addi 30,30,foo@l */
1707 continue;
c906108c 1708
c5aa993b
JM		 1709 }
1710 else if ((op & 0xfc000001) == 0x48000001)
1711 { /* bl foo,
1712 to save fprs??? */
c906108c 1713
c5aa993b 1714 fdata->frameless = 0;
3c77c82a
DJ		 1715
1716 /* If the return address has already been saved, we can skip
1717 calls to blrl (for PIC). */
e17a4113 1718 if (lr_reg != -1 && bl_to_blrl_insn_p (pc, op, byte_order))
46a9b8ed
DJ		 1719 {
1720 fdata->used_bl = 1;
1721 continue;
1722 }
3c77c82a 1723
6be8bc0c 1724 /* Don't skip over the subroutine call if it is not within
ebd98106
FF		 1725 the first three instructions of the prologue and either
1726 we have no line table information or the line info tells
1727 us that the subroutine call is not part of the line
1728 associated with the prologue. */
c5aa993b 1729 if ((pc - orig_pc) > 8)
ebd98106
FF		 1730 {
1731 struct symtab_and_line prologue_sal = find_pc_line (orig_pc, 0);
1732 struct symtab_and_line this_sal = find_pc_line (pc, 0);
1733
1734 if ((prologue_sal.line == 0) || (prologue_sal.line != this_sal.line))
1735 break;
1736 }
c5aa993b 1737
e17a4113 1738 op = read_memory_integer (pc + 4, 4, byte_order);
c5aa993b 1739
6be8bc0c
EZ		 1740 /* At this point, make sure this is not a trampoline
1741 function (a function that simply calls another functions,
1742 and nothing else). If the next is not a nop, this branch
1743 was part of the function prologue. */
c5aa993b
JM		 1744
1745 if (op == 0x4def7b82 || op == 0) /* crorc 15, 15, 15 */
1746 break; /* don't skip over
1747 this branch */
c5aa993b 1748
46a9b8ed
DJ		 1749 fdata->used_bl = 1;
1750 continue;
c5aa993b 1751 }
98f08d3d
KB		 1752 /* update stack pointer */
1753 else if ((op & 0xfc1f0000) == 0x94010000)
1754 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
c5aa993b
JM		 1755 fdata->frameless = 0;
1756 fdata->offset = SIGNED_SHORT (op);
1757 offset = fdata->offset;
1758 continue;
c5aa993b 1759 }
98f08d3d
KB		 1760 else if ((op & 0xfc1f016a) == 0x7c01016e)
1761 { /* stwux rX,r1,rY */
1762 /* no way to figure out what r1 is going to be */
1763 fdata->frameless = 0;
1764 offset = fdata->offset;
1765 continue;
1766 }
1767 else if ((op & 0xfc1f0003) == 0xf8010001)
1768 { /* stdu rX,NUM(r1) */
1769 fdata->frameless = 0;
1770 fdata->offset = SIGNED_SHORT (op & ~3UL);
1771 offset = fdata->offset;
1772 continue;
1773 }
1774 else if ((op & 0xfc1f016a) == 0x7c01016a)
1775 { /* stdux rX,r1,rY */
1776 /* no way to figure out what r1 is going to be */
c5aa993b
JM		 1777 fdata->frameless = 0;
1778 offset = fdata->offset;
1779 continue;
c5aa993b 1780 }
7313566f
FF		 1781 else if ((op & 0xffff0000) == 0x38210000)
1782 { /* addi r1,r1,SIMM */
1783 fdata->frameless = 0;
1784 fdata->offset += SIGNED_SHORT (op);
1785 offset = fdata->offset;
1786 continue;
1787 }
4e463ff5
DJ		 1788 /* Load up minimal toc pointer. Do not treat an epilogue restore
1789 of r31 as a minimal TOC load. */
98f08d3d
KB		 1790 else if (((op >> 22) == 0x20f || /* l r31,... or l r30,... */
1791 (op >> 22) == 0x3af) /* ld r31,... or ld r30,... */
4e463ff5 1792 && !framep
c5aa993b 1793 && !minimal_toc_loaded)
98f08d3d 1794 {
c5aa993b
JM		 1795 minimal_toc_loaded = 1;
1796 continue;
1797
f6077098
KB		 1798 /* move parameters from argument registers to local variable
1799 registers */
1800 }
1801 else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1802 (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1803 (((op >> 21) & 31) <= 10) &&
96ff0de4 1804 ((long) ((op >> 16) & 31) >= fdata->saved_gpr)) /* Rx: local var reg */
f6077098
KB		 1805 {
1806 continue;
1807
c5aa993b
JM		 1808 /* store parameters in stack */
1809 }
e802b915 1810 /* Move parameters from argument registers to temporary register. */
773df3e5 1811 else if (store_param_on_stack_p (op, framep, &r0_contains_arg))
e802b915 1812 {
c5aa993b
JM		 1813 continue;
1814
1815 /* Set up frame pointer */
1816 }
1817 else if (op == 0x603f0000 /* oril r31, r1, 0x0 */
1818 || op == 0x7c3f0b78)
1819 { /* mr r31, r1 */
1820 fdata->frameless = 0;
1821 framep = 1;
6f99cb26 1822 fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31);
c5aa993b
JM		 1823 continue;
1824
1825 /* Another way to set up the frame pointer. */
1826 }
1827 else if ((op & 0xfc1fffff) == 0x38010000)
1828 { /* addi rX, r1, 0x0 */
1829 fdata->frameless = 0;
1830 framep = 1;
6f99cb26
AC		 1831 fdata->alloca_reg = (tdep->ppc_gp0_regnum
1832 + ((op & ~0x38010000) >> 21));
c5aa993b 1833 continue;
c5aa993b 1834 }
6be8bc0c
EZ		 1835 /* AltiVec related instructions. */
1836 /* Store the vrsave register (spr 256) in another register for
1837 later manipulation, or load a register into the vrsave
1838 register. 2 instructions are used: mfvrsave and
1839 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1840 and mtspr SPR256, Rn. */
1841 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1842 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1843 else if ((op & 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1844 {
1845 vrsave_reg = GET_SRC_REG (op);
1846 continue;
1847 }
1848 else if ((op & 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1849 {
1850 continue;
1851 }
1852 /* Store the register where vrsave was saved to onto the stack:
1853 rS is the register where vrsave was stored in a previous
1854 instruction. */
1855 /* 100100 sssss 00001 dddddddd dddddddd */
1856 else if ((op & 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1857 {
1858 if (vrsave_reg == GET_SRC_REG (op))
1859 {
1860 fdata->vrsave_offset = SIGNED_SHORT (op) + offset;
1861 vrsave_reg = -1;
1862 }
1863 continue;
1864 }
1865 /* Compute the new value of vrsave, by modifying the register
1866 where vrsave was saved to. */
1867 else if (((op & 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1868 || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1869 {
1870 continue;
1871 }
1872 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1873 in a pair of insns to save the vector registers on the
1874 stack. */
1875 /* 001110 00000 00000 iiii iiii iiii iiii */
96ff0de4
EZ		 1876 /* 001110 01110 00000 iiii iiii iiii iiii */
1877 else if ((op & 0xffff0000) == 0x38000000 /* li r0, SIMM */
1878 || (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */
6be8bc0c 1879 {
773df3e5
JB		 1880 if ((op & 0xffff0000) == 0x38000000)
1881 r0_contains_arg = 0;
6be8bc0c
EZ		 1882 li_found_pc = pc;
1883 vr_saved_offset = SIGNED_SHORT (op);
773df3e5
JB		 1884
1885 /* This insn by itself is not part of the prologue, unless
1886 if part of the pair of insns mentioned above. So do not
1887 record this insn as part of the prologue yet. */
1888 prev_insn_was_prologue_insn = 0;
6be8bc0c
EZ		 1889 }
1890 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1891 /* 011111 sssss 11111 00000 00111001110 */
1892 else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
1893 {
1894 if (pc == (li_found_pc + 4))
1895 {
1896 vr_reg = GET_SRC_REG (op);
1897 /* If this is the first vector reg to be saved, or if
1898 it has a lower number than others previously seen,
1899 reupdate the frame info. */
1900 if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg)
1901 {
1902 fdata->saved_vr = vr_reg;
1903 fdata->vr_offset = vr_saved_offset + offset;
1904 }
1905 vr_saved_offset = -1;
1906 vr_reg = -1;
1907 li_found_pc = 0;
1908 }
1909 }
1910 /* End AltiVec related instructions. */
96ff0de4
EZ		 1911
1912 /* Start BookE related instructions. */
1913 /* Store gen register S at (r31+uimm).
1914 Any register less than r13 is volatile, so we don't care. */
1915 /* 000100 sssss 11111 iiiii 01100100001 */
1916 else if (arch_info->mach == bfd_mach_ppc_e500
1917 && (op & 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
1918 {
1919 if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
1920 {
1921 unsigned int imm;
1922 ev_reg = GET_SRC_REG (op);
1923 imm = (op >> 11) & 0x1f;
1924 ev_offset = imm * 8;
1925 /* If this is the first vector reg to be saved, or if
1926 it has a lower number than others previously seen,
1927 reupdate the frame info. */
1928 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1929 {
1930 fdata->saved_ev = ev_reg;
1931 fdata->ev_offset = ev_offset + offset;
1932 }
1933 }
1934 continue;
1935 }
1936 /* Store gen register rS at (r1+rB). */
1937 /* 000100 sssss 00001 bbbbb 01100100000 */
1938 else if (arch_info->mach == bfd_mach_ppc_e500
1939 && (op & 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
1940 {
1941 if (pc == (li_found_pc + 4))
1942 {
1943 ev_reg = GET_SRC_REG (op);
1944 /* If this is the first vector reg to be saved, or if
1945 it has a lower number than others previously seen,
1946 reupdate the frame info. */
1947 /* We know the contents of rB from the previous instruction. */
1948 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1949 {
1950 fdata->saved_ev = ev_reg;
1951 fdata->ev_offset = vr_saved_offset + offset;
1952 }
1953 vr_saved_offset = -1;
1954 ev_reg = -1;
1955 li_found_pc = 0;
1956 }
1957 continue;
1958 }
1959 /* Store gen register r31 at (rA+uimm). */
1960 /* 000100 11111 aaaaa iiiii 01100100001 */
1961 else if (arch_info->mach == bfd_mach_ppc_e500
1962 && (op & 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
1963 {
1964 /* Wwe know that the source register is 31 already, but
1965 it can't hurt to compute it. */
1966 ev_reg = GET_SRC_REG (op);
1967 ev_offset = ((op >> 11) & 0x1f) * 8;
1968 /* If this is the first vector reg to be saved, or if
1969 it has a lower number than others previously seen,
1970 reupdate the frame info. */
1971 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1972 {
1973 fdata->saved_ev = ev_reg;
1974 fdata->ev_offset = ev_offset + offset;
1975 }
1976
1977 continue;
1978 }
1979 /* Store gen register S at (r31+r0).
1980 Store param on stack when offset from SP bigger than 4 bytes. */
1981 /* 000100 sssss 11111 00000 01100100000 */
1982 else if (arch_info->mach == bfd_mach_ppc_e500
1983 && (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
1984 {
1985 if (pc == (li_found_pc + 4))
1986 {
1987 if ((op & 0x03e00000) >= 0x01a00000)
1988 {
1989 ev_reg = GET_SRC_REG (op);
1990 /* If this is the first vector reg to be saved, or if
1991 it has a lower number than others previously seen,
1992 reupdate the frame info. */
1993 /* We know the contents of r0 from the previous
1994 instruction. */
1995 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1996 {
1997 fdata->saved_ev = ev_reg;
1998 fdata->ev_offset = vr_saved_offset + offset;
1999 }
2000 ev_reg = -1;
2001 }
2002 vr_saved_offset = -1;
2003 li_found_pc = 0;
2004 continue;
2005 }
2006 }
2007 /* End BookE related instructions. */
2008
c5aa993b
JM		 2009 else
2010 {
46a9b8ed
DJ		 2011 unsigned int all_mask = ~((1U << fdata->saved_gpr) - 1);
2012
55d05f3b
KB		 2013 /* Not a recognized prologue instruction.
2014 Handle optimizer code motions into the prologue by continuing
2015 the search if we have no valid frame yet or if the return
46a9b8ed
DJ		 2016 address is not yet saved in the frame. Also skip instructions
2017 if some of the GPRs expected to be saved are not yet saved. */
2018 if (fdata->frameless == 0 && fdata->nosavedpc == 0
2019 && (fdata->gpr_mask & all_mask) == all_mask)
55d05f3b
KB		 2020 break;
2021
2022 if (op == 0x4e800020 /* blr */
2023 || op == 0x4e800420) /* bctr */
2024 /* Do not scan past epilogue in frameless functions or
2025 trampolines. */
2026 break;
2027 if ((op & 0xf4000000) == 0x40000000) /* bxx */
64366f1c 2028 /* Never skip branches. */
55d05f3b
KB		 2029 break;
2030
2031 if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns)
2032 /* Do not scan too many insns, scanning insns is expensive with
2033 remote targets. */
2034 break;
2035
2036 /* Continue scanning. */
2037 prev_insn_was_prologue_insn = 0;
2038 continue;
c5aa993b 2039 }
c906108c
SS		 2040 }
2041
2042#if 0
2043/* I have problems with skipping over __main() that I need to address
2044 * sometime. Previously, I used to use misc_function_vector which
2045 * didn't work as well as I wanted to be. -MGO */
2046
2047 /* If the first thing after skipping a prolog is a branch to a function,
2048 this might be a call to an initializer in main(), introduced by gcc2.
64366f1c 2049 We'd like to skip over it as well. Fortunately, xlc does some extra
c906108c 2050 work before calling a function right after a prologue, thus we can
64366f1c 2051 single out such gcc2 behaviour. */
c906108c 2052
c906108c 2053
c5aa993b
JM		 2054 if ((op & 0xfc000001) == 0x48000001)
2055 { /* bl foo, an initializer function? */
e17a4113 2056 op = read_memory_integer (pc + 4, 4, byte_order);
c5aa993b
JM		 2057
2058 if (op == 0x4def7b82)
2059 { /* cror 0xf, 0xf, 0xf (nop) */
c906108c 2060
64366f1c
EZ		 2061 /* Check and see if we are in main. If so, skip over this
2062 initializer function as well. */
c906108c 2063
c5aa993b 2064 tmp = find_pc_misc_function (pc);
6314a349
AC		 2065 if (tmp >= 0
2066 && strcmp (misc_function_vector[tmp].name, main_name ()) == 0)
c5aa993b
JM		 2067 return pc + 8;
2068 }
c906108c 2069 }
c906108c 2070#endif /* 0 */
c5aa993b 2071
46a9b8ed
DJ		 2072 if (pc == lim_pc && lr_reg >= 0)
2073 fdata->lr_register = lr_reg;
2074
c5aa993b 2075 fdata->offset = -fdata->offset;
ddb20c56 2076 return last_prologue_pc;
c906108c
SS		 2077}
2078
7a78ae4e 2079static CORE_ADDR
4a7622d1 2080rs6000_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
c906108c 2081{
4a7622d1
UW		 2082 struct rs6000_framedata frame;
2083 CORE_ADDR limit_pc, func_addr;
c906108c 2084
4a7622d1
UW		 2085 /* See if we can determine the end of the prologue via the symbol table.
2086 If so, then return either PC, or the PC after the prologue, whichever
2087 is greater. */
2088 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
c5aa993b 2089 {
d80b854b
UW		 2090 CORE_ADDR post_prologue_pc
2091 = skip_prologue_using_sal (gdbarch, func_addr);
4a7622d1
UW		 2092 if (post_prologue_pc != 0)
2093 return max (pc, post_prologue_pc);
c906108c 2094 }
c906108c 2095
4a7622d1
UW		 2096 /* Can't determine prologue from the symbol table, need to examine
2097 instructions. */
c906108c 2098
4a7622d1
UW		 2099 /* Find an upper limit on the function prologue using the debug
2100 information. If the debug information could not be used to provide
2101 that bound, then use an arbitrary large number as the upper bound. */
d80b854b 2102 limit_pc = skip_prologue_using_sal (gdbarch, pc);
4a7622d1
UW		 2103 if (limit_pc == 0)
2104 limit_pc = pc + 100; /* Magic. */
794a477a 2105
4a7622d1
UW		 2106 pc = skip_prologue (gdbarch, pc, limit_pc, &frame);
2107 return pc;
c906108c 2108}
c906108c 2109
8ab3d180
KB		 2110/* When compiling for EABI, some versions of GCC emit a call to __eabi
2111 in the prologue of main().
2112
2113 The function below examines the code pointed at by PC and checks to
2114 see if it corresponds to a call to __eabi. If so, it returns the
2115 address of the instruction following that call. Otherwise, it simply
2116 returns PC. */
2117
63807e1d 2118static CORE_ADDR
8ab3d180
KB		 2119rs6000_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
2120{
e17a4113 2121 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
8ab3d180
KB		 2122 gdb_byte buf[4];
2123 unsigned long op;
2124
2125 if (target_read_memory (pc, buf, 4))
2126 return pc;
e17a4113 2127 op = extract_unsigned_integer (buf, 4, byte_order);
8ab3d180
KB		 2128
2129 if ((op & BL_MASK) == BL_INSTRUCTION)
2130 {
2131 CORE_ADDR displ = op & BL_DISPLACEMENT_MASK;
2132 CORE_ADDR call_dest = pc + 4 + displ;
2133 struct minimal_symbol *s = lookup_minimal_symbol_by_pc (call_dest);
2134
2135 /* We check for ___eabi (three leading underscores) in addition
2136 to __eabi in case the GCC option "-fleading-underscore" was
2137 used to compile the program. */
2138 if (s != NULL
2139 && SYMBOL_LINKAGE_NAME (s) != NULL
2140 && (strcmp (SYMBOL_LINKAGE_NAME (s), "__eabi") == 0
2141 || strcmp (SYMBOL_LINKAGE_NAME (s), "___eabi") == 0))
2142 pc += 4;
2143 }
2144 return pc;
2145}
383f0f5b 2146
4a7622d1
UW		 2147/* All the ABI's require 16 byte alignment. */
2148static CORE_ADDR
2149rs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
2150{
2151 return (addr & -16);
c906108c
SS		 2152}
2153
977adac5
ND		 2154/* Return whether handle_inferior_event() should proceed through code
2155 starting at PC in function NAME when stepping.
2156
2157 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
2158 handle memory references that are too distant to fit in instructions
2159 generated by the compiler. For example, if 'foo' in the following
2160 instruction:
2161
2162 lwz r9,foo(r2)
2163
2164 is greater than 32767, the linker might replace the lwz with a branch to
2165 somewhere in @FIX1 that does the load in 2 instructions and then branches
2166 back to where execution should continue.
2167
2168 GDB should silently step over @FIX code, just like AIX dbx does.
2ec664f5
MS		 2169 Unfortunately, the linker uses the "b" instruction for the
2170 branches, meaning that the link register doesn't get set.
2171 Therefore, GDB's usual step_over_function () mechanism won't work.
977adac5 2172
e76f05fa
UW		 2173 Instead, use the gdbarch_skip_trampoline_code and
2174 gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past
2ec664f5 2175 @FIX code. */
977adac5 2176
63807e1d 2177static int
e17a4113
UW		 2178rs6000_in_solib_return_trampoline (struct gdbarch *gdbarch,
2179 CORE_ADDR pc, char *name)
977adac5
ND		 2180{
2181 return name && !strncmp (name, "@FIX", 4);
2182}
2183
2184/* Skip code that the user doesn't want to see when stepping:
2185
2186 1. Indirect function calls use a piece of trampoline code to do context
2187 switching, i.e. to set the new TOC table. Skip such code if we are on
2188 its first instruction (as when we have single-stepped to here).
2189
2190 2. Skip shared library trampoline code (which is different from
c906108c 2191 indirect function call trampolines).
977adac5
ND		 2192
2193 3. Skip bigtoc fixup code.
2194
c906108c 2195 Result is desired PC to step until, or NULL if we are not in
977adac5 2196 code that should be skipped. */
c906108c 2197
63807e1d 2198static CORE_ADDR
52f729a7 2199rs6000_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc)
c906108c 2200{
e17a4113
UW		 2201 struct gdbarch *gdbarch = get_frame_arch (frame);
2202 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2203 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
52f0bd74 2204 unsigned int ii, op;
977adac5 2205 int rel;
c906108c 2206 CORE_ADDR solib_target_pc;
977adac5 2207 struct minimal_symbol *msymbol;
c906108c 2208
c5aa993b
JM		 2209 static unsigned trampoline_code[] =
2210 {
2211 0x800b0000, /* l r0,0x0(r11) */
2212 0x90410014, /* st r2,0x14(r1) */
2213 0x7c0903a6, /* mtctr r0 */
2214 0x804b0004, /* l r2,0x4(r11) */
2215 0x816b0008, /* l r11,0x8(r11) */
2216 0x4e800420, /* bctr */
2217 0x4e800020, /* br */
2218 0
c906108c
SS		 2219 };
2220
977adac5
ND		 2221 /* Check for bigtoc fixup code. */
2222 msymbol = lookup_minimal_symbol_by_pc (pc);
2ec664f5 2223 if (msymbol
e17a4113
UW		 2224 && rs6000_in_solib_return_trampoline (gdbarch, pc,
2225 SYMBOL_LINKAGE_NAME (msymbol)))
977adac5
ND		 2226 {
2227 /* Double-check that the third instruction from PC is relative "b". */
e17a4113 2228 op = read_memory_integer (pc + 8, 4, byte_order);
977adac5
ND		 2229 if ((op & 0xfc000003) == 0x48000000)
2230 {
2231 /* Extract bits 6-29 as a signed 24-bit relative word address and
2232 add it to the containing PC. */
2233 rel = ((int)(op << 6) >> 6);
2234 return pc + 8 + rel;
2235 }
2236 }
2237
c906108c 2238 /* If pc is in a shared library trampoline, return its target. */
52f729a7 2239 solib_target_pc = find_solib_trampoline_target (frame, pc);
c906108c
SS		 2240 if (solib_target_pc)
2241 return solib_target_pc;
2242
c5aa993b
JM		 2243 for (ii = 0; trampoline_code[ii]; ++ii)
2244 {
e17a4113 2245 op = read_memory_integer (pc + (ii * 4), 4, byte_order);
c5aa993b
JM		 2246 if (op != trampoline_code[ii])
2247 return 0;
2248 }
52f729a7 2249 ii = get_frame_register_unsigned (frame, 11); /* r11 holds destination addr */
e17a4113 2250 pc = read_memory_unsigned_integer (ii, tdep->wordsize, byte_order);
c906108c
SS		 2251 return pc;
2252}
2253
794ac428
UW		 2254/* ISA-specific vector types. */
2255
2256static struct type *
2257rs6000_builtin_type_vec64 (struct gdbarch *gdbarch)
2258{
2259 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2260
2261 if (!tdep->ppc_builtin_type_vec64)
2262 {
df4df182
UW		 2263 const struct builtin_type *bt = builtin_type (gdbarch);
2264
794ac428
UW		 2265 /* The type we're building is this: */
2266#if 0
2267 union __gdb_builtin_type_vec64
2268 {
2269 int64_t uint64;
2270 float v2_float[2];
2271 int32_t v2_int32[2];
2272 int16_t v4_int16[4];
2273 int8_t v8_int8[8];
2274 };
2275#endif
2276
2277 struct type *t;
2278
e9bb382b
UW		 2279 t = arch_composite_type (gdbarch,
2280 "__ppc_builtin_type_vec64", TYPE_CODE_UNION);
df4df182 2281 append_composite_type_field (t, "uint64", bt->builtin_int64);
794ac428 2282 append_composite_type_field (t, "v2_float",
df4df182 2283 init_vector_type (bt->builtin_float, 2));
794ac428 2284 append_composite_type_field (t, "v2_int32",
df4df182 2285 init_vector_type (bt->builtin_int32, 2));
794ac428 2286 append_composite_type_field (t, "v4_int16",
df4df182 2287 init_vector_type (bt->builtin_int16, 4));
794ac428 2288 append_composite_type_field (t, "v8_int8",
df4df182 2289 init_vector_type (bt->builtin_int8, 8));
794ac428 2290
876cecd0 2291 TYPE_VECTOR (t) = 1;
794ac428
UW		 2292 TYPE_NAME (t) = "ppc_builtin_type_vec64";
2293 tdep->ppc_builtin_type_vec64 = t;
2294 }
2295
2296 return tdep->ppc_builtin_type_vec64;
2297}
2298
604c2f83
LM		 2299/* Vector 128 type. */
2300
2301static struct type *
2302rs6000_builtin_type_vec128 (struct gdbarch *gdbarch)
2303{
2304 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2305
2306 if (!tdep->ppc_builtin_type_vec128)
2307 {
df4df182
UW		 2308 const struct builtin_type *bt = builtin_type (gdbarch);
2309
604c2f83
LM		 2310 /* The type we're building is this
2311
2312 type = union __ppc_builtin_type_vec128 {
2313 uint128_t uint128;
2314 float v4_float[4];
2315 int32_t v4_int32[4];
2316 int16_t v8_int16[8];
2317 int8_t v16_int8[16];
2318 }
2319 */
2320
2321 struct type *t;
2322
e9bb382b
UW		 2323 t = arch_composite_type (gdbarch,
2324 "__ppc_builtin_type_vec128", TYPE_CODE_UNION);
df4df182 2325 append_composite_type_field (t, "uint128", bt->builtin_uint128);
604c2f83 2326 append_composite_type_field (t, "v4_float",
df4df182 2327 init_vector_type (bt->builtin_float, 4));
604c2f83 2328 append_composite_type_field (t, "v4_int32",
df4df182 2329 init_vector_type (bt->builtin_int32, 4));
604c2f83 2330 append_composite_type_field (t, "v8_int16",
df4df182 2331 init_vector_type (bt->builtin_int16, 8));
604c2f83 2332 append_composite_type_field (t, "v16_int8",
df4df182 2333 init_vector_type (bt->builtin_int8, 16));
604c2f83 2334
803e1097 2335 TYPE_VECTOR (t) = 1;
604c2f83
LM		 2336 TYPE_NAME (t) = "ppc_builtin_type_vec128";
2337 tdep->ppc_builtin_type_vec128 = t;
2338 }
2339
2340 return tdep->ppc_builtin_type_vec128;
2341}
2342
7cc46491
DJ		 2343/* Return the name of register number REGNO, or the empty string if it
2344 is an anonymous register. */
7a78ae4e 2345
fa88f677 2346static const char *
d93859e2 2347rs6000_register_name (struct gdbarch *gdbarch, int regno)
7a78ae4e 2348{
d93859e2 2349 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
7a78ae4e 2350
7cc46491
DJ		 2351 /* The upper half "registers" have names in the XML description,
2352 but we present only the low GPRs and the full 64-bit registers
2353 to the user. */
2354 if (tdep->ppc_ev0_upper_regnum >= 0
2355 && tdep->ppc_ev0_upper_regnum <= regno
2356 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
2357 return "";
2358
604c2f83
LM		 2359 /* Hide the upper halves of the vs0~vs31 registers. */
2360 if (tdep->ppc_vsr0_regnum >= 0
2361 && tdep->ppc_vsr0_upper_regnum <= regno
2362 && regno < tdep->ppc_vsr0_upper_regnum + ppc_num_gprs)
2363 return "";
2364
7cc46491 2365 /* Check if the SPE pseudo registers are available. */
5a9e69ba 2366 if (IS_SPE_PSEUDOREG (tdep, regno))
7cc46491
DJ		 2367 {
2368 static const char *const spe_regnames[] = {
2369 "ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7",
2370 "ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15",
2371 "ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23",
2372 "ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31",
2373 };
2374 return spe_regnames[regno - tdep->ppc_ev0_regnum];
2375 }
2376
f949c649
TJB		 2377 /* Check if the decimal128 pseudo-registers are available. */
2378 if (IS_DFP_PSEUDOREG (tdep, regno))
2379 {
2380 static const char *const dfp128_regnames[] = {
2381 "dl0", "dl1", "dl2", "dl3",
2382 "dl4", "dl5", "dl6", "dl7",
2383 "dl8", "dl9", "dl10", "dl11",
2384 "dl12", "dl13", "dl14", "dl15"
2385 };
2386 return dfp128_regnames[regno - tdep->ppc_dl0_regnum];
2387 }
2388
604c2f83
LM		 2389 /* Check if this is a VSX pseudo-register. */
2390 if (IS_VSX_PSEUDOREG (tdep, regno))
2391 {
2392 static const char *const vsx_regnames[] = {
2393 "vs0", "vs1", "vs2", "vs3", "vs4", "vs5", "vs6", "vs7",
2394 "vs8", "vs9", "vs10", "vs11", "vs12", "vs13", "vs14",
2395 "vs15", "vs16", "vs17", "vs18", "vs19", "vs20", "vs21",
2396 "vs22", "vs23", "vs24", "vs25", "vs26", "vs27", "vs28",
2397 "vs29", "vs30", "vs31", "vs32", "vs33", "vs34", "vs35",
2398 "vs36", "vs37", "vs38", "vs39", "vs40", "vs41", "vs42",
2399 "vs43", "vs44", "vs45", "vs46", "vs47", "vs48", "vs49",
2400 "vs50", "vs51", "vs52", "vs53", "vs54", "vs55", "vs56",
2401 "vs57", "vs58", "vs59", "vs60", "vs61", "vs62", "vs63"
2402 };
2403 return vsx_regnames[regno - tdep->ppc_vsr0_regnum];
2404 }
2405
2406 /* Check if the this is a Extended FP pseudo-register. */
2407 if (IS_EFP_PSEUDOREG (tdep, regno))
2408 {
2409 static const char *const efpr_regnames[] = {
2410 "f32", "f33", "f34", "f35", "f36", "f37", "f38",
2411 "f39", "f40", "f41", "f42", "f43", "f44", "f45",
2412 "f46", "f47", "f48", "f49", "f50", "f51",
2413 "f52", "f53", "f54", "f55", "f56", "f57",
2414 "f58", "f59", "f60", "f61", "f62", "f63"
2415 };
2416 return efpr_regnames[regno - tdep->ppc_efpr0_regnum];
2417 }
2418
d93859e2 2419 return tdesc_register_name (gdbarch, regno);
7a78ae4e
ND		 2420}
2421
7cc46491
DJ		 2422/* Return the GDB type object for the "standard" data type of data in
2423 register N. */
7a78ae4e
ND		 2424
2425static struct type *
7cc46491 2426rs6000_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
7a78ae4e 2427{
691d145a 2428 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
7a78ae4e 2429
7cc46491 2430 /* These are the only pseudo-registers we support. */
f949c649 2431 gdb_assert (IS_SPE_PSEUDOREG (tdep, regnum)
604c2f83
LM		 2432 || IS_DFP_PSEUDOREG (tdep, regnum)
2433 || IS_VSX_PSEUDOREG (tdep, regnum)
2434 || IS_EFP_PSEUDOREG (tdep, regnum));
7cc46491 2435
f949c649
TJB		 2436 /* These are the e500 pseudo-registers. */
2437 if (IS_SPE_PSEUDOREG (tdep, regnum))
2438 return rs6000_builtin_type_vec64 (gdbarch);
604c2f83
LM		 2439 else if (IS_DFP_PSEUDOREG (tdep, regnum))
2440 /* PPC decimal128 pseudo-registers. */
f949c649 2441 return builtin_type (gdbarch)->builtin_declong;
604c2f83
LM		 2442 else if (IS_VSX_PSEUDOREG (tdep, regnum))
2443 /* POWER7 VSX pseudo-registers. */
2444 return rs6000_builtin_type_vec128 (gdbarch);
2445 else
2446 /* POWER7 Extended FP pseudo-registers. */
2447 return builtin_type (gdbarch)->builtin_double;
7a78ae4e
ND		 2448}
2449
c44ca51c
AC		 2450/* Is REGNUM a member of REGGROUP? */
2451static int
7cc46491
DJ		 2452rs6000_pseudo_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2453 struct reggroup *group)
c44ca51c
AC		 2454{
2455 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
c44ca51c 2456
7cc46491 2457 /* These are the only pseudo-registers we support. */
f949c649 2458 gdb_assert (IS_SPE_PSEUDOREG (tdep, regnum)
604c2f83
LM		 2459 || IS_DFP_PSEUDOREG (tdep, regnum)
2460 || IS_VSX_PSEUDOREG (tdep, regnum)
2461 || IS_EFP_PSEUDOREG (tdep, regnum));
c44ca51c 2462
604c2f83
LM		 2463 /* These are the e500 pseudo-registers or the POWER7 VSX registers. */
2464 if (IS_SPE_PSEUDOREG (tdep, regnum) || IS_VSX_PSEUDOREG (tdep, regnum))
f949c649 2465 return group == all_reggroup || group == vector_reggroup;
7cc46491 2466 else
604c2f83 2467 /* PPC decimal128 or Extended FP pseudo-registers. */
f949c649 2468 return group == all_reggroup || group == float_reggroup;
c44ca51c
AC		 2469}
2470
691d145a 2471/* The register format for RS/6000 floating point registers is always
64366f1c 2472 double, we need a conversion if the memory format is float. */
7a78ae4e
ND		 2473
2474static int
0abe36f5
MD		 2475rs6000_convert_register_p (struct gdbarch *gdbarch, int regnum,
2476 struct type *type)
7a78ae4e 2477{
0abe36f5 2478 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
7cc46491
DJ		 2479
2480 return (tdep->ppc_fp0_regnum >= 0
2481 && regnum >= tdep->ppc_fp0_regnum
2482 && regnum < tdep->ppc_fp0_regnum + ppc_num_fprs
2483 && TYPE_CODE (type) == TYPE_CODE_FLT
0dfff4cb
UW		 2484 && TYPE_LENGTH (type)
2485 != TYPE_LENGTH (builtin_type (gdbarch)->builtin_double));
7a78ae4e
ND		 2486}
2487
7a78ae4e 2488static void
691d145a
JB		 2489rs6000_register_to_value (struct frame_info *frame,
2490 int regnum,
2491 struct type *type,
50fd1280 2492 gdb_byte *to)
7a78ae4e 2493{
0dfff4cb 2494 struct gdbarch *gdbarch = get_frame_arch (frame);
50fd1280 2495 gdb_byte from[MAX_REGISTER_SIZE];
691d145a 2496
691d145a 2497 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
7a78ae4e 2498
691d145a 2499 get_frame_register (frame, regnum, from);
0dfff4cb
UW		 2500 convert_typed_floating (from, builtin_type (gdbarch)->builtin_double,
2501 to, type);
691d145a 2502}
7a292a7a 2503
7a78ae4e 2504static void
691d145a
JB		 2505rs6000_value_to_register (struct frame_info *frame,
2506 int regnum,
2507 struct type *type,
50fd1280 2508 const gdb_byte *from)
7a78ae4e 2509{
0dfff4cb 2510 struct gdbarch *gdbarch = get_frame_arch (frame);
50fd1280 2511 gdb_byte to[MAX_REGISTER_SIZE];
691d145a 2512
691d145a
JB		 2513 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
2514
0dfff4cb
UW		 2515 convert_typed_floating (from, type,
2516 to, builtin_type (gdbarch)->builtin_double);
691d145a 2517 put_frame_register (frame, regnum, to);
7a78ae4e 2518}
c906108c 2519
6ced10dd
JB		 2520/* Move SPE vector register values between a 64-bit buffer and the two
2521 32-bit raw register halves in a regcache. This function handles
2522 both splitting a 64-bit value into two 32-bit halves, and joining
2523 two halves into a whole 64-bit value, depending on the function
2524 passed as the MOVE argument.
2525
2526 EV_REG must be the number of an SPE evN vector register --- a
2527 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
2528 64-bit buffer.
2529
2530 Call MOVE once for each 32-bit half of that register, passing
2531 REGCACHE, the number of the raw register corresponding to that
2532 half, and the address of the appropriate half of BUFFER.
2533
2534 For example, passing 'regcache_raw_read' as the MOVE function will
2535 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
2536 'regcache_raw_supply' will supply the contents of BUFFER to the
2537 appropriate pair of raw registers in REGCACHE.
2538
2539 You may need to cast away some 'const' qualifiers when passing
2540 MOVE, since this function can't tell at compile-time which of
2541 REGCACHE or BUFFER is acting as the source of the data. If C had
2542 co-variant type qualifiers, ... */
2543static void
2544e500_move_ev_register (void (*move) (struct regcache *regcache,
50fd1280 2545 int regnum, gdb_byte *buf),
6ced10dd 2546 struct regcache *regcache, int ev_reg,
50fd1280 2547 gdb_byte *buffer)
6ced10dd
JB		 2548{
2549 struct gdbarch *arch = get_regcache_arch (regcache);
2550 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
2551 int reg_index;
50fd1280 2552 gdb_byte *byte_buffer = buffer;
6ced10dd 2553
5a9e69ba 2554 gdb_assert (IS_SPE_PSEUDOREG (tdep, ev_reg));
6ced10dd
JB		 2555
2556 reg_index = ev_reg - tdep->ppc_ev0_regnum;
2557
8b164abb 2558 if (gdbarch_byte_order (arch) == BFD_ENDIAN_BIG)
6ced10dd
JB		 2559 {
2560 move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer);
2561 move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer + 4);
2562 }
2563 else
2564 {
2565 move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer);
2566 move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer + 4);
2567 }
2568}
2569
c8001721
EZ		 2570static void
2571e500_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
50fd1280 2572 int reg_nr, gdb_byte *buffer)
f949c649
TJB		 2573{
2574 e500_move_ev_register (regcache_raw_read, regcache, reg_nr, buffer);
2575}
2576
2577static void
2578e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2579 int reg_nr, const gdb_byte *buffer)
2580{
2581 e500_move_ev_register ((void (*) (struct regcache *, int, gdb_byte *))
2582 regcache_raw_write,
2583 regcache, reg_nr, (gdb_byte *) buffer);
2584}
2585
604c2f83 2586/* Read method for DFP pseudo-registers. */
f949c649 2587static void
604c2f83 2588dfp_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
f949c649
TJB		 2589 int reg_nr, gdb_byte *buffer)
2590{
2591 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2592 int reg_index = reg_nr - tdep->ppc_dl0_regnum;
2593
2594 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2595 {
2596 /* Read two FP registers to form a whole dl register. */
2597 regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2598 2 * reg_index, buffer);
2599 regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2600 2 * reg_index + 1, buffer + 8);
2601 }
2602 else
2603 {
2604 regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2605 2 * reg_index + 1, buffer + 8);
2606 regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2607 2 * reg_index, buffer);
2608 }
2609}
2610
604c2f83 2611/* Write method for DFP pseudo-registers. */
f949c649 2612static void
604c2f83 2613dfp_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
f949c649
TJB		 2614 int reg_nr, const gdb_byte *buffer)
2615{
2616 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2617 int reg_index = reg_nr - tdep->ppc_dl0_regnum;
2618
2619 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2620 {
2621 /* Write each half of the dl register into a separate
2622 FP register. */
2623 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2624 2 * reg_index, buffer);
2625 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2626 2 * reg_index + 1, buffer + 8);
2627 }
2628 else
2629 {
2630 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2631 2 * reg_index + 1, buffer + 8);
2632 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2633 2 * reg_index, buffer);
2634 }
2635}
2636
604c2f83
LM		 2637/* Read method for POWER7 VSX pseudo-registers. */
2638static void
2639vsx_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2640 int reg_nr, gdb_byte *buffer)
2641{
2642 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2643 int reg_index = reg_nr - tdep->ppc_vsr0_regnum;
2644
2645 /* Read the portion that overlaps the VMX registers. */
2646 if (reg_index > 31)
2647 regcache_raw_read (regcache, tdep->ppc_vr0_regnum +
2648 reg_index - 32, buffer);
2649 else
2650 /* Read the portion that overlaps the FPR registers. */
2651 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2652 {
2653 regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2654 reg_index, buffer);
2655 regcache_raw_read (regcache, tdep->ppc_vsr0_upper_regnum +
2656 reg_index, buffer + 8);
2657 }
2658 else
2659 {
2660 regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2661 reg_index, buffer + 8);
2662 regcache_raw_read (regcache, tdep->ppc_vsr0_upper_regnum +
2663 reg_index, buffer);
2664 }
2665}
2666
2667/* Write method for POWER7 VSX pseudo-registers. */
2668static void
2669vsx_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2670 int reg_nr, const gdb_byte *buffer)
2671{
2672 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2673 int reg_index = reg_nr - tdep->ppc_vsr0_regnum;
2674
2675 /* Write the portion that overlaps the VMX registers. */
2676 if (reg_index > 31)
2677 regcache_raw_write (regcache, tdep->ppc_vr0_regnum +
2678 reg_index - 32, buffer);
2679 else
2680 /* Write the portion that overlaps the FPR registers. */
2681 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2682 {
2683 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2684 reg_index, buffer);
2685 regcache_raw_write (regcache, tdep->ppc_vsr0_upper_regnum +
2686 reg_index, buffer + 8);
2687 }
2688 else
2689 {
2690 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2691 reg_index, buffer + 8);
2692 regcache_raw_write (regcache, tdep->ppc_vsr0_upper_regnum +
2693 reg_index, buffer);
2694 }
2695}
2696
2697/* Read method for POWER7 Extended FP pseudo-registers. */
2698static void
2699efpr_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2700 int reg_nr, gdb_byte *buffer)
2701{
2702 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2703 int reg_index = reg_nr - tdep->ppc_efpr0_regnum;
2704
2705 /* Read the portion that overlaps the VMX registers. */
2706 regcache_raw_read (regcache, tdep->ppc_vr0_regnum +
2707 reg_index, buffer);
2708}
2709
2710/* Write method for POWER7 Extended FP pseudo-registers. */
2711static void
2712efpr_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2713 int reg_nr, const gdb_byte *buffer)
2714{
2715 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2716 int reg_index = reg_nr - tdep->ppc_efpr0_regnum;
2717
2718 /* Write the portion that overlaps the VMX registers. */
2719 regcache_raw_write (regcache, tdep->ppc_vr0_regnum +
2720 reg_index, buffer);
2721}
2722
f949c649
TJB		 2723static void
2724rs6000_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2725 int reg_nr, gdb_byte *buffer)
c8001721 2726{
6ced10dd 2727 struct gdbarch *regcache_arch = get_regcache_arch (regcache);
c8001721
EZ		 2728 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2729
6ced10dd 2730 gdb_assert (regcache_arch == gdbarch);
f949c649 2731
5a9e69ba 2732 if (IS_SPE_PSEUDOREG (tdep, reg_nr))
f949c649
TJB		 2733 e500_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
2734 else if (IS_DFP_PSEUDOREG (tdep, reg_nr))
604c2f83
LM		 2735 dfp_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
2736 else if (IS_VSX_PSEUDOREG (tdep, reg_nr))
2737 vsx_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
2738 else if (IS_EFP_PSEUDOREG (tdep, reg_nr))
2739 efpr_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
6ced10dd 2740 else
a44bddec 2741 internal_error (__FILE__, __LINE__,
f949c649
TJB		 2742 _("rs6000_pseudo_register_read: "
2743 "called on unexpected register '%s' (%d)"),
2744 gdbarch_register_name (gdbarch, reg_nr), reg_nr);
c8001721
EZ		 2745}
2746
2747static void
f949c649
TJB		 2748rs6000_pseudo_register_write (struct gdbarch *gdbarch,
2749 struct regcache *regcache,
2750 int reg_nr, const gdb_byte *buffer)
c8001721 2751{
6ced10dd 2752 struct gdbarch *regcache_arch = get_regcache_arch (regcache);
c8001721
EZ		 2753 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2754
6ced10dd 2755 gdb_assert (regcache_arch == gdbarch);
f949c649 2756
5a9e69ba 2757 if (IS_SPE_PSEUDOREG (tdep, reg_nr))
f949c649
TJB		 2758 e500_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
2759 else if (IS_DFP_PSEUDOREG (tdep, reg_nr))
604c2f83
LM		 2760 dfp_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
2761 else if (IS_VSX_PSEUDOREG (tdep, reg_nr))
2762 vsx_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
2763 else if (IS_EFP_PSEUDOREG (tdep, reg_nr))
2764 efpr_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
6ced10dd 2765 else
a44bddec 2766 internal_error (__FILE__, __LINE__,
f949c649
TJB		 2767 _("rs6000_pseudo_register_write: "
2768 "called on unexpected register '%s' (%d)"),
2769 gdbarch_register_name (gdbarch, reg_nr), reg_nr);
6ced10dd
JB		 2770}
2771
18ed0c4e 2772/* Convert a DBX STABS register number to a GDB register number. */
c8001721 2773static int
d3f73121 2774rs6000_stab_reg_to_regnum (struct gdbarch *gdbarch, int num)
c8001721 2775{
d3f73121 2776 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
c8001721 2777
9f744501
JB		 2778 if (0 <= num && num <= 31)
2779 return tdep->ppc_gp0_regnum + num;
2780 else if (32 <= num && num <= 63)
383f0f5b
JB		 2781 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2782 specifies registers the architecture doesn't have? Our
2783 callers don't check the value we return. */
366f009f 2784 return tdep->ppc_fp0_regnum + (num - 32);
18ed0c4e
JB		 2785 else if (77 <= num && num <= 108)
2786 return tdep->ppc_vr0_regnum + (num - 77);
9f744501
JB		 2787 else if (1200 <= num && num < 1200 + 32)
2788 return tdep->ppc_ev0_regnum + (num - 1200);
2789 else
2790 switch (num)
2791 {
2792 case 64:
2793 return tdep->ppc_mq_regnum;
2794 case 65:
2795 return tdep->ppc_lr_regnum;
2796 case 66:
2797 return tdep->ppc_ctr_regnum;
2798 case 76:
2799 return tdep->ppc_xer_regnum;
2800 case 109:
2801 return tdep->ppc_vrsave_regnum;
18ed0c4e
JB		 2802 case 110:
2803 return tdep->ppc_vrsave_regnum - 1; /* vscr */
867e2dc5 2804 case 111:
18ed0c4e 2805 return tdep->ppc_acc_regnum;
867e2dc5 2806 case 112:
18ed0c4e 2807 return tdep->ppc_spefscr_regnum;
9f744501
JB		 2808 default:
2809 return num;
2810 }
18ed0c4e 2811}
9f744501 2812
9f744501 2813
18ed0c4e
JB		 2814/* Convert a Dwarf 2 register number to a GDB register number. */
2815static int
d3f73121 2816rs6000_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int num)
18ed0c4e 2817{
d3f73121 2818 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
9f744501 2819
18ed0c4e
JB		 2820 if (0 <= num && num <= 31)
2821 return tdep->ppc_gp0_regnum + num;
2822 else if (32 <= num && num <= 63)
2823 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2824 specifies registers the architecture doesn't have? Our
2825 callers don't check the value we return. */
2826 return tdep->ppc_fp0_regnum + (num - 32);
2827 else if (1124 <= num && num < 1124 + 32)
2828 return tdep->ppc_vr0_regnum + (num - 1124);
2829 else if (1200 <= num && num < 1200 + 32)
2830 return tdep->ppc_ev0_regnum + (num - 1200);
2831 else
2832 switch (num)
2833 {
a489f789
AS		 2834 case 64:
2835 return tdep->ppc_cr_regnum;
18ed0c4e
JB		 2836 case 67:
2837 return tdep->ppc_vrsave_regnum - 1; /* vscr */
2838 case 99:
2839 return tdep->ppc_acc_regnum;
2840 case 100:
2841 return tdep->ppc_mq_regnum;
2842 case 101:
2843 return tdep->ppc_xer_regnum;
2844 case 108:
2845 return tdep->ppc_lr_regnum;
2846 case 109:
2847 return tdep->ppc_ctr_regnum;
2848 case 356:
2849 return tdep->ppc_vrsave_regnum;
2850 case 612:
2851 return tdep->ppc_spefscr_regnum;
2852 default:
2853 return num;
2854 }
2188cbdd
EZ		 2855}
2856
4fc771b8
DJ		 2857/* Translate a .eh_frame register to DWARF register, or adjust a
2858 .debug_frame register. */
2859
2860static int
2861rs6000_adjust_frame_regnum (struct gdbarch *gdbarch, int num, int eh_frame_p)
2862{
2863 /* GCC releases before 3.4 use GCC internal register numbering in
2864 .debug_frame (and .debug_info, et cetera). The numbering is
2865 different from the standard SysV numbering for everything except
2866 for GPRs and FPRs. We can not detect this problem in most cases
2867 - to get accurate debug info for variables living in lr, ctr, v0,
2868 et cetera, use a newer version of GCC. But we must detect
2869 one important case - lr is in column 65 in .debug_frame output,
2870 instead of 108.
2871
2872 GCC 3.4, and the "hammer" branch, have a related problem. They
2873 record lr register saves in .debug_frame as 108, but still record
2874 the return column as 65. We fix that up too.
2875
2876 We can do this because 65 is assigned to fpsr, and GCC never
2877 generates debug info referring to it. To add support for
2878 handwritten debug info that restores fpsr, we would need to add a
2879 producer version check to this. */
2880 if (!eh_frame_p)
2881 {
2882 if (num == 65)
2883 return 108;
2884 else
2885 return num;
2886 }
2887
2888 /* .eh_frame is GCC specific. For binary compatibility, it uses GCC
2889 internal register numbering; translate that to the standard DWARF2
2890 register numbering. */
2891 if (0 <= num && num <= 63) /* r0-r31,fp0-fp31 */
2892 return num;
2893 else if (68 <= num && num <= 75) /* cr0-cr8 */
2894 return num - 68 + 86;
2895 else if (77 <= num && num <= 108) /* vr0-vr31 */
2896 return num - 77 + 1124;
2897 else
2898 switch (num)
2899 {
2900 case 64: /* mq */
2901 return 100;
2902 case 65: /* lr */
2903 return 108;
2904 case 66: /* ctr */
2905 return 109;
2906 case 76: /* xer */
2907 return 101;
2908 case 109: /* vrsave */
2909 return 356;
2910 case 110: /* vscr */
2911 return 67;
2912 case 111: /* spe_acc */
2913 return 99;
2914 case 112: /* spefscr */
2915 return 612;
2916 default:
2917 return num;
2918 }
2919}
c906108c 2920\f
c5aa993b 2921
7a78ae4e 2922/* Handling the various POWER/PowerPC variants. */
c906108c 2923
c906108c 2924/* Information about a particular processor variant. */
7a78ae4e 2925
c906108c 2926struct variant
c5aa993b
JM		 2927 {
2928 /* Name of this variant. */
2929 char *name;
c906108c 2930
c5aa993b
JM		 2931 /* English description of the variant. */
2932 char *description;
c906108c 2933
64366f1c 2934 /* bfd_arch_info.arch corresponding to variant. */
7a78ae4e
ND		 2935 enum bfd_architecture arch;
2936
64366f1c 2937 /* bfd_arch_info.mach corresponding to variant. */
7a78ae4e
ND		 2938 unsigned long mach;
2939
7cc46491
DJ		 2940 /* Target description for this variant. */
2941 struct target_desc **tdesc;
c5aa993b 2942 };
c906108c 2943
489461e2 2944static struct variant variants[] =
c906108c 2945{
7a78ae4e 2946 {"powerpc", "PowerPC user-level", bfd_arch_powerpc,
7284e1be 2947 bfd_mach_ppc, &tdesc_powerpc_altivec32},
7a78ae4e 2948 {"power", "POWER user-level", bfd_arch_rs6000,
7cc46491 2949 bfd_mach_rs6k, &tdesc_rs6000},
7a78ae4e 2950 {"403", "IBM PowerPC 403", bfd_arch_powerpc,
7cc46491 2951 bfd_mach_ppc_403, &tdesc_powerpc_403},
4d09ffea
MS		 2952 {"405", "IBM PowerPC 405", bfd_arch_powerpc,
2953 bfd_mach_ppc_405, &tdesc_powerpc_405},
7a78ae4e 2954 {"601", "Motorola PowerPC 601", bfd_arch_powerpc,
7cc46491 2955 bfd_mach_ppc_601, &tdesc_powerpc_601},
7a78ae4e 2956 {"602", "Motorola PowerPC 602", bfd_arch_powerpc,
7cc46491 2957 bfd_mach_ppc_602, &tdesc_powerpc_602},
7a78ae4e 2958 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc,
7cc46491 2959 bfd_mach_ppc_603, &tdesc_powerpc_603},
7a78ae4e 2960 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc,
7cc46491 2961 604, &tdesc_powerpc_604},
7a78ae4e 2962 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc,
7cc46491 2963 bfd_mach_ppc_403gc, &tdesc_powerpc_403gc},
7a78ae4e 2964 {"505", "Motorola PowerPC 505", bfd_arch_powerpc,
7cc46491 2965 bfd_mach_ppc_505, &tdesc_powerpc_505},
7a78ae4e 2966 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc,
7cc46491 2967 bfd_mach_ppc_860, &tdesc_powerpc_860},
7a78ae4e 2968 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc,
7cc46491 2969 bfd_mach_ppc_750, &tdesc_powerpc_750},
1fcc0bb8 2970 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc,
7cc46491 2971 bfd_mach_ppc_7400, &tdesc_powerpc_7400},
c8001721 2972 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc,
7cc46491 2973 bfd_mach_ppc_e500, &tdesc_powerpc_e500},
7a78ae4e 2974
5d57ee30
KB		 2975 /* 64-bit */
2976 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc,
7284e1be 2977 bfd_mach_ppc64, &tdesc_powerpc_altivec64},
7a78ae4e 2978 {"620", "Motorola PowerPC 620", bfd_arch_powerpc,
7cc46491 2979 bfd_mach_ppc_620, &tdesc_powerpc_64},
5d57ee30 2980 {"630", "Motorola PowerPC 630", bfd_arch_powerpc,
7cc46491 2981 bfd_mach_ppc_630, &tdesc_powerpc_64},
7a78ae4e 2982 {"a35", "PowerPC A35", bfd_arch_powerpc,
7cc46491 2983 bfd_mach_ppc_a35, &tdesc_powerpc_64},
5d57ee30 2984 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc,
7cc46491 2985 bfd_mach_ppc_rs64ii, &tdesc_powerpc_64},
5d57ee30 2986 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc,
7cc46491 2987 bfd_mach_ppc_rs64iii, &tdesc_powerpc_64},
5d57ee30 2988
64366f1c 2989 /* FIXME: I haven't checked the register sets of the following. */
7a78ae4e 2990 {"rs1", "IBM POWER RS1", bfd_arch_rs6000,
7cc46491 2991 bfd_mach_rs6k_rs1, &tdesc_rs6000},
7a78ae4e 2992 {"rsc", "IBM POWER RSC", bfd_arch_rs6000,
7cc46491 2993 bfd_mach_rs6k_rsc, &tdesc_rs6000},
7a78ae4e 2994 {"rs2", "IBM POWER RS2", bfd_arch_rs6000,
7cc46491 2995 bfd_mach_rs6k_rs2, &tdesc_rs6000},
7a78ae4e 2996
7cc46491 2997 {0, 0, 0, 0, 0}
c906108c
SS		 2998};
2999
7a78ae4e 3000/* Return the variant corresponding to architecture ARCH and machine number
64366f1c 3001 MACH. If no such variant exists, return null. */
c906108c 3002
7a78ae4e
ND		 3003static const struct variant *
3004find_variant_by_arch (enum bfd_architecture arch, unsigned long mach)
c906108c 3005{
7a78ae4e 3006 const struct variant *v;
c5aa993b 3007
7a78ae4e
ND		 3008 for (v = variants; v->name; v++)
3009 if (arch == v->arch && mach == v->mach)
3010 return v;
c906108c 3011
7a78ae4e 3012 return NULL;
c906108c 3013}
9364a0ef
EZ		 3014
3015static int
3016gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info)
3017{
ee4f0f76
DJ		 3018 if (!info->disassembler_options)
3019 info->disassembler_options = "any";
3020
40887e1a 3021 if (info->endian == BFD_ENDIAN_BIG)
9364a0ef
EZ		 3022 return print_insn_big_powerpc (memaddr, info);
3023 else
3024 return print_insn_little_powerpc (memaddr, info);
3025}
7a78ae4e 3026\f
61a65099
KB		 3027static CORE_ADDR
3028rs6000_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
3029{
3e8c568d 3030 return frame_unwind_register_unsigned (next_frame,
8b164abb 3031 gdbarch_pc_regnum (gdbarch));
61a65099
KB		 3032}
3033
3034static struct frame_id
1af5d7ce 3035rs6000_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
61a65099 3036{
1af5d7ce
UW		 3037 return frame_id_build (get_frame_register_unsigned
3038 (this_frame, gdbarch_sp_regnum (gdbarch)),
3039 get_frame_pc (this_frame));
61a65099
KB		 3040}
3041
3042struct rs6000_frame_cache
3043{
3044 CORE_ADDR base;
3045 CORE_ADDR initial_sp;
3046 struct trad_frame_saved_reg *saved_regs;
3047};
3048
3049static struct rs6000_frame_cache *
1af5d7ce 3050rs6000_frame_cache (struct frame_info *this_frame, void **this_cache)
61a65099
KB		 3051{
3052 struct rs6000_frame_cache *cache;
1af5d7ce 3053 struct gdbarch *gdbarch = get_frame_arch (this_frame);
61a65099 3054 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
e17a4113 3055 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
61a65099
KB		 3056 struct rs6000_framedata fdata;
3057 int wordsize = tdep->wordsize;
e10b1c4c 3058 CORE_ADDR func, pc;
61a65099
KB		 3059
3060 if ((*this_cache) != NULL)
3061 return (*this_cache);
3062 cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache);
3063 (*this_cache) = cache;
1af5d7ce 3064 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
61a65099 3065
1af5d7ce
UW		 3066 func = get_frame_func (this_frame);
3067 pc = get_frame_pc (this_frame);
be8626e0 3068 skip_prologue (gdbarch, func, pc, &fdata);
e10b1c4c
DJ		 3069
3070 /* Figure out the parent's stack pointer. */
3071
3072 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
3073 address of the current frame. Things might be easier if the
3074 ->frame pointed to the outer-most address of the frame. In
3075 the mean time, the address of the prev frame is used as the
3076 base address of this frame. */
1af5d7ce
UW		 3077 cache->base = get_frame_register_unsigned
3078 (this_frame, gdbarch_sp_regnum (gdbarch));
e10b1c4c
DJ		 3079
3080 /* If the function appears to be frameless, check a couple of likely
3081 indicators that we have simply failed to find the frame setup.
3082 Two common cases of this are missing symbols (i.e.
ef02daa9 3083 get_frame_func returns the wrong address or 0), and assembly
e10b1c4c
DJ		 3084 stubs which have a fast exit path but set up a frame on the slow
3085 path.
3086
3087 If the LR appears to return to this function, then presume that
3088 we have an ABI compliant frame that we failed to find. */
3089 if (fdata.frameless && fdata.lr_offset == 0)
61a65099 3090 {
e10b1c4c
DJ		 3091 CORE_ADDR saved_lr;
3092 int make_frame = 0;
3093
1af5d7ce 3094 saved_lr = get_frame_register_unsigned (this_frame, tdep->ppc_lr_regnum);
e10b1c4c
DJ		 3095 if (func == 0 && saved_lr == pc)
3096 make_frame = 1;
3097 else if (func != 0)
3098 {
3099 CORE_ADDR saved_func = get_pc_function_start (saved_lr);
3100 if (func == saved_func)
3101 make_frame = 1;
3102 }
3103
3104 if (make_frame)
3105 {
3106 fdata.frameless = 0;
de6a76fd 3107 fdata.lr_offset = tdep->lr_frame_offset;
e10b1c4c 3108 }
61a65099 3109 }
e10b1c4c
DJ		 3110
3111 if (!fdata.frameless)
3112 /* Frameless really means stackless. */
e17a4113
UW		 3113 cache->base
3114 = read_memory_unsigned_integer (cache->base, wordsize, byte_order);
e10b1c4c 3115
3e8c568d 3116 trad_frame_set_value (cache->saved_regs,
8b164abb 3117 gdbarch_sp_regnum (gdbarch), cache->base);
61a65099
KB		 3118
3119 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
3120 All fpr's from saved_fpr to fp31 are saved. */
3121
3122 if (fdata.saved_fpr >= 0)
3123 {
3124 int i;
3125 CORE_ADDR fpr_addr = cache->base + fdata.fpr_offset;
383f0f5b
JB		 3126
3127 /* If skip_prologue says floating-point registers were saved,
3128 but the current architecture has no floating-point registers,
3129 then that's strange. But we have no indices to even record
3130 the addresses under, so we just ignore it. */
3131 if (ppc_floating_point_unit_p (gdbarch))
063715bf 3132 for (i = fdata.saved_fpr; i < ppc_num_fprs; i++)
383f0f5b
JB		 3133 {
3134 cache->saved_regs[tdep->ppc_fp0_regnum + i].addr = fpr_addr;
3135 fpr_addr += 8;
3136 }
61a65099
KB		 3137 }
3138
3139 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
46a9b8ed
DJ		 3140 All gpr's from saved_gpr to gpr31 are saved (except during the
3141 prologue). */
61a65099
KB		 3142
3143 if (fdata.saved_gpr >= 0)
3144 {
3145 int i;
3146 CORE_ADDR gpr_addr = cache->base + fdata.gpr_offset;
063715bf 3147 for (i = fdata.saved_gpr; i < ppc_num_gprs; i++)
61a65099 3148 {
46a9b8ed
DJ		 3149 if (fdata.gpr_mask & (1U << i))
3150 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = gpr_addr;
61a65099
KB		 3151 gpr_addr += wordsize;
3152 }
3153 }
3154
3155 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
3156 All vr's from saved_vr to vr31 are saved. */
3157 if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
3158 {
3159 if (fdata.saved_vr >= 0)
3160 {
3161 int i;
3162 CORE_ADDR vr_addr = cache->base + fdata.vr_offset;
3163 for (i = fdata.saved_vr; i < 32; i++)
3164 {
3165 cache->saved_regs[tdep->ppc_vr0_regnum + i].addr = vr_addr;
3166 vr_addr += register_size (gdbarch, tdep->ppc_vr0_regnum);
3167 }
3168 }
3169 }
3170
3171 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
3172 All vr's from saved_ev to ev31 are saved. ????? */
5a9e69ba 3173 if (tdep->ppc_ev0_regnum != -1)
61a65099
KB		 3174 {
3175 if (fdata.saved_ev >= 0)
3176 {
3177 int i;
3178 CORE_ADDR ev_addr = cache->base + fdata.ev_offset;
063715bf 3179 for (i = fdata.saved_ev; i < ppc_num_gprs; i++)
61a65099
KB		 3180 {
3181 cache->saved_regs[tdep->ppc_ev0_regnum + i].addr = ev_addr;
3182 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + 4;
3183 ev_addr += register_size (gdbarch, tdep->ppc_ev0_regnum);
3184 }
3185 }
3186 }
3187
3188 /* If != 0, fdata.cr_offset is the offset from the frame that
3189 holds the CR. */
3190 if (fdata.cr_offset != 0)
3191 cache->saved_regs[tdep->ppc_cr_regnum].addr = cache->base + fdata.cr_offset;
3192
3193 /* If != 0, fdata.lr_offset is the offset from the frame that
3194 holds the LR. */
3195 if (fdata.lr_offset != 0)
3196 cache->saved_regs[tdep->ppc_lr_regnum].addr = cache->base + fdata.lr_offset;
46a9b8ed
DJ		 3197 else if (fdata.lr_register != -1)
3198 cache->saved_regs[tdep->ppc_lr_regnum].realreg = fdata.lr_register;
61a65099 3199 /* The PC is found in the link register. */
8b164abb 3200 cache->saved_regs[gdbarch_pc_regnum (gdbarch)] =
3e8c568d 3201 cache->saved_regs[tdep->ppc_lr_regnum];
61a65099
KB		 3202
3203 /* If != 0, fdata.vrsave_offset is the offset from the frame that
3204 holds the VRSAVE. */
3205 if (fdata.vrsave_offset != 0)
3206 cache->saved_regs[tdep->ppc_vrsave_regnum].addr = cache->base + fdata.vrsave_offset;
3207
3208 if (fdata.alloca_reg < 0)
3209 /* If no alloca register used, then fi->frame is the value of the
3210 %sp for this frame, and it is good enough. */
1af5d7ce
UW		 3211 cache->initial_sp
3212 = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch));
61a65099 3213 else
1af5d7ce
UW		 3214 cache->initial_sp
3215 = get_frame_register_unsigned (this_frame, fdata.alloca_reg);
61a65099
KB		 3216
3217 return cache;
3218}
3219
3220static void
1af5d7ce 3221rs6000_frame_this_id (struct frame_info *this_frame, void **this_cache,
61a65099
KB		 3222 struct frame_id *this_id)
3223{
1af5d7ce 3224 struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame,
61a65099 3225 this_cache);
5b197912
UW		 3226 /* This marks the outermost frame. */
3227 if (info->base == 0)
3228 return;
3229
1af5d7ce 3230 (*this_id) = frame_id_build (info->base, get_frame_func (this_frame));
61a65099
KB		 3231}
3232
1af5d7ce
UW		 3233static struct value *
3234rs6000_frame_prev_register (struct frame_info *this_frame,
3235 void **this_cache, int regnum)
61a65099 3236{
1af5d7ce 3237 struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame,
61a65099 3238 this_cache);
1af5d7ce 3239 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
61a65099
KB		 3240}
3241
3242static const struct frame_unwind rs6000_frame_unwind =
3243{
3244 NORMAL_FRAME,
3245 rs6000_frame_this_id,
1af5d7ce
UW		 3246 rs6000_frame_prev_register,
3247 NULL,
3248 default_frame_sniffer
61a65099 3249};
61a65099
KB		 3250\f
3251
3252static CORE_ADDR
1af5d7ce 3253rs6000_frame_base_address (struct frame_info *this_frame, void **this_cache)
61a65099 3254{
1af5d7ce 3255 struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame,
61a65099
KB		 3256 this_cache);
3257 return info->initial_sp;
3258}
3259
3260static const struct frame_base rs6000_frame_base = {
3261 &rs6000_frame_unwind,
3262 rs6000_frame_base_address,
3263 rs6000_frame_base_address,
3264 rs6000_frame_base_address
3265};
3266
3267static const struct frame_base *
1af5d7ce 3268rs6000_frame_base_sniffer (struct frame_info *this_frame)
61a65099
KB		 3269{
3270 return &rs6000_frame_base;
3271}
3272
9274a07c
LM		 3273/* DWARF-2 frame support. Used to handle the detection of
3274 clobbered registers during function calls. */
3275
3276static void
3277ppc_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
3278 struct dwarf2_frame_state_reg *reg,
4a4e5149 3279 struct frame_info *this_frame)
9274a07c
LM		 3280{
3281 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3282
3283 /* PPC32 and PPC64 ABI's are the same regarding volatile and
3284 non-volatile registers. We will use the same code for both. */
3285
3286 /* Call-saved GP registers. */
3287 if ((regnum >= tdep->ppc_gp0_regnum + 14
3288 && regnum <= tdep->ppc_gp0_regnum + 31)
3289 || (regnum == tdep->ppc_gp0_regnum + 1))
3290 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
3291
3292 /* Call-clobbered GP registers. */
3293 if ((regnum >= tdep->ppc_gp0_regnum + 3
3294 && regnum <= tdep->ppc_gp0_regnum + 12)
3295 || (regnum == tdep->ppc_gp0_regnum))
3296 reg->how = DWARF2_FRAME_REG_UNDEFINED;
3297
3298 /* Deal with FP registers, if supported. */
3299 if (tdep->ppc_fp0_regnum >= 0)
3300 {
3301 /* Call-saved FP registers. */
3302 if ((regnum >= tdep->ppc_fp0_regnum + 14
3303 && regnum <= tdep->ppc_fp0_regnum + 31))
3304 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
3305
3306 /* Call-clobbered FP registers. */
3307 if ((regnum >= tdep->ppc_fp0_regnum
3308 && regnum <= tdep->ppc_fp0_regnum + 13))
3309 reg->how = DWARF2_FRAME_REG_UNDEFINED;
3310 }
3311
3312 /* Deal with ALTIVEC registers, if supported. */
3313 if (tdep->ppc_vr0_regnum > 0 && tdep->ppc_vrsave_regnum > 0)
3314 {
3315 /* Call-saved Altivec registers. */
3316 if ((regnum >= tdep->ppc_vr0_regnum + 20
3317 && regnum <= tdep->ppc_vr0_regnum + 31)
3318 || regnum == tdep->ppc_vrsave_regnum)
3319 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
3320
3321 /* Call-clobbered Altivec registers. */
3322 if ((regnum >= tdep->ppc_vr0_regnum
3323 && regnum <= tdep->ppc_vr0_regnum + 19))
3324 reg->how = DWARF2_FRAME_REG_UNDEFINED;
3325 }
3326
3327 /* Handle PC register and Stack Pointer correctly. */
40a6adc1 3328 if (regnum == gdbarch_pc_regnum (gdbarch))
9274a07c 3329 reg->how = DWARF2_FRAME_REG_RA;
40a6adc1 3330 else if (regnum == gdbarch_sp_regnum (gdbarch))
9274a07c
LM		 3331 reg->how = DWARF2_FRAME_REG_CFA;
3332}
3333
3334
7a78ae4e
ND		 3335/* Initialize the current architecture based on INFO. If possible, re-use an
3336 architecture from ARCHES, which is a list of architectures already created
3337 during this debugging session.
c906108c 3338
7a78ae4e 3339 Called e.g. at program startup, when reading a core file, and when reading
64366f1c 3340 a binary file. */
c906108c 3341
7a78ae4e
ND		 3342static struct gdbarch *
3343rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3344{
3345 struct gdbarch *gdbarch;
3346 struct gdbarch_tdep *tdep;
7cc46491 3347 int wordsize, from_xcoff_exec, from_elf_exec;
7a78ae4e
ND		 3348 enum bfd_architecture arch;
3349 unsigned long mach;
3350 bfd abfd;
5bf1c677 3351 asection *sect;
55eddb0f
DJ		 3352 enum auto_boolean soft_float_flag = powerpc_soft_float_global;
3353 int soft_float;
3354 enum powerpc_vector_abi vector_abi = powerpc_vector_abi_global;
604c2f83
LM		 3355 int have_fpu = 1, have_spe = 0, have_mq = 0, have_altivec = 0, have_dfp = 0,
3356 have_vsx = 0;
7cc46491
DJ		 3357 int tdesc_wordsize = -1;
3358 const struct target_desc *tdesc = info.target_desc;
3359 struct tdesc_arch_data *tdesc_data = NULL;
f949c649 3360 int num_pseudoregs = 0;
604c2f83 3361 int cur_reg;
7a78ae4e 3362
f4d9bade
UW		 3363 /* INFO may refer to a binary that is not of the PowerPC architecture,
3364 e.g. when debugging a stand-alone SPE executable on a Cell/B.E. system.
3365 In this case, we must not attempt to infer properties of the (PowerPC
3366 side) of the target system from properties of that executable. Trust
3367 the target description instead. */
3368 if (info.abfd
3369 && bfd_get_arch (info.abfd) != bfd_arch_powerpc
3370 && bfd_get_arch (info.abfd) != bfd_arch_rs6000)
3371 info.abfd = NULL;
3372
9aa1e687 3373 from_xcoff_exec = info.abfd && info.abfd->format == bfd_object &&
7a78ae4e
ND		 3374 bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour;
3375
9aa1e687
KB		 3376 from_elf_exec = info.abfd && info.abfd->format == bfd_object &&
3377 bfd_get_flavour (info.abfd) == bfd_target_elf_flavour;
3378
e712c1cf 3379 /* Check word size. If INFO is from a binary file, infer it from
64366f1c 3380 that, else choose a likely default. */
9aa1e687 3381 if (from_xcoff_exec)
c906108c 3382 {
11ed25ac 3383 if (bfd_xcoff_is_xcoff64 (info.abfd))
7a78ae4e
ND		 3384 wordsize = 8;
3385 else
3386 wordsize = 4;
c906108c 3387 }
9aa1e687
KB		 3388 else if (from_elf_exec)
3389 {
3390 if (elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
3391 wordsize = 8;
3392 else
3393 wordsize = 4;
3394 }
7cc46491
DJ		 3395 else if (tdesc_has_registers (tdesc))
3396 wordsize = -1;
c906108c 3397 else
7a78ae4e 3398 {
27b15785
KB		 3399 if (info.bfd_arch_info != NULL && info.bfd_arch_info->bits_per_word != 0)
3400 wordsize = info.bfd_arch_info->bits_per_word /
3401 info.bfd_arch_info->bits_per_byte;
3402 else
3403 wordsize = 4;
7a78ae4e 3404 }
c906108c 3405
475bbd17
JB		 3406 /* Get the architecture and machine from the BFD. */
3407 arch = info.bfd_arch_info->arch;
3408 mach = info.bfd_arch_info->mach;
5bf1c677
EZ		 3409
3410 /* For e500 executables, the apuinfo section is of help here. Such
3411 section contains the identifier and revision number of each
3412 Application-specific Processing Unit that is present on the
3413 chip. The content of the section is determined by the assembler
3414 which looks at each instruction and determines which unit (and
3415 which version of it) can execute it. In our case we just look for
3416 the existance of the section. */
3417
3418 if (info.abfd)
3419 {
3420 sect = bfd_get_section_by_name (info.abfd, ".PPC.EMB.apuinfo");
3421 if (sect)
3422 {
3423 arch = info.bfd_arch_info->arch;
3424 mach = bfd_mach_ppc_e500;
3425 bfd_default_set_arch_mach (&abfd, arch, mach);
3426 info.bfd_arch_info = bfd_get_arch_info (&abfd);
3427 }
3428 }
3429
7cc46491
DJ		 3430 /* Find a default target description which describes our register
3431 layout, if we do not already have one. */
3432 if (! tdesc_has_registers (tdesc))
3433 {
3434 const struct variant *v;
3435
3436 /* Choose variant. */
3437 v = find_variant_by_arch (arch, mach);
3438 if (!v)
3439 return NULL;
3440
3441 tdesc = *v->tdesc;
3442 }
3443
3444 gdb_assert (tdesc_has_registers (tdesc));
3445
3446 /* Check any target description for validity. */
3447 if (tdesc_has_registers (tdesc))
3448 {
3449 static const char *const gprs[] = {
3450 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
3451 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
3452 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
3453 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
3454 };
3455 static const char *const segment_regs[] = {
3456 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
3457 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
3458 };
3459 const struct tdesc_feature *feature;
3460 int i, valid_p;
3461 static const char *const msr_names[] = { "msr", "ps" };
3462 static const char *const cr_names[] = { "cr", "cnd" };
3463 static const char *const ctr_names[] = { "ctr", "cnt" };
3464
3465 feature = tdesc_find_feature (tdesc,
3466 "org.gnu.gdb.power.core");
3467 if (feature == NULL)
3468 return NULL;
3469
3470 tdesc_data = tdesc_data_alloc ();
3471
3472 valid_p = 1;
3473 for (i = 0; i < ppc_num_gprs; i++)
3474 valid_p &= tdesc_numbered_register (feature, tdesc_data, i, gprs[i]);
3475 valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_PC_REGNUM,
3476 "pc");
3477 valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_LR_REGNUM,
3478 "lr");
3479 valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_XER_REGNUM,
3480 "xer");
3481
3482 /* Allow alternate names for these registers, to accomodate GDB's
3483 historic naming. */
3484 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3485 PPC_MSR_REGNUM, msr_names);
3486 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3487 PPC_CR_REGNUM, cr_names);
3488 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3489 PPC_CTR_REGNUM, ctr_names);
3490
3491 if (!valid_p)
3492 {
3493 tdesc_data_cleanup (tdesc_data);
3494 return NULL;
3495 }
3496
3497 have_mq = tdesc_numbered_register (feature, tdesc_data, PPC_MQ_REGNUM,
3498 "mq");
3499
3500 tdesc_wordsize = tdesc_register_size (feature, "pc") / 8;
3501 if (wordsize == -1)
3502 wordsize = tdesc_wordsize;
3503
3504 feature = tdesc_find_feature (tdesc,
3505 "org.gnu.gdb.power.fpu");
3506 if (feature != NULL)
3507 {
3508 static const char *const fprs[] = {
3509 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
3510 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
3511 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
3512 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
3513 };
3514 valid_p = 1;
3515 for (i = 0; i < ppc_num_fprs; i++)
3516 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3517 PPC_F0_REGNUM + i, fprs[i]);
3518 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3519 PPC_FPSCR_REGNUM, "fpscr");
3520
3521 if (!valid_p)
3522 {
3523 tdesc_data_cleanup (tdesc_data);
3524 return NULL;
3525 }
3526 have_fpu = 1;
3527 }
3528 else
3529 have_fpu = 0;
3530
f949c649
TJB		 3531 /* The DFP pseudo-registers will be available when there are floating
3532 point registers. */
3533 have_dfp = have_fpu;
3534
7cc46491
DJ		 3535 feature = tdesc_find_feature (tdesc,
3536 "org.gnu.gdb.power.altivec");
3537 if (feature != NULL)
3538 {
3539 static const char *const vector_regs[] = {
3540 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
3541 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
3542 "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23",
3543 "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31"
3544 };
3545
3546 valid_p = 1;
3547 for (i = 0; i < ppc_num_gprs; i++)
3548 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3549 PPC_VR0_REGNUM + i,
3550 vector_regs[i]);
3551 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3552 PPC_VSCR_REGNUM, "vscr");
3553 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3554 PPC_VRSAVE_REGNUM, "vrsave");
3555
3556 if (have_spe || !valid_p)
3557 {
3558 tdesc_data_cleanup (tdesc_data);
3559 return NULL;
3560 }
3561 have_altivec = 1;
3562 }
3563 else
3564 have_altivec = 0;
3565
604c2f83
LM		 3566 /* Check for POWER7 VSX registers support. */
3567 feature = tdesc_find_feature (tdesc,
3568 "org.gnu.gdb.power.vsx");
3569
3570 if (feature != NULL)
3571 {
3572 static const char *const vsx_regs[] = {
3573 "vs0h", "vs1h", "vs2h", "vs3h", "vs4h", "vs5h",
3574 "vs6h", "vs7h", "vs8h", "vs9h", "vs10h", "vs11h",
3575 "vs12h", "vs13h", "vs14h", "vs15h", "vs16h", "vs17h",
3576 "vs18h", "vs19h", "vs20h", "vs21h", "vs22h", "vs23h",
3577 "vs24h", "vs25h", "vs26h", "vs27h", "vs28h", "vs29h",
3578 "vs30h", "vs31h"
3579 };
3580
3581 valid_p = 1;
3582
3583 for (i = 0; i < ppc_num_vshrs; i++)
3584 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3585 PPC_VSR0_UPPER_REGNUM + i,
3586 vsx_regs[i]);
3587 if (!valid_p)
3588 {
3589 tdesc_data_cleanup (tdesc_data);
3590 return NULL;
3591 }
3592
3593 have_vsx = 1;
3594 }
3595 else
3596 have_vsx = 0;
3597
7cc46491
DJ		 3598 /* On machines supporting the SPE APU, the general-purpose registers
3599 are 64 bits long. There are SIMD vector instructions to treat them
3600 as pairs of floats, but the rest of the instruction set treats them
3601 as 32-bit registers, and only operates on their lower halves.
3602
3603 In the GDB regcache, we treat their high and low halves as separate
3604 registers. The low halves we present as the general-purpose
3605 registers, and then we have pseudo-registers that stitch together
3606 the upper and lower halves and present them as pseudo-registers.
3607
3608 Thus, the target description is expected to supply the upper
3609 halves separately. */
3610
3611 feature = tdesc_find_feature (tdesc,
3612 "org.gnu.gdb.power.spe");
3613 if (feature != NULL)
3614 {
3615 static const char *const upper_spe[] = {
3616 "ev0h", "ev1h", "ev2h", "ev3h",
3617 "ev4h", "ev5h", "ev6h", "ev7h",
3618 "ev8h", "ev9h", "ev10h", "ev11h",
3619 "ev12h", "ev13h", "ev14h", "ev15h",
3620 "ev16h", "ev17h", "ev18h", "ev19h",
3621 "ev20h", "ev21h", "ev22h", "ev23h",
3622 "ev24h", "ev25h", "ev26h", "ev27h",
3623 "ev28h", "ev29h", "ev30h", "ev31h"
3624 };
3625
3626 valid_p = 1;
3627 for (i = 0; i < ppc_num_gprs; i++)
3628 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3629 PPC_SPE_UPPER_GP0_REGNUM + i,
3630 upper_spe[i]);
3631 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3632 PPC_SPE_ACC_REGNUM, "acc");
3633 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3634 PPC_SPE_FSCR_REGNUM, "spefscr");
3635
3636 if (have_mq || have_fpu || !valid_p)
3637 {
3638 tdesc_data_cleanup (tdesc_data);
3639 return NULL;
3640 }
3641 have_spe = 1;
3642 }
3643 else
3644 have_spe = 0;
3645 }
3646
3647 /* If we have a 64-bit binary on a 32-bit target, complain. Also
3648 complain for a 32-bit binary on a 64-bit target; we do not yet
3649 support that. For instance, the 32-bit ABI routines expect
3650 32-bit GPRs.
3651
3652 As long as there isn't an explicit target description, we'll
3653 choose one based on the BFD architecture and get a word size
3654 matching the binary (probably powerpc:common or
3655 powerpc:common64). So there is only trouble if a 64-bit target
3656 supplies a 64-bit description while debugging a 32-bit
3657 binary. */
3658 if (tdesc_wordsize != -1 && tdesc_wordsize != wordsize)
3659 {
3660 tdesc_data_cleanup (tdesc_data);
3661 return NULL;
3662 }
3663
55eddb0f
DJ		 3664#ifdef HAVE_ELF
3665 if (soft_float_flag == AUTO_BOOLEAN_AUTO && from_elf_exec)
3666 {
3667 switch (bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU,
3668 Tag_GNU_Power_ABI_FP))
3669 {
3670 case 1:
3671 soft_float_flag = AUTO_BOOLEAN_FALSE;
3672 break;
3673 case 2:
3674 soft_float_flag = AUTO_BOOLEAN_TRUE;
3675 break;
3676 default:
3677 break;
3678 }
3679 }
3680
3681 if (vector_abi == POWERPC_VEC_AUTO && from_elf_exec)
3682 {
3683 switch (bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU,
3684 Tag_GNU_Power_ABI_Vector))
3685 {
3686 case 1:
3687 vector_abi = POWERPC_VEC_GENERIC;
3688 break;
3689 case 2:
3690 vector_abi = POWERPC_VEC_ALTIVEC;
3691 break;
3692 case 3:
3693 vector_abi = POWERPC_VEC_SPE;
3694 break;
3695 default:
3696 break;
3697 }
3698 }
3699#endif
3700
3701 if (soft_float_flag == AUTO_BOOLEAN_TRUE)
3702 soft_float = 1;
3703 else if (soft_float_flag == AUTO_BOOLEAN_FALSE)
3704 soft_float = 0;
3705 else
3706 soft_float = !have_fpu;
3707
3708 /* If we have a hard float binary or setting but no floating point
3709 registers, downgrade to soft float anyway. We're still somewhat
3710 useful in this scenario. */
3711 if (!soft_float && !have_fpu)
3712 soft_float = 1;
3713
3714 /* Similarly for vector registers. */
3715 if (vector_abi == POWERPC_VEC_ALTIVEC && !have_altivec)
3716 vector_abi = POWERPC_VEC_GENERIC;
3717
3718 if (vector_abi == POWERPC_VEC_SPE && !have_spe)
3719 vector_abi = POWERPC_VEC_GENERIC;
3720
3721 if (vector_abi == POWERPC_VEC_AUTO)
3722 {
3723 if (have_altivec)
3724 vector_abi = POWERPC_VEC_ALTIVEC;
3725 else if (have_spe)
3726 vector_abi = POWERPC_VEC_SPE;
3727 else
3728 vector_abi = POWERPC_VEC_GENERIC;
3729 }
3730
3731 /* Do not limit the vector ABI based on available hardware, since we
3732 do not yet know what hardware we'll decide we have. Yuck! FIXME! */
3733
7cc46491
DJ		 3734 /* Find a candidate among extant architectures. */
3735 for (arches = gdbarch_list_lookup_by_info (arches, &info);
3736 arches != NULL;
3737 arches = gdbarch_list_lookup_by_info (arches->next, &info))
3738 {
3739 /* Word size in the various PowerPC bfd_arch_info structs isn't
3740 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
3741 separate word size check. */
3742 tdep = gdbarch_tdep (arches->gdbarch);
55eddb0f
DJ		 3743 if (tdep && tdep->soft_float != soft_float)
3744 continue;
3745 if (tdep && tdep->vector_abi != vector_abi)
3746 continue;
7cc46491
DJ		 3747 if (tdep && tdep->wordsize == wordsize)
3748 {
3749 if (tdesc_data != NULL)
3750 tdesc_data_cleanup (tdesc_data);
3751 return arches->gdbarch;
3752 }
3753 }
3754
3755 /* None found, create a new architecture from INFO, whose bfd_arch_info
3756 validity depends on the source:
3757 - executable useless
3758 - rs6000_host_arch() good
3759 - core file good
3760 - "set arch" trust blindly
3761 - GDB startup useless but harmless */
3762
3763 tdep = XCALLOC (1, struct gdbarch_tdep);
3764 tdep->wordsize = wordsize;
55eddb0f
DJ		 3765 tdep->soft_float = soft_float;
3766 tdep->vector_abi = vector_abi;
7cc46491 3767
7a78ae4e 3768 gdbarch = gdbarch_alloc (&info, tdep);
7a78ae4e 3769
7cc46491
DJ		 3770 tdep->ppc_gp0_regnum = PPC_R0_REGNUM;
3771 tdep->ppc_toc_regnum = PPC_R0_REGNUM + 2;
3772 tdep->ppc_ps_regnum = PPC_MSR_REGNUM;
3773 tdep->ppc_cr_regnum = PPC_CR_REGNUM;
3774 tdep->ppc_lr_regnum = PPC_LR_REGNUM;
3775 tdep->ppc_ctr_regnum = PPC_CTR_REGNUM;
3776 tdep->ppc_xer_regnum = PPC_XER_REGNUM;
3777 tdep->ppc_mq_regnum = have_mq ? PPC_MQ_REGNUM : -1;
3778
3779 tdep->ppc_fp0_regnum = have_fpu ? PPC_F0_REGNUM : -1;
3780 tdep->ppc_fpscr_regnum = have_fpu ? PPC_FPSCR_REGNUM : -1;
604c2f83 3781 tdep->ppc_vsr0_upper_regnum = have_vsx ? PPC_VSR0_UPPER_REGNUM : -1;
7cc46491
DJ		 3782 tdep->ppc_vr0_regnum = have_altivec ? PPC_VR0_REGNUM : -1;
3783 tdep->ppc_vrsave_regnum = have_altivec ? PPC_VRSAVE_REGNUM : -1;
3784 tdep->ppc_ev0_upper_regnum = have_spe ? PPC_SPE_UPPER_GP0_REGNUM : -1;
3785 tdep->ppc_acc_regnum = have_spe ? PPC_SPE_ACC_REGNUM : -1;
3786 tdep->ppc_spefscr_regnum = have_spe ? PPC_SPE_FSCR_REGNUM : -1;
3787
3788 set_gdbarch_pc_regnum (gdbarch, PPC_PC_REGNUM);
3789 set_gdbarch_sp_regnum (gdbarch, PPC_R0_REGNUM + 1);
3790 set_gdbarch_deprecated_fp_regnum (gdbarch, PPC_R0_REGNUM + 1);
3791 set_gdbarch_fp0_regnum (gdbarch, tdep->ppc_fp0_regnum);
9f643768 3792 set_gdbarch_register_sim_regno (gdbarch, rs6000_register_sim_regno);
7cc46491
DJ		 3793
3794 /* The XML specification for PowerPC sensibly calls the MSR "msr".
3795 GDB traditionally called it "ps", though, so let GDB add an
3796 alias. */
3797 set_gdbarch_ps_regnum (gdbarch, tdep->ppc_ps_regnum);
3798
4a7622d1 3799 if (wordsize == 8)
05580c65 3800 set_gdbarch_return_value (gdbarch, ppc64_sysv_abi_return_value);
afd48b75 3801 else
4a7622d1 3802 set_gdbarch_return_value (gdbarch, ppc_sysv_abi_return_value);
c8001721 3803
baffbae0
JB		 3804 /* Set lr_frame_offset. */
3805 if (wordsize == 8)
3806 tdep->lr_frame_offset = 16;
baffbae0 3807 else
4a7622d1 3808 tdep->lr_frame_offset = 4;
baffbae0 3809
604c2f83 3810 if (have_spe || have_dfp || have_vsx)
7cc46491 3811 {
f949c649
TJB		 3812 set_gdbarch_pseudo_register_read (gdbarch, rs6000_pseudo_register_read);
3813 set_gdbarch_pseudo_register_write (gdbarch, rs6000_pseudo_register_write);
7cc46491 3814 }
1fcc0bb8 3815
e0d24f8d
WZ		 3816 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
3817
56a6dfb9 3818 /* Select instruction printer. */
708ff411 3819 if (arch == bfd_arch_rs6000)
9364a0ef 3820 set_gdbarch_print_insn (gdbarch, print_insn_rs6000);
56a6dfb9 3821 else
9364a0ef 3822 set_gdbarch_print_insn (gdbarch, gdb_print_insn_powerpc);
7495d1dc 3823
5a9e69ba 3824 set_gdbarch_num_regs (gdbarch, PPC_NUM_REGS);
f949c649
TJB		 3825
3826 if (have_spe)
3827 num_pseudoregs += 32;
3828 if (have_dfp)
3829 num_pseudoregs += 16;
604c2f83
LM		 3830 if (have_vsx)
3831 /* Include both VSX and Extended FP registers. */
3832 num_pseudoregs += 96;
f949c649
TJB		 3833
3834 set_gdbarch_num_pseudo_regs (gdbarch, num_pseudoregs);
7a78ae4e
ND		 3835
3836 set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
3837 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
3838 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
3839 set_gdbarch_long_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
3840 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
3841 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
3842 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
4a7622d1 3843 set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT);
4e409299 3844 set_gdbarch_char_signed (gdbarch, 0);
7a78ae4e 3845
11269d7e 3846 set_gdbarch_frame_align (gdbarch, rs6000_frame_align);
4a7622d1 3847 if (wordsize == 8)
8b148df9
AC		 3848 /* PPC64 SYSV. */
3849 set_gdbarch_frame_red_zone_size (gdbarch, 288);
7a78ae4e 3850
691d145a
JB		 3851 set_gdbarch_convert_register_p (gdbarch, rs6000_convert_register_p);
3852 set_gdbarch_register_to_value (gdbarch, rs6000_register_to_value);
3853 set_gdbarch_value_to_register (gdbarch, rs6000_value_to_register);
3854
18ed0c4e
JB		 3855 set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_stab_reg_to_regnum);
3856 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rs6000_dwarf2_reg_to_regnum);
d217aaed 3857
4a7622d1 3858 if (wordsize == 4)
77b2b6d4 3859 set_gdbarch_push_dummy_call (gdbarch, ppc_sysv_abi_push_dummy_call);
4a7622d1 3860 else if (wordsize == 8)
8be9034a 3861 set_gdbarch_push_dummy_call (gdbarch, ppc64_sysv_abi_push_dummy_call);
7a78ae4e 3862
7a78ae4e 3863 set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue);
0d1243d9 3864 set_gdbarch_in_function_epilogue_p (gdbarch, rs6000_in_function_epilogue_p);
8ab3d180 3865 set_gdbarch_skip_main_prologue (gdbarch, rs6000_skip_main_prologue);
0d1243d9 3866
7a78ae4e 3867 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
7a78ae4e
ND		 3868 set_gdbarch_breakpoint_from_pc (gdbarch, rs6000_breakpoint_from_pc);
3869
203c3895
UW		 3870 /* The value of symbols of type N_SO and N_FUN maybe null when
3871 it shouldn't be. */
3872 set_gdbarch_sofun_address_maybe_missing (gdbarch, 1);
3873
ce5eab59 3874 /* Handles single stepping of atomic sequences. */
4a7622d1 3875 set_gdbarch_software_single_step (gdbarch, ppc_deal_with_atomic_sequence);
ce5eab59 3876
7a78ae4e
ND		 3877 /* Not sure on this. FIXMEmgo */
3878 set_gdbarch_frame_args_skip (gdbarch, 8);
3879
143985b7
AF		 3880 /* Helpers for function argument information. */
3881 set_gdbarch_fetch_pointer_argument (gdbarch, rs6000_fetch_pointer_argument);
3882
6f7f3f0d
UW		 3883 /* Trampoline. */
3884 set_gdbarch_in_solib_return_trampoline
3885 (gdbarch, rs6000_in_solib_return_trampoline);
3886 set_gdbarch_skip_trampoline_code (gdbarch, rs6000_skip_trampoline_code);
3887
4fc771b8 3888 /* Hook in the DWARF CFI frame unwinder. */
1af5d7ce 3889 dwarf2_append_unwinders (gdbarch);
4fc771b8
DJ		 3890 dwarf2_frame_set_adjust_regnum (gdbarch, rs6000_adjust_frame_regnum);
3891
9274a07c
LM		 3892 /* Frame handling. */
3893 dwarf2_frame_set_init_reg (gdbarch, ppc_dwarf2_frame_init_reg);
3894
2454a024
UW		 3895 /* Setup displaced stepping. */
3896 set_gdbarch_displaced_step_copy_insn (gdbarch,
3897 simple_displaced_step_copy_insn);
3898 set_gdbarch_displaced_step_fixup (gdbarch, ppc_displaced_step_fixup);
3899 set_gdbarch_displaced_step_free_closure (gdbarch,
3900 simple_displaced_step_free_closure);
3901 set_gdbarch_displaced_step_location (gdbarch,
3902 displaced_step_at_entry_point);
3903
3904 set_gdbarch_max_insn_length (gdbarch, PPC_INSN_SIZE);
3905
7b112f9c 3906 /* Hook in ABI-specific overrides, if they have been registered. */
8a4c2d24
UW		 3907 info.target_desc = tdesc;
3908 info.tdep_info = (void *) tdesc_data;
4be87837 3909 gdbarch_init_osabi (info, gdbarch);
7b112f9c 3910
61a65099
KB		 3911 switch (info.osabi)
3912 {
f5aecab8 3913 case GDB_OSABI_LINUX:
61a65099
KB		 3914 case GDB_OSABI_NETBSD_AOUT:
3915 case GDB_OSABI_NETBSD_ELF:
3916 case GDB_OSABI_UNKNOWN:
61a65099 3917 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
1af5d7ce
UW		 3918 frame_unwind_append_unwinder (gdbarch, &rs6000_frame_unwind);
3919 set_gdbarch_dummy_id (gdbarch, rs6000_dummy_id);
61a65099
KB		 3920 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
3921 break;
3922 default:
61a65099 3923 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
81332287
KB		 3924
3925 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
1af5d7ce
UW		 3926 frame_unwind_append_unwinder (gdbarch, &rs6000_frame_unwind);
3927 set_gdbarch_dummy_id (gdbarch, rs6000_dummy_id);
81332287 3928 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
61a65099
KB		 3929 }
3930
7cc46491
DJ		 3931 set_tdesc_pseudo_register_type (gdbarch, rs6000_pseudo_register_type);
3932 set_tdesc_pseudo_register_reggroup_p (gdbarch,
3933 rs6000_pseudo_register_reggroup_p);
3934 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
3935
3936 /* Override the normal target description method to make the SPE upper
3937 halves anonymous. */
3938 set_gdbarch_register_name (gdbarch, rs6000_register_name);
3939
604c2f83
LM		 3940 /* Choose register numbers for all supported pseudo-registers. */
3941 tdep->ppc_ev0_regnum = -1;
3942 tdep->ppc_dl0_regnum = -1;
3943 tdep->ppc_vsr0_regnum = -1;
3944 tdep->ppc_efpr0_regnum = -1;
9f643768 3945
604c2f83
LM		 3946 cur_reg = gdbarch_num_regs (gdbarch);
3947
3948 if (have_spe)
3949 {
3950 tdep->ppc_ev0_regnum = cur_reg;
3951 cur_reg += 32;
3952 }
3953 if (have_dfp)
3954 {
3955 tdep->ppc_dl0_regnum = cur_reg;
3956 cur_reg += 16;
3957 }
3958 if (have_vsx)
3959 {
3960 tdep->ppc_vsr0_regnum = cur_reg;
3961 cur_reg += 64;
3962 tdep->ppc_efpr0_regnum = cur_reg;
3963 cur_reg += 32;
3964 }
f949c649 3965
604c2f83
LM		 3966 gdb_assert (gdbarch_num_regs (gdbarch)
3967 + gdbarch_num_pseudo_regs (gdbarch) == cur_reg);
f949c649 3968
7a78ae4e 3969 return gdbarch;
c906108c
SS		 3970}
3971
7b112f9c 3972static void
8b164abb 3973rs6000_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
7b112f9c 3974{
8b164abb 3975 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
7b112f9c
JT		 3976
3977 if (tdep == NULL)
3978 return;
3979
4be87837 3980 /* FIXME: Dump gdbarch_tdep. */
7b112f9c
JT		 3981}
3982
55eddb0f
DJ		 3983/* PowerPC-specific commands. */
3984
3985static void
3986set_powerpc_command (char *args, int from_tty)
3987{
3988 printf_unfiltered (_("\
3989\"set powerpc\" must be followed by an appropriate subcommand.\n"));
3990 help_list (setpowerpccmdlist, "set powerpc ", all_commands, gdb_stdout);
3991}
3992
3993static void
3994show_powerpc_command (char *args, int from_tty)
3995{
3996 cmd_show_list (showpowerpccmdlist, from_tty, "");
3997}
3998
3999static void
4000powerpc_set_soft_float (char *args, int from_tty,
4001 struct cmd_list_element *c)
4002{
4003 struct gdbarch_info info;
4004
4005 /* Update the architecture. */
4006 gdbarch_info_init (&info);
4007 if (!gdbarch_update_p (info))
4008 internal_error (__FILE__, __LINE__, "could not update architecture");
4009}
4010
4011static void
4012powerpc_set_vector_abi (char *args, int from_tty,
4013 struct cmd_list_element *c)
4014{
4015 struct gdbarch_info info;
4016 enum powerpc_vector_abi vector_abi;
4017
4018 for (vector_abi = POWERPC_VEC_AUTO;
4019 vector_abi != POWERPC_VEC_LAST;
4020 vector_abi++)
4021 if (strcmp (powerpc_vector_abi_string,
4022 powerpc_vector_strings[vector_abi]) == 0)
4023 {
4024 powerpc_vector_abi_global = vector_abi;
4025 break;
4026 }
4027
4028 if (vector_abi == POWERPC_VEC_LAST)
4029 internal_error (__FILE__, __LINE__, _("Invalid vector ABI accepted: %s."),
4030 powerpc_vector_abi_string);
4031
4032 /* Update the architecture. */
4033 gdbarch_info_init (&info);
4034 if (!gdbarch_update_p (info))
4035 internal_error (__FILE__, __LINE__, "could not update architecture");
4036}
4037
c906108c
SS		 4038/* Initialization code. */
4039
a78f21af 4040extern initialize_file_ftype _initialize_rs6000_tdep; /* -Wmissing-prototypes */
b9362cc7 4041
c906108c 4042void
fba45db2 4043_initialize_rs6000_tdep (void)
c906108c 4044{
7b112f9c
JT		 4045 gdbarch_register (bfd_arch_rs6000, rs6000_gdbarch_init, rs6000_dump_tdep);
4046 gdbarch_register (bfd_arch_powerpc, rs6000_gdbarch_init, rs6000_dump_tdep);
7cc46491
DJ		 4047
4048 /* Initialize the standard target descriptions. */
4049 initialize_tdesc_powerpc_32 ();
7284e1be 4050 initialize_tdesc_powerpc_altivec32 ();
604c2f83 4051 initialize_tdesc_powerpc_vsx32 ();
7cc46491
DJ		 4052 initialize_tdesc_powerpc_403 ();
4053 initialize_tdesc_powerpc_403gc ();
4d09ffea 4054 initialize_tdesc_powerpc_405 ();
7cc46491
DJ		 4055 initialize_tdesc_powerpc_505 ();
4056 initialize_tdesc_powerpc_601 ();
4057 initialize_tdesc_powerpc_602 ();
4058 initialize_tdesc_powerpc_603 ();
4059 initialize_tdesc_powerpc_604 ();
4060 initialize_tdesc_powerpc_64 ();
7284e1be 4061 initialize_tdesc_powerpc_altivec64 ();
604c2f83 4062 initialize_tdesc_powerpc_vsx64 ();
7cc46491
DJ		 4063 initialize_tdesc_powerpc_7400 ();
4064 initialize_tdesc_powerpc_750 ();
4065 initialize_tdesc_powerpc_860 ();
4066 initialize_tdesc_powerpc_e500 ();
4067 initialize_tdesc_rs6000 ();
55eddb0f
DJ		 4068
4069 /* Add root prefix command for all "set powerpc"/"show powerpc"
4070 commands. */
4071 add_prefix_cmd ("powerpc", no_class, set_powerpc_command,
4072 _("Various PowerPC-specific commands."),
4073 &setpowerpccmdlist, "set powerpc ", 0, &setlist);
4074
4075 add_prefix_cmd ("powerpc", no_class, show_powerpc_command,
4076 _("Various PowerPC-specific commands."),
4077 &showpowerpccmdlist, "show powerpc ", 0, &showlist);
4078
4079 /* Add a command to allow the user to force the ABI. */
4080 add_setshow_auto_boolean_cmd ("soft-float", class_support,
4081 &powerpc_soft_float_global,
4082 _("Set whether to use a soft-float ABI."),
4083 _("Show whether to use a soft-float ABI."),
4084 NULL,
4085 powerpc_set_soft_float, NULL,
4086 &setpowerpccmdlist, &showpowerpccmdlist);
4087
4088 add_setshow_enum_cmd ("vector-abi", class_support, powerpc_vector_strings,
4089 &powerpc_vector_abi_string,
4090 _("Set the vector ABI."),
4091 _("Show the vector ABI."),
4092 NULL, powerpc_set_vector_abi, NULL,
4093 &setpowerpccmdlist, &showpowerpccmdlist);
c906108c 4094}
GDB Binutils - Deliverables
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