Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for GDB, the GNU debugger. |
7aea86e6 | 2 | |
197e01b6 | 3 | Copyright (C) 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, |
721d14ba DJ |
4 | 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006 |
5 | Free Software Foundation, Inc. | |
c906108c | 6 | |
c5aa993b | 7 | This file is part of GDB. |
c906108c | 8 | |
c5aa993b JM |
9 | This program is free software; you can redistribute it and/or modify |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2 of the License, or | |
12 | (at your option) any later version. | |
c906108c | 13 | |
c5aa993b JM |
14 | This program is distributed in the hope that it will be useful, |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
c906108c | 18 | |
c5aa993b JM |
19 | You should have received a copy of the GNU General Public License |
20 | along with this program; if not, write to the Free Software | |
197e01b6 EZ |
21 | Foundation, Inc., 51 Franklin Street, Fifth Floor, |
22 | Boston, MA 02110-1301, USA. */ | |
c906108c SS |
23 | |
24 | #include "defs.h" | |
25 | #include "frame.h" | |
26 | #include "inferior.h" | |
27 | #include "symtab.h" | |
28 | #include "target.h" | |
29 | #include "gdbcore.h" | |
30 | #include "gdbcmd.h" | |
c906108c | 31 | #include "objfiles.h" |
7a78ae4e | 32 | #include "arch-utils.h" |
4e052eda | 33 | #include "regcache.h" |
d195bc9f | 34 | #include "regset.h" |
d16aafd8 | 35 | #include "doublest.h" |
fd0407d6 | 36 | #include "value.h" |
1fcc0bb8 | 37 | #include "parser-defs.h" |
4be87837 | 38 | #include "osabi.h" |
7d9b040b | 39 | #include "infcall.h" |
9f643768 JB |
40 | #include "sim-regno.h" |
41 | #include "gdb/sim-ppc.h" | |
6ced10dd | 42 | #include "reggroups.h" |
7a78ae4e | 43 | |
2fccf04a | 44 | #include "libbfd.h" /* for bfd_default_set_arch_mach */ |
7a78ae4e | 45 | #include "coff/internal.h" /* for libcoff.h */ |
2fccf04a | 46 | #include "libcoff.h" /* for xcoff_data */ |
11ed25ac KB |
47 | #include "coff/xcoff.h" |
48 | #include "libxcoff.h" | |
7a78ae4e | 49 | |
9aa1e687 | 50 | #include "elf-bfd.h" |
7a78ae4e | 51 | |
6ded7999 | 52 | #include "solib-svr4.h" |
9aa1e687 | 53 | #include "ppc-tdep.h" |
7a78ae4e | 54 | |
338ef23d | 55 | #include "gdb_assert.h" |
a89aa300 | 56 | #include "dis-asm.h" |
338ef23d | 57 | |
61a65099 KB |
58 | #include "trad-frame.h" |
59 | #include "frame-unwind.h" | |
60 | #include "frame-base.h" | |
61 | ||
c44ca51c | 62 | #include "reggroups.h" |
1f82754b | 63 | #include "rs6000-tdep.h" |
c44ca51c | 64 | |
7a78ae4e ND |
65 | /* If the kernel has to deliver a signal, it pushes a sigcontext |
66 | structure on the stack and then calls the signal handler, passing | |
67 | the address of the sigcontext in an argument register. Usually | |
68 | the signal handler doesn't save this register, so we have to | |
69 | access the sigcontext structure via an offset from the signal handler | |
70 | frame. | |
71 | The following constants were determined by experimentation on AIX 3.2. */ | |
72 | #define SIG_FRAME_PC_OFFSET 96 | |
73 | #define SIG_FRAME_LR_OFFSET 108 | |
74 | #define SIG_FRAME_FP_OFFSET 284 | |
75 | ||
7a78ae4e ND |
76 | /* To be used by skip_prologue. */ |
77 | ||
78 | struct rs6000_framedata | |
79 | { | |
80 | int offset; /* total size of frame --- the distance | |
81 | by which we decrement sp to allocate | |
82 | the frame */ | |
83 | int saved_gpr; /* smallest # of saved gpr */ | |
84 | int saved_fpr; /* smallest # of saved fpr */ | |
6be8bc0c | 85 | int saved_vr; /* smallest # of saved vr */ |
96ff0de4 | 86 | int saved_ev; /* smallest # of saved ev */ |
7a78ae4e ND |
87 | int alloca_reg; /* alloca register number (frame ptr) */ |
88 | char frameless; /* true if frameless functions. */ | |
89 | char nosavedpc; /* true if pc not saved. */ | |
90 | int gpr_offset; /* offset of saved gprs from prev sp */ | |
91 | int fpr_offset; /* offset of saved fprs from prev sp */ | |
6be8bc0c | 92 | int vr_offset; /* offset of saved vrs from prev sp */ |
96ff0de4 | 93 | int ev_offset; /* offset of saved evs from prev sp */ |
7a78ae4e ND |
94 | int lr_offset; /* offset of saved lr */ |
95 | int cr_offset; /* offset of saved cr */ | |
6be8bc0c | 96 | int vrsave_offset; /* offset of saved vrsave register */ |
7a78ae4e ND |
97 | }; |
98 | ||
99 | /* Description of a single register. */ | |
100 | ||
101 | struct reg | |
102 | { | |
103 | char *name; /* name of register */ | |
0bcc32ae JB |
104 | unsigned char sz32; /* size on 32-bit arch, 0 if nonexistent */ |
105 | unsigned char sz64; /* size on 64-bit arch, 0 if nonexistent */ | |
7a78ae4e | 106 | unsigned char fpr; /* whether register is floating-point */ |
489461e2 | 107 | unsigned char pseudo; /* whether register is pseudo */ |
13ac140c JB |
108 | int spr_num; /* PowerPC SPR number, or -1 if not an SPR. |
109 | This is an ISA SPR number, not a GDB | |
110 | register number. */ | |
7a78ae4e ND |
111 | }; |
112 | ||
c906108c SS |
113 | /* Breakpoint shadows for the single step instructions will be kept here. */ |
114 | ||
c5aa993b | 115 | static struct sstep_breaks |
50fd1280 AC |
116 | { |
117 | /* Address, or 0 if this is not in use. */ | |
118 | CORE_ADDR address; | |
119 | /* Shadow contents. */ | |
120 | gdb_byte data[4]; | |
121 | } | |
c5aa993b | 122 | stepBreaks[2]; |
c906108c SS |
123 | |
124 | /* Hook for determining the TOC address when calling functions in the | |
125 | inferior under AIX. The initialization code in rs6000-nat.c sets | |
126 | this hook to point to find_toc_address. */ | |
127 | ||
7a78ae4e ND |
128 | CORE_ADDR (*rs6000_find_toc_address_hook) (CORE_ADDR) = NULL; |
129 | ||
130 | /* Hook to set the current architecture when starting a child process. | |
131 | rs6000-nat.c sets this. */ | |
132 | ||
133 | void (*rs6000_set_host_arch_hook) (int) = NULL; | |
c906108c SS |
134 | |
135 | /* Static function prototypes */ | |
136 | ||
a14ed312 KB |
137 | static CORE_ADDR branch_dest (int opcode, int instr, CORE_ADDR pc, |
138 | CORE_ADDR safety); | |
077276e8 KB |
139 | static CORE_ADDR skip_prologue (CORE_ADDR, CORE_ADDR, |
140 | struct rs6000_framedata *); | |
c906108c | 141 | |
64b84175 KB |
142 | /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */ |
143 | int | |
144 | altivec_register_p (int regno) | |
145 | { | |
146 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
147 | if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0) | |
148 | return 0; | |
149 | else | |
150 | return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum); | |
151 | } | |
152 | ||
383f0f5b | 153 | |
867e2dc5 JB |
154 | /* Return true if REGNO is an SPE register, false otherwise. */ |
155 | int | |
156 | spe_register_p (int regno) | |
157 | { | |
158 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
159 | ||
160 | /* Is it a reference to EV0 -- EV31, and do we have those? */ | |
161 | if (tdep->ppc_ev0_regnum >= 0 | |
162 | && tdep->ppc_ev31_regnum >= 0 | |
163 | && tdep->ppc_ev0_regnum <= regno && regno <= tdep->ppc_ev31_regnum) | |
164 | return 1; | |
165 | ||
6ced10dd JB |
166 | /* Is it a reference to one of the raw upper GPR halves? */ |
167 | if (tdep->ppc_ev0_upper_regnum >= 0 | |
168 | && tdep->ppc_ev0_upper_regnum <= regno | |
169 | && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) | |
170 | return 1; | |
171 | ||
867e2dc5 JB |
172 | /* Is it a reference to the 64-bit accumulator, and do we have that? */ |
173 | if (tdep->ppc_acc_regnum >= 0 | |
174 | && tdep->ppc_acc_regnum == regno) | |
175 | return 1; | |
176 | ||
177 | /* Is it a reference to the SPE floating-point status and control register, | |
178 | and do we have that? */ | |
179 | if (tdep->ppc_spefscr_regnum >= 0 | |
180 | && tdep->ppc_spefscr_regnum == regno) | |
181 | return 1; | |
182 | ||
183 | return 0; | |
184 | } | |
185 | ||
186 | ||
383f0f5b JB |
187 | /* Return non-zero if the architecture described by GDBARCH has |
188 | floating-point registers (f0 --- f31 and fpscr). */ | |
0a613259 AC |
189 | int |
190 | ppc_floating_point_unit_p (struct gdbarch *gdbarch) | |
191 | { | |
383f0f5b JB |
192 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
193 | ||
194 | return (tdep->ppc_fp0_regnum >= 0 | |
195 | && tdep->ppc_fpscr_regnum >= 0); | |
0a613259 | 196 | } |
9f643768 | 197 | |
09991fa0 JB |
198 | |
199 | /* Check that TABLE[GDB_REGNO] is not already initialized, and then | |
200 | set it to SIM_REGNO. | |
201 | ||
202 | This is a helper function for init_sim_regno_table, constructing | |
203 | the table mapping GDB register numbers to sim register numbers; we | |
204 | initialize every element in that table to -1 before we start | |
205 | filling it in. */ | |
9f643768 JB |
206 | static void |
207 | set_sim_regno (int *table, int gdb_regno, int sim_regno) | |
208 | { | |
209 | /* Make sure we don't try to assign any given GDB register a sim | |
210 | register number more than once. */ | |
211 | gdb_assert (table[gdb_regno] == -1); | |
212 | table[gdb_regno] = sim_regno; | |
213 | } | |
214 | ||
09991fa0 JB |
215 | |
216 | /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register | |
217 | numbers to simulator register numbers, based on the values placed | |
218 | in the ARCH->tdep->ppc_foo_regnum members. */ | |
9f643768 JB |
219 | static void |
220 | init_sim_regno_table (struct gdbarch *arch) | |
221 | { | |
222 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); | |
223 | int total_regs = gdbarch_num_regs (arch) + gdbarch_num_pseudo_regs (arch); | |
224 | const struct reg *regs = tdep->regs; | |
225 | int *sim_regno = GDBARCH_OBSTACK_CALLOC (arch, total_regs, int); | |
226 | int i; | |
227 | ||
228 | /* Presume that all registers not explicitly mentioned below are | |
229 | unavailable from the sim. */ | |
230 | for (i = 0; i < total_regs; i++) | |
231 | sim_regno[i] = -1; | |
232 | ||
233 | /* General-purpose registers. */ | |
234 | for (i = 0; i < ppc_num_gprs; i++) | |
235 | set_sim_regno (sim_regno, tdep->ppc_gp0_regnum + i, sim_ppc_r0_regnum + i); | |
236 | ||
237 | /* Floating-point registers. */ | |
238 | if (tdep->ppc_fp0_regnum >= 0) | |
239 | for (i = 0; i < ppc_num_fprs; i++) | |
240 | set_sim_regno (sim_regno, | |
241 | tdep->ppc_fp0_regnum + i, | |
242 | sim_ppc_f0_regnum + i); | |
243 | if (tdep->ppc_fpscr_regnum >= 0) | |
244 | set_sim_regno (sim_regno, tdep->ppc_fpscr_regnum, sim_ppc_fpscr_regnum); | |
245 | ||
246 | set_sim_regno (sim_regno, gdbarch_pc_regnum (arch), sim_ppc_pc_regnum); | |
247 | set_sim_regno (sim_regno, tdep->ppc_ps_regnum, sim_ppc_ps_regnum); | |
248 | set_sim_regno (sim_regno, tdep->ppc_cr_regnum, sim_ppc_cr_regnum); | |
249 | ||
250 | /* Segment registers. */ | |
251 | if (tdep->ppc_sr0_regnum >= 0) | |
252 | for (i = 0; i < ppc_num_srs; i++) | |
253 | set_sim_regno (sim_regno, | |
254 | tdep->ppc_sr0_regnum + i, | |
255 | sim_ppc_sr0_regnum + i); | |
256 | ||
257 | /* Altivec registers. */ | |
258 | if (tdep->ppc_vr0_regnum >= 0) | |
259 | { | |
260 | for (i = 0; i < ppc_num_vrs; i++) | |
261 | set_sim_regno (sim_regno, | |
262 | tdep->ppc_vr0_regnum + i, | |
263 | sim_ppc_vr0_regnum + i); | |
264 | ||
265 | /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum, | |
266 | we can treat this more like the other cases. */ | |
267 | set_sim_regno (sim_regno, | |
268 | tdep->ppc_vr0_regnum + ppc_num_vrs, | |
269 | sim_ppc_vscr_regnum); | |
270 | } | |
271 | /* vsave is a special-purpose register, so the code below handles it. */ | |
272 | ||
273 | /* SPE APU (E500) registers. */ | |
274 | if (tdep->ppc_ev0_regnum >= 0) | |
275 | for (i = 0; i < ppc_num_gprs; i++) | |
276 | set_sim_regno (sim_regno, | |
277 | tdep->ppc_ev0_regnum + i, | |
278 | sim_ppc_ev0_regnum + i); | |
6ced10dd JB |
279 | if (tdep->ppc_ev0_upper_regnum >= 0) |
280 | for (i = 0; i < ppc_num_gprs; i++) | |
281 | set_sim_regno (sim_regno, | |
282 | tdep->ppc_ev0_upper_regnum + i, | |
283 | sim_ppc_rh0_regnum + i); | |
9f643768 JB |
284 | if (tdep->ppc_acc_regnum >= 0) |
285 | set_sim_regno (sim_regno, tdep->ppc_acc_regnum, sim_ppc_acc_regnum); | |
286 | /* spefscr is a special-purpose register, so the code below handles it. */ | |
287 | ||
288 | /* Now handle all special-purpose registers. Verify that they | |
289 | haven't mistakenly been assigned numbers by any of the above | |
290 | code). */ | |
291 | for (i = 0; i < total_regs; i++) | |
292 | if (regs[i].spr_num >= 0) | |
293 | set_sim_regno (sim_regno, i, regs[i].spr_num + sim_ppc_spr0_regnum); | |
294 | ||
295 | /* Drop the initialized array into place. */ | |
296 | tdep->sim_regno = sim_regno; | |
297 | } | |
298 | ||
09991fa0 JB |
299 | |
300 | /* Given a GDB register number REG, return the corresponding SIM | |
301 | register number. */ | |
9f643768 JB |
302 | static int |
303 | rs6000_register_sim_regno (int reg) | |
304 | { | |
305 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
306 | int sim_regno; | |
307 | ||
308 | gdb_assert (0 <= reg && reg <= NUM_REGS + NUM_PSEUDO_REGS); | |
309 | sim_regno = tdep->sim_regno[reg]; | |
310 | ||
311 | if (sim_regno >= 0) | |
312 | return sim_regno; | |
313 | else | |
314 | return LEGACY_SIM_REGNO_IGNORE; | |
315 | } | |
316 | ||
d195bc9f MK |
317 | \f |
318 | ||
319 | /* Register set support functions. */ | |
320 | ||
321 | static void | |
322 | ppc_supply_reg (struct regcache *regcache, int regnum, | |
50fd1280 | 323 | const gdb_byte *regs, size_t offset) |
d195bc9f MK |
324 | { |
325 | if (regnum != -1 && offset != -1) | |
326 | regcache_raw_supply (regcache, regnum, regs + offset); | |
327 | } | |
328 | ||
329 | static void | |
330 | ppc_collect_reg (const struct regcache *regcache, int regnum, | |
50fd1280 | 331 | gdb_byte *regs, size_t offset) |
d195bc9f MK |
332 | { |
333 | if (regnum != -1 && offset != -1) | |
334 | regcache_raw_collect (regcache, regnum, regs + offset); | |
335 | } | |
336 | ||
337 | /* Supply register REGNUM in the general-purpose register set REGSET | |
338 | from the buffer specified by GREGS and LEN to register cache | |
339 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
340 | ||
341 | void | |
342 | ppc_supply_gregset (const struct regset *regset, struct regcache *regcache, | |
343 | int regnum, const void *gregs, size_t len) | |
344 | { | |
345 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
346 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
347 | const struct ppc_reg_offsets *offsets = regset->descr; | |
348 | size_t offset; | |
349 | int i; | |
350 | ||
cdf2c5f5 | 351 | for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset; |
063715bf | 352 | i < tdep->ppc_gp0_regnum + ppc_num_gprs; |
cdf2c5f5 | 353 | i++, offset += 4) |
d195bc9f MK |
354 | { |
355 | if (regnum == -1 || regnum == i) | |
356 | ppc_supply_reg (regcache, i, gregs, offset); | |
357 | } | |
358 | ||
359 | if (regnum == -1 || regnum == PC_REGNUM) | |
360 | ppc_supply_reg (regcache, PC_REGNUM, gregs, offsets->pc_offset); | |
361 | if (regnum == -1 || regnum == tdep->ppc_ps_regnum) | |
362 | ppc_supply_reg (regcache, tdep->ppc_ps_regnum, | |
363 | gregs, offsets->ps_offset); | |
364 | if (regnum == -1 || regnum == tdep->ppc_cr_regnum) | |
365 | ppc_supply_reg (regcache, tdep->ppc_cr_regnum, | |
366 | gregs, offsets->cr_offset); | |
367 | if (regnum == -1 || regnum == tdep->ppc_lr_regnum) | |
368 | ppc_supply_reg (regcache, tdep->ppc_lr_regnum, | |
369 | gregs, offsets->lr_offset); | |
370 | if (regnum == -1 || regnum == tdep->ppc_ctr_regnum) | |
371 | ppc_supply_reg (regcache, tdep->ppc_ctr_regnum, | |
372 | gregs, offsets->ctr_offset); | |
373 | if (regnum == -1 || regnum == tdep->ppc_xer_regnum) | |
374 | ppc_supply_reg (regcache, tdep->ppc_xer_regnum, | |
375 | gregs, offsets->cr_offset); | |
376 | if (regnum == -1 || regnum == tdep->ppc_mq_regnum) | |
377 | ppc_supply_reg (regcache, tdep->ppc_mq_regnum, gregs, offsets->mq_offset); | |
378 | } | |
379 | ||
380 | /* Supply register REGNUM in the floating-point register set REGSET | |
381 | from the buffer specified by FPREGS and LEN to register cache | |
382 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
383 | ||
384 | void | |
385 | ppc_supply_fpregset (const struct regset *regset, struct regcache *regcache, | |
386 | int regnum, const void *fpregs, size_t len) | |
387 | { | |
388 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
389 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
390 | const struct ppc_reg_offsets *offsets = regset->descr; | |
391 | size_t offset; | |
392 | int i; | |
393 | ||
383f0f5b JB |
394 | gdb_assert (ppc_floating_point_unit_p (gdbarch)); |
395 | ||
d195bc9f | 396 | offset = offsets->f0_offset; |
366f009f JB |
397 | for (i = tdep->ppc_fp0_regnum; |
398 | i < tdep->ppc_fp0_regnum + ppc_num_fprs; | |
bdbcb8b4 | 399 | i++, offset += 8) |
d195bc9f MK |
400 | { |
401 | if (regnum == -1 || regnum == i) | |
402 | ppc_supply_reg (regcache, i, fpregs, offset); | |
403 | } | |
404 | ||
405 | if (regnum == -1 || regnum == tdep->ppc_fpscr_regnum) | |
406 | ppc_supply_reg (regcache, tdep->ppc_fpscr_regnum, | |
407 | fpregs, offsets->fpscr_offset); | |
408 | } | |
409 | ||
410 | /* Collect register REGNUM in the general-purpose register set | |
411 | REGSET. from register cache REGCACHE into the buffer specified by | |
412 | GREGS and LEN. If REGNUM is -1, do this for all registers in | |
413 | REGSET. */ | |
414 | ||
415 | void | |
416 | ppc_collect_gregset (const struct regset *regset, | |
417 | const struct regcache *regcache, | |
418 | int regnum, void *gregs, size_t len) | |
419 | { | |
420 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
421 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
422 | const struct ppc_reg_offsets *offsets = regset->descr; | |
423 | size_t offset; | |
424 | int i; | |
425 | ||
426 | offset = offsets->r0_offset; | |
cdf2c5f5 | 427 | for (i = tdep->ppc_gp0_regnum; |
063715bf | 428 | i < tdep->ppc_gp0_regnum + ppc_num_gprs; |
cdf2c5f5 | 429 | i++, offset += 4) |
d195bc9f MK |
430 | { |
431 | if (regnum == -1 || regnum == i) | |
2e56e9c1 | 432 | ppc_collect_reg (regcache, i, gregs, offset); |
d195bc9f MK |
433 | } |
434 | ||
435 | if (regnum == -1 || regnum == PC_REGNUM) | |
436 | ppc_collect_reg (regcache, PC_REGNUM, gregs, offsets->pc_offset); | |
437 | if (regnum == -1 || regnum == tdep->ppc_ps_regnum) | |
438 | ppc_collect_reg (regcache, tdep->ppc_ps_regnum, | |
439 | gregs, offsets->ps_offset); | |
440 | if (regnum == -1 || regnum == tdep->ppc_cr_regnum) | |
441 | ppc_collect_reg (regcache, tdep->ppc_cr_regnum, | |
442 | gregs, offsets->cr_offset); | |
443 | if (regnum == -1 || regnum == tdep->ppc_lr_regnum) | |
444 | ppc_collect_reg (regcache, tdep->ppc_lr_regnum, | |
445 | gregs, offsets->lr_offset); | |
446 | if (regnum == -1 || regnum == tdep->ppc_ctr_regnum) | |
447 | ppc_collect_reg (regcache, tdep->ppc_ctr_regnum, | |
448 | gregs, offsets->ctr_offset); | |
449 | if (regnum == -1 || regnum == tdep->ppc_xer_regnum) | |
450 | ppc_collect_reg (regcache, tdep->ppc_xer_regnum, | |
451 | gregs, offsets->xer_offset); | |
452 | if (regnum == -1 || regnum == tdep->ppc_mq_regnum) | |
453 | ppc_collect_reg (regcache, tdep->ppc_mq_regnum, | |
454 | gregs, offsets->mq_offset); | |
455 | } | |
456 | ||
457 | /* Collect register REGNUM in the floating-point register set | |
458 | REGSET. from register cache REGCACHE into the buffer specified by | |
459 | FPREGS and LEN. If REGNUM is -1, do this for all registers in | |
460 | REGSET. */ | |
461 | ||
462 | void | |
463 | ppc_collect_fpregset (const struct regset *regset, | |
464 | const struct regcache *regcache, | |
465 | int regnum, void *fpregs, size_t len) | |
466 | { | |
467 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
468 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
469 | const struct ppc_reg_offsets *offsets = regset->descr; | |
470 | size_t offset; | |
471 | int i; | |
472 | ||
383f0f5b JB |
473 | gdb_assert (ppc_floating_point_unit_p (gdbarch)); |
474 | ||
d195bc9f | 475 | offset = offsets->f0_offset; |
366f009f JB |
476 | for (i = tdep->ppc_fp0_regnum; |
477 | i <= tdep->ppc_fp0_regnum + ppc_num_fprs; | |
bdbcb8b4 | 478 | i++, offset += 8) |
d195bc9f MK |
479 | { |
480 | if (regnum == -1 || regnum == i) | |
bdbcb8b4 | 481 | ppc_collect_reg (regcache, i, fpregs, offset); |
d195bc9f MK |
482 | } |
483 | ||
484 | if (regnum == -1 || regnum == tdep->ppc_fpscr_regnum) | |
485 | ppc_collect_reg (regcache, tdep->ppc_fpscr_regnum, | |
486 | fpregs, offsets->fpscr_offset); | |
487 | } | |
488 | \f | |
0a613259 | 489 | |
7a78ae4e | 490 | /* Read a LEN-byte address from debugged memory address MEMADDR. */ |
c906108c | 491 | |
7a78ae4e ND |
492 | static CORE_ADDR |
493 | read_memory_addr (CORE_ADDR memaddr, int len) | |
494 | { | |
495 | return read_memory_unsigned_integer (memaddr, len); | |
496 | } | |
c906108c | 497 | |
7a78ae4e ND |
498 | static CORE_ADDR |
499 | rs6000_skip_prologue (CORE_ADDR pc) | |
b83266a0 SS |
500 | { |
501 | struct rs6000_framedata frame; | |
077276e8 | 502 | pc = skip_prologue (pc, 0, &frame); |
b83266a0 SS |
503 | return pc; |
504 | } | |
505 | ||
0d1243d9 PG |
506 | static int |
507 | insn_changes_sp_or_jumps (unsigned long insn) | |
508 | { | |
509 | int opcode = (insn >> 26) & 0x03f; | |
510 | int sd = (insn >> 21) & 0x01f; | |
511 | int a = (insn >> 16) & 0x01f; | |
512 | int subcode = (insn >> 1) & 0x3ff; | |
513 | ||
514 | /* Changes the stack pointer. */ | |
515 | ||
516 | /* NOTE: There are many ways to change the value of a given register. | |
517 | The ways below are those used when the register is R1, the SP, | |
518 | in a funtion's epilogue. */ | |
519 | ||
520 | if (opcode == 31 && subcode == 444 && a == 1) | |
521 | return 1; /* mr R1,Rn */ | |
522 | if (opcode == 14 && sd == 1) | |
523 | return 1; /* addi R1,Rn,simm */ | |
524 | if (opcode == 58 && sd == 1) | |
525 | return 1; /* ld R1,ds(Rn) */ | |
526 | ||
527 | /* Transfers control. */ | |
528 | ||
529 | if (opcode == 18) | |
530 | return 1; /* b */ | |
531 | if (opcode == 16) | |
532 | return 1; /* bc */ | |
533 | if (opcode == 19 && subcode == 16) | |
534 | return 1; /* bclr */ | |
535 | if (opcode == 19 && subcode == 528) | |
536 | return 1; /* bcctr */ | |
537 | ||
538 | return 0; | |
539 | } | |
540 | ||
541 | /* Return true if we are in the function's epilogue, i.e. after the | |
542 | instruction that destroyed the function's stack frame. | |
543 | ||
544 | 1) scan forward from the point of execution: | |
545 | a) If you find an instruction that modifies the stack pointer | |
546 | or transfers control (except a return), execution is not in | |
547 | an epilogue, return. | |
548 | b) Stop scanning if you find a return instruction or reach the | |
549 | end of the function or reach the hard limit for the size of | |
550 | an epilogue. | |
551 | 2) scan backward from the point of execution: | |
552 | a) If you find an instruction that modifies the stack pointer, | |
553 | execution *is* in an epilogue, return. | |
554 | b) Stop scanning if you reach an instruction that transfers | |
555 | control or the beginning of the function or reach the hard | |
556 | limit for the size of an epilogue. */ | |
557 | ||
558 | static int | |
559 | rs6000_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
560 | { | |
561 | bfd_byte insn_buf[PPC_INSN_SIZE]; | |
562 | CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end; | |
563 | unsigned long insn; | |
564 | struct frame_info *curfrm; | |
565 | ||
566 | /* Find the search limits based on function boundaries and hard limit. */ | |
567 | ||
568 | if (!find_pc_partial_function (pc, NULL, &func_start, &func_end)) | |
569 | return 0; | |
570 | ||
571 | epilogue_start = pc - PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE; | |
572 | if (epilogue_start < func_start) epilogue_start = func_start; | |
573 | ||
574 | epilogue_end = pc + PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE; | |
575 | if (epilogue_end > func_end) epilogue_end = func_end; | |
576 | ||
577 | curfrm = get_current_frame (); | |
578 | ||
579 | /* Scan forward until next 'blr'. */ | |
580 | ||
581 | for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += PPC_INSN_SIZE) | |
582 | { | |
583 | if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE)) | |
584 | return 0; | |
585 | insn = extract_signed_integer (insn_buf, PPC_INSN_SIZE); | |
586 | if (insn == 0x4e800020) | |
587 | break; | |
588 | if (insn_changes_sp_or_jumps (insn)) | |
589 | return 0; | |
590 | } | |
591 | ||
592 | /* Scan backward until adjustment to stack pointer (R1). */ | |
593 | ||
594 | for (scan_pc = pc - PPC_INSN_SIZE; | |
595 | scan_pc >= epilogue_start; | |
596 | scan_pc -= PPC_INSN_SIZE) | |
597 | { | |
598 | if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE)) | |
599 | return 0; | |
600 | insn = extract_signed_integer (insn_buf, PPC_INSN_SIZE); | |
601 | if (insn_changes_sp_or_jumps (insn)) | |
602 | return 1; | |
603 | } | |
604 | ||
605 | return 0; | |
606 | } | |
607 | ||
b83266a0 | 608 | |
c906108c SS |
609 | /* Fill in fi->saved_regs */ |
610 | ||
611 | struct frame_extra_info | |
612 | { | |
613 | /* Functions calling alloca() change the value of the stack | |
614 | pointer. We need to use initial stack pointer (which is saved in | |
615 | r31 by gcc) in such cases. If a compiler emits traceback table, | |
616 | then we should use the alloca register specified in traceback | |
617 | table. FIXME. */ | |
c5aa993b | 618 | CORE_ADDR initial_sp; /* initial stack pointer. */ |
c906108c SS |
619 | }; |
620 | ||
143985b7 | 621 | /* Get the ith function argument for the current function. */ |
b9362cc7 | 622 | static CORE_ADDR |
143985b7 AF |
623 | rs6000_fetch_pointer_argument (struct frame_info *frame, int argi, |
624 | struct type *type) | |
625 | { | |
50fd1280 | 626 | return get_frame_register_unsigned (frame, 3 + argi); |
143985b7 AF |
627 | } |
628 | ||
c906108c SS |
629 | /* Calculate the destination of a branch/jump. Return -1 if not a branch. */ |
630 | ||
631 | static CORE_ADDR | |
7a78ae4e | 632 | branch_dest (int opcode, int instr, CORE_ADDR pc, CORE_ADDR safety) |
c906108c SS |
633 | { |
634 | CORE_ADDR dest; | |
635 | int immediate; | |
636 | int absolute; | |
637 | int ext_op; | |
638 | ||
639 | absolute = (int) ((instr >> 1) & 1); | |
640 | ||
c5aa993b JM |
641 | switch (opcode) |
642 | { | |
643 | case 18: | |
644 | immediate = ((instr & ~3) << 6) >> 6; /* br unconditional */ | |
645 | if (absolute) | |
646 | dest = immediate; | |
647 | else | |
648 | dest = pc + immediate; | |
649 | break; | |
650 | ||
651 | case 16: | |
652 | immediate = ((instr & ~3) << 16) >> 16; /* br conditional */ | |
653 | if (absolute) | |
654 | dest = immediate; | |
655 | else | |
656 | dest = pc + immediate; | |
657 | break; | |
658 | ||
659 | case 19: | |
660 | ext_op = (instr >> 1) & 0x3ff; | |
661 | ||
662 | if (ext_op == 16) /* br conditional register */ | |
663 | { | |
2188cbdd | 664 | dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum) & ~3; |
c5aa993b JM |
665 | |
666 | /* If we are about to return from a signal handler, dest is | |
667 | something like 0x3c90. The current frame is a signal handler | |
668 | caller frame, upon completion of the sigreturn system call | |
669 | execution will return to the saved PC in the frame. */ | |
670 | if (dest < TEXT_SEGMENT_BASE) | |
671 | { | |
672 | struct frame_info *fi; | |
673 | ||
674 | fi = get_current_frame (); | |
675 | if (fi != NULL) | |
8b36eed8 | 676 | dest = read_memory_addr (get_frame_base (fi) + SIG_FRAME_PC_OFFSET, |
21283beb | 677 | gdbarch_tdep (current_gdbarch)->wordsize); |
c5aa993b JM |
678 | } |
679 | } | |
680 | ||
681 | else if (ext_op == 528) /* br cond to count reg */ | |
682 | { | |
2188cbdd | 683 | dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_ctr_regnum) & ~3; |
c5aa993b JM |
684 | |
685 | /* If we are about to execute a system call, dest is something | |
686 | like 0x22fc or 0x3b00. Upon completion the system call | |
687 | will return to the address in the link register. */ | |
688 | if (dest < TEXT_SEGMENT_BASE) | |
2188cbdd | 689 | dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum) & ~3; |
c5aa993b JM |
690 | } |
691 | else | |
692 | return -1; | |
693 | break; | |
c906108c | 694 | |
c5aa993b JM |
695 | default: |
696 | return -1; | |
697 | } | |
c906108c SS |
698 | return (dest < TEXT_SEGMENT_BASE) ? safety : dest; |
699 | } | |
700 | ||
701 | ||
702 | /* Sequence of bytes for breakpoint instruction. */ | |
703 | ||
f4f9705a | 704 | const static unsigned char * |
7a78ae4e | 705 | rs6000_breakpoint_from_pc (CORE_ADDR *bp_addr, int *bp_size) |
c906108c | 706 | { |
aaab4dba AC |
707 | static unsigned char big_breakpoint[] = { 0x7d, 0x82, 0x10, 0x08 }; |
708 | static unsigned char little_breakpoint[] = { 0x08, 0x10, 0x82, 0x7d }; | |
c906108c | 709 | *bp_size = 4; |
d7449b42 | 710 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c906108c SS |
711 | return big_breakpoint; |
712 | else | |
713 | return little_breakpoint; | |
714 | } | |
715 | ||
716 | ||
717 | /* AIX does not support PT_STEP. Simulate it. */ | |
718 | ||
719 | void | |
379d08a1 AC |
720 | rs6000_software_single_step (enum target_signal signal, |
721 | int insert_breakpoints_p) | |
c906108c | 722 | { |
7c40d541 KB |
723 | CORE_ADDR dummy; |
724 | int breakp_sz; | |
50fd1280 | 725 | const gdb_byte *breakp = rs6000_breakpoint_from_pc (&dummy, &breakp_sz); |
c906108c SS |
726 | int ii, insn; |
727 | CORE_ADDR loc; | |
728 | CORE_ADDR breaks[2]; | |
729 | int opcode; | |
730 | ||
c5aa993b JM |
731 | if (insert_breakpoints_p) |
732 | { | |
c906108c | 733 | |
c5aa993b | 734 | loc = read_pc (); |
c906108c | 735 | |
c5aa993b | 736 | insn = read_memory_integer (loc, 4); |
c906108c | 737 | |
7c40d541 | 738 | breaks[0] = loc + breakp_sz; |
c5aa993b JM |
739 | opcode = insn >> 26; |
740 | breaks[1] = branch_dest (opcode, insn, loc, breaks[0]); | |
c906108c | 741 | |
c5aa993b JM |
742 | /* Don't put two breakpoints on the same address. */ |
743 | if (breaks[1] == breaks[0]) | |
744 | breaks[1] = -1; | |
c906108c | 745 | |
c5aa993b | 746 | stepBreaks[1].address = 0; |
c906108c | 747 | |
c5aa993b JM |
748 | for (ii = 0; ii < 2; ++ii) |
749 | { | |
c906108c | 750 | |
c5aa993b JM |
751 | /* ignore invalid breakpoint. */ |
752 | if (breaks[ii] == -1) | |
753 | continue; | |
7c40d541 | 754 | target_insert_breakpoint (breaks[ii], stepBreaks[ii].data); |
c5aa993b JM |
755 | stepBreaks[ii].address = breaks[ii]; |
756 | } | |
c906108c | 757 | |
c5aa993b JM |
758 | } |
759 | else | |
760 | { | |
c906108c | 761 | |
c5aa993b JM |
762 | /* remove step breakpoints. */ |
763 | for (ii = 0; ii < 2; ++ii) | |
764 | if (stepBreaks[ii].address != 0) | |
7c40d541 KB |
765 | target_remove_breakpoint (stepBreaks[ii].address, |
766 | stepBreaks[ii].data); | |
c5aa993b | 767 | } |
c906108c | 768 | errno = 0; /* FIXME, don't ignore errors! */ |
c5aa993b | 769 | /* What errors? {read,write}_memory call error(). */ |
c906108c SS |
770 | } |
771 | ||
772 | ||
773 | /* return pc value after skipping a function prologue and also return | |
774 | information about a function frame. | |
775 | ||
776 | in struct rs6000_framedata fdata: | |
c5aa993b JM |
777 | - frameless is TRUE, if function does not have a frame. |
778 | - nosavedpc is TRUE, if function does not save %pc value in its frame. | |
779 | - offset is the initial size of this stack frame --- the amount by | |
780 | which we decrement the sp to allocate the frame. | |
781 | - saved_gpr is the number of the first saved gpr. | |
782 | - saved_fpr is the number of the first saved fpr. | |
6be8bc0c | 783 | - saved_vr is the number of the first saved vr. |
96ff0de4 | 784 | - saved_ev is the number of the first saved ev. |
c5aa993b JM |
785 | - alloca_reg is the number of the register used for alloca() handling. |
786 | Otherwise -1. | |
787 | - gpr_offset is the offset of the first saved gpr from the previous frame. | |
788 | - fpr_offset is the offset of the first saved fpr from the previous frame. | |
6be8bc0c | 789 | - vr_offset is the offset of the first saved vr from the previous frame. |
96ff0de4 | 790 | - ev_offset is the offset of the first saved ev from the previous frame. |
c5aa993b JM |
791 | - lr_offset is the offset of the saved lr |
792 | - cr_offset is the offset of the saved cr | |
6be8bc0c | 793 | - vrsave_offset is the offset of the saved vrsave register |
c5aa993b | 794 | */ |
c906108c SS |
795 | |
796 | #define SIGNED_SHORT(x) \ | |
797 | ((sizeof (short) == 2) \ | |
798 | ? ((int)(short)(x)) \ | |
799 | : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000))) | |
800 | ||
801 | #define GET_SRC_REG(x) (((x) >> 21) & 0x1f) | |
802 | ||
55d05f3b KB |
803 | /* Limit the number of skipped non-prologue instructions, as the examining |
804 | of the prologue is expensive. */ | |
805 | static int max_skip_non_prologue_insns = 10; | |
806 | ||
807 | /* Given PC representing the starting address of a function, and | |
808 | LIM_PC which is the (sloppy) limit to which to scan when looking | |
809 | for a prologue, attempt to further refine this limit by using | |
810 | the line data in the symbol table. If successful, a better guess | |
811 | on where the prologue ends is returned, otherwise the previous | |
812 | value of lim_pc is returned. */ | |
634aa483 AC |
813 | |
814 | /* FIXME: cagney/2004-02-14: This function and logic have largely been | |
815 | superseded by skip_prologue_using_sal. */ | |
816 | ||
55d05f3b KB |
817 | static CORE_ADDR |
818 | refine_prologue_limit (CORE_ADDR pc, CORE_ADDR lim_pc) | |
819 | { | |
820 | struct symtab_and_line prologue_sal; | |
821 | ||
822 | prologue_sal = find_pc_line (pc, 0); | |
823 | if (prologue_sal.line != 0) | |
824 | { | |
825 | int i; | |
826 | CORE_ADDR addr = prologue_sal.end; | |
827 | ||
828 | /* Handle the case in which compiler's optimizer/scheduler | |
829 | has moved instructions into the prologue. We scan ahead | |
830 | in the function looking for address ranges whose corresponding | |
831 | line number is less than or equal to the first one that we | |
832 | found for the function. (It can be less than when the | |
833 | scheduler puts a body instruction before the first prologue | |
834 | instruction.) */ | |
835 | for (i = 2 * max_skip_non_prologue_insns; | |
836 | i > 0 && (lim_pc == 0 || addr < lim_pc); | |
837 | i--) | |
838 | { | |
839 | struct symtab_and_line sal; | |
840 | ||
841 | sal = find_pc_line (addr, 0); | |
842 | if (sal.line == 0) | |
843 | break; | |
844 | if (sal.line <= prologue_sal.line | |
845 | && sal.symtab == prologue_sal.symtab) | |
846 | { | |
847 | prologue_sal = sal; | |
848 | } | |
849 | addr = sal.end; | |
850 | } | |
851 | ||
852 | if (lim_pc == 0 || prologue_sal.end < lim_pc) | |
853 | lim_pc = prologue_sal.end; | |
854 | } | |
855 | return lim_pc; | |
856 | } | |
857 | ||
773df3e5 JB |
858 | /* Return nonzero if the given instruction OP can be part of the prologue |
859 | of a function and saves a parameter on the stack. FRAMEP should be | |
860 | set if one of the previous instructions in the function has set the | |
861 | Frame Pointer. */ | |
862 | ||
863 | static int | |
864 | store_param_on_stack_p (unsigned long op, int framep, int *r0_contains_arg) | |
865 | { | |
866 | /* Move parameters from argument registers to temporary register. */ | |
867 | if ((op & 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */ | |
868 | { | |
869 | /* Rx must be scratch register r0. */ | |
870 | const int rx_regno = (op >> 16) & 31; | |
871 | /* Ry: Only r3 - r10 are used for parameter passing. */ | |
872 | const int ry_regno = GET_SRC_REG (op); | |
873 | ||
874 | if (rx_regno == 0 && ry_regno >= 3 && ry_regno <= 10) | |
875 | { | |
876 | *r0_contains_arg = 1; | |
877 | return 1; | |
878 | } | |
879 | else | |
880 | return 0; | |
881 | } | |
882 | ||
883 | /* Save a General Purpose Register on stack. */ | |
884 | ||
885 | if ((op & 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */ | |
886 | (op & 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */ | |
887 | { | |
888 | /* Rx: Only r3 - r10 are used for parameter passing. */ | |
889 | const int rx_regno = GET_SRC_REG (op); | |
890 | ||
891 | return (rx_regno >= 3 && rx_regno <= 10); | |
892 | } | |
893 | ||
894 | /* Save a General Purpose Register on stack via the Frame Pointer. */ | |
895 | ||
896 | if (framep && | |
897 | ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */ | |
898 | (op & 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */ | |
899 | (op & 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */ | |
900 | { | |
901 | /* Rx: Usually, only r3 - r10 are used for parameter passing. | |
902 | However, the compiler sometimes uses r0 to hold an argument. */ | |
903 | const int rx_regno = GET_SRC_REG (op); | |
904 | ||
905 | return ((rx_regno >= 3 && rx_regno <= 10) | |
906 | || (rx_regno == 0 && *r0_contains_arg)); | |
907 | } | |
908 | ||
909 | if ((op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */ | |
910 | { | |
911 | /* Only f2 - f8 are used for parameter passing. */ | |
912 | const int src_regno = GET_SRC_REG (op); | |
913 | ||
914 | return (src_regno >= 2 && src_regno <= 8); | |
915 | } | |
916 | ||
917 | if (framep && ((op & 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */ | |
918 | { | |
919 | /* Only f2 - f8 are used for parameter passing. */ | |
920 | const int src_regno = GET_SRC_REG (op); | |
921 | ||
922 | return (src_regno >= 2 && src_regno <= 8); | |
923 | } | |
924 | ||
925 | /* Not an insn that saves a parameter on stack. */ | |
926 | return 0; | |
927 | } | |
55d05f3b | 928 | |
7a78ae4e | 929 | static CORE_ADDR |
077276e8 | 930 | skip_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct rs6000_framedata *fdata) |
c906108c SS |
931 | { |
932 | CORE_ADDR orig_pc = pc; | |
55d05f3b | 933 | CORE_ADDR last_prologue_pc = pc; |
6be8bc0c | 934 | CORE_ADDR li_found_pc = 0; |
50fd1280 | 935 | gdb_byte buf[4]; |
c906108c SS |
936 | unsigned long op; |
937 | long offset = 0; | |
6be8bc0c | 938 | long vr_saved_offset = 0; |
482ca3f5 KB |
939 | int lr_reg = -1; |
940 | int cr_reg = -1; | |
6be8bc0c | 941 | int vr_reg = -1; |
96ff0de4 EZ |
942 | int ev_reg = -1; |
943 | long ev_offset = 0; | |
6be8bc0c | 944 | int vrsave_reg = -1; |
c906108c SS |
945 | int reg; |
946 | int framep = 0; | |
947 | int minimal_toc_loaded = 0; | |
ddb20c56 | 948 | int prev_insn_was_prologue_insn = 1; |
55d05f3b | 949 | int num_skip_non_prologue_insns = 0; |
773df3e5 | 950 | int r0_contains_arg = 0; |
96ff0de4 | 951 | const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (current_gdbarch); |
6f99cb26 | 952 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
96ff0de4 | 953 | |
55d05f3b KB |
954 | /* Attempt to find the end of the prologue when no limit is specified. |
955 | Note that refine_prologue_limit() has been written so that it may | |
956 | be used to "refine" the limits of non-zero PC values too, but this | |
957 | is only safe if we 1) trust the line information provided by the | |
958 | compiler and 2) iterate enough to actually find the end of the | |
959 | prologue. | |
960 | ||
961 | It may become a good idea at some point (for both performance and | |
962 | accuracy) to unconditionally call refine_prologue_limit(). But, | |
963 | until we can make a clear determination that this is beneficial, | |
964 | we'll play it safe and only use it to obtain a limit when none | |
965 | has been specified. */ | |
966 | if (lim_pc == 0) | |
967 | lim_pc = refine_prologue_limit (pc, lim_pc); | |
c906108c | 968 | |
ddb20c56 | 969 | memset (fdata, 0, sizeof (struct rs6000_framedata)); |
c906108c SS |
970 | fdata->saved_gpr = -1; |
971 | fdata->saved_fpr = -1; | |
6be8bc0c | 972 | fdata->saved_vr = -1; |
96ff0de4 | 973 | fdata->saved_ev = -1; |
c906108c SS |
974 | fdata->alloca_reg = -1; |
975 | fdata->frameless = 1; | |
976 | fdata->nosavedpc = 1; | |
977 | ||
55d05f3b | 978 | for (;; pc += 4) |
c906108c | 979 | { |
ddb20c56 KB |
980 | /* Sometimes it isn't clear if an instruction is a prologue |
981 | instruction or not. When we encounter one of these ambiguous | |
982 | cases, we'll set prev_insn_was_prologue_insn to 0 (false). | |
983 | Otherwise, we'll assume that it really is a prologue instruction. */ | |
984 | if (prev_insn_was_prologue_insn) | |
985 | last_prologue_pc = pc; | |
55d05f3b KB |
986 | |
987 | /* Stop scanning if we've hit the limit. */ | |
988 | if (lim_pc != 0 && pc >= lim_pc) | |
989 | break; | |
990 | ||
ddb20c56 KB |
991 | prev_insn_was_prologue_insn = 1; |
992 | ||
55d05f3b | 993 | /* Fetch the instruction and convert it to an integer. */ |
ddb20c56 KB |
994 | if (target_read_memory (pc, buf, 4)) |
995 | break; | |
996 | op = extract_signed_integer (buf, 4); | |
c906108c | 997 | |
c5aa993b JM |
998 | if ((op & 0xfc1fffff) == 0x7c0802a6) |
999 | { /* mflr Rx */ | |
43b1ab88 AC |
1000 | /* Since shared library / PIC code, which needs to get its |
1001 | address at runtime, can appear to save more than one link | |
1002 | register vis: | |
1003 | ||
1004 | *INDENT-OFF* | |
1005 | stwu r1,-304(r1) | |
1006 | mflr r3 | |
1007 | bl 0xff570d0 (blrl) | |
1008 | stw r30,296(r1) | |
1009 | mflr r30 | |
1010 | stw r31,300(r1) | |
1011 | stw r3,308(r1); | |
1012 | ... | |
1013 | *INDENT-ON* | |
1014 | ||
1015 | remember just the first one, but skip over additional | |
1016 | ones. */ | |
721d14ba | 1017 | if (lr_reg == -1) |
43b1ab88 | 1018 | lr_reg = (op & 0x03e00000); |
773df3e5 JB |
1019 | if (lr_reg == 0) |
1020 | r0_contains_arg = 0; | |
c5aa993b | 1021 | continue; |
c5aa993b JM |
1022 | } |
1023 | else if ((op & 0xfc1fffff) == 0x7c000026) | |
1024 | { /* mfcr Rx */ | |
98f08d3d | 1025 | cr_reg = (op & 0x03e00000); |
773df3e5 JB |
1026 | if (cr_reg == 0) |
1027 | r0_contains_arg = 0; | |
c5aa993b | 1028 | continue; |
c906108c | 1029 | |
c906108c | 1030 | } |
c5aa993b JM |
1031 | else if ((op & 0xfc1f0000) == 0xd8010000) |
1032 | { /* stfd Rx,NUM(r1) */ | |
1033 | reg = GET_SRC_REG (op); | |
1034 | if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg) | |
1035 | { | |
1036 | fdata->saved_fpr = reg; | |
1037 | fdata->fpr_offset = SIGNED_SHORT (op) + offset; | |
1038 | } | |
1039 | continue; | |
c906108c | 1040 | |
c5aa993b JM |
1041 | } |
1042 | else if (((op & 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */ | |
7a78ae4e ND |
1043 | (((op & 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */ |
1044 | (op & 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */ | |
1045 | (op & 0x03e00000) >= 0x01a00000)) /* rx >= r13 */ | |
c5aa993b JM |
1046 | { |
1047 | ||
1048 | reg = GET_SRC_REG (op); | |
1049 | if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg) | |
1050 | { | |
1051 | fdata->saved_gpr = reg; | |
7a78ae4e | 1052 | if ((op & 0xfc1f0003) == 0xf8010000) |
98f08d3d | 1053 | op &= ~3UL; |
c5aa993b JM |
1054 | fdata->gpr_offset = SIGNED_SHORT (op) + offset; |
1055 | } | |
1056 | continue; | |
c906108c | 1057 | |
ddb20c56 KB |
1058 | } |
1059 | else if ((op & 0xffff0000) == 0x60000000) | |
1060 | { | |
96ff0de4 | 1061 | /* nop */ |
ddb20c56 KB |
1062 | /* Allow nops in the prologue, but do not consider them to |
1063 | be part of the prologue unless followed by other prologue | |
1064 | instructions. */ | |
1065 | prev_insn_was_prologue_insn = 0; | |
1066 | continue; | |
1067 | ||
c906108c | 1068 | } |
c5aa993b JM |
1069 | else if ((op & 0xffff0000) == 0x3c000000) |
1070 | { /* addis 0,0,NUM, used | |
1071 | for >= 32k frames */ | |
1072 | fdata->offset = (op & 0x0000ffff) << 16; | |
1073 | fdata->frameless = 0; | |
773df3e5 | 1074 | r0_contains_arg = 0; |
c5aa993b JM |
1075 | continue; |
1076 | ||
1077 | } | |
1078 | else if ((op & 0xffff0000) == 0x60000000) | |
1079 | { /* ori 0,0,NUM, 2nd ha | |
1080 | lf of >= 32k frames */ | |
1081 | fdata->offset |= (op & 0x0000ffff); | |
1082 | fdata->frameless = 0; | |
773df3e5 | 1083 | r0_contains_arg = 0; |
c5aa993b JM |
1084 | continue; |
1085 | ||
1086 | } | |
be723e22 | 1087 | else if (lr_reg >= 0 && |
98f08d3d KB |
1088 | /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */ |
1089 | (((op & 0xffff0000) == (lr_reg | 0xf8010000)) || | |
1090 | /* stw Rx, NUM(r1) */ | |
1091 | ((op & 0xffff0000) == (lr_reg | 0x90010000)) || | |
1092 | /* stwu Rx, NUM(r1) */ | |
1093 | ((op & 0xffff0000) == (lr_reg | 0x94010000)))) | |
1094 | { /* where Rx == lr */ | |
1095 | fdata->lr_offset = offset; | |
c5aa993b | 1096 | fdata->nosavedpc = 0; |
be723e22 MS |
1097 | /* Invalidate lr_reg, but don't set it to -1. |
1098 | That would mean that it had never been set. */ | |
1099 | lr_reg = -2; | |
98f08d3d KB |
1100 | if ((op & 0xfc000003) == 0xf8000000 || /* std */ |
1101 | (op & 0xfc000000) == 0x90000000) /* stw */ | |
1102 | { | |
1103 | /* Does not update r1, so add displacement to lr_offset. */ | |
1104 | fdata->lr_offset += SIGNED_SHORT (op); | |
1105 | } | |
c5aa993b JM |
1106 | continue; |
1107 | ||
1108 | } | |
be723e22 | 1109 | else if (cr_reg >= 0 && |
98f08d3d KB |
1110 | /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */ |
1111 | (((op & 0xffff0000) == (cr_reg | 0xf8010000)) || | |
1112 | /* stw Rx, NUM(r1) */ | |
1113 | ((op & 0xffff0000) == (cr_reg | 0x90010000)) || | |
1114 | /* stwu Rx, NUM(r1) */ | |
1115 | ((op & 0xffff0000) == (cr_reg | 0x94010000)))) | |
1116 | { /* where Rx == cr */ | |
1117 | fdata->cr_offset = offset; | |
be723e22 MS |
1118 | /* Invalidate cr_reg, but don't set it to -1. |
1119 | That would mean that it had never been set. */ | |
1120 | cr_reg = -2; | |
98f08d3d KB |
1121 | if ((op & 0xfc000003) == 0xf8000000 || |
1122 | (op & 0xfc000000) == 0x90000000) | |
1123 | { | |
1124 | /* Does not update r1, so add displacement to cr_offset. */ | |
1125 | fdata->cr_offset += SIGNED_SHORT (op); | |
1126 | } | |
c5aa993b JM |
1127 | continue; |
1128 | ||
1129 | } | |
721d14ba DJ |
1130 | else if ((op & 0xfe80ffff) == 0x42800005 && lr_reg != -1) |
1131 | { | |
1132 | /* bcl 20,xx,.+4 is used to get the current PC, with or without | |
1133 | prediction bits. If the LR has already been saved, we can | |
1134 | skip it. */ | |
1135 | continue; | |
1136 | } | |
c5aa993b JM |
1137 | else if (op == 0x48000005) |
1138 | { /* bl .+4 used in | |
1139 | -mrelocatable */ | |
1140 | continue; | |
1141 | ||
1142 | } | |
1143 | else if (op == 0x48000004) | |
1144 | { /* b .+4 (xlc) */ | |
1145 | break; | |
1146 | ||
c5aa993b | 1147 | } |
6be8bc0c EZ |
1148 | else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used |
1149 | in V.4 -mminimal-toc */ | |
c5aa993b JM |
1150 | (op & 0xffff0000) == 0x3bde0000) |
1151 | { /* addi 30,30,foo@l */ | |
1152 | continue; | |
c906108c | 1153 | |
c5aa993b JM |
1154 | } |
1155 | else if ((op & 0xfc000001) == 0x48000001) | |
1156 | { /* bl foo, | |
1157 | to save fprs??? */ | |
c906108c | 1158 | |
c5aa993b | 1159 | fdata->frameless = 0; |
6be8bc0c | 1160 | /* Don't skip over the subroutine call if it is not within |
ebd98106 FF |
1161 | the first three instructions of the prologue and either |
1162 | we have no line table information or the line info tells | |
1163 | us that the subroutine call is not part of the line | |
1164 | associated with the prologue. */ | |
c5aa993b | 1165 | if ((pc - orig_pc) > 8) |
ebd98106 FF |
1166 | { |
1167 | struct symtab_and_line prologue_sal = find_pc_line (orig_pc, 0); | |
1168 | struct symtab_and_line this_sal = find_pc_line (pc, 0); | |
1169 | ||
1170 | if ((prologue_sal.line == 0) || (prologue_sal.line != this_sal.line)) | |
1171 | break; | |
1172 | } | |
c5aa993b JM |
1173 | |
1174 | op = read_memory_integer (pc + 4, 4); | |
1175 | ||
6be8bc0c EZ |
1176 | /* At this point, make sure this is not a trampoline |
1177 | function (a function that simply calls another functions, | |
1178 | and nothing else). If the next is not a nop, this branch | |
1179 | was part of the function prologue. */ | |
c5aa993b JM |
1180 | |
1181 | if (op == 0x4def7b82 || op == 0) /* crorc 15, 15, 15 */ | |
1182 | break; /* don't skip over | |
1183 | this branch */ | |
1184 | continue; | |
1185 | ||
c5aa993b | 1186 | } |
98f08d3d KB |
1187 | /* update stack pointer */ |
1188 | else if ((op & 0xfc1f0000) == 0x94010000) | |
1189 | { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */ | |
c5aa993b JM |
1190 | fdata->frameless = 0; |
1191 | fdata->offset = SIGNED_SHORT (op); | |
1192 | offset = fdata->offset; | |
1193 | continue; | |
c5aa993b | 1194 | } |
98f08d3d KB |
1195 | else if ((op & 0xfc1f016a) == 0x7c01016e) |
1196 | { /* stwux rX,r1,rY */ | |
1197 | /* no way to figure out what r1 is going to be */ | |
1198 | fdata->frameless = 0; | |
1199 | offset = fdata->offset; | |
1200 | continue; | |
1201 | } | |
1202 | else if ((op & 0xfc1f0003) == 0xf8010001) | |
1203 | { /* stdu rX,NUM(r1) */ | |
1204 | fdata->frameless = 0; | |
1205 | fdata->offset = SIGNED_SHORT (op & ~3UL); | |
1206 | offset = fdata->offset; | |
1207 | continue; | |
1208 | } | |
1209 | else if ((op & 0xfc1f016a) == 0x7c01016a) | |
1210 | { /* stdux rX,r1,rY */ | |
1211 | /* no way to figure out what r1 is going to be */ | |
c5aa993b JM |
1212 | fdata->frameless = 0; |
1213 | offset = fdata->offset; | |
1214 | continue; | |
c5aa993b | 1215 | } |
98f08d3d KB |
1216 | /* Load up minimal toc pointer */ |
1217 | else if (((op >> 22) == 0x20f || /* l r31,... or l r30,... */ | |
1218 | (op >> 22) == 0x3af) /* ld r31,... or ld r30,... */ | |
c5aa993b | 1219 | && !minimal_toc_loaded) |
98f08d3d | 1220 | { |
c5aa993b JM |
1221 | minimal_toc_loaded = 1; |
1222 | continue; | |
1223 | ||
f6077098 KB |
1224 | /* move parameters from argument registers to local variable |
1225 | registers */ | |
1226 | } | |
1227 | else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */ | |
1228 | (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */ | |
1229 | (((op >> 21) & 31) <= 10) && | |
96ff0de4 | 1230 | ((long) ((op >> 16) & 31) >= fdata->saved_gpr)) /* Rx: local var reg */ |
f6077098 KB |
1231 | { |
1232 | continue; | |
1233 | ||
c5aa993b JM |
1234 | /* store parameters in stack */ |
1235 | } | |
e802b915 | 1236 | /* Move parameters from argument registers to temporary register. */ |
773df3e5 | 1237 | else if (store_param_on_stack_p (op, framep, &r0_contains_arg)) |
e802b915 | 1238 | { |
c5aa993b JM |
1239 | continue; |
1240 | ||
1241 | /* Set up frame pointer */ | |
1242 | } | |
1243 | else if (op == 0x603f0000 /* oril r31, r1, 0x0 */ | |
1244 | || op == 0x7c3f0b78) | |
1245 | { /* mr r31, r1 */ | |
1246 | fdata->frameless = 0; | |
1247 | framep = 1; | |
6f99cb26 | 1248 | fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31); |
c5aa993b JM |
1249 | continue; |
1250 | ||
1251 | /* Another way to set up the frame pointer. */ | |
1252 | } | |
1253 | else if ((op & 0xfc1fffff) == 0x38010000) | |
1254 | { /* addi rX, r1, 0x0 */ | |
1255 | fdata->frameless = 0; | |
1256 | framep = 1; | |
6f99cb26 AC |
1257 | fdata->alloca_reg = (tdep->ppc_gp0_regnum |
1258 | + ((op & ~0x38010000) >> 21)); | |
c5aa993b | 1259 | continue; |
c5aa993b | 1260 | } |
6be8bc0c EZ |
1261 | /* AltiVec related instructions. */ |
1262 | /* Store the vrsave register (spr 256) in another register for | |
1263 | later manipulation, or load a register into the vrsave | |
1264 | register. 2 instructions are used: mfvrsave and | |
1265 | mtvrsave. They are shorthand notation for mfspr Rn, SPR256 | |
1266 | and mtspr SPR256, Rn. */ | |
1267 | /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110 | |
1268 | mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */ | |
1269 | else if ((op & 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */ | |
1270 | { | |
1271 | vrsave_reg = GET_SRC_REG (op); | |
1272 | continue; | |
1273 | } | |
1274 | else if ((op & 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */ | |
1275 | { | |
1276 | continue; | |
1277 | } | |
1278 | /* Store the register where vrsave was saved to onto the stack: | |
1279 | rS is the register where vrsave was stored in a previous | |
1280 | instruction. */ | |
1281 | /* 100100 sssss 00001 dddddddd dddddddd */ | |
1282 | else if ((op & 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */ | |
1283 | { | |
1284 | if (vrsave_reg == GET_SRC_REG (op)) | |
1285 | { | |
1286 | fdata->vrsave_offset = SIGNED_SHORT (op) + offset; | |
1287 | vrsave_reg = -1; | |
1288 | } | |
1289 | continue; | |
1290 | } | |
1291 | /* Compute the new value of vrsave, by modifying the register | |
1292 | where vrsave was saved to. */ | |
1293 | else if (((op & 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */ | |
1294 | || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */ | |
1295 | { | |
1296 | continue; | |
1297 | } | |
1298 | /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first | |
1299 | in a pair of insns to save the vector registers on the | |
1300 | stack. */ | |
1301 | /* 001110 00000 00000 iiii iiii iiii iiii */ | |
96ff0de4 EZ |
1302 | /* 001110 01110 00000 iiii iiii iiii iiii */ |
1303 | else if ((op & 0xffff0000) == 0x38000000 /* li r0, SIMM */ | |
1304 | || (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */ | |
6be8bc0c | 1305 | { |
773df3e5 JB |
1306 | if ((op & 0xffff0000) == 0x38000000) |
1307 | r0_contains_arg = 0; | |
6be8bc0c EZ |
1308 | li_found_pc = pc; |
1309 | vr_saved_offset = SIGNED_SHORT (op); | |
773df3e5 JB |
1310 | |
1311 | /* This insn by itself is not part of the prologue, unless | |
1312 | if part of the pair of insns mentioned above. So do not | |
1313 | record this insn as part of the prologue yet. */ | |
1314 | prev_insn_was_prologue_insn = 0; | |
6be8bc0c EZ |
1315 | } |
1316 | /* Store vector register S at (r31+r0) aligned to 16 bytes. */ | |
1317 | /* 011111 sssss 11111 00000 00111001110 */ | |
1318 | else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */ | |
1319 | { | |
1320 | if (pc == (li_found_pc + 4)) | |
1321 | { | |
1322 | vr_reg = GET_SRC_REG (op); | |
1323 | /* If this is the first vector reg to be saved, or if | |
1324 | it has a lower number than others previously seen, | |
1325 | reupdate the frame info. */ | |
1326 | if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg) | |
1327 | { | |
1328 | fdata->saved_vr = vr_reg; | |
1329 | fdata->vr_offset = vr_saved_offset + offset; | |
1330 | } | |
1331 | vr_saved_offset = -1; | |
1332 | vr_reg = -1; | |
1333 | li_found_pc = 0; | |
1334 | } | |
1335 | } | |
1336 | /* End AltiVec related instructions. */ | |
96ff0de4 EZ |
1337 | |
1338 | /* Start BookE related instructions. */ | |
1339 | /* Store gen register S at (r31+uimm). | |
1340 | Any register less than r13 is volatile, so we don't care. */ | |
1341 | /* 000100 sssss 11111 iiiii 01100100001 */ | |
1342 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
1343 | && (op & 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */ | |
1344 | { | |
1345 | if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */ | |
1346 | { | |
1347 | unsigned int imm; | |
1348 | ev_reg = GET_SRC_REG (op); | |
1349 | imm = (op >> 11) & 0x1f; | |
1350 | ev_offset = imm * 8; | |
1351 | /* If this is the first vector reg to be saved, or if | |
1352 | it has a lower number than others previously seen, | |
1353 | reupdate the frame info. */ | |
1354 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) | |
1355 | { | |
1356 | fdata->saved_ev = ev_reg; | |
1357 | fdata->ev_offset = ev_offset + offset; | |
1358 | } | |
1359 | } | |
1360 | continue; | |
1361 | } | |
1362 | /* Store gen register rS at (r1+rB). */ | |
1363 | /* 000100 sssss 00001 bbbbb 01100100000 */ | |
1364 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
1365 | && (op & 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */ | |
1366 | { | |
1367 | if (pc == (li_found_pc + 4)) | |
1368 | { | |
1369 | ev_reg = GET_SRC_REG (op); | |
1370 | /* If this is the first vector reg to be saved, or if | |
1371 | it has a lower number than others previously seen, | |
1372 | reupdate the frame info. */ | |
1373 | /* We know the contents of rB from the previous instruction. */ | |
1374 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) | |
1375 | { | |
1376 | fdata->saved_ev = ev_reg; | |
1377 | fdata->ev_offset = vr_saved_offset + offset; | |
1378 | } | |
1379 | vr_saved_offset = -1; | |
1380 | ev_reg = -1; | |
1381 | li_found_pc = 0; | |
1382 | } | |
1383 | continue; | |
1384 | } | |
1385 | /* Store gen register r31 at (rA+uimm). */ | |
1386 | /* 000100 11111 aaaaa iiiii 01100100001 */ | |
1387 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
1388 | && (op & 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */ | |
1389 | { | |
1390 | /* Wwe know that the source register is 31 already, but | |
1391 | it can't hurt to compute it. */ | |
1392 | ev_reg = GET_SRC_REG (op); | |
1393 | ev_offset = ((op >> 11) & 0x1f) * 8; | |
1394 | /* If this is the first vector reg to be saved, or if | |
1395 | it has a lower number than others previously seen, | |
1396 | reupdate the frame info. */ | |
1397 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) | |
1398 | { | |
1399 | fdata->saved_ev = ev_reg; | |
1400 | fdata->ev_offset = ev_offset + offset; | |
1401 | } | |
1402 | ||
1403 | continue; | |
1404 | } | |
1405 | /* Store gen register S at (r31+r0). | |
1406 | Store param on stack when offset from SP bigger than 4 bytes. */ | |
1407 | /* 000100 sssss 11111 00000 01100100000 */ | |
1408 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
1409 | && (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */ | |
1410 | { | |
1411 | if (pc == (li_found_pc + 4)) | |
1412 | { | |
1413 | if ((op & 0x03e00000) >= 0x01a00000) | |
1414 | { | |
1415 | ev_reg = GET_SRC_REG (op); | |
1416 | /* If this is the first vector reg to be saved, or if | |
1417 | it has a lower number than others previously seen, | |
1418 | reupdate the frame info. */ | |
1419 | /* We know the contents of r0 from the previous | |
1420 | instruction. */ | |
1421 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) | |
1422 | { | |
1423 | fdata->saved_ev = ev_reg; | |
1424 | fdata->ev_offset = vr_saved_offset + offset; | |
1425 | } | |
1426 | ev_reg = -1; | |
1427 | } | |
1428 | vr_saved_offset = -1; | |
1429 | li_found_pc = 0; | |
1430 | continue; | |
1431 | } | |
1432 | } | |
1433 | /* End BookE related instructions. */ | |
1434 | ||
c5aa993b JM |
1435 | else |
1436 | { | |
55d05f3b KB |
1437 | /* Not a recognized prologue instruction. |
1438 | Handle optimizer code motions into the prologue by continuing | |
1439 | the search if we have no valid frame yet or if the return | |
1440 | address is not yet saved in the frame. */ | |
1441 | if (fdata->frameless == 0 | |
1442 | && (lr_reg == -1 || fdata->nosavedpc == 0)) | |
1443 | break; | |
1444 | ||
1445 | if (op == 0x4e800020 /* blr */ | |
1446 | || op == 0x4e800420) /* bctr */ | |
1447 | /* Do not scan past epilogue in frameless functions or | |
1448 | trampolines. */ | |
1449 | break; | |
1450 | if ((op & 0xf4000000) == 0x40000000) /* bxx */ | |
64366f1c | 1451 | /* Never skip branches. */ |
55d05f3b KB |
1452 | break; |
1453 | ||
1454 | if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns) | |
1455 | /* Do not scan too many insns, scanning insns is expensive with | |
1456 | remote targets. */ | |
1457 | break; | |
1458 | ||
1459 | /* Continue scanning. */ | |
1460 | prev_insn_was_prologue_insn = 0; | |
1461 | continue; | |
c5aa993b | 1462 | } |
c906108c SS |
1463 | } |
1464 | ||
1465 | #if 0 | |
1466 | /* I have problems with skipping over __main() that I need to address | |
1467 | * sometime. Previously, I used to use misc_function_vector which | |
1468 | * didn't work as well as I wanted to be. -MGO */ | |
1469 | ||
1470 | /* If the first thing after skipping a prolog is a branch to a function, | |
1471 | this might be a call to an initializer in main(), introduced by gcc2. | |
64366f1c | 1472 | We'd like to skip over it as well. Fortunately, xlc does some extra |
c906108c | 1473 | work before calling a function right after a prologue, thus we can |
64366f1c | 1474 | single out such gcc2 behaviour. */ |
c906108c | 1475 | |
c906108c | 1476 | |
c5aa993b JM |
1477 | if ((op & 0xfc000001) == 0x48000001) |
1478 | { /* bl foo, an initializer function? */ | |
1479 | op = read_memory_integer (pc + 4, 4); | |
1480 | ||
1481 | if (op == 0x4def7b82) | |
1482 | { /* cror 0xf, 0xf, 0xf (nop) */ | |
c906108c | 1483 | |
64366f1c EZ |
1484 | /* Check and see if we are in main. If so, skip over this |
1485 | initializer function as well. */ | |
c906108c | 1486 | |
c5aa993b | 1487 | tmp = find_pc_misc_function (pc); |
6314a349 AC |
1488 | if (tmp >= 0 |
1489 | && strcmp (misc_function_vector[tmp].name, main_name ()) == 0) | |
c5aa993b JM |
1490 | return pc + 8; |
1491 | } | |
c906108c | 1492 | } |
c906108c | 1493 | #endif /* 0 */ |
c5aa993b JM |
1494 | |
1495 | fdata->offset = -fdata->offset; | |
ddb20c56 | 1496 | return last_prologue_pc; |
c906108c SS |
1497 | } |
1498 | ||
1499 | ||
1500 | /************************************************************************* | |
f6077098 | 1501 | Support for creating pushing a dummy frame into the stack, and popping |
c906108c SS |
1502 | frames, etc. |
1503 | *************************************************************************/ | |
1504 | ||
c906108c | 1505 | |
11269d7e AC |
1506 | /* All the ABI's require 16 byte alignment. */ |
1507 | static CORE_ADDR | |
1508 | rs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
1509 | { | |
1510 | return (addr & -16); | |
1511 | } | |
1512 | ||
7a78ae4e | 1513 | /* Pass the arguments in either registers, or in the stack. In RS/6000, |
c906108c SS |
1514 | the first eight words of the argument list (that might be less than |
1515 | eight parameters if some parameters occupy more than one word) are | |
7a78ae4e | 1516 | passed in r3..r10 registers. float and double parameters are |
64366f1c EZ |
1517 | passed in fpr's, in addition to that. Rest of the parameters if any |
1518 | are passed in user stack. There might be cases in which half of the | |
c906108c SS |
1519 | parameter is copied into registers, the other half is pushed into |
1520 | stack. | |
1521 | ||
7a78ae4e ND |
1522 | Stack must be aligned on 64-bit boundaries when synthesizing |
1523 | function calls. | |
1524 | ||
c906108c SS |
1525 | If the function is returning a structure, then the return address is passed |
1526 | in r3, then the first 7 words of the parameters can be passed in registers, | |
64366f1c | 1527 | starting from r4. */ |
c906108c | 1528 | |
7a78ae4e | 1529 | static CORE_ADDR |
7d9b040b | 1530 | rs6000_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
77b2b6d4 AC |
1531 | struct regcache *regcache, CORE_ADDR bp_addr, |
1532 | int nargs, struct value **args, CORE_ADDR sp, | |
1533 | int struct_return, CORE_ADDR struct_addr) | |
c906108c | 1534 | { |
7a41266b | 1535 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c SS |
1536 | int ii; |
1537 | int len = 0; | |
c5aa993b JM |
1538 | int argno; /* current argument number */ |
1539 | int argbytes; /* current argument byte */ | |
50fd1280 | 1540 | gdb_byte tmp_buffer[50]; |
c5aa993b | 1541 | int f_argno = 0; /* current floating point argno */ |
21283beb | 1542 | int wordsize = gdbarch_tdep (current_gdbarch)->wordsize; |
7d9b040b | 1543 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
c906108c | 1544 | |
ea7c478f | 1545 | struct value *arg = 0; |
c906108c SS |
1546 | struct type *type; |
1547 | ||
1548 | CORE_ADDR saved_sp; | |
1549 | ||
383f0f5b JB |
1550 | /* The calling convention this function implements assumes the |
1551 | processor has floating-point registers. We shouldn't be using it | |
1552 | on PPC variants that lack them. */ | |
1553 | gdb_assert (ppc_floating_point_unit_p (current_gdbarch)); | |
1554 | ||
64366f1c | 1555 | /* The first eight words of ther arguments are passed in registers. |
7a41266b AC |
1556 | Copy them appropriately. */ |
1557 | ii = 0; | |
1558 | ||
1559 | /* If the function is returning a `struct', then the first word | |
1560 | (which will be passed in r3) is used for struct return address. | |
1561 | In that case we should advance one word and start from r4 | |
1562 | register to copy parameters. */ | |
1563 | if (struct_return) | |
1564 | { | |
1565 | regcache_raw_write_unsigned (regcache, tdep->ppc_gp0_regnum + 3, | |
1566 | struct_addr); | |
1567 | ii++; | |
1568 | } | |
c906108c SS |
1569 | |
1570 | /* | |
c5aa993b JM |
1571 | effectively indirect call... gcc does... |
1572 | ||
1573 | return_val example( float, int); | |
1574 | ||
1575 | eabi: | |
1576 | float in fp0, int in r3 | |
1577 | offset of stack on overflow 8/16 | |
1578 | for varargs, must go by type. | |
1579 | power open: | |
1580 | float in r3&r4, int in r5 | |
1581 | offset of stack on overflow different | |
1582 | both: | |
1583 | return in r3 or f0. If no float, must study how gcc emulates floats; | |
1584 | pay attention to arg promotion. | |
1585 | User may have to cast\args to handle promotion correctly | |
1586 | since gdb won't know if prototype supplied or not. | |
1587 | */ | |
c906108c | 1588 | |
c5aa993b JM |
1589 | for (argno = 0, argbytes = 0; argno < nargs && ii < 8; ++ii) |
1590 | { | |
3acba339 | 1591 | int reg_size = register_size (current_gdbarch, ii + 3); |
c5aa993b JM |
1592 | |
1593 | arg = args[argno]; | |
df407dfe | 1594 | type = check_typedef (value_type (arg)); |
c5aa993b JM |
1595 | len = TYPE_LENGTH (type); |
1596 | ||
1597 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
1598 | { | |
1599 | ||
64366f1c | 1600 | /* Floating point arguments are passed in fpr's, as well as gpr's. |
c5aa993b | 1601 | There are 13 fpr's reserved for passing parameters. At this point |
64366f1c | 1602 | there is no way we would run out of them. */ |
c5aa993b | 1603 | |
9f335945 KB |
1604 | gdb_assert (len <= 8); |
1605 | ||
1606 | regcache_cooked_write (regcache, | |
1607 | tdep->ppc_fp0_regnum + 1 + f_argno, | |
0fd88904 | 1608 | value_contents (arg)); |
c5aa993b JM |
1609 | ++f_argno; |
1610 | } | |
1611 | ||
f6077098 | 1612 | if (len > reg_size) |
c5aa993b JM |
1613 | { |
1614 | ||
64366f1c | 1615 | /* Argument takes more than one register. */ |
c5aa993b JM |
1616 | while (argbytes < len) |
1617 | { | |
50fd1280 | 1618 | gdb_byte word[MAX_REGISTER_SIZE]; |
9f335945 KB |
1619 | memset (word, 0, reg_size); |
1620 | memcpy (word, | |
0fd88904 | 1621 | ((char *) value_contents (arg)) + argbytes, |
f6077098 KB |
1622 | (len - argbytes) > reg_size |
1623 | ? reg_size : len - argbytes); | |
9f335945 KB |
1624 | regcache_cooked_write (regcache, |
1625 | tdep->ppc_gp0_regnum + 3 + ii, | |
1626 | word); | |
f6077098 | 1627 | ++ii, argbytes += reg_size; |
c5aa993b JM |
1628 | |
1629 | if (ii >= 8) | |
1630 | goto ran_out_of_registers_for_arguments; | |
1631 | } | |
1632 | argbytes = 0; | |
1633 | --ii; | |
1634 | } | |
1635 | else | |
64366f1c EZ |
1636 | { |
1637 | /* Argument can fit in one register. No problem. */ | |
d7449b42 | 1638 | int adj = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? reg_size - len : 0; |
50fd1280 | 1639 | gdb_byte word[MAX_REGISTER_SIZE]; |
9f335945 KB |
1640 | |
1641 | memset (word, 0, reg_size); | |
0fd88904 | 1642 | memcpy (word, value_contents (arg), len); |
9f335945 | 1643 | regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 3 +ii, word); |
c5aa993b JM |
1644 | } |
1645 | ++argno; | |
c906108c | 1646 | } |
c906108c SS |
1647 | |
1648 | ran_out_of_registers_for_arguments: | |
1649 | ||
7a78ae4e | 1650 | saved_sp = read_sp (); |
cc9836a8 | 1651 | |
64366f1c | 1652 | /* Location for 8 parameters are always reserved. */ |
7a78ae4e | 1653 | sp -= wordsize * 8; |
f6077098 | 1654 | |
64366f1c | 1655 | /* Another six words for back chain, TOC register, link register, etc. */ |
7a78ae4e | 1656 | sp -= wordsize * 6; |
f6077098 | 1657 | |
64366f1c | 1658 | /* Stack pointer must be quadword aligned. */ |
7a78ae4e | 1659 | sp &= -16; |
c906108c | 1660 | |
64366f1c EZ |
1661 | /* If there are more arguments, allocate space for them in |
1662 | the stack, then push them starting from the ninth one. */ | |
c906108c | 1663 | |
c5aa993b JM |
1664 | if ((argno < nargs) || argbytes) |
1665 | { | |
1666 | int space = 0, jj; | |
c906108c | 1667 | |
c5aa993b JM |
1668 | if (argbytes) |
1669 | { | |
1670 | space += ((len - argbytes + 3) & -4); | |
1671 | jj = argno + 1; | |
1672 | } | |
1673 | else | |
1674 | jj = argno; | |
c906108c | 1675 | |
c5aa993b JM |
1676 | for (; jj < nargs; ++jj) |
1677 | { | |
ea7c478f | 1678 | struct value *val = args[jj]; |
df407dfe | 1679 | space += ((TYPE_LENGTH (value_type (val))) + 3) & -4; |
c5aa993b | 1680 | } |
c906108c | 1681 | |
64366f1c | 1682 | /* Add location required for the rest of the parameters. */ |
f6077098 | 1683 | space = (space + 15) & -16; |
c5aa993b | 1684 | sp -= space; |
c906108c | 1685 | |
7aea86e6 AC |
1686 | /* This is another instance we need to be concerned about |
1687 | securing our stack space. If we write anything underneath %sp | |
1688 | (r1), we might conflict with the kernel who thinks he is free | |
1689 | to use this area. So, update %sp first before doing anything | |
1690 | else. */ | |
1691 | ||
1692 | regcache_raw_write_signed (regcache, SP_REGNUM, sp); | |
1693 | ||
64366f1c EZ |
1694 | /* If the last argument copied into the registers didn't fit there |
1695 | completely, push the rest of it into stack. */ | |
c906108c | 1696 | |
c5aa993b JM |
1697 | if (argbytes) |
1698 | { | |
1699 | write_memory (sp + 24 + (ii * 4), | |
50fd1280 | 1700 | value_contents (arg) + argbytes, |
c5aa993b JM |
1701 | len - argbytes); |
1702 | ++argno; | |
1703 | ii += ((len - argbytes + 3) & -4) / 4; | |
1704 | } | |
c906108c | 1705 | |
64366f1c | 1706 | /* Push the rest of the arguments into stack. */ |
c5aa993b JM |
1707 | for (; argno < nargs; ++argno) |
1708 | { | |
c906108c | 1709 | |
c5aa993b | 1710 | arg = args[argno]; |
df407dfe | 1711 | type = check_typedef (value_type (arg)); |
c5aa993b | 1712 | len = TYPE_LENGTH (type); |
c906108c SS |
1713 | |
1714 | ||
64366f1c EZ |
1715 | /* Float types should be passed in fpr's, as well as in the |
1716 | stack. */ | |
c5aa993b JM |
1717 | if (TYPE_CODE (type) == TYPE_CODE_FLT && f_argno < 13) |
1718 | { | |
c906108c | 1719 | |
9f335945 | 1720 | gdb_assert (len <= 8); |
c906108c | 1721 | |
9f335945 KB |
1722 | regcache_cooked_write (regcache, |
1723 | tdep->ppc_fp0_regnum + 1 + f_argno, | |
0fd88904 | 1724 | value_contents (arg)); |
c5aa993b JM |
1725 | ++f_argno; |
1726 | } | |
c906108c | 1727 | |
50fd1280 | 1728 | write_memory (sp + 24 + (ii * 4), value_contents (arg), len); |
c5aa993b JM |
1729 | ii += ((len + 3) & -4) / 4; |
1730 | } | |
c906108c | 1731 | } |
c906108c | 1732 | |
69517000 | 1733 | /* Set the stack pointer. According to the ABI, the SP is meant to |
7aea86e6 AC |
1734 | be set _before_ the corresponding stack space is used. On AIX, |
1735 | this even applies when the target has been completely stopped! | |
1736 | Not doing this can lead to conflicts with the kernel which thinks | |
1737 | that it still has control over this not-yet-allocated stack | |
1738 | region. */ | |
33a7c2fc AC |
1739 | regcache_raw_write_signed (regcache, SP_REGNUM, sp); |
1740 | ||
7aea86e6 | 1741 | /* Set back chain properly. */ |
8ba0209f AM |
1742 | store_unsigned_integer (tmp_buffer, wordsize, saved_sp); |
1743 | write_memory (sp, tmp_buffer, wordsize); | |
7aea86e6 | 1744 | |
e56a0ecc AC |
1745 | /* Point the inferior function call's return address at the dummy's |
1746 | breakpoint. */ | |
1747 | regcache_raw_write_signed (regcache, tdep->ppc_lr_regnum, bp_addr); | |
1748 | ||
794a477a AC |
1749 | /* Set the TOC register, get the value from the objfile reader |
1750 | which, in turn, gets it from the VMAP table. */ | |
1751 | if (rs6000_find_toc_address_hook != NULL) | |
1752 | { | |
1753 | CORE_ADDR tocvalue = (*rs6000_find_toc_address_hook) (func_addr); | |
1754 | regcache_raw_write_signed (regcache, tdep->ppc_toc_regnum, tocvalue); | |
1755 | } | |
1756 | ||
c906108c SS |
1757 | target_store_registers (-1); |
1758 | return sp; | |
1759 | } | |
c906108c | 1760 | |
b9ff3018 AC |
1761 | /* PowerOpen always puts structures in memory. Vectors, which were |
1762 | added later, do get returned in a register though. */ | |
1763 | ||
1764 | static int | |
1765 | rs6000_use_struct_convention (int gcc_p, struct type *value_type) | |
1766 | { | |
1767 | if ((TYPE_LENGTH (value_type) == 16 || TYPE_LENGTH (value_type) == 8) | |
1768 | && TYPE_VECTOR (value_type)) | |
1769 | return 0; | |
1770 | return 1; | |
1771 | } | |
1772 | ||
7a78ae4e | 1773 | static void |
50fd1280 AC |
1774 | rs6000_extract_return_value (struct type *valtype, gdb_byte *regbuf, |
1775 | gdb_byte *valbuf) | |
c906108c SS |
1776 | { |
1777 | int offset = 0; | |
ace1378a | 1778 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c | 1779 | |
383f0f5b JB |
1780 | /* The calling convention this function implements assumes the |
1781 | processor has floating-point registers. We shouldn't be using it | |
1782 | on PPC variants that lack them. */ | |
1783 | gdb_assert (ppc_floating_point_unit_p (current_gdbarch)); | |
1784 | ||
c5aa993b JM |
1785 | if (TYPE_CODE (valtype) == TYPE_CODE_FLT) |
1786 | { | |
c906108c | 1787 | |
c5aa993b JM |
1788 | /* floats and doubles are returned in fpr1. fpr's have a size of 8 bytes. |
1789 | We need to truncate the return value into float size (4 byte) if | |
64366f1c | 1790 | necessary. */ |
c906108c | 1791 | |
65951cd9 | 1792 | convert_typed_floating (®buf[DEPRECATED_REGISTER_BYTE |
366f009f | 1793 | (tdep->ppc_fp0_regnum + 1)], |
65951cd9 JG |
1794 | builtin_type_double, |
1795 | valbuf, | |
1796 | valtype); | |
c5aa993b | 1797 | } |
ace1378a EZ |
1798 | else if (TYPE_CODE (valtype) == TYPE_CODE_ARRAY |
1799 | && TYPE_LENGTH (valtype) == 16 | |
1800 | && TYPE_VECTOR (valtype)) | |
1801 | { | |
62700349 | 1802 | memcpy (valbuf, regbuf + DEPRECATED_REGISTER_BYTE (tdep->ppc_vr0_regnum + 2), |
ace1378a EZ |
1803 | TYPE_LENGTH (valtype)); |
1804 | } | |
c5aa993b JM |
1805 | else |
1806 | { | |
1807 | /* return value is copied starting from r3. */ | |
d7449b42 | 1808 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
3acba339 AC |
1809 | && TYPE_LENGTH (valtype) < register_size (current_gdbarch, 3)) |
1810 | offset = register_size (current_gdbarch, 3) - TYPE_LENGTH (valtype); | |
c5aa993b JM |
1811 | |
1812 | memcpy (valbuf, | |
62700349 | 1813 | regbuf + DEPRECATED_REGISTER_BYTE (3) + offset, |
c906108c | 1814 | TYPE_LENGTH (valtype)); |
c906108c | 1815 | } |
c906108c SS |
1816 | } |
1817 | ||
977adac5 ND |
1818 | /* Return whether handle_inferior_event() should proceed through code |
1819 | starting at PC in function NAME when stepping. | |
1820 | ||
1821 | The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to | |
1822 | handle memory references that are too distant to fit in instructions | |
1823 | generated by the compiler. For example, if 'foo' in the following | |
1824 | instruction: | |
1825 | ||
1826 | lwz r9,foo(r2) | |
1827 | ||
1828 | is greater than 32767, the linker might replace the lwz with a branch to | |
1829 | somewhere in @FIX1 that does the load in 2 instructions and then branches | |
1830 | back to where execution should continue. | |
1831 | ||
1832 | GDB should silently step over @FIX code, just like AIX dbx does. | |
2ec664f5 MS |
1833 | Unfortunately, the linker uses the "b" instruction for the |
1834 | branches, meaning that the link register doesn't get set. | |
1835 | Therefore, GDB's usual step_over_function () mechanism won't work. | |
977adac5 | 1836 | |
2ec664f5 MS |
1837 | Instead, use the IN_SOLIB_RETURN_TRAMPOLINE and |
1838 | SKIP_TRAMPOLINE_CODE hooks in handle_inferior_event() to skip past | |
1839 | @FIX code. */ | |
977adac5 ND |
1840 | |
1841 | int | |
1842 | rs6000_in_solib_return_trampoline (CORE_ADDR pc, char *name) | |
1843 | { | |
1844 | return name && !strncmp (name, "@FIX", 4); | |
1845 | } | |
1846 | ||
1847 | /* Skip code that the user doesn't want to see when stepping: | |
1848 | ||
1849 | 1. Indirect function calls use a piece of trampoline code to do context | |
1850 | switching, i.e. to set the new TOC table. Skip such code if we are on | |
1851 | its first instruction (as when we have single-stepped to here). | |
1852 | ||
1853 | 2. Skip shared library trampoline code (which is different from | |
c906108c | 1854 | indirect function call trampolines). |
977adac5 ND |
1855 | |
1856 | 3. Skip bigtoc fixup code. | |
1857 | ||
c906108c | 1858 | Result is desired PC to step until, or NULL if we are not in |
977adac5 | 1859 | code that should be skipped. */ |
c906108c SS |
1860 | |
1861 | CORE_ADDR | |
7a78ae4e | 1862 | rs6000_skip_trampoline_code (CORE_ADDR pc) |
c906108c | 1863 | { |
52f0bd74 | 1864 | unsigned int ii, op; |
977adac5 | 1865 | int rel; |
c906108c | 1866 | CORE_ADDR solib_target_pc; |
977adac5 | 1867 | struct minimal_symbol *msymbol; |
c906108c | 1868 | |
c5aa993b JM |
1869 | static unsigned trampoline_code[] = |
1870 | { | |
1871 | 0x800b0000, /* l r0,0x0(r11) */ | |
1872 | 0x90410014, /* st r2,0x14(r1) */ | |
1873 | 0x7c0903a6, /* mtctr r0 */ | |
1874 | 0x804b0004, /* l r2,0x4(r11) */ | |
1875 | 0x816b0008, /* l r11,0x8(r11) */ | |
1876 | 0x4e800420, /* bctr */ | |
1877 | 0x4e800020, /* br */ | |
1878 | 0 | |
c906108c SS |
1879 | }; |
1880 | ||
977adac5 ND |
1881 | /* Check for bigtoc fixup code. */ |
1882 | msymbol = lookup_minimal_symbol_by_pc (pc); | |
2ec664f5 MS |
1883 | if (msymbol |
1884 | && rs6000_in_solib_return_trampoline (pc, | |
1885 | DEPRECATED_SYMBOL_NAME (msymbol))) | |
977adac5 ND |
1886 | { |
1887 | /* Double-check that the third instruction from PC is relative "b". */ | |
1888 | op = read_memory_integer (pc + 8, 4); | |
1889 | if ((op & 0xfc000003) == 0x48000000) | |
1890 | { | |
1891 | /* Extract bits 6-29 as a signed 24-bit relative word address and | |
1892 | add it to the containing PC. */ | |
1893 | rel = ((int)(op << 6) >> 6); | |
1894 | return pc + 8 + rel; | |
1895 | } | |
1896 | } | |
1897 | ||
c906108c SS |
1898 | /* If pc is in a shared library trampoline, return its target. */ |
1899 | solib_target_pc = find_solib_trampoline_target (pc); | |
1900 | if (solib_target_pc) | |
1901 | return solib_target_pc; | |
1902 | ||
c5aa993b JM |
1903 | for (ii = 0; trampoline_code[ii]; ++ii) |
1904 | { | |
1905 | op = read_memory_integer (pc + (ii * 4), 4); | |
1906 | if (op != trampoline_code[ii]) | |
1907 | return 0; | |
1908 | } | |
1909 | ii = read_register (11); /* r11 holds destination addr */ | |
21283beb | 1910 | pc = read_memory_addr (ii, gdbarch_tdep (current_gdbarch)->wordsize); /* (r11) value */ |
c906108c SS |
1911 | return pc; |
1912 | } | |
1913 | ||
7a78ae4e | 1914 | /* Return the size of register REG when words are WORDSIZE bytes long. If REG |
64366f1c | 1915 | isn't available with that word size, return 0. */ |
7a78ae4e ND |
1916 | |
1917 | static int | |
1918 | regsize (const struct reg *reg, int wordsize) | |
1919 | { | |
1920 | return wordsize == 8 ? reg->sz64 : reg->sz32; | |
1921 | } | |
1922 | ||
1923 | /* Return the name of register number N, or null if no such register exists | |
64366f1c | 1924 | in the current architecture. */ |
7a78ae4e | 1925 | |
fa88f677 | 1926 | static const char * |
7a78ae4e ND |
1927 | rs6000_register_name (int n) |
1928 | { | |
21283beb | 1929 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
7a78ae4e ND |
1930 | const struct reg *reg = tdep->regs + n; |
1931 | ||
1932 | if (!regsize (reg, tdep->wordsize)) | |
1933 | return NULL; | |
1934 | return reg->name; | |
1935 | } | |
1936 | ||
7a78ae4e ND |
1937 | /* Return the GDB type object for the "standard" data type |
1938 | of data in register N. */ | |
1939 | ||
1940 | static struct type * | |
691d145a | 1941 | rs6000_register_type (struct gdbarch *gdbarch, int n) |
7a78ae4e | 1942 | { |
691d145a | 1943 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7a78ae4e ND |
1944 | const struct reg *reg = tdep->regs + n; |
1945 | ||
1fcc0bb8 EZ |
1946 | if (reg->fpr) |
1947 | return builtin_type_double; | |
1948 | else | |
1949 | { | |
1950 | int size = regsize (reg, tdep->wordsize); | |
1951 | switch (size) | |
1952 | { | |
449a5da4 AC |
1953 | case 0: |
1954 | return builtin_type_int0; | |
1955 | case 4: | |
ed6edd9b | 1956 | return builtin_type_uint32; |
1fcc0bb8 | 1957 | case 8: |
c8001721 EZ |
1958 | if (tdep->ppc_ev0_regnum <= n && n <= tdep->ppc_ev31_regnum) |
1959 | return builtin_type_vec64; | |
1960 | else | |
ed6edd9b | 1961 | return builtin_type_uint64; |
1fcc0bb8 EZ |
1962 | break; |
1963 | case 16: | |
08cf96df | 1964 | return builtin_type_vec128; |
1fcc0bb8 EZ |
1965 | break; |
1966 | default: | |
e2e0b3e5 | 1967 | internal_error (__FILE__, __LINE__, _("Register %d size %d unknown"), |
449a5da4 | 1968 | n, size); |
1fcc0bb8 EZ |
1969 | } |
1970 | } | |
7a78ae4e ND |
1971 | } |
1972 | ||
c44ca51c AC |
1973 | /* Is REGNUM a member of REGGROUP? */ |
1974 | static int | |
1975 | rs6000_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
1976 | struct reggroup *group) | |
1977 | { | |
1978 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1979 | int float_p; | |
1980 | int vector_p; | |
1981 | int general_p; | |
1982 | ||
1983 | if (REGISTER_NAME (regnum) == NULL | |
1984 | || *REGISTER_NAME (regnum) == '\0') | |
1985 | return 0; | |
1986 | if (group == all_reggroup) | |
1987 | return 1; | |
1988 | ||
1989 | float_p = (regnum == tdep->ppc_fpscr_regnum | |
1990 | || (regnum >= tdep->ppc_fp0_regnum | |
1991 | && regnum < tdep->ppc_fp0_regnum + 32)); | |
1992 | if (group == float_reggroup) | |
1993 | return float_p; | |
1994 | ||
826d5376 PG |
1995 | vector_p = ((tdep->ppc_vr0_regnum >= 0 |
1996 | && regnum >= tdep->ppc_vr0_regnum | |
c44ca51c | 1997 | && regnum < tdep->ppc_vr0_regnum + 32) |
826d5376 PG |
1998 | || (tdep->ppc_ev0_regnum >= 0 |
1999 | && regnum >= tdep->ppc_ev0_regnum | |
c44ca51c | 2000 | && regnum < tdep->ppc_ev0_regnum + 32) |
3bf49e1b | 2001 | || regnum == tdep->ppc_vrsave_regnum - 1 /* vscr */ |
c44ca51c AC |
2002 | || regnum == tdep->ppc_vrsave_regnum |
2003 | || regnum == tdep->ppc_acc_regnum | |
2004 | || regnum == tdep->ppc_spefscr_regnum); | |
2005 | if (group == vector_reggroup) | |
2006 | return vector_p; | |
2007 | ||
2008 | /* Note that PS aka MSR isn't included - it's a system register (and | |
2009 | besides, due to GCC's CFI foobar you do not want to restore | |
2010 | it). */ | |
2011 | general_p = ((regnum >= tdep->ppc_gp0_regnum | |
2012 | && regnum < tdep->ppc_gp0_regnum + 32) | |
2013 | || regnum == tdep->ppc_toc_regnum | |
2014 | || regnum == tdep->ppc_cr_regnum | |
2015 | || regnum == tdep->ppc_lr_regnum | |
2016 | || regnum == tdep->ppc_ctr_regnum | |
2017 | || regnum == tdep->ppc_xer_regnum | |
2018 | || regnum == PC_REGNUM); | |
2019 | if (group == general_reggroup) | |
2020 | return general_p; | |
2021 | ||
2022 | if (group == save_reggroup || group == restore_reggroup) | |
2023 | return general_p || vector_p || float_p; | |
2024 | ||
2025 | return 0; | |
2026 | } | |
2027 | ||
691d145a | 2028 | /* The register format for RS/6000 floating point registers is always |
64366f1c | 2029 | double, we need a conversion if the memory format is float. */ |
7a78ae4e ND |
2030 | |
2031 | static int | |
691d145a | 2032 | rs6000_convert_register_p (int regnum, struct type *type) |
7a78ae4e | 2033 | { |
691d145a JB |
2034 | const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum; |
2035 | ||
2036 | return (reg->fpr | |
2037 | && TYPE_CODE (type) == TYPE_CODE_FLT | |
2038 | && TYPE_LENGTH (type) != TYPE_LENGTH (builtin_type_double)); | |
7a78ae4e ND |
2039 | } |
2040 | ||
7a78ae4e | 2041 | static void |
691d145a JB |
2042 | rs6000_register_to_value (struct frame_info *frame, |
2043 | int regnum, | |
2044 | struct type *type, | |
50fd1280 | 2045 | gdb_byte *to) |
7a78ae4e | 2046 | { |
691d145a | 2047 | const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum; |
50fd1280 | 2048 | gdb_byte from[MAX_REGISTER_SIZE]; |
691d145a JB |
2049 | |
2050 | gdb_assert (reg->fpr); | |
2051 | gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT); | |
7a78ae4e | 2052 | |
691d145a JB |
2053 | get_frame_register (frame, regnum, from); |
2054 | convert_typed_floating (from, builtin_type_double, to, type); | |
2055 | } | |
7a292a7a | 2056 | |
7a78ae4e | 2057 | static void |
691d145a JB |
2058 | rs6000_value_to_register (struct frame_info *frame, |
2059 | int regnum, | |
2060 | struct type *type, | |
50fd1280 | 2061 | const gdb_byte *from) |
7a78ae4e | 2062 | { |
691d145a | 2063 | const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum; |
50fd1280 | 2064 | gdb_byte to[MAX_REGISTER_SIZE]; |
691d145a JB |
2065 | |
2066 | gdb_assert (reg->fpr); | |
2067 | gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT); | |
2068 | ||
2069 | convert_typed_floating (from, type, to, builtin_type_double); | |
2070 | put_frame_register (frame, regnum, to); | |
7a78ae4e | 2071 | } |
c906108c | 2072 | |
6ced10dd JB |
2073 | /* Move SPE vector register values between a 64-bit buffer and the two |
2074 | 32-bit raw register halves in a regcache. This function handles | |
2075 | both splitting a 64-bit value into two 32-bit halves, and joining | |
2076 | two halves into a whole 64-bit value, depending on the function | |
2077 | passed as the MOVE argument. | |
2078 | ||
2079 | EV_REG must be the number of an SPE evN vector register --- a | |
2080 | pseudoregister. REGCACHE must be a regcache, and BUFFER must be a | |
2081 | 64-bit buffer. | |
2082 | ||
2083 | Call MOVE once for each 32-bit half of that register, passing | |
2084 | REGCACHE, the number of the raw register corresponding to that | |
2085 | half, and the address of the appropriate half of BUFFER. | |
2086 | ||
2087 | For example, passing 'regcache_raw_read' as the MOVE function will | |
2088 | fill BUFFER with the full 64-bit contents of EV_REG. Or, passing | |
2089 | 'regcache_raw_supply' will supply the contents of BUFFER to the | |
2090 | appropriate pair of raw registers in REGCACHE. | |
2091 | ||
2092 | You may need to cast away some 'const' qualifiers when passing | |
2093 | MOVE, since this function can't tell at compile-time which of | |
2094 | REGCACHE or BUFFER is acting as the source of the data. If C had | |
2095 | co-variant type qualifiers, ... */ | |
2096 | static void | |
2097 | e500_move_ev_register (void (*move) (struct regcache *regcache, | |
50fd1280 | 2098 | int regnum, gdb_byte *buf), |
6ced10dd | 2099 | struct regcache *regcache, int ev_reg, |
50fd1280 | 2100 | gdb_byte *buffer) |
6ced10dd JB |
2101 | { |
2102 | struct gdbarch *arch = get_regcache_arch (regcache); | |
2103 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); | |
2104 | int reg_index; | |
50fd1280 | 2105 | gdb_byte *byte_buffer = buffer; |
6ced10dd JB |
2106 | |
2107 | gdb_assert (tdep->ppc_ev0_regnum <= ev_reg | |
2108 | && ev_reg < tdep->ppc_ev0_regnum + ppc_num_gprs); | |
2109 | ||
2110 | reg_index = ev_reg - tdep->ppc_ev0_regnum; | |
2111 | ||
2112 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
2113 | { | |
2114 | move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer); | |
2115 | move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer + 4); | |
2116 | } | |
2117 | else | |
2118 | { | |
2119 | move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer); | |
2120 | move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer + 4); | |
2121 | } | |
2122 | } | |
2123 | ||
c8001721 EZ |
2124 | static void |
2125 | e500_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
50fd1280 | 2126 | int reg_nr, gdb_byte *buffer) |
c8001721 | 2127 | { |
6ced10dd | 2128 | struct gdbarch *regcache_arch = get_regcache_arch (regcache); |
c8001721 EZ |
2129 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2130 | ||
6ced10dd JB |
2131 | gdb_assert (regcache_arch == gdbarch); |
2132 | ||
2133 | if (tdep->ppc_ev0_regnum <= reg_nr | |
2134 | && reg_nr < tdep->ppc_ev0_regnum + ppc_num_gprs) | |
2135 | e500_move_ev_register (regcache_raw_read, regcache, reg_nr, buffer); | |
2136 | else | |
a44bddec | 2137 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 AC |
2138 | _("e500_pseudo_register_read: " |
2139 | "called on unexpected register '%s' (%d)"), | |
a44bddec | 2140 | gdbarch_register_name (gdbarch, reg_nr), reg_nr); |
c8001721 EZ |
2141 | } |
2142 | ||
2143 | static void | |
2144 | e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
50fd1280 | 2145 | int reg_nr, const gdb_byte *buffer) |
c8001721 | 2146 | { |
6ced10dd | 2147 | struct gdbarch *regcache_arch = get_regcache_arch (regcache); |
c8001721 EZ |
2148 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2149 | ||
6ced10dd JB |
2150 | gdb_assert (regcache_arch == gdbarch); |
2151 | ||
2152 | if (tdep->ppc_ev0_regnum <= reg_nr | |
2153 | && reg_nr < tdep->ppc_ev0_regnum + ppc_num_gprs) | |
50fd1280 | 2154 | e500_move_ev_register ((void (*) (struct regcache *, int, gdb_byte *)) |
6ced10dd | 2155 | regcache_raw_write, |
50fd1280 | 2156 | regcache, reg_nr, (gdb_byte *) buffer); |
6ced10dd | 2157 | else |
a44bddec | 2158 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 AC |
2159 | _("e500_pseudo_register_read: " |
2160 | "called on unexpected register '%s' (%d)"), | |
a44bddec | 2161 | gdbarch_register_name (gdbarch, reg_nr), reg_nr); |
6ced10dd JB |
2162 | } |
2163 | ||
2164 | /* The E500 needs a custom reggroup function: it has anonymous raw | |
2165 | registers, and default_register_reggroup_p assumes that anonymous | |
2166 | registers are not members of any reggroup. */ | |
2167 | static int | |
2168 | e500_register_reggroup_p (struct gdbarch *gdbarch, | |
2169 | int regnum, | |
2170 | struct reggroup *group) | |
2171 | { | |
2172 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2173 | ||
2174 | /* The save and restore register groups need to include the | |
2175 | upper-half registers, even though they're anonymous. */ | |
2176 | if ((group == save_reggroup | |
2177 | || group == restore_reggroup) | |
2178 | && (tdep->ppc_ev0_upper_regnum <= regnum | |
2179 | && regnum < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)) | |
2180 | return 1; | |
2181 | ||
2182 | /* In all other regards, the default reggroup definition is fine. */ | |
2183 | return default_register_reggroup_p (gdbarch, regnum, group); | |
c8001721 EZ |
2184 | } |
2185 | ||
18ed0c4e | 2186 | /* Convert a DBX STABS register number to a GDB register number. */ |
c8001721 | 2187 | static int |
18ed0c4e | 2188 | rs6000_stab_reg_to_regnum (int num) |
c8001721 | 2189 | { |
9f744501 | 2190 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c8001721 | 2191 | |
9f744501 JB |
2192 | if (0 <= num && num <= 31) |
2193 | return tdep->ppc_gp0_regnum + num; | |
2194 | else if (32 <= num && num <= 63) | |
383f0f5b JB |
2195 | /* FIXME: jimb/2004-05-05: What should we do when the debug info |
2196 | specifies registers the architecture doesn't have? Our | |
2197 | callers don't check the value we return. */ | |
366f009f | 2198 | return tdep->ppc_fp0_regnum + (num - 32); |
18ed0c4e JB |
2199 | else if (77 <= num && num <= 108) |
2200 | return tdep->ppc_vr0_regnum + (num - 77); | |
9f744501 JB |
2201 | else if (1200 <= num && num < 1200 + 32) |
2202 | return tdep->ppc_ev0_regnum + (num - 1200); | |
2203 | else | |
2204 | switch (num) | |
2205 | { | |
2206 | case 64: | |
2207 | return tdep->ppc_mq_regnum; | |
2208 | case 65: | |
2209 | return tdep->ppc_lr_regnum; | |
2210 | case 66: | |
2211 | return tdep->ppc_ctr_regnum; | |
2212 | case 76: | |
2213 | return tdep->ppc_xer_regnum; | |
2214 | case 109: | |
2215 | return tdep->ppc_vrsave_regnum; | |
18ed0c4e JB |
2216 | case 110: |
2217 | return tdep->ppc_vrsave_regnum - 1; /* vscr */ | |
867e2dc5 | 2218 | case 111: |
18ed0c4e | 2219 | return tdep->ppc_acc_regnum; |
867e2dc5 | 2220 | case 112: |
18ed0c4e | 2221 | return tdep->ppc_spefscr_regnum; |
9f744501 JB |
2222 | default: |
2223 | return num; | |
2224 | } | |
18ed0c4e | 2225 | } |
9f744501 | 2226 | |
9f744501 | 2227 | |
18ed0c4e JB |
2228 | /* Convert a Dwarf 2 register number to a GDB register number. */ |
2229 | static int | |
2230 | rs6000_dwarf2_reg_to_regnum (int num) | |
2231 | { | |
2232 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
9f744501 | 2233 | |
18ed0c4e JB |
2234 | if (0 <= num && num <= 31) |
2235 | return tdep->ppc_gp0_regnum + num; | |
2236 | else if (32 <= num && num <= 63) | |
2237 | /* FIXME: jimb/2004-05-05: What should we do when the debug info | |
2238 | specifies registers the architecture doesn't have? Our | |
2239 | callers don't check the value we return. */ | |
2240 | return tdep->ppc_fp0_regnum + (num - 32); | |
2241 | else if (1124 <= num && num < 1124 + 32) | |
2242 | return tdep->ppc_vr0_regnum + (num - 1124); | |
2243 | else if (1200 <= num && num < 1200 + 32) | |
2244 | return tdep->ppc_ev0_regnum + (num - 1200); | |
2245 | else | |
2246 | switch (num) | |
2247 | { | |
2248 | case 67: | |
2249 | return tdep->ppc_vrsave_regnum - 1; /* vscr */ | |
2250 | case 99: | |
2251 | return tdep->ppc_acc_regnum; | |
2252 | case 100: | |
2253 | return tdep->ppc_mq_regnum; | |
2254 | case 101: | |
2255 | return tdep->ppc_xer_regnum; | |
2256 | case 108: | |
2257 | return tdep->ppc_lr_regnum; | |
2258 | case 109: | |
2259 | return tdep->ppc_ctr_regnum; | |
2260 | case 356: | |
2261 | return tdep->ppc_vrsave_regnum; | |
2262 | case 612: | |
2263 | return tdep->ppc_spefscr_regnum; | |
2264 | default: | |
2265 | return num; | |
2266 | } | |
2188cbdd EZ |
2267 | } |
2268 | ||
18ed0c4e | 2269 | |
7a78ae4e | 2270 | static void |
a3c001ce JB |
2271 | rs6000_store_return_value (struct type *type, |
2272 | struct regcache *regcache, | |
50fd1280 | 2273 | const gdb_byte *valbuf) |
7a78ae4e | 2274 | { |
a3c001ce JB |
2275 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
2276 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2277 | int regnum = -1; | |
ace1378a | 2278 | |
383f0f5b JB |
2279 | /* The calling convention this function implements assumes the |
2280 | processor has floating-point registers. We shouldn't be using it | |
2281 | on PPC variants that lack them. */ | |
a3c001ce | 2282 | gdb_assert (ppc_floating_point_unit_p (gdbarch)); |
383f0f5b | 2283 | |
7a78ae4e | 2284 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
7a78ae4e ND |
2285 | /* Floating point values are returned starting from FPR1 and up. |
2286 | Say a double_double_double type could be returned in | |
64366f1c | 2287 | FPR1/FPR2/FPR3 triple. */ |
a3c001ce | 2288 | regnum = tdep->ppc_fp0_regnum + 1; |
ace1378a EZ |
2289 | else if (TYPE_CODE (type) == TYPE_CODE_ARRAY) |
2290 | { | |
2291 | if (TYPE_LENGTH (type) == 16 | |
2292 | && TYPE_VECTOR (type)) | |
a3c001ce JB |
2293 | regnum = tdep->ppc_vr0_regnum + 2; |
2294 | else | |
a44bddec | 2295 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 AC |
2296 | _("rs6000_store_return_value: " |
2297 | "unexpected array return type")); | |
ace1378a | 2298 | } |
7a78ae4e | 2299 | else |
64366f1c | 2300 | /* Everything else is returned in GPR3 and up. */ |
a3c001ce JB |
2301 | regnum = tdep->ppc_gp0_regnum + 3; |
2302 | ||
2303 | { | |
2304 | size_t bytes_written = 0; | |
2305 | ||
2306 | while (bytes_written < TYPE_LENGTH (type)) | |
2307 | { | |
2308 | /* How much of this value can we write to this register? */ | |
2309 | size_t bytes_to_write = min (TYPE_LENGTH (type) - bytes_written, | |
2310 | register_size (gdbarch, regnum)); | |
2311 | regcache_cooked_write_part (regcache, regnum, | |
2312 | 0, bytes_to_write, | |
50fd1280 | 2313 | valbuf + bytes_written); |
a3c001ce JB |
2314 | regnum++; |
2315 | bytes_written += bytes_to_write; | |
2316 | } | |
2317 | } | |
7a78ae4e ND |
2318 | } |
2319 | ||
a3c001ce | 2320 | |
7a78ae4e ND |
2321 | /* Extract from an array REGBUF containing the (raw) register state |
2322 | the address in which a function should return its structure value, | |
2323 | as a CORE_ADDR (or an expression that can be used as one). */ | |
2324 | ||
2325 | static CORE_ADDR | |
11269d7e AC |
2326 | rs6000_extract_struct_value_address (struct regcache *regcache) |
2327 | { | |
2328 | /* FIXME: cagney/2002-09-26: PR gdb/724: When making an inferior | |
2329 | function call GDB knows the address of the struct return value | |
2330 | and hence, should not need to call this function. Unfortunately, | |
e8a8712a AC |
2331 | the current call_function_by_hand() code only saves the most |
2332 | recent struct address leading to occasional calls. The code | |
2333 | should instead maintain a stack of such addresses (in the dummy | |
2334 | frame object). */ | |
11269d7e AC |
2335 | /* NOTE: cagney/2002-09-26: Return 0 which indicates that we've |
2336 | really got no idea where the return value is being stored. While | |
2337 | r3, on function entry, contained the address it will have since | |
2338 | been reused (scratch) and hence wouldn't be valid */ | |
2339 | return 0; | |
7a78ae4e ND |
2340 | } |
2341 | ||
64366f1c | 2342 | /* Hook called when a new child process is started. */ |
7a78ae4e ND |
2343 | |
2344 | void | |
2345 | rs6000_create_inferior (int pid) | |
2346 | { | |
2347 | if (rs6000_set_host_arch_hook) | |
2348 | rs6000_set_host_arch_hook (pid); | |
c906108c SS |
2349 | } |
2350 | \f | |
e2d0e7eb | 2351 | /* Support for CONVERT_FROM_FUNC_PTR_ADDR (ARCH, ADDR, TARG). |
7a78ae4e ND |
2352 | |
2353 | Usually a function pointer's representation is simply the address | |
2354 | of the function. On the RS/6000 however, a function pointer is | |
8ba0209f | 2355 | represented by a pointer to an OPD entry. This OPD entry contains |
7a78ae4e ND |
2356 | three words, the first word is the address of the function, the |
2357 | second word is the TOC pointer (r2), and the third word is the | |
2358 | static chain value. Throughout GDB it is currently assumed that a | |
2359 | function pointer contains the address of the function, which is not | |
2360 | easy to fix. In addition, the conversion of a function address to | |
8ba0209f | 2361 | a function pointer would require allocation of an OPD entry in the |
7a78ae4e ND |
2362 | inferior's memory space, with all its drawbacks. To be able to |
2363 | call C++ virtual methods in the inferior (which are called via | |
f517ea4e | 2364 | function pointers), find_function_addr uses this function to get the |
7a78ae4e ND |
2365 | function address from a function pointer. */ |
2366 | ||
f517ea4e PS |
2367 | /* Return real function address if ADDR (a function pointer) is in the data |
2368 | space and is therefore a special function pointer. */ | |
c906108c | 2369 | |
b9362cc7 | 2370 | static CORE_ADDR |
e2d0e7eb AC |
2371 | rs6000_convert_from_func_ptr_addr (struct gdbarch *gdbarch, |
2372 | CORE_ADDR addr, | |
2373 | struct target_ops *targ) | |
c906108c SS |
2374 | { |
2375 | struct obj_section *s; | |
2376 | ||
2377 | s = find_pc_section (addr); | |
2378 | if (s && s->the_bfd_section->flags & SEC_CODE) | |
7a78ae4e | 2379 | return addr; |
c906108c | 2380 | |
7a78ae4e | 2381 | /* ADDR is in the data space, so it's a special function pointer. */ |
21283beb | 2382 | return read_memory_addr (addr, gdbarch_tdep (current_gdbarch)->wordsize); |
c906108c | 2383 | } |
c906108c | 2384 | \f |
c5aa993b | 2385 | |
7a78ae4e | 2386 | /* Handling the various POWER/PowerPC variants. */ |
c906108c SS |
2387 | |
2388 | ||
7a78ae4e ND |
2389 | /* The arrays here called registers_MUMBLE hold information about available |
2390 | registers. | |
c906108c SS |
2391 | |
2392 | For each family of PPC variants, I've tried to isolate out the | |
2393 | common registers and put them up front, so that as long as you get | |
2394 | the general family right, GDB will correctly identify the registers | |
2395 | common to that family. The common register sets are: | |
2396 | ||
2397 | For the 60x family: hid0 hid1 iabr dabr pir | |
2398 | ||
2399 | For the 505 and 860 family: eie eid nri | |
2400 | ||
2401 | For the 403 and 403GC: icdbdr esr dear evpr cdbcr tsr tcr pit tbhi | |
c5aa993b JM |
2402 | tblo srr2 srr3 dbsr dbcr iac1 iac2 dac1 dac2 dccr iccr pbl1 |
2403 | pbu1 pbl2 pbu2 | |
c906108c SS |
2404 | |
2405 | Most of these register groups aren't anything formal. I arrived at | |
2406 | them by looking at the registers that occurred in more than one | |
6f5987a6 KB |
2407 | processor. |
2408 | ||
2409 | Note: kevinb/2002-04-30: Support for the fpscr register was added | |
2410 | during April, 2002. Slot 70 is being used for PowerPC and slot 71 | |
2411 | for Power. For PowerPC, slot 70 was unused and was already in the | |
2412 | PPC_UISA_SPRS which is ideally where fpscr should go. For Power, | |
2413 | slot 70 was being used for "mq", so the next available slot (71) | |
2414 | was chosen. It would have been nice to be able to make the | |
2415 | register numbers the same across processor cores, but this wasn't | |
2416 | possible without either 1) renumbering some registers for some | |
2417 | processors or 2) assigning fpscr to a really high slot that's | |
2418 | larger than any current register number. Doing (1) is bad because | |
2419 | existing stubs would break. Doing (2) is undesirable because it | |
2420 | would introduce a really large gap between fpscr and the rest of | |
2421 | the registers for most processors. */ | |
7a78ae4e | 2422 | |
64366f1c | 2423 | /* Convenience macros for populating register arrays. */ |
7a78ae4e | 2424 | |
64366f1c | 2425 | /* Within another macro, convert S to a string. */ |
7a78ae4e ND |
2426 | |
2427 | #define STR(s) #s | |
2428 | ||
2429 | /* Return a struct reg defining register NAME that's 32 bits on 32-bit systems | |
64366f1c | 2430 | and 64 bits on 64-bit systems. */ |
13ac140c | 2431 | #define R(name) { STR(name), 4, 8, 0, 0, -1 } |
7a78ae4e ND |
2432 | |
2433 | /* Return a struct reg defining register NAME that's 32 bits on all | |
64366f1c | 2434 | systems. */ |
13ac140c | 2435 | #define R4(name) { STR(name), 4, 4, 0, 0, -1 } |
7a78ae4e ND |
2436 | |
2437 | /* Return a struct reg defining register NAME that's 64 bits on all | |
64366f1c | 2438 | systems. */ |
13ac140c | 2439 | #define R8(name) { STR(name), 8, 8, 0, 0, -1 } |
7a78ae4e | 2440 | |
1fcc0bb8 | 2441 | /* Return a struct reg defining register NAME that's 128 bits on all |
64366f1c | 2442 | systems. */ |
13ac140c | 2443 | #define R16(name) { STR(name), 16, 16, 0, 0, -1 } |
1fcc0bb8 | 2444 | |
64366f1c | 2445 | /* Return a struct reg defining floating-point register NAME. */ |
13ac140c | 2446 | #define F(name) { STR(name), 8, 8, 1, 0, -1 } |
489461e2 | 2447 | |
6ced10dd JB |
2448 | /* Return a struct reg defining a pseudo register NAME that is 64 bits |
2449 | long on all systems. */ | |
2450 | #define P8(name) { STR(name), 8, 8, 0, 1, -1 } | |
7a78ae4e ND |
2451 | |
2452 | /* Return a struct reg defining register NAME that's 32 bits on 32-bit | |
64366f1c | 2453 | systems and that doesn't exist on 64-bit systems. */ |
13ac140c | 2454 | #define R32(name) { STR(name), 4, 0, 0, 0, -1 } |
7a78ae4e ND |
2455 | |
2456 | /* Return a struct reg defining register NAME that's 64 bits on 64-bit | |
64366f1c | 2457 | systems and that doesn't exist on 32-bit systems. */ |
13ac140c | 2458 | #define R64(name) { STR(name), 0, 8, 0, 0, -1 } |
7a78ae4e | 2459 | |
64366f1c | 2460 | /* Return a struct reg placeholder for a register that doesn't exist. */ |
13ac140c | 2461 | #define R0 { 0, 0, 0, 0, 0, -1 } |
7a78ae4e | 2462 | |
6ced10dd JB |
2463 | /* Return a struct reg defining an anonymous raw register that's 32 |
2464 | bits on all systems. */ | |
2465 | #define A4 { 0, 4, 4, 0, 0, -1 } | |
2466 | ||
13ac140c JB |
2467 | /* Return a struct reg defining an SPR named NAME that is 32 bits on |
2468 | 32-bit systems and 64 bits on 64-bit systems. */ | |
2469 | #define S(name) { STR(name), 4, 8, 0, 0, ppc_spr_ ## name } | |
2470 | ||
2471 | /* Return a struct reg defining an SPR named NAME that is 32 bits on | |
2472 | all systems. */ | |
2473 | #define S4(name) { STR(name), 4, 4, 0, 0, ppc_spr_ ## name } | |
2474 | ||
2475 | /* Return a struct reg defining an SPR named NAME that is 32 bits on | |
2476 | all systems, and whose SPR number is NUMBER. */ | |
2477 | #define SN4(name, number) { STR(name), 4, 4, 0, 0, (number) } | |
2478 | ||
2479 | /* Return a struct reg defining an SPR named NAME that's 64 bits on | |
2480 | 64-bit systems and that doesn't exist on 32-bit systems. */ | |
2481 | #define S64(name) { STR(name), 0, 8, 0, 0, ppc_spr_ ## name } | |
2482 | ||
7a78ae4e ND |
2483 | /* UISA registers common across all architectures, including POWER. */ |
2484 | ||
2485 | #define COMMON_UISA_REGS \ | |
2486 | /* 0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), \ | |
2487 | /* 8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \ | |
2488 | /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \ | |
2489 | /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \ | |
2490 | /* 32 */ F(f0), F(f1), F(f2), F(f3), F(f4), F(f5), F(f6), F(f7), \ | |
2491 | /* 40 */ F(f8), F(f9), F(f10),F(f11),F(f12),F(f13),F(f14),F(f15), \ | |
2492 | /* 48 */ F(f16),F(f17),F(f18),F(f19),F(f20),F(f21),F(f22),F(f23), \ | |
2493 | /* 56 */ F(f24),F(f25),F(f26),F(f27),F(f28),F(f29),F(f30),F(f31), \ | |
2494 | /* 64 */ R(pc), R(ps) | |
2495 | ||
2496 | /* UISA-level SPRs for PowerPC. */ | |
2497 | #define PPC_UISA_SPRS \ | |
13ac140c | 2498 | /* 66 */ R4(cr), S(lr), S(ctr), S4(xer), R4(fpscr) |
7a78ae4e | 2499 | |
c8001721 EZ |
2500 | /* UISA-level SPRs for PowerPC without floating point support. */ |
2501 | #define PPC_UISA_NOFP_SPRS \ | |
13ac140c | 2502 | /* 66 */ R4(cr), S(lr), S(ctr), S4(xer), R0 |
c8001721 | 2503 | |
7a78ae4e ND |
2504 | /* Segment registers, for PowerPC. */ |
2505 | #define PPC_SEGMENT_REGS \ | |
2506 | /* 71 */ R32(sr0), R32(sr1), R32(sr2), R32(sr3), \ | |
2507 | /* 75 */ R32(sr4), R32(sr5), R32(sr6), R32(sr7), \ | |
2508 | /* 79 */ R32(sr8), R32(sr9), R32(sr10), R32(sr11), \ | |
2509 | /* 83 */ R32(sr12), R32(sr13), R32(sr14), R32(sr15) | |
2510 | ||
2511 | /* OEA SPRs for PowerPC. */ | |
2512 | #define PPC_OEA_SPRS \ | |
13ac140c JB |
2513 | /* 87 */ S4(pvr), \ |
2514 | /* 88 */ S(ibat0u), S(ibat0l), S(ibat1u), S(ibat1l), \ | |
2515 | /* 92 */ S(ibat2u), S(ibat2l), S(ibat3u), S(ibat3l), \ | |
2516 | /* 96 */ S(dbat0u), S(dbat0l), S(dbat1u), S(dbat1l), \ | |
2517 | /* 100 */ S(dbat2u), S(dbat2l), S(dbat3u), S(dbat3l), \ | |
2518 | /* 104 */ S(sdr1), S64(asr), S(dar), S4(dsisr), \ | |
2519 | /* 108 */ S(sprg0), S(sprg1), S(sprg2), S(sprg3), \ | |
2520 | /* 112 */ S(srr0), S(srr1), S(tbl), S(tbu), \ | |
2521 | /* 116 */ S4(dec), S(dabr), S4(ear) | |
7a78ae4e | 2522 | |
64366f1c | 2523 | /* AltiVec registers. */ |
1fcc0bb8 EZ |
2524 | #define PPC_ALTIVEC_REGS \ |
2525 | /*119*/R16(vr0), R16(vr1), R16(vr2), R16(vr3), R16(vr4), R16(vr5), R16(vr6), R16(vr7), \ | |
2526 | /*127*/R16(vr8), R16(vr9), R16(vr10),R16(vr11),R16(vr12),R16(vr13),R16(vr14),R16(vr15), \ | |
2527 | /*135*/R16(vr16),R16(vr17),R16(vr18),R16(vr19),R16(vr20),R16(vr21),R16(vr22),R16(vr23), \ | |
2528 | /*143*/R16(vr24),R16(vr25),R16(vr26),R16(vr27),R16(vr28),R16(vr29),R16(vr30),R16(vr31), \ | |
2529 | /*151*/R4(vscr), R4(vrsave) | |
2530 | ||
c8001721 | 2531 | |
6ced10dd JB |
2532 | /* On machines supporting the SPE APU, the general-purpose registers |
2533 | are 64 bits long. There are SIMD vector instructions to treat them | |
2534 | as pairs of floats, but the rest of the instruction set treats them | |
2535 | as 32-bit registers, and only operates on their lower halves. | |
2536 | ||
2537 | In the GDB regcache, we treat their high and low halves as separate | |
2538 | registers. The low halves we present as the general-purpose | |
2539 | registers, and then we have pseudo-registers that stitch together | |
2540 | the upper and lower halves and present them as pseudo-registers. */ | |
2541 | ||
2542 | /* SPE GPR lower halves --- raw registers. */ | |
2543 | #define PPC_SPE_GP_REGS \ | |
2544 | /* 0 */ R4(r0), R4(r1), R4(r2), R4(r3), R4(r4), R4(r5), R4(r6), R4(r7), \ | |
2545 | /* 8 */ R4(r8), R4(r9), R4(r10),R4(r11),R4(r12),R4(r13),R4(r14),R4(r15), \ | |
2546 | /* 16 */ R4(r16),R4(r17),R4(r18),R4(r19),R4(r20),R4(r21),R4(r22),R4(r23), \ | |
2547 | /* 24 */ R4(r24),R4(r25),R4(r26),R4(r27),R4(r28),R4(r29),R4(r30),R4(r31) | |
2548 | ||
2549 | /* SPE GPR upper halves --- anonymous raw registers. */ | |
2550 | #define PPC_SPE_UPPER_GP_REGS \ | |
2551 | /* 0 */ A4, A4, A4, A4, A4, A4, A4, A4, \ | |
2552 | /* 8 */ A4, A4, A4, A4, A4, A4, A4, A4, \ | |
2553 | /* 16 */ A4, A4, A4, A4, A4, A4, A4, A4, \ | |
2554 | /* 24 */ A4, A4, A4, A4, A4, A4, A4, A4 | |
2555 | ||
2556 | /* SPE GPR vector registers --- pseudo registers based on underlying | |
2557 | gprs and the anonymous upper half raw registers. */ | |
2558 | #define PPC_EV_PSEUDO_REGS \ | |
2559 | /* 0*/P8(ev0), P8(ev1), P8(ev2), P8(ev3), P8(ev4), P8(ev5), P8(ev6), P8(ev7), \ | |
2560 | /* 8*/P8(ev8), P8(ev9), P8(ev10),P8(ev11),P8(ev12),P8(ev13),P8(ev14),P8(ev15),\ | |
2561 | /*16*/P8(ev16),P8(ev17),P8(ev18),P8(ev19),P8(ev20),P8(ev21),P8(ev22),P8(ev23),\ | |
2562 | /*24*/P8(ev24),P8(ev25),P8(ev26),P8(ev27),P8(ev28),P8(ev29),P8(ev30),P8(ev31) | |
c8001721 | 2563 | |
7a78ae4e | 2564 | /* IBM POWER (pre-PowerPC) architecture, user-level view. We only cover |
64366f1c | 2565 | user-level SPR's. */ |
7a78ae4e | 2566 | static const struct reg registers_power[] = |
c906108c | 2567 | { |
7a78ae4e | 2568 | COMMON_UISA_REGS, |
13ac140c | 2569 | /* 66 */ R4(cnd), S(lr), S(cnt), S4(xer), S4(mq), |
e3f36dbd | 2570 | /* 71 */ R4(fpscr) |
c906108c SS |
2571 | }; |
2572 | ||
7a78ae4e | 2573 | /* PowerPC UISA - a PPC processor as viewed by user-level code. A UISA-only |
64366f1c | 2574 | view of the PowerPC. */ |
7a78ae4e | 2575 | static const struct reg registers_powerpc[] = |
c906108c | 2576 | { |
7a78ae4e | 2577 | COMMON_UISA_REGS, |
1fcc0bb8 EZ |
2578 | PPC_UISA_SPRS, |
2579 | PPC_ALTIVEC_REGS | |
c906108c SS |
2580 | }; |
2581 | ||
13ac140c JB |
2582 | /* IBM PowerPC 403. |
2583 | ||
2584 | Some notes about the "tcr" special-purpose register: | |
2585 | - On the 403 and 403GC, SPR 986 is named "tcr", and it controls the | |
2586 | 403's programmable interval timer, fixed interval timer, and | |
2587 | watchdog timer. | |
2588 | - On the 602, SPR 984 is named "tcr", and it controls the 602's | |
2589 | watchdog timer, and nothing else. | |
2590 | ||
2591 | Some of the fields are similar between the two, but they're not | |
2592 | compatible with each other. Since the two variants have different | |
2593 | registers, with different numbers, but the same name, we can't | |
2594 | splice the register name to get the SPR number. */ | |
7a78ae4e | 2595 | static const struct reg registers_403[] = |
c5aa993b | 2596 | { |
7a78ae4e ND |
2597 | COMMON_UISA_REGS, |
2598 | PPC_UISA_SPRS, | |
2599 | PPC_SEGMENT_REGS, | |
2600 | PPC_OEA_SPRS, | |
13ac140c JB |
2601 | /* 119 */ S(icdbdr), S(esr), S(dear), S(evpr), |
2602 | /* 123 */ S(cdbcr), S(tsr), SN4(tcr, ppc_spr_403_tcr), S(pit), | |
2603 | /* 127 */ S(tbhi), S(tblo), S(srr2), S(srr3), | |
2604 | /* 131 */ S(dbsr), S(dbcr), S(iac1), S(iac2), | |
2605 | /* 135 */ S(dac1), S(dac2), S(dccr), S(iccr), | |
2606 | /* 139 */ S(pbl1), S(pbu1), S(pbl2), S(pbu2) | |
c906108c SS |
2607 | }; |
2608 | ||
13ac140c JB |
2609 | /* IBM PowerPC 403GC. |
2610 | See the comments about 'tcr' for the 403, above. */ | |
7a78ae4e | 2611 | static const struct reg registers_403GC[] = |
c5aa993b | 2612 | { |
7a78ae4e ND |
2613 | COMMON_UISA_REGS, |
2614 | PPC_UISA_SPRS, | |
2615 | PPC_SEGMENT_REGS, | |
2616 | PPC_OEA_SPRS, | |
13ac140c JB |
2617 | /* 119 */ S(icdbdr), S(esr), S(dear), S(evpr), |
2618 | /* 123 */ S(cdbcr), S(tsr), SN4(tcr, ppc_spr_403_tcr), S(pit), | |
2619 | /* 127 */ S(tbhi), S(tblo), S(srr2), S(srr3), | |
2620 | /* 131 */ S(dbsr), S(dbcr), S(iac1), S(iac2), | |
2621 | /* 135 */ S(dac1), S(dac2), S(dccr), S(iccr), | |
2622 | /* 139 */ S(pbl1), S(pbu1), S(pbl2), S(pbu2), | |
2623 | /* 143 */ S(zpr), S(pid), S(sgr), S(dcwr), | |
2624 | /* 147 */ S(tbhu), S(tblu) | |
c906108c SS |
2625 | }; |
2626 | ||
64366f1c | 2627 | /* Motorola PowerPC 505. */ |
7a78ae4e | 2628 | static const struct reg registers_505[] = |
c5aa993b | 2629 | { |
7a78ae4e ND |
2630 | COMMON_UISA_REGS, |
2631 | PPC_UISA_SPRS, | |
2632 | PPC_SEGMENT_REGS, | |
2633 | PPC_OEA_SPRS, | |
13ac140c | 2634 | /* 119 */ S(eie), S(eid), S(nri) |
c906108c SS |
2635 | }; |
2636 | ||
64366f1c | 2637 | /* Motorola PowerPC 860 or 850. */ |
7a78ae4e | 2638 | static const struct reg registers_860[] = |
c5aa993b | 2639 | { |
7a78ae4e ND |
2640 | COMMON_UISA_REGS, |
2641 | PPC_UISA_SPRS, | |
2642 | PPC_SEGMENT_REGS, | |
2643 | PPC_OEA_SPRS, | |
13ac140c JB |
2644 | /* 119 */ S(eie), S(eid), S(nri), S(cmpa), |
2645 | /* 123 */ S(cmpb), S(cmpc), S(cmpd), S(icr), | |
2646 | /* 127 */ S(der), S(counta), S(countb), S(cmpe), | |
2647 | /* 131 */ S(cmpf), S(cmpg), S(cmph), S(lctrl1), | |
2648 | /* 135 */ S(lctrl2), S(ictrl), S(bar), S(ic_cst), | |
2649 | /* 139 */ S(ic_adr), S(ic_dat), S(dc_cst), S(dc_adr), | |
2650 | /* 143 */ S(dc_dat), S(dpdr), S(dpir), S(immr), | |
2651 | /* 147 */ S(mi_ctr), S(mi_ap), S(mi_epn), S(mi_twc), | |
2652 | /* 151 */ S(mi_rpn), S(md_ctr), S(m_casid), S(md_ap), | |
2653 | /* 155 */ S(md_epn), S(m_twb), S(md_twc), S(md_rpn), | |
2654 | /* 159 */ S(m_tw), S(mi_dbcam), S(mi_dbram0), S(mi_dbram1), | |
2655 | /* 163 */ S(md_dbcam), S(md_dbram0), S(md_dbram1) | |
c906108c SS |
2656 | }; |
2657 | ||
7a78ae4e ND |
2658 | /* Motorola PowerPC 601. Note that the 601 has different register numbers |
2659 | for reading and writing RTCU and RTCL. However, how one reads and writes a | |
c906108c | 2660 | register is the stub's problem. */ |
7a78ae4e | 2661 | static const struct reg registers_601[] = |
c5aa993b | 2662 | { |
7a78ae4e ND |
2663 | COMMON_UISA_REGS, |
2664 | PPC_UISA_SPRS, | |
2665 | PPC_SEGMENT_REGS, | |
2666 | PPC_OEA_SPRS, | |
13ac140c JB |
2667 | /* 119 */ S(hid0), S(hid1), S(iabr), S(dabr), |
2668 | /* 123 */ S(pir), S(mq), S(rtcu), S(rtcl) | |
c906108c SS |
2669 | }; |
2670 | ||
13ac140c JB |
2671 | /* Motorola PowerPC 602. |
2672 | See the notes under the 403 about 'tcr'. */ | |
7a78ae4e | 2673 | static const struct reg registers_602[] = |
c5aa993b | 2674 | { |
7a78ae4e ND |
2675 | COMMON_UISA_REGS, |
2676 | PPC_UISA_SPRS, | |
2677 | PPC_SEGMENT_REGS, | |
2678 | PPC_OEA_SPRS, | |
13ac140c JB |
2679 | /* 119 */ S(hid0), S(hid1), S(iabr), R0, |
2680 | /* 123 */ R0, SN4(tcr, ppc_spr_602_tcr), S(ibr), S(esasrr), | |
2681 | /* 127 */ S(sebr), S(ser), S(sp), S(lt) | |
c906108c SS |
2682 | }; |
2683 | ||
64366f1c | 2684 | /* Motorola/IBM PowerPC 603 or 603e. */ |
7a78ae4e | 2685 | static const struct reg registers_603[] = |
c5aa993b | 2686 | { |
7a78ae4e ND |
2687 | COMMON_UISA_REGS, |
2688 | PPC_UISA_SPRS, | |
2689 | PPC_SEGMENT_REGS, | |
2690 | PPC_OEA_SPRS, | |
13ac140c JB |
2691 | /* 119 */ S(hid0), S(hid1), S(iabr), R0, |
2692 | /* 123 */ R0, S(dmiss), S(dcmp), S(hash1), | |
2693 | /* 127 */ S(hash2), S(imiss), S(icmp), S(rpa) | |
c906108c SS |
2694 | }; |
2695 | ||
64366f1c | 2696 | /* Motorola PowerPC 604 or 604e. */ |
7a78ae4e | 2697 | static const struct reg registers_604[] = |
c5aa993b | 2698 | { |
7a78ae4e ND |
2699 | COMMON_UISA_REGS, |
2700 | PPC_UISA_SPRS, | |
2701 | PPC_SEGMENT_REGS, | |
2702 | PPC_OEA_SPRS, | |
13ac140c JB |
2703 | /* 119 */ S(hid0), S(hid1), S(iabr), S(dabr), |
2704 | /* 123 */ S(pir), S(mmcr0), S(pmc1), S(pmc2), | |
2705 | /* 127 */ S(sia), S(sda) | |
c906108c SS |
2706 | }; |
2707 | ||
64366f1c | 2708 | /* Motorola/IBM PowerPC 750 or 740. */ |
7a78ae4e | 2709 | static const struct reg registers_750[] = |
c5aa993b | 2710 | { |
7a78ae4e ND |
2711 | COMMON_UISA_REGS, |
2712 | PPC_UISA_SPRS, | |
2713 | PPC_SEGMENT_REGS, | |
2714 | PPC_OEA_SPRS, | |
13ac140c JB |
2715 | /* 119 */ S(hid0), S(hid1), S(iabr), S(dabr), |
2716 | /* 123 */ R0, S(ummcr0), S(upmc1), S(upmc2), | |
2717 | /* 127 */ S(usia), S(ummcr1), S(upmc3), S(upmc4), | |
2718 | /* 131 */ S(mmcr0), S(pmc1), S(pmc2), S(sia), | |
2719 | /* 135 */ S(mmcr1), S(pmc3), S(pmc4), S(l2cr), | |
2720 | /* 139 */ S(ictc), S(thrm1), S(thrm2), S(thrm3) | |
c906108c SS |
2721 | }; |
2722 | ||
2723 | ||
64366f1c | 2724 | /* Motorola PowerPC 7400. */ |
1fcc0bb8 EZ |
2725 | static const struct reg registers_7400[] = |
2726 | { | |
2727 | /* gpr0-gpr31, fpr0-fpr31 */ | |
2728 | COMMON_UISA_REGS, | |
13c7b1ca | 2729 | /* cr, lr, ctr, xer, fpscr */ |
1fcc0bb8 EZ |
2730 | PPC_UISA_SPRS, |
2731 | /* sr0-sr15 */ | |
2732 | PPC_SEGMENT_REGS, | |
2733 | PPC_OEA_SPRS, | |
2734 | /* vr0-vr31, vrsave, vscr */ | |
2735 | PPC_ALTIVEC_REGS | |
2736 | /* FIXME? Add more registers? */ | |
2737 | }; | |
2738 | ||
c8001721 EZ |
2739 | /* Motorola e500. */ |
2740 | static const struct reg registers_e500[] = | |
2741 | { | |
6ced10dd JB |
2742 | /* 0 .. 31 */ PPC_SPE_GP_REGS, |
2743 | /* 32 .. 63 */ PPC_SPE_UPPER_GP_REGS, | |
2744 | /* 64 .. 65 */ R(pc), R(ps), | |
2745 | /* 66 .. 70 */ PPC_UISA_NOFP_SPRS, | |
2746 | /* 71 .. 72 */ R8(acc), S4(spefscr), | |
338ef23d AC |
2747 | /* NOTE: Add new registers here the end of the raw register |
2748 | list and just before the first pseudo register. */ | |
6ced10dd | 2749 | /* 73 .. 104 */ PPC_EV_PSEUDO_REGS |
c8001721 EZ |
2750 | }; |
2751 | ||
c906108c | 2752 | /* Information about a particular processor variant. */ |
7a78ae4e | 2753 | |
c906108c | 2754 | struct variant |
c5aa993b JM |
2755 | { |
2756 | /* Name of this variant. */ | |
2757 | char *name; | |
c906108c | 2758 | |
c5aa993b JM |
2759 | /* English description of the variant. */ |
2760 | char *description; | |
c906108c | 2761 | |
64366f1c | 2762 | /* bfd_arch_info.arch corresponding to variant. */ |
7a78ae4e ND |
2763 | enum bfd_architecture arch; |
2764 | ||
64366f1c | 2765 | /* bfd_arch_info.mach corresponding to variant. */ |
7a78ae4e ND |
2766 | unsigned long mach; |
2767 | ||
489461e2 EZ |
2768 | /* Number of real registers. */ |
2769 | int nregs; | |
2770 | ||
2771 | /* Number of pseudo registers. */ | |
2772 | int npregs; | |
2773 | ||
2774 | /* Number of total registers (the sum of nregs and npregs). */ | |
2775 | int num_tot_regs; | |
2776 | ||
c5aa993b JM |
2777 | /* Table of register names; registers[R] is the name of the register |
2778 | number R. */ | |
7a78ae4e | 2779 | const struct reg *regs; |
c5aa993b | 2780 | }; |
c906108c | 2781 | |
489461e2 EZ |
2782 | #define tot_num_registers(list) (sizeof (list) / sizeof((list)[0])) |
2783 | ||
2784 | static int | |
2785 | num_registers (const struct reg *reg_list, int num_tot_regs) | |
2786 | { | |
2787 | int i; | |
2788 | int nregs = 0; | |
2789 | ||
2790 | for (i = 0; i < num_tot_regs; i++) | |
2791 | if (!reg_list[i].pseudo) | |
2792 | nregs++; | |
2793 | ||
2794 | return nregs; | |
2795 | } | |
2796 | ||
2797 | static int | |
2798 | num_pseudo_registers (const struct reg *reg_list, int num_tot_regs) | |
2799 | { | |
2800 | int i; | |
2801 | int npregs = 0; | |
2802 | ||
2803 | for (i = 0; i < num_tot_regs; i++) | |
2804 | if (reg_list[i].pseudo) | |
2805 | npregs ++; | |
2806 | ||
2807 | return npregs; | |
2808 | } | |
c906108c | 2809 | |
c906108c SS |
2810 | /* Information in this table comes from the following web sites: |
2811 | IBM: http://www.chips.ibm.com:80/products/embedded/ | |
2812 | Motorola: http://www.mot.com/SPS/PowerPC/ | |
2813 | ||
2814 | I'm sure I've got some of the variant descriptions not quite right. | |
2815 | Please report any inaccuracies you find to GDB's maintainer. | |
2816 | ||
2817 | If you add entries to this table, please be sure to allow the new | |
2818 | value as an argument to the --with-cpu flag, in configure.in. */ | |
2819 | ||
489461e2 | 2820 | static struct variant variants[] = |
c906108c | 2821 | { |
489461e2 | 2822 | |
7a78ae4e | 2823 | {"powerpc", "PowerPC user-level", bfd_arch_powerpc, |
489461e2 EZ |
2824 | bfd_mach_ppc, -1, -1, tot_num_registers (registers_powerpc), |
2825 | registers_powerpc}, | |
7a78ae4e | 2826 | {"power", "POWER user-level", bfd_arch_rs6000, |
489461e2 EZ |
2827 | bfd_mach_rs6k, -1, -1, tot_num_registers (registers_power), |
2828 | registers_power}, | |
7a78ae4e | 2829 | {"403", "IBM PowerPC 403", bfd_arch_powerpc, |
489461e2 EZ |
2830 | bfd_mach_ppc_403, -1, -1, tot_num_registers (registers_403), |
2831 | registers_403}, | |
7a78ae4e | 2832 | {"601", "Motorola PowerPC 601", bfd_arch_powerpc, |
489461e2 EZ |
2833 | bfd_mach_ppc_601, -1, -1, tot_num_registers (registers_601), |
2834 | registers_601}, | |
7a78ae4e | 2835 | {"602", "Motorola PowerPC 602", bfd_arch_powerpc, |
489461e2 EZ |
2836 | bfd_mach_ppc_602, -1, -1, tot_num_registers (registers_602), |
2837 | registers_602}, | |
7a78ae4e | 2838 | {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc, |
489461e2 EZ |
2839 | bfd_mach_ppc_603, -1, -1, tot_num_registers (registers_603), |
2840 | registers_603}, | |
7a78ae4e | 2841 | {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc, |
489461e2 EZ |
2842 | 604, -1, -1, tot_num_registers (registers_604), |
2843 | registers_604}, | |
7a78ae4e | 2844 | {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc, |
489461e2 EZ |
2845 | bfd_mach_ppc_403gc, -1, -1, tot_num_registers (registers_403GC), |
2846 | registers_403GC}, | |
7a78ae4e | 2847 | {"505", "Motorola PowerPC 505", bfd_arch_powerpc, |
489461e2 EZ |
2848 | bfd_mach_ppc_505, -1, -1, tot_num_registers (registers_505), |
2849 | registers_505}, | |
7a78ae4e | 2850 | {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc, |
489461e2 EZ |
2851 | bfd_mach_ppc_860, -1, -1, tot_num_registers (registers_860), |
2852 | registers_860}, | |
7a78ae4e | 2853 | {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc, |
489461e2 EZ |
2854 | bfd_mach_ppc_750, -1, -1, tot_num_registers (registers_750), |
2855 | registers_750}, | |
1fcc0bb8 | 2856 | {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc, |
489461e2 EZ |
2857 | bfd_mach_ppc_7400, -1, -1, tot_num_registers (registers_7400), |
2858 | registers_7400}, | |
c8001721 EZ |
2859 | {"e500", "Motorola PowerPC e500", bfd_arch_powerpc, |
2860 | bfd_mach_ppc_e500, -1, -1, tot_num_registers (registers_e500), | |
2861 | registers_e500}, | |
7a78ae4e | 2862 | |
5d57ee30 KB |
2863 | /* 64-bit */ |
2864 | {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc, | |
489461e2 EZ |
2865 | bfd_mach_ppc64, -1, -1, tot_num_registers (registers_powerpc), |
2866 | registers_powerpc}, | |
7a78ae4e | 2867 | {"620", "Motorola PowerPC 620", bfd_arch_powerpc, |
489461e2 EZ |
2868 | bfd_mach_ppc_620, -1, -1, tot_num_registers (registers_powerpc), |
2869 | registers_powerpc}, | |
5d57ee30 | 2870 | {"630", "Motorola PowerPC 630", bfd_arch_powerpc, |
489461e2 EZ |
2871 | bfd_mach_ppc_630, -1, -1, tot_num_registers (registers_powerpc), |
2872 | registers_powerpc}, | |
7a78ae4e | 2873 | {"a35", "PowerPC A35", bfd_arch_powerpc, |
489461e2 EZ |
2874 | bfd_mach_ppc_a35, -1, -1, tot_num_registers (registers_powerpc), |
2875 | registers_powerpc}, | |
5d57ee30 | 2876 | {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc, |
489461e2 EZ |
2877 | bfd_mach_ppc_rs64ii, -1, -1, tot_num_registers (registers_powerpc), |
2878 | registers_powerpc}, | |
5d57ee30 | 2879 | {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc, |
489461e2 EZ |
2880 | bfd_mach_ppc_rs64iii, -1, -1, tot_num_registers (registers_powerpc), |
2881 | registers_powerpc}, | |
5d57ee30 | 2882 | |
64366f1c | 2883 | /* FIXME: I haven't checked the register sets of the following. */ |
7a78ae4e | 2884 | {"rs1", "IBM POWER RS1", bfd_arch_rs6000, |
489461e2 EZ |
2885 | bfd_mach_rs6k_rs1, -1, -1, tot_num_registers (registers_power), |
2886 | registers_power}, | |
7a78ae4e | 2887 | {"rsc", "IBM POWER RSC", bfd_arch_rs6000, |
489461e2 EZ |
2888 | bfd_mach_rs6k_rsc, -1, -1, tot_num_registers (registers_power), |
2889 | registers_power}, | |
7a78ae4e | 2890 | {"rs2", "IBM POWER RS2", bfd_arch_rs6000, |
489461e2 EZ |
2891 | bfd_mach_rs6k_rs2, -1, -1, tot_num_registers (registers_power), |
2892 | registers_power}, | |
7a78ae4e | 2893 | |
489461e2 | 2894 | {0, 0, 0, 0, 0, 0, 0, 0} |
c906108c SS |
2895 | }; |
2896 | ||
64366f1c | 2897 | /* Initialize the number of registers and pseudo registers in each variant. */ |
489461e2 EZ |
2898 | |
2899 | static void | |
2900 | init_variants (void) | |
2901 | { | |
2902 | struct variant *v; | |
2903 | ||
2904 | for (v = variants; v->name; v++) | |
2905 | { | |
2906 | if (v->nregs == -1) | |
2907 | v->nregs = num_registers (v->regs, v->num_tot_regs); | |
2908 | if (v->npregs == -1) | |
2909 | v->npregs = num_pseudo_registers (v->regs, v->num_tot_regs); | |
2910 | } | |
2911 | } | |
c906108c | 2912 | |
7a78ae4e | 2913 | /* Return the variant corresponding to architecture ARCH and machine number |
64366f1c | 2914 | MACH. If no such variant exists, return null. */ |
c906108c | 2915 | |
7a78ae4e ND |
2916 | static const struct variant * |
2917 | find_variant_by_arch (enum bfd_architecture arch, unsigned long mach) | |
c906108c | 2918 | { |
7a78ae4e | 2919 | const struct variant *v; |
c5aa993b | 2920 | |
7a78ae4e ND |
2921 | for (v = variants; v->name; v++) |
2922 | if (arch == v->arch && mach == v->mach) | |
2923 | return v; | |
c906108c | 2924 | |
7a78ae4e | 2925 | return NULL; |
c906108c | 2926 | } |
9364a0ef EZ |
2927 | |
2928 | static int | |
2929 | gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info) | |
2930 | { | |
2931 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
2932 | return print_insn_big_powerpc (memaddr, info); | |
2933 | else | |
2934 | return print_insn_little_powerpc (memaddr, info); | |
2935 | } | |
7a78ae4e | 2936 | \f |
61a65099 KB |
2937 | static CORE_ADDR |
2938 | rs6000_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
2939 | { | |
2940 | return frame_unwind_register_unsigned (next_frame, PC_REGNUM); | |
2941 | } | |
2942 | ||
2943 | static struct frame_id | |
2944 | rs6000_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
2945 | { | |
2946 | return frame_id_build (frame_unwind_register_unsigned (next_frame, | |
2947 | SP_REGNUM), | |
2948 | frame_pc_unwind (next_frame)); | |
2949 | } | |
2950 | ||
2951 | struct rs6000_frame_cache | |
2952 | { | |
2953 | CORE_ADDR base; | |
2954 | CORE_ADDR initial_sp; | |
2955 | struct trad_frame_saved_reg *saved_regs; | |
2956 | }; | |
2957 | ||
2958 | static struct rs6000_frame_cache * | |
2959 | rs6000_frame_cache (struct frame_info *next_frame, void **this_cache) | |
2960 | { | |
2961 | struct rs6000_frame_cache *cache; | |
2962 | struct gdbarch *gdbarch = get_frame_arch (next_frame); | |
2963 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2964 | struct rs6000_framedata fdata; | |
2965 | int wordsize = tdep->wordsize; | |
e10b1c4c | 2966 | CORE_ADDR func, pc; |
61a65099 KB |
2967 | |
2968 | if ((*this_cache) != NULL) | |
2969 | return (*this_cache); | |
2970 | cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache); | |
2971 | (*this_cache) = cache; | |
2972 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
2973 | ||
e10b1c4c DJ |
2974 | func = frame_func_unwind (next_frame); |
2975 | pc = frame_pc_unwind (next_frame); | |
2976 | skip_prologue (func, pc, &fdata); | |
2977 | ||
2978 | /* Figure out the parent's stack pointer. */ | |
2979 | ||
2980 | /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most | |
2981 | address of the current frame. Things might be easier if the | |
2982 | ->frame pointed to the outer-most address of the frame. In | |
2983 | the mean time, the address of the prev frame is used as the | |
2984 | base address of this frame. */ | |
2985 | cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM); | |
2986 | ||
2987 | /* If the function appears to be frameless, check a couple of likely | |
2988 | indicators that we have simply failed to find the frame setup. | |
2989 | Two common cases of this are missing symbols (i.e. | |
2990 | frame_func_unwind returns the wrong address or 0), and assembly | |
2991 | stubs which have a fast exit path but set up a frame on the slow | |
2992 | path. | |
2993 | ||
2994 | If the LR appears to return to this function, then presume that | |
2995 | we have an ABI compliant frame that we failed to find. */ | |
2996 | if (fdata.frameless && fdata.lr_offset == 0) | |
61a65099 | 2997 | { |
e10b1c4c DJ |
2998 | CORE_ADDR saved_lr; |
2999 | int make_frame = 0; | |
3000 | ||
3001 | saved_lr = frame_unwind_register_unsigned (next_frame, | |
3002 | tdep->ppc_lr_regnum); | |
3003 | if (func == 0 && saved_lr == pc) | |
3004 | make_frame = 1; | |
3005 | else if (func != 0) | |
3006 | { | |
3007 | CORE_ADDR saved_func = get_pc_function_start (saved_lr); | |
3008 | if (func == saved_func) | |
3009 | make_frame = 1; | |
3010 | } | |
3011 | ||
3012 | if (make_frame) | |
3013 | { | |
3014 | fdata.frameless = 0; | |
3015 | fdata.lr_offset = wordsize; | |
3016 | } | |
61a65099 | 3017 | } |
e10b1c4c DJ |
3018 | |
3019 | if (!fdata.frameless) | |
3020 | /* Frameless really means stackless. */ | |
3021 | cache->base = read_memory_addr (cache->base, wordsize); | |
3022 | ||
61a65099 KB |
3023 | trad_frame_set_value (cache->saved_regs, SP_REGNUM, cache->base); |
3024 | ||
3025 | /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr. | |
3026 | All fpr's from saved_fpr to fp31 are saved. */ | |
3027 | ||
3028 | if (fdata.saved_fpr >= 0) | |
3029 | { | |
3030 | int i; | |
3031 | CORE_ADDR fpr_addr = cache->base + fdata.fpr_offset; | |
383f0f5b JB |
3032 | |
3033 | /* If skip_prologue says floating-point registers were saved, | |
3034 | but the current architecture has no floating-point registers, | |
3035 | then that's strange. But we have no indices to even record | |
3036 | the addresses under, so we just ignore it. */ | |
3037 | if (ppc_floating_point_unit_p (gdbarch)) | |
063715bf | 3038 | for (i = fdata.saved_fpr; i < ppc_num_fprs; i++) |
383f0f5b JB |
3039 | { |
3040 | cache->saved_regs[tdep->ppc_fp0_regnum + i].addr = fpr_addr; | |
3041 | fpr_addr += 8; | |
3042 | } | |
61a65099 KB |
3043 | } |
3044 | ||
3045 | /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr. | |
3046 | All gpr's from saved_gpr to gpr31 are saved. */ | |
3047 | ||
3048 | if (fdata.saved_gpr >= 0) | |
3049 | { | |
3050 | int i; | |
3051 | CORE_ADDR gpr_addr = cache->base + fdata.gpr_offset; | |
063715bf | 3052 | for (i = fdata.saved_gpr; i < ppc_num_gprs; i++) |
61a65099 KB |
3053 | { |
3054 | cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = gpr_addr; | |
3055 | gpr_addr += wordsize; | |
3056 | } | |
3057 | } | |
3058 | ||
3059 | /* if != -1, fdata.saved_vr is the smallest number of saved_vr. | |
3060 | All vr's from saved_vr to vr31 are saved. */ | |
3061 | if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) | |
3062 | { | |
3063 | if (fdata.saved_vr >= 0) | |
3064 | { | |
3065 | int i; | |
3066 | CORE_ADDR vr_addr = cache->base + fdata.vr_offset; | |
3067 | for (i = fdata.saved_vr; i < 32; i++) | |
3068 | { | |
3069 | cache->saved_regs[tdep->ppc_vr0_regnum + i].addr = vr_addr; | |
3070 | vr_addr += register_size (gdbarch, tdep->ppc_vr0_regnum); | |
3071 | } | |
3072 | } | |
3073 | } | |
3074 | ||
3075 | /* if != -1, fdata.saved_ev is the smallest number of saved_ev. | |
3076 | All vr's from saved_ev to ev31 are saved. ????? */ | |
3077 | if (tdep->ppc_ev0_regnum != -1 && tdep->ppc_ev31_regnum != -1) | |
3078 | { | |
3079 | if (fdata.saved_ev >= 0) | |
3080 | { | |
3081 | int i; | |
3082 | CORE_ADDR ev_addr = cache->base + fdata.ev_offset; | |
063715bf | 3083 | for (i = fdata.saved_ev; i < ppc_num_gprs; i++) |
61a65099 KB |
3084 | { |
3085 | cache->saved_regs[tdep->ppc_ev0_regnum + i].addr = ev_addr; | |
3086 | cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + 4; | |
3087 | ev_addr += register_size (gdbarch, tdep->ppc_ev0_regnum); | |
3088 | } | |
3089 | } | |
3090 | } | |
3091 | ||
3092 | /* If != 0, fdata.cr_offset is the offset from the frame that | |
3093 | holds the CR. */ | |
3094 | if (fdata.cr_offset != 0) | |
3095 | cache->saved_regs[tdep->ppc_cr_regnum].addr = cache->base + fdata.cr_offset; | |
3096 | ||
3097 | /* If != 0, fdata.lr_offset is the offset from the frame that | |
3098 | holds the LR. */ | |
3099 | if (fdata.lr_offset != 0) | |
3100 | cache->saved_regs[tdep->ppc_lr_regnum].addr = cache->base + fdata.lr_offset; | |
3101 | /* The PC is found in the link register. */ | |
3102 | cache->saved_regs[PC_REGNUM] = cache->saved_regs[tdep->ppc_lr_regnum]; | |
3103 | ||
3104 | /* If != 0, fdata.vrsave_offset is the offset from the frame that | |
3105 | holds the VRSAVE. */ | |
3106 | if (fdata.vrsave_offset != 0) | |
3107 | cache->saved_regs[tdep->ppc_vrsave_regnum].addr = cache->base + fdata.vrsave_offset; | |
3108 | ||
3109 | if (fdata.alloca_reg < 0) | |
3110 | /* If no alloca register used, then fi->frame is the value of the | |
3111 | %sp for this frame, and it is good enough. */ | |
3112 | cache->initial_sp = frame_unwind_register_unsigned (next_frame, SP_REGNUM); | |
3113 | else | |
3114 | cache->initial_sp = frame_unwind_register_unsigned (next_frame, | |
3115 | fdata.alloca_reg); | |
3116 | ||
3117 | return cache; | |
3118 | } | |
3119 | ||
3120 | static void | |
3121 | rs6000_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
3122 | struct frame_id *this_id) | |
3123 | { | |
3124 | struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame, | |
3125 | this_cache); | |
3126 | (*this_id) = frame_id_build (info->base, frame_func_unwind (next_frame)); | |
3127 | } | |
3128 | ||
3129 | static void | |
3130 | rs6000_frame_prev_register (struct frame_info *next_frame, | |
3131 | void **this_cache, | |
3132 | int regnum, int *optimizedp, | |
3133 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
50fd1280 | 3134 | int *realnump, gdb_byte *valuep) |
61a65099 KB |
3135 | { |
3136 | struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame, | |
3137 | this_cache); | |
1f67027d AC |
3138 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, |
3139 | optimizedp, lvalp, addrp, realnump, valuep); | |
61a65099 KB |
3140 | } |
3141 | ||
3142 | static const struct frame_unwind rs6000_frame_unwind = | |
3143 | { | |
3144 | NORMAL_FRAME, | |
3145 | rs6000_frame_this_id, | |
3146 | rs6000_frame_prev_register | |
3147 | }; | |
3148 | ||
3149 | static const struct frame_unwind * | |
3150 | rs6000_frame_sniffer (struct frame_info *next_frame) | |
3151 | { | |
3152 | return &rs6000_frame_unwind; | |
3153 | } | |
3154 | ||
3155 | \f | |
3156 | ||
3157 | static CORE_ADDR | |
3158 | rs6000_frame_base_address (struct frame_info *next_frame, | |
3159 | void **this_cache) | |
3160 | { | |
3161 | struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame, | |
3162 | this_cache); | |
3163 | return info->initial_sp; | |
3164 | } | |
3165 | ||
3166 | static const struct frame_base rs6000_frame_base = { | |
3167 | &rs6000_frame_unwind, | |
3168 | rs6000_frame_base_address, | |
3169 | rs6000_frame_base_address, | |
3170 | rs6000_frame_base_address | |
3171 | }; | |
3172 | ||
3173 | static const struct frame_base * | |
3174 | rs6000_frame_base_sniffer (struct frame_info *next_frame) | |
3175 | { | |
3176 | return &rs6000_frame_base; | |
3177 | } | |
3178 | ||
7a78ae4e ND |
3179 | /* Initialize the current architecture based on INFO. If possible, re-use an |
3180 | architecture from ARCHES, which is a list of architectures already created | |
3181 | during this debugging session. | |
c906108c | 3182 | |
7a78ae4e | 3183 | Called e.g. at program startup, when reading a core file, and when reading |
64366f1c | 3184 | a binary file. */ |
c906108c | 3185 | |
7a78ae4e ND |
3186 | static struct gdbarch * |
3187 | rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
3188 | { | |
3189 | struct gdbarch *gdbarch; | |
3190 | struct gdbarch_tdep *tdep; | |
708ff411 | 3191 | int wordsize, from_xcoff_exec, from_elf_exec, i, off; |
7a78ae4e ND |
3192 | struct reg *regs; |
3193 | const struct variant *v; | |
3194 | enum bfd_architecture arch; | |
3195 | unsigned long mach; | |
3196 | bfd abfd; | |
7b112f9c | 3197 | int sysv_abi; |
5bf1c677 | 3198 | asection *sect; |
7a78ae4e | 3199 | |
9aa1e687 | 3200 | from_xcoff_exec = info.abfd && info.abfd->format == bfd_object && |
7a78ae4e ND |
3201 | bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour; |
3202 | ||
9aa1e687 KB |
3203 | from_elf_exec = info.abfd && info.abfd->format == bfd_object && |
3204 | bfd_get_flavour (info.abfd) == bfd_target_elf_flavour; | |
3205 | ||
3206 | sysv_abi = info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour; | |
3207 | ||
e712c1cf | 3208 | /* Check word size. If INFO is from a binary file, infer it from |
64366f1c | 3209 | that, else choose a likely default. */ |
9aa1e687 | 3210 | if (from_xcoff_exec) |
c906108c | 3211 | { |
11ed25ac | 3212 | if (bfd_xcoff_is_xcoff64 (info.abfd)) |
7a78ae4e ND |
3213 | wordsize = 8; |
3214 | else | |
3215 | wordsize = 4; | |
c906108c | 3216 | } |
9aa1e687 KB |
3217 | else if (from_elf_exec) |
3218 | { | |
3219 | if (elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
3220 | wordsize = 8; | |
3221 | else | |
3222 | wordsize = 4; | |
3223 | } | |
c906108c | 3224 | else |
7a78ae4e | 3225 | { |
27b15785 KB |
3226 | if (info.bfd_arch_info != NULL && info.bfd_arch_info->bits_per_word != 0) |
3227 | wordsize = info.bfd_arch_info->bits_per_word / | |
3228 | info.bfd_arch_info->bits_per_byte; | |
3229 | else | |
3230 | wordsize = 4; | |
7a78ae4e | 3231 | } |
c906108c | 3232 | |
13c0b536 | 3233 | /* Find a candidate among extant architectures. */ |
7a78ae4e ND |
3234 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
3235 | arches != NULL; | |
3236 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
3237 | { | |
3238 | /* Word size in the various PowerPC bfd_arch_info structs isn't | |
3239 | meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform | |
64366f1c | 3240 | separate word size check. */ |
7a78ae4e | 3241 | tdep = gdbarch_tdep (arches->gdbarch); |
4be87837 | 3242 | if (tdep && tdep->wordsize == wordsize) |
7a78ae4e ND |
3243 | return arches->gdbarch; |
3244 | } | |
c906108c | 3245 | |
7a78ae4e ND |
3246 | /* None found, create a new architecture from INFO, whose bfd_arch_info |
3247 | validity depends on the source: | |
3248 | - executable useless | |
3249 | - rs6000_host_arch() good | |
3250 | - core file good | |
3251 | - "set arch" trust blindly | |
3252 | - GDB startup useless but harmless */ | |
c906108c | 3253 | |
9aa1e687 | 3254 | if (!from_xcoff_exec) |
c906108c | 3255 | { |
b732d07d | 3256 | arch = info.bfd_arch_info->arch; |
7a78ae4e | 3257 | mach = info.bfd_arch_info->mach; |
c906108c | 3258 | } |
7a78ae4e | 3259 | else |
c906108c | 3260 | { |
7a78ae4e | 3261 | arch = bfd_arch_powerpc; |
35cec841 | 3262 | bfd_default_set_arch_mach (&abfd, arch, 0); |
7a78ae4e | 3263 | info.bfd_arch_info = bfd_get_arch_info (&abfd); |
35cec841 | 3264 | mach = info.bfd_arch_info->mach; |
7a78ae4e ND |
3265 | } |
3266 | tdep = xmalloc (sizeof (struct gdbarch_tdep)); | |
3267 | tdep->wordsize = wordsize; | |
5bf1c677 EZ |
3268 | |
3269 | /* For e500 executables, the apuinfo section is of help here. Such | |
3270 | section contains the identifier and revision number of each | |
3271 | Application-specific Processing Unit that is present on the | |
3272 | chip. The content of the section is determined by the assembler | |
3273 | which looks at each instruction and determines which unit (and | |
3274 | which version of it) can execute it. In our case we just look for | |
3275 | the existance of the section. */ | |
3276 | ||
3277 | if (info.abfd) | |
3278 | { | |
3279 | sect = bfd_get_section_by_name (info.abfd, ".PPC.EMB.apuinfo"); | |
3280 | if (sect) | |
3281 | { | |
3282 | arch = info.bfd_arch_info->arch; | |
3283 | mach = bfd_mach_ppc_e500; | |
3284 | bfd_default_set_arch_mach (&abfd, arch, mach); | |
3285 | info.bfd_arch_info = bfd_get_arch_info (&abfd); | |
3286 | } | |
3287 | } | |
3288 | ||
7a78ae4e | 3289 | gdbarch = gdbarch_alloc (&info, tdep); |
7a78ae4e | 3290 | |
489461e2 EZ |
3291 | /* Initialize the number of real and pseudo registers in each variant. */ |
3292 | init_variants (); | |
3293 | ||
64366f1c | 3294 | /* Choose variant. */ |
7a78ae4e ND |
3295 | v = find_variant_by_arch (arch, mach); |
3296 | if (!v) | |
dd47e6fd EZ |
3297 | return NULL; |
3298 | ||
7a78ae4e ND |
3299 | tdep->regs = v->regs; |
3300 | ||
2188cbdd | 3301 | tdep->ppc_gp0_regnum = 0; |
2188cbdd EZ |
3302 | tdep->ppc_toc_regnum = 2; |
3303 | tdep->ppc_ps_regnum = 65; | |
3304 | tdep->ppc_cr_regnum = 66; | |
3305 | tdep->ppc_lr_regnum = 67; | |
3306 | tdep->ppc_ctr_regnum = 68; | |
3307 | tdep->ppc_xer_regnum = 69; | |
3308 | if (v->mach == bfd_mach_ppc_601) | |
3309 | tdep->ppc_mq_regnum = 124; | |
708ff411 | 3310 | else if (arch == bfd_arch_rs6000) |
2188cbdd | 3311 | tdep->ppc_mq_regnum = 70; |
e3f36dbd KB |
3312 | else |
3313 | tdep->ppc_mq_regnum = -1; | |
366f009f | 3314 | tdep->ppc_fp0_regnum = 32; |
708ff411 | 3315 | tdep->ppc_fpscr_regnum = (arch == bfd_arch_rs6000) ? 71 : 70; |
f86a7158 | 3316 | tdep->ppc_sr0_regnum = 71; |
baffbae0 JB |
3317 | tdep->ppc_vr0_regnum = -1; |
3318 | tdep->ppc_vrsave_regnum = -1; | |
6ced10dd | 3319 | tdep->ppc_ev0_upper_regnum = -1; |
baffbae0 JB |
3320 | tdep->ppc_ev0_regnum = -1; |
3321 | tdep->ppc_ev31_regnum = -1; | |
867e2dc5 JB |
3322 | tdep->ppc_acc_regnum = -1; |
3323 | tdep->ppc_spefscr_regnum = -1; | |
2188cbdd | 3324 | |
c8001721 EZ |
3325 | set_gdbarch_pc_regnum (gdbarch, 64); |
3326 | set_gdbarch_sp_regnum (gdbarch, 1); | |
0ba6dca9 | 3327 | set_gdbarch_deprecated_fp_regnum (gdbarch, 1); |
9f643768 | 3328 | set_gdbarch_register_sim_regno (gdbarch, rs6000_register_sim_regno); |
afd48b75 | 3329 | if (sysv_abi && wordsize == 8) |
05580c65 | 3330 | set_gdbarch_return_value (gdbarch, ppc64_sysv_abi_return_value); |
e754ae69 | 3331 | else if (sysv_abi && wordsize == 4) |
05580c65 | 3332 | set_gdbarch_return_value (gdbarch, ppc_sysv_abi_return_value); |
afd48b75 AC |
3333 | else |
3334 | { | |
3335 | set_gdbarch_deprecated_extract_return_value (gdbarch, rs6000_extract_return_value); | |
a3c001ce | 3336 | set_gdbarch_store_return_value (gdbarch, rs6000_store_return_value); |
afd48b75 | 3337 | } |
c8001721 | 3338 | |
baffbae0 JB |
3339 | /* Set lr_frame_offset. */ |
3340 | if (wordsize == 8) | |
3341 | tdep->lr_frame_offset = 16; | |
3342 | else if (sysv_abi) | |
3343 | tdep->lr_frame_offset = 4; | |
3344 | else | |
3345 | tdep->lr_frame_offset = 8; | |
3346 | ||
f86a7158 JB |
3347 | if (v->arch == bfd_arch_rs6000) |
3348 | tdep->ppc_sr0_regnum = -1; | |
3349 | else if (v->arch == bfd_arch_powerpc) | |
1fcc0bb8 EZ |
3350 | switch (v->mach) |
3351 | { | |
3352 | case bfd_mach_ppc: | |
412b3060 | 3353 | tdep->ppc_sr0_regnum = -1; |
1fcc0bb8 EZ |
3354 | tdep->ppc_vr0_regnum = 71; |
3355 | tdep->ppc_vrsave_regnum = 104; | |
3356 | break; | |
3357 | case bfd_mach_ppc_7400: | |
3358 | tdep->ppc_vr0_regnum = 119; | |
54c2a1e6 | 3359 | tdep->ppc_vrsave_regnum = 152; |
c8001721 EZ |
3360 | break; |
3361 | case bfd_mach_ppc_e500: | |
c8001721 | 3362 | tdep->ppc_toc_regnum = -1; |
6ced10dd JB |
3363 | tdep->ppc_ev0_upper_regnum = 32; |
3364 | tdep->ppc_ev0_regnum = 73; | |
3365 | tdep->ppc_ev31_regnum = 104; | |
3366 | tdep->ppc_acc_regnum = 71; | |
3367 | tdep->ppc_spefscr_regnum = 72; | |
383f0f5b JB |
3368 | tdep->ppc_fp0_regnum = -1; |
3369 | tdep->ppc_fpscr_regnum = -1; | |
f86a7158 | 3370 | tdep->ppc_sr0_regnum = -1; |
c8001721 EZ |
3371 | set_gdbarch_pseudo_register_read (gdbarch, e500_pseudo_register_read); |
3372 | set_gdbarch_pseudo_register_write (gdbarch, e500_pseudo_register_write); | |
6ced10dd | 3373 | set_gdbarch_register_reggroup_p (gdbarch, e500_register_reggroup_p); |
1fcc0bb8 | 3374 | break; |
f86a7158 JB |
3375 | |
3376 | case bfd_mach_ppc64: | |
3377 | case bfd_mach_ppc_620: | |
3378 | case bfd_mach_ppc_630: | |
3379 | case bfd_mach_ppc_a35: | |
3380 | case bfd_mach_ppc_rs64ii: | |
3381 | case bfd_mach_ppc_rs64iii: | |
3382 | /* These processor's register sets don't have segment registers. */ | |
3383 | tdep->ppc_sr0_regnum = -1; | |
3384 | break; | |
1fcc0bb8 | 3385 | } |
f86a7158 JB |
3386 | else |
3387 | internal_error (__FILE__, __LINE__, | |
e2e0b3e5 AC |
3388 | _("rs6000_gdbarch_init: " |
3389 | "received unexpected BFD 'arch' value")); | |
1fcc0bb8 | 3390 | |
e0d24f8d WZ |
3391 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); |
3392 | ||
338ef23d AC |
3393 | /* Sanity check on registers. */ |
3394 | gdb_assert (strcmp (tdep->regs[tdep->ppc_gp0_regnum].name, "r0") == 0); | |
3395 | ||
56a6dfb9 | 3396 | /* Select instruction printer. */ |
708ff411 | 3397 | if (arch == bfd_arch_rs6000) |
9364a0ef | 3398 | set_gdbarch_print_insn (gdbarch, print_insn_rs6000); |
56a6dfb9 | 3399 | else |
9364a0ef | 3400 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_powerpc); |
7495d1dc | 3401 | |
7a78ae4e | 3402 | set_gdbarch_write_pc (gdbarch, generic_target_write_pc); |
7a78ae4e ND |
3403 | |
3404 | set_gdbarch_num_regs (gdbarch, v->nregs); | |
c8001721 | 3405 | set_gdbarch_num_pseudo_regs (gdbarch, v->npregs); |
7a78ae4e | 3406 | set_gdbarch_register_name (gdbarch, rs6000_register_name); |
691d145a | 3407 | set_gdbarch_register_type (gdbarch, rs6000_register_type); |
c44ca51c | 3408 | set_gdbarch_register_reggroup_p (gdbarch, rs6000_register_reggroup_p); |
7a78ae4e ND |
3409 | |
3410 | set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT); | |
3411 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); | |
3412 | set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
3413 | set_gdbarch_long_bit (gdbarch, wordsize * TARGET_CHAR_BIT); | |
3414 | set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
3415 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
3416 | set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
ab9fe00e KB |
3417 | if (sysv_abi) |
3418 | set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT); | |
3419 | else | |
3420 | set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
4e409299 | 3421 | set_gdbarch_char_signed (gdbarch, 0); |
7a78ae4e | 3422 | |
11269d7e | 3423 | set_gdbarch_frame_align (gdbarch, rs6000_frame_align); |
8b148df9 AC |
3424 | if (sysv_abi && wordsize == 8) |
3425 | /* PPC64 SYSV. */ | |
3426 | set_gdbarch_frame_red_zone_size (gdbarch, 288); | |
3427 | else if (!sysv_abi && wordsize == 4) | |
5bffac25 AC |
3428 | /* PowerOpen / AIX 32 bit. The saved area or red zone consists of |
3429 | 19 4 byte GPRS + 18 8 byte FPRs giving a total of 220 bytes. | |
3430 | Problem is, 220 isn't frame (16 byte) aligned. Round it up to | |
3431 | 224. */ | |
3432 | set_gdbarch_frame_red_zone_size (gdbarch, 224); | |
7a78ae4e | 3433 | |
691d145a JB |
3434 | set_gdbarch_convert_register_p (gdbarch, rs6000_convert_register_p); |
3435 | set_gdbarch_register_to_value (gdbarch, rs6000_register_to_value); | |
3436 | set_gdbarch_value_to_register (gdbarch, rs6000_value_to_register); | |
3437 | ||
18ed0c4e JB |
3438 | set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_stab_reg_to_regnum); |
3439 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rs6000_dwarf2_reg_to_regnum); | |
2ea5f656 KB |
3440 | /* Note: kevinb/2002-04-12: I'm not convinced that rs6000_push_arguments() |
3441 | is correct for the SysV ABI when the wordsize is 8, but I'm also | |
3442 | fairly certain that ppc_sysv_abi_push_arguments() will give even | |
3443 | worse results since it only works for 32-bit code. So, for the moment, | |
3444 | we're better off calling rs6000_push_arguments() since it works for | |
3445 | 64-bit code. At some point in the future, this matter needs to be | |
3446 | revisited. */ | |
3447 | if (sysv_abi && wordsize == 4) | |
77b2b6d4 | 3448 | set_gdbarch_push_dummy_call (gdbarch, ppc_sysv_abi_push_dummy_call); |
8be9034a AC |
3449 | else if (sysv_abi && wordsize == 8) |
3450 | set_gdbarch_push_dummy_call (gdbarch, ppc64_sysv_abi_push_dummy_call); | |
9aa1e687 | 3451 | else |
77b2b6d4 | 3452 | set_gdbarch_push_dummy_call (gdbarch, rs6000_push_dummy_call); |
7a78ae4e | 3453 | |
74055713 | 3454 | set_gdbarch_deprecated_extract_struct_value_address (gdbarch, rs6000_extract_struct_value_address); |
7a78ae4e ND |
3455 | |
3456 | set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue); | |
0d1243d9 PG |
3457 | set_gdbarch_in_function_epilogue_p (gdbarch, rs6000_in_function_epilogue_p); |
3458 | ||
7a78ae4e | 3459 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
7a78ae4e ND |
3460 | set_gdbarch_breakpoint_from_pc (gdbarch, rs6000_breakpoint_from_pc); |
3461 | ||
6066c3de AC |
3462 | /* Handle the 64-bit SVR4 minimal-symbol convention of using "FN" |
3463 | for the descriptor and ".FN" for the entry-point -- a user | |
3464 | specifying "break FN" will unexpectedly end up with a breakpoint | |
3465 | on the descriptor and not the function. This architecture method | |
3466 | transforms any breakpoints on descriptors into breakpoints on the | |
3467 | corresponding entry point. */ | |
3468 | if (sysv_abi && wordsize == 8) | |
3469 | set_gdbarch_adjust_breakpoint_address (gdbarch, ppc64_sysv_abi_adjust_breakpoint_address); | |
3470 | ||
7a78ae4e ND |
3471 | /* Not sure on this. FIXMEmgo */ |
3472 | set_gdbarch_frame_args_skip (gdbarch, 8); | |
3473 | ||
05580c65 | 3474 | if (!sysv_abi) |
b5622e8d | 3475 | set_gdbarch_deprecated_use_struct_convention (gdbarch, rs6000_use_struct_convention); |
8e0662df | 3476 | |
15813d3f AC |
3477 | if (!sysv_abi) |
3478 | { | |
3479 | /* Handle RS/6000 function pointers (which are really function | |
3480 | descriptors). */ | |
f517ea4e PS |
3481 | set_gdbarch_convert_from_func_ptr_addr (gdbarch, |
3482 | rs6000_convert_from_func_ptr_addr); | |
9aa1e687 | 3483 | } |
7a78ae4e | 3484 | |
143985b7 AF |
3485 | /* Helpers for function argument information. */ |
3486 | set_gdbarch_fetch_pointer_argument (gdbarch, rs6000_fetch_pointer_argument); | |
3487 | ||
7b112f9c | 3488 | /* Hook in ABI-specific overrides, if they have been registered. */ |
4be87837 | 3489 | gdbarch_init_osabi (info, gdbarch); |
7b112f9c | 3490 | |
61a65099 KB |
3491 | switch (info.osabi) |
3492 | { | |
f5aecab8 PG |
3493 | case GDB_OSABI_LINUX: |
3494 | /* FIXME: pgilliam/2005-10-21: Assume all PowerPC 64-bit linux systems | |
3495 | have altivec registers. If not, ptrace will fail the first time it's | |
3496 | called to access one and will not be called again. This wart will | |
3497 | be removed when Daniel Jacobowitz's proposal for autodetecting target | |
3498 | registers is implemented. */ | |
3499 | if ((v->arch == bfd_arch_powerpc) && ((v->mach)== bfd_mach_ppc64)) | |
3500 | { | |
3501 | tdep->ppc_vr0_regnum = 71; | |
3502 | tdep->ppc_vrsave_regnum = 104; | |
3503 | } | |
3504 | /* Fall Thru */ | |
61a65099 KB |
3505 | case GDB_OSABI_NETBSD_AOUT: |
3506 | case GDB_OSABI_NETBSD_ELF: | |
3507 | case GDB_OSABI_UNKNOWN: | |
61a65099 KB |
3508 | set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc); |
3509 | frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer); | |
3510 | set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id); | |
3511 | frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer); | |
3512 | break; | |
3513 | default: | |
61a65099 | 3514 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); |
81332287 KB |
3515 | |
3516 | set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc); | |
3517 | frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer); | |
3518 | set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id); | |
3519 | frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer); | |
61a65099 KB |
3520 | } |
3521 | ||
9f643768 JB |
3522 | init_sim_regno_table (gdbarch); |
3523 | ||
7a78ae4e | 3524 | return gdbarch; |
c906108c SS |
3525 | } |
3526 | ||
7b112f9c JT |
3527 | static void |
3528 | rs6000_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
3529 | { | |
3530 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3531 | ||
3532 | if (tdep == NULL) | |
3533 | return; | |
3534 | ||
4be87837 | 3535 | /* FIXME: Dump gdbarch_tdep. */ |
7b112f9c JT |
3536 | } |
3537 | ||
c906108c SS |
3538 | /* Initialization code. */ |
3539 | ||
a78f21af | 3540 | extern initialize_file_ftype _initialize_rs6000_tdep; /* -Wmissing-prototypes */ |
b9362cc7 | 3541 | |
c906108c | 3542 | void |
fba45db2 | 3543 | _initialize_rs6000_tdep (void) |
c906108c | 3544 | { |
7b112f9c JT |
3545 | gdbarch_register (bfd_arch_rs6000, rs6000_gdbarch_init, rs6000_dump_tdep); |
3546 | gdbarch_register (bfd_arch_powerpc, rs6000_gdbarch_init, rs6000_dump_tdep); | |
c906108c | 3547 | } |