Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for GDB, the GNU debugger. |
7aea86e6 | 2 | |
6aba47ca DJ |
3 | Copyright (C) 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, |
4 | 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 | |
721d14ba | 5 | Free Software Foundation, Inc. |
c906108c | 6 | |
c5aa993b | 7 | This file is part of GDB. |
c906108c | 8 | |
c5aa993b JM |
9 | This program is free software; you can redistribute it and/or modify |
10 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 11 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 12 | (at your option) any later version. |
c906108c | 13 | |
c5aa993b JM |
14 | This program is distributed in the hope that it will be useful, |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
c906108c | 18 | |
c5aa993b | 19 | You should have received a copy of the GNU General Public License |
a9762ec7 | 20 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
21 | |
22 | #include "defs.h" | |
23 | #include "frame.h" | |
24 | #include "inferior.h" | |
25 | #include "symtab.h" | |
26 | #include "target.h" | |
27 | #include "gdbcore.h" | |
28 | #include "gdbcmd.h" | |
c906108c | 29 | #include "objfiles.h" |
7a78ae4e | 30 | #include "arch-utils.h" |
4e052eda | 31 | #include "regcache.h" |
d195bc9f | 32 | #include "regset.h" |
d16aafd8 | 33 | #include "doublest.h" |
fd0407d6 | 34 | #include "value.h" |
1fcc0bb8 | 35 | #include "parser-defs.h" |
4be87837 | 36 | #include "osabi.h" |
7d9b040b | 37 | #include "infcall.h" |
9f643768 JB |
38 | #include "sim-regno.h" |
39 | #include "gdb/sim-ppc.h" | |
6ced10dd | 40 | #include "reggroups.h" |
4fc771b8 | 41 | #include "dwarf2-frame.h" |
7cc46491 DJ |
42 | #include "target-descriptions.h" |
43 | #include "user-regs.h" | |
7a78ae4e | 44 | |
2fccf04a | 45 | #include "libbfd.h" /* for bfd_default_set_arch_mach */ |
7a78ae4e | 46 | #include "coff/internal.h" /* for libcoff.h */ |
2fccf04a | 47 | #include "libcoff.h" /* for xcoff_data */ |
11ed25ac KB |
48 | #include "coff/xcoff.h" |
49 | #include "libxcoff.h" | |
7a78ae4e | 50 | |
9aa1e687 | 51 | #include "elf-bfd.h" |
7a78ae4e | 52 | |
6ded7999 | 53 | #include "solib-svr4.h" |
9aa1e687 | 54 | #include "ppc-tdep.h" |
7a78ae4e | 55 | |
338ef23d | 56 | #include "gdb_assert.h" |
a89aa300 | 57 | #include "dis-asm.h" |
338ef23d | 58 | |
61a65099 KB |
59 | #include "trad-frame.h" |
60 | #include "frame-unwind.h" | |
61 | #include "frame-base.h" | |
62 | ||
1f82754b | 63 | #include "rs6000-tdep.h" |
c44ca51c | 64 | |
7cc46491 DJ |
65 | #include "features/rs6000/powerpc-32.c" |
66 | #include "features/rs6000/powerpc-403.c" | |
67 | #include "features/rs6000/powerpc-403gc.c" | |
68 | #include "features/rs6000/powerpc-505.c" | |
69 | #include "features/rs6000/powerpc-601.c" | |
70 | #include "features/rs6000/powerpc-602.c" | |
71 | #include "features/rs6000/powerpc-603.c" | |
72 | #include "features/rs6000/powerpc-604.c" | |
73 | #include "features/rs6000/powerpc-64.c" | |
74 | #include "features/rs6000/powerpc-7400.c" | |
75 | #include "features/rs6000/powerpc-750.c" | |
76 | #include "features/rs6000/powerpc-860.c" | |
77 | #include "features/rs6000/powerpc-e500.c" | |
78 | #include "features/rs6000/rs6000.c" | |
79 | ||
7a78ae4e ND |
80 | /* If the kernel has to deliver a signal, it pushes a sigcontext |
81 | structure on the stack and then calls the signal handler, passing | |
82 | the address of the sigcontext in an argument register. Usually | |
83 | the signal handler doesn't save this register, so we have to | |
84 | access the sigcontext structure via an offset from the signal handler | |
85 | frame. | |
86 | The following constants were determined by experimentation on AIX 3.2. */ | |
87 | #define SIG_FRAME_PC_OFFSET 96 | |
88 | #define SIG_FRAME_LR_OFFSET 108 | |
89 | #define SIG_FRAME_FP_OFFSET 284 | |
90 | ||
7a78ae4e ND |
91 | /* To be used by skip_prologue. */ |
92 | ||
93 | struct rs6000_framedata | |
94 | { | |
95 | int offset; /* total size of frame --- the distance | |
96 | by which we decrement sp to allocate | |
97 | the frame */ | |
98 | int saved_gpr; /* smallest # of saved gpr */ | |
99 | int saved_fpr; /* smallest # of saved fpr */ | |
6be8bc0c | 100 | int saved_vr; /* smallest # of saved vr */ |
96ff0de4 | 101 | int saved_ev; /* smallest # of saved ev */ |
7a78ae4e ND |
102 | int alloca_reg; /* alloca register number (frame ptr) */ |
103 | char frameless; /* true if frameless functions. */ | |
104 | char nosavedpc; /* true if pc not saved. */ | |
105 | int gpr_offset; /* offset of saved gprs from prev sp */ | |
106 | int fpr_offset; /* offset of saved fprs from prev sp */ | |
6be8bc0c | 107 | int vr_offset; /* offset of saved vrs from prev sp */ |
96ff0de4 | 108 | int ev_offset; /* offset of saved evs from prev sp */ |
7a78ae4e ND |
109 | int lr_offset; /* offset of saved lr */ |
110 | int cr_offset; /* offset of saved cr */ | |
6be8bc0c | 111 | int vrsave_offset; /* offset of saved vrsave register */ |
7a78ae4e ND |
112 | }; |
113 | ||
114 | /* Description of a single register. */ | |
115 | ||
116 | struct reg | |
117 | { | |
118 | char *name; /* name of register */ | |
0bcc32ae JB |
119 | unsigned char sz32; /* size on 32-bit arch, 0 if nonexistent */ |
120 | unsigned char sz64; /* size on 64-bit arch, 0 if nonexistent */ | |
7a78ae4e | 121 | unsigned char fpr; /* whether register is floating-point */ |
489461e2 | 122 | unsigned char pseudo; /* whether register is pseudo */ |
13ac140c JB |
123 | int spr_num; /* PowerPC SPR number, or -1 if not an SPR. |
124 | This is an ISA SPR number, not a GDB | |
125 | register number. */ | |
7a78ae4e ND |
126 | }; |
127 | ||
c906108c SS |
128 | /* Hook for determining the TOC address when calling functions in the |
129 | inferior under AIX. The initialization code in rs6000-nat.c sets | |
130 | this hook to point to find_toc_address. */ | |
131 | ||
7a78ae4e ND |
132 | CORE_ADDR (*rs6000_find_toc_address_hook) (CORE_ADDR) = NULL; |
133 | ||
c906108c SS |
134 | /* Static function prototypes */ |
135 | ||
0b1b3e42 UW |
136 | static CORE_ADDR branch_dest (struct frame_info *frame, int opcode, |
137 | int instr, CORE_ADDR pc, CORE_ADDR safety); | |
077276e8 KB |
138 | static CORE_ADDR skip_prologue (CORE_ADDR, CORE_ADDR, |
139 | struct rs6000_framedata *); | |
c906108c | 140 | |
64b84175 KB |
141 | /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */ |
142 | int | |
143 | altivec_register_p (int regno) | |
144 | { | |
145 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
146 | if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0) | |
147 | return 0; | |
148 | else | |
149 | return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum); | |
150 | } | |
151 | ||
383f0f5b | 152 | |
867e2dc5 JB |
153 | /* Return true if REGNO is an SPE register, false otherwise. */ |
154 | int | |
155 | spe_register_p (int regno) | |
156 | { | |
157 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
158 | ||
159 | /* Is it a reference to EV0 -- EV31, and do we have those? */ | |
160 | if (tdep->ppc_ev0_regnum >= 0 | |
161 | && tdep->ppc_ev31_regnum >= 0 | |
162 | && tdep->ppc_ev0_regnum <= regno && regno <= tdep->ppc_ev31_regnum) | |
163 | return 1; | |
164 | ||
6ced10dd JB |
165 | /* Is it a reference to one of the raw upper GPR halves? */ |
166 | if (tdep->ppc_ev0_upper_regnum >= 0 | |
167 | && tdep->ppc_ev0_upper_regnum <= regno | |
168 | && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) | |
169 | return 1; | |
170 | ||
867e2dc5 JB |
171 | /* Is it a reference to the 64-bit accumulator, and do we have that? */ |
172 | if (tdep->ppc_acc_regnum >= 0 | |
173 | && tdep->ppc_acc_regnum == regno) | |
174 | return 1; | |
175 | ||
176 | /* Is it a reference to the SPE floating-point status and control register, | |
177 | and do we have that? */ | |
178 | if (tdep->ppc_spefscr_regnum >= 0 | |
179 | && tdep->ppc_spefscr_regnum == regno) | |
180 | return 1; | |
181 | ||
182 | return 0; | |
183 | } | |
184 | ||
185 | ||
383f0f5b JB |
186 | /* Return non-zero if the architecture described by GDBARCH has |
187 | floating-point registers (f0 --- f31 and fpscr). */ | |
0a613259 AC |
188 | int |
189 | ppc_floating_point_unit_p (struct gdbarch *gdbarch) | |
190 | { | |
383f0f5b JB |
191 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
192 | ||
193 | return (tdep->ppc_fp0_regnum >= 0 | |
194 | && tdep->ppc_fpscr_regnum >= 0); | |
0a613259 | 195 | } |
9f643768 | 196 | |
09991fa0 JB |
197 | |
198 | /* Check that TABLE[GDB_REGNO] is not already initialized, and then | |
199 | set it to SIM_REGNO. | |
200 | ||
201 | This is a helper function for init_sim_regno_table, constructing | |
202 | the table mapping GDB register numbers to sim register numbers; we | |
203 | initialize every element in that table to -1 before we start | |
204 | filling it in. */ | |
9f643768 JB |
205 | static void |
206 | set_sim_regno (int *table, int gdb_regno, int sim_regno) | |
207 | { | |
208 | /* Make sure we don't try to assign any given GDB register a sim | |
209 | register number more than once. */ | |
210 | gdb_assert (table[gdb_regno] == -1); | |
211 | table[gdb_regno] = sim_regno; | |
212 | } | |
213 | ||
09991fa0 JB |
214 | |
215 | /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register | |
216 | numbers to simulator register numbers, based on the values placed | |
217 | in the ARCH->tdep->ppc_foo_regnum members. */ | |
9f643768 JB |
218 | static void |
219 | init_sim_regno_table (struct gdbarch *arch) | |
220 | { | |
221 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); | |
7cc46491 | 222 | int total_regs = gdbarch_num_regs (arch); |
9f643768 JB |
223 | int *sim_regno = GDBARCH_OBSTACK_CALLOC (arch, total_regs, int); |
224 | int i; | |
7cc46491 DJ |
225 | static const char *const segment_regs[] = { |
226 | "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7", | |
227 | "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15" | |
228 | }; | |
9f643768 JB |
229 | |
230 | /* Presume that all registers not explicitly mentioned below are | |
231 | unavailable from the sim. */ | |
232 | for (i = 0; i < total_regs; i++) | |
233 | sim_regno[i] = -1; | |
234 | ||
235 | /* General-purpose registers. */ | |
236 | for (i = 0; i < ppc_num_gprs; i++) | |
237 | set_sim_regno (sim_regno, tdep->ppc_gp0_regnum + i, sim_ppc_r0_regnum + i); | |
238 | ||
239 | /* Floating-point registers. */ | |
240 | if (tdep->ppc_fp0_regnum >= 0) | |
241 | for (i = 0; i < ppc_num_fprs; i++) | |
242 | set_sim_regno (sim_regno, | |
243 | tdep->ppc_fp0_regnum + i, | |
244 | sim_ppc_f0_regnum + i); | |
245 | if (tdep->ppc_fpscr_regnum >= 0) | |
246 | set_sim_regno (sim_regno, tdep->ppc_fpscr_regnum, sim_ppc_fpscr_regnum); | |
247 | ||
248 | set_sim_regno (sim_regno, gdbarch_pc_regnum (arch), sim_ppc_pc_regnum); | |
249 | set_sim_regno (sim_regno, tdep->ppc_ps_regnum, sim_ppc_ps_regnum); | |
250 | set_sim_regno (sim_regno, tdep->ppc_cr_regnum, sim_ppc_cr_regnum); | |
251 | ||
252 | /* Segment registers. */ | |
7cc46491 DJ |
253 | for (i = 0; i < ppc_num_srs; i++) |
254 | { | |
255 | int gdb_regno; | |
256 | ||
257 | gdb_regno = user_reg_map_name_to_regnum (arch, segment_regs[i], -1); | |
258 | if (gdb_regno >= 0) | |
259 | set_sim_regno (sim_regno, gdb_regno, sim_ppc_sr0_regnum + i); | |
260 | } | |
9f643768 JB |
261 | |
262 | /* Altivec registers. */ | |
263 | if (tdep->ppc_vr0_regnum >= 0) | |
264 | { | |
265 | for (i = 0; i < ppc_num_vrs; i++) | |
266 | set_sim_regno (sim_regno, | |
267 | tdep->ppc_vr0_regnum + i, | |
268 | sim_ppc_vr0_regnum + i); | |
269 | ||
270 | /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum, | |
271 | we can treat this more like the other cases. */ | |
272 | set_sim_regno (sim_regno, | |
273 | tdep->ppc_vr0_regnum + ppc_num_vrs, | |
274 | sim_ppc_vscr_regnum); | |
275 | } | |
276 | /* vsave is a special-purpose register, so the code below handles it. */ | |
277 | ||
278 | /* SPE APU (E500) registers. */ | |
6ced10dd JB |
279 | if (tdep->ppc_ev0_upper_regnum >= 0) |
280 | for (i = 0; i < ppc_num_gprs; i++) | |
281 | set_sim_regno (sim_regno, | |
282 | tdep->ppc_ev0_upper_regnum + i, | |
283 | sim_ppc_rh0_regnum + i); | |
9f643768 JB |
284 | if (tdep->ppc_acc_regnum >= 0) |
285 | set_sim_regno (sim_regno, tdep->ppc_acc_regnum, sim_ppc_acc_regnum); | |
286 | /* spefscr is a special-purpose register, so the code below handles it. */ | |
287 | ||
7cc46491 | 288 | #ifdef WITH_SIM |
9f643768 JB |
289 | /* Now handle all special-purpose registers. Verify that they |
290 | haven't mistakenly been assigned numbers by any of the above | |
7cc46491 DJ |
291 | code. */ |
292 | for (i = 0; i < sim_ppc_num_sprs; i++) | |
293 | { | |
294 | const char *spr_name = sim_spr_register_name (i); | |
295 | int gdb_regno = -1; | |
296 | ||
297 | if (spr_name != NULL) | |
298 | gdb_regno = user_reg_map_name_to_regnum (arch, spr_name, -1); | |
299 | ||
300 | if (gdb_regno != -1) | |
301 | set_sim_regno (sim_regno, gdb_regno, sim_ppc_spr0_regnum + i); | |
302 | } | |
303 | #endif | |
9f643768 JB |
304 | |
305 | /* Drop the initialized array into place. */ | |
306 | tdep->sim_regno = sim_regno; | |
307 | } | |
308 | ||
09991fa0 JB |
309 | |
310 | /* Given a GDB register number REG, return the corresponding SIM | |
311 | register number. */ | |
9f643768 JB |
312 | static int |
313 | rs6000_register_sim_regno (int reg) | |
314 | { | |
315 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
316 | int sim_regno; | |
317 | ||
7cc46491 DJ |
318 | if (tdep->sim_regno == NULL) |
319 | init_sim_regno_table (current_gdbarch); | |
320 | ||
f57d151a UW |
321 | gdb_assert (0 <= reg |
322 | && reg <= gdbarch_num_regs (current_gdbarch) | |
323 | + gdbarch_num_pseudo_regs (current_gdbarch)); | |
9f643768 JB |
324 | sim_regno = tdep->sim_regno[reg]; |
325 | ||
326 | if (sim_regno >= 0) | |
327 | return sim_regno; | |
328 | else | |
329 | return LEGACY_SIM_REGNO_IGNORE; | |
330 | } | |
331 | ||
d195bc9f MK |
332 | \f |
333 | ||
334 | /* Register set support functions. */ | |
335 | ||
f2db237a AM |
336 | /* REGS + OFFSET contains register REGNUM in a field REGSIZE wide. |
337 | Write the register to REGCACHE. */ | |
338 | ||
d195bc9f MK |
339 | static void |
340 | ppc_supply_reg (struct regcache *regcache, int regnum, | |
f2db237a | 341 | const gdb_byte *regs, size_t offset, int regsize) |
d195bc9f MK |
342 | { |
343 | if (regnum != -1 && offset != -1) | |
f2db237a AM |
344 | { |
345 | if (regsize > 4) | |
346 | { | |
347 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
348 | int gdb_regsize = register_size (gdbarch, regnum); | |
349 | if (gdb_regsize < regsize | |
350 | && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
351 | offset += regsize - gdb_regsize; | |
352 | } | |
353 | regcache_raw_supply (regcache, regnum, regs + offset); | |
354 | } | |
d195bc9f MK |
355 | } |
356 | ||
f2db237a AM |
357 | /* Read register REGNUM from REGCACHE and store to REGS + OFFSET |
358 | in a field REGSIZE wide. Zero pad as necessary. */ | |
359 | ||
d195bc9f MK |
360 | static void |
361 | ppc_collect_reg (const struct regcache *regcache, int regnum, | |
f2db237a | 362 | gdb_byte *regs, size_t offset, int regsize) |
d195bc9f MK |
363 | { |
364 | if (regnum != -1 && offset != -1) | |
f2db237a AM |
365 | { |
366 | if (regsize > 4) | |
367 | { | |
368 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
369 | int gdb_regsize = register_size (gdbarch, regnum); | |
370 | if (gdb_regsize < regsize) | |
371 | { | |
372 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
373 | { | |
374 | memset (regs + offset, 0, regsize - gdb_regsize); | |
375 | offset += regsize - gdb_regsize; | |
376 | } | |
377 | else | |
378 | memset (regs + offset + regsize - gdb_regsize, 0, | |
379 | regsize - gdb_regsize); | |
380 | } | |
381 | } | |
382 | regcache_raw_collect (regcache, regnum, regs + offset); | |
383 | } | |
d195bc9f MK |
384 | } |
385 | ||
f2db237a AM |
386 | static int |
387 | ppc_greg_offset (struct gdbarch *gdbarch, | |
388 | struct gdbarch_tdep *tdep, | |
389 | const struct ppc_reg_offsets *offsets, | |
390 | int regnum, | |
391 | int *regsize) | |
392 | { | |
393 | *regsize = offsets->gpr_size; | |
394 | if (regnum >= tdep->ppc_gp0_regnum | |
395 | && regnum < tdep->ppc_gp0_regnum + ppc_num_gprs) | |
396 | return (offsets->r0_offset | |
397 | + (regnum - tdep->ppc_gp0_regnum) * offsets->gpr_size); | |
398 | ||
399 | if (regnum == gdbarch_pc_regnum (gdbarch)) | |
400 | return offsets->pc_offset; | |
401 | ||
402 | if (regnum == tdep->ppc_ps_regnum) | |
403 | return offsets->ps_offset; | |
404 | ||
405 | if (regnum == tdep->ppc_lr_regnum) | |
406 | return offsets->lr_offset; | |
407 | ||
408 | if (regnum == tdep->ppc_ctr_regnum) | |
409 | return offsets->ctr_offset; | |
410 | ||
411 | *regsize = offsets->xr_size; | |
412 | if (regnum == tdep->ppc_cr_regnum) | |
413 | return offsets->cr_offset; | |
414 | ||
415 | if (regnum == tdep->ppc_xer_regnum) | |
416 | return offsets->xer_offset; | |
417 | ||
418 | if (regnum == tdep->ppc_mq_regnum) | |
419 | return offsets->mq_offset; | |
420 | ||
421 | return -1; | |
422 | } | |
423 | ||
424 | static int | |
425 | ppc_fpreg_offset (struct gdbarch_tdep *tdep, | |
426 | const struct ppc_reg_offsets *offsets, | |
427 | int regnum) | |
428 | { | |
429 | if (regnum >= tdep->ppc_fp0_regnum | |
430 | && regnum < tdep->ppc_fp0_regnum + ppc_num_fprs) | |
431 | return offsets->f0_offset + (regnum - tdep->ppc_fp0_regnum) * 8; | |
432 | ||
433 | if (regnum == tdep->ppc_fpscr_regnum) | |
434 | return offsets->fpscr_offset; | |
435 | ||
436 | return -1; | |
437 | } | |
438 | ||
d195bc9f MK |
439 | /* Supply register REGNUM in the general-purpose register set REGSET |
440 | from the buffer specified by GREGS and LEN to register cache | |
441 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
442 | ||
443 | void | |
444 | ppc_supply_gregset (const struct regset *regset, struct regcache *regcache, | |
445 | int regnum, const void *gregs, size_t len) | |
446 | { | |
447 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
448 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
449 | const struct ppc_reg_offsets *offsets = regset->descr; | |
450 | size_t offset; | |
f2db237a | 451 | int regsize; |
d195bc9f | 452 | |
f2db237a | 453 | if (regnum == -1) |
d195bc9f | 454 | { |
f2db237a AM |
455 | int i; |
456 | int gpr_size = offsets->gpr_size; | |
457 | ||
458 | for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset; | |
459 | i < tdep->ppc_gp0_regnum + ppc_num_gprs; | |
460 | i++, offset += gpr_size) | |
461 | ppc_supply_reg (regcache, i, gregs, offset, gpr_size); | |
462 | ||
463 | ppc_supply_reg (regcache, gdbarch_pc_regnum (gdbarch), | |
464 | gregs, offsets->pc_offset, gpr_size); | |
465 | ppc_supply_reg (regcache, tdep->ppc_ps_regnum, | |
466 | gregs, offsets->ps_offset, gpr_size); | |
467 | ppc_supply_reg (regcache, tdep->ppc_lr_regnum, | |
468 | gregs, offsets->lr_offset, gpr_size); | |
469 | ppc_supply_reg (regcache, tdep->ppc_ctr_regnum, | |
470 | gregs, offsets->ctr_offset, gpr_size); | |
471 | ppc_supply_reg (regcache, tdep->ppc_cr_regnum, | |
472 | gregs, offsets->cr_offset, offsets->xr_size); | |
473 | ppc_supply_reg (regcache, tdep->ppc_xer_regnum, | |
474 | gregs, offsets->xer_offset, offsets->xr_size); | |
475 | ppc_supply_reg (regcache, tdep->ppc_mq_regnum, | |
476 | gregs, offsets->mq_offset, offsets->xr_size); | |
477 | return; | |
d195bc9f MK |
478 | } |
479 | ||
f2db237a AM |
480 | offset = ppc_greg_offset (gdbarch, tdep, offsets, regnum, ®size); |
481 | ppc_supply_reg (regcache, regnum, gregs, offset, regsize); | |
d195bc9f MK |
482 | } |
483 | ||
484 | /* Supply register REGNUM in the floating-point register set REGSET | |
485 | from the buffer specified by FPREGS and LEN to register cache | |
486 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
487 | ||
488 | void | |
489 | ppc_supply_fpregset (const struct regset *regset, struct regcache *regcache, | |
490 | int regnum, const void *fpregs, size_t len) | |
491 | { | |
492 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
f2db237a AM |
493 | struct gdbarch_tdep *tdep; |
494 | const struct ppc_reg_offsets *offsets; | |
d195bc9f | 495 | size_t offset; |
d195bc9f | 496 | |
f2db237a AM |
497 | if (!ppc_floating_point_unit_p (gdbarch)) |
498 | return; | |
383f0f5b | 499 | |
f2db237a AM |
500 | tdep = gdbarch_tdep (gdbarch); |
501 | offsets = regset->descr; | |
502 | if (regnum == -1) | |
d195bc9f | 503 | { |
f2db237a AM |
504 | int i; |
505 | ||
506 | for (i = tdep->ppc_fp0_regnum, offset = offsets->f0_offset; | |
507 | i < tdep->ppc_fp0_regnum + ppc_num_fprs; | |
508 | i++, offset += 8) | |
509 | ppc_supply_reg (regcache, i, fpregs, offset, 8); | |
510 | ||
511 | ppc_supply_reg (regcache, tdep->ppc_fpscr_regnum, | |
512 | fpregs, offsets->fpscr_offset, offsets->fpscr_size); | |
513 | return; | |
d195bc9f MK |
514 | } |
515 | ||
f2db237a AM |
516 | offset = ppc_fpreg_offset (tdep, offsets, regnum); |
517 | ppc_supply_reg (regcache, regnum, fpregs, offset, | |
518 | regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8); | |
d195bc9f MK |
519 | } |
520 | ||
521 | /* Collect register REGNUM in the general-purpose register set | |
f2db237a | 522 | REGSET from register cache REGCACHE into the buffer specified by |
d195bc9f MK |
523 | GREGS and LEN. If REGNUM is -1, do this for all registers in |
524 | REGSET. */ | |
525 | ||
526 | void | |
527 | ppc_collect_gregset (const struct regset *regset, | |
528 | const struct regcache *regcache, | |
529 | int regnum, void *gregs, size_t len) | |
530 | { | |
531 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
532 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
533 | const struct ppc_reg_offsets *offsets = regset->descr; | |
534 | size_t offset; | |
f2db237a | 535 | int regsize; |
d195bc9f | 536 | |
f2db237a | 537 | if (regnum == -1) |
d195bc9f | 538 | { |
f2db237a AM |
539 | int i; |
540 | int gpr_size = offsets->gpr_size; | |
541 | ||
542 | for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset; | |
543 | i < tdep->ppc_gp0_regnum + ppc_num_gprs; | |
544 | i++, offset += gpr_size) | |
545 | ppc_collect_reg (regcache, i, gregs, offset, gpr_size); | |
546 | ||
547 | ppc_collect_reg (regcache, gdbarch_pc_regnum (gdbarch), | |
548 | gregs, offsets->pc_offset, gpr_size); | |
549 | ppc_collect_reg (regcache, tdep->ppc_ps_regnum, | |
550 | gregs, offsets->ps_offset, gpr_size); | |
551 | ppc_collect_reg (regcache, tdep->ppc_lr_regnum, | |
552 | gregs, offsets->lr_offset, gpr_size); | |
553 | ppc_collect_reg (regcache, tdep->ppc_ctr_regnum, | |
554 | gregs, offsets->ctr_offset, gpr_size); | |
555 | ppc_collect_reg (regcache, tdep->ppc_cr_regnum, | |
556 | gregs, offsets->cr_offset, offsets->xr_size); | |
557 | ppc_collect_reg (regcache, tdep->ppc_xer_regnum, | |
558 | gregs, offsets->xer_offset, offsets->xr_size); | |
559 | ppc_collect_reg (regcache, tdep->ppc_mq_regnum, | |
560 | gregs, offsets->mq_offset, offsets->xr_size); | |
561 | return; | |
d195bc9f MK |
562 | } |
563 | ||
f2db237a AM |
564 | offset = ppc_greg_offset (gdbarch, tdep, offsets, regnum, ®size); |
565 | ppc_collect_reg (regcache, regnum, gregs, offset, regsize); | |
d195bc9f MK |
566 | } |
567 | ||
568 | /* Collect register REGNUM in the floating-point register set | |
f2db237a | 569 | REGSET from register cache REGCACHE into the buffer specified by |
d195bc9f MK |
570 | FPREGS and LEN. If REGNUM is -1, do this for all registers in |
571 | REGSET. */ | |
572 | ||
573 | void | |
574 | ppc_collect_fpregset (const struct regset *regset, | |
575 | const struct regcache *regcache, | |
576 | int regnum, void *fpregs, size_t len) | |
577 | { | |
578 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
f2db237a AM |
579 | struct gdbarch_tdep *tdep; |
580 | const struct ppc_reg_offsets *offsets; | |
d195bc9f | 581 | size_t offset; |
d195bc9f | 582 | |
f2db237a AM |
583 | if (!ppc_floating_point_unit_p (gdbarch)) |
584 | return; | |
383f0f5b | 585 | |
f2db237a AM |
586 | tdep = gdbarch_tdep (gdbarch); |
587 | offsets = regset->descr; | |
588 | if (regnum == -1) | |
d195bc9f | 589 | { |
f2db237a AM |
590 | int i; |
591 | ||
592 | for (i = tdep->ppc_fp0_regnum, offset = offsets->f0_offset; | |
593 | i < tdep->ppc_fp0_regnum + ppc_num_fprs; | |
594 | i++, offset += 8) | |
595 | ppc_collect_reg (regcache, i, fpregs, offset, 8); | |
596 | ||
597 | ppc_collect_reg (regcache, tdep->ppc_fpscr_regnum, | |
598 | fpregs, offsets->fpscr_offset, offsets->fpscr_size); | |
599 | return; | |
d195bc9f MK |
600 | } |
601 | ||
f2db237a AM |
602 | offset = ppc_fpreg_offset (tdep, offsets, regnum); |
603 | ppc_collect_reg (regcache, regnum, fpregs, offset, | |
604 | regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8); | |
d195bc9f MK |
605 | } |
606 | \f | |
0a613259 | 607 | |
7a78ae4e | 608 | /* Read a LEN-byte address from debugged memory address MEMADDR. */ |
c906108c | 609 | |
7a78ae4e ND |
610 | static CORE_ADDR |
611 | read_memory_addr (CORE_ADDR memaddr, int len) | |
612 | { | |
613 | return read_memory_unsigned_integer (memaddr, len); | |
614 | } | |
c906108c | 615 | |
7a78ae4e ND |
616 | static CORE_ADDR |
617 | rs6000_skip_prologue (CORE_ADDR pc) | |
b83266a0 SS |
618 | { |
619 | struct rs6000_framedata frame; | |
4e463ff5 DJ |
620 | CORE_ADDR limit_pc, func_addr; |
621 | ||
622 | /* See if we can determine the end of the prologue via the symbol table. | |
623 | If so, then return either PC, or the PC after the prologue, whichever | |
624 | is greater. */ | |
625 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) | |
626 | { | |
627 | CORE_ADDR post_prologue_pc = skip_prologue_using_sal (func_addr); | |
628 | if (post_prologue_pc != 0) | |
629 | return max (pc, post_prologue_pc); | |
630 | } | |
631 | ||
632 | /* Can't determine prologue from the symbol table, need to examine | |
633 | instructions. */ | |
634 | ||
635 | /* Find an upper limit on the function prologue using the debug | |
636 | information. If the debug information could not be used to provide | |
637 | that bound, then use an arbitrary large number as the upper bound. */ | |
638 | limit_pc = skip_prologue_using_sal (pc); | |
639 | if (limit_pc == 0) | |
640 | limit_pc = pc + 100; /* Magic. */ | |
641 | ||
642 | pc = skip_prologue (pc, limit_pc, &frame); | |
b83266a0 SS |
643 | return pc; |
644 | } | |
645 | ||
0d1243d9 PG |
646 | static int |
647 | insn_changes_sp_or_jumps (unsigned long insn) | |
648 | { | |
649 | int opcode = (insn >> 26) & 0x03f; | |
650 | int sd = (insn >> 21) & 0x01f; | |
651 | int a = (insn >> 16) & 0x01f; | |
652 | int subcode = (insn >> 1) & 0x3ff; | |
653 | ||
654 | /* Changes the stack pointer. */ | |
655 | ||
656 | /* NOTE: There are many ways to change the value of a given register. | |
657 | The ways below are those used when the register is R1, the SP, | |
658 | in a funtion's epilogue. */ | |
659 | ||
660 | if (opcode == 31 && subcode == 444 && a == 1) | |
661 | return 1; /* mr R1,Rn */ | |
662 | if (opcode == 14 && sd == 1) | |
663 | return 1; /* addi R1,Rn,simm */ | |
664 | if (opcode == 58 && sd == 1) | |
665 | return 1; /* ld R1,ds(Rn) */ | |
666 | ||
667 | /* Transfers control. */ | |
668 | ||
669 | if (opcode == 18) | |
670 | return 1; /* b */ | |
671 | if (opcode == 16) | |
672 | return 1; /* bc */ | |
673 | if (opcode == 19 && subcode == 16) | |
674 | return 1; /* bclr */ | |
675 | if (opcode == 19 && subcode == 528) | |
676 | return 1; /* bcctr */ | |
677 | ||
678 | return 0; | |
679 | } | |
680 | ||
681 | /* Return true if we are in the function's epilogue, i.e. after the | |
682 | instruction that destroyed the function's stack frame. | |
683 | ||
684 | 1) scan forward from the point of execution: | |
685 | a) If you find an instruction that modifies the stack pointer | |
686 | or transfers control (except a return), execution is not in | |
687 | an epilogue, return. | |
688 | b) Stop scanning if you find a return instruction or reach the | |
689 | end of the function or reach the hard limit for the size of | |
690 | an epilogue. | |
691 | 2) scan backward from the point of execution: | |
692 | a) If you find an instruction that modifies the stack pointer, | |
693 | execution *is* in an epilogue, return. | |
694 | b) Stop scanning if you reach an instruction that transfers | |
695 | control or the beginning of the function or reach the hard | |
696 | limit for the size of an epilogue. */ | |
697 | ||
698 | static int | |
699 | rs6000_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
700 | { | |
701 | bfd_byte insn_buf[PPC_INSN_SIZE]; | |
702 | CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end; | |
703 | unsigned long insn; | |
704 | struct frame_info *curfrm; | |
705 | ||
706 | /* Find the search limits based on function boundaries and hard limit. */ | |
707 | ||
708 | if (!find_pc_partial_function (pc, NULL, &func_start, &func_end)) | |
709 | return 0; | |
710 | ||
711 | epilogue_start = pc - PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE; | |
712 | if (epilogue_start < func_start) epilogue_start = func_start; | |
713 | ||
714 | epilogue_end = pc + PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE; | |
715 | if (epilogue_end > func_end) epilogue_end = func_end; | |
716 | ||
717 | curfrm = get_current_frame (); | |
718 | ||
719 | /* Scan forward until next 'blr'. */ | |
720 | ||
721 | for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += PPC_INSN_SIZE) | |
722 | { | |
723 | if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE)) | |
724 | return 0; | |
4e463ff5 | 725 | insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE); |
0d1243d9 PG |
726 | if (insn == 0x4e800020) |
727 | break; | |
728 | if (insn_changes_sp_or_jumps (insn)) | |
729 | return 0; | |
730 | } | |
731 | ||
732 | /* Scan backward until adjustment to stack pointer (R1). */ | |
733 | ||
734 | for (scan_pc = pc - PPC_INSN_SIZE; | |
735 | scan_pc >= epilogue_start; | |
736 | scan_pc -= PPC_INSN_SIZE) | |
737 | { | |
738 | if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE)) | |
739 | return 0; | |
4e463ff5 | 740 | insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE); |
0d1243d9 PG |
741 | if (insn_changes_sp_or_jumps (insn)) |
742 | return 1; | |
743 | } | |
744 | ||
745 | return 0; | |
746 | } | |
747 | ||
143985b7 | 748 | /* Get the ith function argument for the current function. */ |
b9362cc7 | 749 | static CORE_ADDR |
143985b7 AF |
750 | rs6000_fetch_pointer_argument (struct frame_info *frame, int argi, |
751 | struct type *type) | |
752 | { | |
50fd1280 | 753 | return get_frame_register_unsigned (frame, 3 + argi); |
143985b7 AF |
754 | } |
755 | ||
c906108c SS |
756 | /* Calculate the destination of a branch/jump. Return -1 if not a branch. */ |
757 | ||
758 | static CORE_ADDR | |
0b1b3e42 UW |
759 | branch_dest (struct frame_info *frame, int opcode, int instr, |
760 | CORE_ADDR pc, CORE_ADDR safety) | |
c906108c | 761 | { |
0b1b3e42 | 762 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (frame)); |
c906108c SS |
763 | CORE_ADDR dest; |
764 | int immediate; | |
765 | int absolute; | |
766 | int ext_op; | |
767 | ||
768 | absolute = (int) ((instr >> 1) & 1); | |
769 | ||
c5aa993b JM |
770 | switch (opcode) |
771 | { | |
772 | case 18: | |
773 | immediate = ((instr & ~3) << 6) >> 6; /* br unconditional */ | |
774 | if (absolute) | |
775 | dest = immediate; | |
776 | else | |
777 | dest = pc + immediate; | |
778 | break; | |
779 | ||
780 | case 16: | |
781 | immediate = ((instr & ~3) << 16) >> 16; /* br conditional */ | |
782 | if (absolute) | |
783 | dest = immediate; | |
784 | else | |
785 | dest = pc + immediate; | |
786 | break; | |
787 | ||
788 | case 19: | |
789 | ext_op = (instr >> 1) & 0x3ff; | |
790 | ||
791 | if (ext_op == 16) /* br conditional register */ | |
792 | { | |
0b1b3e42 | 793 | dest = get_frame_register_unsigned (frame, tdep->ppc_lr_regnum) & ~3; |
c5aa993b JM |
794 | |
795 | /* If we are about to return from a signal handler, dest is | |
796 | something like 0x3c90. The current frame is a signal handler | |
797 | caller frame, upon completion of the sigreturn system call | |
798 | execution will return to the saved PC in the frame. */ | |
0b1b3e42 UW |
799 | if (dest < tdep->text_segment_base) |
800 | dest = read_memory_addr (get_frame_base (frame) + SIG_FRAME_PC_OFFSET, | |
801 | tdep->wordsize); | |
c5aa993b JM |
802 | } |
803 | ||
804 | else if (ext_op == 528) /* br cond to count reg */ | |
805 | { | |
0b1b3e42 | 806 | dest = get_frame_register_unsigned (frame, tdep->ppc_ctr_regnum) & ~3; |
c5aa993b JM |
807 | |
808 | /* If we are about to execute a system call, dest is something | |
809 | like 0x22fc or 0x3b00. Upon completion the system call | |
810 | will return to the address in the link register. */ | |
0b1b3e42 UW |
811 | if (dest < tdep->text_segment_base) |
812 | dest = get_frame_register_unsigned (frame, tdep->ppc_lr_regnum) & ~3; | |
c5aa993b JM |
813 | } |
814 | else | |
815 | return -1; | |
816 | break; | |
c906108c | 817 | |
c5aa993b JM |
818 | default: |
819 | return -1; | |
820 | } | |
0b1b3e42 | 821 | return (dest < tdep->text_segment_base) ? safety : dest; |
c906108c SS |
822 | } |
823 | ||
824 | ||
825 | /* Sequence of bytes for breakpoint instruction. */ | |
826 | ||
f4f9705a | 827 | const static unsigned char * |
7a78ae4e | 828 | rs6000_breakpoint_from_pc (CORE_ADDR *bp_addr, int *bp_size) |
c906108c | 829 | { |
aaab4dba AC |
830 | static unsigned char big_breakpoint[] = { 0x7d, 0x82, 0x10, 0x08 }; |
831 | static unsigned char little_breakpoint[] = { 0x08, 0x10, 0x82, 0x7d }; | |
c906108c | 832 | *bp_size = 4; |
4c6b5505 | 833 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
c906108c SS |
834 | return big_breakpoint; |
835 | else | |
836 | return little_breakpoint; | |
837 | } | |
838 | ||
839 | ||
ce5eab59 UW |
840 | /* Instruction masks used during single-stepping of atomic sequences. */ |
841 | #define LWARX_MASK 0xfc0007fe | |
842 | #define LWARX_INSTRUCTION 0x7c000028 | |
843 | #define LDARX_INSTRUCTION 0x7c0000A8 | |
844 | #define STWCX_MASK 0xfc0007ff | |
845 | #define STWCX_INSTRUCTION 0x7c00012d | |
846 | #define STDCX_INSTRUCTION 0x7c0001ad | |
847 | #define BC_MASK 0xfc000000 | |
848 | #define BC_INSTRUCTION 0x40000000 | |
849 | ||
850 | /* Checks for an atomic sequence of instructions beginning with a LWARX/LDARX | |
851 | instruction and ending with a STWCX/STDCX instruction. If such a sequence | |
852 | is found, attempt to step through it. A breakpoint is placed at the end of | |
853 | the sequence. */ | |
854 | ||
855 | static int | |
0b1b3e42 | 856 | deal_with_atomic_sequence (struct frame_info *frame) |
ce5eab59 | 857 | { |
0b1b3e42 | 858 | CORE_ADDR pc = get_frame_pc (frame); |
ce5eab59 UW |
859 | CORE_ADDR breaks[2] = {-1, -1}; |
860 | CORE_ADDR loc = pc; | |
861 | CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */ | |
24d45690 | 862 | CORE_ADDR closing_insn; /* Instruction that closes the atomic sequence. */ |
ce5eab59 UW |
863 | int insn = read_memory_integer (loc, PPC_INSN_SIZE); |
864 | int insn_count; | |
865 | int index; | |
866 | int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ | |
867 | const int atomic_sequence_length = 16; /* Instruction sequence length. */ | |
24d45690 | 868 | int opcode; /* Branch instruction's OPcode. */ |
ce5eab59 UW |
869 | int bc_insn_count = 0; /* Conditional branch instruction count. */ |
870 | ||
871 | /* Assume all atomic sequences start with a lwarx/ldarx instruction. */ | |
872 | if ((insn & LWARX_MASK) != LWARX_INSTRUCTION | |
873 | && (insn & LWARX_MASK) != LDARX_INSTRUCTION) | |
874 | return 0; | |
875 | ||
876 | /* Assume that no atomic sequence is longer than "atomic_sequence_length" | |
877 | instructions. */ | |
878 | for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) | |
879 | { | |
880 | loc += PPC_INSN_SIZE; | |
881 | insn = read_memory_integer (loc, PPC_INSN_SIZE); | |
882 | ||
883 | /* Assume that there is at most one conditional branch in the atomic | |
884 | sequence. If a conditional branch is found, put a breakpoint in | |
885 | its destination address. */ | |
886 | if ((insn & BC_MASK) == BC_INSTRUCTION) | |
887 | { | |
888 | if (bc_insn_count >= 1) | |
889 | return 0; /* More than one conditional branch found, fallback | |
890 | to the standard single-step code. */ | |
891 | ||
24d45690 | 892 | opcode = insn >> 26; |
0b1b3e42 | 893 | branch_bp = branch_dest (frame, opcode, insn, pc, breaks[0]); |
ce5eab59 UW |
894 | |
895 | if (branch_bp != -1) | |
896 | { | |
897 | breaks[1] = branch_bp; | |
898 | bc_insn_count++; | |
899 | last_breakpoint++; | |
900 | } | |
901 | } | |
902 | ||
903 | if ((insn & STWCX_MASK) == STWCX_INSTRUCTION | |
904 | || (insn & STWCX_MASK) == STDCX_INSTRUCTION) | |
905 | break; | |
906 | } | |
907 | ||
908 | /* Assume that the atomic sequence ends with a stwcx/stdcx instruction. */ | |
909 | if ((insn & STWCX_MASK) != STWCX_INSTRUCTION | |
910 | && (insn & STWCX_MASK) != STDCX_INSTRUCTION) | |
911 | return 0; | |
912 | ||
24d45690 | 913 | closing_insn = loc; |
ce5eab59 UW |
914 | loc += PPC_INSN_SIZE; |
915 | insn = read_memory_integer (loc, PPC_INSN_SIZE); | |
916 | ||
917 | /* Insert a breakpoint right after the end of the atomic sequence. */ | |
918 | breaks[0] = loc; | |
919 | ||
24d45690 UW |
920 | /* Check for duplicated breakpoints. Check also for a breakpoint |
921 | placed (branch instruction's destination) at the stwcx/stdcx | |
922 | instruction, this resets the reservation and take us back to the | |
923 | lwarx/ldarx instruction at the beginning of the atomic sequence. */ | |
924 | if (last_breakpoint && ((breaks[1] == breaks[0]) | |
925 | || (breaks[1] == closing_insn))) | |
ce5eab59 UW |
926 | last_breakpoint = 0; |
927 | ||
928 | /* Effectively inserts the breakpoints. */ | |
929 | for (index = 0; index <= last_breakpoint; index++) | |
930 | insert_single_step_breakpoint (breaks[index]); | |
931 | ||
932 | return 1; | |
933 | } | |
934 | ||
935 | /* AIX does not support PT_STEP. Simulate it. */ | |
c906108c | 936 | |
e6590a1b | 937 | int |
0b1b3e42 | 938 | rs6000_software_single_step (struct frame_info *frame) |
c906108c | 939 | { |
7c40d541 KB |
940 | CORE_ADDR dummy; |
941 | int breakp_sz; | |
50fd1280 | 942 | const gdb_byte *breakp = rs6000_breakpoint_from_pc (&dummy, &breakp_sz); |
c906108c SS |
943 | int ii, insn; |
944 | CORE_ADDR loc; | |
945 | CORE_ADDR breaks[2]; | |
946 | int opcode; | |
947 | ||
0b1b3e42 | 948 | loc = get_frame_pc (frame); |
c906108c | 949 | |
e0cd558a | 950 | insn = read_memory_integer (loc, 4); |
c906108c | 951 | |
0b1b3e42 | 952 | if (deal_with_atomic_sequence (frame)) |
ce5eab59 UW |
953 | return 1; |
954 | ||
e0cd558a UW |
955 | breaks[0] = loc + breakp_sz; |
956 | opcode = insn >> 26; | |
0b1b3e42 | 957 | breaks[1] = branch_dest (frame, opcode, insn, loc, breaks[0]); |
c906108c | 958 | |
e0cd558a UW |
959 | /* Don't put two breakpoints on the same address. */ |
960 | if (breaks[1] == breaks[0]) | |
961 | breaks[1] = -1; | |
c906108c | 962 | |
e0cd558a UW |
963 | for (ii = 0; ii < 2; ++ii) |
964 | { | |
965 | /* ignore invalid breakpoint. */ | |
966 | if (breaks[ii] == -1) | |
967 | continue; | |
968 | insert_single_step_breakpoint (breaks[ii]); | |
c5aa993b | 969 | } |
c906108c | 970 | |
c906108c | 971 | errno = 0; /* FIXME, don't ignore errors! */ |
c5aa993b | 972 | /* What errors? {read,write}_memory call error(). */ |
e6590a1b | 973 | return 1; |
c906108c SS |
974 | } |
975 | ||
976 | ||
c906108c SS |
977 | #define SIGNED_SHORT(x) \ |
978 | ((sizeof (short) == 2) \ | |
979 | ? ((int)(short)(x)) \ | |
980 | : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000))) | |
981 | ||
982 | #define GET_SRC_REG(x) (((x) >> 21) & 0x1f) | |
983 | ||
55d05f3b KB |
984 | /* Limit the number of skipped non-prologue instructions, as the examining |
985 | of the prologue is expensive. */ | |
986 | static int max_skip_non_prologue_insns = 10; | |
987 | ||
773df3e5 JB |
988 | /* Return nonzero if the given instruction OP can be part of the prologue |
989 | of a function and saves a parameter on the stack. FRAMEP should be | |
990 | set if one of the previous instructions in the function has set the | |
991 | Frame Pointer. */ | |
992 | ||
993 | static int | |
994 | store_param_on_stack_p (unsigned long op, int framep, int *r0_contains_arg) | |
995 | { | |
996 | /* Move parameters from argument registers to temporary register. */ | |
997 | if ((op & 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */ | |
998 | { | |
999 | /* Rx must be scratch register r0. */ | |
1000 | const int rx_regno = (op >> 16) & 31; | |
1001 | /* Ry: Only r3 - r10 are used for parameter passing. */ | |
1002 | const int ry_regno = GET_SRC_REG (op); | |
1003 | ||
1004 | if (rx_regno == 0 && ry_regno >= 3 && ry_regno <= 10) | |
1005 | { | |
1006 | *r0_contains_arg = 1; | |
1007 | return 1; | |
1008 | } | |
1009 | else | |
1010 | return 0; | |
1011 | } | |
1012 | ||
1013 | /* Save a General Purpose Register on stack. */ | |
1014 | ||
1015 | if ((op & 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */ | |
1016 | (op & 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */ | |
1017 | { | |
1018 | /* Rx: Only r3 - r10 are used for parameter passing. */ | |
1019 | const int rx_regno = GET_SRC_REG (op); | |
1020 | ||
1021 | return (rx_regno >= 3 && rx_regno <= 10); | |
1022 | } | |
1023 | ||
1024 | /* Save a General Purpose Register on stack via the Frame Pointer. */ | |
1025 | ||
1026 | if (framep && | |
1027 | ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */ | |
1028 | (op & 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */ | |
1029 | (op & 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */ | |
1030 | { | |
1031 | /* Rx: Usually, only r3 - r10 are used for parameter passing. | |
1032 | However, the compiler sometimes uses r0 to hold an argument. */ | |
1033 | const int rx_regno = GET_SRC_REG (op); | |
1034 | ||
1035 | return ((rx_regno >= 3 && rx_regno <= 10) | |
1036 | || (rx_regno == 0 && *r0_contains_arg)); | |
1037 | } | |
1038 | ||
1039 | if ((op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */ | |
1040 | { | |
1041 | /* Only f2 - f8 are used for parameter passing. */ | |
1042 | const int src_regno = GET_SRC_REG (op); | |
1043 | ||
1044 | return (src_regno >= 2 && src_regno <= 8); | |
1045 | } | |
1046 | ||
1047 | if (framep && ((op & 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */ | |
1048 | { | |
1049 | /* Only f2 - f8 are used for parameter passing. */ | |
1050 | const int src_regno = GET_SRC_REG (op); | |
1051 | ||
1052 | return (src_regno >= 2 && src_regno <= 8); | |
1053 | } | |
1054 | ||
1055 | /* Not an insn that saves a parameter on stack. */ | |
1056 | return 0; | |
1057 | } | |
55d05f3b | 1058 | |
3c77c82a DJ |
1059 | /* Assuming that INSN is a "bl" instruction located at PC, return |
1060 | nonzero if the destination of the branch is a "blrl" instruction. | |
1061 | ||
1062 | This sequence is sometimes found in certain function prologues. | |
1063 | It allows the function to load the LR register with a value that | |
1064 | they can use to access PIC data using PC-relative offsets. */ | |
1065 | ||
1066 | static int | |
1067 | bl_to_blrl_insn_p (CORE_ADDR pc, int insn) | |
1068 | { | |
0b1b3e42 UW |
1069 | CORE_ADDR dest; |
1070 | int immediate; | |
1071 | int absolute; | |
3c77c82a DJ |
1072 | int dest_insn; |
1073 | ||
0b1b3e42 UW |
1074 | absolute = (int) ((insn >> 1) & 1); |
1075 | immediate = ((insn & ~3) << 6) >> 6; | |
1076 | if (absolute) | |
1077 | dest = immediate; | |
1078 | else | |
1079 | dest = pc + immediate; | |
1080 | ||
3c77c82a DJ |
1081 | dest_insn = read_memory_integer (dest, 4); |
1082 | if ((dest_insn & 0xfc00ffff) == 0x4c000021) /* blrl */ | |
1083 | return 1; | |
1084 | ||
1085 | return 0; | |
1086 | } | |
1087 | ||
6a16c029 TJB |
1088 | /* return pc value after skipping a function prologue and also return |
1089 | information about a function frame. | |
1090 | ||
1091 | in struct rs6000_framedata fdata: | |
1092 | - frameless is TRUE, if function does not have a frame. | |
1093 | - nosavedpc is TRUE, if function does not save %pc value in its frame. | |
1094 | - offset is the initial size of this stack frame --- the amount by | |
1095 | which we decrement the sp to allocate the frame. | |
1096 | - saved_gpr is the number of the first saved gpr. | |
1097 | - saved_fpr is the number of the first saved fpr. | |
1098 | - saved_vr is the number of the first saved vr. | |
1099 | - saved_ev is the number of the first saved ev. | |
1100 | - alloca_reg is the number of the register used for alloca() handling. | |
1101 | Otherwise -1. | |
1102 | - gpr_offset is the offset of the first saved gpr from the previous frame. | |
1103 | - fpr_offset is the offset of the first saved fpr from the previous frame. | |
1104 | - vr_offset is the offset of the first saved vr from the previous frame. | |
1105 | - ev_offset is the offset of the first saved ev from the previous frame. | |
1106 | - lr_offset is the offset of the saved lr | |
1107 | - cr_offset is the offset of the saved cr | |
1108 | - vrsave_offset is the offset of the saved vrsave register | |
1109 | */ | |
1110 | ||
7a78ae4e | 1111 | static CORE_ADDR |
077276e8 | 1112 | skip_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct rs6000_framedata *fdata) |
c906108c SS |
1113 | { |
1114 | CORE_ADDR orig_pc = pc; | |
55d05f3b | 1115 | CORE_ADDR last_prologue_pc = pc; |
6be8bc0c | 1116 | CORE_ADDR li_found_pc = 0; |
50fd1280 | 1117 | gdb_byte buf[4]; |
c906108c SS |
1118 | unsigned long op; |
1119 | long offset = 0; | |
6be8bc0c | 1120 | long vr_saved_offset = 0; |
482ca3f5 KB |
1121 | int lr_reg = -1; |
1122 | int cr_reg = -1; | |
6be8bc0c | 1123 | int vr_reg = -1; |
96ff0de4 EZ |
1124 | int ev_reg = -1; |
1125 | long ev_offset = 0; | |
6be8bc0c | 1126 | int vrsave_reg = -1; |
c906108c SS |
1127 | int reg; |
1128 | int framep = 0; | |
1129 | int minimal_toc_loaded = 0; | |
ddb20c56 | 1130 | int prev_insn_was_prologue_insn = 1; |
55d05f3b | 1131 | int num_skip_non_prologue_insns = 0; |
773df3e5 | 1132 | int r0_contains_arg = 0; |
96ff0de4 | 1133 | const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (current_gdbarch); |
6f99cb26 | 1134 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c | 1135 | |
ddb20c56 | 1136 | memset (fdata, 0, sizeof (struct rs6000_framedata)); |
c906108c SS |
1137 | fdata->saved_gpr = -1; |
1138 | fdata->saved_fpr = -1; | |
6be8bc0c | 1139 | fdata->saved_vr = -1; |
96ff0de4 | 1140 | fdata->saved_ev = -1; |
c906108c SS |
1141 | fdata->alloca_reg = -1; |
1142 | fdata->frameless = 1; | |
1143 | fdata->nosavedpc = 1; | |
1144 | ||
55d05f3b | 1145 | for (;; pc += 4) |
c906108c | 1146 | { |
ddb20c56 KB |
1147 | /* Sometimes it isn't clear if an instruction is a prologue |
1148 | instruction or not. When we encounter one of these ambiguous | |
1149 | cases, we'll set prev_insn_was_prologue_insn to 0 (false). | |
1150 | Otherwise, we'll assume that it really is a prologue instruction. */ | |
1151 | if (prev_insn_was_prologue_insn) | |
1152 | last_prologue_pc = pc; | |
55d05f3b KB |
1153 | |
1154 | /* Stop scanning if we've hit the limit. */ | |
4e463ff5 | 1155 | if (pc >= lim_pc) |
55d05f3b KB |
1156 | break; |
1157 | ||
ddb20c56 KB |
1158 | prev_insn_was_prologue_insn = 1; |
1159 | ||
55d05f3b | 1160 | /* Fetch the instruction and convert it to an integer. */ |
ddb20c56 KB |
1161 | if (target_read_memory (pc, buf, 4)) |
1162 | break; | |
4e463ff5 | 1163 | op = extract_unsigned_integer (buf, 4); |
c906108c | 1164 | |
c5aa993b JM |
1165 | if ((op & 0xfc1fffff) == 0x7c0802a6) |
1166 | { /* mflr Rx */ | |
43b1ab88 AC |
1167 | /* Since shared library / PIC code, which needs to get its |
1168 | address at runtime, can appear to save more than one link | |
1169 | register vis: | |
1170 | ||
1171 | *INDENT-OFF* | |
1172 | stwu r1,-304(r1) | |
1173 | mflr r3 | |
1174 | bl 0xff570d0 (blrl) | |
1175 | stw r30,296(r1) | |
1176 | mflr r30 | |
1177 | stw r31,300(r1) | |
1178 | stw r3,308(r1); | |
1179 | ... | |
1180 | *INDENT-ON* | |
1181 | ||
1182 | remember just the first one, but skip over additional | |
1183 | ones. */ | |
721d14ba | 1184 | if (lr_reg == -1) |
43b1ab88 | 1185 | lr_reg = (op & 0x03e00000); |
773df3e5 JB |
1186 | if (lr_reg == 0) |
1187 | r0_contains_arg = 0; | |
c5aa993b | 1188 | continue; |
c5aa993b JM |
1189 | } |
1190 | else if ((op & 0xfc1fffff) == 0x7c000026) | |
1191 | { /* mfcr Rx */ | |
98f08d3d | 1192 | cr_reg = (op & 0x03e00000); |
773df3e5 JB |
1193 | if (cr_reg == 0) |
1194 | r0_contains_arg = 0; | |
c5aa993b | 1195 | continue; |
c906108c | 1196 | |
c906108c | 1197 | } |
c5aa993b JM |
1198 | else if ((op & 0xfc1f0000) == 0xd8010000) |
1199 | { /* stfd Rx,NUM(r1) */ | |
1200 | reg = GET_SRC_REG (op); | |
1201 | if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg) | |
1202 | { | |
1203 | fdata->saved_fpr = reg; | |
1204 | fdata->fpr_offset = SIGNED_SHORT (op) + offset; | |
1205 | } | |
1206 | continue; | |
c906108c | 1207 | |
c5aa993b JM |
1208 | } |
1209 | else if (((op & 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */ | |
7a78ae4e ND |
1210 | (((op & 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */ |
1211 | (op & 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */ | |
1212 | (op & 0x03e00000) >= 0x01a00000)) /* rx >= r13 */ | |
c5aa993b JM |
1213 | { |
1214 | ||
1215 | reg = GET_SRC_REG (op); | |
1216 | if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg) | |
1217 | { | |
1218 | fdata->saved_gpr = reg; | |
7a78ae4e | 1219 | if ((op & 0xfc1f0003) == 0xf8010000) |
98f08d3d | 1220 | op &= ~3UL; |
c5aa993b JM |
1221 | fdata->gpr_offset = SIGNED_SHORT (op) + offset; |
1222 | } | |
1223 | continue; | |
c906108c | 1224 | |
ddb20c56 KB |
1225 | } |
1226 | else if ((op & 0xffff0000) == 0x60000000) | |
1227 | { | |
96ff0de4 | 1228 | /* nop */ |
ddb20c56 KB |
1229 | /* Allow nops in the prologue, but do not consider them to |
1230 | be part of the prologue unless followed by other prologue | |
1231 | instructions. */ | |
1232 | prev_insn_was_prologue_insn = 0; | |
1233 | continue; | |
1234 | ||
c906108c | 1235 | } |
c5aa993b JM |
1236 | else if ((op & 0xffff0000) == 0x3c000000) |
1237 | { /* addis 0,0,NUM, used | |
1238 | for >= 32k frames */ | |
1239 | fdata->offset = (op & 0x0000ffff) << 16; | |
1240 | fdata->frameless = 0; | |
773df3e5 | 1241 | r0_contains_arg = 0; |
c5aa993b JM |
1242 | continue; |
1243 | ||
1244 | } | |
1245 | else if ((op & 0xffff0000) == 0x60000000) | |
1246 | { /* ori 0,0,NUM, 2nd ha | |
1247 | lf of >= 32k frames */ | |
1248 | fdata->offset |= (op & 0x0000ffff); | |
1249 | fdata->frameless = 0; | |
773df3e5 | 1250 | r0_contains_arg = 0; |
c5aa993b JM |
1251 | continue; |
1252 | ||
1253 | } | |
be723e22 | 1254 | else if (lr_reg >= 0 && |
98f08d3d KB |
1255 | /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */ |
1256 | (((op & 0xffff0000) == (lr_reg | 0xf8010000)) || | |
1257 | /* stw Rx, NUM(r1) */ | |
1258 | ((op & 0xffff0000) == (lr_reg | 0x90010000)) || | |
1259 | /* stwu Rx, NUM(r1) */ | |
1260 | ((op & 0xffff0000) == (lr_reg | 0x94010000)))) | |
1261 | { /* where Rx == lr */ | |
1262 | fdata->lr_offset = offset; | |
c5aa993b | 1263 | fdata->nosavedpc = 0; |
be723e22 MS |
1264 | /* Invalidate lr_reg, but don't set it to -1. |
1265 | That would mean that it had never been set. */ | |
1266 | lr_reg = -2; | |
98f08d3d KB |
1267 | if ((op & 0xfc000003) == 0xf8000000 || /* std */ |
1268 | (op & 0xfc000000) == 0x90000000) /* stw */ | |
1269 | { | |
1270 | /* Does not update r1, so add displacement to lr_offset. */ | |
1271 | fdata->lr_offset += SIGNED_SHORT (op); | |
1272 | } | |
c5aa993b JM |
1273 | continue; |
1274 | ||
1275 | } | |
be723e22 | 1276 | else if (cr_reg >= 0 && |
98f08d3d KB |
1277 | /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */ |
1278 | (((op & 0xffff0000) == (cr_reg | 0xf8010000)) || | |
1279 | /* stw Rx, NUM(r1) */ | |
1280 | ((op & 0xffff0000) == (cr_reg | 0x90010000)) || | |
1281 | /* stwu Rx, NUM(r1) */ | |
1282 | ((op & 0xffff0000) == (cr_reg | 0x94010000)))) | |
1283 | { /* where Rx == cr */ | |
1284 | fdata->cr_offset = offset; | |
be723e22 MS |
1285 | /* Invalidate cr_reg, but don't set it to -1. |
1286 | That would mean that it had never been set. */ | |
1287 | cr_reg = -2; | |
98f08d3d KB |
1288 | if ((op & 0xfc000003) == 0xf8000000 || |
1289 | (op & 0xfc000000) == 0x90000000) | |
1290 | { | |
1291 | /* Does not update r1, so add displacement to cr_offset. */ | |
1292 | fdata->cr_offset += SIGNED_SHORT (op); | |
1293 | } | |
c5aa993b JM |
1294 | continue; |
1295 | ||
1296 | } | |
721d14ba DJ |
1297 | else if ((op & 0xfe80ffff) == 0x42800005 && lr_reg != -1) |
1298 | { | |
1299 | /* bcl 20,xx,.+4 is used to get the current PC, with or without | |
1300 | prediction bits. If the LR has already been saved, we can | |
1301 | skip it. */ | |
1302 | continue; | |
1303 | } | |
c5aa993b JM |
1304 | else if (op == 0x48000005) |
1305 | { /* bl .+4 used in | |
1306 | -mrelocatable */ | |
1307 | continue; | |
1308 | ||
1309 | } | |
1310 | else if (op == 0x48000004) | |
1311 | { /* b .+4 (xlc) */ | |
1312 | break; | |
1313 | ||
c5aa993b | 1314 | } |
6be8bc0c EZ |
1315 | else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used |
1316 | in V.4 -mminimal-toc */ | |
c5aa993b JM |
1317 | (op & 0xffff0000) == 0x3bde0000) |
1318 | { /* addi 30,30,foo@l */ | |
1319 | continue; | |
c906108c | 1320 | |
c5aa993b JM |
1321 | } |
1322 | else if ((op & 0xfc000001) == 0x48000001) | |
1323 | { /* bl foo, | |
1324 | to save fprs??? */ | |
c906108c | 1325 | |
c5aa993b | 1326 | fdata->frameless = 0; |
3c77c82a DJ |
1327 | |
1328 | /* If the return address has already been saved, we can skip | |
1329 | calls to blrl (for PIC). */ | |
1330 | if (lr_reg != -1 && bl_to_blrl_insn_p (pc, op)) | |
1331 | continue; | |
1332 | ||
6be8bc0c | 1333 | /* Don't skip over the subroutine call if it is not within |
ebd98106 FF |
1334 | the first three instructions of the prologue and either |
1335 | we have no line table information or the line info tells | |
1336 | us that the subroutine call is not part of the line | |
1337 | associated with the prologue. */ | |
c5aa993b | 1338 | if ((pc - orig_pc) > 8) |
ebd98106 FF |
1339 | { |
1340 | struct symtab_and_line prologue_sal = find_pc_line (orig_pc, 0); | |
1341 | struct symtab_and_line this_sal = find_pc_line (pc, 0); | |
1342 | ||
1343 | if ((prologue_sal.line == 0) || (prologue_sal.line != this_sal.line)) | |
1344 | break; | |
1345 | } | |
c5aa993b JM |
1346 | |
1347 | op = read_memory_integer (pc + 4, 4); | |
1348 | ||
6be8bc0c EZ |
1349 | /* At this point, make sure this is not a trampoline |
1350 | function (a function that simply calls another functions, | |
1351 | and nothing else). If the next is not a nop, this branch | |
1352 | was part of the function prologue. */ | |
c5aa993b JM |
1353 | |
1354 | if (op == 0x4def7b82 || op == 0) /* crorc 15, 15, 15 */ | |
1355 | break; /* don't skip over | |
1356 | this branch */ | |
1357 | continue; | |
1358 | ||
c5aa993b | 1359 | } |
98f08d3d KB |
1360 | /* update stack pointer */ |
1361 | else if ((op & 0xfc1f0000) == 0x94010000) | |
1362 | { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */ | |
c5aa993b JM |
1363 | fdata->frameless = 0; |
1364 | fdata->offset = SIGNED_SHORT (op); | |
1365 | offset = fdata->offset; | |
1366 | continue; | |
c5aa993b | 1367 | } |
98f08d3d KB |
1368 | else if ((op & 0xfc1f016a) == 0x7c01016e) |
1369 | { /* stwux rX,r1,rY */ | |
1370 | /* no way to figure out what r1 is going to be */ | |
1371 | fdata->frameless = 0; | |
1372 | offset = fdata->offset; | |
1373 | continue; | |
1374 | } | |
1375 | else if ((op & 0xfc1f0003) == 0xf8010001) | |
1376 | { /* stdu rX,NUM(r1) */ | |
1377 | fdata->frameless = 0; | |
1378 | fdata->offset = SIGNED_SHORT (op & ~3UL); | |
1379 | offset = fdata->offset; | |
1380 | continue; | |
1381 | } | |
1382 | else if ((op & 0xfc1f016a) == 0x7c01016a) | |
1383 | { /* stdux rX,r1,rY */ | |
1384 | /* no way to figure out what r1 is going to be */ | |
c5aa993b JM |
1385 | fdata->frameless = 0; |
1386 | offset = fdata->offset; | |
1387 | continue; | |
c5aa993b | 1388 | } |
7313566f FF |
1389 | else if ((op & 0xffff0000) == 0x38210000) |
1390 | { /* addi r1,r1,SIMM */ | |
1391 | fdata->frameless = 0; | |
1392 | fdata->offset += SIGNED_SHORT (op); | |
1393 | offset = fdata->offset; | |
1394 | continue; | |
1395 | } | |
4e463ff5 DJ |
1396 | /* Load up minimal toc pointer. Do not treat an epilogue restore |
1397 | of r31 as a minimal TOC load. */ | |
98f08d3d KB |
1398 | else if (((op >> 22) == 0x20f || /* l r31,... or l r30,... */ |
1399 | (op >> 22) == 0x3af) /* ld r31,... or ld r30,... */ | |
4e463ff5 | 1400 | && !framep |
c5aa993b | 1401 | && !minimal_toc_loaded) |
98f08d3d | 1402 | { |
c5aa993b JM |
1403 | minimal_toc_loaded = 1; |
1404 | continue; | |
1405 | ||
f6077098 KB |
1406 | /* move parameters from argument registers to local variable |
1407 | registers */ | |
1408 | } | |
1409 | else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */ | |
1410 | (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */ | |
1411 | (((op >> 21) & 31) <= 10) && | |
96ff0de4 | 1412 | ((long) ((op >> 16) & 31) >= fdata->saved_gpr)) /* Rx: local var reg */ |
f6077098 KB |
1413 | { |
1414 | continue; | |
1415 | ||
c5aa993b JM |
1416 | /* store parameters in stack */ |
1417 | } | |
e802b915 | 1418 | /* Move parameters from argument registers to temporary register. */ |
773df3e5 | 1419 | else if (store_param_on_stack_p (op, framep, &r0_contains_arg)) |
e802b915 | 1420 | { |
c5aa993b JM |
1421 | continue; |
1422 | ||
1423 | /* Set up frame pointer */ | |
1424 | } | |
1425 | else if (op == 0x603f0000 /* oril r31, r1, 0x0 */ | |
1426 | || op == 0x7c3f0b78) | |
1427 | { /* mr r31, r1 */ | |
1428 | fdata->frameless = 0; | |
1429 | framep = 1; | |
6f99cb26 | 1430 | fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31); |
c5aa993b JM |
1431 | continue; |
1432 | ||
1433 | /* Another way to set up the frame pointer. */ | |
1434 | } | |
1435 | else if ((op & 0xfc1fffff) == 0x38010000) | |
1436 | { /* addi rX, r1, 0x0 */ | |
1437 | fdata->frameless = 0; | |
1438 | framep = 1; | |
6f99cb26 AC |
1439 | fdata->alloca_reg = (tdep->ppc_gp0_regnum |
1440 | + ((op & ~0x38010000) >> 21)); | |
c5aa993b | 1441 | continue; |
c5aa993b | 1442 | } |
6be8bc0c EZ |
1443 | /* AltiVec related instructions. */ |
1444 | /* Store the vrsave register (spr 256) in another register for | |
1445 | later manipulation, or load a register into the vrsave | |
1446 | register. 2 instructions are used: mfvrsave and | |
1447 | mtvrsave. They are shorthand notation for mfspr Rn, SPR256 | |
1448 | and mtspr SPR256, Rn. */ | |
1449 | /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110 | |
1450 | mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */ | |
1451 | else if ((op & 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */ | |
1452 | { | |
1453 | vrsave_reg = GET_SRC_REG (op); | |
1454 | continue; | |
1455 | } | |
1456 | else if ((op & 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */ | |
1457 | { | |
1458 | continue; | |
1459 | } | |
1460 | /* Store the register where vrsave was saved to onto the stack: | |
1461 | rS is the register where vrsave was stored in a previous | |
1462 | instruction. */ | |
1463 | /* 100100 sssss 00001 dddddddd dddddddd */ | |
1464 | else if ((op & 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */ | |
1465 | { | |
1466 | if (vrsave_reg == GET_SRC_REG (op)) | |
1467 | { | |
1468 | fdata->vrsave_offset = SIGNED_SHORT (op) + offset; | |
1469 | vrsave_reg = -1; | |
1470 | } | |
1471 | continue; | |
1472 | } | |
1473 | /* Compute the new value of vrsave, by modifying the register | |
1474 | where vrsave was saved to. */ | |
1475 | else if (((op & 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */ | |
1476 | || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */ | |
1477 | { | |
1478 | continue; | |
1479 | } | |
1480 | /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first | |
1481 | in a pair of insns to save the vector registers on the | |
1482 | stack. */ | |
1483 | /* 001110 00000 00000 iiii iiii iiii iiii */ | |
96ff0de4 EZ |
1484 | /* 001110 01110 00000 iiii iiii iiii iiii */ |
1485 | else if ((op & 0xffff0000) == 0x38000000 /* li r0, SIMM */ | |
1486 | || (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */ | |
6be8bc0c | 1487 | { |
773df3e5 JB |
1488 | if ((op & 0xffff0000) == 0x38000000) |
1489 | r0_contains_arg = 0; | |
6be8bc0c EZ |
1490 | li_found_pc = pc; |
1491 | vr_saved_offset = SIGNED_SHORT (op); | |
773df3e5 JB |
1492 | |
1493 | /* This insn by itself is not part of the prologue, unless | |
1494 | if part of the pair of insns mentioned above. So do not | |
1495 | record this insn as part of the prologue yet. */ | |
1496 | prev_insn_was_prologue_insn = 0; | |
6be8bc0c EZ |
1497 | } |
1498 | /* Store vector register S at (r31+r0) aligned to 16 bytes. */ | |
1499 | /* 011111 sssss 11111 00000 00111001110 */ | |
1500 | else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */ | |
1501 | { | |
1502 | if (pc == (li_found_pc + 4)) | |
1503 | { | |
1504 | vr_reg = GET_SRC_REG (op); | |
1505 | /* If this is the first vector reg to be saved, or if | |
1506 | it has a lower number than others previously seen, | |
1507 | reupdate the frame info. */ | |
1508 | if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg) | |
1509 | { | |
1510 | fdata->saved_vr = vr_reg; | |
1511 | fdata->vr_offset = vr_saved_offset + offset; | |
1512 | } | |
1513 | vr_saved_offset = -1; | |
1514 | vr_reg = -1; | |
1515 | li_found_pc = 0; | |
1516 | } | |
1517 | } | |
1518 | /* End AltiVec related instructions. */ | |
96ff0de4 EZ |
1519 | |
1520 | /* Start BookE related instructions. */ | |
1521 | /* Store gen register S at (r31+uimm). | |
1522 | Any register less than r13 is volatile, so we don't care. */ | |
1523 | /* 000100 sssss 11111 iiiii 01100100001 */ | |
1524 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
1525 | && (op & 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */ | |
1526 | { | |
1527 | if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */ | |
1528 | { | |
1529 | unsigned int imm; | |
1530 | ev_reg = GET_SRC_REG (op); | |
1531 | imm = (op >> 11) & 0x1f; | |
1532 | ev_offset = imm * 8; | |
1533 | /* If this is the first vector reg to be saved, or if | |
1534 | it has a lower number than others previously seen, | |
1535 | reupdate the frame info. */ | |
1536 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) | |
1537 | { | |
1538 | fdata->saved_ev = ev_reg; | |
1539 | fdata->ev_offset = ev_offset + offset; | |
1540 | } | |
1541 | } | |
1542 | continue; | |
1543 | } | |
1544 | /* Store gen register rS at (r1+rB). */ | |
1545 | /* 000100 sssss 00001 bbbbb 01100100000 */ | |
1546 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
1547 | && (op & 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */ | |
1548 | { | |
1549 | if (pc == (li_found_pc + 4)) | |
1550 | { | |
1551 | ev_reg = GET_SRC_REG (op); | |
1552 | /* If this is the first vector reg to be saved, or if | |
1553 | it has a lower number than others previously seen, | |
1554 | reupdate the frame info. */ | |
1555 | /* We know the contents of rB from the previous instruction. */ | |
1556 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) | |
1557 | { | |
1558 | fdata->saved_ev = ev_reg; | |
1559 | fdata->ev_offset = vr_saved_offset + offset; | |
1560 | } | |
1561 | vr_saved_offset = -1; | |
1562 | ev_reg = -1; | |
1563 | li_found_pc = 0; | |
1564 | } | |
1565 | continue; | |
1566 | } | |
1567 | /* Store gen register r31 at (rA+uimm). */ | |
1568 | /* 000100 11111 aaaaa iiiii 01100100001 */ | |
1569 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
1570 | && (op & 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */ | |
1571 | { | |
1572 | /* Wwe know that the source register is 31 already, but | |
1573 | it can't hurt to compute it. */ | |
1574 | ev_reg = GET_SRC_REG (op); | |
1575 | ev_offset = ((op >> 11) & 0x1f) * 8; | |
1576 | /* If this is the first vector reg to be saved, or if | |
1577 | it has a lower number than others previously seen, | |
1578 | reupdate the frame info. */ | |
1579 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) | |
1580 | { | |
1581 | fdata->saved_ev = ev_reg; | |
1582 | fdata->ev_offset = ev_offset + offset; | |
1583 | } | |
1584 | ||
1585 | continue; | |
1586 | } | |
1587 | /* Store gen register S at (r31+r0). | |
1588 | Store param on stack when offset from SP bigger than 4 bytes. */ | |
1589 | /* 000100 sssss 11111 00000 01100100000 */ | |
1590 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
1591 | && (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */ | |
1592 | { | |
1593 | if (pc == (li_found_pc + 4)) | |
1594 | { | |
1595 | if ((op & 0x03e00000) >= 0x01a00000) | |
1596 | { | |
1597 | ev_reg = GET_SRC_REG (op); | |
1598 | /* If this is the first vector reg to be saved, or if | |
1599 | it has a lower number than others previously seen, | |
1600 | reupdate the frame info. */ | |
1601 | /* We know the contents of r0 from the previous | |
1602 | instruction. */ | |
1603 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) | |
1604 | { | |
1605 | fdata->saved_ev = ev_reg; | |
1606 | fdata->ev_offset = vr_saved_offset + offset; | |
1607 | } | |
1608 | ev_reg = -1; | |
1609 | } | |
1610 | vr_saved_offset = -1; | |
1611 | li_found_pc = 0; | |
1612 | continue; | |
1613 | } | |
1614 | } | |
1615 | /* End BookE related instructions. */ | |
1616 | ||
c5aa993b JM |
1617 | else |
1618 | { | |
55d05f3b KB |
1619 | /* Not a recognized prologue instruction. |
1620 | Handle optimizer code motions into the prologue by continuing | |
1621 | the search if we have no valid frame yet or if the return | |
1622 | address is not yet saved in the frame. */ | |
4e463ff5 | 1623 | if (fdata->frameless == 0 && fdata->nosavedpc == 0) |
55d05f3b KB |
1624 | break; |
1625 | ||
1626 | if (op == 0x4e800020 /* blr */ | |
1627 | || op == 0x4e800420) /* bctr */ | |
1628 | /* Do not scan past epilogue in frameless functions or | |
1629 | trampolines. */ | |
1630 | break; | |
1631 | if ((op & 0xf4000000) == 0x40000000) /* bxx */ | |
64366f1c | 1632 | /* Never skip branches. */ |
55d05f3b KB |
1633 | break; |
1634 | ||
1635 | if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns) | |
1636 | /* Do not scan too many insns, scanning insns is expensive with | |
1637 | remote targets. */ | |
1638 | break; | |
1639 | ||
1640 | /* Continue scanning. */ | |
1641 | prev_insn_was_prologue_insn = 0; | |
1642 | continue; | |
c5aa993b | 1643 | } |
c906108c SS |
1644 | } |
1645 | ||
1646 | #if 0 | |
1647 | /* I have problems with skipping over __main() that I need to address | |
1648 | * sometime. Previously, I used to use misc_function_vector which | |
1649 | * didn't work as well as I wanted to be. -MGO */ | |
1650 | ||
1651 | /* If the first thing after skipping a prolog is a branch to a function, | |
1652 | this might be a call to an initializer in main(), introduced by gcc2. | |
64366f1c | 1653 | We'd like to skip over it as well. Fortunately, xlc does some extra |
c906108c | 1654 | work before calling a function right after a prologue, thus we can |
64366f1c | 1655 | single out such gcc2 behaviour. */ |
c906108c | 1656 | |
c906108c | 1657 | |
c5aa993b JM |
1658 | if ((op & 0xfc000001) == 0x48000001) |
1659 | { /* bl foo, an initializer function? */ | |
1660 | op = read_memory_integer (pc + 4, 4); | |
1661 | ||
1662 | if (op == 0x4def7b82) | |
1663 | { /* cror 0xf, 0xf, 0xf (nop) */ | |
c906108c | 1664 | |
64366f1c EZ |
1665 | /* Check and see if we are in main. If so, skip over this |
1666 | initializer function as well. */ | |
c906108c | 1667 | |
c5aa993b | 1668 | tmp = find_pc_misc_function (pc); |
6314a349 AC |
1669 | if (tmp >= 0 |
1670 | && strcmp (misc_function_vector[tmp].name, main_name ()) == 0) | |
c5aa993b JM |
1671 | return pc + 8; |
1672 | } | |
c906108c | 1673 | } |
c906108c | 1674 | #endif /* 0 */ |
c5aa993b JM |
1675 | |
1676 | fdata->offset = -fdata->offset; | |
ddb20c56 | 1677 | return last_prologue_pc; |
c906108c SS |
1678 | } |
1679 | ||
1680 | ||
1681 | /************************************************************************* | |
f6077098 | 1682 | Support for creating pushing a dummy frame into the stack, and popping |
c906108c SS |
1683 | frames, etc. |
1684 | *************************************************************************/ | |
1685 | ||
c906108c | 1686 | |
11269d7e AC |
1687 | /* All the ABI's require 16 byte alignment. */ |
1688 | static CORE_ADDR | |
1689 | rs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
1690 | { | |
1691 | return (addr & -16); | |
1692 | } | |
1693 | ||
7a78ae4e | 1694 | /* Pass the arguments in either registers, or in the stack. In RS/6000, |
c906108c SS |
1695 | the first eight words of the argument list (that might be less than |
1696 | eight parameters if some parameters occupy more than one word) are | |
7a78ae4e | 1697 | passed in r3..r10 registers. float and double parameters are |
64366f1c EZ |
1698 | passed in fpr's, in addition to that. Rest of the parameters if any |
1699 | are passed in user stack. There might be cases in which half of the | |
c906108c SS |
1700 | parameter is copied into registers, the other half is pushed into |
1701 | stack. | |
1702 | ||
7a78ae4e ND |
1703 | Stack must be aligned on 64-bit boundaries when synthesizing |
1704 | function calls. | |
1705 | ||
c906108c SS |
1706 | If the function is returning a structure, then the return address is passed |
1707 | in r3, then the first 7 words of the parameters can be passed in registers, | |
64366f1c | 1708 | starting from r4. */ |
c906108c | 1709 | |
7a78ae4e | 1710 | static CORE_ADDR |
7d9b040b | 1711 | rs6000_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
77b2b6d4 AC |
1712 | struct regcache *regcache, CORE_ADDR bp_addr, |
1713 | int nargs, struct value **args, CORE_ADDR sp, | |
1714 | int struct_return, CORE_ADDR struct_addr) | |
c906108c | 1715 | { |
8b164abb | 1716 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
c906108c SS |
1717 | int ii; |
1718 | int len = 0; | |
c5aa993b JM |
1719 | int argno; /* current argument number */ |
1720 | int argbytes; /* current argument byte */ | |
50fd1280 | 1721 | gdb_byte tmp_buffer[50]; |
c5aa993b | 1722 | int f_argno = 0; /* current floating point argno */ |
8b164abb | 1723 | int wordsize = gdbarch_tdep (gdbarch)->wordsize; |
7d9b040b | 1724 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
c906108c | 1725 | |
ea7c478f | 1726 | struct value *arg = 0; |
c906108c SS |
1727 | struct type *type; |
1728 | ||
fb4443d8 | 1729 | ULONGEST saved_sp; |
c906108c | 1730 | |
383f0f5b JB |
1731 | /* The calling convention this function implements assumes the |
1732 | processor has floating-point registers. We shouldn't be using it | |
1733 | on PPC variants that lack them. */ | |
8b164abb | 1734 | gdb_assert (ppc_floating_point_unit_p (gdbarch)); |
383f0f5b | 1735 | |
64366f1c | 1736 | /* The first eight words of ther arguments are passed in registers. |
7a41266b AC |
1737 | Copy them appropriately. */ |
1738 | ii = 0; | |
1739 | ||
1740 | /* If the function is returning a `struct', then the first word | |
1741 | (which will be passed in r3) is used for struct return address. | |
1742 | In that case we should advance one word and start from r4 | |
1743 | register to copy parameters. */ | |
1744 | if (struct_return) | |
1745 | { | |
1746 | regcache_raw_write_unsigned (regcache, tdep->ppc_gp0_regnum + 3, | |
1747 | struct_addr); | |
1748 | ii++; | |
1749 | } | |
c906108c SS |
1750 | |
1751 | /* | |
c5aa993b JM |
1752 | effectively indirect call... gcc does... |
1753 | ||
1754 | return_val example( float, int); | |
1755 | ||
1756 | eabi: | |
1757 | float in fp0, int in r3 | |
1758 | offset of stack on overflow 8/16 | |
1759 | for varargs, must go by type. | |
1760 | power open: | |
1761 | float in r3&r4, int in r5 | |
1762 | offset of stack on overflow different | |
1763 | both: | |
1764 | return in r3 or f0. If no float, must study how gcc emulates floats; | |
1765 | pay attention to arg promotion. | |
1766 | User may have to cast\args to handle promotion correctly | |
1767 | since gdb won't know if prototype supplied or not. | |
1768 | */ | |
c906108c | 1769 | |
c5aa993b JM |
1770 | for (argno = 0, argbytes = 0; argno < nargs && ii < 8; ++ii) |
1771 | { | |
8b164abb | 1772 | int reg_size = register_size (gdbarch, ii + 3); |
c5aa993b JM |
1773 | |
1774 | arg = args[argno]; | |
df407dfe | 1775 | type = check_typedef (value_type (arg)); |
c5aa993b JM |
1776 | len = TYPE_LENGTH (type); |
1777 | ||
1778 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
1779 | { | |
1780 | ||
64366f1c | 1781 | /* Floating point arguments are passed in fpr's, as well as gpr's. |
c5aa993b | 1782 | There are 13 fpr's reserved for passing parameters. At this point |
64366f1c | 1783 | there is no way we would run out of them. */ |
c5aa993b | 1784 | |
9f335945 KB |
1785 | gdb_assert (len <= 8); |
1786 | ||
1787 | regcache_cooked_write (regcache, | |
1788 | tdep->ppc_fp0_regnum + 1 + f_argno, | |
0fd88904 | 1789 | value_contents (arg)); |
c5aa993b JM |
1790 | ++f_argno; |
1791 | } | |
1792 | ||
f6077098 | 1793 | if (len > reg_size) |
c5aa993b JM |
1794 | { |
1795 | ||
64366f1c | 1796 | /* Argument takes more than one register. */ |
c5aa993b JM |
1797 | while (argbytes < len) |
1798 | { | |
50fd1280 | 1799 | gdb_byte word[MAX_REGISTER_SIZE]; |
9f335945 KB |
1800 | memset (word, 0, reg_size); |
1801 | memcpy (word, | |
0fd88904 | 1802 | ((char *) value_contents (arg)) + argbytes, |
f6077098 KB |
1803 | (len - argbytes) > reg_size |
1804 | ? reg_size : len - argbytes); | |
9f335945 KB |
1805 | regcache_cooked_write (regcache, |
1806 | tdep->ppc_gp0_regnum + 3 + ii, | |
1807 | word); | |
f6077098 | 1808 | ++ii, argbytes += reg_size; |
c5aa993b JM |
1809 | |
1810 | if (ii >= 8) | |
1811 | goto ran_out_of_registers_for_arguments; | |
1812 | } | |
1813 | argbytes = 0; | |
1814 | --ii; | |
1815 | } | |
1816 | else | |
64366f1c EZ |
1817 | { |
1818 | /* Argument can fit in one register. No problem. */ | |
8b164abb | 1819 | int adj = gdbarch_byte_order (gdbarch) |
4c6b5505 | 1820 | == BFD_ENDIAN_BIG ? reg_size - len : 0; |
50fd1280 | 1821 | gdb_byte word[MAX_REGISTER_SIZE]; |
9f335945 KB |
1822 | |
1823 | memset (word, 0, reg_size); | |
0fd88904 | 1824 | memcpy (word, value_contents (arg), len); |
9f335945 | 1825 | regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 3 +ii, word); |
c5aa993b JM |
1826 | } |
1827 | ++argno; | |
c906108c | 1828 | } |
c906108c SS |
1829 | |
1830 | ran_out_of_registers_for_arguments: | |
1831 | ||
3e8c568d | 1832 | regcache_cooked_read_unsigned (regcache, |
8b164abb | 1833 | gdbarch_sp_regnum (gdbarch), |
3e8c568d | 1834 | &saved_sp); |
cc9836a8 | 1835 | |
64366f1c | 1836 | /* Location for 8 parameters are always reserved. */ |
7a78ae4e | 1837 | sp -= wordsize * 8; |
f6077098 | 1838 | |
64366f1c | 1839 | /* Another six words for back chain, TOC register, link register, etc. */ |
7a78ae4e | 1840 | sp -= wordsize * 6; |
f6077098 | 1841 | |
64366f1c | 1842 | /* Stack pointer must be quadword aligned. */ |
7a78ae4e | 1843 | sp &= -16; |
c906108c | 1844 | |
64366f1c EZ |
1845 | /* If there are more arguments, allocate space for them in |
1846 | the stack, then push them starting from the ninth one. */ | |
c906108c | 1847 | |
c5aa993b JM |
1848 | if ((argno < nargs) || argbytes) |
1849 | { | |
1850 | int space = 0, jj; | |
c906108c | 1851 | |
c5aa993b JM |
1852 | if (argbytes) |
1853 | { | |
1854 | space += ((len - argbytes + 3) & -4); | |
1855 | jj = argno + 1; | |
1856 | } | |
1857 | else | |
1858 | jj = argno; | |
c906108c | 1859 | |
c5aa993b JM |
1860 | for (; jj < nargs; ++jj) |
1861 | { | |
ea7c478f | 1862 | struct value *val = args[jj]; |
df407dfe | 1863 | space += ((TYPE_LENGTH (value_type (val))) + 3) & -4; |
c5aa993b | 1864 | } |
c906108c | 1865 | |
64366f1c | 1866 | /* Add location required for the rest of the parameters. */ |
f6077098 | 1867 | space = (space + 15) & -16; |
c5aa993b | 1868 | sp -= space; |
c906108c | 1869 | |
7aea86e6 AC |
1870 | /* This is another instance we need to be concerned about |
1871 | securing our stack space. If we write anything underneath %sp | |
1872 | (r1), we might conflict with the kernel who thinks he is free | |
1873 | to use this area. So, update %sp first before doing anything | |
1874 | else. */ | |
1875 | ||
3e8c568d | 1876 | regcache_raw_write_signed (regcache, |
8b164abb | 1877 | gdbarch_sp_regnum (gdbarch), sp); |
7aea86e6 | 1878 | |
64366f1c EZ |
1879 | /* If the last argument copied into the registers didn't fit there |
1880 | completely, push the rest of it into stack. */ | |
c906108c | 1881 | |
c5aa993b JM |
1882 | if (argbytes) |
1883 | { | |
1884 | write_memory (sp + 24 + (ii * 4), | |
50fd1280 | 1885 | value_contents (arg) + argbytes, |
c5aa993b JM |
1886 | len - argbytes); |
1887 | ++argno; | |
1888 | ii += ((len - argbytes + 3) & -4) / 4; | |
1889 | } | |
c906108c | 1890 | |
64366f1c | 1891 | /* Push the rest of the arguments into stack. */ |
c5aa993b JM |
1892 | for (; argno < nargs; ++argno) |
1893 | { | |
c906108c | 1894 | |
c5aa993b | 1895 | arg = args[argno]; |
df407dfe | 1896 | type = check_typedef (value_type (arg)); |
c5aa993b | 1897 | len = TYPE_LENGTH (type); |
c906108c SS |
1898 | |
1899 | ||
64366f1c EZ |
1900 | /* Float types should be passed in fpr's, as well as in the |
1901 | stack. */ | |
c5aa993b JM |
1902 | if (TYPE_CODE (type) == TYPE_CODE_FLT && f_argno < 13) |
1903 | { | |
c906108c | 1904 | |
9f335945 | 1905 | gdb_assert (len <= 8); |
c906108c | 1906 | |
9f335945 KB |
1907 | regcache_cooked_write (regcache, |
1908 | tdep->ppc_fp0_regnum + 1 + f_argno, | |
0fd88904 | 1909 | value_contents (arg)); |
c5aa993b JM |
1910 | ++f_argno; |
1911 | } | |
c906108c | 1912 | |
50fd1280 | 1913 | write_memory (sp + 24 + (ii * 4), value_contents (arg), len); |
c5aa993b JM |
1914 | ii += ((len + 3) & -4) / 4; |
1915 | } | |
c906108c | 1916 | } |
c906108c | 1917 | |
69517000 | 1918 | /* Set the stack pointer. According to the ABI, the SP is meant to |
7aea86e6 AC |
1919 | be set _before_ the corresponding stack space is used. On AIX, |
1920 | this even applies when the target has been completely stopped! | |
1921 | Not doing this can lead to conflicts with the kernel which thinks | |
1922 | that it still has control over this not-yet-allocated stack | |
1923 | region. */ | |
8b164abb | 1924 | regcache_raw_write_signed (regcache, gdbarch_sp_regnum (gdbarch), sp); |
33a7c2fc | 1925 | |
7aea86e6 | 1926 | /* Set back chain properly. */ |
8ba0209f AM |
1927 | store_unsigned_integer (tmp_buffer, wordsize, saved_sp); |
1928 | write_memory (sp, tmp_buffer, wordsize); | |
7aea86e6 | 1929 | |
e56a0ecc AC |
1930 | /* Point the inferior function call's return address at the dummy's |
1931 | breakpoint. */ | |
1932 | regcache_raw_write_signed (regcache, tdep->ppc_lr_regnum, bp_addr); | |
1933 | ||
794a477a AC |
1934 | /* Set the TOC register, get the value from the objfile reader |
1935 | which, in turn, gets it from the VMAP table. */ | |
1936 | if (rs6000_find_toc_address_hook != NULL) | |
1937 | { | |
1938 | CORE_ADDR tocvalue = (*rs6000_find_toc_address_hook) (func_addr); | |
1939 | regcache_raw_write_signed (regcache, tdep->ppc_toc_regnum, tocvalue); | |
1940 | } | |
1941 | ||
56be3814 | 1942 | target_store_registers (regcache, -1); |
c906108c SS |
1943 | return sp; |
1944 | } | |
c906108c | 1945 | |
d217aaed MK |
1946 | static enum return_value_convention |
1947 | rs6000_return_value (struct gdbarch *gdbarch, struct type *valtype, | |
1948 | struct regcache *regcache, gdb_byte *readbuf, | |
1949 | const gdb_byte *writebuf) | |
c906108c | 1950 | { |
8b164abb | 1951 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
d217aaed | 1952 | gdb_byte buf[8]; |
c906108c | 1953 | |
383f0f5b JB |
1954 | /* The calling convention this function implements assumes the |
1955 | processor has floating-point registers. We shouldn't be using it | |
d217aaed | 1956 | on PowerPC variants that lack them. */ |
8b164abb | 1957 | gdb_assert (ppc_floating_point_unit_p (gdbarch)); |
383f0f5b | 1958 | |
d217aaed MK |
1959 | /* AltiVec extension: Functions that declare a vector data type as a |
1960 | return value place that return value in VR2. */ | |
1961 | if (TYPE_CODE (valtype) == TYPE_CODE_ARRAY && TYPE_VECTOR (valtype) | |
1962 | && TYPE_LENGTH (valtype) == 16) | |
c5aa993b | 1963 | { |
d217aaed MK |
1964 | if (readbuf) |
1965 | regcache_cooked_read (regcache, tdep->ppc_vr0_regnum + 2, readbuf); | |
1966 | if (writebuf) | |
1967 | regcache_cooked_write (regcache, tdep->ppc_vr0_regnum + 2, writebuf); | |
c906108c | 1968 | |
d217aaed | 1969 | return RETURN_VALUE_REGISTER_CONVENTION; |
c5aa993b | 1970 | } |
d217aaed MK |
1971 | |
1972 | /* If the called subprogram returns an aggregate, there exists an | |
1973 | implicit first argument, whose value is the address of a caller- | |
1974 | allocated buffer into which the callee is assumed to store its | |
1975 | return value. All explicit parameters are appropriately | |
1976 | relabeled. */ | |
1977 | if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT | |
1978 | || TYPE_CODE (valtype) == TYPE_CODE_UNION | |
1979 | || TYPE_CODE (valtype) == TYPE_CODE_ARRAY) | |
1980 | return RETURN_VALUE_STRUCT_CONVENTION; | |
1981 | ||
1982 | /* Scalar floating-point values are returned in FPR1 for float or | |
1983 | double, and in FPR1:FPR2 for quadword precision. Fortran | |
1984 | complex*8 and complex*16 are returned in FPR1:FPR2, and | |
1985 | complex*32 is returned in FPR1:FPR4. */ | |
1986 | if (TYPE_CODE (valtype) == TYPE_CODE_FLT | |
1987 | && (TYPE_LENGTH (valtype) == 4 || TYPE_LENGTH (valtype) == 8)) | |
1988 | { | |
1989 | struct type *regtype = register_type (gdbarch, tdep->ppc_fp0_regnum); | |
1990 | gdb_byte regval[8]; | |
1991 | ||
1992 | /* FIXME: kettenis/2007-01-01: Add support for quadword | |
1993 | precision and complex. */ | |
1994 | ||
1995 | if (readbuf) | |
1996 | { | |
1997 | regcache_cooked_read (regcache, tdep->ppc_fp0_regnum + 1, regval); | |
1998 | convert_typed_floating (regval, regtype, readbuf, valtype); | |
1999 | } | |
2000 | if (writebuf) | |
2001 | { | |
2002 | convert_typed_floating (writebuf, valtype, regval, regtype); | |
2003 | regcache_cooked_write (regcache, tdep->ppc_fp0_regnum + 1, regval); | |
2004 | } | |
2005 | ||
2006 | return RETURN_VALUE_REGISTER_CONVENTION; | |
2007 | } | |
2008 | ||
2009 | /* Values of the types int, long, short, pointer, and char (length | |
2010 | is less than or equal to four bytes), as well as bit values of | |
2011 | lengths less than or equal to 32 bits, must be returned right | |
2012 | justified in GPR3 with signed values sign extended and unsigned | |
2013 | values zero extended, as necessary. */ | |
2014 | if (TYPE_LENGTH (valtype) <= tdep->wordsize) | |
ace1378a | 2015 | { |
d217aaed MK |
2016 | if (readbuf) |
2017 | { | |
2018 | ULONGEST regval; | |
2019 | ||
2020 | /* For reading we don't have to worry about sign extension. */ | |
2021 | regcache_cooked_read_unsigned (regcache, tdep->ppc_gp0_regnum + 3, | |
2022 | ®val); | |
2023 | store_unsigned_integer (readbuf, TYPE_LENGTH (valtype), regval); | |
2024 | } | |
2025 | if (writebuf) | |
2026 | { | |
2027 | /* For writing, use unpack_long since that should handle any | |
2028 | required sign extension. */ | |
2029 | regcache_cooked_write_unsigned (regcache, tdep->ppc_gp0_regnum + 3, | |
2030 | unpack_long (valtype, writebuf)); | |
2031 | } | |
2032 | ||
2033 | return RETURN_VALUE_REGISTER_CONVENTION; | |
ace1378a | 2034 | } |
d217aaed MK |
2035 | |
2036 | /* Eight-byte non-floating-point scalar values must be returned in | |
2037 | GPR3:GPR4. */ | |
2038 | ||
2039 | if (TYPE_LENGTH (valtype) == 8) | |
c5aa993b | 2040 | { |
d217aaed MK |
2041 | gdb_assert (TYPE_CODE (valtype) != TYPE_CODE_FLT); |
2042 | gdb_assert (tdep->wordsize == 4); | |
2043 | ||
2044 | if (readbuf) | |
2045 | { | |
2046 | gdb_byte regval[8]; | |
2047 | ||
2048 | regcache_cooked_read (regcache, tdep->ppc_gp0_regnum + 3, regval); | |
2049 | regcache_cooked_read (regcache, tdep->ppc_gp0_regnum + 4, | |
2050 | regval + 4); | |
2051 | memcpy (readbuf, regval, 8); | |
2052 | } | |
2053 | if (writebuf) | |
2054 | { | |
2055 | regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 3, writebuf); | |
2056 | regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 4, | |
2057 | writebuf + 4); | |
2058 | } | |
2059 | ||
2060 | return RETURN_VALUE_REGISTER_CONVENTION; | |
c906108c | 2061 | } |
d217aaed MK |
2062 | |
2063 | return RETURN_VALUE_STRUCT_CONVENTION; | |
c906108c SS |
2064 | } |
2065 | ||
977adac5 ND |
2066 | /* Return whether handle_inferior_event() should proceed through code |
2067 | starting at PC in function NAME when stepping. | |
2068 | ||
2069 | The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to | |
2070 | handle memory references that are too distant to fit in instructions | |
2071 | generated by the compiler. For example, if 'foo' in the following | |
2072 | instruction: | |
2073 | ||
2074 | lwz r9,foo(r2) | |
2075 | ||
2076 | is greater than 32767, the linker might replace the lwz with a branch to | |
2077 | somewhere in @FIX1 that does the load in 2 instructions and then branches | |
2078 | back to where execution should continue. | |
2079 | ||
2080 | GDB should silently step over @FIX code, just like AIX dbx does. | |
2ec664f5 MS |
2081 | Unfortunately, the linker uses the "b" instruction for the |
2082 | branches, meaning that the link register doesn't get set. | |
2083 | Therefore, GDB's usual step_over_function () mechanism won't work. | |
977adac5 | 2084 | |
e76f05fa UW |
2085 | Instead, use the gdbarch_skip_trampoline_code and |
2086 | gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past | |
2ec664f5 | 2087 | @FIX code. */ |
977adac5 ND |
2088 | |
2089 | int | |
2090 | rs6000_in_solib_return_trampoline (CORE_ADDR pc, char *name) | |
2091 | { | |
2092 | return name && !strncmp (name, "@FIX", 4); | |
2093 | } | |
2094 | ||
2095 | /* Skip code that the user doesn't want to see when stepping: | |
2096 | ||
2097 | 1. Indirect function calls use a piece of trampoline code to do context | |
2098 | switching, i.e. to set the new TOC table. Skip such code if we are on | |
2099 | its first instruction (as when we have single-stepped to here). | |
2100 | ||
2101 | 2. Skip shared library trampoline code (which is different from | |
c906108c | 2102 | indirect function call trampolines). |
977adac5 ND |
2103 | |
2104 | 3. Skip bigtoc fixup code. | |
2105 | ||
c906108c | 2106 | Result is desired PC to step until, or NULL if we are not in |
977adac5 | 2107 | code that should be skipped. */ |
c906108c SS |
2108 | |
2109 | CORE_ADDR | |
52f729a7 | 2110 | rs6000_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 2111 | { |
52f0bd74 | 2112 | unsigned int ii, op; |
977adac5 | 2113 | int rel; |
c906108c | 2114 | CORE_ADDR solib_target_pc; |
977adac5 | 2115 | struct minimal_symbol *msymbol; |
c906108c | 2116 | |
c5aa993b JM |
2117 | static unsigned trampoline_code[] = |
2118 | { | |
2119 | 0x800b0000, /* l r0,0x0(r11) */ | |
2120 | 0x90410014, /* st r2,0x14(r1) */ | |
2121 | 0x7c0903a6, /* mtctr r0 */ | |
2122 | 0x804b0004, /* l r2,0x4(r11) */ | |
2123 | 0x816b0008, /* l r11,0x8(r11) */ | |
2124 | 0x4e800420, /* bctr */ | |
2125 | 0x4e800020, /* br */ | |
2126 | 0 | |
c906108c SS |
2127 | }; |
2128 | ||
977adac5 ND |
2129 | /* Check for bigtoc fixup code. */ |
2130 | msymbol = lookup_minimal_symbol_by_pc (pc); | |
2ec664f5 MS |
2131 | if (msymbol |
2132 | && rs6000_in_solib_return_trampoline (pc, | |
2133 | DEPRECATED_SYMBOL_NAME (msymbol))) | |
977adac5 ND |
2134 | { |
2135 | /* Double-check that the third instruction from PC is relative "b". */ | |
2136 | op = read_memory_integer (pc + 8, 4); | |
2137 | if ((op & 0xfc000003) == 0x48000000) | |
2138 | { | |
2139 | /* Extract bits 6-29 as a signed 24-bit relative word address and | |
2140 | add it to the containing PC. */ | |
2141 | rel = ((int)(op << 6) >> 6); | |
2142 | return pc + 8 + rel; | |
2143 | } | |
2144 | } | |
2145 | ||
c906108c | 2146 | /* If pc is in a shared library trampoline, return its target. */ |
52f729a7 | 2147 | solib_target_pc = find_solib_trampoline_target (frame, pc); |
c906108c SS |
2148 | if (solib_target_pc) |
2149 | return solib_target_pc; | |
2150 | ||
c5aa993b JM |
2151 | for (ii = 0; trampoline_code[ii]; ++ii) |
2152 | { | |
2153 | op = read_memory_integer (pc + (ii * 4), 4); | |
2154 | if (op != trampoline_code[ii]) | |
2155 | return 0; | |
2156 | } | |
52f729a7 | 2157 | ii = get_frame_register_unsigned (frame, 11); /* r11 holds destination addr */ |
8b164abb UW |
2158 | pc = read_memory_addr (ii, |
2159 | gdbarch_tdep (get_frame_arch (frame))->wordsize); /* (r11) value */ | |
c906108c SS |
2160 | return pc; |
2161 | } | |
2162 | ||
794ac428 UW |
2163 | /* ISA-specific vector types. */ |
2164 | ||
2165 | static struct type * | |
2166 | rs6000_builtin_type_vec64 (struct gdbarch *gdbarch) | |
2167 | { | |
2168 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2169 | ||
2170 | if (!tdep->ppc_builtin_type_vec64) | |
2171 | { | |
2172 | /* The type we're building is this: */ | |
2173 | #if 0 | |
2174 | union __gdb_builtin_type_vec64 | |
2175 | { | |
2176 | int64_t uint64; | |
2177 | float v2_float[2]; | |
2178 | int32_t v2_int32[2]; | |
2179 | int16_t v4_int16[4]; | |
2180 | int8_t v8_int8[8]; | |
2181 | }; | |
2182 | #endif | |
2183 | ||
2184 | struct type *t; | |
2185 | ||
2186 | t = init_composite_type ("__ppc_builtin_type_vec64", TYPE_CODE_UNION); | |
2187 | append_composite_type_field (t, "uint64", builtin_type_int64); | |
2188 | append_composite_type_field (t, "v2_float", | |
2189 | init_vector_type (builtin_type_float, 2)); | |
2190 | append_composite_type_field (t, "v2_int32", | |
2191 | init_vector_type (builtin_type_int32, 2)); | |
2192 | append_composite_type_field (t, "v4_int16", | |
2193 | init_vector_type (builtin_type_int16, 4)); | |
2194 | append_composite_type_field (t, "v8_int8", | |
2195 | init_vector_type (builtin_type_int8, 8)); | |
2196 | ||
2197 | TYPE_FLAGS (t) |= TYPE_FLAG_VECTOR; | |
2198 | TYPE_NAME (t) = "ppc_builtin_type_vec64"; | |
2199 | tdep->ppc_builtin_type_vec64 = t; | |
2200 | } | |
2201 | ||
2202 | return tdep->ppc_builtin_type_vec64; | |
2203 | } | |
2204 | ||
7a78ae4e | 2205 | /* Return the size of register REG when words are WORDSIZE bytes long. If REG |
64366f1c | 2206 | isn't available with that word size, return 0. */ |
7a78ae4e ND |
2207 | |
2208 | static int | |
2209 | regsize (const struct reg *reg, int wordsize) | |
2210 | { | |
2211 | return wordsize == 8 ? reg->sz64 : reg->sz32; | |
2212 | } | |
2213 | ||
7cc46491 DJ |
2214 | /* Return the name of register number REGNO, or the empty string if it |
2215 | is an anonymous register. */ | |
7a78ae4e | 2216 | |
fa88f677 | 2217 | static const char * |
7cc46491 | 2218 | rs6000_register_name (int regno) |
7a78ae4e | 2219 | { |
21283beb | 2220 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
7a78ae4e | 2221 | |
7cc46491 DJ |
2222 | /* The upper half "registers" have names in the XML description, |
2223 | but we present only the low GPRs and the full 64-bit registers | |
2224 | to the user. */ | |
2225 | if (tdep->ppc_ev0_upper_regnum >= 0 | |
2226 | && tdep->ppc_ev0_upper_regnum <= regno | |
2227 | && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) | |
2228 | return ""; | |
2229 | ||
2230 | /* Check if the SPE pseudo registers are available. */ | |
2231 | if (tdep->ppc_ev0_regnum >= 0 | |
2232 | && tdep->ppc_ev0_regnum <= regno | |
2233 | && regno < tdep->ppc_ev0_regnum + ppc_num_gprs) | |
2234 | { | |
2235 | static const char *const spe_regnames[] = { | |
2236 | "ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7", | |
2237 | "ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15", | |
2238 | "ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23", | |
2239 | "ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31", | |
2240 | }; | |
2241 | return spe_regnames[regno - tdep->ppc_ev0_regnum]; | |
2242 | } | |
2243 | ||
2244 | return tdesc_register_name (regno); | |
7a78ae4e ND |
2245 | } |
2246 | ||
7cc46491 DJ |
2247 | /* Return the GDB type object for the "standard" data type of data in |
2248 | register N. */ | |
7a78ae4e ND |
2249 | |
2250 | static struct type * | |
7cc46491 | 2251 | rs6000_pseudo_register_type (struct gdbarch *gdbarch, int regnum) |
7a78ae4e | 2252 | { |
691d145a | 2253 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7a78ae4e | 2254 | |
7cc46491 DJ |
2255 | /* These are the only pseudo-registers we support. */ |
2256 | gdb_assert (tdep->ppc_ev0_regnum >= 0 | |
2257 | && regnum >= tdep->ppc_ev0_regnum | |
2258 | && regnum < tdep->ppc_ev0_regnum + 32); | |
2259 | ||
2260 | return rs6000_builtin_type_vec64 (gdbarch); | |
7a78ae4e ND |
2261 | } |
2262 | ||
c44ca51c AC |
2263 | /* Is REGNUM a member of REGGROUP? */ |
2264 | static int | |
7cc46491 DJ |
2265 | rs6000_pseudo_register_reggroup_p (struct gdbarch *gdbarch, int regnum, |
2266 | struct reggroup *group) | |
c44ca51c AC |
2267 | { |
2268 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
c44ca51c | 2269 | |
7cc46491 DJ |
2270 | /* These are the only pseudo-registers we support. */ |
2271 | gdb_assert (tdep->ppc_ev0_regnum >= 0 | |
2272 | && regnum >= tdep->ppc_ev0_regnum | |
2273 | && regnum < tdep->ppc_ev0_regnum + 32); | |
c44ca51c | 2274 | |
7cc46491 DJ |
2275 | if (group == all_reggroup || group == vector_reggroup) |
2276 | return 1; | |
2277 | else | |
2278 | return 0; | |
c44ca51c AC |
2279 | } |
2280 | ||
691d145a | 2281 | /* The register format for RS/6000 floating point registers is always |
64366f1c | 2282 | double, we need a conversion if the memory format is float. */ |
7a78ae4e ND |
2283 | |
2284 | static int | |
691d145a | 2285 | rs6000_convert_register_p (int regnum, struct type *type) |
7a78ae4e | 2286 | { |
7cc46491 DJ |
2287 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2288 | ||
2289 | return (tdep->ppc_fp0_regnum >= 0 | |
2290 | && regnum >= tdep->ppc_fp0_regnum | |
2291 | && regnum < tdep->ppc_fp0_regnum + ppc_num_fprs | |
2292 | && TYPE_CODE (type) == TYPE_CODE_FLT | |
2293 | && TYPE_LENGTH (type) != TYPE_LENGTH (builtin_type_double)); | |
7a78ae4e ND |
2294 | } |
2295 | ||
7a78ae4e | 2296 | static void |
691d145a JB |
2297 | rs6000_register_to_value (struct frame_info *frame, |
2298 | int regnum, | |
2299 | struct type *type, | |
50fd1280 | 2300 | gdb_byte *to) |
7a78ae4e | 2301 | { |
50fd1280 | 2302 | gdb_byte from[MAX_REGISTER_SIZE]; |
691d145a | 2303 | |
691d145a | 2304 | gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT); |
7a78ae4e | 2305 | |
691d145a JB |
2306 | get_frame_register (frame, regnum, from); |
2307 | convert_typed_floating (from, builtin_type_double, to, type); | |
2308 | } | |
7a292a7a | 2309 | |
7a78ae4e | 2310 | static void |
691d145a JB |
2311 | rs6000_value_to_register (struct frame_info *frame, |
2312 | int regnum, | |
2313 | struct type *type, | |
50fd1280 | 2314 | const gdb_byte *from) |
7a78ae4e | 2315 | { |
50fd1280 | 2316 | gdb_byte to[MAX_REGISTER_SIZE]; |
691d145a | 2317 | |
691d145a JB |
2318 | gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT); |
2319 | ||
2320 | convert_typed_floating (from, type, to, builtin_type_double); | |
2321 | put_frame_register (frame, regnum, to); | |
7a78ae4e | 2322 | } |
c906108c | 2323 | |
6ced10dd JB |
2324 | /* Move SPE vector register values between a 64-bit buffer and the two |
2325 | 32-bit raw register halves in a regcache. This function handles | |
2326 | both splitting a 64-bit value into two 32-bit halves, and joining | |
2327 | two halves into a whole 64-bit value, depending on the function | |
2328 | passed as the MOVE argument. | |
2329 | ||
2330 | EV_REG must be the number of an SPE evN vector register --- a | |
2331 | pseudoregister. REGCACHE must be a regcache, and BUFFER must be a | |
2332 | 64-bit buffer. | |
2333 | ||
2334 | Call MOVE once for each 32-bit half of that register, passing | |
2335 | REGCACHE, the number of the raw register corresponding to that | |
2336 | half, and the address of the appropriate half of BUFFER. | |
2337 | ||
2338 | For example, passing 'regcache_raw_read' as the MOVE function will | |
2339 | fill BUFFER with the full 64-bit contents of EV_REG. Or, passing | |
2340 | 'regcache_raw_supply' will supply the contents of BUFFER to the | |
2341 | appropriate pair of raw registers in REGCACHE. | |
2342 | ||
2343 | You may need to cast away some 'const' qualifiers when passing | |
2344 | MOVE, since this function can't tell at compile-time which of | |
2345 | REGCACHE or BUFFER is acting as the source of the data. If C had | |
2346 | co-variant type qualifiers, ... */ | |
2347 | static void | |
2348 | e500_move_ev_register (void (*move) (struct regcache *regcache, | |
50fd1280 | 2349 | int regnum, gdb_byte *buf), |
6ced10dd | 2350 | struct regcache *regcache, int ev_reg, |
50fd1280 | 2351 | gdb_byte *buffer) |
6ced10dd JB |
2352 | { |
2353 | struct gdbarch *arch = get_regcache_arch (regcache); | |
2354 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); | |
2355 | int reg_index; | |
50fd1280 | 2356 | gdb_byte *byte_buffer = buffer; |
6ced10dd JB |
2357 | |
2358 | gdb_assert (tdep->ppc_ev0_regnum <= ev_reg | |
2359 | && ev_reg < tdep->ppc_ev0_regnum + ppc_num_gprs); | |
2360 | ||
2361 | reg_index = ev_reg - tdep->ppc_ev0_regnum; | |
2362 | ||
8b164abb | 2363 | if (gdbarch_byte_order (arch) == BFD_ENDIAN_BIG) |
6ced10dd JB |
2364 | { |
2365 | move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer); | |
2366 | move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer + 4); | |
2367 | } | |
2368 | else | |
2369 | { | |
2370 | move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer); | |
2371 | move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer + 4); | |
2372 | } | |
2373 | } | |
2374 | ||
c8001721 EZ |
2375 | static void |
2376 | e500_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
50fd1280 | 2377 | int reg_nr, gdb_byte *buffer) |
c8001721 | 2378 | { |
6ced10dd | 2379 | struct gdbarch *regcache_arch = get_regcache_arch (regcache); |
c8001721 EZ |
2380 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2381 | ||
6ced10dd JB |
2382 | gdb_assert (regcache_arch == gdbarch); |
2383 | ||
2384 | if (tdep->ppc_ev0_regnum <= reg_nr | |
2385 | && reg_nr < tdep->ppc_ev0_regnum + ppc_num_gprs) | |
2386 | e500_move_ev_register (regcache_raw_read, regcache, reg_nr, buffer); | |
2387 | else | |
a44bddec | 2388 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 AC |
2389 | _("e500_pseudo_register_read: " |
2390 | "called on unexpected register '%s' (%d)"), | |
a44bddec | 2391 | gdbarch_register_name (gdbarch, reg_nr), reg_nr); |
c8001721 EZ |
2392 | } |
2393 | ||
2394 | static void | |
2395 | e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
50fd1280 | 2396 | int reg_nr, const gdb_byte *buffer) |
c8001721 | 2397 | { |
6ced10dd | 2398 | struct gdbarch *regcache_arch = get_regcache_arch (regcache); |
c8001721 EZ |
2399 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2400 | ||
6ced10dd JB |
2401 | gdb_assert (regcache_arch == gdbarch); |
2402 | ||
2403 | if (tdep->ppc_ev0_regnum <= reg_nr | |
2404 | && reg_nr < tdep->ppc_ev0_regnum + ppc_num_gprs) | |
50fd1280 | 2405 | e500_move_ev_register ((void (*) (struct regcache *, int, gdb_byte *)) |
6ced10dd | 2406 | regcache_raw_write, |
50fd1280 | 2407 | regcache, reg_nr, (gdb_byte *) buffer); |
6ced10dd | 2408 | else |
a44bddec | 2409 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 AC |
2410 | _("e500_pseudo_register_read: " |
2411 | "called on unexpected register '%s' (%d)"), | |
a44bddec | 2412 | gdbarch_register_name (gdbarch, reg_nr), reg_nr); |
6ced10dd JB |
2413 | } |
2414 | ||
18ed0c4e | 2415 | /* Convert a DBX STABS register number to a GDB register number. */ |
c8001721 | 2416 | static int |
18ed0c4e | 2417 | rs6000_stab_reg_to_regnum (int num) |
c8001721 | 2418 | { |
9f744501 | 2419 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c8001721 | 2420 | |
9f744501 JB |
2421 | if (0 <= num && num <= 31) |
2422 | return tdep->ppc_gp0_regnum + num; | |
2423 | else if (32 <= num && num <= 63) | |
383f0f5b JB |
2424 | /* FIXME: jimb/2004-05-05: What should we do when the debug info |
2425 | specifies registers the architecture doesn't have? Our | |
2426 | callers don't check the value we return. */ | |
366f009f | 2427 | return tdep->ppc_fp0_regnum + (num - 32); |
18ed0c4e JB |
2428 | else if (77 <= num && num <= 108) |
2429 | return tdep->ppc_vr0_regnum + (num - 77); | |
9f744501 JB |
2430 | else if (1200 <= num && num < 1200 + 32) |
2431 | return tdep->ppc_ev0_regnum + (num - 1200); | |
2432 | else | |
2433 | switch (num) | |
2434 | { | |
2435 | case 64: | |
2436 | return tdep->ppc_mq_regnum; | |
2437 | case 65: | |
2438 | return tdep->ppc_lr_regnum; | |
2439 | case 66: | |
2440 | return tdep->ppc_ctr_regnum; | |
2441 | case 76: | |
2442 | return tdep->ppc_xer_regnum; | |
2443 | case 109: | |
2444 | return tdep->ppc_vrsave_regnum; | |
18ed0c4e JB |
2445 | case 110: |
2446 | return tdep->ppc_vrsave_regnum - 1; /* vscr */ | |
867e2dc5 | 2447 | case 111: |
18ed0c4e | 2448 | return tdep->ppc_acc_regnum; |
867e2dc5 | 2449 | case 112: |
18ed0c4e | 2450 | return tdep->ppc_spefscr_regnum; |
9f744501 JB |
2451 | default: |
2452 | return num; | |
2453 | } | |
18ed0c4e | 2454 | } |
9f744501 | 2455 | |
9f744501 | 2456 | |
18ed0c4e JB |
2457 | /* Convert a Dwarf 2 register number to a GDB register number. */ |
2458 | static int | |
2459 | rs6000_dwarf2_reg_to_regnum (int num) | |
2460 | { | |
2461 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
9f744501 | 2462 | |
18ed0c4e JB |
2463 | if (0 <= num && num <= 31) |
2464 | return tdep->ppc_gp0_regnum + num; | |
2465 | else if (32 <= num && num <= 63) | |
2466 | /* FIXME: jimb/2004-05-05: What should we do when the debug info | |
2467 | specifies registers the architecture doesn't have? Our | |
2468 | callers don't check the value we return. */ | |
2469 | return tdep->ppc_fp0_regnum + (num - 32); | |
2470 | else if (1124 <= num && num < 1124 + 32) | |
2471 | return tdep->ppc_vr0_regnum + (num - 1124); | |
2472 | else if (1200 <= num && num < 1200 + 32) | |
2473 | return tdep->ppc_ev0_regnum + (num - 1200); | |
2474 | else | |
2475 | switch (num) | |
2476 | { | |
a489f789 AS |
2477 | case 64: |
2478 | return tdep->ppc_cr_regnum; | |
18ed0c4e JB |
2479 | case 67: |
2480 | return tdep->ppc_vrsave_regnum - 1; /* vscr */ | |
2481 | case 99: | |
2482 | return tdep->ppc_acc_regnum; | |
2483 | case 100: | |
2484 | return tdep->ppc_mq_regnum; | |
2485 | case 101: | |
2486 | return tdep->ppc_xer_regnum; | |
2487 | case 108: | |
2488 | return tdep->ppc_lr_regnum; | |
2489 | case 109: | |
2490 | return tdep->ppc_ctr_regnum; | |
2491 | case 356: | |
2492 | return tdep->ppc_vrsave_regnum; | |
2493 | case 612: | |
2494 | return tdep->ppc_spefscr_regnum; | |
2495 | default: | |
2496 | return num; | |
2497 | } | |
2188cbdd EZ |
2498 | } |
2499 | ||
4fc771b8 DJ |
2500 | /* Translate a .eh_frame register to DWARF register, or adjust a |
2501 | .debug_frame register. */ | |
2502 | ||
2503 | static int | |
2504 | rs6000_adjust_frame_regnum (struct gdbarch *gdbarch, int num, int eh_frame_p) | |
2505 | { | |
2506 | /* GCC releases before 3.4 use GCC internal register numbering in | |
2507 | .debug_frame (and .debug_info, et cetera). The numbering is | |
2508 | different from the standard SysV numbering for everything except | |
2509 | for GPRs and FPRs. We can not detect this problem in most cases | |
2510 | - to get accurate debug info for variables living in lr, ctr, v0, | |
2511 | et cetera, use a newer version of GCC. But we must detect | |
2512 | one important case - lr is in column 65 in .debug_frame output, | |
2513 | instead of 108. | |
2514 | ||
2515 | GCC 3.4, and the "hammer" branch, have a related problem. They | |
2516 | record lr register saves in .debug_frame as 108, but still record | |
2517 | the return column as 65. We fix that up too. | |
2518 | ||
2519 | We can do this because 65 is assigned to fpsr, and GCC never | |
2520 | generates debug info referring to it. To add support for | |
2521 | handwritten debug info that restores fpsr, we would need to add a | |
2522 | producer version check to this. */ | |
2523 | if (!eh_frame_p) | |
2524 | { | |
2525 | if (num == 65) | |
2526 | return 108; | |
2527 | else | |
2528 | return num; | |
2529 | } | |
2530 | ||
2531 | /* .eh_frame is GCC specific. For binary compatibility, it uses GCC | |
2532 | internal register numbering; translate that to the standard DWARF2 | |
2533 | register numbering. */ | |
2534 | if (0 <= num && num <= 63) /* r0-r31,fp0-fp31 */ | |
2535 | return num; | |
2536 | else if (68 <= num && num <= 75) /* cr0-cr8 */ | |
2537 | return num - 68 + 86; | |
2538 | else if (77 <= num && num <= 108) /* vr0-vr31 */ | |
2539 | return num - 77 + 1124; | |
2540 | else | |
2541 | switch (num) | |
2542 | { | |
2543 | case 64: /* mq */ | |
2544 | return 100; | |
2545 | case 65: /* lr */ | |
2546 | return 108; | |
2547 | case 66: /* ctr */ | |
2548 | return 109; | |
2549 | case 76: /* xer */ | |
2550 | return 101; | |
2551 | case 109: /* vrsave */ | |
2552 | return 356; | |
2553 | case 110: /* vscr */ | |
2554 | return 67; | |
2555 | case 111: /* spe_acc */ | |
2556 | return 99; | |
2557 | case 112: /* spefscr */ | |
2558 | return 612; | |
2559 | default: | |
2560 | return num; | |
2561 | } | |
2562 | } | |
c906108c | 2563 | \f |
e2d0e7eb | 2564 | /* Support for CONVERT_FROM_FUNC_PTR_ADDR (ARCH, ADDR, TARG). |
7a78ae4e ND |
2565 | |
2566 | Usually a function pointer's representation is simply the address | |
2567 | of the function. On the RS/6000 however, a function pointer is | |
8ba0209f | 2568 | represented by a pointer to an OPD entry. This OPD entry contains |
7a78ae4e ND |
2569 | three words, the first word is the address of the function, the |
2570 | second word is the TOC pointer (r2), and the third word is the | |
2571 | static chain value. Throughout GDB it is currently assumed that a | |
2572 | function pointer contains the address of the function, which is not | |
2573 | easy to fix. In addition, the conversion of a function address to | |
8ba0209f | 2574 | a function pointer would require allocation of an OPD entry in the |
7a78ae4e ND |
2575 | inferior's memory space, with all its drawbacks. To be able to |
2576 | call C++ virtual methods in the inferior (which are called via | |
f517ea4e | 2577 | function pointers), find_function_addr uses this function to get the |
7a78ae4e ND |
2578 | function address from a function pointer. */ |
2579 | ||
f517ea4e PS |
2580 | /* Return real function address if ADDR (a function pointer) is in the data |
2581 | space and is therefore a special function pointer. */ | |
c906108c | 2582 | |
b9362cc7 | 2583 | static CORE_ADDR |
e2d0e7eb AC |
2584 | rs6000_convert_from_func_ptr_addr (struct gdbarch *gdbarch, |
2585 | CORE_ADDR addr, | |
2586 | struct target_ops *targ) | |
c906108c SS |
2587 | { |
2588 | struct obj_section *s; | |
2589 | ||
2590 | s = find_pc_section (addr); | |
2591 | if (s && s->the_bfd_section->flags & SEC_CODE) | |
7a78ae4e | 2592 | return addr; |
c906108c | 2593 | |
7a78ae4e | 2594 | /* ADDR is in the data space, so it's a special function pointer. */ |
7f68ac27 | 2595 | return read_memory_addr (addr, gdbarch_tdep (gdbarch)->wordsize); |
c906108c | 2596 | } |
c906108c | 2597 | \f |
c5aa993b | 2598 | |
7a78ae4e | 2599 | /* Handling the various POWER/PowerPC variants. */ |
c906108c | 2600 | |
c906108c | 2601 | /* Information about a particular processor variant. */ |
7a78ae4e | 2602 | |
c906108c | 2603 | struct variant |
c5aa993b JM |
2604 | { |
2605 | /* Name of this variant. */ | |
2606 | char *name; | |
c906108c | 2607 | |
c5aa993b JM |
2608 | /* English description of the variant. */ |
2609 | char *description; | |
c906108c | 2610 | |
64366f1c | 2611 | /* bfd_arch_info.arch corresponding to variant. */ |
7a78ae4e ND |
2612 | enum bfd_architecture arch; |
2613 | ||
64366f1c | 2614 | /* bfd_arch_info.mach corresponding to variant. */ |
7a78ae4e ND |
2615 | unsigned long mach; |
2616 | ||
7cc46491 DJ |
2617 | /* Target description for this variant. */ |
2618 | struct target_desc **tdesc; | |
c5aa993b | 2619 | }; |
c906108c | 2620 | |
489461e2 | 2621 | static struct variant variants[] = |
c906108c | 2622 | { |
7a78ae4e | 2623 | {"powerpc", "PowerPC user-level", bfd_arch_powerpc, |
7cc46491 | 2624 | bfd_mach_ppc, &tdesc_powerpc_32}, |
7a78ae4e | 2625 | {"power", "POWER user-level", bfd_arch_rs6000, |
7cc46491 | 2626 | bfd_mach_rs6k, &tdesc_rs6000}, |
7a78ae4e | 2627 | {"403", "IBM PowerPC 403", bfd_arch_powerpc, |
7cc46491 | 2628 | bfd_mach_ppc_403, &tdesc_powerpc_403}, |
7a78ae4e | 2629 | {"601", "Motorola PowerPC 601", bfd_arch_powerpc, |
7cc46491 | 2630 | bfd_mach_ppc_601, &tdesc_powerpc_601}, |
7a78ae4e | 2631 | {"602", "Motorola PowerPC 602", bfd_arch_powerpc, |
7cc46491 | 2632 | bfd_mach_ppc_602, &tdesc_powerpc_602}, |
7a78ae4e | 2633 | {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc, |
7cc46491 | 2634 | bfd_mach_ppc_603, &tdesc_powerpc_603}, |
7a78ae4e | 2635 | {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc, |
7cc46491 | 2636 | 604, &tdesc_powerpc_604}, |
7a78ae4e | 2637 | {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc, |
7cc46491 | 2638 | bfd_mach_ppc_403gc, &tdesc_powerpc_403gc}, |
7a78ae4e | 2639 | {"505", "Motorola PowerPC 505", bfd_arch_powerpc, |
7cc46491 | 2640 | bfd_mach_ppc_505, &tdesc_powerpc_505}, |
7a78ae4e | 2641 | {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc, |
7cc46491 | 2642 | bfd_mach_ppc_860, &tdesc_powerpc_860}, |
7a78ae4e | 2643 | {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc, |
7cc46491 | 2644 | bfd_mach_ppc_750, &tdesc_powerpc_750}, |
1fcc0bb8 | 2645 | {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc, |
7cc46491 | 2646 | bfd_mach_ppc_7400, &tdesc_powerpc_7400}, |
c8001721 | 2647 | {"e500", "Motorola PowerPC e500", bfd_arch_powerpc, |
7cc46491 | 2648 | bfd_mach_ppc_e500, &tdesc_powerpc_e500}, |
7a78ae4e | 2649 | |
5d57ee30 KB |
2650 | /* 64-bit */ |
2651 | {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc, | |
7cc46491 | 2652 | bfd_mach_ppc64, &tdesc_powerpc_64}, |
7a78ae4e | 2653 | {"620", "Motorola PowerPC 620", bfd_arch_powerpc, |
7cc46491 | 2654 | bfd_mach_ppc_620, &tdesc_powerpc_64}, |
5d57ee30 | 2655 | {"630", "Motorola PowerPC 630", bfd_arch_powerpc, |
7cc46491 | 2656 | bfd_mach_ppc_630, &tdesc_powerpc_64}, |
7a78ae4e | 2657 | {"a35", "PowerPC A35", bfd_arch_powerpc, |
7cc46491 | 2658 | bfd_mach_ppc_a35, &tdesc_powerpc_64}, |
5d57ee30 | 2659 | {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc, |
7cc46491 | 2660 | bfd_mach_ppc_rs64ii, &tdesc_powerpc_64}, |
5d57ee30 | 2661 | {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc, |
7cc46491 | 2662 | bfd_mach_ppc_rs64iii, &tdesc_powerpc_64}, |
5d57ee30 | 2663 | |
64366f1c | 2664 | /* FIXME: I haven't checked the register sets of the following. */ |
7a78ae4e | 2665 | {"rs1", "IBM POWER RS1", bfd_arch_rs6000, |
7cc46491 | 2666 | bfd_mach_rs6k_rs1, &tdesc_rs6000}, |
7a78ae4e | 2667 | {"rsc", "IBM POWER RSC", bfd_arch_rs6000, |
7cc46491 | 2668 | bfd_mach_rs6k_rsc, &tdesc_rs6000}, |
7a78ae4e | 2669 | {"rs2", "IBM POWER RS2", bfd_arch_rs6000, |
7cc46491 | 2670 | bfd_mach_rs6k_rs2, &tdesc_rs6000}, |
7a78ae4e | 2671 | |
7cc46491 | 2672 | {0, 0, 0, 0, 0} |
c906108c SS |
2673 | }; |
2674 | ||
7a78ae4e | 2675 | /* Return the variant corresponding to architecture ARCH and machine number |
64366f1c | 2676 | MACH. If no such variant exists, return null. */ |
c906108c | 2677 | |
7a78ae4e ND |
2678 | static const struct variant * |
2679 | find_variant_by_arch (enum bfd_architecture arch, unsigned long mach) | |
c906108c | 2680 | { |
7a78ae4e | 2681 | const struct variant *v; |
c5aa993b | 2682 | |
7a78ae4e ND |
2683 | for (v = variants; v->name; v++) |
2684 | if (arch == v->arch && mach == v->mach) | |
2685 | return v; | |
c906108c | 2686 | |
7a78ae4e | 2687 | return NULL; |
c906108c | 2688 | } |
9364a0ef EZ |
2689 | |
2690 | static int | |
2691 | gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info) | |
2692 | { | |
ee4f0f76 DJ |
2693 | if (!info->disassembler_options) |
2694 | info->disassembler_options = "any"; | |
2695 | ||
4c6b5505 | 2696 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
9364a0ef EZ |
2697 | return print_insn_big_powerpc (memaddr, info); |
2698 | else | |
2699 | return print_insn_little_powerpc (memaddr, info); | |
2700 | } | |
7a78ae4e | 2701 | \f |
61a65099 KB |
2702 | static CORE_ADDR |
2703 | rs6000_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
2704 | { | |
3e8c568d | 2705 | return frame_unwind_register_unsigned (next_frame, |
8b164abb | 2706 | gdbarch_pc_regnum (gdbarch)); |
61a65099 KB |
2707 | } |
2708 | ||
2709 | static struct frame_id | |
2710 | rs6000_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
2711 | { | |
3e8c568d | 2712 | return frame_id_build (frame_unwind_register_unsigned |
8b164abb | 2713 | (next_frame, gdbarch_sp_regnum (gdbarch)), |
3e8c568d | 2714 | frame_pc_unwind (next_frame)); |
61a65099 KB |
2715 | } |
2716 | ||
2717 | struct rs6000_frame_cache | |
2718 | { | |
2719 | CORE_ADDR base; | |
2720 | CORE_ADDR initial_sp; | |
2721 | struct trad_frame_saved_reg *saved_regs; | |
2722 | }; | |
2723 | ||
2724 | static struct rs6000_frame_cache * | |
2725 | rs6000_frame_cache (struct frame_info *next_frame, void **this_cache) | |
2726 | { | |
2727 | struct rs6000_frame_cache *cache; | |
2728 | struct gdbarch *gdbarch = get_frame_arch (next_frame); | |
2729 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2730 | struct rs6000_framedata fdata; | |
2731 | int wordsize = tdep->wordsize; | |
e10b1c4c | 2732 | CORE_ADDR func, pc; |
61a65099 KB |
2733 | |
2734 | if ((*this_cache) != NULL) | |
2735 | return (*this_cache); | |
2736 | cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache); | |
2737 | (*this_cache) = cache; | |
2738 | cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); | |
2739 | ||
93d42b30 | 2740 | func = frame_func_unwind (next_frame, NORMAL_FRAME); |
e10b1c4c DJ |
2741 | pc = frame_pc_unwind (next_frame); |
2742 | skip_prologue (func, pc, &fdata); | |
2743 | ||
2744 | /* Figure out the parent's stack pointer. */ | |
2745 | ||
2746 | /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most | |
2747 | address of the current frame. Things might be easier if the | |
2748 | ->frame pointed to the outer-most address of the frame. In | |
2749 | the mean time, the address of the prev frame is used as the | |
2750 | base address of this frame. */ | |
3e8c568d | 2751 | cache->base = frame_unwind_register_unsigned |
8b164abb | 2752 | (next_frame, gdbarch_sp_regnum (gdbarch)); |
e10b1c4c DJ |
2753 | |
2754 | /* If the function appears to be frameless, check a couple of likely | |
2755 | indicators that we have simply failed to find the frame setup. | |
2756 | Two common cases of this are missing symbols (i.e. | |
2757 | frame_func_unwind returns the wrong address or 0), and assembly | |
2758 | stubs which have a fast exit path but set up a frame on the slow | |
2759 | path. | |
2760 | ||
2761 | If the LR appears to return to this function, then presume that | |
2762 | we have an ABI compliant frame that we failed to find. */ | |
2763 | if (fdata.frameless && fdata.lr_offset == 0) | |
61a65099 | 2764 | { |
e10b1c4c DJ |
2765 | CORE_ADDR saved_lr; |
2766 | int make_frame = 0; | |
2767 | ||
2768 | saved_lr = frame_unwind_register_unsigned (next_frame, | |
2769 | tdep->ppc_lr_regnum); | |
2770 | if (func == 0 && saved_lr == pc) | |
2771 | make_frame = 1; | |
2772 | else if (func != 0) | |
2773 | { | |
2774 | CORE_ADDR saved_func = get_pc_function_start (saved_lr); | |
2775 | if (func == saved_func) | |
2776 | make_frame = 1; | |
2777 | } | |
2778 | ||
2779 | if (make_frame) | |
2780 | { | |
2781 | fdata.frameless = 0; | |
de6a76fd | 2782 | fdata.lr_offset = tdep->lr_frame_offset; |
e10b1c4c | 2783 | } |
61a65099 | 2784 | } |
e10b1c4c DJ |
2785 | |
2786 | if (!fdata.frameless) | |
2787 | /* Frameless really means stackless. */ | |
2788 | cache->base = read_memory_addr (cache->base, wordsize); | |
2789 | ||
3e8c568d | 2790 | trad_frame_set_value (cache->saved_regs, |
8b164abb | 2791 | gdbarch_sp_regnum (gdbarch), cache->base); |
61a65099 KB |
2792 | |
2793 | /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr. | |
2794 | All fpr's from saved_fpr to fp31 are saved. */ | |
2795 | ||
2796 | if (fdata.saved_fpr >= 0) | |
2797 | { | |
2798 | int i; | |
2799 | CORE_ADDR fpr_addr = cache->base + fdata.fpr_offset; | |
383f0f5b JB |
2800 | |
2801 | /* If skip_prologue says floating-point registers were saved, | |
2802 | but the current architecture has no floating-point registers, | |
2803 | then that's strange. But we have no indices to even record | |
2804 | the addresses under, so we just ignore it. */ | |
2805 | if (ppc_floating_point_unit_p (gdbarch)) | |
063715bf | 2806 | for (i = fdata.saved_fpr; i < ppc_num_fprs; i++) |
383f0f5b JB |
2807 | { |
2808 | cache->saved_regs[tdep->ppc_fp0_regnum + i].addr = fpr_addr; | |
2809 | fpr_addr += 8; | |
2810 | } | |
61a65099 KB |
2811 | } |
2812 | ||
2813 | /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr. | |
2814 | All gpr's from saved_gpr to gpr31 are saved. */ | |
2815 | ||
2816 | if (fdata.saved_gpr >= 0) | |
2817 | { | |
2818 | int i; | |
2819 | CORE_ADDR gpr_addr = cache->base + fdata.gpr_offset; | |
063715bf | 2820 | for (i = fdata.saved_gpr; i < ppc_num_gprs; i++) |
61a65099 KB |
2821 | { |
2822 | cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = gpr_addr; | |
2823 | gpr_addr += wordsize; | |
2824 | } | |
2825 | } | |
2826 | ||
2827 | /* if != -1, fdata.saved_vr is the smallest number of saved_vr. | |
2828 | All vr's from saved_vr to vr31 are saved. */ | |
2829 | if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) | |
2830 | { | |
2831 | if (fdata.saved_vr >= 0) | |
2832 | { | |
2833 | int i; | |
2834 | CORE_ADDR vr_addr = cache->base + fdata.vr_offset; | |
2835 | for (i = fdata.saved_vr; i < 32; i++) | |
2836 | { | |
2837 | cache->saved_regs[tdep->ppc_vr0_regnum + i].addr = vr_addr; | |
2838 | vr_addr += register_size (gdbarch, tdep->ppc_vr0_regnum); | |
2839 | } | |
2840 | } | |
2841 | } | |
2842 | ||
2843 | /* if != -1, fdata.saved_ev is the smallest number of saved_ev. | |
2844 | All vr's from saved_ev to ev31 are saved. ????? */ | |
2845 | if (tdep->ppc_ev0_regnum != -1 && tdep->ppc_ev31_regnum != -1) | |
2846 | { | |
2847 | if (fdata.saved_ev >= 0) | |
2848 | { | |
2849 | int i; | |
2850 | CORE_ADDR ev_addr = cache->base + fdata.ev_offset; | |
063715bf | 2851 | for (i = fdata.saved_ev; i < ppc_num_gprs; i++) |
61a65099 KB |
2852 | { |
2853 | cache->saved_regs[tdep->ppc_ev0_regnum + i].addr = ev_addr; | |
2854 | cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + 4; | |
2855 | ev_addr += register_size (gdbarch, tdep->ppc_ev0_regnum); | |
2856 | } | |
2857 | } | |
2858 | } | |
2859 | ||
2860 | /* If != 0, fdata.cr_offset is the offset from the frame that | |
2861 | holds the CR. */ | |
2862 | if (fdata.cr_offset != 0) | |
2863 | cache->saved_regs[tdep->ppc_cr_regnum].addr = cache->base + fdata.cr_offset; | |
2864 | ||
2865 | /* If != 0, fdata.lr_offset is the offset from the frame that | |
2866 | holds the LR. */ | |
2867 | if (fdata.lr_offset != 0) | |
2868 | cache->saved_regs[tdep->ppc_lr_regnum].addr = cache->base + fdata.lr_offset; | |
2869 | /* The PC is found in the link register. */ | |
8b164abb | 2870 | cache->saved_regs[gdbarch_pc_regnum (gdbarch)] = |
3e8c568d | 2871 | cache->saved_regs[tdep->ppc_lr_regnum]; |
61a65099 KB |
2872 | |
2873 | /* If != 0, fdata.vrsave_offset is the offset from the frame that | |
2874 | holds the VRSAVE. */ | |
2875 | if (fdata.vrsave_offset != 0) | |
2876 | cache->saved_regs[tdep->ppc_vrsave_regnum].addr = cache->base + fdata.vrsave_offset; | |
2877 | ||
2878 | if (fdata.alloca_reg < 0) | |
2879 | /* If no alloca register used, then fi->frame is the value of the | |
2880 | %sp for this frame, and it is good enough. */ | |
3e8c568d | 2881 | cache->initial_sp = frame_unwind_register_unsigned |
8b164abb | 2882 | (next_frame, gdbarch_sp_regnum (gdbarch)); |
61a65099 KB |
2883 | else |
2884 | cache->initial_sp = frame_unwind_register_unsigned (next_frame, | |
2885 | fdata.alloca_reg); | |
2886 | ||
2887 | return cache; | |
2888 | } | |
2889 | ||
2890 | static void | |
2891 | rs6000_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
2892 | struct frame_id *this_id) | |
2893 | { | |
2894 | struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame, | |
2895 | this_cache); | |
93d42b30 DJ |
2896 | (*this_id) = frame_id_build (info->base, |
2897 | frame_func_unwind (next_frame, NORMAL_FRAME)); | |
61a65099 KB |
2898 | } |
2899 | ||
2900 | static void | |
2901 | rs6000_frame_prev_register (struct frame_info *next_frame, | |
2902 | void **this_cache, | |
2903 | int regnum, int *optimizedp, | |
2904 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
50fd1280 | 2905 | int *realnump, gdb_byte *valuep) |
61a65099 KB |
2906 | { |
2907 | struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame, | |
2908 | this_cache); | |
1f67027d AC |
2909 | trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, |
2910 | optimizedp, lvalp, addrp, realnump, valuep); | |
61a65099 KB |
2911 | } |
2912 | ||
2913 | static const struct frame_unwind rs6000_frame_unwind = | |
2914 | { | |
2915 | NORMAL_FRAME, | |
2916 | rs6000_frame_this_id, | |
2917 | rs6000_frame_prev_register | |
2918 | }; | |
2919 | ||
2920 | static const struct frame_unwind * | |
2921 | rs6000_frame_sniffer (struct frame_info *next_frame) | |
2922 | { | |
2923 | return &rs6000_frame_unwind; | |
2924 | } | |
2925 | ||
2926 | \f | |
2927 | ||
2928 | static CORE_ADDR | |
2929 | rs6000_frame_base_address (struct frame_info *next_frame, | |
2930 | void **this_cache) | |
2931 | { | |
2932 | struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame, | |
2933 | this_cache); | |
2934 | return info->initial_sp; | |
2935 | } | |
2936 | ||
2937 | static const struct frame_base rs6000_frame_base = { | |
2938 | &rs6000_frame_unwind, | |
2939 | rs6000_frame_base_address, | |
2940 | rs6000_frame_base_address, | |
2941 | rs6000_frame_base_address | |
2942 | }; | |
2943 | ||
2944 | static const struct frame_base * | |
2945 | rs6000_frame_base_sniffer (struct frame_info *next_frame) | |
2946 | { | |
2947 | return &rs6000_frame_base; | |
2948 | } | |
2949 | ||
7a78ae4e ND |
2950 | /* Initialize the current architecture based on INFO. If possible, re-use an |
2951 | architecture from ARCHES, which is a list of architectures already created | |
2952 | during this debugging session. | |
c906108c | 2953 | |
7a78ae4e | 2954 | Called e.g. at program startup, when reading a core file, and when reading |
64366f1c | 2955 | a binary file. */ |
c906108c | 2956 | |
7a78ae4e ND |
2957 | static struct gdbarch * |
2958 | rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
2959 | { | |
2960 | struct gdbarch *gdbarch; | |
2961 | struct gdbarch_tdep *tdep; | |
7cc46491 | 2962 | int wordsize, from_xcoff_exec, from_elf_exec; |
7a78ae4e ND |
2963 | enum bfd_architecture arch; |
2964 | unsigned long mach; | |
2965 | bfd abfd; | |
7b112f9c | 2966 | int sysv_abi; |
5bf1c677 | 2967 | asection *sect; |
7cc46491 DJ |
2968 | int have_fpu = 1, have_spe = 0, have_mq = 0, have_altivec = 0; |
2969 | int tdesc_wordsize = -1; | |
2970 | const struct target_desc *tdesc = info.target_desc; | |
2971 | struct tdesc_arch_data *tdesc_data = NULL; | |
2972 | int num_sprs = 0; | |
7a78ae4e | 2973 | |
9aa1e687 | 2974 | from_xcoff_exec = info.abfd && info.abfd->format == bfd_object && |
7a78ae4e ND |
2975 | bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour; |
2976 | ||
9aa1e687 KB |
2977 | from_elf_exec = info.abfd && info.abfd->format == bfd_object && |
2978 | bfd_get_flavour (info.abfd) == bfd_target_elf_flavour; | |
2979 | ||
2980 | sysv_abi = info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour; | |
2981 | ||
e712c1cf | 2982 | /* Check word size. If INFO is from a binary file, infer it from |
64366f1c | 2983 | that, else choose a likely default. */ |
9aa1e687 | 2984 | if (from_xcoff_exec) |
c906108c | 2985 | { |
11ed25ac | 2986 | if (bfd_xcoff_is_xcoff64 (info.abfd)) |
7a78ae4e ND |
2987 | wordsize = 8; |
2988 | else | |
2989 | wordsize = 4; | |
c906108c | 2990 | } |
9aa1e687 KB |
2991 | else if (from_elf_exec) |
2992 | { | |
2993 | if (elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
2994 | wordsize = 8; | |
2995 | else | |
2996 | wordsize = 4; | |
2997 | } | |
7cc46491 DJ |
2998 | else if (tdesc_has_registers (tdesc)) |
2999 | wordsize = -1; | |
c906108c | 3000 | else |
7a78ae4e | 3001 | { |
27b15785 KB |
3002 | if (info.bfd_arch_info != NULL && info.bfd_arch_info->bits_per_word != 0) |
3003 | wordsize = info.bfd_arch_info->bits_per_word / | |
3004 | info.bfd_arch_info->bits_per_byte; | |
3005 | else | |
3006 | wordsize = 4; | |
7a78ae4e | 3007 | } |
c906108c | 3008 | |
9aa1e687 | 3009 | if (!from_xcoff_exec) |
c906108c | 3010 | { |
b732d07d | 3011 | arch = info.bfd_arch_info->arch; |
7a78ae4e | 3012 | mach = info.bfd_arch_info->mach; |
c906108c | 3013 | } |
7a78ae4e | 3014 | else |
c906108c | 3015 | { |
7a78ae4e | 3016 | arch = bfd_arch_powerpc; |
35cec841 | 3017 | bfd_default_set_arch_mach (&abfd, arch, 0); |
7a78ae4e | 3018 | info.bfd_arch_info = bfd_get_arch_info (&abfd); |
35cec841 | 3019 | mach = info.bfd_arch_info->mach; |
7a78ae4e | 3020 | } |
5bf1c677 EZ |
3021 | |
3022 | /* For e500 executables, the apuinfo section is of help here. Such | |
3023 | section contains the identifier and revision number of each | |
3024 | Application-specific Processing Unit that is present on the | |
3025 | chip. The content of the section is determined by the assembler | |
3026 | which looks at each instruction and determines which unit (and | |
3027 | which version of it) can execute it. In our case we just look for | |
3028 | the existance of the section. */ | |
3029 | ||
3030 | if (info.abfd) | |
3031 | { | |
3032 | sect = bfd_get_section_by_name (info.abfd, ".PPC.EMB.apuinfo"); | |
3033 | if (sect) | |
3034 | { | |
3035 | arch = info.bfd_arch_info->arch; | |
3036 | mach = bfd_mach_ppc_e500; | |
3037 | bfd_default_set_arch_mach (&abfd, arch, mach); | |
3038 | info.bfd_arch_info = bfd_get_arch_info (&abfd); | |
3039 | } | |
3040 | } | |
3041 | ||
7cc46491 DJ |
3042 | /* Find a default target description which describes our register |
3043 | layout, if we do not already have one. */ | |
3044 | if (! tdesc_has_registers (tdesc)) | |
3045 | { | |
3046 | const struct variant *v; | |
3047 | ||
3048 | /* Choose variant. */ | |
3049 | v = find_variant_by_arch (arch, mach); | |
3050 | if (!v) | |
3051 | return NULL; | |
3052 | ||
3053 | tdesc = *v->tdesc; | |
3054 | } | |
3055 | ||
3056 | gdb_assert (tdesc_has_registers (tdesc)); | |
3057 | ||
3058 | /* Check any target description for validity. */ | |
3059 | if (tdesc_has_registers (tdesc)) | |
3060 | { | |
3061 | static const char *const gprs[] = { | |
3062 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
3063 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
3064 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
3065 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" | |
3066 | }; | |
3067 | static const char *const segment_regs[] = { | |
3068 | "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7", | |
3069 | "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15" | |
3070 | }; | |
3071 | const struct tdesc_feature *feature; | |
3072 | int i, valid_p; | |
3073 | static const char *const msr_names[] = { "msr", "ps" }; | |
3074 | static const char *const cr_names[] = { "cr", "cnd" }; | |
3075 | static const char *const ctr_names[] = { "ctr", "cnt" }; | |
3076 | ||
3077 | feature = tdesc_find_feature (tdesc, | |
3078 | "org.gnu.gdb.power.core"); | |
3079 | if (feature == NULL) | |
3080 | return NULL; | |
3081 | ||
3082 | tdesc_data = tdesc_data_alloc (); | |
3083 | ||
3084 | valid_p = 1; | |
3085 | for (i = 0; i < ppc_num_gprs; i++) | |
3086 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, gprs[i]); | |
3087 | valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_PC_REGNUM, | |
3088 | "pc"); | |
3089 | valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_LR_REGNUM, | |
3090 | "lr"); | |
3091 | valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_XER_REGNUM, | |
3092 | "xer"); | |
3093 | ||
3094 | /* Allow alternate names for these registers, to accomodate GDB's | |
3095 | historic naming. */ | |
3096 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data, | |
3097 | PPC_MSR_REGNUM, msr_names); | |
3098 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data, | |
3099 | PPC_CR_REGNUM, cr_names); | |
3100 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data, | |
3101 | PPC_CTR_REGNUM, ctr_names); | |
3102 | ||
3103 | if (!valid_p) | |
3104 | { | |
3105 | tdesc_data_cleanup (tdesc_data); | |
3106 | return NULL; | |
3107 | } | |
3108 | ||
3109 | have_mq = tdesc_numbered_register (feature, tdesc_data, PPC_MQ_REGNUM, | |
3110 | "mq"); | |
3111 | ||
3112 | tdesc_wordsize = tdesc_register_size (feature, "pc") / 8; | |
3113 | if (wordsize == -1) | |
3114 | wordsize = tdesc_wordsize; | |
3115 | ||
3116 | feature = tdesc_find_feature (tdesc, | |
3117 | "org.gnu.gdb.power.fpu"); | |
3118 | if (feature != NULL) | |
3119 | { | |
3120 | static const char *const fprs[] = { | |
3121 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
3122 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
3123 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
3124 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31" | |
3125 | }; | |
3126 | valid_p = 1; | |
3127 | for (i = 0; i < ppc_num_fprs; i++) | |
3128 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
3129 | PPC_F0_REGNUM + i, fprs[i]); | |
3130 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
3131 | PPC_FPSCR_REGNUM, "fpscr"); | |
3132 | ||
3133 | if (!valid_p) | |
3134 | { | |
3135 | tdesc_data_cleanup (tdesc_data); | |
3136 | return NULL; | |
3137 | } | |
3138 | have_fpu = 1; | |
3139 | } | |
3140 | else | |
3141 | have_fpu = 0; | |
3142 | ||
3143 | feature = tdesc_find_feature (tdesc, | |
3144 | "org.gnu.gdb.power.altivec"); | |
3145 | if (feature != NULL) | |
3146 | { | |
3147 | static const char *const vector_regs[] = { | |
3148 | "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7", | |
3149 | "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15", | |
3150 | "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23", | |
3151 | "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31" | |
3152 | }; | |
3153 | ||
3154 | valid_p = 1; | |
3155 | for (i = 0; i < ppc_num_gprs; i++) | |
3156 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
3157 | PPC_VR0_REGNUM + i, | |
3158 | vector_regs[i]); | |
3159 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
3160 | PPC_VSCR_REGNUM, "vscr"); | |
3161 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
3162 | PPC_VRSAVE_REGNUM, "vrsave"); | |
3163 | ||
3164 | if (have_spe || !valid_p) | |
3165 | { | |
3166 | tdesc_data_cleanup (tdesc_data); | |
3167 | return NULL; | |
3168 | } | |
3169 | have_altivec = 1; | |
3170 | } | |
3171 | else | |
3172 | have_altivec = 0; | |
3173 | ||
3174 | /* On machines supporting the SPE APU, the general-purpose registers | |
3175 | are 64 bits long. There are SIMD vector instructions to treat them | |
3176 | as pairs of floats, but the rest of the instruction set treats them | |
3177 | as 32-bit registers, and only operates on their lower halves. | |
3178 | ||
3179 | In the GDB regcache, we treat their high and low halves as separate | |
3180 | registers. The low halves we present as the general-purpose | |
3181 | registers, and then we have pseudo-registers that stitch together | |
3182 | the upper and lower halves and present them as pseudo-registers. | |
3183 | ||
3184 | Thus, the target description is expected to supply the upper | |
3185 | halves separately. */ | |
3186 | ||
3187 | feature = tdesc_find_feature (tdesc, | |
3188 | "org.gnu.gdb.power.spe"); | |
3189 | if (feature != NULL) | |
3190 | { | |
3191 | static const char *const upper_spe[] = { | |
3192 | "ev0h", "ev1h", "ev2h", "ev3h", | |
3193 | "ev4h", "ev5h", "ev6h", "ev7h", | |
3194 | "ev8h", "ev9h", "ev10h", "ev11h", | |
3195 | "ev12h", "ev13h", "ev14h", "ev15h", | |
3196 | "ev16h", "ev17h", "ev18h", "ev19h", | |
3197 | "ev20h", "ev21h", "ev22h", "ev23h", | |
3198 | "ev24h", "ev25h", "ev26h", "ev27h", | |
3199 | "ev28h", "ev29h", "ev30h", "ev31h" | |
3200 | }; | |
3201 | ||
3202 | valid_p = 1; | |
3203 | for (i = 0; i < ppc_num_gprs; i++) | |
3204 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
3205 | PPC_SPE_UPPER_GP0_REGNUM + i, | |
3206 | upper_spe[i]); | |
3207 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
3208 | PPC_SPE_ACC_REGNUM, "acc"); | |
3209 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
3210 | PPC_SPE_FSCR_REGNUM, "spefscr"); | |
3211 | ||
3212 | if (have_mq || have_fpu || !valid_p) | |
3213 | { | |
3214 | tdesc_data_cleanup (tdesc_data); | |
3215 | return NULL; | |
3216 | } | |
3217 | have_spe = 1; | |
3218 | } | |
3219 | else | |
3220 | have_spe = 0; | |
3221 | } | |
3222 | ||
3223 | /* If we have a 64-bit binary on a 32-bit target, complain. Also | |
3224 | complain for a 32-bit binary on a 64-bit target; we do not yet | |
3225 | support that. For instance, the 32-bit ABI routines expect | |
3226 | 32-bit GPRs. | |
3227 | ||
3228 | As long as there isn't an explicit target description, we'll | |
3229 | choose one based on the BFD architecture and get a word size | |
3230 | matching the binary (probably powerpc:common or | |
3231 | powerpc:common64). So there is only trouble if a 64-bit target | |
3232 | supplies a 64-bit description while debugging a 32-bit | |
3233 | binary. */ | |
3234 | if (tdesc_wordsize != -1 && tdesc_wordsize != wordsize) | |
3235 | { | |
3236 | tdesc_data_cleanup (tdesc_data); | |
3237 | return NULL; | |
3238 | } | |
3239 | ||
3240 | /* Find a candidate among extant architectures. */ | |
3241 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
3242 | arches != NULL; | |
3243 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
3244 | { | |
3245 | /* Word size in the various PowerPC bfd_arch_info structs isn't | |
3246 | meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform | |
3247 | separate word size check. */ | |
3248 | tdep = gdbarch_tdep (arches->gdbarch); | |
3249 | if (tdep && tdep->wordsize == wordsize) | |
3250 | { | |
3251 | if (tdesc_data != NULL) | |
3252 | tdesc_data_cleanup (tdesc_data); | |
3253 | return arches->gdbarch; | |
3254 | } | |
3255 | } | |
3256 | ||
3257 | /* None found, create a new architecture from INFO, whose bfd_arch_info | |
3258 | validity depends on the source: | |
3259 | - executable useless | |
3260 | - rs6000_host_arch() good | |
3261 | - core file good | |
3262 | - "set arch" trust blindly | |
3263 | - GDB startup useless but harmless */ | |
3264 | ||
3265 | tdep = XCALLOC (1, struct gdbarch_tdep); | |
3266 | tdep->wordsize = wordsize; | |
3267 | ||
7a78ae4e | 3268 | gdbarch = gdbarch_alloc (&info, tdep); |
7a78ae4e | 3269 | |
7cc46491 DJ |
3270 | tdep->ppc_gp0_regnum = PPC_R0_REGNUM; |
3271 | tdep->ppc_toc_regnum = PPC_R0_REGNUM + 2; | |
3272 | tdep->ppc_ps_regnum = PPC_MSR_REGNUM; | |
3273 | tdep->ppc_cr_regnum = PPC_CR_REGNUM; | |
3274 | tdep->ppc_lr_regnum = PPC_LR_REGNUM; | |
3275 | tdep->ppc_ctr_regnum = PPC_CTR_REGNUM; | |
3276 | tdep->ppc_xer_regnum = PPC_XER_REGNUM; | |
3277 | tdep->ppc_mq_regnum = have_mq ? PPC_MQ_REGNUM : -1; | |
3278 | ||
3279 | tdep->ppc_fp0_regnum = have_fpu ? PPC_F0_REGNUM : -1; | |
3280 | tdep->ppc_fpscr_regnum = have_fpu ? PPC_FPSCR_REGNUM : -1; | |
3281 | tdep->ppc_vr0_regnum = have_altivec ? PPC_VR0_REGNUM : -1; | |
3282 | tdep->ppc_vrsave_regnum = have_altivec ? PPC_VRSAVE_REGNUM : -1; | |
3283 | tdep->ppc_ev0_upper_regnum = have_spe ? PPC_SPE_UPPER_GP0_REGNUM : -1; | |
3284 | tdep->ppc_acc_regnum = have_spe ? PPC_SPE_ACC_REGNUM : -1; | |
3285 | tdep->ppc_spefscr_regnum = have_spe ? PPC_SPE_FSCR_REGNUM : -1; | |
3286 | ||
3287 | set_gdbarch_pc_regnum (gdbarch, PPC_PC_REGNUM); | |
3288 | set_gdbarch_sp_regnum (gdbarch, PPC_R0_REGNUM + 1); | |
3289 | set_gdbarch_deprecated_fp_regnum (gdbarch, PPC_R0_REGNUM + 1); | |
3290 | set_gdbarch_fp0_regnum (gdbarch, tdep->ppc_fp0_regnum); | |
9f643768 | 3291 | set_gdbarch_register_sim_regno (gdbarch, rs6000_register_sim_regno); |
7cc46491 DJ |
3292 | |
3293 | /* The XML specification for PowerPC sensibly calls the MSR "msr". | |
3294 | GDB traditionally called it "ps", though, so let GDB add an | |
3295 | alias. */ | |
3296 | set_gdbarch_ps_regnum (gdbarch, tdep->ppc_ps_regnum); | |
3297 | ||
afd48b75 | 3298 | if (sysv_abi && wordsize == 8) |
05580c65 | 3299 | set_gdbarch_return_value (gdbarch, ppc64_sysv_abi_return_value); |
e754ae69 | 3300 | else if (sysv_abi && wordsize == 4) |
05580c65 | 3301 | set_gdbarch_return_value (gdbarch, ppc_sysv_abi_return_value); |
afd48b75 | 3302 | else |
d217aaed | 3303 | set_gdbarch_return_value (gdbarch, rs6000_return_value); |
c8001721 | 3304 | |
baffbae0 JB |
3305 | /* Set lr_frame_offset. */ |
3306 | if (wordsize == 8) | |
3307 | tdep->lr_frame_offset = 16; | |
3308 | else if (sysv_abi) | |
3309 | tdep->lr_frame_offset = 4; | |
3310 | else | |
3311 | tdep->lr_frame_offset = 8; | |
3312 | ||
7cc46491 DJ |
3313 | if (have_spe) |
3314 | { | |
3315 | set_gdbarch_pseudo_register_read (gdbarch, e500_pseudo_register_read); | |
3316 | set_gdbarch_pseudo_register_write (gdbarch, e500_pseudo_register_write); | |
3317 | } | |
1fcc0bb8 | 3318 | |
e0d24f8d WZ |
3319 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); |
3320 | ||
56a6dfb9 | 3321 | /* Select instruction printer. */ |
708ff411 | 3322 | if (arch == bfd_arch_rs6000) |
9364a0ef | 3323 | set_gdbarch_print_insn (gdbarch, print_insn_rs6000); |
56a6dfb9 | 3324 | else |
9364a0ef | 3325 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_powerpc); |
7495d1dc | 3326 | |
7cc46491 DJ |
3327 | set_gdbarch_num_regs (gdbarch, PPC_NUM_REGS + num_sprs); |
3328 | set_gdbarch_num_pseudo_regs (gdbarch, have_spe ? 32 : 0); | |
7a78ae4e ND |
3329 | |
3330 | set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT); | |
3331 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); | |
3332 | set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
3333 | set_gdbarch_long_bit (gdbarch, wordsize * TARGET_CHAR_BIT); | |
3334 | set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
3335 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
3336 | set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
ab9fe00e KB |
3337 | if (sysv_abi) |
3338 | set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT); | |
3339 | else | |
3340 | set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
4e409299 | 3341 | set_gdbarch_char_signed (gdbarch, 0); |
7a78ae4e | 3342 | |
11269d7e | 3343 | set_gdbarch_frame_align (gdbarch, rs6000_frame_align); |
8b148df9 AC |
3344 | if (sysv_abi && wordsize == 8) |
3345 | /* PPC64 SYSV. */ | |
3346 | set_gdbarch_frame_red_zone_size (gdbarch, 288); | |
3347 | else if (!sysv_abi && wordsize == 4) | |
5bffac25 AC |
3348 | /* PowerOpen / AIX 32 bit. The saved area or red zone consists of |
3349 | 19 4 byte GPRS + 18 8 byte FPRs giving a total of 220 bytes. | |
3350 | Problem is, 220 isn't frame (16 byte) aligned. Round it up to | |
3351 | 224. */ | |
3352 | set_gdbarch_frame_red_zone_size (gdbarch, 224); | |
7a78ae4e | 3353 | |
691d145a JB |
3354 | set_gdbarch_convert_register_p (gdbarch, rs6000_convert_register_p); |
3355 | set_gdbarch_register_to_value (gdbarch, rs6000_register_to_value); | |
3356 | set_gdbarch_value_to_register (gdbarch, rs6000_value_to_register); | |
3357 | ||
18ed0c4e JB |
3358 | set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_stab_reg_to_regnum); |
3359 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rs6000_dwarf2_reg_to_regnum); | |
d217aaed | 3360 | |
2ea5f656 | 3361 | if (sysv_abi && wordsize == 4) |
77b2b6d4 | 3362 | set_gdbarch_push_dummy_call (gdbarch, ppc_sysv_abi_push_dummy_call); |
8be9034a AC |
3363 | else if (sysv_abi && wordsize == 8) |
3364 | set_gdbarch_push_dummy_call (gdbarch, ppc64_sysv_abi_push_dummy_call); | |
9aa1e687 | 3365 | else |
77b2b6d4 | 3366 | set_gdbarch_push_dummy_call (gdbarch, rs6000_push_dummy_call); |
7a78ae4e | 3367 | |
7a78ae4e | 3368 | set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue); |
0d1243d9 PG |
3369 | set_gdbarch_in_function_epilogue_p (gdbarch, rs6000_in_function_epilogue_p); |
3370 | ||
7a78ae4e | 3371 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
7a78ae4e ND |
3372 | set_gdbarch_breakpoint_from_pc (gdbarch, rs6000_breakpoint_from_pc); |
3373 | ||
ce5eab59 UW |
3374 | /* Handles single stepping of atomic sequences. */ |
3375 | set_gdbarch_software_single_step (gdbarch, deal_with_atomic_sequence); | |
3376 | ||
6066c3de AC |
3377 | /* Handle the 64-bit SVR4 minimal-symbol convention of using "FN" |
3378 | for the descriptor and ".FN" for the entry-point -- a user | |
3379 | specifying "break FN" will unexpectedly end up with a breakpoint | |
3380 | on the descriptor and not the function. This architecture method | |
3381 | transforms any breakpoints on descriptors into breakpoints on the | |
3382 | corresponding entry point. */ | |
3383 | if (sysv_abi && wordsize == 8) | |
3384 | set_gdbarch_adjust_breakpoint_address (gdbarch, ppc64_sysv_abi_adjust_breakpoint_address); | |
3385 | ||
7a78ae4e ND |
3386 | /* Not sure on this. FIXMEmgo */ |
3387 | set_gdbarch_frame_args_skip (gdbarch, 8); | |
3388 | ||
15813d3f AC |
3389 | if (!sysv_abi) |
3390 | { | |
3391 | /* Handle RS/6000 function pointers (which are really function | |
3392 | descriptors). */ | |
f517ea4e PS |
3393 | set_gdbarch_convert_from_func_ptr_addr (gdbarch, |
3394 | rs6000_convert_from_func_ptr_addr); | |
9aa1e687 | 3395 | } |
7a78ae4e | 3396 | |
143985b7 AF |
3397 | /* Helpers for function argument information. */ |
3398 | set_gdbarch_fetch_pointer_argument (gdbarch, rs6000_fetch_pointer_argument); | |
3399 | ||
6f7f3f0d UW |
3400 | /* Trampoline. */ |
3401 | set_gdbarch_in_solib_return_trampoline | |
3402 | (gdbarch, rs6000_in_solib_return_trampoline); | |
3403 | set_gdbarch_skip_trampoline_code (gdbarch, rs6000_skip_trampoline_code); | |
3404 | ||
4fc771b8 DJ |
3405 | /* Hook in the DWARF CFI frame unwinder. */ |
3406 | frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer); | |
3407 | dwarf2_frame_set_adjust_regnum (gdbarch, rs6000_adjust_frame_regnum); | |
3408 | ||
7b112f9c | 3409 | /* Hook in ABI-specific overrides, if they have been registered. */ |
4be87837 | 3410 | gdbarch_init_osabi (info, gdbarch); |
7b112f9c | 3411 | |
61a65099 KB |
3412 | switch (info.osabi) |
3413 | { | |
f5aecab8 | 3414 | case GDB_OSABI_LINUX: |
61a65099 KB |
3415 | case GDB_OSABI_NETBSD_AOUT: |
3416 | case GDB_OSABI_NETBSD_ELF: | |
3417 | case GDB_OSABI_UNKNOWN: | |
61a65099 KB |
3418 | set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc); |
3419 | frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer); | |
3420 | set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id); | |
3421 | frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer); | |
3422 | break; | |
3423 | default: | |
61a65099 | 3424 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); |
81332287 KB |
3425 | |
3426 | set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc); | |
3427 | frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer); | |
3428 | set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id); | |
3429 | frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer); | |
61a65099 KB |
3430 | } |
3431 | ||
7cc46491 DJ |
3432 | set_tdesc_pseudo_register_type (gdbarch, rs6000_pseudo_register_type); |
3433 | set_tdesc_pseudo_register_reggroup_p (gdbarch, | |
3434 | rs6000_pseudo_register_reggroup_p); | |
3435 | tdesc_use_registers (gdbarch, tdesc, tdesc_data); | |
3436 | ||
3437 | /* Override the normal target description method to make the SPE upper | |
3438 | halves anonymous. */ | |
3439 | set_gdbarch_register_name (gdbarch, rs6000_register_name); | |
3440 | ||
3441 | /* Recording the numbering of pseudo registers. */ | |
3442 | tdep->ppc_ev0_regnum = have_spe ? gdbarch_num_regs (gdbarch) : -1; | |
3443 | tdep->ppc_ev31_regnum = have_spe ? tdep->ppc_ev0_regnum + 31 : -1; | |
9f643768 | 3444 | |
7a78ae4e | 3445 | return gdbarch; |
c906108c SS |
3446 | } |
3447 | ||
7b112f9c | 3448 | static void |
8b164abb | 3449 | rs6000_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
7b112f9c | 3450 | { |
8b164abb | 3451 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7b112f9c JT |
3452 | |
3453 | if (tdep == NULL) | |
3454 | return; | |
3455 | ||
4be87837 | 3456 | /* FIXME: Dump gdbarch_tdep. */ |
7b112f9c JT |
3457 | } |
3458 | ||
c906108c SS |
3459 | /* Initialization code. */ |
3460 | ||
a78f21af | 3461 | extern initialize_file_ftype _initialize_rs6000_tdep; /* -Wmissing-prototypes */ |
b9362cc7 | 3462 | |
c906108c | 3463 | void |
fba45db2 | 3464 | _initialize_rs6000_tdep (void) |
c906108c | 3465 | { |
7b112f9c JT |
3466 | gdbarch_register (bfd_arch_rs6000, rs6000_gdbarch_init, rs6000_dump_tdep); |
3467 | gdbarch_register (bfd_arch_powerpc, rs6000_gdbarch_init, rs6000_dump_tdep); | |
7cc46491 DJ |
3468 | |
3469 | /* Initialize the standard target descriptions. */ | |
3470 | initialize_tdesc_powerpc_32 (); | |
3471 | initialize_tdesc_powerpc_403 (); | |
3472 | initialize_tdesc_powerpc_403gc (); | |
3473 | initialize_tdesc_powerpc_505 (); | |
3474 | initialize_tdesc_powerpc_601 (); | |
3475 | initialize_tdesc_powerpc_602 (); | |
3476 | initialize_tdesc_powerpc_603 (); | |
3477 | initialize_tdesc_powerpc_604 (); | |
3478 | initialize_tdesc_powerpc_64 (); | |
3479 | initialize_tdesc_powerpc_7400 (); | |
3480 | initialize_tdesc_powerpc_750 (); | |
3481 | initialize_tdesc_powerpc_860 (); | |
3482 | initialize_tdesc_powerpc_e500 (); | |
3483 | initialize_tdesc_rs6000 (); | |
c906108c | 3484 | } |