Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for GDB, the GNU debugger. |
7aea86e6 | 2 | |
e2882c85 | 3 | Copyright (C) 1986-2018 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 10 | (at your option) any later version. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b | 17 | You should have received a copy of the GNU General Public License |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
19 | |
20 | #include "defs.h" | |
21 | #include "frame.h" | |
22 | #include "inferior.h" | |
45741a9c | 23 | #include "infrun.h" |
c906108c SS |
24 | #include "symtab.h" |
25 | #include "target.h" | |
26 | #include "gdbcore.h" | |
27 | #include "gdbcmd.h" | |
c906108c | 28 | #include "objfiles.h" |
7a78ae4e | 29 | #include "arch-utils.h" |
4e052eda | 30 | #include "regcache.h" |
d195bc9f | 31 | #include "regset.h" |
3b2ca824 | 32 | #include "target-float.h" |
fd0407d6 | 33 | #include "value.h" |
1fcc0bb8 | 34 | #include "parser-defs.h" |
4be87837 | 35 | #include "osabi.h" |
7d9b040b | 36 | #include "infcall.h" |
9f643768 JB |
37 | #include "sim-regno.h" |
38 | #include "gdb/sim-ppc.h" | |
6ced10dd | 39 | #include "reggroups.h" |
4fc771b8 | 40 | #include "dwarf2-frame.h" |
7cc46491 DJ |
41 | #include "target-descriptions.h" |
42 | #include "user-regs.h" | |
b4cdae6f WW |
43 | #include "record-full.h" |
44 | #include "auxv.h" | |
7a78ae4e | 45 | |
7a78ae4e | 46 | #include "coff/internal.h" /* for libcoff.h */ |
2fccf04a | 47 | #include "libcoff.h" /* for xcoff_data */ |
11ed25ac KB |
48 | #include "coff/xcoff.h" |
49 | #include "libxcoff.h" | |
7a78ae4e | 50 | |
9aa1e687 | 51 | #include "elf-bfd.h" |
55eddb0f | 52 | #include "elf/ppc.h" |
cd453cd0 | 53 | #include "elf/ppc64.h" |
7a78ae4e | 54 | |
6ded7999 | 55 | #include "solib-svr4.h" |
9aa1e687 | 56 | #include "ppc-tdep.h" |
debb1f09 | 57 | #include "ppc-ravenscar-thread.h" |
7a78ae4e | 58 | |
a89aa300 | 59 | #include "dis-asm.h" |
338ef23d | 60 | |
61a65099 KB |
61 | #include "trad-frame.h" |
62 | #include "frame-unwind.h" | |
63 | #include "frame-base.h" | |
64 | ||
a67914de MK |
65 | #include "ax.h" |
66 | #include "ax-gdb.h" | |
325fac50 | 67 | #include <algorithm> |
a67914de | 68 | |
7cc46491 | 69 | #include "features/rs6000/powerpc-32.c" |
7284e1be | 70 | #include "features/rs6000/powerpc-altivec32.c" |
604c2f83 | 71 | #include "features/rs6000/powerpc-vsx32.c" |
7cc46491 DJ |
72 | #include "features/rs6000/powerpc-403.c" |
73 | #include "features/rs6000/powerpc-403gc.c" | |
4d09ffea | 74 | #include "features/rs6000/powerpc-405.c" |
7cc46491 DJ |
75 | #include "features/rs6000/powerpc-505.c" |
76 | #include "features/rs6000/powerpc-601.c" | |
77 | #include "features/rs6000/powerpc-602.c" | |
78 | #include "features/rs6000/powerpc-603.c" | |
79 | #include "features/rs6000/powerpc-604.c" | |
80 | #include "features/rs6000/powerpc-64.c" | |
7284e1be | 81 | #include "features/rs6000/powerpc-altivec64.c" |
604c2f83 | 82 | #include "features/rs6000/powerpc-vsx64.c" |
7cc46491 DJ |
83 | #include "features/rs6000/powerpc-7400.c" |
84 | #include "features/rs6000/powerpc-750.c" | |
85 | #include "features/rs6000/powerpc-860.c" | |
86 | #include "features/rs6000/powerpc-e500.c" | |
87 | #include "features/rs6000/rs6000.c" | |
88 | ||
5a9e69ba TJB |
89 | /* Determine if regnum is an SPE pseudo-register. */ |
90 | #define IS_SPE_PSEUDOREG(tdep, regnum) ((tdep)->ppc_ev0_regnum >= 0 \ | |
91 | && (regnum) >= (tdep)->ppc_ev0_regnum \ | |
92 | && (regnum) < (tdep)->ppc_ev0_regnum + 32) | |
93 | ||
f949c649 TJB |
94 | /* Determine if regnum is a decimal float pseudo-register. */ |
95 | #define IS_DFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_dl0_regnum >= 0 \ | |
96 | && (regnum) >= (tdep)->ppc_dl0_regnum \ | |
97 | && (regnum) < (tdep)->ppc_dl0_regnum + 16) | |
98 | ||
604c2f83 LM |
99 | /* Determine if regnum is a POWER7 VSX register. */ |
100 | #define IS_VSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_vsr0_regnum >= 0 \ | |
101 | && (regnum) >= (tdep)->ppc_vsr0_regnum \ | |
102 | && (regnum) < (tdep)->ppc_vsr0_regnum + ppc_num_vsrs) | |
103 | ||
104 | /* Determine if regnum is a POWER7 Extended FP register. */ | |
105 | #define IS_EFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_efpr0_regnum >= 0 \ | |
106 | && (regnum) >= (tdep)->ppc_efpr0_regnum \ | |
d9492458 | 107 | && (regnum) < (tdep)->ppc_efpr0_regnum + ppc_num_efprs) |
604c2f83 | 108 | |
65b48a81 PB |
109 | /* Holds the current set of options to be passed to the disassembler. */ |
110 | static char *powerpc_disassembler_options; | |
111 | ||
55eddb0f DJ |
112 | /* The list of available "set powerpc ..." and "show powerpc ..." |
113 | commands. */ | |
114 | static struct cmd_list_element *setpowerpccmdlist = NULL; | |
115 | static struct cmd_list_element *showpowerpccmdlist = NULL; | |
116 | ||
117 | static enum auto_boolean powerpc_soft_float_global = AUTO_BOOLEAN_AUTO; | |
118 | ||
119 | /* The vector ABI to use. Keep this in sync with powerpc_vector_abi. */ | |
40478521 | 120 | static const char *const powerpc_vector_strings[] = |
55eddb0f DJ |
121 | { |
122 | "auto", | |
123 | "generic", | |
124 | "altivec", | |
125 | "spe", | |
126 | NULL | |
127 | }; | |
128 | ||
129 | /* A variable that can be configured by the user. */ | |
130 | static enum powerpc_vector_abi powerpc_vector_abi_global = POWERPC_VEC_AUTO; | |
131 | static const char *powerpc_vector_abi_string = "auto"; | |
132 | ||
0df8b418 | 133 | /* To be used by skip_prologue. */ |
7a78ae4e ND |
134 | |
135 | struct rs6000_framedata | |
136 | { | |
137 | int offset; /* total size of frame --- the distance | |
138 | by which we decrement sp to allocate | |
139 | the frame */ | |
140 | int saved_gpr; /* smallest # of saved gpr */ | |
46a9b8ed | 141 | unsigned int gpr_mask; /* Each bit is an individual saved GPR. */ |
7a78ae4e | 142 | int saved_fpr; /* smallest # of saved fpr */ |
6be8bc0c | 143 | int saved_vr; /* smallest # of saved vr */ |
96ff0de4 | 144 | int saved_ev; /* smallest # of saved ev */ |
7a78ae4e | 145 | int alloca_reg; /* alloca register number (frame ptr) */ |
0df8b418 MS |
146 | char frameless; /* true if frameless functions. */ |
147 | char nosavedpc; /* true if pc not saved. */ | |
46a9b8ed | 148 | char used_bl; /* true if link register clobbered */ |
7a78ae4e ND |
149 | int gpr_offset; /* offset of saved gprs from prev sp */ |
150 | int fpr_offset; /* offset of saved fprs from prev sp */ | |
6be8bc0c | 151 | int vr_offset; /* offset of saved vrs from prev sp */ |
96ff0de4 | 152 | int ev_offset; /* offset of saved evs from prev sp */ |
7a78ae4e | 153 | int lr_offset; /* offset of saved lr */ |
46a9b8ed | 154 | int lr_register; /* register of saved lr, if trustworthy */ |
7a78ae4e | 155 | int cr_offset; /* offset of saved cr */ |
6be8bc0c | 156 | int vrsave_offset; /* offset of saved vrsave register */ |
7a78ae4e ND |
157 | }; |
158 | ||
c906108c | 159 | |
604c2f83 LM |
160 | /* Is REGNO a VSX register? Return 1 if so, 0 otherwise. */ |
161 | int | |
162 | vsx_register_p (struct gdbarch *gdbarch, int regno) | |
163 | { | |
164 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
165 | if (tdep->ppc_vsr0_regnum < 0) | |
166 | return 0; | |
167 | else | |
168 | return (regno >= tdep->ppc_vsr0_upper_regnum && regno | |
169 | <= tdep->ppc_vsr0_upper_regnum + 31); | |
170 | } | |
171 | ||
64b84175 KB |
172 | /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */ |
173 | int | |
be8626e0 | 174 | altivec_register_p (struct gdbarch *gdbarch, int regno) |
64b84175 | 175 | { |
be8626e0 | 176 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
64b84175 KB |
177 | if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0) |
178 | return 0; | |
179 | else | |
180 | return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum); | |
181 | } | |
182 | ||
383f0f5b | 183 | |
867e2dc5 JB |
184 | /* Return true if REGNO is an SPE register, false otherwise. */ |
185 | int | |
be8626e0 | 186 | spe_register_p (struct gdbarch *gdbarch, int regno) |
867e2dc5 | 187 | { |
be8626e0 | 188 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
867e2dc5 JB |
189 | |
190 | /* Is it a reference to EV0 -- EV31, and do we have those? */ | |
5a9e69ba | 191 | if (IS_SPE_PSEUDOREG (tdep, regno)) |
867e2dc5 JB |
192 | return 1; |
193 | ||
6ced10dd JB |
194 | /* Is it a reference to one of the raw upper GPR halves? */ |
195 | if (tdep->ppc_ev0_upper_regnum >= 0 | |
196 | && tdep->ppc_ev0_upper_regnum <= regno | |
197 | && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) | |
198 | return 1; | |
199 | ||
867e2dc5 JB |
200 | /* Is it a reference to the 64-bit accumulator, and do we have that? */ |
201 | if (tdep->ppc_acc_regnum >= 0 | |
202 | && tdep->ppc_acc_regnum == regno) | |
203 | return 1; | |
204 | ||
205 | /* Is it a reference to the SPE floating-point status and control register, | |
206 | and do we have that? */ | |
207 | if (tdep->ppc_spefscr_regnum >= 0 | |
208 | && tdep->ppc_spefscr_regnum == regno) | |
209 | return 1; | |
210 | ||
211 | return 0; | |
212 | } | |
213 | ||
214 | ||
383f0f5b JB |
215 | /* Return non-zero if the architecture described by GDBARCH has |
216 | floating-point registers (f0 --- f31 and fpscr). */ | |
0a613259 AC |
217 | int |
218 | ppc_floating_point_unit_p (struct gdbarch *gdbarch) | |
219 | { | |
383f0f5b JB |
220 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
221 | ||
222 | return (tdep->ppc_fp0_regnum >= 0 | |
223 | && tdep->ppc_fpscr_regnum >= 0); | |
0a613259 | 224 | } |
9f643768 | 225 | |
06caf7d2 CES |
226 | /* Return non-zero if the architecture described by GDBARCH has |
227 | Altivec registers (vr0 --- vr31, vrsave and vscr). */ | |
228 | int | |
229 | ppc_altivec_support_p (struct gdbarch *gdbarch) | |
230 | { | |
231 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
232 | ||
233 | return (tdep->ppc_vr0_regnum >= 0 | |
234 | && tdep->ppc_vrsave_regnum >= 0); | |
235 | } | |
09991fa0 JB |
236 | |
237 | /* Check that TABLE[GDB_REGNO] is not already initialized, and then | |
238 | set it to SIM_REGNO. | |
239 | ||
240 | This is a helper function for init_sim_regno_table, constructing | |
241 | the table mapping GDB register numbers to sim register numbers; we | |
242 | initialize every element in that table to -1 before we start | |
243 | filling it in. */ | |
9f643768 JB |
244 | static void |
245 | set_sim_regno (int *table, int gdb_regno, int sim_regno) | |
246 | { | |
247 | /* Make sure we don't try to assign any given GDB register a sim | |
248 | register number more than once. */ | |
249 | gdb_assert (table[gdb_regno] == -1); | |
250 | table[gdb_regno] = sim_regno; | |
251 | } | |
252 | ||
09991fa0 JB |
253 | |
254 | /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register | |
255 | numbers to simulator register numbers, based on the values placed | |
256 | in the ARCH->tdep->ppc_foo_regnum members. */ | |
9f643768 JB |
257 | static void |
258 | init_sim_regno_table (struct gdbarch *arch) | |
259 | { | |
260 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); | |
7cc46491 | 261 | int total_regs = gdbarch_num_regs (arch); |
9f643768 JB |
262 | int *sim_regno = GDBARCH_OBSTACK_CALLOC (arch, total_regs, int); |
263 | int i; | |
7cc46491 DJ |
264 | static const char *const segment_regs[] = { |
265 | "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7", | |
266 | "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15" | |
267 | }; | |
9f643768 JB |
268 | |
269 | /* Presume that all registers not explicitly mentioned below are | |
270 | unavailable from the sim. */ | |
271 | for (i = 0; i < total_regs; i++) | |
272 | sim_regno[i] = -1; | |
273 | ||
274 | /* General-purpose registers. */ | |
275 | for (i = 0; i < ppc_num_gprs; i++) | |
276 | set_sim_regno (sim_regno, tdep->ppc_gp0_regnum + i, sim_ppc_r0_regnum + i); | |
277 | ||
278 | /* Floating-point registers. */ | |
279 | if (tdep->ppc_fp0_regnum >= 0) | |
280 | for (i = 0; i < ppc_num_fprs; i++) | |
281 | set_sim_regno (sim_regno, | |
282 | tdep->ppc_fp0_regnum + i, | |
283 | sim_ppc_f0_regnum + i); | |
284 | if (tdep->ppc_fpscr_regnum >= 0) | |
285 | set_sim_regno (sim_regno, tdep->ppc_fpscr_regnum, sim_ppc_fpscr_regnum); | |
286 | ||
287 | set_sim_regno (sim_regno, gdbarch_pc_regnum (arch), sim_ppc_pc_regnum); | |
288 | set_sim_regno (sim_regno, tdep->ppc_ps_regnum, sim_ppc_ps_regnum); | |
289 | set_sim_regno (sim_regno, tdep->ppc_cr_regnum, sim_ppc_cr_regnum); | |
290 | ||
291 | /* Segment registers. */ | |
7cc46491 DJ |
292 | for (i = 0; i < ppc_num_srs; i++) |
293 | { | |
294 | int gdb_regno; | |
295 | ||
296 | gdb_regno = user_reg_map_name_to_regnum (arch, segment_regs[i], -1); | |
297 | if (gdb_regno >= 0) | |
298 | set_sim_regno (sim_regno, gdb_regno, sim_ppc_sr0_regnum + i); | |
299 | } | |
9f643768 JB |
300 | |
301 | /* Altivec registers. */ | |
302 | if (tdep->ppc_vr0_regnum >= 0) | |
303 | { | |
304 | for (i = 0; i < ppc_num_vrs; i++) | |
305 | set_sim_regno (sim_regno, | |
306 | tdep->ppc_vr0_regnum + i, | |
307 | sim_ppc_vr0_regnum + i); | |
308 | ||
309 | /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum, | |
310 | we can treat this more like the other cases. */ | |
311 | set_sim_regno (sim_regno, | |
312 | tdep->ppc_vr0_regnum + ppc_num_vrs, | |
313 | sim_ppc_vscr_regnum); | |
314 | } | |
315 | /* vsave is a special-purpose register, so the code below handles it. */ | |
316 | ||
317 | /* SPE APU (E500) registers. */ | |
6ced10dd JB |
318 | if (tdep->ppc_ev0_upper_regnum >= 0) |
319 | for (i = 0; i < ppc_num_gprs; i++) | |
320 | set_sim_regno (sim_regno, | |
321 | tdep->ppc_ev0_upper_regnum + i, | |
322 | sim_ppc_rh0_regnum + i); | |
9f643768 JB |
323 | if (tdep->ppc_acc_regnum >= 0) |
324 | set_sim_regno (sim_regno, tdep->ppc_acc_regnum, sim_ppc_acc_regnum); | |
325 | /* spefscr is a special-purpose register, so the code below handles it. */ | |
326 | ||
976102cd | 327 | #ifdef WITH_PPC_SIM |
9f643768 JB |
328 | /* Now handle all special-purpose registers. Verify that they |
329 | haven't mistakenly been assigned numbers by any of the above | |
7cc46491 DJ |
330 | code. */ |
331 | for (i = 0; i < sim_ppc_num_sprs; i++) | |
332 | { | |
333 | const char *spr_name = sim_spr_register_name (i); | |
334 | int gdb_regno = -1; | |
335 | ||
336 | if (spr_name != NULL) | |
337 | gdb_regno = user_reg_map_name_to_regnum (arch, spr_name, -1); | |
338 | ||
339 | if (gdb_regno != -1) | |
340 | set_sim_regno (sim_regno, gdb_regno, sim_ppc_spr0_regnum + i); | |
341 | } | |
342 | #endif | |
9f643768 JB |
343 | |
344 | /* Drop the initialized array into place. */ | |
345 | tdep->sim_regno = sim_regno; | |
346 | } | |
347 | ||
09991fa0 JB |
348 | |
349 | /* Given a GDB register number REG, return the corresponding SIM | |
350 | register number. */ | |
9f643768 | 351 | static int |
e7faf938 | 352 | rs6000_register_sim_regno (struct gdbarch *gdbarch, int reg) |
9f643768 | 353 | { |
e7faf938 | 354 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
9f643768 JB |
355 | int sim_regno; |
356 | ||
7cc46491 | 357 | if (tdep->sim_regno == NULL) |
e7faf938 | 358 | init_sim_regno_table (gdbarch); |
7cc46491 | 359 | |
f57d151a | 360 | gdb_assert (0 <= reg |
e7faf938 MD |
361 | && reg <= gdbarch_num_regs (gdbarch) |
362 | + gdbarch_num_pseudo_regs (gdbarch)); | |
9f643768 JB |
363 | sim_regno = tdep->sim_regno[reg]; |
364 | ||
365 | if (sim_regno >= 0) | |
366 | return sim_regno; | |
367 | else | |
368 | return LEGACY_SIM_REGNO_IGNORE; | |
369 | } | |
370 | ||
d195bc9f MK |
371 | \f |
372 | ||
373 | /* Register set support functions. */ | |
374 | ||
f2db237a AM |
375 | /* REGS + OFFSET contains register REGNUM in a field REGSIZE wide. |
376 | Write the register to REGCACHE. */ | |
377 | ||
7284e1be | 378 | void |
d195bc9f | 379 | ppc_supply_reg (struct regcache *regcache, int regnum, |
f2db237a | 380 | const gdb_byte *regs, size_t offset, int regsize) |
d195bc9f MK |
381 | { |
382 | if (regnum != -1 && offset != -1) | |
f2db237a AM |
383 | { |
384 | if (regsize > 4) | |
385 | { | |
ac7936df | 386 | struct gdbarch *gdbarch = regcache->arch (); |
f2db237a AM |
387 | int gdb_regsize = register_size (gdbarch, regnum); |
388 | if (gdb_regsize < regsize | |
389 | && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
390 | offset += regsize - gdb_regsize; | |
391 | } | |
392 | regcache_raw_supply (regcache, regnum, regs + offset); | |
393 | } | |
d195bc9f MK |
394 | } |
395 | ||
f2db237a AM |
396 | /* Read register REGNUM from REGCACHE and store to REGS + OFFSET |
397 | in a field REGSIZE wide. Zero pad as necessary. */ | |
398 | ||
7284e1be | 399 | void |
d195bc9f | 400 | ppc_collect_reg (const struct regcache *regcache, int regnum, |
f2db237a | 401 | gdb_byte *regs, size_t offset, int regsize) |
d195bc9f MK |
402 | { |
403 | if (regnum != -1 && offset != -1) | |
f2db237a AM |
404 | { |
405 | if (regsize > 4) | |
406 | { | |
ac7936df | 407 | struct gdbarch *gdbarch = regcache->arch (); |
f2db237a AM |
408 | int gdb_regsize = register_size (gdbarch, regnum); |
409 | if (gdb_regsize < regsize) | |
410 | { | |
411 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
412 | { | |
413 | memset (regs + offset, 0, regsize - gdb_regsize); | |
414 | offset += regsize - gdb_regsize; | |
415 | } | |
416 | else | |
417 | memset (regs + offset + regsize - gdb_regsize, 0, | |
418 | regsize - gdb_regsize); | |
419 | } | |
420 | } | |
421 | regcache_raw_collect (regcache, regnum, regs + offset); | |
422 | } | |
d195bc9f MK |
423 | } |
424 | ||
f2db237a AM |
425 | static int |
426 | ppc_greg_offset (struct gdbarch *gdbarch, | |
427 | struct gdbarch_tdep *tdep, | |
428 | const struct ppc_reg_offsets *offsets, | |
429 | int regnum, | |
430 | int *regsize) | |
431 | { | |
432 | *regsize = offsets->gpr_size; | |
433 | if (regnum >= tdep->ppc_gp0_regnum | |
434 | && regnum < tdep->ppc_gp0_regnum + ppc_num_gprs) | |
435 | return (offsets->r0_offset | |
436 | + (regnum - tdep->ppc_gp0_regnum) * offsets->gpr_size); | |
437 | ||
438 | if (regnum == gdbarch_pc_regnum (gdbarch)) | |
439 | return offsets->pc_offset; | |
440 | ||
441 | if (regnum == tdep->ppc_ps_regnum) | |
442 | return offsets->ps_offset; | |
443 | ||
444 | if (regnum == tdep->ppc_lr_regnum) | |
445 | return offsets->lr_offset; | |
446 | ||
447 | if (regnum == tdep->ppc_ctr_regnum) | |
448 | return offsets->ctr_offset; | |
449 | ||
450 | *regsize = offsets->xr_size; | |
451 | if (regnum == tdep->ppc_cr_regnum) | |
452 | return offsets->cr_offset; | |
453 | ||
454 | if (regnum == tdep->ppc_xer_regnum) | |
455 | return offsets->xer_offset; | |
456 | ||
457 | if (regnum == tdep->ppc_mq_regnum) | |
458 | return offsets->mq_offset; | |
459 | ||
460 | return -1; | |
461 | } | |
462 | ||
463 | static int | |
464 | ppc_fpreg_offset (struct gdbarch_tdep *tdep, | |
465 | const struct ppc_reg_offsets *offsets, | |
466 | int regnum) | |
467 | { | |
468 | if (regnum >= tdep->ppc_fp0_regnum | |
469 | && regnum < tdep->ppc_fp0_regnum + ppc_num_fprs) | |
470 | return offsets->f0_offset + (regnum - tdep->ppc_fp0_regnum) * 8; | |
471 | ||
472 | if (regnum == tdep->ppc_fpscr_regnum) | |
473 | return offsets->fpscr_offset; | |
474 | ||
475 | return -1; | |
476 | } | |
477 | ||
d195bc9f MK |
478 | /* Supply register REGNUM in the general-purpose register set REGSET |
479 | from the buffer specified by GREGS and LEN to register cache | |
480 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
481 | ||
482 | void | |
483 | ppc_supply_gregset (const struct regset *regset, struct regcache *regcache, | |
484 | int regnum, const void *gregs, size_t len) | |
485 | { | |
ac7936df | 486 | struct gdbarch *gdbarch = regcache->arch (); |
d195bc9f | 487 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
19ba03f4 SM |
488 | const struct ppc_reg_offsets *offsets |
489 | = (const struct ppc_reg_offsets *) regset->regmap; | |
d195bc9f | 490 | size_t offset; |
f2db237a | 491 | int regsize; |
d195bc9f | 492 | |
f2db237a | 493 | if (regnum == -1) |
d195bc9f | 494 | { |
f2db237a AM |
495 | int i; |
496 | int gpr_size = offsets->gpr_size; | |
497 | ||
498 | for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset; | |
499 | i < tdep->ppc_gp0_regnum + ppc_num_gprs; | |
500 | i++, offset += gpr_size) | |
19ba03f4 SM |
501 | ppc_supply_reg (regcache, i, (const gdb_byte *) gregs, offset, |
502 | gpr_size); | |
f2db237a AM |
503 | |
504 | ppc_supply_reg (regcache, gdbarch_pc_regnum (gdbarch), | |
19ba03f4 | 505 | (const gdb_byte *) gregs, offsets->pc_offset, gpr_size); |
f2db237a | 506 | ppc_supply_reg (regcache, tdep->ppc_ps_regnum, |
19ba03f4 | 507 | (const gdb_byte *) gregs, offsets->ps_offset, gpr_size); |
f2db237a | 508 | ppc_supply_reg (regcache, tdep->ppc_lr_regnum, |
19ba03f4 | 509 | (const gdb_byte *) gregs, offsets->lr_offset, gpr_size); |
f2db237a | 510 | ppc_supply_reg (regcache, tdep->ppc_ctr_regnum, |
19ba03f4 | 511 | (const gdb_byte *) gregs, offsets->ctr_offset, gpr_size); |
f2db237a | 512 | ppc_supply_reg (regcache, tdep->ppc_cr_regnum, |
19ba03f4 SM |
513 | (const gdb_byte *) gregs, offsets->cr_offset, |
514 | offsets->xr_size); | |
f2db237a | 515 | ppc_supply_reg (regcache, tdep->ppc_xer_regnum, |
19ba03f4 SM |
516 | (const gdb_byte *) gregs, offsets->xer_offset, |
517 | offsets->xr_size); | |
f2db237a | 518 | ppc_supply_reg (regcache, tdep->ppc_mq_regnum, |
19ba03f4 SM |
519 | (const gdb_byte *) gregs, offsets->mq_offset, |
520 | offsets->xr_size); | |
f2db237a | 521 | return; |
d195bc9f MK |
522 | } |
523 | ||
f2db237a | 524 | offset = ppc_greg_offset (gdbarch, tdep, offsets, regnum, ®size); |
19ba03f4 | 525 | ppc_supply_reg (regcache, regnum, (const gdb_byte *) gregs, offset, regsize); |
d195bc9f MK |
526 | } |
527 | ||
528 | /* Supply register REGNUM in the floating-point register set REGSET | |
529 | from the buffer specified by FPREGS and LEN to register cache | |
530 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
531 | ||
532 | void | |
533 | ppc_supply_fpregset (const struct regset *regset, struct regcache *regcache, | |
534 | int regnum, const void *fpregs, size_t len) | |
535 | { | |
ac7936df | 536 | struct gdbarch *gdbarch = regcache->arch (); |
f2db237a AM |
537 | struct gdbarch_tdep *tdep; |
538 | const struct ppc_reg_offsets *offsets; | |
d195bc9f | 539 | size_t offset; |
d195bc9f | 540 | |
f2db237a AM |
541 | if (!ppc_floating_point_unit_p (gdbarch)) |
542 | return; | |
383f0f5b | 543 | |
f2db237a | 544 | tdep = gdbarch_tdep (gdbarch); |
19ba03f4 | 545 | offsets = (const struct ppc_reg_offsets *) regset->regmap; |
f2db237a | 546 | if (regnum == -1) |
d195bc9f | 547 | { |
f2db237a AM |
548 | int i; |
549 | ||
550 | for (i = tdep->ppc_fp0_regnum, offset = offsets->f0_offset; | |
551 | i < tdep->ppc_fp0_regnum + ppc_num_fprs; | |
552 | i++, offset += 8) | |
19ba03f4 | 553 | ppc_supply_reg (regcache, i, (const gdb_byte *) fpregs, offset, 8); |
f2db237a AM |
554 | |
555 | ppc_supply_reg (regcache, tdep->ppc_fpscr_regnum, | |
19ba03f4 SM |
556 | (const gdb_byte *) fpregs, offsets->fpscr_offset, |
557 | offsets->fpscr_size); | |
f2db237a | 558 | return; |
d195bc9f MK |
559 | } |
560 | ||
f2db237a | 561 | offset = ppc_fpreg_offset (tdep, offsets, regnum); |
19ba03f4 | 562 | ppc_supply_reg (regcache, regnum, (const gdb_byte *) fpregs, offset, |
f2db237a | 563 | regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8); |
d195bc9f MK |
564 | } |
565 | ||
566 | /* Collect register REGNUM in the general-purpose register set | |
f2db237a | 567 | REGSET from register cache REGCACHE into the buffer specified by |
d195bc9f MK |
568 | GREGS and LEN. If REGNUM is -1, do this for all registers in |
569 | REGSET. */ | |
570 | ||
571 | void | |
572 | ppc_collect_gregset (const struct regset *regset, | |
573 | const struct regcache *regcache, | |
574 | int regnum, void *gregs, size_t len) | |
575 | { | |
ac7936df | 576 | struct gdbarch *gdbarch = regcache->arch (); |
d195bc9f | 577 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
19ba03f4 SM |
578 | const struct ppc_reg_offsets *offsets |
579 | = (const struct ppc_reg_offsets *) regset->regmap; | |
d195bc9f | 580 | size_t offset; |
f2db237a | 581 | int regsize; |
d195bc9f | 582 | |
f2db237a | 583 | if (regnum == -1) |
d195bc9f | 584 | { |
f2db237a AM |
585 | int i; |
586 | int gpr_size = offsets->gpr_size; | |
587 | ||
588 | for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset; | |
589 | i < tdep->ppc_gp0_regnum + ppc_num_gprs; | |
590 | i++, offset += gpr_size) | |
19ba03f4 | 591 | ppc_collect_reg (regcache, i, (gdb_byte *) gregs, offset, gpr_size); |
f2db237a AM |
592 | |
593 | ppc_collect_reg (regcache, gdbarch_pc_regnum (gdbarch), | |
19ba03f4 | 594 | (gdb_byte *) gregs, offsets->pc_offset, gpr_size); |
f2db237a | 595 | ppc_collect_reg (regcache, tdep->ppc_ps_regnum, |
19ba03f4 | 596 | (gdb_byte *) gregs, offsets->ps_offset, gpr_size); |
f2db237a | 597 | ppc_collect_reg (regcache, tdep->ppc_lr_regnum, |
19ba03f4 | 598 | (gdb_byte *) gregs, offsets->lr_offset, gpr_size); |
f2db237a | 599 | ppc_collect_reg (regcache, tdep->ppc_ctr_regnum, |
19ba03f4 | 600 | (gdb_byte *) gregs, offsets->ctr_offset, gpr_size); |
f2db237a | 601 | ppc_collect_reg (regcache, tdep->ppc_cr_regnum, |
19ba03f4 SM |
602 | (gdb_byte *) gregs, offsets->cr_offset, |
603 | offsets->xr_size); | |
f2db237a | 604 | ppc_collect_reg (regcache, tdep->ppc_xer_regnum, |
19ba03f4 SM |
605 | (gdb_byte *) gregs, offsets->xer_offset, |
606 | offsets->xr_size); | |
f2db237a | 607 | ppc_collect_reg (regcache, tdep->ppc_mq_regnum, |
19ba03f4 SM |
608 | (gdb_byte *) gregs, offsets->mq_offset, |
609 | offsets->xr_size); | |
f2db237a | 610 | return; |
d195bc9f MK |
611 | } |
612 | ||
f2db237a | 613 | offset = ppc_greg_offset (gdbarch, tdep, offsets, regnum, ®size); |
19ba03f4 | 614 | ppc_collect_reg (regcache, regnum, (gdb_byte *) gregs, offset, regsize); |
d195bc9f MK |
615 | } |
616 | ||
617 | /* Collect register REGNUM in the floating-point register set | |
f2db237a | 618 | REGSET from register cache REGCACHE into the buffer specified by |
d195bc9f MK |
619 | FPREGS and LEN. If REGNUM is -1, do this for all registers in |
620 | REGSET. */ | |
621 | ||
622 | void | |
623 | ppc_collect_fpregset (const struct regset *regset, | |
624 | const struct regcache *regcache, | |
625 | int regnum, void *fpregs, size_t len) | |
626 | { | |
ac7936df | 627 | struct gdbarch *gdbarch = regcache->arch (); |
f2db237a AM |
628 | struct gdbarch_tdep *tdep; |
629 | const struct ppc_reg_offsets *offsets; | |
d195bc9f | 630 | size_t offset; |
d195bc9f | 631 | |
f2db237a AM |
632 | if (!ppc_floating_point_unit_p (gdbarch)) |
633 | return; | |
383f0f5b | 634 | |
f2db237a | 635 | tdep = gdbarch_tdep (gdbarch); |
19ba03f4 | 636 | offsets = (const struct ppc_reg_offsets *) regset->regmap; |
f2db237a | 637 | if (regnum == -1) |
d195bc9f | 638 | { |
f2db237a AM |
639 | int i; |
640 | ||
641 | for (i = tdep->ppc_fp0_regnum, offset = offsets->f0_offset; | |
642 | i < tdep->ppc_fp0_regnum + ppc_num_fprs; | |
643 | i++, offset += 8) | |
19ba03f4 | 644 | ppc_collect_reg (regcache, i, (gdb_byte *) fpregs, offset, 8); |
f2db237a AM |
645 | |
646 | ppc_collect_reg (regcache, tdep->ppc_fpscr_regnum, | |
19ba03f4 SM |
647 | (gdb_byte *) fpregs, offsets->fpscr_offset, |
648 | offsets->fpscr_size); | |
f2db237a | 649 | return; |
d195bc9f MK |
650 | } |
651 | ||
f2db237a | 652 | offset = ppc_fpreg_offset (tdep, offsets, regnum); |
19ba03f4 | 653 | ppc_collect_reg (regcache, regnum, (gdb_byte *) fpregs, offset, |
f2db237a | 654 | regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8); |
d195bc9f | 655 | } |
06caf7d2 | 656 | |
0d1243d9 PG |
657 | static int |
658 | insn_changes_sp_or_jumps (unsigned long insn) | |
659 | { | |
660 | int opcode = (insn >> 26) & 0x03f; | |
661 | int sd = (insn >> 21) & 0x01f; | |
662 | int a = (insn >> 16) & 0x01f; | |
663 | int subcode = (insn >> 1) & 0x3ff; | |
664 | ||
665 | /* Changes the stack pointer. */ | |
666 | ||
667 | /* NOTE: There are many ways to change the value of a given register. | |
668 | The ways below are those used when the register is R1, the SP, | |
669 | in a funtion's epilogue. */ | |
670 | ||
671 | if (opcode == 31 && subcode == 444 && a == 1) | |
672 | return 1; /* mr R1,Rn */ | |
673 | if (opcode == 14 && sd == 1) | |
674 | return 1; /* addi R1,Rn,simm */ | |
675 | if (opcode == 58 && sd == 1) | |
676 | return 1; /* ld R1,ds(Rn) */ | |
677 | ||
678 | /* Transfers control. */ | |
679 | ||
680 | if (opcode == 18) | |
681 | return 1; /* b */ | |
682 | if (opcode == 16) | |
683 | return 1; /* bc */ | |
684 | if (opcode == 19 && subcode == 16) | |
685 | return 1; /* bclr */ | |
686 | if (opcode == 19 && subcode == 528) | |
687 | return 1; /* bcctr */ | |
688 | ||
689 | return 0; | |
690 | } | |
691 | ||
692 | /* Return true if we are in the function's epilogue, i.e. after the | |
693 | instruction that destroyed the function's stack frame. | |
694 | ||
695 | 1) scan forward from the point of execution: | |
696 | a) If you find an instruction that modifies the stack pointer | |
697 | or transfers control (except a return), execution is not in | |
698 | an epilogue, return. | |
699 | b) Stop scanning if you find a return instruction or reach the | |
700 | end of the function or reach the hard limit for the size of | |
701 | an epilogue. | |
702 | 2) scan backward from the point of execution: | |
703 | a) If you find an instruction that modifies the stack pointer, | |
704 | execution *is* in an epilogue, return. | |
705 | b) Stop scanning if you reach an instruction that transfers | |
706 | control or the beginning of the function or reach the hard | |
707 | limit for the size of an epilogue. */ | |
708 | ||
709 | static int | |
2608dbf8 WW |
710 | rs6000_in_function_epilogue_frame_p (struct frame_info *curfrm, |
711 | struct gdbarch *gdbarch, CORE_ADDR pc) | |
0d1243d9 | 712 | { |
46a9b8ed | 713 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
e17a4113 | 714 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
0d1243d9 PG |
715 | bfd_byte insn_buf[PPC_INSN_SIZE]; |
716 | CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end; | |
717 | unsigned long insn; | |
0d1243d9 PG |
718 | |
719 | /* Find the search limits based on function boundaries and hard limit. */ | |
720 | ||
721 | if (!find_pc_partial_function (pc, NULL, &func_start, &func_end)) | |
722 | return 0; | |
723 | ||
724 | epilogue_start = pc - PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE; | |
725 | if (epilogue_start < func_start) epilogue_start = func_start; | |
726 | ||
727 | epilogue_end = pc + PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE; | |
728 | if (epilogue_end > func_end) epilogue_end = func_end; | |
729 | ||
0d1243d9 PG |
730 | /* Scan forward until next 'blr'. */ |
731 | ||
732 | for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += PPC_INSN_SIZE) | |
733 | { | |
734 | if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE)) | |
735 | return 0; | |
e17a4113 | 736 | insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE, byte_order); |
0d1243d9 PG |
737 | if (insn == 0x4e800020) |
738 | break; | |
46a9b8ed DJ |
739 | /* Assume a bctr is a tail call unless it points strictly within |
740 | this function. */ | |
741 | if (insn == 0x4e800420) | |
742 | { | |
743 | CORE_ADDR ctr = get_frame_register_unsigned (curfrm, | |
744 | tdep->ppc_ctr_regnum); | |
745 | if (ctr > func_start && ctr < func_end) | |
746 | return 0; | |
747 | else | |
748 | break; | |
749 | } | |
0d1243d9 PG |
750 | if (insn_changes_sp_or_jumps (insn)) |
751 | return 0; | |
752 | } | |
753 | ||
754 | /* Scan backward until adjustment to stack pointer (R1). */ | |
755 | ||
756 | for (scan_pc = pc - PPC_INSN_SIZE; | |
757 | scan_pc >= epilogue_start; | |
758 | scan_pc -= PPC_INSN_SIZE) | |
759 | { | |
760 | if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE)) | |
761 | return 0; | |
e17a4113 | 762 | insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE, byte_order); |
0d1243d9 PG |
763 | if (insn_changes_sp_or_jumps (insn)) |
764 | return 1; | |
765 | } | |
766 | ||
767 | return 0; | |
768 | } | |
769 | ||
c9cf6e20 | 770 | /* Implement the stack_frame_destroyed_p gdbarch method. */ |
2608dbf8 WW |
771 | |
772 | static int | |
c9cf6e20 | 773 | rs6000_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
2608dbf8 WW |
774 | { |
775 | return rs6000_in_function_epilogue_frame_p (get_current_frame (), | |
776 | gdbarch, pc); | |
777 | } | |
778 | ||
143985b7 | 779 | /* Get the ith function argument for the current function. */ |
b9362cc7 | 780 | static CORE_ADDR |
143985b7 AF |
781 | rs6000_fetch_pointer_argument (struct frame_info *frame, int argi, |
782 | struct type *type) | |
783 | { | |
50fd1280 | 784 | return get_frame_register_unsigned (frame, 3 + argi); |
143985b7 AF |
785 | } |
786 | ||
c906108c SS |
787 | /* Sequence of bytes for breakpoint instruction. */ |
788 | ||
04180708 YQ |
789 | constexpr gdb_byte big_breakpoint[] = { 0x7d, 0x82, 0x10, 0x08 }; |
790 | constexpr gdb_byte little_breakpoint[] = { 0x08, 0x10, 0x82, 0x7d }; | |
d19280ad | 791 | |
04180708 YQ |
792 | typedef BP_MANIPULATION_ENDIAN (little_breakpoint, big_breakpoint) |
793 | rs6000_breakpoint; | |
c906108c | 794 | |
f74c6cad LM |
795 | /* Instruction masks for displaced stepping. */ |
796 | #define BRANCH_MASK 0xfc000000 | |
797 | #define BP_MASK 0xFC0007FE | |
798 | #define B_INSN 0x48000000 | |
799 | #define BC_INSN 0x40000000 | |
800 | #define BXL_INSN 0x4c000000 | |
801 | #define BP_INSN 0x7C000008 | |
802 | ||
7f03bd92 PA |
803 | /* Instruction masks used during single-stepping of atomic |
804 | sequences. */ | |
2039d74e | 805 | #define LOAD_AND_RESERVE_MASK 0xfc0007fe |
7f03bd92 PA |
806 | #define LWARX_INSTRUCTION 0x7c000028 |
807 | #define LDARX_INSTRUCTION 0x7c0000A8 | |
2039d74e EBM |
808 | #define LBARX_INSTRUCTION 0x7c000068 |
809 | #define LHARX_INSTRUCTION 0x7c0000e8 | |
810 | #define LQARX_INSTRUCTION 0x7c000228 | |
811 | #define STORE_CONDITIONAL_MASK 0xfc0007ff | |
7f03bd92 PA |
812 | #define STWCX_INSTRUCTION 0x7c00012d |
813 | #define STDCX_INSTRUCTION 0x7c0001ad | |
2039d74e EBM |
814 | #define STBCX_INSTRUCTION 0x7c00056d |
815 | #define STHCX_INSTRUCTION 0x7c0005ad | |
816 | #define STQCX_INSTRUCTION 0x7c00016d | |
817 | ||
818 | /* Check if insn is one of the Load And Reserve instructions used for atomic | |
819 | sequences. */ | |
820 | #define IS_LOAD_AND_RESERVE_INSN(insn) ((insn & LOAD_AND_RESERVE_MASK) == LWARX_INSTRUCTION \ | |
821 | || (insn & LOAD_AND_RESERVE_MASK) == LDARX_INSTRUCTION \ | |
822 | || (insn & LOAD_AND_RESERVE_MASK) == LBARX_INSTRUCTION \ | |
823 | || (insn & LOAD_AND_RESERVE_MASK) == LHARX_INSTRUCTION \ | |
824 | || (insn & LOAD_AND_RESERVE_MASK) == LQARX_INSTRUCTION) | |
825 | /* Check if insn is one of the Store Conditional instructions used for atomic | |
826 | sequences. */ | |
827 | #define IS_STORE_CONDITIONAL_INSN(insn) ((insn & STORE_CONDITIONAL_MASK) == STWCX_INSTRUCTION \ | |
828 | || (insn & STORE_CONDITIONAL_MASK) == STDCX_INSTRUCTION \ | |
829 | || (insn & STORE_CONDITIONAL_MASK) == STBCX_INSTRUCTION \ | |
830 | || (insn & STORE_CONDITIONAL_MASK) == STHCX_INSTRUCTION \ | |
831 | || (insn & STORE_CONDITIONAL_MASK) == STQCX_INSTRUCTION) | |
7f03bd92 | 832 | |
cfba9872 SM |
833 | typedef buf_displaced_step_closure ppc_displaced_step_closure; |
834 | ||
c2508e90 | 835 | /* We can't displaced step atomic sequences. */ |
7f03bd92 PA |
836 | |
837 | static struct displaced_step_closure * | |
838 | ppc_displaced_step_copy_insn (struct gdbarch *gdbarch, | |
839 | CORE_ADDR from, CORE_ADDR to, | |
840 | struct regcache *regs) | |
841 | { | |
842 | size_t len = gdbarch_max_insn_length (gdbarch); | |
cfba9872 SM |
843 | std::unique_ptr<ppc_displaced_step_closure> closure |
844 | (new ppc_displaced_step_closure (len)); | |
845 | gdb_byte *buf = closure->buf.data (); | |
7f03bd92 PA |
846 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
847 | int insn; | |
848 | ||
849 | read_memory (from, buf, len); | |
850 | ||
851 | insn = extract_signed_integer (buf, PPC_INSN_SIZE, byte_order); | |
852 | ||
2039d74e EBM |
853 | /* Assume all atomic sequences start with a Load and Reserve instruction. */ |
854 | if (IS_LOAD_AND_RESERVE_INSN (insn)) | |
7f03bd92 PA |
855 | { |
856 | if (debug_displaced) | |
857 | { | |
858 | fprintf_unfiltered (gdb_stdlog, | |
859 | "displaced: can't displaced step " | |
860 | "atomic sequence at %s\n", | |
861 | paddress (gdbarch, from)); | |
862 | } | |
cfba9872 | 863 | |
7f03bd92 PA |
864 | return NULL; |
865 | } | |
866 | ||
867 | write_memory (to, buf, len); | |
868 | ||
869 | if (debug_displaced) | |
870 | { | |
871 | fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ", | |
872 | paddress (gdbarch, from), paddress (gdbarch, to)); | |
873 | displaced_step_dump_bytes (gdb_stdlog, buf, len); | |
874 | } | |
875 | ||
cfba9872 | 876 | return closure.release (); |
7f03bd92 PA |
877 | } |
878 | ||
f74c6cad LM |
879 | /* Fix up the state of registers and memory after having single-stepped |
880 | a displaced instruction. */ | |
63807e1d | 881 | static void |
f74c6cad | 882 | ppc_displaced_step_fixup (struct gdbarch *gdbarch, |
cfba9872 | 883 | struct displaced_step_closure *closure_, |
63807e1d PA |
884 | CORE_ADDR from, CORE_ADDR to, |
885 | struct regcache *regs) | |
f74c6cad | 886 | { |
e17a4113 | 887 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7f03bd92 | 888 | /* Our closure is a copy of the instruction. */ |
cfba9872 SM |
889 | ppc_displaced_step_closure *closure = (ppc_displaced_step_closure *) closure_; |
890 | ULONGEST insn = extract_unsigned_integer (closure->buf.data (), | |
891 | PPC_INSN_SIZE, byte_order); | |
f74c6cad LM |
892 | ULONGEST opcode = 0; |
893 | /* Offset for non PC-relative instructions. */ | |
894 | LONGEST offset = PPC_INSN_SIZE; | |
895 | ||
896 | opcode = insn & BRANCH_MASK; | |
897 | ||
898 | if (debug_displaced) | |
899 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 UW |
900 | "displaced: (ppc) fixup (%s, %s)\n", |
901 | paddress (gdbarch, from), paddress (gdbarch, to)); | |
f74c6cad LM |
902 | |
903 | ||
904 | /* Handle PC-relative branch instructions. */ | |
905 | if (opcode == B_INSN || opcode == BC_INSN || opcode == BXL_INSN) | |
906 | { | |
a4fafde3 | 907 | ULONGEST current_pc; |
f74c6cad LM |
908 | |
909 | /* Read the current PC value after the instruction has been executed | |
910 | in a displaced location. Calculate the offset to be applied to the | |
911 | original PC value before the displaced stepping. */ | |
912 | regcache_cooked_read_unsigned (regs, gdbarch_pc_regnum (gdbarch), | |
913 | ¤t_pc); | |
914 | offset = current_pc - to; | |
915 | ||
916 | if (opcode != BXL_INSN) | |
917 | { | |
918 | /* Check for AA bit indicating whether this is an absolute | |
919 | addressing or PC-relative (1: absolute, 0: relative). */ | |
920 | if (!(insn & 0x2)) | |
921 | { | |
922 | /* PC-relative addressing is being used in the branch. */ | |
923 | if (debug_displaced) | |
924 | fprintf_unfiltered | |
925 | (gdb_stdlog, | |
5af949e3 UW |
926 | "displaced: (ppc) branch instruction: %s\n" |
927 | "displaced: (ppc) adjusted PC from %s to %s\n", | |
928 | paddress (gdbarch, insn), paddress (gdbarch, current_pc), | |
929 | paddress (gdbarch, from + offset)); | |
f74c6cad | 930 | |
0df8b418 MS |
931 | regcache_cooked_write_unsigned (regs, |
932 | gdbarch_pc_regnum (gdbarch), | |
f74c6cad LM |
933 | from + offset); |
934 | } | |
935 | } | |
936 | else | |
937 | { | |
938 | /* If we're here, it means we have a branch to LR or CTR. If the | |
939 | branch was taken, the offset is probably greater than 4 (the next | |
940 | instruction), so it's safe to assume that an offset of 4 means we | |
941 | did not take the branch. */ | |
942 | if (offset == PPC_INSN_SIZE) | |
943 | regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch), | |
944 | from + PPC_INSN_SIZE); | |
945 | } | |
946 | ||
947 | /* Check for LK bit indicating whether we should set the link | |
948 | register to point to the next instruction | |
949 | (1: Set, 0: Don't set). */ | |
950 | if (insn & 0x1) | |
951 | { | |
952 | /* Link register needs to be set to the next instruction's PC. */ | |
953 | regcache_cooked_write_unsigned (regs, | |
954 | gdbarch_tdep (gdbarch)->ppc_lr_regnum, | |
955 | from + PPC_INSN_SIZE); | |
956 | if (debug_displaced) | |
957 | fprintf_unfiltered (gdb_stdlog, | |
5af949e3 UW |
958 | "displaced: (ppc) adjusted LR to %s\n", |
959 | paddress (gdbarch, from + PPC_INSN_SIZE)); | |
f74c6cad LM |
960 | |
961 | } | |
962 | } | |
963 | /* Check for breakpoints in the inferior. If we've found one, place the PC | |
964 | right at the breakpoint instruction. */ | |
965 | else if ((insn & BP_MASK) == BP_INSN) | |
966 | regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch), from); | |
967 | else | |
968 | /* Handle any other instructions that do not fit in the categories above. */ | |
969 | regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch), | |
970 | from + offset); | |
971 | } | |
c906108c | 972 | |
99e40580 UW |
973 | /* Always use hardware single-stepping to execute the |
974 | displaced instruction. */ | |
975 | static int | |
976 | ppc_displaced_step_hw_singlestep (struct gdbarch *gdbarch, | |
977 | struct displaced_step_closure *closure) | |
978 | { | |
979 | return 1; | |
980 | } | |
981 | ||
2039d74e EBM |
982 | /* Checks for an atomic sequence of instructions beginning with a |
983 | Load And Reserve instruction and ending with a Store Conditional | |
984 | instruction. If such a sequence is found, attempt to step through it. | |
985 | A breakpoint is placed at the end of the sequence. */ | |
a0ff9e1a | 986 | std::vector<CORE_ADDR> |
f5ea389a | 987 | ppc_deal_with_atomic_sequence (struct regcache *regcache) |
ce5eab59 | 988 | { |
ac7936df | 989 | struct gdbarch *gdbarch = regcache->arch (); |
e17a4113 | 990 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
41e26ad3 | 991 | CORE_ADDR pc = regcache_read_pc (regcache); |
ce5eab59 UW |
992 | CORE_ADDR breaks[2] = {-1, -1}; |
993 | CORE_ADDR loc = pc; | |
24d45690 | 994 | CORE_ADDR closing_insn; /* Instruction that closes the atomic sequence. */ |
e17a4113 | 995 | int insn = read_memory_integer (loc, PPC_INSN_SIZE, byte_order); |
ce5eab59 UW |
996 | int insn_count; |
997 | int index; | |
998 | int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ | |
999 | const int atomic_sequence_length = 16; /* Instruction sequence length. */ | |
ce5eab59 UW |
1000 | int bc_insn_count = 0; /* Conditional branch instruction count. */ |
1001 | ||
2039d74e EBM |
1002 | /* Assume all atomic sequences start with a Load And Reserve instruction. */ |
1003 | if (!IS_LOAD_AND_RESERVE_INSN (insn)) | |
a0ff9e1a | 1004 | return {}; |
ce5eab59 UW |
1005 | |
1006 | /* Assume that no atomic sequence is longer than "atomic_sequence_length" | |
1007 | instructions. */ | |
1008 | for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) | |
1009 | { | |
1010 | loc += PPC_INSN_SIZE; | |
e17a4113 | 1011 | insn = read_memory_integer (loc, PPC_INSN_SIZE, byte_order); |
ce5eab59 UW |
1012 | |
1013 | /* Assume that there is at most one conditional branch in the atomic | |
1014 | sequence. If a conditional branch is found, put a breakpoint in | |
1015 | its destination address. */ | |
f74c6cad | 1016 | if ((insn & BRANCH_MASK) == BC_INSN) |
ce5eab59 | 1017 | { |
a3769e0c AM |
1018 | int immediate = ((insn & 0xfffc) ^ 0x8000) - 0x8000; |
1019 | int absolute = insn & 2; | |
4a7622d1 | 1020 | |
ce5eab59 | 1021 | if (bc_insn_count >= 1) |
a0ff9e1a SM |
1022 | return {}; /* More than one conditional branch found, fallback |
1023 | to the standard single-step code. */ | |
4a7622d1 UW |
1024 | |
1025 | if (absolute) | |
1026 | breaks[1] = immediate; | |
1027 | else | |
a3769e0c | 1028 | breaks[1] = loc + immediate; |
4a7622d1 UW |
1029 | |
1030 | bc_insn_count++; | |
1031 | last_breakpoint++; | |
ce5eab59 UW |
1032 | } |
1033 | ||
2039d74e | 1034 | if (IS_STORE_CONDITIONAL_INSN (insn)) |
ce5eab59 UW |
1035 | break; |
1036 | } | |
1037 | ||
2039d74e EBM |
1038 | /* Assume that the atomic sequence ends with a Store Conditional |
1039 | instruction. */ | |
1040 | if (!IS_STORE_CONDITIONAL_INSN (insn)) | |
a0ff9e1a | 1041 | return {}; |
ce5eab59 | 1042 | |
24d45690 | 1043 | closing_insn = loc; |
ce5eab59 | 1044 | loc += PPC_INSN_SIZE; |
ce5eab59 UW |
1045 | |
1046 | /* Insert a breakpoint right after the end of the atomic sequence. */ | |
1047 | breaks[0] = loc; | |
1048 | ||
24d45690 | 1049 | /* Check for duplicated breakpoints. Check also for a breakpoint |
a3769e0c AM |
1050 | placed (branch instruction's destination) anywhere in sequence. */ |
1051 | if (last_breakpoint | |
1052 | && (breaks[1] == breaks[0] | |
1053 | || (breaks[1] >= pc && breaks[1] <= closing_insn))) | |
ce5eab59 UW |
1054 | last_breakpoint = 0; |
1055 | ||
a0ff9e1a SM |
1056 | std::vector<CORE_ADDR> next_pcs; |
1057 | ||
ce5eab59 | 1058 | for (index = 0; index <= last_breakpoint; index++) |
a0ff9e1a | 1059 | next_pcs.push_back (breaks[index]); |
ce5eab59 | 1060 | |
93f9a11f | 1061 | return next_pcs; |
ce5eab59 UW |
1062 | } |
1063 | ||
c906108c | 1064 | |
c906108c SS |
1065 | #define SIGNED_SHORT(x) \ |
1066 | ((sizeof (short) == 2) \ | |
1067 | ? ((int)(short)(x)) \ | |
1068 | : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000))) | |
1069 | ||
1070 | #define GET_SRC_REG(x) (((x) >> 21) & 0x1f) | |
1071 | ||
55d05f3b KB |
1072 | /* Limit the number of skipped non-prologue instructions, as the examining |
1073 | of the prologue is expensive. */ | |
1074 | static int max_skip_non_prologue_insns = 10; | |
1075 | ||
773df3e5 JB |
1076 | /* Return nonzero if the given instruction OP can be part of the prologue |
1077 | of a function and saves a parameter on the stack. FRAMEP should be | |
1078 | set if one of the previous instructions in the function has set the | |
1079 | Frame Pointer. */ | |
1080 | ||
1081 | static int | |
1082 | store_param_on_stack_p (unsigned long op, int framep, int *r0_contains_arg) | |
1083 | { | |
1084 | /* Move parameters from argument registers to temporary register. */ | |
1085 | if ((op & 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */ | |
1086 | { | |
1087 | /* Rx must be scratch register r0. */ | |
1088 | const int rx_regno = (op >> 16) & 31; | |
1089 | /* Ry: Only r3 - r10 are used for parameter passing. */ | |
1090 | const int ry_regno = GET_SRC_REG (op); | |
1091 | ||
1092 | if (rx_regno == 0 && ry_regno >= 3 && ry_regno <= 10) | |
1093 | { | |
1094 | *r0_contains_arg = 1; | |
1095 | return 1; | |
1096 | } | |
1097 | else | |
1098 | return 0; | |
1099 | } | |
1100 | ||
1101 | /* Save a General Purpose Register on stack. */ | |
1102 | ||
1103 | if ((op & 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */ | |
1104 | (op & 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */ | |
1105 | { | |
1106 | /* Rx: Only r3 - r10 are used for parameter passing. */ | |
1107 | const int rx_regno = GET_SRC_REG (op); | |
1108 | ||
1109 | return (rx_regno >= 3 && rx_regno <= 10); | |
1110 | } | |
1111 | ||
1112 | /* Save a General Purpose Register on stack via the Frame Pointer. */ | |
1113 | ||
1114 | if (framep && | |
1115 | ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */ | |
1116 | (op & 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */ | |
1117 | (op & 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */ | |
1118 | { | |
1119 | /* Rx: Usually, only r3 - r10 are used for parameter passing. | |
1120 | However, the compiler sometimes uses r0 to hold an argument. */ | |
1121 | const int rx_regno = GET_SRC_REG (op); | |
1122 | ||
1123 | return ((rx_regno >= 3 && rx_regno <= 10) | |
1124 | || (rx_regno == 0 && *r0_contains_arg)); | |
1125 | } | |
1126 | ||
1127 | if ((op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */ | |
1128 | { | |
1129 | /* Only f2 - f8 are used for parameter passing. */ | |
1130 | const int src_regno = GET_SRC_REG (op); | |
1131 | ||
1132 | return (src_regno >= 2 && src_regno <= 8); | |
1133 | } | |
1134 | ||
1135 | if (framep && ((op & 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */ | |
1136 | { | |
1137 | /* Only f2 - f8 are used for parameter passing. */ | |
1138 | const int src_regno = GET_SRC_REG (op); | |
1139 | ||
1140 | return (src_regno >= 2 && src_regno <= 8); | |
1141 | } | |
1142 | ||
1143 | /* Not an insn that saves a parameter on stack. */ | |
1144 | return 0; | |
1145 | } | |
55d05f3b | 1146 | |
3c77c82a DJ |
1147 | /* Assuming that INSN is a "bl" instruction located at PC, return |
1148 | nonzero if the destination of the branch is a "blrl" instruction. | |
1149 | ||
1150 | This sequence is sometimes found in certain function prologues. | |
1151 | It allows the function to load the LR register with a value that | |
1152 | they can use to access PIC data using PC-relative offsets. */ | |
1153 | ||
1154 | static int | |
e17a4113 | 1155 | bl_to_blrl_insn_p (CORE_ADDR pc, int insn, enum bfd_endian byte_order) |
3c77c82a | 1156 | { |
0b1b3e42 UW |
1157 | CORE_ADDR dest; |
1158 | int immediate; | |
1159 | int absolute; | |
3c77c82a DJ |
1160 | int dest_insn; |
1161 | ||
0b1b3e42 UW |
1162 | absolute = (int) ((insn >> 1) & 1); |
1163 | immediate = ((insn & ~3) << 6) >> 6; | |
1164 | if (absolute) | |
1165 | dest = immediate; | |
1166 | else | |
1167 | dest = pc + immediate; | |
1168 | ||
e17a4113 | 1169 | dest_insn = read_memory_integer (dest, 4, byte_order); |
3c77c82a DJ |
1170 | if ((dest_insn & 0xfc00ffff) == 0x4c000021) /* blrl */ |
1171 | return 1; | |
1172 | ||
1173 | return 0; | |
1174 | } | |
1175 | ||
dd6d677f PFC |
1176 | /* Return true if OP is a stw or std instruction with |
1177 | register operands RS and RA and any immediate offset. | |
1178 | ||
1179 | If WITH_UPDATE is true, also return true if OP is | |
1180 | a stwu or stdu instruction with the same operands. | |
1181 | ||
1182 | Return false otherwise. | |
1183 | */ | |
1184 | static bool | |
1185 | store_insn_p (unsigned long op, unsigned long rs, | |
1186 | unsigned long ra, bool with_update) | |
1187 | { | |
1188 | rs = rs << 21; | |
1189 | ra = ra << 16; | |
1190 | ||
1191 | if (/* std RS, SIMM(RA) */ | |
1192 | ((op & 0xffff0003) == (rs | ra | 0xf8000000)) || | |
1193 | /* stw RS, SIMM(RA) */ | |
1194 | ((op & 0xffff0000) == (rs | ra | 0x90000000))) | |
1195 | return true; | |
1196 | ||
1197 | if (with_update) | |
1198 | { | |
1199 | if (/* stdu RS, SIMM(RA) */ | |
1200 | ((op & 0xffff0003) == (rs | ra | 0xf8000001)) || | |
1201 | /* stwu RS, SIMM(RA) */ | |
1202 | ((op & 0xffff0000) == (rs | ra | 0x94000000))) | |
1203 | return true; | |
1204 | } | |
1205 | ||
1206 | return false; | |
1207 | } | |
1208 | ||
0df8b418 | 1209 | /* Masks for decoding a branch-and-link (bl) instruction. |
8ab3d180 KB |
1210 | |
1211 | BL_MASK and BL_INSTRUCTION are used in combination with each other. | |
1212 | The former is anded with the opcode in question; if the result of | |
1213 | this masking operation is equal to BL_INSTRUCTION, then the opcode in | |
1214 | question is a ``bl'' instruction. | |
1215 | ||
1216 | BL_DISPLACMENT_MASK is anded with the opcode in order to extract | |
1217 | the branch displacement. */ | |
1218 | ||
1219 | #define BL_MASK 0xfc000001 | |
1220 | #define BL_INSTRUCTION 0x48000001 | |
1221 | #define BL_DISPLACEMENT_MASK 0x03fffffc | |
1222 | ||
de9f48f0 | 1223 | static unsigned long |
e17a4113 | 1224 | rs6000_fetch_instruction (struct gdbarch *gdbarch, const CORE_ADDR pc) |
de9f48f0 | 1225 | { |
e17a4113 | 1226 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
de9f48f0 JG |
1227 | gdb_byte buf[4]; |
1228 | unsigned long op; | |
1229 | ||
1230 | /* Fetch the instruction and convert it to an integer. */ | |
1231 | if (target_read_memory (pc, buf, 4)) | |
1232 | return 0; | |
e17a4113 | 1233 | op = extract_unsigned_integer (buf, 4, byte_order); |
de9f48f0 JG |
1234 | |
1235 | return op; | |
1236 | } | |
1237 | ||
1238 | /* GCC generates several well-known sequences of instructions at the begining | |
1239 | of each function prologue when compiling with -fstack-check. If one of | |
1240 | such sequences starts at START_PC, then return the address of the | |
1241 | instruction immediately past this sequence. Otherwise, return START_PC. */ | |
1242 | ||
1243 | static CORE_ADDR | |
e17a4113 | 1244 | rs6000_skip_stack_check (struct gdbarch *gdbarch, const CORE_ADDR start_pc) |
de9f48f0 JG |
1245 | { |
1246 | CORE_ADDR pc = start_pc; | |
e17a4113 | 1247 | unsigned long op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 JG |
1248 | |
1249 | /* First possible sequence: A small number of probes. | |
1250 | stw 0, -<some immediate>(1) | |
0df8b418 | 1251 | [repeat this instruction any (small) number of times]. */ |
de9f48f0 JG |
1252 | |
1253 | if ((op & 0xffff0000) == 0x90010000) | |
1254 | { | |
1255 | while ((op & 0xffff0000) == 0x90010000) | |
1256 | { | |
1257 | pc = pc + 4; | |
e17a4113 | 1258 | op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 JG |
1259 | } |
1260 | return pc; | |
1261 | } | |
1262 | ||
1263 | /* Second sequence: A probing loop. | |
1264 | addi 12,1,-<some immediate> | |
1265 | lis 0,-<some immediate> | |
1266 | [possibly ori 0,0,<some immediate>] | |
1267 | add 0,12,0 | |
1268 | cmpw 0,12,0 | |
1269 | beq 0,<disp> | |
1270 | addi 12,12,-<some immediate> | |
1271 | stw 0,0(12) | |
1272 | b <disp> | |
0df8b418 | 1273 | [possibly one last probe: stw 0,<some immediate>(12)]. */ |
de9f48f0 JG |
1274 | |
1275 | while (1) | |
1276 | { | |
1277 | /* addi 12,1,-<some immediate> */ | |
1278 | if ((op & 0xffff0000) != 0x39810000) | |
1279 | break; | |
1280 | ||
1281 | /* lis 0,-<some immediate> */ | |
1282 | pc = pc + 4; | |
e17a4113 | 1283 | op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 JG |
1284 | if ((op & 0xffff0000) != 0x3c000000) |
1285 | break; | |
1286 | ||
1287 | pc = pc + 4; | |
e17a4113 | 1288 | op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 JG |
1289 | /* [possibly ori 0,0,<some immediate>] */ |
1290 | if ((op & 0xffff0000) == 0x60000000) | |
1291 | { | |
1292 | pc = pc + 4; | |
e17a4113 | 1293 | op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 JG |
1294 | } |
1295 | /* add 0,12,0 */ | |
1296 | if (op != 0x7c0c0214) | |
1297 | break; | |
1298 | ||
1299 | /* cmpw 0,12,0 */ | |
1300 | pc = pc + 4; | |
e17a4113 | 1301 | op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 JG |
1302 | if (op != 0x7c0c0000) |
1303 | break; | |
1304 | ||
1305 | /* beq 0,<disp> */ | |
1306 | pc = pc + 4; | |
e17a4113 | 1307 | op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 JG |
1308 | if ((op & 0xff9f0001) != 0x41820000) |
1309 | break; | |
1310 | ||
1311 | /* addi 12,12,-<some immediate> */ | |
1312 | pc = pc + 4; | |
e17a4113 | 1313 | op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 JG |
1314 | if ((op & 0xffff0000) != 0x398c0000) |
1315 | break; | |
1316 | ||
1317 | /* stw 0,0(12) */ | |
1318 | pc = pc + 4; | |
e17a4113 | 1319 | op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 JG |
1320 | if (op != 0x900c0000) |
1321 | break; | |
1322 | ||
1323 | /* b <disp> */ | |
1324 | pc = pc + 4; | |
e17a4113 | 1325 | op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 JG |
1326 | if ((op & 0xfc000001) != 0x48000000) |
1327 | break; | |
1328 | ||
0df8b418 | 1329 | /* [possibly one last probe: stw 0,<some immediate>(12)]. */ |
de9f48f0 | 1330 | pc = pc + 4; |
e17a4113 | 1331 | op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 JG |
1332 | if ((op & 0xffff0000) == 0x900c0000) |
1333 | { | |
1334 | pc = pc + 4; | |
e17a4113 | 1335 | op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 JG |
1336 | } |
1337 | ||
1338 | /* We found a valid stack-check sequence, return the new PC. */ | |
1339 | return pc; | |
1340 | } | |
1341 | ||
1342 | /* Third sequence: No probe; instead, a comparizon between the stack size | |
1343 | limit (saved in a run-time global variable) and the current stack | |
1344 | pointer: | |
1345 | ||
1346 | addi 0,1,-<some immediate> | |
1347 | lis 12,__gnat_stack_limit@ha | |
1348 | lwz 12,__gnat_stack_limit@l(12) | |
1349 | twllt 0,12 | |
1350 | ||
1351 | or, with a small variant in the case of a bigger stack frame: | |
1352 | addis 0,1,<some immediate> | |
1353 | addic 0,0,-<some immediate> | |
1354 | lis 12,__gnat_stack_limit@ha | |
1355 | lwz 12,__gnat_stack_limit@l(12) | |
1356 | twllt 0,12 | |
1357 | */ | |
1358 | while (1) | |
1359 | { | |
1360 | /* addi 0,1,-<some immediate> */ | |
1361 | if ((op & 0xffff0000) != 0x38010000) | |
1362 | { | |
1363 | /* small stack frame variant not recognized; try the | |
1364 | big stack frame variant: */ | |
1365 | ||
1366 | /* addis 0,1,<some immediate> */ | |
1367 | if ((op & 0xffff0000) != 0x3c010000) | |
1368 | break; | |
1369 | ||
1370 | /* addic 0,0,-<some immediate> */ | |
1371 | pc = pc + 4; | |
e17a4113 | 1372 | op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 JG |
1373 | if ((op & 0xffff0000) != 0x30000000) |
1374 | break; | |
1375 | } | |
1376 | ||
1377 | /* lis 12,<some immediate> */ | |
1378 | pc = pc + 4; | |
e17a4113 | 1379 | op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 JG |
1380 | if ((op & 0xffff0000) != 0x3d800000) |
1381 | break; | |
1382 | ||
1383 | /* lwz 12,<some immediate>(12) */ | |
1384 | pc = pc + 4; | |
e17a4113 | 1385 | op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 JG |
1386 | if ((op & 0xffff0000) != 0x818c0000) |
1387 | break; | |
1388 | ||
1389 | /* twllt 0,12 */ | |
1390 | pc = pc + 4; | |
e17a4113 | 1391 | op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 JG |
1392 | if ((op & 0xfffffffe) != 0x7c406008) |
1393 | break; | |
1394 | ||
1395 | /* We found a valid stack-check sequence, return the new PC. */ | |
1396 | return pc; | |
1397 | } | |
1398 | ||
1399 | /* No stack check code in our prologue, return the start_pc. */ | |
1400 | return start_pc; | |
1401 | } | |
1402 | ||
6a16c029 TJB |
1403 | /* return pc value after skipping a function prologue and also return |
1404 | information about a function frame. | |
1405 | ||
1406 | in struct rs6000_framedata fdata: | |
1407 | - frameless is TRUE, if function does not have a frame. | |
1408 | - nosavedpc is TRUE, if function does not save %pc value in its frame. | |
1409 | - offset is the initial size of this stack frame --- the amount by | |
1410 | which we decrement the sp to allocate the frame. | |
1411 | - saved_gpr is the number of the first saved gpr. | |
1412 | - saved_fpr is the number of the first saved fpr. | |
1413 | - saved_vr is the number of the first saved vr. | |
1414 | - saved_ev is the number of the first saved ev. | |
1415 | - alloca_reg is the number of the register used for alloca() handling. | |
1416 | Otherwise -1. | |
1417 | - gpr_offset is the offset of the first saved gpr from the previous frame. | |
1418 | - fpr_offset is the offset of the first saved fpr from the previous frame. | |
1419 | - vr_offset is the offset of the first saved vr from the previous frame. | |
1420 | - ev_offset is the offset of the first saved ev from the previous frame. | |
1421 | - lr_offset is the offset of the saved lr | |
1422 | - cr_offset is the offset of the saved cr | |
0df8b418 | 1423 | - vrsave_offset is the offset of the saved vrsave register. */ |
6a16c029 | 1424 | |
7a78ae4e | 1425 | static CORE_ADDR |
be8626e0 MD |
1426 | skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, CORE_ADDR lim_pc, |
1427 | struct rs6000_framedata *fdata) | |
c906108c SS |
1428 | { |
1429 | CORE_ADDR orig_pc = pc; | |
55d05f3b | 1430 | CORE_ADDR last_prologue_pc = pc; |
6be8bc0c | 1431 | CORE_ADDR li_found_pc = 0; |
50fd1280 | 1432 | gdb_byte buf[4]; |
c906108c SS |
1433 | unsigned long op; |
1434 | long offset = 0; | |
dd6d677f | 1435 | long alloca_reg_offset = 0; |
6be8bc0c | 1436 | long vr_saved_offset = 0; |
482ca3f5 KB |
1437 | int lr_reg = -1; |
1438 | int cr_reg = -1; | |
6be8bc0c | 1439 | int vr_reg = -1; |
96ff0de4 EZ |
1440 | int ev_reg = -1; |
1441 | long ev_offset = 0; | |
6be8bc0c | 1442 | int vrsave_reg = -1; |
c906108c SS |
1443 | int reg; |
1444 | int framep = 0; | |
1445 | int minimal_toc_loaded = 0; | |
ddb20c56 | 1446 | int prev_insn_was_prologue_insn = 1; |
55d05f3b | 1447 | int num_skip_non_prologue_insns = 0; |
773df3e5 | 1448 | int r0_contains_arg = 0; |
be8626e0 MD |
1449 | const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (gdbarch); |
1450 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
e17a4113 | 1451 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
c906108c | 1452 | |
ddb20c56 | 1453 | memset (fdata, 0, sizeof (struct rs6000_framedata)); |
c906108c SS |
1454 | fdata->saved_gpr = -1; |
1455 | fdata->saved_fpr = -1; | |
6be8bc0c | 1456 | fdata->saved_vr = -1; |
96ff0de4 | 1457 | fdata->saved_ev = -1; |
c906108c SS |
1458 | fdata->alloca_reg = -1; |
1459 | fdata->frameless = 1; | |
1460 | fdata->nosavedpc = 1; | |
46a9b8ed | 1461 | fdata->lr_register = -1; |
c906108c | 1462 | |
e17a4113 | 1463 | pc = rs6000_skip_stack_check (gdbarch, pc); |
de9f48f0 JG |
1464 | if (pc >= lim_pc) |
1465 | pc = lim_pc; | |
1466 | ||
55d05f3b | 1467 | for (;; pc += 4) |
c906108c | 1468 | { |
ddb20c56 KB |
1469 | /* Sometimes it isn't clear if an instruction is a prologue |
1470 | instruction or not. When we encounter one of these ambiguous | |
1471 | cases, we'll set prev_insn_was_prologue_insn to 0 (false). | |
0df8b418 | 1472 | Otherwise, we'll assume that it really is a prologue instruction. */ |
ddb20c56 KB |
1473 | if (prev_insn_was_prologue_insn) |
1474 | last_prologue_pc = pc; | |
55d05f3b KB |
1475 | |
1476 | /* Stop scanning if we've hit the limit. */ | |
4e463ff5 | 1477 | if (pc >= lim_pc) |
55d05f3b KB |
1478 | break; |
1479 | ||
ddb20c56 KB |
1480 | prev_insn_was_prologue_insn = 1; |
1481 | ||
55d05f3b | 1482 | /* Fetch the instruction and convert it to an integer. */ |
ddb20c56 KB |
1483 | if (target_read_memory (pc, buf, 4)) |
1484 | break; | |
e17a4113 | 1485 | op = extract_unsigned_integer (buf, 4, byte_order); |
c906108c | 1486 | |
c5aa993b JM |
1487 | if ((op & 0xfc1fffff) == 0x7c0802a6) |
1488 | { /* mflr Rx */ | |
43b1ab88 AC |
1489 | /* Since shared library / PIC code, which needs to get its |
1490 | address at runtime, can appear to save more than one link | |
1491 | register vis: | |
1492 | ||
1493 | *INDENT-OFF* | |
1494 | stwu r1,-304(r1) | |
1495 | mflr r3 | |
1496 | bl 0xff570d0 (blrl) | |
1497 | stw r30,296(r1) | |
1498 | mflr r30 | |
1499 | stw r31,300(r1) | |
1500 | stw r3,308(r1); | |
1501 | ... | |
1502 | *INDENT-ON* | |
1503 | ||
1504 | remember just the first one, but skip over additional | |
1505 | ones. */ | |
721d14ba | 1506 | if (lr_reg == -1) |
dd6d677f | 1507 | lr_reg = (op & 0x03e00000) >> 21; |
773df3e5 JB |
1508 | if (lr_reg == 0) |
1509 | r0_contains_arg = 0; | |
c5aa993b | 1510 | continue; |
c5aa993b JM |
1511 | } |
1512 | else if ((op & 0xfc1fffff) == 0x7c000026) | |
1513 | { /* mfcr Rx */ | |
dd6d677f | 1514 | cr_reg = (op & 0x03e00000) >> 21; |
773df3e5 JB |
1515 | if (cr_reg == 0) |
1516 | r0_contains_arg = 0; | |
c5aa993b | 1517 | continue; |
c906108c | 1518 | |
c906108c | 1519 | } |
c5aa993b JM |
1520 | else if ((op & 0xfc1f0000) == 0xd8010000) |
1521 | { /* stfd Rx,NUM(r1) */ | |
1522 | reg = GET_SRC_REG (op); | |
1523 | if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg) | |
1524 | { | |
1525 | fdata->saved_fpr = reg; | |
1526 | fdata->fpr_offset = SIGNED_SHORT (op) + offset; | |
1527 | } | |
1528 | continue; | |
c906108c | 1529 | |
c5aa993b JM |
1530 | } |
1531 | else if (((op & 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */ | |
7a78ae4e ND |
1532 | (((op & 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */ |
1533 | (op & 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */ | |
1534 | (op & 0x03e00000) >= 0x01a00000)) /* rx >= r13 */ | |
c5aa993b JM |
1535 | { |
1536 | ||
1537 | reg = GET_SRC_REG (op); | |
46a9b8ed DJ |
1538 | if ((op & 0xfc1f0000) == 0xbc010000) |
1539 | fdata->gpr_mask |= ~((1U << reg) - 1); | |
1540 | else | |
1541 | fdata->gpr_mask |= 1U << reg; | |
c5aa993b JM |
1542 | if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg) |
1543 | { | |
1544 | fdata->saved_gpr = reg; | |
7a78ae4e | 1545 | if ((op & 0xfc1f0003) == 0xf8010000) |
98f08d3d | 1546 | op &= ~3UL; |
c5aa993b JM |
1547 | fdata->gpr_offset = SIGNED_SHORT (op) + offset; |
1548 | } | |
1549 | continue; | |
c906108c | 1550 | |
ddb20c56 | 1551 | } |
ef1bc9e7 AM |
1552 | else if ((op & 0xffff0000) == 0x3c4c0000 |
1553 | || (op & 0xffff0000) == 0x3c400000 | |
1554 | || (op & 0xffff0000) == 0x38420000) | |
1555 | { | |
1556 | /* . 0: addis 2,12,.TOC.-0b@ha | |
1557 | . addi 2,2,.TOC.-0b@l | |
1558 | or | |
1559 | . lis 2,.TOC.@ha | |
1560 | . addi 2,2,.TOC.@l | |
1561 | used by ELFv2 global entry points to set up r2. */ | |
1562 | continue; | |
1563 | } | |
1564 | else if (op == 0x60000000) | |
ddb20c56 | 1565 | { |
96ff0de4 | 1566 | /* nop */ |
ddb20c56 KB |
1567 | /* Allow nops in the prologue, but do not consider them to |
1568 | be part of the prologue unless followed by other prologue | |
0df8b418 | 1569 | instructions. */ |
ddb20c56 KB |
1570 | prev_insn_was_prologue_insn = 0; |
1571 | continue; | |
1572 | ||
c906108c | 1573 | } |
c5aa993b | 1574 | else if ((op & 0xffff0000) == 0x3c000000) |
ef1bc9e7 | 1575 | { /* addis 0,0,NUM, used for >= 32k frames */ |
c5aa993b JM |
1576 | fdata->offset = (op & 0x0000ffff) << 16; |
1577 | fdata->frameless = 0; | |
773df3e5 | 1578 | r0_contains_arg = 0; |
c5aa993b JM |
1579 | continue; |
1580 | ||
1581 | } | |
1582 | else if ((op & 0xffff0000) == 0x60000000) | |
ef1bc9e7 | 1583 | { /* ori 0,0,NUM, 2nd half of >= 32k frames */ |
c5aa993b JM |
1584 | fdata->offset |= (op & 0x0000ffff); |
1585 | fdata->frameless = 0; | |
773df3e5 | 1586 | r0_contains_arg = 0; |
c5aa993b JM |
1587 | continue; |
1588 | ||
1589 | } | |
be723e22 | 1590 | else if (lr_reg >= 0 && |
dd6d677f PFC |
1591 | ((store_insn_p (op, lr_reg, 1, true)) || |
1592 | (framep && | |
1593 | (store_insn_p (op, lr_reg, | |
1594 | fdata->alloca_reg - tdep->ppc_gp0_regnum, | |
1595 | false))))) | |
1596 | { | |
1597 | if (store_insn_p (op, lr_reg, 1, true)) | |
1598 | fdata->lr_offset = offset; | |
1599 | else /* LR save through frame pointer. */ | |
1600 | fdata->lr_offset = alloca_reg_offset; | |
1601 | ||
c5aa993b | 1602 | fdata->nosavedpc = 0; |
be723e22 MS |
1603 | /* Invalidate lr_reg, but don't set it to -1. |
1604 | That would mean that it had never been set. */ | |
1605 | lr_reg = -2; | |
98f08d3d KB |
1606 | if ((op & 0xfc000003) == 0xf8000000 || /* std */ |
1607 | (op & 0xfc000000) == 0x90000000) /* stw */ | |
1608 | { | |
1609 | /* Does not update r1, so add displacement to lr_offset. */ | |
1610 | fdata->lr_offset += SIGNED_SHORT (op); | |
1611 | } | |
c5aa993b JM |
1612 | continue; |
1613 | ||
1614 | } | |
be723e22 | 1615 | else if (cr_reg >= 0 && |
dd6d677f PFC |
1616 | (store_insn_p (op, cr_reg, 1, true))) |
1617 | { | |
98f08d3d | 1618 | fdata->cr_offset = offset; |
be723e22 MS |
1619 | /* Invalidate cr_reg, but don't set it to -1. |
1620 | That would mean that it had never been set. */ | |
1621 | cr_reg = -2; | |
98f08d3d KB |
1622 | if ((op & 0xfc000003) == 0xf8000000 || |
1623 | (op & 0xfc000000) == 0x90000000) | |
1624 | { | |
1625 | /* Does not update r1, so add displacement to cr_offset. */ | |
1626 | fdata->cr_offset += SIGNED_SHORT (op); | |
1627 | } | |
c5aa993b JM |
1628 | continue; |
1629 | ||
1630 | } | |
721d14ba DJ |
1631 | else if ((op & 0xfe80ffff) == 0x42800005 && lr_reg != -1) |
1632 | { | |
1633 | /* bcl 20,xx,.+4 is used to get the current PC, with or without | |
1634 | prediction bits. If the LR has already been saved, we can | |
1635 | skip it. */ | |
1636 | continue; | |
1637 | } | |
c5aa993b JM |
1638 | else if (op == 0x48000005) |
1639 | { /* bl .+4 used in | |
1640 | -mrelocatable */ | |
46a9b8ed | 1641 | fdata->used_bl = 1; |
c5aa993b JM |
1642 | continue; |
1643 | ||
1644 | } | |
1645 | else if (op == 0x48000004) | |
1646 | { /* b .+4 (xlc) */ | |
1647 | break; | |
1648 | ||
c5aa993b | 1649 | } |
6be8bc0c EZ |
1650 | else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used |
1651 | in V.4 -mminimal-toc */ | |
c5aa993b JM |
1652 | (op & 0xffff0000) == 0x3bde0000) |
1653 | { /* addi 30,30,foo@l */ | |
1654 | continue; | |
c906108c | 1655 | |
c5aa993b JM |
1656 | } |
1657 | else if ((op & 0xfc000001) == 0x48000001) | |
1658 | { /* bl foo, | |
0df8b418 | 1659 | to save fprs??? */ |
c906108c | 1660 | |
c5aa993b | 1661 | fdata->frameless = 0; |
3c77c82a DJ |
1662 | |
1663 | /* If the return address has already been saved, we can skip | |
1664 | calls to blrl (for PIC). */ | |
e17a4113 | 1665 | if (lr_reg != -1 && bl_to_blrl_insn_p (pc, op, byte_order)) |
46a9b8ed DJ |
1666 | { |
1667 | fdata->used_bl = 1; | |
1668 | continue; | |
1669 | } | |
3c77c82a | 1670 | |
6be8bc0c | 1671 | /* Don't skip over the subroutine call if it is not within |
ebd98106 FF |
1672 | the first three instructions of the prologue and either |
1673 | we have no line table information or the line info tells | |
1674 | us that the subroutine call is not part of the line | |
1675 | associated with the prologue. */ | |
c5aa993b | 1676 | if ((pc - orig_pc) > 8) |
ebd98106 FF |
1677 | { |
1678 | struct symtab_and_line prologue_sal = find_pc_line (orig_pc, 0); | |
1679 | struct symtab_and_line this_sal = find_pc_line (pc, 0); | |
1680 | ||
0df8b418 MS |
1681 | if ((prologue_sal.line == 0) |
1682 | || (prologue_sal.line != this_sal.line)) | |
ebd98106 FF |
1683 | break; |
1684 | } | |
c5aa993b | 1685 | |
e17a4113 | 1686 | op = read_memory_integer (pc + 4, 4, byte_order); |
c5aa993b | 1687 | |
6be8bc0c EZ |
1688 | /* At this point, make sure this is not a trampoline |
1689 | function (a function that simply calls another functions, | |
1690 | and nothing else). If the next is not a nop, this branch | |
0df8b418 | 1691 | was part of the function prologue. */ |
c5aa993b JM |
1692 | |
1693 | if (op == 0x4def7b82 || op == 0) /* crorc 15, 15, 15 */ | |
0df8b418 MS |
1694 | break; /* Don't skip over |
1695 | this branch. */ | |
c5aa993b | 1696 | |
46a9b8ed DJ |
1697 | fdata->used_bl = 1; |
1698 | continue; | |
c5aa993b | 1699 | } |
98f08d3d KB |
1700 | /* update stack pointer */ |
1701 | else if ((op & 0xfc1f0000) == 0x94010000) | |
1702 | { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */ | |
c5aa993b JM |
1703 | fdata->frameless = 0; |
1704 | fdata->offset = SIGNED_SHORT (op); | |
1705 | offset = fdata->offset; | |
1706 | continue; | |
c5aa993b | 1707 | } |
7a8f494c PFC |
1708 | else if ((op & 0xfc1f07fa) == 0x7c01016a) |
1709 | { /* stwux rX,r1,rY || stdux rX,r1,rY */ | |
0df8b418 | 1710 | /* No way to figure out what r1 is going to be. */ |
98f08d3d KB |
1711 | fdata->frameless = 0; |
1712 | offset = fdata->offset; | |
1713 | continue; | |
1714 | } | |
1715 | else if ((op & 0xfc1f0003) == 0xf8010001) | |
1716 | { /* stdu rX,NUM(r1) */ | |
1717 | fdata->frameless = 0; | |
1718 | fdata->offset = SIGNED_SHORT (op & ~3UL); | |
1719 | offset = fdata->offset; | |
1720 | continue; | |
1721 | } | |
7313566f FF |
1722 | else if ((op & 0xffff0000) == 0x38210000) |
1723 | { /* addi r1,r1,SIMM */ | |
1724 | fdata->frameless = 0; | |
1725 | fdata->offset += SIGNED_SHORT (op); | |
1726 | offset = fdata->offset; | |
1727 | continue; | |
1728 | } | |
4e463ff5 DJ |
1729 | /* Load up minimal toc pointer. Do not treat an epilogue restore |
1730 | of r31 as a minimal TOC load. */ | |
0df8b418 MS |
1731 | else if (((op >> 22) == 0x20f || /* l r31,... or l r30,... */ |
1732 | (op >> 22) == 0x3af) /* ld r31,... or ld r30,... */ | |
4e463ff5 | 1733 | && !framep |
c5aa993b | 1734 | && !minimal_toc_loaded) |
98f08d3d | 1735 | { |
c5aa993b JM |
1736 | minimal_toc_loaded = 1; |
1737 | continue; | |
1738 | ||
f6077098 KB |
1739 | /* move parameters from argument registers to local variable |
1740 | registers */ | |
1741 | } | |
1742 | else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */ | |
1743 | (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */ | |
1744 | (((op >> 21) & 31) <= 10) && | |
0df8b418 MS |
1745 | ((long) ((op >> 16) & 31) |
1746 | >= fdata->saved_gpr)) /* Rx: local var reg */ | |
f6077098 KB |
1747 | { |
1748 | continue; | |
1749 | ||
c5aa993b JM |
1750 | /* store parameters in stack */ |
1751 | } | |
e802b915 | 1752 | /* Move parameters from argument registers to temporary register. */ |
773df3e5 | 1753 | else if (store_param_on_stack_p (op, framep, &r0_contains_arg)) |
e802b915 | 1754 | { |
c5aa993b JM |
1755 | continue; |
1756 | ||
1757 | /* Set up frame pointer */ | |
1758 | } | |
76219d77 JB |
1759 | else if (op == 0x603d0000) /* oril r29, r1, 0x0 */ |
1760 | { | |
1761 | fdata->frameless = 0; | |
1762 | framep = 1; | |
1763 | fdata->alloca_reg = (tdep->ppc_gp0_regnum + 29); | |
dd6d677f | 1764 | alloca_reg_offset = offset; |
76219d77 JB |
1765 | continue; |
1766 | ||
1767 | /* Another way to set up the frame pointer. */ | |
1768 | } | |
c5aa993b JM |
1769 | else if (op == 0x603f0000 /* oril r31, r1, 0x0 */ |
1770 | || op == 0x7c3f0b78) | |
1771 | { /* mr r31, r1 */ | |
1772 | fdata->frameless = 0; | |
1773 | framep = 1; | |
6f99cb26 | 1774 | fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31); |
dd6d677f | 1775 | alloca_reg_offset = offset; |
c5aa993b JM |
1776 | continue; |
1777 | ||
1778 | /* Another way to set up the frame pointer. */ | |
1779 | } | |
1780 | else if ((op & 0xfc1fffff) == 0x38010000) | |
1781 | { /* addi rX, r1, 0x0 */ | |
1782 | fdata->frameless = 0; | |
1783 | framep = 1; | |
6f99cb26 AC |
1784 | fdata->alloca_reg = (tdep->ppc_gp0_regnum |
1785 | + ((op & ~0x38010000) >> 21)); | |
dd6d677f | 1786 | alloca_reg_offset = offset; |
c5aa993b | 1787 | continue; |
c5aa993b | 1788 | } |
6be8bc0c EZ |
1789 | /* AltiVec related instructions. */ |
1790 | /* Store the vrsave register (spr 256) in another register for | |
1791 | later manipulation, or load a register into the vrsave | |
1792 | register. 2 instructions are used: mfvrsave and | |
1793 | mtvrsave. They are shorthand notation for mfspr Rn, SPR256 | |
1794 | and mtspr SPR256, Rn. */ | |
1795 | /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110 | |
1796 | mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */ | |
1797 | else if ((op & 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */ | |
1798 | { | |
1799 | vrsave_reg = GET_SRC_REG (op); | |
1800 | continue; | |
1801 | } | |
1802 | else if ((op & 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */ | |
1803 | { | |
1804 | continue; | |
1805 | } | |
1806 | /* Store the register where vrsave was saved to onto the stack: | |
1807 | rS is the register where vrsave was stored in a previous | |
1808 | instruction. */ | |
1809 | /* 100100 sssss 00001 dddddddd dddddddd */ | |
1810 | else if ((op & 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */ | |
1811 | { | |
1812 | if (vrsave_reg == GET_SRC_REG (op)) | |
1813 | { | |
1814 | fdata->vrsave_offset = SIGNED_SHORT (op) + offset; | |
1815 | vrsave_reg = -1; | |
1816 | } | |
1817 | continue; | |
1818 | } | |
1819 | /* Compute the new value of vrsave, by modifying the register | |
1820 | where vrsave was saved to. */ | |
1821 | else if (((op & 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */ | |
1822 | || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */ | |
1823 | { | |
1824 | continue; | |
1825 | } | |
1826 | /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first | |
1827 | in a pair of insns to save the vector registers on the | |
1828 | stack. */ | |
1829 | /* 001110 00000 00000 iiii iiii iiii iiii */ | |
96ff0de4 EZ |
1830 | /* 001110 01110 00000 iiii iiii iiii iiii */ |
1831 | else if ((op & 0xffff0000) == 0x38000000 /* li r0, SIMM */ | |
1832 | || (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */ | |
6be8bc0c | 1833 | { |
773df3e5 JB |
1834 | if ((op & 0xffff0000) == 0x38000000) |
1835 | r0_contains_arg = 0; | |
6be8bc0c EZ |
1836 | li_found_pc = pc; |
1837 | vr_saved_offset = SIGNED_SHORT (op); | |
773df3e5 JB |
1838 | |
1839 | /* This insn by itself is not part of the prologue, unless | |
0df8b418 | 1840 | if part of the pair of insns mentioned above. So do not |
773df3e5 JB |
1841 | record this insn as part of the prologue yet. */ |
1842 | prev_insn_was_prologue_insn = 0; | |
6be8bc0c EZ |
1843 | } |
1844 | /* Store vector register S at (r31+r0) aligned to 16 bytes. */ | |
1845 | /* 011111 sssss 11111 00000 00111001110 */ | |
1846 | else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */ | |
1847 | { | |
1848 | if (pc == (li_found_pc + 4)) | |
1849 | { | |
1850 | vr_reg = GET_SRC_REG (op); | |
1851 | /* If this is the first vector reg to be saved, or if | |
1852 | it has a lower number than others previously seen, | |
1853 | reupdate the frame info. */ | |
1854 | if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg) | |
1855 | { | |
1856 | fdata->saved_vr = vr_reg; | |
1857 | fdata->vr_offset = vr_saved_offset + offset; | |
1858 | } | |
1859 | vr_saved_offset = -1; | |
1860 | vr_reg = -1; | |
1861 | li_found_pc = 0; | |
1862 | } | |
1863 | } | |
1864 | /* End AltiVec related instructions. */ | |
96ff0de4 EZ |
1865 | |
1866 | /* Start BookE related instructions. */ | |
1867 | /* Store gen register S at (r31+uimm). | |
1868 | Any register less than r13 is volatile, so we don't care. */ | |
1869 | /* 000100 sssss 11111 iiiii 01100100001 */ | |
1870 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
1871 | && (op & 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */ | |
1872 | { | |
1873 | if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */ | |
1874 | { | |
1875 | unsigned int imm; | |
1876 | ev_reg = GET_SRC_REG (op); | |
1877 | imm = (op >> 11) & 0x1f; | |
1878 | ev_offset = imm * 8; | |
1879 | /* If this is the first vector reg to be saved, or if | |
1880 | it has a lower number than others previously seen, | |
1881 | reupdate the frame info. */ | |
1882 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) | |
1883 | { | |
1884 | fdata->saved_ev = ev_reg; | |
1885 | fdata->ev_offset = ev_offset + offset; | |
1886 | } | |
1887 | } | |
1888 | continue; | |
1889 | } | |
1890 | /* Store gen register rS at (r1+rB). */ | |
1891 | /* 000100 sssss 00001 bbbbb 01100100000 */ | |
1892 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
1893 | && (op & 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */ | |
1894 | { | |
1895 | if (pc == (li_found_pc + 4)) | |
1896 | { | |
1897 | ev_reg = GET_SRC_REG (op); | |
1898 | /* If this is the first vector reg to be saved, or if | |
1899 | it has a lower number than others previously seen, | |
1900 | reupdate the frame info. */ | |
1901 | /* We know the contents of rB from the previous instruction. */ | |
1902 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) | |
1903 | { | |
1904 | fdata->saved_ev = ev_reg; | |
1905 | fdata->ev_offset = vr_saved_offset + offset; | |
1906 | } | |
1907 | vr_saved_offset = -1; | |
1908 | ev_reg = -1; | |
1909 | li_found_pc = 0; | |
1910 | } | |
1911 | continue; | |
1912 | } | |
1913 | /* Store gen register r31 at (rA+uimm). */ | |
1914 | /* 000100 11111 aaaaa iiiii 01100100001 */ | |
1915 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
1916 | && (op & 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */ | |
1917 | { | |
1918 | /* Wwe know that the source register is 31 already, but | |
1919 | it can't hurt to compute it. */ | |
1920 | ev_reg = GET_SRC_REG (op); | |
1921 | ev_offset = ((op >> 11) & 0x1f) * 8; | |
1922 | /* If this is the first vector reg to be saved, or if | |
1923 | it has a lower number than others previously seen, | |
1924 | reupdate the frame info. */ | |
1925 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) | |
1926 | { | |
1927 | fdata->saved_ev = ev_reg; | |
1928 | fdata->ev_offset = ev_offset + offset; | |
1929 | } | |
1930 | ||
1931 | continue; | |
1932 | } | |
1933 | /* Store gen register S at (r31+r0). | |
1934 | Store param on stack when offset from SP bigger than 4 bytes. */ | |
1935 | /* 000100 sssss 11111 00000 01100100000 */ | |
1936 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
1937 | && (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */ | |
1938 | { | |
1939 | if (pc == (li_found_pc + 4)) | |
1940 | { | |
1941 | if ((op & 0x03e00000) >= 0x01a00000) | |
1942 | { | |
1943 | ev_reg = GET_SRC_REG (op); | |
1944 | /* If this is the first vector reg to be saved, or if | |
1945 | it has a lower number than others previously seen, | |
1946 | reupdate the frame info. */ | |
1947 | /* We know the contents of r0 from the previous | |
1948 | instruction. */ | |
1949 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) | |
1950 | { | |
1951 | fdata->saved_ev = ev_reg; | |
1952 | fdata->ev_offset = vr_saved_offset + offset; | |
1953 | } | |
1954 | ev_reg = -1; | |
1955 | } | |
1956 | vr_saved_offset = -1; | |
1957 | li_found_pc = 0; | |
1958 | continue; | |
1959 | } | |
1960 | } | |
1961 | /* End BookE related instructions. */ | |
1962 | ||
c5aa993b JM |
1963 | else |
1964 | { | |
46a9b8ed DJ |
1965 | unsigned int all_mask = ~((1U << fdata->saved_gpr) - 1); |
1966 | ||
55d05f3b KB |
1967 | /* Not a recognized prologue instruction. |
1968 | Handle optimizer code motions into the prologue by continuing | |
1969 | the search if we have no valid frame yet or if the return | |
46a9b8ed DJ |
1970 | address is not yet saved in the frame. Also skip instructions |
1971 | if some of the GPRs expected to be saved are not yet saved. */ | |
1972 | if (fdata->frameless == 0 && fdata->nosavedpc == 0 | |
1973 | && (fdata->gpr_mask & all_mask) == all_mask) | |
55d05f3b KB |
1974 | break; |
1975 | ||
1976 | if (op == 0x4e800020 /* blr */ | |
1977 | || op == 0x4e800420) /* bctr */ | |
1978 | /* Do not scan past epilogue in frameless functions or | |
1979 | trampolines. */ | |
1980 | break; | |
1981 | if ((op & 0xf4000000) == 0x40000000) /* bxx */ | |
64366f1c | 1982 | /* Never skip branches. */ |
55d05f3b KB |
1983 | break; |
1984 | ||
1985 | if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns) | |
1986 | /* Do not scan too many insns, scanning insns is expensive with | |
1987 | remote targets. */ | |
1988 | break; | |
1989 | ||
1990 | /* Continue scanning. */ | |
1991 | prev_insn_was_prologue_insn = 0; | |
1992 | continue; | |
c5aa993b | 1993 | } |
c906108c SS |
1994 | } |
1995 | ||
1996 | #if 0 | |
1997 | /* I have problems with skipping over __main() that I need to address | |
0df8b418 | 1998 | * sometime. Previously, I used to use misc_function_vector which |
c906108c SS |
1999 | * didn't work as well as I wanted to be. -MGO */ |
2000 | ||
2001 | /* If the first thing after skipping a prolog is a branch to a function, | |
2002 | this might be a call to an initializer in main(), introduced by gcc2. | |
64366f1c | 2003 | We'd like to skip over it as well. Fortunately, xlc does some extra |
c906108c | 2004 | work before calling a function right after a prologue, thus we can |
64366f1c | 2005 | single out such gcc2 behaviour. */ |
c906108c | 2006 | |
c906108c | 2007 | |
c5aa993b | 2008 | if ((op & 0xfc000001) == 0x48000001) |
0df8b418 | 2009 | { /* bl foo, an initializer function? */ |
e17a4113 | 2010 | op = read_memory_integer (pc + 4, 4, byte_order); |
c5aa993b JM |
2011 | |
2012 | if (op == 0x4def7b82) | |
2013 | { /* cror 0xf, 0xf, 0xf (nop) */ | |
c906108c | 2014 | |
64366f1c EZ |
2015 | /* Check and see if we are in main. If so, skip over this |
2016 | initializer function as well. */ | |
c906108c | 2017 | |
c5aa993b | 2018 | tmp = find_pc_misc_function (pc); |
6314a349 AC |
2019 | if (tmp >= 0 |
2020 | && strcmp (misc_function_vector[tmp].name, main_name ()) == 0) | |
c5aa993b JM |
2021 | return pc + 8; |
2022 | } | |
c906108c | 2023 | } |
c906108c | 2024 | #endif /* 0 */ |
c5aa993b | 2025 | |
46a9b8ed | 2026 | if (pc == lim_pc && lr_reg >= 0) |
dd6d677f | 2027 | fdata->lr_register = lr_reg; |
46a9b8ed | 2028 | |
c5aa993b | 2029 | fdata->offset = -fdata->offset; |
ddb20c56 | 2030 | return last_prologue_pc; |
c906108c SS |
2031 | } |
2032 | ||
7a78ae4e | 2033 | static CORE_ADDR |
4a7622d1 | 2034 | rs6000_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
c906108c | 2035 | { |
4a7622d1 | 2036 | struct rs6000_framedata frame; |
e3acb115 | 2037 | CORE_ADDR limit_pc, func_addr, func_end_addr = 0; |
c906108c | 2038 | |
4a7622d1 UW |
2039 | /* See if we can determine the end of the prologue via the symbol table. |
2040 | If so, then return either PC, or the PC after the prologue, whichever | |
2041 | is greater. */ | |
e3acb115 | 2042 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end_addr)) |
c5aa993b | 2043 | { |
d80b854b UW |
2044 | CORE_ADDR post_prologue_pc |
2045 | = skip_prologue_using_sal (gdbarch, func_addr); | |
4a7622d1 | 2046 | if (post_prologue_pc != 0) |
325fac50 | 2047 | return std::max (pc, post_prologue_pc); |
c906108c | 2048 | } |
c906108c | 2049 | |
4a7622d1 UW |
2050 | /* Can't determine prologue from the symbol table, need to examine |
2051 | instructions. */ | |
c906108c | 2052 | |
4a7622d1 UW |
2053 | /* Find an upper limit on the function prologue using the debug |
2054 | information. If the debug information could not be used to provide | |
2055 | that bound, then use an arbitrary large number as the upper bound. */ | |
d80b854b | 2056 | limit_pc = skip_prologue_using_sal (gdbarch, pc); |
4a7622d1 UW |
2057 | if (limit_pc == 0) |
2058 | limit_pc = pc + 100; /* Magic. */ | |
794a477a | 2059 | |
e3acb115 JB |
2060 | /* Do not allow limit_pc to be past the function end, if we know |
2061 | where that end is... */ | |
2062 | if (func_end_addr && limit_pc > func_end_addr) | |
2063 | limit_pc = func_end_addr; | |
2064 | ||
4a7622d1 UW |
2065 | pc = skip_prologue (gdbarch, pc, limit_pc, &frame); |
2066 | return pc; | |
c906108c | 2067 | } |
c906108c | 2068 | |
8ab3d180 KB |
2069 | /* When compiling for EABI, some versions of GCC emit a call to __eabi |
2070 | in the prologue of main(). | |
2071 | ||
2072 | The function below examines the code pointed at by PC and checks to | |
2073 | see if it corresponds to a call to __eabi. If so, it returns the | |
2074 | address of the instruction following that call. Otherwise, it simply | |
2075 | returns PC. */ | |
2076 | ||
63807e1d | 2077 | static CORE_ADDR |
8ab3d180 KB |
2078 | rs6000_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
2079 | { | |
e17a4113 | 2080 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
8ab3d180 KB |
2081 | gdb_byte buf[4]; |
2082 | unsigned long op; | |
2083 | ||
2084 | if (target_read_memory (pc, buf, 4)) | |
2085 | return pc; | |
e17a4113 | 2086 | op = extract_unsigned_integer (buf, 4, byte_order); |
8ab3d180 KB |
2087 | |
2088 | if ((op & BL_MASK) == BL_INSTRUCTION) | |
2089 | { | |
2090 | CORE_ADDR displ = op & BL_DISPLACEMENT_MASK; | |
2091 | CORE_ADDR call_dest = pc + 4 + displ; | |
7cbd4a93 | 2092 | struct bound_minimal_symbol s = lookup_minimal_symbol_by_pc (call_dest); |
8ab3d180 KB |
2093 | |
2094 | /* We check for ___eabi (three leading underscores) in addition | |
2095 | to __eabi in case the GCC option "-fleading-underscore" was | |
2096 | used to compile the program. */ | |
7cbd4a93 | 2097 | if (s.minsym != NULL |
efd66ac6 TT |
2098 | && MSYMBOL_LINKAGE_NAME (s.minsym) != NULL |
2099 | && (strcmp (MSYMBOL_LINKAGE_NAME (s.minsym), "__eabi") == 0 | |
2100 | || strcmp (MSYMBOL_LINKAGE_NAME (s.minsym), "___eabi") == 0)) | |
8ab3d180 KB |
2101 | pc += 4; |
2102 | } | |
2103 | return pc; | |
2104 | } | |
383f0f5b | 2105 | |
4a7622d1 UW |
2106 | /* All the ABI's require 16 byte alignment. */ |
2107 | static CORE_ADDR | |
2108 | rs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
2109 | { | |
2110 | return (addr & -16); | |
c906108c SS |
2111 | } |
2112 | ||
977adac5 ND |
2113 | /* Return whether handle_inferior_event() should proceed through code |
2114 | starting at PC in function NAME when stepping. | |
2115 | ||
2116 | The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to | |
2117 | handle memory references that are too distant to fit in instructions | |
2118 | generated by the compiler. For example, if 'foo' in the following | |
2119 | instruction: | |
2120 | ||
2121 | lwz r9,foo(r2) | |
2122 | ||
2123 | is greater than 32767, the linker might replace the lwz with a branch to | |
2124 | somewhere in @FIX1 that does the load in 2 instructions and then branches | |
2125 | back to where execution should continue. | |
2126 | ||
2127 | GDB should silently step over @FIX code, just like AIX dbx does. | |
2ec664f5 MS |
2128 | Unfortunately, the linker uses the "b" instruction for the |
2129 | branches, meaning that the link register doesn't get set. | |
2130 | Therefore, GDB's usual step_over_function () mechanism won't work. | |
977adac5 | 2131 | |
e76f05fa UW |
2132 | Instead, use the gdbarch_skip_trampoline_code and |
2133 | gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past | |
2ec664f5 | 2134 | @FIX code. */ |
977adac5 | 2135 | |
63807e1d | 2136 | static int |
e17a4113 | 2137 | rs6000_in_solib_return_trampoline (struct gdbarch *gdbarch, |
2c02bd72 | 2138 | CORE_ADDR pc, const char *name) |
977adac5 | 2139 | { |
61012eef | 2140 | return name && startswith (name, "@FIX"); |
977adac5 ND |
2141 | } |
2142 | ||
2143 | /* Skip code that the user doesn't want to see when stepping: | |
2144 | ||
2145 | 1. Indirect function calls use a piece of trampoline code to do context | |
2146 | switching, i.e. to set the new TOC table. Skip such code if we are on | |
2147 | its first instruction (as when we have single-stepped to here). | |
2148 | ||
2149 | 2. Skip shared library trampoline code (which is different from | |
c906108c | 2150 | indirect function call trampolines). |
977adac5 ND |
2151 | |
2152 | 3. Skip bigtoc fixup code. | |
2153 | ||
c906108c | 2154 | Result is desired PC to step until, or NULL if we are not in |
977adac5 | 2155 | code that should be skipped. */ |
c906108c | 2156 | |
63807e1d | 2157 | static CORE_ADDR |
52f729a7 | 2158 | rs6000_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 2159 | { |
e17a4113 UW |
2160 | struct gdbarch *gdbarch = get_frame_arch (frame); |
2161 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2162 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
52f0bd74 | 2163 | unsigned int ii, op; |
977adac5 | 2164 | int rel; |
c906108c | 2165 | CORE_ADDR solib_target_pc; |
7cbd4a93 | 2166 | struct bound_minimal_symbol msymbol; |
c906108c | 2167 | |
c5aa993b JM |
2168 | static unsigned trampoline_code[] = |
2169 | { | |
2170 | 0x800b0000, /* l r0,0x0(r11) */ | |
2171 | 0x90410014, /* st r2,0x14(r1) */ | |
2172 | 0x7c0903a6, /* mtctr r0 */ | |
2173 | 0x804b0004, /* l r2,0x4(r11) */ | |
2174 | 0x816b0008, /* l r11,0x8(r11) */ | |
2175 | 0x4e800420, /* bctr */ | |
2176 | 0x4e800020, /* br */ | |
2177 | 0 | |
c906108c SS |
2178 | }; |
2179 | ||
977adac5 ND |
2180 | /* Check for bigtoc fixup code. */ |
2181 | msymbol = lookup_minimal_symbol_by_pc (pc); | |
7cbd4a93 | 2182 | if (msymbol.minsym |
e17a4113 | 2183 | && rs6000_in_solib_return_trampoline (gdbarch, pc, |
efd66ac6 | 2184 | MSYMBOL_LINKAGE_NAME (msymbol.minsym))) |
977adac5 ND |
2185 | { |
2186 | /* Double-check that the third instruction from PC is relative "b". */ | |
e17a4113 | 2187 | op = read_memory_integer (pc + 8, 4, byte_order); |
977adac5 ND |
2188 | if ((op & 0xfc000003) == 0x48000000) |
2189 | { | |
2190 | /* Extract bits 6-29 as a signed 24-bit relative word address and | |
2191 | add it to the containing PC. */ | |
2192 | rel = ((int)(op << 6) >> 6); | |
2193 | return pc + 8 + rel; | |
2194 | } | |
2195 | } | |
2196 | ||
c906108c | 2197 | /* If pc is in a shared library trampoline, return its target. */ |
52f729a7 | 2198 | solib_target_pc = find_solib_trampoline_target (frame, pc); |
c906108c SS |
2199 | if (solib_target_pc) |
2200 | return solib_target_pc; | |
2201 | ||
c5aa993b JM |
2202 | for (ii = 0; trampoline_code[ii]; ++ii) |
2203 | { | |
e17a4113 | 2204 | op = read_memory_integer (pc + (ii * 4), 4, byte_order); |
c5aa993b JM |
2205 | if (op != trampoline_code[ii]) |
2206 | return 0; | |
2207 | } | |
0df8b418 MS |
2208 | ii = get_frame_register_unsigned (frame, 11); /* r11 holds destination |
2209 | addr. */ | |
e17a4113 | 2210 | pc = read_memory_unsigned_integer (ii, tdep->wordsize, byte_order); |
c906108c SS |
2211 | return pc; |
2212 | } | |
2213 | ||
794ac428 UW |
2214 | /* ISA-specific vector types. */ |
2215 | ||
2216 | static struct type * | |
2217 | rs6000_builtin_type_vec64 (struct gdbarch *gdbarch) | |
2218 | { | |
2219 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2220 | ||
2221 | if (!tdep->ppc_builtin_type_vec64) | |
2222 | { | |
df4df182 UW |
2223 | const struct builtin_type *bt = builtin_type (gdbarch); |
2224 | ||
794ac428 UW |
2225 | /* The type we're building is this: */ |
2226 | #if 0 | |
2227 | union __gdb_builtin_type_vec64 | |
2228 | { | |
2229 | int64_t uint64; | |
2230 | float v2_float[2]; | |
2231 | int32_t v2_int32[2]; | |
2232 | int16_t v4_int16[4]; | |
2233 | int8_t v8_int8[8]; | |
2234 | }; | |
2235 | #endif | |
2236 | ||
2237 | struct type *t; | |
2238 | ||
e9bb382b UW |
2239 | t = arch_composite_type (gdbarch, |
2240 | "__ppc_builtin_type_vec64", TYPE_CODE_UNION); | |
df4df182 | 2241 | append_composite_type_field (t, "uint64", bt->builtin_int64); |
794ac428 | 2242 | append_composite_type_field (t, "v2_float", |
df4df182 | 2243 | init_vector_type (bt->builtin_float, 2)); |
794ac428 | 2244 | append_composite_type_field (t, "v2_int32", |
df4df182 | 2245 | init_vector_type (bt->builtin_int32, 2)); |
794ac428 | 2246 | append_composite_type_field (t, "v4_int16", |
df4df182 | 2247 | init_vector_type (bt->builtin_int16, 4)); |
794ac428 | 2248 | append_composite_type_field (t, "v8_int8", |
df4df182 | 2249 | init_vector_type (bt->builtin_int8, 8)); |
794ac428 | 2250 | |
876cecd0 | 2251 | TYPE_VECTOR (t) = 1; |
794ac428 UW |
2252 | TYPE_NAME (t) = "ppc_builtin_type_vec64"; |
2253 | tdep->ppc_builtin_type_vec64 = t; | |
2254 | } | |
2255 | ||
2256 | return tdep->ppc_builtin_type_vec64; | |
2257 | } | |
2258 | ||
604c2f83 LM |
2259 | /* Vector 128 type. */ |
2260 | ||
2261 | static struct type * | |
2262 | rs6000_builtin_type_vec128 (struct gdbarch *gdbarch) | |
2263 | { | |
2264 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2265 | ||
2266 | if (!tdep->ppc_builtin_type_vec128) | |
2267 | { | |
df4df182 UW |
2268 | const struct builtin_type *bt = builtin_type (gdbarch); |
2269 | ||
604c2f83 LM |
2270 | /* The type we're building is this |
2271 | ||
2272 | type = union __ppc_builtin_type_vec128 { | |
2273 | uint128_t uint128; | |
db9f5df8 | 2274 | double v2_double[2]; |
604c2f83 LM |
2275 | float v4_float[4]; |
2276 | int32_t v4_int32[4]; | |
2277 | int16_t v8_int16[8]; | |
2278 | int8_t v16_int8[16]; | |
2279 | } | |
2280 | */ | |
2281 | ||
2282 | struct type *t; | |
2283 | ||
e9bb382b UW |
2284 | t = arch_composite_type (gdbarch, |
2285 | "__ppc_builtin_type_vec128", TYPE_CODE_UNION); | |
df4df182 | 2286 | append_composite_type_field (t, "uint128", bt->builtin_uint128); |
db9f5df8 UW |
2287 | append_composite_type_field (t, "v2_double", |
2288 | init_vector_type (bt->builtin_double, 2)); | |
604c2f83 | 2289 | append_composite_type_field (t, "v4_float", |
df4df182 | 2290 | init_vector_type (bt->builtin_float, 4)); |
604c2f83 | 2291 | append_composite_type_field (t, "v4_int32", |
df4df182 | 2292 | init_vector_type (bt->builtin_int32, 4)); |
604c2f83 | 2293 | append_composite_type_field (t, "v8_int16", |
df4df182 | 2294 | init_vector_type (bt->builtin_int16, 8)); |
604c2f83 | 2295 | append_composite_type_field (t, "v16_int8", |
df4df182 | 2296 | init_vector_type (bt->builtin_int8, 16)); |
604c2f83 | 2297 | |
803e1097 | 2298 | TYPE_VECTOR (t) = 1; |
604c2f83 LM |
2299 | TYPE_NAME (t) = "ppc_builtin_type_vec128"; |
2300 | tdep->ppc_builtin_type_vec128 = t; | |
2301 | } | |
2302 | ||
2303 | return tdep->ppc_builtin_type_vec128; | |
2304 | } | |
2305 | ||
7cc46491 DJ |
2306 | /* Return the name of register number REGNO, or the empty string if it |
2307 | is an anonymous register. */ | |
7a78ae4e | 2308 | |
fa88f677 | 2309 | static const char * |
d93859e2 | 2310 | rs6000_register_name (struct gdbarch *gdbarch, int regno) |
7a78ae4e | 2311 | { |
d93859e2 | 2312 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7a78ae4e | 2313 | |
7cc46491 DJ |
2314 | /* The upper half "registers" have names in the XML description, |
2315 | but we present only the low GPRs and the full 64-bit registers | |
2316 | to the user. */ | |
2317 | if (tdep->ppc_ev0_upper_regnum >= 0 | |
2318 | && tdep->ppc_ev0_upper_regnum <= regno | |
2319 | && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) | |
2320 | return ""; | |
2321 | ||
604c2f83 LM |
2322 | /* Hide the upper halves of the vs0~vs31 registers. */ |
2323 | if (tdep->ppc_vsr0_regnum >= 0 | |
2324 | && tdep->ppc_vsr0_upper_regnum <= regno | |
2325 | && regno < tdep->ppc_vsr0_upper_regnum + ppc_num_gprs) | |
2326 | return ""; | |
2327 | ||
7cc46491 | 2328 | /* Check if the SPE pseudo registers are available. */ |
5a9e69ba | 2329 | if (IS_SPE_PSEUDOREG (tdep, regno)) |
7cc46491 DJ |
2330 | { |
2331 | static const char *const spe_regnames[] = { | |
2332 | "ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7", | |
2333 | "ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15", | |
2334 | "ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23", | |
2335 | "ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31", | |
2336 | }; | |
2337 | return spe_regnames[regno - tdep->ppc_ev0_regnum]; | |
2338 | } | |
2339 | ||
f949c649 TJB |
2340 | /* Check if the decimal128 pseudo-registers are available. */ |
2341 | if (IS_DFP_PSEUDOREG (tdep, regno)) | |
2342 | { | |
2343 | static const char *const dfp128_regnames[] = { | |
2344 | "dl0", "dl1", "dl2", "dl3", | |
2345 | "dl4", "dl5", "dl6", "dl7", | |
2346 | "dl8", "dl9", "dl10", "dl11", | |
2347 | "dl12", "dl13", "dl14", "dl15" | |
2348 | }; | |
2349 | return dfp128_regnames[regno - tdep->ppc_dl0_regnum]; | |
2350 | } | |
2351 | ||
604c2f83 LM |
2352 | /* Check if this is a VSX pseudo-register. */ |
2353 | if (IS_VSX_PSEUDOREG (tdep, regno)) | |
2354 | { | |
2355 | static const char *const vsx_regnames[] = { | |
2356 | "vs0", "vs1", "vs2", "vs3", "vs4", "vs5", "vs6", "vs7", | |
2357 | "vs8", "vs9", "vs10", "vs11", "vs12", "vs13", "vs14", | |
2358 | "vs15", "vs16", "vs17", "vs18", "vs19", "vs20", "vs21", | |
2359 | "vs22", "vs23", "vs24", "vs25", "vs26", "vs27", "vs28", | |
2360 | "vs29", "vs30", "vs31", "vs32", "vs33", "vs34", "vs35", | |
2361 | "vs36", "vs37", "vs38", "vs39", "vs40", "vs41", "vs42", | |
2362 | "vs43", "vs44", "vs45", "vs46", "vs47", "vs48", "vs49", | |
2363 | "vs50", "vs51", "vs52", "vs53", "vs54", "vs55", "vs56", | |
2364 | "vs57", "vs58", "vs59", "vs60", "vs61", "vs62", "vs63" | |
2365 | }; | |
2366 | return vsx_regnames[regno - tdep->ppc_vsr0_regnum]; | |
2367 | } | |
2368 | ||
2369 | /* Check if the this is a Extended FP pseudo-register. */ | |
2370 | if (IS_EFP_PSEUDOREG (tdep, regno)) | |
2371 | { | |
2372 | static const char *const efpr_regnames[] = { | |
2373 | "f32", "f33", "f34", "f35", "f36", "f37", "f38", | |
2374 | "f39", "f40", "f41", "f42", "f43", "f44", "f45", | |
2375 | "f46", "f47", "f48", "f49", "f50", "f51", | |
2376 | "f52", "f53", "f54", "f55", "f56", "f57", | |
2377 | "f58", "f59", "f60", "f61", "f62", "f63" | |
2378 | }; | |
2379 | return efpr_regnames[regno - tdep->ppc_efpr0_regnum]; | |
2380 | } | |
2381 | ||
d93859e2 | 2382 | return tdesc_register_name (gdbarch, regno); |
7a78ae4e ND |
2383 | } |
2384 | ||
7cc46491 DJ |
2385 | /* Return the GDB type object for the "standard" data type of data in |
2386 | register N. */ | |
7a78ae4e ND |
2387 | |
2388 | static struct type * | |
7cc46491 | 2389 | rs6000_pseudo_register_type (struct gdbarch *gdbarch, int regnum) |
7a78ae4e | 2390 | { |
691d145a | 2391 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7a78ae4e | 2392 | |
7cc46491 | 2393 | /* These are the only pseudo-registers we support. */ |
f949c649 | 2394 | gdb_assert (IS_SPE_PSEUDOREG (tdep, regnum) |
604c2f83 LM |
2395 | || IS_DFP_PSEUDOREG (tdep, regnum) |
2396 | || IS_VSX_PSEUDOREG (tdep, regnum) | |
2397 | || IS_EFP_PSEUDOREG (tdep, regnum)); | |
7cc46491 | 2398 | |
f949c649 TJB |
2399 | /* These are the e500 pseudo-registers. */ |
2400 | if (IS_SPE_PSEUDOREG (tdep, regnum)) | |
2401 | return rs6000_builtin_type_vec64 (gdbarch); | |
604c2f83 LM |
2402 | else if (IS_DFP_PSEUDOREG (tdep, regnum)) |
2403 | /* PPC decimal128 pseudo-registers. */ | |
f949c649 | 2404 | return builtin_type (gdbarch)->builtin_declong; |
604c2f83 LM |
2405 | else if (IS_VSX_PSEUDOREG (tdep, regnum)) |
2406 | /* POWER7 VSX pseudo-registers. */ | |
2407 | return rs6000_builtin_type_vec128 (gdbarch); | |
2408 | else | |
2409 | /* POWER7 Extended FP pseudo-registers. */ | |
2410 | return builtin_type (gdbarch)->builtin_double; | |
7a78ae4e ND |
2411 | } |
2412 | ||
c44ca51c AC |
2413 | /* Is REGNUM a member of REGGROUP? */ |
2414 | static int | |
7cc46491 DJ |
2415 | rs6000_pseudo_register_reggroup_p (struct gdbarch *gdbarch, int regnum, |
2416 | struct reggroup *group) | |
c44ca51c AC |
2417 | { |
2418 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
c44ca51c | 2419 | |
7cc46491 | 2420 | /* These are the only pseudo-registers we support. */ |
f949c649 | 2421 | gdb_assert (IS_SPE_PSEUDOREG (tdep, regnum) |
604c2f83 LM |
2422 | || IS_DFP_PSEUDOREG (tdep, regnum) |
2423 | || IS_VSX_PSEUDOREG (tdep, regnum) | |
2424 | || IS_EFP_PSEUDOREG (tdep, regnum)); | |
c44ca51c | 2425 | |
604c2f83 LM |
2426 | /* These are the e500 pseudo-registers or the POWER7 VSX registers. */ |
2427 | if (IS_SPE_PSEUDOREG (tdep, regnum) || IS_VSX_PSEUDOREG (tdep, regnum)) | |
f949c649 | 2428 | return group == all_reggroup || group == vector_reggroup; |
7cc46491 | 2429 | else |
604c2f83 | 2430 | /* PPC decimal128 or Extended FP pseudo-registers. */ |
f949c649 | 2431 | return group == all_reggroup || group == float_reggroup; |
c44ca51c AC |
2432 | } |
2433 | ||
691d145a | 2434 | /* The register format for RS/6000 floating point registers is always |
64366f1c | 2435 | double, we need a conversion if the memory format is float. */ |
7a78ae4e ND |
2436 | |
2437 | static int | |
0abe36f5 MD |
2438 | rs6000_convert_register_p (struct gdbarch *gdbarch, int regnum, |
2439 | struct type *type) | |
7a78ae4e | 2440 | { |
0abe36f5 | 2441 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7cc46491 DJ |
2442 | |
2443 | return (tdep->ppc_fp0_regnum >= 0 | |
2444 | && regnum >= tdep->ppc_fp0_regnum | |
2445 | && regnum < tdep->ppc_fp0_regnum + ppc_num_fprs | |
2446 | && TYPE_CODE (type) == TYPE_CODE_FLT | |
0dfff4cb UW |
2447 | && TYPE_LENGTH (type) |
2448 | != TYPE_LENGTH (builtin_type (gdbarch)->builtin_double)); | |
7a78ae4e ND |
2449 | } |
2450 | ||
8dccd430 | 2451 | static int |
691d145a JB |
2452 | rs6000_register_to_value (struct frame_info *frame, |
2453 | int regnum, | |
2454 | struct type *type, | |
8dccd430 PA |
2455 | gdb_byte *to, |
2456 | int *optimizedp, int *unavailablep) | |
7a78ae4e | 2457 | { |
0dfff4cb | 2458 | struct gdbarch *gdbarch = get_frame_arch (frame); |
0f068fb5 | 2459 | gdb_byte from[PPC_MAX_REGISTER_SIZE]; |
691d145a | 2460 | |
691d145a | 2461 | gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT); |
7a78ae4e | 2462 | |
8dccd430 PA |
2463 | if (!get_frame_register_bytes (frame, regnum, 0, |
2464 | register_size (gdbarch, regnum), | |
2465 | from, optimizedp, unavailablep)) | |
2466 | return 0; | |
2467 | ||
3b2ca824 UW |
2468 | target_float_convert (from, builtin_type (gdbarch)->builtin_double, |
2469 | to, type); | |
8dccd430 PA |
2470 | *optimizedp = *unavailablep = 0; |
2471 | return 1; | |
691d145a | 2472 | } |
7a292a7a | 2473 | |
7a78ae4e | 2474 | static void |
691d145a JB |
2475 | rs6000_value_to_register (struct frame_info *frame, |
2476 | int regnum, | |
2477 | struct type *type, | |
50fd1280 | 2478 | const gdb_byte *from) |
7a78ae4e | 2479 | { |
0dfff4cb | 2480 | struct gdbarch *gdbarch = get_frame_arch (frame); |
0f068fb5 | 2481 | gdb_byte to[PPC_MAX_REGISTER_SIZE]; |
691d145a | 2482 | |
691d145a JB |
2483 | gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT); |
2484 | ||
3b2ca824 UW |
2485 | target_float_convert (from, type, |
2486 | to, builtin_type (gdbarch)->builtin_double); | |
691d145a | 2487 | put_frame_register (frame, regnum, to); |
7a78ae4e | 2488 | } |
c906108c | 2489 | |
05d1431c PA |
2490 | /* The type of a function that moves the value of REG between CACHE |
2491 | or BUF --- in either direction. */ | |
2492 | typedef enum register_status (*move_ev_register_func) (struct regcache *, | |
2493 | int, void *); | |
2494 | ||
6ced10dd JB |
2495 | /* Move SPE vector register values between a 64-bit buffer and the two |
2496 | 32-bit raw register halves in a regcache. This function handles | |
2497 | both splitting a 64-bit value into two 32-bit halves, and joining | |
2498 | two halves into a whole 64-bit value, depending on the function | |
2499 | passed as the MOVE argument. | |
2500 | ||
2501 | EV_REG must be the number of an SPE evN vector register --- a | |
2502 | pseudoregister. REGCACHE must be a regcache, and BUFFER must be a | |
2503 | 64-bit buffer. | |
2504 | ||
2505 | Call MOVE once for each 32-bit half of that register, passing | |
2506 | REGCACHE, the number of the raw register corresponding to that | |
2507 | half, and the address of the appropriate half of BUFFER. | |
2508 | ||
2509 | For example, passing 'regcache_raw_read' as the MOVE function will | |
2510 | fill BUFFER with the full 64-bit contents of EV_REG. Or, passing | |
2511 | 'regcache_raw_supply' will supply the contents of BUFFER to the | |
2512 | appropriate pair of raw registers in REGCACHE. | |
2513 | ||
2514 | You may need to cast away some 'const' qualifiers when passing | |
2515 | MOVE, since this function can't tell at compile-time which of | |
2516 | REGCACHE or BUFFER is acting as the source of the data. If C had | |
2517 | co-variant type qualifiers, ... */ | |
05d1431c PA |
2518 | |
2519 | static enum register_status | |
2520 | e500_move_ev_register (move_ev_register_func move, | |
2521 | struct regcache *regcache, int ev_reg, void *buffer) | |
6ced10dd | 2522 | { |
ac7936df | 2523 | struct gdbarch *arch = regcache->arch (); |
6ced10dd JB |
2524 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); |
2525 | int reg_index; | |
19ba03f4 | 2526 | gdb_byte *byte_buffer = (gdb_byte *) buffer; |
05d1431c | 2527 | enum register_status status; |
6ced10dd | 2528 | |
5a9e69ba | 2529 | gdb_assert (IS_SPE_PSEUDOREG (tdep, ev_reg)); |
6ced10dd JB |
2530 | |
2531 | reg_index = ev_reg - tdep->ppc_ev0_regnum; | |
2532 | ||
8b164abb | 2533 | if (gdbarch_byte_order (arch) == BFD_ENDIAN_BIG) |
6ced10dd | 2534 | { |
05d1431c PA |
2535 | status = move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, |
2536 | byte_buffer); | |
2537 | if (status == REG_VALID) | |
2538 | status = move (regcache, tdep->ppc_gp0_regnum + reg_index, | |
2539 | byte_buffer + 4); | |
6ced10dd JB |
2540 | } |
2541 | else | |
2542 | { | |
05d1431c PA |
2543 | status = move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer); |
2544 | if (status == REG_VALID) | |
2545 | status = move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, | |
2546 | byte_buffer + 4); | |
6ced10dd | 2547 | } |
05d1431c PA |
2548 | |
2549 | return status; | |
6ced10dd JB |
2550 | } |
2551 | ||
05d1431c PA |
2552 | static enum register_status |
2553 | do_regcache_raw_write (struct regcache *regcache, int regnum, void *buffer) | |
2554 | { | |
10eaee5f | 2555 | regcache->raw_write (regnum, (const gdb_byte *) buffer); |
05d1431c PA |
2556 | |
2557 | return REG_VALID; | |
2558 | } | |
2559 | ||
2560 | static enum register_status | |
849d0ba8 YQ |
2561 | e500_pseudo_register_read (struct gdbarch *gdbarch, readable_regcache *regcache, |
2562 | int ev_reg, gdb_byte *buffer) | |
f949c649 | 2563 | { |
849d0ba8 YQ |
2564 | struct gdbarch *arch = regcache->arch (); |
2565 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); | |
2566 | int reg_index; | |
2567 | enum register_status status; | |
2568 | ||
2569 | gdb_assert (IS_SPE_PSEUDOREG (tdep, ev_reg)); | |
2570 | ||
2571 | reg_index = ev_reg - tdep->ppc_ev0_regnum; | |
2572 | ||
2573 | if (gdbarch_byte_order (arch) == BFD_ENDIAN_BIG) | |
2574 | { | |
2575 | status = regcache->raw_read (tdep->ppc_ev0_upper_regnum + reg_index, | |
2576 | buffer); | |
2577 | if (status == REG_VALID) | |
2578 | status = regcache->raw_read (tdep->ppc_gp0_regnum + reg_index, | |
2579 | buffer + 4); | |
2580 | } | |
2581 | else | |
2582 | { | |
2583 | status = regcache->raw_read (tdep->ppc_gp0_regnum + reg_index, buffer); | |
2584 | if (status == REG_VALID) | |
2585 | status = regcache->raw_read (tdep->ppc_ev0_upper_regnum + reg_index, | |
2586 | buffer + 4); | |
2587 | } | |
2588 | ||
2589 | return status; | |
2590 | ||
f949c649 TJB |
2591 | } |
2592 | ||
2593 | static void | |
2594 | e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
2595 | int reg_nr, const gdb_byte *buffer) | |
2596 | { | |
05d1431c PA |
2597 | e500_move_ev_register (do_regcache_raw_write, regcache, |
2598 | reg_nr, (void *) buffer); | |
f949c649 TJB |
2599 | } |
2600 | ||
604c2f83 | 2601 | /* Read method for DFP pseudo-registers. */ |
05d1431c | 2602 | static enum register_status |
849d0ba8 | 2603 | dfp_pseudo_register_read (struct gdbarch *gdbarch, readable_regcache *regcache, |
f949c649 TJB |
2604 | int reg_nr, gdb_byte *buffer) |
2605 | { | |
2606 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2607 | int reg_index = reg_nr - tdep->ppc_dl0_regnum; | |
05d1431c | 2608 | enum register_status status; |
f949c649 TJB |
2609 | |
2610 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
2611 | { | |
2612 | /* Read two FP registers to form a whole dl register. */ | |
03f50fc8 YQ |
2613 | status = regcache->raw_read (tdep->ppc_fp0_regnum + |
2614 | 2 * reg_index, buffer); | |
05d1431c | 2615 | if (status == REG_VALID) |
03f50fc8 YQ |
2616 | status = regcache->raw_read (tdep->ppc_fp0_regnum + |
2617 | 2 * reg_index + 1, buffer + 8); | |
f949c649 TJB |
2618 | } |
2619 | else | |
2620 | { | |
03f50fc8 YQ |
2621 | status = regcache->raw_read (tdep->ppc_fp0_regnum + |
2622 | 2 * reg_index + 1, buffer); | |
05d1431c | 2623 | if (status == REG_VALID) |
03f50fc8 YQ |
2624 | status = regcache->raw_read (tdep->ppc_fp0_regnum + |
2625 | 2 * reg_index, buffer + 8); | |
f949c649 | 2626 | } |
05d1431c PA |
2627 | |
2628 | return status; | |
f949c649 TJB |
2629 | } |
2630 | ||
604c2f83 | 2631 | /* Write method for DFP pseudo-registers. */ |
f949c649 | 2632 | static void |
604c2f83 | 2633 | dfp_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, |
f949c649 TJB |
2634 | int reg_nr, const gdb_byte *buffer) |
2635 | { | |
2636 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2637 | int reg_index = reg_nr - tdep->ppc_dl0_regnum; | |
2638 | ||
2639 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
2640 | { | |
2641 | /* Write each half of the dl register into a separate | |
2642 | FP register. */ | |
10eaee5f | 2643 | regcache->raw_write (tdep->ppc_fp0_regnum + |
f949c649 | 2644 | 2 * reg_index, buffer); |
10eaee5f | 2645 | regcache->raw_write (tdep->ppc_fp0_regnum + |
f949c649 TJB |
2646 | 2 * reg_index + 1, buffer + 8); |
2647 | } | |
2648 | else | |
2649 | { | |
10eaee5f | 2650 | regcache->raw_write (tdep->ppc_fp0_regnum + |
0ff3e01f | 2651 | 2 * reg_index + 1, buffer); |
10eaee5f | 2652 | regcache->raw_write (tdep->ppc_fp0_regnum + |
0ff3e01f | 2653 | 2 * reg_index, buffer + 8); |
f949c649 TJB |
2654 | } |
2655 | } | |
2656 | ||
604c2f83 | 2657 | /* Read method for POWER7 VSX pseudo-registers. */ |
05d1431c | 2658 | static enum register_status |
849d0ba8 | 2659 | vsx_pseudo_register_read (struct gdbarch *gdbarch, readable_regcache *regcache, |
604c2f83 LM |
2660 | int reg_nr, gdb_byte *buffer) |
2661 | { | |
2662 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2663 | int reg_index = reg_nr - tdep->ppc_vsr0_regnum; | |
05d1431c | 2664 | enum register_status status; |
604c2f83 LM |
2665 | |
2666 | /* Read the portion that overlaps the VMX registers. */ | |
2667 | if (reg_index > 31) | |
03f50fc8 YQ |
2668 | status = regcache->raw_read (tdep->ppc_vr0_regnum + |
2669 | reg_index - 32, buffer); | |
604c2f83 LM |
2670 | else |
2671 | /* Read the portion that overlaps the FPR registers. */ | |
2672 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
2673 | { | |
03f50fc8 YQ |
2674 | status = regcache->raw_read (tdep->ppc_fp0_regnum + |
2675 | reg_index, buffer); | |
05d1431c | 2676 | if (status == REG_VALID) |
03f50fc8 YQ |
2677 | status = regcache->raw_read (tdep->ppc_vsr0_upper_regnum + |
2678 | reg_index, buffer + 8); | |
604c2f83 LM |
2679 | } |
2680 | else | |
2681 | { | |
03f50fc8 YQ |
2682 | status = regcache->raw_read (tdep->ppc_fp0_regnum + |
2683 | reg_index, buffer + 8); | |
05d1431c | 2684 | if (status == REG_VALID) |
03f50fc8 YQ |
2685 | status = regcache->raw_read (tdep->ppc_vsr0_upper_regnum + |
2686 | reg_index, buffer); | |
604c2f83 | 2687 | } |
05d1431c PA |
2688 | |
2689 | return status; | |
604c2f83 LM |
2690 | } |
2691 | ||
2692 | /* Write method for POWER7 VSX pseudo-registers. */ | |
2693 | static void | |
2694 | vsx_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
2695 | int reg_nr, const gdb_byte *buffer) | |
2696 | { | |
2697 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2698 | int reg_index = reg_nr - tdep->ppc_vsr0_regnum; | |
2699 | ||
2700 | /* Write the portion that overlaps the VMX registers. */ | |
2701 | if (reg_index > 31) | |
10eaee5f | 2702 | regcache->raw_write (tdep->ppc_vr0_regnum + |
604c2f83 LM |
2703 | reg_index - 32, buffer); |
2704 | else | |
2705 | /* Write the portion that overlaps the FPR registers. */ | |
2706 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
2707 | { | |
10eaee5f | 2708 | regcache->raw_write (tdep->ppc_fp0_regnum + |
604c2f83 | 2709 | reg_index, buffer); |
10eaee5f | 2710 | regcache->raw_write (tdep->ppc_vsr0_upper_regnum + |
604c2f83 LM |
2711 | reg_index, buffer + 8); |
2712 | } | |
2713 | else | |
2714 | { | |
10eaee5f | 2715 | regcache->raw_write (tdep->ppc_fp0_regnum + |
604c2f83 | 2716 | reg_index, buffer + 8); |
10eaee5f | 2717 | regcache->raw_write (tdep->ppc_vsr0_upper_regnum + |
604c2f83 LM |
2718 | reg_index, buffer); |
2719 | } | |
2720 | } | |
2721 | ||
2722 | /* Read method for POWER7 Extended FP pseudo-registers. */ | |
05d1431c | 2723 | static enum register_status |
849d0ba8 | 2724 | efpr_pseudo_register_read (struct gdbarch *gdbarch, readable_regcache *regcache, |
604c2f83 LM |
2725 | int reg_nr, gdb_byte *buffer) |
2726 | { | |
2727 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2728 | int reg_index = reg_nr - tdep->ppc_efpr0_regnum; | |
084ee545 | 2729 | int offset = gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG ? 0 : 8; |
604c2f83 | 2730 | |
d9492458 | 2731 | /* Read the portion that overlaps the VMX register. */ |
849d0ba8 YQ |
2732 | return regcache->raw_read_part (tdep->ppc_vr0_regnum + reg_index, |
2733 | offset, register_size (gdbarch, reg_nr), | |
2734 | buffer); | |
604c2f83 LM |
2735 | } |
2736 | ||
2737 | /* Write method for POWER7 Extended FP pseudo-registers. */ | |
2738 | static void | |
2739 | efpr_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
2740 | int reg_nr, const gdb_byte *buffer) | |
2741 | { | |
2742 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2743 | int reg_index = reg_nr - tdep->ppc_efpr0_regnum; | |
084ee545 | 2744 | int offset = gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG ? 0 : 8; |
604c2f83 | 2745 | |
d9492458 | 2746 | /* Write the portion that overlaps the VMX register. */ |
4f0420fd SM |
2747 | regcache->raw_write_part (tdep->ppc_vr0_regnum + reg_index, offset, |
2748 | register_size (gdbarch, reg_nr), buffer); | |
604c2f83 LM |
2749 | } |
2750 | ||
05d1431c | 2751 | static enum register_status |
0df8b418 | 2752 | rs6000_pseudo_register_read (struct gdbarch *gdbarch, |
849d0ba8 | 2753 | readable_regcache *regcache, |
f949c649 | 2754 | int reg_nr, gdb_byte *buffer) |
c8001721 | 2755 | { |
ac7936df | 2756 | struct gdbarch *regcache_arch = regcache->arch (); |
c8001721 EZ |
2757 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2758 | ||
6ced10dd | 2759 | gdb_assert (regcache_arch == gdbarch); |
f949c649 | 2760 | |
5a9e69ba | 2761 | if (IS_SPE_PSEUDOREG (tdep, reg_nr)) |
05d1431c | 2762 | return e500_pseudo_register_read (gdbarch, regcache, reg_nr, buffer); |
f949c649 | 2763 | else if (IS_DFP_PSEUDOREG (tdep, reg_nr)) |
05d1431c | 2764 | return dfp_pseudo_register_read (gdbarch, regcache, reg_nr, buffer); |
604c2f83 | 2765 | else if (IS_VSX_PSEUDOREG (tdep, reg_nr)) |
05d1431c | 2766 | return vsx_pseudo_register_read (gdbarch, regcache, reg_nr, buffer); |
604c2f83 | 2767 | else if (IS_EFP_PSEUDOREG (tdep, reg_nr)) |
05d1431c | 2768 | return efpr_pseudo_register_read (gdbarch, regcache, reg_nr, buffer); |
6ced10dd | 2769 | else |
a44bddec | 2770 | internal_error (__FILE__, __LINE__, |
f949c649 TJB |
2771 | _("rs6000_pseudo_register_read: " |
2772 | "called on unexpected register '%s' (%d)"), | |
2773 | gdbarch_register_name (gdbarch, reg_nr), reg_nr); | |
c8001721 EZ |
2774 | } |
2775 | ||
2776 | static void | |
f949c649 TJB |
2777 | rs6000_pseudo_register_write (struct gdbarch *gdbarch, |
2778 | struct regcache *regcache, | |
2779 | int reg_nr, const gdb_byte *buffer) | |
c8001721 | 2780 | { |
ac7936df | 2781 | struct gdbarch *regcache_arch = regcache->arch (); |
c8001721 EZ |
2782 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2783 | ||
6ced10dd | 2784 | gdb_assert (regcache_arch == gdbarch); |
f949c649 | 2785 | |
5a9e69ba | 2786 | if (IS_SPE_PSEUDOREG (tdep, reg_nr)) |
f949c649 TJB |
2787 | e500_pseudo_register_write (gdbarch, regcache, reg_nr, buffer); |
2788 | else if (IS_DFP_PSEUDOREG (tdep, reg_nr)) | |
604c2f83 LM |
2789 | dfp_pseudo_register_write (gdbarch, regcache, reg_nr, buffer); |
2790 | else if (IS_VSX_PSEUDOREG (tdep, reg_nr)) | |
2791 | vsx_pseudo_register_write (gdbarch, regcache, reg_nr, buffer); | |
2792 | else if (IS_EFP_PSEUDOREG (tdep, reg_nr)) | |
2793 | efpr_pseudo_register_write (gdbarch, regcache, reg_nr, buffer); | |
6ced10dd | 2794 | else |
a44bddec | 2795 | internal_error (__FILE__, __LINE__, |
f949c649 TJB |
2796 | _("rs6000_pseudo_register_write: " |
2797 | "called on unexpected register '%s' (%d)"), | |
2798 | gdbarch_register_name (gdbarch, reg_nr), reg_nr); | |
6ced10dd JB |
2799 | } |
2800 | ||
2a2fa07b MK |
2801 | static int |
2802 | rs6000_ax_pseudo_register_collect (struct gdbarch *gdbarch, | |
2803 | struct agent_expr *ax, int reg_nr) | |
2804 | { | |
2805 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2806 | if (IS_SPE_PSEUDOREG (tdep, reg_nr)) | |
2807 | { | |
2808 | int reg_index = reg_nr - tdep->ppc_ev0_regnum; | |
2809 | ax_reg_mask (ax, tdep->ppc_gp0_regnum + reg_index); | |
2810 | ax_reg_mask (ax, tdep->ppc_ev0_upper_regnum + reg_index); | |
2811 | } | |
2812 | else if (IS_DFP_PSEUDOREG (tdep, reg_nr)) | |
2813 | { | |
2814 | int reg_index = reg_nr - tdep->ppc_dl0_regnum; | |
2815 | ax_reg_mask (ax, tdep->ppc_fp0_regnum + 2 * reg_index); | |
2816 | ax_reg_mask (ax, tdep->ppc_fp0_regnum + 2 * reg_index + 1); | |
2817 | } | |
2818 | else if (IS_VSX_PSEUDOREG (tdep, reg_nr)) | |
2819 | { | |
2820 | int reg_index = reg_nr - tdep->ppc_vsr0_regnum; | |
2821 | if (reg_index > 31) | |
2822 | { | |
2823 | ax_reg_mask (ax, tdep->ppc_vr0_regnum + reg_index - 32); | |
2824 | } | |
2825 | else | |
2826 | { | |
2827 | ax_reg_mask (ax, tdep->ppc_fp0_regnum + reg_index); | |
2828 | ax_reg_mask (ax, tdep->ppc_vsr0_upper_regnum + reg_index); | |
2829 | } | |
2830 | } | |
2831 | else if (IS_EFP_PSEUDOREG (tdep, reg_nr)) | |
2832 | { | |
2833 | int reg_index = reg_nr - tdep->ppc_efpr0_regnum; | |
2834 | ax_reg_mask (ax, tdep->ppc_vr0_regnum + reg_index); | |
2835 | } | |
2836 | else | |
2837 | internal_error (__FILE__, __LINE__, | |
2838 | _("rs6000_pseudo_register_collect: " | |
2839 | "called on unexpected register '%s' (%d)"), | |
2840 | gdbarch_register_name (gdbarch, reg_nr), reg_nr); | |
2841 | return 0; | |
2842 | } | |
2843 | ||
2844 | ||
a67914de MK |
2845 | static void |
2846 | rs6000_gen_return_address (struct gdbarch *gdbarch, | |
2847 | struct agent_expr *ax, struct axs_value *value, | |
2848 | CORE_ADDR scope) | |
2849 | { | |
2850 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2851 | value->type = register_type (gdbarch, tdep->ppc_lr_regnum); | |
2852 | value->kind = axs_lvalue_register; | |
2853 | value->u.reg = tdep->ppc_lr_regnum; | |
2854 | } | |
2855 | ||
2856 | ||
18ed0c4e | 2857 | /* Convert a DBX STABS register number to a GDB register number. */ |
c8001721 | 2858 | static int |
d3f73121 | 2859 | rs6000_stab_reg_to_regnum (struct gdbarch *gdbarch, int num) |
c8001721 | 2860 | { |
d3f73121 | 2861 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
c8001721 | 2862 | |
9f744501 JB |
2863 | if (0 <= num && num <= 31) |
2864 | return tdep->ppc_gp0_regnum + num; | |
2865 | else if (32 <= num && num <= 63) | |
383f0f5b JB |
2866 | /* FIXME: jimb/2004-05-05: What should we do when the debug info |
2867 | specifies registers the architecture doesn't have? Our | |
2868 | callers don't check the value we return. */ | |
366f009f | 2869 | return tdep->ppc_fp0_regnum + (num - 32); |
18ed0c4e JB |
2870 | else if (77 <= num && num <= 108) |
2871 | return tdep->ppc_vr0_regnum + (num - 77); | |
9f744501 | 2872 | else if (1200 <= num && num < 1200 + 32) |
e1ec1b42 | 2873 | return tdep->ppc_ev0_upper_regnum + (num - 1200); |
9f744501 JB |
2874 | else |
2875 | switch (num) | |
2876 | { | |
2877 | case 64: | |
2878 | return tdep->ppc_mq_regnum; | |
2879 | case 65: | |
2880 | return tdep->ppc_lr_regnum; | |
2881 | case 66: | |
2882 | return tdep->ppc_ctr_regnum; | |
2883 | case 76: | |
2884 | return tdep->ppc_xer_regnum; | |
2885 | case 109: | |
2886 | return tdep->ppc_vrsave_regnum; | |
18ed0c4e JB |
2887 | case 110: |
2888 | return tdep->ppc_vrsave_regnum - 1; /* vscr */ | |
867e2dc5 | 2889 | case 111: |
18ed0c4e | 2890 | return tdep->ppc_acc_regnum; |
867e2dc5 | 2891 | case 112: |
18ed0c4e | 2892 | return tdep->ppc_spefscr_regnum; |
9f744501 JB |
2893 | default: |
2894 | return num; | |
2895 | } | |
18ed0c4e | 2896 | } |
9f744501 | 2897 | |
9f744501 | 2898 | |
18ed0c4e JB |
2899 | /* Convert a Dwarf 2 register number to a GDB register number. */ |
2900 | static int | |
d3f73121 | 2901 | rs6000_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int num) |
18ed0c4e | 2902 | { |
d3f73121 | 2903 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
9f744501 | 2904 | |
18ed0c4e JB |
2905 | if (0 <= num && num <= 31) |
2906 | return tdep->ppc_gp0_regnum + num; | |
2907 | else if (32 <= num && num <= 63) | |
2908 | /* FIXME: jimb/2004-05-05: What should we do when the debug info | |
2909 | specifies registers the architecture doesn't have? Our | |
2910 | callers don't check the value we return. */ | |
2911 | return tdep->ppc_fp0_regnum + (num - 32); | |
2912 | else if (1124 <= num && num < 1124 + 32) | |
2913 | return tdep->ppc_vr0_regnum + (num - 1124); | |
2914 | else if (1200 <= num && num < 1200 + 32) | |
e1ec1b42 | 2915 | return tdep->ppc_ev0_upper_regnum + (num - 1200); |
18ed0c4e JB |
2916 | else |
2917 | switch (num) | |
2918 | { | |
a489f789 AS |
2919 | case 64: |
2920 | return tdep->ppc_cr_regnum; | |
18ed0c4e JB |
2921 | case 67: |
2922 | return tdep->ppc_vrsave_regnum - 1; /* vscr */ | |
2923 | case 99: | |
2924 | return tdep->ppc_acc_regnum; | |
2925 | case 100: | |
2926 | return tdep->ppc_mq_regnum; | |
2927 | case 101: | |
2928 | return tdep->ppc_xer_regnum; | |
2929 | case 108: | |
2930 | return tdep->ppc_lr_regnum; | |
2931 | case 109: | |
2932 | return tdep->ppc_ctr_regnum; | |
2933 | case 356: | |
2934 | return tdep->ppc_vrsave_regnum; | |
2935 | case 612: | |
2936 | return tdep->ppc_spefscr_regnum; | |
2937 | default: | |
2938 | return num; | |
2939 | } | |
2188cbdd EZ |
2940 | } |
2941 | ||
4fc771b8 DJ |
2942 | /* Translate a .eh_frame register to DWARF register, or adjust a |
2943 | .debug_frame register. */ | |
2944 | ||
2945 | static int | |
2946 | rs6000_adjust_frame_regnum (struct gdbarch *gdbarch, int num, int eh_frame_p) | |
2947 | { | |
2948 | /* GCC releases before 3.4 use GCC internal register numbering in | |
2949 | .debug_frame (and .debug_info, et cetera). The numbering is | |
2950 | different from the standard SysV numbering for everything except | |
2951 | for GPRs and FPRs. We can not detect this problem in most cases | |
2952 | - to get accurate debug info for variables living in lr, ctr, v0, | |
2953 | et cetera, use a newer version of GCC. But we must detect | |
2954 | one important case - lr is in column 65 in .debug_frame output, | |
2955 | instead of 108. | |
2956 | ||
2957 | GCC 3.4, and the "hammer" branch, have a related problem. They | |
2958 | record lr register saves in .debug_frame as 108, but still record | |
2959 | the return column as 65. We fix that up too. | |
2960 | ||
2961 | We can do this because 65 is assigned to fpsr, and GCC never | |
2962 | generates debug info referring to it. To add support for | |
2963 | handwritten debug info that restores fpsr, we would need to add a | |
2964 | producer version check to this. */ | |
2965 | if (!eh_frame_p) | |
2966 | { | |
2967 | if (num == 65) | |
2968 | return 108; | |
2969 | else | |
2970 | return num; | |
2971 | } | |
2972 | ||
2973 | /* .eh_frame is GCC specific. For binary compatibility, it uses GCC | |
2974 | internal register numbering; translate that to the standard DWARF2 | |
2975 | register numbering. */ | |
2976 | if (0 <= num && num <= 63) /* r0-r31,fp0-fp31 */ | |
2977 | return num; | |
2978 | else if (68 <= num && num <= 75) /* cr0-cr8 */ | |
2979 | return num - 68 + 86; | |
2980 | else if (77 <= num && num <= 108) /* vr0-vr31 */ | |
2981 | return num - 77 + 1124; | |
2982 | else | |
2983 | switch (num) | |
2984 | { | |
2985 | case 64: /* mq */ | |
2986 | return 100; | |
2987 | case 65: /* lr */ | |
2988 | return 108; | |
2989 | case 66: /* ctr */ | |
2990 | return 109; | |
2991 | case 76: /* xer */ | |
2992 | return 101; | |
2993 | case 109: /* vrsave */ | |
2994 | return 356; | |
2995 | case 110: /* vscr */ | |
2996 | return 67; | |
2997 | case 111: /* spe_acc */ | |
2998 | return 99; | |
2999 | case 112: /* spefscr */ | |
3000 | return 612; | |
3001 | default: | |
3002 | return num; | |
3003 | } | |
3004 | } | |
c906108c | 3005 | \f |
c5aa993b | 3006 | |
7a78ae4e | 3007 | /* Handling the various POWER/PowerPC variants. */ |
c906108c | 3008 | |
c906108c | 3009 | /* Information about a particular processor variant. */ |
7a78ae4e | 3010 | |
c906108c | 3011 | struct variant |
c5aa993b JM |
3012 | { |
3013 | /* Name of this variant. */ | |
a121b7c1 | 3014 | const char *name; |
c906108c | 3015 | |
c5aa993b | 3016 | /* English description of the variant. */ |
a121b7c1 | 3017 | const char *description; |
c906108c | 3018 | |
64366f1c | 3019 | /* bfd_arch_info.arch corresponding to variant. */ |
7a78ae4e ND |
3020 | enum bfd_architecture arch; |
3021 | ||
64366f1c | 3022 | /* bfd_arch_info.mach corresponding to variant. */ |
7a78ae4e ND |
3023 | unsigned long mach; |
3024 | ||
7cc46491 DJ |
3025 | /* Target description for this variant. */ |
3026 | struct target_desc **tdesc; | |
c5aa993b | 3027 | }; |
c906108c | 3028 | |
489461e2 | 3029 | static struct variant variants[] = |
c906108c | 3030 | { |
7a78ae4e | 3031 | {"powerpc", "PowerPC user-level", bfd_arch_powerpc, |
7284e1be | 3032 | bfd_mach_ppc, &tdesc_powerpc_altivec32}, |
7a78ae4e | 3033 | {"power", "POWER user-level", bfd_arch_rs6000, |
7cc46491 | 3034 | bfd_mach_rs6k, &tdesc_rs6000}, |
7a78ae4e | 3035 | {"403", "IBM PowerPC 403", bfd_arch_powerpc, |
7cc46491 | 3036 | bfd_mach_ppc_403, &tdesc_powerpc_403}, |
4d09ffea MS |
3037 | {"405", "IBM PowerPC 405", bfd_arch_powerpc, |
3038 | bfd_mach_ppc_405, &tdesc_powerpc_405}, | |
7a78ae4e | 3039 | {"601", "Motorola PowerPC 601", bfd_arch_powerpc, |
7cc46491 | 3040 | bfd_mach_ppc_601, &tdesc_powerpc_601}, |
7a78ae4e | 3041 | {"602", "Motorola PowerPC 602", bfd_arch_powerpc, |
7cc46491 | 3042 | bfd_mach_ppc_602, &tdesc_powerpc_602}, |
7a78ae4e | 3043 | {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc, |
7cc46491 | 3044 | bfd_mach_ppc_603, &tdesc_powerpc_603}, |
7a78ae4e | 3045 | {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc, |
7cc46491 | 3046 | 604, &tdesc_powerpc_604}, |
7a78ae4e | 3047 | {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc, |
7cc46491 | 3048 | bfd_mach_ppc_403gc, &tdesc_powerpc_403gc}, |
7a78ae4e | 3049 | {"505", "Motorola PowerPC 505", bfd_arch_powerpc, |
7cc46491 | 3050 | bfd_mach_ppc_505, &tdesc_powerpc_505}, |
7a78ae4e | 3051 | {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc, |
7cc46491 | 3052 | bfd_mach_ppc_860, &tdesc_powerpc_860}, |
7a78ae4e | 3053 | {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc, |
7cc46491 | 3054 | bfd_mach_ppc_750, &tdesc_powerpc_750}, |
1fcc0bb8 | 3055 | {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc, |
7cc46491 | 3056 | bfd_mach_ppc_7400, &tdesc_powerpc_7400}, |
c8001721 | 3057 | {"e500", "Motorola PowerPC e500", bfd_arch_powerpc, |
7cc46491 | 3058 | bfd_mach_ppc_e500, &tdesc_powerpc_e500}, |
7a78ae4e | 3059 | |
5d57ee30 KB |
3060 | /* 64-bit */ |
3061 | {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc, | |
7284e1be | 3062 | bfd_mach_ppc64, &tdesc_powerpc_altivec64}, |
7a78ae4e | 3063 | {"620", "Motorola PowerPC 620", bfd_arch_powerpc, |
7cc46491 | 3064 | bfd_mach_ppc_620, &tdesc_powerpc_64}, |
5d57ee30 | 3065 | {"630", "Motorola PowerPC 630", bfd_arch_powerpc, |
7cc46491 | 3066 | bfd_mach_ppc_630, &tdesc_powerpc_64}, |
7a78ae4e | 3067 | {"a35", "PowerPC A35", bfd_arch_powerpc, |
7cc46491 | 3068 | bfd_mach_ppc_a35, &tdesc_powerpc_64}, |
5d57ee30 | 3069 | {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc, |
7cc46491 | 3070 | bfd_mach_ppc_rs64ii, &tdesc_powerpc_64}, |
5d57ee30 | 3071 | {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc, |
7cc46491 | 3072 | bfd_mach_ppc_rs64iii, &tdesc_powerpc_64}, |
5d57ee30 | 3073 | |
64366f1c | 3074 | /* FIXME: I haven't checked the register sets of the following. */ |
7a78ae4e | 3075 | {"rs1", "IBM POWER RS1", bfd_arch_rs6000, |
7cc46491 | 3076 | bfd_mach_rs6k_rs1, &tdesc_rs6000}, |
7a78ae4e | 3077 | {"rsc", "IBM POWER RSC", bfd_arch_rs6000, |
7cc46491 | 3078 | bfd_mach_rs6k_rsc, &tdesc_rs6000}, |
7a78ae4e | 3079 | {"rs2", "IBM POWER RS2", bfd_arch_rs6000, |
7cc46491 | 3080 | bfd_mach_rs6k_rs2, &tdesc_rs6000}, |
7a78ae4e | 3081 | |
3e45d68b | 3082 | {0, 0, (enum bfd_architecture) 0, 0, 0} |
c906108c SS |
3083 | }; |
3084 | ||
7a78ae4e | 3085 | /* Return the variant corresponding to architecture ARCH and machine number |
64366f1c | 3086 | MACH. If no such variant exists, return null. */ |
c906108c | 3087 | |
7a78ae4e ND |
3088 | static const struct variant * |
3089 | find_variant_by_arch (enum bfd_architecture arch, unsigned long mach) | |
c906108c | 3090 | { |
7a78ae4e | 3091 | const struct variant *v; |
c5aa993b | 3092 | |
7a78ae4e ND |
3093 | for (v = variants; v->name; v++) |
3094 | if (arch == v->arch && mach == v->mach) | |
3095 | return v; | |
c906108c | 3096 | |
7a78ae4e | 3097 | return NULL; |
c906108c | 3098 | } |
9364a0ef | 3099 | |
7a78ae4e | 3100 | \f |
61a65099 KB |
3101 | static CORE_ADDR |
3102 | rs6000_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
3103 | { | |
3e8c568d | 3104 | return frame_unwind_register_unsigned (next_frame, |
8b164abb | 3105 | gdbarch_pc_regnum (gdbarch)); |
61a65099 KB |
3106 | } |
3107 | ||
3108 | static struct frame_id | |
1af5d7ce | 3109 | rs6000_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
61a65099 | 3110 | { |
1af5d7ce UW |
3111 | return frame_id_build (get_frame_register_unsigned |
3112 | (this_frame, gdbarch_sp_regnum (gdbarch)), | |
3113 | get_frame_pc (this_frame)); | |
61a65099 KB |
3114 | } |
3115 | ||
3116 | struct rs6000_frame_cache | |
3117 | { | |
3118 | CORE_ADDR base; | |
3119 | CORE_ADDR initial_sp; | |
3120 | struct trad_frame_saved_reg *saved_regs; | |
50ae56ec WW |
3121 | |
3122 | /* Set BASE_P to true if this frame cache is properly initialized. | |
3123 | Otherwise set to false because some registers or memory cannot | |
3124 | collected. */ | |
3125 | int base_p; | |
3126 | /* Cache PC for building unavailable frame. */ | |
3127 | CORE_ADDR pc; | |
61a65099 KB |
3128 | }; |
3129 | ||
3130 | static struct rs6000_frame_cache * | |
1af5d7ce | 3131 | rs6000_frame_cache (struct frame_info *this_frame, void **this_cache) |
61a65099 KB |
3132 | { |
3133 | struct rs6000_frame_cache *cache; | |
1af5d7ce | 3134 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
61a65099 | 3135 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
e17a4113 | 3136 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
61a65099 KB |
3137 | struct rs6000_framedata fdata; |
3138 | int wordsize = tdep->wordsize; | |
338435ef | 3139 | CORE_ADDR func = 0, pc = 0; |
61a65099 KB |
3140 | |
3141 | if ((*this_cache) != NULL) | |
19ba03f4 | 3142 | return (struct rs6000_frame_cache *) (*this_cache); |
61a65099 KB |
3143 | cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache); |
3144 | (*this_cache) = cache; | |
50ae56ec | 3145 | cache->pc = 0; |
1af5d7ce | 3146 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
61a65099 | 3147 | |
50ae56ec WW |
3148 | TRY |
3149 | { | |
3150 | func = get_frame_func (this_frame); | |
3151 | cache->pc = func; | |
3152 | pc = get_frame_pc (this_frame); | |
3153 | skip_prologue (gdbarch, func, pc, &fdata); | |
3154 | ||
3155 | /* Figure out the parent's stack pointer. */ | |
3156 | ||
3157 | /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most | |
3158 | address of the current frame. Things might be easier if the | |
3159 | ->frame pointed to the outer-most address of the frame. In | |
3160 | the mean time, the address of the prev frame is used as the | |
3161 | base address of this frame. */ | |
3162 | cache->base = get_frame_register_unsigned | |
3163 | (this_frame, gdbarch_sp_regnum (gdbarch)); | |
3164 | } | |
3165 | CATCH (ex, RETURN_MASK_ERROR) | |
3166 | { | |
3167 | if (ex.error != NOT_AVAILABLE_ERROR) | |
3168 | throw_exception (ex); | |
1ed0c2a4 | 3169 | return (struct rs6000_frame_cache *) (*this_cache); |
50ae56ec WW |
3170 | } |
3171 | END_CATCH | |
e10b1c4c DJ |
3172 | |
3173 | /* If the function appears to be frameless, check a couple of likely | |
3174 | indicators that we have simply failed to find the frame setup. | |
3175 | Two common cases of this are missing symbols (i.e. | |
ef02daa9 | 3176 | get_frame_func returns the wrong address or 0), and assembly |
e10b1c4c DJ |
3177 | stubs which have a fast exit path but set up a frame on the slow |
3178 | path. | |
3179 | ||
3180 | If the LR appears to return to this function, then presume that | |
3181 | we have an ABI compliant frame that we failed to find. */ | |
3182 | if (fdata.frameless && fdata.lr_offset == 0) | |
61a65099 | 3183 | { |
e10b1c4c DJ |
3184 | CORE_ADDR saved_lr; |
3185 | int make_frame = 0; | |
3186 | ||
1af5d7ce | 3187 | saved_lr = get_frame_register_unsigned (this_frame, tdep->ppc_lr_regnum); |
e10b1c4c DJ |
3188 | if (func == 0 && saved_lr == pc) |
3189 | make_frame = 1; | |
3190 | else if (func != 0) | |
3191 | { | |
3192 | CORE_ADDR saved_func = get_pc_function_start (saved_lr); | |
3193 | if (func == saved_func) | |
3194 | make_frame = 1; | |
3195 | } | |
3196 | ||
3197 | if (make_frame) | |
3198 | { | |
3199 | fdata.frameless = 0; | |
de6a76fd | 3200 | fdata.lr_offset = tdep->lr_frame_offset; |
e10b1c4c | 3201 | } |
61a65099 | 3202 | } |
e10b1c4c DJ |
3203 | |
3204 | if (!fdata.frameless) | |
9d9bf2df EBM |
3205 | { |
3206 | /* Frameless really means stackless. */ | |
cc2c4da8 | 3207 | ULONGEST backchain; |
9d9bf2df | 3208 | |
cc2c4da8 MK |
3209 | if (safe_read_memory_unsigned_integer (cache->base, wordsize, |
3210 | byte_order, &backchain)) | |
9d9bf2df EBM |
3211 | cache->base = (CORE_ADDR) backchain; |
3212 | } | |
e10b1c4c | 3213 | |
3e8c568d | 3214 | trad_frame_set_value (cache->saved_regs, |
8b164abb | 3215 | gdbarch_sp_regnum (gdbarch), cache->base); |
61a65099 KB |
3216 | |
3217 | /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr. | |
3218 | All fpr's from saved_fpr to fp31 are saved. */ | |
3219 | ||
3220 | if (fdata.saved_fpr >= 0) | |
3221 | { | |
3222 | int i; | |
3223 | CORE_ADDR fpr_addr = cache->base + fdata.fpr_offset; | |
383f0f5b JB |
3224 | |
3225 | /* If skip_prologue says floating-point registers were saved, | |
3226 | but the current architecture has no floating-point registers, | |
3227 | then that's strange. But we have no indices to even record | |
3228 | the addresses under, so we just ignore it. */ | |
3229 | if (ppc_floating_point_unit_p (gdbarch)) | |
063715bf | 3230 | for (i = fdata.saved_fpr; i < ppc_num_fprs; i++) |
383f0f5b JB |
3231 | { |
3232 | cache->saved_regs[tdep->ppc_fp0_regnum + i].addr = fpr_addr; | |
3233 | fpr_addr += 8; | |
3234 | } | |
61a65099 KB |
3235 | } |
3236 | ||
3237 | /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr. | |
46a9b8ed DJ |
3238 | All gpr's from saved_gpr to gpr31 are saved (except during the |
3239 | prologue). */ | |
61a65099 KB |
3240 | |
3241 | if (fdata.saved_gpr >= 0) | |
3242 | { | |
3243 | int i; | |
3244 | CORE_ADDR gpr_addr = cache->base + fdata.gpr_offset; | |
063715bf | 3245 | for (i = fdata.saved_gpr; i < ppc_num_gprs; i++) |
61a65099 | 3246 | { |
46a9b8ed DJ |
3247 | if (fdata.gpr_mask & (1U << i)) |
3248 | cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = gpr_addr; | |
61a65099 KB |
3249 | gpr_addr += wordsize; |
3250 | } | |
3251 | } | |
3252 | ||
3253 | /* if != -1, fdata.saved_vr is the smallest number of saved_vr. | |
3254 | All vr's from saved_vr to vr31 are saved. */ | |
3255 | if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) | |
3256 | { | |
3257 | if (fdata.saved_vr >= 0) | |
3258 | { | |
3259 | int i; | |
3260 | CORE_ADDR vr_addr = cache->base + fdata.vr_offset; | |
3261 | for (i = fdata.saved_vr; i < 32; i++) | |
3262 | { | |
3263 | cache->saved_regs[tdep->ppc_vr0_regnum + i].addr = vr_addr; | |
3264 | vr_addr += register_size (gdbarch, tdep->ppc_vr0_regnum); | |
3265 | } | |
3266 | } | |
3267 | } | |
3268 | ||
3269 | /* if != -1, fdata.saved_ev is the smallest number of saved_ev. | |
0df8b418 | 3270 | All vr's from saved_ev to ev31 are saved. ????? */ |
5a9e69ba | 3271 | if (tdep->ppc_ev0_regnum != -1) |
61a65099 KB |
3272 | { |
3273 | if (fdata.saved_ev >= 0) | |
3274 | { | |
3275 | int i; | |
3276 | CORE_ADDR ev_addr = cache->base + fdata.ev_offset; | |
dea80df0 MR |
3277 | CORE_ADDR off = (byte_order == BFD_ENDIAN_BIG ? 4 : 0); |
3278 | ||
063715bf | 3279 | for (i = fdata.saved_ev; i < ppc_num_gprs; i++) |
61a65099 KB |
3280 | { |
3281 | cache->saved_regs[tdep->ppc_ev0_regnum + i].addr = ev_addr; | |
dea80df0 | 3282 | cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + off; |
61a65099 | 3283 | ev_addr += register_size (gdbarch, tdep->ppc_ev0_regnum); |
dea80df0 | 3284 | } |
61a65099 KB |
3285 | } |
3286 | } | |
3287 | ||
3288 | /* If != 0, fdata.cr_offset is the offset from the frame that | |
3289 | holds the CR. */ | |
3290 | if (fdata.cr_offset != 0) | |
0df8b418 MS |
3291 | cache->saved_regs[tdep->ppc_cr_regnum].addr |
3292 | = cache->base + fdata.cr_offset; | |
61a65099 KB |
3293 | |
3294 | /* If != 0, fdata.lr_offset is the offset from the frame that | |
3295 | holds the LR. */ | |
3296 | if (fdata.lr_offset != 0) | |
0df8b418 MS |
3297 | cache->saved_regs[tdep->ppc_lr_regnum].addr |
3298 | = cache->base + fdata.lr_offset; | |
46a9b8ed DJ |
3299 | else if (fdata.lr_register != -1) |
3300 | cache->saved_regs[tdep->ppc_lr_regnum].realreg = fdata.lr_register; | |
61a65099 | 3301 | /* The PC is found in the link register. */ |
8b164abb | 3302 | cache->saved_regs[gdbarch_pc_regnum (gdbarch)] = |
3e8c568d | 3303 | cache->saved_regs[tdep->ppc_lr_regnum]; |
61a65099 KB |
3304 | |
3305 | /* If != 0, fdata.vrsave_offset is the offset from the frame that | |
3306 | holds the VRSAVE. */ | |
3307 | if (fdata.vrsave_offset != 0) | |
0df8b418 MS |
3308 | cache->saved_regs[tdep->ppc_vrsave_regnum].addr |
3309 | = cache->base + fdata.vrsave_offset; | |
61a65099 KB |
3310 | |
3311 | if (fdata.alloca_reg < 0) | |
3312 | /* If no alloca register used, then fi->frame is the value of the | |
3313 | %sp for this frame, and it is good enough. */ | |
1af5d7ce UW |
3314 | cache->initial_sp |
3315 | = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch)); | |
61a65099 | 3316 | else |
1af5d7ce UW |
3317 | cache->initial_sp |
3318 | = get_frame_register_unsigned (this_frame, fdata.alloca_reg); | |
61a65099 | 3319 | |
50ae56ec | 3320 | cache->base_p = 1; |
61a65099 KB |
3321 | return cache; |
3322 | } | |
3323 | ||
3324 | static void | |
1af5d7ce | 3325 | rs6000_frame_this_id (struct frame_info *this_frame, void **this_cache, |
61a65099 KB |
3326 | struct frame_id *this_id) |
3327 | { | |
1af5d7ce | 3328 | struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame, |
61a65099 | 3329 | this_cache); |
50ae56ec WW |
3330 | |
3331 | if (!info->base_p) | |
3332 | { | |
3333 | (*this_id) = frame_id_build_unavailable_stack (info->pc); | |
3334 | return; | |
3335 | } | |
3336 | ||
5b197912 UW |
3337 | /* This marks the outermost frame. */ |
3338 | if (info->base == 0) | |
3339 | return; | |
3340 | ||
1af5d7ce | 3341 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); |
61a65099 KB |
3342 | } |
3343 | ||
1af5d7ce UW |
3344 | static struct value * |
3345 | rs6000_frame_prev_register (struct frame_info *this_frame, | |
3346 | void **this_cache, int regnum) | |
61a65099 | 3347 | { |
1af5d7ce | 3348 | struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame, |
61a65099 | 3349 | this_cache); |
1af5d7ce | 3350 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
61a65099 KB |
3351 | } |
3352 | ||
3353 | static const struct frame_unwind rs6000_frame_unwind = | |
3354 | { | |
3355 | NORMAL_FRAME, | |
8fbca658 | 3356 | default_frame_unwind_stop_reason, |
61a65099 | 3357 | rs6000_frame_this_id, |
1af5d7ce UW |
3358 | rs6000_frame_prev_register, |
3359 | NULL, | |
3360 | default_frame_sniffer | |
61a65099 | 3361 | }; |
2608dbf8 | 3362 | |
ddeca1df WW |
3363 | /* Allocate and initialize a frame cache for an epilogue frame. |
3364 | SP is restored and prev-PC is stored in LR. */ | |
3365 | ||
2608dbf8 WW |
3366 | static struct rs6000_frame_cache * |
3367 | rs6000_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache) | |
3368 | { | |
2608dbf8 WW |
3369 | struct rs6000_frame_cache *cache; |
3370 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
3371 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2608dbf8 WW |
3372 | |
3373 | if (*this_cache) | |
19ba03f4 | 3374 | return (struct rs6000_frame_cache *) *this_cache; |
2608dbf8 WW |
3375 | |
3376 | cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache); | |
3377 | (*this_cache) = cache; | |
3378 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); | |
3379 | ||
492d29ea | 3380 | TRY |
2608dbf8 WW |
3381 | { |
3382 | /* At this point the stack looks as if we just entered the | |
3383 | function, and the return address is stored in LR. */ | |
3384 | CORE_ADDR sp, lr; | |
3385 | ||
3386 | sp = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch)); | |
3387 | lr = get_frame_register_unsigned (this_frame, tdep->ppc_lr_regnum); | |
3388 | ||
3389 | cache->base = sp; | |
3390 | cache->initial_sp = sp; | |
3391 | ||
3392 | trad_frame_set_value (cache->saved_regs, | |
3393 | gdbarch_pc_regnum (gdbarch), lr); | |
3394 | } | |
492d29ea | 3395 | CATCH (ex, RETURN_MASK_ERROR) |
7556d4a4 PA |
3396 | { |
3397 | if (ex.error != NOT_AVAILABLE_ERROR) | |
3398 | throw_exception (ex); | |
3399 | } | |
492d29ea | 3400 | END_CATCH |
2608dbf8 WW |
3401 | |
3402 | return cache; | |
3403 | } | |
3404 | ||
ddeca1df WW |
3405 | /* Implementation of frame_unwind.this_id, as defined in frame_unwind.h. |
3406 | Return the frame ID of an epilogue frame. */ | |
3407 | ||
2608dbf8 WW |
3408 | static void |
3409 | rs6000_epilogue_frame_this_id (struct frame_info *this_frame, | |
3410 | void **this_cache, struct frame_id *this_id) | |
3411 | { | |
3412 | CORE_ADDR pc; | |
3413 | struct rs6000_frame_cache *info = | |
3414 | rs6000_epilogue_frame_cache (this_frame, this_cache); | |
3415 | ||
3416 | pc = get_frame_func (this_frame); | |
3417 | if (info->base == 0) | |
3418 | (*this_id) = frame_id_build_unavailable_stack (pc); | |
3419 | else | |
3420 | (*this_id) = frame_id_build (info->base, pc); | |
3421 | } | |
3422 | ||
ddeca1df WW |
3423 | /* Implementation of frame_unwind.prev_register, as defined in frame_unwind.h. |
3424 | Return the register value of REGNUM in previous frame. */ | |
3425 | ||
2608dbf8 WW |
3426 | static struct value * |
3427 | rs6000_epilogue_frame_prev_register (struct frame_info *this_frame, | |
3428 | void **this_cache, int regnum) | |
3429 | { | |
3430 | struct rs6000_frame_cache *info = | |
3431 | rs6000_epilogue_frame_cache (this_frame, this_cache); | |
3432 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); | |
3433 | } | |
3434 | ||
ddeca1df WW |
3435 | /* Implementation of frame_unwind.sniffer, as defined in frame_unwind.h. |
3436 | Check whether this an epilogue frame. */ | |
3437 | ||
2608dbf8 WW |
3438 | static int |
3439 | rs6000_epilogue_frame_sniffer (const struct frame_unwind *self, | |
3440 | struct frame_info *this_frame, | |
3441 | void **this_prologue_cache) | |
3442 | { | |
3443 | if (frame_relative_level (this_frame) == 0) | |
3444 | return rs6000_in_function_epilogue_frame_p (this_frame, | |
3445 | get_frame_arch (this_frame), | |
3446 | get_frame_pc (this_frame)); | |
3447 | else | |
3448 | return 0; | |
3449 | } | |
3450 | ||
ddeca1df WW |
3451 | /* Frame unwinder for epilogue frame. This is required for reverse step-over |
3452 | a function without debug information. */ | |
3453 | ||
2608dbf8 WW |
3454 | static const struct frame_unwind rs6000_epilogue_frame_unwind = |
3455 | { | |
3456 | NORMAL_FRAME, | |
3457 | default_frame_unwind_stop_reason, | |
3458 | rs6000_epilogue_frame_this_id, rs6000_epilogue_frame_prev_register, | |
3459 | NULL, | |
3460 | rs6000_epilogue_frame_sniffer | |
3461 | }; | |
61a65099 KB |
3462 | \f |
3463 | ||
3464 | static CORE_ADDR | |
1af5d7ce | 3465 | rs6000_frame_base_address (struct frame_info *this_frame, void **this_cache) |
61a65099 | 3466 | { |
1af5d7ce | 3467 | struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame, |
61a65099 KB |
3468 | this_cache); |
3469 | return info->initial_sp; | |
3470 | } | |
3471 | ||
3472 | static const struct frame_base rs6000_frame_base = { | |
3473 | &rs6000_frame_unwind, | |
3474 | rs6000_frame_base_address, | |
3475 | rs6000_frame_base_address, | |
3476 | rs6000_frame_base_address | |
3477 | }; | |
3478 | ||
3479 | static const struct frame_base * | |
1af5d7ce | 3480 | rs6000_frame_base_sniffer (struct frame_info *this_frame) |
61a65099 KB |
3481 | { |
3482 | return &rs6000_frame_base; | |
3483 | } | |
3484 | ||
9274a07c LM |
3485 | /* DWARF-2 frame support. Used to handle the detection of |
3486 | clobbered registers during function calls. */ | |
3487 | ||
3488 | static void | |
3489 | ppc_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
3490 | struct dwarf2_frame_state_reg *reg, | |
4a4e5149 | 3491 | struct frame_info *this_frame) |
9274a07c LM |
3492 | { |
3493 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3494 | ||
3495 | /* PPC32 and PPC64 ABI's are the same regarding volatile and | |
3496 | non-volatile registers. We will use the same code for both. */ | |
3497 | ||
3498 | /* Call-saved GP registers. */ | |
3499 | if ((regnum >= tdep->ppc_gp0_regnum + 14 | |
3500 | && regnum <= tdep->ppc_gp0_regnum + 31) | |
3501 | || (regnum == tdep->ppc_gp0_regnum + 1)) | |
3502 | reg->how = DWARF2_FRAME_REG_SAME_VALUE; | |
3503 | ||
3504 | /* Call-clobbered GP registers. */ | |
3505 | if ((regnum >= tdep->ppc_gp0_regnum + 3 | |
3506 | && regnum <= tdep->ppc_gp0_regnum + 12) | |
3507 | || (regnum == tdep->ppc_gp0_regnum)) | |
3508 | reg->how = DWARF2_FRAME_REG_UNDEFINED; | |
3509 | ||
3510 | /* Deal with FP registers, if supported. */ | |
3511 | if (tdep->ppc_fp0_regnum >= 0) | |
3512 | { | |
3513 | /* Call-saved FP registers. */ | |
3514 | if ((regnum >= tdep->ppc_fp0_regnum + 14 | |
3515 | && regnum <= tdep->ppc_fp0_regnum + 31)) | |
3516 | reg->how = DWARF2_FRAME_REG_SAME_VALUE; | |
3517 | ||
3518 | /* Call-clobbered FP registers. */ | |
3519 | if ((regnum >= tdep->ppc_fp0_regnum | |
3520 | && regnum <= tdep->ppc_fp0_regnum + 13)) | |
3521 | reg->how = DWARF2_FRAME_REG_UNDEFINED; | |
3522 | } | |
3523 | ||
3524 | /* Deal with ALTIVEC registers, if supported. */ | |
3525 | if (tdep->ppc_vr0_regnum > 0 && tdep->ppc_vrsave_regnum > 0) | |
3526 | { | |
3527 | /* Call-saved Altivec registers. */ | |
3528 | if ((regnum >= tdep->ppc_vr0_regnum + 20 | |
3529 | && regnum <= tdep->ppc_vr0_regnum + 31) | |
3530 | || regnum == tdep->ppc_vrsave_regnum) | |
3531 | reg->how = DWARF2_FRAME_REG_SAME_VALUE; | |
3532 | ||
3533 | /* Call-clobbered Altivec registers. */ | |
3534 | if ((regnum >= tdep->ppc_vr0_regnum | |
3535 | && regnum <= tdep->ppc_vr0_regnum + 19)) | |
3536 | reg->how = DWARF2_FRAME_REG_UNDEFINED; | |
3537 | } | |
3538 | ||
3539 | /* Handle PC register and Stack Pointer correctly. */ | |
40a6adc1 | 3540 | if (regnum == gdbarch_pc_regnum (gdbarch)) |
9274a07c | 3541 | reg->how = DWARF2_FRAME_REG_RA; |
40a6adc1 | 3542 | else if (regnum == gdbarch_sp_regnum (gdbarch)) |
9274a07c LM |
3543 | reg->how = DWARF2_FRAME_REG_CFA; |
3544 | } | |
3545 | ||
3546 | ||
74af9197 NF |
3547 | /* Return true if a .gnu_attributes section exists in BFD and it |
3548 | indicates we are using SPE extensions OR if a .PPC.EMB.apuinfo | |
3549 | section exists in BFD and it indicates that SPE extensions are in | |
3550 | use. Check the .gnu.attributes section first, as the binary might be | |
3551 | compiled for SPE, but not actually using SPE instructions. */ | |
3552 | ||
3553 | static int | |
3554 | bfd_uses_spe_extensions (bfd *abfd) | |
3555 | { | |
3556 | asection *sect; | |
3557 | gdb_byte *contents = NULL; | |
3558 | bfd_size_type size; | |
3559 | gdb_byte *ptr; | |
3560 | int success = 0; | |
3561 | int vector_abi; | |
3562 | ||
3563 | if (!abfd) | |
3564 | return 0; | |
3565 | ||
50a99728 | 3566 | #ifdef HAVE_ELF |
74af9197 NF |
3567 | /* Using Tag_GNU_Power_ABI_Vector here is a bit of a hack, as the user |
3568 | could be using the SPE vector abi without actually using any spe | |
3569 | bits whatsoever. But it's close enough for now. */ | |
3570 | vector_abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_GNU, | |
3571 | Tag_GNU_Power_ABI_Vector); | |
3572 | if (vector_abi == 3) | |
3573 | return 1; | |
50a99728 | 3574 | #endif |
74af9197 NF |
3575 | |
3576 | sect = bfd_get_section_by_name (abfd, ".PPC.EMB.apuinfo"); | |
3577 | if (!sect) | |
3578 | return 0; | |
3579 | ||
3580 | size = bfd_get_section_size (sect); | |
224c3ddb | 3581 | contents = (gdb_byte *) xmalloc (size); |
74af9197 NF |
3582 | if (!bfd_get_section_contents (abfd, sect, contents, 0, size)) |
3583 | { | |
3584 | xfree (contents); | |
3585 | return 0; | |
3586 | } | |
3587 | ||
3588 | /* Parse the .PPC.EMB.apuinfo section. The layout is as follows: | |
3589 | ||
3590 | struct { | |
3591 | uint32 name_len; | |
3592 | uint32 data_len; | |
3593 | uint32 type; | |
3594 | char name[name_len rounded up to 4-byte alignment]; | |
3595 | char data[data_len]; | |
3596 | }; | |
3597 | ||
3598 | Technically, there's only supposed to be one such structure in a | |
3599 | given apuinfo section, but the linker is not always vigilant about | |
3600 | merging apuinfo sections from input files. Just go ahead and parse | |
3601 | them all, exiting early when we discover the binary uses SPE | |
3602 | insns. | |
3603 | ||
3604 | It's not specified in what endianness the information in this | |
3605 | section is stored. Assume that it's the endianness of the BFD. */ | |
3606 | ptr = contents; | |
3607 | while (1) | |
3608 | { | |
3609 | unsigned int name_len; | |
3610 | unsigned int data_len; | |
3611 | unsigned int type; | |
3612 | ||
3613 | /* If we can't read the first three fields, we're done. */ | |
3614 | if (size < 12) | |
3615 | break; | |
3616 | ||
3617 | name_len = bfd_get_32 (abfd, ptr); | |
3618 | name_len = (name_len + 3) & ~3U; /* Round to 4 bytes. */ | |
3619 | data_len = bfd_get_32 (abfd, ptr + 4); | |
3620 | type = bfd_get_32 (abfd, ptr + 8); | |
3621 | ptr += 12; | |
3622 | ||
3623 | /* The name must be "APUinfo\0". */ | |
3624 | if (name_len != 8 | |
3625 | && strcmp ((const char *) ptr, "APUinfo") != 0) | |
3626 | break; | |
3627 | ptr += name_len; | |
3628 | ||
3629 | /* The type must be 2. */ | |
3630 | if (type != 2) | |
3631 | break; | |
3632 | ||
3633 | /* The data is stored as a series of uint32. The upper half of | |
3634 | each uint32 indicates the particular APU used and the lower | |
3635 | half indicates the revision of that APU. We just care about | |
3636 | the upper half. */ | |
3637 | ||
3638 | /* Not 4-byte quantities. */ | |
3639 | if (data_len & 3U) | |
3640 | break; | |
3641 | ||
3642 | while (data_len) | |
3643 | { | |
3644 | unsigned int apuinfo = bfd_get_32 (abfd, ptr); | |
3645 | unsigned int apu = apuinfo >> 16; | |
3646 | ptr += 4; | |
3647 | data_len -= 4; | |
3648 | ||
3649 | /* The SPE APU is 0x100; the SPEFP APU is 0x101. Accept | |
3650 | either. */ | |
3651 | if (apu == 0x100 || apu == 0x101) | |
3652 | { | |
3653 | success = 1; | |
3654 | data_len = 0; | |
3655 | } | |
3656 | } | |
3657 | ||
3658 | if (success) | |
3659 | break; | |
3660 | } | |
3661 | ||
3662 | xfree (contents); | |
3663 | return success; | |
3664 | } | |
3665 | ||
b4cdae6f WW |
3666 | /* These are macros for parsing instruction fields (I.1.6.28) */ |
3667 | ||
3668 | #define PPC_FIELD(value, from, len) \ | |
3669 | (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1)) | |
3670 | #define PPC_SEXT(v, bs) \ | |
3671 | ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \ | |
3672 | ^ ((CORE_ADDR) 1 << ((bs) - 1))) \ | |
3673 | - ((CORE_ADDR) 1 << ((bs) - 1))) | |
3674 | #define PPC_OP6(insn) PPC_FIELD (insn, 0, 6) | |
3675 | #define PPC_EXTOP(insn) PPC_FIELD (insn, 21, 10) | |
3676 | #define PPC_RT(insn) PPC_FIELD (insn, 6, 5) | |
3677 | #define PPC_RS(insn) PPC_FIELD (insn, 6, 5) | |
3678 | #define PPC_RA(insn) PPC_FIELD (insn, 11, 5) | |
3679 | #define PPC_RB(insn) PPC_FIELD (insn, 16, 5) | |
3680 | #define PPC_NB(insn) PPC_FIELD (insn, 16, 5) | |
3681 | #define PPC_VRT(insn) PPC_FIELD (insn, 6, 5) | |
3682 | #define PPC_FRT(insn) PPC_FIELD (insn, 6, 5) | |
3683 | #define PPC_SPR(insn) (PPC_FIELD (insn, 11, 5) \ | |
3684 | | (PPC_FIELD (insn, 16, 5) << 5)) | |
3685 | #define PPC_BO(insn) PPC_FIELD (insn, 6, 5) | |
3686 | #define PPC_T(insn) PPC_FIELD (insn, 6, 5) | |
3687 | #define PPC_D(insn) PPC_SEXT (PPC_FIELD (insn, 16, 16), 16) | |
3688 | #define PPC_DS(insn) PPC_SEXT (PPC_FIELD (insn, 16, 14), 14) | |
6ec2b213 | 3689 | #define PPC_DQ(insn) PPC_SEXT (PPC_FIELD (insn, 16, 12), 12) |
b4cdae6f WW |
3690 | #define PPC_BIT(insn,n) ((insn & (1 << (31 - (n)))) ? 1 : 0) |
3691 | #define PPC_OE(insn) PPC_BIT (insn, 21) | |
3692 | #define PPC_RC(insn) PPC_BIT (insn, 31) | |
3693 | #define PPC_Rc(insn) PPC_BIT (insn, 21) | |
3694 | #define PPC_LK(insn) PPC_BIT (insn, 31) | |
3695 | #define PPC_TX(insn) PPC_BIT (insn, 31) | |
3696 | #define PPC_LEV(insn) PPC_FIELD (insn, 20, 7) | |
3697 | ||
3698 | #define PPC_XT(insn) ((PPC_TX (insn) << 5) | PPC_T (insn)) | |
3699 | #define PPC_XER_NB(xer) (xer & 0x7f) | |
3700 | ||
ddeca1df WW |
3701 | /* Record Vector-Scalar Registers. |
3702 | For VSR less than 32, it's represented by an FPR and an VSR-upper register. | |
3703 | Otherwise, it's just a VR register. Record them accordingly. */ | |
b4cdae6f WW |
3704 | |
3705 | static int | |
3706 | ppc_record_vsr (struct regcache *regcache, struct gdbarch_tdep *tdep, int vsr) | |
3707 | { | |
3708 | if (vsr < 0 || vsr >= 64) | |
3709 | return -1; | |
3710 | ||
3711 | if (vsr >= 32) | |
3712 | { | |
3713 | if (tdep->ppc_vr0_regnum >= 0) | |
3714 | record_full_arch_list_add_reg (regcache, tdep->ppc_vr0_regnum + vsr - 32); | |
3715 | } | |
3716 | else | |
3717 | { | |
3718 | if (tdep->ppc_fp0_regnum >= 0) | |
3719 | record_full_arch_list_add_reg (regcache, tdep->ppc_fp0_regnum + vsr); | |
3720 | if (tdep->ppc_vsr0_upper_regnum >= 0) | |
3721 | record_full_arch_list_add_reg (regcache, | |
3722 | tdep->ppc_vsr0_upper_regnum + vsr); | |
3723 | } | |
3724 | ||
3725 | return 0; | |
3726 | } | |
3727 | ||
ddeca1df WW |
3728 | /* Parse and record instructions primary opcode-4 at ADDR. |
3729 | Return 0 if successful. */ | |
b4cdae6f WW |
3730 | |
3731 | static int | |
3732 | ppc_process_record_op4 (struct gdbarch *gdbarch, struct regcache *regcache, | |
ddeca1df | 3733 | CORE_ADDR addr, uint32_t insn) |
b4cdae6f WW |
3734 | { |
3735 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3736 | int ext = PPC_FIELD (insn, 21, 11); | |
6ec2b213 | 3737 | int vra = PPC_FIELD (insn, 11, 5); |
b4cdae6f WW |
3738 | |
3739 | switch (ext & 0x3f) | |
3740 | { | |
3741 | case 32: /* Vector Multiply-High-Add Signed Halfword Saturate */ | |
3742 | case 33: /* Vector Multiply-High-Round-Add Signed Halfword Saturate */ | |
3743 | case 39: /* Vector Multiply-Sum Unsigned Halfword Saturate */ | |
3744 | case 41: /* Vector Multiply-Sum Signed Halfword Saturate */ | |
3745 | record_full_arch_list_add_reg (regcache, PPC_VSCR_REGNUM); | |
3746 | /* FALL-THROUGH */ | |
3747 | case 42: /* Vector Select */ | |
3748 | case 43: /* Vector Permute */ | |
6ec2b213 | 3749 | case 59: /* Vector Permute Right-indexed */ |
b4cdae6f WW |
3750 | case 44: /* Vector Shift Left Double by Octet Immediate */ |
3751 | case 45: /* Vector Permute and Exclusive-OR */ | |
3752 | case 60: /* Vector Add Extended Unsigned Quadword Modulo */ | |
3753 | case 61: /* Vector Add Extended & write Carry Unsigned Quadword */ | |
3754 | case 62: /* Vector Subtract Extended Unsigned Quadword Modulo */ | |
3755 | case 63: /* Vector Subtract Extended & write Carry Unsigned Quadword */ | |
3756 | case 34: /* Vector Multiply-Low-Add Unsigned Halfword Modulo */ | |
6ec2b213 | 3757 | case 35: /* Vector Multiply-Sum Unsigned Doubleword Modulo */ |
b4cdae6f WW |
3758 | case 36: /* Vector Multiply-Sum Unsigned Byte Modulo */ |
3759 | case 37: /* Vector Multiply-Sum Mixed Byte Modulo */ | |
3760 | case 38: /* Vector Multiply-Sum Unsigned Halfword Modulo */ | |
3761 | case 40: /* Vector Multiply-Sum Signed Halfword Modulo */ | |
3762 | case 46: /* Vector Multiply-Add Single-Precision */ | |
3763 | case 47: /* Vector Negative Multiply-Subtract Single-Precision */ | |
3764 | record_full_arch_list_add_reg (regcache, | |
3765 | tdep->ppc_vr0_regnum + PPC_VRT (insn)); | |
3766 | return 0; | |
6ec2b213 EBM |
3767 | |
3768 | case 48: /* Multiply-Add High Doubleword */ | |
3769 | case 49: /* Multiply-Add High Doubleword Unsigned */ | |
3770 | case 51: /* Multiply-Add Low Doubleword */ | |
3771 | record_full_arch_list_add_reg (regcache, | |
3772 | tdep->ppc_gp0_regnum + PPC_RT (insn)); | |
3773 | return 0; | |
b4cdae6f WW |
3774 | } |
3775 | ||
3776 | switch ((ext & 0x1ff)) | |
3777 | { | |
6ec2b213 EBM |
3778 | case 385: |
3779 | if (vra != 0 /* Decimal Convert To Signed Quadword */ | |
3780 | && vra != 2 /* Decimal Convert From Signed Quadword */ | |
3781 | && vra != 4 /* Decimal Convert To Zoned */ | |
3782 | && vra != 5 /* Decimal Convert To National */ | |
3783 | && vra != 6 /* Decimal Convert From Zoned */ | |
3784 | && vra != 7 /* Decimal Convert From National */ | |
3785 | && vra != 31) /* Decimal Set Sign */ | |
3786 | break; | |
e3829d13 | 3787 | /* Fall through. */ |
b4cdae6f WW |
3788 | /* 5.16 Decimal Integer Arithmetic Instructions */ |
3789 | case 1: /* Decimal Add Modulo */ | |
3790 | case 65: /* Decimal Subtract Modulo */ | |
3791 | ||
6ec2b213 EBM |
3792 | case 193: /* Decimal Shift */ |
3793 | case 129: /* Decimal Unsigned Shift */ | |
3794 | case 449: /* Decimal Shift and Round */ | |
3795 | ||
3796 | case 257: /* Decimal Truncate */ | |
3797 | case 321: /* Decimal Unsigned Truncate */ | |
3798 | ||
b4cdae6f WW |
3799 | /* Bit-21 should be set. */ |
3800 | if (!PPC_BIT (insn, 21)) | |
3801 | break; | |
3802 | ||
3803 | record_full_arch_list_add_reg (regcache, | |
3804 | tdep->ppc_vr0_regnum + PPC_VRT (insn)); | |
3805 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
3806 | return 0; | |
3807 | } | |
3808 | ||
3809 | /* Bit-21 is used for RC */ | |
3810 | switch (ext & 0x3ff) | |
3811 | { | |
3812 | case 6: /* Vector Compare Equal To Unsigned Byte */ | |
3813 | case 70: /* Vector Compare Equal To Unsigned Halfword */ | |
3814 | case 134: /* Vector Compare Equal To Unsigned Word */ | |
3815 | case 199: /* Vector Compare Equal To Unsigned Doubleword */ | |
3816 | case 774: /* Vector Compare Greater Than Signed Byte */ | |
3817 | case 838: /* Vector Compare Greater Than Signed Halfword */ | |
3818 | case 902: /* Vector Compare Greater Than Signed Word */ | |
3819 | case 967: /* Vector Compare Greater Than Signed Doubleword */ | |
3820 | case 518: /* Vector Compare Greater Than Unsigned Byte */ | |
3821 | case 646: /* Vector Compare Greater Than Unsigned Word */ | |
3822 | case 582: /* Vector Compare Greater Than Unsigned Halfword */ | |
3823 | case 711: /* Vector Compare Greater Than Unsigned Doubleword */ | |
3824 | case 966: /* Vector Compare Bounds Single-Precision */ | |
3825 | case 198: /* Vector Compare Equal To Single-Precision */ | |
3826 | case 454: /* Vector Compare Greater Than or Equal To Single-Precision */ | |
3827 | case 710: /* Vector Compare Greater Than Single-Precision */ | |
6ec2b213 EBM |
3828 | case 7: /* Vector Compare Not Equal Byte */ |
3829 | case 71: /* Vector Compare Not Equal Halfword */ | |
3830 | case 135: /* Vector Compare Not Equal Word */ | |
3831 | case 263: /* Vector Compare Not Equal or Zero Byte */ | |
3832 | case 327: /* Vector Compare Not Equal or Zero Halfword */ | |
3833 | case 391: /* Vector Compare Not Equal or Zero Word */ | |
b4cdae6f WW |
3834 | if (PPC_Rc (insn)) |
3835 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
3836 | record_full_arch_list_add_reg (regcache, | |
3837 | tdep->ppc_vr0_regnum + PPC_VRT (insn)); | |
3838 | return 0; | |
3839 | } | |
3840 | ||
6ec2b213 EBM |
3841 | if (ext == 1538) |
3842 | { | |
3843 | switch (vra) | |
3844 | { | |
3845 | case 0: /* Vector Count Leading Zero Least-Significant Bits | |
3846 | Byte */ | |
3847 | case 1: /* Vector Count Trailing Zero Least-Significant Bits | |
3848 | Byte */ | |
3849 | record_full_arch_list_add_reg (regcache, | |
3850 | tdep->ppc_gp0_regnum + PPC_RT (insn)); | |
3851 | return 0; | |
3852 | ||
3853 | case 6: /* Vector Negate Word */ | |
3854 | case 7: /* Vector Negate Doubleword */ | |
3855 | case 8: /* Vector Parity Byte Word */ | |
3856 | case 9: /* Vector Parity Byte Doubleword */ | |
3857 | case 10: /* Vector Parity Byte Quadword */ | |
3858 | case 16: /* Vector Extend Sign Byte To Word */ | |
3859 | case 17: /* Vector Extend Sign Halfword To Word */ | |
3860 | case 24: /* Vector Extend Sign Byte To Doubleword */ | |
3861 | case 25: /* Vector Extend Sign Halfword To Doubleword */ | |
3862 | case 26: /* Vector Extend Sign Word To Doubleword */ | |
3863 | case 28: /* Vector Count Trailing Zeros Byte */ | |
3864 | case 29: /* Vector Count Trailing Zeros Halfword */ | |
3865 | case 30: /* Vector Count Trailing Zeros Word */ | |
3866 | case 31: /* Vector Count Trailing Zeros Doubleword */ | |
3867 | record_full_arch_list_add_reg (regcache, | |
3868 | tdep->ppc_vr0_regnum + PPC_VRT (insn)); | |
3869 | return 0; | |
3870 | } | |
3871 | } | |
3872 | ||
b4cdae6f WW |
3873 | switch (ext) |
3874 | { | |
3875 | case 142: /* Vector Pack Unsigned Halfword Unsigned Saturate */ | |
3876 | case 206: /* Vector Pack Unsigned Word Unsigned Saturate */ | |
3877 | case 270: /* Vector Pack Signed Halfword Unsigned Saturate */ | |
3878 | case 334: /* Vector Pack Signed Word Unsigned Saturate */ | |
3879 | case 398: /* Vector Pack Signed Halfword Signed Saturate */ | |
3880 | case 462: /* Vector Pack Signed Word Signed Saturate */ | |
3881 | case 1230: /* Vector Pack Unsigned Doubleword Unsigned Saturate */ | |
3882 | case 1358: /* Vector Pack Signed Doubleword Unsigned Saturate */ | |
3883 | case 1486: /* Vector Pack Signed Doubleword Signed Saturate */ | |
3884 | case 512: /* Vector Add Unsigned Byte Saturate */ | |
3885 | case 576: /* Vector Add Unsigned Halfword Saturate */ | |
3886 | case 640: /* Vector Add Unsigned Word Saturate */ | |
3887 | case 768: /* Vector Add Signed Byte Saturate */ | |
3888 | case 832: /* Vector Add Signed Halfword Saturate */ | |
3889 | case 896: /* Vector Add Signed Word Saturate */ | |
3890 | case 1536: /* Vector Subtract Unsigned Byte Saturate */ | |
3891 | case 1600: /* Vector Subtract Unsigned Halfword Saturate */ | |
3892 | case 1664: /* Vector Subtract Unsigned Word Saturate */ | |
3893 | case 1792: /* Vector Subtract Signed Byte Saturate */ | |
3894 | case 1856: /* Vector Subtract Signed Halfword Saturate */ | |
3895 | case 1920: /* Vector Subtract Signed Word Saturate */ | |
3896 | ||
3897 | case 1544: /* Vector Sum across Quarter Unsigned Byte Saturate */ | |
3898 | case 1800: /* Vector Sum across Quarter Signed Byte Saturate */ | |
3899 | case 1608: /* Vector Sum across Quarter Signed Halfword Saturate */ | |
3900 | case 1672: /* Vector Sum across Half Signed Word Saturate */ | |
3901 | case 1928: /* Vector Sum across Signed Word Saturate */ | |
3902 | case 970: /* Vector Convert To Signed Fixed-Point Word Saturate */ | |
3903 | case 906: /* Vector Convert To Unsigned Fixed-Point Word Saturate */ | |
3904 | record_full_arch_list_add_reg (regcache, PPC_VSCR_REGNUM); | |
3905 | /* FALL-THROUGH */ | |
3906 | case 12: /* Vector Merge High Byte */ | |
3907 | case 14: /* Vector Pack Unsigned Halfword Unsigned Modulo */ | |
3908 | case 76: /* Vector Merge High Halfword */ | |
3909 | case 78: /* Vector Pack Unsigned Word Unsigned Modulo */ | |
3910 | case 140: /* Vector Merge High Word */ | |
3911 | case 268: /* Vector Merge Low Byte */ | |
3912 | case 332: /* Vector Merge Low Halfword */ | |
3913 | case 396: /* Vector Merge Low Word */ | |
3914 | case 526: /* Vector Unpack High Signed Byte */ | |
3915 | case 590: /* Vector Unpack High Signed Halfword */ | |
3916 | case 654: /* Vector Unpack Low Signed Byte */ | |
3917 | case 718: /* Vector Unpack Low Signed Halfword */ | |
3918 | case 782: /* Vector Pack Pixel */ | |
3919 | case 846: /* Vector Unpack High Pixel */ | |
3920 | case 974: /* Vector Unpack Low Pixel */ | |
3921 | case 1102: /* Vector Pack Unsigned Doubleword Unsigned Modulo */ | |
3922 | case 1614: /* Vector Unpack High Signed Word */ | |
3923 | case 1676: /* Vector Merge Odd Word */ | |
3924 | case 1742: /* Vector Unpack Low Signed Word */ | |
3925 | case 1932: /* Vector Merge Even Word */ | |
3926 | case 524: /* Vector Splat Byte */ | |
3927 | case 588: /* Vector Splat Halfword */ | |
3928 | case 652: /* Vector Splat Word */ | |
3929 | case 780: /* Vector Splat Immediate Signed Byte */ | |
3930 | case 844: /* Vector Splat Immediate Signed Halfword */ | |
3931 | case 908: /* Vector Splat Immediate Signed Word */ | |
3932 | case 452: /* Vector Shift Left */ | |
3933 | case 708: /* Vector Shift Right */ | |
3934 | case 1036: /* Vector Shift Left by Octet */ | |
3935 | case 1100: /* Vector Shift Right by Octet */ | |
3936 | case 0: /* Vector Add Unsigned Byte Modulo */ | |
3937 | case 64: /* Vector Add Unsigned Halfword Modulo */ | |
3938 | case 128: /* Vector Add Unsigned Word Modulo */ | |
3939 | case 192: /* Vector Add Unsigned Doubleword Modulo */ | |
3940 | case 256: /* Vector Add Unsigned Quadword Modulo */ | |
3941 | case 320: /* Vector Add & write Carry Unsigned Quadword */ | |
3942 | case 384: /* Vector Add and Write Carry-Out Unsigned Word */ | |
3943 | case 8: /* Vector Multiply Odd Unsigned Byte */ | |
3944 | case 72: /* Vector Multiply Odd Unsigned Halfword */ | |
3945 | case 136: /* Vector Multiply Odd Unsigned Word */ | |
3946 | case 264: /* Vector Multiply Odd Signed Byte */ | |
3947 | case 328: /* Vector Multiply Odd Signed Halfword */ | |
3948 | case 392: /* Vector Multiply Odd Signed Word */ | |
3949 | case 520: /* Vector Multiply Even Unsigned Byte */ | |
3950 | case 584: /* Vector Multiply Even Unsigned Halfword */ | |
3951 | case 648: /* Vector Multiply Even Unsigned Word */ | |
3952 | case 776: /* Vector Multiply Even Signed Byte */ | |
3953 | case 840: /* Vector Multiply Even Signed Halfword */ | |
3954 | case 904: /* Vector Multiply Even Signed Word */ | |
3955 | case 137: /* Vector Multiply Unsigned Word Modulo */ | |
3956 | case 1024: /* Vector Subtract Unsigned Byte Modulo */ | |
3957 | case 1088: /* Vector Subtract Unsigned Halfword Modulo */ | |
3958 | case 1152: /* Vector Subtract Unsigned Word Modulo */ | |
3959 | case 1216: /* Vector Subtract Unsigned Doubleword Modulo */ | |
3960 | case 1280: /* Vector Subtract Unsigned Quadword Modulo */ | |
3961 | case 1344: /* Vector Subtract & write Carry Unsigned Quadword */ | |
3962 | case 1408: /* Vector Subtract and Write Carry-Out Unsigned Word */ | |
3963 | case 1282: /* Vector Average Signed Byte */ | |
3964 | case 1346: /* Vector Average Signed Halfword */ | |
3965 | case 1410: /* Vector Average Signed Word */ | |
3966 | case 1026: /* Vector Average Unsigned Byte */ | |
3967 | case 1090: /* Vector Average Unsigned Halfword */ | |
3968 | case 1154: /* Vector Average Unsigned Word */ | |
3969 | case 258: /* Vector Maximum Signed Byte */ | |
3970 | case 322: /* Vector Maximum Signed Halfword */ | |
3971 | case 386: /* Vector Maximum Signed Word */ | |
3972 | case 450: /* Vector Maximum Signed Doubleword */ | |
3973 | case 2: /* Vector Maximum Unsigned Byte */ | |
3974 | case 66: /* Vector Maximum Unsigned Halfword */ | |
3975 | case 130: /* Vector Maximum Unsigned Word */ | |
3976 | case 194: /* Vector Maximum Unsigned Doubleword */ | |
3977 | case 770: /* Vector Minimum Signed Byte */ | |
3978 | case 834: /* Vector Minimum Signed Halfword */ | |
3979 | case 898: /* Vector Minimum Signed Word */ | |
3980 | case 962: /* Vector Minimum Signed Doubleword */ | |
3981 | case 514: /* Vector Minimum Unsigned Byte */ | |
3982 | case 578: /* Vector Minimum Unsigned Halfword */ | |
3983 | case 642: /* Vector Minimum Unsigned Word */ | |
3984 | case 706: /* Vector Minimum Unsigned Doubleword */ | |
3985 | case 1028: /* Vector Logical AND */ | |
3986 | case 1668: /* Vector Logical Equivalent */ | |
3987 | case 1092: /* Vector Logical AND with Complement */ | |
3988 | case 1412: /* Vector Logical NAND */ | |
3989 | case 1348: /* Vector Logical OR with Complement */ | |
3990 | case 1156: /* Vector Logical OR */ | |
3991 | case 1284: /* Vector Logical NOR */ | |
3992 | case 1220: /* Vector Logical XOR */ | |
3993 | case 4: /* Vector Rotate Left Byte */ | |
3994 | case 132: /* Vector Rotate Left Word VX-form */ | |
3995 | case 68: /* Vector Rotate Left Halfword */ | |
3996 | case 196: /* Vector Rotate Left Doubleword */ | |
3997 | case 260: /* Vector Shift Left Byte */ | |
3998 | case 388: /* Vector Shift Left Word */ | |
3999 | case 324: /* Vector Shift Left Halfword */ | |
4000 | case 1476: /* Vector Shift Left Doubleword */ | |
4001 | case 516: /* Vector Shift Right Byte */ | |
4002 | case 644: /* Vector Shift Right Word */ | |
4003 | case 580: /* Vector Shift Right Halfword */ | |
4004 | case 1732: /* Vector Shift Right Doubleword */ | |
4005 | case 772: /* Vector Shift Right Algebraic Byte */ | |
4006 | case 900: /* Vector Shift Right Algebraic Word */ | |
4007 | case 836: /* Vector Shift Right Algebraic Halfword */ | |
4008 | case 964: /* Vector Shift Right Algebraic Doubleword */ | |
4009 | case 10: /* Vector Add Single-Precision */ | |
4010 | case 74: /* Vector Subtract Single-Precision */ | |
4011 | case 1034: /* Vector Maximum Single-Precision */ | |
4012 | case 1098: /* Vector Minimum Single-Precision */ | |
4013 | case 842: /* Vector Convert From Signed Fixed-Point Word */ | |
4014 | case 778: /* Vector Convert From Unsigned Fixed-Point Word */ | |
4015 | case 714: /* Vector Round to Single-Precision Integer toward -Infinity */ | |
4016 | case 522: /* Vector Round to Single-Precision Integer Nearest */ | |
4017 | case 650: /* Vector Round to Single-Precision Integer toward +Infinity */ | |
4018 | case 586: /* Vector Round to Single-Precision Integer toward Zero */ | |
4019 | case 394: /* Vector 2 Raised to the Exponent Estimate Floating-Point */ | |
4020 | case 458: /* Vector Log Base 2 Estimate Floating-Point */ | |
4021 | case 266: /* Vector Reciprocal Estimate Single-Precision */ | |
4022 | case 330: /* Vector Reciprocal Square Root Estimate Single-Precision */ | |
4023 | case 1288: /* Vector AES Cipher */ | |
4024 | case 1289: /* Vector AES Cipher Last */ | |
4025 | case 1352: /* Vector AES Inverse Cipher */ | |
4026 | case 1353: /* Vector AES Inverse Cipher Last */ | |
4027 | case 1480: /* Vector AES SubBytes */ | |
4028 | case 1730: /* Vector SHA-512 Sigma Doubleword */ | |
4029 | case 1666: /* Vector SHA-256 Sigma Word */ | |
4030 | case 1032: /* Vector Polynomial Multiply-Sum Byte */ | |
4031 | case 1160: /* Vector Polynomial Multiply-Sum Word */ | |
4032 | case 1096: /* Vector Polynomial Multiply-Sum Halfword */ | |
4033 | case 1224: /* Vector Polynomial Multiply-Sum Doubleword */ | |
4034 | case 1292: /* Vector Gather Bits by Bytes by Doubleword */ | |
4035 | case 1794: /* Vector Count Leading Zeros Byte */ | |
4036 | case 1858: /* Vector Count Leading Zeros Halfword */ | |
4037 | case 1922: /* Vector Count Leading Zeros Word */ | |
4038 | case 1986: /* Vector Count Leading Zeros Doubleword */ | |
4039 | case 1795: /* Vector Population Count Byte */ | |
4040 | case 1859: /* Vector Population Count Halfword */ | |
4041 | case 1923: /* Vector Population Count Word */ | |
4042 | case 1987: /* Vector Population Count Doubleword */ | |
4043 | case 1356: /* Vector Bit Permute Quadword */ | |
6ec2b213 EBM |
4044 | case 1484: /* Vector Bit Permute Doubleword */ |
4045 | case 513: /* Vector Multiply-by-10 Unsigned Quadword */ | |
4046 | case 1: /* Vector Multiply-by-10 & write Carry Unsigned | |
4047 | Quadword */ | |
4048 | case 577: /* Vector Multiply-by-10 Extended Unsigned Quadword */ | |
4049 | case 65: /* Vector Multiply-by-10 Extended & write Carry | |
4050 | Unsigned Quadword */ | |
4051 | case 1027: /* Vector Absolute Difference Unsigned Byte */ | |
4052 | case 1091: /* Vector Absolute Difference Unsigned Halfword */ | |
4053 | case 1155: /* Vector Absolute Difference Unsigned Word */ | |
4054 | case 1796: /* Vector Shift Right Variable */ | |
4055 | case 1860: /* Vector Shift Left Variable */ | |
4056 | case 133: /* Vector Rotate Left Word then Mask Insert */ | |
4057 | case 197: /* Vector Rotate Left Doubleword then Mask Insert */ | |
4058 | case 389: /* Vector Rotate Left Word then AND with Mask */ | |
4059 | case 453: /* Vector Rotate Left Doubleword then AND with Mask */ | |
4060 | case 525: /* Vector Extract Unsigned Byte */ | |
4061 | case 589: /* Vector Extract Unsigned Halfword */ | |
4062 | case 653: /* Vector Extract Unsigned Word */ | |
4063 | case 717: /* Vector Extract Doubleword */ | |
4064 | case 781: /* Vector Insert Byte */ | |
4065 | case 845: /* Vector Insert Halfword */ | |
4066 | case 909: /* Vector Insert Word */ | |
4067 | case 973: /* Vector Insert Doubleword */ | |
b4cdae6f WW |
4068 | record_full_arch_list_add_reg (regcache, |
4069 | tdep->ppc_vr0_regnum + PPC_VRT (insn)); | |
4070 | return 0; | |
4071 | ||
6ec2b213 EBM |
4072 | case 1549: /* Vector Extract Unsigned Byte Left-Indexed */ |
4073 | case 1613: /* Vector Extract Unsigned Halfword Left-Indexed */ | |
4074 | case 1677: /* Vector Extract Unsigned Word Left-Indexed */ | |
4075 | case 1805: /* Vector Extract Unsigned Byte Right-Indexed */ | |
4076 | case 1869: /* Vector Extract Unsigned Halfword Right-Indexed */ | |
4077 | case 1933: /* Vector Extract Unsigned Word Right-Indexed */ | |
4078 | record_full_arch_list_add_reg (regcache, | |
4079 | tdep->ppc_gp0_regnum + PPC_RT (insn)); | |
4080 | return 0; | |
4081 | ||
b4cdae6f WW |
4082 | case 1604: /* Move To Vector Status and Control Register */ |
4083 | record_full_arch_list_add_reg (regcache, PPC_VSCR_REGNUM); | |
4084 | return 0; | |
4085 | case 1540: /* Move From Vector Status and Control Register */ | |
4086 | record_full_arch_list_add_reg (regcache, | |
4087 | tdep->ppc_vr0_regnum + PPC_VRT (insn)); | |
4088 | return 0; | |
6ec2b213 EBM |
4089 | case 833: /* Decimal Copy Sign */ |
4090 | record_full_arch_list_add_reg (regcache, | |
4091 | tdep->ppc_vr0_regnum + PPC_VRT (insn)); | |
4092 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
4093 | return 0; | |
b4cdae6f WW |
4094 | } |
4095 | ||
810c1026 WW |
4096 | fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x " |
4097 | "at %s, 4-%d.\n", insn, paddress (gdbarch, addr), ext); | |
b4cdae6f WW |
4098 | return -1; |
4099 | } | |
4100 | ||
ddeca1df WW |
4101 | /* Parse and record instructions of primary opcode-19 at ADDR. |
4102 | Return 0 if successful. */ | |
b4cdae6f WW |
4103 | |
4104 | static int | |
4105 | ppc_process_record_op19 (struct gdbarch *gdbarch, struct regcache *regcache, | |
4106 | CORE_ADDR addr, uint32_t insn) | |
4107 | { | |
4108 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
4109 | int ext = PPC_EXTOP (insn); | |
4110 | ||
6ec2b213 EBM |
4111 | switch (ext & 0x01f) |
4112 | { | |
4113 | case 2: /* Add PC Immediate Shifted */ | |
4114 | record_full_arch_list_add_reg (regcache, | |
4115 | tdep->ppc_gp0_regnum + PPC_RT (insn)); | |
4116 | return 0; | |
4117 | } | |
4118 | ||
b4cdae6f WW |
4119 | switch (ext) |
4120 | { | |
4121 | case 0: /* Move Condition Register Field */ | |
4122 | case 33: /* Condition Register NOR */ | |
4123 | case 129: /* Condition Register AND with Complement */ | |
4124 | case 193: /* Condition Register XOR */ | |
4125 | case 225: /* Condition Register NAND */ | |
4126 | case 257: /* Condition Register AND */ | |
4127 | case 289: /* Condition Register Equivalent */ | |
4128 | case 417: /* Condition Register OR with Complement */ | |
4129 | case 449: /* Condition Register OR */ | |
4130 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
4131 | return 0; | |
4132 | ||
4133 | case 16: /* Branch Conditional */ | |
4134 | case 560: /* Branch Conditional to Branch Target Address Register */ | |
4135 | if ((PPC_BO (insn) & 0x4) == 0) | |
4136 | record_full_arch_list_add_reg (regcache, tdep->ppc_ctr_regnum); | |
4137 | /* FALL-THROUGH */ | |
4138 | case 528: /* Branch Conditional to Count Register */ | |
4139 | if (PPC_LK (insn)) | |
4140 | record_full_arch_list_add_reg (regcache, tdep->ppc_lr_regnum); | |
4141 | return 0; | |
4142 | ||
4143 | case 150: /* Instruction Synchronize */ | |
4144 | /* Do nothing. */ | |
4145 | return 0; | |
4146 | } | |
4147 | ||
810c1026 WW |
4148 | fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x " |
4149 | "at %s, 19-%d.\n", insn, paddress (gdbarch, addr), ext); | |
b4cdae6f WW |
4150 | return -1; |
4151 | } | |
4152 | ||
ddeca1df WW |
4153 | /* Parse and record instructions of primary opcode-31 at ADDR. |
4154 | Return 0 if successful. */ | |
b4cdae6f WW |
4155 | |
4156 | static int | |
4157 | ppc_process_record_op31 (struct gdbarch *gdbarch, struct regcache *regcache, | |
4158 | CORE_ADDR addr, uint32_t insn) | |
4159 | { | |
4160 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
4161 | int ext = PPC_EXTOP (insn); | |
4162 | int tmp, nr, nb, i; | |
4163 | CORE_ADDR at_dcsz, ea = 0; | |
4164 | ULONGEST rb, ra, xer; | |
4165 | int size = 0; | |
4166 | ||
4167 | /* These instructions have OE bit. */ | |
4168 | switch (ext & 0x1ff) | |
4169 | { | |
4170 | /* These write RT and XER. Update CR if RC is set. */ | |
4171 | case 8: /* Subtract from carrying */ | |
4172 | case 10: /* Add carrying */ | |
4173 | case 136: /* Subtract from extended */ | |
4174 | case 138: /* Add extended */ | |
4175 | case 200: /* Subtract from zero extended */ | |
4176 | case 202: /* Add to zero extended */ | |
4177 | case 232: /* Subtract from minus one extended */ | |
4178 | case 234: /* Add to minus one extended */ | |
4179 | /* CA is always altered, but SO/OV are only altered when OE=1. | |
4180 | In any case, XER is always altered. */ | |
4181 | record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum); | |
4182 | if (PPC_RC (insn)) | |
4183 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
4184 | record_full_arch_list_add_reg (regcache, | |
4185 | tdep->ppc_gp0_regnum + PPC_RT (insn)); | |
4186 | return 0; | |
4187 | ||
4188 | /* These write RT. Update CR if RC is set and update XER if OE is set. */ | |
4189 | case 40: /* Subtract from */ | |
4190 | case 104: /* Negate */ | |
4191 | case 233: /* Multiply low doubleword */ | |
4192 | case 235: /* Multiply low word */ | |
4193 | case 266: /* Add */ | |
4194 | case 393: /* Divide Doubleword Extended Unsigned */ | |
4195 | case 395: /* Divide Word Extended Unsigned */ | |
4196 | case 425: /* Divide Doubleword Extended */ | |
4197 | case 427: /* Divide Word Extended */ | |
4198 | case 457: /* Divide Doubleword Unsigned */ | |
4199 | case 459: /* Divide Word Unsigned */ | |
4200 | case 489: /* Divide Doubleword */ | |
4201 | case 491: /* Divide Word */ | |
4202 | if (PPC_OE (insn)) | |
4203 | record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum); | |
4204 | /* FALL-THROUGH */ | |
4205 | case 9: /* Multiply High Doubleword Unsigned */ | |
4206 | case 11: /* Multiply High Word Unsigned */ | |
4207 | case 73: /* Multiply High Doubleword */ | |
4208 | case 75: /* Multiply High Word */ | |
4209 | if (PPC_RC (insn)) | |
4210 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
4211 | record_full_arch_list_add_reg (regcache, | |
4212 | tdep->ppc_gp0_regnum + PPC_RT (insn)); | |
4213 | return 0; | |
4214 | } | |
4215 | ||
4216 | if ((ext & 0x1f) == 15) | |
4217 | { | |
4218 | /* Integer Select. bit[16:20] is used for BC. */ | |
4219 | record_full_arch_list_add_reg (regcache, | |
4220 | tdep->ppc_gp0_regnum + PPC_RT (insn)); | |
4221 | return 0; | |
4222 | } | |
4223 | ||
6ec2b213 EBM |
4224 | if ((ext & 0xff) == 170) |
4225 | { | |
4226 | /* Add Extended using alternate carry bits */ | |
4227 | record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum); | |
4228 | record_full_arch_list_add_reg (regcache, | |
4229 | tdep->ppc_gp0_regnum + PPC_RT (insn)); | |
4230 | return 0; | |
4231 | } | |
4232 | ||
b4cdae6f WW |
4233 | switch (ext) |
4234 | { | |
4235 | case 78: /* Determine Leftmost Zero Byte */ | |
4236 | if (PPC_RC (insn)) | |
4237 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
4238 | record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum); | |
4239 | record_full_arch_list_add_reg (regcache, | |
4240 | tdep->ppc_gp0_regnum + PPC_RT (insn)); | |
4241 | return 0; | |
4242 | ||
4243 | /* These only write RT. */ | |
4244 | case 19: /* Move from condition register */ | |
4245 | /* Move From One Condition Register Field */ | |
4246 | case 74: /* Add and Generate Sixes */ | |
4247 | case 74 | 0x200: /* Add and Generate Sixes (bit-21 dont-care) */ | |
4248 | case 302: /* Move From Branch History Rolling Buffer */ | |
4249 | case 339: /* Move From Special Purpose Register */ | |
4250 | case 371: /* Move From Time Base [Phased-Out] */ | |
6ec2b213 EBM |
4251 | case 309: /* Load Doubleword Monitored Indexed */ |
4252 | case 128: /* Set Boolean */ | |
4253 | case 755: /* Deliver A Random Number */ | |
b4cdae6f WW |
4254 | record_full_arch_list_add_reg (regcache, |
4255 | tdep->ppc_gp0_regnum + PPC_RT (insn)); | |
4256 | return 0; | |
4257 | ||
4258 | /* These only write to RA. */ | |
4259 | case 51: /* Move From VSR Doubleword */ | |
4260 | case 115: /* Move From VSR Word and Zero */ | |
4261 | case 122: /* Population count bytes */ | |
4262 | case 378: /* Population count words */ | |
4263 | case 506: /* Population count doublewords */ | |
4264 | case 154: /* Parity Word */ | |
4265 | case 186: /* Parity Doubleword */ | |
4266 | case 252: /* Bit Permute Doubleword */ | |
4267 | case 282: /* Convert Declets To Binary Coded Decimal */ | |
4268 | case 314: /* Convert Binary Coded Decimal To Declets */ | |
4269 | case 508: /* Compare bytes */ | |
6ec2b213 | 4270 | case 307: /* Move From VSR Lower Doubleword */ |
b4cdae6f WW |
4271 | record_full_arch_list_add_reg (regcache, |
4272 | tdep->ppc_gp0_regnum + PPC_RA (insn)); | |
4273 | return 0; | |
4274 | ||
4275 | /* These write CR and optional RA. */ | |
4276 | case 792: /* Shift Right Algebraic Word */ | |
4277 | case 794: /* Shift Right Algebraic Doubleword */ | |
4278 | case 824: /* Shift Right Algebraic Word Immediate */ | |
4279 | case 826: /* Shift Right Algebraic Doubleword Immediate (413) */ | |
4280 | case 826 | 1: /* Shift Right Algebraic Doubleword Immediate (413) */ | |
4281 | record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum); | |
4282 | record_full_arch_list_add_reg (regcache, | |
4283 | tdep->ppc_gp0_regnum + PPC_RA (insn)); | |
4284 | /* FALL-THROUGH */ | |
4285 | case 0: /* Compare */ | |
4286 | case 32: /* Compare logical */ | |
4287 | case 144: /* Move To Condition Register Fields */ | |
4288 | /* Move To One Condition Register Field */ | |
6ec2b213 EBM |
4289 | case 192: /* Compare Ranged Byte */ |
4290 | case 224: /* Compare Equal Byte */ | |
4291 | case 576: /* Move XER to CR Extended */ | |
4292 | case 902: /* Paste (should always fail due to single-stepping and | |
4293 | the memory location might not be accessible, so | |
4294 | record only CR) */ | |
b4cdae6f WW |
4295 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); |
4296 | return 0; | |
4297 | ||
4298 | /* These write to RT. Update RA if 'update indexed.' */ | |
4299 | case 53: /* Load Doubleword with Update Indexed */ | |
4300 | case 119: /* Load Byte and Zero with Update Indexed */ | |
4301 | case 311: /* Load Halfword and Zero with Update Indexed */ | |
4302 | case 55: /* Load Word and Zero with Update Indexed */ | |
4303 | case 375: /* Load Halfword Algebraic with Update Indexed */ | |
4304 | case 373: /* Load Word Algebraic with Update Indexed */ | |
4305 | record_full_arch_list_add_reg (regcache, | |
4306 | tdep->ppc_gp0_regnum + PPC_RA (insn)); | |
4307 | /* FALL-THROUGH */ | |
4308 | case 21: /* Load Doubleword Indexed */ | |
4309 | case 52: /* Load Byte And Reserve Indexed */ | |
4310 | case 116: /* Load Halfword And Reserve Indexed */ | |
4311 | case 20: /* Load Word And Reserve Indexed */ | |
4312 | case 84: /* Load Doubleword And Reserve Indexed */ | |
4313 | case 87: /* Load Byte and Zero Indexed */ | |
4314 | case 279: /* Load Halfword and Zero Indexed */ | |
4315 | case 23: /* Load Word and Zero Indexed */ | |
4316 | case 343: /* Load Halfword Algebraic Indexed */ | |
4317 | case 341: /* Load Word Algebraic Indexed */ | |
4318 | case 790: /* Load Halfword Byte-Reverse Indexed */ | |
4319 | case 534: /* Load Word Byte-Reverse Indexed */ | |
4320 | case 532: /* Load Doubleword Byte-Reverse Indexed */ | |
6ec2b213 EBM |
4321 | case 582: /* Load Word Atomic */ |
4322 | case 614: /* Load Doubleword Atomic */ | |
4323 | case 265: /* Modulo Unsigned Doubleword */ | |
4324 | case 777: /* Modulo Signed Doubleword */ | |
4325 | case 267: /* Modulo Unsigned Word */ | |
4326 | case 779: /* Modulo Signed Word */ | |
b4cdae6f WW |
4327 | record_full_arch_list_add_reg (regcache, |
4328 | tdep->ppc_gp0_regnum + PPC_RT (insn)); | |
4329 | return 0; | |
4330 | ||
4331 | case 597: /* Load String Word Immediate */ | |
4332 | case 533: /* Load String Word Indexed */ | |
4333 | if (ext == 597) | |
4334 | { | |
4335 | nr = PPC_NB (insn); | |
4336 | if (nr == 0) | |
4337 | nr = 32; | |
4338 | } | |
4339 | else | |
4340 | { | |
4341 | regcache_raw_read_unsigned (regcache, tdep->ppc_xer_regnum, &xer); | |
4342 | nr = PPC_XER_NB (xer); | |
4343 | } | |
4344 | ||
4345 | nr = (nr + 3) >> 2; | |
4346 | ||
4347 | /* If n=0, the contents of register RT are undefined. */ | |
4348 | if (nr == 0) | |
4349 | nr = 1; | |
4350 | ||
4351 | for (i = 0; i < nr; i++) | |
4352 | record_full_arch_list_add_reg (regcache, | |
4353 | tdep->ppc_gp0_regnum | |
4354 | + ((PPC_RT (insn) + i) & 0x1f)); | |
4355 | return 0; | |
4356 | ||
4357 | case 276: /* Load Quadword And Reserve Indexed */ | |
4358 | tmp = tdep->ppc_gp0_regnum + (PPC_RT (insn) & ~1); | |
4359 | record_full_arch_list_add_reg (regcache, tmp); | |
4360 | record_full_arch_list_add_reg (regcache, tmp + 1); | |
4361 | return 0; | |
4362 | ||
4363 | /* These write VRT. */ | |
4364 | case 6: /* Load Vector for Shift Left Indexed */ | |
4365 | case 38: /* Load Vector for Shift Right Indexed */ | |
4366 | case 7: /* Load Vector Element Byte Indexed */ | |
4367 | case 39: /* Load Vector Element Halfword Indexed */ | |
4368 | case 71: /* Load Vector Element Word Indexed */ | |
4369 | case 103: /* Load Vector Indexed */ | |
4370 | case 359: /* Load Vector Indexed LRU */ | |
4371 | record_full_arch_list_add_reg (regcache, | |
4372 | tdep->ppc_vr0_regnum + PPC_VRT (insn)); | |
4373 | return 0; | |
4374 | ||
4375 | /* These write FRT. Update RA if 'update indexed.' */ | |
4376 | case 567: /* Load Floating-Point Single with Update Indexed */ | |
4377 | case 631: /* Load Floating-Point Double with Update Indexed */ | |
4378 | record_full_arch_list_add_reg (regcache, | |
4379 | tdep->ppc_gp0_regnum + PPC_RA (insn)); | |
4380 | /* FALL-THROUGH */ | |
4381 | case 535: /* Load Floating-Point Single Indexed */ | |
4382 | case 599: /* Load Floating-Point Double Indexed */ | |
4383 | case 855: /* Load Floating-Point as Integer Word Algebraic Indexed */ | |
4384 | case 887: /* Load Floating-Point as Integer Word and Zero Indexed */ | |
4385 | record_full_arch_list_add_reg (regcache, | |
4386 | tdep->ppc_fp0_regnum + PPC_FRT (insn)); | |
4387 | return 0; | |
4388 | ||
4389 | case 791: /* Load Floating-Point Double Pair Indexed */ | |
4390 | tmp = tdep->ppc_fp0_regnum + (PPC_FRT (insn) & ~1); | |
4391 | record_full_arch_list_add_reg (regcache, tmp); | |
4392 | record_full_arch_list_add_reg (regcache, tmp + 1); | |
4393 | return 0; | |
4394 | ||
4395 | case 179: /* Move To VSR Doubleword */ | |
4396 | case 211: /* Move To VSR Word Algebraic */ | |
4397 | case 243: /* Move To VSR Word and Zero */ | |
4398 | case 588: /* Load VSX Scalar Doubleword Indexed */ | |
4399 | case 524: /* Load VSX Scalar Single-Precision Indexed */ | |
4400 | case 76: /* Load VSX Scalar as Integer Word Algebraic Indexed */ | |
4401 | case 12: /* Load VSX Scalar as Integer Word and Zero Indexed */ | |
4402 | case 844: /* Load VSX Vector Doubleword*2 Indexed */ | |
4403 | case 332: /* Load VSX Vector Doubleword & Splat Indexed */ | |
4404 | case 780: /* Load VSX Vector Word*4 Indexed */ | |
6ec2b213 EBM |
4405 | case 268: /* Load VSX Vector Indexed */ |
4406 | case 364: /* Load VSX Vector Word & Splat Indexed */ | |
4407 | case 812: /* Load VSX Vector Halfword*8 Indexed */ | |
4408 | case 876: /* Load VSX Vector Byte*16 Indexed */ | |
4409 | case 269: /* Load VSX Vector with Length */ | |
4410 | case 301: /* Load VSX Vector Left-justified with Length */ | |
4411 | case 781: /* Load VSX Scalar as Integer Byte & Zero Indexed */ | |
4412 | case 813: /* Load VSX Scalar as Integer Halfword & Zero Indexed */ | |
4413 | case 403: /* Move To VSR Word & Splat */ | |
4414 | case 435: /* Move To VSR Double Doubleword */ | |
b4cdae6f WW |
4415 | ppc_record_vsr (regcache, tdep, PPC_XT (insn)); |
4416 | return 0; | |
4417 | ||
4418 | /* These write RA. Update CR if RC is set. */ | |
4419 | case 24: /* Shift Left Word */ | |
4420 | case 26: /* Count Leading Zeros Word */ | |
4421 | case 27: /* Shift Left Doubleword */ | |
4422 | case 28: /* AND */ | |
4423 | case 58: /* Count Leading Zeros Doubleword */ | |
4424 | case 60: /* AND with Complement */ | |
4425 | case 124: /* NOR */ | |
4426 | case 284: /* Equivalent */ | |
4427 | case 316: /* XOR */ | |
4428 | case 476: /* NAND */ | |
4429 | case 412: /* OR with Complement */ | |
4430 | case 444: /* OR */ | |
4431 | case 536: /* Shift Right Word */ | |
4432 | case 539: /* Shift Right Doubleword */ | |
4433 | case 922: /* Extend Sign Halfword */ | |
4434 | case 954: /* Extend Sign Byte */ | |
4435 | case 986: /* Extend Sign Word */ | |
6ec2b213 EBM |
4436 | case 538: /* Count Trailing Zeros Word */ |
4437 | case 570: /* Count Trailing Zeros Doubleword */ | |
4438 | case 890: /* Extend-Sign Word and Shift Left Immediate (445) */ | |
4439 | case 890 | 1: /* Extend-Sign Word and Shift Left Immediate (445) */ | |
b4cdae6f WW |
4440 | if (PPC_RC (insn)) |
4441 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
4442 | record_full_arch_list_add_reg (regcache, | |
4443 | tdep->ppc_gp0_regnum + PPC_RA (insn)); | |
4444 | return 0; | |
4445 | ||
4446 | /* Store memory. */ | |
4447 | case 181: /* Store Doubleword with Update Indexed */ | |
4448 | case 183: /* Store Word with Update Indexed */ | |
4449 | case 247: /* Store Byte with Update Indexed */ | |
4450 | case 439: /* Store Half Word with Update Indexed */ | |
4451 | case 695: /* Store Floating-Point Single with Update Indexed */ | |
4452 | case 759: /* Store Floating-Point Double with Update Indexed */ | |
4453 | record_full_arch_list_add_reg (regcache, | |
4454 | tdep->ppc_gp0_regnum + PPC_RA (insn)); | |
4455 | /* FALL-THROUGH */ | |
4456 | case 135: /* Store Vector Element Byte Indexed */ | |
4457 | case 167: /* Store Vector Element Halfword Indexed */ | |
4458 | case 199: /* Store Vector Element Word Indexed */ | |
4459 | case 231: /* Store Vector Indexed */ | |
4460 | case 487: /* Store Vector Indexed LRU */ | |
4461 | case 716: /* Store VSX Scalar Doubleword Indexed */ | |
4462 | case 140: /* Store VSX Scalar as Integer Word Indexed */ | |
4463 | case 652: /* Store VSX Scalar Single-Precision Indexed */ | |
4464 | case 972: /* Store VSX Vector Doubleword*2 Indexed */ | |
4465 | case 908: /* Store VSX Vector Word*4 Indexed */ | |
4466 | case 149: /* Store Doubleword Indexed */ | |
4467 | case 151: /* Store Word Indexed */ | |
4468 | case 215: /* Store Byte Indexed */ | |
4469 | case 407: /* Store Half Word Indexed */ | |
4470 | case 694: /* Store Byte Conditional Indexed */ | |
4471 | case 726: /* Store Halfword Conditional Indexed */ | |
4472 | case 150: /* Store Word Conditional Indexed */ | |
4473 | case 214: /* Store Doubleword Conditional Indexed */ | |
4474 | case 182: /* Store Quadword Conditional Indexed */ | |
4475 | case 662: /* Store Word Byte-Reverse Indexed */ | |
4476 | case 918: /* Store Halfword Byte-Reverse Indexed */ | |
4477 | case 660: /* Store Doubleword Byte-Reverse Indexed */ | |
4478 | case 663: /* Store Floating-Point Single Indexed */ | |
4479 | case 727: /* Store Floating-Point Double Indexed */ | |
4480 | case 919: /* Store Floating-Point Double Pair Indexed */ | |
4481 | case 983: /* Store Floating-Point as Integer Word Indexed */ | |
6ec2b213 EBM |
4482 | case 396: /* Store VSX Vector Indexed */ |
4483 | case 940: /* Store VSX Vector Halfword*8 Indexed */ | |
4484 | case 1004: /* Store VSX Vector Byte*16 Indexed */ | |
4485 | case 909: /* Store VSX Scalar as Integer Byte Indexed */ | |
4486 | case 941: /* Store VSX Scalar as Integer Halfword Indexed */ | |
b4cdae6f WW |
4487 | if (ext == 694 || ext == 726 || ext == 150 || ext == 214 || ext == 182) |
4488 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
4489 | ||
4490 | ra = 0; | |
4491 | if (PPC_RA (insn) != 0) | |
4492 | regcache_raw_read_unsigned (regcache, | |
4493 | tdep->ppc_gp0_regnum + PPC_RA (insn), &ra); | |
4494 | regcache_raw_read_unsigned (regcache, | |
4495 | tdep->ppc_gp0_regnum + PPC_RB (insn), &rb); | |
4496 | ea = ra + rb; | |
4497 | ||
4498 | switch (ext) | |
4499 | { | |
4500 | case 183: /* Store Word with Update Indexed */ | |
4501 | case 199: /* Store Vector Element Word Indexed */ | |
4502 | case 140: /* Store VSX Scalar as Integer Word Indexed */ | |
4503 | case 652: /* Store VSX Scalar Single-Precision Indexed */ | |
4504 | case 151: /* Store Word Indexed */ | |
4505 | case 150: /* Store Word Conditional Indexed */ | |
4506 | case 662: /* Store Word Byte-Reverse Indexed */ | |
4507 | case 663: /* Store Floating-Point Single Indexed */ | |
4508 | case 695: /* Store Floating-Point Single with Update Indexed */ | |
4509 | case 983: /* Store Floating-Point as Integer Word Indexed */ | |
4510 | size = 4; | |
4511 | break; | |
4512 | case 247: /* Store Byte with Update Indexed */ | |
4513 | case 135: /* Store Vector Element Byte Indexed */ | |
4514 | case 215: /* Store Byte Indexed */ | |
4515 | case 694: /* Store Byte Conditional Indexed */ | |
6ec2b213 | 4516 | case 909: /* Store VSX Scalar as Integer Byte Indexed */ |
b4cdae6f WW |
4517 | size = 1; |
4518 | break; | |
4519 | case 439: /* Store Halfword with Update Indexed */ | |
4520 | case 167: /* Store Vector Element Halfword Indexed */ | |
4521 | case 407: /* Store Halfword Indexed */ | |
4522 | case 726: /* Store Halfword Conditional Indexed */ | |
4523 | case 918: /* Store Halfword Byte-Reverse Indexed */ | |
6ec2b213 | 4524 | case 941: /* Store VSX Scalar as Integer Halfword Indexed */ |
b4cdae6f WW |
4525 | size = 2; |
4526 | break; | |
4527 | case 181: /* Store Doubleword with Update Indexed */ | |
4528 | case 716: /* Store VSX Scalar Doubleword Indexed */ | |
4529 | case 149: /* Store Doubleword Indexed */ | |
4530 | case 214: /* Store Doubleword Conditional Indexed */ | |
4531 | case 660: /* Store Doubleword Byte-Reverse Indexed */ | |
4532 | case 727: /* Store Floating-Point Double Indexed */ | |
4533 | case 759: /* Store Floating-Point Double with Update Indexed */ | |
4534 | size = 8; | |
4535 | break; | |
4536 | case 972: /* Store VSX Vector Doubleword*2 Indexed */ | |
4537 | case 908: /* Store VSX Vector Word*4 Indexed */ | |
4538 | case 182: /* Store Quadword Conditional Indexed */ | |
4539 | case 231: /* Store Vector Indexed */ | |
4540 | case 487: /* Store Vector Indexed LRU */ | |
4541 | case 919: /* Store Floating-Point Double Pair Indexed */ | |
6ec2b213 EBM |
4542 | case 396: /* Store VSX Vector Indexed */ |
4543 | case 940: /* Store VSX Vector Halfword*8 Indexed */ | |
4544 | case 1004: /* Store VSX Vector Byte*16 Indexed */ | |
b4cdae6f WW |
4545 | size = 16; |
4546 | break; | |
4547 | default: | |
4548 | gdb_assert (0); | |
4549 | } | |
4550 | ||
4551 | /* Align address for Store Vector instructions. */ | |
4552 | switch (ext) | |
4553 | { | |
4554 | case 167: /* Store Vector Element Halfword Indexed */ | |
4555 | addr = addr & ~0x1ULL; | |
4556 | break; | |
4557 | ||
4558 | case 199: /* Store Vector Element Word Indexed */ | |
4559 | addr = addr & ~0x3ULL; | |
4560 | break; | |
4561 | ||
4562 | case 231: /* Store Vector Indexed */ | |
4563 | case 487: /* Store Vector Indexed LRU */ | |
4564 | addr = addr & ~0xfULL; | |
4565 | break; | |
4566 | } | |
4567 | ||
4568 | record_full_arch_list_add_mem (addr, size); | |
4569 | return 0; | |
4570 | ||
6ec2b213 EBM |
4571 | case 397: /* Store VSX Vector with Length */ |
4572 | case 429: /* Store VSX Vector Left-justified with Length */ | |
de678454 | 4573 | ra = 0; |
6ec2b213 EBM |
4574 | if (PPC_RA (insn) != 0) |
4575 | regcache_raw_read_unsigned (regcache, | |
de678454 EBM |
4576 | tdep->ppc_gp0_regnum + PPC_RA (insn), &ra); |
4577 | ea = ra; | |
6ec2b213 EBM |
4578 | regcache_raw_read_unsigned (regcache, |
4579 | tdep->ppc_gp0_regnum + PPC_RB (insn), &rb); | |
4580 | /* Store up to 16 bytes. */ | |
4581 | nb = (rb & 0xff) > 16 ? 16 : (rb & 0xff); | |
4582 | if (nb > 0) | |
4583 | record_full_arch_list_add_mem (ea, nb); | |
4584 | return 0; | |
4585 | ||
4586 | case 710: /* Store Word Atomic */ | |
4587 | case 742: /* Store Doubleword Atomic */ | |
de678454 | 4588 | ra = 0; |
6ec2b213 EBM |
4589 | if (PPC_RA (insn) != 0) |
4590 | regcache_raw_read_unsigned (regcache, | |
de678454 EBM |
4591 | tdep->ppc_gp0_regnum + PPC_RA (insn), &ra); |
4592 | ea = ra; | |
6ec2b213 EBM |
4593 | switch (ext) |
4594 | { | |
4595 | case 710: /* Store Word Atomic */ | |
4596 | size = 8; | |
4597 | break; | |
4598 | case 742: /* Store Doubleword Atomic */ | |
4599 | size = 16; | |
4600 | break; | |
4601 | default: | |
4602 | gdb_assert (0); | |
4603 | } | |
4604 | record_full_arch_list_add_mem (ea, size); | |
4605 | return 0; | |
4606 | ||
b4cdae6f WW |
4607 | case 725: /* Store String Word Immediate */ |
4608 | ra = 0; | |
4609 | if (PPC_RA (insn) != 0) | |
9f7efd5b EBM |
4610 | regcache_raw_read_unsigned (regcache, |
4611 | tdep->ppc_gp0_regnum + PPC_RA (insn), &ra); | |
b4cdae6f WW |
4612 | ea += ra; |
4613 | ||
4614 | nb = PPC_NB (insn); | |
4615 | if (nb == 0) | |
4616 | nb = 32; | |
4617 | ||
4618 | record_full_arch_list_add_mem (ea, nb); | |
4619 | ||
4620 | return 0; | |
4621 | ||
4622 | case 661: /* Store String Word Indexed */ | |
4623 | ra = 0; | |
4624 | if (PPC_RA (insn) != 0) | |
9f7efd5b EBM |
4625 | regcache_raw_read_unsigned (regcache, |
4626 | tdep->ppc_gp0_regnum + PPC_RA (insn), &ra); | |
b4cdae6f WW |
4627 | ea += ra; |
4628 | ||
4629 | regcache_raw_read_unsigned (regcache, tdep->ppc_xer_regnum, &xer); | |
4630 | nb = PPC_XER_NB (xer); | |
4631 | ||
4632 | if (nb != 0) | |
4633 | { | |
9f7efd5b EBM |
4634 | regcache_raw_read_unsigned (regcache, |
4635 | tdep->ppc_gp0_regnum + PPC_RB (insn), | |
4636 | &rb); | |
b4cdae6f WW |
4637 | ea += rb; |
4638 | record_full_arch_list_add_mem (ea, nb); | |
4639 | } | |
4640 | ||
4641 | return 0; | |
4642 | ||
4643 | case 467: /* Move To Special Purpose Register */ | |
4644 | switch (PPC_SPR (insn)) | |
4645 | { | |
4646 | case 1: /* XER */ | |
4647 | record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum); | |
4648 | return 0; | |
4649 | case 8: /* LR */ | |
4650 | record_full_arch_list_add_reg (regcache, tdep->ppc_lr_regnum); | |
4651 | return 0; | |
4652 | case 9: /* CTR */ | |
4653 | record_full_arch_list_add_reg (regcache, tdep->ppc_ctr_regnum); | |
4654 | return 0; | |
4655 | case 256: /* VRSAVE */ | |
4656 | record_full_arch_list_add_reg (regcache, tdep->ppc_vrsave_regnum); | |
4657 | return 0; | |
4658 | } | |
4659 | ||
4660 | goto UNKNOWN_OP; | |
4661 | ||
4662 | case 147: /* Move To Split Little Endian */ | |
4663 | record_full_arch_list_add_reg (regcache, tdep->ppc_ps_regnum); | |
4664 | return 0; | |
4665 | ||
4666 | case 512: /* Move to Condition Register from XER */ | |
4667 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
4668 | record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum); | |
4669 | return 0; | |
4670 | ||
4671 | case 4: /* Trap Word */ | |
4672 | case 68: /* Trap Doubleword */ | |
4673 | case 430: /* Clear BHRB */ | |
4674 | case 598: /* Synchronize */ | |
4675 | case 62: /* Wait for Interrupt */ | |
6ec2b213 | 4676 | case 30: /* Wait */ |
b4cdae6f WW |
4677 | case 22: /* Instruction Cache Block Touch */ |
4678 | case 854: /* Enforce In-order Execution of I/O */ | |
4679 | case 246: /* Data Cache Block Touch for Store */ | |
4680 | case 54: /* Data Cache Block Store */ | |
4681 | case 86: /* Data Cache Block Flush */ | |
4682 | case 278: /* Data Cache Block Touch */ | |
4683 | case 758: /* Data Cache Block Allocate */ | |
4684 | case 982: /* Instruction Cache Block Invalidate */ | |
6ec2b213 EBM |
4685 | case 774: /* Copy */ |
4686 | case 838: /* CP_Abort */ | |
b4cdae6f WW |
4687 | return 0; |
4688 | ||
4689 | case 654: /* Transaction Begin */ | |
4690 | case 686: /* Transaction End */ | |
b4cdae6f WW |
4691 | case 750: /* Transaction Suspend or Resume */ |
4692 | case 782: /* Transaction Abort Word Conditional */ | |
4693 | case 814: /* Transaction Abort Doubleword Conditional */ | |
4694 | case 846: /* Transaction Abort Word Conditional Immediate */ | |
4695 | case 878: /* Transaction Abort Doubleword Conditional Immediate */ | |
4696 | case 910: /* Transaction Abort */ | |
d44c67f3 EBM |
4697 | record_full_arch_list_add_reg (regcache, tdep->ppc_ps_regnum); |
4698 | /* FALL-THROUGH */ | |
4699 | case 718: /* Transaction Check */ | |
4700 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
4701 | return 0; | |
b4cdae6f WW |
4702 | |
4703 | case 1014: /* Data Cache Block set to Zero */ | |
f6ac5f3d | 4704 | if (target_auxv_search (target_stack, AT_DCACHEBSIZE, &at_dcsz) <= 0 |
b4cdae6f WW |
4705 | || at_dcsz == 0) |
4706 | at_dcsz = 128; /* Assume 128-byte cache line size (POWER8) */ | |
4707 | ||
bec734b2 | 4708 | ra = 0; |
b4cdae6f WW |
4709 | if (PPC_RA (insn) != 0) |
4710 | regcache_raw_read_unsigned (regcache, | |
4711 | tdep->ppc_gp0_regnum + PPC_RA (insn), &ra); | |
4712 | regcache_raw_read_unsigned (regcache, | |
4713 | tdep->ppc_gp0_regnum + PPC_RB (insn), &rb); | |
4714 | ea = (ra + rb) & ~((ULONGEST) (at_dcsz - 1)); | |
4715 | record_full_arch_list_add_mem (ea, at_dcsz); | |
4716 | return 0; | |
4717 | } | |
4718 | ||
4719 | UNKNOWN_OP: | |
810c1026 WW |
4720 | fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x " |
4721 | "at %s, 31-%d.\n", insn, paddress (gdbarch, addr), ext); | |
b4cdae6f WW |
4722 | return -1; |
4723 | } | |
4724 | ||
ddeca1df WW |
4725 | /* Parse and record instructions of primary opcode-59 at ADDR. |
4726 | Return 0 if successful. */ | |
b4cdae6f WW |
4727 | |
4728 | static int | |
4729 | ppc_process_record_op59 (struct gdbarch *gdbarch, struct regcache *regcache, | |
4730 | CORE_ADDR addr, uint32_t insn) | |
4731 | { | |
4732 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
4733 | int ext = PPC_EXTOP (insn); | |
4734 | ||
4735 | switch (ext & 0x1f) | |
4736 | { | |
4737 | case 18: /* Floating Divide */ | |
4738 | case 20: /* Floating Subtract */ | |
4739 | case 21: /* Floating Add */ | |
4740 | case 22: /* Floating Square Root */ | |
4741 | case 24: /* Floating Reciprocal Estimate */ | |
4742 | case 25: /* Floating Multiply */ | |
4743 | case 26: /* Floating Reciprocal Square Root Estimate */ | |
4744 | case 28: /* Floating Multiply-Subtract */ | |
4745 | case 29: /* Floating Multiply-Add */ | |
4746 | case 30: /* Floating Negative Multiply-Subtract */ | |
4747 | case 31: /* Floating Negative Multiply-Add */ | |
4748 | record_full_arch_list_add_reg (regcache, | |
4749 | tdep->ppc_fp0_regnum + PPC_FRT (insn)); | |
4750 | if (PPC_RC (insn)) | |
4751 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
4752 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
4753 | ||
4754 | return 0; | |
4755 | } | |
4756 | ||
4757 | switch (ext) | |
4758 | { | |
4759 | case 2: /* DFP Add */ | |
4760 | case 3: /* DFP Quantize */ | |
4761 | case 34: /* DFP Multiply */ | |
4762 | case 35: /* DFP Reround */ | |
4763 | case 67: /* DFP Quantize Immediate */ | |
4764 | case 99: /* DFP Round To FP Integer With Inexact */ | |
4765 | case 227: /* DFP Round To FP Integer Without Inexact */ | |
4766 | case 258: /* DFP Convert To DFP Long! */ | |
4767 | case 290: /* DFP Convert To Fixed */ | |
4768 | case 514: /* DFP Subtract */ | |
4769 | case 546: /* DFP Divide */ | |
4770 | case 770: /* DFP Round To DFP Short! */ | |
4771 | case 802: /* DFP Convert From Fixed */ | |
4772 | case 834: /* DFP Encode BCD To DPD */ | |
4773 | if (PPC_RC (insn)) | |
4774 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
4775 | record_full_arch_list_add_reg (regcache, | |
4776 | tdep->ppc_fp0_regnum + PPC_FRT (insn)); | |
4777 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
4778 | return 0; | |
4779 | ||
4780 | case 130: /* DFP Compare Ordered */ | |
4781 | case 162: /* DFP Test Exponent */ | |
4782 | case 194: /* DFP Test Data Class */ | |
4783 | case 226: /* DFP Test Data Group */ | |
4784 | case 642: /* DFP Compare Unordered */ | |
4785 | case 674: /* DFP Test Significance */ | |
6ec2b213 | 4786 | case 675: /* DFP Test Significance Immediate */ |
b4cdae6f WW |
4787 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); |
4788 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
4789 | return 0; | |
4790 | ||
4791 | case 66: /* DFP Shift Significand Left Immediate */ | |
4792 | case 98: /* DFP Shift Significand Right Immediate */ | |
4793 | case 322: /* DFP Decode DPD To BCD */ | |
4794 | case 354: /* DFP Extract Biased Exponent */ | |
4795 | case 866: /* DFP Insert Biased Exponent */ | |
4796 | record_full_arch_list_add_reg (regcache, | |
4797 | tdep->ppc_fp0_regnum + PPC_FRT (insn)); | |
4798 | if (PPC_RC (insn)) | |
4799 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
4800 | return 0; | |
4801 | ||
4802 | case 846: /* Floating Convert From Integer Doubleword Single */ | |
4803 | case 974: /* Floating Convert From Integer Doubleword Unsigned | |
4804 | Single */ | |
4805 | record_full_arch_list_add_reg (regcache, | |
4806 | tdep->ppc_fp0_regnum + PPC_FRT (insn)); | |
4807 | if (PPC_RC (insn)) | |
4808 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
4809 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
4810 | ||
4811 | return 0; | |
4812 | } | |
4813 | ||
810c1026 WW |
4814 | fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x " |
4815 | "at %s, 59-%d.\n", insn, paddress (gdbarch, addr), ext); | |
b4cdae6f WW |
4816 | return -1; |
4817 | } | |
4818 | ||
ddeca1df WW |
4819 | /* Parse and record instructions of primary opcode-60 at ADDR. |
4820 | Return 0 if successful. */ | |
b4cdae6f WW |
4821 | |
4822 | static int | |
4823 | ppc_process_record_op60 (struct gdbarch *gdbarch, struct regcache *regcache, | |
4824 | CORE_ADDR addr, uint32_t insn) | |
4825 | { | |
4826 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
4827 | int ext = PPC_EXTOP (insn); | |
b4cdae6f WW |
4828 | |
4829 | switch (ext >> 2) | |
4830 | { | |
4831 | case 0: /* VSX Scalar Add Single-Precision */ | |
4832 | case 32: /* VSX Scalar Add Double-Precision */ | |
4833 | case 24: /* VSX Scalar Divide Single-Precision */ | |
4834 | case 56: /* VSX Scalar Divide Double-Precision */ | |
4835 | case 176: /* VSX Scalar Copy Sign Double-Precision */ | |
4836 | case 33: /* VSX Scalar Multiply-Add Double-Precision */ | |
4837 | case 41: /* ditto */ | |
4838 | case 1: /* VSX Scalar Multiply-Add Single-Precision */ | |
4839 | case 9: /* ditto */ | |
4840 | case 160: /* VSX Scalar Maximum Double-Precision */ | |
4841 | case 168: /* VSX Scalar Minimum Double-Precision */ | |
4842 | case 49: /* VSX Scalar Multiply-Subtract Double-Precision */ | |
4843 | case 57: /* ditto */ | |
4844 | case 17: /* VSX Scalar Multiply-Subtract Single-Precision */ | |
4845 | case 25: /* ditto */ | |
4846 | case 48: /* VSX Scalar Multiply Double-Precision */ | |
4847 | case 16: /* VSX Scalar Multiply Single-Precision */ | |
4848 | case 161: /* VSX Scalar Negative Multiply-Add Double-Precision */ | |
4849 | case 169: /* ditto */ | |
4850 | case 129: /* VSX Scalar Negative Multiply-Add Single-Precision */ | |
4851 | case 137: /* ditto */ | |
4852 | case 177: /* VSX Scalar Negative Multiply-Subtract Double-Precision */ | |
4853 | case 185: /* ditto */ | |
4854 | case 145: /* VSX Scalar Negative Multiply-Subtract Single-Precision */ | |
4855 | case 153: /* ditto */ | |
4856 | case 40: /* VSX Scalar Subtract Double-Precision */ | |
4857 | case 8: /* VSX Scalar Subtract Single-Precision */ | |
4858 | case 96: /* VSX Vector Add Double-Precision */ | |
4859 | case 64: /* VSX Vector Add Single-Precision */ | |
4860 | case 120: /* VSX Vector Divide Double-Precision */ | |
4861 | case 88: /* VSX Vector Divide Single-Precision */ | |
4862 | case 97: /* VSX Vector Multiply-Add Double-Precision */ | |
4863 | case 105: /* ditto */ | |
4864 | case 65: /* VSX Vector Multiply-Add Single-Precision */ | |
4865 | case 73: /* ditto */ | |
4866 | case 224: /* VSX Vector Maximum Double-Precision */ | |
4867 | case 192: /* VSX Vector Maximum Single-Precision */ | |
4868 | case 232: /* VSX Vector Minimum Double-Precision */ | |
4869 | case 200: /* VSX Vector Minimum Single-Precision */ | |
4870 | case 113: /* VSX Vector Multiply-Subtract Double-Precision */ | |
4871 | case 121: /* ditto */ | |
4872 | case 81: /* VSX Vector Multiply-Subtract Single-Precision */ | |
4873 | case 89: /* ditto */ | |
4874 | case 112: /* VSX Vector Multiply Double-Precision */ | |
4875 | case 80: /* VSX Vector Multiply Single-Precision */ | |
4876 | case 225: /* VSX Vector Negative Multiply-Add Double-Precision */ | |
4877 | case 233: /* ditto */ | |
4878 | case 193: /* VSX Vector Negative Multiply-Add Single-Precision */ | |
4879 | case 201: /* ditto */ | |
4880 | case 241: /* VSX Vector Negative Multiply-Subtract Double-Precision */ | |
4881 | case 249: /* ditto */ | |
4882 | case 209: /* VSX Vector Negative Multiply-Subtract Single-Precision */ | |
4883 | case 217: /* ditto */ | |
4884 | case 104: /* VSX Vector Subtract Double-Precision */ | |
4885 | case 72: /* VSX Vector Subtract Single-Precision */ | |
6ec2b213 EBM |
4886 | case 128: /* VSX Scalar Maximum Type-C Double-Precision */ |
4887 | case 136: /* VSX Scalar Minimum Type-C Double-Precision */ | |
4888 | case 144: /* VSX Scalar Maximum Type-J Double-Precision */ | |
4889 | case 152: /* VSX Scalar Minimum Type-J Double-Precision */ | |
4890 | case 3: /* VSX Scalar Compare Equal Double-Precision */ | |
4891 | case 11: /* VSX Scalar Compare Greater Than Double-Precision */ | |
4892 | case 19: /* VSX Scalar Compare Greater Than or Equal | |
4893 | Double-Precision */ | |
b4cdae6f | 4894 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); |
6ec2b213 | 4895 | /* FALL-THROUGH */ |
b4cdae6f WW |
4896 | case 240: /* VSX Vector Copy Sign Double-Precision */ |
4897 | case 208: /* VSX Vector Copy Sign Single-Precision */ | |
4898 | case 130: /* VSX Logical AND */ | |
4899 | case 138: /* VSX Logical AND with Complement */ | |
4900 | case 186: /* VSX Logical Equivalence */ | |
4901 | case 178: /* VSX Logical NAND */ | |
4902 | case 170: /* VSX Logical OR with Complement */ | |
4903 | case 162: /* VSX Logical NOR */ | |
4904 | case 146: /* VSX Logical OR */ | |
4905 | case 154: /* VSX Logical XOR */ | |
4906 | case 18: /* VSX Merge High Word */ | |
4907 | case 50: /* VSX Merge Low Word */ | |
4908 | case 10: /* VSX Permute Doubleword Immediate (DM=0) */ | |
4909 | case 10 | 0x20: /* VSX Permute Doubleword Immediate (DM=1) */ | |
4910 | case 10 | 0x40: /* VSX Permute Doubleword Immediate (DM=2) */ | |
4911 | case 10 | 0x60: /* VSX Permute Doubleword Immediate (DM=3) */ | |
4912 | case 2: /* VSX Shift Left Double by Word Immediate (SHW=0) */ | |
4913 | case 2 | 0x20: /* VSX Shift Left Double by Word Immediate (SHW=1) */ | |
4914 | case 2 | 0x40: /* VSX Shift Left Double by Word Immediate (SHW=2) */ | |
4915 | case 2 | 0x60: /* VSX Shift Left Double by Word Immediate (SHW=3) */ | |
6ec2b213 EBM |
4916 | case 216: /* VSX Vector Insert Exponent Single-Precision */ |
4917 | case 248: /* VSX Vector Insert Exponent Double-Precision */ | |
4918 | case 26: /* VSX Vector Permute */ | |
4919 | case 58: /* VSX Vector Permute Right-indexed */ | |
4920 | case 213: /* VSX Vector Test Data Class Single-Precision (DC=0) */ | |
4921 | case 213 | 0x8: /* VSX Vector Test Data Class Single-Precision (DC=1) */ | |
4922 | case 245: /* VSX Vector Test Data Class Double-Precision (DC=0) */ | |
4923 | case 245 | 0x8: /* VSX Vector Test Data Class Double-Precision (DC=1) */ | |
b4cdae6f WW |
4924 | ppc_record_vsr (regcache, tdep, PPC_XT (insn)); |
4925 | return 0; | |
4926 | ||
4927 | case 61: /* VSX Scalar Test for software Divide Double-Precision */ | |
4928 | case 125: /* VSX Vector Test for software Divide Double-Precision */ | |
4929 | case 93: /* VSX Vector Test for software Divide Single-Precision */ | |
4930 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
4931 | return 0; | |
4932 | ||
4933 | case 35: /* VSX Scalar Compare Unordered Double-Precision */ | |
4934 | case 43: /* VSX Scalar Compare Ordered Double-Precision */ | |
6ec2b213 | 4935 | case 59: /* VSX Scalar Compare Exponents Double-Precision */ |
b4cdae6f WW |
4936 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); |
4937 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
4938 | return 0; | |
4939 | } | |
4940 | ||
4941 | switch ((ext >> 2) & 0x7f) /* Mask out Rc-bit. */ | |
4942 | { | |
4943 | case 99: /* VSX Vector Compare Equal To Double-Precision */ | |
4944 | case 67: /* VSX Vector Compare Equal To Single-Precision */ | |
4945 | case 115: /* VSX Vector Compare Greater Than or | |
4946 | Equal To Double-Precision */ | |
4947 | case 83: /* VSX Vector Compare Greater Than or | |
4948 | Equal To Single-Precision */ | |
4949 | case 107: /* VSX Vector Compare Greater Than Double-Precision */ | |
4950 | case 75: /* VSX Vector Compare Greater Than Single-Precision */ | |
4951 | if (PPC_Rc (insn)) | |
4952 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
4953 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
4954 | ppc_record_vsr (regcache, tdep, PPC_XT (insn)); | |
4955 | return 0; | |
4956 | } | |
4957 | ||
4958 | switch (ext >> 1) | |
4959 | { | |
4960 | case 265: /* VSX Scalar round Double-Precision to | |
4961 | Single-Precision and Convert to | |
4962 | Single-Precision format */ | |
4963 | case 344: /* VSX Scalar truncate Double-Precision to | |
4964 | Integer and Convert to Signed Integer | |
4965 | Doubleword format with Saturate */ | |
4966 | case 88: /* VSX Scalar truncate Double-Precision to | |
4967 | Integer and Convert to Signed Integer Word | |
4968 | Format with Saturate */ | |
4969 | case 328: /* VSX Scalar truncate Double-Precision integer | |
4970 | and Convert to Unsigned Integer Doubleword | |
4971 | Format with Saturate */ | |
4972 | case 72: /* VSX Scalar truncate Double-Precision to | |
4973 | Integer and Convert to Unsigned Integer Word | |
4974 | Format with Saturate */ | |
4975 | case 329: /* VSX Scalar Convert Single-Precision to | |
4976 | Double-Precision format */ | |
4977 | case 376: /* VSX Scalar Convert Signed Integer | |
4978 | Doubleword to floating-point format and | |
4979 | Round to Double-Precision format */ | |
4980 | case 312: /* VSX Scalar Convert Signed Integer | |
4981 | Doubleword to floating-point format and | |
4982 | round to Single-Precision */ | |
4983 | case 360: /* VSX Scalar Convert Unsigned Integer | |
4984 | Doubleword to floating-point format and | |
4985 | Round to Double-Precision format */ | |
4986 | case 296: /* VSX Scalar Convert Unsigned Integer | |
4987 | Doubleword to floating-point format and | |
4988 | Round to Single-Precision */ | |
4989 | case 73: /* VSX Scalar Round to Double-Precision Integer | |
4990 | Using Round to Nearest Away */ | |
4991 | case 107: /* VSX Scalar Round to Double-Precision Integer | |
4992 | Exact using Current rounding mode */ | |
4993 | case 121: /* VSX Scalar Round to Double-Precision Integer | |
4994 | Using Round toward -Infinity */ | |
4995 | case 105: /* VSX Scalar Round to Double-Precision Integer | |
4996 | Using Round toward +Infinity */ | |
4997 | case 89: /* VSX Scalar Round to Double-Precision Integer | |
4998 | Using Round toward Zero */ | |
4999 | case 90: /* VSX Scalar Reciprocal Estimate Double-Precision */ | |
5000 | case 26: /* VSX Scalar Reciprocal Estimate Single-Precision */ | |
5001 | case 281: /* VSX Scalar Round to Single-Precision */ | |
5002 | case 74: /* VSX Scalar Reciprocal Square Root Estimate | |
5003 | Double-Precision */ | |
5004 | case 10: /* VSX Scalar Reciprocal Square Root Estimate | |
5005 | Single-Precision */ | |
5006 | case 75: /* VSX Scalar Square Root Double-Precision */ | |
5007 | case 11: /* VSX Scalar Square Root Single-Precision */ | |
5008 | case 393: /* VSX Vector round Double-Precision to | |
5009 | Single-Precision and Convert to | |
5010 | Single-Precision format */ | |
5011 | case 472: /* VSX Vector truncate Double-Precision to | |
5012 | Integer and Convert to Signed Integer | |
5013 | Doubleword format with Saturate */ | |
5014 | case 216: /* VSX Vector truncate Double-Precision to | |
5015 | Integer and Convert to Signed Integer Word | |
5016 | Format with Saturate */ | |
5017 | case 456: /* VSX Vector truncate Double-Precision to | |
5018 | Integer and Convert to Unsigned Integer | |
5019 | Doubleword format with Saturate */ | |
5020 | case 200: /* VSX Vector truncate Double-Precision to | |
5021 | Integer and Convert to Unsigned Integer Word | |
5022 | Format with Saturate */ | |
5023 | case 457: /* VSX Vector Convert Single-Precision to | |
5024 | Double-Precision format */ | |
5025 | case 408: /* VSX Vector truncate Single-Precision to | |
5026 | Integer and Convert to Signed Integer | |
5027 | Doubleword format with Saturate */ | |
5028 | case 152: /* VSX Vector truncate Single-Precision to | |
5029 | Integer and Convert to Signed Integer Word | |
5030 | Format with Saturate */ | |
5031 | case 392: /* VSX Vector truncate Single-Precision to | |
5032 | Integer and Convert to Unsigned Integer | |
5033 | Doubleword format with Saturate */ | |
5034 | case 136: /* VSX Vector truncate Single-Precision to | |
5035 | Integer and Convert to Unsigned Integer Word | |
5036 | Format with Saturate */ | |
5037 | case 504: /* VSX Vector Convert and round Signed Integer | |
5038 | Doubleword to Double-Precision format */ | |
5039 | case 440: /* VSX Vector Convert and round Signed Integer | |
5040 | Doubleword to Single-Precision format */ | |
5041 | case 248: /* VSX Vector Convert Signed Integer Word to | |
5042 | Double-Precision format */ | |
5043 | case 184: /* VSX Vector Convert and round Signed Integer | |
5044 | Word to Single-Precision format */ | |
5045 | case 488: /* VSX Vector Convert and round Unsigned | |
5046 | Integer Doubleword to Double-Precision format */ | |
5047 | case 424: /* VSX Vector Convert and round Unsigned | |
5048 | Integer Doubleword to Single-Precision format */ | |
5049 | case 232: /* VSX Vector Convert and round Unsigned | |
5050 | Integer Word to Double-Precision format */ | |
5051 | case 168: /* VSX Vector Convert and round Unsigned | |
5052 | Integer Word to Single-Precision format */ | |
5053 | case 201: /* VSX Vector Round to Double-Precision | |
5054 | Integer using round to Nearest Away */ | |
5055 | case 235: /* VSX Vector Round to Double-Precision | |
5056 | Integer Exact using Current rounding mode */ | |
5057 | case 249: /* VSX Vector Round to Double-Precision | |
5058 | Integer using round toward -Infinity */ | |
5059 | case 233: /* VSX Vector Round to Double-Precision | |
5060 | Integer using round toward +Infinity */ | |
5061 | case 217: /* VSX Vector Round to Double-Precision | |
5062 | Integer using round toward Zero */ | |
5063 | case 218: /* VSX Vector Reciprocal Estimate Double-Precision */ | |
5064 | case 154: /* VSX Vector Reciprocal Estimate Single-Precision */ | |
5065 | case 137: /* VSX Vector Round to Single-Precision Integer | |
5066 | Using Round to Nearest Away */ | |
5067 | case 171: /* VSX Vector Round to Single-Precision Integer | |
5068 | Exact Using Current rounding mode */ | |
5069 | case 185: /* VSX Vector Round to Single-Precision Integer | |
5070 | Using Round toward -Infinity */ | |
5071 | case 169: /* VSX Vector Round to Single-Precision Integer | |
5072 | Using Round toward +Infinity */ | |
5073 | case 153: /* VSX Vector Round to Single-Precision Integer | |
5074 | Using round toward Zero */ | |
5075 | case 202: /* VSX Vector Reciprocal Square Root Estimate | |
5076 | Double-Precision */ | |
5077 | case 138: /* VSX Vector Reciprocal Square Root Estimate | |
5078 | Single-Precision */ | |
5079 | case 203: /* VSX Vector Square Root Double-Precision */ | |
5080 | case 139: /* VSX Vector Square Root Single-Precision */ | |
5081 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
6ec2b213 | 5082 | /* FALL-THROUGH */ |
b4cdae6f WW |
5083 | case 345: /* VSX Scalar Absolute Value Double-Precision */ |
5084 | case 267: /* VSX Scalar Convert Scalar Single-Precision to | |
5085 | Vector Single-Precision format Non-signalling */ | |
5086 | case 331: /* VSX Scalar Convert Single-Precision to | |
5087 | Double-Precision format Non-signalling */ | |
5088 | case 361: /* VSX Scalar Negative Absolute Value Double-Precision */ | |
5089 | case 377: /* VSX Scalar Negate Double-Precision */ | |
5090 | case 473: /* VSX Vector Absolute Value Double-Precision */ | |
5091 | case 409: /* VSX Vector Absolute Value Single-Precision */ | |
5092 | case 489: /* VSX Vector Negative Absolute Value Double-Precision */ | |
5093 | case 425: /* VSX Vector Negative Absolute Value Single-Precision */ | |
5094 | case 505: /* VSX Vector Negate Double-Precision */ | |
5095 | case 441: /* VSX Vector Negate Single-Precision */ | |
5096 | case 164: /* VSX Splat Word */ | |
6ec2b213 EBM |
5097 | case 165: /* VSX Vector Extract Unsigned Word */ |
5098 | case 181: /* VSX Vector Insert Word */ | |
b4cdae6f WW |
5099 | ppc_record_vsr (regcache, tdep, PPC_XT (insn)); |
5100 | return 0; | |
5101 | ||
6ec2b213 EBM |
5102 | case 298: /* VSX Scalar Test Data Class Single-Precision */ |
5103 | case 362: /* VSX Scalar Test Data Class Double-Precision */ | |
5104 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
5105 | /* FALL-THROUGH */ | |
b4cdae6f WW |
5106 | case 106: /* VSX Scalar Test for software Square Root |
5107 | Double-Precision */ | |
5108 | case 234: /* VSX Vector Test for software Square Root | |
5109 | Double-Precision */ | |
5110 | case 170: /* VSX Vector Test for software Square Root | |
5111 | Single-Precision */ | |
5112 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
5113 | return 0; | |
6ec2b213 EBM |
5114 | |
5115 | case 347: | |
5116 | switch (PPC_FIELD (insn, 11, 5)) | |
5117 | { | |
5118 | case 0: /* VSX Scalar Extract Exponent Double-Precision */ | |
5119 | case 1: /* VSX Scalar Extract Significand Double-Precision */ | |
5120 | record_full_arch_list_add_reg (regcache, | |
5121 | tdep->ppc_gp0_regnum + PPC_RT (insn)); | |
5122 | return 0; | |
5123 | case 16: /* VSX Scalar Convert Half-Precision format to | |
5124 | Double-Precision format */ | |
5125 | case 17: /* VSX Scalar round & Convert Double-Precision format | |
5126 | to Half-Precision format */ | |
5127 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
5128 | ppc_record_vsr (regcache, tdep, PPC_XT (insn)); | |
5129 | return 0; | |
5130 | } | |
5131 | break; | |
5132 | ||
5133 | case 475: | |
5134 | switch (PPC_FIELD (insn, 11, 5)) | |
5135 | { | |
5136 | case 24: /* VSX Vector Convert Half-Precision format to | |
5137 | Single-Precision format */ | |
5138 | case 25: /* VSX Vector round and Convert Single-Precision format | |
5139 | to Half-Precision format */ | |
5140 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
5141 | /* FALL-THROUGH */ | |
5142 | case 0: /* VSX Vector Extract Exponent Double-Precision */ | |
5143 | case 1: /* VSX Vector Extract Significand Double-Precision */ | |
5144 | case 7: /* VSX Vector Byte-Reverse Halfword */ | |
5145 | case 8: /* VSX Vector Extract Exponent Single-Precision */ | |
5146 | case 9: /* VSX Vector Extract Significand Single-Precision */ | |
5147 | case 15: /* VSX Vector Byte-Reverse Word */ | |
5148 | case 23: /* VSX Vector Byte-Reverse Doubleword */ | |
5149 | case 31: /* VSX Vector Byte-Reverse Quadword */ | |
5150 | ppc_record_vsr (regcache, tdep, PPC_XT (insn)); | |
5151 | return 0; | |
5152 | } | |
5153 | break; | |
5154 | } | |
5155 | ||
5156 | switch (ext) | |
5157 | { | |
5158 | case 360: /* VSX Vector Splat Immediate Byte */ | |
5159 | if (PPC_FIELD (insn, 11, 2) == 0) | |
5160 | { | |
5161 | ppc_record_vsr (regcache, tdep, PPC_XT (insn)); | |
5162 | return 0; | |
5163 | } | |
5164 | break; | |
5165 | case 918: /* VSX Scalar Insert Exponent Double-Precision */ | |
5166 | ppc_record_vsr (regcache, tdep, PPC_XT (insn)); | |
5167 | return 0; | |
b4cdae6f WW |
5168 | } |
5169 | ||
5170 | if (((ext >> 3) & 0x3) == 3) /* VSX Select */ | |
5171 | { | |
5172 | ppc_record_vsr (regcache, tdep, PPC_XT (insn)); | |
5173 | return 0; | |
5174 | } | |
5175 | ||
810c1026 WW |
5176 | fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x " |
5177 | "at %s, 60-%d.\n", insn, paddress (gdbarch, addr), ext); | |
b4cdae6f WW |
5178 | return -1; |
5179 | } | |
5180 | ||
6ec2b213 EBM |
5181 | /* Parse and record instructions of primary opcode-61 at ADDR. |
5182 | Return 0 if successful. */ | |
5183 | ||
5184 | static int | |
5185 | ppc_process_record_op61 (struct gdbarch *gdbarch, struct regcache *regcache, | |
5186 | CORE_ADDR addr, uint32_t insn) | |
5187 | { | |
5188 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
5189 | ULONGEST ea = 0; | |
5190 | int size; | |
5191 | ||
5192 | switch (insn & 0x3) | |
5193 | { | |
5194 | case 0: /* Store Floating-Point Double Pair */ | |
5195 | case 2: /* Store VSX Scalar Doubleword */ | |
5196 | case 3: /* Store VSX Scalar Single */ | |
5197 | if (PPC_RA (insn) != 0) | |
5198 | regcache_raw_read_unsigned (regcache, | |
5199 | tdep->ppc_gp0_regnum + PPC_RA (insn), | |
5200 | &ea); | |
5201 | ea += PPC_DS (insn) << 2; | |
5202 | switch (insn & 0x3) | |
5203 | { | |
5204 | case 0: /* Store Floating-Point Double Pair */ | |
5205 | size = 16; | |
5206 | break; | |
5207 | case 2: /* Store VSX Scalar Doubleword */ | |
5208 | size = 8; | |
5209 | break; | |
5210 | case 3: /* Store VSX Scalar Single */ | |
5211 | size = 4; | |
5212 | break; | |
5213 | default: | |
5214 | gdb_assert (0); | |
5215 | } | |
5216 | record_full_arch_list_add_mem (ea, size); | |
5217 | return 0; | |
5218 | } | |
5219 | ||
5220 | switch (insn & 0x7) | |
5221 | { | |
5222 | case 1: /* Load VSX Vector */ | |
5223 | ppc_record_vsr (regcache, tdep, PPC_XT (insn)); | |
5224 | return 0; | |
5225 | case 5: /* Store VSX Vector */ | |
5226 | if (PPC_RA (insn) != 0) | |
5227 | regcache_raw_read_unsigned (regcache, | |
5228 | tdep->ppc_gp0_regnum + PPC_RA (insn), | |
5229 | &ea); | |
5230 | ea += PPC_DQ (insn) << 4; | |
5231 | record_full_arch_list_add_mem (ea, 16); | |
5232 | return 0; | |
5233 | } | |
5234 | ||
5235 | fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x " | |
5236 | "at %s.\n", insn, paddress (gdbarch, addr)); | |
5237 | return -1; | |
5238 | } | |
5239 | ||
ddeca1df WW |
5240 | /* Parse and record instructions of primary opcode-63 at ADDR. |
5241 | Return 0 if successful. */ | |
b4cdae6f WW |
5242 | |
5243 | static int | |
5244 | ppc_process_record_op63 (struct gdbarch *gdbarch, struct regcache *regcache, | |
5245 | CORE_ADDR addr, uint32_t insn) | |
5246 | { | |
5247 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
5248 | int ext = PPC_EXTOP (insn); | |
5249 | int tmp; | |
5250 | ||
5251 | switch (ext & 0x1f) | |
5252 | { | |
5253 | case 18: /* Floating Divide */ | |
5254 | case 20: /* Floating Subtract */ | |
5255 | case 21: /* Floating Add */ | |
5256 | case 22: /* Floating Square Root */ | |
5257 | case 24: /* Floating Reciprocal Estimate */ | |
5258 | case 25: /* Floating Multiply */ | |
5259 | case 26: /* Floating Reciprocal Square Root Estimate */ | |
5260 | case 28: /* Floating Multiply-Subtract */ | |
5261 | case 29: /* Floating Multiply-Add */ | |
5262 | case 30: /* Floating Negative Multiply-Subtract */ | |
5263 | case 31: /* Floating Negative Multiply-Add */ | |
5264 | record_full_arch_list_add_reg (regcache, | |
5265 | tdep->ppc_fp0_regnum + PPC_FRT (insn)); | |
5266 | if (PPC_RC (insn)) | |
5267 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
5268 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
5269 | return 0; | |
5270 | ||
5271 | case 23: /* Floating Select */ | |
5272 | record_full_arch_list_add_reg (regcache, | |
5273 | tdep->ppc_fp0_regnum + PPC_FRT (insn)); | |
5274 | if (PPC_RC (insn)) | |
5275 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
8aabe2e2 | 5276 | return 0; |
b4cdae6f WW |
5277 | } |
5278 | ||
6ec2b213 EBM |
5279 | switch (ext & 0xff) |
5280 | { | |
5281 | case 5: /* VSX Scalar Round to Quad-Precision Integer */ | |
5282 | case 37: /* VSX Scalar Round Quad-Precision to Double-Extended | |
5283 | Precision */ | |
5284 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
5285 | ppc_record_vsr (regcache, tdep, PPC_VRT (insn) + 32); | |
5286 | return 0; | |
5287 | } | |
5288 | ||
b4cdae6f WW |
5289 | switch (ext) |
5290 | { | |
5291 | case 2: /* DFP Add Quad */ | |
5292 | case 3: /* DFP Quantize Quad */ | |
5293 | case 34: /* DFP Multiply Quad */ | |
5294 | case 35: /* DFP Reround Quad */ | |
5295 | case 67: /* DFP Quantize Immediate Quad */ | |
5296 | case 99: /* DFP Round To FP Integer With Inexact Quad */ | |
5297 | case 227: /* DFP Round To FP Integer Without Inexact Quad */ | |
5298 | case 258: /* DFP Convert To DFP Extended Quad */ | |
5299 | case 514: /* DFP Subtract Quad */ | |
5300 | case 546: /* DFP Divide Quad */ | |
5301 | case 770: /* DFP Round To DFP Long Quad */ | |
5302 | case 802: /* DFP Convert From Fixed Quad */ | |
5303 | case 834: /* DFP Encode BCD To DPD Quad */ | |
5304 | if (PPC_RC (insn)) | |
5305 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
5306 | tmp = tdep->ppc_fp0_regnum + (PPC_FRT (insn) & ~1); | |
5307 | record_full_arch_list_add_reg (regcache, tmp); | |
5308 | record_full_arch_list_add_reg (regcache, tmp + 1); | |
5309 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
5310 | return 0; | |
5311 | ||
5312 | case 130: /* DFP Compare Ordered Quad */ | |
5313 | case 162: /* DFP Test Exponent Quad */ | |
5314 | case 194: /* DFP Test Data Class Quad */ | |
5315 | case 226: /* DFP Test Data Group Quad */ | |
5316 | case 642: /* DFP Compare Unordered Quad */ | |
5317 | case 674: /* DFP Test Significance Quad */ | |
6ec2b213 | 5318 | case 675: /* DFP Test Significance Immediate Quad */ |
b4cdae6f WW |
5319 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); |
5320 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
5321 | return 0; | |
5322 | ||
5323 | case 66: /* DFP Shift Significand Left Immediate Quad */ | |
5324 | case 98: /* DFP Shift Significand Right Immediate Quad */ | |
5325 | case 322: /* DFP Decode DPD To BCD Quad */ | |
5326 | case 866: /* DFP Insert Biased Exponent Quad */ | |
5327 | tmp = tdep->ppc_fp0_regnum + (PPC_FRT (insn) & ~1); | |
5328 | record_full_arch_list_add_reg (regcache, tmp); | |
5329 | record_full_arch_list_add_reg (regcache, tmp + 1); | |
5330 | if (PPC_RC (insn)) | |
5331 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
5332 | return 0; | |
5333 | ||
5334 | case 290: /* DFP Convert To Fixed Quad */ | |
5335 | record_full_arch_list_add_reg (regcache, | |
5336 | tdep->ppc_fp0_regnum + PPC_FRT (insn)); | |
5337 | if (PPC_RC (insn)) | |
5338 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
5339 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
8aabe2e2 | 5340 | return 0; |
b4cdae6f WW |
5341 | |
5342 | case 354: /* DFP Extract Biased Exponent Quad */ | |
5343 | record_full_arch_list_add_reg (regcache, | |
5344 | tdep->ppc_fp0_regnum + PPC_FRT (insn)); | |
5345 | if (PPC_RC (insn)) | |
5346 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
5347 | return 0; | |
5348 | ||
5349 | case 12: /* Floating Round to Single-Precision */ | |
5350 | case 14: /* Floating Convert To Integer Word */ | |
5351 | case 15: /* Floating Convert To Integer Word | |
5352 | with round toward Zero */ | |
5353 | case 142: /* Floating Convert To Integer Word Unsigned */ | |
5354 | case 143: /* Floating Convert To Integer Word Unsigned | |
5355 | with round toward Zero */ | |
5356 | case 392: /* Floating Round to Integer Nearest */ | |
5357 | case 424: /* Floating Round to Integer Toward Zero */ | |
5358 | case 456: /* Floating Round to Integer Plus */ | |
5359 | case 488: /* Floating Round to Integer Minus */ | |
5360 | case 814: /* Floating Convert To Integer Doubleword */ | |
5361 | case 815: /* Floating Convert To Integer Doubleword | |
5362 | with round toward Zero */ | |
5363 | case 846: /* Floating Convert From Integer Doubleword */ | |
5364 | case 942: /* Floating Convert To Integer Doubleword Unsigned */ | |
5365 | case 943: /* Floating Convert To Integer Doubleword Unsigned | |
5366 | with round toward Zero */ | |
5367 | case 974: /* Floating Convert From Integer Doubleword Unsigned */ | |
5368 | record_full_arch_list_add_reg (regcache, | |
5369 | tdep->ppc_fp0_regnum + PPC_FRT (insn)); | |
5370 | if (PPC_RC (insn)) | |
5371 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
5372 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
5373 | return 0; | |
5374 | ||
6ec2b213 EBM |
5375 | case 583: |
5376 | switch (PPC_FIELD (insn, 11, 5)) | |
5377 | { | |
5378 | case 1: /* Move From FPSCR & Clear Enables */ | |
5379 | case 20: /* Move From FPSCR Control & set DRN */ | |
5380 | case 21: /* Move From FPSCR Control & set DRN Immediate */ | |
5381 | case 22: /* Move From FPSCR Control & set RN */ | |
5382 | case 23: /* Move From FPSCR Control & set RN Immediate */ | |
5383 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
e3829d13 | 5384 | /* Fall through. */ |
6ec2b213 EBM |
5385 | case 0: /* Move From FPSCR */ |
5386 | case 24: /* Move From FPSCR Lightweight */ | |
5387 | if (PPC_FIELD (insn, 11, 5) == 0 && PPC_RC (insn)) | |
5388 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
5389 | record_full_arch_list_add_reg (regcache, | |
5390 | tdep->ppc_fp0_regnum | |
5391 | + PPC_FRT (insn)); | |
5392 | return 0; | |
5393 | } | |
5394 | break; | |
5395 | ||
b4cdae6f WW |
5396 | case 8: /* Floating Copy Sign */ |
5397 | case 40: /* Floating Negate */ | |
5398 | case 72: /* Floating Move Register */ | |
5399 | case 136: /* Floating Negative Absolute Value */ | |
5400 | case 264: /* Floating Absolute Value */ | |
5401 | record_full_arch_list_add_reg (regcache, | |
5402 | tdep->ppc_fp0_regnum + PPC_FRT (insn)); | |
5403 | if (PPC_RC (insn)) | |
5404 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
5405 | return 0; | |
5406 | ||
5407 | case 838: /* Floating Merge Odd Word */ | |
5408 | case 966: /* Floating Merge Even Word */ | |
5409 | record_full_arch_list_add_reg (regcache, | |
5410 | tdep->ppc_fp0_regnum + PPC_FRT (insn)); | |
5411 | return 0; | |
5412 | ||
5413 | case 38: /* Move To FPSCR Bit 1 */ | |
5414 | case 70: /* Move To FPSCR Bit 0 */ | |
5415 | case 134: /* Move To FPSCR Field Immediate */ | |
5416 | case 711: /* Move To FPSCR Fields */ | |
5417 | if (PPC_RC (insn)) | |
5418 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
5419 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
8aabe2e2 | 5420 | return 0; |
b4cdae6f WW |
5421 | |
5422 | case 0: /* Floating Compare Unordered */ | |
5423 | case 32: /* Floating Compare Ordered */ | |
5424 | case 64: /* Move to Condition Register from FPSCR */ | |
6ec2b213 EBM |
5425 | case 132: /* VSX Scalar Compare Ordered Quad-Precision */ |
5426 | case 164: /* VSX Scalar Compare Exponents Quad-Precision */ | |
5427 | case 644: /* VSX Scalar Compare Unordered Quad-Precision */ | |
5428 | case 708: /* VSX Scalar Test Data Class Quad-Precision */ | |
b4cdae6f WW |
5429 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); |
5430 | /* FALL-THROUGH */ | |
5431 | case 128: /* Floating Test for software Divide */ | |
5432 | case 160: /* Floating Test for software Square Root */ | |
5433 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
5434 | return 0; | |
5435 | ||
6ec2b213 EBM |
5436 | case 4: /* VSX Scalar Add Quad-Precision */ |
5437 | case 36: /* VSX Scalar Multiply Quad-Precision */ | |
5438 | case 388: /* VSX Scalar Multiply-Add Quad-Precision */ | |
5439 | case 420: /* VSX Scalar Multiply-Subtract Quad-Precision */ | |
5440 | case 452: /* VSX Scalar Negative Multiply-Add Quad-Precision */ | |
5441 | case 484: /* VSX Scalar Negative Multiply-Subtract | |
5442 | Quad-Precision */ | |
5443 | case 516: /* VSX Scalar Subtract Quad-Precision */ | |
5444 | case 548: /* VSX Scalar Divide Quad-Precision */ | |
5445 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
5446 | /* FALL-THROUGH */ | |
5447 | case 100: /* VSX Scalar Copy Sign Quad-Precision */ | |
5448 | case 868: /* VSX Scalar Insert Exponent Quad-Precision */ | |
5449 | ppc_record_vsr (regcache, tdep, PPC_VRT (insn) + 32); | |
5450 | return 0; | |
5451 | ||
5452 | case 804: | |
5453 | switch (PPC_FIELD (insn, 11, 5)) | |
5454 | { | |
5455 | case 27: /* VSX Scalar Square Root Quad-Precision */ | |
5456 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
5457 | /* FALL-THROUGH */ | |
5458 | case 0: /* VSX Scalar Absolute Quad-Precision */ | |
5459 | case 2: /* VSX Scalar Extract Exponent Quad-Precision */ | |
5460 | case 8: /* VSX Scalar Negative Absolute Quad-Precision */ | |
5461 | case 16: /* VSX Scalar Negate Quad-Precision */ | |
5462 | case 18: /* VSX Scalar Extract Significand Quad-Precision */ | |
5463 | ppc_record_vsr (regcache, tdep, PPC_VRT (insn) + 32); | |
5464 | return 0; | |
5465 | } | |
5466 | break; | |
5467 | ||
5468 | case 836: | |
5469 | switch (PPC_FIELD (insn, 11, 5)) | |
5470 | { | |
5471 | case 1: /* VSX Scalar truncate & Convert Quad-Precision format | |
5472 | to Unsigned Word format */ | |
5473 | case 2: /* VSX Scalar Convert Unsigned Doubleword format to | |
5474 | Quad-Precision format */ | |
5475 | case 9: /* VSX Scalar truncate & Convert Quad-Precision format | |
5476 | to Signed Word format */ | |
5477 | case 10: /* VSX Scalar Convert Signed Doubleword format to | |
5478 | Quad-Precision format */ | |
5479 | case 17: /* VSX Scalar truncate & Convert Quad-Precision format | |
5480 | to Unsigned Doubleword format */ | |
5481 | case 20: /* VSX Scalar round & Convert Quad-Precision format to | |
5482 | Double-Precision format */ | |
5483 | case 22: /* VSX Scalar Convert Double-Precision format to | |
5484 | Quad-Precision format */ | |
5485 | case 25: /* VSX Scalar truncate & Convert Quad-Precision format | |
5486 | to Signed Doubleword format */ | |
5487 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
5488 | ppc_record_vsr (regcache, tdep, PPC_VRT (insn) + 32); | |
5489 | return 0; | |
5490 | } | |
b4cdae6f WW |
5491 | } |
5492 | ||
810c1026 | 5493 | fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x " |
6ec2b213 | 5494 | "at %s, 63-%d.\n", insn, paddress (gdbarch, addr), ext); |
b4cdae6f WW |
5495 | return -1; |
5496 | } | |
5497 | ||
5498 | /* Parse the current instruction and record the values of the registers and | |
5499 | memory that will be changed in current instruction to "record_arch_list". | |
5500 | Return -1 if something wrong. */ | |
5501 | ||
5502 | int | |
5503 | ppc_process_record (struct gdbarch *gdbarch, struct regcache *regcache, | |
5504 | CORE_ADDR addr) | |
5505 | { | |
5506 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
5507 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
5508 | uint32_t insn; | |
5509 | int op6, tmp, i; | |
5510 | ||
5511 | insn = read_memory_unsigned_integer (addr, 4, byte_order); | |
5512 | op6 = PPC_OP6 (insn); | |
5513 | ||
5514 | switch (op6) | |
5515 | { | |
5516 | case 2: /* Trap Doubleword Immediate */ | |
5517 | case 3: /* Trap Word Immediate */ | |
5518 | /* Do nothing. */ | |
5519 | break; | |
5520 | ||
5521 | case 4: | |
5522 | if (ppc_process_record_op4 (gdbarch, regcache, addr, insn) != 0) | |
5523 | return -1; | |
5524 | break; | |
5525 | ||
5526 | case 17: /* System call */ | |
5527 | if (PPC_LEV (insn) != 0) | |
5528 | goto UNKNOWN_OP; | |
5529 | ||
5530 | if (tdep->ppc_syscall_record != NULL) | |
5531 | { | |
5532 | if (tdep->ppc_syscall_record (regcache) != 0) | |
5533 | return -1; | |
5534 | } | |
5535 | else | |
5536 | { | |
5537 | printf_unfiltered (_("no syscall record support\n")); | |
5538 | return -1; | |
5539 | } | |
5540 | break; | |
5541 | ||
5542 | case 7: /* Multiply Low Immediate */ | |
5543 | record_full_arch_list_add_reg (regcache, | |
5544 | tdep->ppc_gp0_regnum + PPC_RT (insn)); | |
5545 | break; | |
5546 | ||
5547 | case 8: /* Subtract From Immediate Carrying */ | |
5548 | record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum); | |
5549 | record_full_arch_list_add_reg (regcache, | |
5550 | tdep->ppc_gp0_regnum + PPC_RT (insn)); | |
5551 | break; | |
5552 | ||
5553 | case 10: /* Compare Logical Immediate */ | |
5554 | case 11: /* Compare Immediate */ | |
5555 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
5556 | break; | |
5557 | ||
5558 | case 13: /* Add Immediate Carrying and Record */ | |
5559 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
5560 | /* FALL-THROUGH */ | |
5561 | case 12: /* Add Immediate Carrying */ | |
5562 | record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum); | |
5563 | /* FALL-THROUGH */ | |
5564 | case 14: /* Add Immediate */ | |
5565 | case 15: /* Add Immediate Shifted */ | |
5566 | record_full_arch_list_add_reg (regcache, | |
5567 | tdep->ppc_gp0_regnum + PPC_RT (insn)); | |
5568 | break; | |
5569 | ||
5570 | case 16: /* Branch Conditional */ | |
5571 | if ((PPC_BO (insn) & 0x4) == 0) | |
5572 | record_full_arch_list_add_reg (regcache, tdep->ppc_ctr_regnum); | |
5573 | /* FALL-THROUGH */ | |
5574 | case 18: /* Branch */ | |
5575 | if (PPC_LK (insn)) | |
5576 | record_full_arch_list_add_reg (regcache, tdep->ppc_lr_regnum); | |
5577 | break; | |
5578 | ||
5579 | case 19: | |
5580 | if (ppc_process_record_op19 (gdbarch, regcache, addr, insn) != 0) | |
5581 | return -1; | |
5582 | break; | |
5583 | ||
5584 | case 20: /* Rotate Left Word Immediate then Mask Insert */ | |
5585 | case 21: /* Rotate Left Word Immediate then AND with Mask */ | |
5586 | case 23: /* Rotate Left Word then AND with Mask */ | |
5587 | case 30: /* Rotate Left Doubleword Immediate then Clear Left */ | |
5588 | /* Rotate Left Doubleword Immediate then Clear Right */ | |
5589 | /* Rotate Left Doubleword Immediate then Clear */ | |
5590 | /* Rotate Left Doubleword then Clear Left */ | |
5591 | /* Rotate Left Doubleword then Clear Right */ | |
5592 | /* Rotate Left Doubleword Immediate then Mask Insert */ | |
5593 | if (PPC_RC (insn)) | |
5594 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
5595 | record_full_arch_list_add_reg (regcache, | |
5596 | tdep->ppc_gp0_regnum + PPC_RA (insn)); | |
5597 | break; | |
5598 | ||
5599 | case 28: /* AND Immediate */ | |
5600 | case 29: /* AND Immediate Shifted */ | |
5601 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
5602 | /* FALL-THROUGH */ | |
5603 | case 24: /* OR Immediate */ | |
5604 | case 25: /* OR Immediate Shifted */ | |
5605 | case 26: /* XOR Immediate */ | |
5606 | case 27: /* XOR Immediate Shifted */ | |
5607 | record_full_arch_list_add_reg (regcache, | |
5608 | tdep->ppc_gp0_regnum + PPC_RA (insn)); | |
5609 | break; | |
5610 | ||
5611 | case 31: | |
5612 | if (ppc_process_record_op31 (gdbarch, regcache, addr, insn) != 0) | |
5613 | return -1; | |
5614 | break; | |
5615 | ||
5616 | case 33: /* Load Word and Zero with Update */ | |
5617 | case 35: /* Load Byte and Zero with Update */ | |
5618 | case 41: /* Load Halfword and Zero with Update */ | |
5619 | case 43: /* Load Halfword Algebraic with Update */ | |
5620 | record_full_arch_list_add_reg (regcache, | |
5621 | tdep->ppc_gp0_regnum + PPC_RA (insn)); | |
5622 | /* FALL-THROUGH */ | |
5623 | case 32: /* Load Word and Zero */ | |
5624 | case 34: /* Load Byte and Zero */ | |
5625 | case 40: /* Load Halfword and Zero */ | |
5626 | case 42: /* Load Halfword Algebraic */ | |
5627 | record_full_arch_list_add_reg (regcache, | |
5628 | tdep->ppc_gp0_regnum + PPC_RT (insn)); | |
5629 | break; | |
5630 | ||
5631 | case 46: /* Load Multiple Word */ | |
5632 | for (i = PPC_RT (insn); i < 32; i++) | |
5633 | record_full_arch_list_add_reg (regcache, tdep->ppc_gp0_regnum + i); | |
5634 | break; | |
5635 | ||
5636 | case 56: /* Load Quadword */ | |
5637 | tmp = tdep->ppc_gp0_regnum + (PPC_RT (insn) & ~1); | |
5638 | record_full_arch_list_add_reg (regcache, tmp); | |
5639 | record_full_arch_list_add_reg (regcache, tmp + 1); | |
5640 | break; | |
5641 | ||
5642 | case 49: /* Load Floating-Point Single with Update */ | |
5643 | case 51: /* Load Floating-Point Double with Update */ | |
5644 | record_full_arch_list_add_reg (regcache, | |
5645 | tdep->ppc_gp0_regnum + PPC_RA (insn)); | |
5646 | /* FALL-THROUGH */ | |
5647 | case 48: /* Load Floating-Point Single */ | |
5648 | case 50: /* Load Floating-Point Double */ | |
5649 | record_full_arch_list_add_reg (regcache, | |
5650 | tdep->ppc_fp0_regnum + PPC_FRT (insn)); | |
5651 | break; | |
5652 | ||
5653 | case 47: /* Store Multiple Word */ | |
5654 | { | |
5655 | ULONGEST addr = 0; | |
5656 | ||
5657 | if (PPC_RA (insn) != 0) | |
5658 | regcache_raw_read_unsigned (regcache, | |
5659 | tdep->ppc_gp0_regnum + PPC_RA (insn), | |
5660 | &addr); | |
5661 | ||
5662 | addr += PPC_D (insn); | |
5663 | record_full_arch_list_add_mem (addr, 4 * (32 - PPC_RS (insn))); | |
5664 | } | |
5665 | break; | |
5666 | ||
5667 | case 37: /* Store Word with Update */ | |
5668 | case 39: /* Store Byte with Update */ | |
5669 | case 45: /* Store Halfword with Update */ | |
5670 | case 53: /* Store Floating-Point Single with Update */ | |
5671 | case 55: /* Store Floating-Point Double with Update */ | |
5672 | record_full_arch_list_add_reg (regcache, | |
5673 | tdep->ppc_gp0_regnum + PPC_RA (insn)); | |
5674 | /* FALL-THROUGH */ | |
5675 | case 36: /* Store Word */ | |
5676 | case 38: /* Store Byte */ | |
5677 | case 44: /* Store Halfword */ | |
5678 | case 52: /* Store Floating-Point Single */ | |
5679 | case 54: /* Store Floating-Point Double */ | |
5680 | { | |
5681 | ULONGEST addr = 0; | |
5682 | int size = -1; | |
5683 | ||
5684 | if (PPC_RA (insn) != 0) | |
5685 | regcache_raw_read_unsigned (regcache, | |
5686 | tdep->ppc_gp0_regnum + PPC_RA (insn), | |
5687 | &addr); | |
5688 | addr += PPC_D (insn); | |
5689 | ||
5690 | if (op6 == 36 || op6 == 37 || op6 == 52 || op6 == 53) | |
5691 | size = 4; | |
5692 | else if (op6 == 54 || op6 == 55) | |
5693 | size = 8; | |
5694 | else if (op6 == 44 || op6 == 45) | |
5695 | size = 2; | |
5696 | else if (op6 == 38 || op6 == 39) | |
5697 | size = 1; | |
5698 | else | |
5699 | gdb_assert (0); | |
5700 | ||
5701 | record_full_arch_list_add_mem (addr, size); | |
5702 | } | |
5703 | break; | |
5704 | ||
6ec2b213 EBM |
5705 | case 57: |
5706 | switch (insn & 0x3) | |
5707 | { | |
5708 | case 0: /* Load Floating-Point Double Pair */ | |
5709 | tmp = tdep->ppc_fp0_regnum + (PPC_RT (insn) & ~1); | |
5710 | record_full_arch_list_add_reg (regcache, tmp); | |
5711 | record_full_arch_list_add_reg (regcache, tmp + 1); | |
5712 | break; | |
5713 | case 2: /* Load VSX Scalar Doubleword */ | |
5714 | case 3: /* Load VSX Scalar Single */ | |
5715 | ppc_record_vsr (regcache, tdep, PPC_VRT (insn) + 32); | |
5716 | break; | |
5717 | default: | |
5718 | goto UNKNOWN_OP; | |
5719 | } | |
b4cdae6f WW |
5720 | break; |
5721 | ||
5722 | case 58: /* Load Doubleword */ | |
5723 | /* Load Doubleword with Update */ | |
5724 | /* Load Word Algebraic */ | |
5725 | if (PPC_FIELD (insn, 30, 2) > 2) | |
5726 | goto UNKNOWN_OP; | |
5727 | ||
5728 | record_full_arch_list_add_reg (regcache, | |
5729 | tdep->ppc_gp0_regnum + PPC_RT (insn)); | |
5730 | if (PPC_BIT (insn, 31)) | |
5731 | record_full_arch_list_add_reg (regcache, | |
5732 | tdep->ppc_gp0_regnum + PPC_RA (insn)); | |
5733 | break; | |
5734 | ||
5735 | case 59: | |
5736 | if (ppc_process_record_op59 (gdbarch, regcache, addr, insn) != 0) | |
5737 | return -1; | |
5738 | break; | |
5739 | ||
5740 | case 60: | |
5741 | if (ppc_process_record_op60 (gdbarch, regcache, addr, insn) != 0) | |
5742 | return -1; | |
5743 | break; | |
5744 | ||
6ec2b213 EBM |
5745 | case 61: |
5746 | if (ppc_process_record_op61 (gdbarch, regcache, addr, insn) != 0) | |
5747 | return -1; | |
5748 | break; | |
5749 | ||
b4cdae6f WW |
5750 | case 62: /* Store Doubleword */ |
5751 | /* Store Doubleword with Update */ | |
5752 | /* Store Quadword with Update */ | |
5753 | { | |
5754 | ULONGEST addr = 0; | |
5755 | int size; | |
5756 | int sub2 = PPC_FIELD (insn, 30, 2); | |
5757 | ||
6ec2b213 | 5758 | if (sub2 > 2) |
b4cdae6f WW |
5759 | goto UNKNOWN_OP; |
5760 | ||
5761 | if (PPC_RA (insn) != 0) | |
5762 | regcache_raw_read_unsigned (regcache, | |
5763 | tdep->ppc_gp0_regnum + PPC_RA (insn), | |
5764 | &addr); | |
5765 | ||
6ec2b213 | 5766 | size = (sub2 == 2) ? 16 : 8; |
b4cdae6f WW |
5767 | |
5768 | addr += PPC_DS (insn) << 2; | |
5769 | record_full_arch_list_add_mem (addr, size); | |
5770 | ||
5771 | if (op6 == 62 && sub2 == 1) | |
5772 | record_full_arch_list_add_reg (regcache, | |
5773 | tdep->ppc_gp0_regnum + | |
5774 | PPC_RA (insn)); | |
5775 | ||
5776 | break; | |
5777 | } | |
5778 | ||
5779 | case 63: | |
5780 | if (ppc_process_record_op63 (gdbarch, regcache, addr, insn) != 0) | |
5781 | return -1; | |
5782 | break; | |
5783 | ||
5784 | default: | |
5785 | UNKNOWN_OP: | |
810c1026 WW |
5786 | fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x " |
5787 | "at %s, %d.\n", insn, paddress (gdbarch, addr), op6); | |
b4cdae6f WW |
5788 | return -1; |
5789 | } | |
5790 | ||
5791 | if (record_full_arch_list_add_reg (regcache, PPC_PC_REGNUM)) | |
5792 | return -1; | |
5793 | if (record_full_arch_list_add_end ()) | |
5794 | return -1; | |
5795 | return 0; | |
5796 | } | |
5797 | ||
7a78ae4e ND |
5798 | /* Initialize the current architecture based on INFO. If possible, re-use an |
5799 | architecture from ARCHES, which is a list of architectures already created | |
5800 | during this debugging session. | |
c906108c | 5801 | |
7a78ae4e | 5802 | Called e.g. at program startup, when reading a core file, and when reading |
64366f1c | 5803 | a binary file. */ |
c906108c | 5804 | |
7a78ae4e ND |
5805 | static struct gdbarch * |
5806 | rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
5807 | { | |
5808 | struct gdbarch *gdbarch; | |
5809 | struct gdbarch_tdep *tdep; | |
7cc46491 | 5810 | int wordsize, from_xcoff_exec, from_elf_exec; |
7a78ae4e ND |
5811 | enum bfd_architecture arch; |
5812 | unsigned long mach; | |
5813 | bfd abfd; | |
55eddb0f DJ |
5814 | enum auto_boolean soft_float_flag = powerpc_soft_float_global; |
5815 | int soft_float; | |
ed0f4273 | 5816 | enum powerpc_long_double_abi long_double_abi = POWERPC_LONG_DOUBLE_AUTO; |
55eddb0f | 5817 | enum powerpc_vector_abi vector_abi = powerpc_vector_abi_global; |
cd453cd0 | 5818 | enum powerpc_elf_abi elf_abi = POWERPC_ELF_AUTO; |
604c2f83 LM |
5819 | int have_fpu = 1, have_spe = 0, have_mq = 0, have_altivec = 0, have_dfp = 0, |
5820 | have_vsx = 0; | |
7cc46491 DJ |
5821 | int tdesc_wordsize = -1; |
5822 | const struct target_desc *tdesc = info.target_desc; | |
5823 | struct tdesc_arch_data *tdesc_data = NULL; | |
f949c649 | 5824 | int num_pseudoregs = 0; |
604c2f83 | 5825 | int cur_reg; |
7a78ae4e | 5826 | |
f4d9bade UW |
5827 | /* INFO may refer to a binary that is not of the PowerPC architecture, |
5828 | e.g. when debugging a stand-alone SPE executable on a Cell/B.E. system. | |
5829 | In this case, we must not attempt to infer properties of the (PowerPC | |
5830 | side) of the target system from properties of that executable. Trust | |
5831 | the target description instead. */ | |
5832 | if (info.abfd | |
5833 | && bfd_get_arch (info.abfd) != bfd_arch_powerpc | |
5834 | && bfd_get_arch (info.abfd) != bfd_arch_rs6000) | |
5835 | info.abfd = NULL; | |
5836 | ||
9aa1e687 | 5837 | from_xcoff_exec = info.abfd && info.abfd->format == bfd_object && |
7a78ae4e ND |
5838 | bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour; |
5839 | ||
9aa1e687 KB |
5840 | from_elf_exec = info.abfd && info.abfd->format == bfd_object && |
5841 | bfd_get_flavour (info.abfd) == bfd_target_elf_flavour; | |
5842 | ||
e712c1cf | 5843 | /* Check word size. If INFO is from a binary file, infer it from |
64366f1c | 5844 | that, else choose a likely default. */ |
9aa1e687 | 5845 | if (from_xcoff_exec) |
c906108c | 5846 | { |
11ed25ac | 5847 | if (bfd_xcoff_is_xcoff64 (info.abfd)) |
7a78ae4e ND |
5848 | wordsize = 8; |
5849 | else | |
5850 | wordsize = 4; | |
c906108c | 5851 | } |
9aa1e687 KB |
5852 | else if (from_elf_exec) |
5853 | { | |
5854 | if (elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
5855 | wordsize = 8; | |
5856 | else | |
5857 | wordsize = 4; | |
5858 | } | |
7cc46491 DJ |
5859 | else if (tdesc_has_registers (tdesc)) |
5860 | wordsize = -1; | |
c906108c | 5861 | else |
7a78ae4e | 5862 | { |
27b15785 | 5863 | if (info.bfd_arch_info != NULL && info.bfd_arch_info->bits_per_word != 0) |
16d8013c JB |
5864 | wordsize = (info.bfd_arch_info->bits_per_word |
5865 | / info.bfd_arch_info->bits_per_byte); | |
27b15785 KB |
5866 | else |
5867 | wordsize = 4; | |
7a78ae4e | 5868 | } |
c906108c | 5869 | |
475bbd17 JB |
5870 | /* Get the architecture and machine from the BFD. */ |
5871 | arch = info.bfd_arch_info->arch; | |
5872 | mach = info.bfd_arch_info->mach; | |
5bf1c677 EZ |
5873 | |
5874 | /* For e500 executables, the apuinfo section is of help here. Such | |
5875 | section contains the identifier and revision number of each | |
5876 | Application-specific Processing Unit that is present on the | |
5877 | chip. The content of the section is determined by the assembler | |
5878 | which looks at each instruction and determines which unit (and | |
74af9197 NF |
5879 | which version of it) can execute it. Grovel through the section |
5880 | looking for relevant e500 APUs. */ | |
5bf1c677 | 5881 | |
74af9197 | 5882 | if (bfd_uses_spe_extensions (info.abfd)) |
5bf1c677 | 5883 | { |
74af9197 NF |
5884 | arch = info.bfd_arch_info->arch; |
5885 | mach = bfd_mach_ppc_e500; | |
5886 | bfd_default_set_arch_mach (&abfd, arch, mach); | |
5887 | info.bfd_arch_info = bfd_get_arch_info (&abfd); | |
5bf1c677 EZ |
5888 | } |
5889 | ||
7cc46491 DJ |
5890 | /* Find a default target description which describes our register |
5891 | layout, if we do not already have one. */ | |
5892 | if (! tdesc_has_registers (tdesc)) | |
5893 | { | |
5894 | const struct variant *v; | |
5895 | ||
5896 | /* Choose variant. */ | |
5897 | v = find_variant_by_arch (arch, mach); | |
5898 | if (!v) | |
5899 | return NULL; | |
5900 | ||
5901 | tdesc = *v->tdesc; | |
5902 | } | |
5903 | ||
5904 | gdb_assert (tdesc_has_registers (tdesc)); | |
5905 | ||
5906 | /* Check any target description for validity. */ | |
5907 | if (tdesc_has_registers (tdesc)) | |
5908 | { | |
5909 | static const char *const gprs[] = { | |
5910 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
5911 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
5912 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
5913 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" | |
5914 | }; | |
7cc46491 DJ |
5915 | const struct tdesc_feature *feature; |
5916 | int i, valid_p; | |
5917 | static const char *const msr_names[] = { "msr", "ps" }; | |
5918 | static const char *const cr_names[] = { "cr", "cnd" }; | |
5919 | static const char *const ctr_names[] = { "ctr", "cnt" }; | |
5920 | ||
5921 | feature = tdesc_find_feature (tdesc, | |
5922 | "org.gnu.gdb.power.core"); | |
5923 | if (feature == NULL) | |
5924 | return NULL; | |
5925 | ||
5926 | tdesc_data = tdesc_data_alloc (); | |
5927 | ||
5928 | valid_p = 1; | |
5929 | for (i = 0; i < ppc_num_gprs; i++) | |
5930 | valid_p &= tdesc_numbered_register (feature, tdesc_data, i, gprs[i]); | |
5931 | valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_PC_REGNUM, | |
5932 | "pc"); | |
5933 | valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_LR_REGNUM, | |
5934 | "lr"); | |
5935 | valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_XER_REGNUM, | |
5936 | "xer"); | |
5937 | ||
5938 | /* Allow alternate names for these registers, to accomodate GDB's | |
5939 | historic naming. */ | |
5940 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data, | |
5941 | PPC_MSR_REGNUM, msr_names); | |
5942 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data, | |
5943 | PPC_CR_REGNUM, cr_names); | |
5944 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data, | |
5945 | PPC_CTR_REGNUM, ctr_names); | |
5946 | ||
5947 | if (!valid_p) | |
5948 | { | |
5949 | tdesc_data_cleanup (tdesc_data); | |
5950 | return NULL; | |
5951 | } | |
5952 | ||
5953 | have_mq = tdesc_numbered_register (feature, tdesc_data, PPC_MQ_REGNUM, | |
5954 | "mq"); | |
5955 | ||
5956 | tdesc_wordsize = tdesc_register_size (feature, "pc") / 8; | |
5957 | if (wordsize == -1) | |
5958 | wordsize = tdesc_wordsize; | |
5959 | ||
5960 | feature = tdesc_find_feature (tdesc, | |
5961 | "org.gnu.gdb.power.fpu"); | |
5962 | if (feature != NULL) | |
5963 | { | |
5964 | static const char *const fprs[] = { | |
5965 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
5966 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
5967 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
5968 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31" | |
5969 | }; | |
5970 | valid_p = 1; | |
5971 | for (i = 0; i < ppc_num_fprs; i++) | |
5972 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5973 | PPC_F0_REGNUM + i, fprs[i]); | |
5974 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
5975 | PPC_FPSCR_REGNUM, "fpscr"); | |
5976 | ||
5977 | if (!valid_p) | |
5978 | { | |
5979 | tdesc_data_cleanup (tdesc_data); | |
5980 | return NULL; | |
5981 | } | |
5982 | have_fpu = 1; | |
0fb2aaa1 PFC |
5983 | |
5984 | /* The fpscr register was expanded in isa 2.05 to 64 bits | |
5985 | along with the addition of the decimal floating point | |
5986 | facility. */ | |
5987 | if (tdesc_register_size (feature, "fpscr") > 32) | |
5988 | have_dfp = 1; | |
7cc46491 DJ |
5989 | } |
5990 | else | |
5991 | have_fpu = 0; | |
5992 | ||
5993 | feature = tdesc_find_feature (tdesc, | |
5994 | "org.gnu.gdb.power.altivec"); | |
5995 | if (feature != NULL) | |
5996 | { | |
5997 | static const char *const vector_regs[] = { | |
5998 | "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7", | |
5999 | "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15", | |
6000 | "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23", | |
6001 | "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31" | |
6002 | }; | |
6003 | ||
6004 | valid_p = 1; | |
6005 | for (i = 0; i < ppc_num_gprs; i++) | |
6006 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
6007 | PPC_VR0_REGNUM + i, | |
6008 | vector_regs[i]); | |
6009 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
6010 | PPC_VSCR_REGNUM, "vscr"); | |
6011 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
6012 | PPC_VRSAVE_REGNUM, "vrsave"); | |
6013 | ||
6014 | if (have_spe || !valid_p) | |
6015 | { | |
6016 | tdesc_data_cleanup (tdesc_data); | |
6017 | return NULL; | |
6018 | } | |
6019 | have_altivec = 1; | |
6020 | } | |
6021 | else | |
6022 | have_altivec = 0; | |
6023 | ||
604c2f83 LM |
6024 | /* Check for POWER7 VSX registers support. */ |
6025 | feature = tdesc_find_feature (tdesc, | |
6026 | "org.gnu.gdb.power.vsx"); | |
6027 | ||
6028 | if (feature != NULL) | |
6029 | { | |
6030 | static const char *const vsx_regs[] = { | |
6031 | "vs0h", "vs1h", "vs2h", "vs3h", "vs4h", "vs5h", | |
6032 | "vs6h", "vs7h", "vs8h", "vs9h", "vs10h", "vs11h", | |
6033 | "vs12h", "vs13h", "vs14h", "vs15h", "vs16h", "vs17h", | |
6034 | "vs18h", "vs19h", "vs20h", "vs21h", "vs22h", "vs23h", | |
6035 | "vs24h", "vs25h", "vs26h", "vs27h", "vs28h", "vs29h", | |
6036 | "vs30h", "vs31h" | |
6037 | }; | |
6038 | ||
6039 | valid_p = 1; | |
6040 | ||
6041 | for (i = 0; i < ppc_num_vshrs; i++) | |
6042 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
6043 | PPC_VSR0_UPPER_REGNUM + i, | |
6044 | vsx_regs[i]); | |
6045 | if (!valid_p) | |
6046 | { | |
6047 | tdesc_data_cleanup (tdesc_data); | |
6048 | return NULL; | |
6049 | } | |
6050 | ||
6051 | have_vsx = 1; | |
6052 | } | |
6053 | else | |
6054 | have_vsx = 0; | |
6055 | ||
7cc46491 DJ |
6056 | /* On machines supporting the SPE APU, the general-purpose registers |
6057 | are 64 bits long. There are SIMD vector instructions to treat them | |
6058 | as pairs of floats, but the rest of the instruction set treats them | |
6059 | as 32-bit registers, and only operates on their lower halves. | |
6060 | ||
6061 | In the GDB regcache, we treat their high and low halves as separate | |
6062 | registers. The low halves we present as the general-purpose | |
6063 | registers, and then we have pseudo-registers that stitch together | |
6064 | the upper and lower halves and present them as pseudo-registers. | |
6065 | ||
6066 | Thus, the target description is expected to supply the upper | |
6067 | halves separately. */ | |
6068 | ||
6069 | feature = tdesc_find_feature (tdesc, | |
6070 | "org.gnu.gdb.power.spe"); | |
6071 | if (feature != NULL) | |
6072 | { | |
6073 | static const char *const upper_spe[] = { | |
6074 | "ev0h", "ev1h", "ev2h", "ev3h", | |
6075 | "ev4h", "ev5h", "ev6h", "ev7h", | |
6076 | "ev8h", "ev9h", "ev10h", "ev11h", | |
6077 | "ev12h", "ev13h", "ev14h", "ev15h", | |
6078 | "ev16h", "ev17h", "ev18h", "ev19h", | |
6079 | "ev20h", "ev21h", "ev22h", "ev23h", | |
6080 | "ev24h", "ev25h", "ev26h", "ev27h", | |
6081 | "ev28h", "ev29h", "ev30h", "ev31h" | |
6082 | }; | |
6083 | ||
6084 | valid_p = 1; | |
6085 | for (i = 0; i < ppc_num_gprs; i++) | |
6086 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
6087 | PPC_SPE_UPPER_GP0_REGNUM + i, | |
6088 | upper_spe[i]); | |
6089 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
6090 | PPC_SPE_ACC_REGNUM, "acc"); | |
6091 | valid_p &= tdesc_numbered_register (feature, tdesc_data, | |
6092 | PPC_SPE_FSCR_REGNUM, "spefscr"); | |
6093 | ||
6094 | if (have_mq || have_fpu || !valid_p) | |
6095 | { | |
6096 | tdesc_data_cleanup (tdesc_data); | |
6097 | return NULL; | |
6098 | } | |
6099 | have_spe = 1; | |
6100 | } | |
6101 | else | |
6102 | have_spe = 0; | |
6103 | } | |
6104 | ||
6105 | /* If we have a 64-bit binary on a 32-bit target, complain. Also | |
6106 | complain for a 32-bit binary on a 64-bit target; we do not yet | |
6107 | support that. For instance, the 32-bit ABI routines expect | |
6108 | 32-bit GPRs. | |
6109 | ||
6110 | As long as there isn't an explicit target description, we'll | |
6111 | choose one based on the BFD architecture and get a word size | |
6112 | matching the binary (probably powerpc:common or | |
6113 | powerpc:common64). So there is only trouble if a 64-bit target | |
6114 | supplies a 64-bit description while debugging a 32-bit | |
6115 | binary. */ | |
6116 | if (tdesc_wordsize != -1 && tdesc_wordsize != wordsize) | |
6117 | { | |
6118 | tdesc_data_cleanup (tdesc_data); | |
6119 | return NULL; | |
6120 | } | |
6121 | ||
55eddb0f | 6122 | #ifdef HAVE_ELF |
cd453cd0 UW |
6123 | if (from_elf_exec) |
6124 | { | |
6125 | switch (elf_elfheader (info.abfd)->e_flags & EF_PPC64_ABI) | |
6126 | { | |
6127 | case 1: | |
6128 | elf_abi = POWERPC_ELF_V1; | |
6129 | break; | |
6130 | case 2: | |
6131 | elf_abi = POWERPC_ELF_V2; | |
6132 | break; | |
6133 | default: | |
6134 | break; | |
6135 | } | |
6136 | } | |
6137 | ||
55eddb0f DJ |
6138 | if (soft_float_flag == AUTO_BOOLEAN_AUTO && from_elf_exec) |
6139 | { | |
6140 | switch (bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU, | |
ed0f4273 | 6141 | Tag_GNU_Power_ABI_FP) & 3) |
55eddb0f DJ |
6142 | { |
6143 | case 1: | |
6144 | soft_float_flag = AUTO_BOOLEAN_FALSE; | |
6145 | break; | |
6146 | case 2: | |
6147 | soft_float_flag = AUTO_BOOLEAN_TRUE; | |
6148 | break; | |
6149 | default: | |
6150 | break; | |
6151 | } | |
6152 | } | |
6153 | ||
ed0f4273 UW |
6154 | if (long_double_abi == POWERPC_LONG_DOUBLE_AUTO && from_elf_exec) |
6155 | { | |
6156 | switch (bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU, | |
6157 | Tag_GNU_Power_ABI_FP) >> 2) | |
6158 | { | |
6159 | case 1: | |
6160 | long_double_abi = POWERPC_LONG_DOUBLE_IBM128; | |
6161 | break; | |
6162 | case 3: | |
6163 | long_double_abi = POWERPC_LONG_DOUBLE_IEEE128; | |
6164 | break; | |
6165 | default: | |
6166 | break; | |
6167 | } | |
6168 | } | |
6169 | ||
55eddb0f DJ |
6170 | if (vector_abi == POWERPC_VEC_AUTO && from_elf_exec) |
6171 | { | |
6172 | switch (bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU, | |
6173 | Tag_GNU_Power_ABI_Vector)) | |
6174 | { | |
6175 | case 1: | |
6176 | vector_abi = POWERPC_VEC_GENERIC; | |
6177 | break; | |
6178 | case 2: | |
6179 | vector_abi = POWERPC_VEC_ALTIVEC; | |
6180 | break; | |
6181 | case 3: | |
6182 | vector_abi = POWERPC_VEC_SPE; | |
6183 | break; | |
6184 | default: | |
6185 | break; | |
6186 | } | |
6187 | } | |
6188 | #endif | |
6189 | ||
cd453cd0 UW |
6190 | /* At this point, the only supported ELF-based 64-bit little-endian |
6191 | operating system is GNU/Linux, and this uses the ELFv2 ABI by | |
6192 | default. All other supported ELF-based operating systems use the | |
6193 | ELFv1 ABI by default. Therefore, if the ABI marker is missing, | |
6194 | e.g. because we run a legacy binary, or have attached to a process | |
6195 | and have not found any associated binary file, set the default | |
6196 | according to this heuristic. */ | |
6197 | if (elf_abi == POWERPC_ELF_AUTO) | |
6198 | { | |
6199 | if (wordsize == 8 && info.byte_order == BFD_ENDIAN_LITTLE) | |
6200 | elf_abi = POWERPC_ELF_V2; | |
6201 | else | |
6202 | elf_abi = POWERPC_ELF_V1; | |
6203 | } | |
6204 | ||
55eddb0f DJ |
6205 | if (soft_float_flag == AUTO_BOOLEAN_TRUE) |
6206 | soft_float = 1; | |
6207 | else if (soft_float_flag == AUTO_BOOLEAN_FALSE) | |
6208 | soft_float = 0; | |
6209 | else | |
6210 | soft_float = !have_fpu; | |
6211 | ||
6212 | /* If we have a hard float binary or setting but no floating point | |
6213 | registers, downgrade to soft float anyway. We're still somewhat | |
6214 | useful in this scenario. */ | |
6215 | if (!soft_float && !have_fpu) | |
6216 | soft_float = 1; | |
6217 | ||
6218 | /* Similarly for vector registers. */ | |
6219 | if (vector_abi == POWERPC_VEC_ALTIVEC && !have_altivec) | |
6220 | vector_abi = POWERPC_VEC_GENERIC; | |
6221 | ||
6222 | if (vector_abi == POWERPC_VEC_SPE && !have_spe) | |
6223 | vector_abi = POWERPC_VEC_GENERIC; | |
6224 | ||
6225 | if (vector_abi == POWERPC_VEC_AUTO) | |
6226 | { | |
6227 | if (have_altivec) | |
6228 | vector_abi = POWERPC_VEC_ALTIVEC; | |
6229 | else if (have_spe) | |
6230 | vector_abi = POWERPC_VEC_SPE; | |
6231 | else | |
6232 | vector_abi = POWERPC_VEC_GENERIC; | |
6233 | } | |
6234 | ||
6235 | /* Do not limit the vector ABI based on available hardware, since we | |
6236 | do not yet know what hardware we'll decide we have. Yuck! FIXME! */ | |
6237 | ||
7cc46491 DJ |
6238 | /* Find a candidate among extant architectures. */ |
6239 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
6240 | arches != NULL; | |
6241 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
6242 | { | |
6243 | /* Word size in the various PowerPC bfd_arch_info structs isn't | |
6244 | meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform | |
6245 | separate word size check. */ | |
6246 | tdep = gdbarch_tdep (arches->gdbarch); | |
cd453cd0 UW |
6247 | if (tdep && tdep->elf_abi != elf_abi) |
6248 | continue; | |
55eddb0f DJ |
6249 | if (tdep && tdep->soft_float != soft_float) |
6250 | continue; | |
ed0f4273 UW |
6251 | if (tdep && tdep->long_double_abi != long_double_abi) |
6252 | continue; | |
55eddb0f DJ |
6253 | if (tdep && tdep->vector_abi != vector_abi) |
6254 | continue; | |
7cc46491 DJ |
6255 | if (tdep && tdep->wordsize == wordsize) |
6256 | { | |
6257 | if (tdesc_data != NULL) | |
6258 | tdesc_data_cleanup (tdesc_data); | |
6259 | return arches->gdbarch; | |
6260 | } | |
6261 | } | |
6262 | ||
6263 | /* None found, create a new architecture from INFO, whose bfd_arch_info | |
6264 | validity depends on the source: | |
6265 | - executable useless | |
6266 | - rs6000_host_arch() good | |
6267 | - core file good | |
6268 | - "set arch" trust blindly | |
6269 | - GDB startup useless but harmless */ | |
6270 | ||
fc270c35 | 6271 | tdep = XCNEW (struct gdbarch_tdep); |
7cc46491 | 6272 | tdep->wordsize = wordsize; |
cd453cd0 | 6273 | tdep->elf_abi = elf_abi; |
55eddb0f | 6274 | tdep->soft_float = soft_float; |
ed0f4273 | 6275 | tdep->long_double_abi = long_double_abi; |
55eddb0f | 6276 | tdep->vector_abi = vector_abi; |
7cc46491 | 6277 | |
7a78ae4e | 6278 | gdbarch = gdbarch_alloc (&info, tdep); |
7a78ae4e | 6279 | |
7cc46491 DJ |
6280 | tdep->ppc_gp0_regnum = PPC_R0_REGNUM; |
6281 | tdep->ppc_toc_regnum = PPC_R0_REGNUM + 2; | |
6282 | tdep->ppc_ps_regnum = PPC_MSR_REGNUM; | |
6283 | tdep->ppc_cr_regnum = PPC_CR_REGNUM; | |
6284 | tdep->ppc_lr_regnum = PPC_LR_REGNUM; | |
6285 | tdep->ppc_ctr_regnum = PPC_CTR_REGNUM; | |
6286 | tdep->ppc_xer_regnum = PPC_XER_REGNUM; | |
6287 | tdep->ppc_mq_regnum = have_mq ? PPC_MQ_REGNUM : -1; | |
6288 | ||
6289 | tdep->ppc_fp0_regnum = have_fpu ? PPC_F0_REGNUM : -1; | |
6290 | tdep->ppc_fpscr_regnum = have_fpu ? PPC_FPSCR_REGNUM : -1; | |
604c2f83 | 6291 | tdep->ppc_vsr0_upper_regnum = have_vsx ? PPC_VSR0_UPPER_REGNUM : -1; |
7cc46491 DJ |
6292 | tdep->ppc_vr0_regnum = have_altivec ? PPC_VR0_REGNUM : -1; |
6293 | tdep->ppc_vrsave_regnum = have_altivec ? PPC_VRSAVE_REGNUM : -1; | |
6294 | tdep->ppc_ev0_upper_regnum = have_spe ? PPC_SPE_UPPER_GP0_REGNUM : -1; | |
6295 | tdep->ppc_acc_regnum = have_spe ? PPC_SPE_ACC_REGNUM : -1; | |
6296 | tdep->ppc_spefscr_regnum = have_spe ? PPC_SPE_FSCR_REGNUM : -1; | |
6297 | ||
6298 | set_gdbarch_pc_regnum (gdbarch, PPC_PC_REGNUM); | |
6299 | set_gdbarch_sp_regnum (gdbarch, PPC_R0_REGNUM + 1); | |
7cc46491 | 6300 | set_gdbarch_fp0_regnum (gdbarch, tdep->ppc_fp0_regnum); |
9f643768 | 6301 | set_gdbarch_register_sim_regno (gdbarch, rs6000_register_sim_regno); |
7cc46491 DJ |
6302 | |
6303 | /* The XML specification for PowerPC sensibly calls the MSR "msr". | |
6304 | GDB traditionally called it "ps", though, so let GDB add an | |
6305 | alias. */ | |
6306 | set_gdbarch_ps_regnum (gdbarch, tdep->ppc_ps_regnum); | |
6307 | ||
4a7622d1 | 6308 | if (wordsize == 8) |
05580c65 | 6309 | set_gdbarch_return_value (gdbarch, ppc64_sysv_abi_return_value); |
afd48b75 | 6310 | else |
4a7622d1 | 6311 | set_gdbarch_return_value (gdbarch, ppc_sysv_abi_return_value); |
c8001721 | 6312 | |
baffbae0 JB |
6313 | /* Set lr_frame_offset. */ |
6314 | if (wordsize == 8) | |
6315 | tdep->lr_frame_offset = 16; | |
baffbae0 | 6316 | else |
4a7622d1 | 6317 | tdep->lr_frame_offset = 4; |
baffbae0 | 6318 | |
604c2f83 | 6319 | if (have_spe || have_dfp || have_vsx) |
7cc46491 | 6320 | { |
f949c649 | 6321 | set_gdbarch_pseudo_register_read (gdbarch, rs6000_pseudo_register_read); |
0df8b418 MS |
6322 | set_gdbarch_pseudo_register_write (gdbarch, |
6323 | rs6000_pseudo_register_write); | |
2a2fa07b MK |
6324 | set_gdbarch_ax_pseudo_register_collect (gdbarch, |
6325 | rs6000_ax_pseudo_register_collect); | |
7cc46491 | 6326 | } |
1fcc0bb8 | 6327 | |
a67914de MK |
6328 | set_gdbarch_gen_return_address (gdbarch, rs6000_gen_return_address); |
6329 | ||
e0d24f8d WZ |
6330 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); |
6331 | ||
5a9e69ba | 6332 | set_gdbarch_num_regs (gdbarch, PPC_NUM_REGS); |
f949c649 TJB |
6333 | |
6334 | if (have_spe) | |
6335 | num_pseudoregs += 32; | |
6336 | if (have_dfp) | |
6337 | num_pseudoregs += 16; | |
604c2f83 LM |
6338 | if (have_vsx) |
6339 | /* Include both VSX and Extended FP registers. */ | |
6340 | num_pseudoregs += 96; | |
f949c649 TJB |
6341 | |
6342 | set_gdbarch_num_pseudo_regs (gdbarch, num_pseudoregs); | |
7a78ae4e ND |
6343 | |
6344 | set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT); | |
6345 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); | |
6346 | set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
6347 | set_gdbarch_long_bit (gdbarch, wordsize * TARGET_CHAR_BIT); | |
6348 | set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
6349 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
6350 | set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
4a7622d1 | 6351 | set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT); |
4e409299 | 6352 | set_gdbarch_char_signed (gdbarch, 0); |
7a78ae4e | 6353 | |
11269d7e | 6354 | set_gdbarch_frame_align (gdbarch, rs6000_frame_align); |
4a7622d1 | 6355 | if (wordsize == 8) |
8b148df9 AC |
6356 | /* PPC64 SYSV. */ |
6357 | set_gdbarch_frame_red_zone_size (gdbarch, 288); | |
7a78ae4e | 6358 | |
691d145a JB |
6359 | set_gdbarch_convert_register_p (gdbarch, rs6000_convert_register_p); |
6360 | set_gdbarch_register_to_value (gdbarch, rs6000_register_to_value); | |
6361 | set_gdbarch_value_to_register (gdbarch, rs6000_value_to_register); | |
6362 | ||
18ed0c4e JB |
6363 | set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_stab_reg_to_regnum); |
6364 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rs6000_dwarf2_reg_to_regnum); | |
d217aaed | 6365 | |
4a7622d1 | 6366 | if (wordsize == 4) |
77b2b6d4 | 6367 | set_gdbarch_push_dummy_call (gdbarch, ppc_sysv_abi_push_dummy_call); |
4a7622d1 | 6368 | else if (wordsize == 8) |
8be9034a | 6369 | set_gdbarch_push_dummy_call (gdbarch, ppc64_sysv_abi_push_dummy_call); |
7a78ae4e | 6370 | |
7a78ae4e | 6371 | set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue); |
c9cf6e20 | 6372 | set_gdbarch_stack_frame_destroyed_p (gdbarch, rs6000_stack_frame_destroyed_p); |
8ab3d180 | 6373 | set_gdbarch_skip_main_prologue (gdbarch, rs6000_skip_main_prologue); |
0d1243d9 | 6374 | |
7a78ae4e | 6375 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
04180708 YQ |
6376 | |
6377 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, | |
6378 | rs6000_breakpoint::kind_from_pc); | |
6379 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, | |
6380 | rs6000_breakpoint::bp_from_kind); | |
7a78ae4e | 6381 | |
203c3895 | 6382 | /* The value of symbols of type N_SO and N_FUN maybe null when |
0df8b418 | 6383 | it shouldn't be. */ |
203c3895 UW |
6384 | set_gdbarch_sofun_address_maybe_missing (gdbarch, 1); |
6385 | ||
ce5eab59 | 6386 | /* Handles single stepping of atomic sequences. */ |
4a7622d1 | 6387 | set_gdbarch_software_single_step (gdbarch, ppc_deal_with_atomic_sequence); |
ce5eab59 | 6388 | |
0df8b418 | 6389 | /* Not sure on this. FIXMEmgo */ |
7a78ae4e ND |
6390 | set_gdbarch_frame_args_skip (gdbarch, 8); |
6391 | ||
143985b7 AF |
6392 | /* Helpers for function argument information. */ |
6393 | set_gdbarch_fetch_pointer_argument (gdbarch, rs6000_fetch_pointer_argument); | |
6394 | ||
6f7f3f0d UW |
6395 | /* Trampoline. */ |
6396 | set_gdbarch_in_solib_return_trampoline | |
6397 | (gdbarch, rs6000_in_solib_return_trampoline); | |
6398 | set_gdbarch_skip_trampoline_code (gdbarch, rs6000_skip_trampoline_code); | |
6399 | ||
4fc771b8 | 6400 | /* Hook in the DWARF CFI frame unwinder. */ |
1af5d7ce | 6401 | dwarf2_append_unwinders (gdbarch); |
4fc771b8 DJ |
6402 | dwarf2_frame_set_adjust_regnum (gdbarch, rs6000_adjust_frame_regnum); |
6403 | ||
9274a07c LM |
6404 | /* Frame handling. */ |
6405 | dwarf2_frame_set_init_reg (gdbarch, ppc_dwarf2_frame_init_reg); | |
6406 | ||
2454a024 UW |
6407 | /* Setup displaced stepping. */ |
6408 | set_gdbarch_displaced_step_copy_insn (gdbarch, | |
7f03bd92 | 6409 | ppc_displaced_step_copy_insn); |
99e40580 UW |
6410 | set_gdbarch_displaced_step_hw_singlestep (gdbarch, |
6411 | ppc_displaced_step_hw_singlestep); | |
2454a024 | 6412 | set_gdbarch_displaced_step_fixup (gdbarch, ppc_displaced_step_fixup); |
2454a024 UW |
6413 | set_gdbarch_displaced_step_location (gdbarch, |
6414 | displaced_step_at_entry_point); | |
6415 | ||
6416 | set_gdbarch_max_insn_length (gdbarch, PPC_INSN_SIZE); | |
6417 | ||
7b112f9c | 6418 | /* Hook in ABI-specific overrides, if they have been registered. */ |
8a4c2d24 | 6419 | info.target_desc = tdesc; |
0dba2a6c | 6420 | info.tdesc_data = tdesc_data; |
4be87837 | 6421 | gdbarch_init_osabi (info, gdbarch); |
7b112f9c | 6422 | |
61a65099 KB |
6423 | switch (info.osabi) |
6424 | { | |
f5aecab8 | 6425 | case GDB_OSABI_LINUX: |
1736a7bd | 6426 | case GDB_OSABI_NETBSD: |
61a65099 | 6427 | case GDB_OSABI_UNKNOWN: |
61a65099 | 6428 | set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc); |
2608dbf8 | 6429 | frame_unwind_append_unwinder (gdbarch, &rs6000_epilogue_frame_unwind); |
1af5d7ce UW |
6430 | frame_unwind_append_unwinder (gdbarch, &rs6000_frame_unwind); |
6431 | set_gdbarch_dummy_id (gdbarch, rs6000_dummy_id); | |
61a65099 KB |
6432 | frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer); |
6433 | break; | |
6434 | default: | |
61a65099 | 6435 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); |
81332287 KB |
6436 | |
6437 | set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc); | |
2608dbf8 | 6438 | frame_unwind_append_unwinder (gdbarch, &rs6000_epilogue_frame_unwind); |
1af5d7ce UW |
6439 | frame_unwind_append_unwinder (gdbarch, &rs6000_frame_unwind); |
6440 | set_gdbarch_dummy_id (gdbarch, rs6000_dummy_id); | |
81332287 | 6441 | frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer); |
61a65099 KB |
6442 | } |
6443 | ||
7cc46491 DJ |
6444 | set_tdesc_pseudo_register_type (gdbarch, rs6000_pseudo_register_type); |
6445 | set_tdesc_pseudo_register_reggroup_p (gdbarch, | |
6446 | rs6000_pseudo_register_reggroup_p); | |
6447 | tdesc_use_registers (gdbarch, tdesc, tdesc_data); | |
6448 | ||
6449 | /* Override the normal target description method to make the SPE upper | |
6450 | halves anonymous. */ | |
6451 | set_gdbarch_register_name (gdbarch, rs6000_register_name); | |
6452 | ||
604c2f83 LM |
6453 | /* Choose register numbers for all supported pseudo-registers. */ |
6454 | tdep->ppc_ev0_regnum = -1; | |
6455 | tdep->ppc_dl0_regnum = -1; | |
6456 | tdep->ppc_vsr0_regnum = -1; | |
6457 | tdep->ppc_efpr0_regnum = -1; | |
9f643768 | 6458 | |
604c2f83 LM |
6459 | cur_reg = gdbarch_num_regs (gdbarch); |
6460 | ||
6461 | if (have_spe) | |
6462 | { | |
6463 | tdep->ppc_ev0_regnum = cur_reg; | |
6464 | cur_reg += 32; | |
6465 | } | |
6466 | if (have_dfp) | |
6467 | { | |
6468 | tdep->ppc_dl0_regnum = cur_reg; | |
6469 | cur_reg += 16; | |
6470 | } | |
6471 | if (have_vsx) | |
6472 | { | |
6473 | tdep->ppc_vsr0_regnum = cur_reg; | |
6474 | cur_reg += 64; | |
6475 | tdep->ppc_efpr0_regnum = cur_reg; | |
6476 | cur_reg += 32; | |
6477 | } | |
f949c649 | 6478 | |
604c2f83 LM |
6479 | gdb_assert (gdbarch_num_regs (gdbarch) |
6480 | + gdbarch_num_pseudo_regs (gdbarch) == cur_reg); | |
f949c649 | 6481 | |
debb1f09 JB |
6482 | /* Register the ravenscar_arch_ops. */ |
6483 | if (mach == bfd_mach_ppc_e500) | |
6484 | register_e500_ravenscar_ops (gdbarch); | |
6485 | else | |
6486 | register_ppc_ravenscar_ops (gdbarch); | |
6487 | ||
65b48a81 PB |
6488 | set_gdbarch_disassembler_options (gdbarch, &powerpc_disassembler_options); |
6489 | set_gdbarch_valid_disassembler_options (gdbarch, | |
6490 | disassembler_options_powerpc ()); | |
6491 | ||
7a78ae4e | 6492 | return gdbarch; |
c906108c SS |
6493 | } |
6494 | ||
7b112f9c | 6495 | static void |
8b164abb | 6496 | rs6000_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
7b112f9c | 6497 | { |
8b164abb | 6498 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7b112f9c JT |
6499 | |
6500 | if (tdep == NULL) | |
6501 | return; | |
6502 | ||
4be87837 | 6503 | /* FIXME: Dump gdbarch_tdep. */ |
7b112f9c JT |
6504 | } |
6505 | ||
55eddb0f DJ |
6506 | /* PowerPC-specific commands. */ |
6507 | ||
6508 | static void | |
981a3fb3 | 6509 | set_powerpc_command (const char *args, int from_tty) |
55eddb0f DJ |
6510 | { |
6511 | printf_unfiltered (_("\ | |
6512 | \"set powerpc\" must be followed by an appropriate subcommand.\n")); | |
6513 | help_list (setpowerpccmdlist, "set powerpc ", all_commands, gdb_stdout); | |
6514 | } | |
6515 | ||
6516 | static void | |
981a3fb3 | 6517 | show_powerpc_command (const char *args, int from_tty) |
55eddb0f DJ |
6518 | { |
6519 | cmd_show_list (showpowerpccmdlist, from_tty, ""); | |
6520 | } | |
6521 | ||
6522 | static void | |
eb4c3f4a | 6523 | powerpc_set_soft_float (const char *args, int from_tty, |
55eddb0f DJ |
6524 | struct cmd_list_element *c) |
6525 | { | |
6526 | struct gdbarch_info info; | |
6527 | ||
6528 | /* Update the architecture. */ | |
6529 | gdbarch_info_init (&info); | |
6530 | if (!gdbarch_update_p (info)) | |
9b20d036 | 6531 | internal_error (__FILE__, __LINE__, _("could not update architecture")); |
55eddb0f DJ |
6532 | } |
6533 | ||
6534 | static void | |
eb4c3f4a | 6535 | powerpc_set_vector_abi (const char *args, int from_tty, |
55eddb0f DJ |
6536 | struct cmd_list_element *c) |
6537 | { | |
6538 | struct gdbarch_info info; | |
570dc176 | 6539 | int vector_abi; |
55eddb0f DJ |
6540 | |
6541 | for (vector_abi = POWERPC_VEC_AUTO; | |
6542 | vector_abi != POWERPC_VEC_LAST; | |
6543 | vector_abi++) | |
6544 | if (strcmp (powerpc_vector_abi_string, | |
6545 | powerpc_vector_strings[vector_abi]) == 0) | |
6546 | { | |
aead7601 | 6547 | powerpc_vector_abi_global = (enum powerpc_vector_abi) vector_abi; |
55eddb0f DJ |
6548 | break; |
6549 | } | |
6550 | ||
6551 | if (vector_abi == POWERPC_VEC_LAST) | |
6552 | internal_error (__FILE__, __LINE__, _("Invalid vector ABI accepted: %s."), | |
6553 | powerpc_vector_abi_string); | |
6554 | ||
6555 | /* Update the architecture. */ | |
6556 | gdbarch_info_init (&info); | |
6557 | if (!gdbarch_update_p (info)) | |
9b20d036 | 6558 | internal_error (__FILE__, __LINE__, _("could not update architecture")); |
55eddb0f DJ |
6559 | } |
6560 | ||
e09342b5 TJB |
6561 | /* Show the current setting of the exact watchpoints flag. */ |
6562 | ||
6563 | static void | |
6564 | show_powerpc_exact_watchpoints (struct ui_file *file, int from_tty, | |
6565 | struct cmd_list_element *c, | |
6566 | const char *value) | |
6567 | { | |
6568 | fprintf_filtered (file, _("Use of exact watchpoints is %s.\n"), value); | |
6569 | } | |
6570 | ||
845d4708 | 6571 | /* Read a PPC instruction from memory. */ |
d78489bf AT |
6572 | |
6573 | static unsigned int | |
845d4708 | 6574 | read_insn (struct frame_info *frame, CORE_ADDR pc) |
d78489bf | 6575 | { |
845d4708 AM |
6576 | struct gdbarch *gdbarch = get_frame_arch (frame); |
6577 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
6578 | ||
6579 | return read_memory_unsigned_integer (pc, 4, byte_order); | |
d78489bf AT |
6580 | } |
6581 | ||
6582 | /* Return non-zero if the instructions at PC match the series | |
6583 | described in PATTERN, or zero otherwise. PATTERN is an array of | |
6584 | 'struct ppc_insn_pattern' objects, terminated by an entry whose | |
6585 | mask is zero. | |
6586 | ||
7433498b | 6587 | When the match is successful, fill INSNS[i] with what PATTERN[i] |
d78489bf | 6588 | matched. If PATTERN[i] is optional, and the instruction wasn't |
7433498b AM |
6589 | present, set INSNS[i] to 0 (which is not a valid PPC instruction). |
6590 | INSNS should have as many elements as PATTERN, minus the terminator. | |
6591 | Note that, if PATTERN contains optional instructions which aren't | |
6592 | present in memory, then INSNS will have holes, so INSNS[i] isn't | |
6593 | necessarily the i'th instruction in memory. */ | |
d78489bf AT |
6594 | |
6595 | int | |
845d4708 | 6596 | ppc_insns_match_pattern (struct frame_info *frame, CORE_ADDR pc, |
7433498b | 6597 | const struct ppc_insn_pattern *pattern, |
845d4708 | 6598 | unsigned int *insns) |
d78489bf AT |
6599 | { |
6600 | int i; | |
845d4708 | 6601 | unsigned int insn; |
d78489bf | 6602 | |
845d4708 | 6603 | for (i = 0, insn = 0; pattern[i].mask; i++) |
d78489bf | 6604 | { |
845d4708 AM |
6605 | if (insn == 0) |
6606 | insn = read_insn (frame, pc); | |
6607 | insns[i] = 0; | |
6608 | if ((insn & pattern[i].mask) == pattern[i].data) | |
6609 | { | |
6610 | insns[i] = insn; | |
6611 | pc += 4; | |
6612 | insn = 0; | |
6613 | } | |
6614 | else if (!pattern[i].optional) | |
d78489bf AT |
6615 | return 0; |
6616 | } | |
6617 | ||
6618 | return 1; | |
6619 | } | |
6620 | ||
6621 | /* Return the 'd' field of the d-form instruction INSN, properly | |
6622 | sign-extended. */ | |
6623 | ||
6624 | CORE_ADDR | |
6625 | ppc_insn_d_field (unsigned int insn) | |
6626 | { | |
6627 | return ((((CORE_ADDR) insn & 0xffff) ^ 0x8000) - 0x8000); | |
6628 | } | |
6629 | ||
6630 | /* Return the 'ds' field of the ds-form instruction INSN, with the two | |
6631 | zero bits concatenated at the right, and properly | |
6632 | sign-extended. */ | |
6633 | ||
6634 | CORE_ADDR | |
6635 | ppc_insn_ds_field (unsigned int insn) | |
6636 | { | |
6637 | return ((((CORE_ADDR) insn & 0xfffc) ^ 0x8000) - 0x8000); | |
6638 | } | |
6639 | ||
c906108c SS |
6640 | /* Initialization code. */ |
6641 | ||
6642 | void | |
fba45db2 | 6643 | _initialize_rs6000_tdep (void) |
c906108c | 6644 | { |
7b112f9c JT |
6645 | gdbarch_register (bfd_arch_rs6000, rs6000_gdbarch_init, rs6000_dump_tdep); |
6646 | gdbarch_register (bfd_arch_powerpc, rs6000_gdbarch_init, rs6000_dump_tdep); | |
7cc46491 DJ |
6647 | |
6648 | /* Initialize the standard target descriptions. */ | |
6649 | initialize_tdesc_powerpc_32 (); | |
7284e1be | 6650 | initialize_tdesc_powerpc_altivec32 (); |
604c2f83 | 6651 | initialize_tdesc_powerpc_vsx32 (); |
7cc46491 DJ |
6652 | initialize_tdesc_powerpc_403 (); |
6653 | initialize_tdesc_powerpc_403gc (); | |
4d09ffea | 6654 | initialize_tdesc_powerpc_405 (); |
7cc46491 DJ |
6655 | initialize_tdesc_powerpc_505 (); |
6656 | initialize_tdesc_powerpc_601 (); | |
6657 | initialize_tdesc_powerpc_602 (); | |
6658 | initialize_tdesc_powerpc_603 (); | |
6659 | initialize_tdesc_powerpc_604 (); | |
6660 | initialize_tdesc_powerpc_64 (); | |
7284e1be | 6661 | initialize_tdesc_powerpc_altivec64 (); |
604c2f83 | 6662 | initialize_tdesc_powerpc_vsx64 (); |
7cc46491 DJ |
6663 | initialize_tdesc_powerpc_7400 (); |
6664 | initialize_tdesc_powerpc_750 (); | |
6665 | initialize_tdesc_powerpc_860 (); | |
6666 | initialize_tdesc_powerpc_e500 (); | |
6667 | initialize_tdesc_rs6000 (); | |
55eddb0f DJ |
6668 | |
6669 | /* Add root prefix command for all "set powerpc"/"show powerpc" | |
6670 | commands. */ | |
6671 | add_prefix_cmd ("powerpc", no_class, set_powerpc_command, | |
6672 | _("Various PowerPC-specific commands."), | |
6673 | &setpowerpccmdlist, "set powerpc ", 0, &setlist); | |
6674 | ||
6675 | add_prefix_cmd ("powerpc", no_class, show_powerpc_command, | |
6676 | _("Various PowerPC-specific commands."), | |
6677 | &showpowerpccmdlist, "show powerpc ", 0, &showlist); | |
6678 | ||
6679 | /* Add a command to allow the user to force the ABI. */ | |
6680 | add_setshow_auto_boolean_cmd ("soft-float", class_support, | |
6681 | &powerpc_soft_float_global, | |
6682 | _("Set whether to use a soft-float ABI."), | |
6683 | _("Show whether to use a soft-float ABI."), | |
6684 | NULL, | |
6685 | powerpc_set_soft_float, NULL, | |
6686 | &setpowerpccmdlist, &showpowerpccmdlist); | |
6687 | ||
6688 | add_setshow_enum_cmd ("vector-abi", class_support, powerpc_vector_strings, | |
6689 | &powerpc_vector_abi_string, | |
6690 | _("Set the vector ABI."), | |
6691 | _("Show the vector ABI."), | |
6692 | NULL, powerpc_set_vector_abi, NULL, | |
6693 | &setpowerpccmdlist, &showpowerpccmdlist); | |
e09342b5 TJB |
6694 | |
6695 | add_setshow_boolean_cmd ("exact-watchpoints", class_support, | |
6696 | &target_exact_watchpoints, | |
6697 | _("\ | |
6698 | Set whether to use just one debug register for watchpoints on scalars."), | |
6699 | _("\ | |
6700 | Show whether to use just one debug register for watchpoints on scalars."), | |
6701 | _("\ | |
6702 | If true, GDB will use only one debug register when watching a variable of\n\ | |
6703 | scalar type, thus assuming that the variable is accessed through the address\n\ | |
6704 | of its first byte."), | |
6705 | NULL, show_powerpc_exact_watchpoints, | |
6706 | &setpowerpccmdlist, &showpowerpccmdlist); | |
c906108c | 6707 | } |