Commit | Line | Data |
---|---|---|
c906108c | 1 | /* Target-dependent code for GDB, the GNU debugger. |
7aea86e6 | 2 | |
3666a048 | 3 | Copyright (C) 1986-2021 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 10 | (at your option) any later version. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b | 17 | You should have received a copy of the GNU General Public License |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
19 | |
20 | #include "defs.h" | |
21 | #include "frame.h" | |
22 | #include "inferior.h" | |
45741a9c | 23 | #include "infrun.h" |
c906108c SS |
24 | #include "symtab.h" |
25 | #include "target.h" | |
26 | #include "gdbcore.h" | |
27 | #include "gdbcmd.h" | |
c906108c | 28 | #include "objfiles.h" |
7a78ae4e | 29 | #include "arch-utils.h" |
4e052eda | 30 | #include "regcache.h" |
d195bc9f | 31 | #include "regset.h" |
3b2ca824 | 32 | #include "target-float.h" |
fd0407d6 | 33 | #include "value.h" |
1fcc0bb8 | 34 | #include "parser-defs.h" |
4be87837 | 35 | #include "osabi.h" |
7d9b040b | 36 | #include "infcall.h" |
9f643768 JB |
37 | #include "sim-regno.h" |
38 | #include "gdb/sim-ppc.h" | |
6f072a10 | 39 | #include "reggroups.h" |
82ca8957 | 40 | #include "dwarf2/frame.h" |
7cc46491 DJ |
41 | #include "target-descriptions.h" |
42 | #include "user-regs.h" | |
b4cdae6f WW |
43 | #include "record-full.h" |
44 | #include "auxv.h" | |
7a78ae4e | 45 | |
7a78ae4e | 46 | #include "coff/internal.h" /* for libcoff.h */ |
2fccf04a | 47 | #include "libcoff.h" /* for xcoff_data */ |
11ed25ac KB |
48 | #include "coff/xcoff.h" |
49 | #include "libxcoff.h" | |
7a78ae4e | 50 | |
9aa1e687 | 51 | #include "elf-bfd.h" |
55eddb0f | 52 | #include "elf/ppc.h" |
cd453cd0 | 53 | #include "elf/ppc64.h" |
7a78ae4e | 54 | |
6ded7999 | 55 | #include "solib-svr4.h" |
9aa1e687 | 56 | #include "ppc-tdep.h" |
debb1f09 | 57 | #include "ppc-ravenscar-thread.h" |
7a78ae4e | 58 | |
a89aa300 | 59 | #include "dis-asm.h" |
338ef23d | 60 | |
61a65099 KB |
61 | #include "trad-frame.h" |
62 | #include "frame-unwind.h" | |
63 | #include "frame-base.h" | |
64 | ||
a67914de MK |
65 | #include "ax.h" |
66 | #include "ax-gdb.h" | |
325fac50 | 67 | #include <algorithm> |
a67914de | 68 | |
7cc46491 | 69 | #include "features/rs6000/powerpc-32.c" |
7284e1be | 70 | #include "features/rs6000/powerpc-altivec32.c" |
604c2f83 | 71 | #include "features/rs6000/powerpc-vsx32.c" |
7cc46491 DJ |
72 | #include "features/rs6000/powerpc-403.c" |
73 | #include "features/rs6000/powerpc-403gc.c" | |
4d09ffea | 74 | #include "features/rs6000/powerpc-405.c" |
7cc46491 DJ |
75 | #include "features/rs6000/powerpc-505.c" |
76 | #include "features/rs6000/powerpc-601.c" | |
77 | #include "features/rs6000/powerpc-602.c" | |
78 | #include "features/rs6000/powerpc-603.c" | |
79 | #include "features/rs6000/powerpc-604.c" | |
80 | #include "features/rs6000/powerpc-64.c" | |
7284e1be | 81 | #include "features/rs6000/powerpc-altivec64.c" |
604c2f83 | 82 | #include "features/rs6000/powerpc-vsx64.c" |
7cc46491 DJ |
83 | #include "features/rs6000/powerpc-7400.c" |
84 | #include "features/rs6000/powerpc-750.c" | |
85 | #include "features/rs6000/powerpc-860.c" | |
86 | #include "features/rs6000/powerpc-e500.c" | |
87 | #include "features/rs6000/rs6000.c" | |
88 | ||
5a9e69ba TJB |
89 | /* Determine if regnum is an SPE pseudo-register. */ |
90 | #define IS_SPE_PSEUDOREG(tdep, regnum) ((tdep)->ppc_ev0_regnum >= 0 \ | |
91 | && (regnum) >= (tdep)->ppc_ev0_regnum \ | |
92 | && (regnum) < (tdep)->ppc_ev0_regnum + 32) | |
93 | ||
f949c649 TJB |
94 | /* Determine if regnum is a decimal float pseudo-register. */ |
95 | #define IS_DFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_dl0_regnum >= 0 \ | |
96 | && (regnum) >= (tdep)->ppc_dl0_regnum \ | |
97 | && (regnum) < (tdep)->ppc_dl0_regnum + 16) | |
98 | ||
6f072a10 PFC |
99 | /* Determine if regnum is a "vX" alias for the raw "vrX" vector |
100 | registers. */ | |
101 | #define IS_V_ALIAS_PSEUDOREG(tdep, regnum) (\ | |
102 | (tdep)->ppc_v0_alias_regnum >= 0 \ | |
103 | && (regnum) >= (tdep)->ppc_v0_alias_regnum \ | |
104 | && (regnum) < (tdep)->ppc_v0_alias_regnum + ppc_num_vrs) | |
105 | ||
604c2f83 LM |
106 | /* Determine if regnum is a POWER7 VSX register. */ |
107 | #define IS_VSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_vsr0_regnum >= 0 \ | |
108 | && (regnum) >= (tdep)->ppc_vsr0_regnum \ | |
109 | && (regnum) < (tdep)->ppc_vsr0_regnum + ppc_num_vsrs) | |
110 | ||
111 | /* Determine if regnum is a POWER7 Extended FP register. */ | |
112 | #define IS_EFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_efpr0_regnum >= 0 \ | |
113 | && (regnum) >= (tdep)->ppc_efpr0_regnum \ | |
d9492458 | 114 | && (regnum) < (tdep)->ppc_efpr0_regnum + ppc_num_efprs) |
604c2f83 | 115 | |
8d619c01 EBM |
116 | /* Determine if regnum is a checkpointed decimal float |
117 | pseudo-register. */ | |
118 | #define IS_CDFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_cdl0_regnum >= 0 \ | |
119 | && (regnum) >= (tdep)->ppc_cdl0_regnum \ | |
120 | && (regnum) < (tdep)->ppc_cdl0_regnum + 16) | |
121 | ||
122 | /* Determine if regnum is a Checkpointed POWER7 VSX register. */ | |
123 | #define IS_CVSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_cvsr0_regnum >= 0 \ | |
124 | && (regnum) >= (tdep)->ppc_cvsr0_regnum \ | |
125 | && (regnum) < (tdep)->ppc_cvsr0_regnum + ppc_num_vsrs) | |
126 | ||
127 | /* Determine if regnum is a Checkpointed POWER7 Extended FP register. */ | |
128 | #define IS_CEFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_cefpr0_regnum >= 0 \ | |
129 | && (regnum) >= (tdep)->ppc_cefpr0_regnum \ | |
130 | && (regnum) < (tdep)->ppc_cefpr0_regnum + ppc_num_efprs) | |
131 | ||
65b48a81 PB |
132 | /* Holds the current set of options to be passed to the disassembler. */ |
133 | static char *powerpc_disassembler_options; | |
134 | ||
55eddb0f DJ |
135 | /* The list of available "set powerpc ..." and "show powerpc ..." |
136 | commands. */ | |
137 | static struct cmd_list_element *setpowerpccmdlist = NULL; | |
138 | static struct cmd_list_element *showpowerpccmdlist = NULL; | |
139 | ||
140 | static enum auto_boolean powerpc_soft_float_global = AUTO_BOOLEAN_AUTO; | |
141 | ||
142 | /* The vector ABI to use. Keep this in sync with powerpc_vector_abi. */ | |
40478521 | 143 | static const char *const powerpc_vector_strings[] = |
55eddb0f DJ |
144 | { |
145 | "auto", | |
146 | "generic", | |
147 | "altivec", | |
148 | "spe", | |
149 | NULL | |
150 | }; | |
151 | ||
152 | /* A variable that can be configured by the user. */ | |
153 | static enum powerpc_vector_abi powerpc_vector_abi_global = POWERPC_VEC_AUTO; | |
154 | static const char *powerpc_vector_abi_string = "auto"; | |
155 | ||
187b041e SM |
156 | /* PowerPC-related per-inferior data. */ |
157 | ||
158 | struct ppc_inferior_data | |
159 | { | |
160 | /* This is an optional in case we add more fields to ppc_inferior_data, we | |
161 | don't want it instantiated as soon as we get the ppc_inferior_data for an | |
162 | inferior. */ | |
480af54c | 163 | gdb::optional<displaced_step_buffers> disp_step_buf; |
187b041e SM |
164 | }; |
165 | ||
166 | static inferior_key<ppc_inferior_data> ppc_inferior_data_key; | |
167 | ||
168 | /* Get the per-inferior PowerPC data for INF. */ | |
169 | ||
170 | static ppc_inferior_data * | |
171 | get_ppc_per_inferior (inferior *inf) | |
172 | { | |
173 | ppc_inferior_data *per_inf = ppc_inferior_data_key.get (inf); | |
174 | ||
175 | if (per_inf == nullptr) | |
176 | per_inf = ppc_inferior_data_key.emplace (inf); | |
177 | ||
178 | return per_inf; | |
179 | } | |
180 | ||
0df8b418 | 181 | /* To be used by skip_prologue. */ |
7a78ae4e ND |
182 | |
183 | struct rs6000_framedata | |
184 | { | |
185 | int offset; /* total size of frame --- the distance | |
186 | by which we decrement sp to allocate | |
187 | the frame */ | |
188 | int saved_gpr; /* smallest # of saved gpr */ | |
46a9b8ed | 189 | unsigned int gpr_mask; /* Each bit is an individual saved GPR. */ |
7a78ae4e | 190 | int saved_fpr; /* smallest # of saved fpr */ |
6be8bc0c | 191 | int saved_vr; /* smallest # of saved vr */ |
96ff0de4 | 192 | int saved_ev; /* smallest # of saved ev */ |
7a78ae4e | 193 | int alloca_reg; /* alloca register number (frame ptr) */ |
0df8b418 MS |
194 | char frameless; /* true if frameless functions. */ |
195 | char nosavedpc; /* true if pc not saved. */ | |
46a9b8ed | 196 | char used_bl; /* true if link register clobbered */ |
7a78ae4e ND |
197 | int gpr_offset; /* offset of saved gprs from prev sp */ |
198 | int fpr_offset; /* offset of saved fprs from prev sp */ | |
6be8bc0c | 199 | int vr_offset; /* offset of saved vrs from prev sp */ |
96ff0de4 | 200 | int ev_offset; /* offset of saved evs from prev sp */ |
7a78ae4e | 201 | int lr_offset; /* offset of saved lr */ |
46a9b8ed | 202 | int lr_register; /* register of saved lr, if trustworthy */ |
7a78ae4e | 203 | int cr_offset; /* offset of saved cr */ |
6be8bc0c | 204 | int vrsave_offset; /* offset of saved vrsave register */ |
7a78ae4e ND |
205 | }; |
206 | ||
c906108c | 207 | |
604c2f83 LM |
208 | /* Is REGNO a VSX register? Return 1 if so, 0 otherwise. */ |
209 | int | |
210 | vsx_register_p (struct gdbarch *gdbarch, int regno) | |
211 | { | |
212 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
213 | if (tdep->ppc_vsr0_regnum < 0) | |
214 | return 0; | |
215 | else | |
216 | return (regno >= tdep->ppc_vsr0_upper_regnum && regno | |
217 | <= tdep->ppc_vsr0_upper_regnum + 31); | |
218 | } | |
219 | ||
64b84175 KB |
220 | /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */ |
221 | int | |
be8626e0 | 222 | altivec_register_p (struct gdbarch *gdbarch, int regno) |
64b84175 | 223 | { |
be8626e0 | 224 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
64b84175 KB |
225 | if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0) |
226 | return 0; | |
227 | else | |
228 | return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum); | |
229 | } | |
230 | ||
383f0f5b | 231 | |
867e2dc5 JB |
232 | /* Return true if REGNO is an SPE register, false otherwise. */ |
233 | int | |
be8626e0 | 234 | spe_register_p (struct gdbarch *gdbarch, int regno) |
867e2dc5 | 235 | { |
be8626e0 | 236 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
867e2dc5 JB |
237 | |
238 | /* Is it a reference to EV0 -- EV31, and do we have those? */ | |
5a9e69ba | 239 | if (IS_SPE_PSEUDOREG (tdep, regno)) |
867e2dc5 JB |
240 | return 1; |
241 | ||
6ced10dd JB |
242 | /* Is it a reference to one of the raw upper GPR halves? */ |
243 | if (tdep->ppc_ev0_upper_regnum >= 0 | |
244 | && tdep->ppc_ev0_upper_regnum <= regno | |
245 | && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) | |
246 | return 1; | |
247 | ||
867e2dc5 JB |
248 | /* Is it a reference to the 64-bit accumulator, and do we have that? */ |
249 | if (tdep->ppc_acc_regnum >= 0 | |
250 | && tdep->ppc_acc_regnum == regno) | |
251 | return 1; | |
252 | ||
253 | /* Is it a reference to the SPE floating-point status and control register, | |
254 | and do we have that? */ | |
255 | if (tdep->ppc_spefscr_regnum >= 0 | |
256 | && tdep->ppc_spefscr_regnum == regno) | |
257 | return 1; | |
258 | ||
259 | return 0; | |
260 | } | |
261 | ||
262 | ||
383f0f5b JB |
263 | /* Return non-zero if the architecture described by GDBARCH has |
264 | floating-point registers (f0 --- f31 and fpscr). */ | |
0a613259 AC |
265 | int |
266 | ppc_floating_point_unit_p (struct gdbarch *gdbarch) | |
267 | { | |
383f0f5b JB |
268 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
269 | ||
270 | return (tdep->ppc_fp0_regnum >= 0 | |
dda83cd7 | 271 | && tdep->ppc_fpscr_regnum >= 0); |
0a613259 | 272 | } |
9f643768 | 273 | |
06caf7d2 CES |
274 | /* Return non-zero if the architecture described by GDBARCH has |
275 | Altivec registers (vr0 --- vr31, vrsave and vscr). */ | |
276 | int | |
277 | ppc_altivec_support_p (struct gdbarch *gdbarch) | |
278 | { | |
279 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
280 | ||
281 | return (tdep->ppc_vr0_regnum >= 0 | |
dda83cd7 | 282 | && tdep->ppc_vrsave_regnum >= 0); |
06caf7d2 | 283 | } |
09991fa0 JB |
284 | |
285 | /* Check that TABLE[GDB_REGNO] is not already initialized, and then | |
286 | set it to SIM_REGNO. | |
287 | ||
288 | This is a helper function for init_sim_regno_table, constructing | |
289 | the table mapping GDB register numbers to sim register numbers; we | |
290 | initialize every element in that table to -1 before we start | |
291 | filling it in. */ | |
9f643768 JB |
292 | static void |
293 | set_sim_regno (int *table, int gdb_regno, int sim_regno) | |
294 | { | |
295 | /* Make sure we don't try to assign any given GDB register a sim | |
296 | register number more than once. */ | |
297 | gdb_assert (table[gdb_regno] == -1); | |
298 | table[gdb_regno] = sim_regno; | |
299 | } | |
300 | ||
09991fa0 JB |
301 | |
302 | /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register | |
303 | numbers to simulator register numbers, based on the values placed | |
304 | in the ARCH->tdep->ppc_foo_regnum members. */ | |
9f643768 JB |
305 | static void |
306 | init_sim_regno_table (struct gdbarch *arch) | |
307 | { | |
308 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); | |
7cc46491 | 309 | int total_regs = gdbarch_num_regs (arch); |
9f643768 JB |
310 | int *sim_regno = GDBARCH_OBSTACK_CALLOC (arch, total_regs, int); |
311 | int i; | |
7cc46491 DJ |
312 | static const char *const segment_regs[] = { |
313 | "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7", | |
314 | "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15" | |
315 | }; | |
9f643768 JB |
316 | |
317 | /* Presume that all registers not explicitly mentioned below are | |
318 | unavailable from the sim. */ | |
319 | for (i = 0; i < total_regs; i++) | |
320 | sim_regno[i] = -1; | |
321 | ||
322 | /* General-purpose registers. */ | |
323 | for (i = 0; i < ppc_num_gprs; i++) | |
324 | set_sim_regno (sim_regno, tdep->ppc_gp0_regnum + i, sim_ppc_r0_regnum + i); | |
325 | ||
326 | /* Floating-point registers. */ | |
327 | if (tdep->ppc_fp0_regnum >= 0) | |
328 | for (i = 0; i < ppc_num_fprs; i++) | |
329 | set_sim_regno (sim_regno, | |
dda83cd7 SM |
330 | tdep->ppc_fp0_regnum + i, |
331 | sim_ppc_f0_regnum + i); | |
9f643768 JB |
332 | if (tdep->ppc_fpscr_regnum >= 0) |
333 | set_sim_regno (sim_regno, tdep->ppc_fpscr_regnum, sim_ppc_fpscr_regnum); | |
334 | ||
335 | set_sim_regno (sim_regno, gdbarch_pc_regnum (arch), sim_ppc_pc_regnum); | |
336 | set_sim_regno (sim_regno, tdep->ppc_ps_regnum, sim_ppc_ps_regnum); | |
337 | set_sim_regno (sim_regno, tdep->ppc_cr_regnum, sim_ppc_cr_regnum); | |
338 | ||
339 | /* Segment registers. */ | |
7cc46491 DJ |
340 | for (i = 0; i < ppc_num_srs; i++) |
341 | { | |
342 | int gdb_regno; | |
343 | ||
344 | gdb_regno = user_reg_map_name_to_regnum (arch, segment_regs[i], -1); | |
345 | if (gdb_regno >= 0) | |
346 | set_sim_regno (sim_regno, gdb_regno, sim_ppc_sr0_regnum + i); | |
347 | } | |
9f643768 JB |
348 | |
349 | /* Altivec registers. */ | |
350 | if (tdep->ppc_vr0_regnum >= 0) | |
351 | { | |
352 | for (i = 0; i < ppc_num_vrs; i++) | |
dda83cd7 SM |
353 | set_sim_regno (sim_regno, |
354 | tdep->ppc_vr0_regnum + i, | |
355 | sim_ppc_vr0_regnum + i); | |
9f643768 JB |
356 | |
357 | /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum, | |
dda83cd7 | 358 | we can treat this more like the other cases. */ |
9f643768 | 359 | set_sim_regno (sim_regno, |
dda83cd7 SM |
360 | tdep->ppc_vr0_regnum + ppc_num_vrs, |
361 | sim_ppc_vscr_regnum); | |
9f643768 JB |
362 | } |
363 | /* vsave is a special-purpose register, so the code below handles it. */ | |
364 | ||
365 | /* SPE APU (E500) registers. */ | |
6ced10dd JB |
366 | if (tdep->ppc_ev0_upper_regnum >= 0) |
367 | for (i = 0; i < ppc_num_gprs; i++) | |
368 | set_sim_regno (sim_regno, | |
dda83cd7 SM |
369 | tdep->ppc_ev0_upper_regnum + i, |
370 | sim_ppc_rh0_regnum + i); | |
9f643768 JB |
371 | if (tdep->ppc_acc_regnum >= 0) |
372 | set_sim_regno (sim_regno, tdep->ppc_acc_regnum, sim_ppc_acc_regnum); | |
373 | /* spefscr is a special-purpose register, so the code below handles it. */ | |
374 | ||
976102cd | 375 | #ifdef WITH_PPC_SIM |
9f643768 JB |
376 | /* Now handle all special-purpose registers. Verify that they |
377 | haven't mistakenly been assigned numbers by any of the above | |
7cc46491 DJ |
378 | code. */ |
379 | for (i = 0; i < sim_ppc_num_sprs; i++) | |
380 | { | |
381 | const char *spr_name = sim_spr_register_name (i); | |
382 | int gdb_regno = -1; | |
383 | ||
384 | if (spr_name != NULL) | |
385 | gdb_regno = user_reg_map_name_to_regnum (arch, spr_name, -1); | |
386 | ||
387 | if (gdb_regno != -1) | |
388 | set_sim_regno (sim_regno, gdb_regno, sim_ppc_spr0_regnum + i); | |
389 | } | |
390 | #endif | |
9f643768 JB |
391 | |
392 | /* Drop the initialized array into place. */ | |
393 | tdep->sim_regno = sim_regno; | |
394 | } | |
395 | ||
09991fa0 JB |
396 | |
397 | /* Given a GDB register number REG, return the corresponding SIM | |
398 | register number. */ | |
9f643768 | 399 | static int |
e7faf938 | 400 | rs6000_register_sim_regno (struct gdbarch *gdbarch, int reg) |
9f643768 | 401 | { |
e7faf938 | 402 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
9f643768 JB |
403 | int sim_regno; |
404 | ||
7cc46491 | 405 | if (tdep->sim_regno == NULL) |
e7faf938 | 406 | init_sim_regno_table (gdbarch); |
7cc46491 | 407 | |
f6efe3f8 | 408 | gdb_assert (0 <= reg && reg <= gdbarch_num_cooked_regs (gdbarch)); |
9f643768 JB |
409 | sim_regno = tdep->sim_regno[reg]; |
410 | ||
411 | if (sim_regno >= 0) | |
412 | return sim_regno; | |
413 | else | |
414 | return LEGACY_SIM_REGNO_IGNORE; | |
415 | } | |
416 | ||
d195bc9f MK |
417 | \f |
418 | ||
419 | /* Register set support functions. */ | |
420 | ||
f2db237a AM |
421 | /* REGS + OFFSET contains register REGNUM in a field REGSIZE wide. |
422 | Write the register to REGCACHE. */ | |
423 | ||
7284e1be | 424 | void |
d195bc9f | 425 | ppc_supply_reg (struct regcache *regcache, int regnum, |
f2db237a | 426 | const gdb_byte *regs, size_t offset, int regsize) |
d195bc9f MK |
427 | { |
428 | if (regnum != -1 && offset != -1) | |
f2db237a AM |
429 | { |
430 | if (regsize > 4) | |
431 | { | |
ac7936df | 432 | struct gdbarch *gdbarch = regcache->arch (); |
f2db237a AM |
433 | int gdb_regsize = register_size (gdbarch, regnum); |
434 | if (gdb_regsize < regsize | |
435 | && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
436 | offset += regsize - gdb_regsize; | |
437 | } | |
73e1c03f | 438 | regcache->raw_supply (regnum, regs + offset); |
f2db237a | 439 | } |
d195bc9f MK |
440 | } |
441 | ||
f2db237a AM |
442 | /* Read register REGNUM from REGCACHE and store to REGS + OFFSET |
443 | in a field REGSIZE wide. Zero pad as necessary. */ | |
444 | ||
7284e1be | 445 | void |
d195bc9f | 446 | ppc_collect_reg (const struct regcache *regcache, int regnum, |
f2db237a | 447 | gdb_byte *regs, size_t offset, int regsize) |
d195bc9f MK |
448 | { |
449 | if (regnum != -1 && offset != -1) | |
f2db237a AM |
450 | { |
451 | if (regsize > 4) | |
452 | { | |
ac7936df | 453 | struct gdbarch *gdbarch = regcache->arch (); |
f2db237a AM |
454 | int gdb_regsize = register_size (gdbarch, regnum); |
455 | if (gdb_regsize < regsize) | |
456 | { | |
457 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
458 | { | |
459 | memset (regs + offset, 0, regsize - gdb_regsize); | |
460 | offset += regsize - gdb_regsize; | |
461 | } | |
462 | else | |
463 | memset (regs + offset + regsize - gdb_regsize, 0, | |
464 | regsize - gdb_regsize); | |
465 | } | |
466 | } | |
34a79281 | 467 | regcache->raw_collect (regnum, regs + offset); |
f2db237a | 468 | } |
d195bc9f MK |
469 | } |
470 | ||
f2db237a AM |
471 | static int |
472 | ppc_greg_offset (struct gdbarch *gdbarch, | |
473 | struct gdbarch_tdep *tdep, | |
474 | const struct ppc_reg_offsets *offsets, | |
475 | int regnum, | |
476 | int *regsize) | |
477 | { | |
478 | *regsize = offsets->gpr_size; | |
479 | if (regnum >= tdep->ppc_gp0_regnum | |
480 | && regnum < tdep->ppc_gp0_regnum + ppc_num_gprs) | |
481 | return (offsets->r0_offset | |
482 | + (regnum - tdep->ppc_gp0_regnum) * offsets->gpr_size); | |
483 | ||
484 | if (regnum == gdbarch_pc_regnum (gdbarch)) | |
485 | return offsets->pc_offset; | |
486 | ||
487 | if (regnum == tdep->ppc_ps_regnum) | |
488 | return offsets->ps_offset; | |
489 | ||
490 | if (regnum == tdep->ppc_lr_regnum) | |
491 | return offsets->lr_offset; | |
492 | ||
493 | if (regnum == tdep->ppc_ctr_regnum) | |
494 | return offsets->ctr_offset; | |
495 | ||
496 | *regsize = offsets->xr_size; | |
497 | if (regnum == tdep->ppc_cr_regnum) | |
498 | return offsets->cr_offset; | |
499 | ||
500 | if (regnum == tdep->ppc_xer_regnum) | |
501 | return offsets->xer_offset; | |
502 | ||
503 | if (regnum == tdep->ppc_mq_regnum) | |
504 | return offsets->mq_offset; | |
505 | ||
506 | return -1; | |
507 | } | |
508 | ||
509 | static int | |
510 | ppc_fpreg_offset (struct gdbarch_tdep *tdep, | |
511 | const struct ppc_reg_offsets *offsets, | |
512 | int regnum) | |
513 | { | |
514 | if (regnum >= tdep->ppc_fp0_regnum | |
515 | && regnum < tdep->ppc_fp0_regnum + ppc_num_fprs) | |
516 | return offsets->f0_offset + (regnum - tdep->ppc_fp0_regnum) * 8; | |
517 | ||
518 | if (regnum == tdep->ppc_fpscr_regnum) | |
519 | return offsets->fpscr_offset; | |
520 | ||
521 | return -1; | |
522 | } | |
523 | ||
d195bc9f MK |
524 | /* Supply register REGNUM in the general-purpose register set REGSET |
525 | from the buffer specified by GREGS and LEN to register cache | |
526 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
527 | ||
528 | void | |
529 | ppc_supply_gregset (const struct regset *regset, struct regcache *regcache, | |
530 | int regnum, const void *gregs, size_t len) | |
531 | { | |
ac7936df | 532 | struct gdbarch *gdbarch = regcache->arch (); |
d195bc9f | 533 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
19ba03f4 SM |
534 | const struct ppc_reg_offsets *offsets |
535 | = (const struct ppc_reg_offsets *) regset->regmap; | |
d195bc9f | 536 | size_t offset; |
f2db237a | 537 | int regsize; |
d195bc9f | 538 | |
f2db237a | 539 | if (regnum == -1) |
d195bc9f | 540 | { |
f2db237a AM |
541 | int i; |
542 | int gpr_size = offsets->gpr_size; | |
543 | ||
544 | for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset; | |
545 | i < tdep->ppc_gp0_regnum + ppc_num_gprs; | |
546 | i++, offset += gpr_size) | |
19ba03f4 SM |
547 | ppc_supply_reg (regcache, i, (const gdb_byte *) gregs, offset, |
548 | gpr_size); | |
f2db237a AM |
549 | |
550 | ppc_supply_reg (regcache, gdbarch_pc_regnum (gdbarch), | |
19ba03f4 | 551 | (const gdb_byte *) gregs, offsets->pc_offset, gpr_size); |
f2db237a | 552 | ppc_supply_reg (regcache, tdep->ppc_ps_regnum, |
19ba03f4 | 553 | (const gdb_byte *) gregs, offsets->ps_offset, gpr_size); |
f2db237a | 554 | ppc_supply_reg (regcache, tdep->ppc_lr_regnum, |
19ba03f4 | 555 | (const gdb_byte *) gregs, offsets->lr_offset, gpr_size); |
f2db237a | 556 | ppc_supply_reg (regcache, tdep->ppc_ctr_regnum, |
19ba03f4 | 557 | (const gdb_byte *) gregs, offsets->ctr_offset, gpr_size); |
f2db237a | 558 | ppc_supply_reg (regcache, tdep->ppc_cr_regnum, |
19ba03f4 SM |
559 | (const gdb_byte *) gregs, offsets->cr_offset, |
560 | offsets->xr_size); | |
f2db237a | 561 | ppc_supply_reg (regcache, tdep->ppc_xer_regnum, |
19ba03f4 SM |
562 | (const gdb_byte *) gregs, offsets->xer_offset, |
563 | offsets->xr_size); | |
f2db237a | 564 | ppc_supply_reg (regcache, tdep->ppc_mq_regnum, |
19ba03f4 SM |
565 | (const gdb_byte *) gregs, offsets->mq_offset, |
566 | offsets->xr_size); | |
f2db237a | 567 | return; |
d195bc9f MK |
568 | } |
569 | ||
f2db237a | 570 | offset = ppc_greg_offset (gdbarch, tdep, offsets, regnum, ®size); |
19ba03f4 | 571 | ppc_supply_reg (regcache, regnum, (const gdb_byte *) gregs, offset, regsize); |
d195bc9f MK |
572 | } |
573 | ||
574 | /* Supply register REGNUM in the floating-point register set REGSET | |
575 | from the buffer specified by FPREGS and LEN to register cache | |
576 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
577 | ||
578 | void | |
579 | ppc_supply_fpregset (const struct regset *regset, struct regcache *regcache, | |
580 | int regnum, const void *fpregs, size_t len) | |
581 | { | |
ac7936df | 582 | struct gdbarch *gdbarch = regcache->arch (); |
f2db237a AM |
583 | struct gdbarch_tdep *tdep; |
584 | const struct ppc_reg_offsets *offsets; | |
d195bc9f | 585 | size_t offset; |
d195bc9f | 586 | |
f2db237a AM |
587 | if (!ppc_floating_point_unit_p (gdbarch)) |
588 | return; | |
383f0f5b | 589 | |
f2db237a | 590 | tdep = gdbarch_tdep (gdbarch); |
19ba03f4 | 591 | offsets = (const struct ppc_reg_offsets *) regset->regmap; |
f2db237a | 592 | if (regnum == -1) |
d195bc9f | 593 | { |
f2db237a AM |
594 | int i; |
595 | ||
596 | for (i = tdep->ppc_fp0_regnum, offset = offsets->f0_offset; | |
597 | i < tdep->ppc_fp0_regnum + ppc_num_fprs; | |
598 | i++, offset += 8) | |
19ba03f4 | 599 | ppc_supply_reg (regcache, i, (const gdb_byte *) fpregs, offset, 8); |
f2db237a AM |
600 | |
601 | ppc_supply_reg (regcache, tdep->ppc_fpscr_regnum, | |
19ba03f4 SM |
602 | (const gdb_byte *) fpregs, offsets->fpscr_offset, |
603 | offsets->fpscr_size); | |
f2db237a | 604 | return; |
d195bc9f MK |
605 | } |
606 | ||
f2db237a | 607 | offset = ppc_fpreg_offset (tdep, offsets, regnum); |
19ba03f4 | 608 | ppc_supply_reg (regcache, regnum, (const gdb_byte *) fpregs, offset, |
f2db237a | 609 | regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8); |
d195bc9f MK |
610 | } |
611 | ||
612 | /* Collect register REGNUM in the general-purpose register set | |
f2db237a | 613 | REGSET from register cache REGCACHE into the buffer specified by |
d195bc9f MK |
614 | GREGS and LEN. If REGNUM is -1, do this for all registers in |
615 | REGSET. */ | |
616 | ||
617 | void | |
618 | ppc_collect_gregset (const struct regset *regset, | |
619 | const struct regcache *regcache, | |
620 | int regnum, void *gregs, size_t len) | |
621 | { | |
ac7936df | 622 | struct gdbarch *gdbarch = regcache->arch (); |
d195bc9f | 623 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
19ba03f4 SM |
624 | const struct ppc_reg_offsets *offsets |
625 | = (const struct ppc_reg_offsets *) regset->regmap; | |
d195bc9f | 626 | size_t offset; |
f2db237a | 627 | int regsize; |
d195bc9f | 628 | |
f2db237a | 629 | if (regnum == -1) |
d195bc9f | 630 | { |
f2db237a AM |
631 | int i; |
632 | int gpr_size = offsets->gpr_size; | |
633 | ||
634 | for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset; | |
635 | i < tdep->ppc_gp0_regnum + ppc_num_gprs; | |
636 | i++, offset += gpr_size) | |
19ba03f4 | 637 | ppc_collect_reg (regcache, i, (gdb_byte *) gregs, offset, gpr_size); |
f2db237a AM |
638 | |
639 | ppc_collect_reg (regcache, gdbarch_pc_regnum (gdbarch), | |
19ba03f4 | 640 | (gdb_byte *) gregs, offsets->pc_offset, gpr_size); |
f2db237a | 641 | ppc_collect_reg (regcache, tdep->ppc_ps_regnum, |
19ba03f4 | 642 | (gdb_byte *) gregs, offsets->ps_offset, gpr_size); |
f2db237a | 643 | ppc_collect_reg (regcache, tdep->ppc_lr_regnum, |
19ba03f4 | 644 | (gdb_byte *) gregs, offsets->lr_offset, gpr_size); |
f2db237a | 645 | ppc_collect_reg (regcache, tdep->ppc_ctr_regnum, |
19ba03f4 | 646 | (gdb_byte *) gregs, offsets->ctr_offset, gpr_size); |
f2db237a | 647 | ppc_collect_reg (regcache, tdep->ppc_cr_regnum, |
19ba03f4 SM |
648 | (gdb_byte *) gregs, offsets->cr_offset, |
649 | offsets->xr_size); | |
f2db237a | 650 | ppc_collect_reg (regcache, tdep->ppc_xer_regnum, |
19ba03f4 SM |
651 | (gdb_byte *) gregs, offsets->xer_offset, |
652 | offsets->xr_size); | |
f2db237a | 653 | ppc_collect_reg (regcache, tdep->ppc_mq_regnum, |
19ba03f4 SM |
654 | (gdb_byte *) gregs, offsets->mq_offset, |
655 | offsets->xr_size); | |
f2db237a | 656 | return; |
d195bc9f MK |
657 | } |
658 | ||
f2db237a | 659 | offset = ppc_greg_offset (gdbarch, tdep, offsets, regnum, ®size); |
19ba03f4 | 660 | ppc_collect_reg (regcache, regnum, (gdb_byte *) gregs, offset, regsize); |
d195bc9f MK |
661 | } |
662 | ||
663 | /* Collect register REGNUM in the floating-point register set | |
f2db237a | 664 | REGSET from register cache REGCACHE into the buffer specified by |
d195bc9f MK |
665 | FPREGS and LEN. If REGNUM is -1, do this for all registers in |
666 | REGSET. */ | |
667 | ||
668 | void | |
669 | ppc_collect_fpregset (const struct regset *regset, | |
670 | const struct regcache *regcache, | |
671 | int regnum, void *fpregs, size_t len) | |
672 | { | |
ac7936df | 673 | struct gdbarch *gdbarch = regcache->arch (); |
f2db237a AM |
674 | struct gdbarch_tdep *tdep; |
675 | const struct ppc_reg_offsets *offsets; | |
d195bc9f | 676 | size_t offset; |
d195bc9f | 677 | |
f2db237a AM |
678 | if (!ppc_floating_point_unit_p (gdbarch)) |
679 | return; | |
383f0f5b | 680 | |
f2db237a | 681 | tdep = gdbarch_tdep (gdbarch); |
19ba03f4 | 682 | offsets = (const struct ppc_reg_offsets *) regset->regmap; |
f2db237a | 683 | if (regnum == -1) |
d195bc9f | 684 | { |
f2db237a AM |
685 | int i; |
686 | ||
687 | for (i = tdep->ppc_fp0_regnum, offset = offsets->f0_offset; | |
688 | i < tdep->ppc_fp0_regnum + ppc_num_fprs; | |
689 | i++, offset += 8) | |
19ba03f4 | 690 | ppc_collect_reg (regcache, i, (gdb_byte *) fpregs, offset, 8); |
f2db237a AM |
691 | |
692 | ppc_collect_reg (regcache, tdep->ppc_fpscr_regnum, | |
19ba03f4 SM |
693 | (gdb_byte *) fpregs, offsets->fpscr_offset, |
694 | offsets->fpscr_size); | |
f2db237a | 695 | return; |
d195bc9f MK |
696 | } |
697 | ||
f2db237a | 698 | offset = ppc_fpreg_offset (tdep, offsets, regnum); |
19ba03f4 | 699 | ppc_collect_reg (regcache, regnum, (gdb_byte *) fpregs, offset, |
f2db237a | 700 | regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8); |
d195bc9f | 701 | } |
06caf7d2 | 702 | |
0d1243d9 PG |
703 | static int |
704 | insn_changes_sp_or_jumps (unsigned long insn) | |
705 | { | |
706 | int opcode = (insn >> 26) & 0x03f; | |
707 | int sd = (insn >> 21) & 0x01f; | |
708 | int a = (insn >> 16) & 0x01f; | |
709 | int subcode = (insn >> 1) & 0x3ff; | |
710 | ||
711 | /* Changes the stack pointer. */ | |
712 | ||
713 | /* NOTE: There are many ways to change the value of a given register. | |
dda83cd7 SM |
714 | The ways below are those used when the register is R1, the SP, |
715 | in a funtion's epilogue. */ | |
0d1243d9 PG |
716 | |
717 | if (opcode == 31 && subcode == 444 && a == 1) | |
718 | return 1; /* mr R1,Rn */ | |
719 | if (opcode == 14 && sd == 1) | |
720 | return 1; /* addi R1,Rn,simm */ | |
721 | if (opcode == 58 && sd == 1) | |
722 | return 1; /* ld R1,ds(Rn) */ | |
723 | ||
724 | /* Transfers control. */ | |
725 | ||
726 | if (opcode == 18) | |
727 | return 1; /* b */ | |
728 | if (opcode == 16) | |
729 | return 1; /* bc */ | |
730 | if (opcode == 19 && subcode == 16) | |
731 | return 1; /* bclr */ | |
732 | if (opcode == 19 && subcode == 528) | |
733 | return 1; /* bcctr */ | |
734 | ||
735 | return 0; | |
736 | } | |
737 | ||
738 | /* Return true if we are in the function's epilogue, i.e. after the | |
739 | instruction that destroyed the function's stack frame. | |
740 | ||
741 | 1) scan forward from the point of execution: | |
742 | a) If you find an instruction that modifies the stack pointer | |
dda83cd7 SM |
743 | or transfers control (except a return), execution is not in |
744 | an epilogue, return. | |
0d1243d9 | 745 | b) Stop scanning if you find a return instruction or reach the |
dda83cd7 SM |
746 | end of the function or reach the hard limit for the size of |
747 | an epilogue. | |
0d1243d9 | 748 | 2) scan backward from the point of execution: |
dda83cd7 SM |
749 | a) If you find an instruction that modifies the stack pointer, |
750 | execution *is* in an epilogue, return. | |
751 | b) Stop scanning if you reach an instruction that transfers | |
752 | control or the beginning of the function or reach the hard | |
753 | limit for the size of an epilogue. */ | |
0d1243d9 PG |
754 | |
755 | static int | |
2608dbf8 WW |
756 | rs6000_in_function_epilogue_frame_p (struct frame_info *curfrm, |
757 | struct gdbarch *gdbarch, CORE_ADDR pc) | |
0d1243d9 | 758 | { |
46a9b8ed | 759 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
e17a4113 | 760 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
0d1243d9 PG |
761 | bfd_byte insn_buf[PPC_INSN_SIZE]; |
762 | CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end; | |
763 | unsigned long insn; | |
0d1243d9 PG |
764 | |
765 | /* Find the search limits based on function boundaries and hard limit. */ | |
766 | ||
767 | if (!find_pc_partial_function (pc, NULL, &func_start, &func_end)) | |
768 | return 0; | |
769 | ||
770 | epilogue_start = pc - PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE; | |
771 | if (epilogue_start < func_start) epilogue_start = func_start; | |
772 | ||
773 | epilogue_end = pc + PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE; | |
774 | if (epilogue_end > func_end) epilogue_end = func_end; | |
775 | ||
0d1243d9 PG |
776 | /* Scan forward until next 'blr'. */ |
777 | ||
778 | for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += PPC_INSN_SIZE) | |
779 | { | |
bdec2917 LM |
780 | if (!safe_frame_unwind_memory (curfrm, scan_pc, |
781 | {insn_buf, PPC_INSN_SIZE})) | |
dda83cd7 | 782 | return 0; |
e17a4113 | 783 | insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE, byte_order); |
0d1243d9 | 784 | if (insn == 0x4e800020) |
dda83cd7 | 785 | break; |
46a9b8ed DJ |
786 | /* Assume a bctr is a tail call unless it points strictly within |
787 | this function. */ | |
788 | if (insn == 0x4e800420) | |
789 | { | |
790 | CORE_ADDR ctr = get_frame_register_unsigned (curfrm, | |
791 | tdep->ppc_ctr_regnum); | |
792 | if (ctr > func_start && ctr < func_end) | |
793 | return 0; | |
794 | else | |
795 | break; | |
796 | } | |
0d1243d9 | 797 | if (insn_changes_sp_or_jumps (insn)) |
dda83cd7 | 798 | return 0; |
0d1243d9 PG |
799 | } |
800 | ||
801 | /* Scan backward until adjustment to stack pointer (R1). */ | |
802 | ||
803 | for (scan_pc = pc - PPC_INSN_SIZE; | |
804 | scan_pc >= epilogue_start; | |
805 | scan_pc -= PPC_INSN_SIZE) | |
806 | { | |
bdec2917 LM |
807 | if (!safe_frame_unwind_memory (curfrm, scan_pc, |
808 | {insn_buf, PPC_INSN_SIZE})) | |
dda83cd7 | 809 | return 0; |
e17a4113 | 810 | insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE, byte_order); |
0d1243d9 | 811 | if (insn_changes_sp_or_jumps (insn)) |
dda83cd7 | 812 | return 1; |
0d1243d9 PG |
813 | } |
814 | ||
815 | return 0; | |
816 | } | |
817 | ||
c9cf6e20 | 818 | /* Implement the stack_frame_destroyed_p gdbarch method. */ |
2608dbf8 WW |
819 | |
820 | static int | |
c9cf6e20 | 821 | rs6000_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
2608dbf8 WW |
822 | { |
823 | return rs6000_in_function_epilogue_frame_p (get_current_frame (), | |
824 | gdbarch, pc); | |
825 | } | |
826 | ||
143985b7 | 827 | /* Get the ith function argument for the current function. */ |
b9362cc7 | 828 | static CORE_ADDR |
143985b7 AF |
829 | rs6000_fetch_pointer_argument (struct frame_info *frame, int argi, |
830 | struct type *type) | |
831 | { | |
50fd1280 | 832 | return get_frame_register_unsigned (frame, 3 + argi); |
143985b7 AF |
833 | } |
834 | ||
c906108c SS |
835 | /* Sequence of bytes for breakpoint instruction. */ |
836 | ||
04180708 YQ |
837 | constexpr gdb_byte big_breakpoint[] = { 0x7d, 0x82, 0x10, 0x08 }; |
838 | constexpr gdb_byte little_breakpoint[] = { 0x08, 0x10, 0x82, 0x7d }; | |
d19280ad | 839 | |
04180708 YQ |
840 | typedef BP_MANIPULATION_ENDIAN (little_breakpoint, big_breakpoint) |
841 | rs6000_breakpoint; | |
c906108c | 842 | |
f74c6cad LM |
843 | /* Instruction masks for displaced stepping. */ |
844 | #define BRANCH_MASK 0xfc000000 | |
845 | #define BP_MASK 0xFC0007FE | |
846 | #define B_INSN 0x48000000 | |
847 | #define BC_INSN 0x40000000 | |
848 | #define BXL_INSN 0x4c000000 | |
849 | #define BP_INSN 0x7C000008 | |
850 | ||
7f03bd92 PA |
851 | /* Instruction masks used during single-stepping of atomic |
852 | sequences. */ | |
2039d74e | 853 | #define LOAD_AND_RESERVE_MASK 0xfc0007fe |
7f03bd92 PA |
854 | #define LWARX_INSTRUCTION 0x7c000028 |
855 | #define LDARX_INSTRUCTION 0x7c0000A8 | |
2039d74e EBM |
856 | #define LBARX_INSTRUCTION 0x7c000068 |
857 | #define LHARX_INSTRUCTION 0x7c0000e8 | |
858 | #define LQARX_INSTRUCTION 0x7c000228 | |
859 | #define STORE_CONDITIONAL_MASK 0xfc0007ff | |
7f03bd92 PA |
860 | #define STWCX_INSTRUCTION 0x7c00012d |
861 | #define STDCX_INSTRUCTION 0x7c0001ad | |
2039d74e EBM |
862 | #define STBCX_INSTRUCTION 0x7c00056d |
863 | #define STHCX_INSTRUCTION 0x7c0005ad | |
864 | #define STQCX_INSTRUCTION 0x7c00016d | |
865 | ||
866 | /* Check if insn is one of the Load And Reserve instructions used for atomic | |
867 | sequences. */ | |
868 | #define IS_LOAD_AND_RESERVE_INSN(insn) ((insn & LOAD_AND_RESERVE_MASK) == LWARX_INSTRUCTION \ | |
869 | || (insn & LOAD_AND_RESERVE_MASK) == LDARX_INSTRUCTION \ | |
870 | || (insn & LOAD_AND_RESERVE_MASK) == LBARX_INSTRUCTION \ | |
871 | || (insn & LOAD_AND_RESERVE_MASK) == LHARX_INSTRUCTION \ | |
872 | || (insn & LOAD_AND_RESERVE_MASK) == LQARX_INSTRUCTION) | |
873 | /* Check if insn is one of the Store Conditional instructions used for atomic | |
874 | sequences. */ | |
875 | #define IS_STORE_CONDITIONAL_INSN(insn) ((insn & STORE_CONDITIONAL_MASK) == STWCX_INSTRUCTION \ | |
876 | || (insn & STORE_CONDITIONAL_MASK) == STDCX_INSTRUCTION \ | |
877 | || (insn & STORE_CONDITIONAL_MASK) == STBCX_INSTRUCTION \ | |
878 | || (insn & STORE_CONDITIONAL_MASK) == STHCX_INSTRUCTION \ | |
879 | || (insn & STORE_CONDITIONAL_MASK) == STQCX_INSTRUCTION) | |
7f03bd92 | 880 | |
1152d984 SM |
881 | typedef buf_displaced_step_copy_insn_closure |
882 | ppc_displaced_step_copy_insn_closure; | |
cfba9872 | 883 | |
c2508e90 | 884 | /* We can't displaced step atomic sequences. */ |
7f03bd92 | 885 | |
1152d984 | 886 | static displaced_step_copy_insn_closure_up |
7f03bd92 PA |
887 | ppc_displaced_step_copy_insn (struct gdbarch *gdbarch, |
888 | CORE_ADDR from, CORE_ADDR to, | |
889 | struct regcache *regs) | |
890 | { | |
891 | size_t len = gdbarch_max_insn_length (gdbarch); | |
1152d984 SM |
892 | std::unique_ptr<ppc_displaced_step_copy_insn_closure> closure |
893 | (new ppc_displaced_step_copy_insn_closure (len)); | |
cfba9872 | 894 | gdb_byte *buf = closure->buf.data (); |
7f03bd92 PA |
895 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
896 | int insn; | |
897 | ||
898 | read_memory (from, buf, len); | |
899 | ||
900 | insn = extract_signed_integer (buf, PPC_INSN_SIZE, byte_order); | |
901 | ||
2039d74e EBM |
902 | /* Assume all atomic sequences start with a Load and Reserve instruction. */ |
903 | if (IS_LOAD_AND_RESERVE_INSN (insn)) | |
7f03bd92 | 904 | { |
136821d9 | 905 | displaced_debug_printf ("can't displaced step atomic sequence at %s", |
7f03bd92 | 906 | paddress (gdbarch, from)); |
cfba9872 | 907 | |
7f03bd92 PA |
908 | return NULL; |
909 | } | |
910 | ||
911 | write_memory (to, buf, len); | |
912 | ||
136821d9 | 913 | displaced_debug_printf ("copy %s->%s: %s", |
dda83cd7 | 914 | paddress (gdbarch, from), paddress (gdbarch, to), |
136821d9 | 915 | displaced_step_dump_bytes (buf, len).c_str ());; |
7f03bd92 | 916 | |
6d0cf446 | 917 | /* This is a work around for a problem with g++ 4.8. */ |
1152d984 | 918 | return displaced_step_copy_insn_closure_up (closure.release ()); |
7f03bd92 PA |
919 | } |
920 | ||
f74c6cad LM |
921 | /* Fix up the state of registers and memory after having single-stepped |
922 | a displaced instruction. */ | |
63807e1d | 923 | static void |
f74c6cad | 924 | ppc_displaced_step_fixup (struct gdbarch *gdbarch, |
1152d984 | 925 | struct displaced_step_copy_insn_closure *closure_, |
63807e1d PA |
926 | CORE_ADDR from, CORE_ADDR to, |
927 | struct regcache *regs) | |
f74c6cad | 928 | { |
e17a4113 | 929 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7f03bd92 | 930 | /* Our closure is a copy of the instruction. */ |
1152d984 SM |
931 | ppc_displaced_step_copy_insn_closure *closure |
932 | = (ppc_displaced_step_copy_insn_closure *) closure_; | |
cfba9872 SM |
933 | ULONGEST insn = extract_unsigned_integer (closure->buf.data (), |
934 | PPC_INSN_SIZE, byte_order); | |
f74c6cad LM |
935 | ULONGEST opcode = 0; |
936 | /* Offset for non PC-relative instructions. */ | |
937 | LONGEST offset = PPC_INSN_SIZE; | |
938 | ||
939 | opcode = insn & BRANCH_MASK; | |
940 | ||
136821d9 SM |
941 | displaced_debug_printf ("(ppc) fixup (%s, %s)", |
942 | paddress (gdbarch, from), paddress (gdbarch, to)); | |
f74c6cad LM |
943 | |
944 | /* Handle PC-relative branch instructions. */ | |
945 | if (opcode == B_INSN || opcode == BC_INSN || opcode == BXL_INSN) | |
946 | { | |
a4fafde3 | 947 | ULONGEST current_pc; |
f74c6cad LM |
948 | |
949 | /* Read the current PC value after the instruction has been executed | |
950 | in a displaced location. Calculate the offset to be applied to the | |
951 | original PC value before the displaced stepping. */ | |
952 | regcache_cooked_read_unsigned (regs, gdbarch_pc_regnum (gdbarch), | |
953 | ¤t_pc); | |
954 | offset = current_pc - to; | |
955 | ||
956 | if (opcode != BXL_INSN) | |
957 | { | |
958 | /* Check for AA bit indicating whether this is an absolute | |
959 | addressing or PC-relative (1: absolute, 0: relative). */ | |
960 | if (!(insn & 0x2)) | |
961 | { | |
962 | /* PC-relative addressing is being used in the branch. */ | |
136821d9 SM |
963 | displaced_debug_printf ("(ppc) branch instruction: %s", |
964 | paddress (gdbarch, insn)); | |
965 | displaced_debug_printf ("(ppc) adjusted PC from %s to %s", | |
966 | paddress (gdbarch, current_pc), | |
967 | paddress (gdbarch, from + offset)); | |
f74c6cad | 968 | |
0df8b418 MS |
969 | regcache_cooked_write_unsigned (regs, |
970 | gdbarch_pc_regnum (gdbarch), | |
f74c6cad LM |
971 | from + offset); |
972 | } | |
973 | } | |
974 | else | |
975 | { | |
976 | /* If we're here, it means we have a branch to LR or CTR. If the | |
977 | branch was taken, the offset is probably greater than 4 (the next | |
978 | instruction), so it's safe to assume that an offset of 4 means we | |
979 | did not take the branch. */ | |
980 | if (offset == PPC_INSN_SIZE) | |
981 | regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch), | |
982 | from + PPC_INSN_SIZE); | |
983 | } | |
984 | ||
985 | /* Check for LK bit indicating whether we should set the link | |
986 | register to point to the next instruction | |
987 | (1: Set, 0: Don't set). */ | |
988 | if (insn & 0x1) | |
989 | { | |
990 | /* Link register needs to be set to the next instruction's PC. */ | |
991 | regcache_cooked_write_unsigned (regs, | |
992 | gdbarch_tdep (gdbarch)->ppc_lr_regnum, | |
993 | from + PPC_INSN_SIZE); | |
136821d9 SM |
994 | displaced_debug_printf ("(ppc) adjusted LR to %s", |
995 | paddress (gdbarch, from + PPC_INSN_SIZE)); | |
f74c6cad LM |
996 | |
997 | } | |
998 | } | |
999 | /* Check for breakpoints in the inferior. If we've found one, place the PC | |
1000 | right at the breakpoint instruction. */ | |
1001 | else if ((insn & BP_MASK) == BP_INSN) | |
1002 | regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch), from); | |
1003 | else | |
1004 | /* Handle any other instructions that do not fit in the categories above. */ | |
1005 | regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch), | |
1006 | from + offset); | |
1007 | } | |
c906108c | 1008 | |
187b041e SM |
1009 | /* Implementation of gdbarch_displaced_step_prepare. */ |
1010 | ||
1011 | static displaced_step_prepare_status | |
1012 | ppc_displaced_step_prepare (gdbarch *arch, thread_info *thread, | |
1013 | CORE_ADDR &displaced_pc) | |
1014 | { | |
1015 | ppc_inferior_data *per_inferior = get_ppc_per_inferior (thread->inf); | |
1016 | ||
1017 | if (!per_inferior->disp_step_buf.has_value ()) | |
1018 | { | |
1019 | /* Figure out where the displaced step buffer is. */ | |
1020 | CORE_ADDR disp_step_buf_addr | |
1021 | = displaced_step_at_entry_point (thread->inf->gdbarch); | |
1022 | ||
1023 | per_inferior->disp_step_buf.emplace (disp_step_buf_addr); | |
1024 | } | |
1025 | ||
1026 | return per_inferior->disp_step_buf->prepare (thread, displaced_pc); | |
1027 | } | |
1028 | ||
1029 | /* Implementation of gdbarch_displaced_step_finish. */ | |
1030 | ||
1031 | static displaced_step_finish_status | |
1032 | ppc_displaced_step_finish (gdbarch *arch, thread_info *thread, | |
1033 | gdb_signal sig) | |
1034 | { | |
1035 | ppc_inferior_data *per_inferior = get_ppc_per_inferior (thread->inf); | |
1036 | ||
1037 | gdb_assert (per_inferior->disp_step_buf.has_value ()); | |
1038 | ||
1039 | return per_inferior->disp_step_buf->finish (arch, thread, sig); | |
1040 | } | |
1041 | ||
1042 | /* Implementation of gdbarch_displaced_step_restore_all_in_ptid. */ | |
1043 | ||
1044 | static void | |
1045 | ppc_displaced_step_restore_all_in_ptid (inferior *parent_inf, ptid_t ptid) | |
1046 | { | |
1047 | ppc_inferior_data *per_inferior = ppc_inferior_data_key.get (parent_inf); | |
1048 | ||
1049 | if (per_inferior == nullptr | |
1050 | || !per_inferior->disp_step_buf.has_value ()) | |
1051 | return; | |
1052 | ||
1053 | per_inferior->disp_step_buf->restore_in_ptid (ptid); | |
1054 | } | |
1055 | ||
99e40580 UW |
1056 | /* Always use hardware single-stepping to execute the |
1057 | displaced instruction. */ | |
07fbbd01 | 1058 | static bool |
40a53766 | 1059 | ppc_displaced_step_hw_singlestep (struct gdbarch *gdbarch) |
99e40580 | 1060 | { |
07fbbd01 | 1061 | return true; |
99e40580 UW |
1062 | } |
1063 | ||
2039d74e EBM |
1064 | /* Checks for an atomic sequence of instructions beginning with a |
1065 | Load And Reserve instruction and ending with a Store Conditional | |
1066 | instruction. If such a sequence is found, attempt to step through it. | |
1067 | A breakpoint is placed at the end of the sequence. */ | |
a0ff9e1a | 1068 | std::vector<CORE_ADDR> |
f5ea389a | 1069 | ppc_deal_with_atomic_sequence (struct regcache *regcache) |
ce5eab59 | 1070 | { |
ac7936df | 1071 | struct gdbarch *gdbarch = regcache->arch (); |
e17a4113 | 1072 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
41e26ad3 | 1073 | CORE_ADDR pc = regcache_read_pc (regcache); |
70ab8ccd | 1074 | CORE_ADDR breaks[2] = {CORE_ADDR_MAX, CORE_ADDR_MAX}; |
ce5eab59 | 1075 | CORE_ADDR loc = pc; |
24d45690 | 1076 | CORE_ADDR closing_insn; /* Instruction that closes the atomic sequence. */ |
e17a4113 | 1077 | int insn = read_memory_integer (loc, PPC_INSN_SIZE, byte_order); |
ce5eab59 UW |
1078 | int insn_count; |
1079 | int index; | |
1080 | int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ | |
1081 | const int atomic_sequence_length = 16; /* Instruction sequence length. */ | |
ce5eab59 UW |
1082 | int bc_insn_count = 0; /* Conditional branch instruction count. */ |
1083 | ||
2039d74e EBM |
1084 | /* Assume all atomic sequences start with a Load And Reserve instruction. */ |
1085 | if (!IS_LOAD_AND_RESERVE_INSN (insn)) | |
a0ff9e1a | 1086 | return {}; |
ce5eab59 UW |
1087 | |
1088 | /* Assume that no atomic sequence is longer than "atomic_sequence_length" | |
1089 | instructions. */ | |
1090 | for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) | |
1091 | { | |
1092 | loc += PPC_INSN_SIZE; | |
e17a4113 | 1093 | insn = read_memory_integer (loc, PPC_INSN_SIZE, byte_order); |
ce5eab59 UW |
1094 | |
1095 | /* Assume that there is at most one conditional branch in the atomic | |
dda83cd7 SM |
1096 | sequence. If a conditional branch is found, put a breakpoint in |
1097 | its destination address. */ | |
f74c6cad | 1098 | if ((insn & BRANCH_MASK) == BC_INSN) |
dda83cd7 SM |
1099 | { |
1100 | int immediate = ((insn & 0xfffc) ^ 0x8000) - 0x8000; | |
1101 | int absolute = insn & 2; | |
4a7622d1 | 1102 | |
dda83cd7 SM |
1103 | if (bc_insn_count >= 1) |
1104 | return {}; /* More than one conditional branch found, fallback | |
1105 | to the standard single-step code. */ | |
4a7622d1 UW |
1106 | |
1107 | if (absolute) | |
1108 | breaks[1] = immediate; | |
1109 | else | |
a3769e0c | 1110 | breaks[1] = loc + immediate; |
4a7622d1 UW |
1111 | |
1112 | bc_insn_count++; | |
1113 | last_breakpoint++; | |
dda83cd7 | 1114 | } |
ce5eab59 | 1115 | |
2039d74e | 1116 | if (IS_STORE_CONDITIONAL_INSN (insn)) |
dda83cd7 | 1117 | break; |
ce5eab59 UW |
1118 | } |
1119 | ||
2039d74e EBM |
1120 | /* Assume that the atomic sequence ends with a Store Conditional |
1121 | instruction. */ | |
1122 | if (!IS_STORE_CONDITIONAL_INSN (insn)) | |
a0ff9e1a | 1123 | return {}; |
ce5eab59 | 1124 | |
24d45690 | 1125 | closing_insn = loc; |
ce5eab59 | 1126 | loc += PPC_INSN_SIZE; |
ce5eab59 UW |
1127 | |
1128 | /* Insert a breakpoint right after the end of the atomic sequence. */ | |
1129 | breaks[0] = loc; | |
1130 | ||
24d45690 | 1131 | /* Check for duplicated breakpoints. Check also for a breakpoint |
a3769e0c AM |
1132 | placed (branch instruction's destination) anywhere in sequence. */ |
1133 | if (last_breakpoint | |
1134 | && (breaks[1] == breaks[0] | |
1135 | || (breaks[1] >= pc && breaks[1] <= closing_insn))) | |
ce5eab59 UW |
1136 | last_breakpoint = 0; |
1137 | ||
a0ff9e1a SM |
1138 | std::vector<CORE_ADDR> next_pcs; |
1139 | ||
ce5eab59 | 1140 | for (index = 0; index <= last_breakpoint; index++) |
a0ff9e1a | 1141 | next_pcs.push_back (breaks[index]); |
ce5eab59 | 1142 | |
93f9a11f | 1143 | return next_pcs; |
ce5eab59 UW |
1144 | } |
1145 | ||
c906108c | 1146 | |
c906108c SS |
1147 | #define SIGNED_SHORT(x) \ |
1148 | ((sizeof (short) == 2) \ | |
1149 | ? ((int)(short)(x)) \ | |
1150 | : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000))) | |
1151 | ||
1152 | #define GET_SRC_REG(x) (((x) >> 21) & 0x1f) | |
1153 | ||
55d05f3b KB |
1154 | /* Limit the number of skipped non-prologue instructions, as the examining |
1155 | of the prologue is expensive. */ | |
1156 | static int max_skip_non_prologue_insns = 10; | |
1157 | ||
773df3e5 JB |
1158 | /* Return nonzero if the given instruction OP can be part of the prologue |
1159 | of a function and saves a parameter on the stack. FRAMEP should be | |
1160 | set if one of the previous instructions in the function has set the | |
1161 | Frame Pointer. */ | |
1162 | ||
1163 | static int | |
1164 | store_param_on_stack_p (unsigned long op, int framep, int *r0_contains_arg) | |
1165 | { | |
1166 | /* Move parameters from argument registers to temporary register. */ | |
1167 | if ((op & 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */ | |
1168 | { | |
1169 | /* Rx must be scratch register r0. */ | |
1170 | const int rx_regno = (op >> 16) & 31; | |
1171 | /* Ry: Only r3 - r10 are used for parameter passing. */ | |
1172 | const int ry_regno = GET_SRC_REG (op); | |
1173 | ||
1174 | if (rx_regno == 0 && ry_regno >= 3 && ry_regno <= 10) | |
dda83cd7 SM |
1175 | { |
1176 | *r0_contains_arg = 1; | |
1177 | return 1; | |
1178 | } | |
773df3e5 | 1179 | else |
dda83cd7 | 1180 | return 0; |
773df3e5 JB |
1181 | } |
1182 | ||
1183 | /* Save a General Purpose Register on stack. */ | |
1184 | ||
1185 | if ((op & 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */ | |
1186 | (op & 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */ | |
1187 | { | |
1188 | /* Rx: Only r3 - r10 are used for parameter passing. */ | |
1189 | const int rx_regno = GET_SRC_REG (op); | |
1190 | ||
1191 | return (rx_regno >= 3 && rx_regno <= 10); | |
1192 | } | |
dda83cd7 | 1193 | |
773df3e5 JB |
1194 | /* Save a General Purpose Register on stack via the Frame Pointer. */ |
1195 | ||
1196 | if (framep && | |
1197 | ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */ | |
1198 | (op & 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */ | |
1199 | (op & 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */ | |
1200 | { | |
1201 | /* Rx: Usually, only r3 - r10 are used for parameter passing. | |
dda83cd7 | 1202 | However, the compiler sometimes uses r0 to hold an argument. */ |
773df3e5 JB |
1203 | const int rx_regno = GET_SRC_REG (op); |
1204 | ||
1205 | return ((rx_regno >= 3 && rx_regno <= 10) | |
dda83cd7 | 1206 | || (rx_regno == 0 && *r0_contains_arg)); |
773df3e5 JB |
1207 | } |
1208 | ||
1209 | if ((op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */ | |
1210 | { | |
1211 | /* Only f2 - f8 are used for parameter passing. */ | |
1212 | const int src_regno = GET_SRC_REG (op); | |
1213 | ||
1214 | return (src_regno >= 2 && src_regno <= 8); | |
1215 | } | |
1216 | ||
1217 | if (framep && ((op & 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */ | |
1218 | { | |
1219 | /* Only f2 - f8 are used for parameter passing. */ | |
1220 | const int src_regno = GET_SRC_REG (op); | |
1221 | ||
1222 | return (src_regno >= 2 && src_regno <= 8); | |
1223 | } | |
1224 | ||
1225 | /* Not an insn that saves a parameter on stack. */ | |
1226 | return 0; | |
1227 | } | |
55d05f3b | 1228 | |
3c77c82a DJ |
1229 | /* Assuming that INSN is a "bl" instruction located at PC, return |
1230 | nonzero if the destination of the branch is a "blrl" instruction. | |
1231 | ||
1232 | This sequence is sometimes found in certain function prologues. | |
1233 | It allows the function to load the LR register with a value that | |
1234 | they can use to access PIC data using PC-relative offsets. */ | |
1235 | ||
1236 | static int | |
e17a4113 | 1237 | bl_to_blrl_insn_p (CORE_ADDR pc, int insn, enum bfd_endian byte_order) |
3c77c82a | 1238 | { |
0b1b3e42 UW |
1239 | CORE_ADDR dest; |
1240 | int immediate; | |
1241 | int absolute; | |
3c77c82a DJ |
1242 | int dest_insn; |
1243 | ||
0b1b3e42 UW |
1244 | absolute = (int) ((insn >> 1) & 1); |
1245 | immediate = ((insn & ~3) << 6) >> 6; | |
1246 | if (absolute) | |
1247 | dest = immediate; | |
1248 | else | |
1249 | dest = pc + immediate; | |
1250 | ||
e17a4113 | 1251 | dest_insn = read_memory_integer (dest, 4, byte_order); |
3c77c82a DJ |
1252 | if ((dest_insn & 0xfc00ffff) == 0x4c000021) /* blrl */ |
1253 | return 1; | |
1254 | ||
1255 | return 0; | |
1256 | } | |
1257 | ||
dd6d677f PFC |
1258 | /* Return true if OP is a stw or std instruction with |
1259 | register operands RS and RA and any immediate offset. | |
1260 | ||
1261 | If WITH_UPDATE is true, also return true if OP is | |
1262 | a stwu or stdu instruction with the same operands. | |
1263 | ||
1264 | Return false otherwise. | |
1265 | */ | |
1266 | static bool | |
1267 | store_insn_p (unsigned long op, unsigned long rs, | |
1268 | unsigned long ra, bool with_update) | |
1269 | { | |
1270 | rs = rs << 21; | |
1271 | ra = ra << 16; | |
1272 | ||
1273 | if (/* std RS, SIMM(RA) */ | |
1274 | ((op & 0xffff0003) == (rs | ra | 0xf8000000)) || | |
1275 | /* stw RS, SIMM(RA) */ | |
1276 | ((op & 0xffff0000) == (rs | ra | 0x90000000))) | |
1277 | return true; | |
1278 | ||
1279 | if (with_update) | |
1280 | { | |
1281 | if (/* stdu RS, SIMM(RA) */ | |
1282 | ((op & 0xffff0003) == (rs | ra | 0xf8000001)) || | |
1283 | /* stwu RS, SIMM(RA) */ | |
1284 | ((op & 0xffff0000) == (rs | ra | 0x94000000))) | |
1285 | return true; | |
1286 | } | |
1287 | ||
1288 | return false; | |
1289 | } | |
1290 | ||
0df8b418 | 1291 | /* Masks for decoding a branch-and-link (bl) instruction. |
8ab3d180 KB |
1292 | |
1293 | BL_MASK and BL_INSTRUCTION are used in combination with each other. | |
1294 | The former is anded with the opcode in question; if the result of | |
1295 | this masking operation is equal to BL_INSTRUCTION, then the opcode in | |
1296 | question is a ``bl'' instruction. | |
1297 | ||
85102364 | 1298 | BL_DISPLACEMENT_MASK is anded with the opcode in order to extract |
8ab3d180 KB |
1299 | the branch displacement. */ |
1300 | ||
1301 | #define BL_MASK 0xfc000001 | |
1302 | #define BL_INSTRUCTION 0x48000001 | |
1303 | #define BL_DISPLACEMENT_MASK 0x03fffffc | |
1304 | ||
de9f48f0 | 1305 | static unsigned long |
e17a4113 | 1306 | rs6000_fetch_instruction (struct gdbarch *gdbarch, const CORE_ADDR pc) |
de9f48f0 | 1307 | { |
e17a4113 | 1308 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
de9f48f0 JG |
1309 | gdb_byte buf[4]; |
1310 | unsigned long op; | |
1311 | ||
1312 | /* Fetch the instruction and convert it to an integer. */ | |
1313 | if (target_read_memory (pc, buf, 4)) | |
1314 | return 0; | |
e17a4113 | 1315 | op = extract_unsigned_integer (buf, 4, byte_order); |
de9f48f0 JG |
1316 | |
1317 | return op; | |
1318 | } | |
1319 | ||
1320 | /* GCC generates several well-known sequences of instructions at the begining | |
1321 | of each function prologue when compiling with -fstack-check. If one of | |
1322 | such sequences starts at START_PC, then return the address of the | |
1323 | instruction immediately past this sequence. Otherwise, return START_PC. */ | |
1324 | ||
1325 | static CORE_ADDR | |
e17a4113 | 1326 | rs6000_skip_stack_check (struct gdbarch *gdbarch, const CORE_ADDR start_pc) |
de9f48f0 JG |
1327 | { |
1328 | CORE_ADDR pc = start_pc; | |
e17a4113 | 1329 | unsigned long op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 JG |
1330 | |
1331 | /* First possible sequence: A small number of probes. | |
dda83cd7 SM |
1332 | stw 0, -<some immediate>(1) |
1333 | [repeat this instruction any (small) number of times]. */ | |
de9f48f0 JG |
1334 | |
1335 | if ((op & 0xffff0000) == 0x90010000) | |
1336 | { | |
1337 | while ((op & 0xffff0000) == 0x90010000) | |
dda83cd7 SM |
1338 | { |
1339 | pc = pc + 4; | |
1340 | op = rs6000_fetch_instruction (gdbarch, pc); | |
1341 | } | |
de9f48f0 JG |
1342 | return pc; |
1343 | } | |
1344 | ||
1345 | /* Second sequence: A probing loop. | |
dda83cd7 SM |
1346 | addi 12,1,-<some immediate> |
1347 | lis 0,-<some immediate> | |
1348 | [possibly ori 0,0,<some immediate>] | |
1349 | add 0,12,0 | |
1350 | cmpw 0,12,0 | |
1351 | beq 0,<disp> | |
1352 | addi 12,12,-<some immediate> | |
1353 | stw 0,0(12) | |
1354 | b <disp> | |
1355 | [possibly one last probe: stw 0,<some immediate>(12)]. */ | |
de9f48f0 JG |
1356 | |
1357 | while (1) | |
1358 | { | |
1359 | /* addi 12,1,-<some immediate> */ | |
1360 | if ((op & 0xffff0000) != 0x39810000) | |
dda83cd7 | 1361 | break; |
de9f48f0 JG |
1362 | |
1363 | /* lis 0,-<some immediate> */ | |
1364 | pc = pc + 4; | |
e17a4113 | 1365 | op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 | 1366 | if ((op & 0xffff0000) != 0x3c000000) |
dda83cd7 | 1367 | break; |
de9f48f0 JG |
1368 | |
1369 | pc = pc + 4; | |
e17a4113 | 1370 | op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 JG |
1371 | /* [possibly ori 0,0,<some immediate>] */ |
1372 | if ((op & 0xffff0000) == 0x60000000) | |
dda83cd7 SM |
1373 | { |
1374 | pc = pc + 4; | |
1375 | op = rs6000_fetch_instruction (gdbarch, pc); | |
1376 | } | |
de9f48f0 JG |
1377 | /* add 0,12,0 */ |
1378 | if (op != 0x7c0c0214) | |
dda83cd7 | 1379 | break; |
de9f48f0 JG |
1380 | |
1381 | /* cmpw 0,12,0 */ | |
1382 | pc = pc + 4; | |
e17a4113 | 1383 | op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 | 1384 | if (op != 0x7c0c0000) |
dda83cd7 | 1385 | break; |
de9f48f0 JG |
1386 | |
1387 | /* beq 0,<disp> */ | |
1388 | pc = pc + 4; | |
e17a4113 | 1389 | op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 | 1390 | if ((op & 0xff9f0001) != 0x41820000) |
dda83cd7 | 1391 | break; |
de9f48f0 JG |
1392 | |
1393 | /* addi 12,12,-<some immediate> */ | |
1394 | pc = pc + 4; | |
e17a4113 | 1395 | op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 | 1396 | if ((op & 0xffff0000) != 0x398c0000) |
dda83cd7 | 1397 | break; |
de9f48f0 JG |
1398 | |
1399 | /* stw 0,0(12) */ | |
1400 | pc = pc + 4; | |
e17a4113 | 1401 | op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 | 1402 | if (op != 0x900c0000) |
dda83cd7 | 1403 | break; |
de9f48f0 JG |
1404 | |
1405 | /* b <disp> */ | |
1406 | pc = pc + 4; | |
e17a4113 | 1407 | op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 | 1408 | if ((op & 0xfc000001) != 0x48000000) |
dda83cd7 | 1409 | break; |
de9f48f0 | 1410 | |
0df8b418 | 1411 | /* [possibly one last probe: stw 0,<some immediate>(12)]. */ |
de9f48f0 | 1412 | pc = pc + 4; |
e17a4113 | 1413 | op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 | 1414 | if ((op & 0xffff0000) == 0x900c0000) |
dda83cd7 SM |
1415 | { |
1416 | pc = pc + 4; | |
1417 | op = rs6000_fetch_instruction (gdbarch, pc); | |
1418 | } | |
de9f48f0 JG |
1419 | |
1420 | /* We found a valid stack-check sequence, return the new PC. */ | |
1421 | return pc; | |
1422 | } | |
1423 | ||
30baf67b | 1424 | /* Third sequence: No probe; instead, a comparison between the stack size |
de9f48f0 JG |
1425 | limit (saved in a run-time global variable) and the current stack |
1426 | pointer: | |
1427 | ||
dda83cd7 SM |
1428 | addi 0,1,-<some immediate> |
1429 | lis 12,__gnat_stack_limit@ha | |
1430 | lwz 12,__gnat_stack_limit@l(12) | |
1431 | twllt 0,12 | |
de9f48f0 JG |
1432 | |
1433 | or, with a small variant in the case of a bigger stack frame: | |
dda83cd7 SM |
1434 | addis 0,1,<some immediate> |
1435 | addic 0,0,-<some immediate> | |
1436 | lis 12,__gnat_stack_limit@ha | |
1437 | lwz 12,__gnat_stack_limit@l(12) | |
1438 | twllt 0,12 | |
de9f48f0 JG |
1439 | */ |
1440 | while (1) | |
1441 | { | |
1442 | /* addi 0,1,-<some immediate> */ | |
1443 | if ((op & 0xffff0000) != 0x38010000) | |
dda83cd7 SM |
1444 | { |
1445 | /* small stack frame variant not recognized; try the | |
1446 | big stack frame variant: */ | |
de9f48f0 | 1447 | |
dda83cd7 SM |
1448 | /* addis 0,1,<some immediate> */ |
1449 | if ((op & 0xffff0000) != 0x3c010000) | |
1450 | break; | |
de9f48f0 | 1451 | |
dda83cd7 SM |
1452 | /* addic 0,0,-<some immediate> */ |
1453 | pc = pc + 4; | |
1454 | op = rs6000_fetch_instruction (gdbarch, pc); | |
1455 | if ((op & 0xffff0000) != 0x30000000) | |
1456 | break; | |
1457 | } | |
de9f48f0 JG |
1458 | |
1459 | /* lis 12,<some immediate> */ | |
1460 | pc = pc + 4; | |
e17a4113 | 1461 | op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 | 1462 | if ((op & 0xffff0000) != 0x3d800000) |
dda83cd7 | 1463 | break; |
de9f48f0 JG |
1464 | |
1465 | /* lwz 12,<some immediate>(12) */ | |
1466 | pc = pc + 4; | |
e17a4113 | 1467 | op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 | 1468 | if ((op & 0xffff0000) != 0x818c0000) |
dda83cd7 | 1469 | break; |
de9f48f0 JG |
1470 | |
1471 | /* twllt 0,12 */ | |
1472 | pc = pc + 4; | |
e17a4113 | 1473 | op = rs6000_fetch_instruction (gdbarch, pc); |
de9f48f0 | 1474 | if ((op & 0xfffffffe) != 0x7c406008) |
dda83cd7 | 1475 | break; |
de9f48f0 JG |
1476 | |
1477 | /* We found a valid stack-check sequence, return the new PC. */ | |
1478 | return pc; | |
1479 | } | |
1480 | ||
1481 | /* No stack check code in our prologue, return the start_pc. */ | |
1482 | return start_pc; | |
1483 | } | |
1484 | ||
6a16c029 TJB |
1485 | /* return pc value after skipping a function prologue and also return |
1486 | information about a function frame. | |
1487 | ||
1488 | in struct rs6000_framedata fdata: | |
1489 | - frameless is TRUE, if function does not have a frame. | |
1490 | - nosavedpc is TRUE, if function does not save %pc value in its frame. | |
1491 | - offset is the initial size of this stack frame --- the amount by | |
1492 | which we decrement the sp to allocate the frame. | |
1493 | - saved_gpr is the number of the first saved gpr. | |
1494 | - saved_fpr is the number of the first saved fpr. | |
1495 | - saved_vr is the number of the first saved vr. | |
1496 | - saved_ev is the number of the first saved ev. | |
1497 | - alloca_reg is the number of the register used for alloca() handling. | |
1498 | Otherwise -1. | |
1499 | - gpr_offset is the offset of the first saved gpr from the previous frame. | |
1500 | - fpr_offset is the offset of the first saved fpr from the previous frame. | |
1501 | - vr_offset is the offset of the first saved vr from the previous frame. | |
1502 | - ev_offset is the offset of the first saved ev from the previous frame. | |
1503 | - lr_offset is the offset of the saved lr | |
1504 | - cr_offset is the offset of the saved cr | |
0df8b418 | 1505 | - vrsave_offset is the offset of the saved vrsave register. */ |
6a16c029 | 1506 | |
7a78ae4e | 1507 | static CORE_ADDR |
be8626e0 MD |
1508 | skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, CORE_ADDR lim_pc, |
1509 | struct rs6000_framedata *fdata) | |
c906108c SS |
1510 | { |
1511 | CORE_ADDR orig_pc = pc; | |
55d05f3b | 1512 | CORE_ADDR last_prologue_pc = pc; |
6be8bc0c | 1513 | CORE_ADDR li_found_pc = 0; |
50fd1280 | 1514 | gdb_byte buf[4]; |
c906108c SS |
1515 | unsigned long op; |
1516 | long offset = 0; | |
dd6d677f | 1517 | long alloca_reg_offset = 0; |
6be8bc0c | 1518 | long vr_saved_offset = 0; |
482ca3f5 KB |
1519 | int lr_reg = -1; |
1520 | int cr_reg = -1; | |
6be8bc0c | 1521 | int vr_reg = -1; |
96ff0de4 EZ |
1522 | int ev_reg = -1; |
1523 | long ev_offset = 0; | |
6be8bc0c | 1524 | int vrsave_reg = -1; |
c906108c SS |
1525 | int reg; |
1526 | int framep = 0; | |
1527 | int minimal_toc_loaded = 0; | |
ddb20c56 | 1528 | int prev_insn_was_prologue_insn = 1; |
55d05f3b | 1529 | int num_skip_non_prologue_insns = 0; |
773df3e5 | 1530 | int r0_contains_arg = 0; |
be8626e0 MD |
1531 | const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (gdbarch); |
1532 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
e17a4113 | 1533 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
c906108c | 1534 | |
ddb20c56 | 1535 | memset (fdata, 0, sizeof (struct rs6000_framedata)); |
c906108c SS |
1536 | fdata->saved_gpr = -1; |
1537 | fdata->saved_fpr = -1; | |
6be8bc0c | 1538 | fdata->saved_vr = -1; |
96ff0de4 | 1539 | fdata->saved_ev = -1; |
c906108c SS |
1540 | fdata->alloca_reg = -1; |
1541 | fdata->frameless = 1; | |
1542 | fdata->nosavedpc = 1; | |
46a9b8ed | 1543 | fdata->lr_register = -1; |
c906108c | 1544 | |
e17a4113 | 1545 | pc = rs6000_skip_stack_check (gdbarch, pc); |
de9f48f0 JG |
1546 | if (pc >= lim_pc) |
1547 | pc = lim_pc; | |
1548 | ||
55d05f3b | 1549 | for (;; pc += 4) |
c906108c | 1550 | { |
ddb20c56 | 1551 | /* Sometimes it isn't clear if an instruction is a prologue |
dda83cd7 | 1552 | instruction or not. When we encounter one of these ambiguous |
ddb20c56 | 1553 | cases, we'll set prev_insn_was_prologue_insn to 0 (false). |
0df8b418 | 1554 | Otherwise, we'll assume that it really is a prologue instruction. */ |
ddb20c56 KB |
1555 | if (prev_insn_was_prologue_insn) |
1556 | last_prologue_pc = pc; | |
55d05f3b KB |
1557 | |
1558 | /* Stop scanning if we've hit the limit. */ | |
4e463ff5 | 1559 | if (pc >= lim_pc) |
55d05f3b KB |
1560 | break; |
1561 | ||
ddb20c56 KB |
1562 | prev_insn_was_prologue_insn = 1; |
1563 | ||
55d05f3b | 1564 | /* Fetch the instruction and convert it to an integer. */ |
ddb20c56 KB |
1565 | if (target_read_memory (pc, buf, 4)) |
1566 | break; | |
e17a4113 | 1567 | op = extract_unsigned_integer (buf, 4, byte_order); |
c906108c | 1568 | |
c5aa993b JM |
1569 | if ((op & 0xfc1fffff) == 0x7c0802a6) |
1570 | { /* mflr Rx */ | |
43b1ab88 AC |
1571 | /* Since shared library / PIC code, which needs to get its |
1572 | address at runtime, can appear to save more than one link | |
1573 | register vis: | |
1574 | ||
1575 | *INDENT-OFF* | |
1576 | stwu r1,-304(r1) | |
1577 | mflr r3 | |
1578 | bl 0xff570d0 (blrl) | |
1579 | stw r30,296(r1) | |
1580 | mflr r30 | |
1581 | stw r31,300(r1) | |
1582 | stw r3,308(r1); | |
1583 | ... | |
1584 | *INDENT-ON* | |
1585 | ||
1586 | remember just the first one, but skip over additional | |
1587 | ones. */ | |
721d14ba | 1588 | if (lr_reg == -1) |
dd6d677f | 1589 | lr_reg = (op & 0x03e00000) >> 21; |
dda83cd7 SM |
1590 | if (lr_reg == 0) |
1591 | r0_contains_arg = 0; | |
c5aa993b | 1592 | continue; |
c5aa993b JM |
1593 | } |
1594 | else if ((op & 0xfc1fffff) == 0x7c000026) | |
1595 | { /* mfcr Rx */ | |
dd6d677f | 1596 | cr_reg = (op & 0x03e00000) >> 21; |
dda83cd7 SM |
1597 | if (cr_reg == 0) |
1598 | r0_contains_arg = 0; | |
c5aa993b | 1599 | continue; |
c906108c | 1600 | |
c906108c | 1601 | } |
c5aa993b JM |
1602 | else if ((op & 0xfc1f0000) == 0xd8010000) |
1603 | { /* stfd Rx,NUM(r1) */ | |
1604 | reg = GET_SRC_REG (op); | |
1605 | if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg) | |
1606 | { | |
1607 | fdata->saved_fpr = reg; | |
1608 | fdata->fpr_offset = SIGNED_SHORT (op) + offset; | |
1609 | } | |
1610 | continue; | |
c906108c | 1611 | |
c5aa993b JM |
1612 | } |
1613 | else if (((op & 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */ | |
7a78ae4e ND |
1614 | (((op & 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */ |
1615 | (op & 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */ | |
1616 | (op & 0x03e00000) >= 0x01a00000)) /* rx >= r13 */ | |
c5aa993b JM |
1617 | { |
1618 | ||
1619 | reg = GET_SRC_REG (op); | |
46a9b8ed DJ |
1620 | if ((op & 0xfc1f0000) == 0xbc010000) |
1621 | fdata->gpr_mask |= ~((1U << reg) - 1); | |
1622 | else | |
1623 | fdata->gpr_mask |= 1U << reg; | |
c5aa993b JM |
1624 | if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg) |
1625 | { | |
1626 | fdata->saved_gpr = reg; | |
7a78ae4e | 1627 | if ((op & 0xfc1f0003) == 0xf8010000) |
98f08d3d | 1628 | op &= ~3UL; |
c5aa993b JM |
1629 | fdata->gpr_offset = SIGNED_SHORT (op) + offset; |
1630 | } | |
1631 | continue; | |
c906108c | 1632 | |
ddb20c56 | 1633 | } |
ef1bc9e7 AM |
1634 | else if ((op & 0xffff0000) == 0x3c4c0000 |
1635 | || (op & 0xffff0000) == 0x3c400000 | |
1636 | || (op & 0xffff0000) == 0x38420000) | |
1637 | { | |
1638 | /* . 0: addis 2,12,.TOC.-0b@ha | |
1639 | . addi 2,2,.TOC.-0b@l | |
1640 | or | |
1641 | . lis 2,.TOC.@ha | |
1642 | . addi 2,2,.TOC.@l | |
1643 | used by ELFv2 global entry points to set up r2. */ | |
1644 | continue; | |
1645 | } | |
1646 | else if (op == 0x60000000) | |
dda83cd7 | 1647 | { |
96ff0de4 | 1648 | /* nop */ |
ddb20c56 KB |
1649 | /* Allow nops in the prologue, but do not consider them to |
1650 | be part of the prologue unless followed by other prologue | |
0df8b418 | 1651 | instructions. */ |
ddb20c56 KB |
1652 | prev_insn_was_prologue_insn = 0; |
1653 | continue; | |
1654 | ||
c906108c | 1655 | } |
c5aa993b | 1656 | else if ((op & 0xffff0000) == 0x3c000000) |
ef1bc9e7 | 1657 | { /* addis 0,0,NUM, used for >= 32k frames */ |
c5aa993b JM |
1658 | fdata->offset = (op & 0x0000ffff) << 16; |
1659 | fdata->frameless = 0; | |
dda83cd7 | 1660 | r0_contains_arg = 0; |
c5aa993b JM |
1661 | continue; |
1662 | ||
1663 | } | |
1664 | else if ((op & 0xffff0000) == 0x60000000) | |
ef1bc9e7 | 1665 | { /* ori 0,0,NUM, 2nd half of >= 32k frames */ |
c5aa993b JM |
1666 | fdata->offset |= (op & 0x0000ffff); |
1667 | fdata->frameless = 0; | |
dda83cd7 | 1668 | r0_contains_arg = 0; |
c5aa993b JM |
1669 | continue; |
1670 | ||
1671 | } | |
be723e22 | 1672 | else if (lr_reg >= 0 && |
dd6d677f PFC |
1673 | ((store_insn_p (op, lr_reg, 1, true)) || |
1674 | (framep && | |
1675 | (store_insn_p (op, lr_reg, | |
1676 | fdata->alloca_reg - tdep->ppc_gp0_regnum, | |
1677 | false))))) | |
1678 | { | |
1679 | if (store_insn_p (op, lr_reg, 1, true)) | |
1680 | fdata->lr_offset = offset; | |
1681 | else /* LR save through frame pointer. */ | |
1682 | fdata->lr_offset = alloca_reg_offset; | |
1683 | ||
c5aa993b | 1684 | fdata->nosavedpc = 0; |
be723e22 MS |
1685 | /* Invalidate lr_reg, but don't set it to -1. |
1686 | That would mean that it had never been set. */ | |
1687 | lr_reg = -2; | |
98f08d3d KB |
1688 | if ((op & 0xfc000003) == 0xf8000000 || /* std */ |
1689 | (op & 0xfc000000) == 0x90000000) /* stw */ | |
1690 | { | |
1691 | /* Does not update r1, so add displacement to lr_offset. */ | |
1692 | fdata->lr_offset += SIGNED_SHORT (op); | |
1693 | } | |
c5aa993b JM |
1694 | continue; |
1695 | ||
1696 | } | |
be723e22 | 1697 | else if (cr_reg >= 0 && |
dd6d677f PFC |
1698 | (store_insn_p (op, cr_reg, 1, true))) |
1699 | { | |
98f08d3d | 1700 | fdata->cr_offset = offset; |
be723e22 MS |
1701 | /* Invalidate cr_reg, but don't set it to -1. |
1702 | That would mean that it had never been set. */ | |
1703 | cr_reg = -2; | |
98f08d3d KB |
1704 | if ((op & 0xfc000003) == 0xf8000000 || |
1705 | (op & 0xfc000000) == 0x90000000) | |
1706 | { | |
1707 | /* Does not update r1, so add displacement to cr_offset. */ | |
1708 | fdata->cr_offset += SIGNED_SHORT (op); | |
1709 | } | |
c5aa993b JM |
1710 | continue; |
1711 | ||
1712 | } | |
721d14ba DJ |
1713 | else if ((op & 0xfe80ffff) == 0x42800005 && lr_reg != -1) |
1714 | { | |
1715 | /* bcl 20,xx,.+4 is used to get the current PC, with or without | |
1716 | prediction bits. If the LR has already been saved, we can | |
1717 | skip it. */ | |
1718 | continue; | |
1719 | } | |
c5aa993b JM |
1720 | else if (op == 0x48000005) |
1721 | { /* bl .+4 used in | |
1722 | -mrelocatable */ | |
46a9b8ed | 1723 | fdata->used_bl = 1; |
c5aa993b JM |
1724 | continue; |
1725 | ||
1726 | } | |
1727 | else if (op == 0x48000004) | |
1728 | { /* b .+4 (xlc) */ | |
1729 | break; | |
1730 | ||
c5aa993b | 1731 | } |
6be8bc0c EZ |
1732 | else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used |
1733 | in V.4 -mminimal-toc */ | |
c5aa993b JM |
1734 | (op & 0xffff0000) == 0x3bde0000) |
1735 | { /* addi 30,30,foo@l */ | |
1736 | continue; | |
c906108c | 1737 | |
c5aa993b JM |
1738 | } |
1739 | else if ((op & 0xfc000001) == 0x48000001) | |
1740 | { /* bl foo, | |
0df8b418 | 1741 | to save fprs??? */ |
c906108c | 1742 | |
c5aa993b | 1743 | fdata->frameless = 0; |
3c77c82a DJ |
1744 | |
1745 | /* If the return address has already been saved, we can skip | |
1746 | calls to blrl (for PIC). */ | |
dda83cd7 | 1747 | if (lr_reg != -1 && bl_to_blrl_insn_p (pc, op, byte_order)) |
46a9b8ed DJ |
1748 | { |
1749 | fdata->used_bl = 1; | |
1750 | continue; | |
1751 | } | |
3c77c82a | 1752 | |
6be8bc0c | 1753 | /* Don't skip over the subroutine call if it is not within |
ebd98106 FF |
1754 | the first three instructions of the prologue and either |
1755 | we have no line table information or the line info tells | |
1756 | us that the subroutine call is not part of the line | |
1757 | associated with the prologue. */ | |
c5aa993b | 1758 | if ((pc - orig_pc) > 8) |
ebd98106 FF |
1759 | { |
1760 | struct symtab_and_line prologue_sal = find_pc_line (orig_pc, 0); | |
1761 | struct symtab_and_line this_sal = find_pc_line (pc, 0); | |
1762 | ||
0df8b418 MS |
1763 | if ((prologue_sal.line == 0) |
1764 | || (prologue_sal.line != this_sal.line)) | |
ebd98106 FF |
1765 | break; |
1766 | } | |
c5aa993b | 1767 | |
e17a4113 | 1768 | op = read_memory_integer (pc + 4, 4, byte_order); |
c5aa993b | 1769 | |
6be8bc0c EZ |
1770 | /* At this point, make sure this is not a trampoline |
1771 | function (a function that simply calls another functions, | |
1772 | and nothing else). If the next is not a nop, this branch | |
0df8b418 | 1773 | was part of the function prologue. */ |
c5aa993b JM |
1774 | |
1775 | if (op == 0x4def7b82 || op == 0) /* crorc 15, 15, 15 */ | |
0df8b418 MS |
1776 | break; /* Don't skip over |
1777 | this branch. */ | |
c5aa993b | 1778 | |
46a9b8ed DJ |
1779 | fdata->used_bl = 1; |
1780 | continue; | |
c5aa993b | 1781 | } |
98f08d3d KB |
1782 | /* update stack pointer */ |
1783 | else if ((op & 0xfc1f0000) == 0x94010000) | |
1784 | { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */ | |
c5aa993b JM |
1785 | fdata->frameless = 0; |
1786 | fdata->offset = SIGNED_SHORT (op); | |
1787 | offset = fdata->offset; | |
1788 | continue; | |
c5aa993b | 1789 | } |
7a8f494c PFC |
1790 | else if ((op & 0xfc1f07fa) == 0x7c01016a) |
1791 | { /* stwux rX,r1,rY || stdux rX,r1,rY */ | |
0df8b418 | 1792 | /* No way to figure out what r1 is going to be. */ |
98f08d3d KB |
1793 | fdata->frameless = 0; |
1794 | offset = fdata->offset; | |
1795 | continue; | |
1796 | } | |
1797 | else if ((op & 0xfc1f0003) == 0xf8010001) | |
1798 | { /* stdu rX,NUM(r1) */ | |
1799 | fdata->frameless = 0; | |
1800 | fdata->offset = SIGNED_SHORT (op & ~3UL); | |
1801 | offset = fdata->offset; | |
1802 | continue; | |
1803 | } | |
7313566f FF |
1804 | else if ((op & 0xffff0000) == 0x38210000) |
1805 | { /* addi r1,r1,SIMM */ | |
1806 | fdata->frameless = 0; | |
1807 | fdata->offset += SIGNED_SHORT (op); | |
1808 | offset = fdata->offset; | |
1809 | continue; | |
1810 | } | |
4e463ff5 DJ |
1811 | /* Load up minimal toc pointer. Do not treat an epilogue restore |
1812 | of r31 as a minimal TOC load. */ | |
0df8b418 MS |
1813 | else if (((op >> 22) == 0x20f || /* l r31,... or l r30,... */ |
1814 | (op >> 22) == 0x3af) /* ld r31,... or ld r30,... */ | |
4e463ff5 | 1815 | && !framep |
c5aa993b | 1816 | && !minimal_toc_loaded) |
98f08d3d | 1817 | { |
c5aa993b JM |
1818 | minimal_toc_loaded = 1; |
1819 | continue; | |
1820 | ||
f6077098 | 1821 | /* move parameters from argument registers to local variable |
dda83cd7 | 1822 | registers */ |
f6077098 KB |
1823 | } |
1824 | else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */ | |
dda83cd7 SM |
1825 | (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */ |
1826 | (((op >> 21) & 31) <= 10) && | |
1827 | ((long) ((op >> 16) & 31) | |
0df8b418 | 1828 | >= fdata->saved_gpr)) /* Rx: local var reg */ |
f6077098 KB |
1829 | { |
1830 | continue; | |
1831 | ||
c5aa993b JM |
1832 | /* store parameters in stack */ |
1833 | } | |
e802b915 | 1834 | /* Move parameters from argument registers to temporary register. */ |
773df3e5 | 1835 | else if (store_param_on_stack_p (op, framep, &r0_contains_arg)) |
dda83cd7 | 1836 | { |
c5aa993b JM |
1837 | continue; |
1838 | ||
1839 | /* Set up frame pointer */ | |
1840 | } | |
76219d77 JB |
1841 | else if (op == 0x603d0000) /* oril r29, r1, 0x0 */ |
1842 | { | |
1843 | fdata->frameless = 0; | |
1844 | framep = 1; | |
1845 | fdata->alloca_reg = (tdep->ppc_gp0_regnum + 29); | |
dd6d677f | 1846 | alloca_reg_offset = offset; |
76219d77 JB |
1847 | continue; |
1848 | ||
1849 | /* Another way to set up the frame pointer. */ | |
1850 | } | |
c5aa993b JM |
1851 | else if (op == 0x603f0000 /* oril r31, r1, 0x0 */ |
1852 | || op == 0x7c3f0b78) | |
1853 | { /* mr r31, r1 */ | |
1854 | fdata->frameless = 0; | |
1855 | framep = 1; | |
6f99cb26 | 1856 | fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31); |
dd6d677f | 1857 | alloca_reg_offset = offset; |
c5aa993b JM |
1858 | continue; |
1859 | ||
1860 | /* Another way to set up the frame pointer. */ | |
1861 | } | |
1862 | else if ((op & 0xfc1fffff) == 0x38010000) | |
1863 | { /* addi rX, r1, 0x0 */ | |
1864 | fdata->frameless = 0; | |
1865 | framep = 1; | |
6f99cb26 AC |
1866 | fdata->alloca_reg = (tdep->ppc_gp0_regnum |
1867 | + ((op & ~0x38010000) >> 21)); | |
dd6d677f | 1868 | alloca_reg_offset = offset; |
c5aa993b | 1869 | continue; |
c5aa993b | 1870 | } |
6be8bc0c EZ |
1871 | /* AltiVec related instructions. */ |
1872 | /* Store the vrsave register (spr 256) in another register for | |
1873 | later manipulation, or load a register into the vrsave | |
1874 | register. 2 instructions are used: mfvrsave and | |
1875 | mtvrsave. They are shorthand notation for mfspr Rn, SPR256 | |
1876 | and mtspr SPR256, Rn. */ | |
1877 | /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110 | |
1878 | mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */ | |
1879 | else if ((op & 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */ | |
1880 | { | |
dda83cd7 | 1881 | vrsave_reg = GET_SRC_REG (op); |
6be8bc0c EZ |
1882 | continue; |
1883 | } | |
1884 | else if ((op & 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */ | |
dda83cd7 SM |
1885 | { |
1886 | continue; | |
1887 | } | |
6be8bc0c | 1888 | /* Store the register where vrsave was saved to onto the stack: |
dda83cd7 | 1889 | rS is the register where vrsave was stored in a previous |
6be8bc0c EZ |
1890 | instruction. */ |
1891 | /* 100100 sssss 00001 dddddddd dddddddd */ | |
1892 | else if ((op & 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */ | |
dda83cd7 SM |
1893 | { |
1894 | if (vrsave_reg == GET_SRC_REG (op)) | |
6be8bc0c EZ |
1895 | { |
1896 | fdata->vrsave_offset = SIGNED_SHORT (op) + offset; | |
1897 | vrsave_reg = -1; | |
1898 | } | |
dda83cd7 SM |
1899 | continue; |
1900 | } | |
6be8bc0c | 1901 | /* Compute the new value of vrsave, by modifying the register |
dda83cd7 | 1902 | where vrsave was saved to. */ |
6be8bc0c EZ |
1903 | else if (((op & 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */ |
1904 | || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */ | |
1905 | { | |
1906 | continue; | |
1907 | } | |
1908 | /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first | |
1909 | in a pair of insns to save the vector registers on the | |
1910 | stack. */ | |
1911 | /* 001110 00000 00000 iiii iiii iiii iiii */ | |
96ff0de4 EZ |
1912 | /* 001110 01110 00000 iiii iiii iiii iiii */ |
1913 | else if ((op & 0xffff0000) == 0x38000000 /* li r0, SIMM */ | |
dda83cd7 | 1914 | || (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */ |
6be8bc0c | 1915 | { |
dda83cd7 SM |
1916 | if ((op & 0xffff0000) == 0x38000000) |
1917 | r0_contains_arg = 0; | |
6be8bc0c EZ |
1918 | li_found_pc = pc; |
1919 | vr_saved_offset = SIGNED_SHORT (op); | |
773df3e5 | 1920 | |
dda83cd7 SM |
1921 | /* This insn by itself is not part of the prologue, unless |
1922 | if part of the pair of insns mentioned above. So do not | |
1923 | record this insn as part of the prologue yet. */ | |
1924 | prev_insn_was_prologue_insn = 0; | |
6be8bc0c EZ |
1925 | } |
1926 | /* Store vector register S at (r31+r0) aligned to 16 bytes. */ | |
1927 | /* 011111 sssss 11111 00000 00111001110 */ | |
1928 | else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */ | |
dda83cd7 | 1929 | { |
6be8bc0c EZ |
1930 | if (pc == (li_found_pc + 4)) |
1931 | { | |
1932 | vr_reg = GET_SRC_REG (op); | |
1933 | /* If this is the first vector reg to be saved, or if | |
1934 | it has a lower number than others previously seen, | |
1935 | reupdate the frame info. */ | |
1936 | if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg) | |
1937 | { | |
1938 | fdata->saved_vr = vr_reg; | |
1939 | fdata->vr_offset = vr_saved_offset + offset; | |
1940 | } | |
1941 | vr_saved_offset = -1; | |
1942 | vr_reg = -1; | |
1943 | li_found_pc = 0; | |
1944 | } | |
1945 | } | |
1946 | /* End AltiVec related instructions. */ | |
96ff0de4 EZ |
1947 | |
1948 | /* Start BookE related instructions. */ | |
1949 | /* Store gen register S at (r31+uimm). | |
dda83cd7 | 1950 | Any register less than r13 is volatile, so we don't care. */ |
96ff0de4 EZ |
1951 | /* 000100 sssss 11111 iiiii 01100100001 */ |
1952 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
1953 | && (op & 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */ | |
1954 | { | |
dda83cd7 | 1955 | if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */ |
96ff0de4 | 1956 | { |
dda83cd7 | 1957 | unsigned int imm; |
96ff0de4 | 1958 | ev_reg = GET_SRC_REG (op); |
dda83cd7 | 1959 | imm = (op >> 11) & 0x1f; |
96ff0de4 EZ |
1960 | ev_offset = imm * 8; |
1961 | /* If this is the first vector reg to be saved, or if | |
1962 | it has a lower number than others previously seen, | |
1963 | reupdate the frame info. */ | |
1964 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) | |
1965 | { | |
1966 | fdata->saved_ev = ev_reg; | |
1967 | fdata->ev_offset = ev_offset + offset; | |
1968 | } | |
1969 | } | |
dda83cd7 SM |
1970 | continue; |
1971 | } | |
96ff0de4 EZ |
1972 | /* Store gen register rS at (r1+rB). */ |
1973 | /* 000100 sssss 00001 bbbbb 01100100000 */ | |
1974 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
1975 | && (op & 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */ | |
1976 | { | |
dda83cd7 SM |
1977 | if (pc == (li_found_pc + 4)) |
1978 | { | |
1979 | ev_reg = GET_SRC_REG (op); | |
96ff0de4 | 1980 | /* If this is the first vector reg to be saved, or if |
dda83cd7 SM |
1981 | it has a lower number than others previously seen, |
1982 | reupdate the frame info. */ | |
1983 | /* We know the contents of rB from the previous instruction. */ | |
96ff0de4 EZ |
1984 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) |
1985 | { | |
dda83cd7 SM |
1986 | fdata->saved_ev = ev_reg; |
1987 | fdata->ev_offset = vr_saved_offset + offset; | |
96ff0de4 EZ |
1988 | } |
1989 | vr_saved_offset = -1; | |
1990 | ev_reg = -1; | |
1991 | li_found_pc = 0; | |
dda83cd7 SM |
1992 | } |
1993 | continue; | |
1994 | } | |
96ff0de4 EZ |
1995 | /* Store gen register r31 at (rA+uimm). */ |
1996 | /* 000100 11111 aaaaa iiiii 01100100001 */ | |
1997 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
1998 | && (op & 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */ | |
dda83cd7 SM |
1999 | { |
2000 | /* Wwe know that the source register is 31 already, but | |
2001 | it can't hurt to compute it. */ | |
96ff0de4 | 2002 | ev_reg = GET_SRC_REG (op); |
dda83cd7 | 2003 | ev_offset = ((op >> 11) & 0x1f) * 8; |
96ff0de4 EZ |
2004 | /* If this is the first vector reg to be saved, or if |
2005 | it has a lower number than others previously seen, | |
2006 | reupdate the frame info. */ | |
2007 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) | |
2008 | { | |
2009 | fdata->saved_ev = ev_reg; | |
2010 | fdata->ev_offset = ev_offset + offset; | |
2011 | } | |
2012 | ||
2013 | continue; | |
2014 | } | |
2015 | /* Store gen register S at (r31+r0). | |
dda83cd7 | 2016 | Store param on stack when offset from SP bigger than 4 bytes. */ |
96ff0de4 EZ |
2017 | /* 000100 sssss 11111 00000 01100100000 */ |
2018 | else if (arch_info->mach == bfd_mach_ppc_e500 | |
2019 | && (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */ | |
2020 | { | |
dda83cd7 SM |
2021 | if (pc == (li_found_pc + 4)) |
2022 | { | |
2023 | if ((op & 0x03e00000) >= 0x01a00000) | |
96ff0de4 EZ |
2024 | { |
2025 | ev_reg = GET_SRC_REG (op); | |
2026 | /* If this is the first vector reg to be saved, or if | |
2027 | it has a lower number than others previously seen, | |
2028 | reupdate the frame info. */ | |
dda83cd7 SM |
2029 | /* We know the contents of r0 from the previous |
2030 | instruction. */ | |
96ff0de4 EZ |
2031 | if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) |
2032 | { | |
2033 | fdata->saved_ev = ev_reg; | |
2034 | fdata->ev_offset = vr_saved_offset + offset; | |
2035 | } | |
2036 | ev_reg = -1; | |
2037 | } | |
2038 | vr_saved_offset = -1; | |
2039 | li_found_pc = 0; | |
2040 | continue; | |
dda83cd7 | 2041 | } |
96ff0de4 EZ |
2042 | } |
2043 | /* End BookE related instructions. */ | |
2044 | ||
c5aa993b JM |
2045 | else |
2046 | { | |
55d05f3b KB |
2047 | /* Not a recognized prologue instruction. |
2048 | Handle optimizer code motions into the prologue by continuing | |
2049 | the search if we have no valid frame yet or if the return | |
46a9b8ed DJ |
2050 | address is not yet saved in the frame. Also skip instructions |
2051 | if some of the GPRs expected to be saved are not yet saved. */ | |
2052 | if (fdata->frameless == 0 && fdata->nosavedpc == 0 | |
1cc62f2e JB |
2053 | && fdata->saved_gpr != -1) |
2054 | { | |
2055 | unsigned int all_mask = ~((1U << fdata->saved_gpr) - 1); | |
2056 | ||
2057 | if ((fdata->gpr_mask & all_mask) == all_mask) | |
2058 | break; | |
2059 | } | |
55d05f3b KB |
2060 | |
2061 | if (op == 0x4e800020 /* blr */ | |
2062 | || op == 0x4e800420) /* bctr */ | |
2063 | /* Do not scan past epilogue in frameless functions or | |
2064 | trampolines. */ | |
2065 | break; | |
2066 | if ((op & 0xf4000000) == 0x40000000) /* bxx */ | |
64366f1c | 2067 | /* Never skip branches. */ |
55d05f3b KB |
2068 | break; |
2069 | ||
2070 | if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns) | |
2071 | /* Do not scan too many insns, scanning insns is expensive with | |
2072 | remote targets. */ | |
2073 | break; | |
2074 | ||
2075 | /* Continue scanning. */ | |
2076 | prev_insn_was_prologue_insn = 0; | |
2077 | continue; | |
c5aa993b | 2078 | } |
c906108c SS |
2079 | } |
2080 | ||
2081 | #if 0 | |
2082 | /* I have problems with skipping over __main() that I need to address | |
0df8b418 | 2083 | * sometime. Previously, I used to use misc_function_vector which |
c906108c SS |
2084 | * didn't work as well as I wanted to be. -MGO */ |
2085 | ||
2086 | /* If the first thing after skipping a prolog is a branch to a function, | |
2087 | this might be a call to an initializer in main(), introduced by gcc2. | |
64366f1c | 2088 | We'd like to skip over it as well. Fortunately, xlc does some extra |
c906108c | 2089 | work before calling a function right after a prologue, thus we can |
64366f1c | 2090 | single out such gcc2 behaviour. */ |
c906108c | 2091 | |
c906108c | 2092 | |
c5aa993b | 2093 | if ((op & 0xfc000001) == 0x48000001) |
0df8b418 | 2094 | { /* bl foo, an initializer function? */ |
e17a4113 | 2095 | op = read_memory_integer (pc + 4, 4, byte_order); |
c5aa993b JM |
2096 | |
2097 | if (op == 0x4def7b82) | |
2098 | { /* cror 0xf, 0xf, 0xf (nop) */ | |
c906108c | 2099 | |
64366f1c EZ |
2100 | /* Check and see if we are in main. If so, skip over this |
2101 | initializer function as well. */ | |
c906108c | 2102 | |
c5aa993b | 2103 | tmp = find_pc_misc_function (pc); |
6314a349 AC |
2104 | if (tmp >= 0 |
2105 | && strcmp (misc_function_vector[tmp].name, main_name ()) == 0) | |
c5aa993b JM |
2106 | return pc + 8; |
2107 | } | |
c906108c | 2108 | } |
c906108c | 2109 | #endif /* 0 */ |
c5aa993b | 2110 | |
46a9b8ed | 2111 | if (pc == lim_pc && lr_reg >= 0) |
dd6d677f | 2112 | fdata->lr_register = lr_reg; |
46a9b8ed | 2113 | |
c5aa993b | 2114 | fdata->offset = -fdata->offset; |
ddb20c56 | 2115 | return last_prologue_pc; |
c906108c SS |
2116 | } |
2117 | ||
7a78ae4e | 2118 | static CORE_ADDR |
4a7622d1 | 2119 | rs6000_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
c906108c | 2120 | { |
4a7622d1 | 2121 | struct rs6000_framedata frame; |
e3acb115 | 2122 | CORE_ADDR limit_pc, func_addr, func_end_addr = 0; |
c906108c | 2123 | |
4a7622d1 UW |
2124 | /* See if we can determine the end of the prologue via the symbol table. |
2125 | If so, then return either PC, or the PC after the prologue, whichever | |
2126 | is greater. */ | |
e3acb115 | 2127 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end_addr)) |
c5aa993b | 2128 | { |
d80b854b UW |
2129 | CORE_ADDR post_prologue_pc |
2130 | = skip_prologue_using_sal (gdbarch, func_addr); | |
4a7622d1 | 2131 | if (post_prologue_pc != 0) |
325fac50 | 2132 | return std::max (pc, post_prologue_pc); |
c906108c | 2133 | } |
c906108c | 2134 | |
4a7622d1 UW |
2135 | /* Can't determine prologue from the symbol table, need to examine |
2136 | instructions. */ | |
c906108c | 2137 | |
4a7622d1 UW |
2138 | /* Find an upper limit on the function prologue using the debug |
2139 | information. If the debug information could not be used to provide | |
2140 | that bound, then use an arbitrary large number as the upper bound. */ | |
d80b854b | 2141 | limit_pc = skip_prologue_using_sal (gdbarch, pc); |
4a7622d1 UW |
2142 | if (limit_pc == 0) |
2143 | limit_pc = pc + 100; /* Magic. */ | |
794a477a | 2144 | |
e3acb115 JB |
2145 | /* Do not allow limit_pc to be past the function end, if we know |
2146 | where that end is... */ | |
2147 | if (func_end_addr && limit_pc > func_end_addr) | |
2148 | limit_pc = func_end_addr; | |
2149 | ||
4a7622d1 UW |
2150 | pc = skip_prologue (gdbarch, pc, limit_pc, &frame); |
2151 | return pc; | |
c906108c | 2152 | } |
c906108c | 2153 | |
8ab3d180 KB |
2154 | /* When compiling for EABI, some versions of GCC emit a call to __eabi |
2155 | in the prologue of main(). | |
2156 | ||
2157 | The function below examines the code pointed at by PC and checks to | |
2158 | see if it corresponds to a call to __eabi. If so, it returns the | |
2159 | address of the instruction following that call. Otherwise, it simply | |
2160 | returns PC. */ | |
2161 | ||
63807e1d | 2162 | static CORE_ADDR |
8ab3d180 KB |
2163 | rs6000_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
2164 | { | |
e17a4113 | 2165 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
8ab3d180 KB |
2166 | gdb_byte buf[4]; |
2167 | unsigned long op; | |
2168 | ||
2169 | if (target_read_memory (pc, buf, 4)) | |
2170 | return pc; | |
e17a4113 | 2171 | op = extract_unsigned_integer (buf, 4, byte_order); |
8ab3d180 KB |
2172 | |
2173 | if ((op & BL_MASK) == BL_INSTRUCTION) | |
2174 | { | |
2175 | CORE_ADDR displ = op & BL_DISPLACEMENT_MASK; | |
2176 | CORE_ADDR call_dest = pc + 4 + displ; | |
7cbd4a93 | 2177 | struct bound_minimal_symbol s = lookup_minimal_symbol_by_pc (call_dest); |
8ab3d180 KB |
2178 | |
2179 | /* We check for ___eabi (three leading underscores) in addition | |
dda83cd7 | 2180 | to __eabi in case the GCC option "-fleading-underscore" was |
8ab3d180 | 2181 | used to compile the program. */ |
7cbd4a93 | 2182 | if (s.minsym != NULL |
dda83cd7 | 2183 | && s.minsym->linkage_name () != NULL |
c9d95fa3 CB |
2184 | && (strcmp (s.minsym->linkage_name (), "__eabi") == 0 |
2185 | || strcmp (s.minsym->linkage_name (), "___eabi") == 0)) | |
8ab3d180 KB |
2186 | pc += 4; |
2187 | } | |
2188 | return pc; | |
2189 | } | |
383f0f5b | 2190 | |
4a7622d1 UW |
2191 | /* All the ABI's require 16 byte alignment. */ |
2192 | static CORE_ADDR | |
2193 | rs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
2194 | { | |
2195 | return (addr & -16); | |
c906108c SS |
2196 | } |
2197 | ||
977adac5 ND |
2198 | /* Return whether handle_inferior_event() should proceed through code |
2199 | starting at PC in function NAME when stepping. | |
2200 | ||
2201 | The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to | |
2202 | handle memory references that are too distant to fit in instructions | |
2203 | generated by the compiler. For example, if 'foo' in the following | |
2204 | instruction: | |
2205 | ||
2206 | lwz r9,foo(r2) | |
2207 | ||
2208 | is greater than 32767, the linker might replace the lwz with a branch to | |
2209 | somewhere in @FIX1 that does the load in 2 instructions and then branches | |
2210 | back to where execution should continue. | |
2211 | ||
2212 | GDB should silently step over @FIX code, just like AIX dbx does. | |
2ec664f5 MS |
2213 | Unfortunately, the linker uses the "b" instruction for the |
2214 | branches, meaning that the link register doesn't get set. | |
2215 | Therefore, GDB's usual step_over_function () mechanism won't work. | |
977adac5 | 2216 | |
e76f05fa UW |
2217 | Instead, use the gdbarch_skip_trampoline_code and |
2218 | gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past | |
2ec664f5 | 2219 | @FIX code. */ |
977adac5 | 2220 | |
63807e1d | 2221 | static int |
e17a4113 | 2222 | rs6000_in_solib_return_trampoline (struct gdbarch *gdbarch, |
2c02bd72 | 2223 | CORE_ADDR pc, const char *name) |
977adac5 | 2224 | { |
61012eef | 2225 | return name && startswith (name, "@FIX"); |
977adac5 ND |
2226 | } |
2227 | ||
2228 | /* Skip code that the user doesn't want to see when stepping: | |
2229 | ||
2230 | 1. Indirect function calls use a piece of trampoline code to do context | |
2231 | switching, i.e. to set the new TOC table. Skip such code if we are on | |
2232 | its first instruction (as when we have single-stepped to here). | |
2233 | ||
2234 | 2. Skip shared library trampoline code (which is different from | |
c906108c | 2235 | indirect function call trampolines). |
977adac5 ND |
2236 | |
2237 | 3. Skip bigtoc fixup code. | |
2238 | ||
c906108c | 2239 | Result is desired PC to step until, or NULL if we are not in |
977adac5 | 2240 | code that should be skipped. */ |
c906108c | 2241 | |
63807e1d | 2242 | static CORE_ADDR |
52f729a7 | 2243 | rs6000_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc) |
c906108c | 2244 | { |
e17a4113 UW |
2245 | struct gdbarch *gdbarch = get_frame_arch (frame); |
2246 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2247 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
52f0bd74 | 2248 | unsigned int ii, op; |
977adac5 | 2249 | int rel; |
c906108c | 2250 | CORE_ADDR solib_target_pc; |
7cbd4a93 | 2251 | struct bound_minimal_symbol msymbol; |
c906108c | 2252 | |
c5aa993b JM |
2253 | static unsigned trampoline_code[] = |
2254 | { | |
2255 | 0x800b0000, /* l r0,0x0(r11) */ | |
2256 | 0x90410014, /* st r2,0x14(r1) */ | |
2257 | 0x7c0903a6, /* mtctr r0 */ | |
2258 | 0x804b0004, /* l r2,0x4(r11) */ | |
2259 | 0x816b0008, /* l r11,0x8(r11) */ | |
2260 | 0x4e800420, /* bctr */ | |
2261 | 0x4e800020, /* br */ | |
2262 | 0 | |
c906108c SS |
2263 | }; |
2264 | ||
977adac5 ND |
2265 | /* Check for bigtoc fixup code. */ |
2266 | msymbol = lookup_minimal_symbol_by_pc (pc); | |
7cbd4a93 | 2267 | if (msymbol.minsym |
e17a4113 | 2268 | && rs6000_in_solib_return_trampoline (gdbarch, pc, |
c9d95fa3 | 2269 | msymbol.minsym->linkage_name ())) |
977adac5 ND |
2270 | { |
2271 | /* Double-check that the third instruction from PC is relative "b". */ | |
e17a4113 | 2272 | op = read_memory_integer (pc + 8, 4, byte_order); |
977adac5 ND |
2273 | if ((op & 0xfc000003) == 0x48000000) |
2274 | { | |
2275 | /* Extract bits 6-29 as a signed 24-bit relative word address and | |
2276 | add it to the containing PC. */ | |
2277 | rel = ((int)(op << 6) >> 6); | |
2278 | return pc + 8 + rel; | |
2279 | } | |
2280 | } | |
2281 | ||
c906108c | 2282 | /* If pc is in a shared library trampoline, return its target. */ |
52f729a7 | 2283 | solib_target_pc = find_solib_trampoline_target (frame, pc); |
c906108c SS |
2284 | if (solib_target_pc) |
2285 | return solib_target_pc; | |
2286 | ||
c5aa993b JM |
2287 | for (ii = 0; trampoline_code[ii]; ++ii) |
2288 | { | |
e17a4113 | 2289 | op = read_memory_integer (pc + (ii * 4), 4, byte_order); |
c5aa993b JM |
2290 | if (op != trampoline_code[ii]) |
2291 | return 0; | |
2292 | } | |
0df8b418 MS |
2293 | ii = get_frame_register_unsigned (frame, 11); /* r11 holds destination |
2294 | addr. */ | |
e17a4113 | 2295 | pc = read_memory_unsigned_integer (ii, tdep->wordsize, byte_order); |
c906108c SS |
2296 | return pc; |
2297 | } | |
2298 | ||
794ac428 UW |
2299 | /* ISA-specific vector types. */ |
2300 | ||
2301 | static struct type * | |
2302 | rs6000_builtin_type_vec64 (struct gdbarch *gdbarch) | |
2303 | { | |
2304 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2305 | ||
2306 | if (!tdep->ppc_builtin_type_vec64) | |
2307 | { | |
df4df182 UW |
2308 | const struct builtin_type *bt = builtin_type (gdbarch); |
2309 | ||
794ac428 UW |
2310 | /* The type we're building is this: */ |
2311 | #if 0 | |
2312 | union __gdb_builtin_type_vec64 | |
2313 | { | |
2314 | int64_t uint64; | |
2315 | float v2_float[2]; | |
2316 | int32_t v2_int32[2]; | |
2317 | int16_t v4_int16[4]; | |
2318 | int8_t v8_int8[8]; | |
2319 | }; | |
2320 | #endif | |
2321 | ||
2322 | struct type *t; | |
2323 | ||
e9bb382b UW |
2324 | t = arch_composite_type (gdbarch, |
2325 | "__ppc_builtin_type_vec64", TYPE_CODE_UNION); | |
df4df182 | 2326 | append_composite_type_field (t, "uint64", bt->builtin_int64); |
794ac428 | 2327 | append_composite_type_field (t, "v2_float", |
df4df182 | 2328 | init_vector_type (bt->builtin_float, 2)); |
794ac428 | 2329 | append_composite_type_field (t, "v2_int32", |
df4df182 | 2330 | init_vector_type (bt->builtin_int32, 2)); |
794ac428 | 2331 | append_composite_type_field (t, "v4_int16", |
df4df182 | 2332 | init_vector_type (bt->builtin_int16, 4)); |
794ac428 | 2333 | append_composite_type_field (t, "v8_int8", |
df4df182 | 2334 | init_vector_type (bt->builtin_int8, 8)); |
794ac428 | 2335 | |
2062087b | 2336 | t->set_is_vector (true); |
d0e39ea2 | 2337 | t->set_name ("ppc_builtin_type_vec64"); |
794ac428 UW |
2338 | tdep->ppc_builtin_type_vec64 = t; |
2339 | } | |
2340 | ||
2341 | return tdep->ppc_builtin_type_vec64; | |
2342 | } | |
2343 | ||
604c2f83 LM |
2344 | /* Vector 128 type. */ |
2345 | ||
2346 | static struct type * | |
2347 | rs6000_builtin_type_vec128 (struct gdbarch *gdbarch) | |
2348 | { | |
2349 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2350 | ||
2351 | if (!tdep->ppc_builtin_type_vec128) | |
2352 | { | |
df4df182 UW |
2353 | const struct builtin_type *bt = builtin_type (gdbarch); |
2354 | ||
604c2f83 LM |
2355 | /* The type we're building is this |
2356 | ||
2357 | type = union __ppc_builtin_type_vec128 { | |
6ba4cb84 | 2358 | float128_t float128; |
604c2f83 | 2359 | uint128_t uint128; |
db9f5df8 | 2360 | double v2_double[2]; |
604c2f83 LM |
2361 | float v4_float[4]; |
2362 | int32_t v4_int32[4]; | |
2363 | int16_t v8_int16[8]; | |
2364 | int8_t v16_int8[16]; | |
2365 | } | |
2366 | */ | |
2367 | ||
6ba4cb84 CL |
2368 | /* PPC specific type for IEEE 128-bit float field */ |
2369 | struct type *t_float128 | |
2370 | = arch_float_type (gdbarch, 128, "float128_t", floatformats_ia64_quad); | |
2371 | ||
604c2f83 LM |
2372 | struct type *t; |
2373 | ||
e9bb382b UW |
2374 | t = arch_composite_type (gdbarch, |
2375 | "__ppc_builtin_type_vec128", TYPE_CODE_UNION); | |
6ba4cb84 | 2376 | append_composite_type_field (t, "float128", t_float128); |
df4df182 | 2377 | append_composite_type_field (t, "uint128", bt->builtin_uint128); |
db9f5df8 UW |
2378 | append_composite_type_field (t, "v2_double", |
2379 | init_vector_type (bt->builtin_double, 2)); | |
604c2f83 | 2380 | append_composite_type_field (t, "v4_float", |
df4df182 | 2381 | init_vector_type (bt->builtin_float, 4)); |
604c2f83 | 2382 | append_composite_type_field (t, "v4_int32", |
df4df182 | 2383 | init_vector_type (bt->builtin_int32, 4)); |
604c2f83 | 2384 | append_composite_type_field (t, "v8_int16", |
df4df182 | 2385 | init_vector_type (bt->builtin_int16, 8)); |
604c2f83 | 2386 | append_composite_type_field (t, "v16_int8", |
df4df182 | 2387 | init_vector_type (bt->builtin_int8, 16)); |
604c2f83 | 2388 | |
2062087b | 2389 | t->set_is_vector (true); |
d0e39ea2 | 2390 | t->set_name ("ppc_builtin_type_vec128"); |
604c2f83 LM |
2391 | tdep->ppc_builtin_type_vec128 = t; |
2392 | } | |
2393 | ||
2394 | return tdep->ppc_builtin_type_vec128; | |
2395 | } | |
2396 | ||
7cc46491 DJ |
2397 | /* Return the name of register number REGNO, or the empty string if it |
2398 | is an anonymous register. */ | |
7a78ae4e | 2399 | |
fa88f677 | 2400 | static const char * |
d93859e2 | 2401 | rs6000_register_name (struct gdbarch *gdbarch, int regno) |
7a78ae4e | 2402 | { |
d93859e2 | 2403 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7a78ae4e | 2404 | |
7cc46491 DJ |
2405 | /* The upper half "registers" have names in the XML description, |
2406 | but we present only the low GPRs and the full 64-bit registers | |
2407 | to the user. */ | |
2408 | if (tdep->ppc_ev0_upper_regnum >= 0 | |
2409 | && tdep->ppc_ev0_upper_regnum <= regno | |
2410 | && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) | |
2411 | return ""; | |
2412 | ||
604c2f83 LM |
2413 | /* Hide the upper halves of the vs0~vs31 registers. */ |
2414 | if (tdep->ppc_vsr0_regnum >= 0 | |
2415 | && tdep->ppc_vsr0_upper_regnum <= regno | |
2416 | && regno < tdep->ppc_vsr0_upper_regnum + ppc_num_gprs) | |
2417 | return ""; | |
2418 | ||
8d619c01 EBM |
2419 | /* Hide the upper halves of the cvs0~cvs31 registers. */ |
2420 | if (PPC_CVSR0_UPPER_REGNUM <= regno | |
2421 | && regno < PPC_CVSR0_UPPER_REGNUM + ppc_num_gprs) | |
2422 | return ""; | |
2423 | ||
7cc46491 | 2424 | /* Check if the SPE pseudo registers are available. */ |
5a9e69ba | 2425 | if (IS_SPE_PSEUDOREG (tdep, regno)) |
7cc46491 DJ |
2426 | { |
2427 | static const char *const spe_regnames[] = { | |
2428 | "ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7", | |
2429 | "ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15", | |
2430 | "ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23", | |
2431 | "ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31", | |
2432 | }; | |
2433 | return spe_regnames[regno - tdep->ppc_ev0_regnum]; | |
2434 | } | |
2435 | ||
f949c649 TJB |
2436 | /* Check if the decimal128 pseudo-registers are available. */ |
2437 | if (IS_DFP_PSEUDOREG (tdep, regno)) | |
2438 | { | |
2439 | static const char *const dfp128_regnames[] = { | |
2440 | "dl0", "dl1", "dl2", "dl3", | |
2441 | "dl4", "dl5", "dl6", "dl7", | |
2442 | "dl8", "dl9", "dl10", "dl11", | |
2443 | "dl12", "dl13", "dl14", "dl15" | |
2444 | }; | |
2445 | return dfp128_regnames[regno - tdep->ppc_dl0_regnum]; | |
2446 | } | |
2447 | ||
6f072a10 PFC |
2448 | /* Check if this is a vX alias for a raw vrX vector register. */ |
2449 | if (IS_V_ALIAS_PSEUDOREG (tdep, regno)) | |
2450 | { | |
2451 | static const char *const vector_alias_regnames[] = { | |
2452 | "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", | |
2453 | "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", | |
2454 | "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", | |
2455 | "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" | |
2456 | }; | |
2457 | return vector_alias_regnames[regno - tdep->ppc_v0_alias_regnum]; | |
2458 | } | |
2459 | ||
604c2f83 LM |
2460 | /* Check if this is a VSX pseudo-register. */ |
2461 | if (IS_VSX_PSEUDOREG (tdep, regno)) | |
2462 | { | |
2463 | static const char *const vsx_regnames[] = { | |
2464 | "vs0", "vs1", "vs2", "vs3", "vs4", "vs5", "vs6", "vs7", | |
2465 | "vs8", "vs9", "vs10", "vs11", "vs12", "vs13", "vs14", | |
2466 | "vs15", "vs16", "vs17", "vs18", "vs19", "vs20", "vs21", | |
2467 | "vs22", "vs23", "vs24", "vs25", "vs26", "vs27", "vs28", | |
2468 | "vs29", "vs30", "vs31", "vs32", "vs33", "vs34", "vs35", | |
2469 | "vs36", "vs37", "vs38", "vs39", "vs40", "vs41", "vs42", | |
2470 | "vs43", "vs44", "vs45", "vs46", "vs47", "vs48", "vs49", | |
2471 | "vs50", "vs51", "vs52", "vs53", "vs54", "vs55", "vs56", | |
2472 | "vs57", "vs58", "vs59", "vs60", "vs61", "vs62", "vs63" | |
2473 | }; | |
2474 | return vsx_regnames[regno - tdep->ppc_vsr0_regnum]; | |
2475 | } | |
2476 | ||
2477 | /* Check if the this is a Extended FP pseudo-register. */ | |
2478 | if (IS_EFP_PSEUDOREG (tdep, regno)) | |
2479 | { | |
2480 | static const char *const efpr_regnames[] = { | |
2481 | "f32", "f33", "f34", "f35", "f36", "f37", "f38", | |
2482 | "f39", "f40", "f41", "f42", "f43", "f44", "f45", | |
2483 | "f46", "f47", "f48", "f49", "f50", "f51", | |
2484 | "f52", "f53", "f54", "f55", "f56", "f57", | |
2485 | "f58", "f59", "f60", "f61", "f62", "f63" | |
2486 | }; | |
2487 | return efpr_regnames[regno - tdep->ppc_efpr0_regnum]; | |
2488 | } | |
2489 | ||
8d619c01 EBM |
2490 | /* Check if this is a Checkpointed DFP pseudo-register. */ |
2491 | if (IS_CDFP_PSEUDOREG (tdep, regno)) | |
2492 | { | |
2493 | static const char *const cdfp128_regnames[] = { | |
2494 | "cdl0", "cdl1", "cdl2", "cdl3", | |
2495 | "cdl4", "cdl5", "cdl6", "cdl7", | |
2496 | "cdl8", "cdl9", "cdl10", "cdl11", | |
2497 | "cdl12", "cdl13", "cdl14", "cdl15" | |
2498 | }; | |
2499 | return cdfp128_regnames[regno - tdep->ppc_cdl0_regnum]; | |
2500 | } | |
2501 | ||
2502 | /* Check if this is a Checkpointed VSX pseudo-register. */ | |
2503 | if (IS_CVSX_PSEUDOREG (tdep, regno)) | |
2504 | { | |
2505 | static const char *const cvsx_regnames[] = { | |
2506 | "cvs0", "cvs1", "cvs2", "cvs3", "cvs4", "cvs5", "cvs6", "cvs7", | |
2507 | "cvs8", "cvs9", "cvs10", "cvs11", "cvs12", "cvs13", "cvs14", | |
2508 | "cvs15", "cvs16", "cvs17", "cvs18", "cvs19", "cvs20", "cvs21", | |
2509 | "cvs22", "cvs23", "cvs24", "cvs25", "cvs26", "cvs27", "cvs28", | |
2510 | "cvs29", "cvs30", "cvs31", "cvs32", "cvs33", "cvs34", "cvs35", | |
2511 | "cvs36", "cvs37", "cvs38", "cvs39", "cvs40", "cvs41", "cvs42", | |
2512 | "cvs43", "cvs44", "cvs45", "cvs46", "cvs47", "cvs48", "cvs49", | |
2513 | "cvs50", "cvs51", "cvs52", "cvs53", "cvs54", "cvs55", "cvs56", | |
2514 | "cvs57", "cvs58", "cvs59", "cvs60", "cvs61", "cvs62", "cvs63" | |
2515 | }; | |
2516 | return cvsx_regnames[regno - tdep->ppc_cvsr0_regnum]; | |
2517 | } | |
2518 | ||
2519 | /* Check if the this is a Checkpointed Extended FP pseudo-register. */ | |
2520 | if (IS_CEFP_PSEUDOREG (tdep, regno)) | |
2521 | { | |
2522 | static const char *const cefpr_regnames[] = { | |
2523 | "cf32", "cf33", "cf34", "cf35", "cf36", "cf37", "cf38", | |
2524 | "cf39", "cf40", "cf41", "cf42", "cf43", "cf44", "cf45", | |
2525 | "cf46", "cf47", "cf48", "cf49", "cf50", "cf51", | |
2526 | "cf52", "cf53", "cf54", "cf55", "cf56", "cf57", | |
2527 | "cf58", "cf59", "cf60", "cf61", "cf62", "cf63" | |
2528 | }; | |
2529 | return cefpr_regnames[regno - tdep->ppc_cefpr0_regnum]; | |
2530 | } | |
2531 | ||
d93859e2 | 2532 | return tdesc_register_name (gdbarch, regno); |
7a78ae4e ND |
2533 | } |
2534 | ||
7cc46491 DJ |
2535 | /* Return the GDB type object for the "standard" data type of data in |
2536 | register N. */ | |
7a78ae4e ND |
2537 | |
2538 | static struct type * | |
7cc46491 | 2539 | rs6000_pseudo_register_type (struct gdbarch *gdbarch, int regnum) |
7a78ae4e | 2540 | { |
691d145a | 2541 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7a78ae4e | 2542 | |
f949c649 TJB |
2543 | /* These are the e500 pseudo-registers. */ |
2544 | if (IS_SPE_PSEUDOREG (tdep, regnum)) | |
2545 | return rs6000_builtin_type_vec64 (gdbarch); | |
8d619c01 EBM |
2546 | else if (IS_DFP_PSEUDOREG (tdep, regnum) |
2547 | || IS_CDFP_PSEUDOREG (tdep, regnum)) | |
604c2f83 | 2548 | /* PPC decimal128 pseudo-registers. */ |
f949c649 | 2549 | return builtin_type (gdbarch)->builtin_declong; |
6f072a10 PFC |
2550 | else if (IS_V_ALIAS_PSEUDOREG (tdep, regnum)) |
2551 | return gdbarch_register_type (gdbarch, | |
2552 | tdep->ppc_vr0_regnum | |
2553 | + (regnum | |
2554 | - tdep->ppc_v0_alias_regnum)); | |
8d619c01 EBM |
2555 | else if (IS_VSX_PSEUDOREG (tdep, regnum) |
2556 | || IS_CVSX_PSEUDOREG (tdep, regnum)) | |
604c2f83 LM |
2557 | /* POWER7 VSX pseudo-registers. */ |
2558 | return rs6000_builtin_type_vec128 (gdbarch); | |
8d619c01 EBM |
2559 | else if (IS_EFP_PSEUDOREG (tdep, regnum) |
2560 | || IS_CEFP_PSEUDOREG (tdep, regnum)) | |
604c2f83 LM |
2561 | /* POWER7 Extended FP pseudo-registers. */ |
2562 | return builtin_type (gdbarch)->builtin_double; | |
8d619c01 EBM |
2563 | else |
2564 | internal_error (__FILE__, __LINE__, | |
2565 | _("rs6000_pseudo_register_type: " | |
2566 | "called on unexpected register '%s' (%d)"), | |
2567 | gdbarch_register_name (gdbarch, regnum), regnum); | |
7a78ae4e ND |
2568 | } |
2569 | ||
6f072a10 PFC |
2570 | /* Check if REGNUM is a member of REGGROUP. We only need to handle |
2571 | the vX aliases for the vector registers by always returning false | |
2572 | to avoid duplicated information in "info register vector/all", | |
2573 | since the raw vrX registers will already show in these cases. For | |
2574 | other pseudo-registers we use the default membership function. */ | |
2575 | ||
2576 | static int | |
2577 | rs6000_pseudo_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
2578 | struct reggroup *group) | |
2579 | { | |
2580 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2581 | ||
2582 | if (IS_V_ALIAS_PSEUDOREG (tdep, regnum)) | |
2583 | return 0; | |
2584 | else | |
2585 | return default_register_reggroup_p (gdbarch, regnum, group); | |
2586 | } | |
2587 | ||
691d145a | 2588 | /* The register format for RS/6000 floating point registers is always |
64366f1c | 2589 | double, we need a conversion if the memory format is float. */ |
7a78ae4e ND |
2590 | |
2591 | static int | |
0abe36f5 MD |
2592 | rs6000_convert_register_p (struct gdbarch *gdbarch, int regnum, |
2593 | struct type *type) | |
7a78ae4e | 2594 | { |
0abe36f5 | 2595 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7cc46491 DJ |
2596 | |
2597 | return (tdep->ppc_fp0_regnum >= 0 | |
2598 | && regnum >= tdep->ppc_fp0_regnum | |
2599 | && regnum < tdep->ppc_fp0_regnum + ppc_num_fprs | |
78134374 | 2600 | && type->code () == TYPE_CODE_FLT |
0dfff4cb UW |
2601 | && TYPE_LENGTH (type) |
2602 | != TYPE_LENGTH (builtin_type (gdbarch)->builtin_double)); | |
7a78ae4e ND |
2603 | } |
2604 | ||
8dccd430 | 2605 | static int |
691d145a | 2606 | rs6000_register_to_value (struct frame_info *frame, |
dda83cd7 SM |
2607 | int regnum, |
2608 | struct type *type, | |
2609 | gdb_byte *to, | |
8dccd430 | 2610 | int *optimizedp, int *unavailablep) |
7a78ae4e | 2611 | { |
0dfff4cb | 2612 | struct gdbarch *gdbarch = get_frame_arch (frame); |
0f068fb5 | 2613 | gdb_byte from[PPC_MAX_REGISTER_SIZE]; |
691d145a | 2614 | |
78134374 | 2615 | gdb_assert (type->code () == TYPE_CODE_FLT); |
7a78ae4e | 2616 | |
8dccd430 | 2617 | if (!get_frame_register_bytes (frame, regnum, 0, |
bdec2917 LM |
2618 | gdb::make_array_view (from, |
2619 | register_size (gdbarch, | |
2620 | regnum)), | |
2621 | optimizedp, unavailablep)) | |
8dccd430 PA |
2622 | return 0; |
2623 | ||
3b2ca824 UW |
2624 | target_float_convert (from, builtin_type (gdbarch)->builtin_double, |
2625 | to, type); | |
8dccd430 PA |
2626 | *optimizedp = *unavailablep = 0; |
2627 | return 1; | |
691d145a | 2628 | } |
7a292a7a | 2629 | |
7a78ae4e | 2630 | static void |
691d145a | 2631 | rs6000_value_to_register (struct frame_info *frame, |
dda83cd7 SM |
2632 | int regnum, |
2633 | struct type *type, | |
2634 | const gdb_byte *from) | |
7a78ae4e | 2635 | { |
0dfff4cb | 2636 | struct gdbarch *gdbarch = get_frame_arch (frame); |
0f068fb5 | 2637 | gdb_byte to[PPC_MAX_REGISTER_SIZE]; |
691d145a | 2638 | |
78134374 | 2639 | gdb_assert (type->code () == TYPE_CODE_FLT); |
691d145a | 2640 | |
3b2ca824 UW |
2641 | target_float_convert (from, type, |
2642 | to, builtin_type (gdbarch)->builtin_double); | |
691d145a | 2643 | put_frame_register (frame, regnum, to); |
7a78ae4e | 2644 | } |
c906108c | 2645 | |
05d1431c PA |
2646 | /* The type of a function that moves the value of REG between CACHE |
2647 | or BUF --- in either direction. */ | |
2648 | typedef enum register_status (*move_ev_register_func) (struct regcache *, | |
2649 | int, void *); | |
2650 | ||
6ced10dd JB |
2651 | /* Move SPE vector register values between a 64-bit buffer and the two |
2652 | 32-bit raw register halves in a regcache. This function handles | |
2653 | both splitting a 64-bit value into two 32-bit halves, and joining | |
2654 | two halves into a whole 64-bit value, depending on the function | |
2655 | passed as the MOVE argument. | |
2656 | ||
2657 | EV_REG must be the number of an SPE evN vector register --- a | |
2658 | pseudoregister. REGCACHE must be a regcache, and BUFFER must be a | |
2659 | 64-bit buffer. | |
2660 | ||
2661 | Call MOVE once for each 32-bit half of that register, passing | |
2662 | REGCACHE, the number of the raw register corresponding to that | |
2663 | half, and the address of the appropriate half of BUFFER. | |
2664 | ||
2665 | For example, passing 'regcache_raw_read' as the MOVE function will | |
2666 | fill BUFFER with the full 64-bit contents of EV_REG. Or, passing | |
2667 | 'regcache_raw_supply' will supply the contents of BUFFER to the | |
2668 | appropriate pair of raw registers in REGCACHE. | |
2669 | ||
2670 | You may need to cast away some 'const' qualifiers when passing | |
2671 | MOVE, since this function can't tell at compile-time which of | |
2672 | REGCACHE or BUFFER is acting as the source of the data. If C had | |
2673 | co-variant type qualifiers, ... */ | |
05d1431c PA |
2674 | |
2675 | static enum register_status | |
2676 | e500_move_ev_register (move_ev_register_func move, | |
2677 | struct regcache *regcache, int ev_reg, void *buffer) | |
6ced10dd | 2678 | { |
ac7936df | 2679 | struct gdbarch *arch = regcache->arch (); |
6ced10dd JB |
2680 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); |
2681 | int reg_index; | |
19ba03f4 | 2682 | gdb_byte *byte_buffer = (gdb_byte *) buffer; |
05d1431c | 2683 | enum register_status status; |
6ced10dd | 2684 | |
5a9e69ba | 2685 | gdb_assert (IS_SPE_PSEUDOREG (tdep, ev_reg)); |
6ced10dd JB |
2686 | |
2687 | reg_index = ev_reg - tdep->ppc_ev0_regnum; | |
2688 | ||
8b164abb | 2689 | if (gdbarch_byte_order (arch) == BFD_ENDIAN_BIG) |
6ced10dd | 2690 | { |
05d1431c PA |
2691 | status = move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, |
2692 | byte_buffer); | |
2693 | if (status == REG_VALID) | |
2694 | status = move (regcache, tdep->ppc_gp0_regnum + reg_index, | |
2695 | byte_buffer + 4); | |
6ced10dd JB |
2696 | } |
2697 | else | |
2698 | { | |
05d1431c PA |
2699 | status = move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer); |
2700 | if (status == REG_VALID) | |
2701 | status = move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, | |
2702 | byte_buffer + 4); | |
6ced10dd | 2703 | } |
05d1431c PA |
2704 | |
2705 | return status; | |
6ced10dd JB |
2706 | } |
2707 | ||
05d1431c PA |
2708 | static enum register_status |
2709 | do_regcache_raw_write (struct regcache *regcache, int regnum, void *buffer) | |
2710 | { | |
10eaee5f | 2711 | regcache->raw_write (regnum, (const gdb_byte *) buffer); |
05d1431c PA |
2712 | |
2713 | return REG_VALID; | |
2714 | } | |
2715 | ||
2716 | static enum register_status | |
849d0ba8 YQ |
2717 | e500_pseudo_register_read (struct gdbarch *gdbarch, readable_regcache *regcache, |
2718 | int ev_reg, gdb_byte *buffer) | |
f949c649 | 2719 | { |
849d0ba8 YQ |
2720 | struct gdbarch *arch = regcache->arch (); |
2721 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); | |
2722 | int reg_index; | |
2723 | enum register_status status; | |
2724 | ||
2725 | gdb_assert (IS_SPE_PSEUDOREG (tdep, ev_reg)); | |
2726 | ||
2727 | reg_index = ev_reg - tdep->ppc_ev0_regnum; | |
2728 | ||
2729 | if (gdbarch_byte_order (arch) == BFD_ENDIAN_BIG) | |
2730 | { | |
2731 | status = regcache->raw_read (tdep->ppc_ev0_upper_regnum + reg_index, | |
2732 | buffer); | |
2733 | if (status == REG_VALID) | |
2734 | status = regcache->raw_read (tdep->ppc_gp0_regnum + reg_index, | |
2735 | buffer + 4); | |
2736 | } | |
2737 | else | |
2738 | { | |
2739 | status = regcache->raw_read (tdep->ppc_gp0_regnum + reg_index, buffer); | |
2740 | if (status == REG_VALID) | |
2741 | status = regcache->raw_read (tdep->ppc_ev0_upper_regnum + reg_index, | |
2742 | buffer + 4); | |
2743 | } | |
2744 | ||
2745 | return status; | |
2746 | ||
f949c649 TJB |
2747 | } |
2748 | ||
2749 | static void | |
2750 | e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
2751 | int reg_nr, const gdb_byte *buffer) | |
2752 | { | |
05d1431c PA |
2753 | e500_move_ev_register (do_regcache_raw_write, regcache, |
2754 | reg_nr, (void *) buffer); | |
f949c649 TJB |
2755 | } |
2756 | ||
604c2f83 | 2757 | /* Read method for DFP pseudo-registers. */ |
05d1431c | 2758 | static enum register_status |
849d0ba8 | 2759 | dfp_pseudo_register_read (struct gdbarch *gdbarch, readable_regcache *regcache, |
f949c649 TJB |
2760 | int reg_nr, gdb_byte *buffer) |
2761 | { | |
2762 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
8d619c01 | 2763 | int reg_index, fp0; |
05d1431c | 2764 | enum register_status status; |
f949c649 | 2765 | |
8d619c01 EBM |
2766 | if (IS_DFP_PSEUDOREG (tdep, reg_nr)) |
2767 | { | |
2768 | reg_index = reg_nr - tdep->ppc_dl0_regnum; | |
2769 | fp0 = PPC_F0_REGNUM; | |
2770 | } | |
2771 | else | |
2772 | { | |
2773 | gdb_assert (IS_CDFP_PSEUDOREG (tdep, reg_nr)); | |
2774 | ||
2775 | reg_index = reg_nr - tdep->ppc_cdl0_regnum; | |
2776 | fp0 = PPC_CF0_REGNUM; | |
2777 | } | |
2778 | ||
f949c649 TJB |
2779 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
2780 | { | |
2781 | /* Read two FP registers to form a whole dl register. */ | |
8d619c01 | 2782 | status = regcache->raw_read (fp0 + 2 * reg_index, buffer); |
05d1431c | 2783 | if (status == REG_VALID) |
8d619c01 EBM |
2784 | status = regcache->raw_read (fp0 + 2 * reg_index + 1, |
2785 | buffer + 8); | |
f949c649 TJB |
2786 | } |
2787 | else | |
2788 | { | |
8d619c01 | 2789 | status = regcache->raw_read (fp0 + 2 * reg_index + 1, buffer); |
05d1431c | 2790 | if (status == REG_VALID) |
8d619c01 | 2791 | status = regcache->raw_read (fp0 + 2 * reg_index, buffer + 8); |
f949c649 | 2792 | } |
05d1431c PA |
2793 | |
2794 | return status; | |
f949c649 TJB |
2795 | } |
2796 | ||
604c2f83 | 2797 | /* Write method for DFP pseudo-registers. */ |
f949c649 | 2798 | static void |
604c2f83 | 2799 | dfp_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, |
f949c649 TJB |
2800 | int reg_nr, const gdb_byte *buffer) |
2801 | { | |
2802 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
8d619c01 EBM |
2803 | int reg_index, fp0; |
2804 | ||
2805 | if (IS_DFP_PSEUDOREG (tdep, reg_nr)) | |
2806 | { | |
2807 | reg_index = reg_nr - tdep->ppc_dl0_regnum; | |
2808 | fp0 = PPC_F0_REGNUM; | |
2809 | } | |
2810 | else | |
2811 | { | |
2812 | gdb_assert (IS_CDFP_PSEUDOREG (tdep, reg_nr)); | |
2813 | ||
2814 | reg_index = reg_nr - tdep->ppc_cdl0_regnum; | |
2815 | fp0 = PPC_CF0_REGNUM; | |
2816 | } | |
f949c649 TJB |
2817 | |
2818 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
2819 | { | |
2820 | /* Write each half of the dl register into a separate | |
8d619c01 EBM |
2821 | FP register. */ |
2822 | regcache->raw_write (fp0 + 2 * reg_index, buffer); | |
2823 | regcache->raw_write (fp0 + 2 * reg_index + 1, buffer + 8); | |
f949c649 TJB |
2824 | } |
2825 | else | |
2826 | { | |
8d619c01 EBM |
2827 | regcache->raw_write (fp0 + 2 * reg_index + 1, buffer); |
2828 | regcache->raw_write (fp0 + 2 * reg_index, buffer + 8); | |
f949c649 TJB |
2829 | } |
2830 | } | |
2831 | ||
6f072a10 PFC |
2832 | /* Read method for the vX aliases for the raw vrX registers. */ |
2833 | ||
2834 | static enum register_status | |
2835 | v_alias_pseudo_register_read (struct gdbarch *gdbarch, | |
2836 | readable_regcache *regcache, int reg_nr, | |
2837 | gdb_byte *buffer) | |
2838 | { | |
2839 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2840 | gdb_assert (IS_V_ALIAS_PSEUDOREG (tdep, reg_nr)); | |
2841 | ||
2842 | return regcache->raw_read (tdep->ppc_vr0_regnum | |
2843 | + (reg_nr - tdep->ppc_v0_alias_regnum), | |
2844 | buffer); | |
2845 | } | |
2846 | ||
2847 | /* Write method for the vX aliases for the raw vrX registers. */ | |
2848 | ||
2849 | static void | |
2850 | v_alias_pseudo_register_write (struct gdbarch *gdbarch, | |
2851 | struct regcache *regcache, | |
2852 | int reg_nr, const gdb_byte *buffer) | |
2853 | { | |
2854 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2855 | gdb_assert (IS_V_ALIAS_PSEUDOREG (tdep, reg_nr)); | |
2856 | ||
2857 | regcache->raw_write (tdep->ppc_vr0_regnum | |
2858 | + (reg_nr - tdep->ppc_v0_alias_regnum), buffer); | |
2859 | } | |
2860 | ||
604c2f83 | 2861 | /* Read method for POWER7 VSX pseudo-registers. */ |
05d1431c | 2862 | static enum register_status |
849d0ba8 | 2863 | vsx_pseudo_register_read (struct gdbarch *gdbarch, readable_regcache *regcache, |
604c2f83 LM |
2864 | int reg_nr, gdb_byte *buffer) |
2865 | { | |
2866 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
8d619c01 | 2867 | int reg_index, vr0, fp0, vsr0_upper; |
05d1431c | 2868 | enum register_status status; |
604c2f83 | 2869 | |
8d619c01 EBM |
2870 | if (IS_VSX_PSEUDOREG (tdep, reg_nr)) |
2871 | { | |
2872 | reg_index = reg_nr - tdep->ppc_vsr0_regnum; | |
2873 | vr0 = PPC_VR0_REGNUM; | |
2874 | fp0 = PPC_F0_REGNUM; | |
2875 | vsr0_upper = PPC_VSR0_UPPER_REGNUM; | |
2876 | } | |
2877 | else | |
2878 | { | |
2879 | gdb_assert (IS_CVSX_PSEUDOREG (tdep, reg_nr)); | |
2880 | ||
2881 | reg_index = reg_nr - tdep->ppc_cvsr0_regnum; | |
2882 | vr0 = PPC_CVR0_REGNUM; | |
2883 | fp0 = PPC_CF0_REGNUM; | |
2884 | vsr0_upper = PPC_CVSR0_UPPER_REGNUM; | |
2885 | } | |
2886 | ||
604c2f83 LM |
2887 | /* Read the portion that overlaps the VMX registers. */ |
2888 | if (reg_index > 31) | |
8d619c01 | 2889 | status = regcache->raw_read (vr0 + reg_index - 32, buffer); |
604c2f83 LM |
2890 | else |
2891 | /* Read the portion that overlaps the FPR registers. */ | |
2892 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
2893 | { | |
8d619c01 | 2894 | status = regcache->raw_read (fp0 + reg_index, buffer); |
05d1431c | 2895 | if (status == REG_VALID) |
8d619c01 EBM |
2896 | status = regcache->raw_read (vsr0_upper + reg_index, |
2897 | buffer + 8); | |
604c2f83 LM |
2898 | } |
2899 | else | |
2900 | { | |
8d619c01 | 2901 | status = regcache->raw_read (fp0 + reg_index, buffer + 8); |
05d1431c | 2902 | if (status == REG_VALID) |
8d619c01 | 2903 | status = regcache->raw_read (vsr0_upper + reg_index, buffer); |
604c2f83 | 2904 | } |
05d1431c PA |
2905 | |
2906 | return status; | |
604c2f83 LM |
2907 | } |
2908 | ||
2909 | /* Write method for POWER7 VSX pseudo-registers. */ | |
2910 | static void | |
2911 | vsx_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
2912 | int reg_nr, const gdb_byte *buffer) | |
2913 | { | |
2914 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
8d619c01 EBM |
2915 | int reg_index, vr0, fp0, vsr0_upper; |
2916 | ||
2917 | if (IS_VSX_PSEUDOREG (tdep, reg_nr)) | |
2918 | { | |
2919 | reg_index = reg_nr - tdep->ppc_vsr0_regnum; | |
2920 | vr0 = PPC_VR0_REGNUM; | |
2921 | fp0 = PPC_F0_REGNUM; | |
2922 | vsr0_upper = PPC_VSR0_UPPER_REGNUM; | |
2923 | } | |
2924 | else | |
2925 | { | |
2926 | gdb_assert (IS_CVSX_PSEUDOREG (tdep, reg_nr)); | |
2927 | ||
2928 | reg_index = reg_nr - tdep->ppc_cvsr0_regnum; | |
2929 | vr0 = PPC_CVR0_REGNUM; | |
2930 | fp0 = PPC_CF0_REGNUM; | |
2931 | vsr0_upper = PPC_CVSR0_UPPER_REGNUM; | |
2932 | } | |
604c2f83 LM |
2933 | |
2934 | /* Write the portion that overlaps the VMX registers. */ | |
2935 | if (reg_index > 31) | |
8d619c01 | 2936 | regcache->raw_write (vr0 + reg_index - 32, buffer); |
604c2f83 LM |
2937 | else |
2938 | /* Write the portion that overlaps the FPR registers. */ | |
2939 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
2940 | { | |
8d619c01 EBM |
2941 | regcache->raw_write (fp0 + reg_index, buffer); |
2942 | regcache->raw_write (vsr0_upper + reg_index, buffer + 8); | |
604c2f83 LM |
2943 | } |
2944 | else | |
2945 | { | |
8d619c01 EBM |
2946 | regcache->raw_write (fp0 + reg_index, buffer + 8); |
2947 | regcache->raw_write (vsr0_upper + reg_index, buffer); | |
604c2f83 LM |
2948 | } |
2949 | } | |
2950 | ||
2951 | /* Read method for POWER7 Extended FP pseudo-registers. */ | |
05d1431c | 2952 | static enum register_status |
8d619c01 | 2953 | efp_pseudo_register_read (struct gdbarch *gdbarch, readable_regcache *regcache, |
604c2f83 LM |
2954 | int reg_nr, gdb_byte *buffer) |
2955 | { | |
2956 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
8d619c01 EBM |
2957 | int reg_index, vr0; |
2958 | ||
2959 | if (IS_EFP_PSEUDOREG (tdep, reg_nr)) | |
2960 | { | |
2961 | reg_index = reg_nr - tdep->ppc_efpr0_regnum; | |
2962 | vr0 = PPC_VR0_REGNUM; | |
2963 | } | |
2964 | else | |
2965 | { | |
2966 | gdb_assert (IS_CEFP_PSEUDOREG (tdep, reg_nr)); | |
2967 | ||
2968 | reg_index = reg_nr - tdep->ppc_cefpr0_regnum; | |
2969 | vr0 = PPC_CVR0_REGNUM; | |
2970 | } | |
2971 | ||
084ee545 | 2972 | int offset = gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG ? 0 : 8; |
604c2f83 | 2973 | |
d9492458 | 2974 | /* Read the portion that overlaps the VMX register. */ |
8d619c01 EBM |
2975 | return regcache->raw_read_part (vr0 + reg_index, offset, |
2976 | register_size (gdbarch, reg_nr), | |
849d0ba8 | 2977 | buffer); |
604c2f83 LM |
2978 | } |
2979 | ||
2980 | /* Write method for POWER7 Extended FP pseudo-registers. */ | |
2981 | static void | |
8d619c01 | 2982 | efp_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, |
604c2f83 LM |
2983 | int reg_nr, const gdb_byte *buffer) |
2984 | { | |
2985 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
8d619c01 | 2986 | int reg_index, vr0; |
084ee545 | 2987 | int offset = gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG ? 0 : 8; |
604c2f83 | 2988 | |
8d619c01 EBM |
2989 | if (IS_EFP_PSEUDOREG (tdep, reg_nr)) |
2990 | { | |
2991 | reg_index = reg_nr - tdep->ppc_efpr0_regnum; | |
2992 | vr0 = PPC_VR0_REGNUM; | |
2993 | } | |
2994 | else | |
2995 | { | |
2996 | gdb_assert (IS_CEFP_PSEUDOREG (tdep, reg_nr)); | |
2997 | ||
2998 | reg_index = reg_nr - tdep->ppc_cefpr0_regnum; | |
2999 | vr0 = PPC_CVR0_REGNUM; | |
3000 | ||
3001 | /* The call to raw_write_part fails silently if the initial read | |
3002 | of the read-update-write sequence returns an invalid status, | |
3003 | so we check this manually and throw an error if needed. */ | |
3004 | regcache->raw_update (vr0 + reg_index); | |
3005 | if (regcache->get_register_status (vr0 + reg_index) != REG_VALID) | |
3006 | error (_("Cannot write to the checkpointed EFP register, " | |
3007 | "the corresponding vector register is unavailable.")); | |
3008 | } | |
3009 | ||
d9492458 | 3010 | /* Write the portion that overlaps the VMX register. */ |
8d619c01 | 3011 | regcache->raw_write_part (vr0 + reg_index, offset, |
4f0420fd | 3012 | register_size (gdbarch, reg_nr), buffer); |
604c2f83 LM |
3013 | } |
3014 | ||
05d1431c | 3015 | static enum register_status |
0df8b418 | 3016 | rs6000_pseudo_register_read (struct gdbarch *gdbarch, |
849d0ba8 | 3017 | readable_regcache *regcache, |
f949c649 | 3018 | int reg_nr, gdb_byte *buffer) |
c8001721 | 3019 | { |
ac7936df | 3020 | struct gdbarch *regcache_arch = regcache->arch (); |
c8001721 EZ |
3021 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3022 | ||
6ced10dd | 3023 | gdb_assert (regcache_arch == gdbarch); |
f949c649 | 3024 | |
5a9e69ba | 3025 | if (IS_SPE_PSEUDOREG (tdep, reg_nr)) |
05d1431c | 3026 | return e500_pseudo_register_read (gdbarch, regcache, reg_nr, buffer); |
8d619c01 EBM |
3027 | else if (IS_DFP_PSEUDOREG (tdep, reg_nr) |
3028 | || IS_CDFP_PSEUDOREG (tdep, reg_nr)) | |
05d1431c | 3029 | return dfp_pseudo_register_read (gdbarch, regcache, reg_nr, buffer); |
6f072a10 PFC |
3030 | else if (IS_V_ALIAS_PSEUDOREG (tdep, reg_nr)) |
3031 | return v_alias_pseudo_register_read (gdbarch, regcache, reg_nr, | |
3032 | buffer); | |
8d619c01 EBM |
3033 | else if (IS_VSX_PSEUDOREG (tdep, reg_nr) |
3034 | || IS_CVSX_PSEUDOREG (tdep, reg_nr)) | |
05d1431c | 3035 | return vsx_pseudo_register_read (gdbarch, regcache, reg_nr, buffer); |
8d619c01 EBM |
3036 | else if (IS_EFP_PSEUDOREG (tdep, reg_nr) |
3037 | || IS_CEFP_PSEUDOREG (tdep, reg_nr)) | |
3038 | return efp_pseudo_register_read (gdbarch, regcache, reg_nr, buffer); | |
6ced10dd | 3039 | else |
a44bddec | 3040 | internal_error (__FILE__, __LINE__, |
f949c649 TJB |
3041 | _("rs6000_pseudo_register_read: " |
3042 | "called on unexpected register '%s' (%d)"), | |
3043 | gdbarch_register_name (gdbarch, reg_nr), reg_nr); | |
c8001721 EZ |
3044 | } |
3045 | ||
3046 | static void | |
f949c649 TJB |
3047 | rs6000_pseudo_register_write (struct gdbarch *gdbarch, |
3048 | struct regcache *regcache, | |
3049 | int reg_nr, const gdb_byte *buffer) | |
c8001721 | 3050 | { |
ac7936df | 3051 | struct gdbarch *regcache_arch = regcache->arch (); |
c8001721 EZ |
3052 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3053 | ||
6ced10dd | 3054 | gdb_assert (regcache_arch == gdbarch); |
f949c649 | 3055 | |
5a9e69ba | 3056 | if (IS_SPE_PSEUDOREG (tdep, reg_nr)) |
f949c649 | 3057 | e500_pseudo_register_write (gdbarch, regcache, reg_nr, buffer); |
8d619c01 EBM |
3058 | else if (IS_DFP_PSEUDOREG (tdep, reg_nr) |
3059 | || IS_CDFP_PSEUDOREG (tdep, reg_nr)) | |
604c2f83 | 3060 | dfp_pseudo_register_write (gdbarch, regcache, reg_nr, buffer); |
6f072a10 PFC |
3061 | else if (IS_V_ALIAS_PSEUDOREG (tdep, reg_nr)) |
3062 | v_alias_pseudo_register_write (gdbarch, regcache, reg_nr, buffer); | |
8d619c01 EBM |
3063 | else if (IS_VSX_PSEUDOREG (tdep, reg_nr) |
3064 | || IS_CVSX_PSEUDOREG (tdep, reg_nr)) | |
604c2f83 | 3065 | vsx_pseudo_register_write (gdbarch, regcache, reg_nr, buffer); |
8d619c01 EBM |
3066 | else if (IS_EFP_PSEUDOREG (tdep, reg_nr) |
3067 | || IS_CEFP_PSEUDOREG (tdep, reg_nr)) | |
3068 | efp_pseudo_register_write (gdbarch, regcache, reg_nr, buffer); | |
6ced10dd | 3069 | else |
a44bddec | 3070 | internal_error (__FILE__, __LINE__, |
f949c649 TJB |
3071 | _("rs6000_pseudo_register_write: " |
3072 | "called on unexpected register '%s' (%d)"), | |
3073 | gdbarch_register_name (gdbarch, reg_nr), reg_nr); | |
6ced10dd JB |
3074 | } |
3075 | ||
8d619c01 EBM |
3076 | /* Set the register mask in AX with the registers that form the DFP or |
3077 | checkpointed DFP pseudo-register REG_NR. */ | |
3078 | ||
3079 | static void | |
3080 | dfp_ax_pseudo_register_collect (struct gdbarch *gdbarch, | |
3081 | struct agent_expr *ax, int reg_nr) | |
3082 | { | |
3083 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3084 | int reg_index, fp0; | |
3085 | ||
3086 | if (IS_DFP_PSEUDOREG (tdep, reg_nr)) | |
3087 | { | |
3088 | reg_index = reg_nr - tdep->ppc_dl0_regnum; | |
3089 | fp0 = PPC_F0_REGNUM; | |
3090 | } | |
3091 | else | |
3092 | { | |
3093 | gdb_assert (IS_CDFP_PSEUDOREG (tdep, reg_nr)); | |
3094 | ||
3095 | reg_index = reg_nr - tdep->ppc_cdl0_regnum; | |
3096 | fp0 = PPC_CF0_REGNUM; | |
3097 | } | |
3098 | ||
3099 | ax_reg_mask (ax, fp0 + 2 * reg_index); | |
3100 | ax_reg_mask (ax, fp0 + 2 * reg_index + 1); | |
3101 | } | |
3102 | ||
6f072a10 PFC |
3103 | /* Set the register mask in AX with the raw vector register that |
3104 | corresponds to its REG_NR alias. */ | |
3105 | ||
3106 | static void | |
3107 | v_alias_pseudo_register_collect (struct gdbarch *gdbarch, | |
3108 | struct agent_expr *ax, int reg_nr) | |
3109 | { | |
3110 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3111 | gdb_assert (IS_V_ALIAS_PSEUDOREG (tdep, reg_nr)); | |
3112 | ||
3113 | ax_reg_mask (ax, tdep->ppc_vr0_regnum | |
3114 | + (reg_nr - tdep->ppc_v0_alias_regnum)); | |
3115 | } | |
3116 | ||
8d619c01 EBM |
3117 | /* Set the register mask in AX with the registers that form the VSX or |
3118 | checkpointed VSX pseudo-register REG_NR. */ | |
3119 | ||
3120 | static void | |
3121 | vsx_ax_pseudo_register_collect (struct gdbarch *gdbarch, | |
3122 | struct agent_expr *ax, int reg_nr) | |
3123 | { | |
3124 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3125 | int reg_index, vr0, fp0, vsr0_upper; | |
3126 | ||
3127 | if (IS_VSX_PSEUDOREG (tdep, reg_nr)) | |
3128 | { | |
3129 | reg_index = reg_nr - tdep->ppc_vsr0_regnum; | |
3130 | vr0 = PPC_VR0_REGNUM; | |
3131 | fp0 = PPC_F0_REGNUM; | |
3132 | vsr0_upper = PPC_VSR0_UPPER_REGNUM; | |
3133 | } | |
3134 | else | |
3135 | { | |
3136 | gdb_assert (IS_CVSX_PSEUDOREG (tdep, reg_nr)); | |
3137 | ||
3138 | reg_index = reg_nr - tdep->ppc_cvsr0_regnum; | |
3139 | vr0 = PPC_CVR0_REGNUM; | |
3140 | fp0 = PPC_CF0_REGNUM; | |
3141 | vsr0_upper = PPC_CVSR0_UPPER_REGNUM; | |
3142 | } | |
3143 | ||
3144 | if (reg_index > 31) | |
3145 | { | |
3146 | ax_reg_mask (ax, vr0 + reg_index - 32); | |
3147 | } | |
3148 | else | |
3149 | { | |
3150 | ax_reg_mask (ax, fp0 + reg_index); | |
3151 | ax_reg_mask (ax, vsr0_upper + reg_index); | |
3152 | } | |
3153 | } | |
3154 | ||
3155 | /* Set the register mask in AX with the register that corresponds to | |
3156 | the EFP or checkpointed EFP pseudo-register REG_NR. */ | |
3157 | ||
3158 | static void | |
3159 | efp_ax_pseudo_register_collect (struct gdbarch *gdbarch, | |
3160 | struct agent_expr *ax, int reg_nr) | |
3161 | { | |
3162 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3163 | int reg_index, vr0; | |
3164 | ||
3165 | if (IS_EFP_PSEUDOREG (tdep, reg_nr)) | |
3166 | { | |
3167 | reg_index = reg_nr - tdep->ppc_efpr0_regnum; | |
3168 | vr0 = PPC_VR0_REGNUM; | |
3169 | } | |
3170 | else | |
3171 | { | |
3172 | gdb_assert (IS_CEFP_PSEUDOREG (tdep, reg_nr)); | |
3173 | ||
3174 | reg_index = reg_nr - tdep->ppc_cefpr0_regnum; | |
3175 | vr0 = PPC_CVR0_REGNUM; | |
3176 | } | |
3177 | ||
3178 | ax_reg_mask (ax, vr0 + reg_index); | |
3179 | } | |
3180 | ||
2a2fa07b MK |
3181 | static int |
3182 | rs6000_ax_pseudo_register_collect (struct gdbarch *gdbarch, | |
3183 | struct agent_expr *ax, int reg_nr) | |
3184 | { | |
3185 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3186 | if (IS_SPE_PSEUDOREG (tdep, reg_nr)) | |
3187 | { | |
3188 | int reg_index = reg_nr - tdep->ppc_ev0_regnum; | |
3189 | ax_reg_mask (ax, tdep->ppc_gp0_regnum + reg_index); | |
3190 | ax_reg_mask (ax, tdep->ppc_ev0_upper_regnum + reg_index); | |
3191 | } | |
8d619c01 EBM |
3192 | else if (IS_DFP_PSEUDOREG (tdep, reg_nr) |
3193 | || IS_CDFP_PSEUDOREG (tdep, reg_nr)) | |
2a2fa07b | 3194 | { |
8d619c01 | 3195 | dfp_ax_pseudo_register_collect (gdbarch, ax, reg_nr); |
2a2fa07b | 3196 | } |
6f072a10 PFC |
3197 | else if (IS_V_ALIAS_PSEUDOREG (tdep, reg_nr)) |
3198 | { | |
3199 | v_alias_pseudo_register_collect (gdbarch, ax, reg_nr); | |
3200 | } | |
8d619c01 EBM |
3201 | else if (IS_VSX_PSEUDOREG (tdep, reg_nr) |
3202 | || IS_CVSX_PSEUDOREG (tdep, reg_nr)) | |
2a2fa07b | 3203 | { |
8d619c01 | 3204 | vsx_ax_pseudo_register_collect (gdbarch, ax, reg_nr); |
2a2fa07b | 3205 | } |
8d619c01 EBM |
3206 | else if (IS_EFP_PSEUDOREG (tdep, reg_nr) |
3207 | || IS_CEFP_PSEUDOREG (tdep, reg_nr)) | |
2a2fa07b | 3208 | { |
8d619c01 | 3209 | efp_ax_pseudo_register_collect (gdbarch, ax, reg_nr); |
2a2fa07b MK |
3210 | } |
3211 | else | |
3212 | internal_error (__FILE__, __LINE__, | |
3213 | _("rs6000_pseudo_register_collect: " | |
3214 | "called on unexpected register '%s' (%d)"), | |
3215 | gdbarch_register_name (gdbarch, reg_nr), reg_nr); | |
3216 | return 0; | |
3217 | } | |
3218 | ||
3219 | ||
a67914de MK |
3220 | static void |
3221 | rs6000_gen_return_address (struct gdbarch *gdbarch, | |
3222 | struct agent_expr *ax, struct axs_value *value, | |
3223 | CORE_ADDR scope) | |
3224 | { | |
3225 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3226 | value->type = register_type (gdbarch, tdep->ppc_lr_regnum); | |
3227 | value->kind = axs_lvalue_register; | |
3228 | value->u.reg = tdep->ppc_lr_regnum; | |
3229 | } | |
3230 | ||
3231 | ||
18ed0c4e | 3232 | /* Convert a DBX STABS register number to a GDB register number. */ |
c8001721 | 3233 | static int |
d3f73121 | 3234 | rs6000_stab_reg_to_regnum (struct gdbarch *gdbarch, int num) |
c8001721 | 3235 | { |
d3f73121 | 3236 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
c8001721 | 3237 | |
9f744501 JB |
3238 | if (0 <= num && num <= 31) |
3239 | return tdep->ppc_gp0_regnum + num; | |
3240 | else if (32 <= num && num <= 63) | |
383f0f5b JB |
3241 | /* FIXME: jimb/2004-05-05: What should we do when the debug info |
3242 | specifies registers the architecture doesn't have? Our | |
3243 | callers don't check the value we return. */ | |
366f009f | 3244 | return tdep->ppc_fp0_regnum + (num - 32); |
18ed0c4e JB |
3245 | else if (77 <= num && num <= 108) |
3246 | return tdep->ppc_vr0_regnum + (num - 77); | |
9f744501 | 3247 | else if (1200 <= num && num < 1200 + 32) |
e1ec1b42 | 3248 | return tdep->ppc_ev0_upper_regnum + (num - 1200); |
9f744501 JB |
3249 | else |
3250 | switch (num) | |
3251 | { | |
3252 | case 64: | |
dda83cd7 | 3253 | return tdep->ppc_mq_regnum; |
9f744501 | 3254 | case 65: |
dda83cd7 | 3255 | return tdep->ppc_lr_regnum; |
9f744501 | 3256 | case 66: |
dda83cd7 | 3257 | return tdep->ppc_ctr_regnum; |
9f744501 | 3258 | case 76: |
dda83cd7 | 3259 | return tdep->ppc_xer_regnum; |
9f744501 | 3260 | case 109: |
dda83cd7 | 3261 | return tdep->ppc_vrsave_regnum; |
18ed0c4e | 3262 | case 110: |
dda83cd7 | 3263 | return tdep->ppc_vrsave_regnum - 1; /* vscr */ |
867e2dc5 | 3264 | case 111: |
dda83cd7 | 3265 | return tdep->ppc_acc_regnum; |
867e2dc5 | 3266 | case 112: |
dda83cd7 | 3267 | return tdep->ppc_spefscr_regnum; |
9f744501 | 3268 | default: |
dda83cd7 | 3269 | return num; |
9f744501 | 3270 | } |
18ed0c4e | 3271 | } |
9f744501 | 3272 | |
9f744501 | 3273 | |
18ed0c4e JB |
3274 | /* Convert a Dwarf 2 register number to a GDB register number. */ |
3275 | static int | |
d3f73121 | 3276 | rs6000_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int num) |
18ed0c4e | 3277 | { |
d3f73121 | 3278 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
9f744501 | 3279 | |
18ed0c4e JB |
3280 | if (0 <= num && num <= 31) |
3281 | return tdep->ppc_gp0_regnum + num; | |
3282 | else if (32 <= num && num <= 63) | |
3283 | /* FIXME: jimb/2004-05-05: What should we do when the debug info | |
3284 | specifies registers the architecture doesn't have? Our | |
3285 | callers don't check the value we return. */ | |
3286 | return tdep->ppc_fp0_regnum + (num - 32); | |
3287 | else if (1124 <= num && num < 1124 + 32) | |
3288 | return tdep->ppc_vr0_regnum + (num - 1124); | |
3289 | else if (1200 <= num && num < 1200 + 32) | |
e1ec1b42 | 3290 | return tdep->ppc_ev0_upper_regnum + (num - 1200); |
18ed0c4e JB |
3291 | else |
3292 | switch (num) | |
3293 | { | |
a489f789 AS |
3294 | case 64: |
3295 | return tdep->ppc_cr_regnum; | |
18ed0c4e | 3296 | case 67: |
dda83cd7 | 3297 | return tdep->ppc_vrsave_regnum - 1; /* vscr */ |
18ed0c4e | 3298 | case 99: |
dda83cd7 | 3299 | return tdep->ppc_acc_regnum; |
18ed0c4e | 3300 | case 100: |
dda83cd7 | 3301 | return tdep->ppc_mq_regnum; |
18ed0c4e | 3302 | case 101: |
dda83cd7 | 3303 | return tdep->ppc_xer_regnum; |
18ed0c4e | 3304 | case 108: |
dda83cd7 | 3305 | return tdep->ppc_lr_regnum; |
18ed0c4e | 3306 | case 109: |
dda83cd7 | 3307 | return tdep->ppc_ctr_regnum; |
18ed0c4e | 3308 | case 356: |
dda83cd7 | 3309 | return tdep->ppc_vrsave_regnum; |
18ed0c4e | 3310 | case 612: |
dda83cd7 | 3311 | return tdep->ppc_spefscr_regnum; |
18ed0c4e | 3312 | } |
aa2045e7 SM |
3313 | |
3314 | /* Unknown DWARF register number. */ | |
3315 | return -1; | |
2188cbdd EZ |
3316 | } |
3317 | ||
4fc771b8 DJ |
3318 | /* Translate a .eh_frame register to DWARF register, or adjust a |
3319 | .debug_frame register. */ | |
3320 | ||
3321 | static int | |
3322 | rs6000_adjust_frame_regnum (struct gdbarch *gdbarch, int num, int eh_frame_p) | |
3323 | { | |
3324 | /* GCC releases before 3.4 use GCC internal register numbering in | |
3325 | .debug_frame (and .debug_info, et cetera). The numbering is | |
3326 | different from the standard SysV numbering for everything except | |
3327 | for GPRs and FPRs. We can not detect this problem in most cases | |
3328 | - to get accurate debug info for variables living in lr, ctr, v0, | |
3329 | et cetera, use a newer version of GCC. But we must detect | |
3330 | one important case - lr is in column 65 in .debug_frame output, | |
3331 | instead of 108. | |
3332 | ||
3333 | GCC 3.4, and the "hammer" branch, have a related problem. They | |
3334 | record lr register saves in .debug_frame as 108, but still record | |
3335 | the return column as 65. We fix that up too. | |
3336 | ||
3337 | We can do this because 65 is assigned to fpsr, and GCC never | |
3338 | generates debug info referring to it. To add support for | |
3339 | handwritten debug info that restores fpsr, we would need to add a | |
3340 | producer version check to this. */ | |
3341 | if (!eh_frame_p) | |
3342 | { | |
3343 | if (num == 65) | |
3344 | return 108; | |
3345 | else | |
3346 | return num; | |
3347 | } | |
3348 | ||
3349 | /* .eh_frame is GCC specific. For binary compatibility, it uses GCC | |
3350 | internal register numbering; translate that to the standard DWARF2 | |
3351 | register numbering. */ | |
3352 | if (0 <= num && num <= 63) /* r0-r31,fp0-fp31 */ | |
3353 | return num; | |
3354 | else if (68 <= num && num <= 75) /* cr0-cr8 */ | |
3355 | return num - 68 + 86; | |
3356 | else if (77 <= num && num <= 108) /* vr0-vr31 */ | |
3357 | return num - 77 + 1124; | |
3358 | else | |
3359 | switch (num) | |
3360 | { | |
3361 | case 64: /* mq */ | |
3362 | return 100; | |
3363 | case 65: /* lr */ | |
3364 | return 108; | |
3365 | case 66: /* ctr */ | |
3366 | return 109; | |
3367 | case 76: /* xer */ | |
3368 | return 101; | |
3369 | case 109: /* vrsave */ | |
3370 | return 356; | |
3371 | case 110: /* vscr */ | |
3372 | return 67; | |
3373 | case 111: /* spe_acc */ | |
3374 | return 99; | |
3375 | case 112: /* spefscr */ | |
3376 | return 612; | |
3377 | default: | |
3378 | return num; | |
3379 | } | |
3380 | } | |
c906108c | 3381 | \f |
c5aa993b | 3382 | |
7a78ae4e | 3383 | /* Handling the various POWER/PowerPC variants. */ |
c906108c | 3384 | |
c906108c | 3385 | /* Information about a particular processor variant. */ |
7a78ae4e | 3386 | |
675127ec | 3387 | struct ppc_variant |
c5aa993b JM |
3388 | { |
3389 | /* Name of this variant. */ | |
a121b7c1 | 3390 | const char *name; |
c906108c | 3391 | |
c5aa993b | 3392 | /* English description of the variant. */ |
a121b7c1 | 3393 | const char *description; |
c906108c | 3394 | |
64366f1c | 3395 | /* bfd_arch_info.arch corresponding to variant. */ |
7a78ae4e ND |
3396 | enum bfd_architecture arch; |
3397 | ||
64366f1c | 3398 | /* bfd_arch_info.mach corresponding to variant. */ |
7a78ae4e ND |
3399 | unsigned long mach; |
3400 | ||
7cc46491 DJ |
3401 | /* Target description for this variant. */ |
3402 | struct target_desc **tdesc; | |
c5aa993b | 3403 | }; |
c906108c | 3404 | |
675127ec | 3405 | static struct ppc_variant variants[] = |
c906108c | 3406 | { |
7a78ae4e | 3407 | {"powerpc", "PowerPC user-level", bfd_arch_powerpc, |
7284e1be | 3408 | bfd_mach_ppc, &tdesc_powerpc_altivec32}, |
7a78ae4e | 3409 | {"power", "POWER user-level", bfd_arch_rs6000, |
7cc46491 | 3410 | bfd_mach_rs6k, &tdesc_rs6000}, |
7a78ae4e | 3411 | {"403", "IBM PowerPC 403", bfd_arch_powerpc, |
7cc46491 | 3412 | bfd_mach_ppc_403, &tdesc_powerpc_403}, |
4d09ffea MS |
3413 | {"405", "IBM PowerPC 405", bfd_arch_powerpc, |
3414 | bfd_mach_ppc_405, &tdesc_powerpc_405}, | |
7a78ae4e | 3415 | {"601", "Motorola PowerPC 601", bfd_arch_powerpc, |
7cc46491 | 3416 | bfd_mach_ppc_601, &tdesc_powerpc_601}, |
7a78ae4e | 3417 | {"602", "Motorola PowerPC 602", bfd_arch_powerpc, |
7cc46491 | 3418 | bfd_mach_ppc_602, &tdesc_powerpc_602}, |
7a78ae4e | 3419 | {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc, |
7cc46491 | 3420 | bfd_mach_ppc_603, &tdesc_powerpc_603}, |
7a78ae4e | 3421 | {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc, |
7cc46491 | 3422 | 604, &tdesc_powerpc_604}, |
7a78ae4e | 3423 | {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc, |
7cc46491 | 3424 | bfd_mach_ppc_403gc, &tdesc_powerpc_403gc}, |
7a78ae4e | 3425 | {"505", "Motorola PowerPC 505", bfd_arch_powerpc, |
7cc46491 | 3426 | bfd_mach_ppc_505, &tdesc_powerpc_505}, |
7a78ae4e | 3427 | {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc, |
7cc46491 | 3428 | bfd_mach_ppc_860, &tdesc_powerpc_860}, |
7a78ae4e | 3429 | {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc, |
7cc46491 | 3430 | bfd_mach_ppc_750, &tdesc_powerpc_750}, |
1fcc0bb8 | 3431 | {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc, |
7cc46491 | 3432 | bfd_mach_ppc_7400, &tdesc_powerpc_7400}, |
c8001721 | 3433 | {"e500", "Motorola PowerPC e500", bfd_arch_powerpc, |
7cc46491 | 3434 | bfd_mach_ppc_e500, &tdesc_powerpc_e500}, |
7a78ae4e | 3435 | |
5d57ee30 KB |
3436 | /* 64-bit */ |
3437 | {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc, | |
7284e1be | 3438 | bfd_mach_ppc64, &tdesc_powerpc_altivec64}, |
7a78ae4e | 3439 | {"620", "Motorola PowerPC 620", bfd_arch_powerpc, |
7cc46491 | 3440 | bfd_mach_ppc_620, &tdesc_powerpc_64}, |
5d57ee30 | 3441 | {"630", "Motorola PowerPC 630", bfd_arch_powerpc, |
7cc46491 | 3442 | bfd_mach_ppc_630, &tdesc_powerpc_64}, |
7a78ae4e | 3443 | {"a35", "PowerPC A35", bfd_arch_powerpc, |
7cc46491 | 3444 | bfd_mach_ppc_a35, &tdesc_powerpc_64}, |
5d57ee30 | 3445 | {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc, |
7cc46491 | 3446 | bfd_mach_ppc_rs64ii, &tdesc_powerpc_64}, |
5d57ee30 | 3447 | {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc, |
7cc46491 | 3448 | bfd_mach_ppc_rs64iii, &tdesc_powerpc_64}, |
5d57ee30 | 3449 | |
64366f1c | 3450 | /* FIXME: I haven't checked the register sets of the following. */ |
7a78ae4e | 3451 | {"rs1", "IBM POWER RS1", bfd_arch_rs6000, |
7cc46491 | 3452 | bfd_mach_rs6k_rs1, &tdesc_rs6000}, |
7a78ae4e | 3453 | {"rsc", "IBM POWER RSC", bfd_arch_rs6000, |
7cc46491 | 3454 | bfd_mach_rs6k_rsc, &tdesc_rs6000}, |
7a78ae4e | 3455 | {"rs2", "IBM POWER RS2", bfd_arch_rs6000, |
7cc46491 | 3456 | bfd_mach_rs6k_rs2, &tdesc_rs6000}, |
7a78ae4e | 3457 | |
3e45d68b | 3458 | {0, 0, (enum bfd_architecture) 0, 0, 0} |
c906108c SS |
3459 | }; |
3460 | ||
7a78ae4e | 3461 | /* Return the variant corresponding to architecture ARCH and machine number |
64366f1c | 3462 | MACH. If no such variant exists, return null. */ |
c906108c | 3463 | |
675127ec | 3464 | static const struct ppc_variant * |
7a78ae4e | 3465 | find_variant_by_arch (enum bfd_architecture arch, unsigned long mach) |
c906108c | 3466 | { |
675127ec | 3467 | const struct ppc_variant *v; |
c5aa993b | 3468 | |
7a78ae4e ND |
3469 | for (v = variants; v->name; v++) |
3470 | if (arch == v->arch && mach == v->mach) | |
3471 | return v; | |
c906108c | 3472 | |
7a78ae4e | 3473 | return NULL; |
c906108c | 3474 | } |
9364a0ef | 3475 | |
7a78ae4e | 3476 | \f |
61a65099 KB |
3477 | |
3478 | struct rs6000_frame_cache | |
3479 | { | |
3480 | CORE_ADDR base; | |
3481 | CORE_ADDR initial_sp; | |
098caef4 | 3482 | trad_frame_saved_reg *saved_regs; |
50ae56ec WW |
3483 | |
3484 | /* Set BASE_P to true if this frame cache is properly initialized. | |
3485 | Otherwise set to false because some registers or memory cannot | |
3486 | collected. */ | |
3487 | int base_p; | |
3488 | /* Cache PC for building unavailable frame. */ | |
3489 | CORE_ADDR pc; | |
61a65099 KB |
3490 | }; |
3491 | ||
3492 | static struct rs6000_frame_cache * | |
1af5d7ce | 3493 | rs6000_frame_cache (struct frame_info *this_frame, void **this_cache) |
61a65099 KB |
3494 | { |
3495 | struct rs6000_frame_cache *cache; | |
1af5d7ce | 3496 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
61a65099 | 3497 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
e17a4113 | 3498 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
61a65099 KB |
3499 | struct rs6000_framedata fdata; |
3500 | int wordsize = tdep->wordsize; | |
338435ef | 3501 | CORE_ADDR func = 0, pc = 0; |
61a65099 KB |
3502 | |
3503 | if ((*this_cache) != NULL) | |
19ba03f4 | 3504 | return (struct rs6000_frame_cache *) (*this_cache); |
61a65099 KB |
3505 | cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache); |
3506 | (*this_cache) = cache; | |
50ae56ec | 3507 | cache->pc = 0; |
1af5d7ce | 3508 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
61a65099 | 3509 | |
a70b8144 | 3510 | try |
50ae56ec WW |
3511 | { |
3512 | func = get_frame_func (this_frame); | |
3513 | cache->pc = func; | |
3514 | pc = get_frame_pc (this_frame); | |
3515 | skip_prologue (gdbarch, func, pc, &fdata); | |
3516 | ||
3517 | /* Figure out the parent's stack pointer. */ | |
3518 | ||
3519 | /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most | |
3520 | address of the current frame. Things might be easier if the | |
3521 | ->frame pointed to the outer-most address of the frame. In | |
3522 | the mean time, the address of the prev frame is used as the | |
3523 | base address of this frame. */ | |
3524 | cache->base = get_frame_register_unsigned | |
3525 | (this_frame, gdbarch_sp_regnum (gdbarch)); | |
3526 | } | |
230d2906 | 3527 | catch (const gdb_exception_error &ex) |
50ae56ec WW |
3528 | { |
3529 | if (ex.error != NOT_AVAILABLE_ERROR) | |
eedc3f4f | 3530 | throw; |
1ed0c2a4 | 3531 | return (struct rs6000_frame_cache *) (*this_cache); |
50ae56ec | 3532 | } |
e10b1c4c DJ |
3533 | |
3534 | /* If the function appears to be frameless, check a couple of likely | |
3535 | indicators that we have simply failed to find the frame setup. | |
3536 | Two common cases of this are missing symbols (i.e. | |
ef02daa9 | 3537 | get_frame_func returns the wrong address or 0), and assembly |
e10b1c4c DJ |
3538 | stubs which have a fast exit path but set up a frame on the slow |
3539 | path. | |
3540 | ||
3541 | If the LR appears to return to this function, then presume that | |
3542 | we have an ABI compliant frame that we failed to find. */ | |
3543 | if (fdata.frameless && fdata.lr_offset == 0) | |
61a65099 | 3544 | { |
e10b1c4c DJ |
3545 | CORE_ADDR saved_lr; |
3546 | int make_frame = 0; | |
3547 | ||
1af5d7ce | 3548 | saved_lr = get_frame_register_unsigned (this_frame, tdep->ppc_lr_regnum); |
e10b1c4c DJ |
3549 | if (func == 0 && saved_lr == pc) |
3550 | make_frame = 1; | |
3551 | else if (func != 0) | |
3552 | { | |
3553 | CORE_ADDR saved_func = get_pc_function_start (saved_lr); | |
3554 | if (func == saved_func) | |
3555 | make_frame = 1; | |
3556 | } | |
3557 | ||
3558 | if (make_frame) | |
3559 | { | |
3560 | fdata.frameless = 0; | |
de6a76fd | 3561 | fdata.lr_offset = tdep->lr_frame_offset; |
e10b1c4c | 3562 | } |
61a65099 | 3563 | } |
e10b1c4c DJ |
3564 | |
3565 | if (!fdata.frameless) | |
9d9bf2df EBM |
3566 | { |
3567 | /* Frameless really means stackless. */ | |
cc2c4da8 | 3568 | ULONGEST backchain; |
9d9bf2df | 3569 | |
cc2c4da8 MK |
3570 | if (safe_read_memory_unsigned_integer (cache->base, wordsize, |
3571 | byte_order, &backchain)) | |
dda83cd7 | 3572 | cache->base = (CORE_ADDR) backchain; |
9d9bf2df | 3573 | } |
e10b1c4c | 3574 | |
a9a87d35 | 3575 | cache->saved_regs[gdbarch_sp_regnum (gdbarch)].set_value (cache->base); |
61a65099 KB |
3576 | |
3577 | /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr. | |
3578 | All fpr's from saved_fpr to fp31 are saved. */ | |
3579 | ||
3580 | if (fdata.saved_fpr >= 0) | |
3581 | { | |
3582 | int i; | |
3583 | CORE_ADDR fpr_addr = cache->base + fdata.fpr_offset; | |
383f0f5b JB |
3584 | |
3585 | /* If skip_prologue says floating-point registers were saved, | |
dda83cd7 SM |
3586 | but the current architecture has no floating-point registers, |
3587 | then that's strange. But we have no indices to even record | |
3588 | the addresses under, so we just ignore it. */ | |
383f0f5b | 3589 | if (ppc_floating_point_unit_p (gdbarch)) |
dda83cd7 SM |
3590 | for (i = fdata.saved_fpr; i < ppc_num_fprs; i++) |
3591 | { | |
098caef4 | 3592 | cache->saved_regs[tdep->ppc_fp0_regnum + i].set_addr (fpr_addr); |
dda83cd7 SM |
3593 | fpr_addr += 8; |
3594 | } | |
61a65099 KB |
3595 | } |
3596 | ||
3597 | /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr. | |
46a9b8ed DJ |
3598 | All gpr's from saved_gpr to gpr31 are saved (except during the |
3599 | prologue). */ | |
61a65099 KB |
3600 | |
3601 | if (fdata.saved_gpr >= 0) | |
3602 | { | |
3603 | int i; | |
3604 | CORE_ADDR gpr_addr = cache->base + fdata.gpr_offset; | |
063715bf | 3605 | for (i = fdata.saved_gpr; i < ppc_num_gprs; i++) |
61a65099 | 3606 | { |
46a9b8ed | 3607 | if (fdata.gpr_mask & (1U << i)) |
098caef4 | 3608 | cache->saved_regs[tdep->ppc_gp0_regnum + i].set_addr (gpr_addr); |
61a65099 KB |
3609 | gpr_addr += wordsize; |
3610 | } | |
3611 | } | |
3612 | ||
3613 | /* if != -1, fdata.saved_vr is the smallest number of saved_vr. | |
3614 | All vr's from saved_vr to vr31 are saved. */ | |
3615 | if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) | |
3616 | { | |
3617 | if (fdata.saved_vr >= 0) | |
3618 | { | |
3619 | int i; | |
3620 | CORE_ADDR vr_addr = cache->base + fdata.vr_offset; | |
3621 | for (i = fdata.saved_vr; i < 32; i++) | |
3622 | { | |
098caef4 | 3623 | cache->saved_regs[tdep->ppc_vr0_regnum + i].set_addr (vr_addr); |
61a65099 KB |
3624 | vr_addr += register_size (gdbarch, tdep->ppc_vr0_regnum); |
3625 | } | |
3626 | } | |
3627 | } | |
3628 | ||
3629 | /* if != -1, fdata.saved_ev is the smallest number of saved_ev. | |
0df8b418 | 3630 | All vr's from saved_ev to ev31 are saved. ????? */ |
5a9e69ba | 3631 | if (tdep->ppc_ev0_regnum != -1) |
61a65099 KB |
3632 | { |
3633 | if (fdata.saved_ev >= 0) | |
3634 | { | |
3635 | int i; | |
3636 | CORE_ADDR ev_addr = cache->base + fdata.ev_offset; | |
dea80df0 MR |
3637 | CORE_ADDR off = (byte_order == BFD_ENDIAN_BIG ? 4 : 0); |
3638 | ||
063715bf | 3639 | for (i = fdata.saved_ev; i < ppc_num_gprs; i++) |
61a65099 | 3640 | { |
098caef4 LM |
3641 | cache->saved_regs[tdep->ppc_ev0_regnum + i].set_addr (ev_addr); |
3642 | cache->saved_regs[tdep->ppc_gp0_regnum + i].set_addr (ev_addr | |
3643 | + off); | |
61a65099 | 3644 | ev_addr += register_size (gdbarch, tdep->ppc_ev0_regnum); |
dea80df0 | 3645 | } |
61a65099 KB |
3646 | } |
3647 | } | |
3648 | ||
3649 | /* If != 0, fdata.cr_offset is the offset from the frame that | |
3650 | holds the CR. */ | |
3651 | if (fdata.cr_offset != 0) | |
098caef4 LM |
3652 | cache->saved_regs[tdep->ppc_cr_regnum].set_addr (cache->base |
3653 | + fdata.cr_offset); | |
61a65099 KB |
3654 | |
3655 | /* If != 0, fdata.lr_offset is the offset from the frame that | |
3656 | holds the LR. */ | |
3657 | if (fdata.lr_offset != 0) | |
098caef4 LM |
3658 | cache->saved_regs[tdep->ppc_lr_regnum].set_addr (cache->base |
3659 | + fdata.lr_offset); | |
46a9b8ed | 3660 | else if (fdata.lr_register != -1) |
098caef4 | 3661 | cache->saved_regs[tdep->ppc_lr_regnum].set_realreg (fdata.lr_register); |
61a65099 | 3662 | /* The PC is found in the link register. */ |
8b164abb | 3663 | cache->saved_regs[gdbarch_pc_regnum (gdbarch)] = |
3e8c568d | 3664 | cache->saved_regs[tdep->ppc_lr_regnum]; |
61a65099 KB |
3665 | |
3666 | /* If != 0, fdata.vrsave_offset is the offset from the frame that | |
3667 | holds the VRSAVE. */ | |
3668 | if (fdata.vrsave_offset != 0) | |
098caef4 LM |
3669 | cache->saved_regs[tdep->ppc_vrsave_regnum].set_addr (cache->base |
3670 | + fdata.vrsave_offset); | |
61a65099 KB |
3671 | |
3672 | if (fdata.alloca_reg < 0) | |
3673 | /* If no alloca register used, then fi->frame is the value of the | |
3674 | %sp for this frame, and it is good enough. */ | |
1af5d7ce UW |
3675 | cache->initial_sp |
3676 | = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch)); | |
61a65099 | 3677 | else |
1af5d7ce UW |
3678 | cache->initial_sp |
3679 | = get_frame_register_unsigned (this_frame, fdata.alloca_reg); | |
61a65099 | 3680 | |
50ae56ec | 3681 | cache->base_p = 1; |
61a65099 KB |
3682 | return cache; |
3683 | } | |
3684 | ||
3685 | static void | |
1af5d7ce | 3686 | rs6000_frame_this_id (struct frame_info *this_frame, void **this_cache, |
61a65099 KB |
3687 | struct frame_id *this_id) |
3688 | { | |
1af5d7ce | 3689 | struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame, |
61a65099 | 3690 | this_cache); |
50ae56ec WW |
3691 | |
3692 | if (!info->base_p) | |
3693 | { | |
3694 | (*this_id) = frame_id_build_unavailable_stack (info->pc); | |
3695 | return; | |
3696 | } | |
3697 | ||
5b197912 UW |
3698 | /* This marks the outermost frame. */ |
3699 | if (info->base == 0) | |
3700 | return; | |
3701 | ||
1af5d7ce | 3702 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); |
61a65099 KB |
3703 | } |
3704 | ||
1af5d7ce UW |
3705 | static struct value * |
3706 | rs6000_frame_prev_register (struct frame_info *this_frame, | |
3707 | void **this_cache, int regnum) | |
61a65099 | 3708 | { |
1af5d7ce | 3709 | struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame, |
61a65099 | 3710 | this_cache); |
1af5d7ce | 3711 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
61a65099 KB |
3712 | } |
3713 | ||
3714 | static const struct frame_unwind rs6000_frame_unwind = | |
3715 | { | |
3716 | NORMAL_FRAME, | |
8fbca658 | 3717 | default_frame_unwind_stop_reason, |
61a65099 | 3718 | rs6000_frame_this_id, |
1af5d7ce UW |
3719 | rs6000_frame_prev_register, |
3720 | NULL, | |
3721 | default_frame_sniffer | |
61a65099 | 3722 | }; |
2608dbf8 | 3723 | |
ddeca1df WW |
3724 | /* Allocate and initialize a frame cache for an epilogue frame. |
3725 | SP is restored and prev-PC is stored in LR. */ | |
3726 | ||
2608dbf8 WW |
3727 | static struct rs6000_frame_cache * |
3728 | rs6000_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache) | |
3729 | { | |
2608dbf8 WW |
3730 | struct rs6000_frame_cache *cache; |
3731 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
3732 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2608dbf8 WW |
3733 | |
3734 | if (*this_cache) | |
19ba03f4 | 3735 | return (struct rs6000_frame_cache *) *this_cache; |
2608dbf8 WW |
3736 | |
3737 | cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache); | |
3738 | (*this_cache) = cache; | |
3739 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); | |
3740 | ||
a70b8144 | 3741 | try |
2608dbf8 WW |
3742 | { |
3743 | /* At this point the stack looks as if we just entered the | |
3744 | function, and the return address is stored in LR. */ | |
3745 | CORE_ADDR sp, lr; | |
3746 | ||
3747 | sp = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch)); | |
3748 | lr = get_frame_register_unsigned (this_frame, tdep->ppc_lr_regnum); | |
3749 | ||
3750 | cache->base = sp; | |
3751 | cache->initial_sp = sp; | |
3752 | ||
a9a87d35 | 3753 | cache->saved_regs[gdbarch_pc_regnum (gdbarch)].set_value (lr); |
2608dbf8 | 3754 | } |
230d2906 | 3755 | catch (const gdb_exception_error &ex) |
7556d4a4 PA |
3756 | { |
3757 | if (ex.error != NOT_AVAILABLE_ERROR) | |
eedc3f4f | 3758 | throw; |
7556d4a4 | 3759 | } |
2608dbf8 WW |
3760 | |
3761 | return cache; | |
3762 | } | |
3763 | ||
ddeca1df WW |
3764 | /* Implementation of frame_unwind.this_id, as defined in frame_unwind.h. |
3765 | Return the frame ID of an epilogue frame. */ | |
3766 | ||
2608dbf8 WW |
3767 | static void |
3768 | rs6000_epilogue_frame_this_id (struct frame_info *this_frame, | |
3769 | void **this_cache, struct frame_id *this_id) | |
3770 | { | |
3771 | CORE_ADDR pc; | |
3772 | struct rs6000_frame_cache *info = | |
3773 | rs6000_epilogue_frame_cache (this_frame, this_cache); | |
3774 | ||
3775 | pc = get_frame_func (this_frame); | |
3776 | if (info->base == 0) | |
3777 | (*this_id) = frame_id_build_unavailable_stack (pc); | |
3778 | else | |
3779 | (*this_id) = frame_id_build (info->base, pc); | |
3780 | } | |
3781 | ||
ddeca1df WW |
3782 | /* Implementation of frame_unwind.prev_register, as defined in frame_unwind.h. |
3783 | Return the register value of REGNUM in previous frame. */ | |
3784 | ||
2608dbf8 WW |
3785 | static struct value * |
3786 | rs6000_epilogue_frame_prev_register (struct frame_info *this_frame, | |
3787 | void **this_cache, int regnum) | |
3788 | { | |
3789 | struct rs6000_frame_cache *info = | |
3790 | rs6000_epilogue_frame_cache (this_frame, this_cache); | |
3791 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); | |
3792 | } | |
3793 | ||
ddeca1df WW |
3794 | /* Implementation of frame_unwind.sniffer, as defined in frame_unwind.h. |
3795 | Check whether this an epilogue frame. */ | |
3796 | ||
2608dbf8 WW |
3797 | static int |
3798 | rs6000_epilogue_frame_sniffer (const struct frame_unwind *self, | |
3799 | struct frame_info *this_frame, | |
3800 | void **this_prologue_cache) | |
3801 | { | |
3802 | if (frame_relative_level (this_frame) == 0) | |
3803 | return rs6000_in_function_epilogue_frame_p (this_frame, | |
3804 | get_frame_arch (this_frame), | |
3805 | get_frame_pc (this_frame)); | |
3806 | else | |
3807 | return 0; | |
3808 | } | |
3809 | ||
ddeca1df WW |
3810 | /* Frame unwinder for epilogue frame. This is required for reverse step-over |
3811 | a function without debug information. */ | |
3812 | ||
2608dbf8 WW |
3813 | static const struct frame_unwind rs6000_epilogue_frame_unwind = |
3814 | { | |
3815 | NORMAL_FRAME, | |
3816 | default_frame_unwind_stop_reason, | |
3817 | rs6000_epilogue_frame_this_id, rs6000_epilogue_frame_prev_register, | |
3818 | NULL, | |
3819 | rs6000_epilogue_frame_sniffer | |
3820 | }; | |
61a65099 KB |
3821 | \f |
3822 | ||
3823 | static CORE_ADDR | |
1af5d7ce | 3824 | rs6000_frame_base_address (struct frame_info *this_frame, void **this_cache) |
61a65099 | 3825 | { |
1af5d7ce | 3826 | struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame, |
61a65099 KB |
3827 | this_cache); |
3828 | return info->initial_sp; | |
3829 | } | |
3830 | ||
3831 | static const struct frame_base rs6000_frame_base = { | |
3832 | &rs6000_frame_unwind, | |
3833 | rs6000_frame_base_address, | |
3834 | rs6000_frame_base_address, | |
3835 | rs6000_frame_base_address | |
3836 | }; | |
3837 | ||
3838 | static const struct frame_base * | |
1af5d7ce | 3839 | rs6000_frame_base_sniffer (struct frame_info *this_frame) |
61a65099 KB |
3840 | { |
3841 | return &rs6000_frame_base; | |
3842 | } | |
3843 | ||
9274a07c LM |
3844 | /* DWARF-2 frame support. Used to handle the detection of |
3845 | clobbered registers during function calls. */ | |
3846 | ||
3847 | static void | |
3848 | ppc_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
3849 | struct dwarf2_frame_state_reg *reg, | |
4a4e5149 | 3850 | struct frame_info *this_frame) |
9274a07c LM |
3851 | { |
3852 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3853 | ||
3854 | /* PPC32 and PPC64 ABI's are the same regarding volatile and | |
3855 | non-volatile registers. We will use the same code for both. */ | |
3856 | ||
3857 | /* Call-saved GP registers. */ | |
3858 | if ((regnum >= tdep->ppc_gp0_regnum + 14 | |
3859 | && regnum <= tdep->ppc_gp0_regnum + 31) | |
3860 | || (regnum == tdep->ppc_gp0_regnum + 1)) | |
3861 | reg->how = DWARF2_FRAME_REG_SAME_VALUE; | |
3862 | ||
3863 | /* Call-clobbered GP registers. */ | |
3864 | if ((regnum >= tdep->ppc_gp0_regnum + 3 | |
3865 | && regnum <= tdep->ppc_gp0_regnum + 12) | |
3866 | || (regnum == tdep->ppc_gp0_regnum)) | |
3867 | reg->how = DWARF2_FRAME_REG_UNDEFINED; | |
3868 | ||
3869 | /* Deal with FP registers, if supported. */ | |
3870 | if (tdep->ppc_fp0_regnum >= 0) | |
3871 | { | |
3872 | /* Call-saved FP registers. */ | |
3873 | if ((regnum >= tdep->ppc_fp0_regnum + 14 | |
3874 | && regnum <= tdep->ppc_fp0_regnum + 31)) | |
3875 | reg->how = DWARF2_FRAME_REG_SAME_VALUE; | |
3876 | ||
3877 | /* Call-clobbered FP registers. */ | |
3878 | if ((regnum >= tdep->ppc_fp0_regnum | |
3879 | && regnum <= tdep->ppc_fp0_regnum + 13)) | |
3880 | reg->how = DWARF2_FRAME_REG_UNDEFINED; | |
3881 | } | |
3882 | ||
3883 | /* Deal with ALTIVEC registers, if supported. */ | |
3884 | if (tdep->ppc_vr0_regnum > 0 && tdep->ppc_vrsave_regnum > 0) | |
3885 | { | |
3886 | /* Call-saved Altivec registers. */ | |
3887 | if ((regnum >= tdep->ppc_vr0_regnum + 20 | |
3888 | && regnum <= tdep->ppc_vr0_regnum + 31) | |
3889 | || regnum == tdep->ppc_vrsave_regnum) | |
3890 | reg->how = DWARF2_FRAME_REG_SAME_VALUE; | |
3891 | ||
3892 | /* Call-clobbered Altivec registers. */ | |
3893 | if ((regnum >= tdep->ppc_vr0_regnum | |
3894 | && regnum <= tdep->ppc_vr0_regnum + 19)) | |
3895 | reg->how = DWARF2_FRAME_REG_UNDEFINED; | |
3896 | } | |
3897 | ||
3898 | /* Handle PC register and Stack Pointer correctly. */ | |
40a6adc1 | 3899 | if (regnum == gdbarch_pc_regnum (gdbarch)) |
9274a07c | 3900 | reg->how = DWARF2_FRAME_REG_RA; |
40a6adc1 | 3901 | else if (regnum == gdbarch_sp_regnum (gdbarch)) |
9274a07c LM |
3902 | reg->how = DWARF2_FRAME_REG_CFA; |
3903 | } | |
3904 | ||
3905 | ||
74af9197 NF |
3906 | /* Return true if a .gnu_attributes section exists in BFD and it |
3907 | indicates we are using SPE extensions OR if a .PPC.EMB.apuinfo | |
3908 | section exists in BFD and it indicates that SPE extensions are in | |
3909 | use. Check the .gnu.attributes section first, as the binary might be | |
3910 | compiled for SPE, but not actually using SPE instructions. */ | |
3911 | ||
3912 | static int | |
3913 | bfd_uses_spe_extensions (bfd *abfd) | |
3914 | { | |
3915 | asection *sect; | |
3916 | gdb_byte *contents = NULL; | |
3917 | bfd_size_type size; | |
3918 | gdb_byte *ptr; | |
3919 | int success = 0; | |
74af9197 NF |
3920 | |
3921 | if (!abfd) | |
3922 | return 0; | |
3923 | ||
50a99728 | 3924 | #ifdef HAVE_ELF |
74af9197 NF |
3925 | /* Using Tag_GNU_Power_ABI_Vector here is a bit of a hack, as the user |
3926 | could be using the SPE vector abi without actually using any spe | |
3927 | bits whatsoever. But it's close enough for now. */ | |
17cbafdb SM |
3928 | int vector_abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_GNU, |
3929 | Tag_GNU_Power_ABI_Vector); | |
74af9197 NF |
3930 | if (vector_abi == 3) |
3931 | return 1; | |
50a99728 | 3932 | #endif |
74af9197 NF |
3933 | |
3934 | sect = bfd_get_section_by_name (abfd, ".PPC.EMB.apuinfo"); | |
3935 | if (!sect) | |
3936 | return 0; | |
3937 | ||
fd361982 | 3938 | size = bfd_section_size (sect); |
224c3ddb | 3939 | contents = (gdb_byte *) xmalloc (size); |
74af9197 NF |
3940 | if (!bfd_get_section_contents (abfd, sect, contents, 0, size)) |
3941 | { | |
3942 | xfree (contents); | |
3943 | return 0; | |
3944 | } | |
3945 | ||
3946 | /* Parse the .PPC.EMB.apuinfo section. The layout is as follows: | |
3947 | ||
3948 | struct { | |
3949 | uint32 name_len; | |
3950 | uint32 data_len; | |
3951 | uint32 type; | |
3952 | char name[name_len rounded up to 4-byte alignment]; | |
3953 | char data[data_len]; | |
3954 | }; | |
3955 | ||
3956 | Technically, there's only supposed to be one such structure in a | |
3957 | given apuinfo section, but the linker is not always vigilant about | |
3958 | merging apuinfo sections from input files. Just go ahead and parse | |
3959 | them all, exiting early when we discover the binary uses SPE | |
3960 | insns. | |
3961 | ||
3962 | It's not specified in what endianness the information in this | |
3963 | section is stored. Assume that it's the endianness of the BFD. */ | |
3964 | ptr = contents; | |
3965 | while (1) | |
3966 | { | |
3967 | unsigned int name_len; | |
3968 | unsigned int data_len; | |
3969 | unsigned int type; | |
3970 | ||
3971 | /* If we can't read the first three fields, we're done. */ | |
3972 | if (size < 12) | |
3973 | break; | |
3974 | ||
3975 | name_len = bfd_get_32 (abfd, ptr); | |
3976 | name_len = (name_len + 3) & ~3U; /* Round to 4 bytes. */ | |
3977 | data_len = bfd_get_32 (abfd, ptr + 4); | |
3978 | type = bfd_get_32 (abfd, ptr + 8); | |
3979 | ptr += 12; | |
3980 | ||
3981 | /* The name must be "APUinfo\0". */ | |
3982 | if (name_len != 8 | |
3983 | && strcmp ((const char *) ptr, "APUinfo") != 0) | |
3984 | break; | |
3985 | ptr += name_len; | |
3986 | ||
3987 | /* The type must be 2. */ | |
3988 | if (type != 2) | |
3989 | break; | |
3990 | ||
3991 | /* The data is stored as a series of uint32. The upper half of | |
3992 | each uint32 indicates the particular APU used and the lower | |
3993 | half indicates the revision of that APU. We just care about | |
3994 | the upper half. */ | |
3995 | ||
3996 | /* Not 4-byte quantities. */ | |
3997 | if (data_len & 3U) | |
3998 | break; | |
3999 | ||
4000 | while (data_len) | |
4001 | { | |
4002 | unsigned int apuinfo = bfd_get_32 (abfd, ptr); | |
4003 | unsigned int apu = apuinfo >> 16; | |
4004 | ptr += 4; | |
4005 | data_len -= 4; | |
4006 | ||
4007 | /* The SPE APU is 0x100; the SPEFP APU is 0x101. Accept | |
4008 | either. */ | |
4009 | if (apu == 0x100 || apu == 0x101) | |
4010 | { | |
4011 | success = 1; | |
4012 | data_len = 0; | |
4013 | } | |
4014 | } | |
4015 | ||
4016 | if (success) | |
4017 | break; | |
4018 | } | |
4019 | ||
4020 | xfree (contents); | |
4021 | return success; | |
4022 | } | |
4023 | ||
b4cdae6f WW |
4024 | /* These are macros for parsing instruction fields (I.1.6.28) */ |
4025 | ||
4026 | #define PPC_FIELD(value, from, len) \ | |
4027 | (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1)) | |
4028 | #define PPC_SEXT(v, bs) \ | |
4029 | ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \ | |
4030 | ^ ((CORE_ADDR) 1 << ((bs) - 1))) \ | |
4031 | - ((CORE_ADDR) 1 << ((bs) - 1))) | |
4032 | #define PPC_OP6(insn) PPC_FIELD (insn, 0, 6) | |
4033 | #define PPC_EXTOP(insn) PPC_FIELD (insn, 21, 10) | |
4034 | #define PPC_RT(insn) PPC_FIELD (insn, 6, 5) | |
4035 | #define PPC_RS(insn) PPC_FIELD (insn, 6, 5) | |
4036 | #define PPC_RA(insn) PPC_FIELD (insn, 11, 5) | |
4037 | #define PPC_RB(insn) PPC_FIELD (insn, 16, 5) | |
4038 | #define PPC_NB(insn) PPC_FIELD (insn, 16, 5) | |
4039 | #define PPC_VRT(insn) PPC_FIELD (insn, 6, 5) | |
4040 | #define PPC_FRT(insn) PPC_FIELD (insn, 6, 5) | |
4041 | #define PPC_SPR(insn) (PPC_FIELD (insn, 11, 5) \ | |
4042 | | (PPC_FIELD (insn, 16, 5) << 5)) | |
4043 | #define PPC_BO(insn) PPC_FIELD (insn, 6, 5) | |
4044 | #define PPC_T(insn) PPC_FIELD (insn, 6, 5) | |
4045 | #define PPC_D(insn) PPC_SEXT (PPC_FIELD (insn, 16, 16), 16) | |
4046 | #define PPC_DS(insn) PPC_SEXT (PPC_FIELD (insn, 16, 14), 14) | |
6ec2b213 | 4047 | #define PPC_DQ(insn) PPC_SEXT (PPC_FIELD (insn, 16, 12), 12) |
b4cdae6f WW |
4048 | #define PPC_BIT(insn,n) ((insn & (1 << (31 - (n)))) ? 1 : 0) |
4049 | #define PPC_OE(insn) PPC_BIT (insn, 21) | |
4050 | #define PPC_RC(insn) PPC_BIT (insn, 31) | |
4051 | #define PPC_Rc(insn) PPC_BIT (insn, 21) | |
4052 | #define PPC_LK(insn) PPC_BIT (insn, 31) | |
4053 | #define PPC_TX(insn) PPC_BIT (insn, 31) | |
4054 | #define PPC_LEV(insn) PPC_FIELD (insn, 20, 7) | |
4055 | ||
4056 | #define PPC_XT(insn) ((PPC_TX (insn) << 5) | PPC_T (insn)) | |
4057 | #define PPC_XER_NB(xer) (xer & 0x7f) | |
4058 | ||
ddeca1df WW |
4059 | /* Record Vector-Scalar Registers. |
4060 | For VSR less than 32, it's represented by an FPR and an VSR-upper register. | |
4061 | Otherwise, it's just a VR register. Record them accordingly. */ | |
b4cdae6f WW |
4062 | |
4063 | static int | |
4064 | ppc_record_vsr (struct regcache *regcache, struct gdbarch_tdep *tdep, int vsr) | |
4065 | { | |
4066 | if (vsr < 0 || vsr >= 64) | |
4067 | return -1; | |
4068 | ||
4069 | if (vsr >= 32) | |
4070 | { | |
4071 | if (tdep->ppc_vr0_regnum >= 0) | |
4072 | record_full_arch_list_add_reg (regcache, tdep->ppc_vr0_regnum + vsr - 32); | |
4073 | } | |
4074 | else | |
4075 | { | |
4076 | if (tdep->ppc_fp0_regnum >= 0) | |
4077 | record_full_arch_list_add_reg (regcache, tdep->ppc_fp0_regnum + vsr); | |
4078 | if (tdep->ppc_vsr0_upper_regnum >= 0) | |
4079 | record_full_arch_list_add_reg (regcache, | |
4080 | tdep->ppc_vsr0_upper_regnum + vsr); | |
4081 | } | |
4082 | ||
4083 | return 0; | |
4084 | } | |
4085 | ||
ddeca1df WW |
4086 | /* Parse and record instructions primary opcode-4 at ADDR. |
4087 | Return 0 if successful. */ | |
b4cdae6f WW |
4088 | |
4089 | static int | |
4090 | ppc_process_record_op4 (struct gdbarch *gdbarch, struct regcache *regcache, | |
ddeca1df | 4091 | CORE_ADDR addr, uint32_t insn) |
b4cdae6f WW |
4092 | { |
4093 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
4094 | int ext = PPC_FIELD (insn, 21, 11); | |
6ec2b213 | 4095 | int vra = PPC_FIELD (insn, 11, 5); |
b4cdae6f WW |
4096 | |
4097 | switch (ext & 0x3f) | |
4098 | { | |
4099 | case 32: /* Vector Multiply-High-Add Signed Halfword Saturate */ | |
4100 | case 33: /* Vector Multiply-High-Round-Add Signed Halfword Saturate */ | |
4101 | case 39: /* Vector Multiply-Sum Unsigned Halfword Saturate */ | |
4102 | case 41: /* Vector Multiply-Sum Signed Halfword Saturate */ | |
4103 | record_full_arch_list_add_reg (regcache, PPC_VSCR_REGNUM); | |
4104 | /* FALL-THROUGH */ | |
4105 | case 42: /* Vector Select */ | |
4106 | case 43: /* Vector Permute */ | |
6ec2b213 | 4107 | case 59: /* Vector Permute Right-indexed */ |
b4cdae6f WW |
4108 | case 44: /* Vector Shift Left Double by Octet Immediate */ |
4109 | case 45: /* Vector Permute and Exclusive-OR */ | |
4110 | case 60: /* Vector Add Extended Unsigned Quadword Modulo */ | |
4111 | case 61: /* Vector Add Extended & write Carry Unsigned Quadword */ | |
4112 | case 62: /* Vector Subtract Extended Unsigned Quadword Modulo */ | |
4113 | case 63: /* Vector Subtract Extended & write Carry Unsigned Quadword */ | |
4114 | case 34: /* Vector Multiply-Low-Add Unsigned Halfword Modulo */ | |
6ec2b213 | 4115 | case 35: /* Vector Multiply-Sum Unsigned Doubleword Modulo */ |
b4cdae6f WW |
4116 | case 36: /* Vector Multiply-Sum Unsigned Byte Modulo */ |
4117 | case 37: /* Vector Multiply-Sum Mixed Byte Modulo */ | |
4118 | case 38: /* Vector Multiply-Sum Unsigned Halfword Modulo */ | |
4119 | case 40: /* Vector Multiply-Sum Signed Halfword Modulo */ | |
4120 | case 46: /* Vector Multiply-Add Single-Precision */ | |
4121 | case 47: /* Vector Negative Multiply-Subtract Single-Precision */ | |
4122 | record_full_arch_list_add_reg (regcache, | |
4123 | tdep->ppc_vr0_regnum + PPC_VRT (insn)); | |
4124 | return 0; | |
6ec2b213 EBM |
4125 | |
4126 | case 48: /* Multiply-Add High Doubleword */ | |
4127 | case 49: /* Multiply-Add High Doubleword Unsigned */ | |
4128 | case 51: /* Multiply-Add Low Doubleword */ | |
4129 | record_full_arch_list_add_reg (regcache, | |
4130 | tdep->ppc_gp0_regnum + PPC_RT (insn)); | |
4131 | return 0; | |
b4cdae6f WW |
4132 | } |
4133 | ||
4134 | switch ((ext & 0x1ff)) | |
4135 | { | |
6ec2b213 EBM |
4136 | case 385: |
4137 | if (vra != 0 /* Decimal Convert To Signed Quadword */ | |
4138 | && vra != 2 /* Decimal Convert From Signed Quadword */ | |
4139 | && vra != 4 /* Decimal Convert To Zoned */ | |
4140 | && vra != 5 /* Decimal Convert To National */ | |
4141 | && vra != 6 /* Decimal Convert From Zoned */ | |
4142 | && vra != 7 /* Decimal Convert From National */ | |
4143 | && vra != 31) /* Decimal Set Sign */ | |
4144 | break; | |
e3829d13 | 4145 | /* Fall through. */ |
b4cdae6f WW |
4146 | /* 5.16 Decimal Integer Arithmetic Instructions */ |
4147 | case 1: /* Decimal Add Modulo */ | |
4148 | case 65: /* Decimal Subtract Modulo */ | |
4149 | ||
6ec2b213 EBM |
4150 | case 193: /* Decimal Shift */ |
4151 | case 129: /* Decimal Unsigned Shift */ | |
4152 | case 449: /* Decimal Shift and Round */ | |
4153 | ||
4154 | case 257: /* Decimal Truncate */ | |
4155 | case 321: /* Decimal Unsigned Truncate */ | |
4156 | ||
b4cdae6f WW |
4157 | /* Bit-21 should be set. */ |
4158 | if (!PPC_BIT (insn, 21)) | |
4159 | break; | |
4160 | ||
4161 | record_full_arch_list_add_reg (regcache, | |
4162 | tdep->ppc_vr0_regnum + PPC_VRT (insn)); | |
4163 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
4164 | return 0; | |
4165 | } | |
4166 | ||
4167 | /* Bit-21 is used for RC */ | |
4168 | switch (ext & 0x3ff) | |
4169 | { | |
4170 | case 6: /* Vector Compare Equal To Unsigned Byte */ | |
4171 | case 70: /* Vector Compare Equal To Unsigned Halfword */ | |
4172 | case 134: /* Vector Compare Equal To Unsigned Word */ | |
4173 | case 199: /* Vector Compare Equal To Unsigned Doubleword */ | |
4174 | case 774: /* Vector Compare Greater Than Signed Byte */ | |
4175 | case 838: /* Vector Compare Greater Than Signed Halfword */ | |
4176 | case 902: /* Vector Compare Greater Than Signed Word */ | |
4177 | case 967: /* Vector Compare Greater Than Signed Doubleword */ | |
4178 | case 518: /* Vector Compare Greater Than Unsigned Byte */ | |
4179 | case 646: /* Vector Compare Greater Than Unsigned Word */ | |
4180 | case 582: /* Vector Compare Greater Than Unsigned Halfword */ | |
4181 | case 711: /* Vector Compare Greater Than Unsigned Doubleword */ | |
4182 | case 966: /* Vector Compare Bounds Single-Precision */ | |
4183 | case 198: /* Vector Compare Equal To Single-Precision */ | |
4184 | case 454: /* Vector Compare Greater Than or Equal To Single-Precision */ | |
4185 | case 710: /* Vector Compare Greater Than Single-Precision */ | |
6ec2b213 EBM |
4186 | case 7: /* Vector Compare Not Equal Byte */ |
4187 | case 71: /* Vector Compare Not Equal Halfword */ | |
4188 | case 135: /* Vector Compare Not Equal Word */ | |
4189 | case 263: /* Vector Compare Not Equal or Zero Byte */ | |
4190 | case 327: /* Vector Compare Not Equal or Zero Halfword */ | |
4191 | case 391: /* Vector Compare Not Equal or Zero Word */ | |
b4cdae6f WW |
4192 | if (PPC_Rc (insn)) |
4193 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
4194 | record_full_arch_list_add_reg (regcache, | |
4195 | tdep->ppc_vr0_regnum + PPC_VRT (insn)); | |
4196 | return 0; | |
4197 | } | |
4198 | ||
6ec2b213 EBM |
4199 | if (ext == 1538) |
4200 | { | |
4201 | switch (vra) | |
4202 | { | |
4203 | case 0: /* Vector Count Leading Zero Least-Significant Bits | |
4204 | Byte */ | |
4205 | case 1: /* Vector Count Trailing Zero Least-Significant Bits | |
4206 | Byte */ | |
4207 | record_full_arch_list_add_reg (regcache, | |
4208 | tdep->ppc_gp0_regnum + PPC_RT (insn)); | |
4209 | return 0; | |
4210 | ||
4211 | case 6: /* Vector Negate Word */ | |
4212 | case 7: /* Vector Negate Doubleword */ | |
4213 | case 8: /* Vector Parity Byte Word */ | |
4214 | case 9: /* Vector Parity Byte Doubleword */ | |
4215 | case 10: /* Vector Parity Byte Quadword */ | |
4216 | case 16: /* Vector Extend Sign Byte To Word */ | |
4217 | case 17: /* Vector Extend Sign Halfword To Word */ | |
4218 | case 24: /* Vector Extend Sign Byte To Doubleword */ | |
4219 | case 25: /* Vector Extend Sign Halfword To Doubleword */ | |
4220 | case 26: /* Vector Extend Sign Word To Doubleword */ | |
4221 | case 28: /* Vector Count Trailing Zeros Byte */ | |
4222 | case 29: /* Vector Count Trailing Zeros Halfword */ | |
4223 | case 30: /* Vector Count Trailing Zeros Word */ | |
4224 | case 31: /* Vector Count Trailing Zeros Doubleword */ | |
4225 | record_full_arch_list_add_reg (regcache, | |
4226 | tdep->ppc_vr0_regnum + PPC_VRT (insn)); | |
4227 | return 0; | |
4228 | } | |
4229 | } | |
4230 | ||
b4cdae6f WW |
4231 | switch (ext) |
4232 | { | |
4233 | case 142: /* Vector Pack Unsigned Halfword Unsigned Saturate */ | |
4234 | case 206: /* Vector Pack Unsigned Word Unsigned Saturate */ | |
4235 | case 270: /* Vector Pack Signed Halfword Unsigned Saturate */ | |
4236 | case 334: /* Vector Pack Signed Word Unsigned Saturate */ | |
4237 | case 398: /* Vector Pack Signed Halfword Signed Saturate */ | |
4238 | case 462: /* Vector Pack Signed Word Signed Saturate */ | |
4239 | case 1230: /* Vector Pack Unsigned Doubleword Unsigned Saturate */ | |
4240 | case 1358: /* Vector Pack Signed Doubleword Unsigned Saturate */ | |
4241 | case 1486: /* Vector Pack Signed Doubleword Signed Saturate */ | |
4242 | case 512: /* Vector Add Unsigned Byte Saturate */ | |
4243 | case 576: /* Vector Add Unsigned Halfword Saturate */ | |
4244 | case 640: /* Vector Add Unsigned Word Saturate */ | |
4245 | case 768: /* Vector Add Signed Byte Saturate */ | |
4246 | case 832: /* Vector Add Signed Halfword Saturate */ | |
4247 | case 896: /* Vector Add Signed Word Saturate */ | |
4248 | case 1536: /* Vector Subtract Unsigned Byte Saturate */ | |
4249 | case 1600: /* Vector Subtract Unsigned Halfword Saturate */ | |
4250 | case 1664: /* Vector Subtract Unsigned Word Saturate */ | |
4251 | case 1792: /* Vector Subtract Signed Byte Saturate */ | |
4252 | case 1856: /* Vector Subtract Signed Halfword Saturate */ | |
4253 | case 1920: /* Vector Subtract Signed Word Saturate */ | |
4254 | ||
4255 | case 1544: /* Vector Sum across Quarter Unsigned Byte Saturate */ | |
4256 | case 1800: /* Vector Sum across Quarter Signed Byte Saturate */ | |
4257 | case 1608: /* Vector Sum across Quarter Signed Halfword Saturate */ | |
4258 | case 1672: /* Vector Sum across Half Signed Word Saturate */ | |
4259 | case 1928: /* Vector Sum across Signed Word Saturate */ | |
4260 | case 970: /* Vector Convert To Signed Fixed-Point Word Saturate */ | |
4261 | case 906: /* Vector Convert To Unsigned Fixed-Point Word Saturate */ | |
4262 | record_full_arch_list_add_reg (regcache, PPC_VSCR_REGNUM); | |
4263 | /* FALL-THROUGH */ | |
4264 | case 12: /* Vector Merge High Byte */ | |
4265 | case 14: /* Vector Pack Unsigned Halfword Unsigned Modulo */ | |
4266 | case 76: /* Vector Merge High Halfword */ | |
4267 | case 78: /* Vector Pack Unsigned Word Unsigned Modulo */ | |
4268 | case 140: /* Vector Merge High Word */ | |
4269 | case 268: /* Vector Merge Low Byte */ | |
4270 | case 332: /* Vector Merge Low Halfword */ | |
4271 | case 396: /* Vector Merge Low Word */ | |
4272 | case 526: /* Vector Unpack High Signed Byte */ | |
4273 | case 590: /* Vector Unpack High Signed Halfword */ | |
4274 | case 654: /* Vector Unpack Low Signed Byte */ | |
4275 | case 718: /* Vector Unpack Low Signed Halfword */ | |
4276 | case 782: /* Vector Pack Pixel */ | |
4277 | case 846: /* Vector Unpack High Pixel */ | |
4278 | case 974: /* Vector Unpack Low Pixel */ | |
4279 | case 1102: /* Vector Pack Unsigned Doubleword Unsigned Modulo */ | |
4280 | case 1614: /* Vector Unpack High Signed Word */ | |
4281 | case 1676: /* Vector Merge Odd Word */ | |
4282 | case 1742: /* Vector Unpack Low Signed Word */ | |
4283 | case 1932: /* Vector Merge Even Word */ | |
4284 | case 524: /* Vector Splat Byte */ | |
4285 | case 588: /* Vector Splat Halfword */ | |
4286 | case 652: /* Vector Splat Word */ | |
4287 | case 780: /* Vector Splat Immediate Signed Byte */ | |
4288 | case 844: /* Vector Splat Immediate Signed Halfword */ | |
4289 | case 908: /* Vector Splat Immediate Signed Word */ | |
4290 | case 452: /* Vector Shift Left */ | |
4291 | case 708: /* Vector Shift Right */ | |
4292 | case 1036: /* Vector Shift Left by Octet */ | |
4293 | case 1100: /* Vector Shift Right by Octet */ | |
4294 | case 0: /* Vector Add Unsigned Byte Modulo */ | |
4295 | case 64: /* Vector Add Unsigned Halfword Modulo */ | |
4296 | case 128: /* Vector Add Unsigned Word Modulo */ | |
4297 | case 192: /* Vector Add Unsigned Doubleword Modulo */ | |
4298 | case 256: /* Vector Add Unsigned Quadword Modulo */ | |
4299 | case 320: /* Vector Add & write Carry Unsigned Quadword */ | |
4300 | case 384: /* Vector Add and Write Carry-Out Unsigned Word */ | |
4301 | case 8: /* Vector Multiply Odd Unsigned Byte */ | |
4302 | case 72: /* Vector Multiply Odd Unsigned Halfword */ | |
4303 | case 136: /* Vector Multiply Odd Unsigned Word */ | |
4304 | case 264: /* Vector Multiply Odd Signed Byte */ | |
4305 | case 328: /* Vector Multiply Odd Signed Halfword */ | |
4306 | case 392: /* Vector Multiply Odd Signed Word */ | |
4307 | case 520: /* Vector Multiply Even Unsigned Byte */ | |
4308 | case 584: /* Vector Multiply Even Unsigned Halfword */ | |
4309 | case 648: /* Vector Multiply Even Unsigned Word */ | |
4310 | case 776: /* Vector Multiply Even Signed Byte */ | |
4311 | case 840: /* Vector Multiply Even Signed Halfword */ | |
4312 | case 904: /* Vector Multiply Even Signed Word */ | |
4313 | case 137: /* Vector Multiply Unsigned Word Modulo */ | |
4314 | case 1024: /* Vector Subtract Unsigned Byte Modulo */ | |
4315 | case 1088: /* Vector Subtract Unsigned Halfword Modulo */ | |
4316 | case 1152: /* Vector Subtract Unsigned Word Modulo */ | |
4317 | case 1216: /* Vector Subtract Unsigned Doubleword Modulo */ | |
4318 | case 1280: /* Vector Subtract Unsigned Quadword Modulo */ | |
4319 | case 1344: /* Vector Subtract & write Carry Unsigned Quadword */ | |
4320 | case 1408: /* Vector Subtract and Write Carry-Out Unsigned Word */ | |
4321 | case 1282: /* Vector Average Signed Byte */ | |
4322 | case 1346: /* Vector Average Signed Halfword */ | |
4323 | case 1410: /* Vector Average Signed Word */ | |
4324 | case 1026: /* Vector Average Unsigned Byte */ | |
4325 | case 1090: /* Vector Average Unsigned Halfword */ | |
4326 | case 1154: /* Vector Average Unsigned Word */ | |
4327 | case 258: /* Vector Maximum Signed Byte */ | |
4328 | case 322: /* Vector Maximum Signed Halfword */ | |
4329 | case 386: /* Vector Maximum Signed Word */ | |
4330 | case 450: /* Vector Maximum Signed Doubleword */ | |
4331 | case 2: /* Vector Maximum Unsigned Byte */ | |
4332 | case 66: /* Vector Maximum Unsigned Halfword */ | |
4333 | case 130: /* Vector Maximum Unsigned Word */ | |
4334 | case 194: /* Vector Maximum Unsigned Doubleword */ | |
4335 | case 770: /* Vector Minimum Signed Byte */ | |
4336 | case 834: /* Vector Minimum Signed Halfword */ | |
4337 | case 898: /* Vector Minimum Signed Word */ | |
4338 | case 962: /* Vector Minimum Signed Doubleword */ | |
4339 | case 514: /* Vector Minimum Unsigned Byte */ | |
4340 | case 578: /* Vector Minimum Unsigned Halfword */ | |
4341 | case 642: /* Vector Minimum Unsigned Word */ | |
4342 | case 706: /* Vector Minimum Unsigned Doubleword */ | |
4343 | case 1028: /* Vector Logical AND */ | |
4344 | case 1668: /* Vector Logical Equivalent */ | |
4345 | case 1092: /* Vector Logical AND with Complement */ | |
4346 | case 1412: /* Vector Logical NAND */ | |
4347 | case 1348: /* Vector Logical OR with Complement */ | |
4348 | case 1156: /* Vector Logical OR */ | |
4349 | case 1284: /* Vector Logical NOR */ | |
4350 | case 1220: /* Vector Logical XOR */ | |
4351 | case 4: /* Vector Rotate Left Byte */ | |
4352 | case 132: /* Vector Rotate Left Word VX-form */ | |
4353 | case 68: /* Vector Rotate Left Halfword */ | |
4354 | case 196: /* Vector Rotate Left Doubleword */ | |
4355 | case 260: /* Vector Shift Left Byte */ | |
4356 | case 388: /* Vector Shift Left Word */ | |
4357 | case 324: /* Vector Shift Left Halfword */ | |
4358 | case 1476: /* Vector Shift Left Doubleword */ | |
4359 | case 516: /* Vector Shift Right Byte */ | |
4360 | case 644: /* Vector Shift Right Word */ | |
4361 | case 580: /* Vector Shift Right Halfword */ | |
4362 | case 1732: /* Vector Shift Right Doubleword */ | |
4363 | case 772: /* Vector Shift Right Algebraic Byte */ | |
4364 | case 900: /* Vector Shift Right Algebraic Word */ | |
4365 | case 836: /* Vector Shift Right Algebraic Halfword */ | |
4366 | case 964: /* Vector Shift Right Algebraic Doubleword */ | |
4367 | case 10: /* Vector Add Single-Precision */ | |
4368 | case 74: /* Vector Subtract Single-Precision */ | |
4369 | case 1034: /* Vector Maximum Single-Precision */ | |
4370 | case 1098: /* Vector Minimum Single-Precision */ | |
4371 | case 842: /* Vector Convert From Signed Fixed-Point Word */ | |
4372 | case 778: /* Vector Convert From Unsigned Fixed-Point Word */ | |
4373 | case 714: /* Vector Round to Single-Precision Integer toward -Infinity */ | |
4374 | case 522: /* Vector Round to Single-Precision Integer Nearest */ | |
4375 | case 650: /* Vector Round to Single-Precision Integer toward +Infinity */ | |
4376 | case 586: /* Vector Round to Single-Precision Integer toward Zero */ | |
4377 | case 394: /* Vector 2 Raised to the Exponent Estimate Floating-Point */ | |
4378 | case 458: /* Vector Log Base 2 Estimate Floating-Point */ | |
4379 | case 266: /* Vector Reciprocal Estimate Single-Precision */ | |
4380 | case 330: /* Vector Reciprocal Square Root Estimate Single-Precision */ | |
4381 | case 1288: /* Vector AES Cipher */ | |
4382 | case 1289: /* Vector AES Cipher Last */ | |
4383 | case 1352: /* Vector AES Inverse Cipher */ | |
4384 | case 1353: /* Vector AES Inverse Cipher Last */ | |
4385 | case 1480: /* Vector AES SubBytes */ | |
4386 | case 1730: /* Vector SHA-512 Sigma Doubleword */ | |
4387 | case 1666: /* Vector SHA-256 Sigma Word */ | |
4388 | case 1032: /* Vector Polynomial Multiply-Sum Byte */ | |
4389 | case 1160: /* Vector Polynomial Multiply-Sum Word */ | |
4390 | case 1096: /* Vector Polynomial Multiply-Sum Halfword */ | |
4391 | case 1224: /* Vector Polynomial Multiply-Sum Doubleword */ | |
4392 | case 1292: /* Vector Gather Bits by Bytes by Doubleword */ | |
4393 | case 1794: /* Vector Count Leading Zeros Byte */ | |
4394 | case 1858: /* Vector Count Leading Zeros Halfword */ | |
4395 | case 1922: /* Vector Count Leading Zeros Word */ | |
4396 | case 1986: /* Vector Count Leading Zeros Doubleword */ | |
4397 | case 1795: /* Vector Population Count Byte */ | |
4398 | case 1859: /* Vector Population Count Halfword */ | |
4399 | case 1923: /* Vector Population Count Word */ | |
4400 | case 1987: /* Vector Population Count Doubleword */ | |
4401 | case 1356: /* Vector Bit Permute Quadword */ | |
6ec2b213 EBM |
4402 | case 1484: /* Vector Bit Permute Doubleword */ |
4403 | case 513: /* Vector Multiply-by-10 Unsigned Quadword */ | |
4404 | case 1: /* Vector Multiply-by-10 & write Carry Unsigned | |
4405 | Quadword */ | |
4406 | case 577: /* Vector Multiply-by-10 Extended Unsigned Quadword */ | |
4407 | case 65: /* Vector Multiply-by-10 Extended & write Carry | |
4408 | Unsigned Quadword */ | |
4409 | case 1027: /* Vector Absolute Difference Unsigned Byte */ | |
4410 | case 1091: /* Vector Absolute Difference Unsigned Halfword */ | |
4411 | case 1155: /* Vector Absolute Difference Unsigned Word */ | |
4412 | case 1796: /* Vector Shift Right Variable */ | |
4413 | case 1860: /* Vector Shift Left Variable */ | |
4414 | case 133: /* Vector Rotate Left Word then Mask Insert */ | |
4415 | case 197: /* Vector Rotate Left Doubleword then Mask Insert */ | |
4416 | case 389: /* Vector Rotate Left Word then AND with Mask */ | |
4417 | case 453: /* Vector Rotate Left Doubleword then AND with Mask */ | |
4418 | case 525: /* Vector Extract Unsigned Byte */ | |
4419 | case 589: /* Vector Extract Unsigned Halfword */ | |
4420 | case 653: /* Vector Extract Unsigned Word */ | |
4421 | case 717: /* Vector Extract Doubleword */ | |
4422 | case 781: /* Vector Insert Byte */ | |
4423 | case 845: /* Vector Insert Halfword */ | |
4424 | case 909: /* Vector Insert Word */ | |
4425 | case 973: /* Vector Insert Doubleword */ | |
b4cdae6f WW |
4426 | record_full_arch_list_add_reg (regcache, |
4427 | tdep->ppc_vr0_regnum + PPC_VRT (insn)); | |
4428 | return 0; | |
4429 | ||
6ec2b213 EBM |
4430 | case 1549: /* Vector Extract Unsigned Byte Left-Indexed */ |
4431 | case 1613: /* Vector Extract Unsigned Halfword Left-Indexed */ | |
4432 | case 1677: /* Vector Extract Unsigned Word Left-Indexed */ | |
4433 | case 1805: /* Vector Extract Unsigned Byte Right-Indexed */ | |
4434 | case 1869: /* Vector Extract Unsigned Halfword Right-Indexed */ | |
4435 | case 1933: /* Vector Extract Unsigned Word Right-Indexed */ | |
4436 | record_full_arch_list_add_reg (regcache, | |
4437 | tdep->ppc_gp0_regnum + PPC_RT (insn)); | |
4438 | return 0; | |
4439 | ||
b4cdae6f WW |
4440 | case 1604: /* Move To Vector Status and Control Register */ |
4441 | record_full_arch_list_add_reg (regcache, PPC_VSCR_REGNUM); | |
4442 | return 0; | |
4443 | case 1540: /* Move From Vector Status and Control Register */ | |
4444 | record_full_arch_list_add_reg (regcache, | |
4445 | tdep->ppc_vr0_regnum + PPC_VRT (insn)); | |
4446 | return 0; | |
6ec2b213 EBM |
4447 | case 833: /* Decimal Copy Sign */ |
4448 | record_full_arch_list_add_reg (regcache, | |
4449 | tdep->ppc_vr0_regnum + PPC_VRT (insn)); | |
4450 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
4451 | return 0; | |
b4cdae6f WW |
4452 | } |
4453 | ||
810c1026 WW |
4454 | fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x " |
4455 | "at %s, 4-%d.\n", insn, paddress (gdbarch, addr), ext); | |
b4cdae6f WW |
4456 | return -1; |
4457 | } | |
4458 | ||
ddeca1df WW |
4459 | /* Parse and record instructions of primary opcode-19 at ADDR. |
4460 | Return 0 if successful. */ | |
b4cdae6f WW |
4461 | |
4462 | static int | |
4463 | ppc_process_record_op19 (struct gdbarch *gdbarch, struct regcache *regcache, | |
4464 | CORE_ADDR addr, uint32_t insn) | |
4465 | { | |
4466 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
4467 | int ext = PPC_EXTOP (insn); | |
4468 | ||
6ec2b213 EBM |
4469 | switch (ext & 0x01f) |
4470 | { | |
4471 | case 2: /* Add PC Immediate Shifted */ | |
4472 | record_full_arch_list_add_reg (regcache, | |
4473 | tdep->ppc_gp0_regnum + PPC_RT (insn)); | |
4474 | return 0; | |
4475 | } | |
4476 | ||
b4cdae6f WW |
4477 | switch (ext) |
4478 | { | |
4479 | case 0: /* Move Condition Register Field */ | |
4480 | case 33: /* Condition Register NOR */ | |
4481 | case 129: /* Condition Register AND with Complement */ | |
4482 | case 193: /* Condition Register XOR */ | |
4483 | case 225: /* Condition Register NAND */ | |
4484 | case 257: /* Condition Register AND */ | |
4485 | case 289: /* Condition Register Equivalent */ | |
4486 | case 417: /* Condition Register OR with Complement */ | |
4487 | case 449: /* Condition Register OR */ | |
4488 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
4489 | return 0; | |
4490 | ||
4491 | case 16: /* Branch Conditional */ | |
4492 | case 560: /* Branch Conditional to Branch Target Address Register */ | |
4493 | if ((PPC_BO (insn) & 0x4) == 0) | |
4494 | record_full_arch_list_add_reg (regcache, tdep->ppc_ctr_regnum); | |
4495 | /* FALL-THROUGH */ | |
4496 | case 528: /* Branch Conditional to Count Register */ | |
4497 | if (PPC_LK (insn)) | |
4498 | record_full_arch_list_add_reg (regcache, tdep->ppc_lr_regnum); | |
4499 | return 0; | |
4500 | ||
4501 | case 150: /* Instruction Synchronize */ | |
4502 | /* Do nothing. */ | |
4503 | return 0; | |
4504 | } | |
4505 | ||
810c1026 WW |
4506 | fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x " |
4507 | "at %s, 19-%d.\n", insn, paddress (gdbarch, addr), ext); | |
b4cdae6f WW |
4508 | return -1; |
4509 | } | |
4510 | ||
ddeca1df WW |
4511 | /* Parse and record instructions of primary opcode-31 at ADDR. |
4512 | Return 0 if successful. */ | |
b4cdae6f WW |
4513 | |
4514 | static int | |
4515 | ppc_process_record_op31 (struct gdbarch *gdbarch, struct regcache *regcache, | |
4516 | CORE_ADDR addr, uint32_t insn) | |
4517 | { | |
4518 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
4519 | int ext = PPC_EXTOP (insn); | |
4520 | int tmp, nr, nb, i; | |
4521 | CORE_ADDR at_dcsz, ea = 0; | |
4522 | ULONGEST rb, ra, xer; | |
4523 | int size = 0; | |
4524 | ||
4525 | /* These instructions have OE bit. */ | |
4526 | switch (ext & 0x1ff) | |
4527 | { | |
4528 | /* These write RT and XER. Update CR if RC is set. */ | |
4529 | case 8: /* Subtract from carrying */ | |
4530 | case 10: /* Add carrying */ | |
4531 | case 136: /* Subtract from extended */ | |
4532 | case 138: /* Add extended */ | |
4533 | case 200: /* Subtract from zero extended */ | |
4534 | case 202: /* Add to zero extended */ | |
4535 | case 232: /* Subtract from minus one extended */ | |
4536 | case 234: /* Add to minus one extended */ | |
4537 | /* CA is always altered, but SO/OV are only altered when OE=1. | |
4538 | In any case, XER is always altered. */ | |
4539 | record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum); | |
4540 | if (PPC_RC (insn)) | |
4541 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
4542 | record_full_arch_list_add_reg (regcache, | |
4543 | tdep->ppc_gp0_regnum + PPC_RT (insn)); | |
4544 | return 0; | |
4545 | ||
4546 | /* These write RT. Update CR if RC is set and update XER if OE is set. */ | |
4547 | case 40: /* Subtract from */ | |
4548 | case 104: /* Negate */ | |
4549 | case 233: /* Multiply low doubleword */ | |
4550 | case 235: /* Multiply low word */ | |
4551 | case 266: /* Add */ | |
4552 | case 393: /* Divide Doubleword Extended Unsigned */ | |
4553 | case 395: /* Divide Word Extended Unsigned */ | |
4554 | case 425: /* Divide Doubleword Extended */ | |
4555 | case 427: /* Divide Word Extended */ | |
4556 | case 457: /* Divide Doubleword Unsigned */ | |
4557 | case 459: /* Divide Word Unsigned */ | |
4558 | case 489: /* Divide Doubleword */ | |
4559 | case 491: /* Divide Word */ | |
4560 | if (PPC_OE (insn)) | |
4561 | record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum); | |
4562 | /* FALL-THROUGH */ | |
4563 | case 9: /* Multiply High Doubleword Unsigned */ | |
4564 | case 11: /* Multiply High Word Unsigned */ | |
4565 | case 73: /* Multiply High Doubleword */ | |
4566 | case 75: /* Multiply High Word */ | |
4567 | if (PPC_RC (insn)) | |
4568 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
4569 | record_full_arch_list_add_reg (regcache, | |
4570 | tdep->ppc_gp0_regnum + PPC_RT (insn)); | |
4571 | return 0; | |
4572 | } | |
4573 | ||
4574 | if ((ext & 0x1f) == 15) | |
4575 | { | |
4576 | /* Integer Select. bit[16:20] is used for BC. */ | |
4577 | record_full_arch_list_add_reg (regcache, | |
4578 | tdep->ppc_gp0_regnum + PPC_RT (insn)); | |
4579 | return 0; | |
4580 | } | |
4581 | ||
6ec2b213 EBM |
4582 | if ((ext & 0xff) == 170) |
4583 | { | |
4584 | /* Add Extended using alternate carry bits */ | |
4585 | record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum); | |
4586 | record_full_arch_list_add_reg (regcache, | |
4587 | tdep->ppc_gp0_regnum + PPC_RT (insn)); | |
4588 | return 0; | |
4589 | } | |
4590 | ||
b4cdae6f WW |
4591 | switch (ext) |
4592 | { | |
4593 | case 78: /* Determine Leftmost Zero Byte */ | |
4594 | if (PPC_RC (insn)) | |
4595 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
4596 | record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum); | |
4597 | record_full_arch_list_add_reg (regcache, | |
4598 | tdep->ppc_gp0_regnum + PPC_RT (insn)); | |
4599 | return 0; | |
4600 | ||
4601 | /* These only write RT. */ | |
4602 | case 19: /* Move from condition register */ | |
4603 | /* Move From One Condition Register Field */ | |
4604 | case 74: /* Add and Generate Sixes */ | |
4605 | case 74 | 0x200: /* Add and Generate Sixes (bit-21 dont-care) */ | |
4606 | case 302: /* Move From Branch History Rolling Buffer */ | |
4607 | case 339: /* Move From Special Purpose Register */ | |
4608 | case 371: /* Move From Time Base [Phased-Out] */ | |
6ec2b213 EBM |
4609 | case 309: /* Load Doubleword Monitored Indexed */ |
4610 | case 128: /* Set Boolean */ | |
4611 | case 755: /* Deliver A Random Number */ | |
b4cdae6f WW |
4612 | record_full_arch_list_add_reg (regcache, |
4613 | tdep->ppc_gp0_regnum + PPC_RT (insn)); | |
4614 | return 0; | |
4615 | ||
4616 | /* These only write to RA. */ | |
4617 | case 51: /* Move From VSR Doubleword */ | |
4618 | case 115: /* Move From VSR Word and Zero */ | |
4619 | case 122: /* Population count bytes */ | |
4620 | case 378: /* Population count words */ | |
4621 | case 506: /* Population count doublewords */ | |
4622 | case 154: /* Parity Word */ | |
4623 | case 186: /* Parity Doubleword */ | |
4624 | case 252: /* Bit Permute Doubleword */ | |
4625 | case 282: /* Convert Declets To Binary Coded Decimal */ | |
4626 | case 314: /* Convert Binary Coded Decimal To Declets */ | |
4627 | case 508: /* Compare bytes */ | |
6ec2b213 | 4628 | case 307: /* Move From VSR Lower Doubleword */ |
b4cdae6f WW |
4629 | record_full_arch_list_add_reg (regcache, |
4630 | tdep->ppc_gp0_regnum + PPC_RA (insn)); | |
4631 | return 0; | |
4632 | ||
4633 | /* These write CR and optional RA. */ | |
4634 | case 792: /* Shift Right Algebraic Word */ | |
4635 | case 794: /* Shift Right Algebraic Doubleword */ | |
4636 | case 824: /* Shift Right Algebraic Word Immediate */ | |
4637 | case 826: /* Shift Right Algebraic Doubleword Immediate (413) */ | |
4638 | case 826 | 1: /* Shift Right Algebraic Doubleword Immediate (413) */ | |
4639 | record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum); | |
4640 | record_full_arch_list_add_reg (regcache, | |
4641 | tdep->ppc_gp0_regnum + PPC_RA (insn)); | |
4642 | /* FALL-THROUGH */ | |
4643 | case 0: /* Compare */ | |
4644 | case 32: /* Compare logical */ | |
4645 | case 144: /* Move To Condition Register Fields */ | |
4646 | /* Move To One Condition Register Field */ | |
6ec2b213 EBM |
4647 | case 192: /* Compare Ranged Byte */ |
4648 | case 224: /* Compare Equal Byte */ | |
4649 | case 576: /* Move XER to CR Extended */ | |
4650 | case 902: /* Paste (should always fail due to single-stepping and | |
4651 | the memory location might not be accessible, so | |
4652 | record only CR) */ | |
b4cdae6f WW |
4653 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); |
4654 | return 0; | |
4655 | ||
4656 | /* These write to RT. Update RA if 'update indexed.' */ | |
4657 | case 53: /* Load Doubleword with Update Indexed */ | |
4658 | case 119: /* Load Byte and Zero with Update Indexed */ | |
4659 | case 311: /* Load Halfword and Zero with Update Indexed */ | |
4660 | case 55: /* Load Word and Zero with Update Indexed */ | |
4661 | case 375: /* Load Halfword Algebraic with Update Indexed */ | |
4662 | case 373: /* Load Word Algebraic with Update Indexed */ | |
4663 | record_full_arch_list_add_reg (regcache, | |
4664 | tdep->ppc_gp0_regnum + PPC_RA (insn)); | |
4665 | /* FALL-THROUGH */ | |
4666 | case 21: /* Load Doubleword Indexed */ | |
4667 | case 52: /* Load Byte And Reserve Indexed */ | |
4668 | case 116: /* Load Halfword And Reserve Indexed */ | |
4669 | case 20: /* Load Word And Reserve Indexed */ | |
4670 | case 84: /* Load Doubleword And Reserve Indexed */ | |
4671 | case 87: /* Load Byte and Zero Indexed */ | |
4672 | case 279: /* Load Halfword and Zero Indexed */ | |
4673 | case 23: /* Load Word and Zero Indexed */ | |
4674 | case 343: /* Load Halfword Algebraic Indexed */ | |
4675 | case 341: /* Load Word Algebraic Indexed */ | |
4676 | case 790: /* Load Halfword Byte-Reverse Indexed */ | |
4677 | case 534: /* Load Word Byte-Reverse Indexed */ | |
4678 | case 532: /* Load Doubleword Byte-Reverse Indexed */ | |
6ec2b213 EBM |
4679 | case 582: /* Load Word Atomic */ |
4680 | case 614: /* Load Doubleword Atomic */ | |
4681 | case 265: /* Modulo Unsigned Doubleword */ | |
4682 | case 777: /* Modulo Signed Doubleword */ | |
4683 | case 267: /* Modulo Unsigned Word */ | |
4684 | case 779: /* Modulo Signed Word */ | |
b4cdae6f WW |
4685 | record_full_arch_list_add_reg (regcache, |
4686 | tdep->ppc_gp0_regnum + PPC_RT (insn)); | |
4687 | return 0; | |
4688 | ||
4689 | case 597: /* Load String Word Immediate */ | |
4690 | case 533: /* Load String Word Indexed */ | |
4691 | if (ext == 597) | |
4692 | { | |
4693 | nr = PPC_NB (insn); | |
4694 | if (nr == 0) | |
4695 | nr = 32; | |
4696 | } | |
4697 | else | |
4698 | { | |
4699 | regcache_raw_read_unsigned (regcache, tdep->ppc_xer_regnum, &xer); | |
4700 | nr = PPC_XER_NB (xer); | |
4701 | } | |
4702 | ||
4703 | nr = (nr + 3) >> 2; | |
4704 | ||
4705 | /* If n=0, the contents of register RT are undefined. */ | |
4706 | if (nr == 0) | |
4707 | nr = 1; | |
4708 | ||
4709 | for (i = 0; i < nr; i++) | |
4710 | record_full_arch_list_add_reg (regcache, | |
4711 | tdep->ppc_gp0_regnum | |
4712 | + ((PPC_RT (insn) + i) & 0x1f)); | |
4713 | return 0; | |
4714 | ||
4715 | case 276: /* Load Quadword And Reserve Indexed */ | |
4716 | tmp = tdep->ppc_gp0_regnum + (PPC_RT (insn) & ~1); | |
4717 | record_full_arch_list_add_reg (regcache, tmp); | |
4718 | record_full_arch_list_add_reg (regcache, tmp + 1); | |
4719 | return 0; | |
4720 | ||
4721 | /* These write VRT. */ | |
4722 | case 6: /* Load Vector for Shift Left Indexed */ | |
4723 | case 38: /* Load Vector for Shift Right Indexed */ | |
4724 | case 7: /* Load Vector Element Byte Indexed */ | |
4725 | case 39: /* Load Vector Element Halfword Indexed */ | |
4726 | case 71: /* Load Vector Element Word Indexed */ | |
4727 | case 103: /* Load Vector Indexed */ | |
4728 | case 359: /* Load Vector Indexed LRU */ | |
4729 | record_full_arch_list_add_reg (regcache, | |
4730 | tdep->ppc_vr0_regnum + PPC_VRT (insn)); | |
4731 | return 0; | |
4732 | ||
4733 | /* These write FRT. Update RA if 'update indexed.' */ | |
4734 | case 567: /* Load Floating-Point Single with Update Indexed */ | |
4735 | case 631: /* Load Floating-Point Double with Update Indexed */ | |
4736 | record_full_arch_list_add_reg (regcache, | |
4737 | tdep->ppc_gp0_regnum + PPC_RA (insn)); | |
4738 | /* FALL-THROUGH */ | |
4739 | case 535: /* Load Floating-Point Single Indexed */ | |
4740 | case 599: /* Load Floating-Point Double Indexed */ | |
4741 | case 855: /* Load Floating-Point as Integer Word Algebraic Indexed */ | |
4742 | case 887: /* Load Floating-Point as Integer Word and Zero Indexed */ | |
4743 | record_full_arch_list_add_reg (regcache, | |
4744 | tdep->ppc_fp0_regnum + PPC_FRT (insn)); | |
4745 | return 0; | |
4746 | ||
4747 | case 791: /* Load Floating-Point Double Pair Indexed */ | |
4748 | tmp = tdep->ppc_fp0_regnum + (PPC_FRT (insn) & ~1); | |
4749 | record_full_arch_list_add_reg (regcache, tmp); | |
4750 | record_full_arch_list_add_reg (regcache, tmp + 1); | |
4751 | return 0; | |
4752 | ||
4753 | case 179: /* Move To VSR Doubleword */ | |
4754 | case 211: /* Move To VSR Word Algebraic */ | |
4755 | case 243: /* Move To VSR Word and Zero */ | |
4756 | case 588: /* Load VSX Scalar Doubleword Indexed */ | |
4757 | case 524: /* Load VSX Scalar Single-Precision Indexed */ | |
4758 | case 76: /* Load VSX Scalar as Integer Word Algebraic Indexed */ | |
4759 | case 12: /* Load VSX Scalar as Integer Word and Zero Indexed */ | |
4760 | case 844: /* Load VSX Vector Doubleword*2 Indexed */ | |
4761 | case 332: /* Load VSX Vector Doubleword & Splat Indexed */ | |
4762 | case 780: /* Load VSX Vector Word*4 Indexed */ | |
6ec2b213 EBM |
4763 | case 268: /* Load VSX Vector Indexed */ |
4764 | case 364: /* Load VSX Vector Word & Splat Indexed */ | |
4765 | case 812: /* Load VSX Vector Halfword*8 Indexed */ | |
4766 | case 876: /* Load VSX Vector Byte*16 Indexed */ | |
4767 | case 269: /* Load VSX Vector with Length */ | |
4768 | case 301: /* Load VSX Vector Left-justified with Length */ | |
4769 | case 781: /* Load VSX Scalar as Integer Byte & Zero Indexed */ | |
4770 | case 813: /* Load VSX Scalar as Integer Halfword & Zero Indexed */ | |
4771 | case 403: /* Move To VSR Word & Splat */ | |
4772 | case 435: /* Move To VSR Double Doubleword */ | |
b4cdae6f WW |
4773 | ppc_record_vsr (regcache, tdep, PPC_XT (insn)); |
4774 | return 0; | |
4775 | ||
4776 | /* These write RA. Update CR if RC is set. */ | |
4777 | case 24: /* Shift Left Word */ | |
4778 | case 26: /* Count Leading Zeros Word */ | |
4779 | case 27: /* Shift Left Doubleword */ | |
4780 | case 28: /* AND */ | |
4781 | case 58: /* Count Leading Zeros Doubleword */ | |
4782 | case 60: /* AND with Complement */ | |
4783 | case 124: /* NOR */ | |
4784 | case 284: /* Equivalent */ | |
4785 | case 316: /* XOR */ | |
4786 | case 476: /* NAND */ | |
4787 | case 412: /* OR with Complement */ | |
4788 | case 444: /* OR */ | |
4789 | case 536: /* Shift Right Word */ | |
4790 | case 539: /* Shift Right Doubleword */ | |
4791 | case 922: /* Extend Sign Halfword */ | |
4792 | case 954: /* Extend Sign Byte */ | |
4793 | case 986: /* Extend Sign Word */ | |
6ec2b213 EBM |
4794 | case 538: /* Count Trailing Zeros Word */ |
4795 | case 570: /* Count Trailing Zeros Doubleword */ | |
4796 | case 890: /* Extend-Sign Word and Shift Left Immediate (445) */ | |
4797 | case 890 | 1: /* Extend-Sign Word and Shift Left Immediate (445) */ | |
7ca18ed6 EBM |
4798 | |
4799 | if (ext == 444 && tdep->ppc_ppr_regnum >= 0 | |
4800 | && (PPC_RS (insn) == PPC_RA (insn)) | |
4801 | && (PPC_RA (insn) == PPC_RB (insn)) | |
4802 | && !PPC_RC (insn)) | |
4803 | { | |
4804 | /* or Rx,Rx,Rx alters PRI in PPR. */ | |
4805 | record_full_arch_list_add_reg (regcache, tdep->ppc_ppr_regnum); | |
4806 | return 0; | |
4807 | } | |
4808 | ||
b4cdae6f WW |
4809 | if (PPC_RC (insn)) |
4810 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
4811 | record_full_arch_list_add_reg (regcache, | |
4812 | tdep->ppc_gp0_regnum + PPC_RA (insn)); | |
4813 | return 0; | |
4814 | ||
4815 | /* Store memory. */ | |
4816 | case 181: /* Store Doubleword with Update Indexed */ | |
4817 | case 183: /* Store Word with Update Indexed */ | |
4818 | case 247: /* Store Byte with Update Indexed */ | |
4819 | case 439: /* Store Half Word with Update Indexed */ | |
4820 | case 695: /* Store Floating-Point Single with Update Indexed */ | |
4821 | case 759: /* Store Floating-Point Double with Update Indexed */ | |
4822 | record_full_arch_list_add_reg (regcache, | |
4823 | tdep->ppc_gp0_regnum + PPC_RA (insn)); | |
4824 | /* FALL-THROUGH */ | |
4825 | case 135: /* Store Vector Element Byte Indexed */ | |
4826 | case 167: /* Store Vector Element Halfword Indexed */ | |
4827 | case 199: /* Store Vector Element Word Indexed */ | |
4828 | case 231: /* Store Vector Indexed */ | |
4829 | case 487: /* Store Vector Indexed LRU */ | |
4830 | case 716: /* Store VSX Scalar Doubleword Indexed */ | |
4831 | case 140: /* Store VSX Scalar as Integer Word Indexed */ | |
4832 | case 652: /* Store VSX Scalar Single-Precision Indexed */ | |
4833 | case 972: /* Store VSX Vector Doubleword*2 Indexed */ | |
4834 | case 908: /* Store VSX Vector Word*4 Indexed */ | |
4835 | case 149: /* Store Doubleword Indexed */ | |
4836 | case 151: /* Store Word Indexed */ | |
4837 | case 215: /* Store Byte Indexed */ | |
4838 | case 407: /* Store Half Word Indexed */ | |
4839 | case 694: /* Store Byte Conditional Indexed */ | |
4840 | case 726: /* Store Halfword Conditional Indexed */ | |
4841 | case 150: /* Store Word Conditional Indexed */ | |
4842 | case 214: /* Store Doubleword Conditional Indexed */ | |
4843 | case 182: /* Store Quadword Conditional Indexed */ | |
4844 | case 662: /* Store Word Byte-Reverse Indexed */ | |
4845 | case 918: /* Store Halfword Byte-Reverse Indexed */ | |
4846 | case 660: /* Store Doubleword Byte-Reverse Indexed */ | |
4847 | case 663: /* Store Floating-Point Single Indexed */ | |
4848 | case 727: /* Store Floating-Point Double Indexed */ | |
4849 | case 919: /* Store Floating-Point Double Pair Indexed */ | |
4850 | case 983: /* Store Floating-Point as Integer Word Indexed */ | |
6ec2b213 EBM |
4851 | case 396: /* Store VSX Vector Indexed */ |
4852 | case 940: /* Store VSX Vector Halfword*8 Indexed */ | |
4853 | case 1004: /* Store VSX Vector Byte*16 Indexed */ | |
4854 | case 909: /* Store VSX Scalar as Integer Byte Indexed */ | |
4855 | case 941: /* Store VSX Scalar as Integer Halfword Indexed */ | |
b4cdae6f WW |
4856 | if (ext == 694 || ext == 726 || ext == 150 || ext == 214 || ext == 182) |
4857 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
4858 | ||
4859 | ra = 0; | |
4860 | if (PPC_RA (insn) != 0) | |
4861 | regcache_raw_read_unsigned (regcache, | |
4862 | tdep->ppc_gp0_regnum + PPC_RA (insn), &ra); | |
4863 | regcache_raw_read_unsigned (regcache, | |
4864 | tdep->ppc_gp0_regnum + PPC_RB (insn), &rb); | |
4865 | ea = ra + rb; | |
4866 | ||
4867 | switch (ext) | |
4868 | { | |
4869 | case 183: /* Store Word with Update Indexed */ | |
4870 | case 199: /* Store Vector Element Word Indexed */ | |
4871 | case 140: /* Store VSX Scalar as Integer Word Indexed */ | |
4872 | case 652: /* Store VSX Scalar Single-Precision Indexed */ | |
4873 | case 151: /* Store Word Indexed */ | |
4874 | case 150: /* Store Word Conditional Indexed */ | |
4875 | case 662: /* Store Word Byte-Reverse Indexed */ | |
4876 | case 663: /* Store Floating-Point Single Indexed */ | |
4877 | case 695: /* Store Floating-Point Single with Update Indexed */ | |
4878 | case 983: /* Store Floating-Point as Integer Word Indexed */ | |
4879 | size = 4; | |
4880 | break; | |
4881 | case 247: /* Store Byte with Update Indexed */ | |
4882 | case 135: /* Store Vector Element Byte Indexed */ | |
4883 | case 215: /* Store Byte Indexed */ | |
4884 | case 694: /* Store Byte Conditional Indexed */ | |
6ec2b213 | 4885 | case 909: /* Store VSX Scalar as Integer Byte Indexed */ |
b4cdae6f WW |
4886 | size = 1; |
4887 | break; | |
4888 | case 439: /* Store Halfword with Update Indexed */ | |
4889 | case 167: /* Store Vector Element Halfword Indexed */ | |
4890 | case 407: /* Store Halfword Indexed */ | |
4891 | case 726: /* Store Halfword Conditional Indexed */ | |
4892 | case 918: /* Store Halfword Byte-Reverse Indexed */ | |
6ec2b213 | 4893 | case 941: /* Store VSX Scalar as Integer Halfword Indexed */ |
b4cdae6f WW |
4894 | size = 2; |
4895 | break; | |
4896 | case 181: /* Store Doubleword with Update Indexed */ | |
4897 | case 716: /* Store VSX Scalar Doubleword Indexed */ | |
4898 | case 149: /* Store Doubleword Indexed */ | |
4899 | case 214: /* Store Doubleword Conditional Indexed */ | |
4900 | case 660: /* Store Doubleword Byte-Reverse Indexed */ | |
4901 | case 727: /* Store Floating-Point Double Indexed */ | |
4902 | case 759: /* Store Floating-Point Double with Update Indexed */ | |
4903 | size = 8; | |
4904 | break; | |
4905 | case 972: /* Store VSX Vector Doubleword*2 Indexed */ | |
4906 | case 908: /* Store VSX Vector Word*4 Indexed */ | |
4907 | case 182: /* Store Quadword Conditional Indexed */ | |
4908 | case 231: /* Store Vector Indexed */ | |
4909 | case 487: /* Store Vector Indexed LRU */ | |
4910 | case 919: /* Store Floating-Point Double Pair Indexed */ | |
6ec2b213 EBM |
4911 | case 396: /* Store VSX Vector Indexed */ |
4912 | case 940: /* Store VSX Vector Halfword*8 Indexed */ | |
4913 | case 1004: /* Store VSX Vector Byte*16 Indexed */ | |
b4cdae6f WW |
4914 | size = 16; |
4915 | break; | |
4916 | default: | |
4917 | gdb_assert (0); | |
4918 | } | |
4919 | ||
4920 | /* Align address for Store Vector instructions. */ | |
4921 | switch (ext) | |
4922 | { | |
4923 | case 167: /* Store Vector Element Halfword Indexed */ | |
4924 | addr = addr & ~0x1ULL; | |
4925 | break; | |
4926 | ||
4927 | case 199: /* Store Vector Element Word Indexed */ | |
4928 | addr = addr & ~0x3ULL; | |
4929 | break; | |
4930 | ||
4931 | case 231: /* Store Vector Indexed */ | |
4932 | case 487: /* Store Vector Indexed LRU */ | |
4933 | addr = addr & ~0xfULL; | |
4934 | break; | |
4935 | } | |
4936 | ||
4937 | record_full_arch_list_add_mem (addr, size); | |
4938 | return 0; | |
4939 | ||
6ec2b213 EBM |
4940 | case 397: /* Store VSX Vector with Length */ |
4941 | case 429: /* Store VSX Vector Left-justified with Length */ | |
de678454 | 4942 | ra = 0; |
6ec2b213 EBM |
4943 | if (PPC_RA (insn) != 0) |
4944 | regcache_raw_read_unsigned (regcache, | |
de678454 EBM |
4945 | tdep->ppc_gp0_regnum + PPC_RA (insn), &ra); |
4946 | ea = ra; | |
6ec2b213 EBM |
4947 | regcache_raw_read_unsigned (regcache, |
4948 | tdep->ppc_gp0_regnum + PPC_RB (insn), &rb); | |
4949 | /* Store up to 16 bytes. */ | |
4950 | nb = (rb & 0xff) > 16 ? 16 : (rb & 0xff); | |
4951 | if (nb > 0) | |
4952 | record_full_arch_list_add_mem (ea, nb); | |
4953 | return 0; | |
4954 | ||
4955 | case 710: /* Store Word Atomic */ | |
4956 | case 742: /* Store Doubleword Atomic */ | |
de678454 | 4957 | ra = 0; |
6ec2b213 EBM |
4958 | if (PPC_RA (insn) != 0) |
4959 | regcache_raw_read_unsigned (regcache, | |
de678454 EBM |
4960 | tdep->ppc_gp0_regnum + PPC_RA (insn), &ra); |
4961 | ea = ra; | |
6ec2b213 EBM |
4962 | switch (ext) |
4963 | { | |
4964 | case 710: /* Store Word Atomic */ | |
4965 | size = 8; | |
4966 | break; | |
4967 | case 742: /* Store Doubleword Atomic */ | |
4968 | size = 16; | |
4969 | break; | |
4970 | default: | |
4971 | gdb_assert (0); | |
4972 | } | |
4973 | record_full_arch_list_add_mem (ea, size); | |
4974 | return 0; | |
4975 | ||
b4cdae6f WW |
4976 | case 725: /* Store String Word Immediate */ |
4977 | ra = 0; | |
4978 | if (PPC_RA (insn) != 0) | |
9f7efd5b EBM |
4979 | regcache_raw_read_unsigned (regcache, |
4980 | tdep->ppc_gp0_regnum + PPC_RA (insn), &ra); | |
b4cdae6f WW |
4981 | ea += ra; |
4982 | ||
4983 | nb = PPC_NB (insn); | |
4984 | if (nb == 0) | |
4985 | nb = 32; | |
4986 | ||
4987 | record_full_arch_list_add_mem (ea, nb); | |
4988 | ||
4989 | return 0; | |
4990 | ||
4991 | case 661: /* Store String Word Indexed */ | |
4992 | ra = 0; | |
4993 | if (PPC_RA (insn) != 0) | |
9f7efd5b EBM |
4994 | regcache_raw_read_unsigned (regcache, |
4995 | tdep->ppc_gp0_regnum + PPC_RA (insn), &ra); | |
b4cdae6f WW |
4996 | ea += ra; |
4997 | ||
4998 | regcache_raw_read_unsigned (regcache, tdep->ppc_xer_regnum, &xer); | |
4999 | nb = PPC_XER_NB (xer); | |
5000 | ||
5001 | if (nb != 0) | |
5002 | { | |
9f7efd5b EBM |
5003 | regcache_raw_read_unsigned (regcache, |
5004 | tdep->ppc_gp0_regnum + PPC_RB (insn), | |
5005 | &rb); | |
b4cdae6f WW |
5006 | ea += rb; |
5007 | record_full_arch_list_add_mem (ea, nb); | |
5008 | } | |
5009 | ||
5010 | return 0; | |
5011 | ||
5012 | case 467: /* Move To Special Purpose Register */ | |
5013 | switch (PPC_SPR (insn)) | |
5014 | { | |
5015 | case 1: /* XER */ | |
5016 | record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum); | |
5017 | return 0; | |
7ca18ed6 EBM |
5018 | case 3: /* DSCR */ |
5019 | if (tdep->ppc_dscr_regnum >= 0) | |
5020 | record_full_arch_list_add_reg (regcache, tdep->ppc_dscr_regnum); | |
5021 | return 0; | |
b4cdae6f WW |
5022 | case 8: /* LR */ |
5023 | record_full_arch_list_add_reg (regcache, tdep->ppc_lr_regnum); | |
5024 | return 0; | |
5025 | case 9: /* CTR */ | |
5026 | record_full_arch_list_add_reg (regcache, tdep->ppc_ctr_regnum); | |
5027 | return 0; | |
5028 | case 256: /* VRSAVE */ | |
5029 | record_full_arch_list_add_reg (regcache, tdep->ppc_vrsave_regnum); | |
5030 | return 0; | |
f2cf6173 EBM |
5031 | case 815: /* TAR */ |
5032 | if (tdep->ppc_tar_regnum >= 0) | |
5033 | record_full_arch_list_add_reg (regcache, tdep->ppc_tar_regnum); | |
5034 | return 0; | |
7ca18ed6 EBM |
5035 | case 896: |
5036 | case 898: /* PPR */ | |
5037 | if (tdep->ppc_ppr_regnum >= 0) | |
5038 | record_full_arch_list_add_reg (regcache, tdep->ppc_ppr_regnum); | |
5039 | return 0; | |
b4cdae6f WW |
5040 | } |
5041 | ||
5042 | goto UNKNOWN_OP; | |
5043 | ||
5044 | case 147: /* Move To Split Little Endian */ | |
5045 | record_full_arch_list_add_reg (regcache, tdep->ppc_ps_regnum); | |
5046 | return 0; | |
5047 | ||
5048 | case 512: /* Move to Condition Register from XER */ | |
5049 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
5050 | record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum); | |
5051 | return 0; | |
5052 | ||
5053 | case 4: /* Trap Word */ | |
5054 | case 68: /* Trap Doubleword */ | |
5055 | case 430: /* Clear BHRB */ | |
5056 | case 598: /* Synchronize */ | |
5057 | case 62: /* Wait for Interrupt */ | |
6ec2b213 | 5058 | case 30: /* Wait */ |
b4cdae6f WW |
5059 | case 22: /* Instruction Cache Block Touch */ |
5060 | case 854: /* Enforce In-order Execution of I/O */ | |
5061 | case 246: /* Data Cache Block Touch for Store */ | |
5062 | case 54: /* Data Cache Block Store */ | |
5063 | case 86: /* Data Cache Block Flush */ | |
5064 | case 278: /* Data Cache Block Touch */ | |
5065 | case 758: /* Data Cache Block Allocate */ | |
5066 | case 982: /* Instruction Cache Block Invalidate */ | |
6ec2b213 EBM |
5067 | case 774: /* Copy */ |
5068 | case 838: /* CP_Abort */ | |
b4cdae6f WW |
5069 | return 0; |
5070 | ||
5071 | case 654: /* Transaction Begin */ | |
5072 | case 686: /* Transaction End */ | |
b4cdae6f WW |
5073 | case 750: /* Transaction Suspend or Resume */ |
5074 | case 782: /* Transaction Abort Word Conditional */ | |
5075 | case 814: /* Transaction Abort Doubleword Conditional */ | |
5076 | case 846: /* Transaction Abort Word Conditional Immediate */ | |
5077 | case 878: /* Transaction Abort Doubleword Conditional Immediate */ | |
5078 | case 910: /* Transaction Abort */ | |
d44c67f3 EBM |
5079 | record_full_arch_list_add_reg (regcache, tdep->ppc_ps_regnum); |
5080 | /* FALL-THROUGH */ | |
5081 | case 718: /* Transaction Check */ | |
5082 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
5083 | return 0; | |
b4cdae6f WW |
5084 | |
5085 | case 1014: /* Data Cache Block set to Zero */ | |
328d42d8 SM |
5086 | if (target_auxv_search (current_inferior ()->top_target (), |
5087 | AT_DCACHEBSIZE, &at_dcsz) <= 0 | |
b4cdae6f WW |
5088 | || at_dcsz == 0) |
5089 | at_dcsz = 128; /* Assume 128-byte cache line size (POWER8) */ | |
5090 | ||
bec734b2 | 5091 | ra = 0; |
b4cdae6f WW |
5092 | if (PPC_RA (insn) != 0) |
5093 | regcache_raw_read_unsigned (regcache, | |
5094 | tdep->ppc_gp0_regnum + PPC_RA (insn), &ra); | |
5095 | regcache_raw_read_unsigned (regcache, | |
5096 | tdep->ppc_gp0_regnum + PPC_RB (insn), &rb); | |
5097 | ea = (ra + rb) & ~((ULONGEST) (at_dcsz - 1)); | |
5098 | record_full_arch_list_add_mem (ea, at_dcsz); | |
5099 | return 0; | |
5100 | } | |
5101 | ||
5102 | UNKNOWN_OP: | |
810c1026 WW |
5103 | fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x " |
5104 | "at %s, 31-%d.\n", insn, paddress (gdbarch, addr), ext); | |
b4cdae6f WW |
5105 | return -1; |
5106 | } | |
5107 | ||
ddeca1df WW |
5108 | /* Parse and record instructions of primary opcode-59 at ADDR. |
5109 | Return 0 if successful. */ | |
b4cdae6f WW |
5110 | |
5111 | static int | |
5112 | ppc_process_record_op59 (struct gdbarch *gdbarch, struct regcache *regcache, | |
5113 | CORE_ADDR addr, uint32_t insn) | |
5114 | { | |
5115 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
5116 | int ext = PPC_EXTOP (insn); | |
5117 | ||
5118 | switch (ext & 0x1f) | |
5119 | { | |
5120 | case 18: /* Floating Divide */ | |
5121 | case 20: /* Floating Subtract */ | |
5122 | case 21: /* Floating Add */ | |
5123 | case 22: /* Floating Square Root */ | |
5124 | case 24: /* Floating Reciprocal Estimate */ | |
5125 | case 25: /* Floating Multiply */ | |
5126 | case 26: /* Floating Reciprocal Square Root Estimate */ | |
5127 | case 28: /* Floating Multiply-Subtract */ | |
5128 | case 29: /* Floating Multiply-Add */ | |
5129 | case 30: /* Floating Negative Multiply-Subtract */ | |
5130 | case 31: /* Floating Negative Multiply-Add */ | |
5131 | record_full_arch_list_add_reg (regcache, | |
5132 | tdep->ppc_fp0_regnum + PPC_FRT (insn)); | |
5133 | if (PPC_RC (insn)) | |
5134 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
5135 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
5136 | ||
5137 | return 0; | |
5138 | } | |
5139 | ||
5140 | switch (ext) | |
5141 | { | |
5142 | case 2: /* DFP Add */ | |
5143 | case 3: /* DFP Quantize */ | |
5144 | case 34: /* DFP Multiply */ | |
5145 | case 35: /* DFP Reround */ | |
5146 | case 67: /* DFP Quantize Immediate */ | |
5147 | case 99: /* DFP Round To FP Integer With Inexact */ | |
5148 | case 227: /* DFP Round To FP Integer Without Inexact */ | |
5149 | case 258: /* DFP Convert To DFP Long! */ | |
5150 | case 290: /* DFP Convert To Fixed */ | |
5151 | case 514: /* DFP Subtract */ | |
5152 | case 546: /* DFP Divide */ | |
5153 | case 770: /* DFP Round To DFP Short! */ | |
5154 | case 802: /* DFP Convert From Fixed */ | |
5155 | case 834: /* DFP Encode BCD To DPD */ | |
5156 | if (PPC_RC (insn)) | |
5157 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
5158 | record_full_arch_list_add_reg (regcache, | |
5159 | tdep->ppc_fp0_regnum + PPC_FRT (insn)); | |
5160 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
5161 | return 0; | |
5162 | ||
5163 | case 130: /* DFP Compare Ordered */ | |
5164 | case 162: /* DFP Test Exponent */ | |
5165 | case 194: /* DFP Test Data Class */ | |
5166 | case 226: /* DFP Test Data Group */ | |
5167 | case 642: /* DFP Compare Unordered */ | |
5168 | case 674: /* DFP Test Significance */ | |
6ec2b213 | 5169 | case 675: /* DFP Test Significance Immediate */ |
b4cdae6f WW |
5170 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); |
5171 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
5172 | return 0; | |
5173 | ||
5174 | case 66: /* DFP Shift Significand Left Immediate */ | |
5175 | case 98: /* DFP Shift Significand Right Immediate */ | |
5176 | case 322: /* DFP Decode DPD To BCD */ | |
5177 | case 354: /* DFP Extract Biased Exponent */ | |
5178 | case 866: /* DFP Insert Biased Exponent */ | |
5179 | record_full_arch_list_add_reg (regcache, | |
5180 | tdep->ppc_fp0_regnum + PPC_FRT (insn)); | |
5181 | if (PPC_RC (insn)) | |
5182 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
5183 | return 0; | |
5184 | ||
5185 | case 846: /* Floating Convert From Integer Doubleword Single */ | |
5186 | case 974: /* Floating Convert From Integer Doubleword Unsigned | |
5187 | Single */ | |
5188 | record_full_arch_list_add_reg (regcache, | |
5189 | tdep->ppc_fp0_regnum + PPC_FRT (insn)); | |
5190 | if (PPC_RC (insn)) | |
5191 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
5192 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
5193 | ||
5194 | return 0; | |
5195 | } | |
5196 | ||
810c1026 WW |
5197 | fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x " |
5198 | "at %s, 59-%d.\n", insn, paddress (gdbarch, addr), ext); | |
b4cdae6f WW |
5199 | return -1; |
5200 | } | |
5201 | ||
ddeca1df WW |
5202 | /* Parse and record instructions of primary opcode-60 at ADDR. |
5203 | Return 0 if successful. */ | |
b4cdae6f WW |
5204 | |
5205 | static int | |
5206 | ppc_process_record_op60 (struct gdbarch *gdbarch, struct regcache *regcache, | |
5207 | CORE_ADDR addr, uint32_t insn) | |
5208 | { | |
5209 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
5210 | int ext = PPC_EXTOP (insn); | |
b4cdae6f WW |
5211 | |
5212 | switch (ext >> 2) | |
5213 | { | |
5214 | case 0: /* VSX Scalar Add Single-Precision */ | |
5215 | case 32: /* VSX Scalar Add Double-Precision */ | |
5216 | case 24: /* VSX Scalar Divide Single-Precision */ | |
5217 | case 56: /* VSX Scalar Divide Double-Precision */ | |
5218 | case 176: /* VSX Scalar Copy Sign Double-Precision */ | |
5219 | case 33: /* VSX Scalar Multiply-Add Double-Precision */ | |
5220 | case 41: /* ditto */ | |
5221 | case 1: /* VSX Scalar Multiply-Add Single-Precision */ | |
5222 | case 9: /* ditto */ | |
5223 | case 160: /* VSX Scalar Maximum Double-Precision */ | |
5224 | case 168: /* VSX Scalar Minimum Double-Precision */ | |
5225 | case 49: /* VSX Scalar Multiply-Subtract Double-Precision */ | |
5226 | case 57: /* ditto */ | |
5227 | case 17: /* VSX Scalar Multiply-Subtract Single-Precision */ | |
5228 | case 25: /* ditto */ | |
5229 | case 48: /* VSX Scalar Multiply Double-Precision */ | |
5230 | case 16: /* VSX Scalar Multiply Single-Precision */ | |
5231 | case 161: /* VSX Scalar Negative Multiply-Add Double-Precision */ | |
5232 | case 169: /* ditto */ | |
5233 | case 129: /* VSX Scalar Negative Multiply-Add Single-Precision */ | |
5234 | case 137: /* ditto */ | |
5235 | case 177: /* VSX Scalar Negative Multiply-Subtract Double-Precision */ | |
5236 | case 185: /* ditto */ | |
5237 | case 145: /* VSX Scalar Negative Multiply-Subtract Single-Precision */ | |
5238 | case 153: /* ditto */ | |
5239 | case 40: /* VSX Scalar Subtract Double-Precision */ | |
5240 | case 8: /* VSX Scalar Subtract Single-Precision */ | |
5241 | case 96: /* VSX Vector Add Double-Precision */ | |
5242 | case 64: /* VSX Vector Add Single-Precision */ | |
5243 | case 120: /* VSX Vector Divide Double-Precision */ | |
5244 | case 88: /* VSX Vector Divide Single-Precision */ | |
5245 | case 97: /* VSX Vector Multiply-Add Double-Precision */ | |
5246 | case 105: /* ditto */ | |
5247 | case 65: /* VSX Vector Multiply-Add Single-Precision */ | |
5248 | case 73: /* ditto */ | |
5249 | case 224: /* VSX Vector Maximum Double-Precision */ | |
5250 | case 192: /* VSX Vector Maximum Single-Precision */ | |
5251 | case 232: /* VSX Vector Minimum Double-Precision */ | |
5252 | case 200: /* VSX Vector Minimum Single-Precision */ | |
5253 | case 113: /* VSX Vector Multiply-Subtract Double-Precision */ | |
5254 | case 121: /* ditto */ | |
5255 | case 81: /* VSX Vector Multiply-Subtract Single-Precision */ | |
5256 | case 89: /* ditto */ | |
5257 | case 112: /* VSX Vector Multiply Double-Precision */ | |
5258 | case 80: /* VSX Vector Multiply Single-Precision */ | |
5259 | case 225: /* VSX Vector Negative Multiply-Add Double-Precision */ | |
5260 | case 233: /* ditto */ | |
5261 | case 193: /* VSX Vector Negative Multiply-Add Single-Precision */ | |
5262 | case 201: /* ditto */ | |
5263 | case 241: /* VSX Vector Negative Multiply-Subtract Double-Precision */ | |
5264 | case 249: /* ditto */ | |
5265 | case 209: /* VSX Vector Negative Multiply-Subtract Single-Precision */ | |
5266 | case 217: /* ditto */ | |
5267 | case 104: /* VSX Vector Subtract Double-Precision */ | |
5268 | case 72: /* VSX Vector Subtract Single-Precision */ | |
6ec2b213 EBM |
5269 | case 128: /* VSX Scalar Maximum Type-C Double-Precision */ |
5270 | case 136: /* VSX Scalar Minimum Type-C Double-Precision */ | |
5271 | case 144: /* VSX Scalar Maximum Type-J Double-Precision */ | |
5272 | case 152: /* VSX Scalar Minimum Type-J Double-Precision */ | |
5273 | case 3: /* VSX Scalar Compare Equal Double-Precision */ | |
5274 | case 11: /* VSX Scalar Compare Greater Than Double-Precision */ | |
5275 | case 19: /* VSX Scalar Compare Greater Than or Equal | |
5276 | Double-Precision */ | |
b4cdae6f | 5277 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); |
6ec2b213 | 5278 | /* FALL-THROUGH */ |
b4cdae6f WW |
5279 | case 240: /* VSX Vector Copy Sign Double-Precision */ |
5280 | case 208: /* VSX Vector Copy Sign Single-Precision */ | |
5281 | case 130: /* VSX Logical AND */ | |
5282 | case 138: /* VSX Logical AND with Complement */ | |
5283 | case 186: /* VSX Logical Equivalence */ | |
5284 | case 178: /* VSX Logical NAND */ | |
5285 | case 170: /* VSX Logical OR with Complement */ | |
5286 | case 162: /* VSX Logical NOR */ | |
5287 | case 146: /* VSX Logical OR */ | |
5288 | case 154: /* VSX Logical XOR */ | |
5289 | case 18: /* VSX Merge High Word */ | |
5290 | case 50: /* VSX Merge Low Word */ | |
5291 | case 10: /* VSX Permute Doubleword Immediate (DM=0) */ | |
5292 | case 10 | 0x20: /* VSX Permute Doubleword Immediate (DM=1) */ | |
5293 | case 10 | 0x40: /* VSX Permute Doubleword Immediate (DM=2) */ | |
5294 | case 10 | 0x60: /* VSX Permute Doubleword Immediate (DM=3) */ | |
5295 | case 2: /* VSX Shift Left Double by Word Immediate (SHW=0) */ | |
5296 | case 2 | 0x20: /* VSX Shift Left Double by Word Immediate (SHW=1) */ | |
5297 | case 2 | 0x40: /* VSX Shift Left Double by Word Immediate (SHW=2) */ | |
5298 | case 2 | 0x60: /* VSX Shift Left Double by Word Immediate (SHW=3) */ | |
6ec2b213 EBM |
5299 | case 216: /* VSX Vector Insert Exponent Single-Precision */ |
5300 | case 248: /* VSX Vector Insert Exponent Double-Precision */ | |
5301 | case 26: /* VSX Vector Permute */ | |
5302 | case 58: /* VSX Vector Permute Right-indexed */ | |
5303 | case 213: /* VSX Vector Test Data Class Single-Precision (DC=0) */ | |
5304 | case 213 | 0x8: /* VSX Vector Test Data Class Single-Precision (DC=1) */ | |
5305 | case 245: /* VSX Vector Test Data Class Double-Precision (DC=0) */ | |
5306 | case 245 | 0x8: /* VSX Vector Test Data Class Double-Precision (DC=1) */ | |
b4cdae6f WW |
5307 | ppc_record_vsr (regcache, tdep, PPC_XT (insn)); |
5308 | return 0; | |
5309 | ||
5310 | case 61: /* VSX Scalar Test for software Divide Double-Precision */ | |
5311 | case 125: /* VSX Vector Test for software Divide Double-Precision */ | |
5312 | case 93: /* VSX Vector Test for software Divide Single-Precision */ | |
5313 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
5314 | return 0; | |
5315 | ||
5316 | case 35: /* VSX Scalar Compare Unordered Double-Precision */ | |
5317 | case 43: /* VSX Scalar Compare Ordered Double-Precision */ | |
6ec2b213 | 5318 | case 59: /* VSX Scalar Compare Exponents Double-Precision */ |
b4cdae6f WW |
5319 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); |
5320 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
5321 | return 0; | |
5322 | } | |
5323 | ||
5324 | switch ((ext >> 2) & 0x7f) /* Mask out Rc-bit. */ | |
5325 | { | |
5326 | case 99: /* VSX Vector Compare Equal To Double-Precision */ | |
5327 | case 67: /* VSX Vector Compare Equal To Single-Precision */ | |
5328 | case 115: /* VSX Vector Compare Greater Than or | |
5329 | Equal To Double-Precision */ | |
5330 | case 83: /* VSX Vector Compare Greater Than or | |
5331 | Equal To Single-Precision */ | |
5332 | case 107: /* VSX Vector Compare Greater Than Double-Precision */ | |
5333 | case 75: /* VSX Vector Compare Greater Than Single-Precision */ | |
5334 | if (PPC_Rc (insn)) | |
5335 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
5336 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
5337 | ppc_record_vsr (regcache, tdep, PPC_XT (insn)); | |
5338 | return 0; | |
5339 | } | |
5340 | ||
5341 | switch (ext >> 1) | |
5342 | { | |
5343 | case 265: /* VSX Scalar round Double-Precision to | |
5344 | Single-Precision and Convert to | |
5345 | Single-Precision format */ | |
5346 | case 344: /* VSX Scalar truncate Double-Precision to | |
5347 | Integer and Convert to Signed Integer | |
5348 | Doubleword format with Saturate */ | |
5349 | case 88: /* VSX Scalar truncate Double-Precision to | |
5350 | Integer and Convert to Signed Integer Word | |
5351 | Format with Saturate */ | |
5352 | case 328: /* VSX Scalar truncate Double-Precision integer | |
5353 | and Convert to Unsigned Integer Doubleword | |
5354 | Format with Saturate */ | |
5355 | case 72: /* VSX Scalar truncate Double-Precision to | |
5356 | Integer and Convert to Unsigned Integer Word | |
5357 | Format with Saturate */ | |
5358 | case 329: /* VSX Scalar Convert Single-Precision to | |
5359 | Double-Precision format */ | |
5360 | case 376: /* VSX Scalar Convert Signed Integer | |
5361 | Doubleword to floating-point format and | |
5362 | Round to Double-Precision format */ | |
5363 | case 312: /* VSX Scalar Convert Signed Integer | |
5364 | Doubleword to floating-point format and | |
5365 | round to Single-Precision */ | |
5366 | case 360: /* VSX Scalar Convert Unsigned Integer | |
5367 | Doubleword to floating-point format and | |
5368 | Round to Double-Precision format */ | |
5369 | case 296: /* VSX Scalar Convert Unsigned Integer | |
5370 | Doubleword to floating-point format and | |
5371 | Round to Single-Precision */ | |
5372 | case 73: /* VSX Scalar Round to Double-Precision Integer | |
5373 | Using Round to Nearest Away */ | |
5374 | case 107: /* VSX Scalar Round to Double-Precision Integer | |
5375 | Exact using Current rounding mode */ | |
5376 | case 121: /* VSX Scalar Round to Double-Precision Integer | |
5377 | Using Round toward -Infinity */ | |
5378 | case 105: /* VSX Scalar Round to Double-Precision Integer | |
5379 | Using Round toward +Infinity */ | |
5380 | case 89: /* VSX Scalar Round to Double-Precision Integer | |
5381 | Using Round toward Zero */ | |
5382 | case 90: /* VSX Scalar Reciprocal Estimate Double-Precision */ | |
5383 | case 26: /* VSX Scalar Reciprocal Estimate Single-Precision */ | |
5384 | case 281: /* VSX Scalar Round to Single-Precision */ | |
5385 | case 74: /* VSX Scalar Reciprocal Square Root Estimate | |
5386 | Double-Precision */ | |
5387 | case 10: /* VSX Scalar Reciprocal Square Root Estimate | |
5388 | Single-Precision */ | |
5389 | case 75: /* VSX Scalar Square Root Double-Precision */ | |
5390 | case 11: /* VSX Scalar Square Root Single-Precision */ | |
5391 | case 393: /* VSX Vector round Double-Precision to | |
5392 | Single-Precision and Convert to | |
5393 | Single-Precision format */ | |
5394 | case 472: /* VSX Vector truncate Double-Precision to | |
5395 | Integer and Convert to Signed Integer | |
5396 | Doubleword format with Saturate */ | |
5397 | case 216: /* VSX Vector truncate Double-Precision to | |
5398 | Integer and Convert to Signed Integer Word | |
5399 | Format with Saturate */ | |
5400 | case 456: /* VSX Vector truncate Double-Precision to | |
5401 | Integer and Convert to Unsigned Integer | |
5402 | Doubleword format with Saturate */ | |
5403 | case 200: /* VSX Vector truncate Double-Precision to | |
5404 | Integer and Convert to Unsigned Integer Word | |
5405 | Format with Saturate */ | |
5406 | case 457: /* VSX Vector Convert Single-Precision to | |
5407 | Double-Precision format */ | |
5408 | case 408: /* VSX Vector truncate Single-Precision to | |
5409 | Integer and Convert to Signed Integer | |
5410 | Doubleword format with Saturate */ | |
5411 | case 152: /* VSX Vector truncate Single-Precision to | |
5412 | Integer and Convert to Signed Integer Word | |
5413 | Format with Saturate */ | |
5414 | case 392: /* VSX Vector truncate Single-Precision to | |
5415 | Integer and Convert to Unsigned Integer | |
5416 | Doubleword format with Saturate */ | |
5417 | case 136: /* VSX Vector truncate Single-Precision to | |
5418 | Integer and Convert to Unsigned Integer Word | |
5419 | Format with Saturate */ | |
5420 | case 504: /* VSX Vector Convert and round Signed Integer | |
5421 | Doubleword to Double-Precision format */ | |
5422 | case 440: /* VSX Vector Convert and round Signed Integer | |
5423 | Doubleword to Single-Precision format */ | |
5424 | case 248: /* VSX Vector Convert Signed Integer Word to | |
5425 | Double-Precision format */ | |
5426 | case 184: /* VSX Vector Convert and round Signed Integer | |
5427 | Word to Single-Precision format */ | |
5428 | case 488: /* VSX Vector Convert and round Unsigned | |
5429 | Integer Doubleword to Double-Precision format */ | |
5430 | case 424: /* VSX Vector Convert and round Unsigned | |
5431 | Integer Doubleword to Single-Precision format */ | |
5432 | case 232: /* VSX Vector Convert and round Unsigned | |
5433 | Integer Word to Double-Precision format */ | |
5434 | case 168: /* VSX Vector Convert and round Unsigned | |
5435 | Integer Word to Single-Precision format */ | |
5436 | case 201: /* VSX Vector Round to Double-Precision | |
5437 | Integer using round to Nearest Away */ | |
5438 | case 235: /* VSX Vector Round to Double-Precision | |
5439 | Integer Exact using Current rounding mode */ | |
5440 | case 249: /* VSX Vector Round to Double-Precision | |
5441 | Integer using round toward -Infinity */ | |
5442 | case 233: /* VSX Vector Round to Double-Precision | |
5443 | Integer using round toward +Infinity */ | |
5444 | case 217: /* VSX Vector Round to Double-Precision | |
5445 | Integer using round toward Zero */ | |
5446 | case 218: /* VSX Vector Reciprocal Estimate Double-Precision */ | |
5447 | case 154: /* VSX Vector Reciprocal Estimate Single-Precision */ | |
5448 | case 137: /* VSX Vector Round to Single-Precision Integer | |
5449 | Using Round to Nearest Away */ | |
5450 | case 171: /* VSX Vector Round to Single-Precision Integer | |
5451 | Exact Using Current rounding mode */ | |
5452 | case 185: /* VSX Vector Round to Single-Precision Integer | |
5453 | Using Round toward -Infinity */ | |
5454 | case 169: /* VSX Vector Round to Single-Precision Integer | |
5455 | Using Round toward +Infinity */ | |
5456 | case 153: /* VSX Vector Round to Single-Precision Integer | |
5457 | Using round toward Zero */ | |
5458 | case 202: /* VSX Vector Reciprocal Square Root Estimate | |
5459 | Double-Precision */ | |
5460 | case 138: /* VSX Vector Reciprocal Square Root Estimate | |
5461 | Single-Precision */ | |
5462 | case 203: /* VSX Vector Square Root Double-Precision */ | |
5463 | case 139: /* VSX Vector Square Root Single-Precision */ | |
5464 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
6ec2b213 | 5465 | /* FALL-THROUGH */ |
b4cdae6f WW |
5466 | case 345: /* VSX Scalar Absolute Value Double-Precision */ |
5467 | case 267: /* VSX Scalar Convert Scalar Single-Precision to | |
5468 | Vector Single-Precision format Non-signalling */ | |
5469 | case 331: /* VSX Scalar Convert Single-Precision to | |
5470 | Double-Precision format Non-signalling */ | |
5471 | case 361: /* VSX Scalar Negative Absolute Value Double-Precision */ | |
5472 | case 377: /* VSX Scalar Negate Double-Precision */ | |
5473 | case 473: /* VSX Vector Absolute Value Double-Precision */ | |
5474 | case 409: /* VSX Vector Absolute Value Single-Precision */ | |
5475 | case 489: /* VSX Vector Negative Absolute Value Double-Precision */ | |
5476 | case 425: /* VSX Vector Negative Absolute Value Single-Precision */ | |
5477 | case 505: /* VSX Vector Negate Double-Precision */ | |
5478 | case 441: /* VSX Vector Negate Single-Precision */ | |
5479 | case 164: /* VSX Splat Word */ | |
6ec2b213 EBM |
5480 | case 165: /* VSX Vector Extract Unsigned Word */ |
5481 | case 181: /* VSX Vector Insert Word */ | |
b4cdae6f WW |
5482 | ppc_record_vsr (regcache, tdep, PPC_XT (insn)); |
5483 | return 0; | |
5484 | ||
6ec2b213 EBM |
5485 | case 298: /* VSX Scalar Test Data Class Single-Precision */ |
5486 | case 362: /* VSX Scalar Test Data Class Double-Precision */ | |
5487 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
5488 | /* FALL-THROUGH */ | |
b4cdae6f WW |
5489 | case 106: /* VSX Scalar Test for software Square Root |
5490 | Double-Precision */ | |
5491 | case 234: /* VSX Vector Test for software Square Root | |
5492 | Double-Precision */ | |
5493 | case 170: /* VSX Vector Test for software Square Root | |
5494 | Single-Precision */ | |
5495 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
5496 | return 0; | |
6ec2b213 EBM |
5497 | |
5498 | case 347: | |
5499 | switch (PPC_FIELD (insn, 11, 5)) | |
5500 | { | |
5501 | case 0: /* VSX Scalar Extract Exponent Double-Precision */ | |
5502 | case 1: /* VSX Scalar Extract Significand Double-Precision */ | |
dda83cd7 | 5503 | record_full_arch_list_add_reg (regcache, |
6ec2b213 EBM |
5504 | tdep->ppc_gp0_regnum + PPC_RT (insn)); |
5505 | return 0; | |
5506 | case 16: /* VSX Scalar Convert Half-Precision format to | |
5507 | Double-Precision format */ | |
5508 | case 17: /* VSX Scalar round & Convert Double-Precision format | |
5509 | to Half-Precision format */ | |
5510 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
5511 | ppc_record_vsr (regcache, tdep, PPC_XT (insn)); | |
5512 | return 0; | |
5513 | } | |
5514 | break; | |
5515 | ||
5516 | case 475: | |
5517 | switch (PPC_FIELD (insn, 11, 5)) | |
5518 | { | |
5519 | case 24: /* VSX Vector Convert Half-Precision format to | |
5520 | Single-Precision format */ | |
5521 | case 25: /* VSX Vector round and Convert Single-Precision format | |
5522 | to Half-Precision format */ | |
5523 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
5524 | /* FALL-THROUGH */ | |
5525 | case 0: /* VSX Vector Extract Exponent Double-Precision */ | |
5526 | case 1: /* VSX Vector Extract Significand Double-Precision */ | |
5527 | case 7: /* VSX Vector Byte-Reverse Halfword */ | |
5528 | case 8: /* VSX Vector Extract Exponent Single-Precision */ | |
5529 | case 9: /* VSX Vector Extract Significand Single-Precision */ | |
5530 | case 15: /* VSX Vector Byte-Reverse Word */ | |
5531 | case 23: /* VSX Vector Byte-Reverse Doubleword */ | |
5532 | case 31: /* VSX Vector Byte-Reverse Quadword */ | |
5533 | ppc_record_vsr (regcache, tdep, PPC_XT (insn)); | |
5534 | return 0; | |
5535 | } | |
5536 | break; | |
5537 | } | |
5538 | ||
5539 | switch (ext) | |
5540 | { | |
5541 | case 360: /* VSX Vector Splat Immediate Byte */ | |
5542 | if (PPC_FIELD (insn, 11, 2) == 0) | |
5543 | { | |
5544 | ppc_record_vsr (regcache, tdep, PPC_XT (insn)); | |
5545 | return 0; | |
5546 | } | |
5547 | break; | |
5548 | case 918: /* VSX Scalar Insert Exponent Double-Precision */ | |
5549 | ppc_record_vsr (regcache, tdep, PPC_XT (insn)); | |
5550 | return 0; | |
b4cdae6f WW |
5551 | } |
5552 | ||
5553 | if (((ext >> 3) & 0x3) == 3) /* VSX Select */ | |
5554 | { | |
5555 | ppc_record_vsr (regcache, tdep, PPC_XT (insn)); | |
5556 | return 0; | |
5557 | } | |
5558 | ||
810c1026 WW |
5559 | fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x " |
5560 | "at %s, 60-%d.\n", insn, paddress (gdbarch, addr), ext); | |
b4cdae6f WW |
5561 | return -1; |
5562 | } | |
5563 | ||
6ec2b213 EBM |
5564 | /* Parse and record instructions of primary opcode-61 at ADDR. |
5565 | Return 0 if successful. */ | |
5566 | ||
5567 | static int | |
5568 | ppc_process_record_op61 (struct gdbarch *gdbarch, struct regcache *regcache, | |
5569 | CORE_ADDR addr, uint32_t insn) | |
5570 | { | |
5571 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
5572 | ULONGEST ea = 0; | |
5573 | int size; | |
5574 | ||
5575 | switch (insn & 0x3) | |
5576 | { | |
5577 | case 0: /* Store Floating-Point Double Pair */ | |
5578 | case 2: /* Store VSX Scalar Doubleword */ | |
5579 | case 3: /* Store VSX Scalar Single */ | |
5580 | if (PPC_RA (insn) != 0) | |
5581 | regcache_raw_read_unsigned (regcache, | |
5582 | tdep->ppc_gp0_regnum + PPC_RA (insn), | |
5583 | &ea); | |
5584 | ea += PPC_DS (insn) << 2; | |
5585 | switch (insn & 0x3) | |
5586 | { | |
5587 | case 0: /* Store Floating-Point Double Pair */ | |
5588 | size = 16; | |
5589 | break; | |
5590 | case 2: /* Store VSX Scalar Doubleword */ | |
5591 | size = 8; | |
5592 | break; | |
5593 | case 3: /* Store VSX Scalar Single */ | |
5594 | size = 4; | |
5595 | break; | |
5596 | default: | |
5597 | gdb_assert (0); | |
5598 | } | |
5599 | record_full_arch_list_add_mem (ea, size); | |
5600 | return 0; | |
5601 | } | |
5602 | ||
5603 | switch (insn & 0x7) | |
5604 | { | |
5605 | case 1: /* Load VSX Vector */ | |
5606 | ppc_record_vsr (regcache, tdep, PPC_XT (insn)); | |
5607 | return 0; | |
5608 | case 5: /* Store VSX Vector */ | |
5609 | if (PPC_RA (insn) != 0) | |
5610 | regcache_raw_read_unsigned (regcache, | |
5611 | tdep->ppc_gp0_regnum + PPC_RA (insn), | |
5612 | &ea); | |
5613 | ea += PPC_DQ (insn) << 4; | |
5614 | record_full_arch_list_add_mem (ea, 16); | |
5615 | return 0; | |
5616 | } | |
5617 | ||
5618 | fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x " | |
5619 | "at %s.\n", insn, paddress (gdbarch, addr)); | |
5620 | return -1; | |
5621 | } | |
5622 | ||
ddeca1df WW |
5623 | /* Parse and record instructions of primary opcode-63 at ADDR. |
5624 | Return 0 if successful. */ | |
b4cdae6f WW |
5625 | |
5626 | static int | |
5627 | ppc_process_record_op63 (struct gdbarch *gdbarch, struct regcache *regcache, | |
5628 | CORE_ADDR addr, uint32_t insn) | |
5629 | { | |
5630 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
5631 | int ext = PPC_EXTOP (insn); | |
5632 | int tmp; | |
5633 | ||
5634 | switch (ext & 0x1f) | |
5635 | { | |
5636 | case 18: /* Floating Divide */ | |
5637 | case 20: /* Floating Subtract */ | |
5638 | case 21: /* Floating Add */ | |
5639 | case 22: /* Floating Square Root */ | |
5640 | case 24: /* Floating Reciprocal Estimate */ | |
5641 | case 25: /* Floating Multiply */ | |
5642 | case 26: /* Floating Reciprocal Square Root Estimate */ | |
5643 | case 28: /* Floating Multiply-Subtract */ | |
5644 | case 29: /* Floating Multiply-Add */ | |
5645 | case 30: /* Floating Negative Multiply-Subtract */ | |
5646 | case 31: /* Floating Negative Multiply-Add */ | |
5647 | record_full_arch_list_add_reg (regcache, | |
5648 | tdep->ppc_fp0_regnum + PPC_FRT (insn)); | |
5649 | if (PPC_RC (insn)) | |
5650 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
5651 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
5652 | return 0; | |
5653 | ||
5654 | case 23: /* Floating Select */ | |
5655 | record_full_arch_list_add_reg (regcache, | |
5656 | tdep->ppc_fp0_regnum + PPC_FRT (insn)); | |
5657 | if (PPC_RC (insn)) | |
5658 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
8aabe2e2 | 5659 | return 0; |
b4cdae6f WW |
5660 | } |
5661 | ||
6ec2b213 EBM |
5662 | switch (ext & 0xff) |
5663 | { | |
5664 | case 5: /* VSX Scalar Round to Quad-Precision Integer */ | |
5665 | case 37: /* VSX Scalar Round Quad-Precision to Double-Extended | |
5666 | Precision */ | |
5667 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
5668 | ppc_record_vsr (regcache, tdep, PPC_VRT (insn) + 32); | |
5669 | return 0; | |
5670 | } | |
5671 | ||
b4cdae6f WW |
5672 | switch (ext) |
5673 | { | |
5674 | case 2: /* DFP Add Quad */ | |
5675 | case 3: /* DFP Quantize Quad */ | |
5676 | case 34: /* DFP Multiply Quad */ | |
5677 | case 35: /* DFP Reround Quad */ | |
5678 | case 67: /* DFP Quantize Immediate Quad */ | |
5679 | case 99: /* DFP Round To FP Integer With Inexact Quad */ | |
5680 | case 227: /* DFP Round To FP Integer Without Inexact Quad */ | |
5681 | case 258: /* DFP Convert To DFP Extended Quad */ | |
5682 | case 514: /* DFP Subtract Quad */ | |
5683 | case 546: /* DFP Divide Quad */ | |
5684 | case 770: /* DFP Round To DFP Long Quad */ | |
5685 | case 802: /* DFP Convert From Fixed Quad */ | |
5686 | case 834: /* DFP Encode BCD To DPD Quad */ | |
5687 | if (PPC_RC (insn)) | |
5688 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
5689 | tmp = tdep->ppc_fp0_regnum + (PPC_FRT (insn) & ~1); | |
5690 | record_full_arch_list_add_reg (regcache, tmp); | |
5691 | record_full_arch_list_add_reg (regcache, tmp + 1); | |
5692 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
5693 | return 0; | |
5694 | ||
5695 | case 130: /* DFP Compare Ordered Quad */ | |
5696 | case 162: /* DFP Test Exponent Quad */ | |
5697 | case 194: /* DFP Test Data Class Quad */ | |
5698 | case 226: /* DFP Test Data Group Quad */ | |
5699 | case 642: /* DFP Compare Unordered Quad */ | |
5700 | case 674: /* DFP Test Significance Quad */ | |
6ec2b213 | 5701 | case 675: /* DFP Test Significance Immediate Quad */ |
b4cdae6f WW |
5702 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); |
5703 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
5704 | return 0; | |
5705 | ||
5706 | case 66: /* DFP Shift Significand Left Immediate Quad */ | |
5707 | case 98: /* DFP Shift Significand Right Immediate Quad */ | |
5708 | case 322: /* DFP Decode DPD To BCD Quad */ | |
5709 | case 866: /* DFP Insert Biased Exponent Quad */ | |
5710 | tmp = tdep->ppc_fp0_regnum + (PPC_FRT (insn) & ~1); | |
5711 | record_full_arch_list_add_reg (regcache, tmp); | |
5712 | record_full_arch_list_add_reg (regcache, tmp + 1); | |
5713 | if (PPC_RC (insn)) | |
5714 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
5715 | return 0; | |
5716 | ||
5717 | case 290: /* DFP Convert To Fixed Quad */ | |
5718 | record_full_arch_list_add_reg (regcache, | |
5719 | tdep->ppc_fp0_regnum + PPC_FRT (insn)); | |
5720 | if (PPC_RC (insn)) | |
5721 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
5722 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
8aabe2e2 | 5723 | return 0; |
b4cdae6f WW |
5724 | |
5725 | case 354: /* DFP Extract Biased Exponent Quad */ | |
5726 | record_full_arch_list_add_reg (regcache, | |
5727 | tdep->ppc_fp0_regnum + PPC_FRT (insn)); | |
5728 | if (PPC_RC (insn)) | |
5729 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
5730 | return 0; | |
5731 | ||
5732 | case 12: /* Floating Round to Single-Precision */ | |
5733 | case 14: /* Floating Convert To Integer Word */ | |
5734 | case 15: /* Floating Convert To Integer Word | |
5735 | with round toward Zero */ | |
5736 | case 142: /* Floating Convert To Integer Word Unsigned */ | |
5737 | case 143: /* Floating Convert To Integer Word Unsigned | |
5738 | with round toward Zero */ | |
5739 | case 392: /* Floating Round to Integer Nearest */ | |
5740 | case 424: /* Floating Round to Integer Toward Zero */ | |
5741 | case 456: /* Floating Round to Integer Plus */ | |
5742 | case 488: /* Floating Round to Integer Minus */ | |
5743 | case 814: /* Floating Convert To Integer Doubleword */ | |
5744 | case 815: /* Floating Convert To Integer Doubleword | |
5745 | with round toward Zero */ | |
5746 | case 846: /* Floating Convert From Integer Doubleword */ | |
5747 | case 942: /* Floating Convert To Integer Doubleword Unsigned */ | |
5748 | case 943: /* Floating Convert To Integer Doubleword Unsigned | |
5749 | with round toward Zero */ | |
5750 | case 974: /* Floating Convert From Integer Doubleword Unsigned */ | |
5751 | record_full_arch_list_add_reg (regcache, | |
5752 | tdep->ppc_fp0_regnum + PPC_FRT (insn)); | |
5753 | if (PPC_RC (insn)) | |
5754 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
5755 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
5756 | return 0; | |
5757 | ||
6ec2b213 EBM |
5758 | case 583: |
5759 | switch (PPC_FIELD (insn, 11, 5)) | |
dda83cd7 | 5760 | { |
6ec2b213 EBM |
5761 | case 1: /* Move From FPSCR & Clear Enables */ |
5762 | case 20: /* Move From FPSCR Control & set DRN */ | |
5763 | case 21: /* Move From FPSCR Control & set DRN Immediate */ | |
5764 | case 22: /* Move From FPSCR Control & set RN */ | |
5765 | case 23: /* Move From FPSCR Control & set RN Immediate */ | |
5766 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
e3829d13 | 5767 | /* Fall through. */ |
6ec2b213 EBM |
5768 | case 0: /* Move From FPSCR */ |
5769 | case 24: /* Move From FPSCR Lightweight */ | |
5770 | if (PPC_FIELD (insn, 11, 5) == 0 && PPC_RC (insn)) | |
5771 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
5772 | record_full_arch_list_add_reg (regcache, | |
5773 | tdep->ppc_fp0_regnum | |
5774 | + PPC_FRT (insn)); | |
5775 | return 0; | |
dda83cd7 | 5776 | } |
6ec2b213 EBM |
5777 | break; |
5778 | ||
b4cdae6f WW |
5779 | case 8: /* Floating Copy Sign */ |
5780 | case 40: /* Floating Negate */ | |
5781 | case 72: /* Floating Move Register */ | |
5782 | case 136: /* Floating Negative Absolute Value */ | |
5783 | case 264: /* Floating Absolute Value */ | |
5784 | record_full_arch_list_add_reg (regcache, | |
5785 | tdep->ppc_fp0_regnum + PPC_FRT (insn)); | |
5786 | if (PPC_RC (insn)) | |
5787 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
5788 | return 0; | |
5789 | ||
5790 | case 838: /* Floating Merge Odd Word */ | |
5791 | case 966: /* Floating Merge Even Word */ | |
5792 | record_full_arch_list_add_reg (regcache, | |
5793 | tdep->ppc_fp0_regnum + PPC_FRT (insn)); | |
5794 | return 0; | |
5795 | ||
5796 | case 38: /* Move To FPSCR Bit 1 */ | |
5797 | case 70: /* Move To FPSCR Bit 0 */ | |
5798 | case 134: /* Move To FPSCR Field Immediate */ | |
5799 | case 711: /* Move To FPSCR Fields */ | |
5800 | if (PPC_RC (insn)) | |
5801 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
5802 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
8aabe2e2 | 5803 | return 0; |
b4cdae6f WW |
5804 | |
5805 | case 0: /* Floating Compare Unordered */ | |
5806 | case 32: /* Floating Compare Ordered */ | |
5807 | case 64: /* Move to Condition Register from FPSCR */ | |
6ec2b213 EBM |
5808 | case 132: /* VSX Scalar Compare Ordered Quad-Precision */ |
5809 | case 164: /* VSX Scalar Compare Exponents Quad-Precision */ | |
5810 | case 644: /* VSX Scalar Compare Unordered Quad-Precision */ | |
5811 | case 708: /* VSX Scalar Test Data Class Quad-Precision */ | |
b4cdae6f WW |
5812 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); |
5813 | /* FALL-THROUGH */ | |
5814 | case 128: /* Floating Test for software Divide */ | |
5815 | case 160: /* Floating Test for software Square Root */ | |
5816 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
5817 | return 0; | |
5818 | ||
6ec2b213 EBM |
5819 | case 4: /* VSX Scalar Add Quad-Precision */ |
5820 | case 36: /* VSX Scalar Multiply Quad-Precision */ | |
5821 | case 388: /* VSX Scalar Multiply-Add Quad-Precision */ | |
5822 | case 420: /* VSX Scalar Multiply-Subtract Quad-Precision */ | |
5823 | case 452: /* VSX Scalar Negative Multiply-Add Quad-Precision */ | |
5824 | case 484: /* VSX Scalar Negative Multiply-Subtract | |
5825 | Quad-Precision */ | |
5826 | case 516: /* VSX Scalar Subtract Quad-Precision */ | |
5827 | case 548: /* VSX Scalar Divide Quad-Precision */ | |
5828 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
5829 | /* FALL-THROUGH */ | |
5830 | case 100: /* VSX Scalar Copy Sign Quad-Precision */ | |
5831 | case 868: /* VSX Scalar Insert Exponent Quad-Precision */ | |
5832 | ppc_record_vsr (regcache, tdep, PPC_VRT (insn) + 32); | |
5833 | return 0; | |
5834 | ||
5835 | case 804: | |
5836 | switch (PPC_FIELD (insn, 11, 5)) | |
5837 | { | |
5838 | case 27: /* VSX Scalar Square Root Quad-Precision */ | |
5839 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
5840 | /* FALL-THROUGH */ | |
5841 | case 0: /* VSX Scalar Absolute Quad-Precision */ | |
5842 | case 2: /* VSX Scalar Extract Exponent Quad-Precision */ | |
5843 | case 8: /* VSX Scalar Negative Absolute Quad-Precision */ | |
5844 | case 16: /* VSX Scalar Negate Quad-Precision */ | |
5845 | case 18: /* VSX Scalar Extract Significand Quad-Precision */ | |
5846 | ppc_record_vsr (regcache, tdep, PPC_VRT (insn) + 32); | |
5847 | return 0; | |
5848 | } | |
5849 | break; | |
5850 | ||
5851 | case 836: | |
5852 | switch (PPC_FIELD (insn, 11, 5)) | |
5853 | { | |
5854 | case 1: /* VSX Scalar truncate & Convert Quad-Precision format | |
5855 | to Unsigned Word format */ | |
5856 | case 2: /* VSX Scalar Convert Unsigned Doubleword format to | |
5857 | Quad-Precision format */ | |
5858 | case 9: /* VSX Scalar truncate & Convert Quad-Precision format | |
5859 | to Signed Word format */ | |
5860 | case 10: /* VSX Scalar Convert Signed Doubleword format to | |
5861 | Quad-Precision format */ | |
5862 | case 17: /* VSX Scalar truncate & Convert Quad-Precision format | |
5863 | to Unsigned Doubleword format */ | |
5864 | case 20: /* VSX Scalar round & Convert Quad-Precision format to | |
5865 | Double-Precision format */ | |
5866 | case 22: /* VSX Scalar Convert Double-Precision format to | |
5867 | Quad-Precision format */ | |
5868 | case 25: /* VSX Scalar truncate & Convert Quad-Precision format | |
5869 | to Signed Doubleword format */ | |
5870 | record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); | |
5871 | ppc_record_vsr (regcache, tdep, PPC_VRT (insn) + 32); | |
5872 | return 0; | |
5873 | } | |
b4cdae6f WW |
5874 | } |
5875 | ||
810c1026 | 5876 | fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x " |
6ec2b213 | 5877 | "at %s, 63-%d.\n", insn, paddress (gdbarch, addr), ext); |
b4cdae6f WW |
5878 | return -1; |
5879 | } | |
5880 | ||
5881 | /* Parse the current instruction and record the values of the registers and | |
5882 | memory that will be changed in current instruction to "record_arch_list". | |
5883 | Return -1 if something wrong. */ | |
5884 | ||
5885 | int | |
5886 | ppc_process_record (struct gdbarch *gdbarch, struct regcache *regcache, | |
5887 | CORE_ADDR addr) | |
5888 | { | |
5889 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
5890 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
5891 | uint32_t insn; | |
5892 | int op6, tmp, i; | |
5893 | ||
5894 | insn = read_memory_unsigned_integer (addr, 4, byte_order); | |
5895 | op6 = PPC_OP6 (insn); | |
5896 | ||
5897 | switch (op6) | |
5898 | { | |
5899 | case 2: /* Trap Doubleword Immediate */ | |
5900 | case 3: /* Trap Word Immediate */ | |
5901 | /* Do nothing. */ | |
5902 | break; | |
5903 | ||
5904 | case 4: | |
5905 | if (ppc_process_record_op4 (gdbarch, regcache, addr, insn) != 0) | |
5906 | return -1; | |
5907 | break; | |
5908 | ||
5909 | case 17: /* System call */ | |
5910 | if (PPC_LEV (insn) != 0) | |
5911 | goto UNKNOWN_OP; | |
5912 | ||
5913 | if (tdep->ppc_syscall_record != NULL) | |
5914 | { | |
5915 | if (tdep->ppc_syscall_record (regcache) != 0) | |
5916 | return -1; | |
5917 | } | |
5918 | else | |
5919 | { | |
5920 | printf_unfiltered (_("no syscall record support\n")); | |
5921 | return -1; | |
5922 | } | |
5923 | break; | |
5924 | ||
5925 | case 7: /* Multiply Low Immediate */ | |
5926 | record_full_arch_list_add_reg (regcache, | |
5927 | tdep->ppc_gp0_regnum + PPC_RT (insn)); | |
5928 | break; | |
5929 | ||
5930 | case 8: /* Subtract From Immediate Carrying */ | |
5931 | record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum); | |
5932 | record_full_arch_list_add_reg (regcache, | |
5933 | tdep->ppc_gp0_regnum + PPC_RT (insn)); | |
5934 | break; | |
5935 | ||
5936 | case 10: /* Compare Logical Immediate */ | |
5937 | case 11: /* Compare Immediate */ | |
5938 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
5939 | break; | |
5940 | ||
5941 | case 13: /* Add Immediate Carrying and Record */ | |
5942 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
5943 | /* FALL-THROUGH */ | |
5944 | case 12: /* Add Immediate Carrying */ | |
5945 | record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum); | |
5946 | /* FALL-THROUGH */ | |
5947 | case 14: /* Add Immediate */ | |
5948 | case 15: /* Add Immediate Shifted */ | |
5949 | record_full_arch_list_add_reg (regcache, | |
5950 | tdep->ppc_gp0_regnum + PPC_RT (insn)); | |
5951 | break; | |
5952 | ||
5953 | case 16: /* Branch Conditional */ | |
5954 | if ((PPC_BO (insn) & 0x4) == 0) | |
5955 | record_full_arch_list_add_reg (regcache, tdep->ppc_ctr_regnum); | |
5956 | /* FALL-THROUGH */ | |
5957 | case 18: /* Branch */ | |
5958 | if (PPC_LK (insn)) | |
5959 | record_full_arch_list_add_reg (regcache, tdep->ppc_lr_regnum); | |
5960 | break; | |
5961 | ||
5962 | case 19: | |
5963 | if (ppc_process_record_op19 (gdbarch, regcache, addr, insn) != 0) | |
5964 | return -1; | |
5965 | break; | |
5966 | ||
5967 | case 20: /* Rotate Left Word Immediate then Mask Insert */ | |
5968 | case 21: /* Rotate Left Word Immediate then AND with Mask */ | |
5969 | case 23: /* Rotate Left Word then AND with Mask */ | |
5970 | case 30: /* Rotate Left Doubleword Immediate then Clear Left */ | |
5971 | /* Rotate Left Doubleword Immediate then Clear Right */ | |
5972 | /* Rotate Left Doubleword Immediate then Clear */ | |
5973 | /* Rotate Left Doubleword then Clear Left */ | |
5974 | /* Rotate Left Doubleword then Clear Right */ | |
5975 | /* Rotate Left Doubleword Immediate then Mask Insert */ | |
5976 | if (PPC_RC (insn)) | |
5977 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
5978 | record_full_arch_list_add_reg (regcache, | |
5979 | tdep->ppc_gp0_regnum + PPC_RA (insn)); | |
5980 | break; | |
5981 | ||
5982 | case 28: /* AND Immediate */ | |
5983 | case 29: /* AND Immediate Shifted */ | |
5984 | record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); | |
5985 | /* FALL-THROUGH */ | |
5986 | case 24: /* OR Immediate */ | |
5987 | case 25: /* OR Immediate Shifted */ | |
5988 | case 26: /* XOR Immediate */ | |
5989 | case 27: /* XOR Immediate Shifted */ | |
5990 | record_full_arch_list_add_reg (regcache, | |
5991 | tdep->ppc_gp0_regnum + PPC_RA (insn)); | |
5992 | break; | |
5993 | ||
5994 | case 31: | |
5995 | if (ppc_process_record_op31 (gdbarch, regcache, addr, insn) != 0) | |
5996 | return -1; | |
5997 | break; | |
5998 | ||
5999 | case 33: /* Load Word and Zero with Update */ | |
6000 | case 35: /* Load Byte and Zero with Update */ | |
6001 | case 41: /* Load Halfword and Zero with Update */ | |
6002 | case 43: /* Load Halfword Algebraic with Update */ | |
6003 | record_full_arch_list_add_reg (regcache, | |
6004 | tdep->ppc_gp0_regnum + PPC_RA (insn)); | |
6005 | /* FALL-THROUGH */ | |
6006 | case 32: /* Load Word and Zero */ | |
6007 | case 34: /* Load Byte and Zero */ | |
6008 | case 40: /* Load Halfword and Zero */ | |
6009 | case 42: /* Load Halfword Algebraic */ | |
6010 | record_full_arch_list_add_reg (regcache, | |
6011 | tdep->ppc_gp0_regnum + PPC_RT (insn)); | |
6012 | break; | |
6013 | ||
6014 | case 46: /* Load Multiple Word */ | |
6015 | for (i = PPC_RT (insn); i < 32; i++) | |
6016 | record_full_arch_list_add_reg (regcache, tdep->ppc_gp0_regnum + i); | |
6017 | break; | |
6018 | ||
6019 | case 56: /* Load Quadword */ | |
6020 | tmp = tdep->ppc_gp0_regnum + (PPC_RT (insn) & ~1); | |
6021 | record_full_arch_list_add_reg (regcache, tmp); | |
6022 | record_full_arch_list_add_reg (regcache, tmp + 1); | |
6023 | break; | |
6024 | ||
6025 | case 49: /* Load Floating-Point Single with Update */ | |
6026 | case 51: /* Load Floating-Point Double with Update */ | |
6027 | record_full_arch_list_add_reg (regcache, | |
6028 | tdep->ppc_gp0_regnum + PPC_RA (insn)); | |
6029 | /* FALL-THROUGH */ | |
6030 | case 48: /* Load Floating-Point Single */ | |
6031 | case 50: /* Load Floating-Point Double */ | |
6032 | record_full_arch_list_add_reg (regcache, | |
6033 | tdep->ppc_fp0_regnum + PPC_FRT (insn)); | |
6034 | break; | |
6035 | ||
6036 | case 47: /* Store Multiple Word */ | |
6037 | { | |
b926417a | 6038 | ULONGEST iaddr = 0; |
b4cdae6f WW |
6039 | |
6040 | if (PPC_RA (insn) != 0) | |
6041 | regcache_raw_read_unsigned (regcache, | |
6042 | tdep->ppc_gp0_regnum + PPC_RA (insn), | |
b926417a | 6043 | &iaddr); |
b4cdae6f | 6044 | |
b926417a TT |
6045 | iaddr += PPC_D (insn); |
6046 | record_full_arch_list_add_mem (iaddr, 4 * (32 - PPC_RS (insn))); | |
b4cdae6f WW |
6047 | } |
6048 | break; | |
6049 | ||
6050 | case 37: /* Store Word with Update */ | |
6051 | case 39: /* Store Byte with Update */ | |
6052 | case 45: /* Store Halfword with Update */ | |
6053 | case 53: /* Store Floating-Point Single with Update */ | |
6054 | case 55: /* Store Floating-Point Double with Update */ | |
6055 | record_full_arch_list_add_reg (regcache, | |
6056 | tdep->ppc_gp0_regnum + PPC_RA (insn)); | |
6057 | /* FALL-THROUGH */ | |
6058 | case 36: /* Store Word */ | |
6059 | case 38: /* Store Byte */ | |
6060 | case 44: /* Store Halfword */ | |
6061 | case 52: /* Store Floating-Point Single */ | |
6062 | case 54: /* Store Floating-Point Double */ | |
6063 | { | |
b926417a | 6064 | ULONGEST iaddr = 0; |
b4cdae6f WW |
6065 | int size = -1; |
6066 | ||
6067 | if (PPC_RA (insn) != 0) | |
6068 | regcache_raw_read_unsigned (regcache, | |
6069 | tdep->ppc_gp0_regnum + PPC_RA (insn), | |
b926417a TT |
6070 | &iaddr); |
6071 | iaddr += PPC_D (insn); | |
b4cdae6f WW |
6072 | |
6073 | if (op6 == 36 || op6 == 37 || op6 == 52 || op6 == 53) | |
6074 | size = 4; | |
6075 | else if (op6 == 54 || op6 == 55) | |
6076 | size = 8; | |
6077 | else if (op6 == 44 || op6 == 45) | |
6078 | size = 2; | |
6079 | else if (op6 == 38 || op6 == 39) | |
6080 | size = 1; | |
6081 | else | |
6082 | gdb_assert (0); | |
6083 | ||
b926417a | 6084 | record_full_arch_list_add_mem (iaddr, size); |
b4cdae6f WW |
6085 | } |
6086 | break; | |
6087 | ||
6ec2b213 EBM |
6088 | case 57: |
6089 | switch (insn & 0x3) | |
dda83cd7 | 6090 | { |
6ec2b213 EBM |
6091 | case 0: /* Load Floating-Point Double Pair */ |
6092 | tmp = tdep->ppc_fp0_regnum + (PPC_RT (insn) & ~1); | |
6093 | record_full_arch_list_add_reg (regcache, tmp); | |
6094 | record_full_arch_list_add_reg (regcache, tmp + 1); | |
6095 | break; | |
6096 | case 2: /* Load VSX Scalar Doubleword */ | |
6097 | case 3: /* Load VSX Scalar Single */ | |
6098 | ppc_record_vsr (regcache, tdep, PPC_VRT (insn) + 32); | |
6099 | break; | |
6100 | default: | |
6101 | goto UNKNOWN_OP; | |
6102 | } | |
b4cdae6f WW |
6103 | break; |
6104 | ||
6105 | case 58: /* Load Doubleword */ | |
6106 | /* Load Doubleword with Update */ | |
6107 | /* Load Word Algebraic */ | |
6108 | if (PPC_FIELD (insn, 30, 2) > 2) | |
6109 | goto UNKNOWN_OP; | |
6110 | ||
6111 | record_full_arch_list_add_reg (regcache, | |
6112 | tdep->ppc_gp0_regnum + PPC_RT (insn)); | |
6113 | if (PPC_BIT (insn, 31)) | |
6114 | record_full_arch_list_add_reg (regcache, | |
6115 | tdep->ppc_gp0_regnum + PPC_RA (insn)); | |
6116 | break; | |
6117 | ||
6118 | case 59: | |
6119 | if (ppc_process_record_op59 (gdbarch, regcache, addr, insn) != 0) | |
6120 | return -1; | |
6121 | break; | |
6122 | ||
6123 | case 60: | |
6124 | if (ppc_process_record_op60 (gdbarch, regcache, addr, insn) != 0) | |
6125 | return -1; | |
6126 | break; | |
6127 | ||
6ec2b213 EBM |
6128 | case 61: |
6129 | if (ppc_process_record_op61 (gdbarch, regcache, addr, insn) != 0) | |
6130 | return -1; | |
6131 | break; | |
6132 | ||
b4cdae6f WW |
6133 | case 62: /* Store Doubleword */ |
6134 | /* Store Doubleword with Update */ | |
6135 | /* Store Quadword with Update */ | |
6136 | { | |
b926417a | 6137 | ULONGEST iaddr = 0; |
b4cdae6f WW |
6138 | int size; |
6139 | int sub2 = PPC_FIELD (insn, 30, 2); | |
6140 | ||
6ec2b213 | 6141 | if (sub2 > 2) |
b4cdae6f WW |
6142 | goto UNKNOWN_OP; |
6143 | ||
6144 | if (PPC_RA (insn) != 0) | |
6145 | regcache_raw_read_unsigned (regcache, | |
6146 | tdep->ppc_gp0_regnum + PPC_RA (insn), | |
b926417a | 6147 | &iaddr); |
b4cdae6f | 6148 | |
6ec2b213 | 6149 | size = (sub2 == 2) ? 16 : 8; |
b4cdae6f | 6150 | |
b926417a TT |
6151 | iaddr += PPC_DS (insn) << 2; |
6152 | record_full_arch_list_add_mem (iaddr, size); | |
b4cdae6f WW |
6153 | |
6154 | if (op6 == 62 && sub2 == 1) | |
6155 | record_full_arch_list_add_reg (regcache, | |
6156 | tdep->ppc_gp0_regnum + | |
6157 | PPC_RA (insn)); | |
6158 | ||
6159 | break; | |
6160 | } | |
6161 | ||
6162 | case 63: | |
6163 | if (ppc_process_record_op63 (gdbarch, regcache, addr, insn) != 0) | |
6164 | return -1; | |
6165 | break; | |
6166 | ||
6167 | default: | |
6168 | UNKNOWN_OP: | |
810c1026 WW |
6169 | fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x " |
6170 | "at %s, %d.\n", insn, paddress (gdbarch, addr), op6); | |
b4cdae6f WW |
6171 | return -1; |
6172 | } | |
6173 | ||
6174 | if (record_full_arch_list_add_reg (regcache, PPC_PC_REGNUM)) | |
6175 | return -1; | |
6176 | if (record_full_arch_list_add_end ()) | |
6177 | return -1; | |
6178 | return 0; | |
6179 | } | |
6180 | ||
7a78ae4e ND |
6181 | /* Initialize the current architecture based on INFO. If possible, re-use an |
6182 | architecture from ARCHES, which is a list of architectures already created | |
6183 | during this debugging session. | |
c906108c | 6184 | |
7a78ae4e | 6185 | Called e.g. at program startup, when reading a core file, and when reading |
64366f1c | 6186 | a binary file. */ |
c906108c | 6187 | |
7a78ae4e ND |
6188 | static struct gdbarch * |
6189 | rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
6190 | { | |
6191 | struct gdbarch *gdbarch; | |
6192 | struct gdbarch_tdep *tdep; | |
7cc46491 | 6193 | int wordsize, from_xcoff_exec, from_elf_exec; |
7a78ae4e ND |
6194 | enum bfd_architecture arch; |
6195 | unsigned long mach; | |
6196 | bfd abfd; | |
55eddb0f DJ |
6197 | enum auto_boolean soft_float_flag = powerpc_soft_float_global; |
6198 | int soft_float; | |
ed0f4273 | 6199 | enum powerpc_long_double_abi long_double_abi = POWERPC_LONG_DOUBLE_AUTO; |
55eddb0f | 6200 | enum powerpc_vector_abi vector_abi = powerpc_vector_abi_global; |
cd453cd0 | 6201 | enum powerpc_elf_abi elf_abi = POWERPC_ELF_AUTO; |
93b4691f | 6202 | int have_fpu = 0, have_spe = 0, have_mq = 0, have_altivec = 0; |
7ca18ed6 | 6203 | int have_dfp = 0, have_vsx = 0, have_ppr = 0, have_dscr = 0; |
8d619c01 EBM |
6204 | int have_tar = 0, have_ebb = 0, have_pmu = 0, have_htm_spr = 0; |
6205 | int have_htm_core = 0, have_htm_fpu = 0, have_htm_altivec = 0; | |
6206 | int have_htm_vsx = 0, have_htm_ppr = 0, have_htm_dscr = 0; | |
6207 | int have_htm_tar = 0; | |
7cc46491 DJ |
6208 | int tdesc_wordsize = -1; |
6209 | const struct target_desc *tdesc = info.target_desc; | |
c1e1314d | 6210 | tdesc_arch_data_up tdesc_data; |
f949c649 | 6211 | int num_pseudoregs = 0; |
604c2f83 | 6212 | int cur_reg; |
7a78ae4e | 6213 | |
9aa1e687 | 6214 | from_xcoff_exec = info.abfd && info.abfd->format == bfd_object && |
7a78ae4e ND |
6215 | bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour; |
6216 | ||
9aa1e687 KB |
6217 | from_elf_exec = info.abfd && info.abfd->format == bfd_object && |
6218 | bfd_get_flavour (info.abfd) == bfd_target_elf_flavour; | |
6219 | ||
e712c1cf | 6220 | /* Check word size. If INFO is from a binary file, infer it from |
64366f1c | 6221 | that, else choose a likely default. */ |
9aa1e687 | 6222 | if (from_xcoff_exec) |
c906108c | 6223 | { |
11ed25ac | 6224 | if (bfd_xcoff_is_xcoff64 (info.abfd)) |
7a78ae4e ND |
6225 | wordsize = 8; |
6226 | else | |
6227 | wordsize = 4; | |
c906108c | 6228 | } |
9aa1e687 KB |
6229 | else if (from_elf_exec) |
6230 | { | |
6231 | if (elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
6232 | wordsize = 8; | |
6233 | else | |
6234 | wordsize = 4; | |
6235 | } | |
7cc46491 DJ |
6236 | else if (tdesc_has_registers (tdesc)) |
6237 | wordsize = -1; | |
c906108c | 6238 | else |
7a78ae4e | 6239 | { |
27b15785 | 6240 | if (info.bfd_arch_info != NULL && info.bfd_arch_info->bits_per_word != 0) |
16d8013c JB |
6241 | wordsize = (info.bfd_arch_info->bits_per_word |
6242 | / info.bfd_arch_info->bits_per_byte); | |
27b15785 KB |
6243 | else |
6244 | wordsize = 4; | |
7a78ae4e | 6245 | } |
c906108c | 6246 | |
475bbd17 JB |
6247 | /* Get the architecture and machine from the BFD. */ |
6248 | arch = info.bfd_arch_info->arch; | |
6249 | mach = info.bfd_arch_info->mach; | |
5bf1c677 EZ |
6250 | |
6251 | /* For e500 executables, the apuinfo section is of help here. Such | |
6252 | section contains the identifier and revision number of each | |
6253 | Application-specific Processing Unit that is present on the | |
6254 | chip. The content of the section is determined by the assembler | |
6255 | which looks at each instruction and determines which unit (and | |
74af9197 NF |
6256 | which version of it) can execute it. Grovel through the section |
6257 | looking for relevant e500 APUs. */ | |
5bf1c677 | 6258 | |
74af9197 | 6259 | if (bfd_uses_spe_extensions (info.abfd)) |
5bf1c677 | 6260 | { |
74af9197 NF |
6261 | arch = info.bfd_arch_info->arch; |
6262 | mach = bfd_mach_ppc_e500; | |
6263 | bfd_default_set_arch_mach (&abfd, arch, mach); | |
6264 | info.bfd_arch_info = bfd_get_arch_info (&abfd); | |
5bf1c677 EZ |
6265 | } |
6266 | ||
7cc46491 DJ |
6267 | /* Find a default target description which describes our register |
6268 | layout, if we do not already have one. */ | |
6269 | if (! tdesc_has_registers (tdesc)) | |
6270 | { | |
675127ec | 6271 | const struct ppc_variant *v; |
7cc46491 DJ |
6272 | |
6273 | /* Choose variant. */ | |
6274 | v = find_variant_by_arch (arch, mach); | |
6275 | if (!v) | |
6276 | return NULL; | |
6277 | ||
6278 | tdesc = *v->tdesc; | |
6279 | } | |
6280 | ||
6281 | gdb_assert (tdesc_has_registers (tdesc)); | |
6282 | ||
6283 | /* Check any target description for validity. */ | |
6284 | if (tdesc_has_registers (tdesc)) | |
6285 | { | |
6286 | static const char *const gprs[] = { | |
6287 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
6288 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
6289 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
6290 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" | |
6291 | }; | |
7cc46491 DJ |
6292 | const struct tdesc_feature *feature; |
6293 | int i, valid_p; | |
6294 | static const char *const msr_names[] = { "msr", "ps" }; | |
6295 | static const char *const cr_names[] = { "cr", "cnd" }; | |
6296 | static const char *const ctr_names[] = { "ctr", "cnt" }; | |
6297 | ||
6298 | feature = tdesc_find_feature (tdesc, | |
6299 | "org.gnu.gdb.power.core"); | |
6300 | if (feature == NULL) | |
6301 | return NULL; | |
6302 | ||
6303 | tdesc_data = tdesc_data_alloc (); | |
6304 | ||
6305 | valid_p = 1; | |
6306 | for (i = 0; i < ppc_num_gprs; i++) | |
c1e1314d TT |
6307 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
6308 | i, gprs[i]); | |
6309 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), | |
6310 | PPC_PC_REGNUM, "pc"); | |
6311 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), | |
6312 | PPC_LR_REGNUM, "lr"); | |
6313 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), | |
6314 | PPC_XER_REGNUM, "xer"); | |
7cc46491 DJ |
6315 | |
6316 | /* Allow alternate names for these registers, to accomodate GDB's | |
6317 | historic naming. */ | |
c1e1314d | 6318 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data.get (), |
7cc46491 | 6319 | PPC_MSR_REGNUM, msr_names); |
c1e1314d | 6320 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data.get (), |
7cc46491 | 6321 | PPC_CR_REGNUM, cr_names); |
c1e1314d | 6322 | valid_p &= tdesc_numbered_register_choices (feature, tdesc_data.get (), |
7cc46491 DJ |
6323 | PPC_CTR_REGNUM, ctr_names); |
6324 | ||
6325 | if (!valid_p) | |
c1e1314d | 6326 | return NULL; |
7cc46491 | 6327 | |
c1e1314d TT |
6328 | have_mq = tdesc_numbered_register (feature, tdesc_data.get (), |
6329 | PPC_MQ_REGNUM, "mq"); | |
7cc46491 | 6330 | |
12863263 | 6331 | tdesc_wordsize = tdesc_register_bitsize (feature, "pc") / 8; |
7cc46491 DJ |
6332 | if (wordsize == -1) |
6333 | wordsize = tdesc_wordsize; | |
6334 | ||
6335 | feature = tdesc_find_feature (tdesc, | |
6336 | "org.gnu.gdb.power.fpu"); | |
6337 | if (feature != NULL) | |
6338 | { | |
6339 | static const char *const fprs[] = { | |
6340 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
6341 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
6342 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
6343 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31" | |
6344 | }; | |
6345 | valid_p = 1; | |
6346 | for (i = 0; i < ppc_num_fprs; i++) | |
c1e1314d | 6347 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
7cc46491 | 6348 | PPC_F0_REGNUM + i, fprs[i]); |
c1e1314d | 6349 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
7cc46491 DJ |
6350 | PPC_FPSCR_REGNUM, "fpscr"); |
6351 | ||
6352 | if (!valid_p) | |
c1e1314d | 6353 | return NULL; |
7cc46491 | 6354 | have_fpu = 1; |
0fb2aaa1 PFC |
6355 | |
6356 | /* The fpscr register was expanded in isa 2.05 to 64 bits | |
6357 | along with the addition of the decimal floating point | |
6358 | facility. */ | |
12863263 | 6359 | if (tdesc_register_bitsize (feature, "fpscr") > 32) |
0fb2aaa1 | 6360 | have_dfp = 1; |
7cc46491 DJ |
6361 | } |
6362 | else | |
6363 | have_fpu = 0; | |
6364 | ||
6365 | feature = tdesc_find_feature (tdesc, | |
6366 | "org.gnu.gdb.power.altivec"); | |
6367 | if (feature != NULL) | |
6368 | { | |
6369 | static const char *const vector_regs[] = { | |
6370 | "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7", | |
6371 | "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15", | |
6372 | "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23", | |
6373 | "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31" | |
6374 | }; | |
6375 | ||
6376 | valid_p = 1; | |
6377 | for (i = 0; i < ppc_num_gprs; i++) | |
c1e1314d | 6378 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
7cc46491 DJ |
6379 | PPC_VR0_REGNUM + i, |
6380 | vector_regs[i]); | |
c1e1314d | 6381 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
7cc46491 | 6382 | PPC_VSCR_REGNUM, "vscr"); |
c1e1314d | 6383 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
7cc46491 DJ |
6384 | PPC_VRSAVE_REGNUM, "vrsave"); |
6385 | ||
6386 | if (have_spe || !valid_p) | |
c1e1314d | 6387 | return NULL; |
7cc46491 DJ |
6388 | have_altivec = 1; |
6389 | } | |
6390 | else | |
6391 | have_altivec = 0; | |
6392 | ||
604c2f83 LM |
6393 | /* Check for POWER7 VSX registers support. */ |
6394 | feature = tdesc_find_feature (tdesc, | |
6395 | "org.gnu.gdb.power.vsx"); | |
6396 | ||
6397 | if (feature != NULL) | |
6398 | { | |
6399 | static const char *const vsx_regs[] = { | |
6400 | "vs0h", "vs1h", "vs2h", "vs3h", "vs4h", "vs5h", | |
6401 | "vs6h", "vs7h", "vs8h", "vs9h", "vs10h", "vs11h", | |
6402 | "vs12h", "vs13h", "vs14h", "vs15h", "vs16h", "vs17h", | |
6403 | "vs18h", "vs19h", "vs20h", "vs21h", "vs22h", "vs23h", | |
6404 | "vs24h", "vs25h", "vs26h", "vs27h", "vs28h", "vs29h", | |
6405 | "vs30h", "vs31h" | |
6406 | }; | |
6407 | ||
6408 | valid_p = 1; | |
6409 | ||
6410 | for (i = 0; i < ppc_num_vshrs; i++) | |
c1e1314d | 6411 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
604c2f83 LM |
6412 | PPC_VSR0_UPPER_REGNUM + i, |
6413 | vsx_regs[i]); | |
81ab84fd PFC |
6414 | |
6415 | if (!valid_p || !have_fpu || !have_altivec) | |
c1e1314d | 6416 | return NULL; |
604c2f83 LM |
6417 | |
6418 | have_vsx = 1; | |
6419 | } | |
6420 | else | |
6421 | have_vsx = 0; | |
6422 | ||
7cc46491 DJ |
6423 | /* On machines supporting the SPE APU, the general-purpose registers |
6424 | are 64 bits long. There are SIMD vector instructions to treat them | |
6425 | as pairs of floats, but the rest of the instruction set treats them | |
6426 | as 32-bit registers, and only operates on their lower halves. | |
6427 | ||
6428 | In the GDB regcache, we treat their high and low halves as separate | |
6429 | registers. The low halves we present as the general-purpose | |
6430 | registers, and then we have pseudo-registers that stitch together | |
6431 | the upper and lower halves and present them as pseudo-registers. | |
6432 | ||
6433 | Thus, the target description is expected to supply the upper | |
6434 | halves separately. */ | |
6435 | ||
6436 | feature = tdesc_find_feature (tdesc, | |
6437 | "org.gnu.gdb.power.spe"); | |
6438 | if (feature != NULL) | |
6439 | { | |
6440 | static const char *const upper_spe[] = { | |
6441 | "ev0h", "ev1h", "ev2h", "ev3h", | |
6442 | "ev4h", "ev5h", "ev6h", "ev7h", | |
6443 | "ev8h", "ev9h", "ev10h", "ev11h", | |
6444 | "ev12h", "ev13h", "ev14h", "ev15h", | |
6445 | "ev16h", "ev17h", "ev18h", "ev19h", | |
6446 | "ev20h", "ev21h", "ev22h", "ev23h", | |
6447 | "ev24h", "ev25h", "ev26h", "ev27h", | |
6448 | "ev28h", "ev29h", "ev30h", "ev31h" | |
6449 | }; | |
6450 | ||
6451 | valid_p = 1; | |
6452 | for (i = 0; i < ppc_num_gprs; i++) | |
c1e1314d | 6453 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
7cc46491 DJ |
6454 | PPC_SPE_UPPER_GP0_REGNUM + i, |
6455 | upper_spe[i]); | |
c1e1314d | 6456 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
7cc46491 | 6457 | PPC_SPE_ACC_REGNUM, "acc"); |
c1e1314d | 6458 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
7cc46491 DJ |
6459 | PPC_SPE_FSCR_REGNUM, "spefscr"); |
6460 | ||
6461 | if (have_mq || have_fpu || !valid_p) | |
c1e1314d | 6462 | return NULL; |
7cc46491 DJ |
6463 | have_spe = 1; |
6464 | } | |
6465 | else | |
6466 | have_spe = 0; | |
7ca18ed6 EBM |
6467 | |
6468 | /* Program Priority Register. */ | |
6469 | feature = tdesc_find_feature (tdesc, | |
6470 | "org.gnu.gdb.power.ppr"); | |
6471 | if (feature != NULL) | |
6472 | { | |
6473 | valid_p = 1; | |
c1e1314d | 6474 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
7ca18ed6 EBM |
6475 | PPC_PPR_REGNUM, "ppr"); |
6476 | ||
6477 | if (!valid_p) | |
c1e1314d | 6478 | return NULL; |
7ca18ed6 EBM |
6479 | have_ppr = 1; |
6480 | } | |
6481 | else | |
6482 | have_ppr = 0; | |
6483 | ||
6484 | /* Data Stream Control Register. */ | |
6485 | feature = tdesc_find_feature (tdesc, | |
6486 | "org.gnu.gdb.power.dscr"); | |
6487 | if (feature != NULL) | |
6488 | { | |
6489 | valid_p = 1; | |
c1e1314d | 6490 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
7ca18ed6 EBM |
6491 | PPC_DSCR_REGNUM, "dscr"); |
6492 | ||
6493 | if (!valid_p) | |
c1e1314d | 6494 | return NULL; |
7ca18ed6 EBM |
6495 | have_dscr = 1; |
6496 | } | |
6497 | else | |
6498 | have_dscr = 0; | |
f2cf6173 EBM |
6499 | |
6500 | /* Target Address Register. */ | |
6501 | feature = tdesc_find_feature (tdesc, | |
6502 | "org.gnu.gdb.power.tar"); | |
6503 | if (feature != NULL) | |
6504 | { | |
6505 | valid_p = 1; | |
c1e1314d | 6506 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
f2cf6173 EBM |
6507 | PPC_TAR_REGNUM, "tar"); |
6508 | ||
6509 | if (!valid_p) | |
c1e1314d | 6510 | return NULL; |
f2cf6173 EBM |
6511 | have_tar = 1; |
6512 | } | |
6513 | else | |
6514 | have_tar = 0; | |
232bfb86 EBM |
6515 | |
6516 | /* Event-based Branching Registers. */ | |
6517 | feature = tdesc_find_feature (tdesc, | |
6518 | "org.gnu.gdb.power.ebb"); | |
6519 | if (feature != NULL) | |
6520 | { | |
6521 | static const char *const ebb_regs[] = { | |
6522 | "bescr", "ebbhr", "ebbrr" | |
6523 | }; | |
6524 | ||
6525 | valid_p = 1; | |
6526 | for (i = 0; i < ARRAY_SIZE (ebb_regs); i++) | |
c1e1314d | 6527 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
232bfb86 EBM |
6528 | PPC_BESCR_REGNUM + i, |
6529 | ebb_regs[i]); | |
6530 | if (!valid_p) | |
c1e1314d | 6531 | return NULL; |
232bfb86 EBM |
6532 | have_ebb = 1; |
6533 | } | |
6534 | else | |
6535 | have_ebb = 0; | |
6536 | ||
6537 | /* Subset of the ISA 2.07 Performance Monitor Registers provided | |
6538 | by Linux. */ | |
6539 | feature = tdesc_find_feature (tdesc, | |
6540 | "org.gnu.gdb.power.linux.pmu"); | |
6541 | if (feature != NULL) | |
6542 | { | |
6543 | valid_p = 1; | |
6544 | ||
c1e1314d | 6545 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
232bfb86 EBM |
6546 | PPC_MMCR0_REGNUM, |
6547 | "mmcr0"); | |
c1e1314d | 6548 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
232bfb86 EBM |
6549 | PPC_MMCR2_REGNUM, |
6550 | "mmcr2"); | |
c1e1314d | 6551 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
232bfb86 EBM |
6552 | PPC_SIAR_REGNUM, |
6553 | "siar"); | |
c1e1314d | 6554 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
232bfb86 EBM |
6555 | PPC_SDAR_REGNUM, |
6556 | "sdar"); | |
c1e1314d | 6557 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
232bfb86 EBM |
6558 | PPC_SIER_REGNUM, |
6559 | "sier"); | |
6560 | ||
6561 | if (!valid_p) | |
c1e1314d | 6562 | return NULL; |
232bfb86 EBM |
6563 | have_pmu = 1; |
6564 | } | |
6565 | else | |
6566 | have_pmu = 0; | |
8d619c01 EBM |
6567 | |
6568 | /* Hardware Transactional Memory Registers. */ | |
6569 | feature = tdesc_find_feature (tdesc, | |
6570 | "org.gnu.gdb.power.htm.spr"); | |
6571 | if (feature != NULL) | |
6572 | { | |
6573 | static const char *const tm_spr_regs[] = { | |
6574 | "tfhar", "texasr", "tfiar" | |
6575 | }; | |
6576 | ||
6577 | valid_p = 1; | |
6578 | for (i = 0; i < ARRAY_SIZE (tm_spr_regs); i++) | |
c1e1314d | 6579 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
8d619c01 EBM |
6580 | PPC_TFHAR_REGNUM + i, |
6581 | tm_spr_regs[i]); | |
6582 | if (!valid_p) | |
c1e1314d | 6583 | return NULL; |
8d619c01 EBM |
6584 | |
6585 | have_htm_spr = 1; | |
6586 | } | |
6587 | else | |
6588 | have_htm_spr = 0; | |
6589 | ||
6590 | feature = tdesc_find_feature (tdesc, | |
6591 | "org.gnu.gdb.power.htm.core"); | |
6592 | if (feature != NULL) | |
6593 | { | |
6594 | static const char *const cgprs[] = { | |
6595 | "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", | |
6596 | "cr8", "cr9", "cr10", "cr11", "cr12", "cr13", "cr14", | |
6597 | "cr15", "cr16", "cr17", "cr18", "cr19", "cr20", "cr21", | |
6598 | "cr22", "cr23", "cr24", "cr25", "cr26", "cr27", "cr28", | |
6599 | "cr29", "cr30", "cr31", "ccr", "cxer", "clr", "cctr" | |
6600 | }; | |
6601 | ||
6602 | valid_p = 1; | |
6603 | ||
6604 | for (i = 0; i < ARRAY_SIZE (cgprs); i++) | |
c1e1314d | 6605 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
8d619c01 EBM |
6606 | PPC_CR0_REGNUM + i, |
6607 | cgprs[i]); | |
6608 | if (!valid_p) | |
c1e1314d | 6609 | return NULL; |
8d619c01 EBM |
6610 | |
6611 | have_htm_core = 1; | |
6612 | } | |
6613 | else | |
6614 | have_htm_core = 0; | |
6615 | ||
6616 | feature = tdesc_find_feature (tdesc, | |
6617 | "org.gnu.gdb.power.htm.fpu"); | |
6618 | if (feature != NULL) | |
6619 | { | |
6620 | valid_p = 1; | |
6621 | ||
6622 | static const char *const cfprs[] = { | |
6623 | "cf0", "cf1", "cf2", "cf3", "cf4", "cf5", "cf6", "cf7", | |
6624 | "cf8", "cf9", "cf10", "cf11", "cf12", "cf13", "cf14", "cf15", | |
6625 | "cf16", "cf17", "cf18", "cf19", "cf20", "cf21", "cf22", | |
6626 | "cf23", "cf24", "cf25", "cf26", "cf27", "cf28", "cf29", | |
6627 | "cf30", "cf31", "cfpscr" | |
6628 | }; | |
6629 | ||
6630 | for (i = 0; i < ARRAY_SIZE (cfprs); i++) | |
c1e1314d | 6631 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
8d619c01 EBM |
6632 | PPC_CF0_REGNUM + i, |
6633 | cfprs[i]); | |
6634 | ||
6635 | if (!valid_p) | |
c1e1314d | 6636 | return NULL; |
8d619c01 EBM |
6637 | have_htm_fpu = 1; |
6638 | } | |
6639 | else | |
6640 | have_htm_fpu = 0; | |
6641 | ||
6642 | feature = tdesc_find_feature (tdesc, | |
6643 | "org.gnu.gdb.power.htm.altivec"); | |
6644 | if (feature != NULL) | |
6645 | { | |
6646 | valid_p = 1; | |
6647 | ||
6648 | static const char *const cvmx[] = { | |
6649 | "cvr0", "cvr1", "cvr2", "cvr3", "cvr4", "cvr5", "cvr6", | |
6650 | "cvr7", "cvr8", "cvr9", "cvr10", "cvr11", "cvr12", "cvr13", | |
6651 | "cvr14", "cvr15","cvr16", "cvr17", "cvr18", "cvr19", "cvr20", | |
6652 | "cvr21", "cvr22", "cvr23", "cvr24", "cvr25", "cvr26", | |
6653 | "cvr27", "cvr28", "cvr29", "cvr30", "cvr31", "cvscr", | |
6654 | "cvrsave" | |
6655 | }; | |
6656 | ||
6657 | for (i = 0; i < ARRAY_SIZE (cvmx); i++) | |
c1e1314d | 6658 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
8d619c01 EBM |
6659 | PPC_CVR0_REGNUM + i, |
6660 | cvmx[i]); | |
6661 | ||
6662 | if (!valid_p) | |
c1e1314d | 6663 | return NULL; |
8d619c01 EBM |
6664 | have_htm_altivec = 1; |
6665 | } | |
6666 | else | |
6667 | have_htm_altivec = 0; | |
6668 | ||
6669 | feature = tdesc_find_feature (tdesc, | |
6670 | "org.gnu.gdb.power.htm.vsx"); | |
6671 | if (feature != NULL) | |
6672 | { | |
6673 | valid_p = 1; | |
6674 | ||
6675 | static const char *const cvsx[] = { | |
6676 | "cvs0h", "cvs1h", "cvs2h", "cvs3h", "cvs4h", "cvs5h", | |
6677 | "cvs6h", "cvs7h", "cvs8h", "cvs9h", "cvs10h", "cvs11h", | |
6678 | "cvs12h", "cvs13h", "cvs14h", "cvs15h", "cvs16h", "cvs17h", | |
6679 | "cvs18h", "cvs19h", "cvs20h", "cvs21h", "cvs22h", "cvs23h", | |
6680 | "cvs24h", "cvs25h", "cvs26h", "cvs27h", "cvs28h", "cvs29h", | |
6681 | "cvs30h", "cvs31h" | |
6682 | }; | |
6683 | ||
6684 | for (i = 0; i < ARRAY_SIZE (cvsx); i++) | |
c1e1314d | 6685 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
8d619c01 EBM |
6686 | (PPC_CVSR0_UPPER_REGNUM |
6687 | + i), | |
6688 | cvsx[i]); | |
6689 | ||
6690 | if (!valid_p || !have_htm_fpu || !have_htm_altivec) | |
c1e1314d | 6691 | return NULL; |
8d619c01 EBM |
6692 | have_htm_vsx = 1; |
6693 | } | |
6694 | else | |
6695 | have_htm_vsx = 0; | |
6696 | ||
6697 | feature = tdesc_find_feature (tdesc, | |
6698 | "org.gnu.gdb.power.htm.ppr"); | |
6699 | if (feature != NULL) | |
6700 | { | |
c1e1314d | 6701 | valid_p = tdesc_numbered_register (feature, tdesc_data.get (), |
8d619c01 EBM |
6702 | PPC_CPPR_REGNUM, "cppr"); |
6703 | ||
6704 | if (!valid_p) | |
c1e1314d | 6705 | return NULL; |
8d619c01 EBM |
6706 | have_htm_ppr = 1; |
6707 | } | |
6708 | else | |
6709 | have_htm_ppr = 0; | |
6710 | ||
6711 | feature = tdesc_find_feature (tdesc, | |
6712 | "org.gnu.gdb.power.htm.dscr"); | |
6713 | if (feature != NULL) | |
6714 | { | |
c1e1314d | 6715 | valid_p = tdesc_numbered_register (feature, tdesc_data.get (), |
8d619c01 EBM |
6716 | PPC_CDSCR_REGNUM, "cdscr"); |
6717 | ||
6718 | if (!valid_p) | |
c1e1314d | 6719 | return NULL; |
8d619c01 EBM |
6720 | have_htm_dscr = 1; |
6721 | } | |
6722 | else | |
6723 | have_htm_dscr = 0; | |
6724 | ||
6725 | feature = tdesc_find_feature (tdesc, | |
6726 | "org.gnu.gdb.power.htm.tar"); | |
6727 | if (feature != NULL) | |
6728 | { | |
c1e1314d | 6729 | valid_p = tdesc_numbered_register (feature, tdesc_data.get (), |
8d619c01 EBM |
6730 | PPC_CTAR_REGNUM, "ctar"); |
6731 | ||
6732 | if (!valid_p) | |
c1e1314d | 6733 | return NULL; |
8d619c01 EBM |
6734 | have_htm_tar = 1; |
6735 | } | |
6736 | else | |
6737 | have_htm_tar = 0; | |
7cc46491 DJ |
6738 | } |
6739 | ||
6740 | /* If we have a 64-bit binary on a 32-bit target, complain. Also | |
6741 | complain for a 32-bit binary on a 64-bit target; we do not yet | |
6742 | support that. For instance, the 32-bit ABI routines expect | |
6743 | 32-bit GPRs. | |
6744 | ||
6745 | As long as there isn't an explicit target description, we'll | |
6746 | choose one based on the BFD architecture and get a word size | |
6747 | matching the binary (probably powerpc:common or | |
6748 | powerpc:common64). So there is only trouble if a 64-bit target | |
6749 | supplies a 64-bit description while debugging a 32-bit | |
6750 | binary. */ | |
6751 | if (tdesc_wordsize != -1 && tdesc_wordsize != wordsize) | |
c1e1314d | 6752 | return NULL; |
7cc46491 | 6753 | |
55eddb0f | 6754 | #ifdef HAVE_ELF |
cd453cd0 UW |
6755 | if (from_elf_exec) |
6756 | { | |
6757 | switch (elf_elfheader (info.abfd)->e_flags & EF_PPC64_ABI) | |
6758 | { | |
6759 | case 1: | |
6760 | elf_abi = POWERPC_ELF_V1; | |
6761 | break; | |
6762 | case 2: | |
6763 | elf_abi = POWERPC_ELF_V2; | |
6764 | break; | |
6765 | default: | |
6766 | break; | |
6767 | } | |
6768 | } | |
6769 | ||
55eddb0f DJ |
6770 | if (soft_float_flag == AUTO_BOOLEAN_AUTO && from_elf_exec) |
6771 | { | |
6772 | switch (bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU, | |
ed0f4273 | 6773 | Tag_GNU_Power_ABI_FP) & 3) |
55eddb0f DJ |
6774 | { |
6775 | case 1: | |
6776 | soft_float_flag = AUTO_BOOLEAN_FALSE; | |
6777 | break; | |
6778 | case 2: | |
6779 | soft_float_flag = AUTO_BOOLEAN_TRUE; | |
6780 | break; | |
6781 | default: | |
6782 | break; | |
6783 | } | |
6784 | } | |
6785 | ||
ed0f4273 UW |
6786 | if (long_double_abi == POWERPC_LONG_DOUBLE_AUTO && from_elf_exec) |
6787 | { | |
6788 | switch (bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU, | |
6789 | Tag_GNU_Power_ABI_FP) >> 2) | |
6790 | { | |
6791 | case 1: | |
6792 | long_double_abi = POWERPC_LONG_DOUBLE_IBM128; | |
6793 | break; | |
6794 | case 3: | |
6795 | long_double_abi = POWERPC_LONG_DOUBLE_IEEE128; | |
6796 | break; | |
6797 | default: | |
6798 | break; | |
6799 | } | |
6800 | } | |
6801 | ||
55eddb0f DJ |
6802 | if (vector_abi == POWERPC_VEC_AUTO && from_elf_exec) |
6803 | { | |
6804 | switch (bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU, | |
6805 | Tag_GNU_Power_ABI_Vector)) | |
6806 | { | |
6807 | case 1: | |
6808 | vector_abi = POWERPC_VEC_GENERIC; | |
6809 | break; | |
6810 | case 2: | |
6811 | vector_abi = POWERPC_VEC_ALTIVEC; | |
6812 | break; | |
6813 | case 3: | |
6814 | vector_abi = POWERPC_VEC_SPE; | |
6815 | break; | |
6816 | default: | |
6817 | break; | |
6818 | } | |
6819 | } | |
6820 | #endif | |
6821 | ||
cd453cd0 UW |
6822 | /* At this point, the only supported ELF-based 64-bit little-endian |
6823 | operating system is GNU/Linux, and this uses the ELFv2 ABI by | |
6824 | default. All other supported ELF-based operating systems use the | |
6825 | ELFv1 ABI by default. Therefore, if the ABI marker is missing, | |
6826 | e.g. because we run a legacy binary, or have attached to a process | |
6827 | and have not found any associated binary file, set the default | |
6828 | according to this heuristic. */ | |
6829 | if (elf_abi == POWERPC_ELF_AUTO) | |
6830 | { | |
6831 | if (wordsize == 8 && info.byte_order == BFD_ENDIAN_LITTLE) | |
dda83cd7 | 6832 | elf_abi = POWERPC_ELF_V2; |
cd453cd0 | 6833 | else |
dda83cd7 | 6834 | elf_abi = POWERPC_ELF_V1; |
cd453cd0 UW |
6835 | } |
6836 | ||
55eddb0f DJ |
6837 | if (soft_float_flag == AUTO_BOOLEAN_TRUE) |
6838 | soft_float = 1; | |
6839 | else if (soft_float_flag == AUTO_BOOLEAN_FALSE) | |
6840 | soft_float = 0; | |
6841 | else | |
6842 | soft_float = !have_fpu; | |
6843 | ||
6844 | /* If we have a hard float binary or setting but no floating point | |
6845 | registers, downgrade to soft float anyway. We're still somewhat | |
6846 | useful in this scenario. */ | |
6847 | if (!soft_float && !have_fpu) | |
6848 | soft_float = 1; | |
6849 | ||
6850 | /* Similarly for vector registers. */ | |
6851 | if (vector_abi == POWERPC_VEC_ALTIVEC && !have_altivec) | |
6852 | vector_abi = POWERPC_VEC_GENERIC; | |
6853 | ||
6854 | if (vector_abi == POWERPC_VEC_SPE && !have_spe) | |
6855 | vector_abi = POWERPC_VEC_GENERIC; | |
6856 | ||
6857 | if (vector_abi == POWERPC_VEC_AUTO) | |
6858 | { | |
6859 | if (have_altivec) | |
6860 | vector_abi = POWERPC_VEC_ALTIVEC; | |
6861 | else if (have_spe) | |
6862 | vector_abi = POWERPC_VEC_SPE; | |
6863 | else | |
6864 | vector_abi = POWERPC_VEC_GENERIC; | |
6865 | } | |
6866 | ||
6867 | /* Do not limit the vector ABI based on available hardware, since we | |
6868 | do not yet know what hardware we'll decide we have. Yuck! FIXME! */ | |
6869 | ||
7cc46491 DJ |
6870 | /* Find a candidate among extant architectures. */ |
6871 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
6872 | arches != NULL; | |
6873 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
6874 | { | |
6875 | /* Word size in the various PowerPC bfd_arch_info structs isn't | |
dda83cd7 SM |
6876 | meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform |
6877 | separate word size check. */ | |
7cc46491 | 6878 | tdep = gdbarch_tdep (arches->gdbarch); |
cd453cd0 UW |
6879 | if (tdep && tdep->elf_abi != elf_abi) |
6880 | continue; | |
55eddb0f DJ |
6881 | if (tdep && tdep->soft_float != soft_float) |
6882 | continue; | |
ed0f4273 UW |
6883 | if (tdep && tdep->long_double_abi != long_double_abi) |
6884 | continue; | |
55eddb0f DJ |
6885 | if (tdep && tdep->vector_abi != vector_abi) |
6886 | continue; | |
7cc46491 | 6887 | if (tdep && tdep->wordsize == wordsize) |
c1e1314d | 6888 | return arches->gdbarch; |
7cc46491 DJ |
6889 | } |
6890 | ||
6891 | /* None found, create a new architecture from INFO, whose bfd_arch_info | |
6892 | validity depends on the source: | |
6893 | - executable useless | |
6894 | - rs6000_host_arch() good | |
6895 | - core file good | |
6896 | - "set arch" trust blindly | |
6897 | - GDB startup useless but harmless */ | |
6898 | ||
fc270c35 | 6899 | tdep = XCNEW (struct gdbarch_tdep); |
7cc46491 | 6900 | tdep->wordsize = wordsize; |
cd453cd0 | 6901 | tdep->elf_abi = elf_abi; |
55eddb0f | 6902 | tdep->soft_float = soft_float; |
ed0f4273 | 6903 | tdep->long_double_abi = long_double_abi; |
55eddb0f | 6904 | tdep->vector_abi = vector_abi; |
7cc46491 | 6905 | |
7a78ae4e | 6906 | gdbarch = gdbarch_alloc (&info, tdep); |
7a78ae4e | 6907 | |
7cc46491 DJ |
6908 | tdep->ppc_gp0_regnum = PPC_R0_REGNUM; |
6909 | tdep->ppc_toc_regnum = PPC_R0_REGNUM + 2; | |
6910 | tdep->ppc_ps_regnum = PPC_MSR_REGNUM; | |
6911 | tdep->ppc_cr_regnum = PPC_CR_REGNUM; | |
6912 | tdep->ppc_lr_regnum = PPC_LR_REGNUM; | |
6913 | tdep->ppc_ctr_regnum = PPC_CTR_REGNUM; | |
6914 | tdep->ppc_xer_regnum = PPC_XER_REGNUM; | |
6915 | tdep->ppc_mq_regnum = have_mq ? PPC_MQ_REGNUM : -1; | |
6916 | ||
6917 | tdep->ppc_fp0_regnum = have_fpu ? PPC_F0_REGNUM : -1; | |
6918 | tdep->ppc_fpscr_regnum = have_fpu ? PPC_FPSCR_REGNUM : -1; | |
604c2f83 | 6919 | tdep->ppc_vsr0_upper_regnum = have_vsx ? PPC_VSR0_UPPER_REGNUM : -1; |
7cc46491 DJ |
6920 | tdep->ppc_vr0_regnum = have_altivec ? PPC_VR0_REGNUM : -1; |
6921 | tdep->ppc_vrsave_regnum = have_altivec ? PPC_VRSAVE_REGNUM : -1; | |
6922 | tdep->ppc_ev0_upper_regnum = have_spe ? PPC_SPE_UPPER_GP0_REGNUM : -1; | |
6923 | tdep->ppc_acc_regnum = have_spe ? PPC_SPE_ACC_REGNUM : -1; | |
6924 | tdep->ppc_spefscr_regnum = have_spe ? PPC_SPE_FSCR_REGNUM : -1; | |
7ca18ed6 EBM |
6925 | tdep->ppc_ppr_regnum = have_ppr ? PPC_PPR_REGNUM : -1; |
6926 | tdep->ppc_dscr_regnum = have_dscr ? PPC_DSCR_REGNUM : -1; | |
f2cf6173 | 6927 | tdep->ppc_tar_regnum = have_tar ? PPC_TAR_REGNUM : -1; |
232bfb86 EBM |
6928 | tdep->have_ebb = have_ebb; |
6929 | ||
6930 | /* If additional pmu registers are added, care must be taken when | |
6931 | setting new fields in the tdep below, to maintain compatibility | |
6932 | with features that only provide some of the registers. Currently | |
6933 | gdb access to the pmu registers is only supported in linux, and | |
6934 | linux only provides a subset of the pmu registers defined in the | |
6935 | architecture. */ | |
6936 | ||
6937 | tdep->ppc_mmcr0_regnum = have_pmu ? PPC_MMCR0_REGNUM : -1; | |
6938 | tdep->ppc_mmcr2_regnum = have_pmu ? PPC_MMCR2_REGNUM : -1; | |
6939 | tdep->ppc_siar_regnum = have_pmu ? PPC_SIAR_REGNUM : -1; | |
6940 | tdep->ppc_sdar_regnum = have_pmu ? PPC_SDAR_REGNUM : -1; | |
6941 | tdep->ppc_sier_regnum = have_pmu ? PPC_SIER_REGNUM : -1; | |
7cc46491 | 6942 | |
8d619c01 EBM |
6943 | tdep->have_htm_spr = have_htm_spr; |
6944 | tdep->have_htm_core = have_htm_core; | |
6945 | tdep->have_htm_fpu = have_htm_fpu; | |
6946 | tdep->have_htm_altivec = have_htm_altivec; | |
6947 | tdep->have_htm_vsx = have_htm_vsx; | |
6948 | tdep->ppc_cppr_regnum = have_htm_ppr ? PPC_CPPR_REGNUM : -1; | |
6949 | tdep->ppc_cdscr_regnum = have_htm_dscr ? PPC_CDSCR_REGNUM : -1; | |
6950 | tdep->ppc_ctar_regnum = have_htm_tar ? PPC_CTAR_REGNUM : -1; | |
6951 | ||
7cc46491 DJ |
6952 | set_gdbarch_pc_regnum (gdbarch, PPC_PC_REGNUM); |
6953 | set_gdbarch_sp_regnum (gdbarch, PPC_R0_REGNUM + 1); | |
7cc46491 | 6954 | set_gdbarch_fp0_regnum (gdbarch, tdep->ppc_fp0_regnum); |
9f643768 | 6955 | set_gdbarch_register_sim_regno (gdbarch, rs6000_register_sim_regno); |
7cc46491 DJ |
6956 | |
6957 | /* The XML specification for PowerPC sensibly calls the MSR "msr". | |
6958 | GDB traditionally called it "ps", though, so let GDB add an | |
6959 | alias. */ | |
6960 | set_gdbarch_ps_regnum (gdbarch, tdep->ppc_ps_regnum); | |
6961 | ||
4a7622d1 | 6962 | if (wordsize == 8) |
05580c65 | 6963 | set_gdbarch_return_value (gdbarch, ppc64_sysv_abi_return_value); |
afd48b75 | 6964 | else |
4a7622d1 | 6965 | set_gdbarch_return_value (gdbarch, ppc_sysv_abi_return_value); |
c8001721 | 6966 | |
baffbae0 JB |
6967 | /* Set lr_frame_offset. */ |
6968 | if (wordsize == 8) | |
6969 | tdep->lr_frame_offset = 16; | |
baffbae0 | 6970 | else |
4a7622d1 | 6971 | tdep->lr_frame_offset = 4; |
baffbae0 | 6972 | |
6f072a10 PFC |
6973 | if (have_spe || have_dfp || have_altivec |
6974 | || have_vsx || have_htm_fpu || have_htm_vsx) | |
7cc46491 | 6975 | { |
f949c649 | 6976 | set_gdbarch_pseudo_register_read (gdbarch, rs6000_pseudo_register_read); |
0df8b418 MS |
6977 | set_gdbarch_pseudo_register_write (gdbarch, |
6978 | rs6000_pseudo_register_write); | |
2a2fa07b MK |
6979 | set_gdbarch_ax_pseudo_register_collect (gdbarch, |
6980 | rs6000_ax_pseudo_register_collect); | |
7cc46491 | 6981 | } |
1fcc0bb8 | 6982 | |
a67914de MK |
6983 | set_gdbarch_gen_return_address (gdbarch, rs6000_gen_return_address); |
6984 | ||
e0d24f8d WZ |
6985 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); |
6986 | ||
5a9e69ba | 6987 | set_gdbarch_num_regs (gdbarch, PPC_NUM_REGS); |
f949c649 TJB |
6988 | |
6989 | if (have_spe) | |
6990 | num_pseudoregs += 32; | |
6991 | if (have_dfp) | |
6992 | num_pseudoregs += 16; | |
6f072a10 PFC |
6993 | if (have_altivec) |
6994 | num_pseudoregs += 32; | |
604c2f83 LM |
6995 | if (have_vsx) |
6996 | /* Include both VSX and Extended FP registers. */ | |
6997 | num_pseudoregs += 96; | |
8d619c01 EBM |
6998 | if (have_htm_fpu) |
6999 | num_pseudoregs += 16; | |
7000 | /* Include both checkpointed VSX and EFP registers. */ | |
7001 | if (have_htm_vsx) | |
7002 | num_pseudoregs += 64 + 32; | |
f949c649 TJB |
7003 | |
7004 | set_gdbarch_num_pseudo_regs (gdbarch, num_pseudoregs); | |
7a78ae4e ND |
7005 | |
7006 | set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT); | |
7007 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); | |
7008 | set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
7009 | set_gdbarch_long_bit (gdbarch, wordsize * TARGET_CHAR_BIT); | |
7010 | set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
7011 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
7012 | set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
4a7622d1 | 7013 | set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT); |
4e409299 | 7014 | set_gdbarch_char_signed (gdbarch, 0); |
7a78ae4e | 7015 | |
11269d7e | 7016 | set_gdbarch_frame_align (gdbarch, rs6000_frame_align); |
4a7622d1 | 7017 | if (wordsize == 8) |
8b148df9 AC |
7018 | /* PPC64 SYSV. */ |
7019 | set_gdbarch_frame_red_zone_size (gdbarch, 288); | |
7a78ae4e | 7020 | |
691d145a JB |
7021 | set_gdbarch_convert_register_p (gdbarch, rs6000_convert_register_p); |
7022 | set_gdbarch_register_to_value (gdbarch, rs6000_register_to_value); | |
7023 | set_gdbarch_value_to_register (gdbarch, rs6000_value_to_register); | |
7024 | ||
18ed0c4e JB |
7025 | set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_stab_reg_to_regnum); |
7026 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rs6000_dwarf2_reg_to_regnum); | |
d217aaed | 7027 | |
4a7622d1 | 7028 | if (wordsize == 4) |
77b2b6d4 | 7029 | set_gdbarch_push_dummy_call (gdbarch, ppc_sysv_abi_push_dummy_call); |
4a7622d1 | 7030 | else if (wordsize == 8) |
8be9034a | 7031 | set_gdbarch_push_dummy_call (gdbarch, ppc64_sysv_abi_push_dummy_call); |
7a78ae4e | 7032 | |
7a78ae4e | 7033 | set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue); |
c9cf6e20 | 7034 | set_gdbarch_stack_frame_destroyed_p (gdbarch, rs6000_stack_frame_destroyed_p); |
8ab3d180 | 7035 | set_gdbarch_skip_main_prologue (gdbarch, rs6000_skip_main_prologue); |
0d1243d9 | 7036 | |
7a78ae4e | 7037 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
04180708 YQ |
7038 | |
7039 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, | |
7040 | rs6000_breakpoint::kind_from_pc); | |
7041 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, | |
7042 | rs6000_breakpoint::bp_from_kind); | |
7a78ae4e | 7043 | |
203c3895 | 7044 | /* The value of symbols of type N_SO and N_FUN maybe null when |
0df8b418 | 7045 | it shouldn't be. */ |
203c3895 UW |
7046 | set_gdbarch_sofun_address_maybe_missing (gdbarch, 1); |
7047 | ||
ce5eab59 | 7048 | /* Handles single stepping of atomic sequences. */ |
4a7622d1 | 7049 | set_gdbarch_software_single_step (gdbarch, ppc_deal_with_atomic_sequence); |
ce5eab59 | 7050 | |
0df8b418 | 7051 | /* Not sure on this. FIXMEmgo */ |
7a78ae4e ND |
7052 | set_gdbarch_frame_args_skip (gdbarch, 8); |
7053 | ||
143985b7 AF |
7054 | /* Helpers for function argument information. */ |
7055 | set_gdbarch_fetch_pointer_argument (gdbarch, rs6000_fetch_pointer_argument); | |
7056 | ||
6f7f3f0d UW |
7057 | /* Trampoline. */ |
7058 | set_gdbarch_in_solib_return_trampoline | |
7059 | (gdbarch, rs6000_in_solib_return_trampoline); | |
7060 | set_gdbarch_skip_trampoline_code (gdbarch, rs6000_skip_trampoline_code); | |
7061 | ||
4fc771b8 | 7062 | /* Hook in the DWARF CFI frame unwinder. */ |
1af5d7ce | 7063 | dwarf2_append_unwinders (gdbarch); |
4fc771b8 DJ |
7064 | dwarf2_frame_set_adjust_regnum (gdbarch, rs6000_adjust_frame_regnum); |
7065 | ||
9274a07c LM |
7066 | /* Frame handling. */ |
7067 | dwarf2_frame_set_init_reg (gdbarch, ppc_dwarf2_frame_init_reg); | |
7068 | ||
2454a024 UW |
7069 | /* Setup displaced stepping. */ |
7070 | set_gdbarch_displaced_step_copy_insn (gdbarch, | |
7f03bd92 | 7071 | ppc_displaced_step_copy_insn); |
99e40580 UW |
7072 | set_gdbarch_displaced_step_hw_singlestep (gdbarch, |
7073 | ppc_displaced_step_hw_singlestep); | |
2454a024 | 7074 | set_gdbarch_displaced_step_fixup (gdbarch, ppc_displaced_step_fixup); |
187b041e SM |
7075 | set_gdbarch_displaced_step_prepare (gdbarch, ppc_displaced_step_prepare); |
7076 | set_gdbarch_displaced_step_finish (gdbarch, ppc_displaced_step_finish); | |
7077 | set_gdbarch_displaced_step_restore_all_in_ptid | |
7078 | (gdbarch, ppc_displaced_step_restore_all_in_ptid); | |
2454a024 UW |
7079 | |
7080 | set_gdbarch_max_insn_length (gdbarch, PPC_INSN_SIZE); | |
7081 | ||
7b112f9c | 7082 | /* Hook in ABI-specific overrides, if they have been registered. */ |
8a4c2d24 | 7083 | info.target_desc = tdesc; |
c1e1314d | 7084 | info.tdesc_data = tdesc_data.get (); |
4be87837 | 7085 | gdbarch_init_osabi (info, gdbarch); |
7b112f9c | 7086 | |
61a65099 KB |
7087 | switch (info.osabi) |
7088 | { | |
f5aecab8 | 7089 | case GDB_OSABI_LINUX: |
1736a7bd | 7090 | case GDB_OSABI_NETBSD: |
61a65099 | 7091 | case GDB_OSABI_UNKNOWN: |
2608dbf8 | 7092 | frame_unwind_append_unwinder (gdbarch, &rs6000_epilogue_frame_unwind); |
1af5d7ce | 7093 | frame_unwind_append_unwinder (gdbarch, &rs6000_frame_unwind); |
61a65099 KB |
7094 | frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer); |
7095 | break; | |
7096 | default: | |
61a65099 | 7097 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); |
81332287 | 7098 | |
2608dbf8 | 7099 | frame_unwind_append_unwinder (gdbarch, &rs6000_epilogue_frame_unwind); |
1af5d7ce | 7100 | frame_unwind_append_unwinder (gdbarch, &rs6000_frame_unwind); |
81332287 | 7101 | frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer); |
61a65099 KB |
7102 | } |
7103 | ||
7cc46491 | 7104 | set_tdesc_pseudo_register_type (gdbarch, rs6000_pseudo_register_type); |
6f072a10 PFC |
7105 | set_tdesc_pseudo_register_reggroup_p (gdbarch, |
7106 | rs6000_pseudo_register_reggroup_p); | |
c1e1314d | 7107 | tdesc_use_registers (gdbarch, tdesc, std::move (tdesc_data)); |
7cc46491 DJ |
7108 | |
7109 | /* Override the normal target description method to make the SPE upper | |
7110 | halves anonymous. */ | |
7111 | set_gdbarch_register_name (gdbarch, rs6000_register_name); | |
7112 | ||
604c2f83 LM |
7113 | /* Choose register numbers for all supported pseudo-registers. */ |
7114 | tdep->ppc_ev0_regnum = -1; | |
7115 | tdep->ppc_dl0_regnum = -1; | |
6f072a10 | 7116 | tdep->ppc_v0_alias_regnum = -1; |
604c2f83 LM |
7117 | tdep->ppc_vsr0_regnum = -1; |
7118 | tdep->ppc_efpr0_regnum = -1; | |
8d619c01 EBM |
7119 | tdep->ppc_cdl0_regnum = -1; |
7120 | tdep->ppc_cvsr0_regnum = -1; | |
7121 | tdep->ppc_cefpr0_regnum = -1; | |
9f643768 | 7122 | |
604c2f83 LM |
7123 | cur_reg = gdbarch_num_regs (gdbarch); |
7124 | ||
7125 | if (have_spe) | |
7126 | { | |
7127 | tdep->ppc_ev0_regnum = cur_reg; | |
7128 | cur_reg += 32; | |
7129 | } | |
7130 | if (have_dfp) | |
7131 | { | |
7132 | tdep->ppc_dl0_regnum = cur_reg; | |
7133 | cur_reg += 16; | |
7134 | } | |
6f072a10 PFC |
7135 | if (have_altivec) |
7136 | { | |
7137 | tdep->ppc_v0_alias_regnum = cur_reg; | |
7138 | cur_reg += 32; | |
7139 | } | |
604c2f83 LM |
7140 | if (have_vsx) |
7141 | { | |
7142 | tdep->ppc_vsr0_regnum = cur_reg; | |
7143 | cur_reg += 64; | |
7144 | tdep->ppc_efpr0_regnum = cur_reg; | |
7145 | cur_reg += 32; | |
7146 | } | |
8d619c01 EBM |
7147 | if (have_htm_fpu) |
7148 | { | |
7149 | tdep->ppc_cdl0_regnum = cur_reg; | |
7150 | cur_reg += 16; | |
7151 | } | |
7152 | if (have_htm_vsx) | |
7153 | { | |
7154 | tdep->ppc_cvsr0_regnum = cur_reg; | |
7155 | cur_reg += 64; | |
7156 | tdep->ppc_cefpr0_regnum = cur_reg; | |
7157 | cur_reg += 32; | |
7158 | } | |
f949c649 | 7159 | |
f6efe3f8 | 7160 | gdb_assert (gdbarch_num_cooked_regs (gdbarch) == cur_reg); |
f949c649 | 7161 | |
debb1f09 JB |
7162 | /* Register the ravenscar_arch_ops. */ |
7163 | if (mach == bfd_mach_ppc_e500) | |
7164 | register_e500_ravenscar_ops (gdbarch); | |
7165 | else | |
7166 | register_ppc_ravenscar_ops (gdbarch); | |
7167 | ||
65b48a81 PB |
7168 | set_gdbarch_disassembler_options (gdbarch, &powerpc_disassembler_options); |
7169 | set_gdbarch_valid_disassembler_options (gdbarch, | |
7170 | disassembler_options_powerpc ()); | |
7171 | ||
7a78ae4e | 7172 | return gdbarch; |
c906108c SS |
7173 | } |
7174 | ||
7b112f9c | 7175 | static void |
8b164abb | 7176 | rs6000_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
7b112f9c | 7177 | { |
8b164abb | 7178 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
7b112f9c JT |
7179 | |
7180 | if (tdep == NULL) | |
7181 | return; | |
7182 | ||
4be87837 | 7183 | /* FIXME: Dump gdbarch_tdep. */ |
7b112f9c JT |
7184 | } |
7185 | ||
55eddb0f | 7186 | static void |
eb4c3f4a | 7187 | powerpc_set_soft_float (const char *args, int from_tty, |
55eddb0f DJ |
7188 | struct cmd_list_element *c) |
7189 | { | |
7190 | struct gdbarch_info info; | |
7191 | ||
7192 | /* Update the architecture. */ | |
7193 | gdbarch_info_init (&info); | |
7194 | if (!gdbarch_update_p (info)) | |
9b20d036 | 7195 | internal_error (__FILE__, __LINE__, _("could not update architecture")); |
55eddb0f DJ |
7196 | } |
7197 | ||
7198 | static void | |
eb4c3f4a | 7199 | powerpc_set_vector_abi (const char *args, int from_tty, |
55eddb0f DJ |
7200 | struct cmd_list_element *c) |
7201 | { | |
7202 | struct gdbarch_info info; | |
570dc176 | 7203 | int vector_abi; |
55eddb0f DJ |
7204 | |
7205 | for (vector_abi = POWERPC_VEC_AUTO; | |
7206 | vector_abi != POWERPC_VEC_LAST; | |
7207 | vector_abi++) | |
7208 | if (strcmp (powerpc_vector_abi_string, | |
7209 | powerpc_vector_strings[vector_abi]) == 0) | |
7210 | { | |
aead7601 | 7211 | powerpc_vector_abi_global = (enum powerpc_vector_abi) vector_abi; |
55eddb0f DJ |
7212 | break; |
7213 | } | |
7214 | ||
7215 | if (vector_abi == POWERPC_VEC_LAST) | |
7216 | internal_error (__FILE__, __LINE__, _("Invalid vector ABI accepted: %s."), | |
7217 | powerpc_vector_abi_string); | |
7218 | ||
7219 | /* Update the architecture. */ | |
7220 | gdbarch_info_init (&info); | |
7221 | if (!gdbarch_update_p (info)) | |
9b20d036 | 7222 | internal_error (__FILE__, __LINE__, _("could not update architecture")); |
55eddb0f DJ |
7223 | } |
7224 | ||
e09342b5 TJB |
7225 | /* Show the current setting of the exact watchpoints flag. */ |
7226 | ||
7227 | static void | |
7228 | show_powerpc_exact_watchpoints (struct ui_file *file, int from_tty, | |
7229 | struct cmd_list_element *c, | |
7230 | const char *value) | |
7231 | { | |
7232 | fprintf_filtered (file, _("Use of exact watchpoints is %s.\n"), value); | |
7233 | } | |
7234 | ||
845d4708 | 7235 | /* Read a PPC instruction from memory. */ |
d78489bf AT |
7236 | |
7237 | static unsigned int | |
845d4708 | 7238 | read_insn (struct frame_info *frame, CORE_ADDR pc) |
d78489bf | 7239 | { |
845d4708 AM |
7240 | struct gdbarch *gdbarch = get_frame_arch (frame); |
7241 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
7242 | ||
7243 | return read_memory_unsigned_integer (pc, 4, byte_order); | |
d78489bf AT |
7244 | } |
7245 | ||
7246 | /* Return non-zero if the instructions at PC match the series | |
7247 | described in PATTERN, or zero otherwise. PATTERN is an array of | |
7248 | 'struct ppc_insn_pattern' objects, terminated by an entry whose | |
7249 | mask is zero. | |
7250 | ||
7433498b | 7251 | When the match is successful, fill INSNS[i] with what PATTERN[i] |
d78489bf | 7252 | matched. If PATTERN[i] is optional, and the instruction wasn't |
7433498b AM |
7253 | present, set INSNS[i] to 0 (which is not a valid PPC instruction). |
7254 | INSNS should have as many elements as PATTERN, minus the terminator. | |
7255 | Note that, if PATTERN contains optional instructions which aren't | |
7256 | present in memory, then INSNS will have holes, so INSNS[i] isn't | |
7257 | necessarily the i'th instruction in memory. */ | |
d78489bf AT |
7258 | |
7259 | int | |
845d4708 | 7260 | ppc_insns_match_pattern (struct frame_info *frame, CORE_ADDR pc, |
7433498b | 7261 | const struct ppc_insn_pattern *pattern, |
845d4708 | 7262 | unsigned int *insns) |
d78489bf AT |
7263 | { |
7264 | int i; | |
845d4708 | 7265 | unsigned int insn; |
d78489bf | 7266 | |
845d4708 | 7267 | for (i = 0, insn = 0; pattern[i].mask; i++) |
d78489bf | 7268 | { |
845d4708 AM |
7269 | if (insn == 0) |
7270 | insn = read_insn (frame, pc); | |
7271 | insns[i] = 0; | |
7272 | if ((insn & pattern[i].mask) == pattern[i].data) | |
7273 | { | |
7274 | insns[i] = insn; | |
7275 | pc += 4; | |
7276 | insn = 0; | |
7277 | } | |
7278 | else if (!pattern[i].optional) | |
d78489bf AT |
7279 | return 0; |
7280 | } | |
7281 | ||
7282 | return 1; | |
7283 | } | |
7284 | ||
7285 | /* Return the 'd' field of the d-form instruction INSN, properly | |
7286 | sign-extended. */ | |
7287 | ||
7288 | CORE_ADDR | |
7289 | ppc_insn_d_field (unsigned int insn) | |
7290 | { | |
7291 | return ((((CORE_ADDR) insn & 0xffff) ^ 0x8000) - 0x8000); | |
7292 | } | |
7293 | ||
7294 | /* Return the 'ds' field of the ds-form instruction INSN, with the two | |
7295 | zero bits concatenated at the right, and properly | |
7296 | sign-extended. */ | |
7297 | ||
7298 | CORE_ADDR | |
7299 | ppc_insn_ds_field (unsigned int insn) | |
7300 | { | |
7301 | return ((((CORE_ADDR) insn & 0xfffc) ^ 0x8000) - 0x8000); | |
7302 | } | |
7303 | ||
c906108c SS |
7304 | /* Initialization code. */ |
7305 | ||
6c265988 | 7306 | void _initialize_rs6000_tdep (); |
c906108c | 7307 | void |
6c265988 | 7308 | _initialize_rs6000_tdep () |
c906108c | 7309 | { |
7b112f9c JT |
7310 | gdbarch_register (bfd_arch_rs6000, rs6000_gdbarch_init, rs6000_dump_tdep); |
7311 | gdbarch_register (bfd_arch_powerpc, rs6000_gdbarch_init, rs6000_dump_tdep); | |
7cc46491 DJ |
7312 | |
7313 | /* Initialize the standard target descriptions. */ | |
7314 | initialize_tdesc_powerpc_32 (); | |
7284e1be | 7315 | initialize_tdesc_powerpc_altivec32 (); |
604c2f83 | 7316 | initialize_tdesc_powerpc_vsx32 (); |
7cc46491 DJ |
7317 | initialize_tdesc_powerpc_403 (); |
7318 | initialize_tdesc_powerpc_403gc (); | |
4d09ffea | 7319 | initialize_tdesc_powerpc_405 (); |
7cc46491 DJ |
7320 | initialize_tdesc_powerpc_505 (); |
7321 | initialize_tdesc_powerpc_601 (); | |
7322 | initialize_tdesc_powerpc_602 (); | |
7323 | initialize_tdesc_powerpc_603 (); | |
7324 | initialize_tdesc_powerpc_604 (); | |
7325 | initialize_tdesc_powerpc_64 (); | |
7284e1be | 7326 | initialize_tdesc_powerpc_altivec64 (); |
604c2f83 | 7327 | initialize_tdesc_powerpc_vsx64 (); |
7cc46491 DJ |
7328 | initialize_tdesc_powerpc_7400 (); |
7329 | initialize_tdesc_powerpc_750 (); | |
7330 | initialize_tdesc_powerpc_860 (); | |
7331 | initialize_tdesc_powerpc_e500 (); | |
7332 | initialize_tdesc_rs6000 (); | |
55eddb0f DJ |
7333 | |
7334 | /* Add root prefix command for all "set powerpc"/"show powerpc" | |
7335 | commands. */ | |
0743fc83 TT |
7336 | add_basic_prefix_cmd ("powerpc", no_class, |
7337 | _("Various PowerPC-specific commands."), | |
7338 | &setpowerpccmdlist, "set powerpc ", 0, &setlist); | |
55eddb0f | 7339 | |
0743fc83 TT |
7340 | add_show_prefix_cmd ("powerpc", no_class, |
7341 | _("Various PowerPC-specific commands."), | |
7342 | &showpowerpccmdlist, "show powerpc ", 0, &showlist); | |
55eddb0f DJ |
7343 | |
7344 | /* Add a command to allow the user to force the ABI. */ | |
7345 | add_setshow_auto_boolean_cmd ("soft-float", class_support, | |
7346 | &powerpc_soft_float_global, | |
7347 | _("Set whether to use a soft-float ABI."), | |
7348 | _("Show whether to use a soft-float ABI."), | |
7349 | NULL, | |
7350 | powerpc_set_soft_float, NULL, | |
7351 | &setpowerpccmdlist, &showpowerpccmdlist); | |
7352 | ||
7353 | add_setshow_enum_cmd ("vector-abi", class_support, powerpc_vector_strings, | |
7354 | &powerpc_vector_abi_string, | |
7355 | _("Set the vector ABI."), | |
7356 | _("Show the vector ABI."), | |
7357 | NULL, powerpc_set_vector_abi, NULL, | |
7358 | &setpowerpccmdlist, &showpowerpccmdlist); | |
e09342b5 TJB |
7359 | |
7360 | add_setshow_boolean_cmd ("exact-watchpoints", class_support, | |
7361 | &target_exact_watchpoints, | |
7362 | _("\ | |
7363 | Set whether to use just one debug register for watchpoints on scalars."), | |
7364 | _("\ | |
7365 | Show whether to use just one debug register for watchpoints on scalars."), | |
7366 | _("\ | |
7367 | If true, GDB will use only one debug register when watching a variable of\n\ | |
7368 | scalar type, thus assuming that the variable is accessed through the address\n\ | |
7369 | of its first byte."), | |
7370 | NULL, show_powerpc_exact_watchpoints, | |
7371 | &setpowerpccmdlist, &showpowerpccmdlist); | |
c906108c | 7372 | } |