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* defs.h (extract_signed_integer, extract_unsigned_integer,
[deliverable/binutils-gdb.git] / gdb / rs6000-tdep.c
CommitLineData
c906108c 1/* Target-dependent code for GDB, the GNU debugger.
7aea86e6 2
6aba47ca 3 Copyright (C) 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
0fb0cc75 4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
721d14ba 5 Free Software Foundation, Inc.
c906108c 6
c5aa993b 7 This file is part of GDB.
c906108c 8
c5aa993b
JM		 9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
a9762ec7 11 the Free Software Foundation; either version 3 of the License, or
c5aa993b 12 (at your option) any later version.
c906108c 13
c5aa993b
JM		 14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
c906108c 18
c5aa993b 19 You should have received a copy of the GNU General Public License
a9762ec7 20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
c906108c
SS		 21
22#include "defs.h"
23#include "frame.h"
24#include "inferior.h"
25#include "symtab.h"
26#include "target.h"
27#include "gdbcore.h"
28#include "gdbcmd.h"
c906108c 29#include "objfiles.h"
7a78ae4e 30#include "arch-utils.h"
4e052eda 31#include "regcache.h"
d195bc9f 32#include "regset.h"
d16aafd8 33#include "doublest.h"
fd0407d6 34#include "value.h"
1fcc0bb8 35#include "parser-defs.h"
4be87837 36#include "osabi.h"
7d9b040b 37#include "infcall.h"
9f643768
JB		 38#include "sim-regno.h"
39#include "gdb/sim-ppc.h"
6ced10dd 40#include "reggroups.h"
4fc771b8 41#include "dwarf2-frame.h"
7cc46491
DJ		 42#include "target-descriptions.h"
43#include "user-regs.h"
7a78ae4e 44
2fccf04a 45#include "libbfd.h" /* for bfd_default_set_arch_mach */
7a78ae4e 46#include "coff/internal.h" /* for libcoff.h */
2fccf04a 47#include "libcoff.h" /* for xcoff_data */
11ed25ac
KB		 48#include "coff/xcoff.h"
49#include "libxcoff.h"
7a78ae4e 50
9aa1e687 51#include "elf-bfd.h"
55eddb0f 52#include "elf/ppc.h"
7a78ae4e 53
6ded7999 54#include "solib-svr4.h"
9aa1e687 55#include "ppc-tdep.h"
7a78ae4e 56
338ef23d 57#include "gdb_assert.h"
a89aa300 58#include "dis-asm.h"
338ef23d 59
61a65099
KB		 60#include "trad-frame.h"
61#include "frame-unwind.h"
62#include "frame-base.h"
63
7cc46491 64#include "features/rs6000/powerpc-32.c"
7284e1be 65#include "features/rs6000/powerpc-altivec32.c"
604c2f83 66#include "features/rs6000/powerpc-vsx32.c"
7cc46491
DJ		 67#include "features/rs6000/powerpc-403.c"
68#include "features/rs6000/powerpc-403gc.c"
69#include "features/rs6000/powerpc-505.c"
70#include "features/rs6000/powerpc-601.c"
71#include "features/rs6000/powerpc-602.c"
72#include "features/rs6000/powerpc-603.c"
73#include "features/rs6000/powerpc-604.c"
74#include "features/rs6000/powerpc-64.c"
7284e1be 75#include "features/rs6000/powerpc-altivec64.c"
604c2f83 76#include "features/rs6000/powerpc-vsx64.c"
7cc46491
DJ		 77#include "features/rs6000/powerpc-7400.c"
78#include "features/rs6000/powerpc-750.c"
79#include "features/rs6000/powerpc-860.c"
80#include "features/rs6000/powerpc-e500.c"
81#include "features/rs6000/rs6000.c"
82
5a9e69ba
TJB		 83/* Determine if regnum is an SPE pseudo-register. */
84#define IS_SPE_PSEUDOREG(tdep, regnum) ((tdep)->ppc_ev0_regnum >= 0 \
85 && (regnum) >= (tdep)->ppc_ev0_regnum \
86 && (regnum) < (tdep)->ppc_ev0_regnum + 32)
87
f949c649
TJB		 88/* Determine if regnum is a decimal float pseudo-register. */
89#define IS_DFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_dl0_regnum >= 0 \
90 && (regnum) >= (tdep)->ppc_dl0_regnum \
91 && (regnum) < (tdep)->ppc_dl0_regnum + 16)
92
604c2f83
LM		 93/* Determine if regnum is a POWER7 VSX register. */
94#define IS_VSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_vsr0_regnum >= 0 \
95 && (regnum) >= (tdep)->ppc_vsr0_regnum \
96 && (regnum) < (tdep)->ppc_vsr0_regnum + ppc_num_vsrs)
97
98/* Determine if regnum is a POWER7 Extended FP register. */
99#define IS_EFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_efpr0_regnum >= 0 \
100 && (regnum) >= (tdep)->ppc_efpr0_regnum \
101 && (regnum) < (tdep)->ppc_efpr0_regnum + ppc_num_fprs)
102
55eddb0f
DJ		 103/* The list of available "set powerpc ..." and "show powerpc ..."
104 commands. */
105static struct cmd_list_element *setpowerpccmdlist = NULL;
106static struct cmd_list_element *showpowerpccmdlist = NULL;
107
108static enum auto_boolean powerpc_soft_float_global = AUTO_BOOLEAN_AUTO;
109
110/* The vector ABI to use. Keep this in sync with powerpc_vector_abi. */
111static const char *powerpc_vector_strings[] =
112{
113 "auto",
114 "generic",
115 "altivec",
116 "spe",
117 NULL
118};
119
120/* A variable that can be configured by the user. */
121static enum powerpc_vector_abi powerpc_vector_abi_global = POWERPC_VEC_AUTO;
122static const char *powerpc_vector_abi_string = "auto";
123
7a78ae4e
ND		 124/* To be used by skip_prologue. */
125
126struct rs6000_framedata
127 {
128 int offset; /* total size of frame --- the distance
129 by which we decrement sp to allocate
130 the frame */
131 int saved_gpr; /* smallest # of saved gpr */
46a9b8ed 132 unsigned int gpr_mask; /* Each bit is an individual saved GPR. */
7a78ae4e 133 int saved_fpr; /* smallest # of saved fpr */
6be8bc0c 134 int saved_vr; /* smallest # of saved vr */
96ff0de4 135 int saved_ev; /* smallest # of saved ev */
7a78ae4e
ND		 136 int alloca_reg; /* alloca register number (frame ptr) */
137 char frameless; /* true if frameless functions. */
138 char nosavedpc; /* true if pc not saved. */
46a9b8ed 139 char used_bl; /* true if link register clobbered */
7a78ae4e
ND		 140 int gpr_offset; /* offset of saved gprs from prev sp */
141 int fpr_offset; /* offset of saved fprs from prev sp */
6be8bc0c 142 int vr_offset; /* offset of saved vrs from prev sp */
96ff0de4 143 int ev_offset; /* offset of saved evs from prev sp */
7a78ae4e 144 int lr_offset; /* offset of saved lr */
46a9b8ed 145 int lr_register; /* register of saved lr, if trustworthy */
7a78ae4e 146 int cr_offset; /* offset of saved cr */
6be8bc0c 147 int vrsave_offset; /* offset of saved vrsave register */
7a78ae4e
ND		 148 };
149
c906108c 150
604c2f83
LM		 151/* Is REGNO a VSX register? Return 1 if so, 0 otherwise. */
152int
153vsx_register_p (struct gdbarch *gdbarch, int regno)
154{
155 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
156 if (tdep->ppc_vsr0_regnum < 0)
157 return 0;
158 else
159 return (regno >= tdep->ppc_vsr0_upper_regnum && regno
160 <= tdep->ppc_vsr0_upper_regnum + 31);
161}
162
64b84175
KB		 163/* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
164int
be8626e0 165altivec_register_p (struct gdbarch *gdbarch, int regno)
64b84175 166{
be8626e0 167 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
64b84175
KB		 168 if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0)
169 return 0;
170 else
171 return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum);
172}
173
383f0f5b 174
867e2dc5
JB		 175/* Return true if REGNO is an SPE register, false otherwise. */
176int
be8626e0 177spe_register_p (struct gdbarch *gdbarch, int regno)
867e2dc5 178{
be8626e0 179 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
867e2dc5
JB		 180
181 /* Is it a reference to EV0 -- EV31, and do we have those? */
5a9e69ba 182 if (IS_SPE_PSEUDOREG (tdep, regno))
867e2dc5
JB		 183 return 1;
184
6ced10dd
JB		 185 /* Is it a reference to one of the raw upper GPR halves? */
186 if (tdep->ppc_ev0_upper_regnum >= 0
187 && tdep->ppc_ev0_upper_regnum <= regno
188 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
189 return 1;
190
867e2dc5
JB		 191 /* Is it a reference to the 64-bit accumulator, and do we have that? */
192 if (tdep->ppc_acc_regnum >= 0
193 && tdep->ppc_acc_regnum == regno)
194 return 1;
195
196 /* Is it a reference to the SPE floating-point status and control register,
197 and do we have that? */
198 if (tdep->ppc_spefscr_regnum >= 0
199 && tdep->ppc_spefscr_regnum == regno)
200 return 1;
201
202 return 0;
203}
204
205
383f0f5b
JB		 206/* Return non-zero if the architecture described by GDBARCH has
207 floating-point registers (f0 --- f31 and fpscr). */
0a613259
AC		 208int
209ppc_floating_point_unit_p (struct gdbarch *gdbarch)
210{
383f0f5b
JB		 211 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
212
213 return (tdep->ppc_fp0_regnum >= 0
214 && tdep->ppc_fpscr_regnum >= 0);
0a613259 215}
9f643768 216
604c2f83
LM		 217/* Return non-zero if the architecture described by GDBARCH has
218 VSX registers (vsr0 --- vsr63). */
63807e1d 219static int
604c2f83
LM		 220ppc_vsx_support_p (struct gdbarch *gdbarch)
221{
222 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
223
224 return tdep->ppc_vsr0_regnum >= 0;
225}
226
06caf7d2
CES		 227/* Return non-zero if the architecture described by GDBARCH has
228 Altivec registers (vr0 --- vr31, vrsave and vscr). */
229int
230ppc_altivec_support_p (struct gdbarch *gdbarch)
231{
232 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
233
234 return (tdep->ppc_vr0_regnum >= 0
235 && tdep->ppc_vrsave_regnum >= 0);
236}
09991fa0
JB		 237
238/* Check that TABLE[GDB_REGNO] is not already initialized, and then
239 set it to SIM_REGNO.
240
241 This is a helper function for init_sim_regno_table, constructing
242 the table mapping GDB register numbers to sim register numbers; we
243 initialize every element in that table to -1 before we start
244 filling it in. */
9f643768
JB		 245static void
246set_sim_regno (int *table, int gdb_regno, int sim_regno)
247{
248 /* Make sure we don't try to assign any given GDB register a sim
249 register number more than once. */
250 gdb_assert (table[gdb_regno] == -1);
251 table[gdb_regno] = sim_regno;
252}
253
09991fa0
JB		 254
255/* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
256 numbers to simulator register numbers, based on the values placed
257 in the ARCH->tdep->ppc_foo_regnum members. */
9f643768
JB		 258static void
259init_sim_regno_table (struct gdbarch *arch)
260{
261 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
7cc46491 262 int total_regs = gdbarch_num_regs (arch);
9f643768
JB		 263 int *sim_regno = GDBARCH_OBSTACK_CALLOC (arch, total_regs, int);
264 int i;
7cc46491
DJ		 265 static const char *const segment_regs[] = {
266 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
267 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
268 };
9f643768
JB		 269
270 /* Presume that all registers not explicitly mentioned below are
271 unavailable from the sim. */
272 for (i = 0; i < total_regs; i++)
273 sim_regno[i] = -1;
274
275 /* General-purpose registers. */
276 for (i = 0; i < ppc_num_gprs; i++)
277 set_sim_regno (sim_regno, tdep->ppc_gp0_regnum + i, sim_ppc_r0_regnum + i);
278
279 /* Floating-point registers. */
280 if (tdep->ppc_fp0_regnum >= 0)
281 for (i = 0; i < ppc_num_fprs; i++)
282 set_sim_regno (sim_regno,
283 tdep->ppc_fp0_regnum + i,
284 sim_ppc_f0_regnum + i);
285 if (tdep->ppc_fpscr_regnum >= 0)
286 set_sim_regno (sim_regno, tdep->ppc_fpscr_regnum, sim_ppc_fpscr_regnum);
287
288 set_sim_regno (sim_regno, gdbarch_pc_regnum (arch), sim_ppc_pc_regnum);
289 set_sim_regno (sim_regno, tdep->ppc_ps_regnum, sim_ppc_ps_regnum);
290 set_sim_regno (sim_regno, tdep->ppc_cr_regnum, sim_ppc_cr_regnum);
291
292 /* Segment registers. */
7cc46491
DJ		 293 for (i = 0; i < ppc_num_srs; i++)
294 {
295 int gdb_regno;
296
297 gdb_regno = user_reg_map_name_to_regnum (arch, segment_regs[i], -1);
298 if (gdb_regno >= 0)
299 set_sim_regno (sim_regno, gdb_regno, sim_ppc_sr0_regnum + i);
300 }
9f643768
JB		 301
302 /* Altivec registers. */
303 if (tdep->ppc_vr0_regnum >= 0)
304 {
305 for (i = 0; i < ppc_num_vrs; i++)
306 set_sim_regno (sim_regno,
307 tdep->ppc_vr0_regnum + i,
308 sim_ppc_vr0_regnum + i);
309
310 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
311 we can treat this more like the other cases. */
312 set_sim_regno (sim_regno,
313 tdep->ppc_vr0_regnum + ppc_num_vrs,
314 sim_ppc_vscr_regnum);
315 }
316 /* vsave is a special-purpose register, so the code below handles it. */
317
318 /* SPE APU (E500) registers. */
6ced10dd
JB		 319 if (tdep->ppc_ev0_upper_regnum >= 0)
320 for (i = 0; i < ppc_num_gprs; i++)
321 set_sim_regno (sim_regno,
322 tdep->ppc_ev0_upper_regnum + i,
323 sim_ppc_rh0_regnum + i);
9f643768
JB		 324 if (tdep->ppc_acc_regnum >= 0)
325 set_sim_regno (sim_regno, tdep->ppc_acc_regnum, sim_ppc_acc_regnum);
326 /* spefscr is a special-purpose register, so the code below handles it. */
327
7cc46491 328#ifdef WITH_SIM
9f643768
JB		 329 /* Now handle all special-purpose registers. Verify that they
330 haven't mistakenly been assigned numbers by any of the above
7cc46491
DJ		 331 code. */
332 for (i = 0; i < sim_ppc_num_sprs; i++)
333 {
334 const char *spr_name = sim_spr_register_name (i);
335 int gdb_regno = -1;
336
337 if (spr_name != NULL)
338 gdb_regno = user_reg_map_name_to_regnum (arch, spr_name, -1);
339
340 if (gdb_regno != -1)
341 set_sim_regno (sim_regno, gdb_regno, sim_ppc_spr0_regnum + i);
342 }
343#endif
9f643768
JB		 344
345 /* Drop the initialized array into place. */
346 tdep->sim_regno = sim_regno;
347}
348
09991fa0
JB		 349
350/* Given a GDB register number REG, return the corresponding SIM
351 register number. */
9f643768 352static int
e7faf938 353rs6000_register_sim_regno (struct gdbarch *gdbarch, int reg)
9f643768 354{
e7faf938 355 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
9f643768
JB		 356 int sim_regno;
357
7cc46491 358 if (tdep->sim_regno == NULL)
e7faf938 359 init_sim_regno_table (gdbarch);
7cc46491 360
f57d151a 361 gdb_assert (0 <= reg
e7faf938
MD		 362 && reg <= gdbarch_num_regs (gdbarch)
363 + gdbarch_num_pseudo_regs (gdbarch));
9f643768
JB		 364 sim_regno = tdep->sim_regno[reg];
365
366 if (sim_regno >= 0)
367 return sim_regno;
368 else
369 return LEGACY_SIM_REGNO_IGNORE;
370}
371
d195bc9f
MK		 372\f
373
374/* Register set support functions. */
375
f2db237a
AM		 376/* REGS + OFFSET contains register REGNUM in a field REGSIZE wide.
377 Write the register to REGCACHE. */
378
7284e1be 379void
d195bc9f 380ppc_supply_reg (struct regcache *regcache, int regnum,
f2db237a 381 const gdb_byte *regs, size_t offset, int regsize)
d195bc9f
MK		 382{
383 if (regnum != -1 && offset != -1)
f2db237a
AM		 384 {
385 if (regsize > 4)
386 {
387 struct gdbarch *gdbarch = get_regcache_arch (regcache);
388 int gdb_regsize = register_size (gdbarch, regnum);
389 if (gdb_regsize < regsize
390 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
391 offset += regsize - gdb_regsize;
392 }
393 regcache_raw_supply (regcache, regnum, regs + offset);
394 }
d195bc9f
MK		 395}
396
f2db237a
AM		 397/* Read register REGNUM from REGCACHE and store to REGS + OFFSET
398 in a field REGSIZE wide. Zero pad as necessary. */
399
7284e1be 400void
d195bc9f 401ppc_collect_reg (const struct regcache *regcache, int regnum,
f2db237a 402 gdb_byte *regs, size_t offset, int regsize)
d195bc9f
MK		 403{
404 if (regnum != -1 && offset != -1)
f2db237a
AM		 405 {
406 if (regsize > 4)
407 {
408 struct gdbarch *gdbarch = get_regcache_arch (regcache);
409 int gdb_regsize = register_size (gdbarch, regnum);
410 if (gdb_regsize < regsize)
411 {
412 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
413 {
414 memset (regs + offset, 0, regsize - gdb_regsize);
415 offset += regsize - gdb_regsize;
416 }
417 else
418 memset (regs + offset + regsize - gdb_regsize, 0,
419 regsize - gdb_regsize);
420 }
421 }
422 regcache_raw_collect (regcache, regnum, regs + offset);
423 }
d195bc9f
MK		 424}
425
f2db237a
AM		 426static int
427ppc_greg_offset (struct gdbarch *gdbarch,
428 struct gdbarch_tdep *tdep,
429 const struct ppc_reg_offsets *offsets,
430 int regnum,
431 int *regsize)
432{
433 *regsize = offsets->gpr_size;
434 if (regnum >= tdep->ppc_gp0_regnum
435 && regnum < tdep->ppc_gp0_regnum + ppc_num_gprs)
436 return (offsets->r0_offset
437 + (regnum - tdep->ppc_gp0_regnum) * offsets->gpr_size);
438
439 if (regnum == gdbarch_pc_regnum (gdbarch))
440 return offsets->pc_offset;
441
442 if (regnum == tdep->ppc_ps_regnum)
443 return offsets->ps_offset;
444
445 if (regnum == tdep->ppc_lr_regnum)
446 return offsets->lr_offset;
447
448 if (regnum == tdep->ppc_ctr_regnum)
449 return offsets->ctr_offset;
450
451 *regsize = offsets->xr_size;
452 if (regnum == tdep->ppc_cr_regnum)
453 return offsets->cr_offset;
454
455 if (regnum == tdep->ppc_xer_regnum)
456 return offsets->xer_offset;
457
458 if (regnum == tdep->ppc_mq_regnum)
459 return offsets->mq_offset;
460
461 return -1;
462}
463
464static int
465ppc_fpreg_offset (struct gdbarch_tdep *tdep,
466 const struct ppc_reg_offsets *offsets,
467 int regnum)
468{
469 if (regnum >= tdep->ppc_fp0_regnum
470 && regnum < tdep->ppc_fp0_regnum + ppc_num_fprs)
471 return offsets->f0_offset + (regnum - tdep->ppc_fp0_regnum) * 8;
472
473 if (regnum == tdep->ppc_fpscr_regnum)
474 return offsets->fpscr_offset;
475
476 return -1;
477}
478
06caf7d2
CES		 479static int
480ppc_vrreg_offset (struct gdbarch_tdep *tdep,
481 const struct ppc_reg_offsets *offsets,
482 int regnum)
483{
484 if (regnum >= tdep->ppc_vr0_regnum
485 && regnum < tdep->ppc_vr0_regnum + ppc_num_vrs)
486 return offsets->vr0_offset + (regnum - tdep->ppc_vr0_regnum) * 16;
487
488 if (regnum == tdep->ppc_vrsave_regnum - 1)
489 return offsets->vscr_offset;
490
491 if (regnum == tdep->ppc_vrsave_regnum)
492 return offsets->vrsave_offset;
493
494 return -1;
495}
496
d195bc9f
MK		 497/* Supply register REGNUM in the general-purpose register set REGSET
498 from the buffer specified by GREGS and LEN to register cache
499 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
500
501void
502ppc_supply_gregset (const struct regset *regset, struct regcache *regcache,
503 int regnum, const void *gregs, size_t len)
504{
505 struct gdbarch *gdbarch = get_regcache_arch (regcache);
506 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
507 const struct ppc_reg_offsets *offsets = regset->descr;
508 size_t offset;
f2db237a 509 int regsize;
d195bc9f 510
f2db237a 511 if (regnum == -1)
d195bc9f 512 {
f2db237a
AM		 513 int i;
514 int gpr_size = offsets->gpr_size;
515
516 for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset;
517 i < tdep->ppc_gp0_regnum + ppc_num_gprs;
518 i++, offset += gpr_size)
519 ppc_supply_reg (regcache, i, gregs, offset, gpr_size);
520
521 ppc_supply_reg (regcache, gdbarch_pc_regnum (gdbarch),
522 gregs, offsets->pc_offset, gpr_size);
523 ppc_supply_reg (regcache, tdep->ppc_ps_regnum,
524 gregs, offsets->ps_offset, gpr_size);
525 ppc_supply_reg (regcache, tdep->ppc_lr_regnum,
526 gregs, offsets->lr_offset, gpr_size);
527 ppc_supply_reg (regcache, tdep->ppc_ctr_regnum,
528 gregs, offsets->ctr_offset, gpr_size);
529 ppc_supply_reg (regcache, tdep->ppc_cr_regnum,
530 gregs, offsets->cr_offset, offsets->xr_size);
531 ppc_supply_reg (regcache, tdep->ppc_xer_regnum,
532 gregs, offsets->xer_offset, offsets->xr_size);
533 ppc_supply_reg (regcache, tdep->ppc_mq_regnum,
534 gregs, offsets->mq_offset, offsets->xr_size);
535 return;
d195bc9f
MK		 536 }
537
f2db237a
AM		 538 offset = ppc_greg_offset (gdbarch, tdep, offsets, regnum, &regsize);
539 ppc_supply_reg (regcache, regnum, gregs, offset, regsize);
d195bc9f
MK		 540}
541
542/* Supply register REGNUM in the floating-point register set REGSET
543 from the buffer specified by FPREGS and LEN to register cache
544 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
545
546void
547ppc_supply_fpregset (const struct regset *regset, struct regcache *regcache,
548 int regnum, const void *fpregs, size_t len)
549{
550 struct gdbarch *gdbarch = get_regcache_arch (regcache);
f2db237a
AM		 551 struct gdbarch_tdep *tdep;
552 const struct ppc_reg_offsets *offsets;
d195bc9f 553 size_t offset;
d195bc9f 554
f2db237a
AM		 555 if (!ppc_floating_point_unit_p (gdbarch))
556 return;
383f0f5b 557
f2db237a
AM		 558 tdep = gdbarch_tdep (gdbarch);
559 offsets = regset->descr;
560 if (regnum == -1)
d195bc9f 561 {
f2db237a
AM		 562 int i;
563
564 for (i = tdep->ppc_fp0_regnum, offset = offsets->f0_offset;
565 i < tdep->ppc_fp0_regnum + ppc_num_fprs;
566 i++, offset += 8)
567 ppc_supply_reg (regcache, i, fpregs, offset, 8);
568
569 ppc_supply_reg (regcache, tdep->ppc_fpscr_regnum,
570 fpregs, offsets->fpscr_offset, offsets->fpscr_size);
571 return;
d195bc9f
MK		 572 }
573
f2db237a
AM		 574 offset = ppc_fpreg_offset (tdep, offsets, regnum);
575 ppc_supply_reg (regcache, regnum, fpregs, offset,
576 regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8);
d195bc9f
MK		 577}
578
604c2f83
LM		 579/* Supply register REGNUM in the VSX register set REGSET
580 from the buffer specified by VSXREGS and LEN to register cache
581 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
582
583void
584ppc_supply_vsxregset (const struct regset *regset, struct regcache *regcache,
585 int regnum, const void *vsxregs, size_t len)
586{
587 struct gdbarch *gdbarch = get_regcache_arch (regcache);
588 struct gdbarch_tdep *tdep;
589
590 if (!ppc_vsx_support_p (gdbarch))
591 return;
592
593 tdep = gdbarch_tdep (gdbarch);
594
595 if (regnum == -1)
596 {
597 int i;
598
599 for (i = tdep->ppc_vsr0_upper_regnum;
600 i < tdep->ppc_vsr0_upper_regnum + 32;
601 i++)
602 ppc_supply_reg (regcache, i, vsxregs, 0, 8);
603
604 return;
605 }
606 else
607 ppc_supply_reg (regcache, regnum, vsxregs, 0, 8);
608}
609
06caf7d2
CES		 610/* Supply register REGNUM in the Altivec register set REGSET
611 from the buffer specified by VRREGS and LEN to register cache
612 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
613
614void
615ppc_supply_vrregset (const struct regset *regset, struct regcache *regcache,
616 int regnum, const void *vrregs, size_t len)
617{
618 struct gdbarch *gdbarch = get_regcache_arch (regcache);
619 struct gdbarch_tdep *tdep;
620 const struct ppc_reg_offsets *offsets;
621 size_t offset;
622
623 if (!ppc_altivec_support_p (gdbarch))
624 return;
625
626 tdep = gdbarch_tdep (gdbarch);
627 offsets = regset->descr;
628 if (regnum == -1)
629 {
630 int i;
631
632 for (i = tdep->ppc_vr0_regnum, offset = offsets->vr0_offset;
633 i < tdep->ppc_vr0_regnum + ppc_num_vrs;
634 i++, offset += 16)
635 ppc_supply_reg (regcache, i, vrregs, offset, 16);
636
637 ppc_supply_reg (regcache, (tdep->ppc_vrsave_regnum - 1),
638 vrregs, offsets->vscr_offset, 4);
639
640 ppc_supply_reg (regcache, tdep->ppc_vrsave_regnum,
641 vrregs, offsets->vrsave_offset, 4);
642 return;
643 }
644
645 offset = ppc_vrreg_offset (tdep, offsets, regnum);
646 if (regnum != tdep->ppc_vrsave_regnum
647 && regnum != tdep->ppc_vrsave_regnum - 1)
648 ppc_supply_reg (regcache, regnum, vrregs, offset, 16);
649 else
650 ppc_supply_reg (regcache, regnum,
651 vrregs, offset, 4);
652}
653
d195bc9f 654/* Collect register REGNUM in the general-purpose register set
f2db237a 655 REGSET from register cache REGCACHE into the buffer specified by
d195bc9f
MK		 656 GREGS and LEN. If REGNUM is -1, do this for all registers in
657 REGSET. */
658
659void
660ppc_collect_gregset (const struct regset *regset,
661 const struct regcache *regcache,
662 int regnum, void *gregs, size_t len)
663{
664 struct gdbarch *gdbarch = get_regcache_arch (regcache);
665 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
666 const struct ppc_reg_offsets *offsets = regset->descr;
667 size_t offset;
f2db237a 668 int regsize;
d195bc9f 669
f2db237a 670 if (regnum == -1)
d195bc9f 671 {
f2db237a
AM		 672 int i;
673 int gpr_size = offsets->gpr_size;
674
675 for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset;
676 i < tdep->ppc_gp0_regnum + ppc_num_gprs;
677 i++, offset += gpr_size)
678 ppc_collect_reg (regcache, i, gregs, offset, gpr_size);
679
680 ppc_collect_reg (regcache, gdbarch_pc_regnum (gdbarch),
681 gregs, offsets->pc_offset, gpr_size);
682 ppc_collect_reg (regcache, tdep->ppc_ps_regnum,
683 gregs, offsets->ps_offset, gpr_size);
684 ppc_collect_reg (regcache, tdep->ppc_lr_regnum,
685 gregs, offsets->lr_offset, gpr_size);
686 ppc_collect_reg (regcache, tdep->ppc_ctr_regnum,
687 gregs, offsets->ctr_offset, gpr_size);
688 ppc_collect_reg (regcache, tdep->ppc_cr_regnum,
689 gregs, offsets->cr_offset, offsets->xr_size);
690 ppc_collect_reg (regcache, tdep->ppc_xer_regnum,
691 gregs, offsets->xer_offset, offsets->xr_size);
692 ppc_collect_reg (regcache, tdep->ppc_mq_regnum,
693 gregs, offsets->mq_offset, offsets->xr_size);
694 return;
d195bc9f
MK		 695 }
696
f2db237a
AM		 697 offset = ppc_greg_offset (gdbarch, tdep, offsets, regnum, &regsize);
698 ppc_collect_reg (regcache, regnum, gregs, offset, regsize);
d195bc9f
MK		 699}
700
701/* Collect register REGNUM in the floating-point register set
f2db237a 702 REGSET from register cache REGCACHE into the buffer specified by
d195bc9f
MK		 703 FPREGS and LEN. If REGNUM is -1, do this for all registers in
704 REGSET. */
705
706void
707ppc_collect_fpregset (const struct regset *regset,
708 const struct regcache *regcache,
709 int regnum, void *fpregs, size_t len)
710{
711 struct gdbarch *gdbarch = get_regcache_arch (regcache);
f2db237a
AM		 712 struct gdbarch_tdep *tdep;
713 const struct ppc_reg_offsets *offsets;
d195bc9f 714 size_t offset;
d195bc9f 715
f2db237a
AM		 716 if (!ppc_floating_point_unit_p (gdbarch))
717 return;
383f0f5b 718
f2db237a
AM		 719 tdep = gdbarch_tdep (gdbarch);
720 offsets = regset->descr;
721 if (regnum == -1)
d195bc9f 722 {
f2db237a
AM		 723 int i;
724
725 for (i = tdep->ppc_fp0_regnum, offset = offsets->f0_offset;
726 i < tdep->ppc_fp0_regnum + ppc_num_fprs;
727 i++, offset += 8)
728 ppc_collect_reg (regcache, i, fpregs, offset, 8);
729
730 ppc_collect_reg (regcache, tdep->ppc_fpscr_regnum,
731 fpregs, offsets->fpscr_offset, offsets->fpscr_size);
732 return;
d195bc9f
MK		 733 }
734
f2db237a
AM		 735 offset = ppc_fpreg_offset (tdep, offsets, regnum);
736 ppc_collect_reg (regcache, regnum, fpregs, offset,
737 regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8);
d195bc9f 738}
06caf7d2 739
604c2f83
LM		 740/* Collect register REGNUM in the VSX register set
741 REGSET from register cache REGCACHE into the buffer specified by
742 VSXREGS and LEN. If REGNUM is -1, do this for all registers in
743 REGSET. */
744
745void
746ppc_collect_vsxregset (const struct regset *regset,
747 const struct regcache *regcache,
748 int regnum, void *vsxregs, size_t len)
749{
750 struct gdbarch *gdbarch = get_regcache_arch (regcache);
751 struct gdbarch_tdep *tdep;
752
753 if (!ppc_vsx_support_p (gdbarch))
754 return;
755
756 tdep = gdbarch_tdep (gdbarch);
757
758 if (regnum == -1)
759 {
760 int i;
761
762 for (i = tdep->ppc_vsr0_upper_regnum;
763 i < tdep->ppc_vsr0_upper_regnum + 32;
764 i++)
765 ppc_collect_reg (regcache, i, vsxregs, 0, 8);
766
767 return;
768 }
769 else
770 ppc_collect_reg (regcache, regnum, vsxregs, 0, 8);
771}
772
773
06caf7d2
CES		 774/* Collect register REGNUM in the Altivec register set
775 REGSET from register cache REGCACHE into the buffer specified by
776 VRREGS and LEN. If REGNUM is -1, do this for all registers in
777 REGSET. */
778
779void
780ppc_collect_vrregset (const struct regset *regset,
781 const struct regcache *regcache,
782 int regnum, void *vrregs, size_t len)
783{
784 struct gdbarch *gdbarch = get_regcache_arch (regcache);
785 struct gdbarch_tdep *tdep;
786 const struct ppc_reg_offsets *offsets;
787 size_t offset;
788
789 if (!ppc_altivec_support_p (gdbarch))
790 return;
791
792 tdep = gdbarch_tdep (gdbarch);
793 offsets = regset->descr;
794 if (regnum == -1)
795 {
796 int i;
797
798 for (i = tdep->ppc_vr0_regnum, offset = offsets->vr0_offset;
799 i < tdep->ppc_vr0_regnum + ppc_num_vrs;
800 i++, offset += 16)
801 ppc_collect_reg (regcache, i, vrregs, offset, 16);
802
803 ppc_collect_reg (regcache, (tdep->ppc_vrsave_regnum - 1),
804 vrregs, offsets->vscr_offset, 4);
805
806 ppc_collect_reg (regcache, tdep->ppc_vrsave_regnum,
807 vrregs, offsets->vrsave_offset, 4);
808 return;
809 }
810
811 offset = ppc_vrreg_offset (tdep, offsets, regnum);
812 if (regnum != tdep->ppc_vrsave_regnum
813 && regnum != tdep->ppc_vrsave_regnum - 1)
814 ppc_collect_reg (regcache, regnum, vrregs, offset, 16);
815 else
816 ppc_collect_reg (regcache, regnum,
817 vrregs, offset, 4);
818}
d195bc9f 819\f
0a613259 820
0d1243d9
PG		 821static int
822insn_changes_sp_or_jumps (unsigned long insn)
823{
824 int opcode = (insn >> 26) & 0x03f;
825 int sd = (insn >> 21) & 0x01f;
826 int a = (insn >> 16) & 0x01f;
827 int subcode = (insn >> 1) & 0x3ff;
828
829 /* Changes the stack pointer. */
830
831 /* NOTE: There are many ways to change the value of a given register.
832 The ways below are those used when the register is R1, the SP,
833 in a funtion's epilogue. */
834
835 if (opcode == 31 && subcode == 444 && a == 1)
836 return 1; /* mr R1,Rn */
837 if (opcode == 14 && sd == 1)
838 return 1; /* addi R1,Rn,simm */
839 if (opcode == 58 && sd == 1)
840 return 1; /* ld R1,ds(Rn) */
841
842 /* Transfers control. */
843
844 if (opcode == 18)
845 return 1; /* b */
846 if (opcode == 16)
847 return 1; /* bc */
848 if (opcode == 19 && subcode == 16)
849 return 1; /* bclr */
850 if (opcode == 19 && subcode == 528)
851 return 1; /* bcctr */
852
853 return 0;
854}
855
856/* Return true if we are in the function's epilogue, i.e. after the
857 instruction that destroyed the function's stack frame.
858
859 1) scan forward from the point of execution:
860 a) If you find an instruction that modifies the stack pointer
861 or transfers control (except a return), execution is not in
862 an epilogue, return.
863 b) Stop scanning if you find a return instruction or reach the
864 end of the function or reach the hard limit for the size of
865 an epilogue.
866 2) scan backward from the point of execution:
867 a) If you find an instruction that modifies the stack pointer,
868 execution *is* in an epilogue, return.
869 b) Stop scanning if you reach an instruction that transfers
870 control or the beginning of the function or reach the hard
871 limit for the size of an epilogue. */
872
873static int
874rs6000_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
875{
46a9b8ed 876 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
e17a4113 877 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
0d1243d9
PG		 878 bfd_byte insn_buf[PPC_INSN_SIZE];
879 CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end;
880 unsigned long insn;
881 struct frame_info *curfrm;
882
883 /* Find the search limits based on function boundaries and hard limit. */
884
885 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
886 return 0;
887
888 epilogue_start = pc - PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE;
889 if (epilogue_start < func_start) epilogue_start = func_start;
890
891 epilogue_end = pc + PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE;
892 if (epilogue_end > func_end) epilogue_end = func_end;
893
894 curfrm = get_current_frame ();
895
896 /* Scan forward until next 'blr'. */
897
898 for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += PPC_INSN_SIZE)
899 {
900 if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE))
901 return 0;
e17a4113 902 insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE, byte_order);
0d1243d9
PG		 903 if (insn == 0x4e800020)
904 break;
46a9b8ed
DJ		 905 /* Assume a bctr is a tail call unless it points strictly within
906 this function. */
907 if (insn == 0x4e800420)
908 {
909 CORE_ADDR ctr = get_frame_register_unsigned (curfrm,
910 tdep->ppc_ctr_regnum);
911 if (ctr > func_start && ctr < func_end)
912 return 0;
913 else
914 break;
915 }
0d1243d9
PG		 916 if (insn_changes_sp_or_jumps (insn))
917 return 0;
918 }
919
920 /* Scan backward until adjustment to stack pointer (R1). */
921
922 for (scan_pc = pc - PPC_INSN_SIZE;
923 scan_pc >= epilogue_start;
924 scan_pc -= PPC_INSN_SIZE)
925 {
926 if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE))
927 return 0;
e17a4113 928 insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE, byte_order);
0d1243d9
PG		 929 if (insn_changes_sp_or_jumps (insn))
930 return 1;
931 }
932
933 return 0;
934}
935
143985b7 936/* Get the ith function argument for the current function. */
b9362cc7 937static CORE_ADDR
143985b7
AF		 938rs6000_fetch_pointer_argument (struct frame_info *frame, int argi,
939 struct type *type)
940{
50fd1280 941 return get_frame_register_unsigned (frame, 3 + argi);
143985b7
AF		 942}
943
c906108c
SS		 944/* Sequence of bytes for breakpoint instruction. */
945
f4f9705a 946const static unsigned char *
67d57894
MD		 947rs6000_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *bp_addr,
948 int *bp_size)
c906108c 949{
aaab4dba
AC		 950 static unsigned char big_breakpoint[] = { 0x7d, 0x82, 0x10, 0x08 };
951 static unsigned char little_breakpoint[] = { 0x08, 0x10, 0x82, 0x7d };
c906108c 952 *bp_size = 4;
67d57894 953 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
c906108c
SS		 954 return big_breakpoint;
955 else
956 return little_breakpoint;
957}
958
f74c6cad
LM		 959/* Instruction masks for displaced stepping. */
960#define BRANCH_MASK 0xfc000000
961#define BP_MASK 0xFC0007FE
962#define B_INSN 0x48000000
963#define BC_INSN 0x40000000
964#define BXL_INSN 0x4c000000
965#define BP_INSN 0x7C000008
966
967/* Fix up the state of registers and memory after having single-stepped
968 a displaced instruction. */
63807e1d 969static void
f74c6cad 970ppc_displaced_step_fixup (struct gdbarch *gdbarch,
63807e1d
PA		 971 struct displaced_step_closure *closure,
972 CORE_ADDR from, CORE_ADDR to,
973 struct regcache *regs)
f74c6cad 974{
e17a4113 975 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
f74c6cad
LM		 976 /* Since we use simple_displaced_step_copy_insn, our closure is a
977 copy of the instruction. */
978 ULONGEST insn = extract_unsigned_integer ((gdb_byte *) closure,
e17a4113 979 PPC_INSN_SIZE, byte_order);
f74c6cad
LM		 980 ULONGEST opcode = 0;
981 /* Offset for non PC-relative instructions. */
982 LONGEST offset = PPC_INSN_SIZE;
983
984 opcode = insn & BRANCH_MASK;
985
986 if (debug_displaced)
987 fprintf_unfiltered (gdb_stdlog,
5af949e3
UW		 988 "displaced: (ppc) fixup (%s, %s)\n",
989 paddress (gdbarch, from), paddress (gdbarch, to));
f74c6cad
LM		 990
991
992 /* Handle PC-relative branch instructions. */
993 if (opcode == B_INSN || opcode == BC_INSN || opcode == BXL_INSN)
994 {
a4fafde3 995 ULONGEST current_pc;
f74c6cad
LM		 996
997 /* Read the current PC value after the instruction has been executed
998 in a displaced location. Calculate the offset to be applied to the
999 original PC value before the displaced stepping. */
1000 regcache_cooked_read_unsigned (regs, gdbarch_pc_regnum (gdbarch),
1001 &current_pc);
1002 offset = current_pc - to;
1003
1004 if (opcode != BXL_INSN)
1005 {
1006 /* Check for AA bit indicating whether this is an absolute
1007 addressing or PC-relative (1: absolute, 0: relative). */
1008 if (!(insn & 0x2))
1009 {
1010 /* PC-relative addressing is being used in the branch. */
1011 if (debug_displaced)
1012 fprintf_unfiltered
1013 (gdb_stdlog,
5af949e3
UW		 1014 "displaced: (ppc) branch instruction: %s\n"
1015 "displaced: (ppc) adjusted PC from %s to %s\n",
1016 paddress (gdbarch, insn), paddress (gdbarch, current_pc),
1017 paddress (gdbarch, from + offset));
f74c6cad
LM		 1018
1019 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch),
1020 from + offset);
1021 }
1022 }
1023 else
1024 {
1025 /* If we're here, it means we have a branch to LR or CTR. If the
1026 branch was taken, the offset is probably greater than 4 (the next
1027 instruction), so it's safe to assume that an offset of 4 means we
1028 did not take the branch. */
1029 if (offset == PPC_INSN_SIZE)
1030 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch),
1031 from + PPC_INSN_SIZE);
1032 }
1033
1034 /* Check for LK bit indicating whether we should set the link
1035 register to point to the next instruction
1036 (1: Set, 0: Don't set). */
1037 if (insn & 0x1)
1038 {
1039 /* Link register needs to be set to the next instruction's PC. */
1040 regcache_cooked_write_unsigned (regs,
1041 gdbarch_tdep (gdbarch)->ppc_lr_regnum,
1042 from + PPC_INSN_SIZE);
1043 if (debug_displaced)
1044 fprintf_unfiltered (gdb_stdlog,
5af949e3
UW		 1045 "displaced: (ppc) adjusted LR to %s\n",
1046 paddress (gdbarch, from + PPC_INSN_SIZE));
f74c6cad
LM		 1047
1048 }
1049 }
1050 /* Check for breakpoints in the inferior. If we've found one, place the PC
1051 right at the breakpoint instruction. */
1052 else if ((insn & BP_MASK) == BP_INSN)
1053 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch), from);
1054 else
1055 /* Handle any other instructions that do not fit in the categories above. */
1056 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch),
1057 from + offset);
1058}
c906108c 1059
ce5eab59
UW		 1060/* Instruction masks used during single-stepping of atomic sequences. */
1061#define LWARX_MASK 0xfc0007fe
1062#define LWARX_INSTRUCTION 0x7c000028
1063#define LDARX_INSTRUCTION 0x7c0000A8
1064#define STWCX_MASK 0xfc0007ff
1065#define STWCX_INSTRUCTION 0x7c00012d
1066#define STDCX_INSTRUCTION 0x7c0001ad
ce5eab59
UW		 1067
1068/* Checks for an atomic sequence of instructions beginning with a LWARX/LDARX
1069 instruction and ending with a STWCX/STDCX instruction. If such a sequence
1070 is found, attempt to step through it. A breakpoint is placed at the end of
1071 the sequence. */
1072
4a7622d1
UW		 1073int
1074ppc_deal_with_atomic_sequence (struct frame_info *frame)
ce5eab59 1075{
a6d9a66e 1076 struct gdbarch *gdbarch = get_frame_arch (frame);
e17a4113 1077 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
0b1b3e42 1078 CORE_ADDR pc = get_frame_pc (frame);
ce5eab59
UW		 1079 CORE_ADDR breaks[2] = {-1, -1};
1080 CORE_ADDR loc = pc;
24d45690 1081 CORE_ADDR closing_insn; /* Instruction that closes the atomic sequence. */
e17a4113 1082 int insn = read_memory_integer (loc, PPC_INSN_SIZE, byte_order);
ce5eab59
UW		 1083 int insn_count;
1084 int index;
1085 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
1086 const int atomic_sequence_length = 16; /* Instruction sequence length. */
24d45690 1087 int opcode; /* Branch instruction's OPcode. */
ce5eab59
UW		 1088 int bc_insn_count = 0; /* Conditional branch instruction count. */
1089
1090 /* Assume all atomic sequences start with a lwarx/ldarx instruction. */
1091 if ((insn & LWARX_MASK) != LWARX_INSTRUCTION
1092 && (insn & LWARX_MASK) != LDARX_INSTRUCTION)
1093 return 0;
1094
1095 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
1096 instructions. */
1097 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
1098 {
1099 loc += PPC_INSN_SIZE;
e17a4113 1100 insn = read_memory_integer (loc, PPC_INSN_SIZE, byte_order);
ce5eab59
UW		 1101
1102 /* Assume that there is at most one conditional branch in the atomic
1103 sequence. If a conditional branch is found, put a breakpoint in
1104 its destination address. */
f74c6cad 1105 if ((insn & BRANCH_MASK) == BC_INSN)
ce5eab59 1106 {
4a7622d1
UW		 1107 int immediate = ((insn & ~3) << 16) >> 16;
1108 int absolute = ((insn >> 1) & 1);
1109
ce5eab59
UW		 1110 if (bc_insn_count >= 1)
1111 return 0; /* More than one conditional branch found, fallback
1112 to the standard single-step code. */
4a7622d1
UW		 1113
1114 if (absolute)
1115 breaks[1] = immediate;
1116 else
1117 breaks[1] = pc + immediate;
1118
1119 bc_insn_count++;
1120 last_breakpoint++;
ce5eab59
UW		 1121 }
1122
1123 if ((insn & STWCX_MASK) == STWCX_INSTRUCTION
1124 || (insn & STWCX_MASK) == STDCX_INSTRUCTION)
1125 break;
1126 }
1127
1128 /* Assume that the atomic sequence ends with a stwcx/stdcx instruction. */
1129 if ((insn & STWCX_MASK) != STWCX_INSTRUCTION
1130 && (insn & STWCX_MASK) != STDCX_INSTRUCTION)
1131 return 0;
1132
24d45690 1133 closing_insn = loc;
ce5eab59 1134 loc += PPC_INSN_SIZE;
e17a4113 1135 insn = read_memory_integer (loc, PPC_INSN_SIZE, byte_order);
ce5eab59
UW		 1136
1137 /* Insert a breakpoint right after the end of the atomic sequence. */
1138 breaks[0] = loc;
1139
24d45690
UW		 1140 /* Check for duplicated breakpoints. Check also for a breakpoint
1141 placed (branch instruction's destination) at the stwcx/stdcx
1142 instruction, this resets the reservation and take us back to the
1143 lwarx/ldarx instruction at the beginning of the atomic sequence. */
1144 if (last_breakpoint && ((breaks[1] == breaks[0])
1145 || (breaks[1] == closing_insn)))
ce5eab59
UW		 1146 last_breakpoint = 0;
1147
1148 /* Effectively inserts the breakpoints. */
1149 for (index = 0; index <= last_breakpoint; index++)
a6d9a66e 1150 insert_single_step_breakpoint (gdbarch, breaks[index]);
ce5eab59
UW		 1151
1152 return 1;
1153}
1154
c906108c 1155
c906108c
SS		 1156#define SIGNED_SHORT(x) \
1157 ((sizeof (short) == 2) \
1158 ? ((int)(short)(x)) \
1159 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
1160
1161#define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
1162
55d05f3b
KB		 1163/* Limit the number of skipped non-prologue instructions, as the examining
1164 of the prologue is expensive. */
1165static int max_skip_non_prologue_insns = 10;
1166
773df3e5
JB		 1167/* Return nonzero if the given instruction OP can be part of the prologue
1168 of a function and saves a parameter on the stack. FRAMEP should be
1169 set if one of the previous instructions in the function has set the
1170 Frame Pointer. */
1171
1172static int
1173store_param_on_stack_p (unsigned long op, int framep, int *r0_contains_arg)
1174{
1175 /* Move parameters from argument registers to temporary register. */
1176 if ((op & 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
1177 {
1178 /* Rx must be scratch register r0. */
1179 const int rx_regno = (op >> 16) & 31;
1180 /* Ry: Only r3 - r10 are used for parameter passing. */
1181 const int ry_regno = GET_SRC_REG (op);
1182
1183 if (rx_regno == 0 && ry_regno >= 3 && ry_regno <= 10)
1184 {
1185 *r0_contains_arg = 1;
1186 return 1;
1187 }
1188 else
1189 return 0;
1190 }
1191
1192 /* Save a General Purpose Register on stack. */
1193
1194 if ((op & 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
1195 (op & 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
1196 {
1197 /* Rx: Only r3 - r10 are used for parameter passing. */
1198 const int rx_regno = GET_SRC_REG (op);
1199
1200 return (rx_regno >= 3 && rx_regno <= 10);
1201 }
1202
1203 /* Save a General Purpose Register on stack via the Frame Pointer. */
1204
1205 if (framep &&
1206 ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
1207 (op & 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
1208 (op & 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
1209 {
1210 /* Rx: Usually, only r3 - r10 are used for parameter passing.
1211 However, the compiler sometimes uses r0 to hold an argument. */
1212 const int rx_regno = GET_SRC_REG (op);
1213
1214 return ((rx_regno >= 3 && rx_regno <= 10)
1215 || (rx_regno == 0 && *r0_contains_arg));
1216 }
1217
1218 if ((op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
1219 {
1220 /* Only f2 - f8 are used for parameter passing. */
1221 const int src_regno = GET_SRC_REG (op);
1222
1223 return (src_regno >= 2 && src_regno <= 8);
1224 }
1225
1226 if (framep && ((op & 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
1227 {
1228 /* Only f2 - f8 are used for parameter passing. */
1229 const int src_regno = GET_SRC_REG (op);
1230
1231 return (src_regno >= 2 && src_regno <= 8);
1232 }
1233
1234 /* Not an insn that saves a parameter on stack. */
1235 return 0;
1236}
55d05f3b 1237
3c77c82a
DJ		 1238/* Assuming that INSN is a "bl" instruction located at PC, return
1239 nonzero if the destination of the branch is a "blrl" instruction.
1240
1241 This sequence is sometimes found in certain function prologues.
1242 It allows the function to load the LR register with a value that
1243 they can use to access PIC data using PC-relative offsets. */
1244
1245static int
e17a4113 1246bl_to_blrl_insn_p (CORE_ADDR pc, int insn, enum bfd_endian byte_order)
3c77c82a 1247{
0b1b3e42
UW		 1248 CORE_ADDR dest;
1249 int immediate;
1250 int absolute;
3c77c82a
DJ		 1251 int dest_insn;
1252
0b1b3e42
UW		 1253 absolute = (int) ((insn >> 1) & 1);
1254 immediate = ((insn & ~3) << 6) >> 6;
1255 if (absolute)
1256 dest = immediate;
1257 else
1258 dest = pc + immediate;
1259
e17a4113 1260 dest_insn = read_memory_integer (dest, 4, byte_order);
3c77c82a
DJ		 1261 if ((dest_insn & 0xfc00ffff) == 0x4c000021) /* blrl */
1262 return 1;
1263
1264 return 0;
1265}
1266
8ab3d180
KB		 1267/* Masks for decoding a branch-and-link (bl) instruction.
1268
1269 BL_MASK and BL_INSTRUCTION are used in combination with each other.
1270 The former is anded with the opcode in question; if the result of
1271 this masking operation is equal to BL_INSTRUCTION, then the opcode in
1272 question is a ``bl'' instruction.
1273
1274 BL_DISPLACMENT_MASK is anded with the opcode in order to extract
1275 the branch displacement. */
1276
1277#define BL_MASK 0xfc000001
1278#define BL_INSTRUCTION 0x48000001
1279#define BL_DISPLACEMENT_MASK 0x03fffffc
1280
de9f48f0 1281static unsigned long
e17a4113 1282rs6000_fetch_instruction (struct gdbarch *gdbarch, const CORE_ADDR pc)
de9f48f0 1283{
e17a4113 1284 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
de9f48f0
JG		 1285 gdb_byte buf[4];
1286 unsigned long op;
1287
1288 /* Fetch the instruction and convert it to an integer. */
1289 if (target_read_memory (pc, buf, 4))
1290 return 0;
e17a4113 1291 op = extract_unsigned_integer (buf, 4, byte_order);
de9f48f0
JG		 1292
1293 return op;
1294}
1295
1296/* GCC generates several well-known sequences of instructions at the begining
1297 of each function prologue when compiling with -fstack-check. If one of
1298 such sequences starts at START_PC, then return the address of the
1299 instruction immediately past this sequence. Otherwise, return START_PC. */
1300
1301static CORE_ADDR
e17a4113 1302rs6000_skip_stack_check (struct gdbarch *gdbarch, const CORE_ADDR start_pc)
de9f48f0
JG		 1303{
1304 CORE_ADDR pc = start_pc;
e17a4113 1305 unsigned long op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1306
1307 /* First possible sequence: A small number of probes.
1308 stw 0, -<some immediate>(1)
1309 [repeat this instruction any (small) number of times]
1310 */
1311
1312 if ((op & 0xffff0000) == 0x90010000)
1313 {
1314 while ((op & 0xffff0000) == 0x90010000)
1315 {
1316 pc = pc + 4;
e17a4113 1317 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1318 }
1319 return pc;
1320 }
1321
1322 /* Second sequence: A probing loop.
1323 addi 12,1,-<some immediate>
1324 lis 0,-<some immediate>
1325 [possibly ori 0,0,<some immediate>]
1326 add 0,12,0
1327 cmpw 0,12,0
1328 beq 0,<disp>
1329 addi 12,12,-<some immediate>
1330 stw 0,0(12)
1331 b <disp>
1332 [possibly one last probe: stw 0,<some immediate>(12)]
1333 */
1334
1335 while (1)
1336 {
1337 /* addi 12,1,-<some immediate> */
1338 if ((op & 0xffff0000) != 0x39810000)
1339 break;
1340
1341 /* lis 0,-<some immediate> */
1342 pc = pc + 4;
e17a4113 1343 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1344 if ((op & 0xffff0000) != 0x3c000000)
1345 break;
1346
1347 pc = pc + 4;
e17a4113 1348 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1349 /* [possibly ori 0,0,<some immediate>] */
1350 if ((op & 0xffff0000) == 0x60000000)
1351 {
1352 pc = pc + 4;
e17a4113 1353 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1354 }
1355 /* add 0,12,0 */
1356 if (op != 0x7c0c0214)
1357 break;
1358
1359 /* cmpw 0,12,0 */
1360 pc = pc + 4;
e17a4113 1361 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1362 if (op != 0x7c0c0000)
1363 break;
1364
1365 /* beq 0,<disp> */
1366 pc = pc + 4;
e17a4113 1367 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1368 if ((op & 0xff9f0001) != 0x41820000)
1369 break;
1370
1371 /* addi 12,12,-<some immediate> */
1372 pc = pc + 4;
e17a4113 1373 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1374 if ((op & 0xffff0000) != 0x398c0000)
1375 break;
1376
1377 /* stw 0,0(12) */
1378 pc = pc + 4;
e17a4113 1379 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1380 if (op != 0x900c0000)
1381 break;
1382
1383 /* b <disp> */
1384 pc = pc + 4;
e17a4113 1385 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1386 if ((op & 0xfc000001) != 0x48000000)
1387 break;
1388
1389 /* [possibly one last probe: stw 0,<some immediate>(12)] */
1390 pc = pc + 4;
e17a4113 1391 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1392 if ((op & 0xffff0000) == 0x900c0000)
1393 {
1394 pc = pc + 4;
e17a4113 1395 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1396 }
1397
1398 /* We found a valid stack-check sequence, return the new PC. */
1399 return pc;
1400 }
1401
1402 /* Third sequence: No probe; instead, a comparizon between the stack size
1403 limit (saved in a run-time global variable) and the current stack
1404 pointer:
1405
1406 addi 0,1,-<some immediate>
1407 lis 12,__gnat_stack_limit@ha
1408 lwz 12,__gnat_stack_limit@l(12)
1409 twllt 0,12
1410
1411 or, with a small variant in the case of a bigger stack frame:
1412 addis 0,1,<some immediate>
1413 addic 0,0,-<some immediate>
1414 lis 12,__gnat_stack_limit@ha
1415 lwz 12,__gnat_stack_limit@l(12)
1416 twllt 0,12
1417 */
1418 while (1)
1419 {
1420 /* addi 0,1,-<some immediate> */
1421 if ((op & 0xffff0000) != 0x38010000)
1422 {
1423 /* small stack frame variant not recognized; try the
1424 big stack frame variant: */
1425
1426 /* addis 0,1,<some immediate> */
1427 if ((op & 0xffff0000) != 0x3c010000)
1428 break;
1429
1430 /* addic 0,0,-<some immediate> */
1431 pc = pc + 4;
e17a4113 1432 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1433 if ((op & 0xffff0000) != 0x30000000)
1434 break;
1435 }
1436
1437 /* lis 12,<some immediate> */
1438 pc = pc + 4;
e17a4113 1439 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1440 if ((op & 0xffff0000) != 0x3d800000)
1441 break;
1442
1443 /* lwz 12,<some immediate>(12) */
1444 pc = pc + 4;
e17a4113 1445 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1446 if ((op & 0xffff0000) != 0x818c0000)
1447 break;
1448
1449 /* twllt 0,12 */
1450 pc = pc + 4;
e17a4113 1451 op = rs6000_fetch_instruction (gdbarch, pc);
de9f48f0
JG		 1452 if ((op & 0xfffffffe) != 0x7c406008)
1453 break;
1454
1455 /* We found a valid stack-check sequence, return the new PC. */
1456 return pc;
1457 }
1458
1459 /* No stack check code in our prologue, return the start_pc. */
1460 return start_pc;
1461}
1462
6a16c029
TJB		 1463/* return pc value after skipping a function prologue and also return
1464 information about a function frame.
1465
1466 in struct rs6000_framedata fdata:
1467 - frameless is TRUE, if function does not have a frame.
1468 - nosavedpc is TRUE, if function does not save %pc value in its frame.
1469 - offset is the initial size of this stack frame --- the amount by
1470 which we decrement the sp to allocate the frame.
1471 - saved_gpr is the number of the first saved gpr.
1472 - saved_fpr is the number of the first saved fpr.
1473 - saved_vr is the number of the first saved vr.
1474 - saved_ev is the number of the first saved ev.
1475 - alloca_reg is the number of the register used for alloca() handling.
1476 Otherwise -1.
1477 - gpr_offset is the offset of the first saved gpr from the previous frame.
1478 - fpr_offset is the offset of the first saved fpr from the previous frame.
1479 - vr_offset is the offset of the first saved vr from the previous frame.
1480 - ev_offset is the offset of the first saved ev from the previous frame.
1481 - lr_offset is the offset of the saved lr
1482 - cr_offset is the offset of the saved cr
1483 - vrsave_offset is the offset of the saved vrsave register
1484 */
1485
7a78ae4e 1486static CORE_ADDR
be8626e0
MD		 1487skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, CORE_ADDR lim_pc,
1488 struct rs6000_framedata *fdata)
c906108c
SS		 1489{
1490 CORE_ADDR orig_pc = pc;
55d05f3b 1491 CORE_ADDR last_prologue_pc = pc;
6be8bc0c 1492 CORE_ADDR li_found_pc = 0;
50fd1280 1493 gdb_byte buf[4];
c906108c
SS		 1494 unsigned long op;
1495 long offset = 0;
6be8bc0c 1496 long vr_saved_offset = 0;
482ca3f5
KB		 1497 int lr_reg = -1;
1498 int cr_reg = -1;
6be8bc0c 1499 int vr_reg = -1;
96ff0de4
EZ		 1500 int ev_reg = -1;
1501 long ev_offset = 0;
6be8bc0c 1502 int vrsave_reg = -1;
c906108c
SS		 1503 int reg;
1504 int framep = 0;
1505 int minimal_toc_loaded = 0;
ddb20c56 1506 int prev_insn_was_prologue_insn = 1;
55d05f3b 1507 int num_skip_non_prologue_insns = 0;
773df3e5 1508 int r0_contains_arg = 0;
be8626e0
MD		 1509 const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (gdbarch);
1510 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
e17a4113 1511 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
c906108c 1512
ddb20c56 1513 memset (fdata, 0, sizeof (struct rs6000_framedata));
c906108c
SS		 1514 fdata->saved_gpr = -1;
1515 fdata->saved_fpr = -1;
6be8bc0c 1516 fdata->saved_vr = -1;
96ff0de4 1517 fdata->saved_ev = -1;
c906108c
SS		 1518 fdata->alloca_reg = -1;
1519 fdata->frameless = 1;
1520 fdata->nosavedpc = 1;
46a9b8ed 1521 fdata->lr_register = -1;
c906108c 1522
e17a4113 1523 pc = rs6000_skip_stack_check (gdbarch, pc);
de9f48f0
JG		 1524 if (pc >= lim_pc)
1525 pc = lim_pc;
1526
55d05f3b 1527 for (;; pc += 4)
c906108c 1528 {
ddb20c56
KB		 1529 /* Sometimes it isn't clear if an instruction is a prologue
1530 instruction or not. When we encounter one of these ambiguous
1531 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
1532 Otherwise, we'll assume that it really is a prologue instruction. */
1533 if (prev_insn_was_prologue_insn)
1534 last_prologue_pc = pc;
55d05f3b
KB		 1535
1536 /* Stop scanning if we've hit the limit. */
4e463ff5 1537 if (pc >= lim_pc)
55d05f3b
KB		 1538 break;
1539
ddb20c56
KB		 1540 prev_insn_was_prologue_insn = 1;
1541
55d05f3b 1542 /* Fetch the instruction and convert it to an integer. */
ddb20c56
KB		 1543 if (target_read_memory (pc, buf, 4))
1544 break;
e17a4113 1545 op = extract_unsigned_integer (buf, 4, byte_order);
c906108c 1546
c5aa993b
JM		 1547 if ((op & 0xfc1fffff) == 0x7c0802a6)
1548 { /* mflr Rx */
43b1ab88
AC		 1549 /* Since shared library / PIC code, which needs to get its
1550 address at runtime, can appear to save more than one link
1551 register vis:
1552
1553 *INDENT-OFF*
1554 stwu r1,-304(r1)
1555 mflr r3
1556 bl 0xff570d0 (blrl)
1557 stw r30,296(r1)
1558 mflr r30
1559 stw r31,300(r1)
1560 stw r3,308(r1);
1561 ...
1562 *INDENT-ON*
1563
1564 remember just the first one, but skip over additional
1565 ones. */
721d14ba 1566 if (lr_reg == -1)
46a9b8ed 1567 lr_reg = (op & 0x03e00000) >> 21;
773df3e5
JB		 1568 if (lr_reg == 0)
1569 r0_contains_arg = 0;
c5aa993b 1570 continue;
c5aa993b
JM		 1571 }
1572 else if ((op & 0xfc1fffff) == 0x7c000026)
1573 { /* mfcr Rx */
98f08d3d 1574 cr_reg = (op & 0x03e00000);
773df3e5
JB		 1575 if (cr_reg == 0)
1576 r0_contains_arg = 0;
c5aa993b 1577 continue;
c906108c 1578
c906108c 1579 }
c5aa993b
JM		 1580 else if ((op & 0xfc1f0000) == 0xd8010000)
1581 { /* stfd Rx,NUM(r1) */
1582 reg = GET_SRC_REG (op);
1583 if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg)
1584 {
1585 fdata->saved_fpr = reg;
1586 fdata->fpr_offset = SIGNED_SHORT (op) + offset;
1587 }
1588 continue;
c906108c 1589
c5aa993b
JM		 1590 }
1591 else if (((op & 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
7a78ae4e
ND		 1592 (((op & 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
1593 (op & 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
1594 (op & 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
c5aa993b
JM		 1595 {
1596
1597 reg = GET_SRC_REG (op);
46a9b8ed
DJ		 1598 if ((op & 0xfc1f0000) == 0xbc010000)
1599 fdata->gpr_mask |= ~((1U << reg) - 1);
1600 else
1601 fdata->gpr_mask |= 1U << reg;
c5aa993b
JM		 1602 if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg)
1603 {
1604 fdata->saved_gpr = reg;
7a78ae4e 1605 if ((op & 0xfc1f0003) == 0xf8010000)
98f08d3d 1606 op &= ~3UL;
c5aa993b
JM		 1607 fdata->gpr_offset = SIGNED_SHORT (op) + offset;
1608 }
1609 continue;
c906108c 1610
ddb20c56
KB		 1611 }
1612 else if ((op & 0xffff0000) == 0x60000000)
1613 {
96ff0de4 1614 /* nop */
ddb20c56
KB		 1615 /* Allow nops in the prologue, but do not consider them to
1616 be part of the prologue unless followed by other prologue
1617 instructions. */
1618 prev_insn_was_prologue_insn = 0;
1619 continue;
1620
c906108c 1621 }
c5aa993b
JM		 1622 else if ((op & 0xffff0000) == 0x3c000000)
1623 { /* addis 0,0,NUM, used
1624 for >= 32k frames */
1625 fdata->offset = (op & 0x0000ffff) << 16;
1626 fdata->frameless = 0;
773df3e5 1627 r0_contains_arg = 0;
c5aa993b
JM		 1628 continue;
1629
1630 }
1631 else if ((op & 0xffff0000) == 0x60000000)
1632 { /* ori 0,0,NUM, 2nd ha
1633 lf of >= 32k frames */
1634 fdata->offset |= (op & 0x0000ffff);
1635 fdata->frameless = 0;
773df3e5 1636 r0_contains_arg = 0;
c5aa993b
JM		 1637 continue;
1638
1639 }
be723e22 1640 else if (lr_reg >= 0 &&
98f08d3d
KB		 1641 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1642 (((op & 0xffff0000) == (lr_reg | 0xf8010000)) ||
1643 /* stw Rx, NUM(r1) */
1644 ((op & 0xffff0000) == (lr_reg | 0x90010000)) ||
1645 /* stwu Rx, NUM(r1) */
1646 ((op & 0xffff0000) == (lr_reg | 0x94010000))))
1647 { /* where Rx == lr */
1648 fdata->lr_offset = offset;
c5aa993b 1649 fdata->nosavedpc = 0;
be723e22
MS		 1650 /* Invalidate lr_reg, but don't set it to -1.
1651 That would mean that it had never been set. */
1652 lr_reg = -2;
98f08d3d
KB		 1653 if ((op & 0xfc000003) == 0xf8000000 || /* std */
1654 (op & 0xfc000000) == 0x90000000) /* stw */
1655 {
1656 /* Does not update r1, so add displacement to lr_offset. */
1657 fdata->lr_offset += SIGNED_SHORT (op);
1658 }
c5aa993b
JM		 1659 continue;
1660
1661 }
be723e22 1662 else if (cr_reg >= 0 &&
98f08d3d
KB		 1663 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1664 (((op & 0xffff0000) == (cr_reg | 0xf8010000)) ||
1665 /* stw Rx, NUM(r1) */
1666 ((op & 0xffff0000) == (cr_reg | 0x90010000)) ||
1667 /* stwu Rx, NUM(r1) */
1668 ((op & 0xffff0000) == (cr_reg | 0x94010000))))
1669 { /* where Rx == cr */
1670 fdata->cr_offset = offset;
be723e22
MS		 1671 /* Invalidate cr_reg, but don't set it to -1.
1672 That would mean that it had never been set. */
1673 cr_reg = -2;
98f08d3d
KB		 1674 if ((op & 0xfc000003) == 0xf8000000 ||
1675 (op & 0xfc000000) == 0x90000000)
1676 {
1677 /* Does not update r1, so add displacement to cr_offset. */
1678 fdata->cr_offset += SIGNED_SHORT (op);
1679 }
c5aa993b
JM		 1680 continue;
1681
1682 }
721d14ba
DJ		 1683 else if ((op & 0xfe80ffff) == 0x42800005 && lr_reg != -1)
1684 {
1685 /* bcl 20,xx,.+4 is used to get the current PC, with or without
1686 prediction bits. If the LR has already been saved, we can
1687 skip it. */
1688 continue;
1689 }
c5aa993b
JM		 1690 else if (op == 0x48000005)
1691 { /* bl .+4 used in
1692 -mrelocatable */
46a9b8ed 1693 fdata->used_bl = 1;
c5aa993b
JM		 1694 continue;
1695
1696 }
1697 else if (op == 0x48000004)
1698 { /* b .+4 (xlc) */
1699 break;
1700
c5aa993b 1701 }
6be8bc0c
EZ		 1702 else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1703 in V.4 -mminimal-toc */
c5aa993b
JM		 1704 (op & 0xffff0000) == 0x3bde0000)
1705 { /* addi 30,30,foo@l */
1706 continue;
c906108c 1707
c5aa993b
JM		 1708 }
1709 else if ((op & 0xfc000001) == 0x48000001)
1710 { /* bl foo,
1711 to save fprs??? */
c906108c 1712
c5aa993b 1713 fdata->frameless = 0;
3c77c82a
DJ		 1714
1715 /* If the return address has already been saved, we can skip
1716 calls to blrl (for PIC). */
e17a4113 1717 if (lr_reg != -1 && bl_to_blrl_insn_p (pc, op, byte_order))
46a9b8ed
DJ		 1718 {
1719 fdata->used_bl = 1;
1720 continue;
1721 }
3c77c82a 1722
6be8bc0c 1723 /* Don't skip over the subroutine call if it is not within
ebd98106
FF		 1724 the first three instructions of the prologue and either
1725 we have no line table information or the line info tells
1726 us that the subroutine call is not part of the line
1727 associated with the prologue. */
c5aa993b 1728 if ((pc - orig_pc) > 8)
ebd98106
FF		 1729 {
1730 struct symtab_and_line prologue_sal = find_pc_line (orig_pc, 0);
1731 struct symtab_and_line this_sal = find_pc_line (pc, 0);
1732
1733 if ((prologue_sal.line == 0) || (prologue_sal.line != this_sal.line))
1734 break;
1735 }
c5aa993b 1736
e17a4113 1737 op = read_memory_integer (pc + 4, 4, byte_order);
c5aa993b 1738
6be8bc0c
EZ		 1739 /* At this point, make sure this is not a trampoline
1740 function (a function that simply calls another functions,
1741 and nothing else). If the next is not a nop, this branch
1742 was part of the function prologue. */
c5aa993b
JM		 1743
1744 if (op == 0x4def7b82 || op == 0) /* crorc 15, 15, 15 */
1745 break; /* don't skip over
1746 this branch */
c5aa993b 1747
46a9b8ed
DJ		 1748 fdata->used_bl = 1;
1749 continue;
c5aa993b 1750 }
98f08d3d
KB		 1751 /* update stack pointer */
1752 else if ((op & 0xfc1f0000) == 0x94010000)
1753 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
c5aa993b
JM		 1754 fdata->frameless = 0;
1755 fdata->offset = SIGNED_SHORT (op);
1756 offset = fdata->offset;
1757 continue;
c5aa993b 1758 }
98f08d3d
KB		 1759 else if ((op & 0xfc1f016a) == 0x7c01016e)
1760 { /* stwux rX,r1,rY */
1761 /* no way to figure out what r1 is going to be */
1762 fdata->frameless = 0;
1763 offset = fdata->offset;
1764 continue;
1765 }
1766 else if ((op & 0xfc1f0003) == 0xf8010001)
1767 { /* stdu rX,NUM(r1) */
1768 fdata->frameless = 0;
1769 fdata->offset = SIGNED_SHORT (op & ~3UL);
1770 offset = fdata->offset;
1771 continue;
1772 }
1773 else if ((op & 0xfc1f016a) == 0x7c01016a)
1774 { /* stdux rX,r1,rY */
1775 /* no way to figure out what r1 is going to be */
c5aa993b
JM		 1776 fdata->frameless = 0;
1777 offset = fdata->offset;
1778 continue;
c5aa993b 1779 }
7313566f
FF		 1780 else if ((op & 0xffff0000) == 0x38210000)
1781 { /* addi r1,r1,SIMM */
1782 fdata->frameless = 0;
1783 fdata->offset += SIGNED_SHORT (op);
1784 offset = fdata->offset;
1785 continue;
1786 }
4e463ff5
DJ		 1787 /* Load up minimal toc pointer. Do not treat an epilogue restore
1788 of r31 as a minimal TOC load. */
98f08d3d
KB		 1789 else if (((op >> 22) == 0x20f || /* l r31,... or l r30,... */
1790 (op >> 22) == 0x3af) /* ld r31,... or ld r30,... */
4e463ff5 1791 && !framep
c5aa993b 1792 && !minimal_toc_loaded)
98f08d3d 1793 {
c5aa993b
JM		 1794 minimal_toc_loaded = 1;
1795 continue;
1796
f6077098
KB		 1797 /* move parameters from argument registers to local variable
1798 registers */
1799 }
1800 else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1801 (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1802 (((op >> 21) & 31) <= 10) &&
96ff0de4 1803 ((long) ((op >> 16) & 31) >= fdata->saved_gpr)) /* Rx: local var reg */
f6077098
KB		 1804 {
1805 continue;
1806
c5aa993b
JM		 1807 /* store parameters in stack */
1808 }
e802b915 1809 /* Move parameters from argument registers to temporary register. */
773df3e5 1810 else if (store_param_on_stack_p (op, framep, &r0_contains_arg))
e802b915 1811 {
c5aa993b
JM		 1812 continue;
1813
1814 /* Set up frame pointer */
1815 }
1816 else if (op == 0x603f0000 /* oril r31, r1, 0x0 */
1817 || op == 0x7c3f0b78)
1818 { /* mr r31, r1 */
1819 fdata->frameless = 0;
1820 framep = 1;
6f99cb26 1821 fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31);
c5aa993b
JM		 1822 continue;
1823
1824 /* Another way to set up the frame pointer. */
1825 }
1826 else if ((op & 0xfc1fffff) == 0x38010000)
1827 { /* addi rX, r1, 0x0 */
1828 fdata->frameless = 0;
1829 framep = 1;
6f99cb26
AC		 1830 fdata->alloca_reg = (tdep->ppc_gp0_regnum
1831 + ((op & ~0x38010000) >> 21));
c5aa993b 1832 continue;
c5aa993b 1833 }
6be8bc0c
EZ		 1834 /* AltiVec related instructions. */
1835 /* Store the vrsave register (spr 256) in another register for
1836 later manipulation, or load a register into the vrsave
1837 register. 2 instructions are used: mfvrsave and
1838 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1839 and mtspr SPR256, Rn. */
1840 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1841 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1842 else if ((op & 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1843 {
1844 vrsave_reg = GET_SRC_REG (op);
1845 continue;
1846 }
1847 else if ((op & 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1848 {
1849 continue;
1850 }
1851 /* Store the register where vrsave was saved to onto the stack:
1852 rS is the register where vrsave was stored in a previous
1853 instruction. */
1854 /* 100100 sssss 00001 dddddddd dddddddd */
1855 else if ((op & 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1856 {
1857 if (vrsave_reg == GET_SRC_REG (op))
1858 {
1859 fdata->vrsave_offset = SIGNED_SHORT (op) + offset;
1860 vrsave_reg = -1;
1861 }
1862 continue;
1863 }
1864 /* Compute the new value of vrsave, by modifying the register
1865 where vrsave was saved to. */
1866 else if (((op & 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1867 || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1868 {
1869 continue;
1870 }
1871 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1872 in a pair of insns to save the vector registers on the
1873 stack. */
1874 /* 001110 00000 00000 iiii iiii iiii iiii */
96ff0de4
EZ		 1875 /* 001110 01110 00000 iiii iiii iiii iiii */
1876 else if ((op & 0xffff0000) == 0x38000000 /* li r0, SIMM */
1877 || (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */
6be8bc0c 1878 {
773df3e5
JB		 1879 if ((op & 0xffff0000) == 0x38000000)
1880 r0_contains_arg = 0;
6be8bc0c
EZ		 1881 li_found_pc = pc;
1882 vr_saved_offset = SIGNED_SHORT (op);
773df3e5
JB		 1883
1884 /* This insn by itself is not part of the prologue, unless
1885 if part of the pair of insns mentioned above. So do not
1886 record this insn as part of the prologue yet. */
1887 prev_insn_was_prologue_insn = 0;
6be8bc0c
EZ		 1888 }
1889 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1890 /* 011111 sssss 11111 00000 00111001110 */
1891 else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
1892 {
1893 if (pc == (li_found_pc + 4))
1894 {
1895 vr_reg = GET_SRC_REG (op);
1896 /* If this is the first vector reg to be saved, or if
1897 it has a lower number than others previously seen,
1898 reupdate the frame info. */
1899 if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg)
1900 {
1901 fdata->saved_vr = vr_reg;
1902 fdata->vr_offset = vr_saved_offset + offset;
1903 }
1904 vr_saved_offset = -1;
1905 vr_reg = -1;
1906 li_found_pc = 0;
1907 }
1908 }
1909 /* End AltiVec related instructions. */
96ff0de4
EZ		 1910
1911 /* Start BookE related instructions. */
1912 /* Store gen register S at (r31+uimm).
1913 Any register less than r13 is volatile, so we don't care. */
1914 /* 000100 sssss 11111 iiiii 01100100001 */
1915 else if (arch_info->mach == bfd_mach_ppc_e500
1916 && (op & 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
1917 {
1918 if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
1919 {
1920 unsigned int imm;
1921 ev_reg = GET_SRC_REG (op);
1922 imm = (op >> 11) & 0x1f;
1923 ev_offset = imm * 8;
1924 /* If this is the first vector reg to be saved, or if
1925 it has a lower number than others previously seen,
1926 reupdate the frame info. */
1927 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1928 {
1929 fdata->saved_ev = ev_reg;
1930 fdata->ev_offset = ev_offset + offset;
1931 }
1932 }
1933 continue;
1934 }
1935 /* Store gen register rS at (r1+rB). */
1936 /* 000100 sssss 00001 bbbbb 01100100000 */
1937 else if (arch_info->mach == bfd_mach_ppc_e500
1938 && (op & 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
1939 {
1940 if (pc == (li_found_pc + 4))
1941 {
1942 ev_reg = GET_SRC_REG (op);
1943 /* If this is the first vector reg to be saved, or if
1944 it has a lower number than others previously seen,
1945 reupdate the frame info. */
1946 /* We know the contents of rB from the previous instruction. */
1947 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1948 {
1949 fdata->saved_ev = ev_reg;
1950 fdata->ev_offset = vr_saved_offset + offset;
1951 }
1952 vr_saved_offset = -1;
1953 ev_reg = -1;
1954 li_found_pc = 0;
1955 }
1956 continue;
1957 }
1958 /* Store gen register r31 at (rA+uimm). */
1959 /* 000100 11111 aaaaa iiiii 01100100001 */
1960 else if (arch_info->mach == bfd_mach_ppc_e500
1961 && (op & 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
1962 {
1963 /* Wwe know that the source register is 31 already, but
1964 it can't hurt to compute it. */
1965 ev_reg = GET_SRC_REG (op);
1966 ev_offset = ((op >> 11) & 0x1f) * 8;
1967 /* If this is the first vector reg to be saved, or if
1968 it has a lower number than others previously seen,
1969 reupdate the frame info. */
1970 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1971 {
1972 fdata->saved_ev = ev_reg;
1973 fdata->ev_offset = ev_offset + offset;
1974 }
1975
1976 continue;
1977 }
1978 /* Store gen register S at (r31+r0).
1979 Store param on stack when offset from SP bigger than 4 bytes. */
1980 /* 000100 sssss 11111 00000 01100100000 */
1981 else if (arch_info->mach == bfd_mach_ppc_e500
1982 && (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
1983 {
1984 if (pc == (li_found_pc + 4))
1985 {
1986 if ((op & 0x03e00000) >= 0x01a00000)
1987 {
1988 ev_reg = GET_SRC_REG (op);
1989 /* If this is the first vector reg to be saved, or if
1990 it has a lower number than others previously seen,
1991 reupdate the frame info. */
1992 /* We know the contents of r0 from the previous
1993 instruction. */
1994 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1995 {
1996 fdata->saved_ev = ev_reg;
1997 fdata->ev_offset = vr_saved_offset + offset;
1998 }
1999 ev_reg = -1;
2000 }
2001 vr_saved_offset = -1;
2002 li_found_pc = 0;
2003 continue;
2004 }
2005 }
2006 /* End BookE related instructions. */
2007
c5aa993b
JM		 2008 else
2009 {
46a9b8ed
DJ		 2010 unsigned int all_mask = ~((1U << fdata->saved_gpr) - 1);
2011
55d05f3b
KB		 2012 /* Not a recognized prologue instruction.
2013 Handle optimizer code motions into the prologue by continuing
2014 the search if we have no valid frame yet or if the return
46a9b8ed
DJ		 2015 address is not yet saved in the frame. Also skip instructions
2016 if some of the GPRs expected to be saved are not yet saved. */
2017 if (fdata->frameless == 0 && fdata->nosavedpc == 0
2018 && (fdata->gpr_mask & all_mask) == all_mask)
55d05f3b
KB		 2019 break;
2020
2021 if (op == 0x4e800020 /* blr */
2022 || op == 0x4e800420) /* bctr */
2023 /* Do not scan past epilogue in frameless functions or
2024 trampolines. */
2025 break;
2026 if ((op & 0xf4000000) == 0x40000000) /* bxx */
64366f1c 2027 /* Never skip branches. */
55d05f3b
KB		 2028 break;
2029
2030 if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns)
2031 /* Do not scan too many insns, scanning insns is expensive with
2032 remote targets. */
2033 break;
2034
2035 /* Continue scanning. */
2036 prev_insn_was_prologue_insn = 0;
2037 continue;
c5aa993b 2038 }
c906108c
SS		 2039 }
2040
2041#if 0
2042/* I have problems with skipping over __main() that I need to address
2043 * sometime. Previously, I used to use misc_function_vector which
2044 * didn't work as well as I wanted to be. -MGO */
2045
2046 /* If the first thing after skipping a prolog is a branch to a function,
2047 this might be a call to an initializer in main(), introduced by gcc2.
64366f1c 2048 We'd like to skip over it as well. Fortunately, xlc does some extra
c906108c 2049 work before calling a function right after a prologue, thus we can
64366f1c 2050 single out such gcc2 behaviour. */
c906108c 2051
c906108c 2052
c5aa993b
JM		 2053 if ((op & 0xfc000001) == 0x48000001)
2054 { /* bl foo, an initializer function? */
e17a4113 2055 op = read_memory_integer (pc + 4, 4, byte_order);
c5aa993b
JM		 2056
2057 if (op == 0x4def7b82)
2058 { /* cror 0xf, 0xf, 0xf (nop) */
c906108c 2059
64366f1c
EZ		 2060 /* Check and see if we are in main. If so, skip over this
2061 initializer function as well. */
c906108c 2062
c5aa993b 2063 tmp = find_pc_misc_function (pc);
6314a349
AC		 2064 if (tmp >= 0
2065 && strcmp (misc_function_vector[tmp].name, main_name ()) == 0)
c5aa993b
JM		 2066 return pc + 8;
2067 }
c906108c 2068 }
c906108c 2069#endif /* 0 */
c5aa993b 2070
46a9b8ed
DJ		 2071 if (pc == lim_pc && lr_reg >= 0)
2072 fdata->lr_register = lr_reg;
2073
c5aa993b 2074 fdata->offset = -fdata->offset;
ddb20c56 2075 return last_prologue_pc;
c906108c
SS		 2076}
2077
7a78ae4e 2078static CORE_ADDR
4a7622d1 2079rs6000_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
c906108c 2080{
4a7622d1
UW		 2081 struct rs6000_framedata frame;
2082 CORE_ADDR limit_pc, func_addr;
c906108c 2083
4a7622d1
UW		 2084 /* See if we can determine the end of the prologue via the symbol table.
2085 If so, then return either PC, or the PC after the prologue, whichever
2086 is greater. */
2087 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
c5aa993b 2088 {
d80b854b
UW		 2089 CORE_ADDR post_prologue_pc
2090 = skip_prologue_using_sal (gdbarch, func_addr);
4a7622d1
UW		 2091 if (post_prologue_pc != 0)
2092 return max (pc, post_prologue_pc);
c906108c 2093 }
c906108c 2094
4a7622d1
UW		 2095 /* Can't determine prologue from the symbol table, need to examine
2096 instructions. */
c906108c 2097
4a7622d1
UW		 2098 /* Find an upper limit on the function prologue using the debug
2099 information. If the debug information could not be used to provide
2100 that bound, then use an arbitrary large number as the upper bound. */
d80b854b 2101 limit_pc = skip_prologue_using_sal (gdbarch, pc);
4a7622d1
UW		 2102 if (limit_pc == 0)
2103 limit_pc = pc + 100; /* Magic. */
794a477a 2104
4a7622d1
UW		 2105 pc = skip_prologue (gdbarch, pc, limit_pc, &frame);
2106 return pc;
c906108c 2107}
c906108c 2108
8ab3d180
KB		 2109/* When compiling for EABI, some versions of GCC emit a call to __eabi
2110 in the prologue of main().
2111
2112 The function below examines the code pointed at by PC and checks to
2113 see if it corresponds to a call to __eabi. If so, it returns the
2114 address of the instruction following that call. Otherwise, it simply
2115 returns PC. */
2116
63807e1d 2117static CORE_ADDR
8ab3d180
KB		 2118rs6000_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
2119{
e17a4113 2120 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
8ab3d180
KB		 2121 gdb_byte buf[4];
2122 unsigned long op;
2123
2124 if (target_read_memory (pc, buf, 4))
2125 return pc;
e17a4113 2126 op = extract_unsigned_integer (buf, 4, byte_order);
8ab3d180
KB		 2127
2128 if ((op & BL_MASK) == BL_INSTRUCTION)
2129 {
2130 CORE_ADDR displ = op & BL_DISPLACEMENT_MASK;
2131 CORE_ADDR call_dest = pc + 4 + displ;
2132 struct minimal_symbol *s = lookup_minimal_symbol_by_pc (call_dest);
2133
2134 /* We check for ___eabi (three leading underscores) in addition
2135 to __eabi in case the GCC option "-fleading-underscore" was
2136 used to compile the program. */
2137 if (s != NULL
2138 && SYMBOL_LINKAGE_NAME (s) != NULL
2139 && (strcmp (SYMBOL_LINKAGE_NAME (s), "__eabi") == 0
2140 || strcmp (SYMBOL_LINKAGE_NAME (s), "___eabi") == 0))
2141 pc += 4;
2142 }
2143 return pc;
2144}
383f0f5b 2145
4a7622d1
UW		 2146/* All the ABI's require 16 byte alignment. */
2147static CORE_ADDR
2148rs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
2149{
2150 return (addr & -16);
c906108c
SS		 2151}
2152
977adac5
ND		 2153/* Return whether handle_inferior_event() should proceed through code
2154 starting at PC in function NAME when stepping.
2155
2156 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
2157 handle memory references that are too distant to fit in instructions
2158 generated by the compiler. For example, if 'foo' in the following
2159 instruction:
2160
2161 lwz r9,foo(r2)
2162
2163 is greater than 32767, the linker might replace the lwz with a branch to
2164 somewhere in @FIX1 that does the load in 2 instructions and then branches
2165 back to where execution should continue.
2166
2167 GDB should silently step over @FIX code, just like AIX dbx does.
2ec664f5
MS		 2168 Unfortunately, the linker uses the "b" instruction for the
2169 branches, meaning that the link register doesn't get set.
2170 Therefore, GDB's usual step_over_function () mechanism won't work.
977adac5 2171
e76f05fa
UW		 2172 Instead, use the gdbarch_skip_trampoline_code and
2173 gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past
2ec664f5 2174 @FIX code. */
977adac5 2175
63807e1d 2176static int
e17a4113
UW		 2177rs6000_in_solib_return_trampoline (struct gdbarch *gdbarch,
2178 CORE_ADDR pc, char *name)
977adac5
ND		 2179{
2180 return name && !strncmp (name, "@FIX", 4);
2181}
2182
2183/* Skip code that the user doesn't want to see when stepping:
2184
2185 1. Indirect function calls use a piece of trampoline code to do context
2186 switching, i.e. to set the new TOC table. Skip such code if we are on
2187 its first instruction (as when we have single-stepped to here).
2188
2189 2. Skip shared library trampoline code (which is different from
c906108c 2190 indirect function call trampolines).
977adac5
ND		 2191
2192 3. Skip bigtoc fixup code.
2193
c906108c 2194 Result is desired PC to step until, or NULL if we are not in
977adac5 2195 code that should be skipped. */
c906108c 2196
63807e1d 2197static CORE_ADDR
52f729a7 2198rs6000_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc)
c906108c 2199{
e17a4113
UW		 2200 struct gdbarch *gdbarch = get_frame_arch (frame);
2201 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2202 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
52f0bd74 2203 unsigned int ii, op;
977adac5 2204 int rel;
c906108c 2205 CORE_ADDR solib_target_pc;
977adac5 2206 struct minimal_symbol *msymbol;
c906108c 2207
c5aa993b
JM		 2208 static unsigned trampoline_code[] =
2209 {
2210 0x800b0000, /* l r0,0x0(r11) */
2211 0x90410014, /* st r2,0x14(r1) */
2212 0x7c0903a6, /* mtctr r0 */
2213 0x804b0004, /* l r2,0x4(r11) */
2214 0x816b0008, /* l r11,0x8(r11) */
2215 0x4e800420, /* bctr */
2216 0x4e800020, /* br */
2217 0
c906108c
SS		 2218 };
2219
977adac5
ND		 2220 /* Check for bigtoc fixup code. */
2221 msymbol = lookup_minimal_symbol_by_pc (pc);
2ec664f5 2222 if (msymbol
e17a4113
UW		 2223 && rs6000_in_solib_return_trampoline (gdbarch, pc,
2224 SYMBOL_LINKAGE_NAME (msymbol)))
977adac5
ND		 2225 {
2226 /* Double-check that the third instruction from PC is relative "b". */
e17a4113 2227 op = read_memory_integer (pc + 8, 4, byte_order);
977adac5
ND		 2228 if ((op & 0xfc000003) == 0x48000000)
2229 {
2230 /* Extract bits 6-29 as a signed 24-bit relative word address and
2231 add it to the containing PC. */
2232 rel = ((int)(op << 6) >> 6);
2233 return pc + 8 + rel;
2234 }
2235 }
2236
c906108c 2237 /* If pc is in a shared library trampoline, return its target. */
52f729a7 2238 solib_target_pc = find_solib_trampoline_target (frame, pc);
c906108c
SS		 2239 if (solib_target_pc)
2240 return solib_target_pc;
2241
c5aa993b
JM		 2242 for (ii = 0; trampoline_code[ii]; ++ii)
2243 {
e17a4113 2244 op = read_memory_integer (pc + (ii * 4), 4, byte_order);
c5aa993b
JM		 2245 if (op != trampoline_code[ii])
2246 return 0;
2247 }
52f729a7 2248 ii = get_frame_register_unsigned (frame, 11); /* r11 holds destination addr */
e17a4113 2249 pc = read_memory_unsigned_integer (ii, tdep->wordsize, byte_order);
c906108c
SS		 2250 return pc;
2251}
2252
794ac428
UW		 2253/* ISA-specific vector types. */
2254
2255static struct type *
2256rs6000_builtin_type_vec64 (struct gdbarch *gdbarch)
2257{
2258 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2259
2260 if (!tdep->ppc_builtin_type_vec64)
2261 {
df4df182
UW		 2262 const struct builtin_type *bt = builtin_type (gdbarch);
2263
794ac428
UW		 2264 /* The type we're building is this: */
2265#if 0
2266 union __gdb_builtin_type_vec64
2267 {
2268 int64_t uint64;
2269 float v2_float[2];
2270 int32_t v2_int32[2];
2271 int16_t v4_int16[4];
2272 int8_t v8_int8[8];
2273 };
2274#endif
2275
2276 struct type *t;
2277
e9bb382b
UW		 2278 t = arch_composite_type (gdbarch,
2279 "__ppc_builtin_type_vec64", TYPE_CODE_UNION);
df4df182 2280 append_composite_type_field (t, "uint64", bt->builtin_int64);
794ac428 2281 append_composite_type_field (t, "v2_float",
df4df182 2282 init_vector_type (bt->builtin_float, 2));
794ac428 2283 append_composite_type_field (t, "v2_int32",
df4df182 2284 init_vector_type (bt->builtin_int32, 2));
794ac428 2285 append_composite_type_field (t, "v4_int16",
df4df182 2286 init_vector_type (bt->builtin_int16, 4));
794ac428 2287 append_composite_type_field (t, "v8_int8",
df4df182 2288 init_vector_type (bt->builtin_int8, 8));
794ac428 2289
876cecd0 2290 TYPE_VECTOR (t) = 1;
794ac428
UW		 2291 TYPE_NAME (t) = "ppc_builtin_type_vec64";
2292 tdep->ppc_builtin_type_vec64 = t;
2293 }
2294
2295 return tdep->ppc_builtin_type_vec64;
2296}
2297
604c2f83
LM		 2298/* Vector 128 type. */
2299
2300static struct type *
2301rs6000_builtin_type_vec128 (struct gdbarch *gdbarch)
2302{
2303 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2304
2305 if (!tdep->ppc_builtin_type_vec128)
2306 {
df4df182
UW		 2307 const struct builtin_type *bt = builtin_type (gdbarch);
2308
604c2f83
LM		 2309 /* The type we're building is this
2310
2311 type = union __ppc_builtin_type_vec128 {
2312 uint128_t uint128;
2313 float v4_float[4];
2314 int32_t v4_int32[4];
2315 int16_t v8_int16[8];
2316 int8_t v16_int8[16];
2317 }
2318 */
2319
2320 struct type *t;
2321
e9bb382b
UW		 2322 t = arch_composite_type (gdbarch,
2323 "__ppc_builtin_type_vec128", TYPE_CODE_UNION);
df4df182 2324 append_composite_type_field (t, "uint128", bt->builtin_uint128);
604c2f83 2325 append_composite_type_field (t, "v4_float",
df4df182 2326 init_vector_type (bt->builtin_float, 4));
604c2f83 2327 append_composite_type_field (t, "v4_int32",
df4df182 2328 init_vector_type (bt->builtin_int32, 4));
604c2f83 2329 append_composite_type_field (t, "v8_int16",
df4df182 2330 init_vector_type (bt->builtin_int16, 8));
604c2f83 2331 append_composite_type_field (t, "v16_int8",
df4df182 2332 init_vector_type (bt->builtin_int8, 16));
604c2f83 2333
803e1097 2334 TYPE_VECTOR (t) = 1;
604c2f83
LM		 2335 TYPE_NAME (t) = "ppc_builtin_type_vec128";
2336 tdep->ppc_builtin_type_vec128 = t;
2337 }
2338
2339 return tdep->ppc_builtin_type_vec128;
2340}
2341
7cc46491
DJ		 2342/* Return the name of register number REGNO, or the empty string if it
2343 is an anonymous register. */
7a78ae4e 2344
fa88f677 2345static const char *
d93859e2 2346rs6000_register_name (struct gdbarch *gdbarch, int regno)
7a78ae4e 2347{
d93859e2 2348 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
7a78ae4e 2349
7cc46491
DJ		 2350 /* The upper half "registers" have names in the XML description,
2351 but we present only the low GPRs and the full 64-bit registers
2352 to the user. */
2353 if (tdep->ppc_ev0_upper_regnum >= 0
2354 && tdep->ppc_ev0_upper_regnum <= regno
2355 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
2356 return "";
2357
604c2f83
LM		 2358 /* Hide the upper halves of the vs0~vs31 registers. */
2359 if (tdep->ppc_vsr0_regnum >= 0
2360 && tdep->ppc_vsr0_upper_regnum <= regno
2361 && regno < tdep->ppc_vsr0_upper_regnum + ppc_num_gprs)
2362 return "";
2363
7cc46491 2364 /* Check if the SPE pseudo registers are available. */
5a9e69ba 2365 if (IS_SPE_PSEUDOREG (tdep, regno))
7cc46491
DJ		 2366 {
2367 static const char *const spe_regnames[] = {
2368 "ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7",
2369 "ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15",
2370 "ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23",
2371 "ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31",
2372 };
2373 return spe_regnames[regno - tdep->ppc_ev0_regnum];
2374 }
2375
f949c649
TJB		 2376 /* Check if the decimal128 pseudo-registers are available. */
2377 if (IS_DFP_PSEUDOREG (tdep, regno))
2378 {
2379 static const char *const dfp128_regnames[] = {
2380 "dl0", "dl1", "dl2", "dl3",
2381 "dl4", "dl5", "dl6", "dl7",
2382 "dl8", "dl9", "dl10", "dl11",
2383 "dl12", "dl13", "dl14", "dl15"
2384 };
2385 return dfp128_regnames[regno - tdep->ppc_dl0_regnum];
2386 }
2387
604c2f83
LM		 2388 /* Check if this is a VSX pseudo-register. */
2389 if (IS_VSX_PSEUDOREG (tdep, regno))
2390 {
2391 static const char *const vsx_regnames[] = {
2392 "vs0", "vs1", "vs2", "vs3", "vs4", "vs5", "vs6", "vs7",
2393 "vs8", "vs9", "vs10", "vs11", "vs12", "vs13", "vs14",
2394 "vs15", "vs16", "vs17", "vs18", "vs19", "vs20", "vs21",
2395 "vs22", "vs23", "vs24", "vs25", "vs26", "vs27", "vs28",
2396 "vs29", "vs30", "vs31", "vs32", "vs33", "vs34", "vs35",
2397 "vs36", "vs37", "vs38", "vs39", "vs40", "vs41", "vs42",
2398 "vs43", "vs44", "vs45", "vs46", "vs47", "vs48", "vs49",
2399 "vs50", "vs51", "vs52", "vs53", "vs54", "vs55", "vs56",
2400 "vs57", "vs58", "vs59", "vs60", "vs61", "vs62", "vs63"
2401 };
2402 return vsx_regnames[regno - tdep->ppc_vsr0_regnum];
2403 }
2404
2405 /* Check if the this is a Extended FP pseudo-register. */
2406 if (IS_EFP_PSEUDOREG (tdep, regno))
2407 {
2408 static const char *const efpr_regnames[] = {
2409 "f32", "f33", "f34", "f35", "f36", "f37", "f38",
2410 "f39", "f40", "f41", "f42", "f43", "f44", "f45",
2411 "f46", "f47", "f48", "f49", "f50", "f51",
2412 "f52", "f53", "f54", "f55", "f56", "f57",
2413 "f58", "f59", "f60", "f61", "f62", "f63"
2414 };
2415 return efpr_regnames[regno - tdep->ppc_efpr0_regnum];
2416 }
2417
d93859e2 2418 return tdesc_register_name (gdbarch, regno);
7a78ae4e
ND		 2419}
2420
7cc46491
DJ		 2421/* Return the GDB type object for the "standard" data type of data in
2422 register N. */
7a78ae4e
ND		 2423
2424static struct type *
7cc46491 2425rs6000_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
7a78ae4e 2426{
691d145a 2427 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
7a78ae4e 2428
7cc46491 2429 /* These are the only pseudo-registers we support. */
f949c649 2430 gdb_assert (IS_SPE_PSEUDOREG (tdep, regnum)
604c2f83
LM		 2431 || IS_DFP_PSEUDOREG (tdep, regnum)
2432 || IS_VSX_PSEUDOREG (tdep, regnum)
2433 || IS_EFP_PSEUDOREG (tdep, regnum));
7cc46491 2434
f949c649
TJB		 2435 /* These are the e500 pseudo-registers. */
2436 if (IS_SPE_PSEUDOREG (tdep, regnum))
2437 return rs6000_builtin_type_vec64 (gdbarch);
604c2f83
LM		 2438 else if (IS_DFP_PSEUDOREG (tdep, regnum))
2439 /* PPC decimal128 pseudo-registers. */
f949c649 2440 return builtin_type (gdbarch)->builtin_declong;
604c2f83
LM		 2441 else if (IS_VSX_PSEUDOREG (tdep, regnum))
2442 /* POWER7 VSX pseudo-registers. */
2443 return rs6000_builtin_type_vec128 (gdbarch);
2444 else
2445 /* POWER7 Extended FP pseudo-registers. */
2446 return builtin_type (gdbarch)->builtin_double;
7a78ae4e
ND		 2447}
2448
c44ca51c
AC		 2449/* Is REGNUM a member of REGGROUP? */
2450static int
7cc46491
DJ		 2451rs6000_pseudo_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2452 struct reggroup *group)
c44ca51c
AC		 2453{
2454 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
c44ca51c 2455
7cc46491 2456 /* These are the only pseudo-registers we support. */
f949c649 2457 gdb_assert (IS_SPE_PSEUDOREG (tdep, regnum)
604c2f83
LM		 2458 || IS_DFP_PSEUDOREG (tdep, regnum)
2459 || IS_VSX_PSEUDOREG (tdep, regnum)
2460 || IS_EFP_PSEUDOREG (tdep, regnum));
c44ca51c 2461
604c2f83
LM		 2462 /* These are the e500 pseudo-registers or the POWER7 VSX registers. */
2463 if (IS_SPE_PSEUDOREG (tdep, regnum) || IS_VSX_PSEUDOREG (tdep, regnum))
f949c649 2464 return group == all_reggroup || group == vector_reggroup;
7cc46491 2465 else
604c2f83 2466 /* PPC decimal128 or Extended FP pseudo-registers. */
f949c649 2467 return group == all_reggroup || group == float_reggroup;
c44ca51c
AC		 2468}
2469
691d145a 2470/* The register format for RS/6000 floating point registers is always
64366f1c 2471 double, we need a conversion if the memory format is float. */
7a78ae4e
ND		 2472
2473static int
0abe36f5
MD		 2474rs6000_convert_register_p (struct gdbarch *gdbarch, int regnum,
2475 struct type *type)
7a78ae4e 2476{
0abe36f5 2477 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
7cc46491
DJ		 2478
2479 return (tdep->ppc_fp0_regnum >= 0
2480 && regnum >= tdep->ppc_fp0_regnum
2481 && regnum < tdep->ppc_fp0_regnum + ppc_num_fprs
2482 && TYPE_CODE (type) == TYPE_CODE_FLT
0dfff4cb
UW		 2483 && TYPE_LENGTH (type)
2484 != TYPE_LENGTH (builtin_type (gdbarch)->builtin_double));
7a78ae4e
ND		 2485}
2486
7a78ae4e 2487static void
691d145a
JB		 2488rs6000_register_to_value (struct frame_info *frame,
2489 int regnum,
2490 struct type *type,
50fd1280 2491 gdb_byte *to)
7a78ae4e 2492{
0dfff4cb 2493 struct gdbarch *gdbarch = get_frame_arch (frame);
50fd1280 2494 gdb_byte from[MAX_REGISTER_SIZE];
691d145a 2495
691d145a 2496 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
7a78ae4e 2497
691d145a 2498 get_frame_register (frame, regnum, from);
0dfff4cb
UW		 2499 convert_typed_floating (from, builtin_type (gdbarch)->builtin_double,
2500 to, type);
691d145a 2501}
7a292a7a 2502
7a78ae4e 2503static void
691d145a
JB		 2504rs6000_value_to_register (struct frame_info *frame,
2505 int regnum,
2506 struct type *type,
50fd1280 2507 const gdb_byte *from)
7a78ae4e 2508{
0dfff4cb 2509 struct gdbarch *gdbarch = get_frame_arch (frame);
50fd1280 2510 gdb_byte to[MAX_REGISTER_SIZE];
691d145a 2511
691d145a
JB		 2512 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
2513
0dfff4cb
UW		 2514 convert_typed_floating (from, type,
2515 to, builtin_type (gdbarch)->builtin_double);
691d145a 2516 put_frame_register (frame, regnum, to);
7a78ae4e 2517}
c906108c 2518
6ced10dd
JB		 2519/* Move SPE vector register values between a 64-bit buffer and the two
2520 32-bit raw register halves in a regcache. This function handles
2521 both splitting a 64-bit value into two 32-bit halves, and joining
2522 two halves into a whole 64-bit value, depending on the function
2523 passed as the MOVE argument.
2524
2525 EV_REG must be the number of an SPE evN vector register --- a
2526 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
2527 64-bit buffer.
2528
2529 Call MOVE once for each 32-bit half of that register, passing
2530 REGCACHE, the number of the raw register corresponding to that
2531 half, and the address of the appropriate half of BUFFER.
2532
2533 For example, passing 'regcache_raw_read' as the MOVE function will
2534 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
2535 'regcache_raw_supply' will supply the contents of BUFFER to the
2536 appropriate pair of raw registers in REGCACHE.
2537
2538 You may need to cast away some 'const' qualifiers when passing
2539 MOVE, since this function can't tell at compile-time which of
2540 REGCACHE or BUFFER is acting as the source of the data. If C had
2541 co-variant type qualifiers, ... */
2542static void
2543e500_move_ev_register (void (*move) (struct regcache *regcache,
50fd1280 2544 int regnum, gdb_byte *buf),
6ced10dd 2545 struct regcache *regcache, int ev_reg,
50fd1280 2546 gdb_byte *buffer)
6ced10dd
JB		 2547{
2548 struct gdbarch *arch = get_regcache_arch (regcache);
2549 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
2550 int reg_index;
50fd1280 2551 gdb_byte *byte_buffer = buffer;
6ced10dd 2552
5a9e69ba 2553 gdb_assert (IS_SPE_PSEUDOREG (tdep, ev_reg));
6ced10dd
JB		 2554
2555 reg_index = ev_reg - tdep->ppc_ev0_regnum;
2556
8b164abb 2557 if (gdbarch_byte_order (arch) == BFD_ENDIAN_BIG)
6ced10dd
JB		 2558 {
2559 move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer);
2560 move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer + 4);
2561 }
2562 else
2563 {
2564 move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer);
2565 move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer + 4);
2566 }
2567}
2568
c8001721
EZ		 2569static void
2570e500_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
50fd1280 2571 int reg_nr, gdb_byte *buffer)
f949c649
TJB		 2572{
2573 e500_move_ev_register (regcache_raw_read, regcache, reg_nr, buffer);
2574}
2575
2576static void
2577e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2578 int reg_nr, const gdb_byte *buffer)
2579{
2580 e500_move_ev_register ((void (*) (struct regcache *, int, gdb_byte *))
2581 regcache_raw_write,
2582 regcache, reg_nr, (gdb_byte *) buffer);
2583}
2584
604c2f83 2585/* Read method for DFP pseudo-registers. */
f949c649 2586static void
604c2f83 2587dfp_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
f949c649
TJB		 2588 int reg_nr, gdb_byte *buffer)
2589{
2590 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2591 int reg_index = reg_nr - tdep->ppc_dl0_regnum;
2592
2593 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2594 {
2595 /* Read two FP registers to form a whole dl register. */
2596 regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2597 2 * reg_index, buffer);
2598 regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2599 2 * reg_index + 1, buffer + 8);
2600 }
2601 else
2602 {
2603 regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2604 2 * reg_index + 1, buffer + 8);
2605 regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2606 2 * reg_index, buffer);
2607 }
2608}
2609
604c2f83 2610/* Write method for DFP pseudo-registers. */
f949c649 2611static void
604c2f83 2612dfp_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
f949c649
TJB		 2613 int reg_nr, const gdb_byte *buffer)
2614{
2615 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2616 int reg_index = reg_nr - tdep->ppc_dl0_regnum;
2617
2618 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2619 {
2620 /* Write each half of the dl register into a separate
2621 FP register. */
2622 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2623 2 * reg_index, buffer);
2624 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2625 2 * reg_index + 1, buffer + 8);
2626 }
2627 else
2628 {
2629 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2630 2 * reg_index + 1, buffer + 8);
2631 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2632 2 * reg_index, buffer);
2633 }
2634}
2635
604c2f83
LM		 2636/* Read method for POWER7 VSX pseudo-registers. */
2637static void
2638vsx_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2639 int reg_nr, gdb_byte *buffer)
2640{
2641 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2642 int reg_index = reg_nr - tdep->ppc_vsr0_regnum;
2643
2644 /* Read the portion that overlaps the VMX registers. */
2645 if (reg_index > 31)
2646 regcache_raw_read (regcache, tdep->ppc_vr0_regnum +
2647 reg_index - 32, buffer);
2648 else
2649 /* Read the portion that overlaps the FPR registers. */
2650 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2651 {
2652 regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2653 reg_index, buffer);
2654 regcache_raw_read (regcache, tdep->ppc_vsr0_upper_regnum +
2655 reg_index, buffer + 8);
2656 }
2657 else
2658 {
2659 regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2660 reg_index, buffer + 8);
2661 regcache_raw_read (regcache, tdep->ppc_vsr0_upper_regnum +
2662 reg_index, buffer);
2663 }
2664}
2665
2666/* Write method for POWER7 VSX pseudo-registers. */
2667static void
2668vsx_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2669 int reg_nr, const gdb_byte *buffer)
2670{
2671 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2672 int reg_index = reg_nr - tdep->ppc_vsr0_regnum;
2673
2674 /* Write the portion that overlaps the VMX registers. */
2675 if (reg_index > 31)
2676 regcache_raw_write (regcache, tdep->ppc_vr0_regnum +
2677 reg_index - 32, buffer);
2678 else
2679 /* Write the portion that overlaps the FPR registers. */
2680 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2681 {
2682 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2683 reg_index, buffer);
2684 regcache_raw_write (regcache, tdep->ppc_vsr0_upper_regnum +
2685 reg_index, buffer + 8);
2686 }
2687 else
2688 {
2689 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2690 reg_index, buffer + 8);
2691 regcache_raw_write (regcache, tdep->ppc_vsr0_upper_regnum +
2692 reg_index, buffer);
2693 }
2694}
2695
2696/* Read method for POWER7 Extended FP pseudo-registers. */
2697static void
2698efpr_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2699 int reg_nr, gdb_byte *buffer)
2700{
2701 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2702 int reg_index = reg_nr - tdep->ppc_efpr0_regnum;
2703
2704 /* Read the portion that overlaps the VMX registers. */
2705 regcache_raw_read (regcache, tdep->ppc_vr0_regnum +
2706 reg_index, buffer);
2707}
2708
2709/* Write method for POWER7 Extended FP pseudo-registers. */
2710static void
2711efpr_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2712 int reg_nr, const gdb_byte *buffer)
2713{
2714 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2715 int reg_index = reg_nr - tdep->ppc_efpr0_regnum;
2716
2717 /* Write the portion that overlaps the VMX registers. */
2718 regcache_raw_write (regcache, tdep->ppc_vr0_regnum +
2719 reg_index, buffer);
2720}
2721
f949c649
TJB		 2722static void
2723rs6000_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2724 int reg_nr, gdb_byte *buffer)
c8001721 2725{
6ced10dd 2726 struct gdbarch *regcache_arch = get_regcache_arch (regcache);
c8001721
EZ		 2727 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2728
6ced10dd 2729 gdb_assert (regcache_arch == gdbarch);
f949c649 2730
5a9e69ba 2731 if (IS_SPE_PSEUDOREG (tdep, reg_nr))
f949c649
TJB		 2732 e500_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
2733 else if (IS_DFP_PSEUDOREG (tdep, reg_nr))
604c2f83
LM		 2734 dfp_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
2735 else if (IS_VSX_PSEUDOREG (tdep, reg_nr))
2736 vsx_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
2737 else if (IS_EFP_PSEUDOREG (tdep, reg_nr))
2738 efpr_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
6ced10dd 2739 else
a44bddec 2740 internal_error (__FILE__, __LINE__,
f949c649
TJB		 2741 _("rs6000_pseudo_register_read: "
2742 "called on unexpected register '%s' (%d)"),
2743 gdbarch_register_name (gdbarch, reg_nr), reg_nr);
c8001721
EZ		 2744}
2745
2746static void
f949c649
TJB		 2747rs6000_pseudo_register_write (struct gdbarch *gdbarch,
2748 struct regcache *regcache,
2749 int reg_nr, const gdb_byte *buffer)
c8001721 2750{
6ced10dd 2751 struct gdbarch *regcache_arch = get_regcache_arch (regcache);
c8001721
EZ		 2752 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2753
6ced10dd 2754 gdb_assert (regcache_arch == gdbarch);
f949c649 2755
5a9e69ba 2756 if (IS_SPE_PSEUDOREG (tdep, reg_nr))
f949c649
TJB		 2757 e500_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
2758 else if (IS_DFP_PSEUDOREG (tdep, reg_nr))
604c2f83
LM		 2759 dfp_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
2760 else if (IS_VSX_PSEUDOREG (tdep, reg_nr))
2761 vsx_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
2762 else if (IS_EFP_PSEUDOREG (tdep, reg_nr))
2763 efpr_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
6ced10dd 2764 else
a44bddec 2765 internal_error (__FILE__, __LINE__,
f949c649
TJB		 2766 _("rs6000_pseudo_register_write: "
2767 "called on unexpected register '%s' (%d)"),
2768 gdbarch_register_name (gdbarch, reg_nr), reg_nr);
6ced10dd
JB		 2769}
2770
18ed0c4e 2771/* Convert a DBX STABS register number to a GDB register number. */
c8001721 2772static int
d3f73121 2773rs6000_stab_reg_to_regnum (struct gdbarch *gdbarch, int num)
c8001721 2774{
d3f73121 2775 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
c8001721 2776
9f744501
JB		 2777 if (0 <= num && num <= 31)
2778 return tdep->ppc_gp0_regnum + num;
2779 else if (32 <= num && num <= 63)
383f0f5b
JB		 2780 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2781 specifies registers the architecture doesn't have? Our
2782 callers don't check the value we return. */
366f009f 2783 return tdep->ppc_fp0_regnum + (num - 32);
18ed0c4e
JB		 2784 else if (77 <= num && num <= 108)
2785 return tdep->ppc_vr0_regnum + (num - 77);
9f744501
JB		 2786 else if (1200 <= num && num < 1200 + 32)
2787 return tdep->ppc_ev0_regnum + (num - 1200);
2788 else
2789 switch (num)
2790 {
2791 case 64:
2792 return tdep->ppc_mq_regnum;
2793 case 65:
2794 return tdep->ppc_lr_regnum;
2795 case 66:
2796 return tdep->ppc_ctr_regnum;
2797 case 76:
2798 return tdep->ppc_xer_regnum;
2799 case 109:
2800 return tdep->ppc_vrsave_regnum;
18ed0c4e
JB		 2801 case 110:
2802 return tdep->ppc_vrsave_regnum - 1; /* vscr */
867e2dc5 2803 case 111:
18ed0c4e 2804 return tdep->ppc_acc_regnum;
867e2dc5 2805 case 112:
18ed0c4e 2806 return tdep->ppc_spefscr_regnum;
9f744501
JB		 2807 default:
2808 return num;
2809 }
18ed0c4e 2810}
9f744501 2811
9f744501 2812
18ed0c4e
JB		 2813/* Convert a Dwarf 2 register number to a GDB register number. */
2814static int
d3f73121 2815rs6000_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int num)
18ed0c4e 2816{
d3f73121 2817 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
9f744501 2818
18ed0c4e
JB		 2819 if (0 <= num && num <= 31)
2820 return tdep->ppc_gp0_regnum + num;
2821 else if (32 <= num && num <= 63)
2822 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2823 specifies registers the architecture doesn't have? Our
2824 callers don't check the value we return. */
2825 return tdep->ppc_fp0_regnum + (num - 32);
2826 else if (1124 <= num && num < 1124 + 32)
2827 return tdep->ppc_vr0_regnum + (num - 1124);
2828 else if (1200 <= num && num < 1200 + 32)
2829 return tdep->ppc_ev0_regnum + (num - 1200);
2830 else
2831 switch (num)
2832 {
a489f789
AS		 2833 case 64:
2834 return tdep->ppc_cr_regnum;
18ed0c4e
JB		 2835 case 67:
2836 return tdep->ppc_vrsave_regnum - 1; /* vscr */
2837 case 99:
2838 return tdep->ppc_acc_regnum;
2839 case 100:
2840 return tdep->ppc_mq_regnum;
2841 case 101:
2842 return tdep->ppc_xer_regnum;
2843 case 108:
2844 return tdep->ppc_lr_regnum;
2845 case 109:
2846 return tdep->ppc_ctr_regnum;
2847 case 356:
2848 return tdep->ppc_vrsave_regnum;
2849 case 612:
2850 return tdep->ppc_spefscr_regnum;
2851 default:
2852 return num;
2853 }
2188cbdd
EZ		 2854}
2855
4fc771b8
DJ		 2856/* Translate a .eh_frame register to DWARF register, or adjust a
2857 .debug_frame register. */
2858
2859static int
2860rs6000_adjust_frame_regnum (struct gdbarch *gdbarch, int num, int eh_frame_p)
2861{
2862 /* GCC releases before 3.4 use GCC internal register numbering in
2863 .debug_frame (and .debug_info, et cetera). The numbering is
2864 different from the standard SysV numbering for everything except
2865 for GPRs and FPRs. We can not detect this problem in most cases
2866 - to get accurate debug info for variables living in lr, ctr, v0,
2867 et cetera, use a newer version of GCC. But we must detect
2868 one important case - lr is in column 65 in .debug_frame output,
2869 instead of 108.
2870
2871 GCC 3.4, and the "hammer" branch, have a related problem. They
2872 record lr register saves in .debug_frame as 108, but still record
2873 the return column as 65. We fix that up too.
2874
2875 We can do this because 65 is assigned to fpsr, and GCC never
2876 generates debug info referring to it. To add support for
2877 handwritten debug info that restores fpsr, we would need to add a
2878 producer version check to this. */
2879 if (!eh_frame_p)
2880 {
2881 if (num == 65)
2882 return 108;
2883 else
2884 return num;
2885 }
2886
2887 /* .eh_frame is GCC specific. For binary compatibility, it uses GCC
2888 internal register numbering; translate that to the standard DWARF2
2889 register numbering. */
2890 if (0 <= num && num <= 63) /* r0-r31,fp0-fp31 */
2891 return num;
2892 else if (68 <= num && num <= 75) /* cr0-cr8 */
2893 return num - 68 + 86;
2894 else if (77 <= num && num <= 108) /* vr0-vr31 */
2895 return num - 77 + 1124;
2896 else
2897 switch (num)
2898 {
2899 case 64: /* mq */
2900 return 100;
2901 case 65: /* lr */
2902 return 108;
2903 case 66: /* ctr */
2904 return 109;
2905 case 76: /* xer */
2906 return 101;
2907 case 109: /* vrsave */
2908 return 356;
2909 case 110: /* vscr */
2910 return 67;
2911 case 111: /* spe_acc */
2912 return 99;
2913 case 112: /* spefscr */
2914 return 612;
2915 default:
2916 return num;
2917 }
2918}
c906108c 2919\f
c5aa993b 2920
7a78ae4e 2921/* Handling the various POWER/PowerPC variants. */
c906108c 2922
c906108c 2923/* Information about a particular processor variant. */
7a78ae4e 2924
c906108c 2925struct variant
c5aa993b
JM		 2926 {
2927 /* Name of this variant. */
2928 char *name;
c906108c 2929
c5aa993b
JM		 2930 /* English description of the variant. */
2931 char *description;
c906108c 2932
64366f1c 2933 /* bfd_arch_info.arch corresponding to variant. */
7a78ae4e
ND		 2934 enum bfd_architecture arch;
2935
64366f1c 2936 /* bfd_arch_info.mach corresponding to variant. */
7a78ae4e
ND		 2937 unsigned long mach;
2938
7cc46491
DJ		 2939 /* Target description for this variant. */
2940 struct target_desc **tdesc;
c5aa993b 2941 };
c906108c 2942
489461e2 2943static struct variant variants[] =
c906108c 2944{
7a78ae4e 2945 {"powerpc", "PowerPC user-level", bfd_arch_powerpc,
7284e1be 2946 bfd_mach_ppc, &tdesc_powerpc_altivec32},
7a78ae4e 2947 {"power", "POWER user-level", bfd_arch_rs6000,
7cc46491 2948 bfd_mach_rs6k, &tdesc_rs6000},
7a78ae4e 2949 {"403", "IBM PowerPC 403", bfd_arch_powerpc,
7cc46491 2950 bfd_mach_ppc_403, &tdesc_powerpc_403},
7a78ae4e 2951 {"601", "Motorola PowerPC 601", bfd_arch_powerpc,
7cc46491 2952 bfd_mach_ppc_601, &tdesc_powerpc_601},
7a78ae4e 2953 {"602", "Motorola PowerPC 602", bfd_arch_powerpc,
7cc46491 2954 bfd_mach_ppc_602, &tdesc_powerpc_602},
7a78ae4e 2955 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc,
7cc46491 2956 bfd_mach_ppc_603, &tdesc_powerpc_603},
7a78ae4e 2957 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc,
7cc46491 2958 604, &tdesc_powerpc_604},
7a78ae4e 2959 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc,
7cc46491 2960 bfd_mach_ppc_403gc, &tdesc_powerpc_403gc},
7a78ae4e 2961 {"505", "Motorola PowerPC 505", bfd_arch_powerpc,
7cc46491 2962 bfd_mach_ppc_505, &tdesc_powerpc_505},
7a78ae4e 2963 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc,
7cc46491 2964 bfd_mach_ppc_860, &tdesc_powerpc_860},
7a78ae4e 2965 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc,
7cc46491 2966 bfd_mach_ppc_750, &tdesc_powerpc_750},
1fcc0bb8 2967 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc,
7cc46491 2968 bfd_mach_ppc_7400, &tdesc_powerpc_7400},
c8001721 2969 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc,
7cc46491 2970 bfd_mach_ppc_e500, &tdesc_powerpc_e500},
7a78ae4e 2971
5d57ee30
KB		 2972 /* 64-bit */
2973 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc,
7284e1be 2974 bfd_mach_ppc64, &tdesc_powerpc_altivec64},
7a78ae4e 2975 {"620", "Motorola PowerPC 620", bfd_arch_powerpc,
7cc46491 2976 bfd_mach_ppc_620, &tdesc_powerpc_64},
5d57ee30 2977 {"630", "Motorola PowerPC 630", bfd_arch_powerpc,
7cc46491 2978 bfd_mach_ppc_630, &tdesc_powerpc_64},
7a78ae4e 2979 {"a35", "PowerPC A35", bfd_arch_powerpc,
7cc46491 2980 bfd_mach_ppc_a35, &tdesc_powerpc_64},
5d57ee30 2981 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc,
7cc46491 2982 bfd_mach_ppc_rs64ii, &tdesc_powerpc_64},
5d57ee30 2983 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc,
7cc46491 2984 bfd_mach_ppc_rs64iii, &tdesc_powerpc_64},
5d57ee30 2985
64366f1c 2986 /* FIXME: I haven't checked the register sets of the following. */
7a78ae4e 2987 {"rs1", "IBM POWER RS1", bfd_arch_rs6000,
7cc46491 2988 bfd_mach_rs6k_rs1, &tdesc_rs6000},
7a78ae4e 2989 {"rsc", "IBM POWER RSC", bfd_arch_rs6000,
7cc46491 2990 bfd_mach_rs6k_rsc, &tdesc_rs6000},
7a78ae4e 2991 {"rs2", "IBM POWER RS2", bfd_arch_rs6000,
7cc46491 2992 bfd_mach_rs6k_rs2, &tdesc_rs6000},
7a78ae4e 2993
7cc46491 2994 {0, 0, 0, 0, 0}
c906108c
SS		 2995};
2996
7a78ae4e 2997/* Return the variant corresponding to architecture ARCH and machine number
64366f1c 2998 MACH. If no such variant exists, return null. */
c906108c 2999
7a78ae4e
ND		 3000static const struct variant *
3001find_variant_by_arch (enum bfd_architecture arch, unsigned long mach)
c906108c 3002{
7a78ae4e 3003 const struct variant *v;
c5aa993b 3004
7a78ae4e
ND		 3005 for (v = variants; v->name; v++)
3006 if (arch == v->arch && mach == v->mach)
3007 return v;
c906108c 3008
7a78ae4e 3009 return NULL;
c906108c 3010}
9364a0ef
EZ		 3011
3012static int
3013gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info)
3014{
ee4f0f76
DJ		 3015 if (!info->disassembler_options)
3016 info->disassembler_options = "any";
3017
40887e1a 3018 if (info->endian == BFD_ENDIAN_BIG)
9364a0ef
EZ		 3019 return print_insn_big_powerpc (memaddr, info);
3020 else
3021 return print_insn_little_powerpc (memaddr, info);
3022}
7a78ae4e 3023\f
61a65099
KB		 3024static CORE_ADDR
3025rs6000_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
3026{
3e8c568d 3027 return frame_unwind_register_unsigned (next_frame,
8b164abb 3028 gdbarch_pc_regnum (gdbarch));
61a65099
KB		 3029}
3030
3031static struct frame_id
1af5d7ce 3032rs6000_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
61a65099 3033{
1af5d7ce
UW		 3034 return frame_id_build (get_frame_register_unsigned
3035 (this_frame, gdbarch_sp_regnum (gdbarch)),
3036 get_frame_pc (this_frame));
61a65099
KB		 3037}
3038
3039struct rs6000_frame_cache
3040{
3041 CORE_ADDR base;
3042 CORE_ADDR initial_sp;
3043 struct trad_frame_saved_reg *saved_regs;
3044};
3045
3046static struct rs6000_frame_cache *
1af5d7ce 3047rs6000_frame_cache (struct frame_info *this_frame, void **this_cache)
61a65099
KB		 3048{
3049 struct rs6000_frame_cache *cache;
1af5d7ce 3050 struct gdbarch *gdbarch = get_frame_arch (this_frame);
61a65099 3051 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
e17a4113 3052 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
61a65099
KB		 3053 struct rs6000_framedata fdata;
3054 int wordsize = tdep->wordsize;
e10b1c4c 3055 CORE_ADDR func, pc;
61a65099
KB		 3056
3057 if ((*this_cache) != NULL)
3058 return (*this_cache);
3059 cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache);
3060 (*this_cache) = cache;
1af5d7ce 3061 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
61a65099 3062
1af5d7ce
UW		 3063 func = get_frame_func (this_frame);
3064 pc = get_frame_pc (this_frame);
be8626e0 3065 skip_prologue (gdbarch, func, pc, &fdata);
e10b1c4c
DJ		 3066
3067 /* Figure out the parent's stack pointer. */
3068
3069 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
3070 address of the current frame. Things might be easier if the
3071 ->frame pointed to the outer-most address of the frame. In
3072 the mean time, the address of the prev frame is used as the
3073 base address of this frame. */
1af5d7ce
UW		 3074 cache->base = get_frame_register_unsigned
3075 (this_frame, gdbarch_sp_regnum (gdbarch));
e10b1c4c
DJ		 3076
3077 /* If the function appears to be frameless, check a couple of likely
3078 indicators that we have simply failed to find the frame setup.
3079 Two common cases of this are missing symbols (i.e.
ef02daa9 3080 get_frame_func returns the wrong address or 0), and assembly
e10b1c4c
DJ		 3081 stubs which have a fast exit path but set up a frame on the slow
3082 path.
3083
3084 If the LR appears to return to this function, then presume that
3085 we have an ABI compliant frame that we failed to find. */
3086 if (fdata.frameless && fdata.lr_offset == 0)
61a65099 3087 {
e10b1c4c
DJ		 3088 CORE_ADDR saved_lr;
3089 int make_frame = 0;
3090
1af5d7ce 3091 saved_lr = get_frame_register_unsigned (this_frame, tdep->ppc_lr_regnum);
e10b1c4c
DJ		 3092 if (func == 0 && saved_lr == pc)
3093 make_frame = 1;
3094 else if (func != 0)
3095 {
3096 CORE_ADDR saved_func = get_pc_function_start (saved_lr);
3097 if (func == saved_func)
3098 make_frame = 1;
3099 }
3100
3101 if (make_frame)
3102 {
3103 fdata.frameless = 0;
de6a76fd 3104 fdata.lr_offset = tdep->lr_frame_offset;
e10b1c4c 3105 }
61a65099 3106 }
e10b1c4c
DJ		 3107
3108 if (!fdata.frameless)
3109 /* Frameless really means stackless. */
e17a4113
UW		 3110 cache->base
3111 = read_memory_unsigned_integer (cache->base, wordsize, byte_order);
e10b1c4c 3112
3e8c568d 3113 trad_frame_set_value (cache->saved_regs,
8b164abb 3114 gdbarch_sp_regnum (gdbarch), cache->base);
61a65099
KB		 3115
3116 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
3117 All fpr's from saved_fpr to fp31 are saved. */
3118
3119 if (fdata.saved_fpr >= 0)
3120 {
3121 int i;
3122 CORE_ADDR fpr_addr = cache->base + fdata.fpr_offset;
383f0f5b
JB		 3123
3124 /* If skip_prologue says floating-point registers were saved,
3125 but the current architecture has no floating-point registers,
3126 then that's strange. But we have no indices to even record
3127 the addresses under, so we just ignore it. */
3128 if (ppc_floating_point_unit_p (gdbarch))
063715bf 3129 for (i = fdata.saved_fpr; i < ppc_num_fprs; i++)
383f0f5b
JB		 3130 {
3131 cache->saved_regs[tdep->ppc_fp0_regnum + i].addr = fpr_addr;
3132 fpr_addr += 8;
3133 }
61a65099
KB		 3134 }
3135
3136 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
46a9b8ed
DJ		 3137 All gpr's from saved_gpr to gpr31 are saved (except during the
3138 prologue). */
61a65099
KB		 3139
3140 if (fdata.saved_gpr >= 0)
3141 {
3142 int i;
3143 CORE_ADDR gpr_addr = cache->base + fdata.gpr_offset;
063715bf 3144 for (i = fdata.saved_gpr; i < ppc_num_gprs; i++)
61a65099 3145 {
46a9b8ed
DJ		 3146 if (fdata.gpr_mask & (1U << i))
3147 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = gpr_addr;
61a65099
KB		 3148 gpr_addr += wordsize;
3149 }
3150 }
3151
3152 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
3153 All vr's from saved_vr to vr31 are saved. */
3154 if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
3155 {
3156 if (fdata.saved_vr >= 0)
3157 {
3158 int i;
3159 CORE_ADDR vr_addr = cache->base + fdata.vr_offset;
3160 for (i = fdata.saved_vr; i < 32; i++)
3161 {
3162 cache->saved_regs[tdep->ppc_vr0_regnum + i].addr = vr_addr;
3163 vr_addr += register_size (gdbarch, tdep->ppc_vr0_regnum);
3164 }
3165 }
3166 }
3167
3168 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
3169 All vr's from saved_ev to ev31 are saved. ????? */
5a9e69ba 3170 if (tdep->ppc_ev0_regnum != -1)
61a65099
KB		 3171 {
3172 if (fdata.saved_ev >= 0)
3173 {
3174 int i;
3175 CORE_ADDR ev_addr = cache->base + fdata.ev_offset;
063715bf 3176 for (i = fdata.saved_ev; i < ppc_num_gprs; i++)
61a65099
KB		 3177 {
3178 cache->saved_regs[tdep->ppc_ev0_regnum + i].addr = ev_addr;
3179 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + 4;
3180 ev_addr += register_size (gdbarch, tdep->ppc_ev0_regnum);
3181 }
3182 }
3183 }
3184
3185 /* If != 0, fdata.cr_offset is the offset from the frame that
3186 holds the CR. */
3187 if (fdata.cr_offset != 0)
3188 cache->saved_regs[tdep->ppc_cr_regnum].addr = cache->base + fdata.cr_offset;
3189
3190 /* If != 0, fdata.lr_offset is the offset from the frame that
3191 holds the LR. */
3192 if (fdata.lr_offset != 0)
3193 cache->saved_regs[tdep->ppc_lr_regnum].addr = cache->base + fdata.lr_offset;
46a9b8ed
DJ		 3194 else if (fdata.lr_register != -1)
3195 cache->saved_regs[tdep->ppc_lr_regnum].realreg = fdata.lr_register;
61a65099 3196 /* The PC is found in the link register. */
8b164abb 3197 cache->saved_regs[gdbarch_pc_regnum (gdbarch)] =
3e8c568d 3198 cache->saved_regs[tdep->ppc_lr_regnum];
61a65099
KB		 3199
3200 /* If != 0, fdata.vrsave_offset is the offset from the frame that
3201 holds the VRSAVE. */
3202 if (fdata.vrsave_offset != 0)
3203 cache->saved_regs[tdep->ppc_vrsave_regnum].addr = cache->base + fdata.vrsave_offset;
3204
3205 if (fdata.alloca_reg < 0)
3206 /* If no alloca register used, then fi->frame is the value of the
3207 %sp for this frame, and it is good enough. */
1af5d7ce
UW		 3208 cache->initial_sp
3209 = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch));
61a65099 3210 else
1af5d7ce
UW		 3211 cache->initial_sp
3212 = get_frame_register_unsigned (this_frame, fdata.alloca_reg);
61a65099
KB		 3213
3214 return cache;
3215}
3216
3217static void
1af5d7ce 3218rs6000_frame_this_id (struct frame_info *this_frame, void **this_cache,
61a65099
KB		 3219 struct frame_id *this_id)
3220{
1af5d7ce 3221 struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame,
61a65099 3222 this_cache);
5b197912
UW		 3223 /* This marks the outermost frame. */
3224 if (info->base == 0)
3225 return;
3226
1af5d7ce 3227 (*this_id) = frame_id_build (info->base, get_frame_func (this_frame));
61a65099
KB		 3228}
3229
1af5d7ce
UW		 3230static struct value *
3231rs6000_frame_prev_register (struct frame_info *this_frame,
3232 void **this_cache, int regnum)
61a65099 3233{
1af5d7ce 3234 struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame,
61a65099 3235 this_cache);
1af5d7ce 3236 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
61a65099
KB		 3237}
3238
3239static const struct frame_unwind rs6000_frame_unwind =
3240{
3241 NORMAL_FRAME,
3242 rs6000_frame_this_id,
1af5d7ce
UW		 3243 rs6000_frame_prev_register,
3244 NULL,
3245 default_frame_sniffer
61a65099 3246};
61a65099
KB		 3247\f
3248
3249static CORE_ADDR
1af5d7ce 3250rs6000_frame_base_address (struct frame_info *this_frame, void **this_cache)
61a65099 3251{
1af5d7ce 3252 struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame,
61a65099
KB		 3253 this_cache);
3254 return info->initial_sp;
3255}
3256
3257static const struct frame_base rs6000_frame_base = {
3258 &rs6000_frame_unwind,
3259 rs6000_frame_base_address,
3260 rs6000_frame_base_address,
3261 rs6000_frame_base_address
3262};
3263
3264static const struct frame_base *
1af5d7ce 3265rs6000_frame_base_sniffer (struct frame_info *this_frame)
61a65099
KB		 3266{
3267 return &rs6000_frame_base;
3268}
3269
9274a07c
LM		 3270/* DWARF-2 frame support. Used to handle the detection of
3271 clobbered registers during function calls. */
3272
3273static void
3274ppc_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
3275 struct dwarf2_frame_state_reg *reg,
4a4e5149 3276 struct frame_info *this_frame)
9274a07c
LM		 3277{
3278 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3279
3280 /* PPC32 and PPC64 ABI's are the same regarding volatile and
3281 non-volatile registers. We will use the same code for both. */
3282
3283 /* Call-saved GP registers. */
3284 if ((regnum >= tdep->ppc_gp0_regnum + 14
3285 && regnum <= tdep->ppc_gp0_regnum + 31)
3286 || (regnum == tdep->ppc_gp0_regnum + 1))
3287 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
3288
3289 /* Call-clobbered GP registers. */
3290 if ((regnum >= tdep->ppc_gp0_regnum + 3
3291 && regnum <= tdep->ppc_gp0_regnum + 12)
3292 || (regnum == tdep->ppc_gp0_regnum))
3293 reg->how = DWARF2_FRAME_REG_UNDEFINED;
3294
3295 /* Deal with FP registers, if supported. */
3296 if (tdep->ppc_fp0_regnum >= 0)
3297 {
3298 /* Call-saved FP registers. */
3299 if ((regnum >= tdep->ppc_fp0_regnum + 14
3300 && regnum <= tdep->ppc_fp0_regnum + 31))
3301 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
3302
3303 /* Call-clobbered FP registers. */
3304 if ((regnum >= tdep->ppc_fp0_regnum
3305 && regnum <= tdep->ppc_fp0_regnum + 13))
3306 reg->how = DWARF2_FRAME_REG_UNDEFINED;
3307 }
3308
3309 /* Deal with ALTIVEC registers, if supported. */
3310 if (tdep->ppc_vr0_regnum > 0 && tdep->ppc_vrsave_regnum > 0)
3311 {
3312 /* Call-saved Altivec registers. */
3313 if ((regnum >= tdep->ppc_vr0_regnum + 20
3314 && regnum <= tdep->ppc_vr0_regnum + 31)
3315 || regnum == tdep->ppc_vrsave_regnum)
3316 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
3317
3318 /* Call-clobbered Altivec registers. */
3319 if ((regnum >= tdep->ppc_vr0_regnum
3320 && regnum <= tdep->ppc_vr0_regnum + 19))
3321 reg->how = DWARF2_FRAME_REG_UNDEFINED;
3322 }
3323
3324 /* Handle PC register and Stack Pointer correctly. */
40a6adc1 3325 if (regnum == gdbarch_pc_regnum (gdbarch))
9274a07c 3326 reg->how = DWARF2_FRAME_REG_RA;
40a6adc1 3327 else if (regnum == gdbarch_sp_regnum (gdbarch))
9274a07c
LM		 3328 reg->how = DWARF2_FRAME_REG_CFA;
3329}
3330
3331
7a78ae4e
ND		 3332/* Initialize the current architecture based on INFO. If possible, re-use an
3333 architecture from ARCHES, which is a list of architectures already created
3334 during this debugging session.
c906108c 3335
7a78ae4e 3336 Called e.g. at program startup, when reading a core file, and when reading
64366f1c 3337 a binary file. */
c906108c 3338
7a78ae4e
ND		 3339static struct gdbarch *
3340rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3341{
3342 struct gdbarch *gdbarch;
3343 struct gdbarch_tdep *tdep;
7cc46491 3344 int wordsize, from_xcoff_exec, from_elf_exec;
7a78ae4e
ND		 3345 enum bfd_architecture arch;
3346 unsigned long mach;
3347 bfd abfd;
5bf1c677 3348 asection *sect;
55eddb0f
DJ		 3349 enum auto_boolean soft_float_flag = powerpc_soft_float_global;
3350 int soft_float;
3351 enum powerpc_vector_abi vector_abi = powerpc_vector_abi_global;
604c2f83
LM		 3352 int have_fpu = 1, have_spe = 0, have_mq = 0, have_altivec = 0, have_dfp = 0,
3353 have_vsx = 0;
7cc46491
DJ		 3354 int tdesc_wordsize = -1;
3355 const struct target_desc *tdesc = info.target_desc;
3356 struct tdesc_arch_data *tdesc_data = NULL;
f949c649 3357 int num_pseudoregs = 0;
604c2f83 3358 int cur_reg;
7a78ae4e 3359
9aa1e687 3360 from_xcoff_exec = info.abfd && info.abfd->format == bfd_object &&
7a78ae4e
ND		 3361 bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour;
3362
9aa1e687
KB		 3363 from_elf_exec = info.abfd && info.abfd->format == bfd_object &&
3364 bfd_get_flavour (info.abfd) == bfd_target_elf_flavour;
3365
e712c1cf 3366 /* Check word size. If INFO is from a binary file, infer it from
64366f1c 3367 that, else choose a likely default. */
9aa1e687 3368 if (from_xcoff_exec)
c906108c 3369 {
11ed25ac 3370 if (bfd_xcoff_is_xcoff64 (info.abfd))
7a78ae4e
ND		 3371 wordsize = 8;
3372 else
3373 wordsize = 4;
c906108c 3374 }
9aa1e687
KB		 3375 else if (from_elf_exec)
3376 {
3377 if (elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
3378 wordsize = 8;
3379 else
3380 wordsize = 4;
3381 }
7cc46491
DJ		 3382 else if (tdesc_has_registers (tdesc))
3383 wordsize = -1;
c906108c 3384 else
7a78ae4e 3385 {
27b15785
KB		 3386 if (info.bfd_arch_info != NULL && info.bfd_arch_info->bits_per_word != 0)
3387 wordsize = info.bfd_arch_info->bits_per_word /
3388 info.bfd_arch_info->bits_per_byte;
3389 else
3390 wordsize = 4;
7a78ae4e 3391 }
c906108c 3392
475bbd17
JB		 3393 /* Get the architecture and machine from the BFD. */
3394 arch = info.bfd_arch_info->arch;
3395 mach = info.bfd_arch_info->mach;
5bf1c677
EZ		 3396
3397 /* For e500 executables, the apuinfo section is of help here. Such
3398 section contains the identifier and revision number of each
3399 Application-specific Processing Unit that is present on the
3400 chip. The content of the section is determined by the assembler
3401 which looks at each instruction and determines which unit (and
3402 which version of it) can execute it. In our case we just look for
3403 the existance of the section. */
3404
3405 if (info.abfd)
3406 {
3407 sect = bfd_get_section_by_name (info.abfd, ".PPC.EMB.apuinfo");
3408 if (sect)
3409 {
3410 arch = info.bfd_arch_info->arch;
3411 mach = bfd_mach_ppc_e500;
3412 bfd_default_set_arch_mach (&abfd, arch, mach);
3413 info.bfd_arch_info = bfd_get_arch_info (&abfd);
3414 }
3415 }
3416
7cc46491
DJ		 3417 /* Find a default target description which describes our register
3418 layout, if we do not already have one. */
3419 if (! tdesc_has_registers (tdesc))
3420 {
3421 const struct variant *v;
3422
3423 /* Choose variant. */
3424 v = find_variant_by_arch (arch, mach);
3425 if (!v)
3426 return NULL;
3427
3428 tdesc = *v->tdesc;
3429 }
3430
3431 gdb_assert (tdesc_has_registers (tdesc));
3432
3433 /* Check any target description for validity. */
3434 if (tdesc_has_registers (tdesc))
3435 {
3436 static const char *const gprs[] = {
3437 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
3438 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
3439 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
3440 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
3441 };
3442 static const char *const segment_regs[] = {
3443 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
3444 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
3445 };
3446 const struct tdesc_feature *feature;
3447 int i, valid_p;
3448 static const char *const msr_names[] = { "msr", "ps" };
3449 static const char *const cr_names[] = { "cr", "cnd" };
3450 static const char *const ctr_names[] = { "ctr", "cnt" };
3451
3452 feature = tdesc_find_feature (tdesc,
3453 "org.gnu.gdb.power.core");
3454 if (feature == NULL)
3455 return NULL;
3456
3457 tdesc_data = tdesc_data_alloc ();
3458
3459 valid_p = 1;
3460 for (i = 0; i < ppc_num_gprs; i++)
3461 valid_p &= tdesc_numbered_register (feature, tdesc_data, i, gprs[i]);
3462 valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_PC_REGNUM,
3463 "pc");
3464 valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_LR_REGNUM,
3465 "lr");
3466 valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_XER_REGNUM,
3467 "xer");
3468
3469 /* Allow alternate names for these registers, to accomodate GDB's
3470 historic naming. */
3471 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3472 PPC_MSR_REGNUM, msr_names);
3473 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3474 PPC_CR_REGNUM, cr_names);
3475 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3476 PPC_CTR_REGNUM, ctr_names);
3477
3478 if (!valid_p)
3479 {
3480 tdesc_data_cleanup (tdesc_data);
3481 return NULL;
3482 }
3483
3484 have_mq = tdesc_numbered_register (feature, tdesc_data, PPC_MQ_REGNUM,
3485 "mq");
3486
3487 tdesc_wordsize = tdesc_register_size (feature, "pc") / 8;
3488 if (wordsize == -1)
3489 wordsize = tdesc_wordsize;
3490
3491 feature = tdesc_find_feature (tdesc,
3492 "org.gnu.gdb.power.fpu");
3493 if (feature != NULL)
3494 {
3495 static const char *const fprs[] = {
3496 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
3497 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
3498 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
3499 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
3500 };
3501 valid_p = 1;
3502 for (i = 0; i < ppc_num_fprs; i++)
3503 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3504 PPC_F0_REGNUM + i, fprs[i]);
3505 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3506 PPC_FPSCR_REGNUM, "fpscr");
3507
3508 if (!valid_p)
3509 {
3510 tdesc_data_cleanup (tdesc_data);
3511 return NULL;
3512 }
3513 have_fpu = 1;
3514 }
3515 else
3516 have_fpu = 0;
3517
f949c649
TJB		 3518 /* The DFP pseudo-registers will be available when there are floating
3519 point registers. */
3520 have_dfp = have_fpu;
3521
7cc46491
DJ		 3522 feature = tdesc_find_feature (tdesc,
3523 "org.gnu.gdb.power.altivec");
3524 if (feature != NULL)
3525 {
3526 static const char *const vector_regs[] = {
3527 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
3528 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
3529 "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23",
3530 "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31"
3531 };
3532
3533 valid_p = 1;
3534 for (i = 0; i < ppc_num_gprs; i++)
3535 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3536 PPC_VR0_REGNUM + i,
3537 vector_regs[i]);
3538 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3539 PPC_VSCR_REGNUM, "vscr");
3540 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3541 PPC_VRSAVE_REGNUM, "vrsave");
3542
3543 if (have_spe || !valid_p)
3544 {
3545 tdesc_data_cleanup (tdesc_data);
3546 return NULL;
3547 }
3548 have_altivec = 1;
3549 }
3550 else
3551 have_altivec = 0;
3552
604c2f83
LM		 3553 /* Check for POWER7 VSX registers support. */
3554 feature = tdesc_find_feature (tdesc,
3555 "org.gnu.gdb.power.vsx");
3556
3557 if (feature != NULL)
3558 {
3559 static const char *const vsx_regs[] = {
3560 "vs0h", "vs1h", "vs2h", "vs3h", "vs4h", "vs5h",
3561 "vs6h", "vs7h", "vs8h", "vs9h", "vs10h", "vs11h",
3562 "vs12h", "vs13h", "vs14h", "vs15h", "vs16h", "vs17h",
3563 "vs18h", "vs19h", "vs20h", "vs21h", "vs22h", "vs23h",
3564 "vs24h", "vs25h", "vs26h", "vs27h", "vs28h", "vs29h",
3565 "vs30h", "vs31h"
3566 };
3567
3568 valid_p = 1;
3569
3570 for (i = 0; i < ppc_num_vshrs; i++)
3571 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3572 PPC_VSR0_UPPER_REGNUM + i,
3573 vsx_regs[i]);
3574 if (!valid_p)
3575 {
3576 tdesc_data_cleanup (tdesc_data);
3577 return NULL;
3578 }
3579
3580 have_vsx = 1;
3581 }
3582 else
3583 have_vsx = 0;
3584
7cc46491
DJ		 3585 /* On machines supporting the SPE APU, the general-purpose registers
3586 are 64 bits long. There are SIMD vector instructions to treat them
3587 as pairs of floats, but the rest of the instruction set treats them
3588 as 32-bit registers, and only operates on their lower halves.
3589
3590 In the GDB regcache, we treat their high and low halves as separate
3591 registers. The low halves we present as the general-purpose
3592 registers, and then we have pseudo-registers that stitch together
3593 the upper and lower halves and present them as pseudo-registers.
3594
3595 Thus, the target description is expected to supply the upper
3596 halves separately. */
3597
3598 feature = tdesc_find_feature (tdesc,
3599 "org.gnu.gdb.power.spe");
3600 if (feature != NULL)
3601 {
3602 static const char *const upper_spe[] = {
3603 "ev0h", "ev1h", "ev2h", "ev3h",
3604 "ev4h", "ev5h", "ev6h", "ev7h",
3605 "ev8h", "ev9h", "ev10h", "ev11h",
3606 "ev12h", "ev13h", "ev14h", "ev15h",
3607 "ev16h", "ev17h", "ev18h", "ev19h",
3608 "ev20h", "ev21h", "ev22h", "ev23h",
3609 "ev24h", "ev25h", "ev26h", "ev27h",
3610 "ev28h", "ev29h", "ev30h", "ev31h"
3611 };
3612
3613 valid_p = 1;
3614 for (i = 0; i < ppc_num_gprs; i++)
3615 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3616 PPC_SPE_UPPER_GP0_REGNUM + i,
3617 upper_spe[i]);
3618 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3619 PPC_SPE_ACC_REGNUM, "acc");
3620 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3621 PPC_SPE_FSCR_REGNUM, "spefscr");
3622
3623 if (have_mq || have_fpu || !valid_p)
3624 {
3625 tdesc_data_cleanup (tdesc_data);
3626 return NULL;
3627 }
3628 have_spe = 1;
3629 }
3630 else
3631 have_spe = 0;
3632 }
3633
3634 /* If we have a 64-bit binary on a 32-bit target, complain. Also
3635 complain for a 32-bit binary on a 64-bit target; we do not yet
3636 support that. For instance, the 32-bit ABI routines expect
3637 32-bit GPRs.
3638
3639 As long as there isn't an explicit target description, we'll
3640 choose one based on the BFD architecture and get a word size
3641 matching the binary (probably powerpc:common or
3642 powerpc:common64). So there is only trouble if a 64-bit target
3643 supplies a 64-bit description while debugging a 32-bit
3644 binary. */
3645 if (tdesc_wordsize != -1 && tdesc_wordsize != wordsize)
3646 {
3647 tdesc_data_cleanup (tdesc_data);
3648 return NULL;
3649 }
3650
55eddb0f
DJ		 3651#ifdef HAVE_ELF
3652 if (soft_float_flag == AUTO_BOOLEAN_AUTO && from_elf_exec)
3653 {
3654 switch (bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU,
3655 Tag_GNU_Power_ABI_FP))
3656 {
3657 case 1:
3658 soft_float_flag = AUTO_BOOLEAN_FALSE;
3659 break;
3660 case 2:
3661 soft_float_flag = AUTO_BOOLEAN_TRUE;
3662 break;
3663 default:
3664 break;
3665 }
3666 }
3667
3668 if (vector_abi == POWERPC_VEC_AUTO && from_elf_exec)
3669 {
3670 switch (bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU,
3671 Tag_GNU_Power_ABI_Vector))
3672 {
3673 case 1:
3674 vector_abi = POWERPC_VEC_GENERIC;
3675 break;
3676 case 2:
3677 vector_abi = POWERPC_VEC_ALTIVEC;
3678 break;
3679 case 3:
3680 vector_abi = POWERPC_VEC_SPE;
3681 break;
3682 default:
3683 break;
3684 }
3685 }
3686#endif
3687
3688 if (soft_float_flag == AUTO_BOOLEAN_TRUE)
3689 soft_float = 1;
3690 else if (soft_float_flag == AUTO_BOOLEAN_FALSE)
3691 soft_float = 0;
3692 else
3693 soft_float = !have_fpu;
3694
3695 /* If we have a hard float binary or setting but no floating point
3696 registers, downgrade to soft float anyway. We're still somewhat
3697 useful in this scenario. */
3698 if (!soft_float && !have_fpu)
3699 soft_float = 1;
3700
3701 /* Similarly for vector registers. */
3702 if (vector_abi == POWERPC_VEC_ALTIVEC && !have_altivec)
3703 vector_abi = POWERPC_VEC_GENERIC;
3704
3705 if (vector_abi == POWERPC_VEC_SPE && !have_spe)
3706 vector_abi = POWERPC_VEC_GENERIC;
3707
3708 if (vector_abi == POWERPC_VEC_AUTO)
3709 {
3710 if (have_altivec)
3711 vector_abi = POWERPC_VEC_ALTIVEC;
3712 else if (have_spe)
3713 vector_abi = POWERPC_VEC_SPE;
3714 else
3715 vector_abi = POWERPC_VEC_GENERIC;
3716 }
3717
3718 /* Do not limit the vector ABI based on available hardware, since we
3719 do not yet know what hardware we'll decide we have. Yuck! FIXME! */
3720
7cc46491
DJ		 3721 /* Find a candidate among extant architectures. */
3722 for (arches = gdbarch_list_lookup_by_info (arches, &info);
3723 arches != NULL;
3724 arches = gdbarch_list_lookup_by_info (arches->next, &info))
3725 {
3726 /* Word size in the various PowerPC bfd_arch_info structs isn't
3727 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
3728 separate word size check. */
3729 tdep = gdbarch_tdep (arches->gdbarch);
55eddb0f
DJ		 3730 if (tdep && tdep->soft_float != soft_float)
3731 continue;
3732 if (tdep && tdep->vector_abi != vector_abi)
3733 continue;
7cc46491
DJ		 3734 if (tdep && tdep->wordsize == wordsize)
3735 {
3736 if (tdesc_data != NULL)
3737 tdesc_data_cleanup (tdesc_data);
3738 return arches->gdbarch;
3739 }
3740 }
3741
3742 /* None found, create a new architecture from INFO, whose bfd_arch_info
3743 validity depends on the source:
3744 - executable useless
3745 - rs6000_host_arch() good
3746 - core file good
3747 - "set arch" trust blindly
3748 - GDB startup useless but harmless */
3749
3750 tdep = XCALLOC (1, struct gdbarch_tdep);
3751 tdep->wordsize = wordsize;
55eddb0f
DJ		 3752 tdep->soft_float = soft_float;
3753 tdep->vector_abi = vector_abi;
7cc46491 3754
7a78ae4e 3755 gdbarch = gdbarch_alloc (&info, tdep);
7a78ae4e 3756
7cc46491
DJ		 3757 tdep->ppc_gp0_regnum = PPC_R0_REGNUM;
3758 tdep->ppc_toc_regnum = PPC_R0_REGNUM + 2;
3759 tdep->ppc_ps_regnum = PPC_MSR_REGNUM;
3760 tdep->ppc_cr_regnum = PPC_CR_REGNUM;
3761 tdep->ppc_lr_regnum = PPC_LR_REGNUM;
3762 tdep->ppc_ctr_regnum = PPC_CTR_REGNUM;
3763 tdep->ppc_xer_regnum = PPC_XER_REGNUM;
3764 tdep->ppc_mq_regnum = have_mq ? PPC_MQ_REGNUM : -1;
3765
3766 tdep->ppc_fp0_regnum = have_fpu ? PPC_F0_REGNUM : -1;
3767 tdep->ppc_fpscr_regnum = have_fpu ? PPC_FPSCR_REGNUM : -1;
604c2f83 3768 tdep->ppc_vsr0_upper_regnum = have_vsx ? PPC_VSR0_UPPER_REGNUM : -1;
7cc46491
DJ		 3769 tdep->ppc_vr0_regnum = have_altivec ? PPC_VR0_REGNUM : -1;
3770 tdep->ppc_vrsave_regnum = have_altivec ? PPC_VRSAVE_REGNUM : -1;
3771 tdep->ppc_ev0_upper_regnum = have_spe ? PPC_SPE_UPPER_GP0_REGNUM : -1;
3772 tdep->ppc_acc_regnum = have_spe ? PPC_SPE_ACC_REGNUM : -1;
3773 tdep->ppc_spefscr_regnum = have_spe ? PPC_SPE_FSCR_REGNUM : -1;
3774
3775 set_gdbarch_pc_regnum (gdbarch, PPC_PC_REGNUM);
3776 set_gdbarch_sp_regnum (gdbarch, PPC_R0_REGNUM + 1);
3777 set_gdbarch_deprecated_fp_regnum (gdbarch, PPC_R0_REGNUM + 1);
3778 set_gdbarch_fp0_regnum (gdbarch, tdep->ppc_fp0_regnum);
9f643768 3779 set_gdbarch_register_sim_regno (gdbarch, rs6000_register_sim_regno);
7cc46491
DJ		 3780
3781 /* The XML specification for PowerPC sensibly calls the MSR "msr".
3782 GDB traditionally called it "ps", though, so let GDB add an
3783 alias. */
3784 set_gdbarch_ps_regnum (gdbarch, tdep->ppc_ps_regnum);
3785
4a7622d1 3786 if (wordsize == 8)
05580c65 3787 set_gdbarch_return_value (gdbarch, ppc64_sysv_abi_return_value);
afd48b75 3788 else
4a7622d1 3789 set_gdbarch_return_value (gdbarch, ppc_sysv_abi_return_value);
c8001721 3790
baffbae0
JB		 3791 /* Set lr_frame_offset. */
3792 if (wordsize == 8)
3793 tdep->lr_frame_offset = 16;
baffbae0 3794 else
4a7622d1 3795 tdep->lr_frame_offset = 4;
baffbae0 3796
604c2f83 3797 if (have_spe || have_dfp || have_vsx)
7cc46491 3798 {
f949c649
TJB		 3799 set_gdbarch_pseudo_register_read (gdbarch, rs6000_pseudo_register_read);
3800 set_gdbarch_pseudo_register_write (gdbarch, rs6000_pseudo_register_write);
7cc46491 3801 }
1fcc0bb8 3802
e0d24f8d
WZ		 3803 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
3804
56a6dfb9 3805 /* Select instruction printer. */
708ff411 3806 if (arch == bfd_arch_rs6000)
9364a0ef 3807 set_gdbarch_print_insn (gdbarch, print_insn_rs6000);
56a6dfb9 3808 else
9364a0ef 3809 set_gdbarch_print_insn (gdbarch, gdb_print_insn_powerpc);
7495d1dc 3810
5a9e69ba 3811 set_gdbarch_num_regs (gdbarch, PPC_NUM_REGS);
f949c649
TJB		 3812
3813 if (have_spe)
3814 num_pseudoregs += 32;
3815 if (have_dfp)
3816 num_pseudoregs += 16;
604c2f83
LM		 3817 if (have_vsx)
3818 /* Include both VSX and Extended FP registers. */
3819 num_pseudoregs += 96;
f949c649
TJB		 3820
3821 set_gdbarch_num_pseudo_regs (gdbarch, num_pseudoregs);
7a78ae4e
ND		 3822
3823 set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
3824 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
3825 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
3826 set_gdbarch_long_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
3827 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
3828 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
3829 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
4a7622d1 3830 set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT);
4e409299 3831 set_gdbarch_char_signed (gdbarch, 0);
7a78ae4e 3832
11269d7e 3833 set_gdbarch_frame_align (gdbarch, rs6000_frame_align);
4a7622d1 3834 if (wordsize == 8)
8b148df9
AC		 3835 /* PPC64 SYSV. */
3836 set_gdbarch_frame_red_zone_size (gdbarch, 288);
7a78ae4e 3837
691d145a
JB		 3838 set_gdbarch_convert_register_p (gdbarch, rs6000_convert_register_p);
3839 set_gdbarch_register_to_value (gdbarch, rs6000_register_to_value);
3840 set_gdbarch_value_to_register (gdbarch, rs6000_value_to_register);
3841
18ed0c4e
JB		 3842 set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_stab_reg_to_regnum);
3843 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rs6000_dwarf2_reg_to_regnum);
d217aaed 3844
4a7622d1 3845 if (wordsize == 4)
77b2b6d4 3846 set_gdbarch_push_dummy_call (gdbarch, ppc_sysv_abi_push_dummy_call);
4a7622d1 3847 else if (wordsize == 8)
8be9034a 3848 set_gdbarch_push_dummy_call (gdbarch, ppc64_sysv_abi_push_dummy_call);
7a78ae4e 3849
7a78ae4e 3850 set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue);
0d1243d9 3851 set_gdbarch_in_function_epilogue_p (gdbarch, rs6000_in_function_epilogue_p);
8ab3d180 3852 set_gdbarch_skip_main_prologue (gdbarch, rs6000_skip_main_prologue);
0d1243d9 3853
7a78ae4e 3854 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
7a78ae4e
ND		 3855 set_gdbarch_breakpoint_from_pc (gdbarch, rs6000_breakpoint_from_pc);
3856
203c3895
UW		 3857 /* The value of symbols of type N_SO and N_FUN maybe null when
3858 it shouldn't be. */
3859 set_gdbarch_sofun_address_maybe_missing (gdbarch, 1);
3860
ce5eab59 3861 /* Handles single stepping of atomic sequences. */
4a7622d1 3862 set_gdbarch_software_single_step (gdbarch, ppc_deal_with_atomic_sequence);
ce5eab59 3863
7a78ae4e
ND		 3864 /* Not sure on this. FIXMEmgo */
3865 set_gdbarch_frame_args_skip (gdbarch, 8);
3866
143985b7
AF		 3867 /* Helpers for function argument information. */
3868 set_gdbarch_fetch_pointer_argument (gdbarch, rs6000_fetch_pointer_argument);
3869
6f7f3f0d
UW		 3870 /* Trampoline. */
3871 set_gdbarch_in_solib_return_trampoline
3872 (gdbarch, rs6000_in_solib_return_trampoline);
3873 set_gdbarch_skip_trampoline_code (gdbarch, rs6000_skip_trampoline_code);
3874
4fc771b8 3875 /* Hook in the DWARF CFI frame unwinder. */
1af5d7ce 3876 dwarf2_append_unwinders (gdbarch);
4fc771b8
DJ		 3877 dwarf2_frame_set_adjust_regnum (gdbarch, rs6000_adjust_frame_regnum);
3878
9274a07c
LM		 3879 /* Frame handling. */
3880 dwarf2_frame_set_init_reg (gdbarch, ppc_dwarf2_frame_init_reg);
3881
2454a024
UW		 3882 /* Setup displaced stepping. */
3883 set_gdbarch_displaced_step_copy_insn (gdbarch,
3884 simple_displaced_step_copy_insn);
3885 set_gdbarch_displaced_step_fixup (gdbarch, ppc_displaced_step_fixup);
3886 set_gdbarch_displaced_step_free_closure (gdbarch,
3887 simple_displaced_step_free_closure);
3888 set_gdbarch_displaced_step_location (gdbarch,
3889 displaced_step_at_entry_point);
3890
3891 set_gdbarch_max_insn_length (gdbarch, PPC_INSN_SIZE);
3892
7b112f9c 3893 /* Hook in ABI-specific overrides, if they have been registered. */
8a4c2d24
UW		 3894 info.target_desc = tdesc;
3895 info.tdep_info = (void *) tdesc_data;
4be87837 3896 gdbarch_init_osabi (info, gdbarch);
7b112f9c 3897
61a65099
KB		 3898 switch (info.osabi)
3899 {
f5aecab8 3900 case GDB_OSABI_LINUX:
61a65099
KB		 3901 case GDB_OSABI_NETBSD_AOUT:
3902 case GDB_OSABI_NETBSD_ELF:
3903 case GDB_OSABI_UNKNOWN:
61a65099 3904 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
1af5d7ce
UW		 3905 frame_unwind_append_unwinder (gdbarch, &rs6000_frame_unwind);
3906 set_gdbarch_dummy_id (gdbarch, rs6000_dummy_id);
61a65099
KB		 3907 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
3908 break;
3909 default:
61a65099 3910 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
81332287
KB		 3911
3912 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
1af5d7ce
UW		 3913 frame_unwind_append_unwinder (gdbarch, &rs6000_frame_unwind);
3914 set_gdbarch_dummy_id (gdbarch, rs6000_dummy_id);
81332287 3915 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
61a65099
KB		 3916 }
3917
7cc46491
DJ		 3918 set_tdesc_pseudo_register_type (gdbarch, rs6000_pseudo_register_type);
3919 set_tdesc_pseudo_register_reggroup_p (gdbarch,
3920 rs6000_pseudo_register_reggroup_p);
3921 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
3922
3923 /* Override the normal target description method to make the SPE upper
3924 halves anonymous. */
3925 set_gdbarch_register_name (gdbarch, rs6000_register_name);
3926
604c2f83
LM		 3927 /* Choose register numbers for all supported pseudo-registers. */
3928 tdep->ppc_ev0_regnum = -1;
3929 tdep->ppc_dl0_regnum = -1;
3930 tdep->ppc_vsr0_regnum = -1;
3931 tdep->ppc_efpr0_regnum = -1;
9f643768 3932
604c2f83
LM		 3933 cur_reg = gdbarch_num_regs (gdbarch);
3934
3935 if (have_spe)
3936 {
3937 tdep->ppc_ev0_regnum = cur_reg;
3938 cur_reg += 32;
3939 }
3940 if (have_dfp)
3941 {
3942 tdep->ppc_dl0_regnum = cur_reg;
3943 cur_reg += 16;
3944 }
3945 if (have_vsx)
3946 {
3947 tdep->ppc_vsr0_regnum = cur_reg;
3948 cur_reg += 64;
3949 tdep->ppc_efpr0_regnum = cur_reg;
3950 cur_reg += 32;
3951 }
f949c649 3952
604c2f83
LM		 3953 gdb_assert (gdbarch_num_regs (gdbarch)
3954 + gdbarch_num_pseudo_regs (gdbarch) == cur_reg);
f949c649 3955
7a78ae4e 3956 return gdbarch;
c906108c
SS		 3957}
3958
7b112f9c 3959static void
8b164abb 3960rs6000_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
7b112f9c 3961{
8b164abb 3962 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
7b112f9c
JT		 3963
3964 if (tdep == NULL)
3965 return;
3966
4be87837 3967 /* FIXME: Dump gdbarch_tdep. */
7b112f9c
JT		 3968}
3969
55eddb0f
DJ		 3970/* PowerPC-specific commands. */
3971
3972static void
3973set_powerpc_command (char *args, int from_tty)
3974{
3975 printf_unfiltered (_("\
3976\"set powerpc\" must be followed by an appropriate subcommand.\n"));
3977 help_list (setpowerpccmdlist, "set powerpc ", all_commands, gdb_stdout);
3978}
3979
3980static void
3981show_powerpc_command (char *args, int from_tty)
3982{
3983 cmd_show_list (showpowerpccmdlist, from_tty, "");
3984}
3985
3986static void
3987powerpc_set_soft_float (char *args, int from_tty,
3988 struct cmd_list_element *c)
3989{
3990 struct gdbarch_info info;
3991
3992 /* Update the architecture. */
3993 gdbarch_info_init (&info);
3994 if (!gdbarch_update_p (info))
3995 internal_error (__FILE__, __LINE__, "could not update architecture");
3996}
3997
3998static void
3999powerpc_set_vector_abi (char *args, int from_tty,
4000 struct cmd_list_element *c)
4001{
4002 struct gdbarch_info info;
4003 enum powerpc_vector_abi vector_abi;
4004
4005 for (vector_abi = POWERPC_VEC_AUTO;
4006 vector_abi != POWERPC_VEC_LAST;
4007 vector_abi++)
4008 if (strcmp (powerpc_vector_abi_string,
4009 powerpc_vector_strings[vector_abi]) == 0)
4010 {
4011 powerpc_vector_abi_global = vector_abi;
4012 break;
4013 }
4014
4015 if (vector_abi == POWERPC_VEC_LAST)
4016 internal_error (__FILE__, __LINE__, _("Invalid vector ABI accepted: %s."),
4017 powerpc_vector_abi_string);
4018
4019 /* Update the architecture. */
4020 gdbarch_info_init (&info);
4021 if (!gdbarch_update_p (info))
4022 internal_error (__FILE__, __LINE__, "could not update architecture");
4023}
4024
c906108c
SS		 4025/* Initialization code. */
4026
a78f21af 4027extern initialize_file_ftype _initialize_rs6000_tdep; /* -Wmissing-prototypes */
b9362cc7 4028
c906108c 4029void
fba45db2 4030_initialize_rs6000_tdep (void)
c906108c 4031{
7b112f9c
JT		 4032 gdbarch_register (bfd_arch_rs6000, rs6000_gdbarch_init, rs6000_dump_tdep);
4033 gdbarch_register (bfd_arch_powerpc, rs6000_gdbarch_init, rs6000_dump_tdep);
7cc46491
DJ		 4034
4035 /* Initialize the standard target descriptions. */
4036 initialize_tdesc_powerpc_32 ();
7284e1be 4037 initialize_tdesc_powerpc_altivec32 ();
604c2f83 4038 initialize_tdesc_powerpc_vsx32 ();
7cc46491
DJ		 4039 initialize_tdesc_powerpc_403 ();
4040 initialize_tdesc_powerpc_403gc ();
4041 initialize_tdesc_powerpc_505 ();
4042 initialize_tdesc_powerpc_601 ();
4043 initialize_tdesc_powerpc_602 ();
4044 initialize_tdesc_powerpc_603 ();
4045 initialize_tdesc_powerpc_604 ();
4046 initialize_tdesc_powerpc_64 ();
7284e1be 4047 initialize_tdesc_powerpc_altivec64 ();
604c2f83 4048 initialize_tdesc_powerpc_vsx64 ();
7cc46491
DJ		 4049 initialize_tdesc_powerpc_7400 ();
4050 initialize_tdesc_powerpc_750 ();
4051 initialize_tdesc_powerpc_860 ();
4052 initialize_tdesc_powerpc_e500 ();
4053 initialize_tdesc_rs6000 ();
55eddb0f
DJ		 4054
4055 /* Add root prefix command for all "set powerpc"/"show powerpc"
4056 commands. */
4057 add_prefix_cmd ("powerpc", no_class, set_powerpc_command,
4058 _("Various PowerPC-specific commands."),
4059 &setpowerpccmdlist, "set powerpc ", 0, &setlist);
4060
4061 add_prefix_cmd ("powerpc", no_class, show_powerpc_command,
4062 _("Various PowerPC-specific commands."),
4063 &showpowerpccmdlist, "show powerpc ", 0, &showlist);
4064
4065 /* Add a command to allow the user to force the ABI. */
4066 add_setshow_auto_boolean_cmd ("soft-float", class_support,
4067 &powerpc_soft_float_global,
4068 _("Set whether to use a soft-float ABI."),
4069 _("Show whether to use a soft-float ABI."),
4070 NULL,
4071 powerpc_set_soft_float, NULL,
4072 &setpowerpccmdlist, &showpowerpccmdlist);
4073
4074 add_setshow_enum_cmd ("vector-abi", class_support, powerpc_vector_strings,
4075 &powerpc_vector_abi_string,
4076 _("Set the vector ABI."),
4077 _("Show the vector ABI."),
4078 NULL, powerpc_set_vector_abi, NULL,
4079 &setpowerpccmdlist, &showpowerpccmdlist);
c906108c 4080}
GDB Binutils - Deliverables
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