Commit | Line | Data |
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41abdfbd JG |
1 | /* IBM RS/6000 host-dependent code for GDB, the GNU debugger. |
2 | Copyright (C) 1986, 1987, 1989, 1991 Free Software Foundation, Inc. | |
3 | ||
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2 of the License, or | |
9 | (at your option) any later version. | |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program; if not, write to the Free Software | |
18 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ | |
19 | ||
41abdfbd | 20 | #include "defs.h" |
41abdfbd JG |
21 | #include "frame.h" |
22 | #include "inferior.h" | |
23 | #include "symtab.h" | |
24 | #include "target.h" | |
25 | ||
26 | #include <sys/param.h> | |
27 | #include <sys/dir.h> | |
28 | #include <sys/user.h> | |
29 | #include <signal.h> | |
30 | #include <sys/ioctl.h> | |
31 | #include <fcntl.h> | |
32 | ||
33 | #include <sys/ptrace.h> | |
34 | #include <sys/reg.h> | |
35 | ||
36 | #include <a.out.h> | |
37 | #include <sys/file.h> | |
38 | #include <sys/stat.h> | |
39 | #include <sys/core.h> | |
40 | #include <sys/ldr.h> | |
818de002 | 41 | #include <sys/utsname.h> |
41abdfbd JG |
42 | |
43 | extern int errno; | |
44 | extern int attach_flag; | |
45 | ||
46 | /* Conversion from gdb-to-system special purpose register numbers.. */ | |
47 | ||
48 | static int special_regs[] = { | |
49 | IAR, /* PC_REGNUM */ | |
50 | MSR, /* PS_REGNUM */ | |
51 | CR, /* CR_REGNUM */ | |
52 | LR, /* LR_REGNUM */ | |
53 | CTR, /* CTR_REGNUM */ | |
54 | XER, /* XER_REGNUM */ | |
55 | MQ /* MQ_REGNUM */ | |
56 | }; | |
57 | ||
58 | ||
59 | /* Nonzero if we just simulated a single step break. */ | |
60 | extern int one_stepped; | |
61 | ||
4ef09e36 | 62 | extern struct obstack frame_cache_obstack; |
2b5a8d9c | 63 | |
41abdfbd | 64 | \f |
818de002 | 65 | void |
1ab3bf1b | 66 | fetch_inferior_registers (regno) |
2b5a8d9c | 67 | int regno; |
41abdfbd JG |
68 | { |
69 | int ii; | |
70 | extern char registers[]; | |
71 | ||
2b5a8d9c | 72 | if (regno < 0) { /* for all registers */ |
41abdfbd | 73 | |
2b5a8d9c PB |
74 | /* read 32 general purpose registers. */ |
75 | ||
76 | for (ii=0; ii < 32; ++ii) | |
77 | *(int*)®isters[REGISTER_BYTE (ii)] = | |
e676a15f | 78 | ptrace (PT_READ_GPR, inferior_pid, (PTRACE_ARG3_TYPE) ii, 0, 0); |
41abdfbd | 79 | |
2b5a8d9c | 80 | /* read general purpose floating point registers. */ |
41abdfbd | 81 | |
2b5a8d9c PB |
82 | for (ii=0; ii < 32; ++ii) |
83 | ptrace (PT_READ_FPR, inferior_pid, | |
e676a15f FF |
84 | (PTRACE_ARG3_TYPE) ®isters [REGISTER_BYTE (FP0_REGNUM+ii)], |
85 | FPR0+ii, 0); | |
41abdfbd | 86 | |
2b5a8d9c PB |
87 | /* read special registers. */ |
88 | for (ii=0; ii <= LAST_SP_REGNUM-FIRST_SP_REGNUM; ++ii) | |
89 | *(int*)®isters[REGISTER_BYTE (FIRST_SP_REGNUM+ii)] = | |
e676a15f FF |
90 | ptrace (PT_READ_GPR, inferior_pid, (PTRACE_ARG3_TYPE) special_regs[ii], |
91 | 0, 0); | |
2b5a8d9c PB |
92 | |
93 | registers_fetched (); | |
94 | return; | |
95 | } | |
96 | ||
97 | /* else an individual register is addressed. */ | |
98 | ||
99 | else if (regno < FP0_REGNUM) { /* a GPR */ | |
100 | *(int*)®isters[REGISTER_BYTE (regno)] = | |
e676a15f | 101 | ptrace (PT_READ_GPR, inferior_pid, (PTRACE_ARG3_TYPE) regno, 0, 0); |
2b5a8d9c PB |
102 | } |
103 | else if (regno <= FPLAST_REGNUM) { /* a FPR */ | |
104 | ptrace (PT_READ_FPR, inferior_pid, | |
e676a15f FF |
105 | (PTRACE_ARG3_TYPE) ®isters [REGISTER_BYTE (regno)], |
106 | (regno-FP0_REGNUM+FPR0), 0); | |
2b5a8d9c PB |
107 | } |
108 | else if (regno <= LAST_SP_REGNUM) { /* a special register */ | |
109 | *(int*)®isters[REGISTER_BYTE (regno)] = | |
110 | ptrace (PT_READ_GPR, inferior_pid, | |
e676a15f | 111 | (PTRACE_ARG3_TYPE) special_regs[regno-FIRST_SP_REGNUM], 0, 0); |
2b5a8d9c PB |
112 | } |
113 | else | |
114 | fprintf (stderr, "gdb error: register no %d not implemented.\n", regno); | |
115 | ||
116 | register_valid [regno] = 1; | |
41abdfbd JG |
117 | } |
118 | ||
119 | /* Store our register values back into the inferior. | |
120 | If REGNO is -1, do this for all registers. | |
121 | Otherwise, REGNO specifies which register (so we can save time). */ | |
122 | ||
1ab3bf1b | 123 | void |
41abdfbd JG |
124 | store_inferior_registers (regno) |
125 | int regno; | |
126 | { | |
127 | extern char registers[]; | |
128 | ||
129 | errno = 0; | |
130 | ||
131 | if (regno == -1) { /* for all registers.. */ | |
132 | int ii; | |
133 | ||
134 | /* execute one dummy instruction (which is a breakpoint) in inferior | |
135 | process. So give kernel a chance to do internal house keeping. | |
136 | Otherwise the following ptrace(2) calls will mess up user stack | |
137 | since kernel will get confused about the bottom of the stack (%sp) */ | |
138 | ||
139 | exec_one_dummy_insn (); | |
140 | ||
141 | /* write general purpose registers first! */ | |
142 | for ( ii=GPR0; ii<=GPR31; ++ii) { | |
e676a15f | 143 | ptrace (PT_WRITE_GPR, inferior_pid, (PTRACE_ARG3_TYPE) ii, |
41abdfbd JG |
144 | *(int*)®isters[REGISTER_BYTE (ii)], 0); |
145 | if ( errno ) { | |
146 | perror ("ptrace write_gpr"); errno = 0; | |
147 | } | |
148 | } | |
149 | ||
150 | /* write floating point registers now. */ | |
151 | for ( ii=0; ii < 32; ++ii) { | |
152 | ptrace (PT_WRITE_FPR, inferior_pid, | |
e676a15f FF |
153 | (PTRACE_ARG3_TYPE) ®isters[REGISTER_BYTE (FP0_REGNUM+ii)], |
154 | FPR0+ii, 0); | |
41abdfbd JG |
155 | if ( errno ) { |
156 | perror ("ptrace write_fpr"); errno = 0; | |
157 | } | |
158 | } | |
159 | ||
160 | /* write special registers. */ | |
161 | for (ii=0; ii <= LAST_SP_REGNUM-FIRST_SP_REGNUM; ++ii) { | |
e676a15f FF |
162 | ptrace (PT_WRITE_GPR, inferior_pid, |
163 | (PTRACE_ARG3_TYPE) special_regs[ii], | |
164 | *(int*)®isters[REGISTER_BYTE (FIRST_SP_REGNUM+ii)], 0); | |
41abdfbd JG |
165 | if ( errno ) { |
166 | perror ("ptrace write_gpr"); errno = 0; | |
167 | } | |
168 | } | |
169 | } | |
170 | ||
171 | /* else, a specific register number is given... */ | |
172 | ||
173 | else if (regno < FP0_REGNUM) { /* a GPR */ | |
174 | ||
e676a15f | 175 | ptrace (PT_WRITE_GPR, inferior_pid, (PTRACE_ARG3_TYPE) regno, |
41abdfbd JG |
176 | *(int*)®isters[REGISTER_BYTE (regno)], 0); |
177 | } | |
178 | ||
179 | else if (regno <= FPLAST_REGNUM) { /* a FPR */ | |
180 | ptrace (PT_WRITE_FPR, inferior_pid, | |
e676a15f FF |
181 | (PTRACE_ARG3_TYPE) ®isters[REGISTER_BYTE (regno)], |
182 | regno-FP0_REGNUM+FPR0, 0); | |
41abdfbd JG |
183 | } |
184 | ||
185 | else if (regno <= LAST_SP_REGNUM) { /* a special register */ | |
186 | ||
e676a15f FF |
187 | ptrace (PT_WRITE_GPR, inferior_pid, |
188 | (PTRACE_ARG3_TYPE) special_regs [regno-FIRST_SP_REGNUM], | |
189 | *(int*)®isters[REGISTER_BYTE (regno)], 0); | |
41abdfbd JG |
190 | } |
191 | ||
192 | else | |
193 | fprintf (stderr, "Gdb error: register no %d not implemented.\n", regno); | |
194 | ||
195 | if ( errno ) { | |
196 | perror ("ptrace write"); errno = 0; | |
41abdfbd | 197 | } |
41abdfbd JG |
198 | } |
199 | ||
200 | void | |
1ab3bf1b | 201 | fetch_core_registers (core_reg_sect, core_reg_size, which, reg_addr) |
41abdfbd JG |
202 | char *core_reg_sect; |
203 | unsigned core_reg_size; | |
204 | int which; | |
1ab3bf1b | 205 | unsigned int reg_addr; /* Unused in this version */ |
41abdfbd JG |
206 | { |
207 | /* fetch GPRs and special registers from the first register section | |
208 | in core bfd. */ | |
209 | if (which == 0) { | |
210 | ||
211 | /* copy GPRs first. */ | |
212 | bcopy (core_reg_sect, registers, 32 * 4); | |
213 | ||
214 | /* gdb's internal register template and bfd's register section layout | |
215 | should share a common include file. FIXMEmgo */ | |
216 | /* then comes special registes. They are supposed to be in the same | |
217 | order in gdb template and bfd `.reg' section. */ | |
218 | core_reg_sect += (32 * 4); | |
219 | bcopy (core_reg_sect, ®isters [REGISTER_BYTE (FIRST_SP_REGNUM)], | |
220 | (LAST_SP_REGNUM - FIRST_SP_REGNUM + 1) * 4); | |
221 | } | |
222 | ||
223 | /* fetch floating point registers from register section 2 in core bfd. */ | |
224 | else if (which == 2) | |
225 | bcopy (core_reg_sect, ®isters [REGISTER_BYTE (FP0_REGNUM)], 32 * 8); | |
226 | ||
227 | else | |
228 | fprintf (stderr, "Gdb error: unknown parameter to fetch_core_registers().\n"); | |
229 | } | |
230 | ||
231 | ||
232 | frameless_function_invocation (fi) | |
233 | struct frame_info *fi; | |
234 | { | |
818de002 | 235 | CORE_ADDR func_start; |
6c6afbb9 | 236 | struct aix_framedata fdata; |
41abdfbd | 237 | |
41abdfbd | 238 | func_start = get_pc_function_start (fi->pc) + FUNCTION_START_OFFSET; |
41abdfbd | 239 | |
818de002 PB |
240 | /* If we failed to find the start of the function, it is a mistake |
241 | to inspect the instructions. */ | |
242 | ||
243 | if (!func_start) | |
244 | return 0; | |
245 | ||
6c6afbb9 PB |
246 | function_frame_info (func_start, &fdata); |
247 | return fdata.frameless; | |
41abdfbd JG |
248 | } |
249 | ||
250 | ||
4ef09e36 PB |
251 | /* If saved registers of frame FI are not known yet, read and cache them. |
252 | &FDATAP contains aix_framedata; TDATAP can be NULL, | |
253 | in which case the framedata are read. | |
254 | */ | |
255 | ||
256 | static void | |
257 | frame_get_cache_fsr (fi, fdatap) | |
258 | struct frame_info *fi; | |
259 | struct aix_framedata *fdatap; | |
260 | { | |
261 | int ii; | |
262 | CORE_ADDR frame_addr; | |
263 | struct aix_framedata work_fdata; | |
264 | if (fi->cache_fsr) | |
265 | return; | |
266 | ||
095db7ce | 267 | if (fdatap == NULL) { |
4ef09e36 PB |
268 | fdatap = &work_fdata; |
269 | function_frame_info (get_pc_function_start (fi->pc), fdatap); | |
270 | } | |
271 | ||
272 | fi->cache_fsr = (struct frame_saved_regs *) | |
273 | obstack_alloc (&frame_cache_obstack, sizeof (struct frame_saved_regs)); | |
274 | bzero (fi->cache_fsr, sizeof (struct frame_saved_regs)); | |
275 | ||
276 | if (fi->prev && fi->prev->frame) | |
277 | frame_addr = fi->prev->frame; | |
278 | else | |
279 | frame_addr = read_memory_integer (fi->frame, 4); | |
280 | ||
281 | /* if != -1, fdatap->saved_fpr is the smallest number of saved_fpr. | |
282 | All fpr's from saved_fpr to fp31 are saved right underneath caller | |
283 | stack pointer, starting from fp31 first. */ | |
284 | ||
285 | if (fdatap->saved_fpr >= 0) { | |
286 | for (ii=31; ii >= fdatap->saved_fpr; --ii) | |
287 | fi->cache_fsr->regs [FP0_REGNUM + ii] = frame_addr - ((32 - ii) * 8); | |
288 | frame_addr -= (32 - fdatap->saved_fpr) * 8; | |
289 | } | |
290 | ||
291 | /* if != -1, fdatap->saved_gpr is the smallest number of saved_gpr. | |
292 | All gpr's from saved_gpr to gpr31 are saved right under saved fprs, | |
293 | starting from r31 first. */ | |
294 | ||
295 | if (fdatap->saved_gpr >= 0) | |
296 | for (ii=31; ii >= fdatap->saved_gpr; --ii) | |
297 | fi->cache_fsr->regs [ii] = frame_addr - ((32 - ii) * 4); | |
298 | } | |
299 | ||
6c6afbb9 PB |
300 | /* Return the address of a frame. This is the inital %sp value when the frame |
301 | was first allocated. For functions calling alloca(), it might be saved in | |
302 | an alloca register. */ | |
303 | ||
304 | CORE_ADDR | |
305 | frame_initial_stack_address (fi) | |
4ef09e36 | 306 | struct frame_info *fi; |
6c6afbb9 | 307 | { |
4ef09e36 | 308 | CORE_ADDR tmpaddr; |
6c6afbb9 PB |
309 | struct aix_framedata fdata; |
310 | struct frame_info *callee_fi; | |
6c6afbb9 PB |
311 | |
312 | /* if the initial stack pointer (frame address) of this frame is known, | |
313 | just return it. */ | |
314 | ||
315 | if (fi->initial_sp) | |
316 | return fi->initial_sp; | |
317 | ||
318 | /* find out if this function is using an alloca register.. */ | |
319 | ||
4ef09e36 | 320 | function_frame_info (get_pc_function_start (fi->pc), &fdata); |
6c6afbb9 PB |
321 | |
322 | /* if saved registers of this frame are not known yet, read and cache them. */ | |
323 | ||
4ef09e36 PB |
324 | if (!fi->cache_fsr) |
325 | frame_get_cache_fsr (fi, &fdata); | |
6c6afbb9 PB |
326 | |
327 | /* If no alloca register used, then fi->frame is the value of the %sp for | |
328 | this frame, and it is good enough. */ | |
329 | ||
330 | if (fdata.alloca_reg < 0) { | |
331 | fi->initial_sp = fi->frame; | |
332 | return fi->initial_sp; | |
333 | } | |
334 | ||
335 | /* This function has an alloca register. If this is the top-most frame | |
336 | (with the lowest address), the value in alloca register is good. */ | |
337 | ||
338 | if (!fi->next) | |
339 | return fi->initial_sp = read_register (fdata.alloca_reg); | |
340 | ||
4ef09e36 | 341 | /* Otherwise, this is a caller frame. Callee has usually already saved |
507e4004 | 342 | registers, but there are exceptions (such as when the callee |
4ef09e36 PB |
343 | has no parameters). Find the address in which caller's alloca |
344 | register is saved. */ | |
6c6afbb9 PB |
345 | |
346 | for (callee_fi = fi->next; callee_fi; callee_fi = callee_fi->next) { | |
347 | ||
348 | if (!callee_fi->cache_fsr) | |
4ef09e36 | 349 | frame_get_cache_fsr (fi, NULL); |
6c6afbb9 PB |
350 | |
351 | /* this is the address in which alloca register is saved. */ | |
352 | ||
353 | tmpaddr = callee_fi->cache_fsr->regs [fdata.alloca_reg]; | |
354 | if (tmpaddr) { | |
355 | fi->initial_sp = read_memory_integer (tmpaddr, 4); | |
356 | return fi->initial_sp; | |
357 | } | |
358 | ||
359 | /* Go look into deeper levels of the frame chain to see if any one of | |
360 | the callees has saved alloca register. */ | |
361 | } | |
362 | ||
363 | /* If alloca register was not saved, by the callee (or any of its callees) | |
364 | then the value in the register is still good. */ | |
365 | ||
366 | return fi->initial_sp = read_register (fdata.alloca_reg); | |
367 | } | |
368 | ||
369 | ||
370 | ||
41abdfbd JG |
371 | /* aixcoff_relocate_symtab - hook for symbol table relocation. |
372 | also reads shared libraries.. */ | |
373 | ||
374 | aixcoff_relocate_symtab (pid) | |
375 | unsigned int pid; | |
376 | { | |
377 | #define MAX_LOAD_SEGS 64 /* maximum number of load segments */ | |
378 | ||
41abdfbd JG |
379 | struct ld_info *ldi; |
380 | int temp; | |
381 | ||
382 | ldi = (void *) alloca(MAX_LOAD_SEGS * sizeof (*ldi)); | |
383 | ||
384 | /* According to my humble theory, aixcoff has some timing problems and | |
385 | when the user stack grows, kernel doesn't update stack info in time | |
386 | and ptrace calls step on user stack. That is why we sleep here a little, | |
387 | and give kernel to update its internals. */ | |
388 | ||
389 | usleep (36000); | |
390 | ||
391 | errno = 0; | |
e676a15f FF |
392 | ptrace(PT_LDINFO, pid, (PTRACE_ARG3_TYPE) ldi, |
393 | MAX_LOAD_SEGS * sizeof(*ldi), ldi); | |
818de002 | 394 | if (errno) { |
41abdfbd | 395 | perror_with_name ("ptrace ldinfo"); |
818de002 PB |
396 | return 0; |
397 | } | |
41abdfbd JG |
398 | |
399 | vmap_ldinfo(ldi); | |
400 | ||
401 | do { | |
402 | add_text_to_loadinfo (ldi->ldinfo_textorg, ldi->ldinfo_dataorg); | |
403 | } while (ldi->ldinfo_next | |
404 | && (ldi = (void *) (ldi->ldinfo_next + (char *) ldi))); | |
405 | ||
818de002 | 406 | #if 0 |
41abdfbd | 407 | /* Now that we've jumbled things around, re-sort them. */ |
1ab3bf1b | 408 | sort_minimal_symbols (); |
818de002 | 409 | #endif |
41abdfbd JG |
410 | |
411 | /* relocate the exec and core sections as well. */ | |
412 | vmap_exec (); | |
413 | } | |
414 | ||
415 | ||
416 | /* Keep an array of load segment information and their TOC table addresses. | |
417 | This info will be useful when calling a shared library function by hand. */ | |
418 | ||
419 | typedef struct { | |
420 | unsigned long textorg, dataorg, toc_offset; | |
421 | } LoadInfo; | |
422 | ||
423 | #define LOADINFOLEN 10 | |
424 | ||
425 | static LoadInfo *loadInfo = NULL; | |
426 | static int loadInfoLen = 0; | |
427 | static int loadInfoTocIndex = 0; | |
818de002 | 428 | int aix_loadInfoTextIndex = 0; |
41abdfbd JG |
429 | |
430 | ||
431 | xcoff_init_loadinfo () | |
432 | { | |
433 | loadInfoTocIndex = 0; | |
818de002 | 434 | aix_loadInfoTextIndex = 0; |
41abdfbd JG |
435 | |
436 | if (loadInfoLen == 0) { | |
437 | loadInfo = (void*) xmalloc (sizeof (LoadInfo) * LOADINFOLEN); | |
438 | loadInfoLen = LOADINFOLEN; | |
439 | } | |
440 | } | |
441 | ||
442 | ||
443 | free_loadinfo () | |
444 | { | |
445 | if (loadInfo) | |
446 | free (loadInfo); | |
447 | loadInfo = NULL; | |
448 | loadInfoLen = 0; | |
449 | loadInfoTocIndex = 0; | |
818de002 | 450 | aix_loadInfoTextIndex = 0; |
41abdfbd JG |
451 | } |
452 | ||
453 | ||
454 | xcoff_add_toc_to_loadinfo (unsigned long tocaddr) | |
455 | { | |
456 | while (loadInfoTocIndex >= loadInfoLen) { | |
457 | loadInfoLen += LOADINFOLEN; | |
458 | loadInfo = (void*) xrealloc (loadInfo, sizeof(LoadInfo) * loadInfoLen); | |
459 | } | |
460 | loadInfo [loadInfoTocIndex++].toc_offset = tocaddr; | |
461 | } | |
462 | ||
463 | ||
464 | add_text_to_loadinfo (unsigned long textaddr, unsigned long dataaddr) | |
465 | { | |
818de002 | 466 | while (aix_loadInfoTextIndex >= loadInfoLen) { |
41abdfbd JG |
467 | loadInfoLen += LOADINFOLEN; |
468 | loadInfo = (void*) xrealloc (loadInfo, sizeof(LoadInfo) * loadInfoLen); | |
469 | } | |
818de002 PB |
470 | loadInfo [aix_loadInfoTextIndex].textorg = textaddr; |
471 | loadInfo [aix_loadInfoTextIndex].dataorg = dataaddr; | |
472 | ++aix_loadInfoTextIndex; | |
41abdfbd JG |
473 | } |
474 | ||
475 | ||
476 | unsigned long | |
477 | find_toc_address (unsigned long pc) | |
478 | { | |
818de002 | 479 | int ii, toc_entry, tocbase = 0; |
41abdfbd | 480 | |
818de002 PB |
481 | for (ii=0; ii < aix_loadInfoTextIndex; ++ii) |
482 | if (pc > loadInfo [ii].textorg && loadInfo [ii].textorg > tocbase) { | |
41abdfbd | 483 | toc_entry = ii; |
818de002 PB |
484 | tocbase = loadInfo [ii].textorg; |
485 | } | |
41abdfbd JG |
486 | |
487 | return loadInfo [toc_entry].dataorg + loadInfo [toc_entry].toc_offset; | |
488 | } | |
489 | ||
490 | ||
491 | /* execute one dummy breakpoint instruction. This way we give kernel | |
492 | a chance to do some housekeeping and update inferior's internal data, | |
493 | including u_area. */ | |
494 | ||
495 | exec_one_dummy_insn () | |
496 | { | |
818de002 | 497 | #define DUMMY_INSN_ADDR (TEXT_SEGMENT_BASE)+0x200 |
41abdfbd JG |
498 | |
499 | unsigned long shadow; | |
500 | unsigned int status, pid; | |
501 | ||
818de002 PB |
502 | /* We plant one dummy breakpoint into DUMMY_INSN_ADDR address. We assume that |
503 | this address will never be executed again by the real code. */ | |
504 | ||
41abdfbd JG |
505 | target_insert_breakpoint (DUMMY_INSN_ADDR, &shadow); |
506 | ||
507 | errno = 0; | |
e676a15f | 508 | ptrace (PT_CONTINUE, inferior_pid, (PTRACE_ARG3_TYPE) DUMMY_INSN_ADDR, 0, 0); |
41abdfbd JG |
509 | if (errno) |
510 | perror ("pt_continue"); | |
511 | ||
512 | do { | |
513 | pid = wait (&status); | |
514 | } while (pid != inferior_pid); | |
515 | ||
516 | target_remove_breakpoint (DUMMY_INSN_ADDR, &shadow); | |
517 | } | |
518 | ||
818de002 | 519 | |
1eeba686 PB |
520 | #if 0 |
521 | ||
522 | *** not needed anymore *** | |
523 | ||
818de002 PB |
524 | /* Return the number of initial trap signals we need to ignore once the inferior |
525 | process starts running. This will be `2' for aix-3.1, `3' for aix-3.2 */ | |
526 | ||
527 | int | |
528 | aix_starting_inferior_traps () | |
529 | { | |
530 | struct utsname unamebuf; | |
531 | ||
532 | if (uname (&unamebuf) == -1) | |
533 | fatal ("uname(3) failed."); | |
534 | ||
535 | /* Assume the future versions will behave like 3.2 and return '3' for | |
536 | anything other than 3.1x. The extra trap in 3.2 is the "trap after the | |
537 | program is loaded" signal. */ | |
538 | ||
539 | if (unamebuf.version[0] == '3' && unamebuf.release[0] == '1') | |
540 | return 2; | |
541 | else | |
542 | return 3; | |
543 | } | |
1eeba686 | 544 | #endif |