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41abdfbd JG |
1 | /* IBM RS/6000 host-dependent code for GDB, the GNU debugger. |
2 | Copyright (C) 1986, 1987, 1989, 1991 Free Software Foundation, Inc. | |
3 | ||
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2 of the License, or | |
9 | (at your option) any later version. | |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program; if not, write to the Free Software | |
18 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ | |
19 | ||
41abdfbd | 20 | #include "defs.h" |
41abdfbd JG |
21 | #include "frame.h" |
22 | #include "inferior.h" | |
23 | #include "symtab.h" | |
24 | #include "target.h" | |
25 | ||
26 | #include <sys/param.h> | |
27 | #include <sys/dir.h> | |
28 | #include <sys/user.h> | |
29 | #include <signal.h> | |
30 | #include <sys/ioctl.h> | |
31 | #include <fcntl.h> | |
32 | ||
33 | #include <sys/ptrace.h> | |
34 | #include <sys/reg.h> | |
35 | ||
36 | #include <a.out.h> | |
37 | #include <sys/file.h> | |
38 | #include <sys/stat.h> | |
39 | #include <sys/core.h> | |
40 | #include <sys/ldr.h> | |
818de002 | 41 | #include <sys/utsname.h> |
41abdfbd JG |
42 | |
43 | extern int errno; | |
44 | extern int attach_flag; | |
45 | ||
46 | /* Conversion from gdb-to-system special purpose register numbers.. */ | |
47 | ||
48 | static int special_regs[] = { | |
49 | IAR, /* PC_REGNUM */ | |
50 | MSR, /* PS_REGNUM */ | |
51 | CR, /* CR_REGNUM */ | |
52 | LR, /* LR_REGNUM */ | |
53 | CTR, /* CTR_REGNUM */ | |
54 | XER, /* XER_REGNUM */ | |
55 | MQ /* MQ_REGNUM */ | |
56 | }; | |
57 | ||
58 | ||
59 | /* Nonzero if we just simulated a single step break. */ | |
60 | extern int one_stepped; | |
61 | ||
2b5a8d9c | 62 | extern char register_valid[]; |
4ef09e36 | 63 | extern struct obstack frame_cache_obstack; |
2b5a8d9c | 64 | |
41abdfbd | 65 | \f |
818de002 | 66 | void |
1ab3bf1b | 67 | fetch_inferior_registers (regno) |
2b5a8d9c | 68 | int regno; |
41abdfbd JG |
69 | { |
70 | int ii; | |
71 | extern char registers[]; | |
72 | ||
2b5a8d9c | 73 | if (regno < 0) { /* for all registers */ |
41abdfbd | 74 | |
2b5a8d9c PB |
75 | /* read 32 general purpose registers. */ |
76 | ||
77 | for (ii=0; ii < 32; ++ii) | |
78 | *(int*)®isters[REGISTER_BYTE (ii)] = | |
41abdfbd JG |
79 | ptrace (PT_READ_GPR, inferior_pid, ii, 0, 0); |
80 | ||
2b5a8d9c | 81 | /* read general purpose floating point registers. */ |
41abdfbd | 82 | |
2b5a8d9c PB |
83 | for (ii=0; ii < 32; ++ii) |
84 | ptrace (PT_READ_FPR, inferior_pid, | |
41abdfbd JG |
85 | (int*)®isters [REGISTER_BYTE (FP0_REGNUM+ii)], FPR0+ii, 0); |
86 | ||
2b5a8d9c PB |
87 | /* read special registers. */ |
88 | for (ii=0; ii <= LAST_SP_REGNUM-FIRST_SP_REGNUM; ++ii) | |
89 | *(int*)®isters[REGISTER_BYTE (FIRST_SP_REGNUM+ii)] = | |
41abdfbd | 90 | ptrace (PT_READ_GPR, inferior_pid, special_regs[ii], 0, 0); |
2b5a8d9c PB |
91 | |
92 | registers_fetched (); | |
93 | return; | |
94 | } | |
95 | ||
96 | /* else an individual register is addressed. */ | |
97 | ||
98 | else if (regno < FP0_REGNUM) { /* a GPR */ | |
99 | *(int*)®isters[REGISTER_BYTE (regno)] = | |
100 | ptrace (PT_READ_GPR, inferior_pid, regno, 0, 0); | |
101 | } | |
102 | else if (regno <= FPLAST_REGNUM) { /* a FPR */ | |
103 | ptrace (PT_READ_FPR, inferior_pid, | |
104 | (int*)®isters [REGISTER_BYTE (regno)], (regno-FP0_REGNUM+FPR0), 0); | |
105 | } | |
106 | else if (regno <= LAST_SP_REGNUM) { /* a special register */ | |
107 | *(int*)®isters[REGISTER_BYTE (regno)] = | |
108 | ptrace (PT_READ_GPR, inferior_pid, | |
109 | special_regs[regno-FIRST_SP_REGNUM], 0, 0); | |
110 | } | |
111 | else | |
112 | fprintf (stderr, "gdb error: register no %d not implemented.\n", regno); | |
113 | ||
114 | register_valid [regno] = 1; | |
41abdfbd JG |
115 | } |
116 | ||
117 | /* Store our register values back into the inferior. | |
118 | If REGNO is -1, do this for all registers. | |
119 | Otherwise, REGNO specifies which register (so we can save time). */ | |
120 | ||
1ab3bf1b | 121 | void |
41abdfbd JG |
122 | store_inferior_registers (regno) |
123 | int regno; | |
124 | { | |
125 | extern char registers[]; | |
126 | ||
127 | errno = 0; | |
128 | ||
129 | if (regno == -1) { /* for all registers.. */ | |
130 | int ii; | |
131 | ||
132 | /* execute one dummy instruction (which is a breakpoint) in inferior | |
133 | process. So give kernel a chance to do internal house keeping. | |
134 | Otherwise the following ptrace(2) calls will mess up user stack | |
135 | since kernel will get confused about the bottom of the stack (%sp) */ | |
136 | ||
137 | exec_one_dummy_insn (); | |
138 | ||
139 | /* write general purpose registers first! */ | |
140 | for ( ii=GPR0; ii<=GPR31; ++ii) { | |
141 | ptrace (PT_WRITE_GPR, inferior_pid, ii, | |
142 | *(int*)®isters[REGISTER_BYTE (ii)], 0); | |
143 | if ( errno ) { | |
144 | perror ("ptrace write_gpr"); errno = 0; | |
145 | } | |
146 | } | |
147 | ||
148 | /* write floating point registers now. */ | |
149 | for ( ii=0; ii < 32; ++ii) { | |
150 | ptrace (PT_WRITE_FPR, inferior_pid, | |
151 | (int*)®isters[REGISTER_BYTE (FP0_REGNUM+ii)], FPR0+ii, 0); | |
152 | if ( errno ) { | |
153 | perror ("ptrace write_fpr"); errno = 0; | |
154 | } | |
155 | } | |
156 | ||
157 | /* write special registers. */ | |
158 | for (ii=0; ii <= LAST_SP_REGNUM-FIRST_SP_REGNUM; ++ii) { | |
159 | ptrace (PT_WRITE_GPR, inferior_pid, special_regs[ii], | |
160 | *(int*)®isters[REGISTER_BYTE (FIRST_SP_REGNUM+ii)], 0); | |
161 | if ( errno ) { | |
162 | perror ("ptrace write_gpr"); errno = 0; | |
163 | } | |
164 | } | |
165 | } | |
166 | ||
167 | /* else, a specific register number is given... */ | |
168 | ||
169 | else if (regno < FP0_REGNUM) { /* a GPR */ | |
170 | ||
171 | ptrace (PT_WRITE_GPR, inferior_pid, regno, | |
172 | *(int*)®isters[REGISTER_BYTE (regno)], 0); | |
173 | } | |
174 | ||
175 | else if (regno <= FPLAST_REGNUM) { /* a FPR */ | |
176 | ptrace (PT_WRITE_FPR, inferior_pid, | |
177 | (int*)®isters[REGISTER_BYTE (regno)], regno-FP0_REGNUM+FPR0, 0); | |
178 | } | |
179 | ||
180 | else if (regno <= LAST_SP_REGNUM) { /* a special register */ | |
181 | ||
182 | ptrace (PT_WRITE_GPR, inferior_pid, special_regs [regno-FIRST_SP_REGNUM], | |
183 | *(int*)®isters[REGISTER_BYTE (regno)], 0); | |
184 | } | |
185 | ||
186 | else | |
187 | fprintf (stderr, "Gdb error: register no %d not implemented.\n", regno); | |
188 | ||
189 | if ( errno ) { | |
190 | perror ("ptrace write"); errno = 0; | |
41abdfbd | 191 | } |
41abdfbd JG |
192 | } |
193 | ||
194 | void | |
1ab3bf1b | 195 | fetch_core_registers (core_reg_sect, core_reg_size, which, reg_addr) |
41abdfbd JG |
196 | char *core_reg_sect; |
197 | unsigned core_reg_size; | |
198 | int which; | |
1ab3bf1b | 199 | unsigned int reg_addr; /* Unused in this version */ |
41abdfbd JG |
200 | { |
201 | /* fetch GPRs and special registers from the first register section | |
202 | in core bfd. */ | |
203 | if (which == 0) { | |
204 | ||
205 | /* copy GPRs first. */ | |
206 | bcopy (core_reg_sect, registers, 32 * 4); | |
207 | ||
208 | /* gdb's internal register template and bfd's register section layout | |
209 | should share a common include file. FIXMEmgo */ | |
210 | /* then comes special registes. They are supposed to be in the same | |
211 | order in gdb template and bfd `.reg' section. */ | |
212 | core_reg_sect += (32 * 4); | |
213 | bcopy (core_reg_sect, ®isters [REGISTER_BYTE (FIRST_SP_REGNUM)], | |
214 | (LAST_SP_REGNUM - FIRST_SP_REGNUM + 1) * 4); | |
215 | } | |
216 | ||
217 | /* fetch floating point registers from register section 2 in core bfd. */ | |
218 | else if (which == 2) | |
219 | bcopy (core_reg_sect, ®isters [REGISTER_BYTE (FP0_REGNUM)], 32 * 8); | |
220 | ||
221 | else | |
222 | fprintf (stderr, "Gdb error: unknown parameter to fetch_core_registers().\n"); | |
223 | } | |
224 | ||
225 | ||
226 | frameless_function_invocation (fi) | |
227 | struct frame_info *fi; | |
228 | { | |
818de002 | 229 | CORE_ADDR func_start; |
6c6afbb9 | 230 | struct aix_framedata fdata; |
41abdfbd | 231 | |
41abdfbd | 232 | func_start = get_pc_function_start (fi->pc) + FUNCTION_START_OFFSET; |
41abdfbd | 233 | |
818de002 PB |
234 | /* If we failed to find the start of the function, it is a mistake |
235 | to inspect the instructions. */ | |
236 | ||
237 | if (!func_start) | |
238 | return 0; | |
239 | ||
6c6afbb9 PB |
240 | function_frame_info (func_start, &fdata); |
241 | return fdata.frameless; | |
41abdfbd JG |
242 | } |
243 | ||
244 | ||
4ef09e36 PB |
245 | /* If saved registers of frame FI are not known yet, read and cache them. |
246 | &FDATAP contains aix_framedata; TDATAP can be NULL, | |
247 | in which case the framedata are read. | |
248 | */ | |
249 | ||
250 | static void | |
251 | frame_get_cache_fsr (fi, fdatap) | |
252 | struct frame_info *fi; | |
253 | struct aix_framedata *fdatap; | |
254 | { | |
255 | int ii; | |
256 | CORE_ADDR frame_addr; | |
257 | struct aix_framedata work_fdata; | |
258 | if (fi->cache_fsr) | |
259 | return; | |
260 | ||
261 | if (fdatap = NULL) { | |
262 | fdatap = &work_fdata; | |
263 | function_frame_info (get_pc_function_start (fi->pc), fdatap); | |
264 | } | |
265 | ||
266 | fi->cache_fsr = (struct frame_saved_regs *) | |
267 | obstack_alloc (&frame_cache_obstack, sizeof (struct frame_saved_regs)); | |
268 | bzero (fi->cache_fsr, sizeof (struct frame_saved_regs)); | |
269 | ||
270 | if (fi->prev && fi->prev->frame) | |
271 | frame_addr = fi->prev->frame; | |
272 | else | |
273 | frame_addr = read_memory_integer (fi->frame, 4); | |
274 | ||
275 | /* if != -1, fdatap->saved_fpr is the smallest number of saved_fpr. | |
276 | All fpr's from saved_fpr to fp31 are saved right underneath caller | |
277 | stack pointer, starting from fp31 first. */ | |
278 | ||
279 | if (fdatap->saved_fpr >= 0) { | |
280 | for (ii=31; ii >= fdatap->saved_fpr; --ii) | |
281 | fi->cache_fsr->regs [FP0_REGNUM + ii] = frame_addr - ((32 - ii) * 8); | |
282 | frame_addr -= (32 - fdatap->saved_fpr) * 8; | |
283 | } | |
284 | ||
285 | /* if != -1, fdatap->saved_gpr is the smallest number of saved_gpr. | |
286 | All gpr's from saved_gpr to gpr31 are saved right under saved fprs, | |
287 | starting from r31 first. */ | |
288 | ||
289 | if (fdatap->saved_gpr >= 0) | |
290 | for (ii=31; ii >= fdatap->saved_gpr; --ii) | |
291 | fi->cache_fsr->regs [ii] = frame_addr - ((32 - ii) * 4); | |
292 | } | |
293 | ||
6c6afbb9 PB |
294 | /* Return the address of a frame. This is the inital %sp value when the frame |
295 | was first allocated. For functions calling alloca(), it might be saved in | |
296 | an alloca register. */ | |
297 | ||
298 | CORE_ADDR | |
299 | frame_initial_stack_address (fi) | |
4ef09e36 | 300 | struct frame_info *fi; |
6c6afbb9 | 301 | { |
4ef09e36 | 302 | CORE_ADDR tmpaddr; |
6c6afbb9 PB |
303 | struct aix_framedata fdata; |
304 | struct frame_info *callee_fi; | |
6c6afbb9 PB |
305 | |
306 | /* if the initial stack pointer (frame address) of this frame is known, | |
307 | just return it. */ | |
308 | ||
309 | if (fi->initial_sp) | |
310 | return fi->initial_sp; | |
311 | ||
312 | /* find out if this function is using an alloca register.. */ | |
313 | ||
4ef09e36 | 314 | function_frame_info (get_pc_function_start (fi->pc), &fdata); |
6c6afbb9 PB |
315 | |
316 | /* if saved registers of this frame are not known yet, read and cache them. */ | |
317 | ||
4ef09e36 PB |
318 | if (!fi->cache_fsr) |
319 | frame_get_cache_fsr (fi, &fdata); | |
6c6afbb9 PB |
320 | |
321 | /* If no alloca register used, then fi->frame is the value of the %sp for | |
322 | this frame, and it is good enough. */ | |
323 | ||
324 | if (fdata.alloca_reg < 0) { | |
325 | fi->initial_sp = fi->frame; | |
326 | return fi->initial_sp; | |
327 | } | |
328 | ||
329 | /* This function has an alloca register. If this is the top-most frame | |
330 | (with the lowest address), the value in alloca register is good. */ | |
331 | ||
332 | if (!fi->next) | |
333 | return fi->initial_sp = read_register (fdata.alloca_reg); | |
334 | ||
4ef09e36 PB |
335 | /* Otherwise, this is a caller frame. Callee has usually already saved |
336 | registers, but there are are exceptions (such as when the callee | |
337 | has no parameters). Find the address in which caller's alloca | |
338 | register is saved. */ | |
6c6afbb9 PB |
339 | |
340 | for (callee_fi = fi->next; callee_fi; callee_fi = callee_fi->next) { | |
341 | ||
342 | if (!callee_fi->cache_fsr) | |
4ef09e36 | 343 | frame_get_cache_fsr (fi, NULL); |
6c6afbb9 PB |
344 | |
345 | /* this is the address in which alloca register is saved. */ | |
346 | ||
347 | tmpaddr = callee_fi->cache_fsr->regs [fdata.alloca_reg]; | |
348 | if (tmpaddr) { | |
349 | fi->initial_sp = read_memory_integer (tmpaddr, 4); | |
350 | return fi->initial_sp; | |
351 | } | |
352 | ||
353 | /* Go look into deeper levels of the frame chain to see if any one of | |
354 | the callees has saved alloca register. */ | |
355 | } | |
356 | ||
357 | /* If alloca register was not saved, by the callee (or any of its callees) | |
358 | then the value in the register is still good. */ | |
359 | ||
360 | return fi->initial_sp = read_register (fdata.alloca_reg); | |
361 | } | |
362 | ||
363 | ||
364 | ||
41abdfbd JG |
365 | /* aixcoff_relocate_symtab - hook for symbol table relocation. |
366 | also reads shared libraries.. */ | |
367 | ||
368 | aixcoff_relocate_symtab (pid) | |
369 | unsigned int pid; | |
370 | { | |
371 | #define MAX_LOAD_SEGS 64 /* maximum number of load segments */ | |
372 | ||
41abdfbd JG |
373 | struct ld_info *ldi; |
374 | int temp; | |
375 | ||
376 | ldi = (void *) alloca(MAX_LOAD_SEGS * sizeof (*ldi)); | |
377 | ||
378 | /* According to my humble theory, aixcoff has some timing problems and | |
379 | when the user stack grows, kernel doesn't update stack info in time | |
380 | and ptrace calls step on user stack. That is why we sleep here a little, | |
381 | and give kernel to update its internals. */ | |
382 | ||
383 | usleep (36000); | |
384 | ||
385 | errno = 0; | |
386 | ptrace(PT_LDINFO, pid, ldi, MAX_LOAD_SEGS * sizeof(*ldi), ldi); | |
818de002 | 387 | if (errno) { |
41abdfbd | 388 | perror_with_name ("ptrace ldinfo"); |
818de002 PB |
389 | return 0; |
390 | } | |
41abdfbd JG |
391 | |
392 | vmap_ldinfo(ldi); | |
393 | ||
394 | do { | |
395 | add_text_to_loadinfo (ldi->ldinfo_textorg, ldi->ldinfo_dataorg); | |
396 | } while (ldi->ldinfo_next | |
397 | && (ldi = (void *) (ldi->ldinfo_next + (char *) ldi))); | |
398 | ||
818de002 | 399 | #if 0 |
41abdfbd | 400 | /* Now that we've jumbled things around, re-sort them. */ |
1ab3bf1b | 401 | sort_minimal_symbols (); |
818de002 | 402 | #endif |
41abdfbd JG |
403 | |
404 | /* relocate the exec and core sections as well. */ | |
405 | vmap_exec (); | |
406 | } | |
407 | ||
408 | ||
409 | /* Keep an array of load segment information and their TOC table addresses. | |
410 | This info will be useful when calling a shared library function by hand. */ | |
411 | ||
412 | typedef struct { | |
413 | unsigned long textorg, dataorg, toc_offset; | |
414 | } LoadInfo; | |
415 | ||
416 | #define LOADINFOLEN 10 | |
417 | ||
418 | static LoadInfo *loadInfo = NULL; | |
419 | static int loadInfoLen = 0; | |
420 | static int loadInfoTocIndex = 0; | |
818de002 | 421 | int aix_loadInfoTextIndex = 0; |
41abdfbd JG |
422 | |
423 | ||
424 | xcoff_init_loadinfo () | |
425 | { | |
426 | loadInfoTocIndex = 0; | |
818de002 | 427 | aix_loadInfoTextIndex = 0; |
41abdfbd JG |
428 | |
429 | if (loadInfoLen == 0) { | |
430 | loadInfo = (void*) xmalloc (sizeof (LoadInfo) * LOADINFOLEN); | |
431 | loadInfoLen = LOADINFOLEN; | |
432 | } | |
433 | } | |
434 | ||
435 | ||
436 | free_loadinfo () | |
437 | { | |
438 | if (loadInfo) | |
439 | free (loadInfo); | |
440 | loadInfo = NULL; | |
441 | loadInfoLen = 0; | |
442 | loadInfoTocIndex = 0; | |
818de002 | 443 | aix_loadInfoTextIndex = 0; |
41abdfbd JG |
444 | } |
445 | ||
446 | ||
447 | xcoff_add_toc_to_loadinfo (unsigned long tocaddr) | |
448 | { | |
449 | while (loadInfoTocIndex >= loadInfoLen) { | |
450 | loadInfoLen += LOADINFOLEN; | |
451 | loadInfo = (void*) xrealloc (loadInfo, sizeof(LoadInfo) * loadInfoLen); | |
452 | } | |
453 | loadInfo [loadInfoTocIndex++].toc_offset = tocaddr; | |
454 | } | |
455 | ||
456 | ||
457 | add_text_to_loadinfo (unsigned long textaddr, unsigned long dataaddr) | |
458 | { | |
818de002 | 459 | while (aix_loadInfoTextIndex >= loadInfoLen) { |
41abdfbd JG |
460 | loadInfoLen += LOADINFOLEN; |
461 | loadInfo = (void*) xrealloc (loadInfo, sizeof(LoadInfo) * loadInfoLen); | |
462 | } | |
818de002 PB |
463 | loadInfo [aix_loadInfoTextIndex].textorg = textaddr; |
464 | loadInfo [aix_loadInfoTextIndex].dataorg = dataaddr; | |
465 | ++aix_loadInfoTextIndex; | |
41abdfbd JG |
466 | } |
467 | ||
468 | ||
469 | unsigned long | |
470 | find_toc_address (unsigned long pc) | |
471 | { | |
818de002 | 472 | int ii, toc_entry, tocbase = 0; |
41abdfbd | 473 | |
818de002 PB |
474 | for (ii=0; ii < aix_loadInfoTextIndex; ++ii) |
475 | if (pc > loadInfo [ii].textorg && loadInfo [ii].textorg > tocbase) { | |
41abdfbd | 476 | toc_entry = ii; |
818de002 PB |
477 | tocbase = loadInfo [ii].textorg; |
478 | } | |
41abdfbd JG |
479 | |
480 | return loadInfo [toc_entry].dataorg + loadInfo [toc_entry].toc_offset; | |
481 | } | |
482 | ||
483 | ||
484 | /* execute one dummy breakpoint instruction. This way we give kernel | |
485 | a chance to do some housekeeping and update inferior's internal data, | |
486 | including u_area. */ | |
487 | ||
488 | exec_one_dummy_insn () | |
489 | { | |
818de002 | 490 | #define DUMMY_INSN_ADDR (TEXT_SEGMENT_BASE)+0x200 |
41abdfbd JG |
491 | |
492 | unsigned long shadow; | |
493 | unsigned int status, pid; | |
494 | ||
818de002 PB |
495 | /* We plant one dummy breakpoint into DUMMY_INSN_ADDR address. We assume that |
496 | this address will never be executed again by the real code. */ | |
497 | ||
41abdfbd JG |
498 | target_insert_breakpoint (DUMMY_INSN_ADDR, &shadow); |
499 | ||
500 | errno = 0; | |
501 | ptrace (PT_CONTINUE, inferior_pid, DUMMY_INSN_ADDR, 0, 0); | |
502 | if (errno) | |
503 | perror ("pt_continue"); | |
504 | ||
505 | do { | |
506 | pid = wait (&status); | |
507 | } while (pid != inferior_pid); | |
508 | ||
509 | target_remove_breakpoint (DUMMY_INSN_ADDR, &shadow); | |
510 | } | |
511 | ||
818de002 PB |
512 | |
513 | /* Return the number of initial trap signals we need to ignore once the inferior | |
514 | process starts running. This will be `2' for aix-3.1, `3' for aix-3.2 */ | |
515 | ||
516 | int | |
517 | aix_starting_inferior_traps () | |
518 | { | |
519 | struct utsname unamebuf; | |
520 | ||
521 | if (uname (&unamebuf) == -1) | |
522 | fatal ("uname(3) failed."); | |
523 | ||
524 | /* Assume the future versions will behave like 3.2 and return '3' for | |
525 | anything other than 3.1x. The extra trap in 3.2 is the "trap after the | |
526 | program is loaded" signal. */ | |
527 | ||
528 | if (unamebuf.version[0] == '3' && unamebuf.release[0] == '1') | |
529 | return 2; | |
530 | else | |
531 | return 3; | |
532 | } |