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gdb/testsuite/
[deliverable/binutils-gdb.git] / gdb / sh-tdep.c
CommitLineData
85a453d5 1/* Target-dependent code for Renesas Super-H, for GDB.
0fd88904 2
0b302171 3 Copyright (C) 1993-2005, 2007-2012 Free Software Foundation, Inc.
c906108c 4
c5aa993b 5 This file is part of GDB.
c906108c 6
c5aa993b
JM		 7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
a9762ec7 9 the Free Software Foundation; either version 3 of the License, or
c5aa993b 10 (at your option) any later version.
c906108c 11
c5aa993b
JM		 12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
c906108c 16
c5aa993b 17 You should have received a copy of the GNU General Public License
a9762ec7 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
c906108c 19
c378eb4e
MS		 20/* Contributed by Steve Chamberlain
21 sac@cygnus.com. */
c906108c
SS		 22
23#include "defs.h"
24#include "frame.h"
1c0159e0
CV		 25#include "frame-base.h"
26#include "frame-unwind.h"
27#include "dwarf2-frame.h"
c906108c 28#include "symtab.h"
c906108c
SS		 29#include "gdbtypes.h"
30#include "gdbcmd.h"
31#include "gdbcore.h"
32#include "value.h"
33#include "dis-asm.h"
73c1f219 34#include "inferior.h"
c906108c 35#include "gdb_string.h"
1c0159e0 36#include "gdb_assert.h"
b4a20239 37#include "arch-utils.h"
fb409745 38#include "floatformat.h"
4e052eda 39#include "regcache.h"
d16aafd8 40#include "doublest.h"
4be87837 41#include "osabi.h"
dda63807 42#include "reggroups.h"
c9ac0a72 43#include "regset.h"
c906108c 44
ab3b8126
JT		 45#include "sh-tdep.h"
46
d658f924 47#include "elf-bfd.h"
1a8629c7
MS		 48#include "solib-svr4.h"
49
55ff77ac 50/* sh flags */
283150cd 51#include "elf/sh.h"
fa8f86ff 52#include "dwarf2.h"
c378eb4e 53/* registers numbers shared with the simulator. */
1c922164 54#include "gdb/sim-sh.h"
283150cd 55
c055b101
CV		 56/* List of "set sh ..." and "show sh ..." commands. */
57static struct cmd_list_element *setshcmdlist = NULL;
58static struct cmd_list_element *showshcmdlist = NULL;
59
60static const char sh_cc_gcc[] = "gcc";
61static const char sh_cc_renesas[] = "renesas";
40478521 62static const char *const sh_cc_enum[] = {
c055b101
CV		 63 sh_cc_gcc,
64 sh_cc_renesas,
65 NULL
66};
67
68static const char *sh_active_calling_convention = sh_cc_gcc;
69
c458d6db 70static void (*sh_show_regs) (struct frame_info *);
cc17453a 71
da962468 72#define SH_NUM_REGS 67
88e04cc1 73
1c0159e0 74struct sh_frame_cache
cc17453a 75{
1c0159e0
CV		 76 /* Base address. */
77 CORE_ADDR base;
78 LONGEST sp_offset;
79 CORE_ADDR pc;
80
c378eb4e 81 /* Flag showing that a frame has been created in the prologue code. */
1c0159e0
CV		 82 int uses_fp;
83
84 /* Saved registers. */
85 CORE_ADDR saved_regs[SH_NUM_REGS];
86 CORE_ADDR saved_sp;
63978407 87};
c906108c 88
c055b101
CV		 89static int
90sh_is_renesas_calling_convention (struct type *func_type)
91{
ca193e27
TS		 92 int val = 0;
93
94 if (func_type)
95 {
96 func_type = check_typedef (func_type);
97
98 if (TYPE_CODE (func_type) == TYPE_CODE_PTR)
99 func_type = check_typedef (TYPE_TARGET_TYPE (func_type));
100
101 if (TYPE_CODE (func_type) == TYPE_CODE_FUNC
102 && TYPE_CALLING_CONVENTION (func_type) == DW_CC_GNU_renesas_sh)
103 val = 1;
104 }
105
106 if (sh_active_calling_convention == sh_cc_renesas)
107 val = 1;
108
109 return val;
c055b101
CV		 110}
111
fa88f677 112static const char *
d93859e2 113sh_sh_register_name (struct gdbarch *gdbarch, int reg_nr)
cc17453a 114{
617daa0e
CV		 115 static char *register_names[] = {
116 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
117 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
118 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
119 "", "",
120 "", "", "", "", "", "", "", "",
121 "", "", "", "", "", "", "", "",
122 "", "",
123 "", "", "", "", "", "", "", "",
124 "", "", "", "", "", "", "", "",
da962468 125 "", "", "", "", "", "", "", "",
cc17453a
EZ		 126 };
127 if (reg_nr < 0)
128 return NULL;
129 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
130 return NULL;
131 return register_names[reg_nr];
132}
133
fa88f677 134static const char *
d93859e2 135sh_sh3_register_name (struct gdbarch *gdbarch, int reg_nr)
cc17453a 136{
617daa0e
CV		 137 static char *register_names[] = {
138 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
139 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
140 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
141 "", "",
142 "", "", "", "", "", "", "", "",
143 "", "", "", "", "", "", "", "",
144 "ssr", "spc",
cc17453a
EZ		 145 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
146 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
da962468 147 "", "", "", "", "", "", "", "",
cc17453a
EZ		 148 };
149 if (reg_nr < 0)
150 return NULL;
151 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
152 return NULL;
153 return register_names[reg_nr];
154}
155
fa88f677 156static const char *
d93859e2 157sh_sh3e_register_name (struct gdbarch *gdbarch, int reg_nr)
cc17453a 158{
617daa0e
CV		 159 static char *register_names[] = {
160 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
161 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
162 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
cc17453a 163 "fpul", "fpscr",
617daa0e
CV		 164 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
165 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
166 "ssr", "spc",
cc17453a
EZ		 167 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
168 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
da962468 169 "", "", "", "", "", "", "", "",
cc17453a
EZ		 170 };
171 if (reg_nr < 0)
172 return NULL;
173 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
174 return NULL;
175 return register_names[reg_nr];
176}
177
2d188dd3 178static const char *
d93859e2 179sh_sh2e_register_name (struct gdbarch *gdbarch, int reg_nr)
2d188dd3 180{
617daa0e
CV		 181 static char *register_names[] = {
182 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
183 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
184 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
2d188dd3 185 "fpul", "fpscr",
617daa0e
CV		 186 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
187 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
188 "", "",
2d188dd3
NC		 189 "", "", "", "", "", "", "", "",
190 "", "", "", "", "", "", "", "",
da962468
CV		 191 "", "", "", "", "", "", "", "",
192 };
193 if (reg_nr < 0)
194 return NULL;
195 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
196 return NULL;
197 return register_names[reg_nr];
198}
199
200static const char *
d93859e2 201sh_sh2a_register_name (struct gdbarch *gdbarch, int reg_nr)
da962468
CV		 202{
203 static char *register_names[] = {
204 /* general registers 0-15 */
205 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
206 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
207 /* 16 - 22 */
208 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
209 /* 23, 24 */
210 "fpul", "fpscr",
211 /* floating point registers 25 - 40 */
212 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
213 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
214 /* 41, 42 */
215 "", "",
216 /* 43 - 62. Banked registers. The bank number used is determined by
c378eb4e 217 the bank register (63). */
da962468
CV		 218 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
219 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
220 "machb", "ivnb", "prb", "gbrb", "maclb",
221 /* 63: register bank number, not a real register but used to
222 communicate the register bank currently get/set. This register
223 is hidden to the user, who manipulates it using the pseudo
224 register called "bank" (67). See below. */
225 "",
226 /* 64 - 66 */
227 "ibcr", "ibnr", "tbr",
228 /* 67: register bank number, the user visible pseudo register. */
229 "bank",
230 /* double precision (pseudo) 68 - 75 */
231 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
232 };
233 if (reg_nr < 0)
234 return NULL;
235 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
236 return NULL;
237 return register_names[reg_nr];
238}
239
240static const char *
d93859e2 241sh_sh2a_nofpu_register_name (struct gdbarch *gdbarch, int reg_nr)
da962468
CV		 242{
243 static char *register_names[] = {
244 /* general registers 0-15 */
245 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
246 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
247 /* 16 - 22 */
248 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
249 /* 23, 24 */
250 "", "",
251 /* floating point registers 25 - 40 */
252 "", "", "", "", "", "", "", "",
253 "", "", "", "", "", "", "", "",
254 /* 41, 42 */
255 "", "",
256 /* 43 - 62. Banked registers. The bank number used is determined by
c378eb4e 257 the bank register (63). */
da962468
CV		 258 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
259 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
260 "machb", "ivnb", "prb", "gbrb", "maclb",
261 /* 63: register bank number, not a real register but used to
262 communicate the register bank currently get/set. This register
263 is hidden to the user, who manipulates it using the pseudo
264 register called "bank" (67). See below. */
265 "",
266 /* 64 - 66 */
267 "ibcr", "ibnr", "tbr",
268 /* 67: register bank number, the user visible pseudo register. */
269 "bank",
270 /* double precision (pseudo) 68 - 75 */
271 "", "", "", "", "", "", "", "",
2d188dd3
NC		 272 };
273 if (reg_nr < 0)
274 return NULL;
275 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
276 return NULL;
277 return register_names[reg_nr];
278}
279
fa88f677 280static const char *
d93859e2 281sh_sh_dsp_register_name (struct gdbarch *gdbarch, int reg_nr)
cc17453a 282{
617daa0e
CV		 283 static char *register_names[] = {
284 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
285 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
286 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
287 "", "dsr",
288 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
289 "y0", "y1", "", "", "", "", "", "mod",
290 "", "",
291 "rs", "re", "", "", "", "", "", "",
292 "", "", "", "", "", "", "", "",
da962468 293 "", "", "", "", "", "", "", "",
cc17453a
EZ		 294 };
295 if (reg_nr < 0)
296 return NULL;
297 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
298 return NULL;
299 return register_names[reg_nr];
300}
301
fa88f677 302static const char *
d93859e2 303sh_sh3_dsp_register_name (struct gdbarch *gdbarch, int reg_nr)
cc17453a 304{
617daa0e
CV		 305 static char *register_names[] = {
306 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
307 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
308 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
309 "", "dsr",
310 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
311 "y0", "y1", "", "", "", "", "", "mod",
312 "ssr", "spc",
313 "rs", "re", "", "", "", "", "", "",
026a72f8
CV		 314 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
315 "", "", "", "", "", "", "", "",
da962468 316 "", "", "", "", "", "", "", "",
cc17453a
EZ		 317 };
318 if (reg_nr < 0)
319 return NULL;
320 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
321 return NULL;
322 return register_names[reg_nr];
323}
324
fa88f677 325static const char *
d93859e2 326sh_sh4_register_name (struct gdbarch *gdbarch, int reg_nr)
53116e27 327{
617daa0e 328 static char *register_names[] = {
a38d2a54 329 /* general registers 0-15 */
617daa0e
CV		 330 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
331 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
a38d2a54 332 /* 16 - 22 */
617daa0e 333 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
a38d2a54 334 /* 23, 24 */
53116e27 335 "fpul", "fpscr",
a38d2a54 336 /* floating point registers 25 - 40 */
617daa0e
CV		 337 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
338 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
a38d2a54 339 /* 41, 42 */
617daa0e 340 "ssr", "spc",
a38d2a54 341 /* bank 0 43 - 50 */
53116e27 342 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
a38d2a54 343 /* bank 1 51 - 58 */
53116e27 344 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
da962468 345 "", "", "", "", "", "", "", "",
c378eb4e 346 /* pseudo bank register. */
da962468 347 "",
a38d2a54 348 /* double precision (pseudo) 59 - 66 */
617daa0e 349 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
a38d2a54 350 /* vectors (pseudo) 67 - 70 */
617daa0e 351 "fv0", "fv4", "fv8", "fv12",
a38d2a54
EZ		 352 /* FIXME: missing XF 71 - 86 */
353 /* FIXME: missing XD 87 - 94 */
53116e27
EZ		 354 };
355 if (reg_nr < 0)
356 return NULL;
357 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
358 return NULL;
359 return register_names[reg_nr];
360}
361
474e5826 362static const char *
d93859e2 363sh_sh4_nofpu_register_name (struct gdbarch *gdbarch, int reg_nr)
474e5826
CV		 364{
365 static char *register_names[] = {
366 /* general registers 0-15 */
367 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
368 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
369 /* 16 - 22 */
370 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
371 /* 23, 24 */
372 "", "",
373 /* floating point registers 25 - 40 -- not for nofpu target */
374 "", "", "", "", "", "", "", "",
375 "", "", "", "", "", "", "", "",
376 /* 41, 42 */
377 "ssr", "spc",
378 /* bank 0 43 - 50 */
379 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
380 /* bank 1 51 - 58 */
381 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
da962468 382 "", "", "", "", "", "", "", "",
c378eb4e 383 /* pseudo bank register. */
da962468 384 "",
474e5826
CV		 385 /* double precision (pseudo) 59 - 66 -- not for nofpu target */
386 "", "", "", "", "", "", "", "",
387 /* vectors (pseudo) 67 - 70 -- not for nofpu target */
388 "", "", "", "",
389 };
390 if (reg_nr < 0)
391 return NULL;
392 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
393 return NULL;
394 return register_names[reg_nr];
395}
396
397static const char *
d93859e2 398sh_sh4al_dsp_register_name (struct gdbarch *gdbarch, int reg_nr)
474e5826
CV		 399{
400 static char *register_names[] = {
401 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
402 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
403 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
404 "", "dsr",
405 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
406 "y0", "y1", "", "", "", "", "", "mod",
407 "ssr", "spc",
408 "rs", "re", "", "", "", "", "", "",
026a72f8
CV		 409 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
410 "", "", "", "", "", "", "", "",
da962468 411 "", "", "", "", "", "", "", "",
474e5826
CV		 412 };
413 if (reg_nr < 0)
414 return NULL;
415 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
416 return NULL;
417 return register_names[reg_nr];
418}
419
3117ed25 420static const unsigned char *
67d57894 421sh_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr)
cc17453a 422{
c378eb4e 423 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes. */
617daa0e
CV		 424 static unsigned char breakpoint[] = { 0xc3, 0xc3 };
425
bac718a6
UW		 426 /* For remote stub targets, trapa #20 is used. */
427 if (strcmp (target_shortname, "remote") == 0)
428 {
429 static unsigned char big_remote_breakpoint[] = { 0xc3, 0x20 };
430 static unsigned char little_remote_breakpoint[] = { 0x20, 0xc3 };
431
67d57894 432 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
bac718a6
UW		 433 {
434 *lenptr = sizeof (big_remote_breakpoint);
435 return big_remote_breakpoint;
436 }
437 else
438 {
439 *lenptr = sizeof (little_remote_breakpoint);
440 return little_remote_breakpoint;
441 }
442 }
443
cc17453a
EZ		 444 *lenptr = sizeof (breakpoint);
445 return breakpoint;
446}
c906108c
SS		 447
448/* Prologue looks like
1c0159e0
CV		 449 mov.l r14,@-r15
450 sts.l pr,@-r15
451 mov.l <regs>,@-r15
452 sub <room_for_loca_vars>,r15
453 mov r15,r14
8db62801 454
c378eb4e 455 Actually it can be more complicated than this but that's it, basically. */
c906108c 456
1c0159e0
CV		 457#define GET_SOURCE_REG(x) (((x) >> 4) & 0xf)
458#define GET_TARGET_REG(x) (((x) >> 8) & 0xf)
459
5f883edd
FF		 460/* JSR @Rm 0100mmmm00001011 */
461#define IS_JSR(x) (((x) & 0xf0ff) == 0x400b)
462
8db62801
EZ		 463/* STS.L PR,@-r15 0100111100100010
464 r15-4-->r15, PR-->(r15) */
c906108c 465#define IS_STS(x) ((x) == 0x4f22)
8db62801 466
03131d99
CV		 467/* STS.L MACL,@-r15 0100111100010010
468 r15-4-->r15, MACL-->(r15) */
469#define IS_MACL_STS(x) ((x) == 0x4f12)
470
8db62801
EZ		 471/* MOV.L Rm,@-r15 00101111mmmm0110
472 r15-4-->r15, Rm-->(R15) */
c906108c 473#define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
8db62801 474
8db62801
EZ		 475/* MOV r15,r14 0110111011110011
476 r15-->r14 */
c906108c 477#define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
8db62801
EZ		 478
479/* ADD #imm,r15 01111111iiiiiiii
480 r15+imm-->r15 */
1c0159e0 481#define IS_ADD_IMM_SP(x) (((x) & 0xff00) == 0x7f00)
8db62801 482
c906108c
SS		 483#define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
484#define IS_SHLL_R3(x) ((x) == 0x4300)
8db62801
EZ		 485
486/* ADD r3,r15 0011111100111100
487 r15+r3-->r15 */
c906108c 488#define IS_ADD_R3SP(x) ((x) == 0x3f3c)
8db62801
EZ		 489
490/* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
8db62801 491 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
8db62801 492 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
f2ea0907 493/* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to
c378eb4e 494 make this entirely clear. */
1c0159e0
CV		 495/* #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) */
496#define IS_FPUSH(x) (((x) & 0xff0f) == 0xff0b)
497
498/* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 4 <= m <= 7 */
499#define IS_MOV_ARG_TO_REG(x) \
500 (((x) & 0xf00f) == 0x6003 && \
501 ((x) & 0x00f0) >= 0x0040 && \
502 ((x) & 0x00f0) <= 0x0070)
503/* MOV.L Rm,@Rn 0010nnnnmmmm0010 n = 14, 4 <= m <= 7 */
504#define IS_MOV_ARG_TO_IND_R14(x) \
505 (((x) & 0xff0f) == 0x2e02 && \
506 ((x) & 0x00f0) >= 0x0040 && \
507 ((x) & 0x00f0) <= 0x0070)
508/* MOV.L Rm,@(disp*4,Rn) 00011110mmmmdddd n = 14, 4 <= m <= 7 */
509#define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \
510 (((x) & 0xff00) == 0x1e00 && \
511 ((x) & 0x00f0) >= 0x0040 && \
512 ((x) & 0x00f0) <= 0x0070)
513
514/* MOV.W @(disp*2,PC),Rn 1001nnnndddddddd */
515#define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000)
516/* MOV.L @(disp*4,PC),Rn 1101nnnndddddddd */
517#define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000)
03131d99
CV		 518/* MOVI20 #imm20,Rn 0000nnnniiii0000 */
519#define IS_MOVI20(x) (((x) & 0xf00f) == 0x0000)
1c0159e0
CV		 520/* SUB Rn,R15 00111111nnnn1000 */
521#define IS_SUB_REG_FROM_SP(x) (((x) & 0xff0f) == 0x3f08)
8db62801 522
1c0159e0 523#define FPSCR_SZ (1 << 20)
cc17453a 524
c378eb4e 525/* The following instructions are used for epilogue testing. */
1c0159e0
CV		 526#define IS_RESTORE_FP(x) ((x) == 0x6ef6)
527#define IS_RTS(x) ((x) == 0x000b)
528#define IS_LDS(x) ((x) == 0x4f26)
03131d99 529#define IS_MACL_LDS(x) ((x) == 0x4f16)
1c0159e0
CV		 530#define IS_MOV_FP_SP(x) ((x) == 0x6fe3)
531#define IS_ADD_REG_TO_FP(x) (((x) & 0xff0f) == 0x3e0c)
532#define IS_ADD_IMM_FP(x) (((x) & 0xff00) == 0x7e00)
cc17453a 533
cc17453a 534static CORE_ADDR
e17a4113
UW		 535sh_analyze_prologue (struct gdbarch *gdbarch,
536 CORE_ADDR pc, CORE_ADDR current_pc,
d2ca4222 537 struct sh_frame_cache *cache, ULONGEST fpscr)
617daa0e 538{
e17a4113 539 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1c0159e0
CV		 540 ULONGEST inst;
541 CORE_ADDR opc;
542 int offset;
543 int sav_offset = 0;
c906108c 544 int r3_val = 0;
1c0159e0 545 int reg, sav_reg = -1;
cc17453a 546
1c0159e0
CV		 547 if (pc >= current_pc)
548 return current_pc;
cc17453a 549
1c0159e0 550 cache->uses_fp = 0;
cc17453a
EZ		 551 for (opc = pc + (2 * 28); pc < opc; pc += 2)
552 {
e17a4113 553 inst = read_memory_unsigned_integer (pc, 2, byte_order);
c378eb4e 554 /* See where the registers will be saved to. */
f2ea0907 555 if (IS_PUSH (inst))
cc17453a 556 {
1c0159e0
CV		 557 cache->saved_regs[GET_SOURCE_REG (inst)] = cache->sp_offset;
558 cache->sp_offset += 4;
cc17453a 559 }
f2ea0907 560 else if (IS_STS (inst))
cc17453a 561 {
1c0159e0
CV		 562 cache->saved_regs[PR_REGNUM] = cache->sp_offset;
563 cache->sp_offset += 4;
cc17453a 564 }
03131d99
CV		 565 else if (IS_MACL_STS (inst))
566 {
567 cache->saved_regs[MACL_REGNUM] = cache->sp_offset;
568 cache->sp_offset += 4;
569 }
f2ea0907 570 else if (IS_MOV_R3 (inst))
cc17453a 571 {
f2ea0907 572 r3_val = ((inst & 0xff) ^ 0x80) - 0x80;
cc17453a 573 }
f2ea0907 574 else if (IS_SHLL_R3 (inst))
cc17453a
EZ		 575 {
576 r3_val <<= 1;
577 }
f2ea0907 578 else if (IS_ADD_R3SP (inst))
cc17453a 579 {
1c0159e0 580 cache->sp_offset += -r3_val;
cc17453a 581 }
f2ea0907 582 else if (IS_ADD_IMM_SP (inst))
cc17453a 583 {
1c0159e0
CV		 584 offset = ((inst & 0xff) ^ 0x80) - 0x80;
585 cache->sp_offset -= offset;
c906108c 586 }
1c0159e0 587 else if (IS_MOVW_PCREL_TO_REG (inst))
617daa0e 588 {
1c0159e0
CV		 589 if (sav_reg < 0)
590 {
591 reg = GET_TARGET_REG (inst);
592 if (reg < 14)
593 {
594 sav_reg = reg;
a2b4a96c 595 offset = (inst & 0xff) << 1;
1c0159e0 596 sav_offset =
e17a4113 597 read_memory_integer ((pc + 4) + offset, 2, byte_order);
1c0159e0
CV		 598 }
599 }
c906108c 600 }
1c0159e0 601 else if (IS_MOVL_PCREL_TO_REG (inst))
617daa0e 602 {
1c0159e0
CV		 603 if (sav_reg < 0)
604 {
a2b4a96c 605 reg = GET_TARGET_REG (inst);
1c0159e0
CV		 606 if (reg < 14)
607 {
608 sav_reg = reg;
a2b4a96c 609 offset = (inst & 0xff) << 2;
1c0159e0 610 sav_offset =
e17a4113
UW		 611 read_memory_integer (((pc & 0xfffffffc) + 4) + offset,
612 4, byte_order);
1c0159e0
CV		 613 }
614 }
c906108c 615 }
03131d99
CV		 616 else if (IS_MOVI20 (inst))
617 {
618 if (sav_reg < 0)
619 {
620 reg = GET_TARGET_REG (inst);
621 if (reg < 14)
622 {
623 sav_reg = reg;
624 sav_offset = GET_SOURCE_REG (inst) << 16;
c378eb4e 625 /* MOVI20 is a 32 bit instruction! */
03131d99 626 pc += 2;
e17a4113
UW		 627 sav_offset
628 |= read_memory_unsigned_integer (pc, 2, byte_order);
03131d99
CV		 629 /* Now sav_offset contains an unsigned 20 bit value.
630 It must still get sign extended. */
631 if (sav_offset & 0x00080000)
632 sav_offset |= 0xfff00000;
633 }
634 }
635 }
1c0159e0 636 else if (IS_SUB_REG_FROM_SP (inst))
617daa0e 637 {
1c0159e0
CV		 638 reg = GET_SOURCE_REG (inst);
639 if (sav_reg > 0 && reg == sav_reg)
640 {
641 sav_reg = -1;
642 }
643 cache->sp_offset += sav_offset;
c906108c 644 }
f2ea0907 645 else if (IS_FPUSH (inst))
c906108c 646 {
d2ca4222 647 if (fpscr & FPSCR_SZ)
c906108c 648 {
1c0159e0 649 cache->sp_offset += 8;
c906108c
SS		 650 }
651 else
652 {
1c0159e0 653 cache->sp_offset += 4;
c906108c
SS		 654 }
655 }
f2ea0907 656 else if (IS_MOV_SP_FP (inst))
617daa0e 657 {
960ccd7d 658 cache->uses_fp = 1;
1c0159e0
CV		 659 /* At this point, only allow argument register moves to other
660 registers or argument register moves to @(X,fp) which are
661 moving the register arguments onto the stack area allocated
662 by a former add somenumber to SP call. Don't allow moving
c378eb4e 663 to an fp indirect address above fp + cache->sp_offset. */
1c0159e0
CV		 664 pc += 2;
665 for (opc = pc + 12; pc < opc; pc += 2)
666 {
e17a4113 667 inst = read_memory_integer (pc, 2, byte_order);
1c0159e0 668 if (IS_MOV_ARG_TO_IND_R14 (inst))
617daa0e 669 {
1c0159e0
CV		 670 reg = GET_SOURCE_REG (inst);
671 if (cache->sp_offset > 0)
617daa0e 672 cache->saved_regs[reg] = cache->sp_offset;
1c0159e0
CV		 673 }
674 else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst))
617daa0e 675 {
1c0159e0
CV		 676 reg = GET_SOURCE_REG (inst);
677 offset = (inst & 0xf) * 4;
678 if (cache->sp_offset > offset)
679 cache->saved_regs[reg] = cache->sp_offset - offset;
680 }
681 else if (IS_MOV_ARG_TO_REG (inst))
617daa0e 682 continue;
1c0159e0
CV		 683 else
684 break;
685 }
686 break;
687 }
5f883edd
FF		 688 else if (IS_JSR (inst))
689 {
690 /* We have found a jsr that has been scheduled into the prologue.
691 If we continue the scan and return a pc someplace after this,
692 then setting a breakpoint on this function will cause it to
693 appear to be called after the function it is calling via the
694 jsr, which will be very confusing. Most likely the next
695 instruction is going to be IS_MOV_SP_FP in the delay slot. If
c378eb4e 696 so, note that before returning the current pc. */
e17a4113 697 inst = read_memory_integer (pc + 2, 2, byte_order);
5f883edd
FF		 698 if (IS_MOV_SP_FP (inst))
699 cache->uses_fp = 1;
700 break;
701 }
c378eb4e
MS		 702#if 0 /* This used to just stop when it found an instruction
703 that was not considered part of the prologue. Now,
704 we just keep going looking for likely
705 instructions. */
c906108c
SS		 706 else
707 break;
2bfa91ee 708#endif
c906108c
SS		 709 }
710
1c0159e0
CV		 711 return pc;
712}
c906108c 713
c378eb4e 714/* Skip any prologue before the guts of a function. */
c906108c 715
c378eb4e
MS		 716/* Skip the prologue using the debug information. If this fails we'll
717 fall back on the 'guess' method below. */
1c0159e0
CV		 718static CORE_ADDR
719after_prologue (CORE_ADDR pc)
720{
721 struct symtab_and_line sal;
722 CORE_ADDR func_addr, func_end;
c906108c 723
1c0159e0
CV		 724 /* If we can not find the symbol in the partial symbol table, then
725 there is no hope we can determine the function's start address
726 with this code. */
727 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
728 return 0;
c906108c 729
1c0159e0
CV		 730 /* Get the line associated with FUNC_ADDR. */
731 sal = find_pc_line (func_addr, 0);
732
733 /* There are only two cases to consider. First, the end of the source line
734 is within the function bounds. In that case we return the end of the
735 source line. Second is the end of the source line extends beyond the
736 bounds of the current function. We need to use the slow code to
737 examine instructions in that case. */
738 if (sal.end < func_end)
739 return sal.end;
740 else
741 return 0;
c906108c
SS		 742}
743
1c0159e0 744static CORE_ADDR
6093d2eb 745sh_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
c906108c 746{
1c0159e0
CV		 747 CORE_ADDR pc;
748 struct sh_frame_cache cache;
749
750 /* See if we can determine the end of the prologue via the symbol table.
751 If so, then return either PC, or the PC after the prologue, whichever
752 is greater. */
753 pc = after_prologue (start_pc);
cc17453a 754
1c0159e0 755 /* If after_prologue returned a useful address, then use it. Else
c378eb4e 756 fall back on the instruction skipping code. */
1c0159e0
CV		 757 if (pc)
758 return max (pc, start_pc);
c906108c 759
1c0159e0 760 cache.sp_offset = -4;
e17a4113 761 pc = sh_analyze_prologue (gdbarch, start_pc, (CORE_ADDR) -1, &cache, 0);
1c0159e0
CV		 762 if (!cache.uses_fp)
763 return start_pc;
c906108c 764
1c0159e0
CV		 765 return pc;
766}
767
2e952408 768/* The ABI says:
9a5cef92
EZ		 769
770 Aggregate types not bigger than 8 bytes that have the same size and
771 alignment as one of the integer scalar types are returned in the
772 same registers as the integer type they match.
773
774 For example, a 2-byte aligned structure with size 2 bytes has the
775 same size and alignment as a short int, and will be returned in R0.
776 A 4-byte aligned structure with size 8 bytes has the same size and
777 alignment as a long long int, and will be returned in R0 and R1.
778
779 When an aggregate type is returned in R0 and R1, R0 contains the
780 first four bytes of the aggregate, and R1 contains the
c378eb4e 781 remainder. If the size of the aggregate type is not a multiple of 4
9a5cef92 782 bytes, the aggregate is tail-padded up to a multiple of 4
c378eb4e 783 bytes. The value of the padding is undefined. For little-endian
9a5cef92
EZ		 784 targets the padding will appear at the most significant end of the
785 last element, for big-endian targets the padding appears at the
786 least significant end of the last element.
787
c378eb4e 788 All other aggregate types are returned by address. The caller
9a5cef92 789 function passes the address of an area large enough to hold the
c378eb4e 790 aggregate value in R2. The called function stores the result in
7fe958be 791 this location.
9a5cef92
EZ		 792
793 To reiterate, structs smaller than 8 bytes could also be returned
794 in memory, if they don't pass the "same size and alignment as an
795 integer type" rule.
796
797 For example, in
798
799 struct s { char c[3]; } wibble;
800 struct s foo(void) { return wibble; }
801
802 the return value from foo() will be in memory, not
803 in R0, because there is no 3-byte integer type.
804
7fe958be
EZ		 805 Similarly, in
806
807 struct s { char c[2]; } wibble;
808 struct s foo(void) { return wibble; }
809
810 because a struct containing two chars has alignment 1, that matches
811 type char, but size 2, that matches type short. There's no integer
812 type that has alignment 1 and size 2, so the struct is returned in
c378eb4e 813 memory. */
9a5cef92 814
1c0159e0 815static int
c055b101 816sh_use_struct_convention (int renesas_abi, struct type *type)
1c0159e0
CV		 817{
818 int len = TYPE_LENGTH (type);
819 int nelem = TYPE_NFIELDS (type);
3f997a97 820
c055b101
CV		 821 /* The Renesas ABI returns aggregate types always on stack. */
822 if (renesas_abi && (TYPE_CODE (type) == TYPE_CODE_STRUCT
823 || TYPE_CODE (type) == TYPE_CODE_UNION))
824 return 1;
825
3f997a97
CV		 826 /* Non-power of 2 length types and types bigger than 8 bytes (which don't
827 fit in two registers anyway) use struct convention. */
828 if (len != 1 && len != 2 && len != 4 && len != 8)
829 return 1;
830
831 /* Scalar types and aggregate types with exactly one field are aligned
832 by definition. They are returned in registers. */
833 if (nelem <= 1)
834 return 0;
835
836 /* If the first field in the aggregate has the same length as the entire
837 aggregate type, the type is returned in registers. */
838 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == len)
839 return 0;
840
841 /* If the size of the aggregate is 8 bytes and the first field is
842 of size 4 bytes its alignment is equal to long long's alignment,
843 so it's returned in registers. */
844 if (len == 8 && TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == 4)
845 return 0;
846
847 /* Otherwise use struct convention. */
848 return 1;
283150cd
EZ		 849}
850
c055b101
CV		 851static int
852sh_use_struct_convention_nofpu (int renesas_abi, struct type *type)
853{
854 /* The Renesas ABI returns long longs/doubles etc. always on stack. */
855 if (renesas_abi && TYPE_NFIELDS (type) == 0 && TYPE_LENGTH (type) >= 8)
856 return 1;
857 return sh_use_struct_convention (renesas_abi, type);
858}
859
19f59343
MS		 860static CORE_ADDR
861sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
862{
863 return sp & ~3;
864}
865
55ff77ac 866/* Function: push_dummy_call (formerly push_arguments)
c906108c
SS		 867 Setup the function arguments for calling a function in the inferior.
868
85a453d5 869 On the Renesas SH architecture, there are four registers (R4 to R7)
c906108c
SS		 870 which are dedicated for passing function arguments. Up to the first
871 four arguments (depending on size) may go into these registers.
872 The rest go on the stack.
873
6df2bf50
MS		 874 MVS: Except on SH variants that have floating point registers.
875 In that case, float and double arguments are passed in the same
876 manner, but using FP registers instead of GP registers.
877
c906108c
SS		 878 Arguments that are smaller than 4 bytes will still take up a whole
879 register or a whole 32-bit word on the stack, and will be
880 right-justified in the register or the stack word. This includes
881 chars, shorts, and small aggregate types.
882
883 Arguments that are larger than 4 bytes may be split between two or
884 more registers. If there are not enough registers free, an argument
885 may be passed partly in a register (or registers), and partly on the
c378eb4e 886 stack. This includes doubles, long longs, and larger aggregates.
c906108c
SS		 887 As far as I know, there is no upper limit to the size of aggregates
888 that will be passed in this way; in other words, the convention of
889 passing a pointer to a large aggregate instead of a copy is not used.
890
6df2bf50 891 MVS: The above appears to be true for the SH variants that do not
55ff77ac 892 have an FPU, however those that have an FPU appear to copy the
6df2bf50
MS		 893 aggregate argument onto the stack (and not place it in registers)
894 if it is larger than 16 bytes (four GP registers).
895
c906108c
SS		 896 An exceptional case exists for struct arguments (and possibly other
897 aggregates such as arrays) if the size is larger than 4 bytes but
898 not a multiple of 4 bytes. In this case the argument is never split
899 between the registers and the stack, but instead is copied in its
900 entirety onto the stack, AND also copied into as many registers as
901 there is room for. In other words, space in registers permitting,
902 two copies of the same argument are passed in. As far as I can tell,
903 only the one on the stack is used, although that may be a function
904 of the level of compiler optimization. I suspect this is a compiler
905 bug. Arguments of these odd sizes are left-justified within the
906 word (as opposed to arguments smaller than 4 bytes, which are
907 right-justified).
c5aa993b 908
c906108c
SS		 909 If the function is to return an aggregate type such as a struct, it
910 is either returned in the normal return value register R0 (if its
911 size is no greater than one byte), or else the caller must allocate
912 space into which the callee will copy the return value (if the size
913 is greater than one byte). In this case, a pointer to the return
914 value location is passed into the callee in register R2, which does
915 not displace any of the other arguments passed in via registers R4
c378eb4e 916 to R7. */
c906108c 917
c378eb4e 918/* Helper function to justify value in register according to endianess. */
e5e33cd9 919static char *
d93859e2 920sh_justify_value_in_reg (struct gdbarch *gdbarch, struct value *val, int len)
e5e33cd9
CV		 921{
922 static char valbuf[4];
923
617daa0e 924 memset (valbuf, 0, sizeof (valbuf));
e5e33cd9
CV		 925 if (len < 4)
926 {
c378eb4e 927 /* value gets right-justified in the register or stack word. */
d93859e2 928 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
0fd88904 929 memcpy (valbuf + (4 - len), (char *) value_contents (val), len);
e5e33cd9 930 else
0fd88904 931 memcpy (valbuf, (char *) value_contents (val), len);
e5e33cd9
CV		 932 return valbuf;
933 }
0fd88904 934 return (char *) value_contents (val);
617daa0e 935}
e5e33cd9 936
c378eb4e 937/* Helper function to eval number of bytes to allocate on stack. */
e5e33cd9
CV		 938static CORE_ADDR
939sh_stack_allocsize (int nargs, struct value **args)
940{
941 int stack_alloc = 0;
942 while (nargs-- > 0)
4991999e 943 stack_alloc += ((TYPE_LENGTH (value_type (args[nargs])) + 3) & ~3);
e5e33cd9
CV		 944 return stack_alloc;
945}
946
947/* Helper functions for getting the float arguments right. Registers usage
948 depends on the ABI and the endianess. The comments should enlighten how
c378eb4e 949 it's intended to work. */
e5e33cd9 950
c378eb4e 951/* This array stores which of the float arg registers are already in use. */
e5e33cd9
CV		 952static int flt_argreg_array[FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM + 1];
953
c378eb4e 954/* This function just resets the above array to "no reg used so far". */
e5e33cd9
CV		 955static void
956sh_init_flt_argreg (void)
957{
958 memset (flt_argreg_array, 0, sizeof flt_argreg_array);
959}
960
961/* This function returns the next register to use for float arg passing.
962 It returns either a valid value between FLOAT_ARG0_REGNUM and
963 FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns
964 FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available.
965
966 Note that register number 0 in flt_argreg_array corresponds with the
967 real float register fr4. In contrast to FLOAT_ARG0_REGNUM (value is
968 29) the parity of the register number is preserved, which is important
c378eb4e 969 for the double register passing test (see the "argreg & 1" test below). */
e5e33cd9 970static int
c055b101 971sh_next_flt_argreg (struct gdbarch *gdbarch, int len, struct type *func_type)
e5e33cd9
CV		 972{
973 int argreg;
974
c378eb4e 975 /* First search for the next free register. */
617daa0e
CV		 976 for (argreg = 0; argreg <= FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM;
977 ++argreg)
e5e33cd9
CV		 978 if (!flt_argreg_array[argreg])
979 break;
980
c378eb4e 981 /* No register left? */
e5e33cd9
CV		 982 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
983 return FLOAT_ARGLAST_REGNUM + 1;
984
985 if (len == 8)
986 {
c378eb4e 987 /* Doubles are always starting in a even register number. */
e5e33cd9 988 if (argreg & 1)
617daa0e 989 {
c055b101
CV		 990 /* In gcc ABI, the skipped register is lost for further argument
991 passing now. Not so in Renesas ABI. */
992 if (!sh_is_renesas_calling_convention (func_type))
993 flt_argreg_array[argreg] = 1;
e5e33cd9
CV		 994
995 ++argreg;
996
c378eb4e 997 /* No register left? */
e5e33cd9
CV		 998 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
999 return FLOAT_ARGLAST_REGNUM + 1;
1000 }
c378eb4e 1001 /* Also mark the next register as used. */
e5e33cd9
CV		 1002 flt_argreg_array[argreg + 1] = 1;
1003 }
c055b101
CV		 1004 else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE
1005 && !sh_is_renesas_calling_convention (func_type))
e5e33cd9 1006 {
c378eb4e 1007 /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */
e5e33cd9
CV		 1008 if (!flt_argreg_array[argreg + 1])
1009 ++argreg;
1010 }
1011 flt_argreg_array[argreg] = 1;
1012 return FLOAT_ARG0_REGNUM + argreg;
1013}
1014
afce3d2a
CV		 1015/* Helper function which figures out, if a type is treated like a float type.
1016
2e952408 1017 The FPU ABIs have a special way how to treat types as float types.
afce3d2a
CV		 1018 Structures with exactly one member, which is of type float or double, are
1019 treated exactly as the base types float or double:
1020
1021 struct sf {
1022 float f;
1023 };
1024
1025 struct sd {
1026 double d;
1027 };
1028
1029 are handled the same way as just
1030
1031 float f;
1032
1033 double d;
1034
1035 As a result, arguments of these struct types are pushed into floating point
1036 registers exactly as floats or doubles, using the same decision algorithm.
1037
1038 The same is valid if these types are used as function return types. The
1039 above structs are returned in fr0 resp. fr0,fr1 instead of in r0, r0,r1
1040 or even using struct convention as it is for other structs. */
1041
1042static int
1043sh_treat_as_flt_p (struct type *type)
1044{
1045 int len = TYPE_LENGTH (type);
1046
1047 /* Ordinary float types are obviously treated as float. */
1048 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1049 return 1;
1050 /* Otherwise non-struct types are not treated as float. */
1051 if (TYPE_CODE (type) != TYPE_CODE_STRUCT)
1052 return 0;
1053 /* Otherwise structs with more than one memeber are not treated as float. */
1054 if (TYPE_NFIELDS (type) != 1)
1055 return 0;
1056 /* Otherwise if the type of that member is float, the whole type is
1057 treated as float. */
1058 if (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) == TYPE_CODE_FLT)
1059 return 1;
1060 /* Otherwise it's not treated as float. */
1061 return 0;
1062}
1063
cc17453a 1064static CORE_ADDR
617daa0e 1065sh_push_dummy_call_fpu (struct gdbarch *gdbarch,
7d9b040b 1066 struct value *function,
617daa0e 1067 struct regcache *regcache,
6df2bf50 1068 CORE_ADDR bp_addr, int nargs,
617daa0e 1069 struct value **args,
6df2bf50
MS		 1070 CORE_ADDR sp, int struct_return,
1071 CORE_ADDR struct_addr)
1072{
e17a4113 1073 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
e5e33cd9
CV		 1074 int stack_offset = 0;
1075 int argreg = ARG0_REGNUM;
8748518b 1076 int flt_argreg = 0;
6df2bf50 1077 int argnum;
c055b101 1078 struct type *func_type = value_type (function);
6df2bf50
MS		 1079 struct type *type;
1080 CORE_ADDR regval;
1081 char *val;
8748518b 1082 int len, reg_size = 0;
afce3d2a
CV		 1083 int pass_on_stack = 0;
1084 int treat_as_flt;
c055b101
CV		 1085 int last_reg_arg = INT_MAX;
1086
1087 /* The Renesas ABI expects all varargs arguments, plus the last
1088 non-vararg argument to be on the stack, no matter how many
1089 registers have been used so far. */
1090 if (sh_is_renesas_calling_convention (func_type)
876cecd0 1091 && TYPE_VARARGS (func_type))
c055b101 1092 last_reg_arg = TYPE_NFIELDS (func_type) - 2;
6df2bf50 1093
c378eb4e 1094 /* First force sp to a 4-byte alignment. */
6df2bf50
MS		 1095 sp = sh_frame_align (gdbarch, sp);
1096
c378eb4e 1097 /* Make room on stack for args. */
e5e33cd9
CV		 1098 sp -= sh_stack_allocsize (nargs, args);
1099
c378eb4e 1100 /* Initialize float argument mechanism. */
e5e33cd9 1101 sh_init_flt_argreg ();
6df2bf50
MS		 1102
1103 /* Now load as many as possible of the first arguments into
1104 registers, and push the rest onto the stack. There are 16 bytes
1105 in four registers available. Loop thru args from first to last. */
e5e33cd9 1106 for (argnum = 0; argnum < nargs; argnum++)
6df2bf50 1107 {
4991999e 1108 type = value_type (args[argnum]);
6df2bf50 1109 len = TYPE_LENGTH (type);
d93859e2 1110 val = sh_justify_value_in_reg (gdbarch, args[argnum], len);
e5e33cd9
CV		 1111
1112 /* Some decisions have to be made how various types are handled.
c378eb4e 1113 This also differs in different ABIs. */
e5e33cd9 1114 pass_on_stack = 0;
e5e33cd9 1115
c378eb4e 1116 /* Find out the next register to use for a floating point value. */
afce3d2a
CV		 1117 treat_as_flt = sh_treat_as_flt_p (type);
1118 if (treat_as_flt)
c055b101
CV		 1119 flt_argreg = sh_next_flt_argreg (gdbarch, len, func_type);
1120 /* In Renesas ABI, long longs and aggregate types are always passed
1121 on stack. */
1122 else if (sh_is_renesas_calling_convention (func_type)
1123 && ((TYPE_CODE (type) == TYPE_CODE_INT && len == 8)
1124 || TYPE_CODE (type) == TYPE_CODE_STRUCT
1125 || TYPE_CODE (type) == TYPE_CODE_UNION))
1126 pass_on_stack = 1;
afce3d2a
CV		 1127 /* In contrast to non-FPU CPUs, arguments are never split between
1128 registers and stack. If an argument doesn't fit in the remaining
1129 registers it's always pushed entirely on the stack. */
1130 else if (len > ((ARGLAST_REGNUM - argreg + 1) * 4))
1131 pass_on_stack = 1;
48db5a3c 1132
6df2bf50
MS		 1133 while (len > 0)
1134 {
afce3d2a
CV		 1135 if ((treat_as_flt && flt_argreg > FLOAT_ARGLAST_REGNUM)
1136 || (!treat_as_flt && (argreg > ARGLAST_REGNUM
c055b101
CV		 1137 || pass_on_stack))
1138 || argnum > last_reg_arg)
617daa0e 1139 {
c378eb4e 1140 /* The data goes entirely on the stack, 4-byte aligned. */
e5e33cd9
CV		 1141 reg_size = (len + 3) & ~3;
1142 write_memory (sp + stack_offset, val, reg_size);
1143 stack_offset += reg_size;
6df2bf50 1144 }
afce3d2a 1145 else if (treat_as_flt && flt_argreg <= FLOAT_ARGLAST_REGNUM)
6df2bf50 1146 {
e5e33cd9
CV		 1147 /* Argument goes in a float argument register. */
1148 reg_size = register_size (gdbarch, flt_argreg);
e17a4113 1149 regval = extract_unsigned_integer (val, reg_size, byte_order);
2e952408
CV		 1150 /* In little endian mode, float types taking two registers
1151 (doubles on sh4, long doubles on sh2e, sh3e and sh4) must
1152 be stored swapped in the argument registers. The below
1153 code first writes the first 32 bits in the next but one
1154 register, increments the val and len values accordingly
1155 and then proceeds as normal by writing the second 32 bits
c378eb4e 1156 into the next register. */
b47193f7 1157 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE
2e952408
CV		 1158 && TYPE_LENGTH (type) == 2 * reg_size)
1159 {
1160 regcache_cooked_write_unsigned (regcache, flt_argreg + 1,
1161 regval);
1162 val += reg_size;
1163 len -= reg_size;
c378eb4e
MS		 1164 regval = extract_unsigned_integer (val, reg_size,
1165 byte_order);
2e952408 1166 }
6df2bf50
MS		 1167 regcache_cooked_write_unsigned (regcache, flt_argreg++, regval);
1168 }
afce3d2a 1169 else if (!treat_as_flt && argreg <= ARGLAST_REGNUM)
e5e33cd9 1170 {
6df2bf50 1171 /* there's room in a register */
e5e33cd9 1172 reg_size = register_size (gdbarch, argreg);
e17a4113 1173 regval = extract_unsigned_integer (val, reg_size, byte_order);
6df2bf50
MS		 1174 regcache_cooked_write_unsigned (regcache, argreg++, regval);
1175 }
c378eb4e
MS		 1176 /* Store the value one register at a time or in one step on
1177 stack. */
e5e33cd9
CV		 1178 len -= reg_size;
1179 val += reg_size;
6df2bf50
MS		 1180 }
1181 }
1182
c055b101
CV		 1183 if (struct_return)
1184 {
1185 if (sh_is_renesas_calling_convention (func_type))
1186 /* If the function uses the Renesas ABI, subtract another 4 bytes from
1187 the stack and store the struct return address there. */
e17a4113 1188 write_memory_unsigned_integer (sp -= 4, 4, byte_order, struct_addr);
c055b101
CV		 1189 else
1190 /* Using the gcc ABI, the "struct return pointer" pseudo-argument has
1191 its own dedicated register. */
1192 regcache_cooked_write_unsigned (regcache,
1193 STRUCT_RETURN_REGNUM, struct_addr);
1194 }
1195
c378eb4e 1196 /* Store return address. */
55ff77ac 1197 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
6df2bf50
MS		 1198
1199 /* Update stack pointer. */
3e8c568d 1200 regcache_cooked_write_unsigned (regcache,
b47193f7 1201 gdbarch_sp_regnum (gdbarch), sp);
6df2bf50
MS		 1202
1203 return sp;
1204}
1205
1206static CORE_ADDR
617daa0e 1207sh_push_dummy_call_nofpu (struct gdbarch *gdbarch,
7d9b040b 1208 struct value *function,
617daa0e
CV		 1209 struct regcache *regcache,
1210 CORE_ADDR bp_addr,
1211 int nargs, struct value **args,
1212 CORE_ADDR sp, int struct_return,
6df2bf50 1213 CORE_ADDR struct_addr)
c906108c 1214{
e17a4113 1215 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
e5e33cd9
CV		 1216 int stack_offset = 0;
1217 int argreg = ARG0_REGNUM;
c906108c 1218 int argnum;
c055b101 1219 struct type *func_type = value_type (function);
c906108c
SS		 1220 struct type *type;
1221 CORE_ADDR regval;
1222 char *val;
c055b101
CV		 1223 int len, reg_size = 0;
1224 int pass_on_stack = 0;
1225 int last_reg_arg = INT_MAX;
1226
1227 /* The Renesas ABI expects all varargs arguments, plus the last
1228 non-vararg argument to be on the stack, no matter how many
1229 registers have been used so far. */
1230 if (sh_is_renesas_calling_convention (func_type)
876cecd0 1231 && TYPE_VARARGS (func_type))
c055b101 1232 last_reg_arg = TYPE_NFIELDS (func_type) - 2;
c906108c 1233
c378eb4e 1234 /* First force sp to a 4-byte alignment. */
19f59343 1235 sp = sh_frame_align (gdbarch, sp);
c906108c 1236
c378eb4e 1237 /* Make room on stack for args. */
e5e33cd9 1238 sp -= sh_stack_allocsize (nargs, args);
c906108c 1239
c906108c
SS		 1240 /* Now load as many as possible of the first arguments into
1241 registers, and push the rest onto the stack. There are 16 bytes
1242 in four registers available. Loop thru args from first to last. */
e5e33cd9 1243 for (argnum = 0; argnum < nargs; argnum++)
617daa0e 1244 {
4991999e 1245 type = value_type (args[argnum]);
c5aa993b 1246 len = TYPE_LENGTH (type);
d93859e2 1247 val = sh_justify_value_in_reg (gdbarch, args[argnum], len);
c906108c 1248
c055b101 1249 /* Some decisions have to be made how various types are handled.
c378eb4e 1250 This also differs in different ABIs. */
c055b101
CV		 1251 pass_on_stack = 0;
1252 /* Renesas ABI pushes doubles and long longs entirely on stack.
1253 Same goes for aggregate types. */
1254 if (sh_is_renesas_calling_convention (func_type)
1255 && ((TYPE_CODE (type) == TYPE_CODE_INT && len >= 8)
1256 || (TYPE_CODE (type) == TYPE_CODE_FLT && len >= 8)
1257 || TYPE_CODE (type) == TYPE_CODE_STRUCT
1258 || TYPE_CODE (type) == TYPE_CODE_UNION))
1259 pass_on_stack = 1;
c906108c
SS		 1260 while (len > 0)
1261 {
c055b101
CV		 1262 if (argreg > ARGLAST_REGNUM || pass_on_stack
1263 || argnum > last_reg_arg)
617daa0e 1264 {
e5e33cd9 1265 /* The remainder of the data goes entirely on the stack,
c378eb4e 1266 4-byte aligned. */
e5e33cd9
CV		 1267 reg_size = (len + 3) & ~3;
1268 write_memory (sp + stack_offset, val, reg_size);
617daa0e 1269 stack_offset += reg_size;
c906108c 1270 }
e5e33cd9 1271 else if (argreg <= ARGLAST_REGNUM)
617daa0e 1272 {
c378eb4e 1273 /* There's room in a register. */
e5e33cd9 1274 reg_size = register_size (gdbarch, argreg);
e17a4113 1275 regval = extract_unsigned_integer (val, reg_size, byte_order);
48db5a3c 1276 regcache_cooked_write_unsigned (regcache, argreg++, regval);
c906108c 1277 }
e5e33cd9
CV		 1278 /* Store the value reg_size bytes at a time. This means that things
1279 larger than reg_size bytes may go partly in registers and partly
c906108c 1280 on the stack. */
e5e33cd9
CV		 1281 len -= reg_size;
1282 val += reg_size;
c906108c
SS		 1283 }
1284 }
48db5a3c 1285
c055b101
CV		 1286 if (struct_return)
1287 {
1288 if (sh_is_renesas_calling_convention (func_type))
1289 /* If the function uses the Renesas ABI, subtract another 4 bytes from
1290 the stack and store the struct return address there. */
e17a4113 1291 write_memory_unsigned_integer (sp -= 4, 4, byte_order, struct_addr);
c055b101
CV		 1292 else
1293 /* Using the gcc ABI, the "struct return pointer" pseudo-argument has
1294 its own dedicated register. */
1295 regcache_cooked_write_unsigned (regcache,
1296 STRUCT_RETURN_REGNUM, struct_addr);
1297 }
1298
c378eb4e 1299 /* Store return address. */
55ff77ac 1300 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
48db5a3c
CV		 1301
1302 /* Update stack pointer. */
3e8c568d 1303 regcache_cooked_write_unsigned (regcache,
b47193f7 1304 gdbarch_sp_regnum (gdbarch), sp);
48db5a3c 1305
c906108c
SS		 1306 return sp;
1307}
1308
cc17453a
EZ		 1309/* Find a function's return value in the appropriate registers (in
1310 regbuf), and copy it into valbuf. Extract from an array REGBUF
1311 containing the (raw) register state a function return value of type
1312 TYPE, and copy that, in virtual format, into VALBUF. */
1313static void
3ffc5b9b
CV		 1314sh_extract_return_value_nofpu (struct type *type, struct regcache *regcache,
1315 void *valbuf)
c906108c 1316{
e17a4113
UW		 1317 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1318 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
cc17453a 1319 int len = TYPE_LENGTH (type);
3116c80a
EZ		 1320 int return_register = R0_REGNUM;
1321 int offset;
617daa0e 1322
cc17453a 1323 if (len <= 4)
3116c80a 1324 {
48db5a3c
CV		 1325 ULONGEST c;
1326
1327 regcache_cooked_read_unsigned (regcache, R0_REGNUM, &c);
e17a4113 1328 store_unsigned_integer (valbuf, len, byte_order, c);
3116c80a 1329 }
48db5a3c 1330 else if (len == 8)
3116c80a 1331 {
48db5a3c
CV		 1332 int i, regnum = R0_REGNUM;
1333 for (i = 0; i < len; i += 4)
617daa0e 1334 regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
3116c80a
EZ		 1335 }
1336 else
8a3fe4f8 1337 error (_("bad size for return value"));
3116c80a
EZ		 1338}
1339
1340static void
3ffc5b9b
CV		 1341sh_extract_return_value_fpu (struct type *type, struct regcache *regcache,
1342 void *valbuf)
3116c80a 1343{
d93859e2 1344 struct gdbarch *gdbarch = get_regcache_arch (regcache);
afce3d2a 1345 if (sh_treat_as_flt_p (type))
3116c80a 1346 {
48db5a3c 1347 int len = TYPE_LENGTH (type);
d93859e2 1348 int i, regnum = gdbarch_fp0_regnum (gdbarch);
48db5a3c 1349 for (i = 0; i < len; i += 4)
d93859e2 1350 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
c378eb4e
MS		 1351 regcache_raw_read (regcache, regnum++,
1352 (char *) valbuf + len - 4 - i);
2e952408
CV		 1353 else
1354 regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
3116c80a 1355 }
cc17453a 1356 else
3ffc5b9b 1357 sh_extract_return_value_nofpu (type, regcache, valbuf);
cc17453a 1358}
c906108c 1359
cc17453a
EZ		 1360/* Write into appropriate registers a function return value
1361 of type TYPE, given in virtual format.
1362 If the architecture is sh4 or sh3e, store a function's return value
1363 in the R0 general register or in the FP0 floating point register,
c378eb4e
MS		 1364 depending on the type of the return value. In all the other cases
1365 the result is stored in r0, left-justified. */
cc17453a 1366static void
3ffc5b9b
CV		 1367sh_store_return_value_nofpu (struct type *type, struct regcache *regcache,
1368 const void *valbuf)
cc17453a 1369{
e17a4113
UW		 1370 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1371 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
48db5a3c
CV		 1372 ULONGEST val;
1373 int len = TYPE_LENGTH (type);
d19b71be 1374
48db5a3c 1375 if (len <= 4)
d19b71be 1376 {
e17a4113 1377 val = extract_unsigned_integer (valbuf, len, byte_order);
48db5a3c 1378 regcache_cooked_write_unsigned (regcache, R0_REGNUM, val);
d19b71be
MS		 1379 }
1380 else
48db5a3c
CV		 1381 {
1382 int i, regnum = R0_REGNUM;
1383 for (i = 0; i < len; i += 4)
617daa0e 1384 regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
48db5a3c 1385 }
cc17453a 1386}
c906108c 1387
cc17453a 1388static void
3ffc5b9b
CV		 1389sh_store_return_value_fpu (struct type *type, struct regcache *regcache,
1390 const void *valbuf)
cc17453a 1391{
d93859e2 1392 struct gdbarch *gdbarch = get_regcache_arch (regcache);
afce3d2a 1393 if (sh_treat_as_flt_p (type))
48db5a3c
CV		 1394 {
1395 int len = TYPE_LENGTH (type);
d93859e2 1396 int i, regnum = gdbarch_fp0_regnum (gdbarch);
48db5a3c 1397 for (i = 0; i < len; i += 4)
d93859e2 1398 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
c8a3b559
CV		 1399 regcache_raw_write (regcache, regnum++,
1400 (char *) valbuf + len - 4 - i);
1401 else
1402 regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
48db5a3c 1403 }
cc17453a 1404 else
3ffc5b9b 1405 sh_store_return_value_nofpu (type, regcache, valbuf);
c906108c
SS		 1406}
1407
c0409442 1408static enum return_value_convention
c055b101
CV		 1409sh_return_value_nofpu (struct gdbarch *gdbarch, struct type *func_type,
1410 struct type *type, struct regcache *regcache,
18cf8b5b 1411 gdb_byte *readbuf, const gdb_byte *writebuf)
c0409442 1412{
c055b101
CV		 1413 if (sh_use_struct_convention_nofpu (
1414 sh_is_renesas_calling_convention (func_type), type))
c0409442
CV		 1415 return RETURN_VALUE_STRUCT_CONVENTION;
1416 if (writebuf)
3ffc5b9b 1417 sh_store_return_value_nofpu (type, regcache, writebuf);
c0409442 1418 else if (readbuf)
3ffc5b9b 1419 sh_extract_return_value_nofpu (type, regcache, readbuf);
c0409442
CV		 1420 return RETURN_VALUE_REGISTER_CONVENTION;
1421}
1422
1423static enum return_value_convention
c055b101
CV		 1424sh_return_value_fpu (struct gdbarch *gdbarch, struct type *func_type,
1425 struct type *type, struct regcache *regcache,
18cf8b5b 1426 gdb_byte *readbuf, const gdb_byte *writebuf)
c0409442 1427{
c055b101
CV		 1428 if (sh_use_struct_convention (
1429 sh_is_renesas_calling_convention (func_type), type))
c0409442
CV		 1430 return RETURN_VALUE_STRUCT_CONVENTION;
1431 if (writebuf)
3ffc5b9b 1432 sh_store_return_value_fpu (type, regcache, writebuf);
c0409442 1433 else if (readbuf)
3ffc5b9b 1434 sh_extract_return_value_fpu (type, regcache, readbuf);
c0409442
CV		 1435 return RETURN_VALUE_REGISTER_CONVENTION;
1436}
1437
c378eb4e 1438/* Print the registers in a form similar to the E7000. */
c906108c
SS		 1439
1440static void
c458d6db 1441sh_generic_show_regs (struct frame_info *frame)
c906108c 1442{
c458d6db
UW		 1443 printf_filtered
1444 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 1445 phex (get_frame_register_unsigned (frame,
1446 gdbarch_pc_regnum
1447 (get_frame_arch (frame))), 4),
c458d6db
UW		 1448 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1449 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1450 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
cc17453a 1451
c458d6db
UW		 1452 printf_filtered
1453 (" GBR %08lx VBR %08lx MACL %08lx\n",
1454 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1455 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1456 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
cc17453a 1457
617daa0e 1458 printf_filtered
a6b0a3f3 1459 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
c458d6db
UW		 1460 (long) get_frame_register_unsigned (frame, 0),
1461 (long) get_frame_register_unsigned (frame, 1),
1462 (long) get_frame_register_unsigned (frame, 2),
1463 (long) get_frame_register_unsigned (frame, 3),
1464 (long) get_frame_register_unsigned (frame, 4),
1465 (long) get_frame_register_unsigned (frame, 5),
1466 (long) get_frame_register_unsigned (frame, 6),
1467 (long) get_frame_register_unsigned (frame, 7));
1468 printf_filtered
1469 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1470 (long) get_frame_register_unsigned (frame, 8),
1471 (long) get_frame_register_unsigned (frame, 9),
1472 (long) get_frame_register_unsigned (frame, 10),
1473 (long) get_frame_register_unsigned (frame, 11),
1474 (long) get_frame_register_unsigned (frame, 12),
1475 (long) get_frame_register_unsigned (frame, 13),
1476 (long) get_frame_register_unsigned (frame, 14),
1477 (long) get_frame_register_unsigned (frame, 15));
cc17453a 1478}
c906108c 1479
cc17453a 1480static void
c458d6db 1481sh3_show_regs (struct frame_info *frame)
cc17453a 1482{
c458d6db
UW		 1483 printf_filtered
1484 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 1485 phex (get_frame_register_unsigned (frame,
1486 gdbarch_pc_regnum
1487 (get_frame_arch (frame))), 4),
c458d6db
UW		 1488 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1489 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1490 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1491
1492 printf_filtered
1493 (" GBR %08lx VBR %08lx MACL %08lx\n",
1494 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1495 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1496 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1497 printf_filtered
1498 (" SSR %08lx SPC %08lx\n",
1499 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1500 (long) get_frame_register_unsigned (frame, SPC_REGNUM));
c906108c 1501
617daa0e 1502 printf_filtered
a6b0a3f3 1503 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
c458d6db
UW		 1504 (long) get_frame_register_unsigned (frame, 0),
1505 (long) get_frame_register_unsigned (frame, 1),
1506 (long) get_frame_register_unsigned (frame, 2),
1507 (long) get_frame_register_unsigned (frame, 3),
1508 (long) get_frame_register_unsigned (frame, 4),
1509 (long) get_frame_register_unsigned (frame, 5),
1510 (long) get_frame_register_unsigned (frame, 6),
1511 (long) get_frame_register_unsigned (frame, 7));
1512 printf_filtered
1513 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1514 (long) get_frame_register_unsigned (frame, 8),
1515 (long) get_frame_register_unsigned (frame, 9),
1516 (long) get_frame_register_unsigned (frame, 10),
1517 (long) get_frame_register_unsigned (frame, 11),
1518 (long) get_frame_register_unsigned (frame, 12),
1519 (long) get_frame_register_unsigned (frame, 13),
1520 (long) get_frame_register_unsigned (frame, 14),
1521 (long) get_frame_register_unsigned (frame, 15));
c906108c
SS		 1522}
1523
2d188dd3 1524static void
c458d6db 1525sh2e_show_regs (struct frame_info *frame)
2d188dd3 1526{
b47193f7 1527 struct gdbarch *gdbarch = get_frame_arch (frame);
c458d6db
UW		 1528 printf_filtered
1529 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 1530 phex (get_frame_register_unsigned (frame,
1531 gdbarch_pc_regnum (gdbarch)), 4),
c458d6db
UW		 1532 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1533 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1534 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1535
1536 printf_filtered
1537 (" GBR %08lx VBR %08lx MACL %08lx\n",
1538 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1539 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1540 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1541 printf_filtered
1542 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1543 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1544 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1545 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1546 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
617daa0e
CV		 1547
1548 printf_filtered
a6b0a3f3 1549 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
c458d6db
UW		 1550 (long) get_frame_register_unsigned (frame, 0),
1551 (long) get_frame_register_unsigned (frame, 1),
1552 (long) get_frame_register_unsigned (frame, 2),
1553 (long) get_frame_register_unsigned (frame, 3),
1554 (long) get_frame_register_unsigned (frame, 4),
1555 (long) get_frame_register_unsigned (frame, 5),
1556 (long) get_frame_register_unsigned (frame, 6),
1557 (long) get_frame_register_unsigned (frame, 7));
1558 printf_filtered
1559 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1560 (long) get_frame_register_unsigned (frame, 8),
1561 (long) get_frame_register_unsigned (frame, 9),
1562 (long) get_frame_register_unsigned (frame, 10),
1563 (long) get_frame_register_unsigned (frame, 11),
1564 (long) get_frame_register_unsigned (frame, 12),
1565 (long) get_frame_register_unsigned (frame, 13),
1566 (long) get_frame_register_unsigned (frame, 14),
1567 (long) get_frame_register_unsigned (frame, 15));
1568
1569 printf_filtered
1570 ("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
3e8c568d 1571 (long) get_frame_register_unsigned
b47193f7 1572 (frame, gdbarch_fp0_regnum (gdbarch) + 0),
3e8c568d 1573 (long) get_frame_register_unsigned
b47193f7 1574 (frame, gdbarch_fp0_regnum (gdbarch) + 1),
3e8c568d 1575 (long) get_frame_register_unsigned
b47193f7 1576 (frame, gdbarch_fp0_regnum (gdbarch) + 2),
3e8c568d 1577 (long) get_frame_register_unsigned
b47193f7 1578 (frame, gdbarch_fp0_regnum (gdbarch) + 3),
3e8c568d 1579 (long) get_frame_register_unsigned
b47193f7 1580 (frame, gdbarch_fp0_regnum (gdbarch) + 4),
3e8c568d 1581 (long) get_frame_register_unsigned
b47193f7 1582 (frame, gdbarch_fp0_regnum (gdbarch) + 5),
3e8c568d 1583 (long) get_frame_register_unsigned
b47193f7 1584 (frame, gdbarch_fp0_regnum (gdbarch) + 6),
3e8c568d 1585 (long) get_frame_register_unsigned
b47193f7 1586 (frame, gdbarch_fp0_regnum (gdbarch) + 7));
c458d6db
UW		 1587 printf_filtered
1588 ("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
3e8c568d 1589 (long) get_frame_register_unsigned
b47193f7 1590 (frame, gdbarch_fp0_regnum (gdbarch) + 8),
3e8c568d 1591 (long) get_frame_register_unsigned
b47193f7 1592 (frame, gdbarch_fp0_regnum (gdbarch) + 9),
3e8c568d 1593 (long) get_frame_register_unsigned
b47193f7 1594 (frame, gdbarch_fp0_regnum (gdbarch) + 10),
3e8c568d 1595 (long) get_frame_register_unsigned
b47193f7 1596 (frame, gdbarch_fp0_regnum (gdbarch) + 11),
3e8c568d 1597 (long) get_frame_register_unsigned
b47193f7 1598 (frame, gdbarch_fp0_regnum (gdbarch) + 12),
3e8c568d 1599 (long) get_frame_register_unsigned
b47193f7 1600 (frame, gdbarch_fp0_regnum (gdbarch) + 13),
3e8c568d 1601 (long) get_frame_register_unsigned
b47193f7 1602 (frame, gdbarch_fp0_regnum (gdbarch) + 14),
3e8c568d 1603 (long) get_frame_register_unsigned
b47193f7 1604 (frame, gdbarch_fp0_regnum (gdbarch) + 15));
2d188dd3
NC		 1605}
1606
da962468 1607static void
c458d6db 1608sh2a_show_regs (struct frame_info *frame)
da962468 1609{
b47193f7 1610 struct gdbarch *gdbarch = get_frame_arch (frame);
c458d6db
UW		 1611 int pr = get_frame_register_unsigned (frame, FPSCR_REGNUM) & 0x80000;
1612
1613 printf_filtered
1614 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 1615 phex (get_frame_register_unsigned (frame,
1616 gdbarch_pc_regnum (gdbarch)), 4),
c458d6db
UW		 1617 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1618 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1619 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1620
1621 printf_filtered
1622 (" GBR %08lx VBR %08lx TBR %08lx MACL %08lx\n",
1623 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1624 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1625 (long) get_frame_register_unsigned (frame, TBR_REGNUM),
1626 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1627 printf_filtered
1628 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1629 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1630 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1631 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1632 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1633
1634 printf_filtered
1635 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1636 (long) get_frame_register_unsigned (frame, 0),
1637 (long) get_frame_register_unsigned (frame, 1),
1638 (long) get_frame_register_unsigned (frame, 2),
1639 (long) get_frame_register_unsigned (frame, 3),
1640 (long) get_frame_register_unsigned (frame, 4),
1641 (long) get_frame_register_unsigned (frame, 5),
1642 (long) get_frame_register_unsigned (frame, 6),
1643 (long) get_frame_register_unsigned (frame, 7));
1644 printf_filtered
1645 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1646 (long) get_frame_register_unsigned (frame, 8),
1647 (long) get_frame_register_unsigned (frame, 9),
1648 (long) get_frame_register_unsigned (frame, 10),
1649 (long) get_frame_register_unsigned (frame, 11),
1650 (long) get_frame_register_unsigned (frame, 12),
1651 (long) get_frame_register_unsigned (frame, 13),
1652 (long) get_frame_register_unsigned (frame, 14),
1653 (long) get_frame_register_unsigned (frame, 15));
1654
1655 printf_filtered
1656 (pr ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1657 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
3e8c568d 1658 (long) get_frame_register_unsigned
b47193f7 1659 (frame, gdbarch_fp0_regnum (gdbarch) + 0),
3e8c568d 1660 (long) get_frame_register_unsigned
b47193f7 1661 (frame, gdbarch_fp0_regnum (gdbarch) + 1),
3e8c568d 1662 (long) get_frame_register_unsigned
b47193f7 1663 (frame, gdbarch_fp0_regnum (gdbarch) + 2),
3e8c568d 1664 (long) get_frame_register_unsigned
b47193f7 1665 (frame, gdbarch_fp0_regnum (gdbarch) + 3),
3e8c568d 1666 (long) get_frame_register_unsigned
b47193f7 1667 (frame, gdbarch_fp0_regnum (gdbarch) + 4),
3e8c568d 1668 (long) get_frame_register_unsigned
b47193f7 1669 (frame, gdbarch_fp0_regnum (gdbarch) + 5),
3e8c568d 1670 (long) get_frame_register_unsigned
b47193f7 1671 (frame, gdbarch_fp0_regnum (gdbarch) + 6),
3e8c568d 1672 (long) get_frame_register_unsigned
b47193f7 1673 (frame, gdbarch_fp0_regnum (gdbarch) + 7));
c458d6db
UW		 1674 printf_filtered
1675 (pr ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1676 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
3e8c568d 1677 (long) get_frame_register_unsigned
b47193f7 1678 (frame, gdbarch_fp0_regnum (gdbarch) + 8),
3e8c568d 1679 (long) get_frame_register_unsigned
b47193f7 1680 (frame, gdbarch_fp0_regnum (gdbarch) + 9),
3e8c568d 1681 (long) get_frame_register_unsigned
b47193f7 1682 (frame, gdbarch_fp0_regnum (gdbarch) + 10),
3e8c568d 1683 (long) get_frame_register_unsigned
b47193f7 1684 (frame, gdbarch_fp0_regnum (gdbarch) + 11),
3e8c568d 1685 (long) get_frame_register_unsigned
b47193f7 1686 (frame, gdbarch_fp0_regnum (gdbarch) + 12),
3e8c568d 1687 (long) get_frame_register_unsigned
b47193f7 1688 (frame, gdbarch_fp0_regnum (gdbarch) + 13),
3e8c568d 1689 (long) get_frame_register_unsigned
b47193f7 1690 (frame, gdbarch_fp0_regnum (gdbarch) + 14),
3e8c568d 1691 (long) get_frame_register_unsigned
b47193f7 1692 (frame, gdbarch_fp0_regnum (gdbarch) + 15));
c458d6db
UW		 1693 printf_filtered
1694 ("BANK=%-3d\n", (int) get_frame_register_unsigned (frame, BANK_REGNUM));
1695 printf_filtered
1696 ("R0b-R7b %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1697 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 0),
1698 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 1),
1699 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 2),
1700 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 3),
1701 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 4),
1702 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 5),
1703 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 6),
1704 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 7));
1705 printf_filtered
1706 ("R8b-R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1707 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 8),
1708 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 9),
1709 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 10),
1710 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 11),
1711 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 12),
1712 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 13),
1713 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 14));
1714 printf_filtered
1715 ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n",
1716 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 15),
1717 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 16),
1718 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 17),
1719 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 18),
1720 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 19));
da962468
CV		 1721}
1722
1723static void
c458d6db 1724sh2a_nofpu_show_regs (struct frame_info *frame)
da962468 1725{
c458d6db
UW		 1726 int pr = get_frame_register_unsigned (frame, FPSCR_REGNUM) & 0x80000;
1727
1728 printf_filtered
1729 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 1730 phex (get_frame_register_unsigned (frame,
1731 gdbarch_pc_regnum
1732 (get_frame_arch (frame))), 4),
c458d6db
UW		 1733 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1734 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1735 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1736
1737 printf_filtered
1738 (" GBR %08lx VBR %08lx TBR %08lx MACL %08lx\n",
1739 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1740 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1741 (long) get_frame_register_unsigned (frame, TBR_REGNUM),
1742 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1743 printf_filtered
1744 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1745 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1746 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1747 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1748 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1749
1750 printf_filtered
1751 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1752 (long) get_frame_register_unsigned (frame, 0),
1753 (long) get_frame_register_unsigned (frame, 1),
1754 (long) get_frame_register_unsigned (frame, 2),
1755 (long) get_frame_register_unsigned (frame, 3),
1756 (long) get_frame_register_unsigned (frame, 4),
1757 (long) get_frame_register_unsigned (frame, 5),
1758 (long) get_frame_register_unsigned (frame, 6),
1759 (long) get_frame_register_unsigned (frame, 7));
1760 printf_filtered
1761 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1762 (long) get_frame_register_unsigned (frame, 8),
1763 (long) get_frame_register_unsigned (frame, 9),
1764 (long) get_frame_register_unsigned (frame, 10),
1765 (long) get_frame_register_unsigned (frame, 11),
1766 (long) get_frame_register_unsigned (frame, 12),
1767 (long) get_frame_register_unsigned (frame, 13),
1768 (long) get_frame_register_unsigned (frame, 14),
1769 (long) get_frame_register_unsigned (frame, 15));
1770
1771 printf_filtered
1772 ("BANK=%-3d\n", (int) get_frame_register_unsigned (frame, BANK_REGNUM));
1773 printf_filtered
1774 ("R0b-R7b %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1775 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 0),
1776 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 1),
1777 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 2),
1778 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 3),
1779 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 4),
1780 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 5),
1781 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 6),
1782 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 7));
1783 printf_filtered
1784 ("R8b-R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1785 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 8),
1786 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 9),
1787 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 10),
1788 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 11),
1789 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 12),
1790 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 13),
1791 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 14));
1792 printf_filtered
1793 ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n",
1794 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 15),
1795 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 16),
1796 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 17),
1797 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 18),
1798 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 19));
da962468
CV		 1799}
1800
cc17453a 1801static void
c458d6db 1802sh3e_show_regs (struct frame_info *frame)
cc17453a 1803{
b47193f7 1804 struct gdbarch *gdbarch = get_frame_arch (frame);
c458d6db
UW		 1805 printf_filtered
1806 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 1807 phex (get_frame_register_unsigned (frame,
1808 gdbarch_pc_regnum (gdbarch)), 4),
c458d6db
UW		 1809 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1810 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1811 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1812
1813 printf_filtered
1814 (" GBR %08lx VBR %08lx MACL %08lx\n",
1815 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1816 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1817 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1818 printf_filtered
1819 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1820 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1821 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1822 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1823 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
c906108c 1824
617daa0e 1825 printf_filtered
a6b0a3f3 1826 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
c458d6db
UW		 1827 (long) get_frame_register_unsigned (frame, 0),
1828 (long) get_frame_register_unsigned (frame, 1),
1829 (long) get_frame_register_unsigned (frame, 2),
1830 (long) get_frame_register_unsigned (frame, 3),
1831 (long) get_frame_register_unsigned (frame, 4),
1832 (long) get_frame_register_unsigned (frame, 5),
1833 (long) get_frame_register_unsigned (frame, 6),
1834 (long) get_frame_register_unsigned (frame, 7));
1835 printf_filtered
1836 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1837 (long) get_frame_register_unsigned (frame, 8),
1838 (long) get_frame_register_unsigned (frame, 9),
1839 (long) get_frame_register_unsigned (frame, 10),
1840 (long) get_frame_register_unsigned (frame, 11),
1841 (long) get_frame_register_unsigned (frame, 12),
1842 (long) get_frame_register_unsigned (frame, 13),
1843 (long) get_frame_register_unsigned (frame, 14),
1844 (long) get_frame_register_unsigned (frame, 15));
1845
1846 printf_filtered
1847 ("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
3e8c568d 1848 (long) get_frame_register_unsigned
b47193f7 1849 (frame, gdbarch_fp0_regnum (gdbarch) + 0),
3e8c568d 1850 (long) get_frame_register_unsigned
b47193f7 1851 (frame, gdbarch_fp0_regnum (gdbarch) + 1),
3e8c568d 1852 (long) get_frame_register_unsigned
b47193f7 1853 (frame, gdbarch_fp0_regnum (gdbarch) + 2),
3e8c568d 1854 (long) get_frame_register_unsigned
b47193f7 1855 (frame, gdbarch_fp0_regnum (gdbarch) + 3),
3e8c568d 1856 (long) get_frame_register_unsigned
b47193f7 1857 (frame, gdbarch_fp0_regnum (gdbarch) + 4),
3e8c568d 1858 (long) get_frame_register_unsigned
b47193f7 1859 (frame, gdbarch_fp0_regnum (gdbarch) + 5),
3e8c568d 1860 (long) get_frame_register_unsigned
b47193f7 1861 (frame, gdbarch_fp0_regnum (gdbarch) + 6),
3e8c568d 1862 (long) get_frame_register_unsigned
b47193f7 1863 (frame, gdbarch_fp0_regnum (gdbarch) + 7));
c458d6db
UW		 1864 printf_filtered
1865 ("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
3e8c568d 1866 (long) get_frame_register_unsigned
b47193f7 1867 (frame, gdbarch_fp0_regnum (gdbarch) + 8),
3e8c568d 1868 (long) get_frame_register_unsigned
b47193f7 1869 (frame, gdbarch_fp0_regnum (gdbarch) + 9),
3e8c568d 1870 (long) get_frame_register_unsigned
b47193f7 1871 (frame, gdbarch_fp0_regnum (gdbarch) + 10),
3e8c568d 1872 (long) get_frame_register_unsigned
b47193f7 1873 (frame, gdbarch_fp0_regnum (gdbarch) + 11),
3e8c568d 1874 (long) get_frame_register_unsigned
b47193f7 1875 (frame, gdbarch_fp0_regnum (gdbarch) + 12),
3e8c568d 1876 (long) get_frame_register_unsigned
b47193f7 1877 (frame, gdbarch_fp0_regnum (gdbarch) + 13),
3e8c568d 1878 (long) get_frame_register_unsigned
b47193f7 1879 (frame, gdbarch_fp0_regnum (gdbarch) + 14),
3e8c568d 1880 (long) get_frame_register_unsigned
b47193f7 1881 (frame, gdbarch_fp0_regnum (gdbarch) + 15));
cc17453a
EZ		 1882}
1883
1884static void
c458d6db 1885sh3_dsp_show_regs (struct frame_info *frame)
c906108c 1886{
c458d6db
UW		 1887 printf_filtered
1888 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 1889 phex (get_frame_register_unsigned (frame,
1890 gdbarch_pc_regnum
1891 (get_frame_arch (frame))), 4),
c458d6db
UW		 1892 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1893 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1894 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
c906108c 1895
c458d6db
UW		 1896 printf_filtered
1897 (" GBR %08lx VBR %08lx MACL %08lx\n",
1898 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1899 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1900 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
cc17453a 1901
c458d6db
UW		 1902 printf_filtered
1903 (" SSR %08lx SPC %08lx DSR %08lx\n",
1904 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1905 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1906 (long) get_frame_register_unsigned (frame, DSR_REGNUM));
617daa0e
CV		 1907
1908 printf_filtered
a6b0a3f3 1909 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
c458d6db
UW		 1910 (long) get_frame_register_unsigned (frame, 0),
1911 (long) get_frame_register_unsigned (frame, 1),
1912 (long) get_frame_register_unsigned (frame, 2),
1913 (long) get_frame_register_unsigned (frame, 3),
1914 (long) get_frame_register_unsigned (frame, 4),
1915 (long) get_frame_register_unsigned (frame, 5),
1916 (long) get_frame_register_unsigned (frame, 6),
1917 (long) get_frame_register_unsigned (frame, 7));
1918 printf_filtered
1919 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1920 (long) get_frame_register_unsigned (frame, 8),
1921 (long) get_frame_register_unsigned (frame, 9),
1922 (long) get_frame_register_unsigned (frame, 10),
1923 (long) get_frame_register_unsigned (frame, 11),
1924 (long) get_frame_register_unsigned (frame, 12),
1925 (long) get_frame_register_unsigned (frame, 13),
1926 (long) get_frame_register_unsigned (frame, 14),
1927 (long) get_frame_register_unsigned (frame, 15));
617daa0e
CV		 1928
1929 printf_filtered
1930 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
c458d6db
UW		 1931 (long) get_frame_register_unsigned (frame, A0G_REGNUM) & 0xff,
1932 (long) get_frame_register_unsigned (frame, A0_REGNUM),
1933 (long) get_frame_register_unsigned (frame, M0_REGNUM),
1934 (long) get_frame_register_unsigned (frame, X0_REGNUM),
1935 (long) get_frame_register_unsigned (frame, Y0_REGNUM),
1936 (long) get_frame_register_unsigned (frame, RS_REGNUM),
1937 (long) get_frame_register_unsigned (frame, MOD_REGNUM));
1938 printf_filtered
1939 ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1940 (long) get_frame_register_unsigned (frame, A1G_REGNUM) & 0xff,
1941 (long) get_frame_register_unsigned (frame, A1_REGNUM),
1942 (long) get_frame_register_unsigned (frame, M1_REGNUM),
1943 (long) get_frame_register_unsigned (frame, X1_REGNUM),
1944 (long) get_frame_register_unsigned (frame, Y1_REGNUM),
1945 (long) get_frame_register_unsigned (frame, RE_REGNUM));
c906108c
SS		 1946}
1947
cc17453a 1948static void
c458d6db 1949sh4_show_regs (struct frame_info *frame)
cc17453a 1950{
b47193f7 1951 struct gdbarch *gdbarch = get_frame_arch (frame);
c458d6db
UW		 1952 int pr = get_frame_register_unsigned (frame, FPSCR_REGNUM) & 0x80000;
1953
1954 printf_filtered
1955 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 1956 phex (get_frame_register_unsigned (frame,
1957 gdbarch_pc_regnum (gdbarch)), 4),
c458d6db
UW		 1958 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1959 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1960 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1961
1962 printf_filtered
1963 (" GBR %08lx VBR %08lx MACL %08lx\n",
1964 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1965 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1966 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1967 printf_filtered
1968 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1969 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1970 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1971 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1972 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1973
1974 printf_filtered
1975 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1976 (long) get_frame_register_unsigned (frame, 0),
1977 (long) get_frame_register_unsigned (frame, 1),
1978 (long) get_frame_register_unsigned (frame, 2),
1979 (long) get_frame_register_unsigned (frame, 3),
1980 (long) get_frame_register_unsigned (frame, 4),
1981 (long) get_frame_register_unsigned (frame, 5),
1982 (long) get_frame_register_unsigned (frame, 6),
1983 (long) get_frame_register_unsigned (frame, 7));
1984 printf_filtered
1985 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1986 (long) get_frame_register_unsigned (frame, 8),
1987 (long) get_frame_register_unsigned (frame, 9),
1988 (long) get_frame_register_unsigned (frame, 10),
1989 (long) get_frame_register_unsigned (frame, 11),
1990 (long) get_frame_register_unsigned (frame, 12),
1991 (long) get_frame_register_unsigned (frame, 13),
1992 (long) get_frame_register_unsigned (frame, 14),
1993 (long) get_frame_register_unsigned (frame, 15));
1994
1995 printf_filtered
1996 (pr ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1997 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
3e8c568d 1998 (long) get_frame_register_unsigned
b47193f7 1999 (frame, gdbarch_fp0_regnum (gdbarch) + 0),
3e8c568d 2000 (long) get_frame_register_unsigned
b47193f7 2001 (frame, gdbarch_fp0_regnum (gdbarch) + 1),
3e8c568d 2002 (long) get_frame_register_unsigned
b47193f7 2003 (frame, gdbarch_fp0_regnum (gdbarch) + 2),
3e8c568d 2004 (long) get_frame_register_unsigned
b47193f7 2005 (frame, gdbarch_fp0_regnum (gdbarch) + 3),
3e8c568d 2006 (long) get_frame_register_unsigned
b47193f7 2007 (frame, gdbarch_fp0_regnum (gdbarch) + 4),
3e8c568d 2008 (long) get_frame_register_unsigned
b47193f7 2009 (frame, gdbarch_fp0_regnum (gdbarch) + 5),
3e8c568d 2010 (long) get_frame_register_unsigned
b47193f7 2011 (frame, gdbarch_fp0_regnum (gdbarch) + 6),
3e8c568d 2012 (long) get_frame_register_unsigned
b47193f7 2013 (frame, gdbarch_fp0_regnum (gdbarch) + 7));
c458d6db
UW		 2014 printf_filtered
2015 (pr ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
2016 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
3e8c568d 2017 (long) get_frame_register_unsigned
b47193f7 2018 (frame, gdbarch_fp0_regnum (gdbarch) + 8),
3e8c568d 2019 (long) get_frame_register_unsigned
b47193f7 2020 (frame, gdbarch_fp0_regnum (gdbarch) + 9),
3e8c568d 2021 (long) get_frame_register_unsigned
b47193f7 2022 (frame, gdbarch_fp0_regnum (gdbarch) + 10),
3e8c568d 2023 (long) get_frame_register_unsigned
b47193f7 2024 (frame, gdbarch_fp0_regnum (gdbarch) + 11),
3e8c568d 2025 (long) get_frame_register_unsigned
b47193f7 2026 (frame, gdbarch_fp0_regnum (gdbarch) + 12),
3e8c568d 2027 (long) get_frame_register_unsigned
b47193f7 2028 (frame, gdbarch_fp0_regnum (gdbarch) + 13),
3e8c568d 2029 (long) get_frame_register_unsigned
b47193f7 2030 (frame, gdbarch_fp0_regnum (gdbarch) + 14),
3e8c568d 2031 (long) get_frame_register_unsigned
b47193f7 2032 (frame, gdbarch_fp0_regnum (gdbarch) + 15));
cc17453a
EZ		 2033}
2034
474e5826 2035static void
c458d6db 2036sh4_nofpu_show_regs (struct frame_info *frame)
474e5826 2037{
c458d6db
UW		 2038 printf_filtered
2039 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 2040 phex (get_frame_register_unsigned (frame,
2041 gdbarch_pc_regnum
2042 (get_frame_arch (frame))), 4),
c458d6db
UW		 2043 (long) get_frame_register_unsigned (frame, SR_REGNUM),
2044 (long) get_frame_register_unsigned (frame, PR_REGNUM),
2045 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
2046
2047 printf_filtered
2048 (" GBR %08lx VBR %08lx MACL %08lx\n",
2049 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
2050 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
2051 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
2052 printf_filtered
2053 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
2054 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
2055 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
2056 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
2057 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
2058
2059 printf_filtered
2060 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2061 (long) get_frame_register_unsigned (frame, 0),
2062 (long) get_frame_register_unsigned (frame, 1),
2063 (long) get_frame_register_unsigned (frame, 2),
2064 (long) get_frame_register_unsigned (frame, 3),
2065 (long) get_frame_register_unsigned (frame, 4),
2066 (long) get_frame_register_unsigned (frame, 5),
2067 (long) get_frame_register_unsigned (frame, 6),
2068 (long) get_frame_register_unsigned (frame, 7));
2069 printf_filtered
2070 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2071 (long) get_frame_register_unsigned (frame, 8),
2072 (long) get_frame_register_unsigned (frame, 9),
2073 (long) get_frame_register_unsigned (frame, 10),
2074 (long) get_frame_register_unsigned (frame, 11),
2075 (long) get_frame_register_unsigned (frame, 12),
2076 (long) get_frame_register_unsigned (frame, 13),
2077 (long) get_frame_register_unsigned (frame, 14),
2078 (long) get_frame_register_unsigned (frame, 15));
474e5826
CV		 2079}
2080
cc17453a 2081static void
c458d6db 2082sh_dsp_show_regs (struct frame_info *frame)
cc17453a 2083{
c458d6db
UW		 2084 printf_filtered
2085 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 2086 phex (get_frame_register_unsigned (frame,
2087 gdbarch_pc_regnum
2088 (get_frame_arch (frame))), 4),
c458d6db
UW		 2089 (long) get_frame_register_unsigned (frame, SR_REGNUM),
2090 (long) get_frame_register_unsigned (frame, PR_REGNUM),
2091 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
a6b0a3f3 2092
c458d6db
UW		 2093 printf_filtered
2094 (" GBR %08lx VBR %08lx DSR %08lx MACL %08lx\n",
2095 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
2096 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
2097 (long) get_frame_register_unsigned (frame, DSR_REGNUM),
2098 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
617daa0e
CV		 2099
2100 printf_filtered
a6b0a3f3 2101 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
c458d6db
UW		 2102 (long) get_frame_register_unsigned (frame, 0),
2103 (long) get_frame_register_unsigned (frame, 1),
2104 (long) get_frame_register_unsigned (frame, 2),
2105 (long) get_frame_register_unsigned (frame, 3),
2106 (long) get_frame_register_unsigned (frame, 4),
2107 (long) get_frame_register_unsigned (frame, 5),
2108 (long) get_frame_register_unsigned (frame, 6),
2109 (long) get_frame_register_unsigned (frame, 7));
2110 printf_filtered
2111 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2112 (long) get_frame_register_unsigned (frame, 8),
2113 (long) get_frame_register_unsigned (frame, 9),
2114 (long) get_frame_register_unsigned (frame, 10),
2115 (long) get_frame_register_unsigned (frame, 11),
2116 (long) get_frame_register_unsigned (frame, 12),
2117 (long) get_frame_register_unsigned (frame, 13),
2118 (long) get_frame_register_unsigned (frame, 14),
2119 (long) get_frame_register_unsigned (frame, 15));
617daa0e
CV		 2120
2121 printf_filtered
2122 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
c458d6db
UW		 2123 (long) get_frame_register_unsigned (frame, A0G_REGNUM) & 0xff,
2124 (long) get_frame_register_unsigned (frame, A0_REGNUM),
2125 (long) get_frame_register_unsigned (frame, M0_REGNUM),
2126 (long) get_frame_register_unsigned (frame, X0_REGNUM),
2127 (long) get_frame_register_unsigned (frame, Y0_REGNUM),
2128 (long) get_frame_register_unsigned (frame, RS_REGNUM),
2129 (long) get_frame_register_unsigned (frame, MOD_REGNUM));
cc17453a 2130 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
c458d6db
UW		 2131 (long) get_frame_register_unsigned (frame, A1G_REGNUM) & 0xff,
2132 (long) get_frame_register_unsigned (frame, A1_REGNUM),
2133 (long) get_frame_register_unsigned (frame, M1_REGNUM),
2134 (long) get_frame_register_unsigned (frame, X1_REGNUM),
2135 (long) get_frame_register_unsigned (frame, Y1_REGNUM),
2136 (long) get_frame_register_unsigned (frame, RE_REGNUM));
cc17453a
EZ		 2137}
2138
a78f21af
AC		 2139static void
2140sh_show_regs_command (char *args, int from_tty)
53116e27
EZ		 2141{
2142 if (sh_show_regs)
c458d6db 2143 (*sh_show_regs) (get_current_frame ());
53116e27
EZ		 2144}
2145
da962468
CV		 2146static struct type *
2147sh_sh2a_register_type (struct gdbarch *gdbarch, int reg_nr)
2148{
b47193f7 2149 if ((reg_nr >= gdbarch_fp0_regnum (gdbarch)
da962468 2150 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
0dfff4cb 2151 return builtin_type (gdbarch)->builtin_float;
da962468 2152 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
0dfff4cb 2153 return builtin_type (gdbarch)->builtin_double;
da962468 2154 else
0dfff4cb 2155 return builtin_type (gdbarch)->builtin_int;
da962468
CV		 2156}
2157
cc17453a
EZ		 2158/* Return the GDB type object for the "standard" data type
2159 of data in register N. */
cc17453a 2160static struct type *
48db5a3c 2161sh_sh3e_register_type (struct gdbarch *gdbarch, int reg_nr)
cc17453a 2162{
b47193f7 2163 if ((reg_nr >= gdbarch_fp0_regnum (gdbarch)
617daa0e 2164 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
0dfff4cb 2165 return builtin_type (gdbarch)->builtin_float;
8db62801 2166 else
0dfff4cb 2167 return builtin_type (gdbarch)->builtin_int;
cc17453a
EZ		 2168}
2169
7f4dbe94 2170static struct type *
0dfff4cb 2171sh_sh4_build_float_register_type (struct gdbarch *gdbarch, int high)
7f4dbe94 2172{
e3506a9f
UW		 2173 return lookup_array_range_type (builtin_type (gdbarch)->builtin_float,
2174 0, high);
7f4dbe94
EZ		 2175}
2176
53116e27 2177static struct type *
48db5a3c 2178sh_sh4_register_type (struct gdbarch *gdbarch, int reg_nr)
53116e27 2179{
b47193f7 2180 if ((reg_nr >= gdbarch_fp0_regnum (gdbarch)
617daa0e 2181 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
0dfff4cb 2182 return builtin_type (gdbarch)->builtin_float;
617daa0e 2183 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
0dfff4cb 2184 return builtin_type (gdbarch)->builtin_double;
617daa0e 2185 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
0dfff4cb 2186 return sh_sh4_build_float_register_type (gdbarch, 3);
53116e27 2187 else
0dfff4cb 2188 return builtin_type (gdbarch)->builtin_int;
53116e27
EZ		 2189}
2190
cc17453a 2191static struct type *
48db5a3c 2192sh_default_register_type (struct gdbarch *gdbarch, int reg_nr)
cc17453a 2193{
0dfff4cb 2194 return builtin_type (gdbarch)->builtin_int;
cc17453a
EZ		 2195}
2196
dda63807
AS		 2197/* Is a register in a reggroup?
2198 The default code in reggroup.c doesn't identify system registers, some
2199 float registers or any of the vector registers.
2200 TODO: sh2a and dsp registers. */
63807e1d 2201static int
dda63807
AS		 2202sh_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2203 struct reggroup *reggroup)
2204{
b47193f7
UW		 2205 if (gdbarch_register_name (gdbarch, regnum) == NULL
2206 || *gdbarch_register_name (gdbarch, regnum) == '\0')
dda63807
AS		 2207 return 0;
2208
2209 if (reggroup == float_reggroup
2210 && (regnum == FPUL_REGNUM
2211 || regnum == FPSCR_REGNUM))
2212 return 1;
2213
2214 if (regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM)
2215 {
2216 if (reggroup == vector_reggroup || reggroup == float_reggroup)
2217 return 1;
2218 if (reggroup == general_reggroup)
2219 return 0;
2220 }
2221
2222 if (regnum == VBR_REGNUM
2223 || regnum == SR_REGNUM
2224 || regnum == FPSCR_REGNUM
2225 || regnum == SSR_REGNUM
2226 || regnum == SPC_REGNUM)
2227 {
2228 if (reggroup == system_reggroup)
2229 return 1;
2230 if (reggroup == general_reggroup)
2231 return 0;
2232 }
2233
2234 /* The default code can cope with any other registers. */
2235 return default_register_reggroup_p (gdbarch, regnum, reggroup);
2236}
2237
fb409745 2238/* On the sh4, the DRi pseudo registers are problematic if the target
c378eb4e 2239 is little endian. When the user writes one of those registers, for
fb409745
EZ		 2240 instance with 'ser var $dr0=1', we want the double to be stored
2241 like this:
2242 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
2243 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2244
2245 This corresponds to little endian byte order & big endian word
2246 order. However if we let gdb write the register w/o conversion, it
2247 will write fr0 and fr1 this way:
2248 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2249 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
2250 because it will consider fr0 and fr1 as a single LE stretch of memory.
2251
2252 To achieve what we want we must force gdb to store things in
2253 floatformat_ieee_double_littlebyte_bigword (which is defined in
2254 include/floatformat.h and libiberty/floatformat.c.
2255
2256 In case the target is big endian, there is no problem, the
2257 raw bytes will look like:
2258 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
2259 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2260
2261 The other pseudo registers (the FVs) also don't pose a problem
c378eb4e 2262 because they are stored as 4 individual FP elements. */
fb409745 2263
7bd872fe 2264static void
b66ba949
CV		 2265sh_register_convert_to_virtual (int regnum, struct type *type,
2266 char *from, char *to)
55ff77ac 2267{
617daa0e 2268 if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
283150cd
EZ		 2269 {
2270 DOUBLEST val;
617daa0e
CV		 2271 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
2272 from, &val);
55ff77ac 2273 store_typed_floating (to, type, val);
283150cd
EZ		 2274 }
2275 else
617daa0e
CV		 2276 error
2277 ("sh_register_convert_to_virtual called with non DR register number");
283150cd
EZ		 2278}
2279
2280static void
b66ba949
CV		 2281sh_register_convert_to_raw (struct type *type, int regnum,
2282 const void *from, void *to)
283150cd 2283{
617daa0e 2284 if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
283150cd 2285 {
48db5a3c 2286 DOUBLEST val = extract_typed_floating (from, type);
617daa0e
CV		 2287 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword,
2288 &val, to);
283150cd
EZ		 2289 }
2290 else
8a3fe4f8 2291 error (_("sh_register_convert_to_raw called with non DR register number"));
283150cd
EZ		 2292}
2293
c378eb4e 2294/* For vectors of 4 floating point registers. */
1c0159e0 2295static int
d93859e2 2296fv_reg_base_num (struct gdbarch *gdbarch, int fv_regnum)
1c0159e0
CV		 2297{
2298 int fp_regnum;
2299
d93859e2 2300 fp_regnum = gdbarch_fp0_regnum (gdbarch)
3e8c568d 2301 + (fv_regnum - FV0_REGNUM) * 4;
1c0159e0
CV		 2302 return fp_regnum;
2303}
2304
c378eb4e 2305/* For double precision floating point registers, i.e 2 fp regs. */
1c0159e0 2306static int
d93859e2 2307dr_reg_base_num (struct gdbarch *gdbarch, int dr_regnum)
1c0159e0
CV		 2308{
2309 int fp_regnum;
2310
d93859e2 2311 fp_regnum = gdbarch_fp0_regnum (gdbarch)
3e8c568d 2312 + (dr_regnum - DR0_REGNUM) * 2;
1c0159e0
CV		 2313 return fp_regnum;
2314}
2315
05d1431c
PA		 2316/* Concatenate PORTIONS contiguous raw registers starting at
2317 BASE_REGNUM into BUFFER. */
2318
2319static enum register_status
2320pseudo_register_read_portions (struct gdbarch *gdbarch,
2321 struct regcache *regcache,
2322 int portions,
2323 int base_regnum, gdb_byte *buffer)
2324{
2325 int portion;
2326
2327 for (portion = 0; portion < portions; portion++)
2328 {
2329 enum register_status status;
2330 gdb_byte *b;
2331
2332 b = buffer + register_size (gdbarch, base_regnum) * portion;
2333 status = regcache_raw_read (regcache, base_regnum + portion, b);
2334 if (status != REG_VALID)
2335 return status;
2336 }
2337
2338 return REG_VALID;
2339}
2340
2341static enum register_status
d8124050 2342sh_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
18cf8b5b 2343 int reg_nr, gdb_byte *buffer)
53116e27 2344{
05d1431c 2345 int base_regnum;
d9d9c31f 2346 char temp_buffer[MAX_REGISTER_SIZE];
05d1431c 2347 enum register_status status;
53116e27 2348
9bed62d7 2349 if (reg_nr == PSEUDO_BANK_REGNUM)
05d1431c
PA		 2350 return regcache_raw_read (regcache, BANK_REGNUM, buffer);
2351 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
7bd872fe 2352 {
d93859e2 2353 base_regnum = dr_reg_base_num (gdbarch, reg_nr);
7bd872fe 2354
c378eb4e 2355 /* Build the value in the provided buffer. */
7bd872fe 2356 /* Read the real regs for which this one is an alias. */
05d1431c
PA		 2357 status = pseudo_register_read_portions (gdbarch, regcache,
2358 2, base_regnum, temp_buffer);
2359 if (status == REG_VALID)
2360 {
2361 /* We must pay attention to the endiannes. */
2362 sh_register_convert_to_virtual (reg_nr,
2363 register_type (gdbarch, reg_nr),
2364 temp_buffer, buffer);
2365 }
2366 return status;
7bd872fe 2367 }
617daa0e 2368 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
53116e27 2369 {
d93859e2 2370 base_regnum = fv_reg_base_num (gdbarch, reg_nr);
7bd872fe
EZ		 2371
2372 /* Read the real regs for which this one is an alias. */
05d1431c
PA		 2373 return pseudo_register_read_portions (gdbarch, regcache,
2374 4, base_regnum, buffer);
53116e27 2375 }
05d1431c
PA		 2376 else
2377 gdb_assert_not_reached ("invalid pseudo register number");
53116e27
EZ		 2378}
2379
a78f21af 2380static void
d8124050 2381sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
18cf8b5b 2382 int reg_nr, const gdb_byte *buffer)
53116e27
EZ		 2383{
2384 int base_regnum, portion;
d9d9c31f 2385 char temp_buffer[MAX_REGISTER_SIZE];
53116e27 2386
9bed62d7
CV		 2387 if (reg_nr == PSEUDO_BANK_REGNUM)
2388 {
2389 /* When the bank register is written to, the whole register bank
2390 is switched and all values in the bank registers must be read
c378eb4e 2391 from the target/sim again. We're just invalidating the regcache
9bed62d7
CV		 2392 so that a re-read happens next time it's necessary. */
2393 int bregnum;
2394
2395 regcache_raw_write (regcache, BANK_REGNUM, buffer);
2396 for (bregnum = R0_BANK0_REGNUM; bregnum < MACLB_REGNUM; ++bregnum)
9c5ea4d9 2397 regcache_invalidate (regcache, bregnum);
9bed62d7
CV		 2398 }
2399 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
53116e27 2400 {
d93859e2 2401 base_regnum = dr_reg_base_num (gdbarch, reg_nr);
53116e27 2402
c378eb4e 2403 /* We must pay attention to the endiannes. */
7b9ee6a8 2404 sh_register_convert_to_raw (register_type (gdbarch, reg_nr),
b66ba949 2405 reg_nr, buffer, temp_buffer);
7bd872fe 2406
53116e27
EZ		 2407 /* Write the real regs for which this one is an alias. */
2408 for (portion = 0; portion < 2; portion++)
617daa0e 2409 regcache_raw_write (regcache, base_regnum + portion,
0818c12a 2410 (temp_buffer
617daa0e
CV		 2411 + register_size (gdbarch,
2412 base_regnum) * portion));
53116e27 2413 }
617daa0e 2414 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
53116e27 2415 {
d93859e2 2416 base_regnum = fv_reg_base_num (gdbarch, reg_nr);
53116e27
EZ		 2417
2418 /* Write the real regs for which this one is an alias. */
2419 for (portion = 0; portion < 4; portion++)
d8124050
AC		 2420 regcache_raw_write (regcache, base_regnum + portion,
2421 ((char *) buffer
617daa0e
CV		 2422 + register_size (gdbarch,
2423 base_regnum) * portion));
53116e27
EZ		 2424 }
2425}
2426
2f14585c 2427static int
e7faf938 2428sh_dsp_register_sim_regno (struct gdbarch *gdbarch, int nr)
2f14585c 2429{
e7faf938
MD		 2430 if (legacy_register_sim_regno (gdbarch, nr) < 0)
2431 return legacy_register_sim_regno (gdbarch, nr);
f2ea0907
CV		 2432 if (nr >= DSR_REGNUM && nr <= Y1_REGNUM)
2433 return nr - DSR_REGNUM + SIM_SH_DSR_REGNUM;
2434 if (nr == MOD_REGNUM)
2f14585c 2435 return SIM_SH_MOD_REGNUM;
f2ea0907 2436 if (nr == RS_REGNUM)
2f14585c 2437 return SIM_SH_RS_REGNUM;
f2ea0907 2438 if (nr == RE_REGNUM)
2f14585c 2439 return SIM_SH_RE_REGNUM;
76cd2bd9
CV		 2440 if (nr >= DSP_R0_BANK_REGNUM && nr <= DSP_R7_BANK_REGNUM)
2441 return nr - DSP_R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM;
2f14585c
JR		 2442 return nr;
2443}
1c0159e0 2444
da962468 2445static int
e7faf938 2446sh_sh2a_register_sim_regno (struct gdbarch *gdbarch, int nr)
da962468
CV		 2447{
2448 switch (nr)
2449 {
2450 case TBR_REGNUM:
2451 return SIM_SH_TBR_REGNUM;
2452 case IBNR_REGNUM:
2453 return SIM_SH_IBNR_REGNUM;
2454 case IBCR_REGNUM:
2455 return SIM_SH_IBCR_REGNUM;
2456 case BANK_REGNUM:
2457 return SIM_SH_BANK_REGNUM;
2458 case MACLB_REGNUM:
2459 return SIM_SH_BANK_MACL_REGNUM;
2460 case GBRB_REGNUM:
2461 return SIM_SH_BANK_GBR_REGNUM;
2462 case PRB_REGNUM:
2463 return SIM_SH_BANK_PR_REGNUM;
2464 case IVNB_REGNUM:
2465 return SIM_SH_BANK_IVN_REGNUM;
2466 case MACHB_REGNUM:
2467 return SIM_SH_BANK_MACH_REGNUM;
2468 default:
2469 break;
2470 }
e7faf938 2471 return legacy_register_sim_regno (gdbarch, nr);
da962468
CV		 2472}
2473
357d3800
AS		 2474/* Set up the register unwinding such that call-clobbered registers are
2475 not displayed in frames >0 because the true value is not certain.
2476 The 'undefined' registers will show up as 'not available' unless the
2477 CFI says otherwise.
2478
2479 This function is currently set up for SH4 and compatible only. */
2480
2481static void
2482sh_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
aff37fc1 2483 struct dwarf2_frame_state_reg *reg,
4a4e5149 2484 struct frame_info *this_frame)
357d3800
AS		 2485{
2486 /* Mark the PC as the destination for the return address. */
b47193f7 2487 if (regnum == gdbarch_pc_regnum (gdbarch))
357d3800
AS		 2488 reg->how = DWARF2_FRAME_REG_RA;
2489
2490 /* Mark the stack pointer as the call frame address. */
b47193f7 2491 else if (regnum == gdbarch_sp_regnum (gdbarch))
357d3800
AS		 2492 reg->how = DWARF2_FRAME_REG_CFA;
2493
2494 /* The above was taken from the default init_reg in dwarf2-frame.c
2495 while the below is SH specific. */
2496
2497 /* Caller save registers. */
2498 else if ((regnum >= R0_REGNUM && regnum <= R0_REGNUM+7)
2499 || (regnum >= FR0_REGNUM && regnum <= FR0_REGNUM+11)
2500 || (regnum >= DR0_REGNUM && regnum <= DR0_REGNUM+5)
2501 || (regnum >= FV0_REGNUM && regnum <= FV0_REGNUM+2)
2502 || (regnum == MACH_REGNUM)
2503 || (regnum == MACL_REGNUM)
2504 || (regnum == FPUL_REGNUM)
2505 || (regnum == SR_REGNUM))
2506 reg->how = DWARF2_FRAME_REG_UNDEFINED;
2507
2508 /* Callee save registers. */
2509 else if ((regnum >= R0_REGNUM+8 && regnum <= R0_REGNUM+15)
2510 || (regnum >= FR0_REGNUM+12 && regnum <= FR0_REGNUM+15)
2511 || (regnum >= DR0_REGNUM+6 && regnum <= DR0_REGNUM+8)
2512 || (regnum == FV0_REGNUM+3))
2513 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
2514
2515 /* Other registers. These are not in the ABI and may or may not
2516 mean anything in frames >0 so don't show them. */
2517 else if ((regnum >= R0_BANK0_REGNUM && regnum <= R0_BANK0_REGNUM+15)
2518 || (regnum == GBR_REGNUM)
2519 || (regnum == VBR_REGNUM)
2520 || (regnum == FPSCR_REGNUM)
2521 || (regnum == SSR_REGNUM)
2522 || (regnum == SPC_REGNUM))
2523 reg->how = DWARF2_FRAME_REG_UNDEFINED;
2524}
2525
1c0159e0
CV		 2526static struct sh_frame_cache *
2527sh_alloc_frame_cache (void)
2528{
2529 struct sh_frame_cache *cache;
2530 int i;
2531
2532 cache = FRAME_OBSTACK_ZALLOC (struct sh_frame_cache);
2533
2534 /* Base address. */
2535 cache->base = 0;
2536 cache->saved_sp = 0;
2537 cache->sp_offset = 0;
2538 cache->pc = 0;
2539
2540 /* Frameless until proven otherwise. */
2541 cache->uses_fp = 0;
617daa0e 2542
1c0159e0
CV		 2543 /* Saved registers. We initialize these to -1 since zero is a valid
2544 offset (that's where fp is supposed to be stored). */
2545 for (i = 0; i < SH_NUM_REGS; i++)
2546 {
2547 cache->saved_regs[i] = -1;
2548 }
617daa0e 2549
1c0159e0 2550 return cache;
617daa0e 2551}
1c0159e0
CV		 2552
2553static struct sh_frame_cache *
94afd7a6 2554sh_frame_cache (struct frame_info *this_frame, void **this_cache)
1c0159e0 2555{
e17a4113 2556 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1c0159e0
CV		 2557 struct sh_frame_cache *cache;
2558 CORE_ADDR current_pc;
2559 int i;
2560
2561 if (*this_cache)
2562 return *this_cache;
2563
2564 cache = sh_alloc_frame_cache ();
2565 *this_cache = cache;
2566
2567 /* In principle, for normal frames, fp holds the frame pointer,
2568 which holds the base address for the current stack frame.
2569 However, for functions that don't need it, the frame pointer is
2570 optional. For these "frameless" functions the frame pointer is
c378eb4e 2571 actually the frame pointer of the calling frame. */
94afd7a6 2572 cache->base = get_frame_register_unsigned (this_frame, FP_REGNUM);
1c0159e0
CV		 2573 if (cache->base == 0)
2574 return cache;
2575
94afd7a6
UW		 2576 cache->pc = get_frame_func (this_frame);
2577 current_pc = get_frame_pc (this_frame);
1c0159e0 2578 if (cache->pc != 0)
d2ca4222
UW		 2579 {
2580 ULONGEST fpscr;
94afd7a6 2581 fpscr = get_frame_register_unsigned (this_frame, FPSCR_REGNUM);
e17a4113 2582 sh_analyze_prologue (gdbarch, cache->pc, current_pc, cache, fpscr);
d2ca4222 2583 }
617daa0e 2584
1c0159e0
CV		 2585 if (!cache->uses_fp)
2586 {
2587 /* We didn't find a valid frame, which means that CACHE->base
2588 currently holds the frame pointer for our calling frame. If
2589 we're at the start of a function, or somewhere half-way its
2590 prologue, the function's frame probably hasn't been fully
2591 setup yet. Try to reconstruct the base address for the stack
2592 frame by looking at the stack pointer. For truly "frameless"
2593 functions this might work too. */
94afd7a6 2594 cache->base = get_frame_register_unsigned
e17a4113 2595 (this_frame, gdbarch_sp_regnum (gdbarch));
1c0159e0
CV		 2596 }
2597
2598 /* Now that we have the base address for the stack frame we can
2599 calculate the value of sp in the calling frame. */
2600 cache->saved_sp = cache->base + cache->sp_offset;
2601
2602 /* Adjust all the saved registers such that they contain addresses
2603 instead of offsets. */
2604 for (i = 0; i < SH_NUM_REGS; i++)
2605 if (cache->saved_regs[i] != -1)
2606 cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i] - 4;
2607
2608 return cache;
2609}
2610
94afd7a6
UW		 2611static struct value *
2612sh_frame_prev_register (struct frame_info *this_frame,
2613 void **this_cache, int regnum)
1c0159e0 2614{
94afd7a6
UW		 2615 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2616 struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache);
1c0159e0
CV		 2617
2618 gdb_assert (regnum >= 0);
2619
b47193f7 2620 if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp)
94afd7a6 2621 return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp);
1c0159e0
CV		 2622
2623 /* The PC of the previous frame is stored in the PR register of
2624 the current frame. Frob regnum so that we pull the value from
2625 the correct place. */
b47193f7 2626 if (regnum == gdbarch_pc_regnum (gdbarch))
1c0159e0
CV		 2627 regnum = PR_REGNUM;
2628
2629 if (regnum < SH_NUM_REGS && cache->saved_regs[regnum] != -1)
94afd7a6
UW		 2630 return frame_unwind_got_memory (this_frame, regnum,
2631 cache->saved_regs[regnum]);
1c0159e0 2632
94afd7a6 2633 return frame_unwind_got_register (this_frame, regnum, regnum);
1c0159e0
CV		 2634}
2635
2636static void
94afd7a6 2637sh_frame_this_id (struct frame_info *this_frame, void **this_cache,
617daa0e
CV		 2638 struct frame_id *this_id)
2639{
94afd7a6 2640 struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache);
1c0159e0
CV		 2641
2642 /* This marks the outermost frame. */
2643 if (cache->base == 0)
2644 return;
2645
2646 *this_id = frame_id_build (cache->saved_sp, cache->pc);
617daa0e 2647}
1c0159e0 2648
617daa0e 2649static const struct frame_unwind sh_frame_unwind = {
1c0159e0 2650 NORMAL_FRAME,
8fbca658 2651 default_frame_unwind_stop_reason,
1c0159e0 2652 sh_frame_this_id,
94afd7a6
UW		 2653 sh_frame_prev_register,
2654 NULL,
2655 default_frame_sniffer
1c0159e0
CV		 2656};
2657
1c0159e0
CV		 2658static CORE_ADDR
2659sh_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
2660{
3e8c568d 2661 return frame_unwind_register_unsigned (next_frame,
b47193f7 2662 gdbarch_sp_regnum (gdbarch));
1c0159e0
CV		 2663}
2664
2665static CORE_ADDR
2666sh_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2667{
3e8c568d 2668 return frame_unwind_register_unsigned (next_frame,
b47193f7 2669 gdbarch_pc_regnum (gdbarch));
1c0159e0
CV		 2670}
2671
2672static struct frame_id
94afd7a6 2673sh_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1c0159e0 2674{
94afd7a6
UW		 2675 CORE_ADDR sp = get_frame_register_unsigned (this_frame,
2676 gdbarch_sp_regnum (gdbarch));
2677 return frame_id_build (sp, get_frame_pc (this_frame));
1c0159e0
CV		 2678}
2679
2680static CORE_ADDR
94afd7a6 2681sh_frame_base_address (struct frame_info *this_frame, void **this_cache)
617daa0e 2682{
94afd7a6 2683 struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache);
617daa0e 2684
1c0159e0
CV		 2685 return cache->base;
2686}
617daa0e
CV		 2687
2688static const struct frame_base sh_frame_base = {
1c0159e0
CV		 2689 &sh_frame_unwind,
2690 sh_frame_base_address,
2691 sh_frame_base_address,
2692 sh_frame_base_address
617daa0e 2693};
1c0159e0
CV		 2694
2695/* The epilogue is defined here as the area at the end of a function,
2696 either on the `ret' instruction itself or after an instruction which
c378eb4e 2697 destroys the function's stack frame. */
1c0159e0
CV		 2698static int
2699sh_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
2700{
e17a4113 2701 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1c0159e0
CV		 2702 CORE_ADDR func_addr = 0, func_end = 0;
2703
2704 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
2705 {
2706 ULONGEST inst;
2707 /* The sh epilogue is max. 14 bytes long. Give another 14 bytes
2708 for a nop and some fixed data (e.g. big offsets) which are
617daa0e 2709 unfortunately also treated as part of the function (which
c378eb4e 2710 means, they are below func_end. */
1c0159e0
CV		 2711 CORE_ADDR addr = func_end - 28;
2712 if (addr < func_addr + 4)
617daa0e 2713 addr = func_addr + 4;
1c0159e0
CV		 2714 if (pc < addr)
2715 return 0;
2716
c378eb4e 2717 /* First search forward until hitting an rts. */
1c0159e0 2718 while (addr < func_end
e17a4113 2719 && !IS_RTS (read_memory_unsigned_integer (addr, 2, byte_order)))
1c0159e0
CV		 2720 addr += 2;
2721 if (addr >= func_end)
617daa0e 2722 return 0;
1c0159e0
CV		 2723
2724 /* At this point we should find a mov.l @r15+,r14 instruction,
2725 either before or after the rts. If not, then the function has
c378eb4e 2726 probably no "normal" epilogue and we bail out here. */
e17a4113
UW		 2727 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
2728 if (IS_RESTORE_FP (read_memory_unsigned_integer (addr - 2, 2,
2729 byte_order)))
617daa0e 2730 addr -= 2;
e17a4113
UW		 2731 else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr + 2, 2,
2732 byte_order)))
1c0159e0
CV		 2733 return 0;
2734
e17a4113 2735 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
03131d99 2736
c378eb4e 2737 /* Step over possible lds.l @r15+,macl. */
03131d99
CV		 2738 if (IS_MACL_LDS (inst))
2739 {
2740 addr -= 2;
e17a4113 2741 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
03131d99
CV		 2742 }
2743
c378eb4e 2744 /* Step over possible lds.l @r15+,pr. */
1c0159e0 2745 if (IS_LDS (inst))
617daa0e 2746 {
1c0159e0 2747 addr -= 2;
e17a4113 2748 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
1c0159e0
CV		 2749 }
2750
c378eb4e 2751 /* Step over possible mov r14,r15. */
1c0159e0 2752 if (IS_MOV_FP_SP (inst))
617daa0e 2753 {
1c0159e0 2754 addr -= 2;
e17a4113 2755 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
1c0159e0
CV		 2756 }
2757
2758 /* Now check for FP adjustments, using add #imm,r14 or add rX, r14
c378eb4e 2759 instructions. */
1c0159e0 2760 while (addr > func_addr + 4
617daa0e 2761 && (IS_ADD_REG_TO_FP (inst) || IS_ADD_IMM_FP (inst)))
1c0159e0
CV		 2762 {
2763 addr -= 2;
e17a4113 2764 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
1c0159e0
CV		 2765 }
2766
03131d99
CV		 2767 /* On SH2a check if the previous instruction was perhaps a MOVI20.
2768 That's allowed for the epilogue. */
2769 if ((gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a
2770 || gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a_nofpu)
2771 && addr > func_addr + 6
e17a4113
UW		 2772 && IS_MOVI20 (read_memory_unsigned_integer (addr - 4, 2,
2773 byte_order)))
03131d99
CV		 2774 addr -= 4;
2775
1c0159e0
CV		 2776 if (pc >= addr)
2777 return 1;
2778 }
2779 return 0;
2780}
c9ac0a72
AS		 2781
2782
2783/* Supply register REGNUM from the buffer specified by REGS and LEN
2784 in the register set REGSET to register cache REGCACHE.
2785 REGTABLE specifies where each register can be found in REGS.
2786 If REGNUM is -1, do this for all registers in REGSET. */
2787
2788void
2789sh_corefile_supply_regset (const struct regset *regset,
2790 struct regcache *regcache,
2791 int regnum, const void *regs, size_t len)
2792{
2793 struct gdbarch *gdbarch = get_regcache_arch (regcache);
2794 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2795 const struct sh_corefile_regmap *regmap = (regset == &sh_corefile_gregset
2796 ? tdep->core_gregmap
2797 : tdep->core_fpregmap);
2798 int i;
2799
2800 for (i = 0; regmap[i].regnum != -1; i++)
2801 {
2802 if ((regnum == -1 || regnum == regmap[i].regnum)
2803 && regmap[i].offset + 4 <= len)
2804 regcache_raw_supply (regcache, regmap[i].regnum,
2805 (char *)regs + regmap[i].offset);
2806 }
2807}
2808
2809/* Collect register REGNUM in the register set REGSET from register cache
2810 REGCACHE into the buffer specified by REGS and LEN.
2811 REGTABLE specifies where each register can be found in REGS.
2812 If REGNUM is -1, do this for all registers in REGSET. */
2813
2814void
2815sh_corefile_collect_regset (const struct regset *regset,
2816 const struct regcache *regcache,
2817 int regnum, void *regs, size_t len)
2818{
2819 struct gdbarch *gdbarch = get_regcache_arch (regcache);
2820 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2821 const struct sh_corefile_regmap *regmap = (regset == &sh_corefile_gregset
2822 ? tdep->core_gregmap
2823 : tdep->core_fpregmap);
2824 int i;
2825
2826 for (i = 0; regmap[i].regnum != -1; i++)
2827 {
2828 if ((regnum == -1 || regnum == regmap[i].regnum)
2829 && regmap[i].offset + 4 <= len)
2830 regcache_raw_collect (regcache, regmap[i].regnum,
2831 (char *)regs + regmap[i].offset);
2832 }
2833}
2834
2835/* The following two regsets have the same contents, so it is tempting to
2836 unify them, but they are distiguished by their address, so don't. */
2837
2838struct regset sh_corefile_gregset =
2839{
2840 NULL,
2841 sh_corefile_supply_regset,
2842 sh_corefile_collect_regset
2843};
2844
2845static struct regset sh_corefile_fpregset =
2846{
2847 NULL,
2848 sh_corefile_supply_regset,
2849 sh_corefile_collect_regset
2850};
2851
2852static const struct regset *
2853sh_regset_from_core_section (struct gdbarch *gdbarch, const char *sect_name,
2854 size_t sect_size)
2855{
2856 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2857
2858 if (tdep->core_gregmap && strcmp (sect_name, ".reg") == 0)
2859 return &sh_corefile_gregset;
2860
2861 if (tdep->core_fpregmap && strcmp (sect_name, ".reg2") == 0)
2862 return &sh_corefile_fpregset;
2863
2864 return NULL;
2865}
ccf00f21 2866\f
cc17453a
EZ		 2867
2868static struct gdbarch *
fba45db2 2869sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
cc17453a 2870{
cc17453a 2871 struct gdbarch *gdbarch;
c9ac0a72 2872 struct gdbarch_tdep *tdep;
d658f924 2873
55ff77ac
CV		 2874 sh_show_regs = sh_generic_show_regs;
2875 switch (info.bfd_arch_info->mach)
2876 {
617daa0e
CV		 2877 case bfd_mach_sh2e:
2878 sh_show_regs = sh2e_show_regs;
2879 break;
da962468
CV		 2880 case bfd_mach_sh2a:
2881 sh_show_regs = sh2a_show_regs;
2882 break;
2883 case bfd_mach_sh2a_nofpu:
2884 sh_show_regs = sh2a_nofpu_show_regs;
2885 break;
617daa0e
CV		 2886 case bfd_mach_sh_dsp:
2887 sh_show_regs = sh_dsp_show_regs;
2888 break;
55ff77ac 2889
617daa0e 2890 case bfd_mach_sh3:
46e8a76b
AS		 2891 case bfd_mach_sh3_nommu:
2892 case bfd_mach_sh2a_nofpu_or_sh3_nommu:
617daa0e
CV		 2893 sh_show_regs = sh3_show_regs;
2894 break;
55ff77ac 2895
617daa0e 2896 case bfd_mach_sh3e:
46e8a76b 2897 case bfd_mach_sh2a_or_sh3e:
617daa0e
CV		 2898 sh_show_regs = sh3e_show_regs;
2899 break;
55ff77ac 2900
617daa0e 2901 case bfd_mach_sh3_dsp:
474e5826 2902 case bfd_mach_sh4al_dsp:
617daa0e
CV		 2903 sh_show_regs = sh3_dsp_show_regs;
2904 break;
55ff77ac 2905
617daa0e 2906 case bfd_mach_sh4:
474e5826 2907 case bfd_mach_sh4a:
46e8a76b 2908 case bfd_mach_sh2a_or_sh4:
617daa0e
CV		 2909 sh_show_regs = sh4_show_regs;
2910 break;
55ff77ac 2911
474e5826 2912 case bfd_mach_sh4_nofpu:
46e8a76b 2913 case bfd_mach_sh4_nommu_nofpu:
474e5826 2914 case bfd_mach_sh4a_nofpu:
46e8a76b 2915 case bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu:
474e5826
CV		 2916 sh_show_regs = sh4_nofpu_show_regs;
2917 break;
2918
617daa0e
CV		 2919 case bfd_mach_sh5:
2920 sh_show_regs = sh64_show_regs;
c378eb4e 2921 /* SH5 is handled entirely in sh64-tdep.c. */
617daa0e 2922 return sh64_gdbarch_init (info, arches);
55ff77ac
CV		 2923 }
2924
4be87837
DJ		 2925 /* If there is already a candidate, use it. */
2926 arches = gdbarch_list_lookup_by_info (arches, &info);
2927 if (arches != NULL)
2928 return arches->gdbarch;
cc17453a
EZ		 2929
2930 /* None found, create a new architecture from the information
c378eb4e 2931 provided. */
c9ac0a72
AS		 2932 tdep = XZALLOC (struct gdbarch_tdep);
2933 gdbarch = gdbarch_alloc (&info, tdep);
cc17453a 2934
48db5a3c
CV		 2935 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2936 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
ec920329 2937 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
48db5a3c
CV		 2938 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2939 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2940 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2941 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
a38d2a54 2942 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
48db5a3c 2943
f2ea0907 2944 set_gdbarch_num_regs (gdbarch, SH_NUM_REGS);
a38d2a54 2945 set_gdbarch_sp_regnum (gdbarch, 15);
a38d2a54 2946 set_gdbarch_pc_regnum (gdbarch, 16);
48db5a3c
CV		 2947 set_gdbarch_fp0_regnum (gdbarch, -1);
2948 set_gdbarch_num_pseudo_regs (gdbarch, 0);
2949
1c0159e0 2950 set_gdbarch_register_type (gdbarch, sh_default_register_type);
dda63807 2951 set_gdbarch_register_reggroup_p (gdbarch, sh_register_reggroup_p);
1c0159e0 2952
eaf90c5d 2953 set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc);
48db5a3c 2954
9dae60cc 2955 set_gdbarch_print_insn (gdbarch, print_insn_sh);
2f14585c 2956 set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);
48db5a3c 2957
c0409442 2958 set_gdbarch_return_value (gdbarch, sh_return_value_nofpu);
1c0159e0 2959
48db5a3c
CV		 2960 set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
2961 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
48db5a3c 2962
1c0159e0
CV		 2963 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu);
2964
48db5a3c
CV		 2965 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2966
19f59343 2967 set_gdbarch_frame_align (gdbarch, sh_frame_align);
1c0159e0
CV		 2968 set_gdbarch_unwind_sp (gdbarch, sh_unwind_sp);
2969 set_gdbarch_unwind_pc (gdbarch, sh_unwind_pc);
94afd7a6 2970 set_gdbarch_dummy_id (gdbarch, sh_dummy_id);
1c0159e0
CV		 2971 frame_base_set_default (gdbarch, &sh_frame_base);
2972
617daa0e 2973 set_gdbarch_in_function_epilogue_p (gdbarch, sh_in_function_epilogue_p);
cc17453a 2974
357d3800
AS		 2975 dwarf2_frame_set_init_reg (gdbarch, sh_dwarf2_frame_init_reg);
2976
c9ac0a72
AS		 2977 set_gdbarch_regset_from_core_section (gdbarch, sh_regset_from_core_section);
2978
cc17453a 2979 switch (info.bfd_arch_info->mach)
8db62801 2980 {
cc17453a 2981 case bfd_mach_sh:
48db5a3c 2982 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
cc17453a 2983 break;
1c0159e0 2984
cc17453a 2985 case bfd_mach_sh2:
48db5a3c 2986 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
617daa0e 2987 break;
1c0159e0 2988
2d188dd3 2989 case bfd_mach_sh2e:
c378eb4e 2990 /* doubles on sh2e and sh3e are actually 4 byte. */
48db5a3c
CV		 2991 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2992
2993 set_gdbarch_register_name (gdbarch, sh_sh2e_register_name);
48db5a3c 2994 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
2d188dd3 2995 set_gdbarch_fp0_regnum (gdbarch, 25);
c0409442 2996 set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
6df2bf50 2997 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2d188dd3 2998 break;
1c0159e0 2999
da962468
CV		 3000 case bfd_mach_sh2a:
3001 set_gdbarch_register_name (gdbarch, sh_sh2a_register_name);
3002 set_gdbarch_register_type (gdbarch, sh_sh2a_register_type);
3003 set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno);
3004
3005 set_gdbarch_fp0_regnum (gdbarch, 25);
3006 set_gdbarch_num_pseudo_regs (gdbarch, 9);
3007 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
3008 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
c0409442 3009 set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
da962468
CV		 3010 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
3011 break;
3012
3013 case bfd_mach_sh2a_nofpu:
3014 set_gdbarch_register_name (gdbarch, sh_sh2a_nofpu_register_name);
3015 set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno);
3016
3017 set_gdbarch_num_pseudo_regs (gdbarch, 1);
3018 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
3019 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
3020 break;
3021
cc17453a 3022 case bfd_mach_sh_dsp:
48db5a3c 3023 set_gdbarch_register_name (gdbarch, sh_sh_dsp_register_name);
2f14585c 3024 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
cc17453a 3025 break;
1c0159e0 3026
cc17453a 3027 case bfd_mach_sh3:
4e6cbc38
AS		 3028 case bfd_mach_sh3_nommu:
3029 case bfd_mach_sh2a_nofpu_or_sh3_nommu:
48db5a3c 3030 set_gdbarch_register_name (gdbarch, sh_sh3_register_name);
cc17453a 3031 break;
1c0159e0 3032
cc17453a 3033 case bfd_mach_sh3e:
4e6cbc38 3034 case bfd_mach_sh2a_or_sh3e:
c378eb4e 3035 /* doubles on sh2e and sh3e are actually 4 byte. */
48db5a3c
CV		 3036 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
3037
3038 set_gdbarch_register_name (gdbarch, sh_sh3e_register_name);
48db5a3c 3039 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
cc17453a 3040 set_gdbarch_fp0_regnum (gdbarch, 25);
c0409442 3041 set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
6df2bf50 3042 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
cc17453a 3043 break;
1c0159e0 3044
cc17453a 3045 case bfd_mach_sh3_dsp:
48db5a3c 3046 set_gdbarch_register_name (gdbarch, sh_sh3_dsp_register_name);
48db5a3c 3047 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
cc17453a 3048 break;
1c0159e0 3049
cc17453a 3050 case bfd_mach_sh4:
474e5826 3051 case bfd_mach_sh4a:
46e8a76b 3052 case bfd_mach_sh2a_or_sh4:
48db5a3c 3053 set_gdbarch_register_name (gdbarch, sh_sh4_register_name);
48db5a3c 3054 set_gdbarch_register_type (gdbarch, sh_sh4_register_type);
cc17453a 3055 set_gdbarch_fp0_regnum (gdbarch, 25);
da962468 3056 set_gdbarch_num_pseudo_regs (gdbarch, 13);
d8124050
AC		 3057 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
3058 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
c0409442 3059 set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
6df2bf50 3060 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
cc17453a 3061 break;
1c0159e0 3062
474e5826
CV		 3063 case bfd_mach_sh4_nofpu:
3064 case bfd_mach_sh4a_nofpu:
4e6cbc38
AS		 3065 case bfd_mach_sh4_nommu_nofpu:
3066 case bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu:
474e5826
CV		 3067 set_gdbarch_register_name (gdbarch, sh_sh4_nofpu_register_name);
3068 break;
3069
3070 case bfd_mach_sh4al_dsp:
3071 set_gdbarch_register_name (gdbarch, sh_sh4al_dsp_register_name);
3072 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
3073 break;
3074
cc17453a 3075 default:
b58cbbf2 3076 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
cc17453a 3077 break;
8db62801 3078 }
cc17453a 3079
4be87837
DJ		 3080 /* Hook in ABI-specific overrides, if they have been registered. */
3081 gdbarch_init_osabi (info, gdbarch);
d658f924 3082
94afd7a6
UW		 3083 dwarf2_append_unwinders (gdbarch);
3084 frame_unwind_append_unwinder (gdbarch, &sh_frame_unwind);
1c0159e0 3085
cc17453a 3086 return gdbarch;
8db62801
EZ		 3087}
3088
c055b101
CV		 3089static void
3090show_sh_command (char *args, int from_tty)
3091{
3092 help_list (showshcmdlist, "show sh ", all_commands, gdb_stdout);
3093}
3094
3095static void
3096set_sh_command (char *args, int from_tty)
3097{
3098 printf_unfiltered
3099 ("\"set sh\" must be followed by an appropriate subcommand.\n");
3100 help_list (setshcmdlist, "set sh ", all_commands, gdb_stdout);
3101}
3102
c378eb4e 3103extern initialize_file_ftype _initialize_sh_tdep; /* -Wmissing-prototypes */
a78f21af 3104
c906108c 3105void
fba45db2 3106_initialize_sh_tdep (void)
c906108c
SS		 3107{
3108 struct cmd_list_element *c;
617daa0e 3109
f2ea0907 3110 gdbarch_register (bfd_arch_sh, sh_gdbarch_init, NULL);
c906108c 3111
1bedd215 3112 add_com ("regs", class_vars, sh_show_regs_command, _("Print all registers"));
c055b101
CV		 3113
3114 add_prefix_cmd ("sh", no_class, set_sh_command, "SH specific commands.",
3115 &setshcmdlist, "set sh ", 0, &setlist);
3116 add_prefix_cmd ("sh", no_class, show_sh_command, "SH specific commands.",
3117 &showshcmdlist, "show sh ", 0, &showlist);
3118
3119 add_setshow_enum_cmd ("calling-convention", class_vars, sh_cc_enum,
3120 &sh_active_calling_convention,
3121 _("Set calling convention used when calling target "
3122 "functions from GDB."),
3123 _("Show calling convention used when calling target "
3124 "functions from GDB."),
3125 _("gcc - Use GCC calling convention (default).\n"
3126 "renesas - Enforce Renesas calling convention."),
3127 NULL, NULL,
3128 &setshcmdlist, &showshcmdlist);
c906108c 3129}
GDB Binutils - Deliverables
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