Commit | Line | Data |
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85a453d5 | 1 | /* Target-dependent code for Renesas Super-H, for GDB. |
0fd88904 | 2 | |
6aba47ca DJ |
3 | Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
4 | 2003, 2004, 2005, 2007 Free Software Foundation, Inc. | |
c906108c | 5 | |
c5aa993b | 6 | This file is part of GDB. |
c906108c | 7 | |
c5aa993b JM |
8 | This program is free software; you can redistribute it and/or modify |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2 of the License, or | |
11 | (at your option) any later version. | |
c906108c | 12 | |
c5aa993b JM |
13 | This program is distributed in the hope that it will be useful, |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
c906108c | 17 | |
c5aa993b JM |
18 | You should have received a copy of the GNU General Public License |
19 | along with this program; if not, write to the Free Software | |
197e01b6 EZ |
20 | Foundation, Inc., 51 Franklin Street, Fifth Floor, |
21 | Boston, MA 02110-1301, USA. */ | |
c906108c SS |
22 | |
23 | /* | |
c5aa993b JM |
24 | Contributed by Steve Chamberlain |
25 | sac@cygnus.com | |
c906108c SS |
26 | */ |
27 | ||
28 | #include "defs.h" | |
29 | #include "frame.h" | |
1c0159e0 CV |
30 | #include "frame-base.h" |
31 | #include "frame-unwind.h" | |
32 | #include "dwarf2-frame.h" | |
c906108c | 33 | #include "symtab.h" |
c906108c SS |
34 | #include "gdbtypes.h" |
35 | #include "gdbcmd.h" | |
36 | #include "gdbcore.h" | |
37 | #include "value.h" | |
38 | #include "dis-asm.h" | |
73c1f219 | 39 | #include "inferior.h" |
c906108c | 40 | #include "gdb_string.h" |
1c0159e0 | 41 | #include "gdb_assert.h" |
b4a20239 | 42 | #include "arch-utils.h" |
fb409745 | 43 | #include "floatformat.h" |
4e052eda | 44 | #include "regcache.h" |
d16aafd8 | 45 | #include "doublest.h" |
4be87837 | 46 | #include "osabi.h" |
dda63807 | 47 | #include "reggroups.h" |
c906108c | 48 | |
ab3b8126 JT |
49 | #include "sh-tdep.h" |
50 | ||
d658f924 | 51 | #include "elf-bfd.h" |
1a8629c7 MS |
52 | #include "solib-svr4.h" |
53 | ||
55ff77ac | 54 | /* sh flags */ |
283150cd EZ |
55 | #include "elf/sh.h" |
56 | /* registers numbers shared with the simulator */ | |
1c922164 | 57 | #include "gdb/sim-sh.h" |
283150cd | 58 | |
55ff77ac | 59 | static void (*sh_show_regs) (void); |
cc17453a | 60 | |
da962468 | 61 | #define SH_NUM_REGS 67 |
88e04cc1 | 62 | |
1c0159e0 | 63 | struct sh_frame_cache |
cc17453a | 64 | { |
1c0159e0 CV |
65 | /* Base address. */ |
66 | CORE_ADDR base; | |
67 | LONGEST sp_offset; | |
68 | CORE_ADDR pc; | |
69 | ||
70 | /* Flag showing that a frame has been created in the prologue code. */ | |
71 | int uses_fp; | |
72 | ||
73 | /* Saved registers. */ | |
74 | CORE_ADDR saved_regs[SH_NUM_REGS]; | |
75 | CORE_ADDR saved_sp; | |
63978407 | 76 | }; |
c906108c | 77 | |
fa88f677 | 78 | static const char * |
cc17453a EZ |
79 | sh_sh_register_name (int reg_nr) |
80 | { | |
617daa0e CV |
81 | static char *register_names[] = { |
82 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
83 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
84 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
85 | "", "", | |
86 | "", "", "", "", "", "", "", "", | |
87 | "", "", "", "", "", "", "", "", | |
88 | "", "", | |
89 | "", "", "", "", "", "", "", "", | |
90 | "", "", "", "", "", "", "", "", | |
da962468 | 91 | "", "", "", "", "", "", "", "", |
cc17453a EZ |
92 | }; |
93 | if (reg_nr < 0) | |
94 | return NULL; | |
95 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
96 | return NULL; | |
97 | return register_names[reg_nr]; | |
98 | } | |
99 | ||
fa88f677 | 100 | static const char * |
cc17453a EZ |
101 | sh_sh3_register_name (int reg_nr) |
102 | { | |
617daa0e CV |
103 | static char *register_names[] = { |
104 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
105 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
106 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
107 | "", "", | |
108 | "", "", "", "", "", "", "", "", | |
109 | "", "", "", "", "", "", "", "", | |
110 | "ssr", "spc", | |
cc17453a EZ |
111 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", |
112 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1" | |
da962468 | 113 | "", "", "", "", "", "", "", "", |
cc17453a EZ |
114 | }; |
115 | if (reg_nr < 0) | |
116 | return NULL; | |
117 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
118 | return NULL; | |
119 | return register_names[reg_nr]; | |
120 | } | |
121 | ||
fa88f677 | 122 | static const char * |
cc17453a EZ |
123 | sh_sh3e_register_name (int reg_nr) |
124 | { | |
617daa0e CV |
125 | static char *register_names[] = { |
126 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
127 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
128 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
cc17453a | 129 | "fpul", "fpscr", |
617daa0e CV |
130 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", |
131 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
132 | "ssr", "spc", | |
cc17453a EZ |
133 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", |
134 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", | |
da962468 | 135 | "", "", "", "", "", "", "", "", |
cc17453a EZ |
136 | }; |
137 | if (reg_nr < 0) | |
138 | return NULL; | |
139 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
140 | return NULL; | |
141 | return register_names[reg_nr]; | |
142 | } | |
143 | ||
2d188dd3 NC |
144 | static const char * |
145 | sh_sh2e_register_name (int reg_nr) | |
146 | { | |
617daa0e CV |
147 | static char *register_names[] = { |
148 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
149 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
150 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
2d188dd3 | 151 | "fpul", "fpscr", |
617daa0e CV |
152 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", |
153 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
154 | "", "", | |
2d188dd3 NC |
155 | "", "", "", "", "", "", "", "", |
156 | "", "", "", "", "", "", "", "", | |
da962468 CV |
157 | "", "", "", "", "", "", "", "", |
158 | }; | |
159 | if (reg_nr < 0) | |
160 | return NULL; | |
161 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
162 | return NULL; | |
163 | return register_names[reg_nr]; | |
164 | } | |
165 | ||
166 | static const char * | |
167 | sh_sh2a_register_name (int reg_nr) | |
168 | { | |
169 | static char *register_names[] = { | |
170 | /* general registers 0-15 */ | |
171 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
172 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
173 | /* 16 - 22 */ | |
174 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
175 | /* 23, 24 */ | |
176 | "fpul", "fpscr", | |
177 | /* floating point registers 25 - 40 */ | |
178 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", | |
179 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
180 | /* 41, 42 */ | |
181 | "", "", | |
182 | /* 43 - 62. Banked registers. The bank number used is determined by | |
183 | the bank register (63). */ | |
184 | "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b", | |
185 | "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", | |
186 | "machb", "ivnb", "prb", "gbrb", "maclb", | |
187 | /* 63: register bank number, not a real register but used to | |
188 | communicate the register bank currently get/set. This register | |
189 | is hidden to the user, who manipulates it using the pseudo | |
190 | register called "bank" (67). See below. */ | |
191 | "", | |
192 | /* 64 - 66 */ | |
193 | "ibcr", "ibnr", "tbr", | |
194 | /* 67: register bank number, the user visible pseudo register. */ | |
195 | "bank", | |
196 | /* double precision (pseudo) 68 - 75 */ | |
197 | "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", | |
198 | }; | |
199 | if (reg_nr < 0) | |
200 | return NULL; | |
201 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
202 | return NULL; | |
203 | return register_names[reg_nr]; | |
204 | } | |
205 | ||
206 | static const char * | |
207 | sh_sh2a_nofpu_register_name (int reg_nr) | |
208 | { | |
209 | static char *register_names[] = { | |
210 | /* general registers 0-15 */ | |
211 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
212 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
213 | /* 16 - 22 */ | |
214 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
215 | /* 23, 24 */ | |
216 | "", "", | |
217 | /* floating point registers 25 - 40 */ | |
218 | "", "", "", "", "", "", "", "", | |
219 | "", "", "", "", "", "", "", "", | |
220 | /* 41, 42 */ | |
221 | "", "", | |
222 | /* 43 - 62. Banked registers. The bank number used is determined by | |
223 | the bank register (63). */ | |
224 | "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b", | |
225 | "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", | |
226 | "machb", "ivnb", "prb", "gbrb", "maclb", | |
227 | /* 63: register bank number, not a real register but used to | |
228 | communicate the register bank currently get/set. This register | |
229 | is hidden to the user, who manipulates it using the pseudo | |
230 | register called "bank" (67). See below. */ | |
231 | "", | |
232 | /* 64 - 66 */ | |
233 | "ibcr", "ibnr", "tbr", | |
234 | /* 67: register bank number, the user visible pseudo register. */ | |
235 | "bank", | |
236 | /* double precision (pseudo) 68 - 75 */ | |
237 | "", "", "", "", "", "", "", "", | |
2d188dd3 NC |
238 | }; |
239 | if (reg_nr < 0) | |
240 | return NULL; | |
241 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
242 | return NULL; | |
243 | return register_names[reg_nr]; | |
244 | } | |
245 | ||
fa88f677 | 246 | static const char * |
cc17453a EZ |
247 | sh_sh_dsp_register_name (int reg_nr) |
248 | { | |
617daa0e CV |
249 | static char *register_names[] = { |
250 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
251 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
252 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
253 | "", "dsr", | |
254 | "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1", | |
255 | "y0", "y1", "", "", "", "", "", "mod", | |
256 | "", "", | |
257 | "rs", "re", "", "", "", "", "", "", | |
258 | "", "", "", "", "", "", "", "", | |
da962468 | 259 | "", "", "", "", "", "", "", "", |
cc17453a EZ |
260 | }; |
261 | if (reg_nr < 0) | |
262 | return NULL; | |
263 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
264 | return NULL; | |
265 | return register_names[reg_nr]; | |
266 | } | |
267 | ||
fa88f677 | 268 | static const char * |
cc17453a EZ |
269 | sh_sh3_dsp_register_name (int reg_nr) |
270 | { | |
617daa0e CV |
271 | static char *register_names[] = { |
272 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
273 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
274 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
275 | "", "dsr", | |
276 | "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1", | |
277 | "y0", "y1", "", "", "", "", "", "mod", | |
278 | "ssr", "spc", | |
279 | "rs", "re", "", "", "", "", "", "", | |
026a72f8 CV |
280 | "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b", |
281 | "", "", "", "", "", "", "", "", | |
da962468 | 282 | "", "", "", "", "", "", "", "", |
cc17453a EZ |
283 | }; |
284 | if (reg_nr < 0) | |
285 | return NULL; | |
286 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
287 | return NULL; | |
288 | return register_names[reg_nr]; | |
289 | } | |
290 | ||
fa88f677 | 291 | static const char * |
53116e27 EZ |
292 | sh_sh4_register_name (int reg_nr) |
293 | { | |
617daa0e | 294 | static char *register_names[] = { |
a38d2a54 | 295 | /* general registers 0-15 */ |
617daa0e CV |
296 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
297 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
a38d2a54 | 298 | /* 16 - 22 */ |
617daa0e | 299 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", |
a38d2a54 | 300 | /* 23, 24 */ |
53116e27 | 301 | "fpul", "fpscr", |
a38d2a54 | 302 | /* floating point registers 25 - 40 */ |
617daa0e CV |
303 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", |
304 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
a38d2a54 | 305 | /* 41, 42 */ |
617daa0e | 306 | "ssr", "spc", |
a38d2a54 | 307 | /* bank 0 43 - 50 */ |
53116e27 | 308 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", |
a38d2a54 | 309 | /* bank 1 51 - 58 */ |
53116e27 | 310 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", |
da962468 CV |
311 | "", "", "", "", "", "", "", "", |
312 | /* pseudo bank register. */ | |
313 | "", | |
a38d2a54 | 314 | /* double precision (pseudo) 59 - 66 */ |
617daa0e | 315 | "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", |
a38d2a54 | 316 | /* vectors (pseudo) 67 - 70 */ |
617daa0e | 317 | "fv0", "fv4", "fv8", "fv12", |
a38d2a54 EZ |
318 | /* FIXME: missing XF 71 - 86 */ |
319 | /* FIXME: missing XD 87 - 94 */ | |
53116e27 EZ |
320 | }; |
321 | if (reg_nr < 0) | |
322 | return NULL; | |
323 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
324 | return NULL; | |
325 | return register_names[reg_nr]; | |
326 | } | |
327 | ||
474e5826 CV |
328 | static const char * |
329 | sh_sh4_nofpu_register_name (int reg_nr) | |
330 | { | |
331 | static char *register_names[] = { | |
332 | /* general registers 0-15 */ | |
333 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
334 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
335 | /* 16 - 22 */ | |
336 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
337 | /* 23, 24 */ | |
338 | "", "", | |
339 | /* floating point registers 25 - 40 -- not for nofpu target */ | |
340 | "", "", "", "", "", "", "", "", | |
341 | "", "", "", "", "", "", "", "", | |
342 | /* 41, 42 */ | |
343 | "ssr", "spc", | |
344 | /* bank 0 43 - 50 */ | |
345 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", | |
346 | /* bank 1 51 - 58 */ | |
347 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", | |
da962468 CV |
348 | "", "", "", "", "", "", "", "", |
349 | /* pseudo bank register. */ | |
350 | "", | |
474e5826 CV |
351 | /* double precision (pseudo) 59 - 66 -- not for nofpu target */ |
352 | "", "", "", "", "", "", "", "", | |
353 | /* vectors (pseudo) 67 - 70 -- not for nofpu target */ | |
354 | "", "", "", "", | |
355 | }; | |
356 | if (reg_nr < 0) | |
357 | return NULL; | |
358 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
359 | return NULL; | |
360 | return register_names[reg_nr]; | |
361 | } | |
362 | ||
363 | static const char * | |
364 | sh_sh4al_dsp_register_name (int reg_nr) | |
365 | { | |
366 | static char *register_names[] = { | |
367 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
368 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
369 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
370 | "", "dsr", | |
371 | "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1", | |
372 | "y0", "y1", "", "", "", "", "", "mod", | |
373 | "ssr", "spc", | |
374 | "rs", "re", "", "", "", "", "", "", | |
026a72f8 CV |
375 | "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b", |
376 | "", "", "", "", "", "", "", "", | |
da962468 | 377 | "", "", "", "", "", "", "", "", |
474e5826 CV |
378 | }; |
379 | if (reg_nr < 0) | |
380 | return NULL; | |
381 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
382 | return NULL; | |
383 | return register_names[reg_nr]; | |
384 | } | |
385 | ||
3117ed25 | 386 | static const unsigned char * |
fba45db2 | 387 | sh_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
cc17453a EZ |
388 | { |
389 | /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */ | |
617daa0e CV |
390 | static unsigned char breakpoint[] = { 0xc3, 0xc3 }; |
391 | ||
bac718a6 UW |
392 | /* For remote stub targets, trapa #20 is used. */ |
393 | if (strcmp (target_shortname, "remote") == 0) | |
394 | { | |
395 | static unsigned char big_remote_breakpoint[] = { 0xc3, 0x20 }; | |
396 | static unsigned char little_remote_breakpoint[] = { 0x20, 0xc3 }; | |
397 | ||
4c6b5505 | 398 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
bac718a6 UW |
399 | { |
400 | *lenptr = sizeof (big_remote_breakpoint); | |
401 | return big_remote_breakpoint; | |
402 | } | |
403 | else | |
404 | { | |
405 | *lenptr = sizeof (little_remote_breakpoint); | |
406 | return little_remote_breakpoint; | |
407 | } | |
408 | } | |
409 | ||
cc17453a EZ |
410 | *lenptr = sizeof (breakpoint); |
411 | return breakpoint; | |
412 | } | |
c906108c SS |
413 | |
414 | /* Prologue looks like | |
1c0159e0 CV |
415 | mov.l r14,@-r15 |
416 | sts.l pr,@-r15 | |
417 | mov.l <regs>,@-r15 | |
418 | sub <room_for_loca_vars>,r15 | |
419 | mov r15,r14 | |
8db62801 | 420 | |
1c0159e0 | 421 | Actually it can be more complicated than this but that's it, basically. |
c5aa993b | 422 | */ |
c906108c | 423 | |
1c0159e0 CV |
424 | #define GET_SOURCE_REG(x) (((x) >> 4) & 0xf) |
425 | #define GET_TARGET_REG(x) (((x) >> 8) & 0xf) | |
426 | ||
5f883edd FF |
427 | /* JSR @Rm 0100mmmm00001011 */ |
428 | #define IS_JSR(x) (((x) & 0xf0ff) == 0x400b) | |
429 | ||
8db62801 EZ |
430 | /* STS.L PR,@-r15 0100111100100010 |
431 | r15-4-->r15, PR-->(r15) */ | |
c906108c | 432 | #define IS_STS(x) ((x) == 0x4f22) |
8db62801 | 433 | |
03131d99 CV |
434 | /* STS.L MACL,@-r15 0100111100010010 |
435 | r15-4-->r15, MACL-->(r15) */ | |
436 | #define IS_MACL_STS(x) ((x) == 0x4f12) | |
437 | ||
8db62801 EZ |
438 | /* MOV.L Rm,@-r15 00101111mmmm0110 |
439 | r15-4-->r15, Rm-->(R15) */ | |
c906108c | 440 | #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06) |
8db62801 | 441 | |
8db62801 EZ |
442 | /* MOV r15,r14 0110111011110011 |
443 | r15-->r14 */ | |
c906108c | 444 | #define IS_MOV_SP_FP(x) ((x) == 0x6ef3) |
8db62801 EZ |
445 | |
446 | /* ADD #imm,r15 01111111iiiiiiii | |
447 | r15+imm-->r15 */ | |
1c0159e0 | 448 | #define IS_ADD_IMM_SP(x) (((x) & 0xff00) == 0x7f00) |
8db62801 | 449 | |
c906108c SS |
450 | #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00) |
451 | #define IS_SHLL_R3(x) ((x) == 0x4300) | |
8db62801 EZ |
452 | |
453 | /* ADD r3,r15 0011111100111100 | |
454 | r15+r3-->r15 */ | |
c906108c | 455 | #define IS_ADD_R3SP(x) ((x) == 0x3f3c) |
8db62801 EZ |
456 | |
457 | /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011 | |
8db62801 | 458 | FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011 |
8db62801 | 459 | FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */ |
f2ea0907 CV |
460 | /* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to |
461 | make this entirely clear. */ | |
1c0159e0 CV |
462 | /* #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) */ |
463 | #define IS_FPUSH(x) (((x) & 0xff0f) == 0xff0b) | |
464 | ||
465 | /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 4 <= m <= 7 */ | |
466 | #define IS_MOV_ARG_TO_REG(x) \ | |
467 | (((x) & 0xf00f) == 0x6003 && \ | |
468 | ((x) & 0x00f0) >= 0x0040 && \ | |
469 | ((x) & 0x00f0) <= 0x0070) | |
470 | /* MOV.L Rm,@Rn 0010nnnnmmmm0010 n = 14, 4 <= m <= 7 */ | |
471 | #define IS_MOV_ARG_TO_IND_R14(x) \ | |
472 | (((x) & 0xff0f) == 0x2e02 && \ | |
473 | ((x) & 0x00f0) >= 0x0040 && \ | |
474 | ((x) & 0x00f0) <= 0x0070) | |
475 | /* MOV.L Rm,@(disp*4,Rn) 00011110mmmmdddd n = 14, 4 <= m <= 7 */ | |
476 | #define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \ | |
477 | (((x) & 0xff00) == 0x1e00 && \ | |
478 | ((x) & 0x00f0) >= 0x0040 && \ | |
479 | ((x) & 0x00f0) <= 0x0070) | |
480 | ||
481 | /* MOV.W @(disp*2,PC),Rn 1001nnnndddddddd */ | |
482 | #define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000) | |
483 | /* MOV.L @(disp*4,PC),Rn 1101nnnndddddddd */ | |
484 | #define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000) | |
03131d99 CV |
485 | /* MOVI20 #imm20,Rn 0000nnnniiii0000 */ |
486 | #define IS_MOVI20(x) (((x) & 0xf00f) == 0x0000) | |
1c0159e0 CV |
487 | /* SUB Rn,R15 00111111nnnn1000 */ |
488 | #define IS_SUB_REG_FROM_SP(x) (((x) & 0xff0f) == 0x3f08) | |
8db62801 | 489 | |
1c0159e0 | 490 | #define FPSCR_SZ (1 << 20) |
cc17453a | 491 | |
1c0159e0 CV |
492 | /* The following instructions are used for epilogue testing. */ |
493 | #define IS_RESTORE_FP(x) ((x) == 0x6ef6) | |
494 | #define IS_RTS(x) ((x) == 0x000b) | |
495 | #define IS_LDS(x) ((x) == 0x4f26) | |
03131d99 | 496 | #define IS_MACL_LDS(x) ((x) == 0x4f16) |
1c0159e0 CV |
497 | #define IS_MOV_FP_SP(x) ((x) == 0x6fe3) |
498 | #define IS_ADD_REG_TO_FP(x) (((x) & 0xff0f) == 0x3e0c) | |
499 | #define IS_ADD_IMM_FP(x) (((x) & 0xff00) == 0x7e00) | |
cc17453a | 500 | |
cc17453a EZ |
501 | /* Disassemble an instruction. */ |
502 | static int | |
617daa0e | 503 | gdb_print_insn_sh (bfd_vma memaddr, disassemble_info * info) |
c906108c | 504 | { |
4c6b5505 | 505 | info->endian = gdbarch_byte_order (current_gdbarch); |
1c509ca8 | 506 | return print_insn_sh (memaddr, info); |
283150cd EZ |
507 | } |
508 | ||
cc17453a | 509 | static CORE_ADDR |
1c0159e0 CV |
510 | sh_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc, |
511 | struct sh_frame_cache *cache) | |
617daa0e | 512 | { |
1c0159e0 CV |
513 | ULONGEST inst; |
514 | CORE_ADDR opc; | |
515 | int offset; | |
516 | int sav_offset = 0; | |
c906108c | 517 | int r3_val = 0; |
1c0159e0 | 518 | int reg, sav_reg = -1; |
cc17453a | 519 | |
1c0159e0 CV |
520 | if (pc >= current_pc) |
521 | return current_pc; | |
cc17453a | 522 | |
1c0159e0 | 523 | cache->uses_fp = 0; |
cc17453a EZ |
524 | for (opc = pc + (2 * 28); pc < opc; pc += 2) |
525 | { | |
1c0159e0 | 526 | inst = read_memory_unsigned_integer (pc, 2); |
cc17453a | 527 | /* See where the registers will be saved to */ |
f2ea0907 | 528 | if (IS_PUSH (inst)) |
cc17453a | 529 | { |
1c0159e0 CV |
530 | cache->saved_regs[GET_SOURCE_REG (inst)] = cache->sp_offset; |
531 | cache->sp_offset += 4; | |
cc17453a | 532 | } |
f2ea0907 | 533 | else if (IS_STS (inst)) |
cc17453a | 534 | { |
1c0159e0 CV |
535 | cache->saved_regs[PR_REGNUM] = cache->sp_offset; |
536 | cache->sp_offset += 4; | |
cc17453a | 537 | } |
03131d99 CV |
538 | else if (IS_MACL_STS (inst)) |
539 | { | |
540 | cache->saved_regs[MACL_REGNUM] = cache->sp_offset; | |
541 | cache->sp_offset += 4; | |
542 | } | |
f2ea0907 | 543 | else if (IS_MOV_R3 (inst)) |
cc17453a | 544 | { |
f2ea0907 | 545 | r3_val = ((inst & 0xff) ^ 0x80) - 0x80; |
cc17453a | 546 | } |
f2ea0907 | 547 | else if (IS_SHLL_R3 (inst)) |
cc17453a EZ |
548 | { |
549 | r3_val <<= 1; | |
550 | } | |
f2ea0907 | 551 | else if (IS_ADD_R3SP (inst)) |
cc17453a | 552 | { |
1c0159e0 | 553 | cache->sp_offset += -r3_val; |
cc17453a | 554 | } |
f2ea0907 | 555 | else if (IS_ADD_IMM_SP (inst)) |
cc17453a | 556 | { |
1c0159e0 CV |
557 | offset = ((inst & 0xff) ^ 0x80) - 0x80; |
558 | cache->sp_offset -= offset; | |
c906108c | 559 | } |
1c0159e0 | 560 | else if (IS_MOVW_PCREL_TO_REG (inst)) |
617daa0e | 561 | { |
1c0159e0 CV |
562 | if (sav_reg < 0) |
563 | { | |
564 | reg = GET_TARGET_REG (inst); | |
565 | if (reg < 14) | |
566 | { | |
567 | sav_reg = reg; | |
a2b4a96c | 568 | offset = (inst & 0xff) << 1; |
1c0159e0 | 569 | sav_offset = |
a2b4a96c | 570 | read_memory_integer ((pc + 4) + offset, 2); |
1c0159e0 CV |
571 | } |
572 | } | |
c906108c | 573 | } |
1c0159e0 | 574 | else if (IS_MOVL_PCREL_TO_REG (inst)) |
617daa0e | 575 | { |
1c0159e0 CV |
576 | if (sav_reg < 0) |
577 | { | |
a2b4a96c | 578 | reg = GET_TARGET_REG (inst); |
1c0159e0 CV |
579 | if (reg < 14) |
580 | { | |
581 | sav_reg = reg; | |
a2b4a96c | 582 | offset = (inst & 0xff) << 2; |
1c0159e0 | 583 | sav_offset = |
a2b4a96c | 584 | read_memory_integer (((pc & 0xfffffffc) + 4) + offset, 4); |
1c0159e0 CV |
585 | } |
586 | } | |
c906108c | 587 | } |
03131d99 CV |
588 | else if (IS_MOVI20 (inst)) |
589 | { | |
590 | if (sav_reg < 0) | |
591 | { | |
592 | reg = GET_TARGET_REG (inst); | |
593 | if (reg < 14) | |
594 | { | |
595 | sav_reg = reg; | |
596 | sav_offset = GET_SOURCE_REG (inst) << 16; | |
597 | /* MOVI20 is a 32 bit instruction! */ | |
598 | pc += 2; | |
599 | sav_offset |= read_memory_unsigned_integer (pc, 2); | |
600 | /* Now sav_offset contains an unsigned 20 bit value. | |
601 | It must still get sign extended. */ | |
602 | if (sav_offset & 0x00080000) | |
603 | sav_offset |= 0xfff00000; | |
604 | } | |
605 | } | |
606 | } | |
1c0159e0 | 607 | else if (IS_SUB_REG_FROM_SP (inst)) |
617daa0e | 608 | { |
1c0159e0 CV |
609 | reg = GET_SOURCE_REG (inst); |
610 | if (sav_reg > 0 && reg == sav_reg) | |
611 | { | |
612 | sav_reg = -1; | |
613 | } | |
614 | cache->sp_offset += sav_offset; | |
c906108c | 615 | } |
f2ea0907 | 616 | else if (IS_FPUSH (inst)) |
c906108c | 617 | { |
f2ea0907 | 618 | if (read_register (FPSCR_REGNUM) & FPSCR_SZ) |
c906108c | 619 | { |
1c0159e0 | 620 | cache->sp_offset += 8; |
c906108c SS |
621 | } |
622 | else | |
623 | { | |
1c0159e0 | 624 | cache->sp_offset += 4; |
c906108c SS |
625 | } |
626 | } | |
f2ea0907 | 627 | else if (IS_MOV_SP_FP (inst)) |
617daa0e | 628 | { |
960ccd7d | 629 | cache->uses_fp = 1; |
1c0159e0 CV |
630 | /* At this point, only allow argument register moves to other |
631 | registers or argument register moves to @(X,fp) which are | |
632 | moving the register arguments onto the stack area allocated | |
633 | by a former add somenumber to SP call. Don't allow moving | |
634 | to an fp indirect address above fp + cache->sp_offset. */ | |
635 | pc += 2; | |
636 | for (opc = pc + 12; pc < opc; pc += 2) | |
637 | { | |
638 | inst = read_memory_integer (pc, 2); | |
639 | if (IS_MOV_ARG_TO_IND_R14 (inst)) | |
617daa0e | 640 | { |
1c0159e0 CV |
641 | reg = GET_SOURCE_REG (inst); |
642 | if (cache->sp_offset > 0) | |
617daa0e | 643 | cache->saved_regs[reg] = cache->sp_offset; |
1c0159e0 CV |
644 | } |
645 | else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst)) | |
617daa0e | 646 | { |
1c0159e0 CV |
647 | reg = GET_SOURCE_REG (inst); |
648 | offset = (inst & 0xf) * 4; | |
649 | if (cache->sp_offset > offset) | |
650 | cache->saved_regs[reg] = cache->sp_offset - offset; | |
651 | } | |
652 | else if (IS_MOV_ARG_TO_REG (inst)) | |
617daa0e | 653 | continue; |
1c0159e0 CV |
654 | else |
655 | break; | |
656 | } | |
657 | break; | |
658 | } | |
5f883edd FF |
659 | else if (IS_JSR (inst)) |
660 | { | |
661 | /* We have found a jsr that has been scheduled into the prologue. | |
662 | If we continue the scan and return a pc someplace after this, | |
663 | then setting a breakpoint on this function will cause it to | |
664 | appear to be called after the function it is calling via the | |
665 | jsr, which will be very confusing. Most likely the next | |
666 | instruction is going to be IS_MOV_SP_FP in the delay slot. If | |
667 | so, note that before returning the current pc. */ | |
668 | inst = read_memory_integer (pc + 2, 2); | |
669 | if (IS_MOV_SP_FP (inst)) | |
670 | cache->uses_fp = 1; | |
671 | break; | |
672 | } | |
617daa0e CV |
673 | #if 0 /* This used to just stop when it found an instruction that |
674 | was not considered part of the prologue. Now, we just | |
675 | keep going looking for likely instructions. */ | |
c906108c SS |
676 | else |
677 | break; | |
2bfa91ee | 678 | #endif |
c906108c SS |
679 | } |
680 | ||
1c0159e0 CV |
681 | return pc; |
682 | } | |
c906108c | 683 | |
1c0159e0 | 684 | /* Skip any prologue before the guts of a function */ |
c906108c | 685 | |
1c0159e0 CV |
686 | /* Skip the prologue using the debug information. If this fails we'll |
687 | fall back on the 'guess' method below. */ | |
688 | static CORE_ADDR | |
689 | after_prologue (CORE_ADDR pc) | |
690 | { | |
691 | struct symtab_and_line sal; | |
692 | CORE_ADDR func_addr, func_end; | |
c906108c | 693 | |
1c0159e0 CV |
694 | /* If we can not find the symbol in the partial symbol table, then |
695 | there is no hope we can determine the function's start address | |
696 | with this code. */ | |
697 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
698 | return 0; | |
c906108c | 699 | |
1c0159e0 CV |
700 | /* Get the line associated with FUNC_ADDR. */ |
701 | sal = find_pc_line (func_addr, 0); | |
702 | ||
703 | /* There are only two cases to consider. First, the end of the source line | |
704 | is within the function bounds. In that case we return the end of the | |
705 | source line. Second is the end of the source line extends beyond the | |
706 | bounds of the current function. We need to use the slow code to | |
707 | examine instructions in that case. */ | |
708 | if (sal.end < func_end) | |
709 | return sal.end; | |
710 | else | |
711 | return 0; | |
c906108c SS |
712 | } |
713 | ||
1c0159e0 CV |
714 | static CORE_ADDR |
715 | sh_skip_prologue (CORE_ADDR start_pc) | |
c906108c | 716 | { |
1c0159e0 CV |
717 | CORE_ADDR pc; |
718 | struct sh_frame_cache cache; | |
719 | ||
720 | /* See if we can determine the end of the prologue via the symbol table. | |
721 | If so, then return either PC, or the PC after the prologue, whichever | |
722 | is greater. */ | |
723 | pc = after_prologue (start_pc); | |
cc17453a | 724 | |
1c0159e0 CV |
725 | /* If after_prologue returned a useful address, then use it. Else |
726 | fall back on the instruction skipping code. */ | |
727 | if (pc) | |
728 | return max (pc, start_pc); | |
c906108c | 729 | |
1c0159e0 CV |
730 | cache.sp_offset = -4; |
731 | pc = sh_analyze_prologue (start_pc, (CORE_ADDR) -1, &cache); | |
732 | if (!cache.uses_fp) | |
733 | return start_pc; | |
c906108c | 734 | |
1c0159e0 CV |
735 | return pc; |
736 | } | |
737 | ||
2e952408 | 738 | /* The ABI says: |
9a5cef92 EZ |
739 | |
740 | Aggregate types not bigger than 8 bytes that have the same size and | |
741 | alignment as one of the integer scalar types are returned in the | |
742 | same registers as the integer type they match. | |
743 | ||
744 | For example, a 2-byte aligned structure with size 2 bytes has the | |
745 | same size and alignment as a short int, and will be returned in R0. | |
746 | A 4-byte aligned structure with size 8 bytes has the same size and | |
747 | alignment as a long long int, and will be returned in R0 and R1. | |
748 | ||
749 | When an aggregate type is returned in R0 and R1, R0 contains the | |
750 | first four bytes of the aggregate, and R1 contains the | |
751 | remainder. If the size of the aggregate type is not a multiple of 4 | |
752 | bytes, the aggregate is tail-padded up to a multiple of 4 | |
753 | bytes. The value of the padding is undefined. For little-endian | |
754 | targets the padding will appear at the most significant end of the | |
755 | last element, for big-endian targets the padding appears at the | |
756 | least significant end of the last element. | |
757 | ||
758 | All other aggregate types are returned by address. The caller | |
759 | function passes the address of an area large enough to hold the | |
760 | aggregate value in R2. The called function stores the result in | |
7fe958be | 761 | this location. |
9a5cef92 EZ |
762 | |
763 | To reiterate, structs smaller than 8 bytes could also be returned | |
764 | in memory, if they don't pass the "same size and alignment as an | |
765 | integer type" rule. | |
766 | ||
767 | For example, in | |
768 | ||
769 | struct s { char c[3]; } wibble; | |
770 | struct s foo(void) { return wibble; } | |
771 | ||
772 | the return value from foo() will be in memory, not | |
773 | in R0, because there is no 3-byte integer type. | |
774 | ||
7fe958be EZ |
775 | Similarly, in |
776 | ||
777 | struct s { char c[2]; } wibble; | |
778 | struct s foo(void) { return wibble; } | |
779 | ||
780 | because a struct containing two chars has alignment 1, that matches | |
781 | type char, but size 2, that matches type short. There's no integer | |
782 | type that has alignment 1 and size 2, so the struct is returned in | |
783 | memory. | |
784 | ||
9a5cef92 EZ |
785 | */ |
786 | ||
1c0159e0 CV |
787 | static int |
788 | sh_use_struct_convention (int gcc_p, struct type *type) | |
789 | { | |
790 | int len = TYPE_LENGTH (type); | |
791 | int nelem = TYPE_NFIELDS (type); | |
3f997a97 CV |
792 | |
793 | /* Non-power of 2 length types and types bigger than 8 bytes (which don't | |
794 | fit in two registers anyway) use struct convention. */ | |
795 | if (len != 1 && len != 2 && len != 4 && len != 8) | |
796 | return 1; | |
797 | ||
798 | /* Scalar types and aggregate types with exactly one field are aligned | |
799 | by definition. They are returned in registers. */ | |
800 | if (nelem <= 1) | |
801 | return 0; | |
802 | ||
803 | /* If the first field in the aggregate has the same length as the entire | |
804 | aggregate type, the type is returned in registers. */ | |
805 | if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == len) | |
806 | return 0; | |
807 | ||
808 | /* If the size of the aggregate is 8 bytes and the first field is | |
809 | of size 4 bytes its alignment is equal to long long's alignment, | |
810 | so it's returned in registers. */ | |
811 | if (len == 8 && TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == 4) | |
812 | return 0; | |
813 | ||
814 | /* Otherwise use struct convention. */ | |
815 | return 1; | |
283150cd EZ |
816 | } |
817 | ||
cc17453a EZ |
818 | /* Extract from an array REGBUF containing the (raw) register state |
819 | the address in which a function should return its structure value, | |
820 | as a CORE_ADDR (or an expression that can be used as one). */ | |
b3df3fff | 821 | static CORE_ADDR |
48db5a3c | 822 | sh_extract_struct_value_address (struct regcache *regcache) |
cc17453a | 823 | { |
48db5a3c | 824 | ULONGEST addr; |
1c0159e0 | 825 | |
48db5a3c CV |
826 | regcache_cooked_read_unsigned (regcache, STRUCT_RETURN_REGNUM, &addr); |
827 | return addr; | |
cc17453a EZ |
828 | } |
829 | ||
19f59343 MS |
830 | static CORE_ADDR |
831 | sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp) | |
832 | { | |
833 | return sp & ~3; | |
834 | } | |
835 | ||
55ff77ac | 836 | /* Function: push_dummy_call (formerly push_arguments) |
c906108c SS |
837 | Setup the function arguments for calling a function in the inferior. |
838 | ||
85a453d5 | 839 | On the Renesas SH architecture, there are four registers (R4 to R7) |
c906108c SS |
840 | which are dedicated for passing function arguments. Up to the first |
841 | four arguments (depending on size) may go into these registers. | |
842 | The rest go on the stack. | |
843 | ||
6df2bf50 MS |
844 | MVS: Except on SH variants that have floating point registers. |
845 | In that case, float and double arguments are passed in the same | |
846 | manner, but using FP registers instead of GP registers. | |
847 | ||
c906108c SS |
848 | Arguments that are smaller than 4 bytes will still take up a whole |
849 | register or a whole 32-bit word on the stack, and will be | |
850 | right-justified in the register or the stack word. This includes | |
851 | chars, shorts, and small aggregate types. | |
852 | ||
853 | Arguments that are larger than 4 bytes may be split between two or | |
854 | more registers. If there are not enough registers free, an argument | |
855 | may be passed partly in a register (or registers), and partly on the | |
856 | stack. This includes doubles, long longs, and larger aggregates. | |
857 | As far as I know, there is no upper limit to the size of aggregates | |
858 | that will be passed in this way; in other words, the convention of | |
859 | passing a pointer to a large aggregate instead of a copy is not used. | |
860 | ||
6df2bf50 | 861 | MVS: The above appears to be true for the SH variants that do not |
55ff77ac | 862 | have an FPU, however those that have an FPU appear to copy the |
6df2bf50 MS |
863 | aggregate argument onto the stack (and not place it in registers) |
864 | if it is larger than 16 bytes (four GP registers). | |
865 | ||
c906108c SS |
866 | An exceptional case exists for struct arguments (and possibly other |
867 | aggregates such as arrays) if the size is larger than 4 bytes but | |
868 | not a multiple of 4 bytes. In this case the argument is never split | |
869 | between the registers and the stack, but instead is copied in its | |
870 | entirety onto the stack, AND also copied into as many registers as | |
871 | there is room for. In other words, space in registers permitting, | |
872 | two copies of the same argument are passed in. As far as I can tell, | |
873 | only the one on the stack is used, although that may be a function | |
874 | of the level of compiler optimization. I suspect this is a compiler | |
875 | bug. Arguments of these odd sizes are left-justified within the | |
876 | word (as opposed to arguments smaller than 4 bytes, which are | |
877 | right-justified). | |
c5aa993b | 878 | |
c906108c SS |
879 | If the function is to return an aggregate type such as a struct, it |
880 | is either returned in the normal return value register R0 (if its | |
881 | size is no greater than one byte), or else the caller must allocate | |
882 | space into which the callee will copy the return value (if the size | |
883 | is greater than one byte). In this case, a pointer to the return | |
884 | value location is passed into the callee in register R2, which does | |
885 | not displace any of the other arguments passed in via registers R4 | |
886 | to R7. */ | |
887 | ||
e5e33cd9 CV |
888 | /* Helper function to justify value in register according to endianess. */ |
889 | static char * | |
890 | sh_justify_value_in_reg (struct value *val, int len) | |
891 | { | |
892 | static char valbuf[4]; | |
893 | ||
617daa0e | 894 | memset (valbuf, 0, sizeof (valbuf)); |
e5e33cd9 CV |
895 | if (len < 4) |
896 | { | |
897 | /* value gets right-justified in the register or stack word */ | |
4c6b5505 | 898 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) |
0fd88904 | 899 | memcpy (valbuf + (4 - len), (char *) value_contents (val), len); |
e5e33cd9 | 900 | else |
0fd88904 | 901 | memcpy (valbuf, (char *) value_contents (val), len); |
e5e33cd9 CV |
902 | return valbuf; |
903 | } | |
0fd88904 | 904 | return (char *) value_contents (val); |
617daa0e | 905 | } |
e5e33cd9 CV |
906 | |
907 | /* Helper function to eval number of bytes to allocate on stack. */ | |
908 | static CORE_ADDR | |
909 | sh_stack_allocsize (int nargs, struct value **args) | |
910 | { | |
911 | int stack_alloc = 0; | |
912 | while (nargs-- > 0) | |
4991999e | 913 | stack_alloc += ((TYPE_LENGTH (value_type (args[nargs])) + 3) & ~3); |
e5e33cd9 CV |
914 | return stack_alloc; |
915 | } | |
916 | ||
917 | /* Helper functions for getting the float arguments right. Registers usage | |
918 | depends on the ABI and the endianess. The comments should enlighten how | |
919 | it's intended to work. */ | |
920 | ||
921 | /* This array stores which of the float arg registers are already in use. */ | |
922 | static int flt_argreg_array[FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM + 1]; | |
923 | ||
924 | /* This function just resets the above array to "no reg used so far". */ | |
925 | static void | |
926 | sh_init_flt_argreg (void) | |
927 | { | |
928 | memset (flt_argreg_array, 0, sizeof flt_argreg_array); | |
929 | } | |
930 | ||
931 | /* This function returns the next register to use for float arg passing. | |
932 | It returns either a valid value between FLOAT_ARG0_REGNUM and | |
933 | FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns | |
934 | FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available. | |
935 | ||
936 | Note that register number 0 in flt_argreg_array corresponds with the | |
937 | real float register fr4. In contrast to FLOAT_ARG0_REGNUM (value is | |
938 | 29) the parity of the register number is preserved, which is important | |
939 | for the double register passing test (see the "argreg & 1" test below). */ | |
940 | static int | |
941 | sh_next_flt_argreg (int len) | |
942 | { | |
943 | int argreg; | |
944 | ||
945 | /* First search for the next free register. */ | |
617daa0e CV |
946 | for (argreg = 0; argreg <= FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM; |
947 | ++argreg) | |
e5e33cd9 CV |
948 | if (!flt_argreg_array[argreg]) |
949 | break; | |
950 | ||
951 | /* No register left? */ | |
952 | if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM) | |
953 | return FLOAT_ARGLAST_REGNUM + 1; | |
954 | ||
955 | if (len == 8) | |
956 | { | |
957 | /* Doubles are always starting in a even register number. */ | |
958 | if (argreg & 1) | |
617daa0e | 959 | { |
e5e33cd9 CV |
960 | flt_argreg_array[argreg] = 1; |
961 | ||
962 | ++argreg; | |
963 | ||
617daa0e | 964 | /* No register left? */ |
e5e33cd9 CV |
965 | if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM) |
966 | return FLOAT_ARGLAST_REGNUM + 1; | |
967 | } | |
968 | /* Also mark the next register as used. */ | |
969 | flt_argreg_array[argreg + 1] = 1; | |
970 | } | |
4c6b5505 | 971 | else if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE) |
e5e33cd9 CV |
972 | { |
973 | /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */ | |
974 | if (!flt_argreg_array[argreg + 1]) | |
975 | ++argreg; | |
976 | } | |
977 | flt_argreg_array[argreg] = 1; | |
978 | return FLOAT_ARG0_REGNUM + argreg; | |
979 | } | |
980 | ||
afce3d2a CV |
981 | /* Helper function which figures out, if a type is treated like a float type. |
982 | ||
2e952408 | 983 | The FPU ABIs have a special way how to treat types as float types. |
afce3d2a CV |
984 | Structures with exactly one member, which is of type float or double, are |
985 | treated exactly as the base types float or double: | |
986 | ||
987 | struct sf { | |
988 | float f; | |
989 | }; | |
990 | ||
991 | struct sd { | |
992 | double d; | |
993 | }; | |
994 | ||
995 | are handled the same way as just | |
996 | ||
997 | float f; | |
998 | ||
999 | double d; | |
1000 | ||
1001 | As a result, arguments of these struct types are pushed into floating point | |
1002 | registers exactly as floats or doubles, using the same decision algorithm. | |
1003 | ||
1004 | The same is valid if these types are used as function return types. The | |
1005 | above structs are returned in fr0 resp. fr0,fr1 instead of in r0, r0,r1 | |
1006 | or even using struct convention as it is for other structs. */ | |
1007 | ||
1008 | static int | |
1009 | sh_treat_as_flt_p (struct type *type) | |
1010 | { | |
1011 | int len = TYPE_LENGTH (type); | |
1012 | ||
1013 | /* Ordinary float types are obviously treated as float. */ | |
1014 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
1015 | return 1; | |
1016 | /* Otherwise non-struct types are not treated as float. */ | |
1017 | if (TYPE_CODE (type) != TYPE_CODE_STRUCT) | |
1018 | return 0; | |
1019 | /* Otherwise structs with more than one memeber are not treated as float. */ | |
1020 | if (TYPE_NFIELDS (type) != 1) | |
1021 | return 0; | |
1022 | /* Otherwise if the type of that member is float, the whole type is | |
1023 | treated as float. */ | |
1024 | if (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) == TYPE_CODE_FLT) | |
1025 | return 1; | |
1026 | /* Otherwise it's not treated as float. */ | |
1027 | return 0; | |
1028 | } | |
1029 | ||
cc17453a | 1030 | static CORE_ADDR |
617daa0e | 1031 | sh_push_dummy_call_fpu (struct gdbarch *gdbarch, |
7d9b040b | 1032 | struct value *function, |
617daa0e | 1033 | struct regcache *regcache, |
6df2bf50 | 1034 | CORE_ADDR bp_addr, int nargs, |
617daa0e | 1035 | struct value **args, |
6df2bf50 MS |
1036 | CORE_ADDR sp, int struct_return, |
1037 | CORE_ADDR struct_addr) | |
1038 | { | |
e5e33cd9 CV |
1039 | int stack_offset = 0; |
1040 | int argreg = ARG0_REGNUM; | |
8748518b | 1041 | int flt_argreg = 0; |
6df2bf50 MS |
1042 | int argnum; |
1043 | struct type *type; | |
1044 | CORE_ADDR regval; | |
1045 | char *val; | |
8748518b | 1046 | int len, reg_size = 0; |
afce3d2a CV |
1047 | int pass_on_stack = 0; |
1048 | int treat_as_flt; | |
6df2bf50 MS |
1049 | |
1050 | /* first force sp to a 4-byte alignment */ | |
1051 | sp = sh_frame_align (gdbarch, sp); | |
1052 | ||
6df2bf50 | 1053 | if (struct_return) |
1c0159e0 | 1054 | regcache_cooked_write_unsigned (regcache, |
617daa0e | 1055 | STRUCT_RETURN_REGNUM, struct_addr); |
6df2bf50 | 1056 | |
e5e33cd9 CV |
1057 | /* make room on stack for args */ |
1058 | sp -= sh_stack_allocsize (nargs, args); | |
1059 | ||
1060 | /* Initialize float argument mechanism. */ | |
1061 | sh_init_flt_argreg (); | |
6df2bf50 MS |
1062 | |
1063 | /* Now load as many as possible of the first arguments into | |
1064 | registers, and push the rest onto the stack. There are 16 bytes | |
1065 | in four registers available. Loop thru args from first to last. */ | |
e5e33cd9 | 1066 | for (argnum = 0; argnum < nargs; argnum++) |
6df2bf50 | 1067 | { |
4991999e | 1068 | type = value_type (args[argnum]); |
6df2bf50 | 1069 | len = TYPE_LENGTH (type); |
e5e33cd9 CV |
1070 | val = sh_justify_value_in_reg (args[argnum], len); |
1071 | ||
1072 | /* Some decisions have to be made how various types are handled. | |
1073 | This also differs in different ABIs. */ | |
1074 | pass_on_stack = 0; | |
e5e33cd9 CV |
1075 | |
1076 | /* Find out the next register to use for a floating point value. */ | |
afce3d2a CV |
1077 | treat_as_flt = sh_treat_as_flt_p (type); |
1078 | if (treat_as_flt) | |
617daa0e | 1079 | flt_argreg = sh_next_flt_argreg (len); |
afce3d2a CV |
1080 | /* In contrast to non-FPU CPUs, arguments are never split between |
1081 | registers and stack. If an argument doesn't fit in the remaining | |
1082 | registers it's always pushed entirely on the stack. */ | |
1083 | else if (len > ((ARGLAST_REGNUM - argreg + 1) * 4)) | |
1084 | pass_on_stack = 1; | |
48db5a3c | 1085 | |
6df2bf50 MS |
1086 | while (len > 0) |
1087 | { | |
afce3d2a CV |
1088 | if ((treat_as_flt && flt_argreg > FLOAT_ARGLAST_REGNUM) |
1089 | || (!treat_as_flt && (argreg > ARGLAST_REGNUM | |
1090 | || pass_on_stack))) | |
617daa0e | 1091 | { |
afce3d2a | 1092 | /* The data goes entirely on the stack, 4-byte aligned. */ |
e5e33cd9 CV |
1093 | reg_size = (len + 3) & ~3; |
1094 | write_memory (sp + stack_offset, val, reg_size); | |
1095 | stack_offset += reg_size; | |
6df2bf50 | 1096 | } |
afce3d2a | 1097 | else if (treat_as_flt && flt_argreg <= FLOAT_ARGLAST_REGNUM) |
6df2bf50 | 1098 | { |
e5e33cd9 CV |
1099 | /* Argument goes in a float argument register. */ |
1100 | reg_size = register_size (gdbarch, flt_argreg); | |
1101 | regval = extract_unsigned_integer (val, reg_size); | |
2e952408 CV |
1102 | /* In little endian mode, float types taking two registers |
1103 | (doubles on sh4, long doubles on sh2e, sh3e and sh4) must | |
1104 | be stored swapped in the argument registers. The below | |
1105 | code first writes the first 32 bits in the next but one | |
1106 | register, increments the val and len values accordingly | |
1107 | and then proceeds as normal by writing the second 32 bits | |
1108 | into the next register. */ | |
4c6b5505 | 1109 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE |
2e952408 CV |
1110 | && TYPE_LENGTH (type) == 2 * reg_size) |
1111 | { | |
1112 | regcache_cooked_write_unsigned (regcache, flt_argreg + 1, | |
1113 | regval); | |
1114 | val += reg_size; | |
1115 | len -= reg_size; | |
1116 | regval = extract_unsigned_integer (val, reg_size); | |
1117 | } | |
6df2bf50 MS |
1118 | regcache_cooked_write_unsigned (regcache, flt_argreg++, regval); |
1119 | } | |
afce3d2a | 1120 | else if (!treat_as_flt && argreg <= ARGLAST_REGNUM) |
e5e33cd9 | 1121 | { |
6df2bf50 | 1122 | /* there's room in a register */ |
e5e33cd9 CV |
1123 | reg_size = register_size (gdbarch, argreg); |
1124 | regval = extract_unsigned_integer (val, reg_size); | |
6df2bf50 MS |
1125 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
1126 | } | |
afce3d2a | 1127 | /* Store the value one register at a time or in one step on stack. */ |
e5e33cd9 CV |
1128 | len -= reg_size; |
1129 | val += reg_size; | |
6df2bf50 MS |
1130 | } |
1131 | } | |
1132 | ||
1133 | /* Store return address. */ | |
55ff77ac | 1134 | regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr); |
6df2bf50 MS |
1135 | |
1136 | /* Update stack pointer. */ | |
1137 | regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp); | |
1138 | ||
1139 | return sp; | |
1140 | } | |
1141 | ||
1142 | static CORE_ADDR | |
617daa0e | 1143 | sh_push_dummy_call_nofpu (struct gdbarch *gdbarch, |
7d9b040b | 1144 | struct value *function, |
617daa0e CV |
1145 | struct regcache *regcache, |
1146 | CORE_ADDR bp_addr, | |
1147 | int nargs, struct value **args, | |
1148 | CORE_ADDR sp, int struct_return, | |
6df2bf50 | 1149 | CORE_ADDR struct_addr) |
c906108c | 1150 | { |
e5e33cd9 CV |
1151 | int stack_offset = 0; |
1152 | int argreg = ARG0_REGNUM; | |
c906108c SS |
1153 | int argnum; |
1154 | struct type *type; | |
1155 | CORE_ADDR regval; | |
1156 | char *val; | |
e5e33cd9 | 1157 | int len, reg_size; |
c906108c SS |
1158 | |
1159 | /* first force sp to a 4-byte alignment */ | |
19f59343 | 1160 | sp = sh_frame_align (gdbarch, sp); |
c906108c | 1161 | |
c906108c | 1162 | if (struct_return) |
55ff77ac | 1163 | regcache_cooked_write_unsigned (regcache, |
617daa0e | 1164 | STRUCT_RETURN_REGNUM, struct_addr); |
c906108c | 1165 | |
e5e33cd9 CV |
1166 | /* make room on stack for args */ |
1167 | sp -= sh_stack_allocsize (nargs, args); | |
c906108c | 1168 | |
c906108c SS |
1169 | /* Now load as many as possible of the first arguments into |
1170 | registers, and push the rest onto the stack. There are 16 bytes | |
1171 | in four registers available. Loop thru args from first to last. */ | |
e5e33cd9 | 1172 | for (argnum = 0; argnum < nargs; argnum++) |
617daa0e | 1173 | { |
4991999e | 1174 | type = value_type (args[argnum]); |
c5aa993b | 1175 | len = TYPE_LENGTH (type); |
e5e33cd9 | 1176 | val = sh_justify_value_in_reg (args[argnum], len); |
c906108c | 1177 | |
c906108c SS |
1178 | while (len > 0) |
1179 | { | |
e5e33cd9 | 1180 | if (argreg > ARGLAST_REGNUM) |
617daa0e | 1181 | { |
e5e33cd9 CV |
1182 | /* The remainder of the data goes entirely on the stack, |
1183 | 4-byte aligned. */ | |
1184 | reg_size = (len + 3) & ~3; | |
1185 | write_memory (sp + stack_offset, val, reg_size); | |
617daa0e | 1186 | stack_offset += reg_size; |
c906108c | 1187 | } |
e5e33cd9 | 1188 | else if (argreg <= ARGLAST_REGNUM) |
617daa0e | 1189 | { |
3bbfbb92 | 1190 | /* there's room in a register */ |
e5e33cd9 CV |
1191 | reg_size = register_size (gdbarch, argreg); |
1192 | regval = extract_unsigned_integer (val, reg_size); | |
48db5a3c | 1193 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
c906108c | 1194 | } |
e5e33cd9 CV |
1195 | /* Store the value reg_size bytes at a time. This means that things |
1196 | larger than reg_size bytes may go partly in registers and partly | |
c906108c | 1197 | on the stack. */ |
e5e33cd9 CV |
1198 | len -= reg_size; |
1199 | val += reg_size; | |
c906108c SS |
1200 | } |
1201 | } | |
48db5a3c CV |
1202 | |
1203 | /* Store return address. */ | |
55ff77ac | 1204 | regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr); |
48db5a3c CV |
1205 | |
1206 | /* Update stack pointer. */ | |
1207 | regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp); | |
1208 | ||
c906108c SS |
1209 | return sp; |
1210 | } | |
1211 | ||
cc17453a EZ |
1212 | /* Find a function's return value in the appropriate registers (in |
1213 | regbuf), and copy it into valbuf. Extract from an array REGBUF | |
1214 | containing the (raw) register state a function return value of type | |
1215 | TYPE, and copy that, in virtual format, into VALBUF. */ | |
1216 | static void | |
3ffc5b9b CV |
1217 | sh_extract_return_value_nofpu (struct type *type, struct regcache *regcache, |
1218 | void *valbuf) | |
c906108c | 1219 | { |
cc17453a | 1220 | int len = TYPE_LENGTH (type); |
3116c80a EZ |
1221 | int return_register = R0_REGNUM; |
1222 | int offset; | |
617daa0e | 1223 | |
cc17453a | 1224 | if (len <= 4) |
3116c80a | 1225 | { |
48db5a3c CV |
1226 | ULONGEST c; |
1227 | ||
1228 | regcache_cooked_read_unsigned (regcache, R0_REGNUM, &c); | |
1229 | store_unsigned_integer (valbuf, len, c); | |
3116c80a | 1230 | } |
48db5a3c | 1231 | else if (len == 8) |
3116c80a | 1232 | { |
48db5a3c CV |
1233 | int i, regnum = R0_REGNUM; |
1234 | for (i = 0; i < len; i += 4) | |
617daa0e | 1235 | regcache_raw_read (regcache, regnum++, (char *) valbuf + i); |
3116c80a EZ |
1236 | } |
1237 | else | |
8a3fe4f8 | 1238 | error (_("bad size for return value")); |
3116c80a EZ |
1239 | } |
1240 | ||
1241 | static void | |
3ffc5b9b CV |
1242 | sh_extract_return_value_fpu (struct type *type, struct regcache *regcache, |
1243 | void *valbuf) | |
3116c80a | 1244 | { |
afce3d2a | 1245 | if (sh_treat_as_flt_p (type)) |
3116c80a | 1246 | { |
48db5a3c CV |
1247 | int len = TYPE_LENGTH (type); |
1248 | int i, regnum = FP0_REGNUM; | |
1249 | for (i = 0; i < len; i += 4) | |
4c6b5505 | 1250 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE) |
2e952408 CV |
1251 | regcache_raw_read (regcache, regnum++, (char *) valbuf + len - 4 - i); |
1252 | else | |
1253 | regcache_raw_read (regcache, regnum++, (char *) valbuf + i); | |
3116c80a | 1254 | } |
cc17453a | 1255 | else |
3ffc5b9b | 1256 | sh_extract_return_value_nofpu (type, regcache, valbuf); |
cc17453a | 1257 | } |
c906108c | 1258 | |
cc17453a EZ |
1259 | /* Write into appropriate registers a function return value |
1260 | of type TYPE, given in virtual format. | |
1261 | If the architecture is sh4 or sh3e, store a function's return value | |
1262 | in the R0 general register or in the FP0 floating point register, | |
1263 | depending on the type of the return value. In all the other cases | |
3bbfbb92 | 1264 | the result is stored in r0, left-justified. */ |
cc17453a | 1265 | static void |
3ffc5b9b CV |
1266 | sh_store_return_value_nofpu (struct type *type, struct regcache *regcache, |
1267 | const void *valbuf) | |
cc17453a | 1268 | { |
48db5a3c CV |
1269 | ULONGEST val; |
1270 | int len = TYPE_LENGTH (type); | |
d19b71be | 1271 | |
48db5a3c | 1272 | if (len <= 4) |
d19b71be | 1273 | { |
48db5a3c CV |
1274 | val = extract_unsigned_integer (valbuf, len); |
1275 | regcache_cooked_write_unsigned (regcache, R0_REGNUM, val); | |
d19b71be MS |
1276 | } |
1277 | else | |
48db5a3c CV |
1278 | { |
1279 | int i, regnum = R0_REGNUM; | |
1280 | for (i = 0; i < len; i += 4) | |
617daa0e | 1281 | regcache_raw_write (regcache, regnum++, (char *) valbuf + i); |
48db5a3c | 1282 | } |
cc17453a | 1283 | } |
c906108c | 1284 | |
cc17453a | 1285 | static void |
3ffc5b9b CV |
1286 | sh_store_return_value_fpu (struct type *type, struct regcache *regcache, |
1287 | const void *valbuf) | |
cc17453a | 1288 | { |
afce3d2a | 1289 | if (sh_treat_as_flt_p (type)) |
48db5a3c CV |
1290 | { |
1291 | int len = TYPE_LENGTH (type); | |
1292 | int i, regnum = FP0_REGNUM; | |
1293 | for (i = 0; i < len; i += 4) | |
4c6b5505 | 1294 | if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE) |
c8a3b559 CV |
1295 | regcache_raw_write (regcache, regnum++, |
1296 | (char *) valbuf + len - 4 - i); | |
1297 | else | |
1298 | regcache_raw_write (regcache, regnum++, (char *) valbuf + i); | |
48db5a3c | 1299 | } |
cc17453a | 1300 | else |
3ffc5b9b | 1301 | sh_store_return_value_nofpu (type, regcache, valbuf); |
c906108c SS |
1302 | } |
1303 | ||
c0409442 CV |
1304 | static enum return_value_convention |
1305 | sh_return_value_nofpu (struct gdbarch *gdbarch, struct type *type, | |
1306 | struct regcache *regcache, | |
18cf8b5b | 1307 | gdb_byte *readbuf, const gdb_byte *writebuf) |
c0409442 CV |
1308 | { |
1309 | if (sh_use_struct_convention (0, type)) | |
1310 | return RETURN_VALUE_STRUCT_CONVENTION; | |
1311 | if (writebuf) | |
3ffc5b9b | 1312 | sh_store_return_value_nofpu (type, regcache, writebuf); |
c0409442 | 1313 | else if (readbuf) |
3ffc5b9b | 1314 | sh_extract_return_value_nofpu (type, regcache, readbuf); |
c0409442 CV |
1315 | return RETURN_VALUE_REGISTER_CONVENTION; |
1316 | } | |
1317 | ||
1318 | static enum return_value_convention | |
1319 | sh_return_value_fpu (struct gdbarch *gdbarch, struct type *type, | |
1320 | struct regcache *regcache, | |
18cf8b5b | 1321 | gdb_byte *readbuf, const gdb_byte *writebuf) |
c0409442 CV |
1322 | { |
1323 | if (sh_use_struct_convention (0, type)) | |
1324 | return RETURN_VALUE_STRUCT_CONVENTION; | |
1325 | if (writebuf) | |
3ffc5b9b | 1326 | sh_store_return_value_fpu (type, regcache, writebuf); |
c0409442 | 1327 | else if (readbuf) |
3ffc5b9b | 1328 | sh_extract_return_value_fpu (type, regcache, readbuf); |
c0409442 CV |
1329 | return RETURN_VALUE_REGISTER_CONVENTION; |
1330 | } | |
1331 | ||
c906108c SS |
1332 | /* Print the registers in a form similar to the E7000 */ |
1333 | ||
1334 | static void | |
fba45db2 | 1335 | sh_generic_show_regs (void) |
c906108c | 1336 | { |
a6b0a3f3 | 1337 | printf_filtered (" PC %s SR %08lx PR %08lx MACH %08lx\n", |
cc17453a | 1338 | paddr (read_register (PC_REGNUM)), |
55ff77ac CV |
1339 | (long) read_register (SR_REGNUM), |
1340 | (long) read_register (PR_REGNUM), | |
a6b0a3f3 | 1341 | (long) read_register (MACH_REGNUM)); |
cc17453a | 1342 | |
a6b0a3f3 AS |
1343 | printf_filtered ( |
1344 | " GBR %08lx VBR %08lx MACL %08lx\n", | |
cc17453a | 1345 | (long) read_register (GBR_REGNUM), |
a6b0a3f3 AS |
1346 | (long) read_register (VBR_REGNUM), |
1347 | (long) read_register (MACL_REGNUM)); | |
cc17453a | 1348 | |
617daa0e | 1349 | printf_filtered |
a6b0a3f3 | 1350 | ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
617daa0e CV |
1351 | (long) read_register (0), (long) read_register (1), |
1352 | (long) read_register (2), (long) read_register (3), | |
1353 | (long) read_register (4), (long) read_register (5), | |
1354 | (long) read_register (6), (long) read_register (7)); | |
a6b0a3f3 | 1355 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
617daa0e CV |
1356 | (long) read_register (8), (long) read_register (9), |
1357 | (long) read_register (10), (long) read_register (11), | |
1358 | (long) read_register (12), (long) read_register (13), | |
1359 | (long) read_register (14), (long) read_register (15)); | |
cc17453a | 1360 | } |
c906108c | 1361 | |
cc17453a | 1362 | static void |
fba45db2 | 1363 | sh3_show_regs (void) |
cc17453a | 1364 | { |
a6b0a3f3 | 1365 | printf_filtered (" PC %s SR %08lx PR %08lx MACH %08lx\n", |
d4f3574e | 1366 | paddr (read_register (PC_REGNUM)), |
55ff77ac CV |
1367 | (long) read_register (SR_REGNUM), |
1368 | (long) read_register (PR_REGNUM), | |
a6b0a3f3 | 1369 | (long) read_register (MACH_REGNUM)); |
d4f3574e | 1370 | |
a6b0a3f3 AS |
1371 | printf_filtered ( |
1372 | " GBR %08lx VBR %08lx MACL %08lx\n", | |
d4f3574e | 1373 | (long) read_register (GBR_REGNUM), |
a6b0a3f3 AS |
1374 | (long) read_register (VBR_REGNUM), |
1375 | (long) read_register (MACL_REGNUM)); | |
1376 | printf_filtered (" SSR %08lx SPC %08lx\n", | |
617daa0e | 1377 | (long) read_register (SSR_REGNUM), |
f2ea0907 | 1378 | (long) read_register (SPC_REGNUM)); |
c906108c | 1379 | |
617daa0e | 1380 | printf_filtered |
a6b0a3f3 | 1381 | ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
617daa0e CV |
1382 | (long) read_register (0), (long) read_register (1), |
1383 | (long) read_register (2), (long) read_register (3), | |
1384 | (long) read_register (4), (long) read_register (5), | |
1385 | (long) read_register (6), (long) read_register (7)); | |
a6b0a3f3 | 1386 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
617daa0e CV |
1387 | (long) read_register (8), (long) read_register (9), |
1388 | (long) read_register (10), (long) read_register (11), | |
1389 | (long) read_register (12), (long) read_register (13), | |
1390 | (long) read_register (14), (long) read_register (15)); | |
c906108c SS |
1391 | } |
1392 | ||
53116e27 | 1393 | |
2d188dd3 NC |
1394 | static void |
1395 | sh2e_show_regs (void) | |
1396 | { | |
a6b0a3f3 | 1397 | printf_filtered (" PC %s SR %08lx PR %08lx MACH %08lx\n", |
2d188dd3 NC |
1398 | paddr (read_register (PC_REGNUM)), |
1399 | (long) read_register (SR_REGNUM), | |
1400 | (long) read_register (PR_REGNUM), | |
a6b0a3f3 | 1401 | (long) read_register (MACH_REGNUM)); |
2d188dd3 | 1402 | |
a6b0a3f3 AS |
1403 | printf_filtered ( |
1404 | " GBR %08lx VBR %08lx MACL %08lx\n", | |
2d188dd3 | 1405 | (long) read_register (GBR_REGNUM), |
a6b0a3f3 AS |
1406 | (long) read_register (VBR_REGNUM), |
1407 | (long) read_register (MACL_REGNUM)); | |
1408 | printf_filtered ( | |
1409 | " SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n", | |
1410 | (long) read_register (SSR_REGNUM), | |
1411 | (long) read_register (SPC_REGNUM), | |
617daa0e CV |
1412 | (long) read_register (FPUL_REGNUM), |
1413 | (long) read_register (FPSCR_REGNUM)); | |
1414 | ||
1415 | printf_filtered | |
a6b0a3f3 | 1416 | ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
617daa0e CV |
1417 | (long) read_register (0), (long) read_register (1), |
1418 | (long) read_register (2), (long) read_register (3), | |
1419 | (long) read_register (4), (long) read_register (5), | |
1420 | (long) read_register (6), (long) read_register (7)); | |
a6b0a3f3 | 1421 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
617daa0e CV |
1422 | (long) read_register (8), (long) read_register (9), |
1423 | (long) read_register (10), (long) read_register (11), | |
1424 | (long) read_register (12), (long) read_register (13), | |
1425 | (long) read_register (14), (long) read_register (15)); | |
1426 | ||
a6b0a3f3 AS |
1427 | printf_filtered ("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
1428 | (long) read_register (FP0_REGNUM + 0), | |
1429 | (long) read_register (FP0_REGNUM + 1), | |
1430 | (long) read_register (FP0_REGNUM + 2), | |
1431 | (long) read_register (FP0_REGNUM + 3), | |
1432 | (long) read_register (FP0_REGNUM + 4), | |
1433 | (long) read_register (FP0_REGNUM + 5), | |
1434 | (long) read_register (FP0_REGNUM + 6), | |
1435 | (long) read_register (FP0_REGNUM + 7)); | |
1436 | printf_filtered ("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1437 | (long) read_register (FP0_REGNUM + 8), | |
1438 | (long) read_register (FP0_REGNUM + 9), | |
1439 | (long) read_register (FP0_REGNUM + 10), | |
1440 | (long) read_register (FP0_REGNUM + 11), | |
1441 | (long) read_register (FP0_REGNUM + 12), | |
1442 | (long) read_register (FP0_REGNUM + 13), | |
1443 | (long) read_register (FP0_REGNUM + 14), | |
1444 | (long) read_register (FP0_REGNUM + 15)); | |
2d188dd3 NC |
1445 | } |
1446 | ||
da962468 CV |
1447 | static void |
1448 | sh2a_show_regs (void) | |
1449 | { | |
1450 | int pr = read_register (FPSCR_REGNUM) & 0x80000; | |
a6b0a3f3 | 1451 | printf_filtered (" PC %s SR %08lx PR %08lx MACH %08lx\n", |
da962468 CV |
1452 | paddr (read_register (PC_REGNUM)), |
1453 | (long) read_register (SR_REGNUM), | |
1454 | (long) read_register (PR_REGNUM), | |
a6b0a3f3 | 1455 | (long) read_register (MACH_REGNUM)); |
da962468 | 1456 | |
a6b0a3f3 AS |
1457 | printf_filtered ( |
1458 | " GBR %08lx VBR %08lx TBR %08lx MACL %08lx\n", | |
da962468 CV |
1459 | (long) read_register (GBR_REGNUM), |
1460 | (long) read_register (VBR_REGNUM), | |
a6b0a3f3 AS |
1461 | (long) read_register (TBR_REGNUM), |
1462 | (long) read_register (MACL_REGNUM)); | |
1463 | printf_filtered ( | |
1464 | " SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n", | |
1465 | (long) read_register (SSR_REGNUM), | |
1466 | (long) read_register (SPC_REGNUM), | |
da962468 CV |
1467 | (long) read_register (FPUL_REGNUM), |
1468 | (long) read_register (FPSCR_REGNUM)); | |
1469 | ||
a6b0a3f3 | 1470 | printf_filtered ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
da962468 CV |
1471 | (long) read_register (0), (long) read_register (1), |
1472 | (long) read_register (2), (long) read_register (3), | |
1473 | (long) read_register (4), (long) read_register (5), | |
1474 | (long) read_register (6), (long) read_register (7)); | |
a6b0a3f3 | 1475 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
da962468 CV |
1476 | (long) read_register (8), (long) read_register (9), |
1477 | (long) read_register (10), (long) read_register (11), | |
1478 | (long) read_register (12), (long) read_register (13), | |
1479 | (long) read_register (14), (long) read_register (15)); | |
1480 | ||
a6b0a3f3 AS |
1481 | printf_filtered ( |
1482 | (pr ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n" | |
1483 | : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), | |
da962468 CV |
1484 | (long) read_register (FP0_REGNUM + 0), |
1485 | (long) read_register (FP0_REGNUM + 1), | |
1486 | (long) read_register (FP0_REGNUM + 2), | |
1487 | (long) read_register (FP0_REGNUM + 3), | |
1488 | (long) read_register (FP0_REGNUM + 4), | |
1489 | (long) read_register (FP0_REGNUM + 5), | |
1490 | (long) read_register (FP0_REGNUM + 6), | |
1491 | (long) read_register (FP0_REGNUM + 7)); | |
a6b0a3f3 AS |
1492 | printf_filtered ( |
1493 | (pr ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n" | |
1494 | : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), | |
da962468 CV |
1495 | (long) read_register (FP0_REGNUM + 8), |
1496 | (long) read_register (FP0_REGNUM + 9), | |
1497 | (long) read_register (FP0_REGNUM + 10), | |
1498 | (long) read_register (FP0_REGNUM + 11), | |
1499 | (long) read_register (FP0_REGNUM + 12), | |
1500 | (long) read_register (FP0_REGNUM + 13), | |
1501 | (long) read_register (FP0_REGNUM + 14), | |
1502 | (long) read_register (FP0_REGNUM + 15)); | |
1503 | printf_filtered ("BANK=%-3d\n", (int) read_register (BANK_REGNUM)); | |
a6b0a3f3 AS |
1504 | printf_filtered ( |
1505 | "R0b-R7b %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
da962468 CV |
1506 | (long) read_register (R0_BANK0_REGNUM + 0), |
1507 | (long) read_register (R0_BANK0_REGNUM + 1), | |
1508 | (long) read_register (R0_BANK0_REGNUM + 2), | |
1509 | (long) read_register (R0_BANK0_REGNUM + 3), | |
1510 | (long) read_register (R0_BANK0_REGNUM + 4), | |
1511 | (long) read_register (R0_BANK0_REGNUM + 5), | |
1512 | (long) read_register (R0_BANK0_REGNUM + 6), | |
1513 | (long) read_register (R0_BANK0_REGNUM + 7)); | |
a6b0a3f3 | 1514 | printf_filtered ("R8b-R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
da962468 CV |
1515 | (long) read_register (R0_BANK0_REGNUM + 8), |
1516 | (long) read_register (R0_BANK0_REGNUM + 9), | |
1517 | (long) read_register (R0_BANK0_REGNUM + 10), | |
1518 | (long) read_register (R0_BANK0_REGNUM + 11), | |
1519 | (long) read_register (R0_BANK0_REGNUM + 12), | |
1520 | (long) read_register (R0_BANK0_REGNUM + 13), | |
1521 | (long) read_register (R0_BANK0_REGNUM + 14)); | |
1522 | printf_filtered ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n", | |
1523 | (long) read_register (R0_BANK0_REGNUM + 15), | |
1524 | (long) read_register (R0_BANK0_REGNUM + 16), | |
1525 | (long) read_register (R0_BANK0_REGNUM + 17), | |
1526 | (long) read_register (R0_BANK0_REGNUM + 18), | |
1527 | (long) read_register (R0_BANK0_REGNUM + 19)); | |
1528 | } | |
1529 | ||
1530 | static void | |
1531 | sh2a_nofpu_show_regs (void) | |
1532 | { | |
1533 | int pr = read_register (FPSCR_REGNUM) & 0x80000; | |
a6b0a3f3 | 1534 | printf_filtered (" PC %s SR %08lx PR %08lx MACH %08lx\n", |
da962468 CV |
1535 | paddr (read_register (PC_REGNUM)), |
1536 | (long) read_register (SR_REGNUM), | |
1537 | (long) read_register (PR_REGNUM), | |
a6b0a3f3 | 1538 | (long) read_register (MACH_REGNUM)); |
da962468 | 1539 | |
a6b0a3f3 AS |
1540 | printf_filtered ( |
1541 | " GBR %08lx VBR %08lx TBR %08lx MACL %08lx\n", | |
da962468 CV |
1542 | (long) read_register (GBR_REGNUM), |
1543 | (long) read_register (VBR_REGNUM), | |
a6b0a3f3 AS |
1544 | (long) read_register (TBR_REGNUM), |
1545 | (long) read_register (MACL_REGNUM)); | |
1546 | printf_filtered ( | |
1547 | " SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n", | |
1548 | (long) read_register (SSR_REGNUM), | |
1549 | (long) read_register (SPC_REGNUM), | |
da962468 CV |
1550 | (long) read_register (FPUL_REGNUM), |
1551 | (long) read_register (FPSCR_REGNUM)); | |
1552 | ||
a6b0a3f3 | 1553 | printf_filtered ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
da962468 CV |
1554 | (long) read_register (0), (long) read_register (1), |
1555 | (long) read_register (2), (long) read_register (3), | |
1556 | (long) read_register (4), (long) read_register (5), | |
1557 | (long) read_register (6), (long) read_register (7)); | |
a6b0a3f3 | 1558 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
da962468 CV |
1559 | (long) read_register (8), (long) read_register (9), |
1560 | (long) read_register (10), (long) read_register (11), | |
1561 | (long) read_register (12), (long) read_register (13), | |
1562 | (long) read_register (14), (long) read_register (15)); | |
1563 | ||
1564 | printf_filtered ("BANK=%-3d\n", (int) read_register (BANK_REGNUM)); | |
a6b0a3f3 AS |
1565 | printf_filtered ( |
1566 | "R0b-R7b %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
da962468 CV |
1567 | (long) read_register (R0_BANK0_REGNUM + 0), |
1568 | (long) read_register (R0_BANK0_REGNUM + 1), | |
1569 | (long) read_register (R0_BANK0_REGNUM + 2), | |
1570 | (long) read_register (R0_BANK0_REGNUM + 3), | |
1571 | (long) read_register (R0_BANK0_REGNUM + 4), | |
1572 | (long) read_register (R0_BANK0_REGNUM + 5), | |
1573 | (long) read_register (R0_BANK0_REGNUM + 6), | |
1574 | (long) read_register (R0_BANK0_REGNUM + 7)); | |
a6b0a3f3 | 1575 | printf_filtered ("R8b-R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
da962468 CV |
1576 | (long) read_register (R0_BANK0_REGNUM + 8), |
1577 | (long) read_register (R0_BANK0_REGNUM + 9), | |
1578 | (long) read_register (R0_BANK0_REGNUM + 10), | |
1579 | (long) read_register (R0_BANK0_REGNUM + 11), | |
1580 | (long) read_register (R0_BANK0_REGNUM + 12), | |
1581 | (long) read_register (R0_BANK0_REGNUM + 13), | |
1582 | (long) read_register (R0_BANK0_REGNUM + 14)); | |
1583 | printf_filtered ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n", | |
1584 | (long) read_register (R0_BANK0_REGNUM + 15), | |
1585 | (long) read_register (R0_BANK0_REGNUM + 16), | |
1586 | (long) read_register (R0_BANK0_REGNUM + 17), | |
1587 | (long) read_register (R0_BANK0_REGNUM + 18), | |
1588 | (long) read_register (R0_BANK0_REGNUM + 19)); | |
1589 | } | |
1590 | ||
cc17453a | 1591 | static void |
fba45db2 | 1592 | sh3e_show_regs (void) |
cc17453a | 1593 | { |
a6b0a3f3 | 1594 | printf_filtered (" PC %s SR %08lx PR %08lx MACH %08lx\n", |
cc17453a | 1595 | paddr (read_register (PC_REGNUM)), |
55ff77ac CV |
1596 | (long) read_register (SR_REGNUM), |
1597 | (long) read_register (PR_REGNUM), | |
a6b0a3f3 | 1598 | (long) read_register (MACH_REGNUM)); |
cc17453a | 1599 | |
a6b0a3f3 AS |
1600 | printf_filtered ( |
1601 | " GBR %08lx VBR %08lx MACL %08lx\n", | |
cc17453a | 1602 | (long) read_register (GBR_REGNUM), |
a6b0a3f3 AS |
1603 | (long) read_register (VBR_REGNUM), |
1604 | (long) read_register (MACL_REGNUM)); | |
1605 | printf_filtered ( | |
1606 | " SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n", | |
f2ea0907 | 1607 | (long) read_register (SSR_REGNUM), |
a6b0a3f3 | 1608 | (long) read_register (SPC_REGNUM), |
f2ea0907 CV |
1609 | (long) read_register (FPUL_REGNUM), |
1610 | (long) read_register (FPSCR_REGNUM)); | |
c906108c | 1611 | |
617daa0e | 1612 | printf_filtered |
a6b0a3f3 | 1613 | ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
617daa0e CV |
1614 | (long) read_register (0), (long) read_register (1), |
1615 | (long) read_register (2), (long) read_register (3), | |
1616 | (long) read_register (4), (long) read_register (5), | |
1617 | (long) read_register (6), (long) read_register (7)); | |
a6b0a3f3 | 1618 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
617daa0e CV |
1619 | (long) read_register (8), (long) read_register (9), |
1620 | (long) read_register (10), (long) read_register (11), | |
1621 | (long) read_register (12), (long) read_register (13), | |
1622 | (long) read_register (14), (long) read_register (15)); | |
1623 | ||
a6b0a3f3 AS |
1624 | printf_filtered ("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
1625 | (long) read_register (FP0_REGNUM + 0), | |
1626 | (long) read_register (FP0_REGNUM + 1), | |
1627 | (long) read_register (FP0_REGNUM + 2), | |
1628 | (long) read_register (FP0_REGNUM + 3), | |
1629 | (long) read_register (FP0_REGNUM + 4), | |
1630 | (long) read_register (FP0_REGNUM + 5), | |
1631 | (long) read_register (FP0_REGNUM + 6), | |
1632 | (long) read_register (FP0_REGNUM + 7)); | |
1633 | printf_filtered ("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1634 | (long) read_register (FP0_REGNUM + 8), | |
1635 | (long) read_register (FP0_REGNUM + 9), | |
1636 | (long) read_register (FP0_REGNUM + 10), | |
1637 | (long) read_register (FP0_REGNUM + 11), | |
1638 | (long) read_register (FP0_REGNUM + 12), | |
1639 | (long) read_register (FP0_REGNUM + 13), | |
1640 | (long) read_register (FP0_REGNUM + 14), | |
1641 | (long) read_register (FP0_REGNUM + 15)); | |
cc17453a EZ |
1642 | } |
1643 | ||
1644 | static void | |
fba45db2 | 1645 | sh3_dsp_show_regs (void) |
c906108c | 1646 | { |
a6b0a3f3 | 1647 | printf_filtered (" PC %s SR %08lx PR %08lx MACH %08lx\n", |
cc17453a | 1648 | paddr (read_register (PC_REGNUM)), |
55ff77ac CV |
1649 | (long) read_register (SR_REGNUM), |
1650 | (long) read_register (PR_REGNUM), | |
a6b0a3f3 | 1651 | (long) read_register (MACH_REGNUM)); |
c906108c | 1652 | |
a6b0a3f3 AS |
1653 | printf_filtered ( |
1654 | " GBR %08lx VBR %08lx MACL %08lx\n", | |
cc17453a | 1655 | (long) read_register (GBR_REGNUM), |
a6b0a3f3 AS |
1656 | (long) read_register (VBR_REGNUM), |
1657 | (long) read_register (MACL_REGNUM)); | |
cc17453a | 1658 | |
a6b0a3f3 | 1659 | printf_filtered (" SSR %08lx SPC %08lx DSR %08lx\n", |
f2ea0907 | 1660 | (long) read_register (SSR_REGNUM), |
a6b0a3f3 AS |
1661 | (long) read_register (SPC_REGNUM), |
1662 | (long) read_register (DSR_REGNUM)); | |
617daa0e CV |
1663 | |
1664 | printf_filtered | |
a6b0a3f3 | 1665 | ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
617daa0e CV |
1666 | (long) read_register (0), (long) read_register (1), |
1667 | (long) read_register (2), (long) read_register (3), | |
1668 | (long) read_register (4), (long) read_register (5), | |
1669 | (long) read_register (6), (long) read_register (7)); | |
a6b0a3f3 | 1670 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
617daa0e CV |
1671 | (long) read_register (8), (long) read_register (9), |
1672 | (long) read_register (10), (long) read_register (11), | |
1673 | (long) read_register (12), (long) read_register (13), | |
1674 | (long) read_register (14), (long) read_register (15)); | |
1675 | ||
1676 | printf_filtered | |
1677 | ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n", | |
1678 | (long) read_register (A0G_REGNUM) & 0xff, | |
1679 | (long) read_register (A0_REGNUM), (long) read_register (M0_REGNUM), | |
1680 | (long) read_register (X0_REGNUM), (long) read_register (Y0_REGNUM), | |
1681 | (long) read_register (RS_REGNUM), (long) read_register (MOD_REGNUM)); | |
cc17453a | 1682 | printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n", |
f2ea0907 CV |
1683 | (long) read_register (A1G_REGNUM) & 0xff, |
1684 | (long) read_register (A1_REGNUM), | |
1685 | (long) read_register (M1_REGNUM), | |
1686 | (long) read_register (X1_REGNUM), | |
1687 | (long) read_register (Y1_REGNUM), | |
1688 | (long) read_register (RE_REGNUM)); | |
c906108c SS |
1689 | } |
1690 | ||
cc17453a | 1691 | static void |
fba45db2 | 1692 | sh4_show_regs (void) |
cc17453a | 1693 | { |
f2ea0907 | 1694 | int pr = read_register (FPSCR_REGNUM) & 0x80000; |
a6b0a3f3 | 1695 | printf_filtered (" PC %s SR %08lx PR %08lx MACH %08lx\n", |
cc17453a | 1696 | paddr (read_register (PC_REGNUM)), |
55ff77ac CV |
1697 | (long) read_register (SR_REGNUM), |
1698 | (long) read_register (PR_REGNUM), | |
a6b0a3f3 | 1699 | (long) read_register (MACH_REGNUM)); |
cc17453a | 1700 | |
a6b0a3f3 AS |
1701 | printf_filtered ( |
1702 | " GBR %08lx VBR %08lx MACL %08lx\n", | |
cc17453a | 1703 | (long) read_register (GBR_REGNUM), |
a6b0a3f3 AS |
1704 | (long) read_register (VBR_REGNUM), |
1705 | (long) read_register (MACL_REGNUM)); | |
1706 | printf_filtered ( | |
1707 | " SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n", | |
f2ea0907 | 1708 | (long) read_register (SSR_REGNUM), |
a6b0a3f3 | 1709 | (long) read_register (SPC_REGNUM), |
f2ea0907 CV |
1710 | (long) read_register (FPUL_REGNUM), |
1711 | (long) read_register (FPSCR_REGNUM)); | |
cc17453a | 1712 | |
a6b0a3f3 AS |
1713 | printf_filtered ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
1714 | (long) read_register (0), (long) read_register (1), | |
1715 | (long) read_register (2), (long) read_register (3), | |
1716 | (long) read_register (4), (long) read_register (5), | |
1717 | (long) read_register (6), (long) read_register (7)); | |
1718 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
617daa0e CV |
1719 | (long) read_register (8), (long) read_register (9), |
1720 | (long) read_register (10), (long) read_register (11), | |
1721 | (long) read_register (12), (long) read_register (13), | |
1722 | (long) read_register (14), (long) read_register (15)); | |
cc17453a | 1723 | |
a6b0a3f3 AS |
1724 | printf_filtered ( |
1725 | (pr ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n" | |
1726 | : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), | |
cc17453a EZ |
1727 | (long) read_register (FP0_REGNUM + 0), |
1728 | (long) read_register (FP0_REGNUM + 1), | |
1729 | (long) read_register (FP0_REGNUM + 2), | |
1730 | (long) read_register (FP0_REGNUM + 3), | |
1731 | (long) read_register (FP0_REGNUM + 4), | |
1732 | (long) read_register (FP0_REGNUM + 5), | |
1733 | (long) read_register (FP0_REGNUM + 6), | |
1734 | (long) read_register (FP0_REGNUM + 7)); | |
a6b0a3f3 AS |
1735 | printf_filtered ( |
1736 | (pr ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n" | |
1737 | : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), | |
cc17453a EZ |
1738 | (long) read_register (FP0_REGNUM + 8), |
1739 | (long) read_register (FP0_REGNUM + 9), | |
1740 | (long) read_register (FP0_REGNUM + 10), | |
1741 | (long) read_register (FP0_REGNUM + 11), | |
1742 | (long) read_register (FP0_REGNUM + 12), | |
1743 | (long) read_register (FP0_REGNUM + 13), | |
1744 | (long) read_register (FP0_REGNUM + 14), | |
1745 | (long) read_register (FP0_REGNUM + 15)); | |
1746 | } | |
1747 | ||
474e5826 CV |
1748 | static void |
1749 | sh4_nofpu_show_regs (void) | |
1750 | { | |
a6b0a3f3 | 1751 | printf_filtered (" PC %s SR %08lx PR %08lx MACH %08lx\n", |
474e5826 CV |
1752 | paddr (read_register (PC_REGNUM)), |
1753 | (long) read_register (SR_REGNUM), | |
1754 | (long) read_register (PR_REGNUM), | |
a6b0a3f3 | 1755 | (long) read_register (MACH_REGNUM)); |
474e5826 | 1756 | |
a6b0a3f3 AS |
1757 | printf_filtered ( |
1758 | " GBR %08lx VBR %08lx MACL %08lx\n", | |
474e5826 | 1759 | (long) read_register (GBR_REGNUM), |
a6b0a3f3 AS |
1760 | (long) read_register (VBR_REGNUM), |
1761 | (long) read_register (MACL_REGNUM)); | |
1762 | printf_filtered ( | |
1763 | " SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n", | |
474e5826 | 1764 | (long) read_register (SSR_REGNUM), |
a6b0a3f3 AS |
1765 | (long) read_register (SPC_REGNUM), |
1766 | (long) read_register (FPUL_REGNUM), | |
1767 | (long) read_register (FPSCR_REGNUM)); | |
474e5826 | 1768 | |
a6b0a3f3 AS |
1769 | printf_filtered ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
1770 | (long) read_register (0), (long) read_register (1), | |
1771 | (long) read_register (2), (long) read_register (3), | |
1772 | (long) read_register (4), (long) read_register (5), | |
1773 | (long) read_register (6), (long) read_register (7)); | |
1774 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
474e5826 CV |
1775 | (long) read_register (8), (long) read_register (9), |
1776 | (long) read_register (10), (long) read_register (11), | |
1777 | (long) read_register (12), (long) read_register (13), | |
1778 | (long) read_register (14), (long) read_register (15)); | |
1779 | } | |
1780 | ||
cc17453a | 1781 | static void |
fba45db2 | 1782 | sh_dsp_show_regs (void) |
cc17453a | 1783 | { |
a6b0a3f3 AS |
1784 | |
1785 | printf_filtered (" PC %s SR %08lx PR %08lx MACH %08lx\n", | |
cc17453a | 1786 | paddr (read_register (PC_REGNUM)), |
55ff77ac CV |
1787 | (long) read_register (SR_REGNUM), |
1788 | (long) read_register (PR_REGNUM), | |
a6b0a3f3 | 1789 | (long) read_register (MACH_REGNUM)); |
cc17453a | 1790 | |
a6b0a3f3 AS |
1791 | printf_filtered ( |
1792 | " GBR %08lx VBR %08lx DSR %08lx MACL %08lx\n", | |
cc17453a | 1793 | (long) read_register (GBR_REGNUM), |
a6b0a3f3 AS |
1794 | (long) read_register (VBR_REGNUM), |
1795 | (long) read_register (DSR_REGNUM), | |
1796 | (long) read_register (MACL_REGNUM)); | |
617daa0e CV |
1797 | |
1798 | printf_filtered | |
a6b0a3f3 | 1799 | ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
617daa0e CV |
1800 | (long) read_register (0), (long) read_register (1), |
1801 | (long) read_register (2), (long) read_register (3), | |
1802 | (long) read_register (4), (long) read_register (5), | |
1803 | (long) read_register (6), (long) read_register (7)); | |
a6b0a3f3 | 1804 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
617daa0e CV |
1805 | (long) read_register (8), (long) read_register (9), |
1806 | (long) read_register (10), (long) read_register (11), | |
1807 | (long) read_register (12), (long) read_register (13), | |
1808 | (long) read_register (14), (long) read_register (15)); | |
1809 | ||
1810 | printf_filtered | |
1811 | ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n", | |
1812 | (long) read_register (A0G_REGNUM) & 0xff, | |
1813 | (long) read_register (A0_REGNUM), (long) read_register (M0_REGNUM), | |
1814 | (long) read_register (X0_REGNUM), (long) read_register (Y0_REGNUM), | |
1815 | (long) read_register (RS_REGNUM), (long) read_register (MOD_REGNUM)); | |
cc17453a | 1816 | printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n", |
f2ea0907 CV |
1817 | (long) read_register (A1G_REGNUM) & 0xff, |
1818 | (long) read_register (A1_REGNUM), | |
1819 | (long) read_register (M1_REGNUM), | |
1820 | (long) read_register (X1_REGNUM), | |
1821 | (long) read_register (Y1_REGNUM), | |
1822 | (long) read_register (RE_REGNUM)); | |
cc17453a EZ |
1823 | } |
1824 | ||
a78f21af AC |
1825 | static void |
1826 | sh_show_regs_command (char *args, int from_tty) | |
53116e27 EZ |
1827 | { |
1828 | if (sh_show_regs) | |
617daa0e | 1829 | (*sh_show_regs) (); |
53116e27 EZ |
1830 | } |
1831 | ||
da962468 CV |
1832 | static struct type * |
1833 | sh_sh2a_register_type (struct gdbarch *gdbarch, int reg_nr) | |
1834 | { | |
1835 | if ((reg_nr >= FP0_REGNUM | |
1836 | && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM)) | |
1837 | return builtin_type_float; | |
1838 | else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM) | |
1839 | return builtin_type_double; | |
1840 | else | |
1841 | return builtin_type_int; | |
1842 | } | |
1843 | ||
cc17453a EZ |
1844 | /* Return the GDB type object for the "standard" data type |
1845 | of data in register N. */ | |
cc17453a | 1846 | static struct type * |
48db5a3c | 1847 | sh_sh3e_register_type (struct gdbarch *gdbarch, int reg_nr) |
cc17453a EZ |
1848 | { |
1849 | if ((reg_nr >= FP0_REGNUM | |
617daa0e | 1850 | && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM)) |
cc17453a | 1851 | return builtin_type_float; |
8db62801 | 1852 | else |
cc17453a EZ |
1853 | return builtin_type_int; |
1854 | } | |
1855 | ||
7f4dbe94 EZ |
1856 | static struct type * |
1857 | sh_sh4_build_float_register_type (int high) | |
1858 | { | |
1859 | struct type *temp; | |
1860 | ||
1861 | temp = create_range_type (NULL, builtin_type_int, 0, high); | |
1862 | return create_array_type (NULL, builtin_type_float, temp); | |
1863 | } | |
1864 | ||
53116e27 | 1865 | static struct type * |
48db5a3c | 1866 | sh_sh4_register_type (struct gdbarch *gdbarch, int reg_nr) |
53116e27 EZ |
1867 | { |
1868 | if ((reg_nr >= FP0_REGNUM | |
617daa0e | 1869 | && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM)) |
53116e27 | 1870 | return builtin_type_float; |
617daa0e | 1871 | else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM) |
53116e27 | 1872 | return builtin_type_double; |
617daa0e | 1873 | else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM) |
53116e27 EZ |
1874 | return sh_sh4_build_float_register_type (3); |
1875 | else | |
1876 | return builtin_type_int; | |
1877 | } | |
1878 | ||
cc17453a | 1879 | static struct type * |
48db5a3c | 1880 | sh_default_register_type (struct gdbarch *gdbarch, int reg_nr) |
cc17453a EZ |
1881 | { |
1882 | return builtin_type_int; | |
1883 | } | |
1884 | ||
dda63807 AS |
1885 | /* Is a register in a reggroup? |
1886 | The default code in reggroup.c doesn't identify system registers, some | |
1887 | float registers or any of the vector registers. | |
1888 | TODO: sh2a and dsp registers. */ | |
1889 | int | |
1890 | sh_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
1891 | struct reggroup *reggroup) | |
1892 | { | |
1893 | if (REGISTER_NAME (regnum) == NULL | |
1894 | || *REGISTER_NAME (regnum) == '\0') | |
1895 | return 0; | |
1896 | ||
1897 | if (reggroup == float_reggroup | |
1898 | && (regnum == FPUL_REGNUM | |
1899 | || regnum == FPSCR_REGNUM)) | |
1900 | return 1; | |
1901 | ||
1902 | if (regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM) | |
1903 | { | |
1904 | if (reggroup == vector_reggroup || reggroup == float_reggroup) | |
1905 | return 1; | |
1906 | if (reggroup == general_reggroup) | |
1907 | return 0; | |
1908 | } | |
1909 | ||
1910 | if (regnum == VBR_REGNUM | |
1911 | || regnum == SR_REGNUM | |
1912 | || regnum == FPSCR_REGNUM | |
1913 | || regnum == SSR_REGNUM | |
1914 | || regnum == SPC_REGNUM) | |
1915 | { | |
1916 | if (reggroup == system_reggroup) | |
1917 | return 1; | |
1918 | if (reggroup == general_reggroup) | |
1919 | return 0; | |
1920 | } | |
1921 | ||
1922 | /* The default code can cope with any other registers. */ | |
1923 | return default_register_reggroup_p (gdbarch, regnum, reggroup); | |
1924 | } | |
1925 | ||
fb409745 EZ |
1926 | /* On the sh4, the DRi pseudo registers are problematic if the target |
1927 | is little endian. When the user writes one of those registers, for | |
1928 | instance with 'ser var $dr0=1', we want the double to be stored | |
1929 | like this: | |
1930 | fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f | |
1931 | fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00 | |
1932 | ||
1933 | This corresponds to little endian byte order & big endian word | |
1934 | order. However if we let gdb write the register w/o conversion, it | |
1935 | will write fr0 and fr1 this way: | |
1936 | fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00 | |
1937 | fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f | |
1938 | because it will consider fr0 and fr1 as a single LE stretch of memory. | |
1939 | ||
1940 | To achieve what we want we must force gdb to store things in | |
1941 | floatformat_ieee_double_littlebyte_bigword (which is defined in | |
1942 | include/floatformat.h and libiberty/floatformat.c. | |
1943 | ||
1944 | In case the target is big endian, there is no problem, the | |
1945 | raw bytes will look like: | |
1946 | fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00 | |
1947 | fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00 | |
1948 | ||
1949 | The other pseudo registers (the FVs) also don't pose a problem | |
1950 | because they are stored as 4 individual FP elements. */ | |
1951 | ||
7bd872fe | 1952 | static void |
b66ba949 CV |
1953 | sh_register_convert_to_virtual (int regnum, struct type *type, |
1954 | char *from, char *to) | |
55ff77ac | 1955 | { |
617daa0e | 1956 | if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM) |
283150cd EZ |
1957 | { |
1958 | DOUBLEST val; | |
617daa0e CV |
1959 | floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, |
1960 | from, &val); | |
55ff77ac | 1961 | store_typed_floating (to, type, val); |
283150cd EZ |
1962 | } |
1963 | else | |
617daa0e CV |
1964 | error |
1965 | ("sh_register_convert_to_virtual called with non DR register number"); | |
283150cd EZ |
1966 | } |
1967 | ||
1968 | static void | |
b66ba949 CV |
1969 | sh_register_convert_to_raw (struct type *type, int regnum, |
1970 | const void *from, void *to) | |
283150cd | 1971 | { |
617daa0e | 1972 | if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM) |
283150cd | 1973 | { |
48db5a3c | 1974 | DOUBLEST val = extract_typed_floating (from, type); |
617daa0e CV |
1975 | floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword, |
1976 | &val, to); | |
283150cd EZ |
1977 | } |
1978 | else | |
8a3fe4f8 | 1979 | error (_("sh_register_convert_to_raw called with non DR register number")); |
283150cd EZ |
1980 | } |
1981 | ||
1c0159e0 CV |
1982 | /* For vectors of 4 floating point registers. */ |
1983 | static int | |
1984 | fv_reg_base_num (int fv_regnum) | |
1985 | { | |
1986 | int fp_regnum; | |
1987 | ||
617daa0e | 1988 | fp_regnum = FP0_REGNUM + (fv_regnum - FV0_REGNUM) * 4; |
1c0159e0 CV |
1989 | return fp_regnum; |
1990 | } | |
1991 | ||
1992 | /* For double precision floating point registers, i.e 2 fp regs.*/ | |
1993 | static int | |
1994 | dr_reg_base_num (int dr_regnum) | |
1995 | { | |
1996 | int fp_regnum; | |
1997 | ||
617daa0e | 1998 | fp_regnum = FP0_REGNUM + (dr_regnum - DR0_REGNUM) * 2; |
1c0159e0 CV |
1999 | return fp_regnum; |
2000 | } | |
2001 | ||
a78f21af | 2002 | static void |
d8124050 | 2003 | sh_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, |
18cf8b5b | 2004 | int reg_nr, gdb_byte *buffer) |
53116e27 EZ |
2005 | { |
2006 | int base_regnum, portion; | |
d9d9c31f | 2007 | char temp_buffer[MAX_REGISTER_SIZE]; |
53116e27 | 2008 | |
9bed62d7 CV |
2009 | if (reg_nr == PSEUDO_BANK_REGNUM) |
2010 | regcache_raw_read (regcache, BANK_REGNUM, buffer); | |
2011 | else | |
617daa0e | 2012 | if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM) |
7bd872fe EZ |
2013 | { |
2014 | base_regnum = dr_reg_base_num (reg_nr); | |
2015 | ||
617daa0e | 2016 | /* Build the value in the provided buffer. */ |
7bd872fe EZ |
2017 | /* Read the real regs for which this one is an alias. */ |
2018 | for (portion = 0; portion < 2; portion++) | |
617daa0e | 2019 | regcache_raw_read (regcache, base_regnum + portion, |
0818c12a | 2020 | (temp_buffer |
617daa0e CV |
2021 | + register_size (gdbarch, |
2022 | base_regnum) * portion)); | |
7bd872fe | 2023 | /* We must pay attention to the endiannes. */ |
b66ba949 | 2024 | sh_register_convert_to_virtual (reg_nr, |
7b9ee6a8 | 2025 | register_type (gdbarch, reg_nr), |
b66ba949 | 2026 | temp_buffer, buffer); |
7bd872fe | 2027 | } |
617daa0e | 2028 | else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM) |
53116e27 | 2029 | { |
7bd872fe EZ |
2030 | base_regnum = fv_reg_base_num (reg_nr); |
2031 | ||
2032 | /* Read the real regs for which this one is an alias. */ | |
2033 | for (portion = 0; portion < 4; portion++) | |
617daa0e | 2034 | regcache_raw_read (regcache, base_regnum + portion, |
d8124050 | 2035 | ((char *) buffer |
617daa0e CV |
2036 | + register_size (gdbarch, |
2037 | base_regnum) * portion)); | |
53116e27 EZ |
2038 | } |
2039 | } | |
2040 | ||
a78f21af | 2041 | static void |
d8124050 | 2042 | sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, |
18cf8b5b | 2043 | int reg_nr, const gdb_byte *buffer) |
53116e27 EZ |
2044 | { |
2045 | int base_regnum, portion; | |
d9d9c31f | 2046 | char temp_buffer[MAX_REGISTER_SIZE]; |
53116e27 | 2047 | |
9bed62d7 CV |
2048 | if (reg_nr == PSEUDO_BANK_REGNUM) |
2049 | { | |
2050 | /* When the bank register is written to, the whole register bank | |
2051 | is switched and all values in the bank registers must be read | |
2052 | from the target/sim again. We're just invalidating the regcache | |
2053 | so that a re-read happens next time it's necessary. */ | |
2054 | int bregnum; | |
2055 | ||
2056 | regcache_raw_write (regcache, BANK_REGNUM, buffer); | |
2057 | for (bregnum = R0_BANK0_REGNUM; bregnum < MACLB_REGNUM; ++bregnum) | |
9c5ea4d9 | 2058 | regcache_invalidate (regcache, bregnum); |
9bed62d7 CV |
2059 | } |
2060 | else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM) | |
53116e27 EZ |
2061 | { |
2062 | base_regnum = dr_reg_base_num (reg_nr); | |
2063 | ||
7bd872fe | 2064 | /* We must pay attention to the endiannes. */ |
7b9ee6a8 | 2065 | sh_register_convert_to_raw (register_type (gdbarch, reg_nr), |
b66ba949 | 2066 | reg_nr, buffer, temp_buffer); |
7bd872fe | 2067 | |
53116e27 EZ |
2068 | /* Write the real regs for which this one is an alias. */ |
2069 | for (portion = 0; portion < 2; portion++) | |
617daa0e | 2070 | regcache_raw_write (regcache, base_regnum + portion, |
0818c12a | 2071 | (temp_buffer |
617daa0e CV |
2072 | + register_size (gdbarch, |
2073 | base_regnum) * portion)); | |
53116e27 | 2074 | } |
617daa0e | 2075 | else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM) |
53116e27 EZ |
2076 | { |
2077 | base_regnum = fv_reg_base_num (reg_nr); | |
2078 | ||
2079 | /* Write the real regs for which this one is an alias. */ | |
2080 | for (portion = 0; portion < 4; portion++) | |
d8124050 AC |
2081 | regcache_raw_write (regcache, base_regnum + portion, |
2082 | ((char *) buffer | |
617daa0e CV |
2083 | + register_size (gdbarch, |
2084 | base_regnum) * portion)); | |
53116e27 EZ |
2085 | } |
2086 | } | |
2087 | ||
2f14585c JR |
2088 | static int |
2089 | sh_dsp_register_sim_regno (int nr) | |
2090 | { | |
2091 | if (legacy_register_sim_regno (nr) < 0) | |
2092 | return legacy_register_sim_regno (nr); | |
f2ea0907 CV |
2093 | if (nr >= DSR_REGNUM && nr <= Y1_REGNUM) |
2094 | return nr - DSR_REGNUM + SIM_SH_DSR_REGNUM; | |
2095 | if (nr == MOD_REGNUM) | |
2f14585c | 2096 | return SIM_SH_MOD_REGNUM; |
f2ea0907 | 2097 | if (nr == RS_REGNUM) |
2f14585c | 2098 | return SIM_SH_RS_REGNUM; |
f2ea0907 | 2099 | if (nr == RE_REGNUM) |
2f14585c | 2100 | return SIM_SH_RE_REGNUM; |
76cd2bd9 CV |
2101 | if (nr >= DSP_R0_BANK_REGNUM && nr <= DSP_R7_BANK_REGNUM) |
2102 | return nr - DSP_R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM; | |
2f14585c JR |
2103 | return nr; |
2104 | } | |
1c0159e0 | 2105 | |
da962468 CV |
2106 | static int |
2107 | sh_sh2a_register_sim_regno (int nr) | |
2108 | { | |
2109 | switch (nr) | |
2110 | { | |
2111 | case TBR_REGNUM: | |
2112 | return SIM_SH_TBR_REGNUM; | |
2113 | case IBNR_REGNUM: | |
2114 | return SIM_SH_IBNR_REGNUM; | |
2115 | case IBCR_REGNUM: | |
2116 | return SIM_SH_IBCR_REGNUM; | |
2117 | case BANK_REGNUM: | |
2118 | return SIM_SH_BANK_REGNUM; | |
2119 | case MACLB_REGNUM: | |
2120 | return SIM_SH_BANK_MACL_REGNUM; | |
2121 | case GBRB_REGNUM: | |
2122 | return SIM_SH_BANK_GBR_REGNUM; | |
2123 | case PRB_REGNUM: | |
2124 | return SIM_SH_BANK_PR_REGNUM; | |
2125 | case IVNB_REGNUM: | |
2126 | return SIM_SH_BANK_IVN_REGNUM; | |
2127 | case MACHB_REGNUM: | |
2128 | return SIM_SH_BANK_MACH_REGNUM; | |
2129 | default: | |
2130 | break; | |
2131 | } | |
2132 | return legacy_register_sim_regno (nr); | |
2133 | } | |
2134 | ||
357d3800 AS |
2135 | /* Set up the register unwinding such that call-clobbered registers are |
2136 | not displayed in frames >0 because the true value is not certain. | |
2137 | The 'undefined' registers will show up as 'not available' unless the | |
2138 | CFI says otherwise. | |
2139 | ||
2140 | This function is currently set up for SH4 and compatible only. */ | |
2141 | ||
2142 | static void | |
2143 | sh_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
aff37fc1 DM |
2144 | struct dwarf2_frame_state_reg *reg, |
2145 | struct frame_info *next_frame) | |
357d3800 AS |
2146 | { |
2147 | /* Mark the PC as the destination for the return address. */ | |
2148 | if (regnum == PC_REGNUM) | |
2149 | reg->how = DWARF2_FRAME_REG_RA; | |
2150 | ||
2151 | /* Mark the stack pointer as the call frame address. */ | |
2152 | else if (regnum == SP_REGNUM) | |
2153 | reg->how = DWARF2_FRAME_REG_CFA; | |
2154 | ||
2155 | /* The above was taken from the default init_reg in dwarf2-frame.c | |
2156 | while the below is SH specific. */ | |
2157 | ||
2158 | /* Caller save registers. */ | |
2159 | else if ((regnum >= R0_REGNUM && regnum <= R0_REGNUM+7) | |
2160 | || (regnum >= FR0_REGNUM && regnum <= FR0_REGNUM+11) | |
2161 | || (regnum >= DR0_REGNUM && regnum <= DR0_REGNUM+5) | |
2162 | || (regnum >= FV0_REGNUM && regnum <= FV0_REGNUM+2) | |
2163 | || (regnum == MACH_REGNUM) | |
2164 | || (regnum == MACL_REGNUM) | |
2165 | || (regnum == FPUL_REGNUM) | |
2166 | || (regnum == SR_REGNUM)) | |
2167 | reg->how = DWARF2_FRAME_REG_UNDEFINED; | |
2168 | ||
2169 | /* Callee save registers. */ | |
2170 | else if ((regnum >= R0_REGNUM+8 && regnum <= R0_REGNUM+15) | |
2171 | || (regnum >= FR0_REGNUM+12 && regnum <= FR0_REGNUM+15) | |
2172 | || (regnum >= DR0_REGNUM+6 && regnum <= DR0_REGNUM+8) | |
2173 | || (regnum == FV0_REGNUM+3)) | |
2174 | reg->how = DWARF2_FRAME_REG_SAME_VALUE; | |
2175 | ||
2176 | /* Other registers. These are not in the ABI and may or may not | |
2177 | mean anything in frames >0 so don't show them. */ | |
2178 | else if ((regnum >= R0_BANK0_REGNUM && regnum <= R0_BANK0_REGNUM+15) | |
2179 | || (regnum == GBR_REGNUM) | |
2180 | || (regnum == VBR_REGNUM) | |
2181 | || (regnum == FPSCR_REGNUM) | |
2182 | || (regnum == SSR_REGNUM) | |
2183 | || (regnum == SPC_REGNUM)) | |
2184 | reg->how = DWARF2_FRAME_REG_UNDEFINED; | |
2185 | } | |
2186 | ||
1c0159e0 CV |
2187 | static struct sh_frame_cache * |
2188 | sh_alloc_frame_cache (void) | |
2189 | { | |
2190 | struct sh_frame_cache *cache; | |
2191 | int i; | |
2192 | ||
2193 | cache = FRAME_OBSTACK_ZALLOC (struct sh_frame_cache); | |
2194 | ||
2195 | /* Base address. */ | |
2196 | cache->base = 0; | |
2197 | cache->saved_sp = 0; | |
2198 | cache->sp_offset = 0; | |
2199 | cache->pc = 0; | |
2200 | ||
2201 | /* Frameless until proven otherwise. */ | |
2202 | cache->uses_fp = 0; | |
617daa0e | 2203 | |
1c0159e0 CV |
2204 | /* Saved registers. We initialize these to -1 since zero is a valid |
2205 | offset (that's where fp is supposed to be stored). */ | |
2206 | for (i = 0; i < SH_NUM_REGS; i++) | |
2207 | { | |
2208 | cache->saved_regs[i] = -1; | |
2209 | } | |
617daa0e | 2210 | |
1c0159e0 | 2211 | return cache; |
617daa0e | 2212 | } |
1c0159e0 CV |
2213 | |
2214 | static struct sh_frame_cache * | |
2215 | sh_frame_cache (struct frame_info *next_frame, void **this_cache) | |
2216 | { | |
2217 | struct sh_frame_cache *cache; | |
2218 | CORE_ADDR current_pc; | |
2219 | int i; | |
2220 | ||
2221 | if (*this_cache) | |
2222 | return *this_cache; | |
2223 | ||
2224 | cache = sh_alloc_frame_cache (); | |
2225 | *this_cache = cache; | |
2226 | ||
2227 | /* In principle, for normal frames, fp holds the frame pointer, | |
2228 | which holds the base address for the current stack frame. | |
2229 | However, for functions that don't need it, the frame pointer is | |
2230 | optional. For these "frameless" functions the frame pointer is | |
2231 | actually the frame pointer of the calling frame. */ | |
2232 | cache->base = frame_unwind_register_unsigned (next_frame, FP_REGNUM); | |
2233 | if (cache->base == 0) | |
2234 | return cache; | |
2235 | ||
93d42b30 | 2236 | cache->pc = frame_func_unwind (next_frame, NORMAL_FRAME); |
1c0159e0 CV |
2237 | current_pc = frame_pc_unwind (next_frame); |
2238 | if (cache->pc != 0) | |
2239 | sh_analyze_prologue (cache->pc, current_pc, cache); | |
617daa0e | 2240 | |
1c0159e0 CV |
2241 | if (!cache->uses_fp) |
2242 | { | |
2243 | /* We didn't find a valid frame, which means that CACHE->base | |
2244 | currently holds the frame pointer for our calling frame. If | |
2245 | we're at the start of a function, or somewhere half-way its | |
2246 | prologue, the function's frame probably hasn't been fully | |
2247 | setup yet. Try to reconstruct the base address for the stack | |
2248 | frame by looking at the stack pointer. For truly "frameless" | |
2249 | functions this might work too. */ | |
2250 | cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM); | |
2251 | } | |
2252 | ||
2253 | /* Now that we have the base address for the stack frame we can | |
2254 | calculate the value of sp in the calling frame. */ | |
2255 | cache->saved_sp = cache->base + cache->sp_offset; | |
2256 | ||
2257 | /* Adjust all the saved registers such that they contain addresses | |
2258 | instead of offsets. */ | |
2259 | for (i = 0; i < SH_NUM_REGS; i++) | |
2260 | if (cache->saved_regs[i] != -1) | |
2261 | cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i] - 4; | |
2262 | ||
2263 | return cache; | |
2264 | } | |
2265 | ||
2266 | static void | |
2267 | sh_frame_prev_register (struct frame_info *next_frame, void **this_cache, | |
2268 | int regnum, int *optimizedp, | |
2269 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
18cf8b5b | 2270 | int *realnump, gdb_byte *valuep) |
1c0159e0 CV |
2271 | { |
2272 | struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache); | |
2273 | ||
2274 | gdb_assert (regnum >= 0); | |
2275 | ||
2276 | if (regnum == SP_REGNUM && cache->saved_sp) | |
2277 | { | |
2278 | *optimizedp = 0; | |
2279 | *lvalp = not_lval; | |
2280 | *addrp = 0; | |
2281 | *realnump = -1; | |
2282 | if (valuep) | |
617daa0e CV |
2283 | { |
2284 | /* Store the value. */ | |
2285 | store_unsigned_integer (valuep, 4, cache->saved_sp); | |
2286 | } | |
1c0159e0 CV |
2287 | return; |
2288 | } | |
2289 | ||
2290 | /* The PC of the previous frame is stored in the PR register of | |
2291 | the current frame. Frob regnum so that we pull the value from | |
2292 | the correct place. */ | |
2293 | if (regnum == PC_REGNUM) | |
2294 | regnum = PR_REGNUM; | |
2295 | ||
2296 | if (regnum < SH_NUM_REGS && cache->saved_regs[regnum] != -1) | |
2297 | { | |
2298 | *optimizedp = 0; | |
2299 | *lvalp = lval_memory; | |
2300 | *addrp = cache->saved_regs[regnum]; | |
2301 | *realnump = -1; | |
2302 | if (valuep) | |
617daa0e CV |
2303 | { |
2304 | /* Read the value in from memory. */ | |
2305 | read_memory (*addrp, valuep, | |
2306 | register_size (current_gdbarch, regnum)); | |
2307 | } | |
1c0159e0 CV |
2308 | return; |
2309 | } | |
2310 | ||
00b25ff3 AC |
2311 | *optimizedp = 0; |
2312 | *lvalp = lval_register; | |
2313 | *addrp = 0; | |
2314 | *realnump = regnum; | |
2315 | if (valuep) | |
2316 | frame_unwind_register (next_frame, (*realnump), valuep); | |
1c0159e0 CV |
2317 | } |
2318 | ||
2319 | static void | |
2320 | sh_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
617daa0e CV |
2321 | struct frame_id *this_id) |
2322 | { | |
1c0159e0 CV |
2323 | struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache); |
2324 | ||
2325 | /* This marks the outermost frame. */ | |
2326 | if (cache->base == 0) | |
2327 | return; | |
2328 | ||
2329 | *this_id = frame_id_build (cache->saved_sp, cache->pc); | |
617daa0e | 2330 | } |
1c0159e0 | 2331 | |
617daa0e | 2332 | static const struct frame_unwind sh_frame_unwind = { |
1c0159e0 CV |
2333 | NORMAL_FRAME, |
2334 | sh_frame_this_id, | |
2335 | sh_frame_prev_register | |
2336 | }; | |
2337 | ||
2338 | static const struct frame_unwind * | |
2339 | sh_frame_sniffer (struct frame_info *next_frame) | |
2340 | { | |
2341 | return &sh_frame_unwind; | |
2342 | } | |
2343 | ||
2344 | static CORE_ADDR | |
2345 | sh_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
2346 | { | |
2347 | return frame_unwind_register_unsigned (next_frame, SP_REGNUM); | |
2348 | } | |
2349 | ||
2350 | static CORE_ADDR | |
2351 | sh_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
2352 | { | |
2353 | return frame_unwind_register_unsigned (next_frame, PC_REGNUM); | |
2354 | } | |
2355 | ||
2356 | static struct frame_id | |
2357 | sh_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
2358 | { | |
2359 | return frame_id_build (sh_unwind_sp (gdbarch, next_frame), | |
2360 | frame_pc_unwind (next_frame)); | |
2361 | } | |
2362 | ||
2363 | static CORE_ADDR | |
2364 | sh_frame_base_address (struct frame_info *next_frame, void **this_cache) | |
617daa0e | 2365 | { |
1c0159e0 | 2366 | struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache); |
617daa0e | 2367 | |
1c0159e0 CV |
2368 | return cache->base; |
2369 | } | |
617daa0e CV |
2370 | |
2371 | static const struct frame_base sh_frame_base = { | |
1c0159e0 CV |
2372 | &sh_frame_unwind, |
2373 | sh_frame_base_address, | |
2374 | sh_frame_base_address, | |
2375 | sh_frame_base_address | |
617daa0e | 2376 | }; |
1c0159e0 CV |
2377 | |
2378 | /* The epilogue is defined here as the area at the end of a function, | |
2379 | either on the `ret' instruction itself or after an instruction which | |
2380 | destroys the function's stack frame. */ | |
2381 | static int | |
2382 | sh_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
2383 | { | |
2384 | CORE_ADDR func_addr = 0, func_end = 0; | |
2385 | ||
2386 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
2387 | { | |
2388 | ULONGEST inst; | |
2389 | /* The sh epilogue is max. 14 bytes long. Give another 14 bytes | |
2390 | for a nop and some fixed data (e.g. big offsets) which are | |
617daa0e CV |
2391 | unfortunately also treated as part of the function (which |
2392 | means, they are below func_end. */ | |
1c0159e0 CV |
2393 | CORE_ADDR addr = func_end - 28; |
2394 | if (addr < func_addr + 4) | |
617daa0e | 2395 | addr = func_addr + 4; |
1c0159e0 CV |
2396 | if (pc < addr) |
2397 | return 0; | |
2398 | ||
2399 | /* First search forward until hitting an rts. */ | |
2400 | while (addr < func_end | |
617daa0e | 2401 | && !IS_RTS (read_memory_unsigned_integer (addr, 2))) |
1c0159e0 CV |
2402 | addr += 2; |
2403 | if (addr >= func_end) | |
617daa0e | 2404 | return 0; |
1c0159e0 CV |
2405 | |
2406 | /* At this point we should find a mov.l @r15+,r14 instruction, | |
2407 | either before or after the rts. If not, then the function has | |
617daa0e | 2408 | probably no "normal" epilogue and we bail out here. */ |
1c0159e0 CV |
2409 | inst = read_memory_unsigned_integer (addr - 2, 2); |
2410 | if (IS_RESTORE_FP (read_memory_unsigned_integer (addr - 2, 2))) | |
617daa0e | 2411 | addr -= 2; |
1c0159e0 CV |
2412 | else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr + 2, 2))) |
2413 | return 0; | |
2414 | ||
1c0159e0 | 2415 | inst = read_memory_unsigned_integer (addr - 2, 2); |
03131d99 CV |
2416 | |
2417 | /* Step over possible lds.l @r15+,macl. */ | |
2418 | if (IS_MACL_LDS (inst)) | |
2419 | { | |
2420 | addr -= 2; | |
2421 | inst = read_memory_unsigned_integer (addr - 2, 2); | |
2422 | } | |
2423 | ||
2424 | /* Step over possible lds.l @r15+,pr. */ | |
1c0159e0 | 2425 | if (IS_LDS (inst)) |
617daa0e | 2426 | { |
1c0159e0 CV |
2427 | addr -= 2; |
2428 | inst = read_memory_unsigned_integer (addr - 2, 2); | |
2429 | } | |
2430 | ||
2431 | /* Step over possible mov r14,r15. */ | |
2432 | if (IS_MOV_FP_SP (inst)) | |
617daa0e | 2433 | { |
1c0159e0 CV |
2434 | addr -= 2; |
2435 | inst = read_memory_unsigned_integer (addr - 2, 2); | |
2436 | } | |
2437 | ||
2438 | /* Now check for FP adjustments, using add #imm,r14 or add rX, r14 | |
2439 | instructions. */ | |
2440 | while (addr > func_addr + 4 | |
617daa0e | 2441 | && (IS_ADD_REG_TO_FP (inst) || IS_ADD_IMM_FP (inst))) |
1c0159e0 CV |
2442 | { |
2443 | addr -= 2; | |
2444 | inst = read_memory_unsigned_integer (addr - 2, 2); | |
2445 | } | |
2446 | ||
03131d99 CV |
2447 | /* On SH2a check if the previous instruction was perhaps a MOVI20. |
2448 | That's allowed for the epilogue. */ | |
2449 | if ((gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a | |
2450 | || gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a_nofpu) | |
2451 | && addr > func_addr + 6 | |
2452 | && IS_MOVI20 (read_memory_unsigned_integer (addr - 4, 2))) | |
2453 | addr -= 4; | |
2454 | ||
1c0159e0 CV |
2455 | if (pc >= addr) |
2456 | return 1; | |
2457 | } | |
2458 | return 0; | |
2459 | } | |
ccf00f21 | 2460 | \f |
cc17453a EZ |
2461 | |
2462 | static struct gdbarch * | |
fba45db2 | 2463 | sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
cc17453a | 2464 | { |
cc17453a | 2465 | struct gdbarch *gdbarch; |
d658f924 | 2466 | |
55ff77ac CV |
2467 | sh_show_regs = sh_generic_show_regs; |
2468 | switch (info.bfd_arch_info->mach) | |
2469 | { | |
617daa0e CV |
2470 | case bfd_mach_sh2e: |
2471 | sh_show_regs = sh2e_show_regs; | |
2472 | break; | |
da962468 CV |
2473 | case bfd_mach_sh2a: |
2474 | sh_show_regs = sh2a_show_regs; | |
2475 | break; | |
2476 | case bfd_mach_sh2a_nofpu: | |
2477 | sh_show_regs = sh2a_nofpu_show_regs; | |
2478 | break; | |
617daa0e CV |
2479 | case bfd_mach_sh_dsp: |
2480 | sh_show_regs = sh_dsp_show_regs; | |
2481 | break; | |
55ff77ac | 2482 | |
617daa0e CV |
2483 | case bfd_mach_sh3: |
2484 | sh_show_regs = sh3_show_regs; | |
2485 | break; | |
55ff77ac | 2486 | |
617daa0e CV |
2487 | case bfd_mach_sh3e: |
2488 | sh_show_regs = sh3e_show_regs; | |
2489 | break; | |
55ff77ac | 2490 | |
617daa0e | 2491 | case bfd_mach_sh3_dsp: |
474e5826 | 2492 | case bfd_mach_sh4al_dsp: |
617daa0e CV |
2493 | sh_show_regs = sh3_dsp_show_regs; |
2494 | break; | |
55ff77ac | 2495 | |
617daa0e | 2496 | case bfd_mach_sh4: |
474e5826 | 2497 | case bfd_mach_sh4a: |
617daa0e CV |
2498 | sh_show_regs = sh4_show_regs; |
2499 | break; | |
55ff77ac | 2500 | |
474e5826 CV |
2501 | case bfd_mach_sh4_nofpu: |
2502 | case bfd_mach_sh4a_nofpu: | |
2503 | sh_show_regs = sh4_nofpu_show_regs; | |
2504 | break; | |
2505 | ||
617daa0e CV |
2506 | case bfd_mach_sh5: |
2507 | sh_show_regs = sh64_show_regs; | |
2508 | /* SH5 is handled entirely in sh64-tdep.c */ | |
2509 | return sh64_gdbarch_init (info, arches); | |
55ff77ac CV |
2510 | } |
2511 | ||
4be87837 DJ |
2512 | /* If there is already a candidate, use it. */ |
2513 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
2514 | if (arches != NULL) | |
2515 | return arches->gdbarch; | |
cc17453a EZ |
2516 | |
2517 | /* None found, create a new architecture from the information | |
2518 | provided. */ | |
f2ea0907 | 2519 | gdbarch = gdbarch_alloc (&info, NULL); |
cc17453a | 2520 | |
48db5a3c CV |
2521 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); |
2522 | set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
ec920329 | 2523 | set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
48db5a3c CV |
2524 | set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); |
2525 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
2526 | set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
2527 | set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
a38d2a54 | 2528 | set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
48db5a3c | 2529 | |
f2ea0907 | 2530 | set_gdbarch_num_regs (gdbarch, SH_NUM_REGS); |
a38d2a54 | 2531 | set_gdbarch_sp_regnum (gdbarch, 15); |
a38d2a54 | 2532 | set_gdbarch_pc_regnum (gdbarch, 16); |
48db5a3c CV |
2533 | set_gdbarch_fp0_regnum (gdbarch, -1); |
2534 | set_gdbarch_num_pseudo_regs (gdbarch, 0); | |
2535 | ||
1c0159e0 | 2536 | set_gdbarch_register_type (gdbarch, sh_default_register_type); |
dda63807 | 2537 | set_gdbarch_register_reggroup_p (gdbarch, sh_register_reggroup_p); |
1c0159e0 | 2538 | |
eaf90c5d | 2539 | set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc); |
48db5a3c | 2540 | |
2bf0cb65 | 2541 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_sh); |
2f14585c | 2542 | set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno); |
48db5a3c CV |
2543 | |
2544 | set_gdbarch_write_pc (gdbarch, generic_target_write_pc); | |
2545 | ||
c0409442 CV |
2546 | set_gdbarch_return_value (gdbarch, sh_return_value_nofpu); |
2547 | set_gdbarch_deprecated_extract_struct_value_address (gdbarch, | |
2548 | sh_extract_struct_value_address); | |
1c0159e0 | 2549 | |
48db5a3c CV |
2550 | set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue); |
2551 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
48db5a3c | 2552 | |
1c0159e0 CV |
2553 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu); |
2554 | ||
48db5a3c CV |
2555 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); |
2556 | ||
19f59343 | 2557 | set_gdbarch_frame_align (gdbarch, sh_frame_align); |
1c0159e0 CV |
2558 | set_gdbarch_unwind_sp (gdbarch, sh_unwind_sp); |
2559 | set_gdbarch_unwind_pc (gdbarch, sh_unwind_pc); | |
2560 | set_gdbarch_unwind_dummy_id (gdbarch, sh_unwind_dummy_id); | |
2561 | frame_base_set_default (gdbarch, &sh_frame_base); | |
2562 | ||
617daa0e | 2563 | set_gdbarch_in_function_epilogue_p (gdbarch, sh_in_function_epilogue_p); |
cc17453a | 2564 | |
357d3800 AS |
2565 | dwarf2_frame_set_init_reg (gdbarch, sh_dwarf2_frame_init_reg); |
2566 | ||
cc17453a | 2567 | switch (info.bfd_arch_info->mach) |
8db62801 | 2568 | { |
cc17453a | 2569 | case bfd_mach_sh: |
48db5a3c | 2570 | set_gdbarch_register_name (gdbarch, sh_sh_register_name); |
cc17453a | 2571 | break; |
1c0159e0 | 2572 | |
cc17453a | 2573 | case bfd_mach_sh2: |
48db5a3c | 2574 | set_gdbarch_register_name (gdbarch, sh_sh_register_name); |
617daa0e | 2575 | break; |
1c0159e0 | 2576 | |
2d188dd3 | 2577 | case bfd_mach_sh2e: |
48db5a3c CV |
2578 | /* doubles on sh2e and sh3e are actually 4 byte. */ |
2579 | set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
2580 | ||
2581 | set_gdbarch_register_name (gdbarch, sh_sh2e_register_name); | |
48db5a3c | 2582 | set_gdbarch_register_type (gdbarch, sh_sh3e_register_type); |
2d188dd3 | 2583 | set_gdbarch_fp0_regnum (gdbarch, 25); |
c0409442 | 2584 | set_gdbarch_return_value (gdbarch, sh_return_value_fpu); |
6df2bf50 | 2585 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); |
2d188dd3 | 2586 | break; |
1c0159e0 | 2587 | |
da962468 CV |
2588 | case bfd_mach_sh2a: |
2589 | set_gdbarch_register_name (gdbarch, sh_sh2a_register_name); | |
2590 | set_gdbarch_register_type (gdbarch, sh_sh2a_register_type); | |
2591 | set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno); | |
2592 | ||
2593 | set_gdbarch_fp0_regnum (gdbarch, 25); | |
2594 | set_gdbarch_num_pseudo_regs (gdbarch, 9); | |
2595 | set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read); | |
2596 | set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write); | |
c0409442 | 2597 | set_gdbarch_return_value (gdbarch, sh_return_value_fpu); |
da962468 CV |
2598 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); |
2599 | break; | |
2600 | ||
2601 | case bfd_mach_sh2a_nofpu: | |
2602 | set_gdbarch_register_name (gdbarch, sh_sh2a_nofpu_register_name); | |
2603 | set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno); | |
2604 | ||
2605 | set_gdbarch_num_pseudo_regs (gdbarch, 1); | |
2606 | set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read); | |
2607 | set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write); | |
2608 | break; | |
2609 | ||
cc17453a | 2610 | case bfd_mach_sh_dsp: |
48db5a3c | 2611 | set_gdbarch_register_name (gdbarch, sh_sh_dsp_register_name); |
2f14585c | 2612 | set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno); |
cc17453a | 2613 | break; |
1c0159e0 | 2614 | |
cc17453a | 2615 | case bfd_mach_sh3: |
4e6cbc38 AS |
2616 | case bfd_mach_sh3_nommu: |
2617 | case bfd_mach_sh2a_nofpu_or_sh3_nommu: | |
48db5a3c | 2618 | set_gdbarch_register_name (gdbarch, sh_sh3_register_name); |
cc17453a | 2619 | break; |
1c0159e0 | 2620 | |
cc17453a | 2621 | case bfd_mach_sh3e: |
4e6cbc38 | 2622 | case bfd_mach_sh2a_or_sh3e: |
48db5a3c CV |
2623 | /* doubles on sh2e and sh3e are actually 4 byte. */ |
2624 | set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
2625 | ||
2626 | set_gdbarch_register_name (gdbarch, sh_sh3e_register_name); | |
48db5a3c | 2627 | set_gdbarch_register_type (gdbarch, sh_sh3e_register_type); |
cc17453a | 2628 | set_gdbarch_fp0_regnum (gdbarch, 25); |
c0409442 | 2629 | set_gdbarch_return_value (gdbarch, sh_return_value_fpu); |
6df2bf50 | 2630 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); |
cc17453a | 2631 | break; |
1c0159e0 | 2632 | |
cc17453a | 2633 | case bfd_mach_sh3_dsp: |
48db5a3c | 2634 | set_gdbarch_register_name (gdbarch, sh_sh3_dsp_register_name); |
48db5a3c | 2635 | set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno); |
cc17453a | 2636 | break; |
1c0159e0 | 2637 | |
cc17453a | 2638 | case bfd_mach_sh4: |
474e5826 | 2639 | case bfd_mach_sh4a: |
48db5a3c | 2640 | set_gdbarch_register_name (gdbarch, sh_sh4_register_name); |
48db5a3c | 2641 | set_gdbarch_register_type (gdbarch, sh_sh4_register_type); |
cc17453a | 2642 | set_gdbarch_fp0_regnum (gdbarch, 25); |
da962468 | 2643 | set_gdbarch_num_pseudo_regs (gdbarch, 13); |
d8124050 AC |
2644 | set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read); |
2645 | set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write); | |
c0409442 | 2646 | set_gdbarch_return_value (gdbarch, sh_return_value_fpu); |
6df2bf50 | 2647 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); |
cc17453a | 2648 | break; |
1c0159e0 | 2649 | |
474e5826 CV |
2650 | case bfd_mach_sh4_nofpu: |
2651 | case bfd_mach_sh4a_nofpu: | |
4e6cbc38 AS |
2652 | case bfd_mach_sh4_nommu_nofpu: |
2653 | case bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu: | |
2654 | case bfd_mach_sh2a_or_sh4: | |
474e5826 CV |
2655 | set_gdbarch_register_name (gdbarch, sh_sh4_nofpu_register_name); |
2656 | break; | |
2657 | ||
2658 | case bfd_mach_sh4al_dsp: | |
2659 | set_gdbarch_register_name (gdbarch, sh_sh4al_dsp_register_name); | |
2660 | set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno); | |
2661 | break; | |
2662 | ||
cc17453a | 2663 | default: |
b58cbbf2 | 2664 | set_gdbarch_register_name (gdbarch, sh_sh_register_name); |
cc17453a | 2665 | break; |
8db62801 | 2666 | } |
cc17453a | 2667 | |
4be87837 DJ |
2668 | /* Hook in ABI-specific overrides, if they have been registered. */ |
2669 | gdbarch_init_osabi (info, gdbarch); | |
d658f924 | 2670 | |
1c0159e0 CV |
2671 | frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer); |
2672 | frame_unwind_append_sniffer (gdbarch, sh_frame_sniffer); | |
2673 | ||
cc17453a | 2674 | return gdbarch; |
8db62801 EZ |
2675 | } |
2676 | ||
617daa0e | 2677 | extern initialize_file_ftype _initialize_sh_tdep; /* -Wmissing-prototypes */ |
a78f21af | 2678 | |
c906108c | 2679 | void |
fba45db2 | 2680 | _initialize_sh_tdep (void) |
c906108c SS |
2681 | { |
2682 | struct cmd_list_element *c; | |
617daa0e | 2683 | |
f2ea0907 | 2684 | gdbarch_register (bfd_arch_sh, sh_gdbarch_init, NULL); |
c906108c | 2685 | |
1bedd215 | 2686 | add_com ("regs", class_vars, sh_show_regs_command, _("Print all registers")); |
c906108c | 2687 | } |