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* rclex.c: (cpp_line): Add code_page pragma support.
[deliverable/binutils-gdb.git] / gdb / sh-tdep.c
CommitLineData
85a453d5 1/* Target-dependent code for Renesas Super-H, for GDB.
0fd88904 2
6aba47ca
DJ		 3 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
4 2003, 2004, 2005, 2007 Free Software Foundation, Inc.
c906108c 5
c5aa993b 6 This file is part of GDB.
c906108c 7
c5aa993b
JM		 8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
c906108c 12
c5aa993b
JM		 13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
c906108c 17
c5aa993b
JM		 18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
197e01b6
EZ		 20 Foundation, Inc., 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA. */
c906108c
SS		 22
23/*
c5aa993b
JM		 24 Contributed by Steve Chamberlain
25 sac@cygnus.com
c906108c
SS		 26 */
27
28#include "defs.h"
29#include "frame.h"
1c0159e0
CV		 30#include "frame-base.h"
31#include "frame-unwind.h"
32#include "dwarf2-frame.h"
c906108c 33#include "symtab.h"
c906108c
SS		 34#include "gdbtypes.h"
35#include "gdbcmd.h"
36#include "gdbcore.h"
37#include "value.h"
38#include "dis-asm.h"
73c1f219 39#include "inferior.h"
c906108c 40#include "gdb_string.h"
1c0159e0 41#include "gdb_assert.h"
b4a20239 42#include "arch-utils.h"
fb409745 43#include "floatformat.h"
4e052eda 44#include "regcache.h"
d16aafd8 45#include "doublest.h"
4be87837 46#include "osabi.h"
dda63807 47#include "reggroups.h"
c906108c 48
ab3b8126
JT		 49#include "sh-tdep.h"
50
d658f924 51#include "elf-bfd.h"
1a8629c7
MS		 52#include "solib-svr4.h"
53
55ff77ac 54/* sh flags */
283150cd
EZ		 55#include "elf/sh.h"
56/* registers numbers shared with the simulator */
1c922164 57#include "gdb/sim-sh.h"
283150cd 58
c458d6db 59static void (*sh_show_regs) (struct frame_info *);
cc17453a 60
da962468 61#define SH_NUM_REGS 67
88e04cc1 62
1c0159e0 63struct sh_frame_cache
cc17453a 64{
1c0159e0
CV		 65 /* Base address. */
66 CORE_ADDR base;
67 LONGEST sp_offset;
68 CORE_ADDR pc;
69
70 /* Flag showing that a frame has been created in the prologue code. */
71 int uses_fp;
72
73 /* Saved registers. */
74 CORE_ADDR saved_regs[SH_NUM_REGS];
75 CORE_ADDR saved_sp;
63978407 76};
c906108c 77
fa88f677 78static const char *
cc17453a
EZ		 79sh_sh_register_name (int reg_nr)
80{
617daa0e
CV		 81 static char *register_names[] = {
82 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
83 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
84 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
85 "", "",
86 "", "", "", "", "", "", "", "",
87 "", "", "", "", "", "", "", "",
88 "", "",
89 "", "", "", "", "", "", "", "",
90 "", "", "", "", "", "", "", "",
da962468 91 "", "", "", "", "", "", "", "",
cc17453a
EZ		 92 };
93 if (reg_nr < 0)
94 return NULL;
95 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
96 return NULL;
97 return register_names[reg_nr];
98}
99
fa88f677 100static const char *
cc17453a
EZ		 101sh_sh3_register_name (int reg_nr)
102{
617daa0e
CV		 103 static char *register_names[] = {
104 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
105 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
106 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
107 "", "",
108 "", "", "", "", "", "", "", "",
109 "", "", "", "", "", "", "", "",
110 "ssr", "spc",
cc17453a
EZ		 111 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
112 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
da962468 113 "", "", "", "", "", "", "", "",
cc17453a
EZ		 114 };
115 if (reg_nr < 0)
116 return NULL;
117 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
118 return NULL;
119 return register_names[reg_nr];
120}
121
fa88f677 122static const char *
cc17453a
EZ		 123sh_sh3e_register_name (int reg_nr)
124{
617daa0e
CV		 125 static char *register_names[] = {
126 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
127 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
128 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
cc17453a 129 "fpul", "fpscr",
617daa0e
CV		 130 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
131 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
132 "ssr", "spc",
cc17453a
EZ		 133 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
134 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
da962468 135 "", "", "", "", "", "", "", "",
cc17453a
EZ		 136 };
137 if (reg_nr < 0)
138 return NULL;
139 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
140 return NULL;
141 return register_names[reg_nr];
142}
143
2d188dd3
NC		 144static const char *
145sh_sh2e_register_name (int reg_nr)
146{
617daa0e
CV		 147 static char *register_names[] = {
148 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
149 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
150 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
2d188dd3 151 "fpul", "fpscr",
617daa0e
CV		 152 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
153 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
154 "", "",
2d188dd3
NC		 155 "", "", "", "", "", "", "", "",
156 "", "", "", "", "", "", "", "",
da962468
CV		 157 "", "", "", "", "", "", "", "",
158 };
159 if (reg_nr < 0)
160 return NULL;
161 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
162 return NULL;
163 return register_names[reg_nr];
164}
165
166static const char *
167sh_sh2a_register_name (int reg_nr)
168{
169 static char *register_names[] = {
170 /* general registers 0-15 */
171 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
172 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
173 /* 16 - 22 */
174 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
175 /* 23, 24 */
176 "fpul", "fpscr",
177 /* floating point registers 25 - 40 */
178 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
179 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
180 /* 41, 42 */
181 "", "",
182 /* 43 - 62. Banked registers. The bank number used is determined by
183 the bank register (63). */
184 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
185 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
186 "machb", "ivnb", "prb", "gbrb", "maclb",
187 /* 63: register bank number, not a real register but used to
188 communicate the register bank currently get/set. This register
189 is hidden to the user, who manipulates it using the pseudo
190 register called "bank" (67). See below. */
191 "",
192 /* 64 - 66 */
193 "ibcr", "ibnr", "tbr",
194 /* 67: register bank number, the user visible pseudo register. */
195 "bank",
196 /* double precision (pseudo) 68 - 75 */
197 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
198 };
199 if (reg_nr < 0)
200 return NULL;
201 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
202 return NULL;
203 return register_names[reg_nr];
204}
205
206static const char *
207sh_sh2a_nofpu_register_name (int reg_nr)
208{
209 static char *register_names[] = {
210 /* general registers 0-15 */
211 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
212 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
213 /* 16 - 22 */
214 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
215 /* 23, 24 */
216 "", "",
217 /* floating point registers 25 - 40 */
218 "", "", "", "", "", "", "", "",
219 "", "", "", "", "", "", "", "",
220 /* 41, 42 */
221 "", "",
222 /* 43 - 62. Banked registers. The bank number used is determined by
223 the bank register (63). */
224 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
225 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
226 "machb", "ivnb", "prb", "gbrb", "maclb",
227 /* 63: register bank number, not a real register but used to
228 communicate the register bank currently get/set. This register
229 is hidden to the user, who manipulates it using the pseudo
230 register called "bank" (67). See below. */
231 "",
232 /* 64 - 66 */
233 "ibcr", "ibnr", "tbr",
234 /* 67: register bank number, the user visible pseudo register. */
235 "bank",
236 /* double precision (pseudo) 68 - 75 */
237 "", "", "", "", "", "", "", "",
2d188dd3
NC		 238 };
239 if (reg_nr < 0)
240 return NULL;
241 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
242 return NULL;
243 return register_names[reg_nr];
244}
245
fa88f677 246static const char *
cc17453a
EZ		 247sh_sh_dsp_register_name (int reg_nr)
248{
617daa0e
CV		 249 static char *register_names[] = {
250 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
251 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
252 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
253 "", "dsr",
254 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
255 "y0", "y1", "", "", "", "", "", "mod",
256 "", "",
257 "rs", "re", "", "", "", "", "", "",
258 "", "", "", "", "", "", "", "",
da962468 259 "", "", "", "", "", "", "", "",
cc17453a
EZ		 260 };
261 if (reg_nr < 0)
262 return NULL;
263 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
264 return NULL;
265 return register_names[reg_nr];
266}
267
fa88f677 268static const char *
cc17453a
EZ		 269sh_sh3_dsp_register_name (int reg_nr)
270{
617daa0e
CV		 271 static char *register_names[] = {
272 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
273 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
274 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
275 "", "dsr",
276 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
277 "y0", "y1", "", "", "", "", "", "mod",
278 "ssr", "spc",
279 "rs", "re", "", "", "", "", "", "",
026a72f8
CV		 280 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
281 "", "", "", "", "", "", "", "",
da962468 282 "", "", "", "", "", "", "", "",
cc17453a
EZ		 283 };
284 if (reg_nr < 0)
285 return NULL;
286 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
287 return NULL;
288 return register_names[reg_nr];
289}
290
fa88f677 291static const char *
53116e27
EZ		 292sh_sh4_register_name (int reg_nr)
293{
617daa0e 294 static char *register_names[] = {
a38d2a54 295 /* general registers 0-15 */
617daa0e
CV		 296 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
297 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
a38d2a54 298 /* 16 - 22 */
617daa0e 299 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
a38d2a54 300 /* 23, 24 */
53116e27 301 "fpul", "fpscr",
a38d2a54 302 /* floating point registers 25 - 40 */
617daa0e
CV		 303 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
304 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
a38d2a54 305 /* 41, 42 */
617daa0e 306 "ssr", "spc",
a38d2a54 307 /* bank 0 43 - 50 */
53116e27 308 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
a38d2a54 309 /* bank 1 51 - 58 */
53116e27 310 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
da962468
CV		 311 "", "", "", "", "", "", "", "",
312 /* pseudo bank register. */
313 "",
a38d2a54 314 /* double precision (pseudo) 59 - 66 */
617daa0e 315 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
a38d2a54 316 /* vectors (pseudo) 67 - 70 */
617daa0e 317 "fv0", "fv4", "fv8", "fv12",
a38d2a54
EZ		 318 /* FIXME: missing XF 71 - 86 */
319 /* FIXME: missing XD 87 - 94 */
53116e27
EZ		 320 };
321 if (reg_nr < 0)
322 return NULL;
323 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
324 return NULL;
325 return register_names[reg_nr];
326}
327
474e5826
CV		 328static const char *
329sh_sh4_nofpu_register_name (int reg_nr)
330{
331 static char *register_names[] = {
332 /* general registers 0-15 */
333 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
334 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
335 /* 16 - 22 */
336 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
337 /* 23, 24 */
338 "", "",
339 /* floating point registers 25 - 40 -- not for nofpu target */
340 "", "", "", "", "", "", "", "",
341 "", "", "", "", "", "", "", "",
342 /* 41, 42 */
343 "ssr", "spc",
344 /* bank 0 43 - 50 */
345 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
346 /* bank 1 51 - 58 */
347 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
da962468
CV		 348 "", "", "", "", "", "", "", "",
349 /* pseudo bank register. */
350 "",
474e5826
CV		 351 /* double precision (pseudo) 59 - 66 -- not for nofpu target */
352 "", "", "", "", "", "", "", "",
353 /* vectors (pseudo) 67 - 70 -- not for nofpu target */
354 "", "", "", "",
355 };
356 if (reg_nr < 0)
357 return NULL;
358 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
359 return NULL;
360 return register_names[reg_nr];
361}
362
363static const char *
364sh_sh4al_dsp_register_name (int reg_nr)
365{
366 static char *register_names[] = {
367 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
368 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
369 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
370 "", "dsr",
371 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
372 "y0", "y1", "", "", "", "", "", "mod",
373 "ssr", "spc",
374 "rs", "re", "", "", "", "", "", "",
026a72f8
CV		 375 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
376 "", "", "", "", "", "", "", "",
da962468 377 "", "", "", "", "", "", "", "",
474e5826
CV		 378 };
379 if (reg_nr < 0)
380 return NULL;
381 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
382 return NULL;
383 return register_names[reg_nr];
384}
385
3117ed25 386static const unsigned char *
fba45db2 387sh_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
cc17453a
EZ		 388{
389 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */
617daa0e
CV		 390 static unsigned char breakpoint[] = { 0xc3, 0xc3 };
391
bac718a6
UW		 392 /* For remote stub targets, trapa #20 is used. */
393 if (strcmp (target_shortname, "remote") == 0)
394 {
395 static unsigned char big_remote_breakpoint[] = { 0xc3, 0x20 };
396 static unsigned char little_remote_breakpoint[] = { 0x20, 0xc3 };
397
4c6b5505 398 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
bac718a6
UW		 399 {
400 *lenptr = sizeof (big_remote_breakpoint);
401 return big_remote_breakpoint;
402 }
403 else
404 {
405 *lenptr = sizeof (little_remote_breakpoint);
406 return little_remote_breakpoint;
407 }
408 }
409
cc17453a
EZ		 410 *lenptr = sizeof (breakpoint);
411 return breakpoint;
412}
c906108c
SS		 413
414/* Prologue looks like
1c0159e0
CV		 415 mov.l r14,@-r15
416 sts.l pr,@-r15
417 mov.l <regs>,@-r15
418 sub <room_for_loca_vars>,r15
419 mov r15,r14
8db62801 420
1c0159e0 421 Actually it can be more complicated than this but that's it, basically.
c5aa993b 422 */
c906108c 423
1c0159e0
CV		 424#define GET_SOURCE_REG(x) (((x) >> 4) & 0xf)
425#define GET_TARGET_REG(x) (((x) >> 8) & 0xf)
426
5f883edd
FF		 427/* JSR @Rm 0100mmmm00001011 */
428#define IS_JSR(x) (((x) & 0xf0ff) == 0x400b)
429
8db62801
EZ		 430/* STS.L PR,@-r15 0100111100100010
431 r15-4-->r15, PR-->(r15) */
c906108c 432#define IS_STS(x) ((x) == 0x4f22)
8db62801 433
03131d99
CV		 434/* STS.L MACL,@-r15 0100111100010010
435 r15-4-->r15, MACL-->(r15) */
436#define IS_MACL_STS(x) ((x) == 0x4f12)
437
8db62801
EZ		 438/* MOV.L Rm,@-r15 00101111mmmm0110
439 r15-4-->r15, Rm-->(R15) */
c906108c 440#define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
8db62801 441
8db62801
EZ		 442/* MOV r15,r14 0110111011110011
443 r15-->r14 */
c906108c 444#define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
8db62801
EZ		 445
446/* ADD #imm,r15 01111111iiiiiiii
447 r15+imm-->r15 */
1c0159e0 448#define IS_ADD_IMM_SP(x) (((x) & 0xff00) == 0x7f00)
8db62801 449
c906108c
SS		 450#define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
451#define IS_SHLL_R3(x) ((x) == 0x4300)
8db62801
EZ		 452
453/* ADD r3,r15 0011111100111100
454 r15+r3-->r15 */
c906108c 455#define IS_ADD_R3SP(x) ((x) == 0x3f3c)
8db62801
EZ		 456
457/* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
8db62801 458 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
8db62801 459 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
f2ea0907
CV		 460/* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to
461 make this entirely clear. */
1c0159e0
CV		 462/* #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) */
463#define IS_FPUSH(x) (((x) & 0xff0f) == 0xff0b)
464
465/* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 4 <= m <= 7 */
466#define IS_MOV_ARG_TO_REG(x) \
467 (((x) & 0xf00f) == 0x6003 && \
468 ((x) & 0x00f0) >= 0x0040 && \
469 ((x) & 0x00f0) <= 0x0070)
470/* MOV.L Rm,@Rn 0010nnnnmmmm0010 n = 14, 4 <= m <= 7 */
471#define IS_MOV_ARG_TO_IND_R14(x) \
472 (((x) & 0xff0f) == 0x2e02 && \
473 ((x) & 0x00f0) >= 0x0040 && \
474 ((x) & 0x00f0) <= 0x0070)
475/* MOV.L Rm,@(disp*4,Rn) 00011110mmmmdddd n = 14, 4 <= m <= 7 */
476#define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \
477 (((x) & 0xff00) == 0x1e00 && \
478 ((x) & 0x00f0) >= 0x0040 && \
479 ((x) & 0x00f0) <= 0x0070)
480
481/* MOV.W @(disp*2,PC),Rn 1001nnnndddddddd */
482#define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000)
483/* MOV.L @(disp*4,PC),Rn 1101nnnndddddddd */
484#define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000)
03131d99
CV		 485/* MOVI20 #imm20,Rn 0000nnnniiii0000 */
486#define IS_MOVI20(x) (((x) & 0xf00f) == 0x0000)
1c0159e0
CV		 487/* SUB Rn,R15 00111111nnnn1000 */
488#define IS_SUB_REG_FROM_SP(x) (((x) & 0xff0f) == 0x3f08)
8db62801 489
1c0159e0 490#define FPSCR_SZ (1 << 20)
cc17453a 491
1c0159e0
CV		 492/* The following instructions are used for epilogue testing. */
493#define IS_RESTORE_FP(x) ((x) == 0x6ef6)
494#define IS_RTS(x) ((x) == 0x000b)
495#define IS_LDS(x) ((x) == 0x4f26)
03131d99 496#define IS_MACL_LDS(x) ((x) == 0x4f16)
1c0159e0
CV		 497#define IS_MOV_FP_SP(x) ((x) == 0x6fe3)
498#define IS_ADD_REG_TO_FP(x) (((x) & 0xff0f) == 0x3e0c)
499#define IS_ADD_IMM_FP(x) (((x) & 0xff00) == 0x7e00)
cc17453a 500
cc17453a
EZ		 501/* Disassemble an instruction. */
502static int
617daa0e 503gdb_print_insn_sh (bfd_vma memaddr, disassemble_info * info)
c906108c 504{
4c6b5505 505 info->endian = gdbarch_byte_order (current_gdbarch);
1c509ca8 506 return print_insn_sh (memaddr, info);
283150cd
EZ		 507}
508
cc17453a 509static CORE_ADDR
1c0159e0 510sh_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc,
d2ca4222 511 struct sh_frame_cache *cache, ULONGEST fpscr)
617daa0e 512{
1c0159e0
CV		 513 ULONGEST inst;
514 CORE_ADDR opc;
515 int offset;
516 int sav_offset = 0;
c906108c 517 int r3_val = 0;
1c0159e0 518 int reg, sav_reg = -1;
cc17453a 519
1c0159e0
CV		 520 if (pc >= current_pc)
521 return current_pc;
cc17453a 522
1c0159e0 523 cache->uses_fp = 0;
cc17453a
EZ		 524 for (opc = pc + (2 * 28); pc < opc; pc += 2)
525 {
1c0159e0 526 inst = read_memory_unsigned_integer (pc, 2);
cc17453a 527 /* See where the registers will be saved to */
f2ea0907 528 if (IS_PUSH (inst))
cc17453a 529 {
1c0159e0
CV		 530 cache->saved_regs[GET_SOURCE_REG (inst)] = cache->sp_offset;
531 cache->sp_offset += 4;
cc17453a 532 }
f2ea0907 533 else if (IS_STS (inst))
cc17453a 534 {
1c0159e0
CV		 535 cache->saved_regs[PR_REGNUM] = cache->sp_offset;
536 cache->sp_offset += 4;
cc17453a 537 }
03131d99
CV		 538 else if (IS_MACL_STS (inst))
539 {
540 cache->saved_regs[MACL_REGNUM] = cache->sp_offset;
541 cache->sp_offset += 4;
542 }
f2ea0907 543 else if (IS_MOV_R3 (inst))
cc17453a 544 {
f2ea0907 545 r3_val = ((inst & 0xff) ^ 0x80) - 0x80;
cc17453a 546 }
f2ea0907 547 else if (IS_SHLL_R3 (inst))
cc17453a
EZ		 548 {
549 r3_val <<= 1;
550 }
f2ea0907 551 else if (IS_ADD_R3SP (inst))
cc17453a 552 {
1c0159e0 553 cache->sp_offset += -r3_val;
cc17453a 554 }
f2ea0907 555 else if (IS_ADD_IMM_SP (inst))
cc17453a 556 {
1c0159e0
CV		 557 offset = ((inst & 0xff) ^ 0x80) - 0x80;
558 cache->sp_offset -= offset;
c906108c 559 }
1c0159e0 560 else if (IS_MOVW_PCREL_TO_REG (inst))
617daa0e 561 {
1c0159e0
CV		 562 if (sav_reg < 0)
563 {
564 reg = GET_TARGET_REG (inst);
565 if (reg < 14)
566 {
567 sav_reg = reg;
a2b4a96c 568 offset = (inst & 0xff) << 1;
1c0159e0 569 sav_offset =
a2b4a96c 570 read_memory_integer ((pc + 4) + offset, 2);
1c0159e0
CV		 571 }
572 }
c906108c 573 }
1c0159e0 574 else if (IS_MOVL_PCREL_TO_REG (inst))
617daa0e 575 {
1c0159e0
CV		 576 if (sav_reg < 0)
577 {
a2b4a96c 578 reg = GET_TARGET_REG (inst);
1c0159e0
CV		 579 if (reg < 14)
580 {
581 sav_reg = reg;
a2b4a96c 582 offset = (inst & 0xff) << 2;
1c0159e0 583 sav_offset =
a2b4a96c 584 read_memory_integer (((pc & 0xfffffffc) + 4) + offset, 4);
1c0159e0
CV		 585 }
586 }
c906108c 587 }
03131d99
CV		 588 else if (IS_MOVI20 (inst))
589 {
590 if (sav_reg < 0)
591 {
592 reg = GET_TARGET_REG (inst);
593 if (reg < 14)
594 {
595 sav_reg = reg;
596 sav_offset = GET_SOURCE_REG (inst) << 16;
597 /* MOVI20 is a 32 bit instruction! */
598 pc += 2;
599 sav_offset |= read_memory_unsigned_integer (pc, 2);
600 /* Now sav_offset contains an unsigned 20 bit value.
601 It must still get sign extended. */
602 if (sav_offset & 0x00080000)
603 sav_offset |= 0xfff00000;
604 }
605 }
606 }
1c0159e0 607 else if (IS_SUB_REG_FROM_SP (inst))
617daa0e 608 {
1c0159e0
CV		 609 reg = GET_SOURCE_REG (inst);
610 if (sav_reg > 0 && reg == sav_reg)
611 {
612 sav_reg = -1;
613 }
614 cache->sp_offset += sav_offset;
c906108c 615 }
f2ea0907 616 else if (IS_FPUSH (inst))
c906108c 617 {
d2ca4222 618 if (fpscr & FPSCR_SZ)
c906108c 619 {
1c0159e0 620 cache->sp_offset += 8;
c906108c
SS		 621 }
622 else
623 {
1c0159e0 624 cache->sp_offset += 4;
c906108c
SS		 625 }
626 }
f2ea0907 627 else if (IS_MOV_SP_FP (inst))
617daa0e 628 {
960ccd7d 629 cache->uses_fp = 1;
1c0159e0
CV		 630 /* At this point, only allow argument register moves to other
631 registers or argument register moves to @(X,fp) which are
632 moving the register arguments onto the stack area allocated
633 by a former add somenumber to SP call. Don't allow moving
634 to an fp indirect address above fp + cache->sp_offset. */
635 pc += 2;
636 for (opc = pc + 12; pc < opc; pc += 2)
637 {
638 inst = read_memory_integer (pc, 2);
639 if (IS_MOV_ARG_TO_IND_R14 (inst))
617daa0e 640 {
1c0159e0
CV		 641 reg = GET_SOURCE_REG (inst);
642 if (cache->sp_offset > 0)
617daa0e 643 cache->saved_regs[reg] = cache->sp_offset;
1c0159e0
CV		 644 }
645 else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst))
617daa0e 646 {
1c0159e0
CV		 647 reg = GET_SOURCE_REG (inst);
648 offset = (inst & 0xf) * 4;
649 if (cache->sp_offset > offset)
650 cache->saved_regs[reg] = cache->sp_offset - offset;
651 }
652 else if (IS_MOV_ARG_TO_REG (inst))
617daa0e 653 continue;
1c0159e0
CV		 654 else
655 break;
656 }
657 break;
658 }
5f883edd
FF		 659 else if (IS_JSR (inst))
660 {
661 /* We have found a jsr that has been scheduled into the prologue.
662 If we continue the scan and return a pc someplace after this,
663 then setting a breakpoint on this function will cause it to
664 appear to be called after the function it is calling via the
665 jsr, which will be very confusing. Most likely the next
666 instruction is going to be IS_MOV_SP_FP in the delay slot. If
667 so, note that before returning the current pc. */
668 inst = read_memory_integer (pc + 2, 2);
669 if (IS_MOV_SP_FP (inst))
670 cache->uses_fp = 1;
671 break;
672 }
617daa0e
CV		 673#if 0 /* This used to just stop when it found an instruction that
674 was not considered part of the prologue. Now, we just
675 keep going looking for likely instructions. */
c906108c
SS		 676 else
677 break;
2bfa91ee 678#endif
c906108c
SS		 679 }
680
1c0159e0
CV		 681 return pc;
682}
c906108c 683
1c0159e0 684/* Skip any prologue before the guts of a function */
c906108c 685
1c0159e0
CV		 686/* Skip the prologue using the debug information. If this fails we'll
687 fall back on the 'guess' method below. */
688static CORE_ADDR
689after_prologue (CORE_ADDR pc)
690{
691 struct symtab_and_line sal;
692 CORE_ADDR func_addr, func_end;
c906108c 693
1c0159e0
CV		 694 /* If we can not find the symbol in the partial symbol table, then
695 there is no hope we can determine the function's start address
696 with this code. */
697 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
698 return 0;
c906108c 699
1c0159e0
CV		 700 /* Get the line associated with FUNC_ADDR. */
701 sal = find_pc_line (func_addr, 0);
702
703 /* There are only two cases to consider. First, the end of the source line
704 is within the function bounds. In that case we return the end of the
705 source line. Second is the end of the source line extends beyond the
706 bounds of the current function. We need to use the slow code to
707 examine instructions in that case. */
708 if (sal.end < func_end)
709 return sal.end;
710 else
711 return 0;
c906108c
SS		 712}
713
1c0159e0
CV		 714static CORE_ADDR
715sh_skip_prologue (CORE_ADDR start_pc)
c906108c 716{
1c0159e0
CV		 717 CORE_ADDR pc;
718 struct sh_frame_cache cache;
719
720 /* See if we can determine the end of the prologue via the symbol table.
721 If so, then return either PC, or the PC after the prologue, whichever
722 is greater. */
723 pc = after_prologue (start_pc);
cc17453a 724
1c0159e0
CV		 725 /* If after_prologue returned a useful address, then use it. Else
726 fall back on the instruction skipping code. */
727 if (pc)
728 return max (pc, start_pc);
c906108c 729
1c0159e0 730 cache.sp_offset = -4;
d2ca4222 731 pc = sh_analyze_prologue (start_pc, (CORE_ADDR) -1, &cache, 0);
1c0159e0
CV		 732 if (!cache.uses_fp)
733 return start_pc;
c906108c 734
1c0159e0
CV		 735 return pc;
736}
737
2e952408 738/* The ABI says:
9a5cef92
EZ		 739
740 Aggregate types not bigger than 8 bytes that have the same size and
741 alignment as one of the integer scalar types are returned in the
742 same registers as the integer type they match.
743
744 For example, a 2-byte aligned structure with size 2 bytes has the
745 same size and alignment as a short int, and will be returned in R0.
746 A 4-byte aligned structure with size 8 bytes has the same size and
747 alignment as a long long int, and will be returned in R0 and R1.
748
749 When an aggregate type is returned in R0 and R1, R0 contains the
750 first four bytes of the aggregate, and R1 contains the
751 remainder. If the size of the aggregate type is not a multiple of 4
752 bytes, the aggregate is tail-padded up to a multiple of 4
753 bytes. The value of the padding is undefined. For little-endian
754 targets the padding will appear at the most significant end of the
755 last element, for big-endian targets the padding appears at the
756 least significant end of the last element.
757
758 All other aggregate types are returned by address. The caller
759 function passes the address of an area large enough to hold the
760 aggregate value in R2. The called function stores the result in
7fe958be 761 this location.
9a5cef92
EZ		 762
763 To reiterate, structs smaller than 8 bytes could also be returned
764 in memory, if they don't pass the "same size and alignment as an
765 integer type" rule.
766
767 For example, in
768
769 struct s { char c[3]; } wibble;
770 struct s foo(void) { return wibble; }
771
772 the return value from foo() will be in memory, not
773 in R0, because there is no 3-byte integer type.
774
7fe958be
EZ		 775 Similarly, in
776
777 struct s { char c[2]; } wibble;
778 struct s foo(void) { return wibble; }
779
780 because a struct containing two chars has alignment 1, that matches
781 type char, but size 2, that matches type short. There's no integer
782 type that has alignment 1 and size 2, so the struct is returned in
783 memory.
784
9a5cef92
EZ		 785*/
786
1c0159e0
CV		 787static int
788sh_use_struct_convention (int gcc_p, struct type *type)
789{
790 int len = TYPE_LENGTH (type);
791 int nelem = TYPE_NFIELDS (type);
3f997a97
CV		 792
793 /* Non-power of 2 length types and types bigger than 8 bytes (which don't
794 fit in two registers anyway) use struct convention. */
795 if (len != 1 && len != 2 && len != 4 && len != 8)
796 return 1;
797
798 /* Scalar types and aggregate types with exactly one field are aligned
799 by definition. They are returned in registers. */
800 if (nelem <= 1)
801 return 0;
802
803 /* If the first field in the aggregate has the same length as the entire
804 aggregate type, the type is returned in registers. */
805 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == len)
806 return 0;
807
808 /* If the size of the aggregate is 8 bytes and the first field is
809 of size 4 bytes its alignment is equal to long long's alignment,
810 so it's returned in registers. */
811 if (len == 8 && TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == 4)
812 return 0;
813
814 /* Otherwise use struct convention. */
815 return 1;
283150cd
EZ		 816}
817
cc17453a
EZ		 818/* Extract from an array REGBUF containing the (raw) register state
819 the address in which a function should return its structure value,
820 as a CORE_ADDR (or an expression that can be used as one). */
b3df3fff 821static CORE_ADDR
48db5a3c 822sh_extract_struct_value_address (struct regcache *regcache)
cc17453a 823{
48db5a3c 824 ULONGEST addr;
1c0159e0 825
48db5a3c
CV		 826 regcache_cooked_read_unsigned (regcache, STRUCT_RETURN_REGNUM, &addr);
827 return addr;
cc17453a
EZ		 828}
829
19f59343
MS		 830static CORE_ADDR
831sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
832{
833 return sp & ~3;
834}
835
55ff77ac 836/* Function: push_dummy_call (formerly push_arguments)
c906108c
SS		 837 Setup the function arguments for calling a function in the inferior.
838
85a453d5 839 On the Renesas SH architecture, there are four registers (R4 to R7)
c906108c
SS		 840 which are dedicated for passing function arguments. Up to the first
841 four arguments (depending on size) may go into these registers.
842 The rest go on the stack.
843
6df2bf50
MS		 844 MVS: Except on SH variants that have floating point registers.
845 In that case, float and double arguments are passed in the same
846 manner, but using FP registers instead of GP registers.
847
c906108c
SS		 848 Arguments that are smaller than 4 bytes will still take up a whole
849 register or a whole 32-bit word on the stack, and will be
850 right-justified in the register or the stack word. This includes
851 chars, shorts, and small aggregate types.
852
853 Arguments that are larger than 4 bytes may be split between two or
854 more registers. If there are not enough registers free, an argument
855 may be passed partly in a register (or registers), and partly on the
856 stack. This includes doubles, long longs, and larger aggregates.
857 As far as I know, there is no upper limit to the size of aggregates
858 that will be passed in this way; in other words, the convention of
859 passing a pointer to a large aggregate instead of a copy is not used.
860
6df2bf50 861 MVS: The above appears to be true for the SH variants that do not
55ff77ac 862 have an FPU, however those that have an FPU appear to copy the
6df2bf50
MS		 863 aggregate argument onto the stack (and not place it in registers)
864 if it is larger than 16 bytes (four GP registers).
865
c906108c
SS		 866 An exceptional case exists for struct arguments (and possibly other
867 aggregates such as arrays) if the size is larger than 4 bytes but
868 not a multiple of 4 bytes. In this case the argument is never split
869 between the registers and the stack, but instead is copied in its
870 entirety onto the stack, AND also copied into as many registers as
871 there is room for. In other words, space in registers permitting,
872 two copies of the same argument are passed in. As far as I can tell,
873 only the one on the stack is used, although that may be a function
874 of the level of compiler optimization. I suspect this is a compiler
875 bug. Arguments of these odd sizes are left-justified within the
876 word (as opposed to arguments smaller than 4 bytes, which are
877 right-justified).
c5aa993b 878
c906108c
SS		 879 If the function is to return an aggregate type such as a struct, it
880 is either returned in the normal return value register R0 (if its
881 size is no greater than one byte), or else the caller must allocate
882 space into which the callee will copy the return value (if the size
883 is greater than one byte). In this case, a pointer to the return
884 value location is passed into the callee in register R2, which does
885 not displace any of the other arguments passed in via registers R4
886 to R7. */
887
e5e33cd9
CV		 888/* Helper function to justify value in register according to endianess. */
889static char *
890sh_justify_value_in_reg (struct value *val, int len)
891{
892 static char valbuf[4];
893
617daa0e 894 memset (valbuf, 0, sizeof (valbuf));
e5e33cd9
CV		 895 if (len < 4)
896 {
897 /* value gets right-justified in the register or stack word */
4c6b5505 898 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
0fd88904 899 memcpy (valbuf + (4 - len), (char *) value_contents (val), len);
e5e33cd9 900 else
0fd88904 901 memcpy (valbuf, (char *) value_contents (val), len);
e5e33cd9
CV		 902 return valbuf;
903 }
0fd88904 904 return (char *) value_contents (val);
617daa0e 905}
e5e33cd9
CV		 906
907/* Helper function to eval number of bytes to allocate on stack. */
908static CORE_ADDR
909sh_stack_allocsize (int nargs, struct value **args)
910{
911 int stack_alloc = 0;
912 while (nargs-- > 0)
4991999e 913 stack_alloc += ((TYPE_LENGTH (value_type (args[nargs])) + 3) & ~3);
e5e33cd9
CV		 914 return stack_alloc;
915}
916
917/* Helper functions for getting the float arguments right. Registers usage
918 depends on the ABI and the endianess. The comments should enlighten how
919 it's intended to work. */
920
921/* This array stores which of the float arg registers are already in use. */
922static int flt_argreg_array[FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM + 1];
923
924/* This function just resets the above array to "no reg used so far". */
925static void
926sh_init_flt_argreg (void)
927{
928 memset (flt_argreg_array, 0, sizeof flt_argreg_array);
929}
930
931/* This function returns the next register to use for float arg passing.
932 It returns either a valid value between FLOAT_ARG0_REGNUM and
933 FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns
934 FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available.
935
936 Note that register number 0 in flt_argreg_array corresponds with the
937 real float register fr4. In contrast to FLOAT_ARG0_REGNUM (value is
938 29) the parity of the register number is preserved, which is important
939 for the double register passing test (see the "argreg & 1" test below). */
940static int
941sh_next_flt_argreg (int len)
942{
943 int argreg;
944
945 /* First search for the next free register. */
617daa0e
CV		 946 for (argreg = 0; argreg <= FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM;
947 ++argreg)
e5e33cd9
CV		 948 if (!flt_argreg_array[argreg])
949 break;
950
951 /* No register left? */
952 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
953 return FLOAT_ARGLAST_REGNUM + 1;
954
955 if (len == 8)
956 {
957 /* Doubles are always starting in a even register number. */
958 if (argreg & 1)
617daa0e 959 {
e5e33cd9
CV		 960 flt_argreg_array[argreg] = 1;
961
962 ++argreg;
963
617daa0e 964 /* No register left? */
e5e33cd9
CV		 965 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
966 return FLOAT_ARGLAST_REGNUM + 1;
967 }
968 /* Also mark the next register as used. */
969 flt_argreg_array[argreg + 1] = 1;
970 }
4c6b5505 971 else if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE)
e5e33cd9
CV		 972 {
973 /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */
974 if (!flt_argreg_array[argreg + 1])
975 ++argreg;
976 }
977 flt_argreg_array[argreg] = 1;
978 return FLOAT_ARG0_REGNUM + argreg;
979}
980
afce3d2a
CV		 981/* Helper function which figures out, if a type is treated like a float type.
982
2e952408 983 The FPU ABIs have a special way how to treat types as float types.
afce3d2a
CV		 984 Structures with exactly one member, which is of type float or double, are
985 treated exactly as the base types float or double:
986
987 struct sf {
988 float f;
989 };
990
991 struct sd {
992 double d;
993 };
994
995 are handled the same way as just
996
997 float f;
998
999 double d;
1000
1001 As a result, arguments of these struct types are pushed into floating point
1002 registers exactly as floats or doubles, using the same decision algorithm.
1003
1004 The same is valid if these types are used as function return types. The
1005 above structs are returned in fr0 resp. fr0,fr1 instead of in r0, r0,r1
1006 or even using struct convention as it is for other structs. */
1007
1008static int
1009sh_treat_as_flt_p (struct type *type)
1010{
1011 int len = TYPE_LENGTH (type);
1012
1013 /* Ordinary float types are obviously treated as float. */
1014 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1015 return 1;
1016 /* Otherwise non-struct types are not treated as float. */
1017 if (TYPE_CODE (type) != TYPE_CODE_STRUCT)
1018 return 0;
1019 /* Otherwise structs with more than one memeber are not treated as float. */
1020 if (TYPE_NFIELDS (type) != 1)
1021 return 0;
1022 /* Otherwise if the type of that member is float, the whole type is
1023 treated as float. */
1024 if (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) == TYPE_CODE_FLT)
1025 return 1;
1026 /* Otherwise it's not treated as float. */
1027 return 0;
1028}
1029
cc17453a 1030static CORE_ADDR
617daa0e 1031sh_push_dummy_call_fpu (struct gdbarch *gdbarch,
7d9b040b 1032 struct value *function,
617daa0e 1033 struct regcache *regcache,
6df2bf50 1034 CORE_ADDR bp_addr, int nargs,
617daa0e 1035 struct value **args,
6df2bf50
MS		 1036 CORE_ADDR sp, int struct_return,
1037 CORE_ADDR struct_addr)
1038{
e5e33cd9
CV		 1039 int stack_offset = 0;
1040 int argreg = ARG0_REGNUM;
8748518b 1041 int flt_argreg = 0;
6df2bf50
MS		 1042 int argnum;
1043 struct type *type;
1044 CORE_ADDR regval;
1045 char *val;
8748518b 1046 int len, reg_size = 0;
afce3d2a
CV		 1047 int pass_on_stack = 0;
1048 int treat_as_flt;
6df2bf50
MS		 1049
1050 /* first force sp to a 4-byte alignment */
1051 sp = sh_frame_align (gdbarch, sp);
1052
6df2bf50 1053 if (struct_return)
1c0159e0 1054 regcache_cooked_write_unsigned (regcache,
617daa0e 1055 STRUCT_RETURN_REGNUM, struct_addr);
6df2bf50 1056
e5e33cd9
CV		 1057 /* make room on stack for args */
1058 sp -= sh_stack_allocsize (nargs, args);
1059
1060 /* Initialize float argument mechanism. */
1061 sh_init_flt_argreg ();
6df2bf50
MS		 1062
1063 /* Now load as many as possible of the first arguments into
1064 registers, and push the rest onto the stack. There are 16 bytes
1065 in four registers available. Loop thru args from first to last. */
e5e33cd9 1066 for (argnum = 0; argnum < nargs; argnum++)
6df2bf50 1067 {
4991999e 1068 type = value_type (args[argnum]);
6df2bf50 1069 len = TYPE_LENGTH (type);
e5e33cd9
CV		 1070 val = sh_justify_value_in_reg (args[argnum], len);
1071
1072 /* Some decisions have to be made how various types are handled.
1073 This also differs in different ABIs. */
1074 pass_on_stack = 0;
e5e33cd9
CV		 1075
1076 /* Find out the next register to use for a floating point value. */
afce3d2a
CV		 1077 treat_as_flt = sh_treat_as_flt_p (type);
1078 if (treat_as_flt)
617daa0e 1079 flt_argreg = sh_next_flt_argreg (len);
afce3d2a
CV		 1080 /* In contrast to non-FPU CPUs, arguments are never split between
1081 registers and stack. If an argument doesn't fit in the remaining
1082 registers it's always pushed entirely on the stack. */
1083 else if (len > ((ARGLAST_REGNUM - argreg + 1) * 4))
1084 pass_on_stack = 1;
48db5a3c 1085
6df2bf50
MS		 1086 while (len > 0)
1087 {
afce3d2a
CV		 1088 if ((treat_as_flt && flt_argreg > FLOAT_ARGLAST_REGNUM)
1089 || (!treat_as_flt && (argreg > ARGLAST_REGNUM
1090 || pass_on_stack)))
617daa0e 1091 {
afce3d2a 1092 /* The data goes entirely on the stack, 4-byte aligned. */
e5e33cd9
CV		 1093 reg_size = (len + 3) & ~3;
1094 write_memory (sp + stack_offset, val, reg_size);
1095 stack_offset += reg_size;
6df2bf50 1096 }
afce3d2a 1097 else if (treat_as_flt && flt_argreg <= FLOAT_ARGLAST_REGNUM)
6df2bf50 1098 {
e5e33cd9
CV		 1099 /* Argument goes in a float argument register. */
1100 reg_size = register_size (gdbarch, flt_argreg);
1101 regval = extract_unsigned_integer (val, reg_size);
2e952408
CV		 1102 /* In little endian mode, float types taking two registers
1103 (doubles on sh4, long doubles on sh2e, sh3e and sh4) must
1104 be stored swapped in the argument registers. The below
1105 code first writes the first 32 bits in the next but one
1106 register, increments the val and len values accordingly
1107 and then proceeds as normal by writing the second 32 bits
1108 into the next register. */
4c6b5505 1109 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE
2e952408
CV		 1110 && TYPE_LENGTH (type) == 2 * reg_size)
1111 {
1112 regcache_cooked_write_unsigned (regcache, flt_argreg + 1,
1113 regval);
1114 val += reg_size;
1115 len -= reg_size;
1116 regval = extract_unsigned_integer (val, reg_size);
1117 }
6df2bf50
MS		 1118 regcache_cooked_write_unsigned (regcache, flt_argreg++, regval);
1119 }
afce3d2a 1120 else if (!treat_as_flt && argreg <= ARGLAST_REGNUM)
e5e33cd9 1121 {
6df2bf50 1122 /* there's room in a register */
e5e33cd9
CV		 1123 reg_size = register_size (gdbarch, argreg);
1124 regval = extract_unsigned_integer (val, reg_size);
6df2bf50
MS		 1125 regcache_cooked_write_unsigned (regcache, argreg++, regval);
1126 }
afce3d2a 1127 /* Store the value one register at a time or in one step on stack. */
e5e33cd9
CV		 1128 len -= reg_size;
1129 val += reg_size;
6df2bf50
MS		 1130 }
1131 }
1132
1133 /* Store return address. */
55ff77ac 1134 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
6df2bf50
MS		 1135
1136 /* Update stack pointer. */
1137 regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp);
1138
1139 return sp;
1140}
1141
1142static CORE_ADDR
617daa0e 1143sh_push_dummy_call_nofpu (struct gdbarch *gdbarch,
7d9b040b 1144 struct value *function,
617daa0e
CV		 1145 struct regcache *regcache,
1146 CORE_ADDR bp_addr,
1147 int nargs, struct value **args,
1148 CORE_ADDR sp, int struct_return,
6df2bf50 1149 CORE_ADDR struct_addr)
c906108c 1150{
e5e33cd9
CV		 1151 int stack_offset = 0;
1152 int argreg = ARG0_REGNUM;
c906108c
SS		 1153 int argnum;
1154 struct type *type;
1155 CORE_ADDR regval;
1156 char *val;
e5e33cd9 1157 int len, reg_size;
c906108c
SS		 1158
1159 /* first force sp to a 4-byte alignment */
19f59343 1160 sp = sh_frame_align (gdbarch, sp);
c906108c 1161
c906108c 1162 if (struct_return)
55ff77ac 1163 regcache_cooked_write_unsigned (regcache,
617daa0e 1164 STRUCT_RETURN_REGNUM, struct_addr);
c906108c 1165
e5e33cd9
CV		 1166 /* make room on stack for args */
1167 sp -= sh_stack_allocsize (nargs, args);
c906108c 1168
c906108c
SS		 1169 /* Now load as many as possible of the first arguments into
1170 registers, and push the rest onto the stack. There are 16 bytes
1171 in four registers available. Loop thru args from first to last. */
e5e33cd9 1172 for (argnum = 0; argnum < nargs; argnum++)
617daa0e 1173 {
4991999e 1174 type = value_type (args[argnum]);
c5aa993b 1175 len = TYPE_LENGTH (type);
e5e33cd9 1176 val = sh_justify_value_in_reg (args[argnum], len);
c906108c 1177
c906108c
SS		 1178 while (len > 0)
1179 {
e5e33cd9 1180 if (argreg > ARGLAST_REGNUM)
617daa0e 1181 {
e5e33cd9
CV		 1182 /* The remainder of the data goes entirely on the stack,
1183 4-byte aligned. */
1184 reg_size = (len + 3) & ~3;
1185 write_memory (sp + stack_offset, val, reg_size);
617daa0e 1186 stack_offset += reg_size;
c906108c 1187 }
e5e33cd9 1188 else if (argreg <= ARGLAST_REGNUM)
617daa0e 1189 {
3bbfbb92 1190 /* there's room in a register */
e5e33cd9
CV		 1191 reg_size = register_size (gdbarch, argreg);
1192 regval = extract_unsigned_integer (val, reg_size);
48db5a3c 1193 regcache_cooked_write_unsigned (regcache, argreg++, regval);
c906108c 1194 }
e5e33cd9
CV		 1195 /* Store the value reg_size bytes at a time. This means that things
1196 larger than reg_size bytes may go partly in registers and partly
c906108c 1197 on the stack. */
e5e33cd9
CV		 1198 len -= reg_size;
1199 val += reg_size;
c906108c
SS		 1200 }
1201 }
48db5a3c
CV		 1202
1203 /* Store return address. */
55ff77ac 1204 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
48db5a3c
CV		 1205
1206 /* Update stack pointer. */
1207 regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp);
1208
c906108c
SS		 1209 return sp;
1210}
1211
cc17453a
EZ		 1212/* Find a function's return value in the appropriate registers (in
1213 regbuf), and copy it into valbuf. Extract from an array REGBUF
1214 containing the (raw) register state a function return value of type
1215 TYPE, and copy that, in virtual format, into VALBUF. */
1216static void
3ffc5b9b
CV		 1217sh_extract_return_value_nofpu (struct type *type, struct regcache *regcache,
1218 void *valbuf)
c906108c 1219{
cc17453a 1220 int len = TYPE_LENGTH (type);
3116c80a
EZ		 1221 int return_register = R0_REGNUM;
1222 int offset;
617daa0e 1223
cc17453a 1224 if (len <= 4)
3116c80a 1225 {
48db5a3c
CV		 1226 ULONGEST c;
1227
1228 regcache_cooked_read_unsigned (regcache, R0_REGNUM, &c);
1229 store_unsigned_integer (valbuf, len, c);
3116c80a 1230 }
48db5a3c 1231 else if (len == 8)
3116c80a 1232 {
48db5a3c
CV		 1233 int i, regnum = R0_REGNUM;
1234 for (i = 0; i < len; i += 4)
617daa0e 1235 regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
3116c80a
EZ		 1236 }
1237 else
8a3fe4f8 1238 error (_("bad size for return value"));
3116c80a
EZ		 1239}
1240
1241static void
3ffc5b9b
CV		 1242sh_extract_return_value_fpu (struct type *type, struct regcache *regcache,
1243 void *valbuf)
3116c80a 1244{
afce3d2a 1245 if (sh_treat_as_flt_p (type))
3116c80a 1246 {
48db5a3c
CV		 1247 int len = TYPE_LENGTH (type);
1248 int i, regnum = FP0_REGNUM;
1249 for (i = 0; i < len; i += 4)
4c6b5505 1250 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE)
2e952408
CV		 1251 regcache_raw_read (regcache, regnum++, (char *) valbuf + len - 4 - i);
1252 else
1253 regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
3116c80a 1254 }
cc17453a 1255 else
3ffc5b9b 1256 sh_extract_return_value_nofpu (type, regcache, valbuf);
cc17453a 1257}
c906108c 1258
cc17453a
EZ		 1259/* Write into appropriate registers a function return value
1260 of type TYPE, given in virtual format.
1261 If the architecture is sh4 or sh3e, store a function's return value
1262 in the R0 general register or in the FP0 floating point register,
1263 depending on the type of the return value. In all the other cases
3bbfbb92 1264 the result is stored in r0, left-justified. */
cc17453a 1265static void
3ffc5b9b
CV		 1266sh_store_return_value_nofpu (struct type *type, struct regcache *regcache,
1267 const void *valbuf)
cc17453a 1268{
48db5a3c
CV		 1269 ULONGEST val;
1270 int len = TYPE_LENGTH (type);
d19b71be 1271
48db5a3c 1272 if (len <= 4)
d19b71be 1273 {
48db5a3c
CV		 1274 val = extract_unsigned_integer (valbuf, len);
1275 regcache_cooked_write_unsigned (regcache, R0_REGNUM, val);
d19b71be
MS		 1276 }
1277 else
48db5a3c
CV		 1278 {
1279 int i, regnum = R0_REGNUM;
1280 for (i = 0; i < len; i += 4)
617daa0e 1281 regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
48db5a3c 1282 }
cc17453a 1283}
c906108c 1284
cc17453a 1285static void
3ffc5b9b
CV		 1286sh_store_return_value_fpu (struct type *type, struct regcache *regcache,
1287 const void *valbuf)
cc17453a 1288{
afce3d2a 1289 if (sh_treat_as_flt_p (type))
48db5a3c
CV		 1290 {
1291 int len = TYPE_LENGTH (type);
1292 int i, regnum = FP0_REGNUM;
1293 for (i = 0; i < len; i += 4)
4c6b5505 1294 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE)
c8a3b559
CV		 1295 regcache_raw_write (regcache, regnum++,
1296 (char *) valbuf + len - 4 - i);
1297 else
1298 regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
48db5a3c 1299 }
cc17453a 1300 else
3ffc5b9b 1301 sh_store_return_value_nofpu (type, regcache, valbuf);
c906108c
SS		 1302}
1303
c0409442
CV		 1304static enum return_value_convention
1305sh_return_value_nofpu (struct gdbarch *gdbarch, struct type *type,
1306 struct regcache *regcache,
18cf8b5b 1307 gdb_byte *readbuf, const gdb_byte *writebuf)
c0409442
CV		 1308{
1309 if (sh_use_struct_convention (0, type))
1310 return RETURN_VALUE_STRUCT_CONVENTION;
1311 if (writebuf)
3ffc5b9b 1312 sh_store_return_value_nofpu (type, regcache, writebuf);
c0409442 1313 else if (readbuf)
3ffc5b9b 1314 sh_extract_return_value_nofpu (type, regcache, readbuf);
c0409442
CV		 1315 return RETURN_VALUE_REGISTER_CONVENTION;
1316}
1317
1318static enum return_value_convention
1319sh_return_value_fpu (struct gdbarch *gdbarch, struct type *type,
1320 struct regcache *regcache,
18cf8b5b 1321 gdb_byte *readbuf, const gdb_byte *writebuf)
c0409442
CV		 1322{
1323 if (sh_use_struct_convention (0, type))
1324 return RETURN_VALUE_STRUCT_CONVENTION;
1325 if (writebuf)
3ffc5b9b 1326 sh_store_return_value_fpu (type, regcache, writebuf);
c0409442 1327 else if (readbuf)
3ffc5b9b 1328 sh_extract_return_value_fpu (type, regcache, readbuf);
c0409442
CV		 1329 return RETURN_VALUE_REGISTER_CONVENTION;
1330}
1331
c906108c
SS		 1332/* Print the registers in a form similar to the E7000 */
1333
1334static void
c458d6db 1335sh_generic_show_regs (struct frame_info *frame)
c906108c 1336{
c458d6db
UW		 1337 printf_filtered
1338 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1339 paddr (get_frame_register_unsigned (frame, PC_REGNUM)),
1340 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1341 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1342 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
cc17453a 1343
c458d6db
UW		 1344 printf_filtered
1345 (" GBR %08lx VBR %08lx MACL %08lx\n",
1346 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1347 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1348 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
cc17453a 1349
617daa0e 1350 printf_filtered
a6b0a3f3 1351 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
c458d6db
UW		 1352 (long) get_frame_register_unsigned (frame, 0),
1353 (long) get_frame_register_unsigned (frame, 1),
1354 (long) get_frame_register_unsigned (frame, 2),
1355 (long) get_frame_register_unsigned (frame, 3),
1356 (long) get_frame_register_unsigned (frame, 4),
1357 (long) get_frame_register_unsigned (frame, 5),
1358 (long) get_frame_register_unsigned (frame, 6),
1359 (long) get_frame_register_unsigned (frame, 7));
1360 printf_filtered
1361 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1362 (long) get_frame_register_unsigned (frame, 8),
1363 (long) get_frame_register_unsigned (frame, 9),
1364 (long) get_frame_register_unsigned (frame, 10),
1365 (long) get_frame_register_unsigned (frame, 11),
1366 (long) get_frame_register_unsigned (frame, 12),
1367 (long) get_frame_register_unsigned (frame, 13),
1368 (long) get_frame_register_unsigned (frame, 14),
1369 (long) get_frame_register_unsigned (frame, 15));
cc17453a 1370}
c906108c 1371
cc17453a 1372static void
c458d6db 1373sh3_show_regs (struct frame_info *frame)
cc17453a 1374{
c458d6db
UW		 1375 printf_filtered
1376 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1377 paddr (get_frame_register_unsigned (frame, PC_REGNUM)),
1378 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1379 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1380 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1381
1382 printf_filtered
1383 (" GBR %08lx VBR %08lx MACL %08lx\n",
1384 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1385 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1386 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1387 printf_filtered
1388 (" SSR %08lx SPC %08lx\n",
1389 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1390 (long) get_frame_register_unsigned (frame, SPC_REGNUM));
c906108c 1391
617daa0e 1392 printf_filtered
a6b0a3f3 1393 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
c458d6db
UW		 1394 (long) get_frame_register_unsigned (frame, 0),
1395 (long) get_frame_register_unsigned (frame, 1),
1396 (long) get_frame_register_unsigned (frame, 2),
1397 (long) get_frame_register_unsigned (frame, 3),
1398 (long) get_frame_register_unsigned (frame, 4),
1399 (long) get_frame_register_unsigned (frame, 5),
1400 (long) get_frame_register_unsigned (frame, 6),
1401 (long) get_frame_register_unsigned (frame, 7));
1402 printf_filtered
1403 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1404 (long) get_frame_register_unsigned (frame, 8),
1405 (long) get_frame_register_unsigned (frame, 9),
1406 (long) get_frame_register_unsigned (frame, 10),
1407 (long) get_frame_register_unsigned (frame, 11),
1408 (long) get_frame_register_unsigned (frame, 12),
1409 (long) get_frame_register_unsigned (frame, 13),
1410 (long) get_frame_register_unsigned (frame, 14),
1411 (long) get_frame_register_unsigned (frame, 15));
c906108c
SS		 1412}
1413
2d188dd3 1414static void
c458d6db 1415sh2e_show_regs (struct frame_info *frame)
2d188dd3 1416{
c458d6db
UW		 1417 printf_filtered
1418 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1419 paddr (get_frame_register_unsigned (frame, PC_REGNUM)),
1420 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1421 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1422 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1423
1424 printf_filtered
1425 (" GBR %08lx VBR %08lx MACL %08lx\n",
1426 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1427 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1428 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1429 printf_filtered
1430 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1431 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1432 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1433 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1434 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
617daa0e
CV		 1435
1436 printf_filtered
a6b0a3f3 1437 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
c458d6db
UW		 1438 (long) get_frame_register_unsigned (frame, 0),
1439 (long) get_frame_register_unsigned (frame, 1),
1440 (long) get_frame_register_unsigned (frame, 2),
1441 (long) get_frame_register_unsigned (frame, 3),
1442 (long) get_frame_register_unsigned (frame, 4),
1443 (long) get_frame_register_unsigned (frame, 5),
1444 (long) get_frame_register_unsigned (frame, 6),
1445 (long) get_frame_register_unsigned (frame, 7));
1446 printf_filtered
1447 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1448 (long) get_frame_register_unsigned (frame, 8),
1449 (long) get_frame_register_unsigned (frame, 9),
1450 (long) get_frame_register_unsigned (frame, 10),
1451 (long) get_frame_register_unsigned (frame, 11),
1452 (long) get_frame_register_unsigned (frame, 12),
1453 (long) get_frame_register_unsigned (frame, 13),
1454 (long) get_frame_register_unsigned (frame, 14),
1455 (long) get_frame_register_unsigned (frame, 15));
1456
1457 printf_filtered
1458 ("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1459 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 0),
1460 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 1),
1461 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 2),
1462 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 3),
1463 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 4),
1464 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 5),
1465 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 6),
1466 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 7));
1467 printf_filtered
1468 ("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1469 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 8),
1470 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 9),
1471 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 10),
1472 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 11),
1473 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 12),
1474 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 13),
1475 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 14),
1476 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 15));
2d188dd3
NC		 1477}
1478
da962468 1479static void
c458d6db 1480sh2a_show_regs (struct frame_info *frame)
da962468 1481{
c458d6db
UW		 1482 int pr = get_frame_register_unsigned (frame, FPSCR_REGNUM) & 0x80000;
1483
1484 printf_filtered
1485 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1486 paddr (get_frame_register_unsigned (frame, PC_REGNUM)),
1487 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1488 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1489 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1490
1491 printf_filtered
1492 (" GBR %08lx VBR %08lx TBR %08lx MACL %08lx\n",
1493 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1494 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1495 (long) get_frame_register_unsigned (frame, TBR_REGNUM),
1496 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1497 printf_filtered
1498 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1499 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1500 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1501 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1502 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1503
1504 printf_filtered
1505 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1506 (long) get_frame_register_unsigned (frame, 0),
1507 (long) get_frame_register_unsigned (frame, 1),
1508 (long) get_frame_register_unsigned (frame, 2),
1509 (long) get_frame_register_unsigned (frame, 3),
1510 (long) get_frame_register_unsigned (frame, 4),
1511 (long) get_frame_register_unsigned (frame, 5),
1512 (long) get_frame_register_unsigned (frame, 6),
1513 (long) get_frame_register_unsigned (frame, 7));
1514 printf_filtered
1515 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1516 (long) get_frame_register_unsigned (frame, 8),
1517 (long) get_frame_register_unsigned (frame, 9),
1518 (long) get_frame_register_unsigned (frame, 10),
1519 (long) get_frame_register_unsigned (frame, 11),
1520 (long) get_frame_register_unsigned (frame, 12),
1521 (long) get_frame_register_unsigned (frame, 13),
1522 (long) get_frame_register_unsigned (frame, 14),
1523 (long) get_frame_register_unsigned (frame, 15));
1524
1525 printf_filtered
1526 (pr ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1527 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1528 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 0),
1529 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 1),
1530 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 2),
1531 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 3),
1532 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 4),
1533 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 5),
1534 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 6),
1535 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 7));
1536 printf_filtered
1537 (pr ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1538 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1539 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 8),
1540 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 9),
1541 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 10),
1542 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 11),
1543 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 12),
1544 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 13),
1545 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 14),
1546 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 15));
1547 printf_filtered
1548 ("BANK=%-3d\n", (int) get_frame_register_unsigned (frame, BANK_REGNUM));
1549 printf_filtered
1550 ("R0b-R7b %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1551 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 0),
1552 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 1),
1553 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 2),
1554 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 3),
1555 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 4),
1556 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 5),
1557 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 6),
1558 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 7));
1559 printf_filtered
1560 ("R8b-R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1561 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 8),
1562 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 9),
1563 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 10),
1564 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 11),
1565 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 12),
1566 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 13),
1567 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 14));
1568 printf_filtered
1569 ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n",
1570 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 15),
1571 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 16),
1572 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 17),
1573 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 18),
1574 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 19));
da962468
CV		 1575}
1576
1577static void
c458d6db 1578sh2a_nofpu_show_regs (struct frame_info *frame)
da962468 1579{
c458d6db
UW		 1580 int pr = get_frame_register_unsigned (frame, FPSCR_REGNUM) & 0x80000;
1581
1582 printf_filtered
1583 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1584 paddr (get_frame_register_unsigned (frame, PC_REGNUM)),
1585 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1586 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1587 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1588
1589 printf_filtered
1590 (" GBR %08lx VBR %08lx TBR %08lx MACL %08lx\n",
1591 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1592 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1593 (long) get_frame_register_unsigned (frame, TBR_REGNUM),
1594 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1595 printf_filtered
1596 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1597 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1598 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1599 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1600 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1601
1602 printf_filtered
1603 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1604 (long) get_frame_register_unsigned (frame, 0),
1605 (long) get_frame_register_unsigned (frame, 1),
1606 (long) get_frame_register_unsigned (frame, 2),
1607 (long) get_frame_register_unsigned (frame, 3),
1608 (long) get_frame_register_unsigned (frame, 4),
1609 (long) get_frame_register_unsigned (frame, 5),
1610 (long) get_frame_register_unsigned (frame, 6),
1611 (long) get_frame_register_unsigned (frame, 7));
1612 printf_filtered
1613 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1614 (long) get_frame_register_unsigned (frame, 8),
1615 (long) get_frame_register_unsigned (frame, 9),
1616 (long) get_frame_register_unsigned (frame, 10),
1617 (long) get_frame_register_unsigned (frame, 11),
1618 (long) get_frame_register_unsigned (frame, 12),
1619 (long) get_frame_register_unsigned (frame, 13),
1620 (long) get_frame_register_unsigned (frame, 14),
1621 (long) get_frame_register_unsigned (frame, 15));
1622
1623 printf_filtered
1624 ("BANK=%-3d\n", (int) get_frame_register_unsigned (frame, BANK_REGNUM));
1625 printf_filtered
1626 ("R0b-R7b %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1627 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 0),
1628 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 1),
1629 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 2),
1630 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 3),
1631 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 4),
1632 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 5),
1633 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 6),
1634 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 7));
1635 printf_filtered
1636 ("R8b-R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1637 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 8),
1638 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 9),
1639 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 10),
1640 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 11),
1641 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 12),
1642 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 13),
1643 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 14));
1644 printf_filtered
1645 ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n",
1646 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 15),
1647 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 16),
1648 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 17),
1649 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 18),
1650 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 19));
da962468
CV		 1651}
1652
cc17453a 1653static void
c458d6db 1654sh3e_show_regs (struct frame_info *frame)
cc17453a 1655{
c458d6db
UW		 1656 printf_filtered
1657 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1658 paddr (get_frame_register_unsigned (frame, PC_REGNUM)),
1659 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1660 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1661 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1662
1663 printf_filtered
1664 (" GBR %08lx VBR %08lx MACL %08lx\n",
1665 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1666 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1667 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1668 printf_filtered
1669 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1670 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1671 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1672 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1673 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
c906108c 1674
617daa0e 1675 printf_filtered
a6b0a3f3 1676 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
c458d6db
UW		 1677 (long) get_frame_register_unsigned (frame, 0),
1678 (long) get_frame_register_unsigned (frame, 1),
1679 (long) get_frame_register_unsigned (frame, 2),
1680 (long) get_frame_register_unsigned (frame, 3),
1681 (long) get_frame_register_unsigned (frame, 4),
1682 (long) get_frame_register_unsigned (frame, 5),
1683 (long) get_frame_register_unsigned (frame, 6),
1684 (long) get_frame_register_unsigned (frame, 7));
1685 printf_filtered
1686 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1687 (long) get_frame_register_unsigned (frame, 8),
1688 (long) get_frame_register_unsigned (frame, 9),
1689 (long) get_frame_register_unsigned (frame, 10),
1690 (long) get_frame_register_unsigned (frame, 11),
1691 (long) get_frame_register_unsigned (frame, 12),
1692 (long) get_frame_register_unsigned (frame, 13),
1693 (long) get_frame_register_unsigned (frame, 14),
1694 (long) get_frame_register_unsigned (frame, 15));
1695
1696 printf_filtered
1697 ("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1698 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 0),
1699 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 1),
1700 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 2),
1701 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 3),
1702 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 4),
1703 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 5),
1704 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 6),
1705 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 7));
1706 printf_filtered
1707 ("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1708 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 8),
1709 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 9),
1710 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 10),
1711 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 11),
1712 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 12),
1713 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 13),
1714 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 14),
1715 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 15));
cc17453a
EZ		 1716}
1717
1718static void
c458d6db 1719sh3_dsp_show_regs (struct frame_info *frame)
c906108c 1720{
c458d6db
UW		 1721 printf_filtered
1722 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1723 paddr (get_frame_register_unsigned (frame, PC_REGNUM)),
1724 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1725 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1726 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
c906108c 1727
c458d6db
UW		 1728 printf_filtered
1729 (" GBR %08lx VBR %08lx MACL %08lx\n",
1730 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1731 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1732 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
cc17453a 1733
c458d6db
UW		 1734 printf_filtered
1735 (" SSR %08lx SPC %08lx DSR %08lx\n",
1736 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1737 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1738 (long) get_frame_register_unsigned (frame, DSR_REGNUM));
617daa0e
CV		 1739
1740 printf_filtered
a6b0a3f3 1741 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
c458d6db
UW		 1742 (long) get_frame_register_unsigned (frame, 0),
1743 (long) get_frame_register_unsigned (frame, 1),
1744 (long) get_frame_register_unsigned (frame, 2),
1745 (long) get_frame_register_unsigned (frame, 3),
1746 (long) get_frame_register_unsigned (frame, 4),
1747 (long) get_frame_register_unsigned (frame, 5),
1748 (long) get_frame_register_unsigned (frame, 6),
1749 (long) get_frame_register_unsigned (frame, 7));
1750 printf_filtered
1751 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1752 (long) get_frame_register_unsigned (frame, 8),
1753 (long) get_frame_register_unsigned (frame, 9),
1754 (long) get_frame_register_unsigned (frame, 10),
1755 (long) get_frame_register_unsigned (frame, 11),
1756 (long) get_frame_register_unsigned (frame, 12),
1757 (long) get_frame_register_unsigned (frame, 13),
1758 (long) get_frame_register_unsigned (frame, 14),
1759 (long) get_frame_register_unsigned (frame, 15));
617daa0e
CV		 1760
1761 printf_filtered
1762 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
c458d6db
UW		 1763 (long) get_frame_register_unsigned (frame, A0G_REGNUM) & 0xff,
1764 (long) get_frame_register_unsigned (frame, A0_REGNUM),
1765 (long) get_frame_register_unsigned (frame, M0_REGNUM),
1766 (long) get_frame_register_unsigned (frame, X0_REGNUM),
1767 (long) get_frame_register_unsigned (frame, Y0_REGNUM),
1768 (long) get_frame_register_unsigned (frame, RS_REGNUM),
1769 (long) get_frame_register_unsigned (frame, MOD_REGNUM));
1770 printf_filtered
1771 ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1772 (long) get_frame_register_unsigned (frame, A1G_REGNUM) & 0xff,
1773 (long) get_frame_register_unsigned (frame, A1_REGNUM),
1774 (long) get_frame_register_unsigned (frame, M1_REGNUM),
1775 (long) get_frame_register_unsigned (frame, X1_REGNUM),
1776 (long) get_frame_register_unsigned (frame, Y1_REGNUM),
1777 (long) get_frame_register_unsigned (frame, RE_REGNUM));
c906108c
SS		 1778}
1779
cc17453a 1780static void
c458d6db 1781sh4_show_regs (struct frame_info *frame)
cc17453a 1782{
c458d6db
UW		 1783 int pr = get_frame_register_unsigned (frame, FPSCR_REGNUM) & 0x80000;
1784
1785 printf_filtered
1786 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1787 paddr (get_frame_register_unsigned (frame, PC_REGNUM)),
1788 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1789 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1790 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1791
1792 printf_filtered
1793 (" GBR %08lx VBR %08lx MACL %08lx\n",
1794 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1795 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1796 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1797 printf_filtered
1798 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1799 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1800 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1801 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1802 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1803
1804 printf_filtered
1805 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1806 (long) get_frame_register_unsigned (frame, 0),
1807 (long) get_frame_register_unsigned (frame, 1),
1808 (long) get_frame_register_unsigned (frame, 2),
1809 (long) get_frame_register_unsigned (frame, 3),
1810 (long) get_frame_register_unsigned (frame, 4),
1811 (long) get_frame_register_unsigned (frame, 5),
1812 (long) get_frame_register_unsigned (frame, 6),
1813 (long) get_frame_register_unsigned (frame, 7));
1814 printf_filtered
1815 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1816 (long) get_frame_register_unsigned (frame, 8),
1817 (long) get_frame_register_unsigned (frame, 9),
1818 (long) get_frame_register_unsigned (frame, 10),
1819 (long) get_frame_register_unsigned (frame, 11),
1820 (long) get_frame_register_unsigned (frame, 12),
1821 (long) get_frame_register_unsigned (frame, 13),
1822 (long) get_frame_register_unsigned (frame, 14),
1823 (long) get_frame_register_unsigned (frame, 15));
1824
1825 printf_filtered
1826 (pr ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1827 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1828 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 0),
1829 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 1),
1830 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 2),
1831 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 3),
1832 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 4),
1833 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 5),
1834 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 6),
1835 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 7));
1836 printf_filtered
1837 (pr ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1838 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1839 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 8),
1840 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 9),
1841 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 10),
1842 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 11),
1843 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 12),
1844 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 13),
1845 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 14),
1846 (long) get_frame_register_unsigned (frame, FP0_REGNUM + 15));
cc17453a
EZ		 1847}
1848
474e5826 1849static void
c458d6db 1850sh4_nofpu_show_regs (struct frame_info *frame)
474e5826 1851{
c458d6db
UW		 1852 printf_filtered
1853 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1854 paddr (get_frame_register_unsigned (frame, PC_REGNUM)),
1855 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1856 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1857 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1858
1859 printf_filtered
1860 (" GBR %08lx VBR %08lx MACL %08lx\n",
1861 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1862 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1863 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1864 printf_filtered
1865 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1866 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1867 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1868 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1869 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1870
1871 printf_filtered
1872 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1873 (long) get_frame_register_unsigned (frame, 0),
1874 (long) get_frame_register_unsigned (frame, 1),
1875 (long) get_frame_register_unsigned (frame, 2),
1876 (long) get_frame_register_unsigned (frame, 3),
1877 (long) get_frame_register_unsigned (frame, 4),
1878 (long) get_frame_register_unsigned (frame, 5),
1879 (long) get_frame_register_unsigned (frame, 6),
1880 (long) get_frame_register_unsigned (frame, 7));
1881 printf_filtered
1882 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1883 (long) get_frame_register_unsigned (frame, 8),
1884 (long) get_frame_register_unsigned (frame, 9),
1885 (long) get_frame_register_unsigned (frame, 10),
1886 (long) get_frame_register_unsigned (frame, 11),
1887 (long) get_frame_register_unsigned (frame, 12),
1888 (long) get_frame_register_unsigned (frame, 13),
1889 (long) get_frame_register_unsigned (frame, 14),
1890 (long) get_frame_register_unsigned (frame, 15));
474e5826
CV		 1891}
1892
cc17453a 1893static void
c458d6db 1894sh_dsp_show_regs (struct frame_info *frame)
cc17453a 1895{
c458d6db
UW		 1896 printf_filtered
1897 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1898 paddr (get_frame_register_unsigned (frame, PC_REGNUM)),
1899 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1900 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1901 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
a6b0a3f3 1902
c458d6db
UW		 1903 printf_filtered
1904 (" GBR %08lx VBR %08lx DSR %08lx MACL %08lx\n",
1905 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1906 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1907 (long) get_frame_register_unsigned (frame, DSR_REGNUM),
1908 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
617daa0e
CV		 1909
1910 printf_filtered
a6b0a3f3 1911 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
c458d6db
UW		 1912 (long) get_frame_register_unsigned (frame, 0),
1913 (long) get_frame_register_unsigned (frame, 1),
1914 (long) get_frame_register_unsigned (frame, 2),
1915 (long) get_frame_register_unsigned (frame, 3),
1916 (long) get_frame_register_unsigned (frame, 4),
1917 (long) get_frame_register_unsigned (frame, 5),
1918 (long) get_frame_register_unsigned (frame, 6),
1919 (long) get_frame_register_unsigned (frame, 7));
1920 printf_filtered
1921 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1922 (long) get_frame_register_unsigned (frame, 8),
1923 (long) get_frame_register_unsigned (frame, 9),
1924 (long) get_frame_register_unsigned (frame, 10),
1925 (long) get_frame_register_unsigned (frame, 11),
1926 (long) get_frame_register_unsigned (frame, 12),
1927 (long) get_frame_register_unsigned (frame, 13),
1928 (long) get_frame_register_unsigned (frame, 14),
1929 (long) get_frame_register_unsigned (frame, 15));
617daa0e
CV		 1930
1931 printf_filtered
1932 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
c458d6db
UW		 1933 (long) get_frame_register_unsigned (frame, A0G_REGNUM) & 0xff,
1934 (long) get_frame_register_unsigned (frame, A0_REGNUM),
1935 (long) get_frame_register_unsigned (frame, M0_REGNUM),
1936 (long) get_frame_register_unsigned (frame, X0_REGNUM),
1937 (long) get_frame_register_unsigned (frame, Y0_REGNUM),
1938 (long) get_frame_register_unsigned (frame, RS_REGNUM),
1939 (long) get_frame_register_unsigned (frame, MOD_REGNUM));
cc17453a 1940 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
c458d6db
UW		 1941 (long) get_frame_register_unsigned (frame, A1G_REGNUM) & 0xff,
1942 (long) get_frame_register_unsigned (frame, A1_REGNUM),
1943 (long) get_frame_register_unsigned (frame, M1_REGNUM),
1944 (long) get_frame_register_unsigned (frame, X1_REGNUM),
1945 (long) get_frame_register_unsigned (frame, Y1_REGNUM),
1946 (long) get_frame_register_unsigned (frame, RE_REGNUM));
cc17453a
EZ		 1947}
1948
a78f21af
AC		 1949static void
1950sh_show_regs_command (char *args, int from_tty)
53116e27
EZ		 1951{
1952 if (sh_show_regs)
c458d6db 1953 (*sh_show_regs) (get_current_frame ());
53116e27
EZ		 1954}
1955
da962468
CV		 1956static struct type *
1957sh_sh2a_register_type (struct gdbarch *gdbarch, int reg_nr)
1958{
1959 if ((reg_nr >= FP0_REGNUM
1960 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
1961 return builtin_type_float;
1962 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
1963 return builtin_type_double;
1964 else
1965 return builtin_type_int;
1966}
1967
cc17453a
EZ		 1968/* Return the GDB type object for the "standard" data type
1969 of data in register N. */
cc17453a 1970static struct type *
48db5a3c 1971sh_sh3e_register_type (struct gdbarch *gdbarch, int reg_nr)
cc17453a
EZ		 1972{
1973 if ((reg_nr >= FP0_REGNUM
617daa0e 1974 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
cc17453a 1975 return builtin_type_float;
8db62801 1976 else
cc17453a
EZ		 1977 return builtin_type_int;
1978}
1979
7f4dbe94
EZ		 1980static struct type *
1981sh_sh4_build_float_register_type (int high)
1982{
1983 struct type *temp;
1984
1985 temp = create_range_type (NULL, builtin_type_int, 0, high);
1986 return create_array_type (NULL, builtin_type_float, temp);
1987}
1988
53116e27 1989static struct type *
48db5a3c 1990sh_sh4_register_type (struct gdbarch *gdbarch, int reg_nr)
53116e27
EZ		 1991{
1992 if ((reg_nr >= FP0_REGNUM
617daa0e 1993 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
53116e27 1994 return builtin_type_float;
617daa0e 1995 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
53116e27 1996 return builtin_type_double;
617daa0e 1997 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
53116e27
EZ		 1998 return sh_sh4_build_float_register_type (3);
1999 else
2000 return builtin_type_int;
2001}
2002
cc17453a 2003static struct type *
48db5a3c 2004sh_default_register_type (struct gdbarch *gdbarch, int reg_nr)
cc17453a
EZ		 2005{
2006 return builtin_type_int;
2007}
2008
dda63807
AS		 2009/* Is a register in a reggroup?
2010 The default code in reggroup.c doesn't identify system registers, some
2011 float registers or any of the vector registers.
2012 TODO: sh2a and dsp registers. */
2013int
2014sh_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2015 struct reggroup *reggroup)
2016{
c9f4d572
UW		 2017 if (gdbarch_register_name (current_gdbarch, regnum) == NULL
2018 || *gdbarch_register_name (current_gdbarch, regnum) == '\0')
dda63807
AS		 2019 return 0;
2020
2021 if (reggroup == float_reggroup
2022 && (regnum == FPUL_REGNUM
2023 || regnum == FPSCR_REGNUM))
2024 return 1;
2025
2026 if (regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM)
2027 {
2028 if (reggroup == vector_reggroup || reggroup == float_reggroup)
2029 return 1;
2030 if (reggroup == general_reggroup)
2031 return 0;
2032 }
2033
2034 if (regnum == VBR_REGNUM
2035 || regnum == SR_REGNUM
2036 || regnum == FPSCR_REGNUM
2037 || regnum == SSR_REGNUM
2038 || regnum == SPC_REGNUM)
2039 {
2040 if (reggroup == system_reggroup)
2041 return 1;
2042 if (reggroup == general_reggroup)
2043 return 0;
2044 }
2045
2046 /* The default code can cope with any other registers. */
2047 return default_register_reggroup_p (gdbarch, regnum, reggroup);
2048}
2049
fb409745
EZ		 2050/* On the sh4, the DRi pseudo registers are problematic if the target
2051 is little endian. When the user writes one of those registers, for
2052 instance with 'ser var $dr0=1', we want the double to be stored
2053 like this:
2054 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
2055 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2056
2057 This corresponds to little endian byte order & big endian word
2058 order. However if we let gdb write the register w/o conversion, it
2059 will write fr0 and fr1 this way:
2060 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2061 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
2062 because it will consider fr0 and fr1 as a single LE stretch of memory.
2063
2064 To achieve what we want we must force gdb to store things in
2065 floatformat_ieee_double_littlebyte_bigword (which is defined in
2066 include/floatformat.h and libiberty/floatformat.c.
2067
2068 In case the target is big endian, there is no problem, the
2069 raw bytes will look like:
2070 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
2071 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2072
2073 The other pseudo registers (the FVs) also don't pose a problem
2074 because they are stored as 4 individual FP elements. */
2075
7bd872fe 2076static void
b66ba949
CV		 2077sh_register_convert_to_virtual (int regnum, struct type *type,
2078 char *from, char *to)
55ff77ac 2079{
617daa0e 2080 if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
283150cd
EZ		 2081 {
2082 DOUBLEST val;
617daa0e
CV		 2083 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
2084 from, &val);
55ff77ac 2085 store_typed_floating (to, type, val);
283150cd
EZ		 2086 }
2087 else
617daa0e
CV		 2088 error
2089 ("sh_register_convert_to_virtual called with non DR register number");
283150cd
EZ		 2090}
2091
2092static void
b66ba949
CV		 2093sh_register_convert_to_raw (struct type *type, int regnum,
2094 const void *from, void *to)
283150cd 2095{
617daa0e 2096 if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
283150cd 2097 {
48db5a3c 2098 DOUBLEST val = extract_typed_floating (from, type);
617daa0e
CV		 2099 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword,
2100 &val, to);
283150cd
EZ		 2101 }
2102 else
8a3fe4f8 2103 error (_("sh_register_convert_to_raw called with non DR register number"));
283150cd
EZ		 2104}
2105
1c0159e0
CV		 2106/* For vectors of 4 floating point registers. */
2107static int
2108fv_reg_base_num (int fv_regnum)
2109{
2110 int fp_regnum;
2111
617daa0e 2112 fp_regnum = FP0_REGNUM + (fv_regnum - FV0_REGNUM) * 4;
1c0159e0
CV		 2113 return fp_regnum;
2114}
2115
2116/* For double precision floating point registers, i.e 2 fp regs.*/
2117static int
2118dr_reg_base_num (int dr_regnum)
2119{
2120 int fp_regnum;
2121
617daa0e 2122 fp_regnum = FP0_REGNUM + (dr_regnum - DR0_REGNUM) * 2;
1c0159e0
CV		 2123 return fp_regnum;
2124}
2125
a78f21af 2126static void
d8124050 2127sh_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
18cf8b5b 2128 int reg_nr, gdb_byte *buffer)
53116e27
EZ		 2129{
2130 int base_regnum, portion;
d9d9c31f 2131 char temp_buffer[MAX_REGISTER_SIZE];
53116e27 2132
9bed62d7
CV		 2133 if (reg_nr == PSEUDO_BANK_REGNUM)
2134 regcache_raw_read (regcache, BANK_REGNUM, buffer);
2135 else
617daa0e 2136 if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
7bd872fe
EZ		 2137 {
2138 base_regnum = dr_reg_base_num (reg_nr);
2139
617daa0e 2140 /* Build the value in the provided buffer. */
7bd872fe
EZ		 2141 /* Read the real regs for which this one is an alias. */
2142 for (portion = 0; portion < 2; portion++)
617daa0e 2143 regcache_raw_read (regcache, base_regnum + portion,
0818c12a 2144 (temp_buffer
617daa0e
CV		 2145 + register_size (gdbarch,
2146 base_regnum) * portion));
7bd872fe 2147 /* We must pay attention to the endiannes. */
b66ba949 2148 sh_register_convert_to_virtual (reg_nr,
7b9ee6a8 2149 register_type (gdbarch, reg_nr),
b66ba949 2150 temp_buffer, buffer);
7bd872fe 2151 }
617daa0e 2152 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
53116e27 2153 {
7bd872fe
EZ		 2154 base_regnum = fv_reg_base_num (reg_nr);
2155
2156 /* Read the real regs for which this one is an alias. */
2157 for (portion = 0; portion < 4; portion++)
617daa0e 2158 regcache_raw_read (regcache, base_regnum + portion,
d8124050 2159 ((char *) buffer
617daa0e
CV		 2160 + register_size (gdbarch,
2161 base_regnum) * portion));
53116e27
EZ		 2162 }
2163}
2164
a78f21af 2165static void
d8124050 2166sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
18cf8b5b 2167 int reg_nr, const gdb_byte *buffer)
53116e27
EZ		 2168{
2169 int base_regnum, portion;
d9d9c31f 2170 char temp_buffer[MAX_REGISTER_SIZE];
53116e27 2171
9bed62d7
CV		 2172 if (reg_nr == PSEUDO_BANK_REGNUM)
2173 {
2174 /* When the bank register is written to, the whole register bank
2175 is switched and all values in the bank registers must be read
2176 from the target/sim again. We're just invalidating the regcache
2177 so that a re-read happens next time it's necessary. */
2178 int bregnum;
2179
2180 regcache_raw_write (regcache, BANK_REGNUM, buffer);
2181 for (bregnum = R0_BANK0_REGNUM; bregnum < MACLB_REGNUM; ++bregnum)
9c5ea4d9 2182 regcache_invalidate (regcache, bregnum);
9bed62d7
CV		 2183 }
2184 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
53116e27
EZ		 2185 {
2186 base_regnum = dr_reg_base_num (reg_nr);
2187
7bd872fe 2188 /* We must pay attention to the endiannes. */
7b9ee6a8 2189 sh_register_convert_to_raw (register_type (gdbarch, reg_nr),
b66ba949 2190 reg_nr, buffer, temp_buffer);
7bd872fe 2191
53116e27
EZ		 2192 /* Write the real regs for which this one is an alias. */
2193 for (portion = 0; portion < 2; portion++)
617daa0e 2194 regcache_raw_write (regcache, base_regnum + portion,
0818c12a 2195 (temp_buffer
617daa0e
CV		 2196 + register_size (gdbarch,
2197 base_regnum) * portion));
53116e27 2198 }
617daa0e 2199 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
53116e27
EZ		 2200 {
2201 base_regnum = fv_reg_base_num (reg_nr);
2202
2203 /* Write the real regs for which this one is an alias. */
2204 for (portion = 0; portion < 4; portion++)
d8124050
AC		 2205 regcache_raw_write (regcache, base_regnum + portion,
2206 ((char *) buffer
617daa0e
CV		 2207 + register_size (gdbarch,
2208 base_regnum) * portion));
53116e27
EZ		 2209 }
2210}
2211
2f14585c
JR		 2212static int
2213sh_dsp_register_sim_regno (int nr)
2214{
2215 if (legacy_register_sim_regno (nr) < 0)
2216 return legacy_register_sim_regno (nr);
f2ea0907
CV		 2217 if (nr >= DSR_REGNUM && nr <= Y1_REGNUM)
2218 return nr - DSR_REGNUM + SIM_SH_DSR_REGNUM;
2219 if (nr == MOD_REGNUM)
2f14585c 2220 return SIM_SH_MOD_REGNUM;
f2ea0907 2221 if (nr == RS_REGNUM)
2f14585c 2222 return SIM_SH_RS_REGNUM;
f2ea0907 2223 if (nr == RE_REGNUM)
2f14585c 2224 return SIM_SH_RE_REGNUM;
76cd2bd9
CV		 2225 if (nr >= DSP_R0_BANK_REGNUM && nr <= DSP_R7_BANK_REGNUM)
2226 return nr - DSP_R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM;
2f14585c
JR		 2227 return nr;
2228}
1c0159e0 2229
da962468
CV		 2230static int
2231sh_sh2a_register_sim_regno (int nr)
2232{
2233 switch (nr)
2234 {
2235 case TBR_REGNUM:
2236 return SIM_SH_TBR_REGNUM;
2237 case IBNR_REGNUM:
2238 return SIM_SH_IBNR_REGNUM;
2239 case IBCR_REGNUM:
2240 return SIM_SH_IBCR_REGNUM;
2241 case BANK_REGNUM:
2242 return SIM_SH_BANK_REGNUM;
2243 case MACLB_REGNUM:
2244 return SIM_SH_BANK_MACL_REGNUM;
2245 case GBRB_REGNUM:
2246 return SIM_SH_BANK_GBR_REGNUM;
2247 case PRB_REGNUM:
2248 return SIM_SH_BANK_PR_REGNUM;
2249 case IVNB_REGNUM:
2250 return SIM_SH_BANK_IVN_REGNUM;
2251 case MACHB_REGNUM:
2252 return SIM_SH_BANK_MACH_REGNUM;
2253 default:
2254 break;
2255 }
2256 return legacy_register_sim_regno (nr);
2257}
2258
357d3800
AS		 2259/* Set up the register unwinding such that call-clobbered registers are
2260 not displayed in frames >0 because the true value is not certain.
2261 The 'undefined' registers will show up as 'not available' unless the
2262 CFI says otherwise.
2263
2264 This function is currently set up for SH4 and compatible only. */
2265
2266static void
2267sh_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
aff37fc1
DM		 2268 struct dwarf2_frame_state_reg *reg,
2269 struct frame_info *next_frame)
357d3800
AS		 2270{
2271 /* Mark the PC as the destination for the return address. */
2272 if (regnum == PC_REGNUM)
2273 reg->how = DWARF2_FRAME_REG_RA;
2274
2275 /* Mark the stack pointer as the call frame address. */
2276 else if (regnum == SP_REGNUM)
2277 reg->how = DWARF2_FRAME_REG_CFA;
2278
2279 /* The above was taken from the default init_reg in dwarf2-frame.c
2280 while the below is SH specific. */
2281
2282 /* Caller save registers. */
2283 else if ((regnum >= R0_REGNUM && regnum <= R0_REGNUM+7)
2284 || (regnum >= FR0_REGNUM && regnum <= FR0_REGNUM+11)
2285 || (regnum >= DR0_REGNUM && regnum <= DR0_REGNUM+5)
2286 || (regnum >= FV0_REGNUM && regnum <= FV0_REGNUM+2)
2287 || (regnum == MACH_REGNUM)
2288 || (regnum == MACL_REGNUM)
2289 || (regnum == FPUL_REGNUM)
2290 || (regnum == SR_REGNUM))
2291 reg->how = DWARF2_FRAME_REG_UNDEFINED;
2292
2293 /* Callee save registers. */
2294 else if ((regnum >= R0_REGNUM+8 && regnum <= R0_REGNUM+15)
2295 || (regnum >= FR0_REGNUM+12 && regnum <= FR0_REGNUM+15)
2296 || (regnum >= DR0_REGNUM+6 && regnum <= DR0_REGNUM+8)
2297 || (regnum == FV0_REGNUM+3))
2298 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
2299
2300 /* Other registers. These are not in the ABI and may or may not
2301 mean anything in frames >0 so don't show them. */
2302 else if ((regnum >= R0_BANK0_REGNUM && regnum <= R0_BANK0_REGNUM+15)
2303 || (regnum == GBR_REGNUM)
2304 || (regnum == VBR_REGNUM)
2305 || (regnum == FPSCR_REGNUM)
2306 || (regnum == SSR_REGNUM)
2307 || (regnum == SPC_REGNUM))
2308 reg->how = DWARF2_FRAME_REG_UNDEFINED;
2309}
2310
1c0159e0
CV		 2311static struct sh_frame_cache *
2312sh_alloc_frame_cache (void)
2313{
2314 struct sh_frame_cache *cache;
2315 int i;
2316
2317 cache = FRAME_OBSTACK_ZALLOC (struct sh_frame_cache);
2318
2319 /* Base address. */
2320 cache->base = 0;
2321 cache->saved_sp = 0;
2322 cache->sp_offset = 0;
2323 cache->pc = 0;
2324
2325 /* Frameless until proven otherwise. */
2326 cache->uses_fp = 0;
617daa0e 2327
1c0159e0
CV		 2328 /* Saved registers. We initialize these to -1 since zero is a valid
2329 offset (that's where fp is supposed to be stored). */
2330 for (i = 0; i < SH_NUM_REGS; i++)
2331 {
2332 cache->saved_regs[i] = -1;
2333 }
617daa0e 2334
1c0159e0 2335 return cache;
617daa0e 2336}
1c0159e0
CV		 2337
2338static struct sh_frame_cache *
2339sh_frame_cache (struct frame_info *next_frame, void **this_cache)
2340{
2341 struct sh_frame_cache *cache;
2342 CORE_ADDR current_pc;
2343 int i;
2344
2345 if (*this_cache)
2346 return *this_cache;
2347
2348 cache = sh_alloc_frame_cache ();
2349 *this_cache = cache;
2350
2351 /* In principle, for normal frames, fp holds the frame pointer,
2352 which holds the base address for the current stack frame.
2353 However, for functions that don't need it, the frame pointer is
2354 optional. For these "frameless" functions the frame pointer is
2355 actually the frame pointer of the calling frame. */
2356 cache->base = frame_unwind_register_unsigned (next_frame, FP_REGNUM);
2357 if (cache->base == 0)
2358 return cache;
2359
93d42b30 2360 cache->pc = frame_func_unwind (next_frame, NORMAL_FRAME);
1c0159e0
CV		 2361 current_pc = frame_pc_unwind (next_frame);
2362 if (cache->pc != 0)
d2ca4222
UW		 2363 {
2364 ULONGEST fpscr;
2365 fpscr = frame_unwind_register_unsigned (next_frame, FPSCR_REGNUM);
2366 sh_analyze_prologue (cache->pc, current_pc, cache, fpscr);
2367 }
617daa0e 2368
1c0159e0
CV		 2369 if (!cache->uses_fp)
2370 {
2371 /* We didn't find a valid frame, which means that CACHE->base
2372 currently holds the frame pointer for our calling frame. If
2373 we're at the start of a function, or somewhere half-way its
2374 prologue, the function's frame probably hasn't been fully
2375 setup yet. Try to reconstruct the base address for the stack
2376 frame by looking at the stack pointer. For truly "frameless"
2377 functions this might work too. */
2378 cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
2379 }
2380
2381 /* Now that we have the base address for the stack frame we can
2382 calculate the value of sp in the calling frame. */
2383 cache->saved_sp = cache->base + cache->sp_offset;
2384
2385 /* Adjust all the saved registers such that they contain addresses
2386 instead of offsets. */
2387 for (i = 0; i < SH_NUM_REGS; i++)
2388 if (cache->saved_regs[i] != -1)
2389 cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i] - 4;
2390
2391 return cache;
2392}
2393
2394static void
2395sh_frame_prev_register (struct frame_info *next_frame, void **this_cache,
2396 int regnum, int *optimizedp,
2397 enum lval_type *lvalp, CORE_ADDR *addrp,
18cf8b5b 2398 int *realnump, gdb_byte *valuep)
1c0159e0
CV		 2399{
2400 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
2401
2402 gdb_assert (regnum >= 0);
2403
2404 if (regnum == SP_REGNUM && cache->saved_sp)
2405 {
2406 *optimizedp = 0;
2407 *lvalp = not_lval;
2408 *addrp = 0;
2409 *realnump = -1;
2410 if (valuep)
617daa0e
CV		 2411 {
2412 /* Store the value. */
2413 store_unsigned_integer (valuep, 4, cache->saved_sp);
2414 }
1c0159e0
CV		 2415 return;
2416 }
2417
2418 /* The PC of the previous frame is stored in the PR register of
2419 the current frame. Frob regnum so that we pull the value from
2420 the correct place. */
2421 if (regnum == PC_REGNUM)
2422 regnum = PR_REGNUM;
2423
2424 if (regnum < SH_NUM_REGS && cache->saved_regs[regnum] != -1)
2425 {
2426 *optimizedp = 0;
2427 *lvalp = lval_memory;
2428 *addrp = cache->saved_regs[regnum];
2429 *realnump = -1;
2430 if (valuep)
617daa0e
CV		 2431 {
2432 /* Read the value in from memory. */
2433 read_memory (*addrp, valuep,
2434 register_size (current_gdbarch, regnum));
2435 }
1c0159e0
CV		 2436 return;
2437 }
2438
00b25ff3
AC		 2439 *optimizedp = 0;
2440 *lvalp = lval_register;
2441 *addrp = 0;
2442 *realnump = regnum;
2443 if (valuep)
2444 frame_unwind_register (next_frame, (*realnump), valuep);
1c0159e0
CV		 2445}
2446
2447static void
2448sh_frame_this_id (struct frame_info *next_frame, void **this_cache,
617daa0e
CV		 2449 struct frame_id *this_id)
2450{
1c0159e0
CV		 2451 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
2452
2453 /* This marks the outermost frame. */
2454 if (cache->base == 0)
2455 return;
2456
2457 *this_id = frame_id_build (cache->saved_sp, cache->pc);
617daa0e 2458}
1c0159e0 2459
617daa0e 2460static const struct frame_unwind sh_frame_unwind = {
1c0159e0
CV		 2461 NORMAL_FRAME,
2462 sh_frame_this_id,
2463 sh_frame_prev_register
2464};
2465
2466static const struct frame_unwind *
2467sh_frame_sniffer (struct frame_info *next_frame)
2468{
2469 return &sh_frame_unwind;
2470}
2471
2472static CORE_ADDR
2473sh_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
2474{
2475 return frame_unwind_register_unsigned (next_frame, SP_REGNUM);
2476}
2477
2478static CORE_ADDR
2479sh_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2480{
2481 return frame_unwind_register_unsigned (next_frame, PC_REGNUM);
2482}
2483
2484static struct frame_id
2485sh_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
2486{
2487 return frame_id_build (sh_unwind_sp (gdbarch, next_frame),
2488 frame_pc_unwind (next_frame));
2489}
2490
2491static CORE_ADDR
2492sh_frame_base_address (struct frame_info *next_frame, void **this_cache)
617daa0e 2493{
1c0159e0 2494 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
617daa0e 2495
1c0159e0
CV		 2496 return cache->base;
2497}
617daa0e
CV		 2498
2499static const struct frame_base sh_frame_base = {
1c0159e0
CV		 2500 &sh_frame_unwind,
2501 sh_frame_base_address,
2502 sh_frame_base_address,
2503 sh_frame_base_address
617daa0e 2504};
1c0159e0
CV		 2505
2506/* The epilogue is defined here as the area at the end of a function,
2507 either on the `ret' instruction itself or after an instruction which
2508 destroys the function's stack frame. */
2509static int
2510sh_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
2511{
2512 CORE_ADDR func_addr = 0, func_end = 0;
2513
2514 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
2515 {
2516 ULONGEST inst;
2517 /* The sh epilogue is max. 14 bytes long. Give another 14 bytes
2518 for a nop and some fixed data (e.g. big offsets) which are
617daa0e
CV		 2519 unfortunately also treated as part of the function (which
2520 means, they are below func_end. */
1c0159e0
CV		 2521 CORE_ADDR addr = func_end - 28;
2522 if (addr < func_addr + 4)
617daa0e 2523 addr = func_addr + 4;
1c0159e0
CV		 2524 if (pc < addr)
2525 return 0;
2526
2527 /* First search forward until hitting an rts. */
2528 while (addr < func_end
617daa0e 2529 && !IS_RTS (read_memory_unsigned_integer (addr, 2)))
1c0159e0
CV		 2530 addr += 2;
2531 if (addr >= func_end)
617daa0e 2532 return 0;
1c0159e0
CV		 2533
2534 /* At this point we should find a mov.l @r15+,r14 instruction,
2535 either before or after the rts. If not, then the function has
617daa0e 2536 probably no "normal" epilogue and we bail out here. */
1c0159e0
CV		 2537 inst = read_memory_unsigned_integer (addr - 2, 2);
2538 if (IS_RESTORE_FP (read_memory_unsigned_integer (addr - 2, 2)))
617daa0e 2539 addr -= 2;
1c0159e0
CV		 2540 else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr + 2, 2)))
2541 return 0;
2542
1c0159e0 2543 inst = read_memory_unsigned_integer (addr - 2, 2);
03131d99
CV		 2544
2545 /* Step over possible lds.l @r15+,macl. */
2546 if (IS_MACL_LDS (inst))
2547 {
2548 addr -= 2;
2549 inst = read_memory_unsigned_integer (addr - 2, 2);
2550 }
2551
2552 /* Step over possible lds.l @r15+,pr. */
1c0159e0 2553 if (IS_LDS (inst))
617daa0e 2554 {
1c0159e0
CV		 2555 addr -= 2;
2556 inst = read_memory_unsigned_integer (addr - 2, 2);
2557 }
2558
2559 /* Step over possible mov r14,r15. */
2560 if (IS_MOV_FP_SP (inst))
617daa0e 2561 {
1c0159e0
CV		 2562 addr -= 2;
2563 inst = read_memory_unsigned_integer (addr - 2, 2);
2564 }
2565
2566 /* Now check for FP adjustments, using add #imm,r14 or add rX, r14
2567 instructions. */
2568 while (addr > func_addr + 4
617daa0e 2569 && (IS_ADD_REG_TO_FP (inst) || IS_ADD_IMM_FP (inst)))
1c0159e0
CV		 2570 {
2571 addr -= 2;
2572 inst = read_memory_unsigned_integer (addr - 2, 2);
2573 }
2574
03131d99
CV		 2575 /* On SH2a check if the previous instruction was perhaps a MOVI20.
2576 That's allowed for the epilogue. */
2577 if ((gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a
2578 || gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a_nofpu)
2579 && addr > func_addr + 6
2580 && IS_MOVI20 (read_memory_unsigned_integer (addr - 4, 2)))
2581 addr -= 4;
2582
1c0159e0
CV		 2583 if (pc >= addr)
2584 return 1;
2585 }
2586 return 0;
2587}
ccf00f21 2588\f
cc17453a
EZ		 2589
2590static struct gdbarch *
fba45db2 2591sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
cc17453a 2592{
cc17453a 2593 struct gdbarch *gdbarch;
d658f924 2594
55ff77ac
CV		 2595 sh_show_regs = sh_generic_show_regs;
2596 switch (info.bfd_arch_info->mach)
2597 {
617daa0e
CV		 2598 case bfd_mach_sh2e:
2599 sh_show_regs = sh2e_show_regs;
2600 break;
da962468
CV		 2601 case bfd_mach_sh2a:
2602 sh_show_regs = sh2a_show_regs;
2603 break;
2604 case bfd_mach_sh2a_nofpu:
2605 sh_show_regs = sh2a_nofpu_show_regs;
2606 break;
617daa0e
CV		 2607 case bfd_mach_sh_dsp:
2608 sh_show_regs = sh_dsp_show_regs;
2609 break;
55ff77ac 2610
617daa0e
CV		 2611 case bfd_mach_sh3:
2612 sh_show_regs = sh3_show_regs;
2613 break;
55ff77ac 2614
617daa0e
CV		 2615 case bfd_mach_sh3e:
2616 sh_show_regs = sh3e_show_regs;
2617 break;
55ff77ac 2618
617daa0e 2619 case bfd_mach_sh3_dsp:
474e5826 2620 case bfd_mach_sh4al_dsp:
617daa0e
CV		 2621 sh_show_regs = sh3_dsp_show_regs;
2622 break;
55ff77ac 2623
617daa0e 2624 case bfd_mach_sh4:
474e5826 2625 case bfd_mach_sh4a:
617daa0e
CV		 2626 sh_show_regs = sh4_show_regs;
2627 break;
55ff77ac 2628
474e5826
CV		 2629 case bfd_mach_sh4_nofpu:
2630 case bfd_mach_sh4a_nofpu:
2631 sh_show_regs = sh4_nofpu_show_regs;
2632 break;
2633
617daa0e
CV		 2634 case bfd_mach_sh5:
2635 sh_show_regs = sh64_show_regs;
2636 /* SH5 is handled entirely in sh64-tdep.c */
2637 return sh64_gdbarch_init (info, arches);
55ff77ac
CV		 2638 }
2639
4be87837
DJ		 2640 /* If there is already a candidate, use it. */
2641 arches = gdbarch_list_lookup_by_info (arches, &info);
2642 if (arches != NULL)
2643 return arches->gdbarch;
cc17453a
EZ		 2644
2645 /* None found, create a new architecture from the information
2646 provided. */
f2ea0907 2647 gdbarch = gdbarch_alloc (&info, NULL);
cc17453a 2648
48db5a3c
CV		 2649 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2650 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
ec920329 2651 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
48db5a3c
CV		 2652 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2653 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2654 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2655 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
a38d2a54 2656 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
48db5a3c 2657
f2ea0907 2658 set_gdbarch_num_regs (gdbarch, SH_NUM_REGS);
a38d2a54 2659 set_gdbarch_sp_regnum (gdbarch, 15);
a38d2a54 2660 set_gdbarch_pc_regnum (gdbarch, 16);
48db5a3c
CV		 2661 set_gdbarch_fp0_regnum (gdbarch, -1);
2662 set_gdbarch_num_pseudo_regs (gdbarch, 0);
2663
1c0159e0 2664 set_gdbarch_register_type (gdbarch, sh_default_register_type);
dda63807 2665 set_gdbarch_register_reggroup_p (gdbarch, sh_register_reggroup_p);
1c0159e0 2666
eaf90c5d 2667 set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc);
48db5a3c 2668
2bf0cb65 2669 set_gdbarch_print_insn (gdbarch, gdb_print_insn_sh);
2f14585c 2670 set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);
48db5a3c 2671
c0409442
CV		 2672 set_gdbarch_return_value (gdbarch, sh_return_value_nofpu);
2673 set_gdbarch_deprecated_extract_struct_value_address (gdbarch,
2674 sh_extract_struct_value_address);
1c0159e0 2675
48db5a3c
CV		 2676 set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
2677 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
48db5a3c 2678
1c0159e0
CV		 2679 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu);
2680
48db5a3c
CV		 2681 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2682
19f59343 2683 set_gdbarch_frame_align (gdbarch, sh_frame_align);
1c0159e0
CV		 2684 set_gdbarch_unwind_sp (gdbarch, sh_unwind_sp);
2685 set_gdbarch_unwind_pc (gdbarch, sh_unwind_pc);
2686 set_gdbarch_unwind_dummy_id (gdbarch, sh_unwind_dummy_id);
2687 frame_base_set_default (gdbarch, &sh_frame_base);
2688
617daa0e 2689 set_gdbarch_in_function_epilogue_p (gdbarch, sh_in_function_epilogue_p);
cc17453a 2690
357d3800
AS		 2691 dwarf2_frame_set_init_reg (gdbarch, sh_dwarf2_frame_init_reg);
2692
cc17453a 2693 switch (info.bfd_arch_info->mach)
8db62801 2694 {
cc17453a 2695 case bfd_mach_sh:
48db5a3c 2696 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
cc17453a 2697 break;
1c0159e0 2698
cc17453a 2699 case bfd_mach_sh2:
48db5a3c 2700 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
617daa0e 2701 break;
1c0159e0 2702
2d188dd3 2703 case bfd_mach_sh2e:
48db5a3c
CV		 2704 /* doubles on sh2e and sh3e are actually 4 byte. */
2705 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2706
2707 set_gdbarch_register_name (gdbarch, sh_sh2e_register_name);
48db5a3c 2708 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
2d188dd3 2709 set_gdbarch_fp0_regnum (gdbarch, 25);
c0409442 2710 set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
6df2bf50 2711 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2d188dd3 2712 break;
1c0159e0 2713
da962468
CV		 2714 case bfd_mach_sh2a:
2715 set_gdbarch_register_name (gdbarch, sh_sh2a_register_name);
2716 set_gdbarch_register_type (gdbarch, sh_sh2a_register_type);
2717 set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno);
2718
2719 set_gdbarch_fp0_regnum (gdbarch, 25);
2720 set_gdbarch_num_pseudo_regs (gdbarch, 9);
2721 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
2722 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
c0409442 2723 set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
da962468
CV		 2724 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2725 break;
2726
2727 case bfd_mach_sh2a_nofpu:
2728 set_gdbarch_register_name (gdbarch, sh_sh2a_nofpu_register_name);
2729 set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno);
2730
2731 set_gdbarch_num_pseudo_regs (gdbarch, 1);
2732 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
2733 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
2734 break;
2735
cc17453a 2736 case bfd_mach_sh_dsp:
48db5a3c 2737 set_gdbarch_register_name (gdbarch, sh_sh_dsp_register_name);
2f14585c 2738 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
cc17453a 2739 break;
1c0159e0 2740
cc17453a 2741 case bfd_mach_sh3:
4e6cbc38
AS		 2742 case bfd_mach_sh3_nommu:
2743 case bfd_mach_sh2a_nofpu_or_sh3_nommu:
48db5a3c 2744 set_gdbarch_register_name (gdbarch, sh_sh3_register_name);
cc17453a 2745 break;
1c0159e0 2746
cc17453a 2747 case bfd_mach_sh3e:
4e6cbc38 2748 case bfd_mach_sh2a_or_sh3e:
48db5a3c
CV		 2749 /* doubles on sh2e and sh3e are actually 4 byte. */
2750 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2751
2752 set_gdbarch_register_name (gdbarch, sh_sh3e_register_name);
48db5a3c 2753 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
cc17453a 2754 set_gdbarch_fp0_regnum (gdbarch, 25);
c0409442 2755 set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
6df2bf50 2756 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
cc17453a 2757 break;
1c0159e0 2758
cc17453a 2759 case bfd_mach_sh3_dsp:
48db5a3c 2760 set_gdbarch_register_name (gdbarch, sh_sh3_dsp_register_name);
48db5a3c 2761 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
cc17453a 2762 break;
1c0159e0 2763
cc17453a 2764 case bfd_mach_sh4:
474e5826 2765 case bfd_mach_sh4a:
48db5a3c 2766 set_gdbarch_register_name (gdbarch, sh_sh4_register_name);
48db5a3c 2767 set_gdbarch_register_type (gdbarch, sh_sh4_register_type);
cc17453a 2768 set_gdbarch_fp0_regnum (gdbarch, 25);
da962468 2769 set_gdbarch_num_pseudo_regs (gdbarch, 13);
d8124050
AC		 2770 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
2771 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
c0409442 2772 set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
6df2bf50 2773 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
cc17453a 2774 break;
1c0159e0 2775
474e5826
CV		 2776 case bfd_mach_sh4_nofpu:
2777 case bfd_mach_sh4a_nofpu:
4e6cbc38
AS		 2778 case bfd_mach_sh4_nommu_nofpu:
2779 case bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu:
2780 case bfd_mach_sh2a_or_sh4:
474e5826
CV		 2781 set_gdbarch_register_name (gdbarch, sh_sh4_nofpu_register_name);
2782 break;
2783
2784 case bfd_mach_sh4al_dsp:
2785 set_gdbarch_register_name (gdbarch, sh_sh4al_dsp_register_name);
2786 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2787 break;
2788
cc17453a 2789 default:
b58cbbf2 2790 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
cc17453a 2791 break;
8db62801 2792 }
cc17453a 2793
4be87837
DJ		 2794 /* Hook in ABI-specific overrides, if they have been registered. */
2795 gdbarch_init_osabi (info, gdbarch);
d658f924 2796
1c0159e0
CV		 2797 frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer);
2798 frame_unwind_append_sniffer (gdbarch, sh_frame_sniffer);
2799
cc17453a 2800 return gdbarch;
8db62801
EZ		 2801}
2802
617daa0e 2803extern initialize_file_ftype _initialize_sh_tdep; /* -Wmissing-prototypes */
a78f21af 2804
c906108c 2805void
fba45db2 2806_initialize_sh_tdep (void)
c906108c
SS		 2807{
2808 struct cmd_list_element *c;
617daa0e 2809
f2ea0907 2810 gdbarch_register (bfd_arch_sh, sh_gdbarch_init, NULL);
c906108c 2811
1bedd215 2812 add_com ("regs", class_vars, sh_show_regs_command, _("Print all registers"));
c906108c 2813}
GDB Binutils - Deliverables
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