Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for Hitachi Super-H, for GDB. |
1e698235 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 |
3116c80a | 3 | Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b JM |
17 | You should have received a copy of the GNU General Public License |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
21 | |
22 | /* | |
c5aa993b JM |
23 | Contributed by Steve Chamberlain |
24 | sac@cygnus.com | |
c906108c SS |
25 | */ |
26 | ||
27 | #include "defs.h" | |
28 | #include "frame.h" | |
c906108c SS |
29 | #include "symtab.h" |
30 | #include "symfile.h" | |
31 | #include "gdbtypes.h" | |
32 | #include "gdbcmd.h" | |
33 | #include "gdbcore.h" | |
34 | #include "value.h" | |
35 | #include "dis-asm.h" | |
73c1f219 | 36 | #include "inferior.h" |
c906108c | 37 | #include "gdb_string.h" |
b4a20239 | 38 | #include "arch-utils.h" |
fb409745 | 39 | #include "floatformat.h" |
4e052eda | 40 | #include "regcache.h" |
d16aafd8 | 41 | #include "doublest.h" |
4be87837 | 42 | #include "osabi.h" |
c906108c | 43 | |
ab3b8126 JT |
44 | #include "sh-tdep.h" |
45 | ||
d658f924 | 46 | #include "elf-bfd.h" |
1a8629c7 MS |
47 | #include "solib-svr4.h" |
48 | ||
283150cd EZ |
49 | /* sh64 flags */ |
50 | #include "elf/sh.h" | |
51 | /* registers numbers shared with the simulator */ | |
1c922164 | 52 | #include "gdb/sim-sh.h" |
283150cd | 53 | |
53116e27 | 54 | void (*sh_show_regs) (void); |
3bbfbb92 | 55 | CORE_ADDR (*skip_prologue_hard_way) (CORE_ADDR); |
cc17453a | 56 | |
88e04cc1 EZ |
57 | #define SH_DEFAULT_NUM_REGS 59 |
58 | ||
cc17453a EZ |
59 | /* Define other aspects of the stack frame. |
60 | we keep a copy of the worked out return pc lying around, since it | |
61 | is a useful bit of info */ | |
62 | ||
63 | struct frame_extra_info | |
64 | { | |
65 | CORE_ADDR return_pc; | |
66 | int leaf_function; | |
67 | int f_offset; | |
63978407 | 68 | }; |
c906108c | 69 | |
fa88f677 | 70 | static const char * |
cc17453a | 71 | sh_generic_register_name (int reg_nr) |
c5aa993b | 72 | { |
cc17453a | 73 | static char *register_names[] = |
c5aa993b | 74 | { |
cc17453a EZ |
75 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
76 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
77 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
78 | "fpul", "fpscr", | |
79 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", | |
80 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
81 | "ssr", "spc", | |
82 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", | |
83 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", | |
84 | }; | |
85 | if (reg_nr < 0) | |
86 | return NULL; | |
87 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
88 | return NULL; | |
89 | return register_names[reg_nr]; | |
90 | } | |
91 | ||
fa88f677 | 92 | static const char * |
cc17453a EZ |
93 | sh_sh_register_name (int reg_nr) |
94 | { | |
95 | static char *register_names[] = | |
63978407 | 96 | { |
cc17453a EZ |
97 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
98 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
99 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
100 | "", "", | |
101 | "", "", "", "", "", "", "", "", | |
102 | "", "", "", "", "", "", "", "", | |
103 | "", "", | |
104 | "", "", "", "", "", "", "", "", | |
105 | "", "", "", "", "", "", "", "", | |
106 | }; | |
107 | if (reg_nr < 0) | |
108 | return NULL; | |
109 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
110 | return NULL; | |
111 | return register_names[reg_nr]; | |
112 | } | |
113 | ||
fa88f677 | 114 | static const char * |
cc17453a EZ |
115 | sh_sh3_register_name (int reg_nr) |
116 | { | |
117 | static char *register_names[] = | |
c5aa993b | 118 | { |
cc17453a EZ |
119 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
120 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
121 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
122 | "", "", | |
123 | "", "", "", "", "", "", "", "", | |
124 | "", "", "", "", "", "", "", "", | |
125 | "ssr", "spc", | |
126 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", | |
127 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1" | |
128 | }; | |
129 | if (reg_nr < 0) | |
130 | return NULL; | |
131 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
132 | return NULL; | |
133 | return register_names[reg_nr]; | |
134 | } | |
135 | ||
fa88f677 | 136 | static const char * |
cc17453a EZ |
137 | sh_sh3e_register_name (int reg_nr) |
138 | { | |
139 | static char *register_names[] = | |
63978407 | 140 | { |
cc17453a EZ |
141 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
142 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
143 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
144 | "fpul", "fpscr", | |
145 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", | |
146 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
147 | "ssr", "spc", | |
148 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", | |
149 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", | |
150 | }; | |
151 | if (reg_nr < 0) | |
152 | return NULL; | |
153 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
154 | return NULL; | |
155 | return register_names[reg_nr]; | |
156 | } | |
157 | ||
2d188dd3 NC |
158 | static const char * |
159 | sh_sh2e_register_name (int reg_nr) | |
160 | { | |
161 | static char *register_names[] = | |
162 | { | |
163 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
164 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
165 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
166 | "fpul", "fpscr", | |
167 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", | |
168 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
169 | "", "", | |
170 | "", "", "", "", "", "", "", "", | |
171 | "", "", "", "", "", "", "", "", | |
172 | }; | |
173 | if (reg_nr < 0) | |
174 | return NULL; | |
175 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
176 | return NULL; | |
177 | return register_names[reg_nr]; | |
178 | } | |
179 | ||
fa88f677 | 180 | static const char * |
cc17453a EZ |
181 | sh_sh_dsp_register_name (int reg_nr) |
182 | { | |
183 | static char *register_names[] = | |
c5aa993b | 184 | { |
cc17453a EZ |
185 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
186 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
187 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
188 | "", "dsr", | |
189 | "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1", | |
190 | "y0", "y1", "", "", "", "", "", "mod", | |
191 | "", "", | |
192 | "rs", "re", "", "", "", "", "", "", | |
193 | "", "", "", "", "", "", "", "", | |
194 | }; | |
195 | if (reg_nr < 0) | |
196 | return NULL; | |
197 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
198 | return NULL; | |
199 | return register_names[reg_nr]; | |
200 | } | |
201 | ||
fa88f677 | 202 | static const char * |
cc17453a EZ |
203 | sh_sh3_dsp_register_name (int reg_nr) |
204 | { | |
205 | static char *register_names[] = | |
c5aa993b | 206 | { |
cc17453a EZ |
207 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
208 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
209 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
210 | "", "dsr", | |
211 | "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1", | |
212 | "y0", "y1", "", "", "", "", "", "mod", | |
213 | "ssr", "spc", | |
214 | "rs", "re", "", "", "", "", "", "", | |
215 | "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b" | |
216 | "", "", "", "", "", "", "", "", | |
217 | }; | |
218 | if (reg_nr < 0) | |
219 | return NULL; | |
220 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
221 | return NULL; | |
222 | return register_names[reg_nr]; | |
223 | } | |
224 | ||
fa88f677 | 225 | static const char * |
53116e27 EZ |
226 | sh_sh4_register_name (int reg_nr) |
227 | { | |
228 | static char *register_names[] = | |
229 | { | |
a38d2a54 | 230 | /* general registers 0-15 */ |
53116e27 EZ |
231 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
232 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
a38d2a54 | 233 | /* 16 - 22 */ |
53116e27 | 234 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", |
a38d2a54 | 235 | /* 23, 24 */ |
53116e27 | 236 | "fpul", "fpscr", |
a38d2a54 | 237 | /* floating point registers 25 - 40 */ |
53116e27 EZ |
238 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", |
239 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
a38d2a54 | 240 | /* 41, 42 */ |
53116e27 | 241 | "ssr", "spc", |
a38d2a54 | 242 | /* bank 0 43 - 50 */ |
53116e27 | 243 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", |
a38d2a54 | 244 | /* bank 1 51 - 58 */ |
53116e27 | 245 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", |
a38d2a54 | 246 | /* double precision (pseudo) 59 - 66 */ |
fe9f384f | 247 | "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", |
a38d2a54 | 248 | /* vectors (pseudo) 67 - 70 */ |
fe9f384f | 249 | "fv0", "fv4", "fv8", "fv12", |
a38d2a54 EZ |
250 | /* FIXME: missing XF 71 - 86 */ |
251 | /* FIXME: missing XD 87 - 94 */ | |
53116e27 EZ |
252 | }; |
253 | if (reg_nr < 0) | |
254 | return NULL; | |
255 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
256 | return NULL; | |
257 | return register_names[reg_nr]; | |
258 | } | |
259 | ||
fa88f677 | 260 | static const char * |
283150cd EZ |
261 | sh_sh64_register_name (int reg_nr) |
262 | { | |
263 | static char *register_names[] = | |
264 | { | |
265 | /* SH MEDIA MODE (ISA 32) */ | |
266 | /* general registers (64-bit) 0-63 */ | |
267 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
268 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
269 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
270 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", | |
271 | "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", | |
272 | "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", | |
273 | "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", | |
274 | "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", | |
275 | ||
276 | /* pc (64-bit) 64 */ | |
277 | "pc", | |
278 | ||
279 | /* status reg., saved status reg., saved pc reg. (64-bit) 65-67 */ | |
280 | "sr", "ssr", "spc", | |
281 | ||
282 | /* target registers (64-bit) 68-75*/ | |
283 | "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", | |
284 | ||
285 | /* floating point state control register (32-bit) 76 */ | |
286 | "fpscr", | |
287 | ||
288 | /* single precision floating point registers (32-bit) 77-140*/ | |
289 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", | |
290 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
291 | "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", | |
292 | "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", | |
293 | "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", | |
294 | "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", | |
295 | "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", | |
296 | "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", | |
297 | ||
298 | /* double precision registers (pseudo) 141-172 */ | |
299 | "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", | |
300 | "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", | |
301 | "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", | |
302 | "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62", | |
303 | ||
304 | /* floating point pairs (pseudo) 173-204*/ | |
305 | "fp0", "fp2", "fp4", "fp6", "fp8", "fp10", "fp12", "fp14", | |
306 | "fp16", "fp18", "fp20", "fp22", "fp24", "fp26", "fp28", "fp30", | |
307 | "fp32", "fp34", "fp36", "fp38", "fp40", "fp42", "fp44", "fp46", | |
308 | "fp48", "fp50", "fp52", "fp54", "fp56", "fp58", "fp60", "fp62", | |
309 | ||
310 | /* floating point vectors (4 floating point regs) (pseudo) 205-220*/ | |
311 | "fv0", "fv4", "fv8", "fv12", "fv16", "fv20", "fv24", "fv28", | |
312 | "fv32", "fv36", "fv40", "fv44", "fv48", "fv52", "fv56", "fv60", | |
313 | ||
314 | /* SH COMPACT MODE (ISA 16) (all pseudo) 221-272*/ | |
315 | "r0_c", "r1_c", "r2_c", "r3_c", "r4_c", "r5_c", "r6_c", "r7_c", | |
316 | "r8_c", "r9_c", "r10_c", "r11_c", "r12_c", "r13_c", "r14_c", "r15_c", | |
317 | "pc_c", | |
318 | "gbr_c", "mach_c", "macl_c", "pr_c", "t_c", | |
319 | "fpscr_c", "fpul_c", | |
320 | "fr0_c", "fr1_c", "fr2_c", "fr3_c", "fr4_c", "fr5_c", "fr6_c", "fr7_c", | |
321 | "fr8_c", "fr9_c", "fr10_c", "fr11_c", "fr12_c", "fr13_c", "fr14_c", "fr15_c", | |
322 | "dr0_c", "dr2_c", "dr4_c", "dr6_c", "dr8_c", "dr10_c", "dr12_c", "dr14_c", | |
323 | "fv0_c", "fv4_c", "fv8_c", "fv12_c", | |
324 | /* FIXME!!!! XF0 XF15, XD0 XD14 ?????*/ | |
325 | }; | |
326 | ||
327 | if (reg_nr < 0) | |
328 | return NULL; | |
329 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
330 | return NULL; | |
331 | return register_names[reg_nr]; | |
332 | } | |
333 | ||
334 | #define NUM_PSEUDO_REGS_SH_MEDIA 80 | |
335 | #define NUM_PSEUDO_REGS_SH_COMPACT 51 | |
336 | ||
3117ed25 | 337 | static const unsigned char * |
fba45db2 | 338 | sh_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
cc17453a EZ |
339 | { |
340 | /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */ | |
341 | static unsigned char breakpoint[] = {0xc3, 0xc3}; | |
342 | ||
343 | *lenptr = sizeof (breakpoint); | |
344 | return breakpoint; | |
345 | } | |
c906108c | 346 | |
48db5a3c CV |
347 | static CORE_ADDR |
348 | sh_push_dummy_code (struct gdbarch *gdbarch, | |
349 | CORE_ADDR sp, CORE_ADDR funaddr, int using_gcc, | |
350 | struct value **args, int nargs, | |
351 | struct type *value_type, | |
352 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr) | |
353 | { | |
354 | /* Allocate space sufficient for a breakpoint. */ | |
355 | sp = (sp - 2) & ~1; | |
356 | /* Store the address of that breakpoint */ | |
357 | *bp_addr = sp; | |
358 | /* sh always starts the call at the callee's entry point. */ | |
359 | *real_pc = funaddr; | |
360 | return sp; | |
361 | } | |
362 | ||
283150cd EZ |
363 | /* Macros and functions for setting and testing a bit in a minimal |
364 | symbol that marks it as 32-bit function. The MSB of the minimal | |
365 | symbol's "info" field is used for this purpose. This field is | |
366 | already being used to store the symbol size, so the assumption is | |
367 | that the symbol size cannot exceed 2^31. | |
368 | ||
369 | ELF_MAKE_MSYMBOL_SPECIAL | |
370 | tests whether an ELF symbol is "special", i.e. refers | |
371 | to a 32-bit function, and sets a "special" bit in a | |
372 | minimal symbol to mark it as a 32-bit function | |
373 | MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol | |
374 | MSYMBOL_SIZE returns the size of the minimal symbol, i.e. | |
375 | the "info" field with the "special" bit masked out */ | |
376 | ||
377 | #define MSYMBOL_IS_SPECIAL(msym) \ | |
378 | (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0) | |
379 | ||
a78f21af | 380 | static void |
283150cd EZ |
381 | sh64_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym) |
382 | { | |
383 | if (msym == NULL) | |
384 | return; | |
385 | ||
386 | if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_SH5_ISA32) | |
387 | { | |
388 | MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) | 0x80000000); | |
389 | SYMBOL_VALUE_ADDRESS (msym) |= 1; | |
390 | } | |
391 | } | |
392 | ||
393 | /* ISA32 (shmedia) function addresses are odd (bit 0 is set). Here | |
394 | are some macros to test, set, or clear bit 0 of addresses. */ | |
395 | #define IS_ISA32_ADDR(addr) ((addr) & 1) | |
396 | #define MAKE_ISA32_ADDR(addr) ((addr) | 1) | |
397 | #define UNMAKE_ISA32_ADDR(addr) ((addr) & ~1) | |
398 | ||
399 | static int | |
400 | pc_is_isa32 (bfd_vma memaddr) | |
401 | { | |
402 | struct minimal_symbol *sym; | |
403 | ||
404 | /* If bit 0 of the address is set, assume this is a | |
405 | ISA32 (shmedia) address. */ | |
406 | if (IS_ISA32_ADDR (memaddr)) | |
407 | return 1; | |
408 | ||
409 | /* A flag indicating that this is a ISA32 function is stored by elfread.c in | |
410 | the high bit of the info field. Use this to decide if the function is | |
411 | ISA16 or ISA32. */ | |
412 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
413 | if (sym) | |
414 | return MSYMBOL_IS_SPECIAL (sym); | |
415 | else | |
416 | return 0; | |
417 | } | |
418 | ||
419 | static const unsigned char * | |
420 | sh_sh64_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) | |
421 | { | |
422 | /* The BRK instruction for shmedia is | |
423 | 01101111 11110101 11111111 11110000 | |
424 | which translates in big endian mode to 0x6f, 0xf5, 0xff, 0xf0 | |
425 | and in little endian mode to 0xf0, 0xff, 0xf5, 0x6f */ | |
426 | ||
427 | /* The BRK instruction for shcompact is | |
428 | 00000000 00111011 | |
429 | which translates in big endian mode to 0x0, 0x3b | |
430 | and in little endian mode to 0x3b, 0x0*/ | |
431 | ||
432 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
433 | { | |
434 | if (pc_is_isa32 (*pcptr)) | |
435 | { | |
436 | static unsigned char big_breakpoint_media[] = {0x6f, 0xf5, 0xff, 0xf0}; | |
437 | *pcptr = UNMAKE_ISA32_ADDR (*pcptr); | |
438 | *lenptr = sizeof (big_breakpoint_media); | |
439 | return big_breakpoint_media; | |
440 | } | |
441 | else | |
442 | { | |
443 | static unsigned char big_breakpoint_compact[] = {0x0, 0x3b}; | |
444 | *lenptr = sizeof (big_breakpoint_compact); | |
445 | return big_breakpoint_compact; | |
446 | } | |
447 | } | |
448 | else | |
449 | { | |
450 | if (pc_is_isa32 (*pcptr)) | |
451 | { | |
452 | static unsigned char little_breakpoint_media[] = {0xf0, 0xff, 0xf5, 0x6f}; | |
453 | *pcptr = UNMAKE_ISA32_ADDR (*pcptr); | |
454 | *lenptr = sizeof (little_breakpoint_media); | |
455 | return little_breakpoint_media; | |
456 | } | |
457 | else | |
458 | { | |
459 | static unsigned char little_breakpoint_compact[] = {0x3b, 0x0}; | |
460 | *lenptr = sizeof (little_breakpoint_compact); | |
461 | return little_breakpoint_compact; | |
462 | } | |
463 | } | |
464 | } | |
465 | ||
c906108c | 466 | /* Prologue looks like |
c5aa993b JM |
467 | [mov.l <regs>,@-r15]... |
468 | [sts.l pr,@-r15] | |
469 | [mov.l r14,@-r15] | |
470 | [mov r15,r14] | |
8db62801 EZ |
471 | |
472 | Actually it can be more complicated than this. For instance, with | |
473 | newer gcc's: | |
474 | ||
475 | mov.l r14,@-r15 | |
476 | add #-12,r15 | |
477 | mov r15,r14 | |
478 | mov r4,r1 | |
479 | mov r5,r2 | |
480 | mov.l r6,@(4,r14) | |
481 | mov.l r7,@(8,r14) | |
482 | mov.b r1,@r14 | |
483 | mov r14,r1 | |
484 | mov r14,r1 | |
485 | add #2,r1 | |
486 | mov.w r2,@r1 | |
487 | ||
c5aa993b | 488 | */ |
c906108c | 489 | |
283150cd EZ |
490 | /* PTABS/L Rn, TRa 0110101111110001nnnnnnl00aaa0000 |
491 | with l=1 and n = 18 0110101111110001010010100aaa0000 */ | |
492 | #define IS_PTABSL_R18(x) (((x) & 0xffffff8f) == 0x6bf14a00) | |
493 | ||
494 | /* STS.L PR,@-r0 0100000000100010 | |
495 | r0-4-->r0, PR-->(r0) */ | |
496 | #define IS_STS_R0(x) ((x) == 0x4022) | |
497 | ||
498 | /* STS PR, Rm 0000mmmm00101010 | |
499 | PR-->Rm */ | |
500 | #define IS_STS_PR(x) (((x) & 0xf0ff) == 0x2a) | |
501 | ||
502 | /* MOV.L Rm,@(disp,r15) 00011111mmmmdddd | |
503 | Rm-->(dispx4+r15) */ | |
504 | #define IS_MOV_TO_R15(x) (((x) & 0xff00) == 0x1f00) | |
505 | ||
506 | /* MOV.L R14,@(disp,r15) 000111111110dddd | |
507 | R14-->(dispx4+r15) */ | |
508 | #define IS_MOV_R14(x) (((x) & 0xfff0) == 0x1fe0) | |
509 | ||
510 | /* ST.Q R14, disp, R18 101011001110dddddddddd0100100000 | |
511 | R18-->(dispx8+R14) */ | |
512 | #define IS_STQ_R18_R14(x) (((x) & 0xfff003ff) == 0xace00120) | |
513 | ||
514 | /* ST.Q R15, disp, R18 101011001111dddddddddd0100100000 | |
515 | R18-->(dispx8+R15) */ | |
516 | #define IS_STQ_R18_R15(x) (((x) & 0xfff003ff) == 0xacf00120) | |
517 | ||
518 | /* ST.L R15, disp, R18 101010001111dddddddddd0100100000 | |
519 | R18-->(dispx4+R15) */ | |
520 | #define IS_STL_R18_R15(x) (((x) & 0xfff003ff) == 0xa8f00120) | |
521 | ||
522 | /* ST.Q R15, disp, R14 1010 1100 1111 dddd dddd dd00 1110 0000 | |
523 | R14-->(dispx8+R15) */ | |
524 | #define IS_STQ_R14_R15(x) (((x) & 0xfff003ff) == 0xacf000e0) | |
525 | ||
526 | /* ST.L R15, disp, R14 1010 1000 1111 dddd dddd dd00 1110 0000 | |
527 | R14-->(dispx4+R15) */ | |
528 | #define IS_STL_R14_R15(x) (((x) & 0xfff003ff) == 0xa8f000e0) | |
529 | ||
530 | /* ADDI.L R15,imm,R15 1101 0100 1111 ssss ssss ss00 1111 0000 | |
531 | R15 + imm --> R15 */ | |
532 | #define IS_ADDIL_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd4f000f0) | |
533 | ||
534 | /* ADDI R15,imm,R15 1101 0000 1111 ssss ssss ss00 1111 0000 | |
535 | R15 + imm --> R15 */ | |
536 | #define IS_ADDI_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd0f000f0) | |
537 | ||
538 | /* ADD.L R15,R63,R14 0000 0000 1111 1000 1111 1100 1110 0000 | |
539 | R15 + R63 --> R14 */ | |
540 | #define IS_ADDL_SP_FP_MEDIA(x) ((x) == 0x00f8fce0) | |
541 | ||
542 | /* ADD R15,R63,R14 0000 0000 1111 1001 1111 1100 1110 0000 | |
543 | R15 + R63 --> R14 */ | |
544 | #define IS_ADD_SP_FP_MEDIA(x) ((x) == 0x00f9fce0) | |
545 | ||
546 | #define IS_MOV_SP_FP_MEDIA(x) (IS_ADDL_SP_FP_MEDIA(x) || IS_ADD_SP_FP_MEDIA(x)) | |
547 | ||
548 | /* MOV #imm, R0 1110 0000 ssss ssss | |
549 | #imm-->R0 */ | |
550 | #define IS_MOV_R0(x) (((x) & 0xff00) == 0xe000) | |
551 | ||
552 | /* MOV.L @(disp,PC), R0 1101 0000 iiii iiii */ | |
553 | #define IS_MOVL_R0(x) (((x) & 0xff00) == 0xd000) | |
554 | ||
555 | /* ADD r15,r0 0011 0000 1111 1100 | |
556 | r15+r0-->r0 */ | |
557 | #define IS_ADD_SP_R0(x) ((x) == 0x30fc) | |
558 | ||
559 | /* MOV.L R14 @-R0 0010 0000 1110 0110 | |
560 | R14-->(R0-4), R0-4-->R0 */ | |
561 | #define IS_MOV_R14_R0(x) ((x) == 0x20e6) | |
562 | ||
563 | /* ADD Rm,R63,Rn Rm+R63-->Rn 0000 00mm mmmm 1001 1111 11nn nnnn 0000 | |
564 | where Rm is one of r2-r9 which are the argument registers. */ | |
565 | /* FIXME: Recognize the float and double register moves too! */ | |
566 | #define IS_MEDIA_IND_ARG_MOV(x) \ | |
567 | ((((x) & 0xfc0ffc0f) == 0x0009fc00) && (((x) & 0x03f00000) >= 0x00200000 && ((x) & 0x03f00000) <= 0x00900000)) | |
568 | ||
569 | /* ST.Q Rn,0,Rm Rm-->Rn+0 1010 11nn nnnn 0000 0000 00mm mmmm 0000 | |
570 | or ST.L Rn,0,Rm Rm-->Rn+0 1010 10nn nnnn 0000 0000 00mm mmmm 0000 | |
571 | where Rm is one of r2-r9 which are the argument registers. */ | |
572 | #define IS_MEDIA_ARG_MOV(x) \ | |
573 | (((((x) & 0xfc0ffc0f) == 0xac000000) || (((x) & 0xfc0ffc0f) == 0xa8000000)) \ | |
574 | && (((x) & 0x000003f0) >= 0x00000020 && ((x) & 0x000003f0) <= 0x00000090)) | |
575 | ||
576 | /* ST.B R14,0,Rn Rn-->(R14+0) 1010 0000 1110 0000 0000 00nn nnnn 0000*/ | |
577 | /* ST.W R14,0,Rn Rn-->(R14+0) 1010 0100 1110 0000 0000 00nn nnnn 0000*/ | |
578 | /* ST.L R14,0,Rn Rn-->(R14+0) 1010 1000 1110 0000 0000 00nn nnnn 0000*/ | |
579 | /* FST.S R14,0,FRn Rn-->(R14+0) 1011 0100 1110 0000 0000 00nn nnnn 0000*/ | |
580 | /* FST.D R14,0,DRn Rn-->(R14+0) 1011 1100 1110 0000 0000 00nn nnnn 0000*/ | |
581 | #define IS_MEDIA_MOV_TO_R14(x) \ | |
582 | ((((x) & 0xfffffc0f) == 0xa0e00000) \ | |
583 | || (((x) & 0xfffffc0f) == 0xa4e00000) \ | |
584 | || (((x) & 0xfffffc0f) == 0xa8e00000) \ | |
585 | || (((x) & 0xfffffc0f) == 0xb4e00000) \ | |
586 | || (((x) & 0xfffffc0f) == 0xbce00000)) | |
587 | ||
588 | /* MOV Rm, Rn Rm-->Rn 0110 nnnn mmmm 0011 | |
589 | where Rm is r2-r9 */ | |
590 | #define IS_COMPACT_IND_ARG_MOV(x) \ | |
591 | ((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0020) && (((x) & 0x00f0) <= 0x0090)) | |
592 | ||
593 | /* compact direct arg move! | |
594 | MOV.L Rn, @r14 0010 1110 mmmm 0010 */ | |
595 | #define IS_COMPACT_ARG_MOV(x) \ | |
596 | (((((x) & 0xff0f) == 0x2e02) && (((x) & 0x00f0) >= 0x0020) && ((x) & 0x00f0) <= 0x0090)) | |
597 | ||
598 | /* MOV.B Rm, @R14 0010 1110 mmmm 0000 | |
599 | MOV.W Rm, @R14 0010 1110 mmmm 0001 */ | |
600 | #define IS_COMPACT_MOV_TO_R14(x) \ | |
601 | ((((x) & 0xff0f) == 0x2e00) || (((x) & 0xff0f) == 0x2e01)) | |
602 | ||
603 | #define IS_JSR_R0(x) ((x) == 0x400b) | |
604 | #define IS_NOP(x) ((x) == 0x0009) | |
605 | ||
606 | ||
8db62801 EZ |
607 | /* STS.L PR,@-r15 0100111100100010 |
608 | r15-4-->r15, PR-->(r15) */ | |
c906108c | 609 | #define IS_STS(x) ((x) == 0x4f22) |
8db62801 EZ |
610 | |
611 | /* MOV.L Rm,@-r15 00101111mmmm0110 | |
612 | r15-4-->r15, Rm-->(R15) */ | |
c906108c | 613 | #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06) |
8db62801 | 614 | |
c906108c | 615 | #define GET_PUSHED_REG(x) (((x) >> 4) & 0xf) |
8db62801 EZ |
616 | |
617 | /* MOV r15,r14 0110111011110011 | |
618 | r15-->r14 */ | |
c906108c | 619 | #define IS_MOV_SP_FP(x) ((x) == 0x6ef3) |
8db62801 EZ |
620 | |
621 | /* ADD #imm,r15 01111111iiiiiiii | |
622 | r15+imm-->r15 */ | |
c906108c | 623 | #define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00) |
8db62801 | 624 | |
c906108c SS |
625 | #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00) |
626 | #define IS_SHLL_R3(x) ((x) == 0x4300) | |
8db62801 EZ |
627 | |
628 | /* ADD r3,r15 0011111100111100 | |
629 | r15+r3-->r15 */ | |
c906108c | 630 | #define IS_ADD_R3SP(x) ((x) == 0x3f3c) |
8db62801 EZ |
631 | |
632 | /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011 | |
8db62801 | 633 | FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011 |
8db62801 | 634 | FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */ |
c906108c | 635 | #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) |
c906108c | 636 | |
8db62801 | 637 | /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 |
8db62801 | 638 | MOV.L Rm,@(disp,Rn) Rm-->(dispx4+Rn) 0001nnnnmmmmdddd |
8db62801 EZ |
639 | MOV.L Rm,@Rn Rm-->(Rn) 0010nnnnmmmm0010 |
640 | where Rm is one of r4,r5,r6,r7 which are the argument registers. */ | |
641 | #define IS_ARG_MOV(x) \ | |
642 | (((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) \ | |
cc17453a EZ |
643 | || ((((x) & 0xf000) == 0x1000) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) \ |
644 | || ((((x) & 0xf00f) == 0x2002) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070))) | |
8db62801 EZ |
645 | |
646 | /* MOV.L Rm,@(disp,r14) 00011110mmmmdddd | |
647 | Rm-->(dispx4+r14) where Rm is one of r4,r5,r6,r7 */ | |
3bbfbb92 | 648 | #define IS_MOV_TO_R14(x) \ |
cc17453a | 649 | ((((x) & 0xff00) == 0x1e) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) |
8db62801 EZ |
650 | |
651 | #define FPSCR_SZ (1 << 20) | |
c906108c | 652 | |
c906108c SS |
653 | /* Skip any prologue before the guts of a function */ |
654 | ||
8db62801 EZ |
655 | /* Skip the prologue using the debug information. If this fails we'll |
656 | fall back on the 'guess' method below. */ | |
657 | static CORE_ADDR | |
fba45db2 | 658 | after_prologue (CORE_ADDR pc) |
8db62801 EZ |
659 | { |
660 | struct symtab_and_line sal; | |
661 | CORE_ADDR func_addr, func_end; | |
662 | ||
663 | /* If we can not find the symbol in the partial symbol table, then | |
664 | there is no hope we can determine the function's start address | |
665 | with this code. */ | |
666 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
667 | return 0; | |
668 | ||
669 | /* Get the line associated with FUNC_ADDR. */ | |
670 | sal = find_pc_line (func_addr, 0); | |
671 | ||
672 | /* There are only two cases to consider. First, the end of the source line | |
673 | is within the function bounds. In that case we return the end of the | |
674 | source line. Second is the end of the source line extends beyond the | |
675 | bounds of the current function. We need to use the slow code to | |
676 | examine instructions in that case. */ | |
677 | if (sal.end < func_end) | |
678 | return sal.end; | |
679 | else | |
680 | return 0; | |
681 | } | |
682 | ||
683 | /* Here we look at each instruction in the function, and try to guess | |
684 | where the prologue ends. Unfortunately this is not always | |
685 | accurate. */ | |
686 | static CORE_ADDR | |
3bbfbb92 | 687 | sh_skip_prologue_hard_way (CORE_ADDR start_pc) |
c906108c | 688 | { |
2bfa91ee | 689 | CORE_ADDR here, end; |
8db62801 | 690 | int updated_fp = 0; |
2bfa91ee EZ |
691 | |
692 | if (!start_pc) | |
693 | return 0; | |
694 | ||
695 | for (here = start_pc, end = start_pc + (2 * 28); here < end;) | |
c906108c | 696 | { |
2bfa91ee EZ |
697 | int w = read_memory_integer (here, 2); |
698 | here += 2; | |
699 | if (IS_FMOV (w) || IS_PUSH (w) || IS_STS (w) || IS_MOV_R3 (w) | |
8db62801 | 700 | || IS_ADD_R3SP (w) || IS_ADD_SP (w) || IS_SHLL_R3 (w) |
3bbfbb92 | 701 | || IS_ARG_MOV (w) || IS_MOV_TO_R14 (w)) |
2bfa91ee EZ |
702 | { |
703 | start_pc = here; | |
2bfa91ee | 704 | } |
8db62801 EZ |
705 | else if (IS_MOV_SP_FP (w)) |
706 | { | |
707 | start_pc = here; | |
708 | updated_fp = 1; | |
709 | } | |
710 | else | |
711 | /* Don't bail out yet, if we are before the copy of sp. */ | |
712 | if (updated_fp) | |
713 | break; | |
c906108c SS |
714 | } |
715 | ||
716 | return start_pc; | |
717 | } | |
718 | ||
283150cd EZ |
719 | static CORE_ADDR |
720 | look_for_args_moves (CORE_ADDR start_pc, int media_mode) | |
721 | { | |
722 | CORE_ADDR here, end; | |
723 | int w; | |
724 | int insn_size = (media_mode ? 4 : 2); | |
725 | ||
726 | for (here = start_pc, end = start_pc + (insn_size * 28); here < end;) | |
727 | { | |
728 | if (media_mode) | |
729 | { | |
730 | w = read_memory_integer (UNMAKE_ISA32_ADDR (here), insn_size); | |
731 | here += insn_size; | |
732 | if (IS_MEDIA_IND_ARG_MOV (w)) | |
733 | { | |
734 | /* This must be followed by a store to r14, so the argument | |
735 | is where the debug info says it is. This can happen after | |
736 | the SP has been saved, unfortunately. */ | |
737 | ||
738 | int next_insn = read_memory_integer (UNMAKE_ISA32_ADDR (here), | |
739 | insn_size); | |
740 | here += insn_size; | |
741 | if (IS_MEDIA_MOV_TO_R14 (next_insn)) | |
742 | start_pc = here; | |
743 | } | |
744 | else if (IS_MEDIA_ARG_MOV (w)) | |
745 | { | |
746 | /* These instructions store directly the argument in r14. */ | |
747 | start_pc = here; | |
748 | } | |
749 | else | |
750 | break; | |
751 | } | |
752 | else | |
753 | { | |
754 | w = read_memory_integer (here, insn_size); | |
755 | w = w & 0xffff; | |
756 | here += insn_size; | |
757 | if (IS_COMPACT_IND_ARG_MOV (w)) | |
758 | { | |
759 | /* This must be followed by a store to r14, so the argument | |
760 | is where the debug info says it is. This can happen after | |
761 | the SP has been saved, unfortunately. */ | |
762 | ||
763 | int next_insn = 0xffff & read_memory_integer (here, insn_size); | |
764 | here += insn_size; | |
765 | if (IS_COMPACT_MOV_TO_R14 (next_insn)) | |
766 | start_pc = here; | |
767 | } | |
768 | else if (IS_COMPACT_ARG_MOV (w)) | |
769 | { | |
770 | /* These instructions store directly the argument in r14. */ | |
771 | start_pc = here; | |
772 | } | |
773 | else if (IS_MOVL_R0 (w)) | |
774 | { | |
775 | /* There is a function that gcc calls to get the arguments | |
776 | passed correctly to the function. Only after this | |
777 | function call the arguments will be found at the place | |
778 | where they are supposed to be. This happens in case the | |
779 | argument has to be stored into a 64-bit register (for | |
780 | instance doubles, long longs). SHcompact doesn't have | |
781 | access to the full 64-bits, so we store the register in | |
782 | stack slot and store the address of the stack slot in | |
783 | the register, then do a call through a wrapper that | |
784 | loads the memory value into the register. A SHcompact | |
785 | callee calls an argument decoder | |
786 | (GCC_shcompact_incoming_args) that stores the 64-bit | |
787 | value in a stack slot and stores the address of the | |
788 | stack slot in the register. GCC thinks the argument is | |
789 | just passed by transparent reference, but this is only | |
790 | true after the argument decoder is called. Such a call | |
791 | needs to be considered part of the prologue. */ | |
792 | ||
793 | /* This must be followed by a JSR @r0 instruction and by | |
794 | a NOP instruction. After these, the prologue is over! */ | |
795 | ||
796 | int next_insn = 0xffff & read_memory_integer (here, insn_size); | |
797 | here += insn_size; | |
798 | if (IS_JSR_R0 (next_insn)) | |
799 | { | |
800 | next_insn = 0xffff & read_memory_integer (here, insn_size); | |
801 | here += insn_size; | |
802 | ||
803 | if (IS_NOP (next_insn)) | |
804 | start_pc = here; | |
805 | } | |
806 | } | |
807 | else | |
808 | break; | |
809 | } | |
810 | } | |
811 | ||
812 | return start_pc; | |
813 | } | |
814 | ||
815 | static CORE_ADDR | |
816 | sh64_skip_prologue_hard_way (CORE_ADDR start_pc) | |
817 | { | |
818 | CORE_ADDR here, end; | |
819 | int updated_fp = 0; | |
820 | int insn_size = 4; | |
821 | int media_mode = 1; | |
822 | ||
823 | if (!start_pc) | |
824 | return 0; | |
825 | ||
826 | if (pc_is_isa32 (start_pc) == 0) | |
827 | { | |
828 | insn_size = 2; | |
829 | media_mode = 0; | |
830 | } | |
831 | ||
832 | for (here = start_pc, end = start_pc + (insn_size * 28); here < end;) | |
833 | { | |
834 | ||
835 | if (media_mode) | |
836 | { | |
837 | int w = read_memory_integer (UNMAKE_ISA32_ADDR (here), insn_size); | |
838 | here += insn_size; | |
839 | if (IS_STQ_R18_R14 (w) || IS_STQ_R18_R15 (w) || IS_STQ_R14_R15 (w) | |
840 | || IS_STL_R14_R15 (w) || IS_STL_R18_R15 (w) | |
841 | || IS_ADDIL_SP_MEDIA (w) || IS_ADDI_SP_MEDIA (w) || IS_PTABSL_R18 (w)) | |
842 | { | |
843 | start_pc = here; | |
844 | } | |
845 | else if (IS_MOV_SP_FP (w) || IS_MOV_SP_FP_MEDIA(w)) | |
846 | { | |
847 | start_pc = here; | |
848 | updated_fp = 1; | |
849 | } | |
850 | else | |
851 | if (updated_fp) | |
852 | { | |
853 | /* Don't bail out yet, we may have arguments stored in | |
854 | registers here, according to the debug info, so that | |
855 | gdb can print the frames correctly. */ | |
856 | start_pc = look_for_args_moves (here - insn_size, media_mode); | |
857 | break; | |
858 | } | |
859 | } | |
860 | else | |
861 | { | |
862 | int w = 0xffff & read_memory_integer (here, insn_size); | |
863 | here += insn_size; | |
864 | ||
865 | if (IS_STS_R0 (w) || IS_STS_PR (w) | |
866 | || IS_MOV_TO_R15 (w) || IS_MOV_R14 (w) | |
867 | || IS_MOV_R0 (w) || IS_ADD_SP_R0 (w) || IS_MOV_R14_R0 (w)) | |
868 | { | |
869 | start_pc = here; | |
870 | } | |
871 | else if (IS_MOV_SP_FP (w)) | |
872 | { | |
873 | start_pc = here; | |
874 | updated_fp = 1; | |
875 | } | |
876 | else | |
877 | if (updated_fp) | |
878 | { | |
879 | /* Don't bail out yet, we may have arguments stored in | |
880 | registers here, according to the debug info, so that | |
881 | gdb can print the frames correctly. */ | |
882 | start_pc = look_for_args_moves (here - insn_size, media_mode); | |
883 | break; | |
884 | } | |
885 | } | |
886 | } | |
887 | ||
888 | return start_pc; | |
889 | } | |
890 | ||
cc17453a | 891 | static CORE_ADDR |
fba45db2 | 892 | sh_skip_prologue (CORE_ADDR pc) |
8db62801 EZ |
893 | { |
894 | CORE_ADDR post_prologue_pc; | |
895 | ||
896 | /* See if we can determine the end of the prologue via the symbol table. | |
897 | If so, then return either PC, or the PC after the prologue, whichever | |
898 | is greater. */ | |
8db62801 EZ |
899 | post_prologue_pc = after_prologue (pc); |
900 | ||
901 | /* If after_prologue returned a useful address, then use it. Else | |
902 | fall back on the instruction skipping code. */ | |
903 | if (post_prologue_pc != 0) | |
904 | return max (pc, post_prologue_pc); | |
905 | else | |
906 | return (skip_prologue_hard_way (pc)); | |
907 | } | |
908 | ||
cc17453a EZ |
909 | /* Immediately after a function call, return the saved pc. |
910 | Can't always go through the frames for this because on some machines | |
911 | the new frame is not set up until the new function executes | |
912 | some instructions. | |
913 | ||
914 | The return address is the value saved in the PR register + 4 */ | |
915 | static CORE_ADDR | |
fba45db2 | 916 | sh_saved_pc_after_call (struct frame_info *frame) |
cc17453a | 917 | { |
3bbfbb92 | 918 | return (ADDR_BITS_REMOVE (read_register (gdbarch_tdep (current_gdbarch)->PR_REGNUM))); |
cc17453a EZ |
919 | } |
920 | ||
921 | /* Should call_function allocate stack space for a struct return? */ | |
922 | static int | |
fba45db2 | 923 | sh_use_struct_convention (int gcc_p, struct type *type) |
cc17453a | 924 | { |
7079c36c | 925 | #if 0 |
cc17453a | 926 | return (TYPE_LENGTH (type) > 1); |
7079c36c CV |
927 | #else |
928 | int len = TYPE_LENGTH (type); | |
929 | int nelem = TYPE_NFIELDS (type); | |
930 | return ((len != 1 && len != 2 && len != 4 && len != 8) || nelem != 1) && | |
931 | (len != 8 || TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) != 4); | |
932 | #endif | |
cc17453a EZ |
933 | } |
934 | ||
283150cd EZ |
935 | static int |
936 | sh64_use_struct_convention (int gcc_p, struct type *type) | |
937 | { | |
938 | return (TYPE_LENGTH (type) > 8); | |
939 | } | |
940 | ||
cc17453a EZ |
941 | /* Store the address of the place in which to copy the structure the |
942 | subroutine will return. This is called from call_function. | |
943 | ||
3bbfbb92 | 944 | We store structs through a pointer passed in R2 */ |
cc17453a | 945 | static void |
48db5a3c | 946 | sh64_store_struct_return (CORE_ADDR addr, CORE_ADDR sp) |
cc17453a EZ |
947 | { |
948 | write_register (STRUCT_RETURN_REGNUM, (addr)); | |
949 | } | |
c906108c | 950 | |
cc17453a EZ |
951 | /* Disassemble an instruction. */ |
952 | static int | |
fba45db2 | 953 | gdb_print_insn_sh (bfd_vma memaddr, disassemble_info *info) |
c906108c | 954 | { |
1c509ca8 JR |
955 | info->endian = TARGET_BYTE_ORDER; |
956 | return print_insn_sh (memaddr, info); | |
283150cd EZ |
957 | } |
958 | ||
a5afb99f AC |
959 | /* Given a GDB frame, determine the address of the calling function's |
960 | frame. This will be used to create a new GDB frame struct, and | |
e9582e71 AC |
961 | then DEPRECATED_INIT_EXTRA_FRAME_INFO and DEPRECATED_INIT_FRAME_PC |
962 | will be called for the new frame. | |
c906108c SS |
963 | |
964 | For us, the frame address is its stack pointer value, so we look up | |
965 | the function prologue to determine the caller's sp value, and return it. */ | |
cc17453a | 966 | static CORE_ADDR |
fba45db2 | 967 | sh_frame_chain (struct frame_info *frame) |
c906108c | 968 | { |
1e2330ba AC |
969 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), |
970 | get_frame_base (frame), | |
971 | get_frame_base (frame))) | |
972 | return get_frame_base (frame); /* dummy frame same as caller's frame */ | |
50abf9e5 | 973 | if (get_frame_pc (frame) && !inside_entry_file (get_frame_pc (frame))) |
da50a4b7 AC |
974 | return read_memory_integer (get_frame_base (frame) |
975 | + get_frame_extra_info (frame)->f_offset, 4); | |
c906108c SS |
976 | else |
977 | return 0; | |
978 | } | |
979 | ||
283150cd EZ |
980 | /* Given a register number RN as it appears in an assembly |
981 | instruction, find the corresponding register number in the GDB | |
982 | scheme. */ | |
983 | static int | |
984 | translate_insn_rn (int rn, int media_mode) | |
985 | { | |
986 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
987 | ||
988 | /* FIXME: this assumes that the number rn is for a not pseudo | |
989 | register only. */ | |
990 | if (media_mode) | |
991 | return rn; | |
992 | else | |
993 | { | |
994 | /* These registers don't have a corresponding compact one. */ | |
995 | /* FIXME: This is probably not enough. */ | |
996 | #if 0 | |
997 | if ((rn >= 16 && rn <= 63) || (rn >= 93 && rn <= 140)) | |
998 | return rn; | |
999 | #endif | |
1000 | if (rn >= 0 && rn <= tdep->R0_C_REGNUM) | |
1001 | return tdep->R0_C_REGNUM + rn; | |
1002 | else | |
1003 | return rn; | |
1004 | } | |
1005 | } | |
1006 | ||
1007 | static CORE_ADDR | |
1008 | sh64_frame_chain (struct frame_info *frame) | |
1009 | { | |
1e2330ba AC |
1010 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), |
1011 | get_frame_base (frame), | |
1012 | get_frame_base (frame))) | |
1013 | return get_frame_base (frame); /* dummy frame same as caller's frame */ | |
50abf9e5 | 1014 | if (get_frame_pc (frame) && !inside_entry_file (get_frame_pc (frame))) |
283150cd | 1015 | { |
50abf9e5 | 1016 | int media_mode = pc_is_isa32 (get_frame_pc (frame)); |
283150cd EZ |
1017 | int size; |
1018 | if (gdbarch_tdep (current_gdbarch)->sh_abi == SH_ABI_32) | |
1019 | size = 4; | |
1020 | else | |
0ba6dca9 | 1021 | size = REGISTER_RAW_SIZE (translate_insn_rn (DEPRECATED_FP_REGNUM, media_mode)); |
da50a4b7 AC |
1022 | return read_memory_integer (get_frame_base (frame) |
1023 | + get_frame_extra_info (frame)->f_offset, | |
1024 | size); | |
283150cd EZ |
1025 | } |
1026 | else | |
1027 | return 0; | |
1028 | } | |
1029 | ||
c906108c SS |
1030 | /* Find REGNUM on the stack. Otherwise, it's in an active register. One thing |
1031 | we might want to do here is to check REGNUM against the clobber mask, and | |
1032 | somehow flag it as invalid if it isn't saved on the stack somewhere. This | |
1033 | would provide a graceful failure mode when trying to get the value of | |
1034 | caller-saves registers for an inner frame. */ | |
cc17453a | 1035 | static CORE_ADDR |
fba45db2 | 1036 | sh_find_callers_reg (struct frame_info *fi, int regnum) |
c906108c | 1037 | { |
11c02a10 | 1038 | for (; fi; fi = get_next_frame (fi)) |
1e2330ba AC |
1039 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), get_frame_base (fi), |
1040 | get_frame_base (fi))) | |
c906108c | 1041 | /* When the caller requests PR from the dummy frame, we return PC because |
c5aa993b | 1042 | that's where the previous routine appears to have done a call from. */ |
1e2330ba AC |
1043 | return deprecated_read_register_dummy (get_frame_pc (fi), |
1044 | get_frame_base (fi), regnum); | |
c5aa993b | 1045 | else |
c906108c | 1046 | { |
f30ee0bc | 1047 | DEPRECATED_FRAME_INIT_SAVED_REGS (fi); |
50abf9e5 | 1048 | if (!get_frame_pc (fi)) |
2bfa91ee | 1049 | return 0; |
b2fb4676 AC |
1050 | if (get_frame_saved_regs (fi)[regnum] != 0) |
1051 | return read_memory_integer (get_frame_saved_regs (fi)[regnum], | |
48db5a3c | 1052 | register_size (current_gdbarch, regnum)); |
c906108c SS |
1053 | } |
1054 | return read_register (regnum); | |
1055 | } | |
1056 | ||
283150cd EZ |
1057 | static CORE_ADDR |
1058 | sh64_get_saved_pr (struct frame_info *fi, int pr_regnum) | |
1059 | { | |
1060 | int media_mode = 0; | |
1061 | ||
11c02a10 | 1062 | for (; fi; fi = get_next_frame (fi)) |
1e2330ba AC |
1063 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), get_frame_base (fi), |
1064 | get_frame_base (fi))) | |
283150cd EZ |
1065 | /* When the caller requests PR from the dummy frame, we return PC because |
1066 | that's where the previous routine appears to have done a call from. */ | |
1e2330ba AC |
1067 | return deprecated_read_register_dummy (get_frame_pc (fi), |
1068 | get_frame_base (fi), pr_regnum); | |
283150cd EZ |
1069 | else |
1070 | { | |
f30ee0bc | 1071 | DEPRECATED_FRAME_INIT_SAVED_REGS (fi); |
50abf9e5 | 1072 | if (!get_frame_pc (fi)) |
283150cd EZ |
1073 | return 0; |
1074 | ||
50abf9e5 | 1075 | media_mode = pc_is_isa32 (get_frame_pc (fi)); |
283150cd | 1076 | |
b2fb4676 | 1077 | if (get_frame_saved_regs (fi)[pr_regnum] != 0) |
283150cd EZ |
1078 | { |
1079 | int gdb_reg_num = translate_insn_rn (pr_regnum, media_mode); | |
1080 | int size = ((gdbarch_tdep (current_gdbarch)->sh_abi == SH_ABI_32) | |
1081 | ? 4 | |
1082 | : REGISTER_RAW_SIZE (gdb_reg_num)); | |
b2fb4676 | 1083 | return read_memory_integer (get_frame_saved_regs (fi)[pr_regnum], size); |
283150cd EZ |
1084 | } |
1085 | } | |
1086 | return read_register (pr_regnum); | |
1087 | } | |
1088 | ||
c906108c SS |
1089 | /* Put here the code to store, into a struct frame_saved_regs, the |
1090 | addresses of the saved registers of frame described by FRAME_INFO. | |
1091 | This includes special registers such as pc and fp saved in special | |
1092 | ways in the stack frame. sp is even more special: the address we | |
1093 | return for it IS the sp for the next frame. */ | |
cc17453a | 1094 | static void |
fba45db2 | 1095 | sh_nofp_frame_init_saved_regs (struct frame_info *fi) |
c906108c | 1096 | { |
e7d717c0 | 1097 | int *where = (int *) alloca ((NUM_REGS + NUM_PSEUDO_REGS) * sizeof(int)); |
c906108c SS |
1098 | int rn; |
1099 | int have_fp = 0; | |
1100 | int depth; | |
1101 | int pc; | |
1102 | int opc; | |
1103 | int insn; | |
1104 | int r3_val = 0; | |
1e2330ba AC |
1105 | char *dummy_regs = deprecated_generic_find_dummy_frame (get_frame_pc (fi), |
1106 | get_frame_base (fi)); | |
cc17453a | 1107 | |
b2fb4676 | 1108 | if (get_frame_saved_regs (fi) == NULL) |
cc17453a EZ |
1109 | frame_saved_regs_zalloc (fi); |
1110 | else | |
b2fb4676 | 1111 | memset (get_frame_saved_regs (fi), 0, SIZEOF_FRAME_SAVED_REGS); |
cc17453a EZ |
1112 | |
1113 | if (dummy_regs) | |
1114 | { | |
1115 | /* DANGER! This is ONLY going to work if the char buffer format of | |
1116 | the saved registers is byte-for-byte identical to the | |
1117 | CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */ | |
7b5849cc | 1118 | memcpy (get_frame_saved_regs (fi), dummy_regs, SIZEOF_FRAME_SAVED_REGS); |
cc17453a EZ |
1119 | return; |
1120 | } | |
1121 | ||
da50a4b7 AC |
1122 | get_frame_extra_info (fi)->leaf_function = 1; |
1123 | get_frame_extra_info (fi)->f_offset = 0; | |
cc17453a | 1124 | |
cd4bffcf | 1125 | for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++) |
cc17453a EZ |
1126 | where[rn] = -1; |
1127 | ||
1128 | depth = 0; | |
1129 | ||
1130 | /* Loop around examining the prologue insns until we find something | |
1131 | that does not appear to be part of the prologue. But give up | |
1132 | after 20 of them, since we're getting silly then. */ | |
1133 | ||
be41e9f4 | 1134 | pc = get_frame_func (fi); |
cc17453a EZ |
1135 | if (!pc) |
1136 | { | |
50abf9e5 | 1137 | deprecated_update_frame_pc_hack (fi, 0); |
cc17453a EZ |
1138 | return; |
1139 | } | |
1140 | ||
1141 | for (opc = pc + (2 * 28); pc < opc; pc += 2) | |
1142 | { | |
1143 | insn = read_memory_integer (pc, 2); | |
1144 | /* See where the registers will be saved to */ | |
1145 | if (IS_PUSH (insn)) | |
1146 | { | |
1147 | rn = GET_PUSHED_REG (insn); | |
1148 | where[rn] = depth; | |
1149 | depth += 4; | |
1150 | } | |
1151 | else if (IS_STS (insn)) | |
1152 | { | |
3bbfbb92 | 1153 | where[gdbarch_tdep (current_gdbarch)->PR_REGNUM] = depth; |
cc17453a | 1154 | /* If we're storing the pr then this isn't a leaf */ |
da50a4b7 | 1155 | get_frame_extra_info (fi)->leaf_function = 0; |
cc17453a EZ |
1156 | depth += 4; |
1157 | } | |
1158 | else if (IS_MOV_R3 (insn)) | |
1159 | { | |
1160 | r3_val = ((insn & 0xff) ^ 0x80) - 0x80; | |
1161 | } | |
1162 | else if (IS_SHLL_R3 (insn)) | |
1163 | { | |
1164 | r3_val <<= 1; | |
1165 | } | |
1166 | else if (IS_ADD_R3SP (insn)) | |
1167 | { | |
1168 | depth += -r3_val; | |
1169 | } | |
1170 | else if (IS_ADD_SP (insn)) | |
1171 | { | |
1172 | depth -= ((insn & 0xff) ^ 0x80) - 0x80; | |
1173 | } | |
1174 | else if (IS_MOV_SP_FP (insn)) | |
1175 | break; | |
1176 | #if 0 /* This used to just stop when it found an instruction that | |
1177 | was not considered part of the prologue. Now, we just | |
1178 | keep going looking for likely instructions. */ | |
1179 | else | |
1180 | break; | |
1181 | #endif | |
1182 | } | |
1183 | ||
1184 | /* Now we know how deep things are, we can work out their addresses */ | |
1185 | ||
cd4bffcf | 1186 | for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++) |
cc17453a EZ |
1187 | { |
1188 | if (where[rn] >= 0) | |
1189 | { | |
0ba6dca9 | 1190 | if (rn == DEPRECATED_FP_REGNUM) |
cc17453a | 1191 | have_fp = 1; |
c906108c | 1192 | |
1e2330ba | 1193 | get_frame_saved_regs (fi)[rn] = get_frame_base (fi) - where[rn] + depth - 4; |
cc17453a EZ |
1194 | } |
1195 | else | |
1196 | { | |
b2fb4676 | 1197 | get_frame_saved_regs (fi)[rn] = 0; |
cc17453a EZ |
1198 | } |
1199 | } | |
1200 | ||
1201 | if (have_fp) | |
1202 | { | |
0ba6dca9 | 1203 | get_frame_saved_regs (fi)[SP_REGNUM] = read_memory_integer (get_frame_saved_regs (fi)[DEPRECATED_FP_REGNUM], 4); |
cc17453a EZ |
1204 | } |
1205 | else | |
1206 | { | |
1e2330ba | 1207 | get_frame_saved_regs (fi)[SP_REGNUM] = get_frame_base (fi) - 4; |
cc17453a EZ |
1208 | } |
1209 | ||
0ba6dca9 | 1210 | get_frame_extra_info (fi)->f_offset = depth - where[DEPRECATED_FP_REGNUM] - 4; |
cc17453a EZ |
1211 | /* Work out the return pc - either from the saved pr or the pr |
1212 | value */ | |
1213 | } | |
1214 | ||
3bbfbb92 EZ |
1215 | /* For vectors of 4 floating point registers. */ |
1216 | static int | |
1217 | fv_reg_base_num (int fv_regnum) | |
1218 | { | |
1219 | int fp_regnum; | |
1220 | ||
1221 | fp_regnum = FP0_REGNUM + | |
1222 | (fv_regnum - gdbarch_tdep (current_gdbarch)->FV0_REGNUM) * 4; | |
1223 | return fp_regnum; | |
1224 | } | |
1225 | ||
1226 | /* For double precision floating point registers, i.e 2 fp regs.*/ | |
1227 | static int | |
1228 | dr_reg_base_num (int dr_regnum) | |
1229 | { | |
1230 | int fp_regnum; | |
1231 | ||
1232 | fp_regnum = FP0_REGNUM + | |
1233 | (dr_regnum - gdbarch_tdep (current_gdbarch)->DR0_REGNUM) * 2; | |
1234 | return fp_regnum; | |
1235 | } | |
1236 | ||
283150cd EZ |
1237 | /* For pairs of floating point registers */ |
1238 | static int | |
1239 | fpp_reg_base_num (int fpp_regnum) | |
1240 | { | |
1241 | int fp_regnum; | |
1242 | ||
1243 | fp_regnum = FP0_REGNUM + | |
1244 | (fpp_regnum - gdbarch_tdep (current_gdbarch)->FPP0_REGNUM) * 2; | |
1245 | return fp_regnum; | |
1246 | } | |
1247 | ||
1248 | static int | |
1249 | is_media_pseudo (int rn) | |
1250 | { | |
1251 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
1252 | ||
1253 | return (rn >= tdep->DR0_REGNUM | |
1254 | && rn <= tdep->FV_LAST_REGNUM); | |
1255 | } | |
1256 | ||
a78f21af | 1257 | static int |
283150cd EZ |
1258 | sh64_get_gdb_regnum (int gcc_regnum, CORE_ADDR pc) |
1259 | { | |
1260 | return translate_insn_rn (gcc_regnum, pc_is_isa32 (pc)); | |
1261 | } | |
1262 | ||
1263 | static int | |
1264 | sh64_media_reg_base_num (int reg_nr) | |
1265 | { | |
1266 | int base_regnum = -1; | |
1267 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
1268 | ||
1269 | if (reg_nr >= tdep->DR0_REGNUM | |
1270 | && reg_nr <= tdep->DR_LAST_REGNUM) | |
1271 | base_regnum = dr_reg_base_num (reg_nr); | |
1272 | ||
1273 | else if (reg_nr >= tdep->FPP0_REGNUM | |
1274 | && reg_nr <= tdep->FPP_LAST_REGNUM) | |
1275 | base_regnum = fpp_reg_base_num (reg_nr); | |
1276 | ||
1277 | else if (reg_nr >= tdep->FV0_REGNUM | |
1278 | && reg_nr <= tdep->FV_LAST_REGNUM) | |
1279 | base_regnum = fv_reg_base_num (reg_nr); | |
1280 | ||
1281 | return base_regnum; | |
1282 | } | |
1283 | ||
1284 | /* *INDENT-OFF* */ | |
1285 | /* | |
1286 | SH COMPACT MODE (ISA 16) (all pseudo) 221-272 | |
1287 | GDB_REGNUM BASE_REGNUM | |
1288 | r0_c 221 0 | |
1289 | r1_c 222 1 | |
1290 | r2_c 223 2 | |
1291 | r3_c 224 3 | |
1292 | r4_c 225 4 | |
1293 | r5_c 226 5 | |
1294 | r6_c 227 6 | |
1295 | r7_c 228 7 | |
1296 | r8_c 229 8 | |
1297 | r9_c 230 9 | |
1298 | r10_c 231 10 | |
1299 | r11_c 232 11 | |
1300 | r12_c 233 12 | |
1301 | r13_c 234 13 | |
1302 | r14_c 235 14 | |
1303 | r15_c 236 15 | |
1304 | ||
1305 | pc_c 237 64 | |
1306 | gbr_c 238 16 | |
1307 | mach_c 239 17 | |
1308 | macl_c 240 17 | |
1309 | pr_c 241 18 | |
1310 | t_c 242 19 | |
1311 | fpscr_c 243 76 | |
1312 | fpul_c 244 109 | |
1313 | ||
1314 | fr0_c 245 77 | |
1315 | fr1_c 246 78 | |
1316 | fr2_c 247 79 | |
1317 | fr3_c 248 80 | |
1318 | fr4_c 249 81 | |
1319 | fr5_c 250 82 | |
1320 | fr6_c 251 83 | |
1321 | fr7_c 252 84 | |
1322 | fr8_c 253 85 | |
1323 | fr9_c 254 86 | |
1324 | fr10_c 255 87 | |
1325 | fr11_c 256 88 | |
1326 | fr12_c 257 89 | |
1327 | fr13_c 258 90 | |
1328 | fr14_c 259 91 | |
1329 | fr15_c 260 92 | |
1330 | ||
1331 | dr0_c 261 77 | |
1332 | dr2_c 262 79 | |
1333 | dr4_c 263 81 | |
1334 | dr6_c 264 83 | |
1335 | dr8_c 265 85 | |
1336 | dr10_c 266 87 | |
1337 | dr12_c 267 89 | |
1338 | dr14_c 268 91 | |
1339 | ||
1340 | fv0_c 269 77 | |
1341 | fv4_c 270 81 | |
1342 | fv8_c 271 85 | |
1343 | fv12_c 272 91 | |
1344 | */ | |
1345 | /* *INDENT-ON* */ | |
1346 | static int | |
1347 | sh64_compact_reg_base_num (int reg_nr) | |
1348 | { | |
1349 | int base_regnum = -1; | |
1350 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
1351 | ||
1352 | /* general register N maps to general register N */ | |
1353 | if (reg_nr >= tdep->R0_C_REGNUM | |
1354 | && reg_nr <= tdep->R_LAST_C_REGNUM) | |
1355 | base_regnum = reg_nr - tdep->R0_C_REGNUM; | |
1356 | ||
1357 | /* floating point register N maps to floating point register N */ | |
1358 | else if (reg_nr >= tdep->FP0_C_REGNUM | |
1359 | && reg_nr <= tdep->FP_LAST_C_REGNUM) | |
1360 | base_regnum = reg_nr - tdep->FP0_C_REGNUM + FP0_REGNUM; | |
1361 | ||
1362 | /* double prec register N maps to base regnum for double prec register N */ | |
1363 | else if (reg_nr >= tdep->DR0_C_REGNUM | |
1364 | && reg_nr <= tdep->DR_LAST_C_REGNUM) | |
1365 | base_regnum = dr_reg_base_num (tdep->DR0_REGNUM | |
1366 | + reg_nr - tdep->DR0_C_REGNUM); | |
1367 | ||
1368 | /* vector N maps to base regnum for vector register N */ | |
1369 | else if (reg_nr >= tdep->FV0_C_REGNUM | |
1370 | && reg_nr <= tdep->FV_LAST_C_REGNUM) | |
1371 | base_regnum = fv_reg_base_num (tdep->FV0_REGNUM | |
1372 | + reg_nr - tdep->FV0_C_REGNUM); | |
1373 | ||
1374 | else if (reg_nr == tdep->PC_C_REGNUM) | |
1375 | base_regnum = PC_REGNUM; | |
1376 | ||
1377 | else if (reg_nr == tdep->GBR_C_REGNUM) | |
1378 | base_regnum = 16; | |
1379 | ||
1380 | else if (reg_nr == tdep->MACH_C_REGNUM | |
1381 | || reg_nr == tdep->MACL_C_REGNUM) | |
1382 | base_regnum = 17; | |
1383 | ||
1384 | else if (reg_nr == tdep->PR_C_REGNUM) | |
1385 | base_regnum = 18; | |
1386 | ||
1387 | else if (reg_nr == tdep->T_C_REGNUM) | |
1388 | base_regnum = 19; | |
1389 | ||
1390 | else if (reg_nr == tdep->FPSCR_C_REGNUM) | |
1391 | base_regnum = tdep->FPSCR_REGNUM; /*???? this register is a mess. */ | |
1392 | ||
1393 | else if (reg_nr == tdep->FPUL_C_REGNUM) | |
1394 | base_regnum = FP0_REGNUM + 32; | |
1395 | ||
1396 | return base_regnum; | |
1397 | } | |
1398 | ||
1399 | /* Given a register number RN (according to the gdb scheme) , return | |
1400 | its corresponding architectural register. In media mode, only a | |
1401 | subset of the registers is pseudo registers. For compact mode, all | |
1402 | the registers are pseudo. */ | |
1403 | static int | |
1404 | translate_rn_to_arch_reg_num (int rn, int media_mode) | |
1405 | { | |
1406 | ||
1407 | if (media_mode) | |
1408 | { | |
1409 | if (!is_media_pseudo (rn)) | |
1410 | return rn; | |
1411 | else | |
1412 | return sh64_media_reg_base_num (rn); | |
1413 | } | |
1414 | else | |
1415 | /* All compact registers are pseudo. */ | |
1416 | return sh64_compact_reg_base_num (rn); | |
1417 | } | |
1418 | ||
1419 | static int | |
1420 | sign_extend (int value, int bits) | |
1421 | { | |
1422 | value = value & ((1 << bits) - 1); | |
1423 | return (value & (1 << (bits - 1)) | |
1424 | ? value | (~((1 << bits) - 1)) | |
1425 | : value); | |
1426 | } | |
1427 | ||
cc17453a | 1428 | static void |
283150cd | 1429 | sh64_nofp_frame_init_saved_regs (struct frame_info *fi) |
cc17453a | 1430 | { |
ddde02bd | 1431 | int *where = (int *) alloca ((NUM_REGS + NUM_PSEUDO_REGS) * sizeof (int)); |
cc17453a EZ |
1432 | int rn; |
1433 | int have_fp = 0; | |
283150cd EZ |
1434 | int fp_regnum; |
1435 | int sp_regnum; | |
1436 | int depth; | |
1437 | int pc; | |
1438 | int opc; | |
1439 | int insn; | |
1440 | int r0_val = 0; | |
1441 | int media_mode = 0; | |
1442 | int insn_size; | |
1443 | int gdb_register_number; | |
1444 | int register_number; | |
1e2330ba | 1445 | char *dummy_regs = deprecated_generic_find_dummy_frame (get_frame_pc (fi), get_frame_base (fi)); |
283150cd EZ |
1446 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
1447 | ||
b2fb4676 | 1448 | if (get_frame_saved_regs (fi) == NULL) |
283150cd EZ |
1449 | frame_saved_regs_zalloc (fi); |
1450 | else | |
b2fb4676 | 1451 | memset (get_frame_saved_regs (fi), 0, SIZEOF_FRAME_SAVED_REGS); |
283150cd EZ |
1452 | |
1453 | if (dummy_regs) | |
1454 | { | |
1455 | /* DANGER! This is ONLY going to work if the char buffer format of | |
1456 | the saved registers is byte-for-byte identical to the | |
1457 | CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */ | |
7b5849cc | 1458 | memcpy (get_frame_saved_regs (fi), dummy_regs, SIZEOF_FRAME_SAVED_REGS); |
283150cd EZ |
1459 | return; |
1460 | } | |
1461 | ||
da50a4b7 AC |
1462 | get_frame_extra_info (fi)->leaf_function = 1; |
1463 | get_frame_extra_info (fi)->f_offset = 0; | |
283150cd EZ |
1464 | |
1465 | for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++) | |
1466 | where[rn] = -1; | |
1467 | ||
1468 | depth = 0; | |
1469 | ||
1470 | /* Loop around examining the prologue insns until we find something | |
1471 | that does not appear to be part of the prologue. But give up | |
1472 | after 20 of them, since we're getting silly then. */ | |
1473 | ||
be41e9f4 | 1474 | pc = get_frame_func (fi); |
283150cd EZ |
1475 | if (!pc) |
1476 | { | |
50abf9e5 | 1477 | deprecated_update_frame_pc_hack (fi, 0); |
283150cd EZ |
1478 | return; |
1479 | } | |
1480 | ||
1481 | if (pc_is_isa32 (pc)) | |
1482 | { | |
1483 | media_mode = 1; | |
1484 | insn_size = 4; | |
1485 | } | |
1486 | else | |
1487 | { | |
1488 | media_mode = 0; | |
1489 | insn_size = 2; | |
1490 | } | |
1491 | ||
1492 | /* The frame pointer register is general register 14 in shmedia and | |
1493 | shcompact modes. In sh compact it is a pseudo register. Same goes | |
1494 | for the stack pointer register, which is register 15. */ | |
0ba6dca9 | 1495 | fp_regnum = translate_insn_rn (DEPRECATED_FP_REGNUM, media_mode); |
283150cd EZ |
1496 | sp_regnum = translate_insn_rn (SP_REGNUM, media_mode); |
1497 | ||
1498 | for (opc = pc + (insn_size * 28); pc < opc; pc += insn_size) | |
1499 | { | |
1500 | insn = read_memory_integer (media_mode ? UNMAKE_ISA32_ADDR (pc) : pc, | |
1501 | insn_size); | |
1502 | ||
1503 | if (media_mode == 0) | |
1504 | { | |
1505 | if (IS_STS_PR (insn)) | |
1506 | { | |
1507 | int next_insn = read_memory_integer (pc + insn_size, insn_size); | |
1508 | if (IS_MOV_TO_R15 (next_insn)) | |
1509 | { | |
1510 | int reg_nr = tdep->PR_C_REGNUM; | |
1511 | ||
1512 | where[reg_nr] = depth - ((((next_insn & 0xf) ^ 0x8) - 0x8) << 2); | |
da50a4b7 | 1513 | get_frame_extra_info (fi)->leaf_function = 0; |
283150cd EZ |
1514 | pc += insn_size; |
1515 | } | |
1516 | } | |
1517 | else if (IS_MOV_R14 (insn)) | |
1518 | { | |
1519 | where[fp_regnum] = depth - ((((insn & 0xf) ^ 0x8) - 0x8) << 2); | |
1520 | } | |
1521 | ||
1522 | else if (IS_MOV_R0 (insn)) | |
1523 | { | |
1524 | /* Put in R0 the offset from SP at which to store some | |
1525 | registers. We are interested in this value, because it | |
1526 | will tell us where the given registers are stored within | |
1527 | the frame. */ | |
1528 | r0_val = ((insn & 0xff) ^ 0x80) - 0x80; | |
1529 | } | |
1530 | else if (IS_ADD_SP_R0 (insn)) | |
1531 | { | |
1532 | /* This instruction still prepares r0, but we don't care. | |
1533 | We already have the offset in r0_val. */ | |
1534 | } | |
1535 | else if (IS_STS_R0 (insn)) | |
1536 | { | |
1537 | /* Store PR at r0_val-4 from SP. Decrement r0 by 4*/ | |
1538 | int reg_nr = tdep->PR_C_REGNUM; | |
1539 | where[reg_nr] = depth - (r0_val - 4); | |
1540 | r0_val -= 4; | |
da50a4b7 | 1541 | get_frame_extra_info (fi)->leaf_function = 0; |
283150cd EZ |
1542 | } |
1543 | else if (IS_MOV_R14_R0 (insn)) | |
1544 | { | |
1545 | /* Store R14 at r0_val-4 from SP. Decrement r0 by 4 */ | |
1546 | where[fp_regnum] = depth - (r0_val - 4); | |
1547 | r0_val -= 4; | |
1548 | } | |
1549 | ||
1550 | else if (IS_ADD_SP (insn)) | |
1551 | { | |
1552 | depth -= ((insn & 0xff) ^ 0x80) - 0x80; | |
1553 | } | |
1554 | else if (IS_MOV_SP_FP (insn)) | |
1555 | break; | |
1556 | } | |
1557 | else | |
1558 | { | |
1559 | if (IS_ADDIL_SP_MEDIA (insn) | |
1560 | || IS_ADDI_SP_MEDIA (insn)) | |
1561 | { | |
1562 | depth -= sign_extend ((((insn & 0xffc00) ^ 0x80000) - 0x80000) >> 10, 9); | |
1563 | } | |
1564 | ||
1565 | else if (IS_STQ_R18_R15 (insn)) | |
1566 | { | |
1567 | where[tdep->PR_REGNUM] = | |
1568 | depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 3); | |
da50a4b7 | 1569 | get_frame_extra_info (fi)->leaf_function = 0; |
283150cd EZ |
1570 | } |
1571 | ||
1572 | else if (IS_STL_R18_R15 (insn)) | |
1573 | { | |
1574 | where[tdep->PR_REGNUM] = | |
1575 | depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 2); | |
da50a4b7 | 1576 | get_frame_extra_info (fi)->leaf_function = 0; |
283150cd EZ |
1577 | } |
1578 | ||
1579 | else if (IS_STQ_R14_R15 (insn)) | |
1580 | { | |
1581 | where[fp_regnum] = depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 3); | |
1582 | } | |
1583 | ||
1584 | else if (IS_STL_R14_R15 (insn)) | |
1585 | { | |
1586 | where[fp_regnum] = depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 2); | |
1587 | } | |
1588 | ||
1589 | else if (IS_MOV_SP_FP_MEDIA (insn)) | |
1590 | break; | |
1591 | } | |
1592 | } | |
1593 | ||
1594 | /* Now we know how deep things are, we can work out their addresses. */ | |
1595 | for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++) | |
1596 | { | |
1597 | register_number = translate_rn_to_arch_reg_num (rn, media_mode); | |
1598 | ||
1599 | if (where[rn] >= 0) | |
1600 | { | |
1601 | if (rn == fp_regnum) | |
1602 | have_fp = 1; | |
1603 | ||
1604 | /* Watch out! saved_regs is only for the real registers, and | |
1605 | doesn't include space for the pseudo registers. */ | |
1e2330ba | 1606 | get_frame_saved_regs (fi)[register_number]= get_frame_base (fi) - where[rn] + depth; |
283150cd EZ |
1607 | |
1608 | } | |
1609 | else | |
b2fb4676 | 1610 | get_frame_saved_regs (fi)[register_number] = 0; |
283150cd EZ |
1611 | } |
1612 | ||
1613 | if (have_fp) | |
1614 | { | |
1615 | /* SP_REGNUM is 15. For shmedia 15 is the real register. For | |
1616 | shcompact 15 is the arch register corresponding to the pseudo | |
1617 | register r15 which still is the SP register. */ | |
1618 | /* The place on the stack where fp is stored contains the sp of | |
1619 | the caller. */ | |
0ba6dca9 AC |
1620 | /* Again, saved_registers contains only space for the real |
1621 | registers, so we store in DEPRECATED_FP_REGNUM position. */ | |
283150cd EZ |
1622 | int size; |
1623 | if (tdep->sh_abi == SH_ABI_32) | |
1624 | size = 4; | |
1625 | else | |
1626 | size = REGISTER_RAW_SIZE (fp_regnum); | |
b2fb4676 | 1627 | get_frame_saved_regs (fi)[sp_regnum] = read_memory_integer (get_frame_saved_regs (fi)[fp_regnum], size); |
283150cd EZ |
1628 | } |
1629 | else | |
1e2330ba | 1630 | get_frame_saved_regs (fi)[sp_regnum] = get_frame_base (fi); |
283150cd | 1631 | |
da50a4b7 | 1632 | get_frame_extra_info (fi)->f_offset = depth - where[fp_regnum]; |
283150cd EZ |
1633 | } |
1634 | ||
1635 | static void | |
1636 | sh_fp_frame_init_saved_regs (struct frame_info *fi) | |
1637 | { | |
ddde02bd | 1638 | int *where = (int *) alloca ((NUM_REGS + NUM_PSEUDO_REGS) * sizeof (int)); |
283150cd EZ |
1639 | int rn; |
1640 | int have_fp = 0; | |
cc17453a EZ |
1641 | int depth; |
1642 | int pc; | |
1643 | int opc; | |
1644 | int insn; | |
1645 | int r3_val = 0; | |
1e2330ba | 1646 | char *dummy_regs = deprecated_generic_find_dummy_frame (get_frame_pc (fi), get_frame_base (fi)); |
f81353e4 | 1647 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
cc17453a | 1648 | |
b2fb4676 | 1649 | if (get_frame_saved_regs (fi) == NULL) |
cc17453a EZ |
1650 | frame_saved_regs_zalloc (fi); |
1651 | else | |
b2fb4676 | 1652 | memset (get_frame_saved_regs (fi), 0, SIZEOF_FRAME_SAVED_REGS); |
cc17453a | 1653 | |
c906108c SS |
1654 | if (dummy_regs) |
1655 | { | |
1656 | /* DANGER! This is ONLY going to work if the char buffer format of | |
c5aa993b JM |
1657 | the saved registers is byte-for-byte identical to the |
1658 | CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */ | |
7b5849cc | 1659 | memcpy (get_frame_saved_regs (fi), dummy_regs, SIZEOF_FRAME_SAVED_REGS); |
c906108c SS |
1660 | return; |
1661 | } | |
1662 | ||
da50a4b7 AC |
1663 | get_frame_extra_info (fi)->leaf_function = 1; |
1664 | get_frame_extra_info (fi)->f_offset = 0; | |
c906108c | 1665 | |
cd4bffcf | 1666 | for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++) |
c906108c SS |
1667 | where[rn] = -1; |
1668 | ||
1669 | depth = 0; | |
1670 | ||
1671 | /* Loop around examining the prologue insns until we find something | |
1672 | that does not appear to be part of the prologue. But give up | |
1673 | after 20 of them, since we're getting silly then. */ | |
1674 | ||
be41e9f4 | 1675 | pc = get_frame_func (fi); |
2bfa91ee | 1676 | if (!pc) |
c906108c | 1677 | { |
50abf9e5 | 1678 | deprecated_update_frame_pc_hack (fi, 0); |
2bfa91ee EZ |
1679 | return; |
1680 | } | |
1681 | ||
1682 | for (opc = pc + (2 * 28); pc < opc; pc += 2) | |
1683 | { | |
1684 | insn = read_memory_integer (pc, 2); | |
c906108c SS |
1685 | /* See where the registers will be saved to */ |
1686 | if (IS_PUSH (insn)) | |
1687 | { | |
c906108c SS |
1688 | rn = GET_PUSHED_REG (insn); |
1689 | where[rn] = depth; | |
c906108c SS |
1690 | depth += 4; |
1691 | } | |
1692 | else if (IS_STS (insn)) | |
1693 | { | |
f81353e4 | 1694 | where[tdep->PR_REGNUM] = depth; |
c906108c | 1695 | /* If we're storing the pr then this isn't a leaf */ |
da50a4b7 | 1696 | get_frame_extra_info (fi)->leaf_function = 0; |
c906108c SS |
1697 | depth += 4; |
1698 | } | |
1699 | else if (IS_MOV_R3 (insn)) | |
1700 | { | |
1701 | r3_val = ((insn & 0xff) ^ 0x80) - 0x80; | |
c906108c SS |
1702 | } |
1703 | else if (IS_SHLL_R3 (insn)) | |
1704 | { | |
1705 | r3_val <<= 1; | |
c906108c SS |
1706 | } |
1707 | else if (IS_ADD_R3SP (insn)) | |
1708 | { | |
1709 | depth += -r3_val; | |
c906108c SS |
1710 | } |
1711 | else if (IS_ADD_SP (insn)) | |
1712 | { | |
c906108c | 1713 | depth -= ((insn & 0xff) ^ 0x80) - 0x80; |
c906108c SS |
1714 | } |
1715 | else if (IS_FMOV (insn)) | |
1716 | { | |
f81353e4 | 1717 | if (read_register (tdep->FPSCR_REGNUM) & FPSCR_SZ) |
c906108c SS |
1718 | { |
1719 | depth += 8; | |
1720 | } | |
1721 | else | |
1722 | { | |
1723 | depth += 4; | |
1724 | } | |
1725 | } | |
2bfa91ee EZ |
1726 | else if (IS_MOV_SP_FP (insn)) |
1727 | break; | |
1728 | #if 0 /* This used to just stop when it found an instruction that | |
1729 | was not considered part of the prologue. Now, we just | |
1730 | keep going looking for likely instructions. */ | |
c906108c SS |
1731 | else |
1732 | break; | |
2bfa91ee | 1733 | #endif |
c906108c SS |
1734 | } |
1735 | ||
1736 | /* Now we know how deep things are, we can work out their addresses */ | |
1737 | ||
cd4bffcf | 1738 | for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++) |
c906108c SS |
1739 | { |
1740 | if (where[rn] >= 0) | |
1741 | { | |
0ba6dca9 | 1742 | if (rn == DEPRECATED_FP_REGNUM) |
c906108c SS |
1743 | have_fp = 1; |
1744 | ||
1e2330ba | 1745 | get_frame_saved_regs (fi)[rn] = get_frame_base (fi) - where[rn] + depth - 4; |
c906108c SS |
1746 | } |
1747 | else | |
1748 | { | |
b2fb4676 | 1749 | get_frame_saved_regs (fi)[rn] = 0; |
c906108c SS |
1750 | } |
1751 | } | |
1752 | ||
1753 | if (have_fp) | |
1754 | { | |
b2fb4676 | 1755 | get_frame_saved_regs (fi)[SP_REGNUM] = |
0ba6dca9 | 1756 | read_memory_integer (get_frame_saved_regs (fi)[DEPRECATED_FP_REGNUM], 4); |
c906108c SS |
1757 | } |
1758 | else | |
1759 | { | |
1e2330ba | 1760 | get_frame_saved_regs (fi)[SP_REGNUM] = get_frame_base (fi) - 4; |
c906108c SS |
1761 | } |
1762 | ||
0ba6dca9 | 1763 | get_frame_extra_info (fi)->f_offset = depth - where[DEPRECATED_FP_REGNUM] - 4; |
c906108c SS |
1764 | /* Work out the return pc - either from the saved pr or the pr |
1765 | value */ | |
1766 | } | |
1767 | ||
cc17453a EZ |
1768 | /* Initialize the extra info saved in a FRAME */ |
1769 | static void | |
fba45db2 | 1770 | sh_init_extra_frame_info (int fromleaf, struct frame_info *fi) |
c906108c | 1771 | { |
cc17453a | 1772 | |
a00a19e9 | 1773 | frame_extra_info_zalloc (fi, sizeof (struct frame_extra_info)); |
c906108c | 1774 | |
11c02a10 | 1775 | if (get_next_frame (fi)) |
8bedc050 | 1776 | deprecated_update_frame_pc_hack (fi, DEPRECATED_FRAME_SAVED_PC (get_next_frame (fi))); |
c906108c | 1777 | |
1e2330ba AC |
1778 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), get_frame_base (fi), |
1779 | get_frame_base (fi))) | |
c906108c | 1780 | { |
04714b91 AC |
1781 | /* We need to setup fi->frame here because call_function_by_hand |
1782 | gets it wrong by assuming it's always FP. */ | |
1e2330ba | 1783 | deprecated_update_frame_base_hack (fi, deprecated_read_register_dummy (get_frame_pc (fi), get_frame_base (fi), |
8ccd593b | 1784 | SP_REGNUM)); |
da50a4b7 | 1785 | get_frame_extra_info (fi)->return_pc = deprecated_read_register_dummy (get_frame_pc (fi), |
1e2330ba | 1786 | get_frame_base (fi), |
135c175f | 1787 | PC_REGNUM); |
b1e29e33 | 1788 | get_frame_extra_info (fi)->f_offset = -(DEPRECATED_CALL_DUMMY_LENGTH + 4); |
da50a4b7 | 1789 | get_frame_extra_info (fi)->leaf_function = 0; |
c906108c SS |
1790 | return; |
1791 | } | |
1792 | else | |
1793 | { | |
f30ee0bc | 1794 | DEPRECATED_FRAME_INIT_SAVED_REGS (fi); |
da50a4b7 | 1795 | get_frame_extra_info (fi)->return_pc = |
cd4bffcf | 1796 | sh_find_callers_reg (fi, gdbarch_tdep (current_gdbarch)->PR_REGNUM); |
c906108c SS |
1797 | } |
1798 | } | |
1799 | ||
283150cd EZ |
1800 | static void |
1801 | sh64_init_extra_frame_info (int fromleaf, struct frame_info *fi) | |
1802 | { | |
50abf9e5 | 1803 | int media_mode = pc_is_isa32 (get_frame_pc (fi)); |
283150cd | 1804 | |
a00a19e9 | 1805 | frame_extra_info_zalloc (fi, sizeof (struct frame_extra_info)); |
283150cd | 1806 | |
11c02a10 | 1807 | if (get_next_frame (fi)) |
8bedc050 | 1808 | deprecated_update_frame_pc_hack (fi, DEPRECATED_FRAME_SAVED_PC (get_next_frame (fi))); |
283150cd | 1809 | |
1e2330ba AC |
1810 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), get_frame_base (fi), |
1811 | get_frame_base (fi))) | |
283150cd | 1812 | { |
04714b91 AC |
1813 | /* We need to setup fi->frame here because call_function_by_hand |
1814 | gets it wrong by assuming it's always FP. */ | |
1e2330ba | 1815 | deprecated_update_frame_base_hack (fi, deprecated_read_register_dummy (get_frame_pc (fi), get_frame_base (fi), SP_REGNUM)); |
da50a4b7 | 1816 | get_frame_extra_info (fi)->return_pc = |
1e2330ba AC |
1817 | deprecated_read_register_dummy (get_frame_pc (fi), |
1818 | get_frame_base (fi), PC_REGNUM); | |
b1e29e33 | 1819 | get_frame_extra_info (fi)->f_offset = -(DEPRECATED_CALL_DUMMY_LENGTH + 4); |
da50a4b7 | 1820 | get_frame_extra_info (fi)->leaf_function = 0; |
283150cd EZ |
1821 | return; |
1822 | } | |
1823 | else | |
1824 | { | |
f30ee0bc | 1825 | DEPRECATED_FRAME_INIT_SAVED_REGS (fi); |
da50a4b7 | 1826 | get_frame_extra_info (fi)->return_pc = |
283150cd EZ |
1827 | sh64_get_saved_pr (fi, gdbarch_tdep (current_gdbarch)->PR_REGNUM); |
1828 | } | |
1829 | } | |
1830 | ||
a78f21af | 1831 | static void |
283150cd EZ |
1832 | sh64_get_saved_register (char *raw_buffer, int *optimized, CORE_ADDR *addrp, |
1833 | struct frame_info *frame, int regnum, | |
1834 | enum lval_type *lval) | |
1835 | { | |
1836 | int media_mode; | |
1837 | int live_regnum = regnum; | |
1838 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
1839 | ||
1840 | if (!target_has_registers) | |
1841 | error ("No registers."); | |
1842 | ||
1843 | /* Normal systems don't optimize out things with register numbers. */ | |
1844 | if (optimized != NULL) | |
1845 | *optimized = 0; | |
1846 | ||
1847 | if (addrp) /* default assumption: not found in memory */ | |
1848 | *addrp = 0; | |
1849 | ||
1850 | if (raw_buffer) | |
1851 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
1852 | ||
1853 | /* We must do this here, before the following while loop changes | |
1854 | frame, and makes it NULL. If this is a media register number, | |
1855 | but we are in compact mode, it will become the corresponding | |
1856 | compact pseudo register. If there is no corresponding compact | |
1857 | pseudo-register what do we do?*/ | |
50abf9e5 | 1858 | media_mode = pc_is_isa32 (get_frame_pc (frame)); |
283150cd EZ |
1859 | live_regnum = translate_insn_rn (regnum, media_mode); |
1860 | ||
1861 | /* Note: since the current frame's registers could only have been | |
1862 | saved by frames INTERIOR TO the current frame, we skip examining | |
1863 | the current frame itself: otherwise, we would be getting the | |
1864 | previous frame's registers which were saved by the current frame. */ | |
1865 | ||
11c02a10 | 1866 | while (frame && ((frame = get_next_frame (frame)) != NULL)) |
283150cd | 1867 | { |
1e2330ba AC |
1868 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), |
1869 | get_frame_base (frame), | |
1870 | get_frame_base (frame))) | |
283150cd EZ |
1871 | { |
1872 | if (lval) /* found it in a CALL_DUMMY frame */ | |
1873 | *lval = not_lval; | |
1874 | if (raw_buffer) | |
1875 | memcpy (raw_buffer, | |
1e2330ba | 1876 | (deprecated_generic_find_dummy_frame (get_frame_pc (frame), get_frame_base (frame)) |
da130f98 | 1877 | + REGISTER_BYTE (regnum)), |
283150cd EZ |
1878 | REGISTER_RAW_SIZE (regnum)); |
1879 | return; | |
1880 | } | |
1881 | ||
f30ee0bc | 1882 | DEPRECATED_FRAME_INIT_SAVED_REGS (frame); |
b2fb4676 AC |
1883 | if (get_frame_saved_regs (frame) != NULL |
1884 | && get_frame_saved_regs (frame)[regnum] != 0) | |
283150cd EZ |
1885 | { |
1886 | if (lval) /* found it saved on the stack */ | |
1887 | *lval = lval_memory; | |
1888 | if (regnum == SP_REGNUM) | |
1889 | { | |
1890 | if (raw_buffer) /* SP register treated specially */ | |
fbd9dcd3 AC |
1891 | store_unsigned_integer (raw_buffer, REGISTER_RAW_SIZE (regnum), |
1892 | get_frame_saved_regs (frame)[regnum]); | |
283150cd EZ |
1893 | } |
1894 | else | |
1895 | { /* any other register */ | |
1896 | ||
1897 | if (addrp) | |
b2fb4676 | 1898 | *addrp = get_frame_saved_regs (frame)[regnum]; |
283150cd EZ |
1899 | if (raw_buffer) |
1900 | { | |
1901 | int size; | |
1902 | if (tdep->sh_abi == SH_ABI_32 | |
0ba6dca9 | 1903 | && (live_regnum == DEPRECATED_FP_REGNUM |
283150cd EZ |
1904 | || live_regnum == tdep->PR_REGNUM)) |
1905 | size = 4; | |
1906 | else | |
1907 | size = REGISTER_RAW_SIZE (live_regnum); | |
1908 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) | |
b2fb4676 | 1909 | read_memory (get_frame_saved_regs (frame)[regnum], raw_buffer, size); |
283150cd | 1910 | else |
b2fb4676 | 1911 | read_memory (get_frame_saved_regs (frame)[regnum], |
283150cd EZ |
1912 | raw_buffer |
1913 | + REGISTER_RAW_SIZE (live_regnum) | |
1914 | - size, | |
1915 | size); | |
1916 | } | |
1917 | } | |
1918 | return; | |
1919 | } | |
1920 | } | |
1921 | ||
1922 | /* If we get thru the loop to this point, it means the register was | |
1923 | not saved in any frame. Return the actual live-register value. */ | |
1924 | ||
1925 | if (lval) /* found it in a live register */ | |
1926 | *lval = lval_register; | |
1927 | if (addrp) | |
1928 | *addrp = REGISTER_BYTE (live_regnum); | |
1929 | if (raw_buffer) | |
4caf0990 | 1930 | deprecated_read_register_gen (live_regnum, raw_buffer); |
283150cd EZ |
1931 | } |
1932 | ||
cc17453a EZ |
1933 | /* Extract from an array REGBUF containing the (raw) register state |
1934 | the address in which a function should return its structure value, | |
1935 | as a CORE_ADDR (or an expression that can be used as one). */ | |
b3df3fff | 1936 | static CORE_ADDR |
48db5a3c | 1937 | sh_extract_struct_value_address (struct regcache *regcache) |
cc17453a | 1938 | { |
48db5a3c CV |
1939 | ULONGEST addr; |
1940 | /*FIXME: Is R0 really correct here? Not STRUCT_RETURN_REGNUM? */ | |
1941 | regcache_cooked_read_unsigned (regcache, STRUCT_RETURN_REGNUM, &addr); | |
1942 | return addr; | |
cc17453a EZ |
1943 | } |
1944 | ||
283150cd EZ |
1945 | static CORE_ADDR |
1946 | sh64_extract_struct_value_address (char *regbuf) | |
1947 | { | |
7c0b4a20 AC |
1948 | return (extract_unsigned_integer ((regbuf + REGISTER_BYTE (STRUCT_RETURN_REGNUM)), |
1949 | REGISTER_RAW_SIZE (STRUCT_RETURN_REGNUM))); | |
283150cd EZ |
1950 | } |
1951 | ||
cc17453a | 1952 | static CORE_ADDR |
fba45db2 | 1953 | sh_frame_saved_pc (struct frame_info *frame) |
cc17453a | 1954 | { |
da50a4b7 | 1955 | return (get_frame_extra_info (frame)->return_pc); |
cc17453a EZ |
1956 | } |
1957 | ||
c906108c SS |
1958 | /* Discard from the stack the innermost frame, |
1959 | restoring all saved registers. */ | |
cc17453a | 1960 | static void |
fba45db2 | 1961 | sh_pop_frame (void) |
c906108c SS |
1962 | { |
1963 | register struct frame_info *frame = get_current_frame (); | |
1964 | register CORE_ADDR fp; | |
1965 | register int regnum; | |
c906108c | 1966 | |
1e2330ba AC |
1967 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), |
1968 | get_frame_base (frame), | |
1969 | get_frame_base (frame))) | |
c906108c SS |
1970 | generic_pop_dummy_frame (); |
1971 | else | |
c5aa993b | 1972 | { |
c193f6ac | 1973 | fp = get_frame_base (frame); |
f30ee0bc | 1974 | DEPRECATED_FRAME_INIT_SAVED_REGS (frame); |
c906108c | 1975 | |
c5aa993b | 1976 | /* Copy regs from where they were saved in the frame */ |
cd4bffcf | 1977 | for (regnum = 0; regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++) |
b2fb4676 | 1978 | if (get_frame_saved_regs (frame)[regnum]) |
cd4bffcf | 1979 | write_register (regnum, |
b2fb4676 | 1980 | read_memory_integer (get_frame_saved_regs (frame)[regnum], 4)); |
c906108c | 1981 | |
da50a4b7 | 1982 | write_register (PC_REGNUM, get_frame_extra_info (frame)->return_pc); |
c5aa993b JM |
1983 | write_register (SP_REGNUM, fp + 4); |
1984 | } | |
c906108c SS |
1985 | flush_cached_frames (); |
1986 | } | |
1987 | ||
283150cd EZ |
1988 | /* Used in the 'return' command. */ |
1989 | static void | |
1990 | sh64_pop_frame (void) | |
1991 | { | |
1992 | register struct frame_info *frame = get_current_frame (); | |
1993 | register CORE_ADDR fp; | |
1994 | register int regnum; | |
1995 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
1996 | ||
50abf9e5 | 1997 | int media_mode = pc_is_isa32 (get_frame_pc (frame)); |
283150cd | 1998 | |
1e2330ba AC |
1999 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), |
2000 | get_frame_base (frame), | |
2001 | get_frame_base (frame))) | |
283150cd EZ |
2002 | generic_pop_dummy_frame (); |
2003 | else | |
2004 | { | |
c193f6ac | 2005 | fp = get_frame_base (frame); |
f30ee0bc | 2006 | DEPRECATED_FRAME_INIT_SAVED_REGS (frame); |
283150cd EZ |
2007 | |
2008 | /* Copy regs from where they were saved in the frame */ | |
2009 | for (regnum = 0; regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++) | |
b2fb4676 | 2010 | if (get_frame_saved_regs (frame)[regnum]) |
283150cd EZ |
2011 | { |
2012 | int size; | |
2013 | if (tdep->sh_abi == SH_ABI_32 | |
0ba6dca9 | 2014 | && (regnum == DEPRECATED_FP_REGNUM |
283150cd EZ |
2015 | || regnum == tdep->PR_REGNUM)) |
2016 | size = 4; | |
2017 | else | |
2018 | size = REGISTER_RAW_SIZE (translate_insn_rn (regnum, | |
2019 | media_mode)); | |
2020 | write_register (regnum, | |
b2fb4676 | 2021 | read_memory_integer (get_frame_saved_regs (frame)[regnum], |
283150cd EZ |
2022 | size)); |
2023 | } | |
2024 | ||
da50a4b7 | 2025 | write_register (PC_REGNUM, get_frame_extra_info (frame)->return_pc); |
283150cd EZ |
2026 | write_register (SP_REGNUM, fp + 8); |
2027 | } | |
2028 | flush_cached_frames (); | |
2029 | } | |
2030 | ||
19f59343 MS |
2031 | static CORE_ADDR |
2032 | sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp) | |
2033 | { | |
2034 | return sp & ~3; | |
2035 | } | |
2036 | ||
6df2bf50 | 2037 | /* Function: sh_push_dummy_call (formerly push_arguments) |
c906108c SS |
2038 | Setup the function arguments for calling a function in the inferior. |
2039 | ||
2040 | On the Hitachi SH architecture, there are four registers (R4 to R7) | |
2041 | which are dedicated for passing function arguments. Up to the first | |
2042 | four arguments (depending on size) may go into these registers. | |
2043 | The rest go on the stack. | |
2044 | ||
6df2bf50 MS |
2045 | MVS: Except on SH variants that have floating point registers. |
2046 | In that case, float and double arguments are passed in the same | |
2047 | manner, but using FP registers instead of GP registers. | |
2048 | ||
c906108c SS |
2049 | Arguments that are smaller than 4 bytes will still take up a whole |
2050 | register or a whole 32-bit word on the stack, and will be | |
2051 | right-justified in the register or the stack word. This includes | |
2052 | chars, shorts, and small aggregate types. | |
2053 | ||
2054 | Arguments that are larger than 4 bytes may be split between two or | |
2055 | more registers. If there are not enough registers free, an argument | |
2056 | may be passed partly in a register (or registers), and partly on the | |
2057 | stack. This includes doubles, long longs, and larger aggregates. | |
2058 | As far as I know, there is no upper limit to the size of aggregates | |
2059 | that will be passed in this way; in other words, the convention of | |
2060 | passing a pointer to a large aggregate instead of a copy is not used. | |
2061 | ||
6df2bf50 MS |
2062 | MVS: The above appears to be true for the SH variants that do not |
2063 | have an FPU, however those that have an FPU appear to copy the | |
2064 | aggregate argument onto the stack (and not place it in registers) | |
2065 | if it is larger than 16 bytes (four GP registers). | |
2066 | ||
c906108c SS |
2067 | An exceptional case exists for struct arguments (and possibly other |
2068 | aggregates such as arrays) if the size is larger than 4 bytes but | |
2069 | not a multiple of 4 bytes. In this case the argument is never split | |
2070 | between the registers and the stack, but instead is copied in its | |
2071 | entirety onto the stack, AND also copied into as many registers as | |
2072 | there is room for. In other words, space in registers permitting, | |
2073 | two copies of the same argument are passed in. As far as I can tell, | |
2074 | only the one on the stack is used, although that may be a function | |
2075 | of the level of compiler optimization. I suspect this is a compiler | |
2076 | bug. Arguments of these odd sizes are left-justified within the | |
2077 | word (as opposed to arguments smaller than 4 bytes, which are | |
2078 | right-justified). | |
c5aa993b | 2079 | |
c906108c SS |
2080 | If the function is to return an aggregate type such as a struct, it |
2081 | is either returned in the normal return value register R0 (if its | |
2082 | size is no greater than one byte), or else the caller must allocate | |
2083 | space into which the callee will copy the return value (if the size | |
2084 | is greater than one byte). In this case, a pointer to the return | |
2085 | value location is passed into the callee in register R2, which does | |
2086 | not displace any of the other arguments passed in via registers R4 | |
2087 | to R7. */ | |
2088 | ||
cc17453a | 2089 | static CORE_ADDR |
6df2bf50 MS |
2090 | sh_push_dummy_call_fpu (struct gdbarch *gdbarch, |
2091 | CORE_ADDR func_addr, | |
2092 | struct regcache *regcache, | |
2093 | CORE_ADDR bp_addr, int nargs, | |
2094 | struct value **args, | |
2095 | CORE_ADDR sp, int struct_return, | |
2096 | CORE_ADDR struct_addr) | |
2097 | { | |
2098 | int stack_offset, stack_alloc; | |
2099 | int argreg, flt_argreg; | |
2100 | int argnum; | |
2101 | struct type *type; | |
2102 | CORE_ADDR regval; | |
2103 | char *val; | |
2104 | char valbuf[4]; | |
2105 | int len; | |
2106 | int odd_sized_struct; | |
2107 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2108 | ||
2109 | /* first force sp to a 4-byte alignment */ | |
2110 | sp = sh_frame_align (gdbarch, sp); | |
2111 | ||
2112 | /* The "struct return pointer" pseudo-argument has its own dedicated | |
2113 | register */ | |
2114 | if (struct_return) | |
2115 | regcache_cooked_write_unsigned (regcache, | |
2116 | STRUCT_RETURN_REGNUM, | |
2117 | struct_addr); | |
2118 | ||
2119 | /* Now make sure there's space on the stack */ | |
2120 | for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++) | |
2121 | stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 3) & ~3); | |
2122 | sp -= stack_alloc; /* make room on stack for args */ | |
2123 | ||
2124 | /* Now load as many as possible of the first arguments into | |
2125 | registers, and push the rest onto the stack. There are 16 bytes | |
2126 | in four registers available. Loop thru args from first to last. */ | |
2127 | ||
2128 | argreg = tdep->ARG0_REGNUM; | |
2129 | flt_argreg = tdep->FLOAT_ARG0_REGNUM; | |
2130 | for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++) | |
2131 | { | |
2132 | type = VALUE_TYPE (args[argnum]); | |
2133 | len = TYPE_LENGTH (type); | |
2134 | memset (valbuf, 0, sizeof (valbuf)); | |
2135 | if (len < 4) | |
2136 | { | |
2137 | /* value gets right-justified in the register or stack word */ | |
2138 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
2139 | memcpy (valbuf + (4 - len), | |
2140 | (char *) VALUE_CONTENTS (args[argnum]), len); | |
2141 | else | |
2142 | memcpy (valbuf, (char *) VALUE_CONTENTS (args[argnum]), len); | |
2143 | val = valbuf; | |
2144 | } | |
2145 | else | |
2146 | val = (char *) VALUE_CONTENTS (args[argnum]); | |
48db5a3c | 2147 | |
6df2bf50 MS |
2148 | if (len > 4 && (len & 3) != 0) |
2149 | odd_sized_struct = 1; /* Such structs go entirely on stack. */ | |
2150 | else if (len > 16) | |
2151 | odd_sized_struct = 1; /* So do aggregates bigger than 4 words. */ | |
2152 | else | |
2153 | odd_sized_struct = 0; | |
2154 | while (len > 0) | |
2155 | { | |
2156 | if ((TYPE_CODE (type) == TYPE_CODE_FLT | |
2157 | && flt_argreg > tdep->FLOAT_ARGLAST_REGNUM) | |
2158 | || argreg > tdep->ARGLAST_REGNUM | |
2159 | || odd_sized_struct) | |
2160 | { | |
2161 | /* must go on the stack */ | |
2162 | write_memory (sp + stack_offset, val, 4); | |
2163 | stack_offset += 4; | |
2164 | } | |
2165 | /* NOTE WELL!!!!! This is not an "else if" clause!!! | |
2166 | That's because some *&^%$ things get passed on the stack | |
2167 | AND in the registers! */ | |
2168 | if (TYPE_CODE (type) == TYPE_CODE_FLT && | |
2169 | flt_argreg > 0 && flt_argreg <= tdep->FLOAT_ARGLAST_REGNUM) | |
2170 | { | |
2171 | /* Argument goes in a single-precision fp reg. */ | |
2172 | regval = extract_unsigned_integer (val, register_size (gdbarch, | |
2173 | argreg)); | |
2174 | regcache_cooked_write_unsigned (regcache, flt_argreg++, regval); | |
2175 | } | |
2176 | else if (argreg <= tdep->ARGLAST_REGNUM) | |
2177 | { | |
2178 | /* there's room in a register */ | |
2179 | regval = extract_unsigned_integer (val, register_size (gdbarch, | |
2180 | argreg)); | |
2181 | regcache_cooked_write_unsigned (regcache, argreg++, regval); | |
2182 | } | |
2183 | /* Store the value 4 bytes at a time. This means that things | |
2184 | larger than 4 bytes may go partly in registers and partly | |
2185 | on the stack. */ | |
2186 | len -= register_size (gdbarch, argreg); | |
2187 | val += register_size (gdbarch, argreg); | |
2188 | } | |
2189 | } | |
2190 | ||
2191 | /* Store return address. */ | |
2192 | regcache_cooked_write_unsigned (regcache, tdep->PR_REGNUM, bp_addr); | |
2193 | ||
2194 | /* Update stack pointer. */ | |
2195 | regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp); | |
2196 | ||
2197 | return sp; | |
2198 | } | |
2199 | ||
2200 | static CORE_ADDR | |
2201 | sh_push_dummy_call_nofpu (struct gdbarch *gdbarch, | |
2202 | CORE_ADDR func_addr, | |
2203 | struct regcache *regcache, | |
2204 | CORE_ADDR bp_addr, | |
2205 | int nargs, struct value **args, | |
2206 | CORE_ADDR sp, int struct_return, | |
2207 | CORE_ADDR struct_addr) | |
c906108c SS |
2208 | { |
2209 | int stack_offset, stack_alloc; | |
2210 | int argreg; | |
2211 | int argnum; | |
2212 | struct type *type; | |
2213 | CORE_ADDR regval; | |
2214 | char *val; | |
2215 | char valbuf[4]; | |
2216 | int len; | |
2217 | int odd_sized_struct; | |
48db5a3c | 2218 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
c906108c SS |
2219 | |
2220 | /* first force sp to a 4-byte alignment */ | |
19f59343 | 2221 | sp = sh_frame_align (gdbarch, sp); |
c906108c SS |
2222 | |
2223 | /* The "struct return pointer" pseudo-argument has its own dedicated | |
2224 | register */ | |
2225 | if (struct_return) | |
6df2bf50 MS |
2226 | regcache_cooked_write_unsigned (regcache, |
2227 | STRUCT_RETURN_REGNUM, | |
2228 | struct_addr); | |
c906108c SS |
2229 | |
2230 | /* Now make sure there's space on the stack */ | |
cc17453a | 2231 | for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++) |
c5aa993b JM |
2232 | stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 3) & ~3); |
2233 | sp -= stack_alloc; /* make room on stack for args */ | |
c906108c | 2234 | |
c906108c SS |
2235 | /* Now load as many as possible of the first arguments into |
2236 | registers, and push the rest onto the stack. There are 16 bytes | |
2237 | in four registers available. Loop thru args from first to last. */ | |
2238 | ||
f81353e4 | 2239 | argreg = tdep->ARG0_REGNUM; |
c906108c SS |
2240 | for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++) |
2241 | { | |
2242 | type = VALUE_TYPE (args[argnum]); | |
c5aa993b JM |
2243 | len = TYPE_LENGTH (type); |
2244 | memset (valbuf, 0, sizeof (valbuf)); | |
c906108c | 2245 | if (len < 4) |
cc17453a EZ |
2246 | { |
2247 | /* value gets right-justified in the register or stack word */ | |
7079c36c CV |
2248 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
2249 | memcpy (valbuf + (4 - len), | |
2250 | (char *) VALUE_CONTENTS (args[argnum]), len); | |
2251 | else | |
2252 | memcpy (valbuf, (char *) VALUE_CONTENTS (args[argnum]), len); | |
c5aa993b JM |
2253 | val = valbuf; |
2254 | } | |
c906108c | 2255 | else |
c5aa993b | 2256 | val = (char *) VALUE_CONTENTS (args[argnum]); |
c906108c SS |
2257 | |
2258 | if (len > 4 && (len & 3) != 0) | |
c5aa993b JM |
2259 | odd_sized_struct = 1; /* such structs go entirely on stack */ |
2260 | else | |
c906108c SS |
2261 | odd_sized_struct = 0; |
2262 | while (len > 0) | |
2263 | { | |
f81353e4 | 2264 | if (argreg > tdep->ARGLAST_REGNUM |
3bbfbb92 EZ |
2265 | || odd_sized_struct) |
2266 | { | |
2267 | /* must go on the stack */ | |
c906108c SS |
2268 | write_memory (sp + stack_offset, val, 4); |
2269 | stack_offset += 4; | |
2270 | } | |
2271 | /* NOTE WELL!!!!! This is not an "else if" clause!!! | |
2272 | That's because some *&^%$ things get passed on the stack | |
2273 | AND in the registers! */ | |
f81353e4 | 2274 | if (argreg <= tdep->ARGLAST_REGNUM) |
3bbfbb92 EZ |
2275 | { |
2276 | /* there's room in a register */ | |
48db5a3c CV |
2277 | regval = extract_unsigned_integer (val, register_size (gdbarch, |
2278 | argreg)); | |
2279 | regcache_cooked_write_unsigned (regcache, argreg++, regval); | |
c906108c SS |
2280 | } |
2281 | /* Store the value 4 bytes at a time. This means that things | |
2282 | larger than 4 bytes may go partly in registers and partly | |
2283 | on the stack. */ | |
48db5a3c CV |
2284 | len -= register_size (gdbarch, argreg); |
2285 | val += register_size (gdbarch, argreg); | |
c906108c SS |
2286 | } |
2287 | } | |
48db5a3c CV |
2288 | |
2289 | /* Store return address. */ | |
2290 | regcache_cooked_write_unsigned (regcache, tdep->PR_REGNUM, bp_addr); | |
2291 | ||
2292 | /* Update stack pointer. */ | |
2293 | regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp); | |
2294 | ||
c906108c SS |
2295 | return sp; |
2296 | } | |
2297 | ||
283150cd EZ |
2298 | /* R2-R9 for integer types and integer equivalent (char, pointers) and |
2299 | non-scalar (struct, union) elements (even if the elements are | |
2300 | floats). | |
2301 | FR0-FR11 for single precision floating point (float) | |
2302 | DR0-DR10 for double precision floating point (double) | |
2303 | ||
2304 | If a float is argument number 3 (for instance) and arguments number | |
2305 | 1,2, and 4 are integer, the mapping will be: | |
2306 | arg1 -->R2, arg2 --> R3, arg3 -->FR0, arg4 --> R5. I.e. R4 is not used. | |
2307 | ||
2308 | If a float is argument number 10 (for instance) and arguments number | |
2309 | 1 through 10 are integer, the mapping will be: | |
2310 | arg1->R2, arg2->R3, arg3->R4, arg4->R5, arg5->R6, arg6->R7, arg7->R8, | |
2311 | arg8->R9, arg9->(0,SP)stack(8-byte aligned), arg10->FR0, arg11->stack(16,SP). | |
2312 | I.e. there is hole in the stack. | |
2313 | ||
2314 | Different rules apply for variable arguments functions, and for functions | |
2315 | for which the prototype is not known. */ | |
2316 | ||
2317 | static CORE_ADDR | |
2318 | sh64_push_arguments (int nargs, struct value **args, CORE_ADDR sp, | |
2319 | int struct_return, CORE_ADDR struct_addr) | |
2320 | { | |
2321 | int stack_offset, stack_alloc; | |
2322 | int int_argreg; | |
2323 | int float_argreg; | |
2324 | int double_argreg; | |
2325 | int float_arg_index = 0; | |
2326 | int double_arg_index = 0; | |
2327 | int argnum; | |
2328 | struct type *type; | |
2329 | CORE_ADDR regval; | |
2330 | char *val; | |
2331 | char valbuf[8]; | |
2332 | char valbuf_tmp[8]; | |
2333 | int len; | |
2334 | int argreg_size; | |
2335 | int fp_args[12]; | |
2336 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2337 | ||
2338 | memset (fp_args, 0, sizeof (fp_args)); | |
2339 | ||
2340 | /* first force sp to a 8-byte alignment */ | |
2341 | sp = sp & ~7; | |
2342 | ||
2343 | /* The "struct return pointer" pseudo-argument has its own dedicated | |
2344 | register */ | |
2345 | ||
2346 | if (struct_return) | |
2347 | write_register (STRUCT_RETURN_REGNUM, struct_addr); | |
2348 | ||
2349 | /* Now make sure there's space on the stack */ | |
2350 | for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++) | |
2351 | stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 7) & ~7); | |
2352 | sp -= stack_alloc; /* make room on stack for args */ | |
2353 | ||
2354 | /* Now load as many as possible of the first arguments into | |
2355 | registers, and push the rest onto the stack. There are 64 bytes | |
2356 | in eight registers available. Loop thru args from first to last. */ | |
2357 | ||
2358 | int_argreg = tdep->ARG0_REGNUM; | |
2359 | float_argreg = FP0_REGNUM; | |
2360 | double_argreg = tdep->DR0_REGNUM; | |
2361 | ||
2362 | for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++) | |
2363 | { | |
2364 | type = VALUE_TYPE (args[argnum]); | |
2365 | len = TYPE_LENGTH (type); | |
2366 | memset (valbuf, 0, sizeof (valbuf)); | |
2367 | ||
2368 | if (TYPE_CODE (type) != TYPE_CODE_FLT) | |
2369 | { | |
2370 | argreg_size = REGISTER_RAW_SIZE (int_argreg); | |
2371 | ||
2372 | if (len < argreg_size) | |
2373 | { | |
2374 | /* value gets right-justified in the register or stack word */ | |
2375 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
2376 | memcpy (valbuf + argreg_size - len, | |
2377 | (char *) VALUE_CONTENTS (args[argnum]), len); | |
2378 | else | |
2379 | memcpy (valbuf, (char *) VALUE_CONTENTS (args[argnum]), len); | |
2380 | ||
2381 | val = valbuf; | |
2382 | } | |
2383 | else | |
2384 | val = (char *) VALUE_CONTENTS (args[argnum]); | |
2385 | ||
2386 | while (len > 0) | |
2387 | { | |
2388 | if (int_argreg > tdep->ARGLAST_REGNUM) | |
2389 | { | |
2390 | /* must go on the stack */ | |
2391 | write_memory (sp + stack_offset, val, argreg_size); | |
2392 | stack_offset += 8;/*argreg_size;*/ | |
2393 | } | |
2394 | /* NOTE WELL!!!!! This is not an "else if" clause!!! | |
2395 | That's because some *&^%$ things get passed on the stack | |
2396 | AND in the registers! */ | |
2397 | if (int_argreg <= tdep->ARGLAST_REGNUM) | |
2398 | { | |
2399 | /* there's room in a register */ | |
7c0b4a20 | 2400 | regval = extract_unsigned_integer (val, argreg_size); |
283150cd EZ |
2401 | write_register (int_argreg, regval); |
2402 | } | |
2403 | /* Store the value 8 bytes at a time. This means that | |
2404 | things larger than 8 bytes may go partly in registers | |
2405 | and partly on the stack. FIXME: argreg is incremented | |
2406 | before we use its size. */ | |
2407 | len -= argreg_size; | |
2408 | val += argreg_size; | |
2409 | int_argreg++; | |
2410 | } | |
2411 | } | |
2412 | else | |
2413 | { | |
2414 | val = (char *) VALUE_CONTENTS (args[argnum]); | |
2415 | if (len == 4) | |
2416 | { | |
2417 | /* Where is it going to be stored? */ | |
2418 | while (fp_args[float_arg_index]) | |
2419 | float_arg_index ++; | |
2420 | ||
2421 | /* Now float_argreg points to the register where it | |
2422 | should be stored. Are we still within the allowed | |
2423 | register set? */ | |
2424 | if (float_arg_index <= tdep->FLOAT_ARGLAST_REGNUM) | |
2425 | { | |
2426 | /* Goes in FR0...FR11 */ | |
4caf0990 AC |
2427 | deprecated_write_register_gen (FP0_REGNUM + float_arg_index, |
2428 | val); | |
283150cd EZ |
2429 | fp_args[float_arg_index] = 1; |
2430 | /* Skip the corresponding general argument register. */ | |
2431 | int_argreg ++; | |
2432 | } | |
2433 | else | |
2434 | ; | |
2435 | /* Store it as the integers, 8 bytes at the time, if | |
2436 | necessary spilling on the stack. */ | |
2437 | ||
2438 | } | |
2439 | else if (len == 8) | |
2440 | { | |
2441 | /* Where is it going to be stored? */ | |
2442 | while (fp_args[double_arg_index]) | |
2443 | double_arg_index += 2; | |
2444 | /* Now double_argreg points to the register | |
2445 | where it should be stored. | |
2446 | Are we still within the allowed register set? */ | |
2447 | if (double_arg_index < tdep->FLOAT_ARGLAST_REGNUM) | |
2448 | { | |
2449 | /* Goes in DR0...DR10 */ | |
2450 | /* The numbering of the DRi registers is consecutive, | |
2451 | i.e. includes odd numbers. */ | |
2452 | int double_register_offset = double_arg_index / 2; | |
2453 | int regnum = tdep->DR0_REGNUM + | |
2454 | double_register_offset; | |
2455 | #if 0 | |
2456 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) | |
2457 | { | |
2458 | memset (valbuf_tmp, 0, sizeof (valbuf_tmp)); | |
781a750d AC |
2459 | DEPRECATED_REGISTER_CONVERT_TO_VIRTUAL (regnum, |
2460 | type, val, | |
2461 | valbuf_tmp); | |
283150cd EZ |
2462 | val = valbuf_tmp; |
2463 | } | |
2464 | #endif | |
2465 | /* Note: must use write_register_gen here instead | |
0818c12a AC |
2466 | of regcache_raw_write, because |
2467 | regcache_raw_write works only for real | |
2468 | registers, not pseudo. write_register_gen will | |
2469 | call the gdbarch function to do register | |
2470 | writes, and that will properly know how to deal | |
2471 | with pseudoregs. */ | |
4caf0990 | 2472 | deprecated_write_register_gen (regnum, val); |
283150cd EZ |
2473 | fp_args[double_arg_index] = 1; |
2474 | fp_args[double_arg_index + 1] = 1; | |
2475 | /* Skip the corresponding general argument register. */ | |
2476 | int_argreg ++; | |
2477 | } | |
2478 | else | |
2479 | ; | |
2480 | /* Store it as the integers, 8 bytes at the time, if | |
2481 | necessary spilling on the stack. */ | |
2482 | } | |
2483 | } | |
2484 | } | |
2485 | return sp; | |
2486 | } | |
2487 | ||
c906108c SS |
2488 | /* Function: push_return_address (pc) |
2489 | Set up the return address for the inferior function call. | |
2490 | Needed for targets where we don't actually execute a JSR/BSR instruction */ | |
2491 | ||
cc17453a | 2492 | static CORE_ADDR |
48db5a3c | 2493 | sh64_push_return_address (CORE_ADDR pc, CORE_ADDR sp) |
c906108c | 2494 | { |
283150cd EZ |
2495 | write_register (gdbarch_tdep (current_gdbarch)->PR_REGNUM, |
2496 | CALL_DUMMY_ADDRESS ()); | |
c906108c SS |
2497 | return sp; |
2498 | } | |
2499 | ||
2500 | /* Function: fix_call_dummy | |
2501 | Poke the callee function's address into the destination part of | |
2502 | the CALL_DUMMY. The address is actually stored in a data word | |
2503 | following the actualy CALL_DUMMY instructions, which will load | |
2504 | it into a register using PC-relative addressing. This function | |
2505 | expects the CALL_DUMMY to look like this: | |
2506 | ||
c5aa993b JM |
2507 | mov.w @(2,PC), R8 |
2508 | jsr @R8 | |
2509 | nop | |
2510 | trap | |
2511 | <destination> | |
2512 | */ | |
c906108c SS |
2513 | |
2514 | #if 0 | |
2515 | void | |
fba45db2 | 2516 | sh_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, int nargs, |
ea7c478f | 2517 | struct value **args, struct type *type, int gcc_p) |
c906108c SS |
2518 | { |
2519 | *(unsigned long *) (dummy + 8) = fun; | |
2520 | } | |
2521 | #endif | |
2522 | ||
cc17453a EZ |
2523 | /* Find a function's return value in the appropriate registers (in |
2524 | regbuf), and copy it into valbuf. Extract from an array REGBUF | |
2525 | containing the (raw) register state a function return value of type | |
2526 | TYPE, and copy that, in virtual format, into VALBUF. */ | |
2527 | static void | |
48db5a3c CV |
2528 | sh_default_extract_return_value (struct type *type, struct regcache *regcache, |
2529 | void *valbuf) | |
c906108c | 2530 | { |
cc17453a | 2531 | int len = TYPE_LENGTH (type); |
3116c80a EZ |
2532 | int return_register = R0_REGNUM; |
2533 | int offset; | |
2534 | ||
cc17453a | 2535 | if (len <= 4) |
3116c80a | 2536 | { |
48db5a3c CV |
2537 | ULONGEST c; |
2538 | ||
2539 | regcache_cooked_read_unsigned (regcache, R0_REGNUM, &c); | |
2540 | store_unsigned_integer (valbuf, len, c); | |
3116c80a | 2541 | } |
48db5a3c | 2542 | else if (len == 8) |
3116c80a | 2543 | { |
48db5a3c CV |
2544 | int i, regnum = R0_REGNUM; |
2545 | for (i = 0; i < len; i += 4) | |
2546 | regcache_raw_read (regcache, regnum++, (char *)valbuf + i); | |
3116c80a EZ |
2547 | } |
2548 | else | |
2549 | error ("bad size for return value"); | |
2550 | } | |
2551 | ||
2552 | static void | |
48db5a3c CV |
2553 | sh3e_sh4_extract_return_value (struct type *type, struct regcache *regcache, |
2554 | void *valbuf) | |
3116c80a | 2555 | { |
3116c80a | 2556 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
3116c80a | 2557 | { |
48db5a3c CV |
2558 | int len = TYPE_LENGTH (type); |
2559 | int i, regnum = FP0_REGNUM; | |
2560 | for (i = 0; i < len; i += 4) | |
2561 | regcache_raw_read (regcache, regnum++, (char *)valbuf + i); | |
3116c80a | 2562 | } |
cc17453a | 2563 | else |
48db5a3c | 2564 | sh_default_extract_return_value (type, regcache, valbuf); |
cc17453a | 2565 | } |
c906108c | 2566 | |
283150cd EZ |
2567 | static void |
2568 | sh64_extract_return_value (struct type *type, char *regbuf, char *valbuf) | |
2569 | { | |
2570 | int offset; | |
2571 | int return_register; | |
2572 | int len = TYPE_LENGTH (type); | |
2573 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2574 | ||
2575 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
2576 | { | |
2577 | if (len == 4) | |
2578 | { | |
2579 | /* Return value stored in FP0_REGNUM */ | |
2580 | return_register = FP0_REGNUM; | |
2581 | offset = REGISTER_BYTE (return_register); | |
2582 | memcpy (valbuf, (char *) regbuf + offset, len); | |
2583 | } | |
2584 | else if (len == 8) | |
2585 | { | |
2586 | /* return value stored in DR0_REGNUM */ | |
2587 | DOUBLEST val; | |
2588 | ||
2589 | return_register = tdep->DR0_REGNUM; | |
2590 | offset = REGISTER_BYTE (return_register); | |
2591 | ||
2592 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) | |
2593 | floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, | |
2594 | (char *) regbuf + offset, &val); | |
2595 | else | |
2596 | floatformat_to_doublest (&floatformat_ieee_double_big, | |
2597 | (char *) regbuf + offset, &val); | |
f1908289 | 2598 | deprecated_store_floating (valbuf, len, val); |
283150cd EZ |
2599 | } |
2600 | } | |
2601 | else | |
2602 | { | |
2603 | if (len <= 8) | |
2604 | { | |
2605 | /* Result is in register 2. If smaller than 8 bytes, it is padded | |
2606 | at the most significant end. */ | |
2607 | return_register = tdep->RETURN_REGNUM; | |
2608 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
2609 | offset = REGISTER_BYTE (return_register) + | |
2610 | REGISTER_RAW_SIZE (return_register) - len; | |
2611 | else | |
2612 | offset = REGISTER_BYTE (return_register); | |
2613 | memcpy (valbuf, (char *) regbuf + offset, len); | |
2614 | } | |
2615 | else | |
2616 | error ("bad size for return value"); | |
2617 | } | |
2618 | } | |
2619 | ||
cc17453a EZ |
2620 | /* Write into appropriate registers a function return value |
2621 | of type TYPE, given in virtual format. | |
2622 | If the architecture is sh4 or sh3e, store a function's return value | |
2623 | in the R0 general register or in the FP0 floating point register, | |
2624 | depending on the type of the return value. In all the other cases | |
3bbfbb92 | 2625 | the result is stored in r0, left-justified. */ |
cc17453a | 2626 | static void |
48db5a3c CV |
2627 | sh_default_store_return_value (struct type *type, struct regcache *regcache, |
2628 | const void *valbuf) | |
cc17453a | 2629 | { |
48db5a3c CV |
2630 | ULONGEST val; |
2631 | int len = TYPE_LENGTH (type); | |
d19b71be | 2632 | |
48db5a3c | 2633 | if (len <= 4) |
d19b71be | 2634 | { |
48db5a3c CV |
2635 | val = extract_unsigned_integer (valbuf, len); |
2636 | regcache_cooked_write_unsigned (regcache, R0_REGNUM, val); | |
d19b71be MS |
2637 | } |
2638 | else | |
48db5a3c CV |
2639 | { |
2640 | int i, regnum = R0_REGNUM; | |
2641 | for (i = 0; i < len; i += 4) | |
2642 | regcache_raw_write (regcache, regnum++, (char *)valbuf + i); | |
2643 | } | |
cc17453a | 2644 | } |
c906108c | 2645 | |
cc17453a | 2646 | static void |
48db5a3c CV |
2647 | sh3e_sh4_store_return_value (struct type *type, struct regcache *regcache, |
2648 | const void *valbuf) | |
cc17453a EZ |
2649 | { |
2650 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
48db5a3c CV |
2651 | { |
2652 | int len = TYPE_LENGTH (type); | |
2653 | int i, regnum = FP0_REGNUM; | |
2654 | for (i = 0; i < len; i += 4) | |
2655 | regcache_raw_write (regcache, regnum++, (char *)valbuf + i); | |
2656 | } | |
cc17453a | 2657 | else |
48db5a3c | 2658 | sh_default_store_return_value (type, regcache, valbuf); |
c906108c SS |
2659 | } |
2660 | ||
283150cd EZ |
2661 | static void |
2662 | sh64_store_return_value (struct type *type, char *valbuf) | |
2663 | { | |
2664 | char buf[64]; /* more than enough... */ | |
2665 | int len = TYPE_LENGTH (type); | |
2666 | ||
2667 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
2668 | { | |
2669 | if (len == 4) | |
2670 | { | |
2671 | /* Return value stored in FP0_REGNUM */ | |
4caf0990 | 2672 | deprecated_write_register_gen (FP0_REGNUM, valbuf); |
283150cd EZ |
2673 | } |
2674 | if (len == 8) | |
2675 | { | |
2676 | /* return value stored in DR0_REGNUM */ | |
2677 | /* FIXME: Implement */ | |
2678 | } | |
2679 | } | |
2680 | else | |
2681 | { | |
2682 | int return_register = gdbarch_tdep (current_gdbarch)->RETURN_REGNUM; | |
2683 | int offset = 0; | |
2684 | ||
2685 | if (len <= REGISTER_RAW_SIZE (return_register)) | |
2686 | { | |
2687 | /* Pad with zeros. */ | |
2688 | memset (buf, 0, REGISTER_RAW_SIZE (return_register)); | |
2689 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) | |
2690 | offset = 0; /*REGISTER_RAW_SIZE (return_register) - len;*/ | |
2691 | else | |
2692 | offset = REGISTER_RAW_SIZE (return_register) - len; | |
2693 | ||
2694 | memcpy (buf + offset, valbuf, len); | |
4caf0990 | 2695 | deprecated_write_register_gen (return_register, buf); |
283150cd EZ |
2696 | } |
2697 | else | |
4caf0990 | 2698 | deprecated_write_register_gen (return_register, valbuf); |
283150cd EZ |
2699 | } |
2700 | } | |
2701 | ||
c906108c SS |
2702 | /* Print the registers in a form similar to the E7000 */ |
2703 | ||
2704 | static void | |
fba45db2 | 2705 | sh_generic_show_regs (void) |
c906108c | 2706 | { |
f81353e4 EZ |
2707 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2708 | ||
cc17453a EZ |
2709 | printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", |
2710 | paddr (read_register (PC_REGNUM)), | |
f81353e4 EZ |
2711 | (long) read_register (tdep->SR_REGNUM), |
2712 | (long) read_register (tdep->PR_REGNUM), | |
cc17453a EZ |
2713 | (long) read_register (MACH_REGNUM), |
2714 | (long) read_register (MACL_REGNUM)); | |
2715 | ||
2716 | printf_filtered ("GBR=%08lx VBR=%08lx", | |
2717 | (long) read_register (GBR_REGNUM), | |
2718 | (long) read_register (VBR_REGNUM)); | |
2719 | ||
2720 | printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
2721 | (long) read_register (0), | |
2722 | (long) read_register (1), | |
2723 | (long) read_register (2), | |
2724 | (long) read_register (3), | |
2725 | (long) read_register (4), | |
2726 | (long) read_register (5), | |
2727 | (long) read_register (6), | |
2728 | (long) read_register (7)); | |
2729 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
2730 | (long) read_register (8), | |
2731 | (long) read_register (9), | |
2732 | (long) read_register (10), | |
2733 | (long) read_register (11), | |
2734 | (long) read_register (12), | |
2735 | (long) read_register (13), | |
2736 | (long) read_register (14), | |
2737 | (long) read_register (15)); | |
2738 | } | |
c906108c | 2739 | |
cc17453a | 2740 | static void |
fba45db2 | 2741 | sh3_show_regs (void) |
cc17453a | 2742 | { |
f81353e4 EZ |
2743 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2744 | ||
d4f3574e SS |
2745 | printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", |
2746 | paddr (read_register (PC_REGNUM)), | |
f81353e4 EZ |
2747 | (long) read_register (tdep->SR_REGNUM), |
2748 | (long) read_register (tdep->PR_REGNUM), | |
d4f3574e SS |
2749 | (long) read_register (MACH_REGNUM), |
2750 | (long) read_register (MACL_REGNUM)); | |
2751 | ||
2752 | printf_filtered ("GBR=%08lx VBR=%08lx", | |
2753 | (long) read_register (GBR_REGNUM), | |
2754 | (long) read_register (VBR_REGNUM)); | |
cc17453a | 2755 | printf_filtered (" SSR=%08lx SPC=%08lx", |
f81353e4 EZ |
2756 | (long) read_register (tdep->SSR_REGNUM), |
2757 | (long) read_register (tdep->SPC_REGNUM)); | |
c906108c | 2758 | |
d4f3574e SS |
2759 | printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
2760 | (long) read_register (0), | |
2761 | (long) read_register (1), | |
2762 | (long) read_register (2), | |
2763 | (long) read_register (3), | |
2764 | (long) read_register (4), | |
2765 | (long) read_register (5), | |
2766 | (long) read_register (6), | |
2767 | (long) read_register (7)); | |
2768 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
2769 | (long) read_register (8), | |
2770 | (long) read_register (9), | |
2771 | (long) read_register (10), | |
2772 | (long) read_register (11), | |
2773 | (long) read_register (12), | |
2774 | (long) read_register (13), | |
2775 | (long) read_register (14), | |
2776 | (long) read_register (15)); | |
c906108c SS |
2777 | } |
2778 | ||
53116e27 | 2779 | |
2d188dd3 NC |
2780 | static void |
2781 | sh2e_show_regs (void) | |
2782 | { | |
2783 | printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", | |
2784 | paddr (read_register (PC_REGNUM)), | |
2785 | (long) read_register (SR_REGNUM), | |
2786 | (long) read_register (PR_REGNUM), | |
2787 | (long) read_register (MACH_REGNUM), | |
2788 | (long) read_register (MACL_REGNUM)); | |
2789 | ||
2790 | printf_filtered ("GBR=%08lx VBR=%08lx", | |
2791 | (long) read_register (GBR_REGNUM), | |
2792 | (long) read_register (VBR_REGNUM)); | |
2793 | printf_filtered (" FPUL=%08lx FPSCR=%08lx", | |
2794 | (long) read_register (gdbarch_tdep (current_gdbarch)->FPUL_REGNUM), | |
2795 | (long) read_register (gdbarch_tdep (current_gdbarch)->FPSCR_REGNUM)); | |
2796 | ||
2797 | printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
2798 | (long) read_register (0), | |
2799 | (long) read_register (1), | |
2800 | (long) read_register (2), | |
2801 | (long) read_register (3), | |
2802 | (long) read_register (4), | |
2803 | (long) read_register (5), | |
2804 | (long) read_register (6), | |
2805 | (long) read_register (7)); | |
2806 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
2807 | (long) read_register (8), | |
2808 | (long) read_register (9), | |
2809 | (long) read_register (10), | |
2810 | (long) read_register (11), | |
2811 | (long) read_register (12), | |
2812 | (long) read_register (13), | |
2813 | (long) read_register (14), | |
2814 | (long) read_register (15)); | |
2815 | ||
2816 | printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), | |
2817 | (long) read_register (FP0_REGNUM + 0), | |
2818 | (long) read_register (FP0_REGNUM + 1), | |
2819 | (long) read_register (FP0_REGNUM + 2), | |
2820 | (long) read_register (FP0_REGNUM + 3), | |
2821 | (long) read_register (FP0_REGNUM + 4), | |
2822 | (long) read_register (FP0_REGNUM + 5), | |
2823 | (long) read_register (FP0_REGNUM + 6), | |
2824 | (long) read_register (FP0_REGNUM + 7)); | |
2825 | printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), | |
2826 | (long) read_register (FP0_REGNUM + 8), | |
2827 | (long) read_register (FP0_REGNUM + 9), | |
2828 | (long) read_register (FP0_REGNUM + 10), | |
2829 | (long) read_register (FP0_REGNUM + 11), | |
2830 | (long) read_register (FP0_REGNUM + 12), | |
2831 | (long) read_register (FP0_REGNUM + 13), | |
2832 | (long) read_register (FP0_REGNUM + 14), | |
2833 | (long) read_register (FP0_REGNUM + 15)); | |
2834 | } | |
2835 | ||
cc17453a | 2836 | static void |
fba45db2 | 2837 | sh3e_show_regs (void) |
cc17453a | 2838 | { |
f81353e4 EZ |
2839 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2840 | ||
cc17453a EZ |
2841 | printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", |
2842 | paddr (read_register (PC_REGNUM)), | |
f81353e4 EZ |
2843 | (long) read_register (tdep->SR_REGNUM), |
2844 | (long) read_register (tdep->PR_REGNUM), | |
cc17453a EZ |
2845 | (long) read_register (MACH_REGNUM), |
2846 | (long) read_register (MACL_REGNUM)); | |
2847 | ||
2848 | printf_filtered ("GBR=%08lx VBR=%08lx", | |
2849 | (long) read_register (GBR_REGNUM), | |
2850 | (long) read_register (VBR_REGNUM)); | |
2851 | printf_filtered (" SSR=%08lx SPC=%08lx", | |
f81353e4 EZ |
2852 | (long) read_register (tdep->SSR_REGNUM), |
2853 | (long) read_register (tdep->SPC_REGNUM)); | |
cc17453a | 2854 | printf_filtered (" FPUL=%08lx FPSCR=%08lx", |
f81353e4 EZ |
2855 | (long) read_register (tdep->FPUL_REGNUM), |
2856 | (long) read_register (tdep->FPSCR_REGNUM)); | |
c906108c | 2857 | |
cc17453a EZ |
2858 | printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
2859 | (long) read_register (0), | |
2860 | (long) read_register (1), | |
2861 | (long) read_register (2), | |
2862 | (long) read_register (3), | |
2863 | (long) read_register (4), | |
2864 | (long) read_register (5), | |
2865 | (long) read_register (6), | |
2866 | (long) read_register (7)); | |
2867 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
2868 | (long) read_register (8), | |
2869 | (long) read_register (9), | |
2870 | (long) read_register (10), | |
2871 | (long) read_register (11), | |
2872 | (long) read_register (12), | |
2873 | (long) read_register (13), | |
2874 | (long) read_register (14), | |
2875 | (long) read_register (15)); | |
2876 | ||
2877 | printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), | |
2878 | (long) read_register (FP0_REGNUM + 0), | |
2879 | (long) read_register (FP0_REGNUM + 1), | |
2880 | (long) read_register (FP0_REGNUM + 2), | |
2881 | (long) read_register (FP0_REGNUM + 3), | |
2882 | (long) read_register (FP0_REGNUM + 4), | |
2883 | (long) read_register (FP0_REGNUM + 5), | |
2884 | (long) read_register (FP0_REGNUM + 6), | |
2885 | (long) read_register (FP0_REGNUM + 7)); | |
2886 | printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), | |
2887 | (long) read_register (FP0_REGNUM + 8), | |
2888 | (long) read_register (FP0_REGNUM + 9), | |
2889 | (long) read_register (FP0_REGNUM + 10), | |
2890 | (long) read_register (FP0_REGNUM + 11), | |
2891 | (long) read_register (FP0_REGNUM + 12), | |
2892 | (long) read_register (FP0_REGNUM + 13), | |
2893 | (long) read_register (FP0_REGNUM + 14), | |
2894 | (long) read_register (FP0_REGNUM + 15)); | |
2895 | } | |
2896 | ||
2897 | static void | |
fba45db2 | 2898 | sh3_dsp_show_regs (void) |
c906108c | 2899 | { |
f81353e4 EZ |
2900 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2901 | ||
cc17453a EZ |
2902 | printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", |
2903 | paddr (read_register (PC_REGNUM)), | |
f81353e4 EZ |
2904 | (long) read_register (tdep->SR_REGNUM), |
2905 | (long) read_register (tdep->PR_REGNUM), | |
cc17453a EZ |
2906 | (long) read_register (MACH_REGNUM), |
2907 | (long) read_register (MACL_REGNUM)); | |
c906108c | 2908 | |
cc17453a EZ |
2909 | printf_filtered ("GBR=%08lx VBR=%08lx", |
2910 | (long) read_register (GBR_REGNUM), | |
2911 | (long) read_register (VBR_REGNUM)); | |
2912 | ||
2913 | printf_filtered (" SSR=%08lx SPC=%08lx", | |
f81353e4 EZ |
2914 | (long) read_register (tdep->SSR_REGNUM), |
2915 | (long) read_register (tdep->SPC_REGNUM)); | |
cc17453a EZ |
2916 | |
2917 | printf_filtered (" DSR=%08lx", | |
f81353e4 | 2918 | (long) read_register (tdep->DSR_REGNUM)); |
cc17453a EZ |
2919 | |
2920 | printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
2921 | (long) read_register (0), | |
2922 | (long) read_register (1), | |
2923 | (long) read_register (2), | |
2924 | (long) read_register (3), | |
2925 | (long) read_register (4), | |
2926 | (long) read_register (5), | |
2927 | (long) read_register (6), | |
2928 | (long) read_register (7)); | |
2929 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
2930 | (long) read_register (8), | |
2931 | (long) read_register (9), | |
2932 | (long) read_register (10), | |
2933 | (long) read_register (11), | |
2934 | (long) read_register (12), | |
2935 | (long) read_register (13), | |
2936 | (long) read_register (14), | |
2937 | (long) read_register (15)); | |
2938 | ||
2939 | printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n", | |
f81353e4 EZ |
2940 | (long) read_register (tdep->A0G_REGNUM) & 0xff, |
2941 | (long) read_register (tdep->A0_REGNUM), | |
2942 | (long) read_register (tdep->M0_REGNUM), | |
2943 | (long) read_register (tdep->X0_REGNUM), | |
2944 | (long) read_register (tdep->Y0_REGNUM), | |
2945 | (long) read_register (tdep->RS_REGNUM), | |
2946 | (long) read_register (tdep->MOD_REGNUM)); | |
cc17453a | 2947 | printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n", |
f81353e4 EZ |
2948 | (long) read_register (tdep->A1G_REGNUM) & 0xff, |
2949 | (long) read_register (tdep->A1_REGNUM), | |
2950 | (long) read_register (tdep->M1_REGNUM), | |
2951 | (long) read_register (tdep->X1_REGNUM), | |
2952 | (long) read_register (tdep->Y1_REGNUM), | |
2953 | (long) read_register (tdep->RE_REGNUM)); | |
c906108c SS |
2954 | } |
2955 | ||
cc17453a | 2956 | static void |
fba45db2 | 2957 | sh4_show_regs (void) |
cc17453a | 2958 | { |
f81353e4 EZ |
2959 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2960 | ||
2961 | int pr = read_register (tdep->FPSCR_REGNUM) & 0x80000; | |
cc17453a EZ |
2962 | printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", |
2963 | paddr (read_register (PC_REGNUM)), | |
f81353e4 EZ |
2964 | (long) read_register (tdep->SR_REGNUM), |
2965 | (long) read_register (tdep->PR_REGNUM), | |
cc17453a EZ |
2966 | (long) read_register (MACH_REGNUM), |
2967 | (long) read_register (MACL_REGNUM)); | |
2968 | ||
2969 | printf_filtered ("GBR=%08lx VBR=%08lx", | |
2970 | (long) read_register (GBR_REGNUM), | |
2971 | (long) read_register (VBR_REGNUM)); | |
2972 | printf_filtered (" SSR=%08lx SPC=%08lx", | |
f81353e4 EZ |
2973 | (long) read_register (tdep->SSR_REGNUM), |
2974 | (long) read_register (tdep->SPC_REGNUM)); | |
cc17453a | 2975 | printf_filtered (" FPUL=%08lx FPSCR=%08lx", |
f81353e4 EZ |
2976 | (long) read_register (tdep->FPUL_REGNUM), |
2977 | (long) read_register (tdep->FPSCR_REGNUM)); | |
cc17453a EZ |
2978 | |
2979 | printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
2980 | (long) read_register (0), | |
2981 | (long) read_register (1), | |
2982 | (long) read_register (2), | |
2983 | (long) read_register (3), | |
2984 | (long) read_register (4), | |
2985 | (long) read_register (5), | |
2986 | (long) read_register (6), | |
2987 | (long) read_register (7)); | |
2988 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
2989 | (long) read_register (8), | |
2990 | (long) read_register (9), | |
2991 | (long) read_register (10), | |
2992 | (long) read_register (11), | |
2993 | (long) read_register (12), | |
2994 | (long) read_register (13), | |
2995 | (long) read_register (14), | |
2996 | (long) read_register (15)); | |
2997 | ||
2998 | printf_filtered ((pr | |
2999 | ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n" | |
3000 | : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), | |
3001 | (long) read_register (FP0_REGNUM + 0), | |
3002 | (long) read_register (FP0_REGNUM + 1), | |
3003 | (long) read_register (FP0_REGNUM + 2), | |
3004 | (long) read_register (FP0_REGNUM + 3), | |
3005 | (long) read_register (FP0_REGNUM + 4), | |
3006 | (long) read_register (FP0_REGNUM + 5), | |
3007 | (long) read_register (FP0_REGNUM + 6), | |
3008 | (long) read_register (FP0_REGNUM + 7)); | |
3009 | printf_filtered ((pr | |
3010 | ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n" | |
3011 | : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), | |
3012 | (long) read_register (FP0_REGNUM + 8), | |
3013 | (long) read_register (FP0_REGNUM + 9), | |
3014 | (long) read_register (FP0_REGNUM + 10), | |
3015 | (long) read_register (FP0_REGNUM + 11), | |
3016 | (long) read_register (FP0_REGNUM + 12), | |
3017 | (long) read_register (FP0_REGNUM + 13), | |
3018 | (long) read_register (FP0_REGNUM + 14), | |
3019 | (long) read_register (FP0_REGNUM + 15)); | |
3020 | } | |
3021 | ||
3022 | static void | |
fba45db2 | 3023 | sh_dsp_show_regs (void) |
cc17453a | 3024 | { |
f81353e4 EZ |
3025 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
3026 | ||
cc17453a EZ |
3027 | printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", |
3028 | paddr (read_register (PC_REGNUM)), | |
f81353e4 EZ |
3029 | (long) read_register (tdep->SR_REGNUM), |
3030 | (long) read_register (tdep->PR_REGNUM), | |
cc17453a EZ |
3031 | (long) read_register (MACH_REGNUM), |
3032 | (long) read_register (MACL_REGNUM)); | |
3033 | ||
3034 | printf_filtered ("GBR=%08lx VBR=%08lx", | |
3035 | (long) read_register (GBR_REGNUM), | |
3036 | (long) read_register (VBR_REGNUM)); | |
3037 | ||
3038 | printf_filtered (" DSR=%08lx", | |
f81353e4 | 3039 | (long) read_register (tdep->DSR_REGNUM)); |
cc17453a EZ |
3040 | |
3041 | printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
3042 | (long) read_register (0), | |
3043 | (long) read_register (1), | |
3044 | (long) read_register (2), | |
3045 | (long) read_register (3), | |
3046 | (long) read_register (4), | |
3047 | (long) read_register (5), | |
3048 | (long) read_register (6), | |
3049 | (long) read_register (7)); | |
3050 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
3051 | (long) read_register (8), | |
3052 | (long) read_register (9), | |
3053 | (long) read_register (10), | |
3054 | (long) read_register (11), | |
3055 | (long) read_register (12), | |
3056 | (long) read_register (13), | |
3057 | (long) read_register (14), | |
3058 | (long) read_register (15)); | |
3059 | ||
3060 | printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n", | |
f81353e4 EZ |
3061 | (long) read_register (tdep->A0G_REGNUM) & 0xff, |
3062 | (long) read_register (tdep->A0_REGNUM), | |
3063 | (long) read_register (tdep->M0_REGNUM), | |
3064 | (long) read_register (tdep->X0_REGNUM), | |
3065 | (long) read_register (tdep->Y0_REGNUM), | |
3066 | (long) read_register (tdep->RS_REGNUM), | |
3067 | (long) read_register (tdep->MOD_REGNUM)); | |
cc17453a | 3068 | printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n", |
f81353e4 EZ |
3069 | (long) read_register (tdep->A1G_REGNUM) & 0xff, |
3070 | (long) read_register (tdep->A1_REGNUM), | |
3071 | (long) read_register (tdep->M1_REGNUM), | |
3072 | (long) read_register (tdep->X1_REGNUM), | |
3073 | (long) read_register (tdep->Y1_REGNUM), | |
3074 | (long) read_register (tdep->RE_REGNUM)); | |
cc17453a EZ |
3075 | } |
3076 | ||
283150cd EZ |
3077 | static void |
3078 | sh64_show_media_regs (void) | |
3079 | { | |
3080 | int i; | |
3081 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3082 | ||
3083 | printf_filtered ("PC=%s SR=%016llx \n", | |
3084 | paddr (read_register (PC_REGNUM)), | |
3085 | (long long) read_register (tdep->SR_REGNUM)); | |
3086 | ||
3087 | printf_filtered ("SSR=%016llx SPC=%016llx \n", | |
3088 | (long long) read_register (tdep->SSR_REGNUM), | |
3089 | (long long) read_register (tdep->SPC_REGNUM)); | |
3090 | printf_filtered ("FPSCR=%016lx\n ", | |
3091 | (long) read_register (tdep->FPSCR_REGNUM)); | |
3092 | ||
3093 | for (i = 0; i < 64; i = i + 4) | |
3094 | printf_filtered ("\nR%d-R%d %016llx %016llx %016llx %016llx\n", | |
3095 | i, i + 3, | |
3096 | (long long) read_register (i + 0), | |
3097 | (long long) read_register (i + 1), | |
3098 | (long long) read_register (i + 2), | |
3099 | (long long) read_register (i + 3)); | |
3100 | ||
3101 | printf_filtered ("\n"); | |
3102 | ||
3103 | for (i = 0; i < 64; i = i + 8) | |
3104 | printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
3105 | i, i + 7, | |
3106 | (long) read_register (FP0_REGNUM + i + 0), | |
3107 | (long) read_register (FP0_REGNUM + i + 1), | |
3108 | (long) read_register (FP0_REGNUM + i + 2), | |
3109 | (long) read_register (FP0_REGNUM + i + 3), | |
3110 | (long) read_register (FP0_REGNUM + i + 4), | |
3111 | (long) read_register (FP0_REGNUM + i + 5), | |
3112 | (long) read_register (FP0_REGNUM + i + 6), | |
3113 | (long) read_register (FP0_REGNUM + i + 7)); | |
3114 | } | |
3115 | ||
3116 | static void | |
3117 | sh64_show_compact_regs (void) | |
3118 | { | |
3119 | int i; | |
3120 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3121 | ||
3122 | printf_filtered ("PC=%s \n", | |
3123 | paddr (read_register (tdep->PC_C_REGNUM))); | |
3124 | ||
3125 | printf_filtered ("GBR=%08lx MACH=%08lx MACL=%08lx PR=%08lx T=%08lx\n", | |
3126 | (long) read_register (tdep->GBR_C_REGNUM), | |
3127 | (long) read_register (tdep->MACH_C_REGNUM), | |
3128 | (long) read_register (tdep->MACL_C_REGNUM), | |
3129 | (long) read_register (tdep->PR_C_REGNUM), | |
3130 | (long) read_register (tdep->T_C_REGNUM)); | |
3131 | printf_filtered ("FPSCR=%08lx FPUL=%08lx\n", | |
3132 | (long) read_register (tdep->FPSCR_REGNUM), | |
3133 | (long) read_register (tdep->FPUL_REGNUM)); | |
3134 | ||
3135 | for (i = 0; i < 16; i = i + 4) | |
3136 | printf_filtered ("\nR%d-R%d %08lx %08lx %08lx %08lx\n", | |
3137 | i, i + 3, | |
3138 | (long) read_register (i + 0), | |
3139 | (long) read_register (i + 1), | |
3140 | (long) read_register (i + 2), | |
3141 | (long) read_register (i + 3)); | |
3142 | ||
3143 | printf_filtered ("\n"); | |
3144 | ||
3145 | for (i = 0; i < 16; i = i + 8) | |
3146 | printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
3147 | i, i + 7, | |
3148 | (long) read_register (FP0_REGNUM + i + 0), | |
3149 | (long) read_register (FP0_REGNUM + i + 1), | |
3150 | (long) read_register (FP0_REGNUM + i + 2), | |
3151 | (long) read_register (FP0_REGNUM + i + 3), | |
3152 | (long) read_register (FP0_REGNUM + i + 4), | |
3153 | (long) read_register (FP0_REGNUM + i + 5), | |
3154 | (long) read_register (FP0_REGNUM + i + 6), | |
3155 | (long) read_register (FP0_REGNUM + i + 7)); | |
3156 | } | |
3157 | ||
3158 | /*FIXME!!! This only shows the registers for shmedia, excluding the | |
3159 | pseudo registers. */ | |
3160 | static void | |
3161 | sh64_show_regs (void) | |
3162 | { | |
50abf9e5 | 3163 | if (pc_is_isa32 (get_frame_pc (deprecated_selected_frame))) |
283150cd EZ |
3164 | sh64_show_media_regs (); |
3165 | else | |
3166 | sh64_show_compact_regs (); | |
3167 | } | |
3168 | ||
a78f21af AC |
3169 | static void |
3170 | sh_show_regs_command (char *args, int from_tty) | |
53116e27 EZ |
3171 | { |
3172 | if (sh_show_regs) | |
3173 | (*sh_show_regs)(); | |
3174 | } | |
3175 | ||
283150cd EZ |
3176 | /* *INDENT-OFF* */ |
3177 | /* | |
3178 | SH MEDIA MODE (ISA 32) | |
3179 | general registers (64-bit) 0-63 | |
3180 | 0 r0, r1, r2, r3, r4, r5, r6, r7, | |
3181 | 64 r8, r9, r10, r11, r12, r13, r14, r15, | |
3182 | 128 r16, r17, r18, r19, r20, r21, r22, r23, | |
3183 | 192 r24, r25, r26, r27, r28, r29, r30, r31, | |
3184 | 256 r32, r33, r34, r35, r36, r37, r38, r39, | |
3185 | 320 r40, r41, r42, r43, r44, r45, r46, r47, | |
3186 | 384 r48, r49, r50, r51, r52, r53, r54, r55, | |
3187 | 448 r56, r57, r58, r59, r60, r61, r62, r63, | |
3188 | ||
3189 | pc (64-bit) 64 | |
3190 | 512 pc, | |
3191 | ||
3192 | status reg., saved status reg., saved pc reg. (64-bit) 65-67 | |
3193 | 520 sr, ssr, spc, | |
3194 | ||
3195 | target registers (64-bit) 68-75 | |
3196 | 544 tr0, tr1, tr2, tr3, tr4, tr5, tr6, tr7, | |
3197 | ||
3198 | floating point state control register (32-bit) 76 | |
3199 | 608 fpscr, | |
3200 | ||
3201 | single precision floating point registers (32-bit) 77-140 | |
3202 | 612 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7, | |
3203 | 644 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15, | |
3204 | 676 fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23, | |
3205 | 708 fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31, | |
3206 | 740 fr32, fr33, fr34, fr35, fr36, fr37, fr38, fr39, | |
3207 | 772 fr40, fr41, fr42, fr43, fr44, fr45, fr46, fr47, | |
3208 | 804 fr48, fr49, fr50, fr51, fr52, fr53, fr54, fr55, | |
3209 | 836 fr56, fr57, fr58, fr59, fr60, fr61, fr62, fr63, | |
3210 | ||
3211 | TOTAL SPACE FOR REGISTERS: 868 bytes | |
3212 | ||
3213 | From here on they are all pseudo registers: no memory allocated. | |
3214 | REGISTER_BYTE returns the register byte for the base register. | |
3215 | ||
3216 | double precision registers (pseudo) 141-172 | |
3217 | dr0, dr2, dr4, dr6, dr8, dr10, dr12, dr14, | |
3218 | dr16, dr18, dr20, dr22, dr24, dr26, dr28, dr30, | |
3219 | dr32, dr34, dr36, dr38, dr40, dr42, dr44, dr46, | |
3220 | dr48, dr50, dr52, dr54, dr56, dr58, dr60, dr62, | |
3221 | ||
3222 | floating point pairs (pseudo) 173-204 | |
3223 | fp0, fp2, fp4, fp6, fp8, fp10, fp12, fp14, | |
3224 | fp16, fp18, fp20, fp22, fp24, fp26, fp28, fp30, | |
3225 | fp32, fp34, fp36, fp38, fp40, fp42, fp44, fp46, | |
3226 | fp48, fp50, fp52, fp54, fp56, fp58, fp60, fp62, | |
3227 | ||
3228 | floating point vectors (4 floating point regs) (pseudo) 205-220 | |
3229 | fv0, fv4, fv8, fv12, fv16, fv20, fv24, fv28, | |
3230 | fv32, fv36, fv40, fv44, fv48, fv52, fv56, fv60, | |
3231 | ||
3232 | SH COMPACT MODE (ISA 16) (all pseudo) 221-272 | |
3233 | r0_c, r1_c, r2_c, r3_c, r4_c, r5_c, r6_c, r7_c, | |
3234 | r8_c, r9_c, r10_c, r11_c, r12_c, r13_c, r14_c, r15_c, | |
3235 | pc_c, | |
3236 | gbr_c, mach_c, macl_c, pr_c, t_c, | |
3237 | fpscr_c, fpul_c, | |
3238 | fr0_c, fr1_c, fr2_c, fr3_c, fr4_c, fr5_c, fr6_c, fr7_c, | |
3239 | fr8_c, fr9_c, fr10_c, fr11_c, fr12_c, fr13_c, fr14_c, fr15_c | |
3240 | dr0_c, dr2_c, dr4_c, dr6_c, dr8_c, dr10_c, dr12_c, dr14_c | |
3241 | fv0_c, fv4_c, fv8_c, fv12_c | |
3242 | */ | |
3243 | /* *INDENT-ON* */ | |
3244 | static int | |
3245 | sh_sh64_register_byte (int reg_nr) | |
3246 | { | |
3247 | int base_regnum = -1; | |
3248 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3249 | ||
3250 | /* If it is a pseudo register, get the number of the first floating | |
3251 | point register that is part of it. */ | |
3252 | if (reg_nr >= tdep->DR0_REGNUM | |
3253 | && reg_nr <= tdep->DR_LAST_REGNUM) | |
3254 | base_regnum = dr_reg_base_num (reg_nr); | |
3255 | ||
3256 | else if (reg_nr >= tdep->FPP0_REGNUM | |
3257 | && reg_nr <= tdep->FPP_LAST_REGNUM) | |
3258 | base_regnum = fpp_reg_base_num (reg_nr); | |
3259 | ||
3260 | else if (reg_nr >= tdep->FV0_REGNUM | |
3261 | && reg_nr <= tdep->FV_LAST_REGNUM) | |
3262 | base_regnum = fv_reg_base_num (reg_nr); | |
3263 | ||
3264 | /* sh compact pseudo register. FPSCR is a pathological case, need to | |
3265 | treat it as special. */ | |
3266 | else if ((reg_nr >= tdep->R0_C_REGNUM | |
3267 | && reg_nr <= tdep->FV_LAST_C_REGNUM) | |
3268 | && reg_nr != tdep->FPSCR_C_REGNUM) | |
3269 | base_regnum = sh64_compact_reg_base_num (reg_nr); | |
3270 | ||
3271 | /* Now return the offset in bytes within the register cache. */ | |
3272 | /* sh media pseudo register, i.e. any of DR, FFP, FV registers. */ | |
3273 | if (reg_nr >= tdep->DR0_REGNUM | |
3274 | && reg_nr <= tdep->FV_LAST_REGNUM) | |
3275 | return (base_regnum - FP0_REGNUM + 1) * 4 | |
3276 | + (tdep->TR7_REGNUM + 1) * 8; | |
3277 | ||
3278 | /* sh compact pseudo register: general register */ | |
3279 | if ((reg_nr >= tdep->R0_C_REGNUM | |
3280 | && reg_nr <= tdep->R_LAST_C_REGNUM)) | |
3281 | return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
3282 | ? base_regnum * 8 + 4 | |
3283 | : base_regnum * 8); | |
3284 | ||
3285 | /* sh compact pseudo register: */ | |
3286 | if (reg_nr == tdep->PC_C_REGNUM | |
3287 | || reg_nr == tdep->GBR_C_REGNUM | |
3288 | || reg_nr == tdep->MACL_C_REGNUM | |
3289 | || reg_nr == tdep->PR_C_REGNUM) | |
3290 | return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
3291 | ? base_regnum * 8 + 4 | |
3292 | : base_regnum * 8); | |
3293 | ||
3294 | if (reg_nr == tdep->MACH_C_REGNUM) | |
3295 | return base_regnum * 8; | |
3296 | ||
3297 | if (reg_nr == tdep->T_C_REGNUM) | |
3298 | return base_regnum * 8; /* FIXME??? how do we get bit 0? Do we have to? */ | |
3299 | ||
3300 | /* sh compact pseudo register: floating point register */ | |
3301 | else if (reg_nr >=tdep->FP0_C_REGNUM | |
3302 | && reg_nr <= tdep->FV_LAST_C_REGNUM) | |
3303 | return (base_regnum - FP0_REGNUM) * 4 | |
3304 | + (tdep->TR7_REGNUM + 1) * 8 + 4; | |
3305 | ||
3306 | else if (reg_nr == tdep->FPSCR_C_REGNUM) | |
3307 | /* This is complicated, for now return the beginning of the | |
3308 | architectural FPSCR register. */ | |
3309 | return (tdep->TR7_REGNUM + 1) * 8; | |
3310 | ||
3311 | else if (reg_nr == tdep->FPUL_C_REGNUM) | |
3312 | return ((base_regnum - FP0_REGNUM) * 4 + | |
3313 | (tdep->TR7_REGNUM + 1) * 8 + 4); | |
3314 | ||
3315 | /* It is not a pseudo register. */ | |
3316 | /* It is a 64 bit register. */ | |
3317 | else if (reg_nr <= tdep->TR7_REGNUM) | |
3318 | return reg_nr * 8; | |
3319 | ||
3320 | /* It is a 32 bit register. */ | |
3321 | else | |
3322 | if (reg_nr == tdep->FPSCR_REGNUM) | |
3323 | return (tdep->FPSCR_REGNUM * 8); | |
3324 | ||
3325 | /* It is floating point 32-bit register */ | |
3326 | else | |
3327 | return ((tdep->TR7_REGNUM + 1) * 8 | |
3328 | + (reg_nr - FP0_REGNUM + 1) * 4); | |
3329 | } | |
3330 | ||
283150cd EZ |
3331 | static int |
3332 | sh_sh64_register_raw_size (int reg_nr) | |
3333 | { | |
3334 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3335 | ||
3336 | if ((reg_nr >= tdep->DR0_REGNUM | |
3337 | && reg_nr <= tdep->DR_LAST_REGNUM) | |
3338 | || (reg_nr >= tdep->FPP0_REGNUM | |
3339 | && reg_nr <= tdep->FPP_LAST_REGNUM) | |
3340 | || (reg_nr >= tdep->DR0_C_REGNUM | |
3341 | && reg_nr <= tdep->DR_LAST_C_REGNUM) | |
3342 | || (reg_nr <= tdep->TR7_REGNUM)) | |
3343 | return 8; | |
3344 | ||
3345 | else if ((reg_nr >= tdep->FV0_REGNUM | |
3346 | && reg_nr <= tdep->FV_LAST_REGNUM) | |
3347 | || (reg_nr >= tdep->FV0_C_REGNUM | |
3348 | && reg_nr <= tdep->FV_LAST_C_REGNUM)) | |
3349 | return 16; | |
3350 | ||
3351 | else /* this covers also the 32-bit SH compact registers. */ | |
3352 | return 4; | |
3353 | } | |
3354 | ||
283150cd EZ |
3355 | /* ??????? FIXME */ |
3356 | static int | |
3357 | sh_sh64_register_virtual_size (int reg_nr) | |
3358 | { | |
3359 | if (reg_nr >= FP0_REGNUM | |
3360 | && reg_nr <= gdbarch_tdep (current_gdbarch)->FP_LAST_REGNUM) | |
3361 | return 4; | |
3362 | else | |
3363 | return 8; | |
3364 | } | |
3365 | ||
cc17453a EZ |
3366 | /* Return the GDB type object for the "standard" data type |
3367 | of data in register N. */ | |
cc17453a | 3368 | static struct type * |
48db5a3c | 3369 | sh_sh3e_register_type (struct gdbarch *gdbarch, int reg_nr) |
cc17453a | 3370 | { |
f81353e4 EZ |
3371 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
3372 | ||
cc17453a | 3373 | if ((reg_nr >= FP0_REGNUM |
f81353e4 EZ |
3374 | && (reg_nr <= tdep->FP_LAST_REGNUM)) |
3375 | || (reg_nr == tdep->FPUL_REGNUM)) | |
cc17453a | 3376 | return builtin_type_float; |
8db62801 | 3377 | else |
cc17453a EZ |
3378 | return builtin_type_int; |
3379 | } | |
3380 | ||
7f4dbe94 EZ |
3381 | static struct type * |
3382 | sh_sh4_build_float_register_type (int high) | |
3383 | { | |
3384 | struct type *temp; | |
3385 | ||
3386 | temp = create_range_type (NULL, builtin_type_int, 0, high); | |
3387 | return create_array_type (NULL, builtin_type_float, temp); | |
3388 | } | |
3389 | ||
53116e27 | 3390 | static struct type * |
48db5a3c | 3391 | sh_sh4_register_type (struct gdbarch *gdbarch, int reg_nr) |
53116e27 | 3392 | { |
48db5a3c | 3393 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
f81353e4 | 3394 | |
53116e27 | 3395 | if ((reg_nr >= FP0_REGNUM |
f81353e4 EZ |
3396 | && (reg_nr <= tdep->FP_LAST_REGNUM)) |
3397 | || (reg_nr == tdep->FPUL_REGNUM)) | |
53116e27 | 3398 | return builtin_type_float; |
f81353e4 EZ |
3399 | else if (reg_nr >= tdep->DR0_REGNUM |
3400 | && reg_nr <= tdep->DR_LAST_REGNUM) | |
53116e27 | 3401 | return builtin_type_double; |
f81353e4 EZ |
3402 | else if (reg_nr >= tdep->FV0_REGNUM |
3403 | && reg_nr <= tdep->FV_LAST_REGNUM) | |
53116e27 EZ |
3404 | return sh_sh4_build_float_register_type (3); |
3405 | else | |
3406 | return builtin_type_int; | |
3407 | } | |
3408 | ||
283150cd EZ |
3409 | static struct type * |
3410 | sh_sh64_register_virtual_type (int reg_nr) | |
3411 | { | |
3412 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3413 | ||
3414 | if ((reg_nr >= FP0_REGNUM | |
3415 | && reg_nr <= tdep->FP_LAST_REGNUM) | |
3416 | || (reg_nr >= tdep->FP0_C_REGNUM | |
3417 | && reg_nr <= tdep->FP_LAST_C_REGNUM)) | |
3418 | return builtin_type_float; | |
3419 | else if ((reg_nr >= tdep->DR0_REGNUM | |
3420 | && reg_nr <= tdep->DR_LAST_REGNUM) | |
3421 | || (reg_nr >= tdep->DR0_C_REGNUM | |
3422 | && reg_nr <= tdep->DR_LAST_C_REGNUM)) | |
3423 | return builtin_type_double; | |
3424 | else if (reg_nr >= tdep->FPP0_REGNUM | |
3425 | && reg_nr <= tdep->FPP_LAST_REGNUM) | |
3426 | return sh_sh4_build_float_register_type (1); | |
3427 | else if ((reg_nr >= tdep->FV0_REGNUM | |
3428 | && reg_nr <= tdep->FV_LAST_REGNUM) | |
3429 | ||(reg_nr >= tdep->FV0_C_REGNUM | |
3430 | && reg_nr <= tdep->FV_LAST_C_REGNUM)) | |
3431 | return sh_sh4_build_float_register_type (3); | |
3432 | else if (reg_nr == tdep->FPSCR_REGNUM) | |
3433 | return builtin_type_int; | |
3434 | else if (reg_nr >= tdep->R0_C_REGNUM | |
3435 | && reg_nr < tdep->FP0_C_REGNUM) | |
3436 | return builtin_type_int; | |
3437 | else | |
3438 | return builtin_type_long_long; | |
3439 | } | |
3440 | ||
cc17453a | 3441 | static struct type * |
48db5a3c | 3442 | sh_default_register_type (struct gdbarch *gdbarch, int reg_nr) |
cc17453a EZ |
3443 | { |
3444 | return builtin_type_int; | |
3445 | } | |
3446 | ||
fb409745 EZ |
3447 | /* On the sh4, the DRi pseudo registers are problematic if the target |
3448 | is little endian. When the user writes one of those registers, for | |
3449 | instance with 'ser var $dr0=1', we want the double to be stored | |
3450 | like this: | |
3451 | fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f | |
3452 | fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00 | |
3453 | ||
3454 | This corresponds to little endian byte order & big endian word | |
3455 | order. However if we let gdb write the register w/o conversion, it | |
3456 | will write fr0 and fr1 this way: | |
3457 | fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00 | |
3458 | fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f | |
3459 | because it will consider fr0 and fr1 as a single LE stretch of memory. | |
3460 | ||
3461 | To achieve what we want we must force gdb to store things in | |
3462 | floatformat_ieee_double_littlebyte_bigword (which is defined in | |
3463 | include/floatformat.h and libiberty/floatformat.c. | |
3464 | ||
3465 | In case the target is big endian, there is no problem, the | |
3466 | raw bytes will look like: | |
3467 | fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00 | |
3468 | fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00 | |
3469 | ||
3470 | The other pseudo registers (the FVs) also don't pose a problem | |
3471 | because they are stored as 4 individual FP elements. */ | |
3472 | ||
7bd872fe | 3473 | static void |
fb409745 EZ |
3474 | sh_sh4_register_convert_to_virtual (int regnum, struct type *type, |
3475 | char *from, char *to) | |
3476 | { | |
f81353e4 EZ |
3477 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
3478 | ||
3479 | if (regnum >= tdep->DR0_REGNUM | |
3480 | && regnum <= tdep->DR_LAST_REGNUM) | |
fb409745 EZ |
3481 | { |
3482 | DOUBLEST val; | |
3483 | floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, from, &val); | |
48db5a3c | 3484 | store_typed_floating (to, type, val); |
fb409745 EZ |
3485 | } |
3486 | else | |
3bbfbb92 | 3487 | error ("sh_register_convert_to_virtual called with non DR register number"); |
fb409745 EZ |
3488 | } |
3489 | ||
a78f21af | 3490 | static void |
283150cd EZ |
3491 | sh_sh64_register_convert_to_virtual (int regnum, struct type *type, |
3492 | char *from, char *to) | |
3493 | { | |
3494 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3495 | ||
3496 | if (TARGET_BYTE_ORDER != BFD_ENDIAN_LITTLE) | |
3497 | { | |
3498 | /* It is a no-op. */ | |
3499 | memcpy (to, from, REGISTER_RAW_SIZE (regnum)); | |
3500 | return; | |
3501 | } | |
3502 | ||
3503 | if ((regnum >= tdep->DR0_REGNUM | |
3504 | && regnum <= tdep->DR_LAST_REGNUM) | |
3505 | || (regnum >= tdep->DR0_C_REGNUM | |
3506 | && regnum <= tdep->DR_LAST_C_REGNUM)) | |
3507 | { | |
3508 | DOUBLEST val; | |
3509 | floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, from, &val); | |
f1908289 | 3510 | deprecated_store_floating(to, TYPE_LENGTH(type), val); |
283150cd EZ |
3511 | } |
3512 | else | |
3513 | error("sh_register_convert_to_virtual called with non DR register number"); | |
3514 | } | |
3515 | ||
3516 | static void | |
3517 | sh_sh4_register_convert_to_raw (struct type *type, int regnum, | |
d8124050 | 3518 | const void *from, void *to) |
283150cd EZ |
3519 | { |
3520 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3521 | ||
3522 | if (regnum >= tdep->DR0_REGNUM | |
3523 | && regnum <= tdep->DR_LAST_REGNUM) | |
3524 | { | |
48db5a3c | 3525 | DOUBLEST val = extract_typed_floating (from, type); |
283150cd EZ |
3526 | floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword, &val, to); |
3527 | } | |
3528 | else | |
3529 | error("sh_register_convert_to_raw called with non DR register number"); | |
3530 | } | |
3531 | ||
a78f21af | 3532 | static void |
283150cd | 3533 | sh_sh64_register_convert_to_raw (struct type *type, int regnum, |
d8124050 | 3534 | const void *from, void *to) |
fb409745 | 3535 | { |
f81353e4 EZ |
3536 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
3537 | ||
283150cd EZ |
3538 | if (TARGET_BYTE_ORDER != BFD_ENDIAN_LITTLE) |
3539 | { | |
3540 | /* It is a no-op. */ | |
3541 | memcpy (to, from, REGISTER_RAW_SIZE (regnum)); | |
3542 | return; | |
3543 | } | |
3544 | ||
3545 | if ((regnum >= tdep->DR0_REGNUM | |
3546 | && regnum <= tdep->DR_LAST_REGNUM) | |
3547 | || (regnum >= tdep->DR0_C_REGNUM | |
3548 | && regnum <= tdep->DR_LAST_C_REGNUM)) | |
fb409745 | 3549 | { |
f1908289 | 3550 | DOUBLEST val = deprecated_extract_floating (from, TYPE_LENGTH(type)); |
fb409745 EZ |
3551 | floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword, &val, to); |
3552 | } | |
3553 | else | |
3554 | error("sh_register_convert_to_raw called with non DR register number"); | |
3555 | } | |
3556 | ||
a78f21af | 3557 | static void |
d8124050 AC |
3558 | sh_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, |
3559 | int reg_nr, void *buffer) | |
53116e27 EZ |
3560 | { |
3561 | int base_regnum, portion; | |
d9d9c31f | 3562 | char temp_buffer[MAX_REGISTER_SIZE]; |
d8124050 | 3563 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
53116e27 | 3564 | |
7bd872fe EZ |
3565 | if (reg_nr >= tdep->DR0_REGNUM |
3566 | && reg_nr <= tdep->DR_LAST_REGNUM) | |
3567 | { | |
3568 | base_regnum = dr_reg_base_num (reg_nr); | |
3569 | ||
3570 | /* Build the value in the provided buffer. */ | |
3571 | /* Read the real regs for which this one is an alias. */ | |
3572 | for (portion = 0; portion < 2; portion++) | |
d8124050 | 3573 | regcache_raw_read (regcache, base_regnum + portion, |
0818c12a | 3574 | (temp_buffer |
48db5a3c | 3575 | + register_size (gdbarch, base_regnum) * portion)); |
7bd872fe EZ |
3576 | /* We must pay attention to the endiannes. */ |
3577 | sh_sh4_register_convert_to_virtual (reg_nr, | |
48db5a3c | 3578 | gdbarch_register_type (gdbarch, reg_nr), |
7bd872fe EZ |
3579 | temp_buffer, buffer); |
3580 | } | |
3581 | else if (reg_nr >= tdep->FV0_REGNUM | |
3582 | && reg_nr <= tdep->FV_LAST_REGNUM) | |
53116e27 | 3583 | { |
7bd872fe EZ |
3584 | base_regnum = fv_reg_base_num (reg_nr); |
3585 | ||
3586 | /* Read the real regs for which this one is an alias. */ | |
3587 | for (portion = 0; portion < 4; portion++) | |
d8124050 AC |
3588 | regcache_raw_read (regcache, base_regnum + portion, |
3589 | ((char *) buffer | |
48db5a3c | 3590 | + register_size (gdbarch, base_regnum) * portion)); |
53116e27 EZ |
3591 | } |
3592 | } | |
3593 | ||
7bd872fe | 3594 | static void |
d8124050 AC |
3595 | sh64_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, |
3596 | int reg_nr, void *buffer) | |
283150cd EZ |
3597 | { |
3598 | int base_regnum; | |
3599 | int portion; | |
3600 | int offset = 0; | |
d9d9c31f | 3601 | char temp_buffer[MAX_REGISTER_SIZE]; |
d8124050 | 3602 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
283150cd EZ |
3603 | |
3604 | if (reg_nr >= tdep->DR0_REGNUM | |
3605 | && reg_nr <= tdep->DR_LAST_REGNUM) | |
3606 | { | |
3607 | base_regnum = dr_reg_base_num (reg_nr); | |
3608 | ||
3609 | /* Build the value in the provided buffer. */ | |
3610 | /* DR regs are double precision registers obtained by | |
3611 | concatenating 2 single precision floating point registers. */ | |
3612 | for (portion = 0; portion < 2; portion++) | |
d8124050 | 3613 | regcache_raw_read (regcache, base_regnum + portion, |
0818c12a AC |
3614 | (temp_buffer |
3615 | + REGISTER_RAW_SIZE (base_regnum) * portion)); | |
283150cd EZ |
3616 | |
3617 | /* We must pay attention to the endiannes. */ | |
3618 | sh_sh64_register_convert_to_virtual (reg_nr, REGISTER_VIRTUAL_TYPE (reg_nr), | |
3619 | temp_buffer, buffer); | |
3620 | ||
3621 | } | |
3622 | ||
3623 | else if (reg_nr >= tdep->FPP0_REGNUM | |
3624 | && reg_nr <= tdep->FPP_LAST_REGNUM) | |
3625 | { | |
3626 | base_regnum = fpp_reg_base_num (reg_nr); | |
3627 | ||
3628 | /* Build the value in the provided buffer. */ | |
3629 | /* FPP regs are pairs of single precision registers obtained by | |
3630 | concatenating 2 single precision floating point registers. */ | |
3631 | for (portion = 0; portion < 2; portion++) | |
d8124050 AC |
3632 | regcache_raw_read (regcache, base_regnum + portion, |
3633 | ((char *) buffer | |
0818c12a | 3634 | + REGISTER_RAW_SIZE (base_regnum) * portion)); |
283150cd EZ |
3635 | } |
3636 | ||
3637 | else if (reg_nr >= tdep->FV0_REGNUM | |
3638 | && reg_nr <= tdep->FV_LAST_REGNUM) | |
3639 | { | |
3640 | base_regnum = fv_reg_base_num (reg_nr); | |
3641 | ||
3642 | /* Build the value in the provided buffer. */ | |
3643 | /* FV regs are vectors of single precision registers obtained by | |
3644 | concatenating 4 single precision floating point registers. */ | |
3645 | for (portion = 0; portion < 4; portion++) | |
d8124050 AC |
3646 | regcache_raw_read (regcache, base_regnum + portion, |
3647 | ((char *) buffer | |
0818c12a | 3648 | + REGISTER_RAW_SIZE (base_regnum) * portion)); |
283150cd EZ |
3649 | } |
3650 | ||
3651 | /* sh compact pseudo registers. 1-to-1 with a shmedia register */ | |
3652 | else if (reg_nr >= tdep->R0_C_REGNUM | |
3653 | && reg_nr <= tdep->T_C_REGNUM) | |
3654 | { | |
3655 | base_regnum = sh64_compact_reg_base_num (reg_nr); | |
3656 | ||
3657 | /* Build the value in the provided buffer. */ | |
d8124050 | 3658 | regcache_raw_read (regcache, base_regnum, temp_buffer); |
283150cd EZ |
3659 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
3660 | offset = 4; | |
3661 | memcpy (buffer, temp_buffer + offset, 4); /* get LOWER 32 bits only????*/ | |
3662 | } | |
3663 | ||
3664 | else if (reg_nr >= tdep->FP0_C_REGNUM | |
3665 | && reg_nr <= tdep->FP_LAST_C_REGNUM) | |
3666 | { | |
3667 | base_regnum = sh64_compact_reg_base_num (reg_nr); | |
3668 | ||
3669 | /* Build the value in the provided buffer. */ | |
3670 | /* Floating point registers map 1-1 to the media fp regs, | |
3671 | they have the same size and endienness. */ | |
d8124050 | 3672 | regcache_raw_read (regcache, base_regnum, buffer); |
283150cd EZ |
3673 | } |
3674 | ||
3675 | else if (reg_nr >= tdep->DR0_C_REGNUM | |
3676 | && reg_nr <= tdep->DR_LAST_C_REGNUM) | |
3677 | { | |
3678 | base_regnum = sh64_compact_reg_base_num (reg_nr); | |
3679 | ||
3680 | /* DR_C regs are double precision registers obtained by | |
3681 | concatenating 2 single precision floating point registers. */ | |
3682 | for (portion = 0; portion < 2; portion++) | |
d8124050 | 3683 | regcache_raw_read (regcache, base_regnum + portion, |
0818c12a AC |
3684 | (temp_buffer |
3685 | + REGISTER_RAW_SIZE (base_regnum) * portion)); | |
283150cd EZ |
3686 | |
3687 | /* We must pay attention to the endiannes. */ | |
3688 | sh_sh64_register_convert_to_virtual (reg_nr, REGISTER_VIRTUAL_TYPE (reg_nr), | |
3689 | temp_buffer, buffer); | |
3690 | } | |
3691 | ||
3692 | else if (reg_nr >= tdep->FV0_C_REGNUM | |
3693 | && reg_nr <= tdep->FV_LAST_C_REGNUM) | |
3694 | { | |
3695 | base_regnum = sh64_compact_reg_base_num (reg_nr); | |
3696 | ||
3697 | /* Build the value in the provided buffer. */ | |
3698 | /* FV_C regs are vectors of single precision registers obtained by | |
3699 | concatenating 4 single precision floating point registers. */ | |
3700 | for (portion = 0; portion < 4; portion++) | |
d8124050 AC |
3701 | regcache_raw_read (regcache, base_regnum + portion, |
3702 | ((char *) buffer | |
0818c12a | 3703 | + REGISTER_RAW_SIZE (base_regnum) * portion)); |
283150cd EZ |
3704 | } |
3705 | ||
3706 | else if (reg_nr == tdep->FPSCR_C_REGNUM) | |
3707 | { | |
3708 | int fpscr_base_regnum; | |
3709 | int sr_base_regnum; | |
3710 | unsigned int fpscr_value; | |
3711 | unsigned int sr_value; | |
3712 | unsigned int fpscr_c_value; | |
3713 | unsigned int fpscr_c_part1_value; | |
3714 | unsigned int fpscr_c_part2_value; | |
3715 | ||
3716 | fpscr_base_regnum = tdep->FPSCR_REGNUM; | |
3717 | sr_base_regnum = tdep->SR_REGNUM; | |
3718 | ||
3719 | /* Build the value in the provided buffer. */ | |
3720 | /* FPSCR_C is a very weird register that contains sparse bits | |
3721 | from the FPSCR and the SR architectural registers. | |
3722 | Specifically: */ | |
3723 | /* *INDENT-OFF* */ | |
3724 | /* | |
3725 | FPSRC_C bit | |
3726 | 0 Bit 0 of FPSCR | |
3727 | 1 reserved | |
3728 | 2-17 Bit 2-18 of FPSCR | |
3729 | 18-20 Bits 12,13,14 of SR | |
3730 | 21-31 reserved | |
3731 | */ | |
3732 | /* *INDENT-ON* */ | |
3733 | /* Get FPSCR into a local buffer */ | |
d8124050 | 3734 | regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer); |
283150cd EZ |
3735 | /* Get value as an int. */ |
3736 | fpscr_value = extract_unsigned_integer (temp_buffer, 4); | |
3737 | /* Get SR into a local buffer */ | |
d8124050 | 3738 | regcache_raw_read (regcache, sr_base_regnum, temp_buffer); |
283150cd EZ |
3739 | /* Get value as an int. */ |
3740 | sr_value = extract_unsigned_integer (temp_buffer, 4); | |
3741 | /* Build the new value. */ | |
3742 | fpscr_c_part1_value = fpscr_value & 0x3fffd; | |
3743 | fpscr_c_part2_value = (sr_value & 0x7000) << 6; | |
3744 | fpscr_c_value = fpscr_c_part1_value | fpscr_c_part2_value; | |
3745 | /* Store that in out buffer!!! */ | |
3746 | store_unsigned_integer (buffer, 4, fpscr_c_value); | |
3747 | /* FIXME There is surely an endianness gotcha here. */ | |
3748 | } | |
3749 | ||
3750 | else if (reg_nr == tdep->FPUL_C_REGNUM) | |
3751 | { | |
3752 | base_regnum = sh64_compact_reg_base_num (reg_nr); | |
3753 | ||
3754 | /* FPUL_C register is floating point register 32, | |
3755 | same size, same endianness. */ | |
d8124050 | 3756 | regcache_raw_read (regcache, base_regnum, buffer); |
283150cd EZ |
3757 | } |
3758 | } | |
3759 | ||
a78f21af | 3760 | static void |
d8124050 AC |
3761 | sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, |
3762 | int reg_nr, const void *buffer) | |
53116e27 EZ |
3763 | { |
3764 | int base_regnum, portion; | |
d9d9c31f | 3765 | char temp_buffer[MAX_REGISTER_SIZE]; |
d8124050 | 3766 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
53116e27 | 3767 | |
f81353e4 EZ |
3768 | if (reg_nr >= tdep->DR0_REGNUM |
3769 | && reg_nr <= tdep->DR_LAST_REGNUM) | |
53116e27 EZ |
3770 | { |
3771 | base_regnum = dr_reg_base_num (reg_nr); | |
3772 | ||
7bd872fe | 3773 | /* We must pay attention to the endiannes. */ |
48db5a3c | 3774 | sh_sh4_register_convert_to_raw (gdbarch_register_type (gdbarch, reg_nr), reg_nr, |
7bd872fe EZ |
3775 | buffer, temp_buffer); |
3776 | ||
53116e27 EZ |
3777 | /* Write the real regs for which this one is an alias. */ |
3778 | for (portion = 0; portion < 2; portion++) | |
d8124050 | 3779 | regcache_raw_write (regcache, base_regnum + portion, |
0818c12a | 3780 | (temp_buffer |
48db5a3c | 3781 | + register_size (gdbarch, base_regnum) * portion)); |
53116e27 | 3782 | } |
f81353e4 EZ |
3783 | else if (reg_nr >= tdep->FV0_REGNUM |
3784 | && reg_nr <= tdep->FV_LAST_REGNUM) | |
53116e27 EZ |
3785 | { |
3786 | base_regnum = fv_reg_base_num (reg_nr); | |
3787 | ||
3788 | /* Write the real regs for which this one is an alias. */ | |
3789 | for (portion = 0; portion < 4; portion++) | |
d8124050 AC |
3790 | regcache_raw_write (regcache, base_regnum + portion, |
3791 | ((char *) buffer | |
48db5a3c | 3792 | + register_size (gdbarch, base_regnum) * portion)); |
53116e27 EZ |
3793 | } |
3794 | } | |
3795 | ||
a78f21af | 3796 | static void |
d8124050 AC |
3797 | sh64_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, |
3798 | int reg_nr, const void *buffer) | |
283150cd EZ |
3799 | { |
3800 | int base_regnum, portion; | |
3801 | int offset; | |
d9d9c31f | 3802 | char temp_buffer[MAX_REGISTER_SIZE]; |
d8124050 | 3803 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
283150cd EZ |
3804 | |
3805 | if (reg_nr >= tdep->DR0_REGNUM | |
3806 | && reg_nr <= tdep->DR_LAST_REGNUM) | |
3807 | { | |
3808 | base_regnum = dr_reg_base_num (reg_nr); | |
3809 | /* We must pay attention to the endiannes. */ | |
3810 | sh_sh64_register_convert_to_raw (REGISTER_VIRTUAL_TYPE (reg_nr), reg_nr, | |
3811 | buffer, temp_buffer); | |
3812 | ||
3813 | ||
3814 | /* Write the real regs for which this one is an alias. */ | |
3815 | for (portion = 0; portion < 2; portion++) | |
d8124050 | 3816 | regcache_raw_write (regcache, base_regnum + portion, |
0818c12a AC |
3817 | (temp_buffer |
3818 | + REGISTER_RAW_SIZE (base_regnum) * portion)); | |
283150cd EZ |
3819 | } |
3820 | ||
3821 | else if (reg_nr >= tdep->FPP0_REGNUM | |
3822 | && reg_nr <= tdep->FPP_LAST_REGNUM) | |
3823 | { | |
3824 | base_regnum = fpp_reg_base_num (reg_nr); | |
3825 | ||
3826 | /* Write the real regs for which this one is an alias. */ | |
3827 | for (portion = 0; portion < 2; portion++) | |
d8124050 AC |
3828 | regcache_raw_write (regcache, base_regnum + portion, |
3829 | ((char *) buffer | |
0818c12a | 3830 | + REGISTER_RAW_SIZE (base_regnum) * portion)); |
283150cd EZ |
3831 | } |
3832 | ||
3833 | else if (reg_nr >= tdep->FV0_REGNUM | |
3834 | && reg_nr <= tdep->FV_LAST_REGNUM) | |
3835 | { | |
3836 | base_regnum = fv_reg_base_num (reg_nr); | |
3837 | ||
3838 | /* Write the real regs for which this one is an alias. */ | |
3839 | for (portion = 0; portion < 4; portion++) | |
d8124050 AC |
3840 | regcache_raw_write (regcache, base_regnum + portion, |
3841 | ((char *) buffer | |
0818c12a | 3842 | + REGISTER_RAW_SIZE (base_regnum) * portion)); |
283150cd EZ |
3843 | } |
3844 | ||
3845 | /* sh compact general pseudo registers. 1-to-1 with a shmedia | |
3846 | register but only 4 bytes of it. */ | |
3847 | else if (reg_nr >= tdep->R0_C_REGNUM | |
3848 | && reg_nr <= tdep->T_C_REGNUM) | |
3849 | { | |
3850 | base_regnum = sh64_compact_reg_base_num (reg_nr); | |
3851 | /* reg_nr is 32 bit here, and base_regnum is 64 bits. */ | |
3852 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3853 | offset = 4; | |
3854 | else | |
3855 | offset = 0; | |
3856 | /* Let's read the value of the base register into a temporary | |
3857 | buffer, so that overwriting the last four bytes with the new | |
3858 | value of the pseudo will leave the upper 4 bytes unchanged. */ | |
d8124050 | 3859 | regcache_raw_read (regcache, base_regnum, temp_buffer); |
283150cd EZ |
3860 | /* Write as an 8 byte quantity */ |
3861 | memcpy (temp_buffer + offset, buffer, 4); | |
d8124050 | 3862 | regcache_raw_write (regcache, base_regnum, temp_buffer); |
283150cd EZ |
3863 | } |
3864 | ||
3865 | /* sh floating point compact pseudo registers. 1-to-1 with a shmedia | |
3866 | registers. Both are 4 bytes. */ | |
3867 | else if (reg_nr >= tdep->FP0_C_REGNUM | |
3868 | && reg_nr <= tdep->FP_LAST_C_REGNUM) | |
3869 | { | |
3870 | base_regnum = sh64_compact_reg_base_num (reg_nr); | |
d8124050 | 3871 | regcache_raw_write (regcache, base_regnum, buffer); |
283150cd EZ |
3872 | } |
3873 | ||
3874 | else if (reg_nr >= tdep->DR0_C_REGNUM | |
3875 | && reg_nr <= tdep->DR_LAST_C_REGNUM) | |
3876 | { | |
3877 | base_regnum = sh64_compact_reg_base_num (reg_nr); | |
3878 | for (portion = 0; portion < 2; portion++) | |
3879 | { | |
3880 | /* We must pay attention to the endiannes. */ | |
3881 | sh_sh64_register_convert_to_raw (REGISTER_VIRTUAL_TYPE (reg_nr), reg_nr, | |
3882 | buffer, temp_buffer); | |
3883 | ||
d8124050 | 3884 | regcache_raw_write (regcache, base_regnum + portion, |
0818c12a AC |
3885 | (temp_buffer |
3886 | + REGISTER_RAW_SIZE (base_regnum) * portion)); | |
283150cd EZ |
3887 | } |
3888 | } | |
3889 | ||
3890 | else if (reg_nr >= tdep->FV0_C_REGNUM | |
3891 | && reg_nr <= tdep->FV_LAST_C_REGNUM) | |
3892 | { | |
3893 | base_regnum = sh64_compact_reg_base_num (reg_nr); | |
3894 | ||
3895 | for (portion = 0; portion < 4; portion++) | |
3896 | { | |
d8124050 AC |
3897 | regcache_raw_write (regcache, base_regnum + portion, |
3898 | ((char *) buffer | |
0818c12a | 3899 | + REGISTER_RAW_SIZE (base_regnum) * portion)); |
283150cd EZ |
3900 | } |
3901 | } | |
3902 | ||
3903 | else if (reg_nr == tdep->FPSCR_C_REGNUM) | |
3904 | { | |
3905 | int fpscr_base_regnum; | |
3906 | int sr_base_regnum; | |
3907 | unsigned int fpscr_value; | |
3908 | unsigned int sr_value; | |
3909 | unsigned int old_fpscr_value; | |
3910 | unsigned int old_sr_value; | |
3911 | unsigned int fpscr_c_value; | |
3912 | unsigned int fpscr_mask; | |
3913 | unsigned int sr_mask; | |
3914 | ||
3915 | fpscr_base_regnum = tdep->FPSCR_REGNUM; | |
3916 | sr_base_regnum = tdep->SR_REGNUM; | |
3917 | ||
3918 | /* FPSCR_C is a very weird register that contains sparse bits | |
3919 | from the FPSCR and the SR architectural registers. | |
3920 | Specifically: */ | |
3921 | /* *INDENT-OFF* */ | |
3922 | /* | |
3923 | FPSRC_C bit | |
3924 | 0 Bit 0 of FPSCR | |
3925 | 1 reserved | |
3926 | 2-17 Bit 2-18 of FPSCR | |
3927 | 18-20 Bits 12,13,14 of SR | |
3928 | 21-31 reserved | |
3929 | */ | |
3930 | /* *INDENT-ON* */ | |
3931 | /* Get value as an int. */ | |
3932 | fpscr_c_value = extract_unsigned_integer (buffer, 4); | |
3933 | ||
3934 | /* Build the new values. */ | |
3935 | fpscr_mask = 0x0003fffd; | |
3936 | sr_mask = 0x001c0000; | |
3937 | ||
3938 | fpscr_value = fpscr_c_value & fpscr_mask; | |
3939 | sr_value = (fpscr_value & sr_mask) >> 6; | |
3940 | ||
d8124050 | 3941 | regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer); |
283150cd EZ |
3942 | old_fpscr_value = extract_unsigned_integer (temp_buffer, 4); |
3943 | old_fpscr_value &= 0xfffc0002; | |
3944 | fpscr_value |= old_fpscr_value; | |
3945 | store_unsigned_integer (temp_buffer, 4, fpscr_value); | |
d8124050 | 3946 | regcache_raw_write (regcache, fpscr_base_regnum, temp_buffer); |
283150cd | 3947 | |
d8124050 | 3948 | regcache_raw_read (regcache, sr_base_regnum, temp_buffer); |
283150cd EZ |
3949 | old_sr_value = extract_unsigned_integer (temp_buffer, 4); |
3950 | old_sr_value &= 0xffff8fff; | |
3951 | sr_value |= old_sr_value; | |
3952 | store_unsigned_integer (temp_buffer, 4, sr_value); | |
d8124050 | 3953 | regcache_raw_write (regcache, sr_base_regnum, temp_buffer); |
283150cd EZ |
3954 | } |
3955 | ||
3956 | else if (reg_nr == tdep->FPUL_C_REGNUM) | |
3957 | { | |
3958 | base_regnum = sh64_compact_reg_base_num (reg_nr); | |
d8124050 | 3959 | regcache_raw_write (regcache, base_regnum, buffer); |
283150cd EZ |
3960 | } |
3961 | } | |
3962 | ||
3bbfbb92 | 3963 | /* Floating point vector of 4 float registers. */ |
53116e27 | 3964 | static void |
48db5a3c CV |
3965 | do_fv_register_info (struct gdbarch *gdbarch, struct ui_file *file, |
3966 | int fv_regnum) | |
53116e27 EZ |
3967 | { |
3968 | int first_fp_reg_num = fv_reg_base_num (fv_regnum); | |
48db5a3c CV |
3969 | fprintf_filtered (file, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n", |
3970 | fv_regnum - gdbarch_tdep (gdbarch)->FV0_REGNUM, | |
53116e27 EZ |
3971 | (int) read_register (first_fp_reg_num), |
3972 | (int) read_register (first_fp_reg_num + 1), | |
3973 | (int) read_register (first_fp_reg_num + 2), | |
3974 | (int) read_register (first_fp_reg_num + 3)); | |
3975 | } | |
3976 | ||
283150cd EZ |
3977 | /* Floating point vector of 4 float registers, compact mode. */ |
3978 | static void | |
3979 | do_fv_c_register_info (int fv_regnum) | |
3980 | { | |
3981 | int first_fp_reg_num = sh64_compact_reg_base_num (fv_regnum); | |
3982 | printf_filtered ("fv%d_c\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n", | |
3983 | fv_regnum - gdbarch_tdep (current_gdbarch)->FV0_C_REGNUM, | |
3984 | (int) read_register (first_fp_reg_num), | |
3985 | (int) read_register (first_fp_reg_num + 1), | |
3986 | (int) read_register (first_fp_reg_num + 2), | |
3987 | (int) read_register (first_fp_reg_num + 3)); | |
3988 | } | |
3989 | ||
3990 | /* Pairs of single regs. The DR are instead double precision | |
3991 | registers. */ | |
3992 | static void | |
3993 | do_fpp_register_info (int fpp_regnum) | |
3994 | { | |
3995 | int first_fp_reg_num = fpp_reg_base_num (fpp_regnum); | |
3996 | ||
3997 | printf_filtered ("fpp%d\t0x%08x\t0x%08x\n", | |
3998 | fpp_regnum - gdbarch_tdep (current_gdbarch)->FPP0_REGNUM, | |
3999 | (int) read_register (first_fp_reg_num), | |
4000 | (int) read_register (first_fp_reg_num + 1)); | |
4001 | } | |
4002 | ||
3bbfbb92 | 4003 | /* Double precision registers. */ |
53116e27 | 4004 | static void |
48db5a3c CV |
4005 | do_dr_register_info (struct gdbarch *gdbarch, struct ui_file *file, |
4006 | int dr_regnum) | |
53116e27 EZ |
4007 | { |
4008 | int first_fp_reg_num = dr_reg_base_num (dr_regnum); | |
4009 | ||
48db5a3c CV |
4010 | fprintf_filtered (file, "dr%d\t0x%08x%08x\n", |
4011 | dr_regnum - gdbarch_tdep (gdbarch)->DR0_REGNUM, | |
53116e27 EZ |
4012 | (int) read_register (first_fp_reg_num), |
4013 | (int) read_register (first_fp_reg_num + 1)); | |
4014 | } | |
4015 | ||
283150cd EZ |
4016 | /* Double precision registers, compact mode. */ |
4017 | static void | |
4018 | do_dr_c_register_info (int dr_regnum) | |
4019 | { | |
4020 | int first_fp_reg_num = sh64_compact_reg_base_num (dr_regnum); | |
4021 | ||
4022 | printf_filtered ("dr%d_c\t0x%08x%08x\n", | |
4023 | dr_regnum - gdbarch_tdep (current_gdbarch)->DR0_C_REGNUM, | |
4024 | (int) read_register (first_fp_reg_num), | |
4025 | (int) read_register (first_fp_reg_num +1)); | |
4026 | } | |
4027 | ||
4028 | /* General register in compact mode. */ | |
4029 | static void | |
4030 | do_r_c_register_info (int r_c_regnum) | |
4031 | { | |
4032 | int regnum = sh64_compact_reg_base_num (r_c_regnum); | |
4033 | ||
4034 | printf_filtered ("r%d_c\t0x%08x\n", | |
4035 | r_c_regnum - gdbarch_tdep (current_gdbarch)->R0_C_REGNUM, | |
4036 | /*FIXME!!!*/ (int) read_register (regnum)); | |
4037 | } | |
4038 | ||
4039 | /* FIXME:!! THIS SHOULD TAKE CARE OF GETTING THE RIGHT PORTION OF THE | |
4040 | shmedia REGISTERS. */ | |
4041 | /* Control registers, compact mode. */ | |
4042 | static void | |
4043 | do_cr_c_register_info (int cr_c_regnum) | |
4044 | { | |
4045 | switch (cr_c_regnum) | |
4046 | { | |
4047 | case 237: printf_filtered ("pc_c\t0x%08x\n", (int) read_register (cr_c_regnum)); | |
4048 | break; | |
4049 | case 238: printf_filtered ("gbr_c\t0x%08x\n", (int) read_register (cr_c_regnum)); | |
4050 | break; | |
4051 | case 239: printf_filtered ("mach_c\t0x%08x\n", (int) read_register (cr_c_regnum)); | |
4052 | break; | |
4053 | case 240: printf_filtered ("macl_c\t0x%08x\n", (int) read_register (cr_c_regnum)); | |
4054 | break; | |
4055 | case 241: printf_filtered ("pr_c\t0x%08x\n", (int) read_register (cr_c_regnum)); | |
4056 | break; | |
4057 | case 242: printf_filtered ("t_c\t0x%08x\n", (int) read_register (cr_c_regnum)); | |
4058 | break; | |
4059 | case 243: printf_filtered ("fpscr_c\t0x%08x\n", (int) read_register (cr_c_regnum)); | |
4060 | break; | |
4061 | case 244: printf_filtered ("fpul_c\t0x%08x\n", (int)read_register (cr_c_regnum)); | |
4062 | break; | |
4063 | } | |
4064 | } | |
4065 | ||
53116e27 | 4066 | static void |
48db5a3c CV |
4067 | sh_print_pseudo_register (struct gdbarch *gdbarch, struct ui_file *file, |
4068 | int regnum) | |
53116e27 | 4069 | { |
48db5a3c | 4070 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
f81353e4 | 4071 | |
53116e27 | 4072 | if (regnum < NUM_REGS || regnum >= NUM_REGS + NUM_PSEUDO_REGS) |
8e65ff28 AC |
4073 | internal_error (__FILE__, __LINE__, |
4074 | "Invalid pseudo register number %d\n", regnum); | |
f81353e4 | 4075 | else if (regnum >= tdep->DR0_REGNUM |
48db5a3c CV |
4076 | && regnum <= tdep->DR_LAST_REGNUM) |
4077 | do_dr_register_info (gdbarch, file, regnum); | |
f81353e4 EZ |
4078 | else if (regnum >= tdep->FV0_REGNUM |
4079 | && regnum <= tdep->FV_LAST_REGNUM) | |
48db5a3c | 4080 | do_fv_register_info (gdbarch, file, regnum); |
53116e27 EZ |
4081 | } |
4082 | ||
53116e27 | 4083 | static void |
48db5a3c | 4084 | sh_do_fp_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum) |
53116e27 EZ |
4085 | { /* do values for FP (float) regs */ |
4086 | char *raw_buffer; | |
4087 | double flt; /* double extracted from raw hex data */ | |
4088 | int inv; | |
4089 | int j; | |
4090 | ||
4091 | /* Allocate space for the float. */ | |
48db5a3c | 4092 | raw_buffer = (char *) alloca (register_size (gdbarch, FP0_REGNUM)); |
53116e27 EZ |
4093 | |
4094 | /* Get the data in raw format. */ | |
48db5a3c | 4095 | if (!frame_register_read (get_selected_frame (), regnum, raw_buffer)) |
53116e27 EZ |
4096 | error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum)); |
4097 | ||
4098 | /* Get the register as a number */ | |
4099 | flt = unpack_double (builtin_type_float, raw_buffer, &inv); | |
4100 | ||
4101 | /* Print the name and some spaces. */ | |
48db5a3c CV |
4102 | fputs_filtered (REGISTER_NAME (regnum), file); |
4103 | print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file); | |
53116e27 EZ |
4104 | |
4105 | /* Print the value. */ | |
93d56215 | 4106 | if (inv) |
48db5a3c | 4107 | fprintf_filtered (file, "<invalid float>"); |
93d56215 | 4108 | else |
48db5a3c | 4109 | fprintf_filtered (file, "%-10.9g", flt); |
53116e27 EZ |
4110 | |
4111 | /* Print the fp register as hex. */ | |
48db5a3c CV |
4112 | fprintf_filtered (file, "\t(raw 0x"); |
4113 | for (j = 0; j < register_size (gdbarch, regnum); j++) | |
53116e27 | 4114 | { |
d7449b42 | 4115 | register int idx = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? j |
48db5a3c CV |
4116 | : register_size (gdbarch, regnum) - 1 - j; |
4117 | fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[idx]); | |
53116e27 | 4118 | } |
48db5a3c CV |
4119 | fprintf_filtered (file, ")"); |
4120 | fprintf_filtered (file, "\n"); | |
53116e27 EZ |
4121 | } |
4122 | ||
283150cd EZ |
4123 | static void |
4124 | sh64_do_pseudo_register (int regnum) | |
4125 | { | |
4126 | /* All the sh64-compact mode registers are pseudo registers. */ | |
4127 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
4128 | ||
4129 | if (regnum < NUM_REGS | |
4130 | || regnum >= NUM_REGS + NUM_PSEUDO_REGS_SH_MEDIA + NUM_PSEUDO_REGS_SH_COMPACT) | |
4131 | internal_error (__FILE__, __LINE__, | |
4132 | "Invalid pseudo register number %d\n", regnum); | |
4133 | ||
4134 | else if ((regnum >= tdep->DR0_REGNUM | |
4135 | && regnum <= tdep->DR_LAST_REGNUM)) | |
48db5a3c | 4136 | do_dr_register_info (current_gdbarch, gdb_stdout, regnum); |
283150cd EZ |
4137 | |
4138 | else if ((regnum >= tdep->DR0_C_REGNUM | |
4139 | && regnum <= tdep->DR_LAST_C_REGNUM)) | |
4140 | do_dr_c_register_info (regnum); | |
4141 | ||
4142 | else if ((regnum >= tdep->FV0_REGNUM | |
4143 | && regnum <= tdep->FV_LAST_REGNUM)) | |
48db5a3c | 4144 | do_fv_register_info (current_gdbarch, gdb_stdout, regnum); |
283150cd EZ |
4145 | |
4146 | else if ((regnum >= tdep->FV0_C_REGNUM | |
4147 | && regnum <= tdep->FV_LAST_C_REGNUM)) | |
4148 | do_fv_c_register_info (regnum); | |
4149 | ||
4150 | else if (regnum >= tdep->FPP0_REGNUM | |
4151 | && regnum <= tdep->FPP_LAST_REGNUM) | |
4152 | do_fpp_register_info (regnum); | |
4153 | ||
4154 | else if (regnum >= tdep->R0_C_REGNUM | |
4155 | && regnum <= tdep->R_LAST_C_REGNUM) | |
4156 | do_r_c_register_info (regnum); /* FIXME, this function will not print the right format */ | |
4157 | ||
4158 | else if (regnum >= tdep->FP0_C_REGNUM | |
4159 | && regnum <= tdep->FP_LAST_C_REGNUM) | |
48db5a3c | 4160 | sh_do_fp_register (current_gdbarch, gdb_stdout, regnum); /* this should work also for pseudoregs */ |
283150cd EZ |
4161 | |
4162 | else if (regnum >= tdep->PC_C_REGNUM | |
4163 | && regnum <= tdep->FPUL_C_REGNUM) | |
4164 | do_cr_c_register_info (regnum); | |
4165 | ||
4166 | } | |
4167 | ||
53116e27 | 4168 | static void |
48db5a3c | 4169 | sh_do_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum) |
53116e27 | 4170 | { |
123a958e | 4171 | char raw_buffer[MAX_REGISTER_SIZE]; |
53116e27 | 4172 | |
48db5a3c CV |
4173 | fputs_filtered (REGISTER_NAME (regnum), file); |
4174 | print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file); | |
53116e27 EZ |
4175 | |
4176 | /* Get the data in raw format. */ | |
48db5a3c CV |
4177 | if (!frame_register_read (get_selected_frame (), regnum, raw_buffer)) |
4178 | fprintf_filtered (file, "*value not available*\n"); | |
53116e27 | 4179 | |
48db5a3c CV |
4180 | val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0, |
4181 | file, 'x', 1, 0, Val_pretty_default); | |
4182 | fprintf_filtered (file, "\t"); | |
4183 | val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0, | |
4184 | file, 0, 1, 0, Val_pretty_default); | |
4185 | fprintf_filtered (file, "\n"); | |
53116e27 EZ |
4186 | } |
4187 | ||
4188 | static void | |
48db5a3c | 4189 | sh_print_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum) |
53116e27 EZ |
4190 | { |
4191 | if (regnum < 0 || regnum >= NUM_REGS + NUM_PSEUDO_REGS) | |
8e65ff28 AC |
4192 | internal_error (__FILE__, __LINE__, |
4193 | "Invalid register number %d\n", regnum); | |
53116e27 | 4194 | |
e30839fe | 4195 | else if (regnum >= 0 && regnum < NUM_REGS) |
53116e27 | 4196 | { |
48db5a3c CV |
4197 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
4198 | sh_do_fp_register (gdbarch, file, regnum); /* FP regs */ | |
53116e27 | 4199 | else |
48db5a3c | 4200 | sh_do_register (gdbarch, file, regnum); /* All other regs */ |
53116e27 EZ |
4201 | } |
4202 | ||
4203 | else if (regnum < NUM_REGS + NUM_PSEUDO_REGS) | |
48db5a3c CV |
4204 | { |
4205 | if (gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh5) | |
4206 | sh64_do_pseudo_register (regnum); | |
4207 | else | |
4208 | sh_print_pseudo_register (gdbarch, file, regnum); | |
4209 | } | |
53116e27 EZ |
4210 | } |
4211 | ||
a78f21af | 4212 | static void |
48db5a3c CV |
4213 | sh_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
4214 | struct frame_info *frame, int regnum, int fpregs) | |
53116e27 EZ |
4215 | { |
4216 | if (regnum != -1) /* do one specified register */ | |
4217 | { | |
4218 | if (*(REGISTER_NAME (regnum)) == '\0') | |
4219 | error ("Not a valid register for the current processor type"); | |
4220 | ||
48db5a3c | 4221 | sh_print_register (gdbarch, file, regnum); |
53116e27 EZ |
4222 | } |
4223 | else | |
4224 | /* do all (or most) registers */ | |
4225 | { | |
4226 | regnum = 0; | |
4227 | while (regnum < NUM_REGS) | |
4228 | { | |
4229 | /* If the register name is empty, it is undefined for this | |
4230 | processor, so don't display anything. */ | |
4231 | if (REGISTER_NAME (regnum) == NULL | |
4232 | || *(REGISTER_NAME (regnum)) == '\0') | |
4233 | { | |
4234 | regnum++; | |
4235 | continue; | |
4236 | } | |
4237 | ||
48db5a3c | 4238 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
53116e27 EZ |
4239 | { |
4240 | if (fpregs) | |
4241 | { | |
4242 | /* true for "INFO ALL-REGISTERS" command */ | |
48db5a3c | 4243 | sh_do_fp_register (gdbarch, file, regnum); /* FP regs */ |
53116e27 EZ |
4244 | regnum ++; |
4245 | } | |
4246 | else | |
48db5a3c | 4247 | regnum += (gdbarch_tdep (gdbarch)->FP_LAST_REGNUM - FP0_REGNUM); /* skip FP regs */ |
53116e27 EZ |
4248 | } |
4249 | else | |
4250 | { | |
48db5a3c | 4251 | sh_do_register (gdbarch, file, regnum); /* All other regs */ |
53116e27 EZ |
4252 | regnum++; |
4253 | } | |
4254 | } | |
4255 | ||
4256 | if (fpregs) | |
4257 | while (regnum < NUM_REGS + NUM_PSEUDO_REGS) | |
4258 | { | |
48db5a3c CV |
4259 | if (gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh5) |
4260 | sh64_do_pseudo_register (regnum); | |
4261 | else | |
4262 | sh_print_pseudo_register (gdbarch, file, regnum); | |
53116e27 EZ |
4263 | regnum++; |
4264 | } | |
4265 | } | |
4266 | } | |
4267 | ||
a78f21af | 4268 | static void |
283150cd EZ |
4269 | sh_compact_do_registers_info (int regnum, int fpregs) |
4270 | { | |
4271 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
4272 | if (regnum != -1) /* do one specified register */ | |
4273 | { | |
4274 | if (*(REGISTER_NAME (regnum)) == '\0') | |
4275 | error ("Not a valid register for the current processor type"); | |
4276 | ||
4277 | if (regnum >= 0 && regnum < tdep->R0_C_REGNUM) | |
4278 | error ("Not a valid register for the current processor mode."); | |
4279 | ||
48db5a3c | 4280 | sh_print_register (current_gdbarch, gdb_stdout, regnum); |
283150cd EZ |
4281 | } |
4282 | else | |
4283 | /* do all compact registers */ | |
4284 | { | |
4285 | regnum = tdep->R0_C_REGNUM; | |
4286 | while (regnum < NUM_REGS + NUM_PSEUDO_REGS) | |
4287 | { | |
48db5a3c | 4288 | sh64_do_pseudo_register (regnum); |
283150cd EZ |
4289 | regnum++; |
4290 | } | |
4291 | } | |
4292 | } | |
4293 | ||
a78f21af | 4294 | static void |
283150cd EZ |
4295 | sh64_do_registers_info (int regnum, int fpregs) |
4296 | { | |
50abf9e5 | 4297 | if (pc_is_isa32 (get_frame_pc (deprecated_selected_frame))) |
48db5a3c CV |
4298 | sh_print_registers_info (current_gdbarch, gdb_stdout, |
4299 | deprecated_selected_frame, regnum, fpregs); | |
283150cd EZ |
4300 | else |
4301 | sh_compact_do_registers_info (regnum, fpregs); | |
4302 | } | |
4303 | ||
1a8629c7 MS |
4304 | #ifdef SVR4_SHARED_LIBS |
4305 | ||
4306 | /* Fetch (and possibly build) an appropriate link_map_offsets structure | |
4307 | for native i386 linux targets using the struct offsets defined in | |
4308 | link.h (but without actual reference to that file). | |
4309 | ||
4310 | This makes it possible to access i386-linux shared libraries from | |
4311 | a gdb that was not built on an i386-linux host (for cross debugging). | |
4312 | */ | |
4313 | ||
4314 | struct link_map_offsets * | |
4315 | sh_linux_svr4_fetch_link_map_offsets (void) | |
4316 | { | |
4317 | static struct link_map_offsets lmo; | |
4318 | static struct link_map_offsets *lmp = 0; | |
4319 | ||
4320 | if (lmp == 0) | |
4321 | { | |
4322 | lmp = &lmo; | |
4323 | ||
4324 | lmo.r_debug_size = 8; /* 20 not actual size but all we need */ | |
4325 | ||
4326 | lmo.r_map_offset = 4; | |
4327 | lmo.r_map_size = 4; | |
4328 | ||
4329 | lmo.link_map_size = 20; /* 552 not actual size but all we need */ | |
4330 | ||
4331 | lmo.l_addr_offset = 0; | |
4332 | lmo.l_addr_size = 4; | |
4333 | ||
4334 | lmo.l_name_offset = 4; | |
4335 | lmo.l_name_size = 4; | |
4336 | ||
4337 | lmo.l_next_offset = 12; | |
4338 | lmo.l_next_size = 4; | |
4339 | ||
4340 | lmo.l_prev_offset = 16; | |
4341 | lmo.l_prev_size = 4; | |
4342 | } | |
4343 | ||
4344 | return lmp; | |
4345 | } | |
4346 | #endif /* SVR4_SHARED_LIBS */ | |
4347 | ||
2f14585c JR |
4348 | \f |
4349 | enum | |
4350 | { | |
4351 | DSP_DSR_REGNUM = 24, | |
4352 | DSP_A0G_REGNUM, | |
4353 | DSP_A0_REGNUM, | |
4354 | DSP_A1G_REGNUM, | |
4355 | DSP_A1_REGNUM, | |
4356 | DSP_M0_REGNUM, | |
4357 | DSP_M1_REGNUM, | |
4358 | DSP_X0_REGNUM, | |
4359 | DSP_X1_REGNUM, | |
4360 | DSP_Y0_REGNUM, | |
4361 | DSP_Y1_REGNUM, | |
4362 | ||
4363 | DSP_MOD_REGNUM = 40, | |
4364 | ||
4365 | DSP_RS_REGNUM = 43, | |
4366 | DSP_RE_REGNUM, | |
4367 | ||
4368 | DSP_R0_BANK_REGNUM = 51, | |
4369 | DSP_R7_BANK_REGNUM = DSP_R0_BANK_REGNUM + 7 | |
4370 | }; | |
4371 | ||
4372 | static int | |
4373 | sh_dsp_register_sim_regno (int nr) | |
4374 | { | |
4375 | if (legacy_register_sim_regno (nr) < 0) | |
4376 | return legacy_register_sim_regno (nr); | |
32f63c4b | 4377 | if (nr >= DSP_DSR_REGNUM && nr <= DSP_Y1_REGNUM) |
2f14585c JR |
4378 | return nr - DSP_DSR_REGNUM + SIM_SH_DSR_REGNUM; |
4379 | if (nr == DSP_MOD_REGNUM) | |
4380 | return SIM_SH_MOD_REGNUM; | |
4381 | if (nr == DSP_RS_REGNUM) | |
4382 | return SIM_SH_RS_REGNUM; | |
4383 | if (nr == DSP_RE_REGNUM) | |
4384 | return SIM_SH_RE_REGNUM; | |
4385 | if (nr >= DSP_R0_BANK_REGNUM && nr <= DSP_R7_BANK_REGNUM) | |
4386 | return nr - DSP_R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM; | |
4387 | return nr; | |
4388 | } | |
d658f924 | 4389 | \f |
cc17453a EZ |
4390 | static gdbarch_init_ftype sh_gdbarch_init; |
4391 | ||
4392 | static struct gdbarch * | |
fba45db2 | 4393 | sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
cc17453a | 4394 | { |
48db5a3c | 4395 | static LONGEST sh64_call_dummy_words[] = {0}; |
cc17453a EZ |
4396 | struct gdbarch *gdbarch; |
4397 | struct gdbarch_tdep *tdep; | |
d658f924 | 4398 | |
4be87837 DJ |
4399 | /* If there is already a candidate, use it. */ |
4400 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
4401 | if (arches != NULL) | |
4402 | return arches->gdbarch; | |
cc17453a EZ |
4403 | |
4404 | /* None found, create a new architecture from the information | |
4405 | provided. */ | |
4406 | tdep = XMALLOC (struct gdbarch_tdep); | |
4407 | gdbarch = gdbarch_alloc (&info, tdep); | |
4408 | ||
a5afb99f AC |
4409 | /* NOTE: cagney/2002-12-06: This can be deleted when this arch is |
4410 | ready to unwind the PC first (see frame.c:get_prev_frame()). */ | |
4411 | set_gdbarch_deprecated_init_frame_pc (gdbarch, init_frame_pc_default); | |
4412 | ||
cc17453a EZ |
4413 | /* Initialize the register numbers that are not common to all the |
4414 | variants to -1, if necessary thse will be overwritten in the case | |
4415 | statement below. */ | |
4416 | tdep->FPUL_REGNUM = -1; | |
4417 | tdep->FPSCR_REGNUM = -1; | |
3bbfbb92 | 4418 | tdep->PR_REGNUM = 17; |
c62a7c7b | 4419 | tdep->SR_REGNUM = 22; |
cc17453a | 4420 | tdep->DSR_REGNUM = -1; |
e6c42fda | 4421 | tdep->FP_LAST_REGNUM = -1; |
cc17453a EZ |
4422 | tdep->A0G_REGNUM = -1; |
4423 | tdep->A0_REGNUM = -1; | |
4424 | tdep->A1G_REGNUM = -1; | |
4425 | tdep->A1_REGNUM = -1; | |
4426 | tdep->M0_REGNUM = -1; | |
4427 | tdep->M1_REGNUM = -1; | |
4428 | tdep->X0_REGNUM = -1; | |
4429 | tdep->X1_REGNUM = -1; | |
4430 | tdep->Y0_REGNUM = -1; | |
4431 | tdep->Y1_REGNUM = -1; | |
4432 | tdep->MOD_REGNUM = -1; | |
4433 | tdep->RS_REGNUM = -1; | |
4434 | tdep->RE_REGNUM = -1; | |
4435 | tdep->SSR_REGNUM = -1; | |
4436 | tdep->SPC_REGNUM = -1; | |
53116e27 | 4437 | tdep->DR0_REGNUM = -1; |
e6c42fda | 4438 | tdep->DR_LAST_REGNUM = -1; |
53116e27 | 4439 | tdep->FV0_REGNUM = -1; |
e6c42fda | 4440 | tdep->FV_LAST_REGNUM = -1; |
3bbfbb92 EZ |
4441 | tdep->ARG0_REGNUM = 4; |
4442 | tdep->ARGLAST_REGNUM = 7; | |
4443 | tdep->RETURN_REGNUM = 0; | |
4444 | tdep->FLOAT_ARGLAST_REGNUM = -1; | |
a38d2a54 | 4445 | |
283150cd EZ |
4446 | tdep->sh_abi = SH_ABI_UNKNOWN; |
4447 | ||
48db5a3c CV |
4448 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); |
4449 | set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
ec920329 | 4450 | set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
48db5a3c CV |
4451 | set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); |
4452 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
4453 | set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
4454 | set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
a38d2a54 | 4455 | set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
48db5a3c | 4456 | |
88e04cc1 | 4457 | set_gdbarch_num_regs (gdbarch, SH_DEFAULT_NUM_REGS); |
a38d2a54 | 4458 | set_gdbarch_sp_regnum (gdbarch, 15); |
0ba6dca9 | 4459 | set_gdbarch_deprecated_fp_regnum (gdbarch, 14); |
a38d2a54 | 4460 | set_gdbarch_pc_regnum (gdbarch, 16); |
48db5a3c CV |
4461 | set_gdbarch_fp0_regnum (gdbarch, -1); |
4462 | set_gdbarch_num_pseudo_regs (gdbarch, 0); | |
4463 | ||
eaf90c5d | 4464 | set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc); |
3bbfbb92 | 4465 | set_gdbarch_use_struct_convention (gdbarch, sh_use_struct_convention); |
48db5a3c | 4466 | |
2bf0cb65 | 4467 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_sh); |
2f14585c | 4468 | set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno); |
48db5a3c CV |
4469 | |
4470 | set_gdbarch_write_pc (gdbarch, generic_target_write_pc); | |
4471 | ||
4472 | set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue); | |
4473 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
4474 | set_gdbarch_decr_pc_after_break (gdbarch, 0); | |
4475 | set_gdbarch_function_start_offset (gdbarch, 0); | |
4476 | ||
4477 | set_gdbarch_frame_args_skip (gdbarch, 0); | |
4478 | set_gdbarch_frameless_function_invocation (gdbarch, frameless_look_for_prologue); | |
4479 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); | |
4480 | ||
3bbfbb92 | 4481 | skip_prologue_hard_way = sh_skip_prologue_hard_way; |
48db5a3c CV |
4482 | |
4483 | set_gdbarch_deprecated_frame_chain (gdbarch, sh_frame_chain); | |
4484 | set_gdbarch_deprecated_get_saved_register (gdbarch, deprecated_generic_get_saved_register); | |
4485 | set_gdbarch_deprecated_init_extra_frame_info (gdbarch, sh_init_extra_frame_info); | |
4486 | set_gdbarch_deprecated_pop_frame (gdbarch, sh_pop_frame); | |
4487 | set_gdbarch_deprecated_frame_saved_pc (gdbarch, sh_frame_saved_pc); | |
4488 | set_gdbarch_deprecated_saved_pc_after_call (gdbarch, sh_saved_pc_after_call); | |
19f59343 | 4489 | set_gdbarch_frame_align (gdbarch, sh_frame_align); |
cc17453a EZ |
4490 | |
4491 | switch (info.bfd_arch_info->mach) | |
8db62801 | 4492 | { |
cc17453a | 4493 | case bfd_mach_sh: |
48db5a3c CV |
4494 | set_gdbarch_register_name (gdbarch, sh_sh_register_name); |
4495 | set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info); | |
cc17453a | 4496 | sh_show_regs = sh_generic_show_regs; |
48db5a3c CV |
4497 | set_gdbarch_register_type (gdbarch, sh_default_register_type); |
4498 | set_gdbarch_push_dummy_code (gdbarch, sh_push_dummy_code); | |
4499 | set_gdbarch_store_return_value (gdbarch, sh_default_store_return_value); | |
4500 | set_gdbarch_extract_return_value (gdbarch, sh_default_extract_return_value); | |
6df2bf50 | 4501 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu); |
48db5a3c CV |
4502 | set_gdbarch_extract_struct_value_address (gdbarch, sh_extract_struct_value_address); |
4503 | ||
f30ee0bc | 4504 | set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs); |
cc17453a EZ |
4505 | break; |
4506 | case bfd_mach_sh2: | |
48db5a3c CV |
4507 | set_gdbarch_register_name (gdbarch, sh_sh_register_name); |
4508 | set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info); | |
cc17453a | 4509 | sh_show_regs = sh_generic_show_regs; |
48db5a3c CV |
4510 | set_gdbarch_register_type (gdbarch, sh_default_register_type); |
4511 | set_gdbarch_push_dummy_code (gdbarch, sh_push_dummy_code); | |
4512 | set_gdbarch_store_return_value (gdbarch, sh_default_store_return_value); | |
4513 | set_gdbarch_extract_return_value (gdbarch, sh_default_extract_return_value); | |
6df2bf50 | 4514 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu); |
48db5a3c CV |
4515 | set_gdbarch_extract_struct_value_address (gdbarch, sh_extract_struct_value_address); |
4516 | ||
f30ee0bc | 4517 | set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs); |
cc17453a | 4518 | break; |
2d188dd3 | 4519 | case bfd_mach_sh2e: |
48db5a3c CV |
4520 | /* doubles on sh2e and sh3e are actually 4 byte. */ |
4521 | set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
4522 | ||
4523 | set_gdbarch_register_name (gdbarch, sh_sh2e_register_name); | |
4524 | set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info); | |
2d188dd3 | 4525 | sh_show_regs = sh2e_show_regs; |
48db5a3c CV |
4526 | set_gdbarch_register_type (gdbarch, sh_sh3e_register_type); |
4527 | set_gdbarch_push_dummy_code (gdbarch, sh_push_dummy_code); | |
2d188dd3 | 4528 | set_gdbarch_fp0_regnum (gdbarch, 25); |
48db5a3c CV |
4529 | set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value); |
4530 | set_gdbarch_extract_return_value (gdbarch, sh3e_sh4_extract_return_value); | |
6df2bf50 | 4531 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); |
48db5a3c | 4532 | set_gdbarch_extract_struct_value_address (gdbarch, sh_extract_struct_value_address); |
2d188dd3 NC |
4533 | tdep->FPUL_REGNUM = 23; |
4534 | tdep->FPSCR_REGNUM = 24; | |
4535 | tdep->FP_LAST_REGNUM = 40; | |
6df2bf50 MS |
4536 | tdep->FLOAT_ARG0_REGNUM = 29; /* FIXME use constants! */ |
4537 | tdep->FLOAT_ARGLAST_REGNUM = 36; /* FIXME use constants! */ | |
48db5a3c | 4538 | |
6df2bf50 MS |
4539 | set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, |
4540 | sh_nofp_frame_init_saved_regs); | |
2d188dd3 | 4541 | break; |
cc17453a | 4542 | case bfd_mach_sh_dsp: |
48db5a3c CV |
4543 | set_gdbarch_register_name (gdbarch, sh_sh_dsp_register_name); |
4544 | set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info); | |
cc17453a | 4545 | sh_show_regs = sh_dsp_show_regs; |
48db5a3c CV |
4546 | set_gdbarch_register_type (gdbarch, sh_default_register_type); |
4547 | set_gdbarch_push_dummy_code (gdbarch, sh_push_dummy_code); | |
2f14585c | 4548 | set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno); |
48db5a3c CV |
4549 | set_gdbarch_store_return_value (gdbarch, sh_default_store_return_value); |
4550 | set_gdbarch_extract_return_value (gdbarch, sh_default_extract_return_value); | |
6df2bf50 | 4551 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu); |
48db5a3c | 4552 | set_gdbarch_extract_struct_value_address (gdbarch, sh_extract_struct_value_address); |
cc17453a EZ |
4553 | tdep->DSR_REGNUM = 24; |
4554 | tdep->A0G_REGNUM = 25; | |
4555 | tdep->A0_REGNUM = 26; | |
4556 | tdep->A1G_REGNUM = 27; | |
4557 | tdep->A1_REGNUM = 28; | |
4558 | tdep->M0_REGNUM = 29; | |
4559 | tdep->M1_REGNUM = 30; | |
4560 | tdep->X0_REGNUM = 31; | |
4561 | tdep->X1_REGNUM = 32; | |
4562 | tdep->Y0_REGNUM = 33; | |
4563 | tdep->Y1_REGNUM = 34; | |
4564 | tdep->MOD_REGNUM = 40; | |
4565 | tdep->RS_REGNUM = 43; | |
4566 | tdep->RE_REGNUM = 44; | |
48db5a3c CV |
4567 | |
4568 | set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs); | |
cc17453a EZ |
4569 | break; |
4570 | case bfd_mach_sh3: | |
48db5a3c CV |
4571 | set_gdbarch_register_name (gdbarch, sh_sh3_register_name); |
4572 | set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info); | |
cc17453a | 4573 | sh_show_regs = sh3_show_regs; |
48db5a3c CV |
4574 | set_gdbarch_register_type (gdbarch, sh_default_register_type); |
4575 | set_gdbarch_push_dummy_code (gdbarch, sh_push_dummy_code); | |
4576 | set_gdbarch_store_return_value (gdbarch, sh_default_store_return_value); | |
4577 | set_gdbarch_extract_return_value (gdbarch, sh_default_extract_return_value); | |
6df2bf50 | 4578 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu); |
48db5a3c | 4579 | set_gdbarch_extract_struct_value_address (gdbarch, sh_extract_struct_value_address); |
cc17453a EZ |
4580 | tdep->SSR_REGNUM = 41; |
4581 | tdep->SPC_REGNUM = 42; | |
48db5a3c CV |
4582 | |
4583 | set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs); | |
cc17453a EZ |
4584 | break; |
4585 | case bfd_mach_sh3e: | |
48db5a3c CV |
4586 | /* doubles on sh2e and sh3e are actually 4 byte. */ |
4587 | set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
4588 | ||
4589 | set_gdbarch_register_name (gdbarch, sh_sh3e_register_name); | |
4590 | set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info); | |
cc17453a | 4591 | sh_show_regs = sh3e_show_regs; |
48db5a3c CV |
4592 | set_gdbarch_register_type (gdbarch, sh_sh3e_register_type); |
4593 | set_gdbarch_push_dummy_code (gdbarch, sh_push_dummy_code); | |
cc17453a | 4594 | set_gdbarch_fp0_regnum (gdbarch, 25); |
48db5a3c CV |
4595 | set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value); |
4596 | set_gdbarch_extract_return_value (gdbarch, sh3e_sh4_extract_return_value); | |
6df2bf50 | 4597 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); |
48db5a3c | 4598 | set_gdbarch_extract_struct_value_address (gdbarch, sh_extract_struct_value_address); |
cc17453a EZ |
4599 | tdep->FPUL_REGNUM = 23; |
4600 | tdep->FPSCR_REGNUM = 24; | |
e6c42fda | 4601 | tdep->FP_LAST_REGNUM = 40; |
6df2bf50 MS |
4602 | tdep->FLOAT_ARG0_REGNUM = 29; /* FIXME use constants! */ |
4603 | tdep->FLOAT_ARGLAST_REGNUM = 36; /* FIXME use constants! */ | |
cc17453a EZ |
4604 | tdep->SSR_REGNUM = 41; |
4605 | tdep->SPC_REGNUM = 42; | |
48db5a3c CV |
4606 | |
4607 | set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh_fp_frame_init_saved_regs); | |
cc17453a EZ |
4608 | break; |
4609 | case bfd_mach_sh3_dsp: | |
48db5a3c CV |
4610 | set_gdbarch_register_name (gdbarch, sh_sh3_dsp_register_name); |
4611 | set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info); | |
cc17453a | 4612 | sh_show_regs = sh3_dsp_show_regs; |
48db5a3c CV |
4613 | set_gdbarch_register_type (gdbarch, sh_default_register_type); |
4614 | set_gdbarch_push_dummy_code (gdbarch, sh_push_dummy_code); | |
4615 | set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno); | |
4616 | set_gdbarch_store_return_value (gdbarch, sh_default_store_return_value); | |
4617 | set_gdbarch_extract_return_value (gdbarch, sh_default_extract_return_value); | |
6df2bf50 | 4618 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu); |
48db5a3c | 4619 | set_gdbarch_extract_struct_value_address (gdbarch, sh_extract_struct_value_address); |
cc17453a EZ |
4620 | tdep->DSR_REGNUM = 24; |
4621 | tdep->A0G_REGNUM = 25; | |
4622 | tdep->A0_REGNUM = 26; | |
4623 | tdep->A1G_REGNUM = 27; | |
4624 | tdep->A1_REGNUM = 28; | |
4625 | tdep->M0_REGNUM = 29; | |
4626 | tdep->M1_REGNUM = 30; | |
4627 | tdep->X0_REGNUM = 31; | |
4628 | tdep->X1_REGNUM = 32; | |
4629 | tdep->Y0_REGNUM = 33; | |
4630 | tdep->Y1_REGNUM = 34; | |
4631 | tdep->MOD_REGNUM = 40; | |
4632 | tdep->RS_REGNUM = 43; | |
4633 | tdep->RE_REGNUM = 44; | |
4634 | tdep->SSR_REGNUM = 41; | |
4635 | tdep->SPC_REGNUM = 42; | |
48db5a3c CV |
4636 | |
4637 | set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs); | |
cc17453a EZ |
4638 | break; |
4639 | case bfd_mach_sh4: | |
48db5a3c CV |
4640 | set_gdbarch_register_name (gdbarch, sh_sh4_register_name); |
4641 | set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info); | |
53116e27 | 4642 | sh_show_regs = sh4_show_regs; |
48db5a3c CV |
4643 | set_gdbarch_register_type (gdbarch, sh_sh4_register_type); |
4644 | set_gdbarch_push_dummy_code (gdbarch, sh_push_dummy_code); | |
cc17453a | 4645 | set_gdbarch_fp0_regnum (gdbarch, 25); |
53116e27 | 4646 | set_gdbarch_num_pseudo_regs (gdbarch, 12); |
d8124050 AC |
4647 | set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read); |
4648 | set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write); | |
48db5a3c CV |
4649 | set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value); |
4650 | set_gdbarch_extract_return_value (gdbarch, sh3e_sh4_extract_return_value); | |
6df2bf50 | 4651 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); |
48db5a3c | 4652 | set_gdbarch_extract_struct_value_address (gdbarch, sh_extract_struct_value_address); |
cc17453a EZ |
4653 | tdep->FPUL_REGNUM = 23; |
4654 | tdep->FPSCR_REGNUM = 24; | |
e6c42fda | 4655 | tdep->FP_LAST_REGNUM = 40; |
cc17453a EZ |
4656 | tdep->SSR_REGNUM = 41; |
4657 | tdep->SPC_REGNUM = 42; | |
53116e27 | 4658 | tdep->DR0_REGNUM = 59; |
e6c42fda | 4659 | tdep->DR_LAST_REGNUM = 66; |
53116e27 | 4660 | tdep->FV0_REGNUM = 67; |
e6c42fda | 4661 | tdep->FV_LAST_REGNUM = 70; |
6df2bf50 MS |
4662 | tdep->FLOAT_ARG0_REGNUM = 29; /* FIXME use constants! */ |
4663 | tdep->FLOAT_ARGLAST_REGNUM = 36; /* FIXME use constants! */ | |
48db5a3c CV |
4664 | |
4665 | set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh_fp_frame_init_saved_regs); | |
cc17453a | 4666 | break; |
283150cd EZ |
4667 | case bfd_mach_sh5: |
4668 | tdep->PR_REGNUM = 18; | |
4669 | tdep->SR_REGNUM = 65; | |
4670 | tdep->FPSCR_REGNUM = SIM_SH64_FPCSR_REGNUM; | |
4671 | tdep->FP_LAST_REGNUM = SIM_SH64_FR0_REGNUM + SIM_SH64_NR_FP_REGS - 1; | |
4672 | tdep->SSR_REGNUM = SIM_SH64_SSR_REGNUM; | |
4673 | tdep->SPC_REGNUM = SIM_SH64_SPC_REGNUM; | |
4674 | tdep->TR7_REGNUM = SIM_SH64_TR0_REGNUM + 7; | |
4675 | tdep->FPP0_REGNUM = 173; | |
4676 | tdep->FPP_LAST_REGNUM = 204; | |
4677 | tdep->DR0_REGNUM = 141; | |
4678 | tdep->DR_LAST_REGNUM = 172; | |
4679 | tdep->FV0_REGNUM = 205; | |
4680 | tdep->FV_LAST_REGNUM = 220; | |
4681 | tdep->R0_C_REGNUM = 221; | |
4682 | tdep->R_LAST_C_REGNUM = 236; | |
4683 | tdep->PC_C_REGNUM = 237; | |
4684 | tdep->GBR_C_REGNUM = 238; | |
4685 | tdep->MACH_C_REGNUM = 239; | |
4686 | tdep->MACL_C_REGNUM = 240; | |
4687 | tdep->PR_C_REGNUM = 241; | |
4688 | tdep->T_C_REGNUM = 242; | |
4689 | tdep->FPSCR_C_REGNUM = 243; | |
4690 | tdep->FPUL_C_REGNUM = 244; | |
4691 | tdep->FP0_C_REGNUM = 245; | |
4692 | tdep->FP_LAST_C_REGNUM = 260; | |
4693 | tdep->DR0_C_REGNUM = 261; | |
4694 | tdep->DR_LAST_C_REGNUM = 268; | |
4695 | tdep->FV0_C_REGNUM = 269; | |
4696 | tdep->FV_LAST_C_REGNUM = 272; | |
4697 | tdep->ARG0_REGNUM = 2; | |
4698 | tdep->ARGLAST_REGNUM = 9; | |
4699 | tdep->RETURN_REGNUM = 2; | |
4700 | tdep->FLOAT_ARGLAST_REGNUM = 11; | |
4701 | ||
4702 | set_gdbarch_num_pseudo_regs (gdbarch, NUM_PSEUDO_REGS_SH_MEDIA + NUM_PSEUDO_REGS_SH_COMPACT); | |
4703 | set_gdbarch_fp0_regnum (gdbarch, SIM_SH64_FR0_REGNUM); | |
4704 | set_gdbarch_pc_regnum (gdbarch, 64); | |
4705 | ||
4706 | /* Determine the ABI */ | |
4707 | if (bfd_get_arch_size (info.abfd) == 64) | |
4708 | { | |
4709 | /* If the ABI is the 64-bit one, it can only be sh-media. */ | |
4710 | tdep->sh_abi = SH_ABI_64; | |
4711 | set_gdbarch_ptr_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
4712 | set_gdbarch_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
4713 | } | |
4714 | else | |
4715 | { | |
4716 | /* If the ABI is the 32-bit one it could be either media or | |
4717 | compact. */ | |
4718 | tdep->sh_abi = SH_ABI_32; | |
4719 | set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
4720 | set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
4721 | } | |
4722 | ||
4723 | /* the number of real registers is the same whether we are in | |
4724 | ISA16(compact) or ISA32(media). */ | |
4725 | set_gdbarch_num_regs (gdbarch, SIM_SH64_NR_REGS); | |
b1e29e33 | 4726 | set_gdbarch_deprecated_register_size (gdbarch, 8); /*????*/ |
48db5a3c | 4727 | set_gdbarch_deprecated_register_bytes (gdbarch, |
b8b527c5 AC |
4728 | ((SIM_SH64_NR_FP_REGS + 1) * 4) |
4729 | + (SIM_SH64_NR_REGS - SIM_SH64_NR_FP_REGS -1) * 8); | |
283150cd | 4730 | |
48db5a3c | 4731 | set_gdbarch_register_name (gdbarch, sh_sh64_register_name); |
283150cd | 4732 | sh_show_regs = sh64_show_regs; |
48db5a3c CV |
4733 | set_gdbarch_deprecated_register_virtual_type (gdbarch, sh_sh64_register_virtual_type); |
4734 | set_gdbarch_deprecated_store_return_value (gdbarch, sh64_store_return_value); | |
283150cd | 4735 | skip_prologue_hard_way = sh64_skip_prologue_hard_way; |
9c04cab7 AC |
4736 | set_gdbarch_deprecated_register_raw_size (gdbarch, sh_sh64_register_raw_size); |
4737 | set_gdbarch_deprecated_register_virtual_size (gdbarch, sh_sh64_register_raw_size); | |
4738 | set_gdbarch_deprecated_register_byte (gdbarch, sh_sh64_register_byte); | |
283150cd | 4739 | /* This seems awfully wrong!*/ |
a0ed5532 | 4740 | /*set_gdbarch_deprecated_max_register_raw_size (gdbarch, 8);*/ |
283150cd | 4741 | /* should include the size of the pseudo regs. */ |
a0ed5532 | 4742 | set_gdbarch_deprecated_max_register_raw_size (gdbarch, 4 * 4); |
283150cd | 4743 | /* Or should that go in the virtual_size? */ |
a0ed5532 AC |
4744 | /*set_gdbarch_deprecated_max_register_virtual_size (gdbarch, 8);*/ |
4745 | set_gdbarch_deprecated_max_register_virtual_size (gdbarch, 4 * 4); | |
d8124050 AC |
4746 | set_gdbarch_pseudo_register_read (gdbarch, sh64_pseudo_register_read); |
4747 | set_gdbarch_pseudo_register_write (gdbarch, sh64_pseudo_register_write); | |
283150cd | 4748 | |
903ad3a6 | 4749 | set_gdbarch_deprecated_do_registers_info (gdbarch, sh64_do_registers_info); |
f30ee0bc | 4750 | set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh64_nofp_frame_init_saved_regs); |
283150cd | 4751 | set_gdbarch_breakpoint_from_pc (gdbarch, sh_sh64_breakpoint_from_pc); |
48db5a3c CV |
4752 | set_gdbarch_deprecated_call_dummy_words (gdbarch, sh64_call_dummy_words); |
4753 | set_gdbarch_deprecated_sizeof_call_dummy_words (gdbarch, sizeof (sh64_call_dummy_words)); | |
4754 | ||
e9582e71 | 4755 | set_gdbarch_deprecated_init_extra_frame_info (gdbarch, sh64_init_extra_frame_info); |
618ce49f | 4756 | set_gdbarch_deprecated_frame_chain (gdbarch, sh64_frame_chain); |
129c1cd6 | 4757 | set_gdbarch_deprecated_get_saved_register (gdbarch, sh64_get_saved_register); |
26e9b323 | 4758 | set_gdbarch_deprecated_extract_return_value (gdbarch, sh64_extract_return_value); |
b81774d8 | 4759 | set_gdbarch_deprecated_push_arguments (gdbarch, sh64_push_arguments); |
48db5a3c CV |
4760 | set_gdbarch_deprecated_push_return_address (gdbarch, sh64_push_return_address); |
4761 | set_gdbarch_deprecated_dummy_write_sp (gdbarch, deprecated_write_sp); | |
4762 | set_gdbarch_deprecated_store_struct_return (gdbarch, sh64_store_struct_return); | |
26e9b323 | 4763 | set_gdbarch_deprecated_extract_struct_value_address (gdbarch, sh64_extract_struct_value_address); |
283150cd | 4764 | set_gdbarch_use_struct_convention (gdbarch, sh64_use_struct_convention); |
749b82f6 | 4765 | set_gdbarch_deprecated_pop_frame (gdbarch, sh64_pop_frame); |
283150cd EZ |
4766 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
4767 | sh64_elf_make_msymbol_special); | |
4768 | break; | |
cc17453a | 4769 | default: |
48db5a3c CV |
4770 | set_gdbarch_register_name (gdbarch, sh_generic_register_name); |
4771 | set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info); | |
cc17453a | 4772 | sh_show_regs = sh_generic_show_regs; |
48db5a3c CV |
4773 | set_gdbarch_register_type (gdbarch, sh_default_register_type); |
4774 | set_gdbarch_push_dummy_code (gdbarch, sh_push_dummy_code); | |
4775 | set_gdbarch_store_return_value (gdbarch, sh_default_store_return_value); | |
4776 | set_gdbarch_extract_return_value (gdbarch, sh_default_extract_return_value); | |
4777 | ||
f30ee0bc | 4778 | set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs); |
cc17453a | 4779 | break; |
8db62801 | 4780 | } |
cc17453a | 4781 | |
4be87837 DJ |
4782 | /* Hook in ABI-specific overrides, if they have been registered. */ |
4783 | gdbarch_init_osabi (info, gdbarch); | |
d658f924 | 4784 | |
cc17453a | 4785 | return gdbarch; |
8db62801 EZ |
4786 | } |
4787 | ||
d658f924 JT |
4788 | static void |
4789 | sh_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
4790 | { | |
4791 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
4792 | ||
4793 | if (tdep == NULL) | |
4794 | return; | |
4795 | ||
4be87837 | 4796 | /* FIXME: dump the rest of gdbarch_tdep. */ |
d658f924 JT |
4797 | } |
4798 | ||
a78f21af AC |
4799 | extern initialize_file_ftype _initialize_sh_tdep; /* -Wmissing-prototypes */ |
4800 | ||
c906108c | 4801 | void |
fba45db2 | 4802 | _initialize_sh_tdep (void) |
c906108c SS |
4803 | { |
4804 | struct cmd_list_element *c; | |
cc17453a | 4805 | |
d658f924 | 4806 | gdbarch_register (bfd_arch_sh, sh_gdbarch_init, sh_dump_tdep); |
c906108c | 4807 | |
53116e27 | 4808 | add_com ("regs", class_vars, sh_show_regs_command, "Print all registers"); |
c906108c | 4809 | } |