Commit | Line | Data |
---|---|---|
c906108c | 1 | /* Target-dependent code for Hitachi Super-H, for GDB. |
1e698235 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 |
3116c80a | 3 | Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b JM |
17 | You should have received a copy of the GNU General Public License |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
21 | |
22 | /* | |
c5aa993b JM |
23 | Contributed by Steve Chamberlain |
24 | sac@cygnus.com | |
c906108c SS |
25 | */ |
26 | ||
27 | #include "defs.h" | |
28 | #include "frame.h" | |
c906108c SS |
29 | #include "symtab.h" |
30 | #include "symfile.h" | |
31 | #include "gdbtypes.h" | |
32 | #include "gdbcmd.h" | |
33 | #include "gdbcore.h" | |
34 | #include "value.h" | |
35 | #include "dis-asm.h" | |
73c1f219 | 36 | #include "inferior.h" |
c906108c | 37 | #include "gdb_string.h" |
b4a20239 | 38 | #include "arch-utils.h" |
fb409745 | 39 | #include "floatformat.h" |
4e052eda | 40 | #include "regcache.h" |
d16aafd8 | 41 | #include "doublest.h" |
4be87837 | 42 | #include "osabi.h" |
c906108c | 43 | |
ab3b8126 JT |
44 | #include "sh-tdep.h" |
45 | ||
d658f924 | 46 | #include "elf-bfd.h" |
1a8629c7 MS |
47 | #include "solib-svr4.h" |
48 | ||
55ff77ac | 49 | /* sh flags */ |
283150cd EZ |
50 | #include "elf/sh.h" |
51 | /* registers numbers shared with the simulator */ | |
1c922164 | 52 | #include "gdb/sim-sh.h" |
283150cd | 53 | |
55ff77ac | 54 | static void (*sh_show_regs) (void); |
cc17453a | 55 | |
f2ea0907 | 56 | #define SH_NUM_REGS 59 |
88e04cc1 | 57 | |
cc17453a EZ |
58 | /* Define other aspects of the stack frame. |
59 | we keep a copy of the worked out return pc lying around, since it | |
60 | is a useful bit of info */ | |
61 | ||
62 | struct frame_extra_info | |
63 | { | |
64 | CORE_ADDR return_pc; | |
65 | int leaf_function; | |
66 | int f_offset; | |
63978407 | 67 | }; |
c906108c | 68 | |
fa88f677 | 69 | static const char * |
cc17453a | 70 | sh_generic_register_name (int reg_nr) |
c5aa993b | 71 | { |
cc17453a | 72 | static char *register_names[] = |
c5aa993b | 73 | { |
cc17453a EZ |
74 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
75 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
76 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
77 | "fpul", "fpscr", | |
78 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", | |
79 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
80 | "ssr", "spc", | |
81 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", | |
82 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", | |
83 | }; | |
84 | if (reg_nr < 0) | |
85 | return NULL; | |
86 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
87 | return NULL; | |
88 | return register_names[reg_nr]; | |
89 | } | |
90 | ||
fa88f677 | 91 | static const char * |
cc17453a EZ |
92 | sh_sh_register_name (int reg_nr) |
93 | { | |
94 | static char *register_names[] = | |
63978407 | 95 | { |
cc17453a EZ |
96 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
97 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
98 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
99 | "", "", | |
100 | "", "", "", "", "", "", "", "", | |
101 | "", "", "", "", "", "", "", "", | |
102 | "", "", | |
103 | "", "", "", "", "", "", "", "", | |
104 | "", "", "", "", "", "", "", "", | |
105 | }; | |
106 | if (reg_nr < 0) | |
107 | return NULL; | |
108 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
109 | return NULL; | |
110 | return register_names[reg_nr]; | |
111 | } | |
112 | ||
fa88f677 | 113 | static const char * |
cc17453a EZ |
114 | sh_sh3_register_name (int reg_nr) |
115 | { | |
116 | static char *register_names[] = | |
c5aa993b | 117 | { |
cc17453a EZ |
118 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
119 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
120 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
121 | "", "", | |
122 | "", "", "", "", "", "", "", "", | |
123 | "", "", "", "", "", "", "", "", | |
124 | "ssr", "spc", | |
125 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", | |
126 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1" | |
127 | }; | |
128 | if (reg_nr < 0) | |
129 | return NULL; | |
130 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
131 | return NULL; | |
132 | return register_names[reg_nr]; | |
133 | } | |
134 | ||
fa88f677 | 135 | static const char * |
cc17453a EZ |
136 | sh_sh3e_register_name (int reg_nr) |
137 | { | |
138 | static char *register_names[] = | |
63978407 | 139 | { |
cc17453a EZ |
140 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
141 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
142 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
143 | "fpul", "fpscr", | |
144 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", | |
145 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
146 | "ssr", "spc", | |
147 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", | |
148 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", | |
149 | }; | |
150 | if (reg_nr < 0) | |
151 | return NULL; | |
152 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
153 | return NULL; | |
154 | return register_names[reg_nr]; | |
155 | } | |
156 | ||
2d188dd3 NC |
157 | static const char * |
158 | sh_sh2e_register_name (int reg_nr) | |
159 | { | |
160 | static char *register_names[] = | |
161 | { | |
162 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
163 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
164 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
165 | "fpul", "fpscr", | |
166 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", | |
167 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
168 | "", "", | |
169 | "", "", "", "", "", "", "", "", | |
170 | "", "", "", "", "", "", "", "", | |
171 | }; | |
172 | if (reg_nr < 0) | |
173 | return NULL; | |
174 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
175 | return NULL; | |
176 | return register_names[reg_nr]; | |
177 | } | |
178 | ||
fa88f677 | 179 | static const char * |
cc17453a EZ |
180 | sh_sh_dsp_register_name (int reg_nr) |
181 | { | |
182 | static char *register_names[] = | |
c5aa993b | 183 | { |
cc17453a EZ |
184 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
185 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
186 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
187 | "", "dsr", | |
188 | "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1", | |
189 | "y0", "y1", "", "", "", "", "", "mod", | |
190 | "", "", | |
191 | "rs", "re", "", "", "", "", "", "", | |
192 | "", "", "", "", "", "", "", "", | |
193 | }; | |
194 | if (reg_nr < 0) | |
195 | return NULL; | |
196 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
197 | return NULL; | |
198 | return register_names[reg_nr]; | |
199 | } | |
200 | ||
fa88f677 | 201 | static const char * |
cc17453a EZ |
202 | sh_sh3_dsp_register_name (int reg_nr) |
203 | { | |
204 | static char *register_names[] = | |
c5aa993b | 205 | { |
cc17453a EZ |
206 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
207 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
208 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
209 | "", "dsr", | |
210 | "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1", | |
211 | "y0", "y1", "", "", "", "", "", "mod", | |
212 | "ssr", "spc", | |
213 | "rs", "re", "", "", "", "", "", "", | |
214 | "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b" | |
215 | "", "", "", "", "", "", "", "", | |
216 | }; | |
217 | if (reg_nr < 0) | |
218 | return NULL; | |
219 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
220 | return NULL; | |
221 | return register_names[reg_nr]; | |
222 | } | |
223 | ||
fa88f677 | 224 | static const char * |
53116e27 EZ |
225 | sh_sh4_register_name (int reg_nr) |
226 | { | |
227 | static char *register_names[] = | |
228 | { | |
a38d2a54 | 229 | /* general registers 0-15 */ |
53116e27 EZ |
230 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
231 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
a38d2a54 | 232 | /* 16 - 22 */ |
53116e27 | 233 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", |
a38d2a54 | 234 | /* 23, 24 */ |
53116e27 | 235 | "fpul", "fpscr", |
a38d2a54 | 236 | /* floating point registers 25 - 40 */ |
53116e27 EZ |
237 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", |
238 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
a38d2a54 | 239 | /* 41, 42 */ |
53116e27 | 240 | "ssr", "spc", |
a38d2a54 | 241 | /* bank 0 43 - 50 */ |
53116e27 | 242 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", |
a38d2a54 | 243 | /* bank 1 51 - 58 */ |
53116e27 | 244 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", |
a38d2a54 | 245 | /* double precision (pseudo) 59 - 66 */ |
fe9f384f | 246 | "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", |
a38d2a54 | 247 | /* vectors (pseudo) 67 - 70 */ |
fe9f384f | 248 | "fv0", "fv4", "fv8", "fv12", |
a38d2a54 EZ |
249 | /* FIXME: missing XF 71 - 86 */ |
250 | /* FIXME: missing XD 87 - 94 */ | |
53116e27 EZ |
251 | }; |
252 | if (reg_nr < 0) | |
253 | return NULL; | |
254 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
255 | return NULL; | |
256 | return register_names[reg_nr]; | |
257 | } | |
258 | ||
3117ed25 | 259 | static const unsigned char * |
fba45db2 | 260 | sh_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
cc17453a EZ |
261 | { |
262 | /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */ | |
263 | static unsigned char breakpoint[] = {0xc3, 0xc3}; | |
264 | ||
265 | *lenptr = sizeof (breakpoint); | |
266 | return breakpoint; | |
267 | } | |
c906108c | 268 | |
48db5a3c CV |
269 | static CORE_ADDR |
270 | sh_push_dummy_code (struct gdbarch *gdbarch, | |
271 | CORE_ADDR sp, CORE_ADDR funaddr, int using_gcc, | |
272 | struct value **args, int nargs, | |
273 | struct type *value_type, | |
274 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr) | |
275 | { | |
276 | /* Allocate space sufficient for a breakpoint. */ | |
277 | sp = (sp - 2) & ~1; | |
278 | /* Store the address of that breakpoint */ | |
279 | *bp_addr = sp; | |
280 | /* sh always starts the call at the callee's entry point. */ | |
281 | *real_pc = funaddr; | |
282 | return sp; | |
283 | } | |
284 | ||
c906108c | 285 | /* Prologue looks like |
c5aa993b JM |
286 | [mov.l <regs>,@-r15]... |
287 | [sts.l pr,@-r15] | |
288 | [mov.l r14,@-r15] | |
289 | [mov r15,r14] | |
8db62801 EZ |
290 | |
291 | Actually it can be more complicated than this. For instance, with | |
292 | newer gcc's: | |
293 | ||
294 | mov.l r14,@-r15 | |
295 | add #-12,r15 | |
296 | mov r15,r14 | |
297 | mov r4,r1 | |
298 | mov r5,r2 | |
299 | mov.l r6,@(4,r14) | |
300 | mov.l r7,@(8,r14) | |
301 | mov.b r1,@r14 | |
302 | mov r14,r1 | |
303 | mov r14,r1 | |
304 | add #2,r1 | |
305 | mov.w r2,@r1 | |
306 | ||
c5aa993b | 307 | */ |
c906108c | 308 | |
8db62801 EZ |
309 | /* STS.L PR,@-r15 0100111100100010 |
310 | r15-4-->r15, PR-->(r15) */ | |
c906108c | 311 | #define IS_STS(x) ((x) == 0x4f22) |
8db62801 EZ |
312 | |
313 | /* MOV.L Rm,@-r15 00101111mmmm0110 | |
314 | r15-4-->r15, Rm-->(R15) */ | |
c906108c | 315 | #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06) |
8db62801 | 316 | |
c906108c | 317 | #define GET_PUSHED_REG(x) (((x) >> 4) & 0xf) |
8db62801 EZ |
318 | |
319 | /* MOV r15,r14 0110111011110011 | |
320 | r15-->r14 */ | |
c906108c | 321 | #define IS_MOV_SP_FP(x) ((x) == 0x6ef3) |
8db62801 EZ |
322 | |
323 | /* ADD #imm,r15 01111111iiiiiiii | |
324 | r15+imm-->r15 */ | |
f2ea0907 | 325 | #define IS_ADD_IMM_SP(x) (((x) & 0xff00) == 0x7f00) |
8db62801 | 326 | |
c906108c SS |
327 | #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00) |
328 | #define IS_SHLL_R3(x) ((x) == 0x4300) | |
8db62801 EZ |
329 | |
330 | /* ADD r3,r15 0011111100111100 | |
331 | r15+r3-->r15 */ | |
c906108c | 332 | #define IS_ADD_R3SP(x) ((x) == 0x3f3c) |
8db62801 EZ |
333 | |
334 | /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011 | |
8db62801 | 335 | FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011 |
8db62801 | 336 | FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */ |
f2ea0907 CV |
337 | /* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to |
338 | make this entirely clear. */ | |
339 | #define IS_FPUSH(x) (((x) & 0xf00f) == 0xf00b) | |
c906108c | 340 | |
8db62801 | 341 | /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 |
8db62801 | 342 | MOV.L Rm,@(disp,Rn) Rm-->(dispx4+Rn) 0001nnnnmmmmdddd |
8db62801 EZ |
343 | MOV.L Rm,@Rn Rm-->(Rn) 0010nnnnmmmm0010 |
344 | where Rm is one of r4,r5,r6,r7 which are the argument registers. */ | |
345 | #define IS_ARG_MOV(x) \ | |
346 | (((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) \ | |
cc17453a EZ |
347 | || ((((x) & 0xf000) == 0x1000) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) \ |
348 | || ((((x) & 0xf00f) == 0x2002) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070))) | |
8db62801 EZ |
349 | |
350 | /* MOV.L Rm,@(disp,r14) 00011110mmmmdddd | |
351 | Rm-->(dispx4+r14) where Rm is one of r4,r5,r6,r7 */ | |
3bbfbb92 | 352 | #define IS_MOV_TO_R14(x) \ |
cc17453a | 353 | ((((x) & 0xff00) == 0x1e) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) |
8db62801 EZ |
354 | |
355 | #define FPSCR_SZ (1 << 20) | |
c906108c | 356 | |
c906108c SS |
357 | /* Skip any prologue before the guts of a function */ |
358 | ||
8db62801 EZ |
359 | /* Skip the prologue using the debug information. If this fails we'll |
360 | fall back on the 'guess' method below. */ | |
361 | static CORE_ADDR | |
fba45db2 | 362 | after_prologue (CORE_ADDR pc) |
8db62801 EZ |
363 | { |
364 | struct symtab_and_line sal; | |
365 | CORE_ADDR func_addr, func_end; | |
366 | ||
367 | /* If we can not find the symbol in the partial symbol table, then | |
368 | there is no hope we can determine the function's start address | |
369 | with this code. */ | |
370 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
371 | return 0; | |
372 | ||
373 | /* Get the line associated with FUNC_ADDR. */ | |
374 | sal = find_pc_line (func_addr, 0); | |
375 | ||
376 | /* There are only two cases to consider. First, the end of the source line | |
377 | is within the function bounds. In that case we return the end of the | |
378 | source line. Second is the end of the source line extends beyond the | |
379 | bounds of the current function. We need to use the slow code to | |
380 | examine instructions in that case. */ | |
381 | if (sal.end < func_end) | |
382 | return sal.end; | |
383 | else | |
384 | return 0; | |
385 | } | |
386 | ||
387 | /* Here we look at each instruction in the function, and try to guess | |
388 | where the prologue ends. Unfortunately this is not always | |
389 | accurate. */ | |
390 | static CORE_ADDR | |
3bbfbb92 | 391 | sh_skip_prologue_hard_way (CORE_ADDR start_pc) |
c906108c | 392 | { |
2bfa91ee | 393 | CORE_ADDR here, end; |
8db62801 | 394 | int updated_fp = 0; |
2bfa91ee EZ |
395 | |
396 | if (!start_pc) | |
397 | return 0; | |
398 | ||
399 | for (here = start_pc, end = start_pc + (2 * 28); here < end;) | |
c906108c | 400 | { |
2bfa91ee EZ |
401 | int w = read_memory_integer (here, 2); |
402 | here += 2; | |
f2ea0907 CV |
403 | if (IS_FPUSH (w) || IS_PUSH (w) || IS_STS (w) || IS_MOV_R3 (w) |
404 | || IS_ADD_R3SP (w) || IS_ADD_IMM_SP (w) || IS_SHLL_R3 (w) | |
3bbfbb92 | 405 | || IS_ARG_MOV (w) || IS_MOV_TO_R14 (w)) |
2bfa91ee EZ |
406 | { |
407 | start_pc = here; | |
2bfa91ee | 408 | } |
8db62801 EZ |
409 | else if (IS_MOV_SP_FP (w)) |
410 | { | |
411 | start_pc = here; | |
412 | updated_fp = 1; | |
413 | } | |
414 | else | |
415 | /* Don't bail out yet, if we are before the copy of sp. */ | |
416 | if (updated_fp) | |
417 | break; | |
c906108c SS |
418 | } |
419 | ||
420 | return start_pc; | |
421 | } | |
422 | ||
cc17453a | 423 | static CORE_ADDR |
fba45db2 | 424 | sh_skip_prologue (CORE_ADDR pc) |
8db62801 EZ |
425 | { |
426 | CORE_ADDR post_prologue_pc; | |
427 | ||
428 | /* See if we can determine the end of the prologue via the symbol table. | |
429 | If so, then return either PC, or the PC after the prologue, whichever | |
430 | is greater. */ | |
8db62801 EZ |
431 | post_prologue_pc = after_prologue (pc); |
432 | ||
433 | /* If after_prologue returned a useful address, then use it. Else | |
434 | fall back on the instruction skipping code. */ | |
435 | if (post_prologue_pc != 0) | |
436 | return max (pc, post_prologue_pc); | |
437 | else | |
55ff77ac | 438 | return sh_skip_prologue_hard_way (pc); |
8db62801 EZ |
439 | } |
440 | ||
cc17453a EZ |
441 | /* Immediately after a function call, return the saved pc. |
442 | Can't always go through the frames for this because on some machines | |
443 | the new frame is not set up until the new function executes | |
444 | some instructions. | |
445 | ||
446 | The return address is the value saved in the PR register + 4 */ | |
447 | static CORE_ADDR | |
fba45db2 | 448 | sh_saved_pc_after_call (struct frame_info *frame) |
cc17453a | 449 | { |
55ff77ac | 450 | return (ADDR_BITS_REMOVE (read_register (PR_REGNUM))); |
cc17453a EZ |
451 | } |
452 | ||
453 | /* Should call_function allocate stack space for a struct return? */ | |
454 | static int | |
fba45db2 | 455 | sh_use_struct_convention (int gcc_p, struct type *type) |
cc17453a | 456 | { |
7079c36c | 457 | #if 0 |
cc17453a | 458 | return (TYPE_LENGTH (type) > 1); |
7079c36c CV |
459 | #else |
460 | int len = TYPE_LENGTH (type); | |
461 | int nelem = TYPE_NFIELDS (type); | |
462 | return ((len != 1 && len != 2 && len != 4 && len != 8) || nelem != 1) && | |
463 | (len != 8 || TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) != 4); | |
464 | #endif | |
cc17453a EZ |
465 | } |
466 | ||
cc17453a EZ |
467 | /* Disassemble an instruction. */ |
468 | static int | |
fba45db2 | 469 | gdb_print_insn_sh (bfd_vma memaddr, disassemble_info *info) |
c906108c | 470 | { |
1c509ca8 JR |
471 | info->endian = TARGET_BYTE_ORDER; |
472 | return print_insn_sh (memaddr, info); | |
283150cd EZ |
473 | } |
474 | ||
a5afb99f AC |
475 | /* Given a GDB frame, determine the address of the calling function's |
476 | frame. This will be used to create a new GDB frame struct, and | |
e9582e71 AC |
477 | then DEPRECATED_INIT_EXTRA_FRAME_INFO and DEPRECATED_INIT_FRAME_PC |
478 | will be called for the new frame. | |
c906108c SS |
479 | |
480 | For us, the frame address is its stack pointer value, so we look up | |
481 | the function prologue to determine the caller's sp value, and return it. */ | |
cc17453a | 482 | static CORE_ADDR |
fba45db2 | 483 | sh_frame_chain (struct frame_info *frame) |
c906108c | 484 | { |
1e2330ba AC |
485 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), |
486 | get_frame_base (frame), | |
487 | get_frame_base (frame))) | |
488 | return get_frame_base (frame); /* dummy frame same as caller's frame */ | |
627b3ba2 AC |
489 | if (get_frame_pc (frame) |
490 | && !deprecated_inside_entry_file (get_frame_pc (frame))) | |
da50a4b7 AC |
491 | return read_memory_integer (get_frame_base (frame) |
492 | + get_frame_extra_info (frame)->f_offset, 4); | |
c906108c SS |
493 | else |
494 | return 0; | |
495 | } | |
496 | ||
497 | /* Find REGNUM on the stack. Otherwise, it's in an active register. One thing | |
498 | we might want to do here is to check REGNUM against the clobber mask, and | |
499 | somehow flag it as invalid if it isn't saved on the stack somewhere. This | |
500 | would provide a graceful failure mode when trying to get the value of | |
501 | caller-saves registers for an inner frame. */ | |
cc17453a | 502 | static CORE_ADDR |
fba45db2 | 503 | sh_find_callers_reg (struct frame_info *fi, int regnum) |
c906108c | 504 | { |
11c02a10 | 505 | for (; fi; fi = get_next_frame (fi)) |
1e2330ba AC |
506 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), get_frame_base (fi), |
507 | get_frame_base (fi))) | |
c906108c | 508 | /* When the caller requests PR from the dummy frame, we return PC because |
c5aa993b | 509 | that's where the previous routine appears to have done a call from. */ |
1e2330ba AC |
510 | return deprecated_read_register_dummy (get_frame_pc (fi), |
511 | get_frame_base (fi), regnum); | |
c5aa993b | 512 | else |
c906108c | 513 | { |
f30ee0bc | 514 | DEPRECATED_FRAME_INIT_SAVED_REGS (fi); |
50abf9e5 | 515 | if (!get_frame_pc (fi)) |
2bfa91ee | 516 | return 0; |
b2fb4676 AC |
517 | if (get_frame_saved_regs (fi)[regnum] != 0) |
518 | return read_memory_integer (get_frame_saved_regs (fi)[regnum], | |
48db5a3c | 519 | register_size (current_gdbarch, regnum)); |
c906108c SS |
520 | } |
521 | return read_register (regnum); | |
522 | } | |
523 | ||
524 | /* Put here the code to store, into a struct frame_saved_regs, the | |
525 | addresses of the saved registers of frame described by FRAME_INFO. | |
526 | This includes special registers such as pc and fp saved in special | |
527 | ways in the stack frame. sp is even more special: the address we | |
528 | return for it IS the sp for the next frame. */ | |
cc17453a | 529 | static void |
fba45db2 | 530 | sh_nofp_frame_init_saved_regs (struct frame_info *fi) |
c906108c | 531 | { |
e7d717c0 | 532 | int *where = (int *) alloca ((NUM_REGS + NUM_PSEUDO_REGS) * sizeof(int)); |
c906108c SS |
533 | int rn; |
534 | int have_fp = 0; | |
535 | int depth; | |
536 | int pc; | |
537 | int opc; | |
f2ea0907 | 538 | int inst; |
c906108c | 539 | int r3_val = 0; |
1e2330ba AC |
540 | char *dummy_regs = deprecated_generic_find_dummy_frame (get_frame_pc (fi), |
541 | get_frame_base (fi)); | |
cc17453a | 542 | |
b2fb4676 | 543 | if (get_frame_saved_regs (fi) == NULL) |
cc17453a EZ |
544 | frame_saved_regs_zalloc (fi); |
545 | else | |
b2fb4676 | 546 | memset (get_frame_saved_regs (fi), 0, SIZEOF_FRAME_SAVED_REGS); |
cc17453a EZ |
547 | |
548 | if (dummy_regs) | |
549 | { | |
550 | /* DANGER! This is ONLY going to work if the char buffer format of | |
551 | the saved registers is byte-for-byte identical to the | |
552 | CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */ | |
7b5849cc | 553 | memcpy (get_frame_saved_regs (fi), dummy_regs, SIZEOF_FRAME_SAVED_REGS); |
cc17453a EZ |
554 | return; |
555 | } | |
556 | ||
da50a4b7 AC |
557 | get_frame_extra_info (fi)->leaf_function = 1; |
558 | get_frame_extra_info (fi)->f_offset = 0; | |
cc17453a | 559 | |
cd4bffcf | 560 | for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++) |
cc17453a EZ |
561 | where[rn] = -1; |
562 | ||
563 | depth = 0; | |
564 | ||
f2ea0907 | 565 | /* Loop around examining the prologue inst until we find something |
cc17453a EZ |
566 | that does not appear to be part of the prologue. But give up |
567 | after 20 of them, since we're getting silly then. */ | |
568 | ||
be41e9f4 | 569 | pc = get_frame_func (fi); |
cc17453a EZ |
570 | if (!pc) |
571 | { | |
50abf9e5 | 572 | deprecated_update_frame_pc_hack (fi, 0); |
cc17453a EZ |
573 | return; |
574 | } | |
575 | ||
576 | for (opc = pc + (2 * 28); pc < opc; pc += 2) | |
577 | { | |
f2ea0907 | 578 | inst = read_memory_integer (pc, 2); |
cc17453a | 579 | /* See where the registers will be saved to */ |
f2ea0907 | 580 | if (IS_PUSH (inst)) |
cc17453a | 581 | { |
f2ea0907 | 582 | rn = GET_PUSHED_REG (inst); |
cc17453a EZ |
583 | where[rn] = depth; |
584 | depth += 4; | |
585 | } | |
f2ea0907 | 586 | else if (IS_STS (inst)) |
cc17453a | 587 | { |
55ff77ac | 588 | where[PR_REGNUM] = depth; |
cc17453a | 589 | /* If we're storing the pr then this isn't a leaf */ |
da50a4b7 | 590 | get_frame_extra_info (fi)->leaf_function = 0; |
cc17453a EZ |
591 | depth += 4; |
592 | } | |
f2ea0907 | 593 | else if (IS_MOV_R3 (inst)) |
cc17453a | 594 | { |
f2ea0907 | 595 | r3_val = ((inst & 0xff) ^ 0x80) - 0x80; |
cc17453a | 596 | } |
f2ea0907 | 597 | else if (IS_SHLL_R3 (inst)) |
cc17453a EZ |
598 | { |
599 | r3_val <<= 1; | |
600 | } | |
f2ea0907 | 601 | else if (IS_ADD_R3SP (inst)) |
cc17453a EZ |
602 | { |
603 | depth += -r3_val; | |
604 | } | |
f2ea0907 | 605 | else if (IS_ADD_IMM_SP (inst)) |
cc17453a | 606 | { |
f2ea0907 | 607 | depth -= ((inst & 0xff) ^ 0x80) - 0x80; |
cc17453a | 608 | } |
f2ea0907 | 609 | else if (IS_MOV_SP_FP (inst)) |
cc17453a EZ |
610 | break; |
611 | #if 0 /* This used to just stop when it found an instruction that | |
612 | was not considered part of the prologue. Now, we just | |
613 | keep going looking for likely instructions. */ | |
614 | else | |
615 | break; | |
616 | #endif | |
617 | } | |
618 | ||
619 | /* Now we know how deep things are, we can work out their addresses */ | |
620 | ||
cd4bffcf | 621 | for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++) |
cc17453a EZ |
622 | { |
623 | if (where[rn] >= 0) | |
624 | { | |
0ba6dca9 | 625 | if (rn == DEPRECATED_FP_REGNUM) |
cc17453a | 626 | have_fp = 1; |
c906108c | 627 | |
1e2330ba | 628 | get_frame_saved_regs (fi)[rn] = get_frame_base (fi) - where[rn] + depth - 4; |
cc17453a EZ |
629 | } |
630 | else | |
631 | { | |
b2fb4676 | 632 | get_frame_saved_regs (fi)[rn] = 0; |
cc17453a EZ |
633 | } |
634 | } | |
635 | ||
636 | if (have_fp) | |
637 | { | |
0ba6dca9 | 638 | get_frame_saved_regs (fi)[SP_REGNUM] = read_memory_integer (get_frame_saved_regs (fi)[DEPRECATED_FP_REGNUM], 4); |
cc17453a EZ |
639 | } |
640 | else | |
641 | { | |
1e2330ba | 642 | get_frame_saved_regs (fi)[SP_REGNUM] = get_frame_base (fi) - 4; |
cc17453a EZ |
643 | } |
644 | ||
0ba6dca9 | 645 | get_frame_extra_info (fi)->f_offset = depth - where[DEPRECATED_FP_REGNUM] - 4; |
cc17453a EZ |
646 | /* Work out the return pc - either from the saved pr or the pr |
647 | value */ | |
648 | } | |
649 | ||
3bbfbb92 EZ |
650 | /* For vectors of 4 floating point registers. */ |
651 | static int | |
652 | fv_reg_base_num (int fv_regnum) | |
653 | { | |
654 | int fp_regnum; | |
655 | ||
656 | fp_regnum = FP0_REGNUM + | |
f2ea0907 | 657 | (fv_regnum - FV0_REGNUM) * 4; |
3bbfbb92 EZ |
658 | return fp_regnum; |
659 | } | |
660 | ||
661 | /* For double precision floating point registers, i.e 2 fp regs.*/ | |
662 | static int | |
663 | dr_reg_base_num (int dr_regnum) | |
664 | { | |
665 | int fp_regnum; | |
666 | ||
667 | fp_regnum = FP0_REGNUM + | |
f2ea0907 | 668 | (dr_regnum - DR0_REGNUM) * 2; |
3bbfbb92 EZ |
669 | return fp_regnum; |
670 | } | |
671 | ||
283150cd EZ |
672 | static void |
673 | sh_fp_frame_init_saved_regs (struct frame_info *fi) | |
674 | { | |
ddde02bd | 675 | int *where = (int *) alloca ((NUM_REGS + NUM_PSEUDO_REGS) * sizeof (int)); |
283150cd EZ |
676 | int rn; |
677 | int have_fp = 0; | |
cc17453a EZ |
678 | int depth; |
679 | int pc; | |
680 | int opc; | |
f2ea0907 | 681 | int inst; |
cc17453a | 682 | int r3_val = 0; |
1e2330ba | 683 | char *dummy_regs = deprecated_generic_find_dummy_frame (get_frame_pc (fi), get_frame_base (fi)); |
cc17453a | 684 | |
b2fb4676 | 685 | if (get_frame_saved_regs (fi) == NULL) |
cc17453a EZ |
686 | frame_saved_regs_zalloc (fi); |
687 | else | |
b2fb4676 | 688 | memset (get_frame_saved_regs (fi), 0, SIZEOF_FRAME_SAVED_REGS); |
cc17453a | 689 | |
c906108c SS |
690 | if (dummy_regs) |
691 | { | |
692 | /* DANGER! This is ONLY going to work if the char buffer format of | |
c5aa993b JM |
693 | the saved registers is byte-for-byte identical to the |
694 | CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */ | |
7b5849cc | 695 | memcpy (get_frame_saved_regs (fi), dummy_regs, SIZEOF_FRAME_SAVED_REGS); |
c906108c SS |
696 | return; |
697 | } | |
698 | ||
da50a4b7 AC |
699 | get_frame_extra_info (fi)->leaf_function = 1; |
700 | get_frame_extra_info (fi)->f_offset = 0; | |
c906108c | 701 | |
cd4bffcf | 702 | for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++) |
c906108c SS |
703 | where[rn] = -1; |
704 | ||
705 | depth = 0; | |
706 | ||
f2ea0907 | 707 | /* Loop around examining the prologue inst until we find something |
c906108c SS |
708 | that does not appear to be part of the prologue. But give up |
709 | after 20 of them, since we're getting silly then. */ | |
710 | ||
be41e9f4 | 711 | pc = get_frame_func (fi); |
2bfa91ee | 712 | if (!pc) |
c906108c | 713 | { |
50abf9e5 | 714 | deprecated_update_frame_pc_hack (fi, 0); |
2bfa91ee EZ |
715 | return; |
716 | } | |
717 | ||
718 | for (opc = pc + (2 * 28); pc < opc; pc += 2) | |
719 | { | |
f2ea0907 | 720 | inst = read_memory_integer (pc, 2); |
c906108c | 721 | /* See where the registers will be saved to */ |
f2ea0907 | 722 | if (IS_PUSH (inst)) |
c906108c | 723 | { |
f2ea0907 | 724 | rn = GET_PUSHED_REG (inst); |
c906108c | 725 | where[rn] = depth; |
c906108c SS |
726 | depth += 4; |
727 | } | |
f2ea0907 | 728 | else if (IS_STS (inst)) |
c906108c | 729 | { |
55ff77ac | 730 | where[PR_REGNUM] = depth; |
c906108c | 731 | /* If we're storing the pr then this isn't a leaf */ |
da50a4b7 | 732 | get_frame_extra_info (fi)->leaf_function = 0; |
c906108c SS |
733 | depth += 4; |
734 | } | |
f2ea0907 | 735 | else if (IS_MOV_R3 (inst)) |
c906108c | 736 | { |
f2ea0907 | 737 | r3_val = ((inst & 0xff) ^ 0x80) - 0x80; |
c906108c | 738 | } |
f2ea0907 | 739 | else if (IS_SHLL_R3 (inst)) |
c906108c SS |
740 | { |
741 | r3_val <<= 1; | |
c906108c | 742 | } |
f2ea0907 | 743 | else if (IS_ADD_R3SP (inst)) |
c906108c SS |
744 | { |
745 | depth += -r3_val; | |
c906108c | 746 | } |
f2ea0907 | 747 | else if (IS_ADD_IMM_SP (inst)) |
c906108c | 748 | { |
f2ea0907 | 749 | depth -= ((inst & 0xff) ^ 0x80) - 0x80; |
c906108c | 750 | } |
f2ea0907 | 751 | else if (IS_FPUSH (inst)) |
c906108c | 752 | { |
f2ea0907 | 753 | if (read_register (FPSCR_REGNUM) & FPSCR_SZ) |
c906108c SS |
754 | { |
755 | depth += 8; | |
756 | } | |
757 | else | |
758 | { | |
759 | depth += 4; | |
760 | } | |
761 | } | |
f2ea0907 | 762 | else if (IS_MOV_SP_FP (inst)) |
2bfa91ee EZ |
763 | break; |
764 | #if 0 /* This used to just stop when it found an instruction that | |
765 | was not considered part of the prologue. Now, we just | |
766 | keep going looking for likely instructions. */ | |
c906108c SS |
767 | else |
768 | break; | |
2bfa91ee | 769 | #endif |
c906108c SS |
770 | } |
771 | ||
772 | /* Now we know how deep things are, we can work out their addresses */ | |
773 | ||
cd4bffcf | 774 | for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++) |
c906108c SS |
775 | { |
776 | if (where[rn] >= 0) | |
777 | { | |
0ba6dca9 | 778 | if (rn == DEPRECATED_FP_REGNUM) |
c906108c SS |
779 | have_fp = 1; |
780 | ||
1e2330ba | 781 | get_frame_saved_regs (fi)[rn] = get_frame_base (fi) - where[rn] + depth - 4; |
c906108c SS |
782 | } |
783 | else | |
784 | { | |
b2fb4676 | 785 | get_frame_saved_regs (fi)[rn] = 0; |
c906108c SS |
786 | } |
787 | } | |
788 | ||
789 | if (have_fp) | |
790 | { | |
b2fb4676 | 791 | get_frame_saved_regs (fi)[SP_REGNUM] = |
0ba6dca9 | 792 | read_memory_integer (get_frame_saved_regs (fi)[DEPRECATED_FP_REGNUM], 4); |
c906108c SS |
793 | } |
794 | else | |
795 | { | |
1e2330ba | 796 | get_frame_saved_regs (fi)[SP_REGNUM] = get_frame_base (fi) - 4; |
c906108c SS |
797 | } |
798 | ||
0ba6dca9 | 799 | get_frame_extra_info (fi)->f_offset = depth - where[DEPRECATED_FP_REGNUM] - 4; |
c906108c SS |
800 | /* Work out the return pc - either from the saved pr or the pr |
801 | value */ | |
802 | } | |
803 | ||
cc17453a EZ |
804 | /* Initialize the extra info saved in a FRAME */ |
805 | static void | |
fba45db2 | 806 | sh_init_extra_frame_info (int fromleaf, struct frame_info *fi) |
c906108c | 807 | { |
cc17453a | 808 | |
a00a19e9 | 809 | frame_extra_info_zalloc (fi, sizeof (struct frame_extra_info)); |
c906108c | 810 | |
11c02a10 | 811 | if (get_next_frame (fi)) |
8bedc050 | 812 | deprecated_update_frame_pc_hack (fi, DEPRECATED_FRAME_SAVED_PC (get_next_frame (fi))); |
c906108c | 813 | |
1e2330ba AC |
814 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), get_frame_base (fi), |
815 | get_frame_base (fi))) | |
c906108c | 816 | { |
04714b91 AC |
817 | /* We need to setup fi->frame here because call_function_by_hand |
818 | gets it wrong by assuming it's always FP. */ | |
1e2330ba | 819 | deprecated_update_frame_base_hack (fi, deprecated_read_register_dummy (get_frame_pc (fi), get_frame_base (fi), |
8ccd593b | 820 | SP_REGNUM)); |
da50a4b7 | 821 | get_frame_extra_info (fi)->return_pc = deprecated_read_register_dummy (get_frame_pc (fi), |
1e2330ba | 822 | get_frame_base (fi), |
135c175f | 823 | PC_REGNUM); |
b1e29e33 | 824 | get_frame_extra_info (fi)->f_offset = -(DEPRECATED_CALL_DUMMY_LENGTH + 4); |
da50a4b7 | 825 | get_frame_extra_info (fi)->leaf_function = 0; |
c906108c SS |
826 | return; |
827 | } | |
828 | else | |
829 | { | |
55ff77ac CV |
830 | DEPRECATED_FRAME_INIT_SAVED_REGS (fi); |
831 | get_frame_extra_info (fi)->return_pc = | |
832 | sh_find_callers_reg (fi, PR_REGNUM); | |
283150cd | 833 | } |
283150cd EZ |
834 | } |
835 | ||
cc17453a EZ |
836 | /* Extract from an array REGBUF containing the (raw) register state |
837 | the address in which a function should return its structure value, | |
838 | as a CORE_ADDR (or an expression that can be used as one). */ | |
b3df3fff | 839 | static CORE_ADDR |
48db5a3c | 840 | sh_extract_struct_value_address (struct regcache *regcache) |
cc17453a | 841 | { |
48db5a3c | 842 | ULONGEST addr; |
48db5a3c CV |
843 | regcache_cooked_read_unsigned (regcache, STRUCT_RETURN_REGNUM, &addr); |
844 | return addr; | |
cc17453a EZ |
845 | } |
846 | ||
847 | static CORE_ADDR | |
fba45db2 | 848 | sh_frame_saved_pc (struct frame_info *frame) |
cc17453a | 849 | { |
da50a4b7 | 850 | return (get_frame_extra_info (frame)->return_pc); |
cc17453a EZ |
851 | } |
852 | ||
c906108c SS |
853 | /* Discard from the stack the innermost frame, |
854 | restoring all saved registers. */ | |
cc17453a | 855 | static void |
fba45db2 | 856 | sh_pop_frame (void) |
c906108c | 857 | { |
52f0bd74 AC |
858 | struct frame_info *frame = get_current_frame (); |
859 | CORE_ADDR fp; | |
860 | int regnum; | |
c906108c | 861 | |
1e2330ba AC |
862 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), |
863 | get_frame_base (frame), | |
864 | get_frame_base (frame))) | |
c906108c SS |
865 | generic_pop_dummy_frame (); |
866 | else | |
c5aa993b | 867 | { |
c193f6ac | 868 | fp = get_frame_base (frame); |
f30ee0bc | 869 | DEPRECATED_FRAME_INIT_SAVED_REGS (frame); |
c906108c | 870 | |
c5aa993b | 871 | /* Copy regs from where they were saved in the frame */ |
cd4bffcf | 872 | for (regnum = 0; regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++) |
b2fb4676 | 873 | if (get_frame_saved_regs (frame)[regnum]) |
cd4bffcf | 874 | write_register (regnum, |
b2fb4676 | 875 | read_memory_integer (get_frame_saved_regs (frame)[regnum], 4)); |
c906108c | 876 | |
da50a4b7 | 877 | write_register (PC_REGNUM, get_frame_extra_info (frame)->return_pc); |
c5aa993b JM |
878 | write_register (SP_REGNUM, fp + 4); |
879 | } | |
c906108c SS |
880 | flush_cached_frames (); |
881 | } | |
882 | ||
19f59343 MS |
883 | static CORE_ADDR |
884 | sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp) | |
885 | { | |
886 | return sp & ~3; | |
887 | } | |
888 | ||
55ff77ac | 889 | /* Function: push_dummy_call (formerly push_arguments) |
c906108c SS |
890 | Setup the function arguments for calling a function in the inferior. |
891 | ||
892 | On the Hitachi SH architecture, there are four registers (R4 to R7) | |
893 | which are dedicated for passing function arguments. Up to the first | |
894 | four arguments (depending on size) may go into these registers. | |
895 | The rest go on the stack. | |
896 | ||
6df2bf50 MS |
897 | MVS: Except on SH variants that have floating point registers. |
898 | In that case, float and double arguments are passed in the same | |
899 | manner, but using FP registers instead of GP registers. | |
900 | ||
c906108c SS |
901 | Arguments that are smaller than 4 bytes will still take up a whole |
902 | register or a whole 32-bit word on the stack, and will be | |
903 | right-justified in the register or the stack word. This includes | |
904 | chars, shorts, and small aggregate types. | |
905 | ||
906 | Arguments that are larger than 4 bytes may be split between two or | |
907 | more registers. If there are not enough registers free, an argument | |
908 | may be passed partly in a register (or registers), and partly on the | |
909 | stack. This includes doubles, long longs, and larger aggregates. | |
910 | As far as I know, there is no upper limit to the size of aggregates | |
911 | that will be passed in this way; in other words, the convention of | |
912 | passing a pointer to a large aggregate instead of a copy is not used. | |
913 | ||
6df2bf50 | 914 | MVS: The above appears to be true for the SH variants that do not |
55ff77ac | 915 | have an FPU, however those that have an FPU appear to copy the |
6df2bf50 MS |
916 | aggregate argument onto the stack (and not place it in registers) |
917 | if it is larger than 16 bytes (four GP registers). | |
918 | ||
c906108c SS |
919 | An exceptional case exists for struct arguments (and possibly other |
920 | aggregates such as arrays) if the size is larger than 4 bytes but | |
921 | not a multiple of 4 bytes. In this case the argument is never split | |
922 | between the registers and the stack, but instead is copied in its | |
923 | entirety onto the stack, AND also copied into as many registers as | |
924 | there is room for. In other words, space in registers permitting, | |
925 | two copies of the same argument are passed in. As far as I can tell, | |
926 | only the one on the stack is used, although that may be a function | |
927 | of the level of compiler optimization. I suspect this is a compiler | |
928 | bug. Arguments of these odd sizes are left-justified within the | |
929 | word (as opposed to arguments smaller than 4 bytes, which are | |
930 | right-justified). | |
c5aa993b | 931 | |
c906108c SS |
932 | If the function is to return an aggregate type such as a struct, it |
933 | is either returned in the normal return value register R0 (if its | |
934 | size is no greater than one byte), or else the caller must allocate | |
935 | space into which the callee will copy the return value (if the size | |
936 | is greater than one byte). In this case, a pointer to the return | |
937 | value location is passed into the callee in register R2, which does | |
938 | not displace any of the other arguments passed in via registers R4 | |
939 | to R7. */ | |
940 | ||
cc17453a | 941 | static CORE_ADDR |
6df2bf50 MS |
942 | sh_push_dummy_call_fpu (struct gdbarch *gdbarch, |
943 | CORE_ADDR func_addr, | |
944 | struct regcache *regcache, | |
945 | CORE_ADDR bp_addr, int nargs, | |
946 | struct value **args, | |
947 | CORE_ADDR sp, int struct_return, | |
948 | CORE_ADDR struct_addr) | |
949 | { | |
950 | int stack_offset, stack_alloc; | |
951 | int argreg, flt_argreg; | |
952 | int argnum; | |
953 | struct type *type; | |
954 | CORE_ADDR regval; | |
955 | char *val; | |
956 | char valbuf[4]; | |
957 | int len; | |
958 | int odd_sized_struct; | |
6df2bf50 MS |
959 | |
960 | /* first force sp to a 4-byte alignment */ | |
961 | sp = sh_frame_align (gdbarch, sp); | |
962 | ||
963 | /* The "struct return pointer" pseudo-argument has its own dedicated | |
964 | register */ | |
965 | if (struct_return) | |
966 | regcache_cooked_write_unsigned (regcache, | |
967 | STRUCT_RETURN_REGNUM, | |
968 | struct_addr); | |
969 | ||
970 | /* Now make sure there's space on the stack */ | |
971 | for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++) | |
972 | stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 3) & ~3); | |
973 | sp -= stack_alloc; /* make room on stack for args */ | |
974 | ||
975 | /* Now load as many as possible of the first arguments into | |
976 | registers, and push the rest onto the stack. There are 16 bytes | |
977 | in four registers available. Loop thru args from first to last. */ | |
978 | ||
55ff77ac CV |
979 | argreg = ARG0_REGNUM; |
980 | flt_argreg = FLOAT_ARG0_REGNUM; | |
6df2bf50 MS |
981 | for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++) |
982 | { | |
983 | type = VALUE_TYPE (args[argnum]); | |
984 | len = TYPE_LENGTH (type); | |
985 | memset (valbuf, 0, sizeof (valbuf)); | |
986 | if (len < 4) | |
987 | { | |
988 | /* value gets right-justified in the register or stack word */ | |
989 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
990 | memcpy (valbuf + (4 - len), | |
991 | (char *) VALUE_CONTENTS (args[argnum]), len); | |
992 | else | |
993 | memcpy (valbuf, (char *) VALUE_CONTENTS (args[argnum]), len); | |
994 | val = valbuf; | |
995 | } | |
996 | else | |
997 | val = (char *) VALUE_CONTENTS (args[argnum]); | |
48db5a3c | 998 | |
6df2bf50 MS |
999 | if (len > 4 && (len & 3) != 0) |
1000 | odd_sized_struct = 1; /* Such structs go entirely on stack. */ | |
1001 | else if (len > 16) | |
1002 | odd_sized_struct = 1; /* So do aggregates bigger than 4 words. */ | |
1003 | else | |
1004 | odd_sized_struct = 0; | |
1005 | while (len > 0) | |
1006 | { | |
1007 | if ((TYPE_CODE (type) == TYPE_CODE_FLT | |
55ff77ac CV |
1008 | && flt_argreg > FLOAT_ARGLAST_REGNUM) |
1009 | || argreg > ARGLAST_REGNUM | |
6df2bf50 MS |
1010 | || odd_sized_struct) |
1011 | { | |
1012 | /* must go on the stack */ | |
1013 | write_memory (sp + stack_offset, val, 4); | |
1014 | stack_offset += 4; | |
1015 | } | |
1016 | /* NOTE WELL!!!!! This is not an "else if" clause!!! | |
1017 | That's because some *&^%$ things get passed on the stack | |
1018 | AND in the registers! */ | |
1019 | if (TYPE_CODE (type) == TYPE_CODE_FLT && | |
55ff77ac | 1020 | flt_argreg > 0 && flt_argreg <= FLOAT_ARGLAST_REGNUM) |
6df2bf50 MS |
1021 | { |
1022 | /* Argument goes in a single-precision fp reg. */ | |
1023 | regval = extract_unsigned_integer (val, register_size (gdbarch, | |
1024 | argreg)); | |
1025 | regcache_cooked_write_unsigned (regcache, flt_argreg++, regval); | |
1026 | } | |
55ff77ac | 1027 | else if (argreg <= ARGLAST_REGNUM) |
6df2bf50 MS |
1028 | { |
1029 | /* there's room in a register */ | |
1030 | regval = extract_unsigned_integer (val, register_size (gdbarch, | |
1031 | argreg)); | |
1032 | regcache_cooked_write_unsigned (regcache, argreg++, regval); | |
1033 | } | |
1034 | /* Store the value 4 bytes at a time. This means that things | |
1035 | larger than 4 bytes may go partly in registers and partly | |
1036 | on the stack. */ | |
1037 | len -= register_size (gdbarch, argreg); | |
1038 | val += register_size (gdbarch, argreg); | |
1039 | } | |
1040 | } | |
1041 | ||
1042 | /* Store return address. */ | |
55ff77ac | 1043 | regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr); |
6df2bf50 MS |
1044 | |
1045 | /* Update stack pointer. */ | |
1046 | regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp); | |
1047 | ||
1048 | return sp; | |
1049 | } | |
1050 | ||
1051 | static CORE_ADDR | |
1052 | sh_push_dummy_call_nofpu (struct gdbarch *gdbarch, | |
1053 | CORE_ADDR func_addr, | |
1054 | struct regcache *regcache, | |
1055 | CORE_ADDR bp_addr, | |
1056 | int nargs, struct value **args, | |
1057 | CORE_ADDR sp, int struct_return, | |
1058 | CORE_ADDR struct_addr) | |
c906108c SS |
1059 | { |
1060 | int stack_offset, stack_alloc; | |
1061 | int argreg; | |
1062 | int argnum; | |
1063 | struct type *type; | |
1064 | CORE_ADDR regval; | |
1065 | char *val; | |
1066 | char valbuf[4]; | |
1067 | int len; | |
1068 | int odd_sized_struct; | |
1069 | ||
1070 | /* first force sp to a 4-byte alignment */ | |
19f59343 | 1071 | sp = sh_frame_align (gdbarch, sp); |
c906108c SS |
1072 | |
1073 | /* The "struct return pointer" pseudo-argument has its own dedicated | |
1074 | register */ | |
1075 | if (struct_return) | |
55ff77ac CV |
1076 | regcache_cooked_write_unsigned (regcache, |
1077 | STRUCT_RETURN_REGNUM, | |
6df2bf50 | 1078 | struct_addr); |
c906108c SS |
1079 | |
1080 | /* Now make sure there's space on the stack */ | |
cc17453a | 1081 | for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++) |
c5aa993b JM |
1082 | stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 3) & ~3); |
1083 | sp -= stack_alloc; /* make room on stack for args */ | |
c906108c | 1084 | |
c906108c SS |
1085 | /* Now load as many as possible of the first arguments into |
1086 | registers, and push the rest onto the stack. There are 16 bytes | |
1087 | in four registers available. Loop thru args from first to last. */ | |
1088 | ||
55ff77ac | 1089 | argreg = ARG0_REGNUM; |
c906108c SS |
1090 | for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++) |
1091 | { | |
1092 | type = VALUE_TYPE (args[argnum]); | |
c5aa993b JM |
1093 | len = TYPE_LENGTH (type); |
1094 | memset (valbuf, 0, sizeof (valbuf)); | |
c906108c | 1095 | if (len < 4) |
cc17453a EZ |
1096 | { |
1097 | /* value gets right-justified in the register or stack word */ | |
7079c36c CV |
1098 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
1099 | memcpy (valbuf + (4 - len), | |
1100 | (char *) VALUE_CONTENTS (args[argnum]), len); | |
1101 | else | |
1102 | memcpy (valbuf, (char *) VALUE_CONTENTS (args[argnum]), len); | |
c5aa993b JM |
1103 | val = valbuf; |
1104 | } | |
c906108c | 1105 | else |
c5aa993b | 1106 | val = (char *) VALUE_CONTENTS (args[argnum]); |
c906108c SS |
1107 | |
1108 | if (len > 4 && (len & 3) != 0) | |
c5aa993b JM |
1109 | odd_sized_struct = 1; /* such structs go entirely on stack */ |
1110 | else | |
c906108c SS |
1111 | odd_sized_struct = 0; |
1112 | while (len > 0) | |
1113 | { | |
55ff77ac | 1114 | if (argreg > ARGLAST_REGNUM |
3bbfbb92 EZ |
1115 | || odd_sized_struct) |
1116 | { | |
1117 | /* must go on the stack */ | |
c906108c SS |
1118 | write_memory (sp + stack_offset, val, 4); |
1119 | stack_offset += 4; | |
1120 | } | |
1121 | /* NOTE WELL!!!!! This is not an "else if" clause!!! | |
1122 | That's because some *&^%$ things get passed on the stack | |
1123 | AND in the registers! */ | |
55ff77ac | 1124 | if (argreg <= ARGLAST_REGNUM) |
3bbfbb92 EZ |
1125 | { |
1126 | /* there's room in a register */ | |
48db5a3c CV |
1127 | regval = extract_unsigned_integer (val, register_size (gdbarch, |
1128 | argreg)); | |
1129 | regcache_cooked_write_unsigned (regcache, argreg++, regval); | |
c906108c SS |
1130 | } |
1131 | /* Store the value 4 bytes at a time. This means that things | |
1132 | larger than 4 bytes may go partly in registers and partly | |
1133 | on the stack. */ | |
48db5a3c CV |
1134 | len -= register_size (gdbarch, argreg); |
1135 | val += register_size (gdbarch, argreg); | |
c906108c SS |
1136 | } |
1137 | } | |
48db5a3c CV |
1138 | |
1139 | /* Store return address. */ | |
55ff77ac | 1140 | regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr); |
48db5a3c CV |
1141 | |
1142 | /* Update stack pointer. */ | |
1143 | regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp); | |
1144 | ||
c906108c SS |
1145 | return sp; |
1146 | } | |
1147 | ||
cc17453a EZ |
1148 | /* Find a function's return value in the appropriate registers (in |
1149 | regbuf), and copy it into valbuf. Extract from an array REGBUF | |
1150 | containing the (raw) register state a function return value of type | |
1151 | TYPE, and copy that, in virtual format, into VALBUF. */ | |
1152 | static void | |
48db5a3c CV |
1153 | sh_default_extract_return_value (struct type *type, struct regcache *regcache, |
1154 | void *valbuf) | |
c906108c | 1155 | { |
cc17453a | 1156 | int len = TYPE_LENGTH (type); |
3116c80a EZ |
1157 | int return_register = R0_REGNUM; |
1158 | int offset; | |
1159 | ||
cc17453a | 1160 | if (len <= 4) |
3116c80a | 1161 | { |
48db5a3c CV |
1162 | ULONGEST c; |
1163 | ||
1164 | regcache_cooked_read_unsigned (regcache, R0_REGNUM, &c); | |
1165 | store_unsigned_integer (valbuf, len, c); | |
3116c80a | 1166 | } |
48db5a3c | 1167 | else if (len == 8) |
3116c80a | 1168 | { |
48db5a3c CV |
1169 | int i, regnum = R0_REGNUM; |
1170 | for (i = 0; i < len; i += 4) | |
1171 | regcache_raw_read (regcache, regnum++, (char *)valbuf + i); | |
3116c80a EZ |
1172 | } |
1173 | else | |
1174 | error ("bad size for return value"); | |
1175 | } | |
1176 | ||
1177 | static void | |
48db5a3c CV |
1178 | sh3e_sh4_extract_return_value (struct type *type, struct regcache *regcache, |
1179 | void *valbuf) | |
3116c80a | 1180 | { |
3116c80a | 1181 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
3116c80a | 1182 | { |
48db5a3c CV |
1183 | int len = TYPE_LENGTH (type); |
1184 | int i, regnum = FP0_REGNUM; | |
1185 | for (i = 0; i < len; i += 4) | |
1186 | regcache_raw_read (regcache, regnum++, (char *)valbuf + i); | |
3116c80a | 1187 | } |
cc17453a | 1188 | else |
48db5a3c | 1189 | sh_default_extract_return_value (type, regcache, valbuf); |
cc17453a | 1190 | } |
c906108c | 1191 | |
cc17453a EZ |
1192 | /* Write into appropriate registers a function return value |
1193 | of type TYPE, given in virtual format. | |
1194 | If the architecture is sh4 or sh3e, store a function's return value | |
1195 | in the R0 general register or in the FP0 floating point register, | |
1196 | depending on the type of the return value. In all the other cases | |
3bbfbb92 | 1197 | the result is stored in r0, left-justified. */ |
cc17453a | 1198 | static void |
48db5a3c CV |
1199 | sh_default_store_return_value (struct type *type, struct regcache *regcache, |
1200 | const void *valbuf) | |
cc17453a | 1201 | { |
48db5a3c CV |
1202 | ULONGEST val; |
1203 | int len = TYPE_LENGTH (type); | |
d19b71be | 1204 | |
48db5a3c | 1205 | if (len <= 4) |
d19b71be | 1206 | { |
48db5a3c CV |
1207 | val = extract_unsigned_integer (valbuf, len); |
1208 | regcache_cooked_write_unsigned (regcache, R0_REGNUM, val); | |
d19b71be MS |
1209 | } |
1210 | else | |
48db5a3c CV |
1211 | { |
1212 | int i, regnum = R0_REGNUM; | |
1213 | for (i = 0; i < len; i += 4) | |
1214 | regcache_raw_write (regcache, regnum++, (char *)valbuf + i); | |
1215 | } | |
cc17453a | 1216 | } |
c906108c | 1217 | |
cc17453a | 1218 | static void |
48db5a3c CV |
1219 | sh3e_sh4_store_return_value (struct type *type, struct regcache *regcache, |
1220 | const void *valbuf) | |
cc17453a EZ |
1221 | { |
1222 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
48db5a3c CV |
1223 | { |
1224 | int len = TYPE_LENGTH (type); | |
1225 | int i, regnum = FP0_REGNUM; | |
1226 | for (i = 0; i < len; i += 4) | |
1227 | regcache_raw_write (regcache, regnum++, (char *)valbuf + i); | |
1228 | } | |
cc17453a | 1229 | else |
48db5a3c | 1230 | sh_default_store_return_value (type, regcache, valbuf); |
c906108c SS |
1231 | } |
1232 | ||
1233 | /* Print the registers in a form similar to the E7000 */ | |
1234 | ||
1235 | static void | |
fba45db2 | 1236 | sh_generic_show_regs (void) |
c906108c | 1237 | { |
cc17453a EZ |
1238 | printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", |
1239 | paddr (read_register (PC_REGNUM)), | |
55ff77ac CV |
1240 | (long) read_register (SR_REGNUM), |
1241 | (long) read_register (PR_REGNUM), | |
cc17453a EZ |
1242 | (long) read_register (MACH_REGNUM), |
1243 | (long) read_register (MACL_REGNUM)); | |
1244 | ||
1245 | printf_filtered ("GBR=%08lx VBR=%08lx", | |
1246 | (long) read_register (GBR_REGNUM), | |
1247 | (long) read_register (VBR_REGNUM)); | |
1248 | ||
1249 | printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1250 | (long) read_register (0), | |
1251 | (long) read_register (1), | |
1252 | (long) read_register (2), | |
1253 | (long) read_register (3), | |
1254 | (long) read_register (4), | |
1255 | (long) read_register (5), | |
1256 | (long) read_register (6), | |
1257 | (long) read_register (7)); | |
1258 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1259 | (long) read_register (8), | |
1260 | (long) read_register (9), | |
1261 | (long) read_register (10), | |
1262 | (long) read_register (11), | |
1263 | (long) read_register (12), | |
1264 | (long) read_register (13), | |
1265 | (long) read_register (14), | |
1266 | (long) read_register (15)); | |
1267 | } | |
c906108c | 1268 | |
cc17453a | 1269 | static void |
fba45db2 | 1270 | sh3_show_regs (void) |
cc17453a | 1271 | { |
d4f3574e SS |
1272 | printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", |
1273 | paddr (read_register (PC_REGNUM)), | |
55ff77ac CV |
1274 | (long) read_register (SR_REGNUM), |
1275 | (long) read_register (PR_REGNUM), | |
d4f3574e SS |
1276 | (long) read_register (MACH_REGNUM), |
1277 | (long) read_register (MACL_REGNUM)); | |
1278 | ||
1279 | printf_filtered ("GBR=%08lx VBR=%08lx", | |
1280 | (long) read_register (GBR_REGNUM), | |
1281 | (long) read_register (VBR_REGNUM)); | |
cc17453a | 1282 | printf_filtered (" SSR=%08lx SPC=%08lx", |
f2ea0907 CV |
1283 | (long) read_register (SSR_REGNUM), |
1284 | (long) read_register (SPC_REGNUM)); | |
c906108c | 1285 | |
d4f3574e SS |
1286 | printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
1287 | (long) read_register (0), | |
1288 | (long) read_register (1), | |
1289 | (long) read_register (2), | |
1290 | (long) read_register (3), | |
1291 | (long) read_register (4), | |
1292 | (long) read_register (5), | |
1293 | (long) read_register (6), | |
1294 | (long) read_register (7)); | |
1295 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1296 | (long) read_register (8), | |
1297 | (long) read_register (9), | |
1298 | (long) read_register (10), | |
1299 | (long) read_register (11), | |
1300 | (long) read_register (12), | |
1301 | (long) read_register (13), | |
1302 | (long) read_register (14), | |
1303 | (long) read_register (15)); | |
c906108c SS |
1304 | } |
1305 | ||
53116e27 | 1306 | |
2d188dd3 NC |
1307 | static void |
1308 | sh2e_show_regs (void) | |
1309 | { | |
1310 | printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", | |
1311 | paddr (read_register (PC_REGNUM)), | |
1312 | (long) read_register (SR_REGNUM), | |
1313 | (long) read_register (PR_REGNUM), | |
1314 | (long) read_register (MACH_REGNUM), | |
1315 | (long) read_register (MACL_REGNUM)); | |
1316 | ||
1317 | printf_filtered ("GBR=%08lx VBR=%08lx", | |
1318 | (long) read_register (GBR_REGNUM), | |
1319 | (long) read_register (VBR_REGNUM)); | |
1320 | printf_filtered (" FPUL=%08lx FPSCR=%08lx", | |
f2ea0907 CV |
1321 | (long) read_register (FPUL_REGNUM), |
1322 | (long) read_register (FPSCR_REGNUM)); | |
2d188dd3 NC |
1323 | |
1324 | printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1325 | (long) read_register (0), | |
1326 | (long) read_register (1), | |
1327 | (long) read_register (2), | |
1328 | (long) read_register (3), | |
1329 | (long) read_register (4), | |
1330 | (long) read_register (5), | |
1331 | (long) read_register (6), | |
1332 | (long) read_register (7)); | |
1333 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1334 | (long) read_register (8), | |
1335 | (long) read_register (9), | |
1336 | (long) read_register (10), | |
1337 | (long) read_register (11), | |
1338 | (long) read_register (12), | |
1339 | (long) read_register (13), | |
1340 | (long) read_register (14), | |
1341 | (long) read_register (15)); | |
1342 | ||
1343 | printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), | |
1344 | (long) read_register (FP0_REGNUM + 0), | |
1345 | (long) read_register (FP0_REGNUM + 1), | |
1346 | (long) read_register (FP0_REGNUM + 2), | |
1347 | (long) read_register (FP0_REGNUM + 3), | |
1348 | (long) read_register (FP0_REGNUM + 4), | |
1349 | (long) read_register (FP0_REGNUM + 5), | |
1350 | (long) read_register (FP0_REGNUM + 6), | |
1351 | (long) read_register (FP0_REGNUM + 7)); | |
1352 | printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), | |
1353 | (long) read_register (FP0_REGNUM + 8), | |
1354 | (long) read_register (FP0_REGNUM + 9), | |
1355 | (long) read_register (FP0_REGNUM + 10), | |
1356 | (long) read_register (FP0_REGNUM + 11), | |
1357 | (long) read_register (FP0_REGNUM + 12), | |
1358 | (long) read_register (FP0_REGNUM + 13), | |
1359 | (long) read_register (FP0_REGNUM + 14), | |
1360 | (long) read_register (FP0_REGNUM + 15)); | |
1361 | } | |
1362 | ||
cc17453a | 1363 | static void |
fba45db2 | 1364 | sh3e_show_regs (void) |
cc17453a EZ |
1365 | { |
1366 | printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", | |
1367 | paddr (read_register (PC_REGNUM)), | |
55ff77ac CV |
1368 | (long) read_register (SR_REGNUM), |
1369 | (long) read_register (PR_REGNUM), | |
cc17453a EZ |
1370 | (long) read_register (MACH_REGNUM), |
1371 | (long) read_register (MACL_REGNUM)); | |
1372 | ||
1373 | printf_filtered ("GBR=%08lx VBR=%08lx", | |
1374 | (long) read_register (GBR_REGNUM), | |
1375 | (long) read_register (VBR_REGNUM)); | |
1376 | printf_filtered (" SSR=%08lx SPC=%08lx", | |
f2ea0907 CV |
1377 | (long) read_register (SSR_REGNUM), |
1378 | (long) read_register (SPC_REGNUM)); | |
cc17453a | 1379 | printf_filtered (" FPUL=%08lx FPSCR=%08lx", |
f2ea0907 CV |
1380 | (long) read_register (FPUL_REGNUM), |
1381 | (long) read_register (FPSCR_REGNUM)); | |
c906108c | 1382 | |
cc17453a EZ |
1383 | printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
1384 | (long) read_register (0), | |
1385 | (long) read_register (1), | |
1386 | (long) read_register (2), | |
1387 | (long) read_register (3), | |
1388 | (long) read_register (4), | |
1389 | (long) read_register (5), | |
1390 | (long) read_register (6), | |
1391 | (long) read_register (7)); | |
1392 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1393 | (long) read_register (8), | |
1394 | (long) read_register (9), | |
1395 | (long) read_register (10), | |
1396 | (long) read_register (11), | |
1397 | (long) read_register (12), | |
1398 | (long) read_register (13), | |
1399 | (long) read_register (14), | |
1400 | (long) read_register (15)); | |
1401 | ||
1402 | printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), | |
1403 | (long) read_register (FP0_REGNUM + 0), | |
1404 | (long) read_register (FP0_REGNUM + 1), | |
1405 | (long) read_register (FP0_REGNUM + 2), | |
1406 | (long) read_register (FP0_REGNUM + 3), | |
1407 | (long) read_register (FP0_REGNUM + 4), | |
1408 | (long) read_register (FP0_REGNUM + 5), | |
1409 | (long) read_register (FP0_REGNUM + 6), | |
1410 | (long) read_register (FP0_REGNUM + 7)); | |
1411 | printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), | |
1412 | (long) read_register (FP0_REGNUM + 8), | |
1413 | (long) read_register (FP0_REGNUM + 9), | |
1414 | (long) read_register (FP0_REGNUM + 10), | |
1415 | (long) read_register (FP0_REGNUM + 11), | |
1416 | (long) read_register (FP0_REGNUM + 12), | |
1417 | (long) read_register (FP0_REGNUM + 13), | |
1418 | (long) read_register (FP0_REGNUM + 14), | |
1419 | (long) read_register (FP0_REGNUM + 15)); | |
1420 | } | |
1421 | ||
1422 | static void | |
fba45db2 | 1423 | sh3_dsp_show_regs (void) |
c906108c | 1424 | { |
cc17453a EZ |
1425 | printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", |
1426 | paddr (read_register (PC_REGNUM)), | |
55ff77ac CV |
1427 | (long) read_register (SR_REGNUM), |
1428 | (long) read_register (PR_REGNUM), | |
cc17453a EZ |
1429 | (long) read_register (MACH_REGNUM), |
1430 | (long) read_register (MACL_REGNUM)); | |
c906108c | 1431 | |
cc17453a EZ |
1432 | printf_filtered ("GBR=%08lx VBR=%08lx", |
1433 | (long) read_register (GBR_REGNUM), | |
1434 | (long) read_register (VBR_REGNUM)); | |
1435 | ||
1436 | printf_filtered (" SSR=%08lx SPC=%08lx", | |
f2ea0907 CV |
1437 | (long) read_register (SSR_REGNUM), |
1438 | (long) read_register (SPC_REGNUM)); | |
cc17453a EZ |
1439 | |
1440 | printf_filtered (" DSR=%08lx", | |
f2ea0907 | 1441 | (long) read_register (DSR_REGNUM)); |
cc17453a EZ |
1442 | |
1443 | printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1444 | (long) read_register (0), | |
1445 | (long) read_register (1), | |
1446 | (long) read_register (2), | |
1447 | (long) read_register (3), | |
1448 | (long) read_register (4), | |
1449 | (long) read_register (5), | |
1450 | (long) read_register (6), | |
1451 | (long) read_register (7)); | |
1452 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1453 | (long) read_register (8), | |
1454 | (long) read_register (9), | |
1455 | (long) read_register (10), | |
1456 | (long) read_register (11), | |
1457 | (long) read_register (12), | |
1458 | (long) read_register (13), | |
1459 | (long) read_register (14), | |
1460 | (long) read_register (15)); | |
1461 | ||
1462 | printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n", | |
f2ea0907 CV |
1463 | (long) read_register (A0G_REGNUM) & 0xff, |
1464 | (long) read_register (A0_REGNUM), | |
1465 | (long) read_register (M0_REGNUM), | |
1466 | (long) read_register (X0_REGNUM), | |
1467 | (long) read_register (Y0_REGNUM), | |
1468 | (long) read_register (RS_REGNUM), | |
1469 | (long) read_register (MOD_REGNUM)); | |
cc17453a | 1470 | printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n", |
f2ea0907 CV |
1471 | (long) read_register (A1G_REGNUM) & 0xff, |
1472 | (long) read_register (A1_REGNUM), | |
1473 | (long) read_register (M1_REGNUM), | |
1474 | (long) read_register (X1_REGNUM), | |
1475 | (long) read_register (Y1_REGNUM), | |
1476 | (long) read_register (RE_REGNUM)); | |
c906108c SS |
1477 | } |
1478 | ||
cc17453a | 1479 | static void |
fba45db2 | 1480 | sh4_show_regs (void) |
cc17453a | 1481 | { |
f2ea0907 | 1482 | int pr = read_register (FPSCR_REGNUM) & 0x80000; |
cc17453a EZ |
1483 | printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", |
1484 | paddr (read_register (PC_REGNUM)), | |
55ff77ac CV |
1485 | (long) read_register (SR_REGNUM), |
1486 | (long) read_register (PR_REGNUM), | |
cc17453a EZ |
1487 | (long) read_register (MACH_REGNUM), |
1488 | (long) read_register (MACL_REGNUM)); | |
1489 | ||
1490 | printf_filtered ("GBR=%08lx VBR=%08lx", | |
1491 | (long) read_register (GBR_REGNUM), | |
1492 | (long) read_register (VBR_REGNUM)); | |
1493 | printf_filtered (" SSR=%08lx SPC=%08lx", | |
f2ea0907 CV |
1494 | (long) read_register (SSR_REGNUM), |
1495 | (long) read_register (SPC_REGNUM)); | |
cc17453a | 1496 | printf_filtered (" FPUL=%08lx FPSCR=%08lx", |
f2ea0907 CV |
1497 | (long) read_register (FPUL_REGNUM), |
1498 | (long) read_register (FPSCR_REGNUM)); | |
cc17453a EZ |
1499 | |
1500 | printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1501 | (long) read_register (0), | |
1502 | (long) read_register (1), | |
1503 | (long) read_register (2), | |
1504 | (long) read_register (3), | |
1505 | (long) read_register (4), | |
1506 | (long) read_register (5), | |
1507 | (long) read_register (6), | |
1508 | (long) read_register (7)); | |
1509 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1510 | (long) read_register (8), | |
1511 | (long) read_register (9), | |
1512 | (long) read_register (10), | |
1513 | (long) read_register (11), | |
1514 | (long) read_register (12), | |
1515 | (long) read_register (13), | |
1516 | (long) read_register (14), | |
1517 | (long) read_register (15)); | |
1518 | ||
1519 | printf_filtered ((pr | |
1520 | ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n" | |
1521 | : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), | |
1522 | (long) read_register (FP0_REGNUM + 0), | |
1523 | (long) read_register (FP0_REGNUM + 1), | |
1524 | (long) read_register (FP0_REGNUM + 2), | |
1525 | (long) read_register (FP0_REGNUM + 3), | |
1526 | (long) read_register (FP0_REGNUM + 4), | |
1527 | (long) read_register (FP0_REGNUM + 5), | |
1528 | (long) read_register (FP0_REGNUM + 6), | |
1529 | (long) read_register (FP0_REGNUM + 7)); | |
1530 | printf_filtered ((pr | |
1531 | ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n" | |
1532 | : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), | |
1533 | (long) read_register (FP0_REGNUM + 8), | |
1534 | (long) read_register (FP0_REGNUM + 9), | |
1535 | (long) read_register (FP0_REGNUM + 10), | |
1536 | (long) read_register (FP0_REGNUM + 11), | |
1537 | (long) read_register (FP0_REGNUM + 12), | |
1538 | (long) read_register (FP0_REGNUM + 13), | |
1539 | (long) read_register (FP0_REGNUM + 14), | |
1540 | (long) read_register (FP0_REGNUM + 15)); | |
1541 | } | |
1542 | ||
1543 | static void | |
fba45db2 | 1544 | sh_dsp_show_regs (void) |
cc17453a EZ |
1545 | { |
1546 | printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", | |
1547 | paddr (read_register (PC_REGNUM)), | |
55ff77ac CV |
1548 | (long) read_register (SR_REGNUM), |
1549 | (long) read_register (PR_REGNUM), | |
cc17453a EZ |
1550 | (long) read_register (MACH_REGNUM), |
1551 | (long) read_register (MACL_REGNUM)); | |
1552 | ||
1553 | printf_filtered ("GBR=%08lx VBR=%08lx", | |
1554 | (long) read_register (GBR_REGNUM), | |
1555 | (long) read_register (VBR_REGNUM)); | |
1556 | ||
1557 | printf_filtered (" DSR=%08lx", | |
f2ea0907 | 1558 | (long) read_register (DSR_REGNUM)); |
cc17453a EZ |
1559 | |
1560 | printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1561 | (long) read_register (0), | |
1562 | (long) read_register (1), | |
1563 | (long) read_register (2), | |
1564 | (long) read_register (3), | |
1565 | (long) read_register (4), | |
1566 | (long) read_register (5), | |
1567 | (long) read_register (6), | |
1568 | (long) read_register (7)); | |
1569 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1570 | (long) read_register (8), | |
1571 | (long) read_register (9), | |
1572 | (long) read_register (10), | |
1573 | (long) read_register (11), | |
1574 | (long) read_register (12), | |
1575 | (long) read_register (13), | |
1576 | (long) read_register (14), | |
1577 | (long) read_register (15)); | |
1578 | ||
1579 | printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n", | |
f2ea0907 CV |
1580 | (long) read_register (A0G_REGNUM) & 0xff, |
1581 | (long) read_register (A0_REGNUM), | |
1582 | (long) read_register (M0_REGNUM), | |
1583 | (long) read_register (X0_REGNUM), | |
1584 | (long) read_register (Y0_REGNUM), | |
1585 | (long) read_register (RS_REGNUM), | |
1586 | (long) read_register (MOD_REGNUM)); | |
cc17453a | 1587 | printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n", |
f2ea0907 CV |
1588 | (long) read_register (A1G_REGNUM) & 0xff, |
1589 | (long) read_register (A1_REGNUM), | |
1590 | (long) read_register (M1_REGNUM), | |
1591 | (long) read_register (X1_REGNUM), | |
1592 | (long) read_register (Y1_REGNUM), | |
1593 | (long) read_register (RE_REGNUM)); | |
cc17453a EZ |
1594 | } |
1595 | ||
a78f21af AC |
1596 | static void |
1597 | sh_show_regs_command (char *args, int from_tty) | |
53116e27 EZ |
1598 | { |
1599 | if (sh_show_regs) | |
1600 | (*sh_show_regs)(); | |
1601 | } | |
1602 | ||
cc17453a EZ |
1603 | /* Return the GDB type object for the "standard" data type |
1604 | of data in register N. */ | |
cc17453a | 1605 | static struct type * |
48db5a3c | 1606 | sh_sh3e_register_type (struct gdbarch *gdbarch, int reg_nr) |
cc17453a EZ |
1607 | { |
1608 | if ((reg_nr >= FP0_REGNUM | |
f2ea0907 CV |
1609 | && (reg_nr <= FP_LAST_REGNUM)) |
1610 | || (reg_nr == FPUL_REGNUM)) | |
cc17453a | 1611 | return builtin_type_float; |
8db62801 | 1612 | else |
cc17453a EZ |
1613 | return builtin_type_int; |
1614 | } | |
1615 | ||
7f4dbe94 EZ |
1616 | static struct type * |
1617 | sh_sh4_build_float_register_type (int high) | |
1618 | { | |
1619 | struct type *temp; | |
1620 | ||
1621 | temp = create_range_type (NULL, builtin_type_int, 0, high); | |
1622 | return create_array_type (NULL, builtin_type_float, temp); | |
1623 | } | |
1624 | ||
53116e27 | 1625 | static struct type * |
48db5a3c | 1626 | sh_sh4_register_type (struct gdbarch *gdbarch, int reg_nr) |
53116e27 EZ |
1627 | { |
1628 | if ((reg_nr >= FP0_REGNUM | |
f2ea0907 CV |
1629 | && (reg_nr <= FP_LAST_REGNUM)) |
1630 | || (reg_nr == FPUL_REGNUM)) | |
53116e27 | 1631 | return builtin_type_float; |
f2ea0907 CV |
1632 | else if (reg_nr >= DR0_REGNUM |
1633 | && reg_nr <= DR_LAST_REGNUM) | |
53116e27 | 1634 | return builtin_type_double; |
f2ea0907 CV |
1635 | else if (reg_nr >= FV0_REGNUM |
1636 | && reg_nr <= FV_LAST_REGNUM) | |
53116e27 EZ |
1637 | return sh_sh4_build_float_register_type (3); |
1638 | else | |
1639 | return builtin_type_int; | |
1640 | } | |
1641 | ||
cc17453a | 1642 | static struct type * |
48db5a3c | 1643 | sh_default_register_type (struct gdbarch *gdbarch, int reg_nr) |
cc17453a EZ |
1644 | { |
1645 | return builtin_type_int; | |
1646 | } | |
1647 | ||
fb409745 EZ |
1648 | /* On the sh4, the DRi pseudo registers are problematic if the target |
1649 | is little endian. When the user writes one of those registers, for | |
1650 | instance with 'ser var $dr0=1', we want the double to be stored | |
1651 | like this: | |
1652 | fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f | |
1653 | fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00 | |
1654 | ||
1655 | This corresponds to little endian byte order & big endian word | |
1656 | order. However if we let gdb write the register w/o conversion, it | |
1657 | will write fr0 and fr1 this way: | |
1658 | fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00 | |
1659 | fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f | |
1660 | because it will consider fr0 and fr1 as a single LE stretch of memory. | |
1661 | ||
1662 | To achieve what we want we must force gdb to store things in | |
1663 | floatformat_ieee_double_littlebyte_bigword (which is defined in | |
1664 | include/floatformat.h and libiberty/floatformat.c. | |
1665 | ||
1666 | In case the target is big endian, there is no problem, the | |
1667 | raw bytes will look like: | |
1668 | fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00 | |
1669 | fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00 | |
1670 | ||
1671 | The other pseudo registers (the FVs) also don't pose a problem | |
1672 | because they are stored as 4 individual FP elements. */ | |
1673 | ||
7bd872fe | 1674 | static void |
fb409745 EZ |
1675 | sh_sh4_register_convert_to_virtual (int regnum, struct type *type, |
1676 | char *from, char *to) | |
55ff77ac | 1677 | { |
f2ea0907 CV |
1678 | if (regnum >= DR0_REGNUM |
1679 | && regnum <= DR_LAST_REGNUM) | |
283150cd EZ |
1680 | { |
1681 | DOUBLEST val; | |
1682 | floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, from, &val); | |
55ff77ac | 1683 | store_typed_floating (to, type, val); |
283150cd EZ |
1684 | } |
1685 | else | |
55ff77ac | 1686 | error ("sh_register_convert_to_virtual called with non DR register number"); |
283150cd EZ |
1687 | } |
1688 | ||
1689 | static void | |
1690 | sh_sh4_register_convert_to_raw (struct type *type, int regnum, | |
d8124050 | 1691 | const void *from, void *to) |
283150cd | 1692 | { |
f2ea0907 CV |
1693 | if (regnum >= DR0_REGNUM |
1694 | && regnum <= DR_LAST_REGNUM) | |
283150cd | 1695 | { |
48db5a3c | 1696 | DOUBLEST val = extract_typed_floating (from, type); |
283150cd EZ |
1697 | floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword, &val, to); |
1698 | } | |
1699 | else | |
1700 | error("sh_register_convert_to_raw called with non DR register number"); | |
1701 | } | |
1702 | ||
a78f21af | 1703 | static void |
d8124050 AC |
1704 | sh_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, |
1705 | int reg_nr, void *buffer) | |
53116e27 EZ |
1706 | { |
1707 | int base_regnum, portion; | |
d9d9c31f | 1708 | char temp_buffer[MAX_REGISTER_SIZE]; |
53116e27 | 1709 | |
f2ea0907 CV |
1710 | if (reg_nr >= DR0_REGNUM |
1711 | && reg_nr <= DR_LAST_REGNUM) | |
7bd872fe EZ |
1712 | { |
1713 | base_regnum = dr_reg_base_num (reg_nr); | |
1714 | ||
1715 | /* Build the value in the provided buffer. */ | |
1716 | /* Read the real regs for which this one is an alias. */ | |
1717 | for (portion = 0; portion < 2; portion++) | |
d8124050 | 1718 | regcache_raw_read (regcache, base_regnum + portion, |
0818c12a | 1719 | (temp_buffer |
48db5a3c | 1720 | + register_size (gdbarch, base_regnum) * portion)); |
7bd872fe EZ |
1721 | /* We must pay attention to the endiannes. */ |
1722 | sh_sh4_register_convert_to_virtual (reg_nr, | |
48db5a3c | 1723 | gdbarch_register_type (gdbarch, reg_nr), |
7bd872fe EZ |
1724 | temp_buffer, buffer); |
1725 | } | |
f2ea0907 CV |
1726 | else if (reg_nr >= FV0_REGNUM |
1727 | && reg_nr <= FV_LAST_REGNUM) | |
53116e27 | 1728 | { |
7bd872fe EZ |
1729 | base_regnum = fv_reg_base_num (reg_nr); |
1730 | ||
1731 | /* Read the real regs for which this one is an alias. */ | |
1732 | for (portion = 0; portion < 4; portion++) | |
d8124050 AC |
1733 | regcache_raw_read (regcache, base_regnum + portion, |
1734 | ((char *) buffer | |
48db5a3c | 1735 | + register_size (gdbarch, base_regnum) * portion)); |
53116e27 EZ |
1736 | } |
1737 | } | |
1738 | ||
a78f21af | 1739 | static void |
d8124050 AC |
1740 | sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, |
1741 | int reg_nr, const void *buffer) | |
53116e27 EZ |
1742 | { |
1743 | int base_regnum, portion; | |
d9d9c31f | 1744 | char temp_buffer[MAX_REGISTER_SIZE]; |
53116e27 | 1745 | |
f2ea0907 CV |
1746 | if (reg_nr >= DR0_REGNUM |
1747 | && reg_nr <= DR_LAST_REGNUM) | |
53116e27 EZ |
1748 | { |
1749 | base_regnum = dr_reg_base_num (reg_nr); | |
1750 | ||
7bd872fe | 1751 | /* We must pay attention to the endiannes. */ |
48db5a3c | 1752 | sh_sh4_register_convert_to_raw (gdbarch_register_type (gdbarch, reg_nr), reg_nr, |
7bd872fe EZ |
1753 | buffer, temp_buffer); |
1754 | ||
53116e27 EZ |
1755 | /* Write the real regs for which this one is an alias. */ |
1756 | for (portion = 0; portion < 2; portion++) | |
d8124050 | 1757 | regcache_raw_write (regcache, base_regnum + portion, |
0818c12a | 1758 | (temp_buffer |
48db5a3c | 1759 | + register_size (gdbarch, base_regnum) * portion)); |
53116e27 | 1760 | } |
f2ea0907 CV |
1761 | else if (reg_nr >= FV0_REGNUM |
1762 | && reg_nr <= FV_LAST_REGNUM) | |
53116e27 EZ |
1763 | { |
1764 | base_regnum = fv_reg_base_num (reg_nr); | |
1765 | ||
1766 | /* Write the real regs for which this one is an alias. */ | |
1767 | for (portion = 0; portion < 4; portion++) | |
d8124050 AC |
1768 | regcache_raw_write (regcache, base_regnum + portion, |
1769 | ((char *) buffer | |
48db5a3c | 1770 | + register_size (gdbarch, base_regnum) * portion)); |
53116e27 EZ |
1771 | } |
1772 | } | |
1773 | ||
3bbfbb92 | 1774 | /* Floating point vector of 4 float registers. */ |
53116e27 | 1775 | static void |
48db5a3c CV |
1776 | do_fv_register_info (struct gdbarch *gdbarch, struct ui_file *file, |
1777 | int fv_regnum) | |
53116e27 EZ |
1778 | { |
1779 | int first_fp_reg_num = fv_reg_base_num (fv_regnum); | |
48db5a3c | 1780 | fprintf_filtered (file, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n", |
f2ea0907 | 1781 | fv_regnum - FV0_REGNUM, |
53116e27 EZ |
1782 | (int) read_register (first_fp_reg_num), |
1783 | (int) read_register (first_fp_reg_num + 1), | |
1784 | (int) read_register (first_fp_reg_num + 2), | |
1785 | (int) read_register (first_fp_reg_num + 3)); | |
1786 | } | |
1787 | ||
3bbfbb92 | 1788 | /* Double precision registers. */ |
53116e27 | 1789 | static void |
48db5a3c CV |
1790 | do_dr_register_info (struct gdbarch *gdbarch, struct ui_file *file, |
1791 | int dr_regnum) | |
53116e27 EZ |
1792 | { |
1793 | int first_fp_reg_num = dr_reg_base_num (dr_regnum); | |
1794 | ||
48db5a3c | 1795 | fprintf_filtered (file, "dr%d\t0x%08x%08x\n", |
f2ea0907 | 1796 | dr_regnum - DR0_REGNUM, |
53116e27 EZ |
1797 | (int) read_register (first_fp_reg_num), |
1798 | (int) read_register (first_fp_reg_num + 1)); | |
1799 | } | |
1800 | ||
1801 | static void | |
48db5a3c CV |
1802 | sh_print_pseudo_register (struct gdbarch *gdbarch, struct ui_file *file, |
1803 | int regnum) | |
53116e27 EZ |
1804 | { |
1805 | if (regnum < NUM_REGS || regnum >= NUM_REGS + NUM_PSEUDO_REGS) | |
8e65ff28 AC |
1806 | internal_error (__FILE__, __LINE__, |
1807 | "Invalid pseudo register number %d\n", regnum); | |
f2ea0907 CV |
1808 | else if (regnum >= DR0_REGNUM |
1809 | && regnum <= DR_LAST_REGNUM) | |
48db5a3c | 1810 | do_dr_register_info (gdbarch, file, regnum); |
f2ea0907 CV |
1811 | else if (regnum >= FV0_REGNUM |
1812 | && regnum <= FV_LAST_REGNUM) | |
48db5a3c | 1813 | do_fv_register_info (gdbarch, file, regnum); |
53116e27 EZ |
1814 | } |
1815 | ||
53116e27 | 1816 | static void |
48db5a3c | 1817 | sh_do_fp_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum) |
53116e27 EZ |
1818 | { /* do values for FP (float) regs */ |
1819 | char *raw_buffer; | |
1820 | double flt; /* double extracted from raw hex data */ | |
1821 | int inv; | |
1822 | int j; | |
1823 | ||
1824 | /* Allocate space for the float. */ | |
48db5a3c | 1825 | raw_buffer = (char *) alloca (register_size (gdbarch, FP0_REGNUM)); |
53116e27 EZ |
1826 | |
1827 | /* Get the data in raw format. */ | |
48db5a3c | 1828 | if (!frame_register_read (get_selected_frame (), regnum, raw_buffer)) |
53116e27 EZ |
1829 | error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum)); |
1830 | ||
1831 | /* Get the register as a number */ | |
1832 | flt = unpack_double (builtin_type_float, raw_buffer, &inv); | |
1833 | ||
1834 | /* Print the name and some spaces. */ | |
48db5a3c CV |
1835 | fputs_filtered (REGISTER_NAME (regnum), file); |
1836 | print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file); | |
53116e27 EZ |
1837 | |
1838 | /* Print the value. */ | |
93d56215 | 1839 | if (inv) |
48db5a3c | 1840 | fprintf_filtered (file, "<invalid float>"); |
93d56215 | 1841 | else |
48db5a3c | 1842 | fprintf_filtered (file, "%-10.9g", flt); |
53116e27 EZ |
1843 | |
1844 | /* Print the fp register as hex. */ | |
48db5a3c CV |
1845 | fprintf_filtered (file, "\t(raw 0x"); |
1846 | for (j = 0; j < register_size (gdbarch, regnum); j++) | |
53116e27 | 1847 | { |
aa1ee363 | 1848 | int idx = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? j |
48db5a3c CV |
1849 | : register_size (gdbarch, regnum) - 1 - j; |
1850 | fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[idx]); | |
53116e27 | 1851 | } |
48db5a3c CV |
1852 | fprintf_filtered (file, ")"); |
1853 | fprintf_filtered (file, "\n"); | |
53116e27 EZ |
1854 | } |
1855 | ||
1856 | static void | |
48db5a3c | 1857 | sh_do_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum) |
53116e27 | 1858 | { |
123a958e | 1859 | char raw_buffer[MAX_REGISTER_SIZE]; |
53116e27 | 1860 | |
48db5a3c CV |
1861 | fputs_filtered (REGISTER_NAME (regnum), file); |
1862 | print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file); | |
53116e27 EZ |
1863 | |
1864 | /* Get the data in raw format. */ | |
48db5a3c CV |
1865 | if (!frame_register_read (get_selected_frame (), regnum, raw_buffer)) |
1866 | fprintf_filtered (file, "*value not available*\n"); | |
53116e27 | 1867 | |
48db5a3c CV |
1868 | val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0, |
1869 | file, 'x', 1, 0, Val_pretty_default); | |
1870 | fprintf_filtered (file, "\t"); | |
1871 | val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0, | |
1872 | file, 0, 1, 0, Val_pretty_default); | |
1873 | fprintf_filtered (file, "\n"); | |
53116e27 EZ |
1874 | } |
1875 | ||
1876 | static void | |
48db5a3c | 1877 | sh_print_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum) |
53116e27 EZ |
1878 | { |
1879 | if (regnum < 0 || regnum >= NUM_REGS + NUM_PSEUDO_REGS) | |
8e65ff28 AC |
1880 | internal_error (__FILE__, __LINE__, |
1881 | "Invalid register number %d\n", regnum); | |
53116e27 | 1882 | |
e30839fe | 1883 | else if (regnum >= 0 && regnum < NUM_REGS) |
53116e27 | 1884 | { |
48db5a3c CV |
1885 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
1886 | sh_do_fp_register (gdbarch, file, regnum); /* FP regs */ | |
53116e27 | 1887 | else |
48db5a3c | 1888 | sh_do_register (gdbarch, file, regnum); /* All other regs */ |
53116e27 EZ |
1889 | } |
1890 | ||
1891 | else if (regnum < NUM_REGS + NUM_PSEUDO_REGS) | |
48db5a3c | 1892 | { |
55ff77ac | 1893 | sh_print_pseudo_register (gdbarch, file, regnum); |
48db5a3c | 1894 | } |
53116e27 EZ |
1895 | } |
1896 | ||
a78f21af | 1897 | static void |
48db5a3c CV |
1898 | sh_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
1899 | struct frame_info *frame, int regnum, int fpregs) | |
53116e27 EZ |
1900 | { |
1901 | if (regnum != -1) /* do one specified register */ | |
1902 | { | |
1903 | if (*(REGISTER_NAME (regnum)) == '\0') | |
1904 | error ("Not a valid register for the current processor type"); | |
1905 | ||
48db5a3c | 1906 | sh_print_register (gdbarch, file, regnum); |
53116e27 EZ |
1907 | } |
1908 | else | |
1909 | /* do all (or most) registers */ | |
1910 | { | |
1911 | regnum = 0; | |
1912 | while (regnum < NUM_REGS) | |
1913 | { | |
1914 | /* If the register name is empty, it is undefined for this | |
1915 | processor, so don't display anything. */ | |
1916 | if (REGISTER_NAME (regnum) == NULL | |
1917 | || *(REGISTER_NAME (regnum)) == '\0') | |
1918 | { | |
1919 | regnum++; | |
1920 | continue; | |
1921 | } | |
1922 | ||
48db5a3c | 1923 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
53116e27 EZ |
1924 | { |
1925 | if (fpregs) | |
1926 | { | |
1927 | /* true for "INFO ALL-REGISTERS" command */ | |
48db5a3c | 1928 | sh_do_fp_register (gdbarch, file, regnum); /* FP regs */ |
53116e27 EZ |
1929 | regnum ++; |
1930 | } | |
1931 | else | |
f2ea0907 | 1932 | regnum += (FP_LAST_REGNUM - FP0_REGNUM); /* skip FP regs */ |
53116e27 EZ |
1933 | } |
1934 | else | |
1935 | { | |
48db5a3c | 1936 | sh_do_register (gdbarch, file, regnum); /* All other regs */ |
53116e27 EZ |
1937 | regnum++; |
1938 | } | |
1939 | } | |
1940 | ||
1941 | if (fpregs) | |
1942 | while (regnum < NUM_REGS + NUM_PSEUDO_REGS) | |
1943 | { | |
55ff77ac | 1944 | sh_print_pseudo_register (gdbarch, file, regnum); |
53116e27 EZ |
1945 | regnum++; |
1946 | } | |
1947 | } | |
1948 | } | |
1949 | ||
1a8629c7 MS |
1950 | #ifdef SVR4_SHARED_LIBS |
1951 | ||
1952 | /* Fetch (and possibly build) an appropriate link_map_offsets structure | |
1953 | for native i386 linux targets using the struct offsets defined in | |
1954 | link.h (but without actual reference to that file). | |
1955 | ||
1956 | This makes it possible to access i386-linux shared libraries from | |
1957 | a gdb that was not built on an i386-linux host (for cross debugging). | |
1958 | */ | |
1959 | ||
1960 | struct link_map_offsets * | |
1961 | sh_linux_svr4_fetch_link_map_offsets (void) | |
1962 | { | |
1963 | static struct link_map_offsets lmo; | |
1964 | static struct link_map_offsets *lmp = 0; | |
1965 | ||
1966 | if (lmp == 0) | |
1967 | { | |
1968 | lmp = &lmo; | |
1969 | ||
1970 | lmo.r_debug_size = 8; /* 20 not actual size but all we need */ | |
1971 | ||
1972 | lmo.r_map_offset = 4; | |
1973 | lmo.r_map_size = 4; | |
1974 | ||
1975 | lmo.link_map_size = 20; /* 552 not actual size but all we need */ | |
1976 | ||
1977 | lmo.l_addr_offset = 0; | |
1978 | lmo.l_addr_size = 4; | |
1979 | ||
1980 | lmo.l_name_offset = 4; | |
1981 | lmo.l_name_size = 4; | |
1982 | ||
1983 | lmo.l_next_offset = 12; | |
1984 | lmo.l_next_size = 4; | |
1985 | ||
1986 | lmo.l_prev_offset = 16; | |
1987 | lmo.l_prev_size = 4; | |
1988 | } | |
1989 | ||
1990 | return lmp; | |
1991 | } | |
1992 | #endif /* SVR4_SHARED_LIBS */ | |
1993 | ||
2f14585c JR |
1994 | static int |
1995 | sh_dsp_register_sim_regno (int nr) | |
1996 | { | |
1997 | if (legacy_register_sim_regno (nr) < 0) | |
1998 | return legacy_register_sim_regno (nr); | |
f2ea0907 CV |
1999 | if (nr >= DSR_REGNUM && nr <= Y1_REGNUM) |
2000 | return nr - DSR_REGNUM + SIM_SH_DSR_REGNUM; | |
2001 | if (nr == MOD_REGNUM) | |
2f14585c | 2002 | return SIM_SH_MOD_REGNUM; |
f2ea0907 | 2003 | if (nr == RS_REGNUM) |
2f14585c | 2004 | return SIM_SH_RS_REGNUM; |
f2ea0907 | 2005 | if (nr == RE_REGNUM) |
2f14585c | 2006 | return SIM_SH_RE_REGNUM; |
f2ea0907 CV |
2007 | if (nr >= R0_BANK_REGNUM && nr <= R7_BANK_REGNUM) |
2008 | return nr - R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM; | |
2f14585c JR |
2009 | return nr; |
2010 | } | |
d658f924 | 2011 | \f |
cc17453a EZ |
2012 | static gdbarch_init_ftype sh_gdbarch_init; |
2013 | ||
2014 | static struct gdbarch * | |
fba45db2 | 2015 | sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
cc17453a | 2016 | { |
cc17453a | 2017 | struct gdbarch *gdbarch; |
d658f924 | 2018 | |
55ff77ac CV |
2019 | sh_show_regs = sh_generic_show_regs; |
2020 | switch (info.bfd_arch_info->mach) | |
2021 | { | |
2022 | case bfd_mach_sh2e: | |
2023 | sh_show_regs = sh2e_show_regs; | |
2024 | break; | |
2025 | case bfd_mach_sh_dsp: | |
2026 | sh_show_regs = sh_dsp_show_regs; | |
2027 | break; | |
2028 | ||
2029 | case bfd_mach_sh3: | |
2030 | sh_show_regs = sh3_show_regs; | |
2031 | break; | |
2032 | ||
2033 | case bfd_mach_sh3e: | |
2034 | sh_show_regs = sh3e_show_regs; | |
2035 | break; | |
2036 | ||
2037 | case bfd_mach_sh3_dsp: | |
2038 | sh_show_regs = sh3_dsp_show_regs; | |
2039 | break; | |
2040 | ||
2041 | case bfd_mach_sh4: | |
2042 | sh_show_regs = sh4_show_regs; | |
2043 | break; | |
2044 | ||
2045 | case bfd_mach_sh5: | |
2046 | sh_show_regs = sh64_show_regs; | |
2047 | /* SH5 is handled entirely in sh64-tdep.c */ | |
2048 | return sh64_gdbarch_init (info, arches); | |
2049 | } | |
2050 | ||
4be87837 DJ |
2051 | /* If there is already a candidate, use it. */ |
2052 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
2053 | if (arches != NULL) | |
2054 | return arches->gdbarch; | |
cc17453a EZ |
2055 | |
2056 | /* None found, create a new architecture from the information | |
2057 | provided. */ | |
f2ea0907 | 2058 | gdbarch = gdbarch_alloc (&info, NULL); |
cc17453a | 2059 | |
a5afb99f AC |
2060 | /* NOTE: cagney/2002-12-06: This can be deleted when this arch is |
2061 | ready to unwind the PC first (see frame.c:get_prev_frame()). */ | |
2062 | set_gdbarch_deprecated_init_frame_pc (gdbarch, init_frame_pc_default); | |
2063 | ||
48db5a3c CV |
2064 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); |
2065 | set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
ec920329 | 2066 | set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
48db5a3c CV |
2067 | set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); |
2068 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
2069 | set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
2070 | set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
a38d2a54 | 2071 | set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
48db5a3c | 2072 | |
f2ea0907 | 2073 | set_gdbarch_num_regs (gdbarch, SH_NUM_REGS); |
a38d2a54 | 2074 | set_gdbarch_sp_regnum (gdbarch, 15); |
0ba6dca9 | 2075 | set_gdbarch_deprecated_fp_regnum (gdbarch, 14); |
a38d2a54 | 2076 | set_gdbarch_pc_regnum (gdbarch, 16); |
48db5a3c CV |
2077 | set_gdbarch_fp0_regnum (gdbarch, -1); |
2078 | set_gdbarch_num_pseudo_regs (gdbarch, 0); | |
2079 | ||
eaf90c5d | 2080 | set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc); |
3bbfbb92 | 2081 | set_gdbarch_use_struct_convention (gdbarch, sh_use_struct_convention); |
48db5a3c | 2082 | |
2bf0cb65 | 2083 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_sh); |
2f14585c | 2084 | set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno); |
48db5a3c CV |
2085 | |
2086 | set_gdbarch_write_pc (gdbarch, generic_target_write_pc); | |
2087 | ||
2088 | set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue); | |
2089 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
2090 | set_gdbarch_decr_pc_after_break (gdbarch, 0); | |
2091 | set_gdbarch_function_start_offset (gdbarch, 0); | |
2092 | ||
2093 | set_gdbarch_frame_args_skip (gdbarch, 0); | |
2094 | set_gdbarch_frameless_function_invocation (gdbarch, frameless_look_for_prologue); | |
2095 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); | |
2096 | ||
48db5a3c CV |
2097 | set_gdbarch_deprecated_frame_chain (gdbarch, sh_frame_chain); |
2098 | set_gdbarch_deprecated_get_saved_register (gdbarch, deprecated_generic_get_saved_register); | |
2099 | set_gdbarch_deprecated_init_extra_frame_info (gdbarch, sh_init_extra_frame_info); | |
2100 | set_gdbarch_deprecated_pop_frame (gdbarch, sh_pop_frame); | |
2101 | set_gdbarch_deprecated_frame_saved_pc (gdbarch, sh_frame_saved_pc); | |
2102 | set_gdbarch_deprecated_saved_pc_after_call (gdbarch, sh_saved_pc_after_call); | |
19f59343 | 2103 | set_gdbarch_frame_align (gdbarch, sh_frame_align); |
cc17453a EZ |
2104 | |
2105 | switch (info.bfd_arch_info->mach) | |
8db62801 | 2106 | { |
cc17453a | 2107 | case bfd_mach_sh: |
48db5a3c CV |
2108 | set_gdbarch_register_name (gdbarch, sh_sh_register_name); |
2109 | set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info); | |
48db5a3c CV |
2110 | set_gdbarch_register_type (gdbarch, sh_default_register_type); |
2111 | set_gdbarch_push_dummy_code (gdbarch, sh_push_dummy_code); | |
2112 | set_gdbarch_store_return_value (gdbarch, sh_default_store_return_value); | |
2113 | set_gdbarch_extract_return_value (gdbarch, sh_default_extract_return_value); | |
6df2bf50 | 2114 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu); |
48db5a3c CV |
2115 | set_gdbarch_extract_struct_value_address (gdbarch, sh_extract_struct_value_address); |
2116 | ||
f30ee0bc | 2117 | set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs); |
cc17453a EZ |
2118 | break; |
2119 | case bfd_mach_sh2: | |
48db5a3c CV |
2120 | set_gdbarch_register_name (gdbarch, sh_sh_register_name); |
2121 | set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info); | |
48db5a3c CV |
2122 | set_gdbarch_register_type (gdbarch, sh_default_register_type); |
2123 | set_gdbarch_push_dummy_code (gdbarch, sh_push_dummy_code); | |
2124 | set_gdbarch_store_return_value (gdbarch, sh_default_store_return_value); | |
2125 | set_gdbarch_extract_return_value (gdbarch, sh_default_extract_return_value); | |
6df2bf50 | 2126 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu); |
48db5a3c CV |
2127 | set_gdbarch_extract_struct_value_address (gdbarch, sh_extract_struct_value_address); |
2128 | ||
f30ee0bc | 2129 | set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs); |
cc17453a | 2130 | break; |
2d188dd3 | 2131 | case bfd_mach_sh2e: |
48db5a3c CV |
2132 | /* doubles on sh2e and sh3e are actually 4 byte. */ |
2133 | set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
2134 | ||
2135 | set_gdbarch_register_name (gdbarch, sh_sh2e_register_name); | |
2136 | set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info); | |
48db5a3c CV |
2137 | set_gdbarch_register_type (gdbarch, sh_sh3e_register_type); |
2138 | set_gdbarch_push_dummy_code (gdbarch, sh_push_dummy_code); | |
2d188dd3 | 2139 | set_gdbarch_fp0_regnum (gdbarch, 25); |
48db5a3c CV |
2140 | set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value); |
2141 | set_gdbarch_extract_return_value (gdbarch, sh3e_sh4_extract_return_value); | |
6df2bf50 | 2142 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); |
48db5a3c | 2143 | set_gdbarch_extract_struct_value_address (gdbarch, sh_extract_struct_value_address); |
48db5a3c | 2144 | |
55ff77ac | 2145 | set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs); |
2d188dd3 | 2146 | break; |
cc17453a | 2147 | case bfd_mach_sh_dsp: |
48db5a3c CV |
2148 | set_gdbarch_register_name (gdbarch, sh_sh_dsp_register_name); |
2149 | set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info); | |
48db5a3c CV |
2150 | set_gdbarch_register_type (gdbarch, sh_default_register_type); |
2151 | set_gdbarch_push_dummy_code (gdbarch, sh_push_dummy_code); | |
2f14585c | 2152 | set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno); |
48db5a3c CV |
2153 | set_gdbarch_store_return_value (gdbarch, sh_default_store_return_value); |
2154 | set_gdbarch_extract_return_value (gdbarch, sh_default_extract_return_value); | |
6df2bf50 | 2155 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu); |
48db5a3c | 2156 | set_gdbarch_extract_struct_value_address (gdbarch, sh_extract_struct_value_address); |
48db5a3c CV |
2157 | |
2158 | set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs); | |
cc17453a EZ |
2159 | break; |
2160 | case bfd_mach_sh3: | |
48db5a3c CV |
2161 | set_gdbarch_register_name (gdbarch, sh_sh3_register_name); |
2162 | set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info); | |
48db5a3c CV |
2163 | set_gdbarch_register_type (gdbarch, sh_default_register_type); |
2164 | set_gdbarch_push_dummy_code (gdbarch, sh_push_dummy_code); | |
2165 | set_gdbarch_store_return_value (gdbarch, sh_default_store_return_value); | |
2166 | set_gdbarch_extract_return_value (gdbarch, sh_default_extract_return_value); | |
6df2bf50 | 2167 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu); |
48db5a3c | 2168 | set_gdbarch_extract_struct_value_address (gdbarch, sh_extract_struct_value_address); |
48db5a3c CV |
2169 | |
2170 | set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs); | |
cc17453a EZ |
2171 | break; |
2172 | case bfd_mach_sh3e: | |
48db5a3c CV |
2173 | /* doubles on sh2e and sh3e are actually 4 byte. */ |
2174 | set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
2175 | ||
2176 | set_gdbarch_register_name (gdbarch, sh_sh3e_register_name); | |
2177 | set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info); | |
48db5a3c CV |
2178 | set_gdbarch_register_type (gdbarch, sh_sh3e_register_type); |
2179 | set_gdbarch_push_dummy_code (gdbarch, sh_push_dummy_code); | |
cc17453a | 2180 | set_gdbarch_fp0_regnum (gdbarch, 25); |
48db5a3c CV |
2181 | set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value); |
2182 | set_gdbarch_extract_return_value (gdbarch, sh3e_sh4_extract_return_value); | |
6df2bf50 | 2183 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); |
48db5a3c | 2184 | set_gdbarch_extract_struct_value_address (gdbarch, sh_extract_struct_value_address); |
48db5a3c CV |
2185 | |
2186 | set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh_fp_frame_init_saved_regs); | |
cc17453a EZ |
2187 | break; |
2188 | case bfd_mach_sh3_dsp: | |
48db5a3c CV |
2189 | set_gdbarch_register_name (gdbarch, sh_sh3_dsp_register_name); |
2190 | set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info); | |
48db5a3c CV |
2191 | set_gdbarch_register_type (gdbarch, sh_default_register_type); |
2192 | set_gdbarch_push_dummy_code (gdbarch, sh_push_dummy_code); | |
2193 | set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno); | |
2194 | set_gdbarch_store_return_value (gdbarch, sh_default_store_return_value); | |
2195 | set_gdbarch_extract_return_value (gdbarch, sh_default_extract_return_value); | |
6df2bf50 | 2196 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu); |
48db5a3c | 2197 | set_gdbarch_extract_struct_value_address (gdbarch, sh_extract_struct_value_address); |
48db5a3c CV |
2198 | |
2199 | set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs); | |
cc17453a EZ |
2200 | break; |
2201 | case bfd_mach_sh4: | |
48db5a3c CV |
2202 | set_gdbarch_register_name (gdbarch, sh_sh4_register_name); |
2203 | set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info); | |
48db5a3c CV |
2204 | set_gdbarch_register_type (gdbarch, sh_sh4_register_type); |
2205 | set_gdbarch_push_dummy_code (gdbarch, sh_push_dummy_code); | |
cc17453a | 2206 | set_gdbarch_fp0_regnum (gdbarch, 25); |
53116e27 | 2207 | set_gdbarch_num_pseudo_regs (gdbarch, 12); |
d8124050 AC |
2208 | set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read); |
2209 | set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write); | |
48db5a3c CV |
2210 | set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value); |
2211 | set_gdbarch_extract_return_value (gdbarch, sh3e_sh4_extract_return_value); | |
6df2bf50 | 2212 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); |
48db5a3c | 2213 | set_gdbarch_extract_struct_value_address (gdbarch, sh_extract_struct_value_address); |
48db5a3c CV |
2214 | |
2215 | set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh_fp_frame_init_saved_regs); | |
cc17453a EZ |
2216 | break; |
2217 | default: | |
48db5a3c CV |
2218 | set_gdbarch_register_name (gdbarch, sh_generic_register_name); |
2219 | set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info); | |
48db5a3c CV |
2220 | set_gdbarch_register_type (gdbarch, sh_default_register_type); |
2221 | set_gdbarch_push_dummy_code (gdbarch, sh_push_dummy_code); | |
2222 | set_gdbarch_store_return_value (gdbarch, sh_default_store_return_value); | |
2223 | set_gdbarch_extract_return_value (gdbarch, sh_default_extract_return_value); | |
2224 | ||
f30ee0bc | 2225 | set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs); |
cc17453a | 2226 | break; |
8db62801 | 2227 | } |
cc17453a | 2228 | |
4be87837 DJ |
2229 | /* Hook in ABI-specific overrides, if they have been registered. */ |
2230 | gdbarch_init_osabi (info, gdbarch); | |
d658f924 | 2231 | |
cc17453a | 2232 | return gdbarch; |
8db62801 EZ |
2233 | } |
2234 | ||
a78f21af AC |
2235 | extern initialize_file_ftype _initialize_sh_tdep; /* -Wmissing-prototypes */ |
2236 | ||
c906108c | 2237 | void |
fba45db2 | 2238 | _initialize_sh_tdep (void) |
c906108c SS |
2239 | { |
2240 | struct cmd_list_element *c; | |
cc17453a | 2241 | |
f2ea0907 | 2242 | gdbarch_register (bfd_arch_sh, sh_gdbarch_init, NULL); |
c906108c | 2243 | |
53116e27 | 2244 | add_com ("regs", class_vars, sh_show_regs_command, "Print all registers"); |
c906108c | 2245 | } |