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* amd64-sol2-tdep.c (amd64_sol2_gregset_reg_offset): Correct
[deliverable/binutils-gdb.git] / gdb / sh-tdep.c
CommitLineData
85a453d5 1/* Target-dependent code for Renesas Super-H, for GDB.
0fd88904 2
0b302171 3 Copyright (C) 1993-2005, 2007-2012 Free Software Foundation, Inc.
c906108c 4
c5aa993b 5 This file is part of GDB.
c906108c 6
c5aa993b
JM		 7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
a9762ec7 9 the Free Software Foundation; either version 3 of the License, or
c5aa993b 10 (at your option) any later version.
c906108c 11
c5aa993b
JM		 12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
c906108c 16
c5aa993b 17 You should have received a copy of the GNU General Public License
a9762ec7 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
c906108c 19
c378eb4e
MS		 20/* Contributed by Steve Chamberlain
21 sac@cygnus.com. */
c906108c
SS		 22
23#include "defs.h"
24#include "frame.h"
1c0159e0
CV		 25#include "frame-base.h"
26#include "frame-unwind.h"
27#include "dwarf2-frame.h"
c906108c 28#include "symtab.h"
c906108c
SS		 29#include "gdbtypes.h"
30#include "gdbcmd.h"
31#include "gdbcore.h"
32#include "value.h"
33#include "dis-asm.h"
73c1f219 34#include "inferior.h"
c906108c 35#include "gdb_string.h"
1c0159e0 36#include "gdb_assert.h"
b4a20239 37#include "arch-utils.h"
fb409745 38#include "floatformat.h"
4e052eda 39#include "regcache.h"
d16aafd8 40#include "doublest.h"
4be87837 41#include "osabi.h"
dda63807 42#include "reggroups.h"
c9ac0a72 43#include "regset.h"
c906108c 44
ab3b8126
JT		 45#include "sh-tdep.h"
46
d658f924 47#include "elf-bfd.h"
1a8629c7
MS		 48#include "solib-svr4.h"
49
55ff77ac 50/* sh flags */
283150cd 51#include "elf/sh.h"
fa8f86ff 52#include "dwarf2.h"
c378eb4e 53/* registers numbers shared with the simulator. */
1c922164 54#include "gdb/sim-sh.h"
283150cd 55
c055b101
CV		 56/* List of "set sh ..." and "show sh ..." commands. */
57static struct cmd_list_element *setshcmdlist = NULL;
58static struct cmd_list_element *showshcmdlist = NULL;
59
60static const char sh_cc_gcc[] = "gcc";
61static const char sh_cc_renesas[] = "renesas";
40478521 62static const char *const sh_cc_enum[] = {
c055b101
CV		 63 sh_cc_gcc,
64 sh_cc_renesas,
65 NULL
66};
67
68static const char *sh_active_calling_convention = sh_cc_gcc;
69
c458d6db 70static void (*sh_show_regs) (struct frame_info *);
cc17453a 71
da962468 72#define SH_NUM_REGS 67
88e04cc1 73
1c0159e0 74struct sh_frame_cache
cc17453a 75{
1c0159e0
CV		 76 /* Base address. */
77 CORE_ADDR base;
78 LONGEST sp_offset;
79 CORE_ADDR pc;
80
c378eb4e 81 /* Flag showing that a frame has been created in the prologue code. */
1c0159e0
CV		 82 int uses_fp;
83
84 /* Saved registers. */
85 CORE_ADDR saved_regs[SH_NUM_REGS];
86 CORE_ADDR saved_sp;
63978407 87};
c906108c 88
c055b101
CV		 89static int
90sh_is_renesas_calling_convention (struct type *func_type)
91{
92 return ((func_type
93 && TYPE_CALLING_CONVENTION (func_type) == DW_CC_GNU_renesas_sh)
94 || sh_active_calling_convention == sh_cc_renesas);
95}
96
fa88f677 97static const char *
d93859e2 98sh_sh_register_name (struct gdbarch *gdbarch, int reg_nr)
cc17453a 99{
617daa0e
CV		 100 static char *register_names[] = {
101 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
102 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
103 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
104 "", "",
105 "", "", "", "", "", "", "", "",
106 "", "", "", "", "", "", "", "",
107 "", "",
108 "", "", "", "", "", "", "", "",
109 "", "", "", "", "", "", "", "",
da962468 110 "", "", "", "", "", "", "", "",
cc17453a
EZ		 111 };
112 if (reg_nr < 0)
113 return NULL;
114 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
115 return NULL;
116 return register_names[reg_nr];
117}
118
fa88f677 119static const char *
d93859e2 120sh_sh3_register_name (struct gdbarch *gdbarch, int reg_nr)
cc17453a 121{
617daa0e
CV		 122 static char *register_names[] = {
123 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
124 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
125 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
126 "", "",
127 "", "", "", "", "", "", "", "",
128 "", "", "", "", "", "", "", "",
129 "ssr", "spc",
cc17453a
EZ		 130 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
131 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
da962468 132 "", "", "", "", "", "", "", "",
cc17453a
EZ		 133 };
134 if (reg_nr < 0)
135 return NULL;
136 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
137 return NULL;
138 return register_names[reg_nr];
139}
140
fa88f677 141static const char *
d93859e2 142sh_sh3e_register_name (struct gdbarch *gdbarch, int reg_nr)
cc17453a 143{
617daa0e
CV		 144 static char *register_names[] = {
145 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
146 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
147 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
cc17453a 148 "fpul", "fpscr",
617daa0e
CV		 149 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
150 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
151 "ssr", "spc",
cc17453a
EZ		 152 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
153 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
da962468 154 "", "", "", "", "", "", "", "",
cc17453a
EZ		 155 };
156 if (reg_nr < 0)
157 return NULL;
158 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
159 return NULL;
160 return register_names[reg_nr];
161}
162
2d188dd3 163static const char *
d93859e2 164sh_sh2e_register_name (struct gdbarch *gdbarch, int reg_nr)
2d188dd3 165{
617daa0e
CV		 166 static char *register_names[] = {
167 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
168 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
169 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
2d188dd3 170 "fpul", "fpscr",
617daa0e
CV		 171 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
172 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
173 "", "",
2d188dd3
NC		 174 "", "", "", "", "", "", "", "",
175 "", "", "", "", "", "", "", "",
da962468
CV		 176 "", "", "", "", "", "", "", "",
177 };
178 if (reg_nr < 0)
179 return NULL;
180 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
181 return NULL;
182 return register_names[reg_nr];
183}
184
185static const char *
d93859e2 186sh_sh2a_register_name (struct gdbarch *gdbarch, int reg_nr)
da962468
CV		 187{
188 static char *register_names[] = {
189 /* general registers 0-15 */
190 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
191 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
192 /* 16 - 22 */
193 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
194 /* 23, 24 */
195 "fpul", "fpscr",
196 /* floating point registers 25 - 40 */
197 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
198 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
199 /* 41, 42 */
200 "", "",
201 /* 43 - 62. Banked registers. The bank number used is determined by
c378eb4e 202 the bank register (63). */
da962468
CV		 203 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
204 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
205 "machb", "ivnb", "prb", "gbrb", "maclb",
206 /* 63: register bank number, not a real register but used to
207 communicate the register bank currently get/set. This register
208 is hidden to the user, who manipulates it using the pseudo
209 register called "bank" (67). See below. */
210 "",
211 /* 64 - 66 */
212 "ibcr", "ibnr", "tbr",
213 /* 67: register bank number, the user visible pseudo register. */
214 "bank",
215 /* double precision (pseudo) 68 - 75 */
216 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
217 };
218 if (reg_nr < 0)
219 return NULL;
220 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
221 return NULL;
222 return register_names[reg_nr];
223}
224
225static const char *
d93859e2 226sh_sh2a_nofpu_register_name (struct gdbarch *gdbarch, int reg_nr)
da962468
CV		 227{
228 static char *register_names[] = {
229 /* general registers 0-15 */
230 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
231 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
232 /* 16 - 22 */
233 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
234 /* 23, 24 */
235 "", "",
236 /* floating point registers 25 - 40 */
237 "", "", "", "", "", "", "", "",
238 "", "", "", "", "", "", "", "",
239 /* 41, 42 */
240 "", "",
241 /* 43 - 62. Banked registers. The bank number used is determined by
c378eb4e 242 the bank register (63). */
da962468
CV		 243 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
244 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
245 "machb", "ivnb", "prb", "gbrb", "maclb",
246 /* 63: register bank number, not a real register but used to
247 communicate the register bank currently get/set. This register
248 is hidden to the user, who manipulates it using the pseudo
249 register called "bank" (67). See below. */
250 "",
251 /* 64 - 66 */
252 "ibcr", "ibnr", "tbr",
253 /* 67: register bank number, the user visible pseudo register. */
254 "bank",
255 /* double precision (pseudo) 68 - 75 */
256 "", "", "", "", "", "", "", "",
2d188dd3
NC		 257 };
258 if (reg_nr < 0)
259 return NULL;
260 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
261 return NULL;
262 return register_names[reg_nr];
263}
264
fa88f677 265static const char *
d93859e2 266sh_sh_dsp_register_name (struct gdbarch *gdbarch, int reg_nr)
cc17453a 267{
617daa0e
CV		 268 static char *register_names[] = {
269 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
270 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
271 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
272 "", "dsr",
273 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
274 "y0", "y1", "", "", "", "", "", "mod",
275 "", "",
276 "rs", "re", "", "", "", "", "", "",
277 "", "", "", "", "", "", "", "",
da962468 278 "", "", "", "", "", "", "", "",
cc17453a
EZ		 279 };
280 if (reg_nr < 0)
281 return NULL;
282 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
283 return NULL;
284 return register_names[reg_nr];
285}
286
fa88f677 287static const char *
d93859e2 288sh_sh3_dsp_register_name (struct gdbarch *gdbarch, int reg_nr)
cc17453a 289{
617daa0e
CV		 290 static char *register_names[] = {
291 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
292 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
293 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
294 "", "dsr",
295 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
296 "y0", "y1", "", "", "", "", "", "mod",
297 "ssr", "spc",
298 "rs", "re", "", "", "", "", "", "",
026a72f8
CV		 299 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
300 "", "", "", "", "", "", "", "",
da962468 301 "", "", "", "", "", "", "", "",
cc17453a
EZ		 302 };
303 if (reg_nr < 0)
304 return NULL;
305 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
306 return NULL;
307 return register_names[reg_nr];
308}
309
fa88f677 310static const char *
d93859e2 311sh_sh4_register_name (struct gdbarch *gdbarch, int reg_nr)
53116e27 312{
617daa0e 313 static char *register_names[] = {
a38d2a54 314 /* general registers 0-15 */
617daa0e
CV		 315 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
316 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
a38d2a54 317 /* 16 - 22 */
617daa0e 318 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
a38d2a54 319 /* 23, 24 */
53116e27 320 "fpul", "fpscr",
a38d2a54 321 /* floating point registers 25 - 40 */
617daa0e
CV		 322 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
323 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
a38d2a54 324 /* 41, 42 */
617daa0e 325 "ssr", "spc",
a38d2a54 326 /* bank 0 43 - 50 */
53116e27 327 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
a38d2a54 328 /* bank 1 51 - 58 */
53116e27 329 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
da962468 330 "", "", "", "", "", "", "", "",
c378eb4e 331 /* pseudo bank register. */
da962468 332 "",
a38d2a54 333 /* double precision (pseudo) 59 - 66 */
617daa0e 334 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
a38d2a54 335 /* vectors (pseudo) 67 - 70 */
617daa0e 336 "fv0", "fv4", "fv8", "fv12",
a38d2a54
EZ		 337 /* FIXME: missing XF 71 - 86 */
338 /* FIXME: missing XD 87 - 94 */
53116e27
EZ		 339 };
340 if (reg_nr < 0)
341 return NULL;
342 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
343 return NULL;
344 return register_names[reg_nr];
345}
346
474e5826 347static const char *
d93859e2 348sh_sh4_nofpu_register_name (struct gdbarch *gdbarch, int reg_nr)
474e5826
CV		 349{
350 static char *register_names[] = {
351 /* general registers 0-15 */
352 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
353 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
354 /* 16 - 22 */
355 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
356 /* 23, 24 */
357 "", "",
358 /* floating point registers 25 - 40 -- not for nofpu target */
359 "", "", "", "", "", "", "", "",
360 "", "", "", "", "", "", "", "",
361 /* 41, 42 */
362 "ssr", "spc",
363 /* bank 0 43 - 50 */
364 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
365 /* bank 1 51 - 58 */
366 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
da962468 367 "", "", "", "", "", "", "", "",
c378eb4e 368 /* pseudo bank register. */
da962468 369 "",
474e5826
CV		 370 /* double precision (pseudo) 59 - 66 -- not for nofpu target */
371 "", "", "", "", "", "", "", "",
372 /* vectors (pseudo) 67 - 70 -- not for nofpu target */
373 "", "", "", "",
374 };
375 if (reg_nr < 0)
376 return NULL;
377 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
378 return NULL;
379 return register_names[reg_nr];
380}
381
382static const char *
d93859e2 383sh_sh4al_dsp_register_name (struct gdbarch *gdbarch, int reg_nr)
474e5826
CV		 384{
385 static char *register_names[] = {
386 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
387 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
388 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
389 "", "dsr",
390 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
391 "y0", "y1", "", "", "", "", "", "mod",
392 "ssr", "spc",
393 "rs", "re", "", "", "", "", "", "",
026a72f8
CV		 394 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
395 "", "", "", "", "", "", "", "",
da962468 396 "", "", "", "", "", "", "", "",
474e5826
CV		 397 };
398 if (reg_nr < 0)
399 return NULL;
400 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
401 return NULL;
402 return register_names[reg_nr];
403}
404
3117ed25 405static const unsigned char *
67d57894 406sh_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr)
cc17453a 407{
c378eb4e 408 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes. */
617daa0e
CV		 409 static unsigned char breakpoint[] = { 0xc3, 0xc3 };
410
bac718a6
UW		 411 /* For remote stub targets, trapa #20 is used. */
412 if (strcmp (target_shortname, "remote") == 0)
413 {
414 static unsigned char big_remote_breakpoint[] = { 0xc3, 0x20 };
415 static unsigned char little_remote_breakpoint[] = { 0x20, 0xc3 };
416
67d57894 417 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
bac718a6
UW		 418 {
419 *lenptr = sizeof (big_remote_breakpoint);
420 return big_remote_breakpoint;
421 }
422 else
423 {
424 *lenptr = sizeof (little_remote_breakpoint);
425 return little_remote_breakpoint;
426 }
427 }
428
cc17453a
EZ		 429 *lenptr = sizeof (breakpoint);
430 return breakpoint;
431}
c906108c
SS		 432
433/* Prologue looks like
1c0159e0
CV		 434 mov.l r14,@-r15
435 sts.l pr,@-r15
436 mov.l <regs>,@-r15
437 sub <room_for_loca_vars>,r15
438 mov r15,r14
8db62801 439
c378eb4e 440 Actually it can be more complicated than this but that's it, basically. */
c906108c 441
1c0159e0
CV		 442#define GET_SOURCE_REG(x) (((x) >> 4) & 0xf)
443#define GET_TARGET_REG(x) (((x) >> 8) & 0xf)
444
5f883edd
FF		 445/* JSR @Rm 0100mmmm00001011 */
446#define IS_JSR(x) (((x) & 0xf0ff) == 0x400b)
447
8db62801
EZ		 448/* STS.L PR,@-r15 0100111100100010
449 r15-4-->r15, PR-->(r15) */
c906108c 450#define IS_STS(x) ((x) == 0x4f22)
8db62801 451
03131d99
CV		 452/* STS.L MACL,@-r15 0100111100010010
453 r15-4-->r15, MACL-->(r15) */
454#define IS_MACL_STS(x) ((x) == 0x4f12)
455
8db62801
EZ		 456/* MOV.L Rm,@-r15 00101111mmmm0110
457 r15-4-->r15, Rm-->(R15) */
c906108c 458#define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
8db62801 459
8db62801
EZ		 460/* MOV r15,r14 0110111011110011
461 r15-->r14 */
c906108c 462#define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
8db62801
EZ		 463
464/* ADD #imm,r15 01111111iiiiiiii
465 r15+imm-->r15 */
1c0159e0 466#define IS_ADD_IMM_SP(x) (((x) & 0xff00) == 0x7f00)
8db62801 467
c906108c
SS		 468#define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
469#define IS_SHLL_R3(x) ((x) == 0x4300)
8db62801
EZ		 470
471/* ADD r3,r15 0011111100111100
472 r15+r3-->r15 */
c906108c 473#define IS_ADD_R3SP(x) ((x) == 0x3f3c)
8db62801
EZ		 474
475/* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
8db62801 476 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
8db62801 477 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
f2ea0907 478/* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to
c378eb4e 479 make this entirely clear. */
1c0159e0
CV		 480/* #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) */
481#define IS_FPUSH(x) (((x) & 0xff0f) == 0xff0b)
482
483/* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 4 <= m <= 7 */
484#define IS_MOV_ARG_TO_REG(x) \
485 (((x) & 0xf00f) == 0x6003 && \
486 ((x) & 0x00f0) >= 0x0040 && \
487 ((x) & 0x00f0) <= 0x0070)
488/* MOV.L Rm,@Rn 0010nnnnmmmm0010 n = 14, 4 <= m <= 7 */
489#define IS_MOV_ARG_TO_IND_R14(x) \
490 (((x) & 0xff0f) == 0x2e02 && \
491 ((x) & 0x00f0) >= 0x0040 && \
492 ((x) & 0x00f0) <= 0x0070)
493/* MOV.L Rm,@(disp*4,Rn) 00011110mmmmdddd n = 14, 4 <= m <= 7 */
494#define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \
495 (((x) & 0xff00) == 0x1e00 && \
496 ((x) & 0x00f0) >= 0x0040 && \
497 ((x) & 0x00f0) <= 0x0070)
498
499/* MOV.W @(disp*2,PC),Rn 1001nnnndddddddd */
500#define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000)
501/* MOV.L @(disp*4,PC),Rn 1101nnnndddddddd */
502#define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000)
03131d99
CV		 503/* MOVI20 #imm20,Rn 0000nnnniiii0000 */
504#define IS_MOVI20(x) (((x) & 0xf00f) == 0x0000)
1c0159e0
CV		 505/* SUB Rn,R15 00111111nnnn1000 */
506#define IS_SUB_REG_FROM_SP(x) (((x) & 0xff0f) == 0x3f08)
8db62801 507
1c0159e0 508#define FPSCR_SZ (1 << 20)
cc17453a 509
c378eb4e 510/* The following instructions are used for epilogue testing. */
1c0159e0
CV		 511#define IS_RESTORE_FP(x) ((x) == 0x6ef6)
512#define IS_RTS(x) ((x) == 0x000b)
513#define IS_LDS(x) ((x) == 0x4f26)
03131d99 514#define IS_MACL_LDS(x) ((x) == 0x4f16)
1c0159e0
CV		 515#define IS_MOV_FP_SP(x) ((x) == 0x6fe3)
516#define IS_ADD_REG_TO_FP(x) (((x) & 0xff0f) == 0x3e0c)
517#define IS_ADD_IMM_FP(x) (((x) & 0xff00) == 0x7e00)
cc17453a 518
cc17453a 519static CORE_ADDR
e17a4113
UW		 520sh_analyze_prologue (struct gdbarch *gdbarch,
521 CORE_ADDR pc, CORE_ADDR current_pc,
d2ca4222 522 struct sh_frame_cache *cache, ULONGEST fpscr)
617daa0e 523{
e17a4113 524 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1c0159e0
CV		 525 ULONGEST inst;
526 CORE_ADDR opc;
527 int offset;
528 int sav_offset = 0;
c906108c 529 int r3_val = 0;
1c0159e0 530 int reg, sav_reg = -1;
cc17453a 531
1c0159e0
CV		 532 if (pc >= current_pc)
533 return current_pc;
cc17453a 534
1c0159e0 535 cache->uses_fp = 0;
cc17453a
EZ		 536 for (opc = pc + (2 * 28); pc < opc; pc += 2)
537 {
e17a4113 538 inst = read_memory_unsigned_integer (pc, 2, byte_order);
c378eb4e 539 /* See where the registers will be saved to. */
f2ea0907 540 if (IS_PUSH (inst))
cc17453a 541 {
1c0159e0
CV		 542 cache->saved_regs[GET_SOURCE_REG (inst)] = cache->sp_offset;
543 cache->sp_offset += 4;
cc17453a 544 }
f2ea0907 545 else if (IS_STS (inst))
cc17453a 546 {
1c0159e0
CV		 547 cache->saved_regs[PR_REGNUM] = cache->sp_offset;
548 cache->sp_offset += 4;
cc17453a 549 }
03131d99
CV		 550 else if (IS_MACL_STS (inst))
551 {
552 cache->saved_regs[MACL_REGNUM] = cache->sp_offset;
553 cache->sp_offset += 4;
554 }
f2ea0907 555 else if (IS_MOV_R3 (inst))
cc17453a 556 {
f2ea0907 557 r3_val = ((inst & 0xff) ^ 0x80) - 0x80;
cc17453a 558 }
f2ea0907 559 else if (IS_SHLL_R3 (inst))
cc17453a
EZ		 560 {
561 r3_val <<= 1;
562 }
f2ea0907 563 else if (IS_ADD_R3SP (inst))
cc17453a 564 {
1c0159e0 565 cache->sp_offset += -r3_val;
cc17453a 566 }
f2ea0907 567 else if (IS_ADD_IMM_SP (inst))
cc17453a 568 {
1c0159e0
CV		 569 offset = ((inst & 0xff) ^ 0x80) - 0x80;
570 cache->sp_offset -= offset;
c906108c 571 }
1c0159e0 572 else if (IS_MOVW_PCREL_TO_REG (inst))
617daa0e 573 {
1c0159e0
CV		 574 if (sav_reg < 0)
575 {
576 reg = GET_TARGET_REG (inst);
577 if (reg < 14)
578 {
579 sav_reg = reg;
a2b4a96c 580 offset = (inst & 0xff) << 1;
1c0159e0 581 sav_offset =
e17a4113 582 read_memory_integer ((pc + 4) + offset, 2, byte_order);
1c0159e0
CV		 583 }
584 }
c906108c 585 }
1c0159e0 586 else if (IS_MOVL_PCREL_TO_REG (inst))
617daa0e 587 {
1c0159e0
CV		 588 if (sav_reg < 0)
589 {
a2b4a96c 590 reg = GET_TARGET_REG (inst);
1c0159e0
CV		 591 if (reg < 14)
592 {
593 sav_reg = reg;
a2b4a96c 594 offset = (inst & 0xff) << 2;
1c0159e0 595 sav_offset =
e17a4113
UW		 596 read_memory_integer (((pc & 0xfffffffc) + 4) + offset,
597 4, byte_order);
1c0159e0
CV		 598 }
599 }
c906108c 600 }
03131d99
CV		 601 else if (IS_MOVI20 (inst))
602 {
603 if (sav_reg < 0)
604 {
605 reg = GET_TARGET_REG (inst);
606 if (reg < 14)
607 {
608 sav_reg = reg;
609 sav_offset = GET_SOURCE_REG (inst) << 16;
c378eb4e 610 /* MOVI20 is a 32 bit instruction! */
03131d99 611 pc += 2;
e17a4113
UW		 612 sav_offset
613 |= read_memory_unsigned_integer (pc, 2, byte_order);
03131d99
CV		 614 /* Now sav_offset contains an unsigned 20 bit value.
615 It must still get sign extended. */
616 if (sav_offset & 0x00080000)
617 sav_offset |= 0xfff00000;
618 }
619 }
620 }
1c0159e0 621 else if (IS_SUB_REG_FROM_SP (inst))
617daa0e 622 {
1c0159e0
CV		 623 reg = GET_SOURCE_REG (inst);
624 if (sav_reg > 0 && reg == sav_reg)
625 {
626 sav_reg = -1;
627 }
628 cache->sp_offset += sav_offset;
c906108c 629 }
f2ea0907 630 else if (IS_FPUSH (inst))
c906108c 631 {
d2ca4222 632 if (fpscr & FPSCR_SZ)
c906108c 633 {
1c0159e0 634 cache->sp_offset += 8;
c906108c
SS		 635 }
636 else
637 {
1c0159e0 638 cache->sp_offset += 4;
c906108c
SS		 639 }
640 }
f2ea0907 641 else if (IS_MOV_SP_FP (inst))
617daa0e 642 {
960ccd7d 643 cache->uses_fp = 1;
1c0159e0
CV		 644 /* At this point, only allow argument register moves to other
645 registers or argument register moves to @(X,fp) which are
646 moving the register arguments onto the stack area allocated
647 by a former add somenumber to SP call. Don't allow moving
c378eb4e 648 to an fp indirect address above fp + cache->sp_offset. */
1c0159e0
CV		 649 pc += 2;
650 for (opc = pc + 12; pc < opc; pc += 2)
651 {
e17a4113 652 inst = read_memory_integer (pc, 2, byte_order);
1c0159e0 653 if (IS_MOV_ARG_TO_IND_R14 (inst))
617daa0e 654 {
1c0159e0
CV		 655 reg = GET_SOURCE_REG (inst);
656 if (cache->sp_offset > 0)
617daa0e 657 cache->saved_regs[reg] = cache->sp_offset;
1c0159e0
CV		 658 }
659 else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst))
617daa0e 660 {
1c0159e0
CV		 661 reg = GET_SOURCE_REG (inst);
662 offset = (inst & 0xf) * 4;
663 if (cache->sp_offset > offset)
664 cache->saved_regs[reg] = cache->sp_offset - offset;
665 }
666 else if (IS_MOV_ARG_TO_REG (inst))
617daa0e 667 continue;
1c0159e0
CV		 668 else
669 break;
670 }
671 break;
672 }
5f883edd
FF		 673 else if (IS_JSR (inst))
674 {
675 /* We have found a jsr that has been scheduled into the prologue.
676 If we continue the scan and return a pc someplace after this,
677 then setting a breakpoint on this function will cause it to
678 appear to be called after the function it is calling via the
679 jsr, which will be very confusing. Most likely the next
680 instruction is going to be IS_MOV_SP_FP in the delay slot. If
c378eb4e 681 so, note that before returning the current pc. */
e17a4113 682 inst = read_memory_integer (pc + 2, 2, byte_order);
5f883edd
FF		 683 if (IS_MOV_SP_FP (inst))
684 cache->uses_fp = 1;
685 break;
686 }
c378eb4e
MS		 687#if 0 /* This used to just stop when it found an instruction
688 that was not considered part of the prologue. Now,
689 we just keep going looking for likely
690 instructions. */
c906108c
SS		 691 else
692 break;
2bfa91ee 693#endif
c906108c
SS		 694 }
695
1c0159e0
CV		 696 return pc;
697}
c906108c 698
c378eb4e 699/* Skip any prologue before the guts of a function. */
c906108c 700
c378eb4e
MS		 701/* Skip the prologue using the debug information. If this fails we'll
702 fall back on the 'guess' method below. */
1c0159e0
CV		 703static CORE_ADDR
704after_prologue (CORE_ADDR pc)
705{
706 struct symtab_and_line sal;
707 CORE_ADDR func_addr, func_end;
c906108c 708
1c0159e0
CV		 709 /* If we can not find the symbol in the partial symbol table, then
710 there is no hope we can determine the function's start address
711 with this code. */
712 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
713 return 0;
c906108c 714
1c0159e0
CV		 715 /* Get the line associated with FUNC_ADDR. */
716 sal = find_pc_line (func_addr, 0);
717
718 /* There are only two cases to consider. First, the end of the source line
719 is within the function bounds. In that case we return the end of the
720 source line. Second is the end of the source line extends beyond the
721 bounds of the current function. We need to use the slow code to
722 examine instructions in that case. */
723 if (sal.end < func_end)
724 return sal.end;
725 else
726 return 0;
c906108c
SS		 727}
728
1c0159e0 729static CORE_ADDR
6093d2eb 730sh_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
c906108c 731{
1c0159e0
CV		 732 CORE_ADDR pc;
733 struct sh_frame_cache cache;
734
735 /* See if we can determine the end of the prologue via the symbol table.
736 If so, then return either PC, or the PC after the prologue, whichever
737 is greater. */
738 pc = after_prologue (start_pc);
cc17453a 739
1c0159e0 740 /* If after_prologue returned a useful address, then use it. Else
c378eb4e 741 fall back on the instruction skipping code. */
1c0159e0
CV		 742 if (pc)
743 return max (pc, start_pc);
c906108c 744
1c0159e0 745 cache.sp_offset = -4;
e17a4113 746 pc = sh_analyze_prologue (gdbarch, start_pc, (CORE_ADDR) -1, &cache, 0);
1c0159e0
CV		 747 if (!cache.uses_fp)
748 return start_pc;
c906108c 749
1c0159e0
CV		 750 return pc;
751}
752
2e952408 753/* The ABI says:
9a5cef92
EZ		 754
755 Aggregate types not bigger than 8 bytes that have the same size and
756 alignment as one of the integer scalar types are returned in the
757 same registers as the integer type they match.
758
759 For example, a 2-byte aligned structure with size 2 bytes has the
760 same size and alignment as a short int, and will be returned in R0.
761 A 4-byte aligned structure with size 8 bytes has the same size and
762 alignment as a long long int, and will be returned in R0 and R1.
763
764 When an aggregate type is returned in R0 and R1, R0 contains the
765 first four bytes of the aggregate, and R1 contains the
c378eb4e 766 remainder. If the size of the aggregate type is not a multiple of 4
9a5cef92 767 bytes, the aggregate is tail-padded up to a multiple of 4
c378eb4e 768 bytes. The value of the padding is undefined. For little-endian
9a5cef92
EZ		 769 targets the padding will appear at the most significant end of the
770 last element, for big-endian targets the padding appears at the
771 least significant end of the last element.
772
c378eb4e 773 All other aggregate types are returned by address. The caller
9a5cef92 774 function passes the address of an area large enough to hold the
c378eb4e 775 aggregate value in R2. The called function stores the result in
7fe958be 776 this location.
9a5cef92
EZ		 777
778 To reiterate, structs smaller than 8 bytes could also be returned
779 in memory, if they don't pass the "same size and alignment as an
780 integer type" rule.
781
782 For example, in
783
784 struct s { char c[3]; } wibble;
785 struct s foo(void) { return wibble; }
786
787 the return value from foo() will be in memory, not
788 in R0, because there is no 3-byte integer type.
789
7fe958be
EZ		 790 Similarly, in
791
792 struct s { char c[2]; } wibble;
793 struct s foo(void) { return wibble; }
794
795 because a struct containing two chars has alignment 1, that matches
796 type char, but size 2, that matches type short. There's no integer
797 type that has alignment 1 and size 2, so the struct is returned in
c378eb4e 798 memory. */
9a5cef92 799
1c0159e0 800static int
c055b101 801sh_use_struct_convention (int renesas_abi, struct type *type)
1c0159e0
CV		 802{
803 int len = TYPE_LENGTH (type);
804 int nelem = TYPE_NFIELDS (type);
3f997a97 805
c055b101
CV		 806 /* The Renesas ABI returns aggregate types always on stack. */
807 if (renesas_abi && (TYPE_CODE (type) == TYPE_CODE_STRUCT
808 || TYPE_CODE (type) == TYPE_CODE_UNION))
809 return 1;
810
3f997a97
CV		 811 /* Non-power of 2 length types and types bigger than 8 bytes (which don't
812 fit in two registers anyway) use struct convention. */
813 if (len != 1 && len != 2 && len != 4 && len != 8)
814 return 1;
815
816 /* Scalar types and aggregate types with exactly one field are aligned
817 by definition. They are returned in registers. */
818 if (nelem <= 1)
819 return 0;
820
821 /* If the first field in the aggregate has the same length as the entire
822 aggregate type, the type is returned in registers. */
823 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == len)
824 return 0;
825
826 /* If the size of the aggregate is 8 bytes and the first field is
827 of size 4 bytes its alignment is equal to long long's alignment,
828 so it's returned in registers. */
829 if (len == 8 && TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == 4)
830 return 0;
831
832 /* Otherwise use struct convention. */
833 return 1;
283150cd
EZ		 834}
835
c055b101
CV		 836static int
837sh_use_struct_convention_nofpu (int renesas_abi, struct type *type)
838{
839 /* The Renesas ABI returns long longs/doubles etc. always on stack. */
840 if (renesas_abi && TYPE_NFIELDS (type) == 0 && TYPE_LENGTH (type) >= 8)
841 return 1;
842 return sh_use_struct_convention (renesas_abi, type);
843}
844
19f59343
MS		 845static CORE_ADDR
846sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
847{
848 return sp & ~3;
849}
850
55ff77ac 851/* Function: push_dummy_call (formerly push_arguments)
c906108c
SS		 852 Setup the function arguments for calling a function in the inferior.
853
85a453d5 854 On the Renesas SH architecture, there are four registers (R4 to R7)
c906108c
SS		 855 which are dedicated for passing function arguments. Up to the first
856 four arguments (depending on size) may go into these registers.
857 The rest go on the stack.
858
6df2bf50
MS		 859 MVS: Except on SH variants that have floating point registers.
860 In that case, float and double arguments are passed in the same
861 manner, but using FP registers instead of GP registers.
862
c906108c
SS		 863 Arguments that are smaller than 4 bytes will still take up a whole
864 register or a whole 32-bit word on the stack, and will be
865 right-justified in the register or the stack word. This includes
866 chars, shorts, and small aggregate types.
867
868 Arguments that are larger than 4 bytes may be split between two or
869 more registers. If there are not enough registers free, an argument
870 may be passed partly in a register (or registers), and partly on the
c378eb4e 871 stack. This includes doubles, long longs, and larger aggregates.
c906108c
SS		 872 As far as I know, there is no upper limit to the size of aggregates
873 that will be passed in this way; in other words, the convention of
874 passing a pointer to a large aggregate instead of a copy is not used.
875
6df2bf50 876 MVS: The above appears to be true for the SH variants that do not
55ff77ac 877 have an FPU, however those that have an FPU appear to copy the
6df2bf50
MS		 878 aggregate argument onto the stack (and not place it in registers)
879 if it is larger than 16 bytes (four GP registers).
880
c906108c
SS		 881 An exceptional case exists for struct arguments (and possibly other
882 aggregates such as arrays) if the size is larger than 4 bytes but
883 not a multiple of 4 bytes. In this case the argument is never split
884 between the registers and the stack, but instead is copied in its
885 entirety onto the stack, AND also copied into as many registers as
886 there is room for. In other words, space in registers permitting,
887 two copies of the same argument are passed in. As far as I can tell,
888 only the one on the stack is used, although that may be a function
889 of the level of compiler optimization. I suspect this is a compiler
890 bug. Arguments of these odd sizes are left-justified within the
891 word (as opposed to arguments smaller than 4 bytes, which are
892 right-justified).
c5aa993b 893
c906108c
SS		 894 If the function is to return an aggregate type such as a struct, it
895 is either returned in the normal return value register R0 (if its
896 size is no greater than one byte), or else the caller must allocate
897 space into which the callee will copy the return value (if the size
898 is greater than one byte). In this case, a pointer to the return
899 value location is passed into the callee in register R2, which does
900 not displace any of the other arguments passed in via registers R4
c378eb4e 901 to R7. */
c906108c 902
c378eb4e 903/* Helper function to justify value in register according to endianess. */
e5e33cd9 904static char *
d93859e2 905sh_justify_value_in_reg (struct gdbarch *gdbarch, struct value *val, int len)
e5e33cd9
CV		 906{
907 static char valbuf[4];
908
617daa0e 909 memset (valbuf, 0, sizeof (valbuf));
e5e33cd9
CV		 910 if (len < 4)
911 {
c378eb4e 912 /* value gets right-justified in the register or stack word. */
d93859e2 913 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
0fd88904 914 memcpy (valbuf + (4 - len), (char *) value_contents (val), len);
e5e33cd9 915 else
0fd88904 916 memcpy (valbuf, (char *) value_contents (val), len);
e5e33cd9
CV		 917 return valbuf;
918 }
0fd88904 919 return (char *) value_contents (val);
617daa0e 920}
e5e33cd9 921
c378eb4e 922/* Helper function to eval number of bytes to allocate on stack. */
e5e33cd9
CV		 923static CORE_ADDR
924sh_stack_allocsize (int nargs, struct value **args)
925{
926 int stack_alloc = 0;
927 while (nargs-- > 0)
4991999e 928 stack_alloc += ((TYPE_LENGTH (value_type (args[nargs])) + 3) & ~3);
e5e33cd9
CV		 929 return stack_alloc;
930}
931
932/* Helper functions for getting the float arguments right. Registers usage
933 depends on the ABI and the endianess. The comments should enlighten how
c378eb4e 934 it's intended to work. */
e5e33cd9 935
c378eb4e 936/* This array stores which of the float arg registers are already in use. */
e5e33cd9
CV		 937static int flt_argreg_array[FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM + 1];
938
c378eb4e 939/* This function just resets the above array to "no reg used so far". */
e5e33cd9
CV		 940static void
941sh_init_flt_argreg (void)
942{
943 memset (flt_argreg_array, 0, sizeof flt_argreg_array);
944}
945
946/* This function returns the next register to use for float arg passing.
947 It returns either a valid value between FLOAT_ARG0_REGNUM and
948 FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns
949 FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available.
950
951 Note that register number 0 in flt_argreg_array corresponds with the
952 real float register fr4. In contrast to FLOAT_ARG0_REGNUM (value is
953 29) the parity of the register number is preserved, which is important
c378eb4e 954 for the double register passing test (see the "argreg & 1" test below). */
e5e33cd9 955static int
c055b101 956sh_next_flt_argreg (struct gdbarch *gdbarch, int len, struct type *func_type)
e5e33cd9
CV		 957{
958 int argreg;
959
c378eb4e 960 /* First search for the next free register. */
617daa0e
CV		 961 for (argreg = 0; argreg <= FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM;
962 ++argreg)
e5e33cd9
CV		 963 if (!flt_argreg_array[argreg])
964 break;
965
c378eb4e 966 /* No register left? */
e5e33cd9
CV		 967 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
968 return FLOAT_ARGLAST_REGNUM + 1;
969
970 if (len == 8)
971 {
c378eb4e 972 /* Doubles are always starting in a even register number. */
e5e33cd9 973 if (argreg & 1)
617daa0e 974 {
c055b101
CV		 975 /* In gcc ABI, the skipped register is lost for further argument
976 passing now. Not so in Renesas ABI. */
977 if (!sh_is_renesas_calling_convention (func_type))
978 flt_argreg_array[argreg] = 1;
e5e33cd9
CV		 979
980 ++argreg;
981
c378eb4e 982 /* No register left? */
e5e33cd9
CV		 983 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
984 return FLOAT_ARGLAST_REGNUM + 1;
985 }
c378eb4e 986 /* Also mark the next register as used. */
e5e33cd9
CV		 987 flt_argreg_array[argreg + 1] = 1;
988 }
c055b101
CV		 989 else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE
990 && !sh_is_renesas_calling_convention (func_type))
e5e33cd9 991 {
c378eb4e 992 /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */
e5e33cd9
CV		 993 if (!flt_argreg_array[argreg + 1])
994 ++argreg;
995 }
996 flt_argreg_array[argreg] = 1;
997 return FLOAT_ARG0_REGNUM + argreg;
998}
999
afce3d2a
CV		 1000/* Helper function which figures out, if a type is treated like a float type.
1001
2e952408 1002 The FPU ABIs have a special way how to treat types as float types.
afce3d2a
CV		 1003 Structures with exactly one member, which is of type float or double, are
1004 treated exactly as the base types float or double:
1005
1006 struct sf {
1007 float f;
1008 };
1009
1010 struct sd {
1011 double d;
1012 };
1013
1014 are handled the same way as just
1015
1016 float f;
1017
1018 double d;
1019
1020 As a result, arguments of these struct types are pushed into floating point
1021 registers exactly as floats or doubles, using the same decision algorithm.
1022
1023 The same is valid if these types are used as function return types. The
1024 above structs are returned in fr0 resp. fr0,fr1 instead of in r0, r0,r1
1025 or even using struct convention as it is for other structs. */
1026
1027static int
1028sh_treat_as_flt_p (struct type *type)
1029{
1030 int len = TYPE_LENGTH (type);
1031
1032 /* Ordinary float types are obviously treated as float. */
1033 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1034 return 1;
1035 /* Otherwise non-struct types are not treated as float. */
1036 if (TYPE_CODE (type) != TYPE_CODE_STRUCT)
1037 return 0;
1038 /* Otherwise structs with more than one memeber are not treated as float. */
1039 if (TYPE_NFIELDS (type) != 1)
1040 return 0;
1041 /* Otherwise if the type of that member is float, the whole type is
1042 treated as float. */
1043 if (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) == TYPE_CODE_FLT)
1044 return 1;
1045 /* Otherwise it's not treated as float. */
1046 return 0;
1047}
1048
cc17453a 1049static CORE_ADDR
617daa0e 1050sh_push_dummy_call_fpu (struct gdbarch *gdbarch,
7d9b040b 1051 struct value *function,
617daa0e 1052 struct regcache *regcache,
6df2bf50 1053 CORE_ADDR bp_addr, int nargs,
617daa0e 1054 struct value **args,
6df2bf50
MS		 1055 CORE_ADDR sp, int struct_return,
1056 CORE_ADDR struct_addr)
1057{
e17a4113 1058 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
e5e33cd9
CV		 1059 int stack_offset = 0;
1060 int argreg = ARG0_REGNUM;
8748518b 1061 int flt_argreg = 0;
6df2bf50 1062 int argnum;
c055b101 1063 struct type *func_type = value_type (function);
6df2bf50
MS		 1064 struct type *type;
1065 CORE_ADDR regval;
1066 char *val;
8748518b 1067 int len, reg_size = 0;
afce3d2a
CV		 1068 int pass_on_stack = 0;
1069 int treat_as_flt;
c055b101
CV		 1070 int last_reg_arg = INT_MAX;
1071
1072 /* The Renesas ABI expects all varargs arguments, plus the last
1073 non-vararg argument to be on the stack, no matter how many
1074 registers have been used so far. */
1075 if (sh_is_renesas_calling_convention (func_type)
876cecd0 1076 && TYPE_VARARGS (func_type))
c055b101 1077 last_reg_arg = TYPE_NFIELDS (func_type) - 2;
6df2bf50 1078
c378eb4e 1079 /* First force sp to a 4-byte alignment. */
6df2bf50
MS		 1080 sp = sh_frame_align (gdbarch, sp);
1081
c378eb4e 1082 /* Make room on stack for args. */
e5e33cd9
CV		 1083 sp -= sh_stack_allocsize (nargs, args);
1084
c378eb4e 1085 /* Initialize float argument mechanism. */
e5e33cd9 1086 sh_init_flt_argreg ();
6df2bf50
MS		 1087
1088 /* Now load as many as possible of the first arguments into
1089 registers, and push the rest onto the stack. There are 16 bytes
1090 in four registers available. Loop thru args from first to last. */
e5e33cd9 1091 for (argnum = 0; argnum < nargs; argnum++)
6df2bf50 1092 {
4991999e 1093 type = value_type (args[argnum]);
6df2bf50 1094 len = TYPE_LENGTH (type);
d93859e2 1095 val = sh_justify_value_in_reg (gdbarch, args[argnum], len);
e5e33cd9
CV		 1096
1097 /* Some decisions have to be made how various types are handled.
c378eb4e 1098 This also differs in different ABIs. */
e5e33cd9 1099 pass_on_stack = 0;
e5e33cd9 1100
c378eb4e 1101 /* Find out the next register to use for a floating point value. */
afce3d2a
CV		 1102 treat_as_flt = sh_treat_as_flt_p (type);
1103 if (treat_as_flt)
c055b101
CV		 1104 flt_argreg = sh_next_flt_argreg (gdbarch, len, func_type);
1105 /* In Renesas ABI, long longs and aggregate types are always passed
1106 on stack. */
1107 else if (sh_is_renesas_calling_convention (func_type)
1108 && ((TYPE_CODE (type) == TYPE_CODE_INT && len == 8)
1109 || TYPE_CODE (type) == TYPE_CODE_STRUCT
1110 || TYPE_CODE (type) == TYPE_CODE_UNION))
1111 pass_on_stack = 1;
afce3d2a
CV		 1112 /* In contrast to non-FPU CPUs, arguments are never split between
1113 registers and stack. If an argument doesn't fit in the remaining
1114 registers it's always pushed entirely on the stack. */
1115 else if (len > ((ARGLAST_REGNUM - argreg + 1) * 4))
1116 pass_on_stack = 1;
48db5a3c 1117
6df2bf50
MS		 1118 while (len > 0)
1119 {
afce3d2a
CV		 1120 if ((treat_as_flt && flt_argreg > FLOAT_ARGLAST_REGNUM)
1121 || (!treat_as_flt && (argreg > ARGLAST_REGNUM
c055b101
CV		 1122 || pass_on_stack))
1123 || argnum > last_reg_arg)
617daa0e 1124 {
c378eb4e 1125 /* The data goes entirely on the stack, 4-byte aligned. */
e5e33cd9
CV		 1126 reg_size = (len + 3) & ~3;
1127 write_memory (sp + stack_offset, val, reg_size);
1128 stack_offset += reg_size;
6df2bf50 1129 }
afce3d2a 1130 else if (treat_as_flt && flt_argreg <= FLOAT_ARGLAST_REGNUM)
6df2bf50 1131 {
e5e33cd9
CV		 1132 /* Argument goes in a float argument register. */
1133 reg_size = register_size (gdbarch, flt_argreg);
e17a4113 1134 regval = extract_unsigned_integer (val, reg_size, byte_order);
2e952408
CV		 1135 /* In little endian mode, float types taking two registers
1136 (doubles on sh4, long doubles on sh2e, sh3e and sh4) must
1137 be stored swapped in the argument registers. The below
1138 code first writes the first 32 bits in the next but one
1139 register, increments the val and len values accordingly
1140 and then proceeds as normal by writing the second 32 bits
c378eb4e 1141 into the next register. */
b47193f7 1142 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE
2e952408
CV		 1143 && TYPE_LENGTH (type) == 2 * reg_size)
1144 {
1145 regcache_cooked_write_unsigned (regcache, flt_argreg + 1,
1146 regval);
1147 val += reg_size;
1148 len -= reg_size;
c378eb4e
MS		 1149 regval = extract_unsigned_integer (val, reg_size,
1150 byte_order);
2e952408 1151 }
6df2bf50
MS		 1152 regcache_cooked_write_unsigned (regcache, flt_argreg++, regval);
1153 }
afce3d2a 1154 else if (!treat_as_flt && argreg <= ARGLAST_REGNUM)
e5e33cd9 1155 {
6df2bf50 1156 /* there's room in a register */
e5e33cd9 1157 reg_size = register_size (gdbarch, argreg);
e17a4113 1158 regval = extract_unsigned_integer (val, reg_size, byte_order);
6df2bf50
MS		 1159 regcache_cooked_write_unsigned (regcache, argreg++, regval);
1160 }
c378eb4e
MS		 1161 /* Store the value one register at a time or in one step on
1162 stack. */
e5e33cd9
CV		 1163 len -= reg_size;
1164 val += reg_size;
6df2bf50
MS		 1165 }
1166 }
1167
c055b101
CV		 1168 if (struct_return)
1169 {
1170 if (sh_is_renesas_calling_convention (func_type))
1171 /* If the function uses the Renesas ABI, subtract another 4 bytes from
1172 the stack and store the struct return address there. */
e17a4113 1173 write_memory_unsigned_integer (sp -= 4, 4, byte_order, struct_addr);
c055b101
CV		 1174 else
1175 /* Using the gcc ABI, the "struct return pointer" pseudo-argument has
1176 its own dedicated register. */
1177 regcache_cooked_write_unsigned (regcache,
1178 STRUCT_RETURN_REGNUM, struct_addr);
1179 }
1180
c378eb4e 1181 /* Store return address. */
55ff77ac 1182 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
6df2bf50
MS		 1183
1184 /* Update stack pointer. */
3e8c568d 1185 regcache_cooked_write_unsigned (regcache,
b47193f7 1186 gdbarch_sp_regnum (gdbarch), sp);
6df2bf50
MS		 1187
1188 return sp;
1189}
1190
1191static CORE_ADDR
617daa0e 1192sh_push_dummy_call_nofpu (struct gdbarch *gdbarch,
7d9b040b 1193 struct value *function,
617daa0e
CV		 1194 struct regcache *regcache,
1195 CORE_ADDR bp_addr,
1196 int nargs, struct value **args,
1197 CORE_ADDR sp, int struct_return,
6df2bf50 1198 CORE_ADDR struct_addr)
c906108c 1199{
e17a4113 1200 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
e5e33cd9
CV		 1201 int stack_offset = 0;
1202 int argreg = ARG0_REGNUM;
c906108c 1203 int argnum;
c055b101 1204 struct type *func_type = value_type (function);
c906108c
SS		 1205 struct type *type;
1206 CORE_ADDR regval;
1207 char *val;
c055b101
CV		 1208 int len, reg_size = 0;
1209 int pass_on_stack = 0;
1210 int last_reg_arg = INT_MAX;
1211
1212 /* The Renesas ABI expects all varargs arguments, plus the last
1213 non-vararg argument to be on the stack, no matter how many
1214 registers have been used so far. */
1215 if (sh_is_renesas_calling_convention (func_type)
876cecd0 1216 && TYPE_VARARGS (func_type))
c055b101 1217 last_reg_arg = TYPE_NFIELDS (func_type) - 2;
c906108c 1218
c378eb4e 1219 /* First force sp to a 4-byte alignment. */
19f59343 1220 sp = sh_frame_align (gdbarch, sp);
c906108c 1221
c378eb4e 1222 /* Make room on stack for args. */
e5e33cd9 1223 sp -= sh_stack_allocsize (nargs, args);
c906108c 1224
c906108c
SS		 1225 /* Now load as many as possible of the first arguments into
1226 registers, and push the rest onto the stack. There are 16 bytes
1227 in four registers available. Loop thru args from first to last. */
e5e33cd9 1228 for (argnum = 0; argnum < nargs; argnum++)
617daa0e 1229 {
4991999e 1230 type = value_type (args[argnum]);
c5aa993b 1231 len = TYPE_LENGTH (type);
d93859e2 1232 val = sh_justify_value_in_reg (gdbarch, args[argnum], len);
c906108c 1233
c055b101 1234 /* Some decisions have to be made how various types are handled.
c378eb4e 1235 This also differs in different ABIs. */
c055b101
CV		 1236 pass_on_stack = 0;
1237 /* Renesas ABI pushes doubles and long longs entirely on stack.
1238 Same goes for aggregate types. */
1239 if (sh_is_renesas_calling_convention (func_type)
1240 && ((TYPE_CODE (type) == TYPE_CODE_INT && len >= 8)
1241 || (TYPE_CODE (type) == TYPE_CODE_FLT && len >= 8)
1242 || TYPE_CODE (type) == TYPE_CODE_STRUCT
1243 || TYPE_CODE (type) == TYPE_CODE_UNION))
1244 pass_on_stack = 1;
c906108c
SS		 1245 while (len > 0)
1246 {
c055b101
CV		 1247 if (argreg > ARGLAST_REGNUM || pass_on_stack
1248 || argnum > last_reg_arg)
617daa0e 1249 {
e5e33cd9 1250 /* The remainder of the data goes entirely on the stack,
c378eb4e 1251 4-byte aligned. */
e5e33cd9
CV		 1252 reg_size = (len + 3) & ~3;
1253 write_memory (sp + stack_offset, val, reg_size);
617daa0e 1254 stack_offset += reg_size;
c906108c 1255 }
e5e33cd9 1256 else if (argreg <= ARGLAST_REGNUM)
617daa0e 1257 {
c378eb4e 1258 /* There's room in a register. */
e5e33cd9 1259 reg_size = register_size (gdbarch, argreg);
e17a4113 1260 regval = extract_unsigned_integer (val, reg_size, byte_order);
48db5a3c 1261 regcache_cooked_write_unsigned (regcache, argreg++, regval);
c906108c 1262 }
e5e33cd9
CV		 1263 /* Store the value reg_size bytes at a time. This means that things
1264 larger than reg_size bytes may go partly in registers and partly
c906108c 1265 on the stack. */
e5e33cd9
CV		 1266 len -= reg_size;
1267 val += reg_size;
c906108c
SS		 1268 }
1269 }
48db5a3c 1270
c055b101
CV		 1271 if (struct_return)
1272 {
1273 if (sh_is_renesas_calling_convention (func_type))
1274 /* If the function uses the Renesas ABI, subtract another 4 bytes from
1275 the stack and store the struct return address there. */
e17a4113 1276 write_memory_unsigned_integer (sp -= 4, 4, byte_order, struct_addr);
c055b101
CV		 1277 else
1278 /* Using the gcc ABI, the "struct return pointer" pseudo-argument has
1279 its own dedicated register. */
1280 regcache_cooked_write_unsigned (regcache,
1281 STRUCT_RETURN_REGNUM, struct_addr);
1282 }
1283
c378eb4e 1284 /* Store return address. */
55ff77ac 1285 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
48db5a3c
CV		 1286
1287 /* Update stack pointer. */
3e8c568d 1288 regcache_cooked_write_unsigned (regcache,
b47193f7 1289 gdbarch_sp_regnum (gdbarch), sp);
48db5a3c 1290
c906108c
SS		 1291 return sp;
1292}
1293
cc17453a
EZ		 1294/* Find a function's return value in the appropriate registers (in
1295 regbuf), and copy it into valbuf. Extract from an array REGBUF
1296 containing the (raw) register state a function return value of type
1297 TYPE, and copy that, in virtual format, into VALBUF. */
1298static void
3ffc5b9b
CV		 1299sh_extract_return_value_nofpu (struct type *type, struct regcache *regcache,
1300 void *valbuf)
c906108c 1301{
e17a4113
UW		 1302 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1303 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
cc17453a 1304 int len = TYPE_LENGTH (type);
3116c80a
EZ		 1305 int return_register = R0_REGNUM;
1306 int offset;
617daa0e 1307
cc17453a 1308 if (len <= 4)
3116c80a 1309 {
48db5a3c
CV		 1310 ULONGEST c;
1311
1312 regcache_cooked_read_unsigned (regcache, R0_REGNUM, &c);
e17a4113 1313 store_unsigned_integer (valbuf, len, byte_order, c);
3116c80a 1314 }
48db5a3c 1315 else if (len == 8)
3116c80a 1316 {
48db5a3c
CV		 1317 int i, regnum = R0_REGNUM;
1318 for (i = 0; i < len; i += 4)
617daa0e 1319 regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
3116c80a
EZ		 1320 }
1321 else
8a3fe4f8 1322 error (_("bad size for return value"));
3116c80a
EZ		 1323}
1324
1325static void
3ffc5b9b
CV		 1326sh_extract_return_value_fpu (struct type *type, struct regcache *regcache,
1327 void *valbuf)
3116c80a 1328{
d93859e2 1329 struct gdbarch *gdbarch = get_regcache_arch (regcache);
afce3d2a 1330 if (sh_treat_as_flt_p (type))
3116c80a 1331 {
48db5a3c 1332 int len = TYPE_LENGTH (type);
d93859e2 1333 int i, regnum = gdbarch_fp0_regnum (gdbarch);
48db5a3c 1334 for (i = 0; i < len; i += 4)
d93859e2 1335 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
c378eb4e
MS		 1336 regcache_raw_read (regcache, regnum++,
1337 (char *) valbuf + len - 4 - i);
2e952408
CV		 1338 else
1339 regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
3116c80a 1340 }
cc17453a 1341 else
3ffc5b9b 1342 sh_extract_return_value_nofpu (type, regcache, valbuf);
cc17453a 1343}
c906108c 1344
cc17453a
EZ		 1345/* Write into appropriate registers a function return value
1346 of type TYPE, given in virtual format.
1347 If the architecture is sh4 or sh3e, store a function's return value
1348 in the R0 general register or in the FP0 floating point register,
c378eb4e
MS		 1349 depending on the type of the return value. In all the other cases
1350 the result is stored in r0, left-justified. */
cc17453a 1351static void
3ffc5b9b
CV		 1352sh_store_return_value_nofpu (struct type *type, struct regcache *regcache,
1353 const void *valbuf)
cc17453a 1354{
e17a4113
UW		 1355 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1356 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
48db5a3c
CV		 1357 ULONGEST val;
1358 int len = TYPE_LENGTH (type);
d19b71be 1359
48db5a3c 1360 if (len <= 4)
d19b71be 1361 {
e17a4113 1362 val = extract_unsigned_integer (valbuf, len, byte_order);
48db5a3c 1363 regcache_cooked_write_unsigned (regcache, R0_REGNUM, val);
d19b71be
MS		 1364 }
1365 else
48db5a3c
CV		 1366 {
1367 int i, regnum = R0_REGNUM;
1368 for (i = 0; i < len; i += 4)
617daa0e 1369 regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
48db5a3c 1370 }
cc17453a 1371}
c906108c 1372
cc17453a 1373static void
3ffc5b9b
CV		 1374sh_store_return_value_fpu (struct type *type, struct regcache *regcache,
1375 const void *valbuf)
cc17453a 1376{
d93859e2 1377 struct gdbarch *gdbarch = get_regcache_arch (regcache);
afce3d2a 1378 if (sh_treat_as_flt_p (type))
48db5a3c
CV		 1379 {
1380 int len = TYPE_LENGTH (type);
d93859e2 1381 int i, regnum = gdbarch_fp0_regnum (gdbarch);
48db5a3c 1382 for (i = 0; i < len; i += 4)
d93859e2 1383 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
c8a3b559
CV		 1384 regcache_raw_write (regcache, regnum++,
1385 (char *) valbuf + len - 4 - i);
1386 else
1387 regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
48db5a3c 1388 }
cc17453a 1389 else
3ffc5b9b 1390 sh_store_return_value_nofpu (type, regcache, valbuf);
c906108c
SS		 1391}
1392
c0409442 1393static enum return_value_convention
c055b101
CV		 1394sh_return_value_nofpu (struct gdbarch *gdbarch, struct type *func_type,
1395 struct type *type, struct regcache *regcache,
18cf8b5b 1396 gdb_byte *readbuf, const gdb_byte *writebuf)
c0409442 1397{
c055b101
CV		 1398 if (sh_use_struct_convention_nofpu (
1399 sh_is_renesas_calling_convention (func_type), type))
c0409442
CV		 1400 return RETURN_VALUE_STRUCT_CONVENTION;
1401 if (writebuf)
3ffc5b9b 1402 sh_store_return_value_nofpu (type, regcache, writebuf);
c0409442 1403 else if (readbuf)
3ffc5b9b 1404 sh_extract_return_value_nofpu (type, regcache, readbuf);
c0409442
CV		 1405 return RETURN_VALUE_REGISTER_CONVENTION;
1406}
1407
1408static enum return_value_convention
c055b101
CV		 1409sh_return_value_fpu (struct gdbarch *gdbarch, struct type *func_type,
1410 struct type *type, struct regcache *regcache,
18cf8b5b 1411 gdb_byte *readbuf, const gdb_byte *writebuf)
c0409442 1412{
c055b101
CV		 1413 if (sh_use_struct_convention (
1414 sh_is_renesas_calling_convention (func_type), type))
c0409442
CV		 1415 return RETURN_VALUE_STRUCT_CONVENTION;
1416 if (writebuf)
3ffc5b9b 1417 sh_store_return_value_fpu (type, regcache, writebuf);
c0409442 1418 else if (readbuf)
3ffc5b9b 1419 sh_extract_return_value_fpu (type, regcache, readbuf);
c0409442
CV		 1420 return RETURN_VALUE_REGISTER_CONVENTION;
1421}
1422
c378eb4e 1423/* Print the registers in a form similar to the E7000. */
c906108c
SS		 1424
1425static void
c458d6db 1426sh_generic_show_regs (struct frame_info *frame)
c906108c 1427{
c458d6db
UW		 1428 printf_filtered
1429 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 1430 phex (get_frame_register_unsigned (frame,
1431 gdbarch_pc_regnum
1432 (get_frame_arch (frame))), 4),
c458d6db
UW		 1433 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1434 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1435 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
cc17453a 1436
c458d6db
UW		 1437 printf_filtered
1438 (" GBR %08lx VBR %08lx MACL %08lx\n",
1439 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1440 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1441 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
cc17453a 1442
617daa0e 1443 printf_filtered
a6b0a3f3 1444 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
c458d6db
UW		 1445 (long) get_frame_register_unsigned (frame, 0),
1446 (long) get_frame_register_unsigned (frame, 1),
1447 (long) get_frame_register_unsigned (frame, 2),
1448 (long) get_frame_register_unsigned (frame, 3),
1449 (long) get_frame_register_unsigned (frame, 4),
1450 (long) get_frame_register_unsigned (frame, 5),
1451 (long) get_frame_register_unsigned (frame, 6),
1452 (long) get_frame_register_unsigned (frame, 7));
1453 printf_filtered
1454 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1455 (long) get_frame_register_unsigned (frame, 8),
1456 (long) get_frame_register_unsigned (frame, 9),
1457 (long) get_frame_register_unsigned (frame, 10),
1458 (long) get_frame_register_unsigned (frame, 11),
1459 (long) get_frame_register_unsigned (frame, 12),
1460 (long) get_frame_register_unsigned (frame, 13),
1461 (long) get_frame_register_unsigned (frame, 14),
1462 (long) get_frame_register_unsigned (frame, 15));
cc17453a 1463}
c906108c 1464
cc17453a 1465static void
c458d6db 1466sh3_show_regs (struct frame_info *frame)
cc17453a 1467{
c458d6db
UW		 1468 printf_filtered
1469 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 1470 phex (get_frame_register_unsigned (frame,
1471 gdbarch_pc_regnum
1472 (get_frame_arch (frame))), 4),
c458d6db
UW		 1473 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1474 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1475 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1476
1477 printf_filtered
1478 (" GBR %08lx VBR %08lx MACL %08lx\n",
1479 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1480 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1481 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1482 printf_filtered
1483 (" SSR %08lx SPC %08lx\n",
1484 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1485 (long) get_frame_register_unsigned (frame, SPC_REGNUM));
c906108c 1486
617daa0e 1487 printf_filtered
a6b0a3f3 1488 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
c458d6db
UW		 1489 (long) get_frame_register_unsigned (frame, 0),
1490 (long) get_frame_register_unsigned (frame, 1),
1491 (long) get_frame_register_unsigned (frame, 2),
1492 (long) get_frame_register_unsigned (frame, 3),
1493 (long) get_frame_register_unsigned (frame, 4),
1494 (long) get_frame_register_unsigned (frame, 5),
1495 (long) get_frame_register_unsigned (frame, 6),
1496 (long) get_frame_register_unsigned (frame, 7));
1497 printf_filtered
1498 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1499 (long) get_frame_register_unsigned (frame, 8),
1500 (long) get_frame_register_unsigned (frame, 9),
1501 (long) get_frame_register_unsigned (frame, 10),
1502 (long) get_frame_register_unsigned (frame, 11),
1503 (long) get_frame_register_unsigned (frame, 12),
1504 (long) get_frame_register_unsigned (frame, 13),
1505 (long) get_frame_register_unsigned (frame, 14),
1506 (long) get_frame_register_unsigned (frame, 15));
c906108c
SS		 1507}
1508
2d188dd3 1509static void
c458d6db 1510sh2e_show_regs (struct frame_info *frame)
2d188dd3 1511{
b47193f7 1512 struct gdbarch *gdbarch = get_frame_arch (frame);
c458d6db
UW		 1513 printf_filtered
1514 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 1515 phex (get_frame_register_unsigned (frame,
1516 gdbarch_pc_regnum (gdbarch)), 4),
c458d6db
UW		 1517 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1518 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1519 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1520
1521 printf_filtered
1522 (" GBR %08lx VBR %08lx MACL %08lx\n",
1523 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1524 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1525 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1526 printf_filtered
1527 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1528 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1529 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1530 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1531 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
617daa0e
CV		 1532
1533 printf_filtered
a6b0a3f3 1534 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
c458d6db
UW		 1535 (long) get_frame_register_unsigned (frame, 0),
1536 (long) get_frame_register_unsigned (frame, 1),
1537 (long) get_frame_register_unsigned (frame, 2),
1538 (long) get_frame_register_unsigned (frame, 3),
1539 (long) get_frame_register_unsigned (frame, 4),
1540 (long) get_frame_register_unsigned (frame, 5),
1541 (long) get_frame_register_unsigned (frame, 6),
1542 (long) get_frame_register_unsigned (frame, 7));
1543 printf_filtered
1544 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1545 (long) get_frame_register_unsigned (frame, 8),
1546 (long) get_frame_register_unsigned (frame, 9),
1547 (long) get_frame_register_unsigned (frame, 10),
1548 (long) get_frame_register_unsigned (frame, 11),
1549 (long) get_frame_register_unsigned (frame, 12),
1550 (long) get_frame_register_unsigned (frame, 13),
1551 (long) get_frame_register_unsigned (frame, 14),
1552 (long) get_frame_register_unsigned (frame, 15));
1553
1554 printf_filtered
1555 ("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
3e8c568d 1556 (long) get_frame_register_unsigned
b47193f7 1557 (frame, gdbarch_fp0_regnum (gdbarch) + 0),
3e8c568d 1558 (long) get_frame_register_unsigned
b47193f7 1559 (frame, gdbarch_fp0_regnum (gdbarch) + 1),
3e8c568d 1560 (long) get_frame_register_unsigned
b47193f7 1561 (frame, gdbarch_fp0_regnum (gdbarch) + 2),
3e8c568d 1562 (long) get_frame_register_unsigned
b47193f7 1563 (frame, gdbarch_fp0_regnum (gdbarch) + 3),
3e8c568d 1564 (long) get_frame_register_unsigned
b47193f7 1565 (frame, gdbarch_fp0_regnum (gdbarch) + 4),
3e8c568d 1566 (long) get_frame_register_unsigned
b47193f7 1567 (frame, gdbarch_fp0_regnum (gdbarch) + 5),
3e8c568d 1568 (long) get_frame_register_unsigned
b47193f7 1569 (frame, gdbarch_fp0_regnum (gdbarch) + 6),
3e8c568d 1570 (long) get_frame_register_unsigned
b47193f7 1571 (frame, gdbarch_fp0_regnum (gdbarch) + 7));
c458d6db
UW		 1572 printf_filtered
1573 ("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
3e8c568d 1574 (long) get_frame_register_unsigned
b47193f7 1575 (frame, gdbarch_fp0_regnum (gdbarch) + 8),
3e8c568d 1576 (long) get_frame_register_unsigned
b47193f7 1577 (frame, gdbarch_fp0_regnum (gdbarch) + 9),
3e8c568d 1578 (long) get_frame_register_unsigned
b47193f7 1579 (frame, gdbarch_fp0_regnum (gdbarch) + 10),
3e8c568d 1580 (long) get_frame_register_unsigned
b47193f7 1581 (frame, gdbarch_fp0_regnum (gdbarch) + 11),
3e8c568d 1582 (long) get_frame_register_unsigned
b47193f7 1583 (frame, gdbarch_fp0_regnum (gdbarch) + 12),
3e8c568d 1584 (long) get_frame_register_unsigned
b47193f7 1585 (frame, gdbarch_fp0_regnum (gdbarch) + 13),
3e8c568d 1586 (long) get_frame_register_unsigned
b47193f7 1587 (frame, gdbarch_fp0_regnum (gdbarch) + 14),
3e8c568d 1588 (long) get_frame_register_unsigned
b47193f7 1589 (frame, gdbarch_fp0_regnum (gdbarch) + 15));
2d188dd3
NC		 1590}
1591
da962468 1592static void
c458d6db 1593sh2a_show_regs (struct frame_info *frame)
da962468 1594{
b47193f7 1595 struct gdbarch *gdbarch = get_frame_arch (frame);
c458d6db
UW		 1596 int pr = get_frame_register_unsigned (frame, FPSCR_REGNUM) & 0x80000;
1597
1598 printf_filtered
1599 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 1600 phex (get_frame_register_unsigned (frame,
1601 gdbarch_pc_regnum (gdbarch)), 4),
c458d6db
UW		 1602 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1603 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1604 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1605
1606 printf_filtered
1607 (" GBR %08lx VBR %08lx TBR %08lx MACL %08lx\n",
1608 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1609 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1610 (long) get_frame_register_unsigned (frame, TBR_REGNUM),
1611 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1612 printf_filtered
1613 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1614 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1615 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1616 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1617 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1618
1619 printf_filtered
1620 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1621 (long) get_frame_register_unsigned (frame, 0),
1622 (long) get_frame_register_unsigned (frame, 1),
1623 (long) get_frame_register_unsigned (frame, 2),
1624 (long) get_frame_register_unsigned (frame, 3),
1625 (long) get_frame_register_unsigned (frame, 4),
1626 (long) get_frame_register_unsigned (frame, 5),
1627 (long) get_frame_register_unsigned (frame, 6),
1628 (long) get_frame_register_unsigned (frame, 7));
1629 printf_filtered
1630 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1631 (long) get_frame_register_unsigned (frame, 8),
1632 (long) get_frame_register_unsigned (frame, 9),
1633 (long) get_frame_register_unsigned (frame, 10),
1634 (long) get_frame_register_unsigned (frame, 11),
1635 (long) get_frame_register_unsigned (frame, 12),
1636 (long) get_frame_register_unsigned (frame, 13),
1637 (long) get_frame_register_unsigned (frame, 14),
1638 (long) get_frame_register_unsigned (frame, 15));
1639
1640 printf_filtered
1641 (pr ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1642 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
3e8c568d 1643 (long) get_frame_register_unsigned
b47193f7 1644 (frame, gdbarch_fp0_regnum (gdbarch) + 0),
3e8c568d 1645 (long) get_frame_register_unsigned
b47193f7 1646 (frame, gdbarch_fp0_regnum (gdbarch) + 1),
3e8c568d 1647 (long) get_frame_register_unsigned
b47193f7 1648 (frame, gdbarch_fp0_regnum (gdbarch) + 2),
3e8c568d 1649 (long) get_frame_register_unsigned
b47193f7 1650 (frame, gdbarch_fp0_regnum (gdbarch) + 3),
3e8c568d 1651 (long) get_frame_register_unsigned
b47193f7 1652 (frame, gdbarch_fp0_regnum (gdbarch) + 4),
3e8c568d 1653 (long) get_frame_register_unsigned
b47193f7 1654 (frame, gdbarch_fp0_regnum (gdbarch) + 5),
3e8c568d 1655 (long) get_frame_register_unsigned
b47193f7 1656 (frame, gdbarch_fp0_regnum (gdbarch) + 6),
3e8c568d 1657 (long) get_frame_register_unsigned
b47193f7 1658 (frame, gdbarch_fp0_regnum (gdbarch) + 7));
c458d6db
UW		 1659 printf_filtered
1660 (pr ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1661 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
3e8c568d 1662 (long) get_frame_register_unsigned
b47193f7 1663 (frame, gdbarch_fp0_regnum (gdbarch) + 8),
3e8c568d 1664 (long) get_frame_register_unsigned
b47193f7 1665 (frame, gdbarch_fp0_regnum (gdbarch) + 9),
3e8c568d 1666 (long) get_frame_register_unsigned
b47193f7 1667 (frame, gdbarch_fp0_regnum (gdbarch) + 10),
3e8c568d 1668 (long) get_frame_register_unsigned
b47193f7 1669 (frame, gdbarch_fp0_regnum (gdbarch) + 11),
3e8c568d 1670 (long) get_frame_register_unsigned
b47193f7 1671 (frame, gdbarch_fp0_regnum (gdbarch) + 12),
3e8c568d 1672 (long) get_frame_register_unsigned
b47193f7 1673 (frame, gdbarch_fp0_regnum (gdbarch) + 13),
3e8c568d 1674 (long) get_frame_register_unsigned
b47193f7 1675 (frame, gdbarch_fp0_regnum (gdbarch) + 14),
3e8c568d 1676 (long) get_frame_register_unsigned
b47193f7 1677 (frame, gdbarch_fp0_regnum (gdbarch) + 15));
c458d6db
UW		 1678 printf_filtered
1679 ("BANK=%-3d\n", (int) get_frame_register_unsigned (frame, BANK_REGNUM));
1680 printf_filtered
1681 ("R0b-R7b %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1682 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 0),
1683 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 1),
1684 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 2),
1685 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 3),
1686 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 4),
1687 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 5),
1688 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 6),
1689 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 7));
1690 printf_filtered
1691 ("R8b-R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1692 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 8),
1693 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 9),
1694 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 10),
1695 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 11),
1696 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 12),
1697 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 13),
1698 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 14));
1699 printf_filtered
1700 ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n",
1701 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 15),
1702 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 16),
1703 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 17),
1704 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 18),
1705 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 19));
da962468
CV		 1706}
1707
1708static void
c458d6db 1709sh2a_nofpu_show_regs (struct frame_info *frame)
da962468 1710{
c458d6db
UW		 1711 int pr = get_frame_register_unsigned (frame, FPSCR_REGNUM) & 0x80000;
1712
1713 printf_filtered
1714 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 1715 phex (get_frame_register_unsigned (frame,
1716 gdbarch_pc_regnum
1717 (get_frame_arch (frame))), 4),
c458d6db
UW		 1718 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1719 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1720 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1721
1722 printf_filtered
1723 (" GBR %08lx VBR %08lx TBR %08lx MACL %08lx\n",
1724 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1725 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1726 (long) get_frame_register_unsigned (frame, TBR_REGNUM),
1727 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1728 printf_filtered
1729 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1730 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1731 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1732 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1733 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1734
1735 printf_filtered
1736 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1737 (long) get_frame_register_unsigned (frame, 0),
1738 (long) get_frame_register_unsigned (frame, 1),
1739 (long) get_frame_register_unsigned (frame, 2),
1740 (long) get_frame_register_unsigned (frame, 3),
1741 (long) get_frame_register_unsigned (frame, 4),
1742 (long) get_frame_register_unsigned (frame, 5),
1743 (long) get_frame_register_unsigned (frame, 6),
1744 (long) get_frame_register_unsigned (frame, 7));
1745 printf_filtered
1746 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1747 (long) get_frame_register_unsigned (frame, 8),
1748 (long) get_frame_register_unsigned (frame, 9),
1749 (long) get_frame_register_unsigned (frame, 10),
1750 (long) get_frame_register_unsigned (frame, 11),
1751 (long) get_frame_register_unsigned (frame, 12),
1752 (long) get_frame_register_unsigned (frame, 13),
1753 (long) get_frame_register_unsigned (frame, 14),
1754 (long) get_frame_register_unsigned (frame, 15));
1755
1756 printf_filtered
1757 ("BANK=%-3d\n", (int) get_frame_register_unsigned (frame, BANK_REGNUM));
1758 printf_filtered
1759 ("R0b-R7b %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1760 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 0),
1761 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 1),
1762 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 2),
1763 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 3),
1764 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 4),
1765 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 5),
1766 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 6),
1767 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 7));
1768 printf_filtered
1769 ("R8b-R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1770 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 8),
1771 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 9),
1772 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 10),
1773 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 11),
1774 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 12),
1775 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 13),
1776 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 14));
1777 printf_filtered
1778 ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n",
1779 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 15),
1780 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 16),
1781 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 17),
1782 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 18),
1783 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 19));
da962468
CV		 1784}
1785
cc17453a 1786static void
c458d6db 1787sh3e_show_regs (struct frame_info *frame)
cc17453a 1788{
b47193f7 1789 struct gdbarch *gdbarch = get_frame_arch (frame);
c458d6db
UW		 1790 printf_filtered
1791 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 1792 phex (get_frame_register_unsigned (frame,
1793 gdbarch_pc_regnum (gdbarch)), 4),
c458d6db
UW		 1794 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1795 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1796 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1797
1798 printf_filtered
1799 (" GBR %08lx VBR %08lx MACL %08lx\n",
1800 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1801 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1802 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1803 printf_filtered
1804 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1805 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1806 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1807 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1808 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
c906108c 1809
617daa0e 1810 printf_filtered
a6b0a3f3 1811 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
c458d6db
UW		 1812 (long) get_frame_register_unsigned (frame, 0),
1813 (long) get_frame_register_unsigned (frame, 1),
1814 (long) get_frame_register_unsigned (frame, 2),
1815 (long) get_frame_register_unsigned (frame, 3),
1816 (long) get_frame_register_unsigned (frame, 4),
1817 (long) get_frame_register_unsigned (frame, 5),
1818 (long) get_frame_register_unsigned (frame, 6),
1819 (long) get_frame_register_unsigned (frame, 7));
1820 printf_filtered
1821 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1822 (long) get_frame_register_unsigned (frame, 8),
1823 (long) get_frame_register_unsigned (frame, 9),
1824 (long) get_frame_register_unsigned (frame, 10),
1825 (long) get_frame_register_unsigned (frame, 11),
1826 (long) get_frame_register_unsigned (frame, 12),
1827 (long) get_frame_register_unsigned (frame, 13),
1828 (long) get_frame_register_unsigned (frame, 14),
1829 (long) get_frame_register_unsigned (frame, 15));
1830
1831 printf_filtered
1832 ("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
3e8c568d 1833 (long) get_frame_register_unsigned
b47193f7 1834 (frame, gdbarch_fp0_regnum (gdbarch) + 0),
3e8c568d 1835 (long) get_frame_register_unsigned
b47193f7 1836 (frame, gdbarch_fp0_regnum (gdbarch) + 1),
3e8c568d 1837 (long) get_frame_register_unsigned
b47193f7 1838 (frame, gdbarch_fp0_regnum (gdbarch) + 2),
3e8c568d 1839 (long) get_frame_register_unsigned
b47193f7 1840 (frame, gdbarch_fp0_regnum (gdbarch) + 3),
3e8c568d 1841 (long) get_frame_register_unsigned
b47193f7 1842 (frame, gdbarch_fp0_regnum (gdbarch) + 4),
3e8c568d 1843 (long) get_frame_register_unsigned
b47193f7 1844 (frame, gdbarch_fp0_regnum (gdbarch) + 5),
3e8c568d 1845 (long) get_frame_register_unsigned
b47193f7 1846 (frame, gdbarch_fp0_regnum (gdbarch) + 6),
3e8c568d 1847 (long) get_frame_register_unsigned
b47193f7 1848 (frame, gdbarch_fp0_regnum (gdbarch) + 7));
c458d6db
UW		 1849 printf_filtered
1850 ("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
3e8c568d 1851 (long) get_frame_register_unsigned
b47193f7 1852 (frame, gdbarch_fp0_regnum (gdbarch) + 8),
3e8c568d 1853 (long) get_frame_register_unsigned
b47193f7 1854 (frame, gdbarch_fp0_regnum (gdbarch) + 9),
3e8c568d 1855 (long) get_frame_register_unsigned
b47193f7 1856 (frame, gdbarch_fp0_regnum (gdbarch) + 10),
3e8c568d 1857 (long) get_frame_register_unsigned
b47193f7 1858 (frame, gdbarch_fp0_regnum (gdbarch) + 11),
3e8c568d 1859 (long) get_frame_register_unsigned
b47193f7 1860 (frame, gdbarch_fp0_regnum (gdbarch) + 12),
3e8c568d 1861 (long) get_frame_register_unsigned
b47193f7 1862 (frame, gdbarch_fp0_regnum (gdbarch) + 13),
3e8c568d 1863 (long) get_frame_register_unsigned
b47193f7 1864 (frame, gdbarch_fp0_regnum (gdbarch) + 14),
3e8c568d 1865 (long) get_frame_register_unsigned
b47193f7 1866 (frame, gdbarch_fp0_regnum (gdbarch) + 15));
cc17453a
EZ		 1867}
1868
1869static void
c458d6db 1870sh3_dsp_show_regs (struct frame_info *frame)
c906108c 1871{
c458d6db
UW		 1872 printf_filtered
1873 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 1874 phex (get_frame_register_unsigned (frame,
1875 gdbarch_pc_regnum
1876 (get_frame_arch (frame))), 4),
c458d6db
UW		 1877 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1878 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1879 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
c906108c 1880
c458d6db
UW		 1881 printf_filtered
1882 (" GBR %08lx VBR %08lx MACL %08lx\n",
1883 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1884 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1885 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
cc17453a 1886
c458d6db
UW		 1887 printf_filtered
1888 (" SSR %08lx SPC %08lx DSR %08lx\n",
1889 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1890 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1891 (long) get_frame_register_unsigned (frame, DSR_REGNUM));
617daa0e
CV		 1892
1893 printf_filtered
a6b0a3f3 1894 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
c458d6db
UW		 1895 (long) get_frame_register_unsigned (frame, 0),
1896 (long) get_frame_register_unsigned (frame, 1),
1897 (long) get_frame_register_unsigned (frame, 2),
1898 (long) get_frame_register_unsigned (frame, 3),
1899 (long) get_frame_register_unsigned (frame, 4),
1900 (long) get_frame_register_unsigned (frame, 5),
1901 (long) get_frame_register_unsigned (frame, 6),
1902 (long) get_frame_register_unsigned (frame, 7));
1903 printf_filtered
1904 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1905 (long) get_frame_register_unsigned (frame, 8),
1906 (long) get_frame_register_unsigned (frame, 9),
1907 (long) get_frame_register_unsigned (frame, 10),
1908 (long) get_frame_register_unsigned (frame, 11),
1909 (long) get_frame_register_unsigned (frame, 12),
1910 (long) get_frame_register_unsigned (frame, 13),
1911 (long) get_frame_register_unsigned (frame, 14),
1912 (long) get_frame_register_unsigned (frame, 15));
617daa0e
CV		 1913
1914 printf_filtered
1915 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
c458d6db
UW		 1916 (long) get_frame_register_unsigned (frame, A0G_REGNUM) & 0xff,
1917 (long) get_frame_register_unsigned (frame, A0_REGNUM),
1918 (long) get_frame_register_unsigned (frame, M0_REGNUM),
1919 (long) get_frame_register_unsigned (frame, X0_REGNUM),
1920 (long) get_frame_register_unsigned (frame, Y0_REGNUM),
1921 (long) get_frame_register_unsigned (frame, RS_REGNUM),
1922 (long) get_frame_register_unsigned (frame, MOD_REGNUM));
1923 printf_filtered
1924 ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1925 (long) get_frame_register_unsigned (frame, A1G_REGNUM) & 0xff,
1926 (long) get_frame_register_unsigned (frame, A1_REGNUM),
1927 (long) get_frame_register_unsigned (frame, M1_REGNUM),
1928 (long) get_frame_register_unsigned (frame, X1_REGNUM),
1929 (long) get_frame_register_unsigned (frame, Y1_REGNUM),
1930 (long) get_frame_register_unsigned (frame, RE_REGNUM));
c906108c
SS		 1931}
1932
cc17453a 1933static void
c458d6db 1934sh4_show_regs (struct frame_info *frame)
cc17453a 1935{
b47193f7 1936 struct gdbarch *gdbarch = get_frame_arch (frame);
c458d6db
UW		 1937 int pr = get_frame_register_unsigned (frame, FPSCR_REGNUM) & 0x80000;
1938
1939 printf_filtered
1940 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 1941 phex (get_frame_register_unsigned (frame,
1942 gdbarch_pc_regnum (gdbarch)), 4),
c458d6db
UW		 1943 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1944 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1945 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1946
1947 printf_filtered
1948 (" GBR %08lx VBR %08lx MACL %08lx\n",
1949 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1950 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1951 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1952 printf_filtered
1953 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1954 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1955 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1956 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1957 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1958
1959 printf_filtered
1960 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1961 (long) get_frame_register_unsigned (frame, 0),
1962 (long) get_frame_register_unsigned (frame, 1),
1963 (long) get_frame_register_unsigned (frame, 2),
1964 (long) get_frame_register_unsigned (frame, 3),
1965 (long) get_frame_register_unsigned (frame, 4),
1966 (long) get_frame_register_unsigned (frame, 5),
1967 (long) get_frame_register_unsigned (frame, 6),
1968 (long) get_frame_register_unsigned (frame, 7));
1969 printf_filtered
1970 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1971 (long) get_frame_register_unsigned (frame, 8),
1972 (long) get_frame_register_unsigned (frame, 9),
1973 (long) get_frame_register_unsigned (frame, 10),
1974 (long) get_frame_register_unsigned (frame, 11),
1975 (long) get_frame_register_unsigned (frame, 12),
1976 (long) get_frame_register_unsigned (frame, 13),
1977 (long) get_frame_register_unsigned (frame, 14),
1978 (long) get_frame_register_unsigned (frame, 15));
1979
1980 printf_filtered
1981 (pr ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1982 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
3e8c568d 1983 (long) get_frame_register_unsigned
b47193f7 1984 (frame, gdbarch_fp0_regnum (gdbarch) + 0),
3e8c568d 1985 (long) get_frame_register_unsigned
b47193f7 1986 (frame, gdbarch_fp0_regnum (gdbarch) + 1),
3e8c568d 1987 (long) get_frame_register_unsigned
b47193f7 1988 (frame, gdbarch_fp0_regnum (gdbarch) + 2),
3e8c568d 1989 (long) get_frame_register_unsigned
b47193f7 1990 (frame, gdbarch_fp0_regnum (gdbarch) + 3),
3e8c568d 1991 (long) get_frame_register_unsigned
b47193f7 1992 (frame, gdbarch_fp0_regnum (gdbarch) + 4),
3e8c568d 1993 (long) get_frame_register_unsigned
b47193f7 1994 (frame, gdbarch_fp0_regnum (gdbarch) + 5),
3e8c568d 1995 (long) get_frame_register_unsigned
b47193f7 1996 (frame, gdbarch_fp0_regnum (gdbarch) + 6),
3e8c568d 1997 (long) get_frame_register_unsigned
b47193f7 1998 (frame, gdbarch_fp0_regnum (gdbarch) + 7));
c458d6db
UW		 1999 printf_filtered
2000 (pr ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
2001 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
3e8c568d 2002 (long) get_frame_register_unsigned
b47193f7 2003 (frame, gdbarch_fp0_regnum (gdbarch) + 8),
3e8c568d 2004 (long) get_frame_register_unsigned
b47193f7 2005 (frame, gdbarch_fp0_regnum (gdbarch) + 9),
3e8c568d 2006 (long) get_frame_register_unsigned
b47193f7 2007 (frame, gdbarch_fp0_regnum (gdbarch) + 10),
3e8c568d 2008 (long) get_frame_register_unsigned
b47193f7 2009 (frame, gdbarch_fp0_regnum (gdbarch) + 11),
3e8c568d 2010 (long) get_frame_register_unsigned
b47193f7 2011 (frame, gdbarch_fp0_regnum (gdbarch) + 12),
3e8c568d 2012 (long) get_frame_register_unsigned
b47193f7 2013 (frame, gdbarch_fp0_regnum (gdbarch) + 13),
3e8c568d 2014 (long) get_frame_register_unsigned
b47193f7 2015 (frame, gdbarch_fp0_regnum (gdbarch) + 14),
3e8c568d 2016 (long) get_frame_register_unsigned
b47193f7 2017 (frame, gdbarch_fp0_regnum (gdbarch) + 15));
cc17453a
EZ		 2018}
2019
474e5826 2020static void
c458d6db 2021sh4_nofpu_show_regs (struct frame_info *frame)
474e5826 2022{
c458d6db
UW		 2023 printf_filtered
2024 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 2025 phex (get_frame_register_unsigned (frame,
2026 gdbarch_pc_regnum
2027 (get_frame_arch (frame))), 4),
c458d6db
UW		 2028 (long) get_frame_register_unsigned (frame, SR_REGNUM),
2029 (long) get_frame_register_unsigned (frame, PR_REGNUM),
2030 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
2031
2032 printf_filtered
2033 (" GBR %08lx VBR %08lx MACL %08lx\n",
2034 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
2035 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
2036 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
2037 printf_filtered
2038 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
2039 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
2040 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
2041 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
2042 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
2043
2044 printf_filtered
2045 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2046 (long) get_frame_register_unsigned (frame, 0),
2047 (long) get_frame_register_unsigned (frame, 1),
2048 (long) get_frame_register_unsigned (frame, 2),
2049 (long) get_frame_register_unsigned (frame, 3),
2050 (long) get_frame_register_unsigned (frame, 4),
2051 (long) get_frame_register_unsigned (frame, 5),
2052 (long) get_frame_register_unsigned (frame, 6),
2053 (long) get_frame_register_unsigned (frame, 7));
2054 printf_filtered
2055 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2056 (long) get_frame_register_unsigned (frame, 8),
2057 (long) get_frame_register_unsigned (frame, 9),
2058 (long) get_frame_register_unsigned (frame, 10),
2059 (long) get_frame_register_unsigned (frame, 11),
2060 (long) get_frame_register_unsigned (frame, 12),
2061 (long) get_frame_register_unsigned (frame, 13),
2062 (long) get_frame_register_unsigned (frame, 14),
2063 (long) get_frame_register_unsigned (frame, 15));
474e5826
CV		 2064}
2065
cc17453a 2066static void
c458d6db 2067sh_dsp_show_regs (struct frame_info *frame)
cc17453a 2068{
c458d6db
UW		 2069 printf_filtered
2070 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 2071 phex (get_frame_register_unsigned (frame,
2072 gdbarch_pc_regnum
2073 (get_frame_arch (frame))), 4),
c458d6db
UW		 2074 (long) get_frame_register_unsigned (frame, SR_REGNUM),
2075 (long) get_frame_register_unsigned (frame, PR_REGNUM),
2076 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
a6b0a3f3 2077
c458d6db
UW		 2078 printf_filtered
2079 (" GBR %08lx VBR %08lx DSR %08lx MACL %08lx\n",
2080 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
2081 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
2082 (long) get_frame_register_unsigned (frame, DSR_REGNUM),
2083 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
617daa0e
CV		 2084
2085 printf_filtered
a6b0a3f3 2086 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
c458d6db
UW		 2087 (long) get_frame_register_unsigned (frame, 0),
2088 (long) get_frame_register_unsigned (frame, 1),
2089 (long) get_frame_register_unsigned (frame, 2),
2090 (long) get_frame_register_unsigned (frame, 3),
2091 (long) get_frame_register_unsigned (frame, 4),
2092 (long) get_frame_register_unsigned (frame, 5),
2093 (long) get_frame_register_unsigned (frame, 6),
2094 (long) get_frame_register_unsigned (frame, 7));
2095 printf_filtered
2096 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2097 (long) get_frame_register_unsigned (frame, 8),
2098 (long) get_frame_register_unsigned (frame, 9),
2099 (long) get_frame_register_unsigned (frame, 10),
2100 (long) get_frame_register_unsigned (frame, 11),
2101 (long) get_frame_register_unsigned (frame, 12),
2102 (long) get_frame_register_unsigned (frame, 13),
2103 (long) get_frame_register_unsigned (frame, 14),
2104 (long) get_frame_register_unsigned (frame, 15));
617daa0e
CV		 2105
2106 printf_filtered
2107 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
c458d6db
UW		 2108 (long) get_frame_register_unsigned (frame, A0G_REGNUM) & 0xff,
2109 (long) get_frame_register_unsigned (frame, A0_REGNUM),
2110 (long) get_frame_register_unsigned (frame, M0_REGNUM),
2111 (long) get_frame_register_unsigned (frame, X0_REGNUM),
2112 (long) get_frame_register_unsigned (frame, Y0_REGNUM),
2113 (long) get_frame_register_unsigned (frame, RS_REGNUM),
2114 (long) get_frame_register_unsigned (frame, MOD_REGNUM));
cc17453a 2115 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
c458d6db
UW		 2116 (long) get_frame_register_unsigned (frame, A1G_REGNUM) & 0xff,
2117 (long) get_frame_register_unsigned (frame, A1_REGNUM),
2118 (long) get_frame_register_unsigned (frame, M1_REGNUM),
2119 (long) get_frame_register_unsigned (frame, X1_REGNUM),
2120 (long) get_frame_register_unsigned (frame, Y1_REGNUM),
2121 (long) get_frame_register_unsigned (frame, RE_REGNUM));
cc17453a
EZ		 2122}
2123
a78f21af
AC		 2124static void
2125sh_show_regs_command (char *args, int from_tty)
53116e27
EZ		 2126{
2127 if (sh_show_regs)
c458d6db 2128 (*sh_show_regs) (get_current_frame ());
53116e27
EZ		 2129}
2130
da962468
CV		 2131static struct type *
2132sh_sh2a_register_type (struct gdbarch *gdbarch, int reg_nr)
2133{
b47193f7 2134 if ((reg_nr >= gdbarch_fp0_regnum (gdbarch)
da962468 2135 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
0dfff4cb 2136 return builtin_type (gdbarch)->builtin_float;
da962468 2137 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
0dfff4cb 2138 return builtin_type (gdbarch)->builtin_double;
da962468 2139 else
0dfff4cb 2140 return builtin_type (gdbarch)->builtin_int;
da962468
CV		 2141}
2142
cc17453a
EZ		 2143/* Return the GDB type object for the "standard" data type
2144 of data in register N. */
cc17453a 2145static struct type *
48db5a3c 2146sh_sh3e_register_type (struct gdbarch *gdbarch, int reg_nr)
cc17453a 2147{
b47193f7 2148 if ((reg_nr >= gdbarch_fp0_regnum (gdbarch)
617daa0e 2149 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
0dfff4cb 2150 return builtin_type (gdbarch)->builtin_float;
8db62801 2151 else
0dfff4cb 2152 return builtin_type (gdbarch)->builtin_int;
cc17453a
EZ		 2153}
2154
7f4dbe94 2155static struct type *
0dfff4cb 2156sh_sh4_build_float_register_type (struct gdbarch *gdbarch, int high)
7f4dbe94 2157{
e3506a9f
UW		 2158 return lookup_array_range_type (builtin_type (gdbarch)->builtin_float,
2159 0, high);
7f4dbe94
EZ		 2160}
2161
53116e27 2162static struct type *
48db5a3c 2163sh_sh4_register_type (struct gdbarch *gdbarch, int reg_nr)
53116e27 2164{
b47193f7 2165 if ((reg_nr >= gdbarch_fp0_regnum (gdbarch)
617daa0e 2166 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
0dfff4cb 2167 return builtin_type (gdbarch)->builtin_float;
617daa0e 2168 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
0dfff4cb 2169 return builtin_type (gdbarch)->builtin_double;
617daa0e 2170 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
0dfff4cb 2171 return sh_sh4_build_float_register_type (gdbarch, 3);
53116e27 2172 else
0dfff4cb 2173 return builtin_type (gdbarch)->builtin_int;
53116e27
EZ		 2174}
2175
cc17453a 2176static struct type *
48db5a3c 2177sh_default_register_type (struct gdbarch *gdbarch, int reg_nr)
cc17453a 2178{
0dfff4cb 2179 return builtin_type (gdbarch)->builtin_int;
cc17453a
EZ		 2180}
2181
dda63807
AS		 2182/* Is a register in a reggroup?
2183 The default code in reggroup.c doesn't identify system registers, some
2184 float registers or any of the vector registers.
2185 TODO: sh2a and dsp registers. */
63807e1d 2186static int
dda63807
AS		 2187sh_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2188 struct reggroup *reggroup)
2189{
b47193f7
UW		 2190 if (gdbarch_register_name (gdbarch, regnum) == NULL
2191 || *gdbarch_register_name (gdbarch, regnum) == '\0')
dda63807
AS		 2192 return 0;
2193
2194 if (reggroup == float_reggroup
2195 && (regnum == FPUL_REGNUM
2196 || regnum == FPSCR_REGNUM))
2197 return 1;
2198
2199 if (regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM)
2200 {
2201 if (reggroup == vector_reggroup || reggroup == float_reggroup)
2202 return 1;
2203 if (reggroup == general_reggroup)
2204 return 0;
2205 }
2206
2207 if (regnum == VBR_REGNUM
2208 || regnum == SR_REGNUM
2209 || regnum == FPSCR_REGNUM
2210 || regnum == SSR_REGNUM
2211 || regnum == SPC_REGNUM)
2212 {
2213 if (reggroup == system_reggroup)
2214 return 1;
2215 if (reggroup == general_reggroup)
2216 return 0;
2217 }
2218
2219 /* The default code can cope with any other registers. */
2220 return default_register_reggroup_p (gdbarch, regnum, reggroup);
2221}
2222
fb409745 2223/* On the sh4, the DRi pseudo registers are problematic if the target
c378eb4e 2224 is little endian. When the user writes one of those registers, for
fb409745
EZ		 2225 instance with 'ser var $dr0=1', we want the double to be stored
2226 like this:
2227 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
2228 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2229
2230 This corresponds to little endian byte order & big endian word
2231 order. However if we let gdb write the register w/o conversion, it
2232 will write fr0 and fr1 this way:
2233 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2234 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
2235 because it will consider fr0 and fr1 as a single LE stretch of memory.
2236
2237 To achieve what we want we must force gdb to store things in
2238 floatformat_ieee_double_littlebyte_bigword (which is defined in
2239 include/floatformat.h and libiberty/floatformat.c.
2240
2241 In case the target is big endian, there is no problem, the
2242 raw bytes will look like:
2243 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
2244 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2245
2246 The other pseudo registers (the FVs) also don't pose a problem
c378eb4e 2247 because they are stored as 4 individual FP elements. */
fb409745 2248
7bd872fe 2249static void
b66ba949
CV		 2250sh_register_convert_to_virtual (int regnum, struct type *type,
2251 char *from, char *to)
55ff77ac 2252{
617daa0e 2253 if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
283150cd
EZ		 2254 {
2255 DOUBLEST val;
617daa0e
CV		 2256 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
2257 from, &val);
55ff77ac 2258 store_typed_floating (to, type, val);
283150cd
EZ		 2259 }
2260 else
617daa0e
CV		 2261 error
2262 ("sh_register_convert_to_virtual called with non DR register number");
283150cd
EZ		 2263}
2264
2265static void
b66ba949
CV		 2266sh_register_convert_to_raw (struct type *type, int regnum,
2267 const void *from, void *to)
283150cd 2268{
617daa0e 2269 if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
283150cd 2270 {
48db5a3c 2271 DOUBLEST val = extract_typed_floating (from, type);
617daa0e
CV		 2272 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword,
2273 &val, to);
283150cd
EZ		 2274 }
2275 else
8a3fe4f8 2276 error (_("sh_register_convert_to_raw called with non DR register number"));
283150cd
EZ		 2277}
2278
c378eb4e 2279/* For vectors of 4 floating point registers. */
1c0159e0 2280static int
d93859e2 2281fv_reg_base_num (struct gdbarch *gdbarch, int fv_regnum)
1c0159e0
CV		 2282{
2283 int fp_regnum;
2284
d93859e2 2285 fp_regnum = gdbarch_fp0_regnum (gdbarch)
3e8c568d 2286 + (fv_regnum - FV0_REGNUM) * 4;
1c0159e0
CV		 2287 return fp_regnum;
2288}
2289
c378eb4e 2290/* For double precision floating point registers, i.e 2 fp regs. */
1c0159e0 2291static int
d93859e2 2292dr_reg_base_num (struct gdbarch *gdbarch, int dr_regnum)
1c0159e0
CV		 2293{
2294 int fp_regnum;
2295
d93859e2 2296 fp_regnum = gdbarch_fp0_regnum (gdbarch)
3e8c568d 2297 + (dr_regnum - DR0_REGNUM) * 2;
1c0159e0
CV		 2298 return fp_regnum;
2299}
2300
05d1431c
PA		 2301/* Concatenate PORTIONS contiguous raw registers starting at
2302 BASE_REGNUM into BUFFER. */
2303
2304static enum register_status
2305pseudo_register_read_portions (struct gdbarch *gdbarch,
2306 struct regcache *regcache,
2307 int portions,
2308 int base_regnum, gdb_byte *buffer)
2309{
2310 int portion;
2311
2312 for (portion = 0; portion < portions; portion++)
2313 {
2314 enum register_status status;
2315 gdb_byte *b;
2316
2317 b = buffer + register_size (gdbarch, base_regnum) * portion;
2318 status = regcache_raw_read (regcache, base_regnum + portion, b);
2319 if (status != REG_VALID)
2320 return status;
2321 }
2322
2323 return REG_VALID;
2324}
2325
2326static enum register_status
d8124050 2327sh_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
18cf8b5b 2328 int reg_nr, gdb_byte *buffer)
53116e27 2329{
05d1431c 2330 int base_regnum;
d9d9c31f 2331 char temp_buffer[MAX_REGISTER_SIZE];
05d1431c 2332 enum register_status status;
53116e27 2333
9bed62d7 2334 if (reg_nr == PSEUDO_BANK_REGNUM)
05d1431c
PA		 2335 return regcache_raw_read (regcache, BANK_REGNUM, buffer);
2336 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
7bd872fe 2337 {
d93859e2 2338 base_regnum = dr_reg_base_num (gdbarch, reg_nr);
7bd872fe 2339
c378eb4e 2340 /* Build the value in the provided buffer. */
7bd872fe 2341 /* Read the real regs for which this one is an alias. */
05d1431c
PA		 2342 status = pseudo_register_read_portions (gdbarch, regcache,
2343 2, base_regnum, temp_buffer);
2344 if (status == REG_VALID)
2345 {
2346 /* We must pay attention to the endiannes. */
2347 sh_register_convert_to_virtual (reg_nr,
2348 register_type (gdbarch, reg_nr),
2349 temp_buffer, buffer);
2350 }
2351 return status;
7bd872fe 2352 }
617daa0e 2353 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
53116e27 2354 {
d93859e2 2355 base_regnum = fv_reg_base_num (gdbarch, reg_nr);
7bd872fe
EZ		 2356
2357 /* Read the real regs for which this one is an alias. */
05d1431c
PA		 2358 return pseudo_register_read_portions (gdbarch, regcache,
2359 4, base_regnum, buffer);
53116e27 2360 }
05d1431c
PA		 2361 else
2362 gdb_assert_not_reached ("invalid pseudo register number");
53116e27
EZ		 2363}
2364
a78f21af 2365static void
d8124050 2366sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
18cf8b5b 2367 int reg_nr, const gdb_byte *buffer)
53116e27
EZ		 2368{
2369 int base_regnum, portion;
d9d9c31f 2370 char temp_buffer[MAX_REGISTER_SIZE];
53116e27 2371
9bed62d7
CV		 2372 if (reg_nr == PSEUDO_BANK_REGNUM)
2373 {
2374 /* When the bank register is written to, the whole register bank
2375 is switched and all values in the bank registers must be read
c378eb4e 2376 from the target/sim again. We're just invalidating the regcache
9bed62d7
CV		 2377 so that a re-read happens next time it's necessary. */
2378 int bregnum;
2379
2380 regcache_raw_write (regcache, BANK_REGNUM, buffer);
2381 for (bregnum = R0_BANK0_REGNUM; bregnum < MACLB_REGNUM; ++bregnum)
9c5ea4d9 2382 regcache_invalidate (regcache, bregnum);
9bed62d7
CV		 2383 }
2384 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
53116e27 2385 {
d93859e2 2386 base_regnum = dr_reg_base_num (gdbarch, reg_nr);
53116e27 2387
c378eb4e 2388 /* We must pay attention to the endiannes. */
7b9ee6a8 2389 sh_register_convert_to_raw (register_type (gdbarch, reg_nr),
b66ba949 2390 reg_nr, buffer, temp_buffer);
7bd872fe 2391
53116e27
EZ		 2392 /* Write the real regs for which this one is an alias. */
2393 for (portion = 0; portion < 2; portion++)
617daa0e 2394 regcache_raw_write (regcache, base_regnum + portion,
0818c12a 2395 (temp_buffer
617daa0e
CV		 2396 + register_size (gdbarch,
2397 base_regnum) * portion));
53116e27 2398 }
617daa0e 2399 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
53116e27 2400 {
d93859e2 2401 base_regnum = fv_reg_base_num (gdbarch, reg_nr);
53116e27
EZ		 2402
2403 /* Write the real regs for which this one is an alias. */
2404 for (portion = 0; portion < 4; portion++)
d8124050
AC		 2405 regcache_raw_write (regcache, base_regnum + portion,
2406 ((char *) buffer
617daa0e
CV		 2407 + register_size (gdbarch,
2408 base_regnum) * portion));
53116e27
EZ		 2409 }
2410}
2411
2f14585c 2412static int
e7faf938 2413sh_dsp_register_sim_regno (struct gdbarch *gdbarch, int nr)
2f14585c 2414{
e7faf938
MD		 2415 if (legacy_register_sim_regno (gdbarch, nr) < 0)
2416 return legacy_register_sim_regno (gdbarch, nr);
f2ea0907
CV		 2417 if (nr >= DSR_REGNUM && nr <= Y1_REGNUM)
2418 return nr - DSR_REGNUM + SIM_SH_DSR_REGNUM;
2419 if (nr == MOD_REGNUM)
2f14585c 2420 return SIM_SH_MOD_REGNUM;
f2ea0907 2421 if (nr == RS_REGNUM)
2f14585c 2422 return SIM_SH_RS_REGNUM;
f2ea0907 2423 if (nr == RE_REGNUM)
2f14585c 2424 return SIM_SH_RE_REGNUM;
76cd2bd9
CV		 2425 if (nr >= DSP_R0_BANK_REGNUM && nr <= DSP_R7_BANK_REGNUM)
2426 return nr - DSP_R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM;
2f14585c
JR		 2427 return nr;
2428}
1c0159e0 2429
da962468 2430static int
e7faf938 2431sh_sh2a_register_sim_regno (struct gdbarch *gdbarch, int nr)
da962468
CV		 2432{
2433 switch (nr)
2434 {
2435 case TBR_REGNUM:
2436 return SIM_SH_TBR_REGNUM;
2437 case IBNR_REGNUM:
2438 return SIM_SH_IBNR_REGNUM;
2439 case IBCR_REGNUM:
2440 return SIM_SH_IBCR_REGNUM;
2441 case BANK_REGNUM:
2442 return SIM_SH_BANK_REGNUM;
2443 case MACLB_REGNUM:
2444 return SIM_SH_BANK_MACL_REGNUM;
2445 case GBRB_REGNUM:
2446 return SIM_SH_BANK_GBR_REGNUM;
2447 case PRB_REGNUM:
2448 return SIM_SH_BANK_PR_REGNUM;
2449 case IVNB_REGNUM:
2450 return SIM_SH_BANK_IVN_REGNUM;
2451 case MACHB_REGNUM:
2452 return SIM_SH_BANK_MACH_REGNUM;
2453 default:
2454 break;
2455 }
e7faf938 2456 return legacy_register_sim_regno (gdbarch, nr);
da962468
CV		 2457}
2458
357d3800
AS		 2459/* Set up the register unwinding such that call-clobbered registers are
2460 not displayed in frames >0 because the true value is not certain.
2461 The 'undefined' registers will show up as 'not available' unless the
2462 CFI says otherwise.
2463
2464 This function is currently set up for SH4 and compatible only. */
2465
2466static void
2467sh_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
aff37fc1 2468 struct dwarf2_frame_state_reg *reg,
4a4e5149 2469 struct frame_info *this_frame)
357d3800
AS		 2470{
2471 /* Mark the PC as the destination for the return address. */
b47193f7 2472 if (regnum == gdbarch_pc_regnum (gdbarch))
357d3800
AS		 2473 reg->how = DWARF2_FRAME_REG_RA;
2474
2475 /* Mark the stack pointer as the call frame address. */
b47193f7 2476 else if (regnum == gdbarch_sp_regnum (gdbarch))
357d3800
AS		 2477 reg->how = DWARF2_FRAME_REG_CFA;
2478
2479 /* The above was taken from the default init_reg in dwarf2-frame.c
2480 while the below is SH specific. */
2481
2482 /* Caller save registers. */
2483 else if ((regnum >= R0_REGNUM && regnum <= R0_REGNUM+7)
2484 || (regnum >= FR0_REGNUM && regnum <= FR0_REGNUM+11)
2485 || (regnum >= DR0_REGNUM && regnum <= DR0_REGNUM+5)
2486 || (regnum >= FV0_REGNUM && regnum <= FV0_REGNUM+2)
2487 || (regnum == MACH_REGNUM)
2488 || (regnum == MACL_REGNUM)
2489 || (regnum == FPUL_REGNUM)
2490 || (regnum == SR_REGNUM))
2491 reg->how = DWARF2_FRAME_REG_UNDEFINED;
2492
2493 /* Callee save registers. */
2494 else if ((regnum >= R0_REGNUM+8 && regnum <= R0_REGNUM+15)
2495 || (regnum >= FR0_REGNUM+12 && regnum <= FR0_REGNUM+15)
2496 || (regnum >= DR0_REGNUM+6 && regnum <= DR0_REGNUM+8)
2497 || (regnum == FV0_REGNUM+3))
2498 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
2499
2500 /* Other registers. These are not in the ABI and may or may not
2501 mean anything in frames >0 so don't show them. */
2502 else if ((regnum >= R0_BANK0_REGNUM && regnum <= R0_BANK0_REGNUM+15)
2503 || (regnum == GBR_REGNUM)
2504 || (regnum == VBR_REGNUM)
2505 || (regnum == FPSCR_REGNUM)
2506 || (regnum == SSR_REGNUM)
2507 || (regnum == SPC_REGNUM))
2508 reg->how = DWARF2_FRAME_REG_UNDEFINED;
2509}
2510
1c0159e0
CV		 2511static struct sh_frame_cache *
2512sh_alloc_frame_cache (void)
2513{
2514 struct sh_frame_cache *cache;
2515 int i;
2516
2517 cache = FRAME_OBSTACK_ZALLOC (struct sh_frame_cache);
2518
2519 /* Base address. */
2520 cache->base = 0;
2521 cache->saved_sp = 0;
2522 cache->sp_offset = 0;
2523 cache->pc = 0;
2524
2525 /* Frameless until proven otherwise. */
2526 cache->uses_fp = 0;
617daa0e 2527
1c0159e0
CV		 2528 /* Saved registers. We initialize these to -1 since zero is a valid
2529 offset (that's where fp is supposed to be stored). */
2530 for (i = 0; i < SH_NUM_REGS; i++)
2531 {
2532 cache->saved_regs[i] = -1;
2533 }
617daa0e 2534
1c0159e0 2535 return cache;
617daa0e 2536}
1c0159e0
CV		 2537
2538static struct sh_frame_cache *
94afd7a6 2539sh_frame_cache (struct frame_info *this_frame, void **this_cache)
1c0159e0 2540{
e17a4113 2541 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1c0159e0
CV		 2542 struct sh_frame_cache *cache;
2543 CORE_ADDR current_pc;
2544 int i;
2545
2546 if (*this_cache)
2547 return *this_cache;
2548
2549 cache = sh_alloc_frame_cache ();
2550 *this_cache = cache;
2551
2552 /* In principle, for normal frames, fp holds the frame pointer,
2553 which holds the base address for the current stack frame.
2554 However, for functions that don't need it, the frame pointer is
2555 optional. For these "frameless" functions the frame pointer is
c378eb4e 2556 actually the frame pointer of the calling frame. */
94afd7a6 2557 cache->base = get_frame_register_unsigned (this_frame, FP_REGNUM);
1c0159e0
CV		 2558 if (cache->base == 0)
2559 return cache;
2560
94afd7a6
UW		 2561 cache->pc = get_frame_func (this_frame);
2562 current_pc = get_frame_pc (this_frame);
1c0159e0 2563 if (cache->pc != 0)
d2ca4222
UW		 2564 {
2565 ULONGEST fpscr;
94afd7a6 2566 fpscr = get_frame_register_unsigned (this_frame, FPSCR_REGNUM);
e17a4113 2567 sh_analyze_prologue (gdbarch, cache->pc, current_pc, cache, fpscr);
d2ca4222 2568 }
617daa0e 2569
1c0159e0
CV		 2570 if (!cache->uses_fp)
2571 {
2572 /* We didn't find a valid frame, which means that CACHE->base
2573 currently holds the frame pointer for our calling frame. If
2574 we're at the start of a function, or somewhere half-way its
2575 prologue, the function's frame probably hasn't been fully
2576 setup yet. Try to reconstruct the base address for the stack
2577 frame by looking at the stack pointer. For truly "frameless"
2578 functions this might work too. */
94afd7a6 2579 cache->base = get_frame_register_unsigned
e17a4113 2580 (this_frame, gdbarch_sp_regnum (gdbarch));
1c0159e0
CV		 2581 }
2582
2583 /* Now that we have the base address for the stack frame we can
2584 calculate the value of sp in the calling frame. */
2585 cache->saved_sp = cache->base + cache->sp_offset;
2586
2587 /* Adjust all the saved registers such that they contain addresses
2588 instead of offsets. */
2589 for (i = 0; i < SH_NUM_REGS; i++)
2590 if (cache->saved_regs[i] != -1)
2591 cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i] - 4;
2592
2593 return cache;
2594}
2595
94afd7a6
UW		 2596static struct value *
2597sh_frame_prev_register (struct frame_info *this_frame,
2598 void **this_cache, int regnum)
1c0159e0 2599{
94afd7a6
UW		 2600 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2601 struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache);
1c0159e0
CV		 2602
2603 gdb_assert (regnum >= 0);
2604
b47193f7 2605 if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp)
94afd7a6 2606 return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp);
1c0159e0
CV		 2607
2608 /* The PC of the previous frame is stored in the PR register of
2609 the current frame. Frob regnum so that we pull the value from
2610 the correct place. */
b47193f7 2611 if (regnum == gdbarch_pc_regnum (gdbarch))
1c0159e0
CV		 2612 regnum = PR_REGNUM;
2613
2614 if (regnum < SH_NUM_REGS && cache->saved_regs[regnum] != -1)
94afd7a6
UW		 2615 return frame_unwind_got_memory (this_frame, regnum,
2616 cache->saved_regs[regnum]);
1c0159e0 2617
94afd7a6 2618 return frame_unwind_got_register (this_frame, regnum, regnum);
1c0159e0
CV		 2619}
2620
2621static void
94afd7a6 2622sh_frame_this_id (struct frame_info *this_frame, void **this_cache,
617daa0e
CV		 2623 struct frame_id *this_id)
2624{
94afd7a6 2625 struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache);
1c0159e0
CV		 2626
2627 /* This marks the outermost frame. */
2628 if (cache->base == 0)
2629 return;
2630
2631 *this_id = frame_id_build (cache->saved_sp, cache->pc);
617daa0e 2632}
1c0159e0 2633
617daa0e 2634static const struct frame_unwind sh_frame_unwind = {
1c0159e0 2635 NORMAL_FRAME,
8fbca658 2636 default_frame_unwind_stop_reason,
1c0159e0 2637 sh_frame_this_id,
94afd7a6
UW		 2638 sh_frame_prev_register,
2639 NULL,
2640 default_frame_sniffer
1c0159e0
CV		 2641};
2642
1c0159e0
CV		 2643static CORE_ADDR
2644sh_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
2645{
3e8c568d 2646 return frame_unwind_register_unsigned (next_frame,
b47193f7 2647 gdbarch_sp_regnum (gdbarch));
1c0159e0
CV		 2648}
2649
2650static CORE_ADDR
2651sh_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2652{
3e8c568d 2653 return frame_unwind_register_unsigned (next_frame,
b47193f7 2654 gdbarch_pc_regnum (gdbarch));
1c0159e0
CV		 2655}
2656
2657static struct frame_id
94afd7a6 2658sh_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1c0159e0 2659{
94afd7a6
UW		 2660 CORE_ADDR sp = get_frame_register_unsigned (this_frame,
2661 gdbarch_sp_regnum (gdbarch));
2662 return frame_id_build (sp, get_frame_pc (this_frame));
1c0159e0
CV		 2663}
2664
2665static CORE_ADDR
94afd7a6 2666sh_frame_base_address (struct frame_info *this_frame, void **this_cache)
617daa0e 2667{
94afd7a6 2668 struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache);
617daa0e 2669
1c0159e0
CV		 2670 return cache->base;
2671}
617daa0e
CV		 2672
2673static const struct frame_base sh_frame_base = {
1c0159e0
CV		 2674 &sh_frame_unwind,
2675 sh_frame_base_address,
2676 sh_frame_base_address,
2677 sh_frame_base_address
617daa0e 2678};
1c0159e0
CV		 2679
2680/* The epilogue is defined here as the area at the end of a function,
2681 either on the `ret' instruction itself or after an instruction which
c378eb4e 2682 destroys the function's stack frame. */
1c0159e0
CV		 2683static int
2684sh_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
2685{
e17a4113 2686 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1c0159e0
CV		 2687 CORE_ADDR func_addr = 0, func_end = 0;
2688
2689 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
2690 {
2691 ULONGEST inst;
2692 /* The sh epilogue is max. 14 bytes long. Give another 14 bytes
2693 for a nop and some fixed data (e.g. big offsets) which are
617daa0e 2694 unfortunately also treated as part of the function (which
c378eb4e 2695 means, they are below func_end. */
1c0159e0
CV		 2696 CORE_ADDR addr = func_end - 28;
2697 if (addr < func_addr + 4)
617daa0e 2698 addr = func_addr + 4;
1c0159e0
CV		 2699 if (pc < addr)
2700 return 0;
2701
c378eb4e 2702 /* First search forward until hitting an rts. */
1c0159e0 2703 while (addr < func_end
e17a4113 2704 && !IS_RTS (read_memory_unsigned_integer (addr, 2, byte_order)))
1c0159e0
CV		 2705 addr += 2;
2706 if (addr >= func_end)
617daa0e 2707 return 0;
1c0159e0
CV		 2708
2709 /* At this point we should find a mov.l @r15+,r14 instruction,
2710 either before or after the rts. If not, then the function has
c378eb4e 2711 probably no "normal" epilogue and we bail out here. */
e17a4113
UW		 2712 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
2713 if (IS_RESTORE_FP (read_memory_unsigned_integer (addr - 2, 2,
2714 byte_order)))
617daa0e 2715 addr -= 2;
e17a4113
UW		 2716 else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr + 2, 2,
2717 byte_order)))
1c0159e0
CV		 2718 return 0;
2719
e17a4113 2720 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
03131d99 2721
c378eb4e 2722 /* Step over possible lds.l @r15+,macl. */
03131d99
CV		 2723 if (IS_MACL_LDS (inst))
2724 {
2725 addr -= 2;
e17a4113 2726 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
03131d99
CV		 2727 }
2728
c378eb4e 2729 /* Step over possible lds.l @r15+,pr. */
1c0159e0 2730 if (IS_LDS (inst))
617daa0e 2731 {
1c0159e0 2732 addr -= 2;
e17a4113 2733 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
1c0159e0
CV		 2734 }
2735
c378eb4e 2736 /* Step over possible mov r14,r15. */
1c0159e0 2737 if (IS_MOV_FP_SP (inst))
617daa0e 2738 {
1c0159e0 2739 addr -= 2;
e17a4113 2740 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
1c0159e0
CV		 2741 }
2742
2743 /* Now check for FP adjustments, using add #imm,r14 or add rX, r14
c378eb4e 2744 instructions. */
1c0159e0 2745 while (addr > func_addr + 4
617daa0e 2746 && (IS_ADD_REG_TO_FP (inst) || IS_ADD_IMM_FP (inst)))
1c0159e0
CV		 2747 {
2748 addr -= 2;
e17a4113 2749 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
1c0159e0
CV		 2750 }
2751
03131d99
CV		 2752 /* On SH2a check if the previous instruction was perhaps a MOVI20.
2753 That's allowed for the epilogue. */
2754 if ((gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a
2755 || gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a_nofpu)
2756 && addr > func_addr + 6
e17a4113
UW		 2757 && IS_MOVI20 (read_memory_unsigned_integer (addr - 4, 2,
2758 byte_order)))
03131d99
CV		 2759 addr -= 4;
2760
1c0159e0
CV		 2761 if (pc >= addr)
2762 return 1;
2763 }
2764 return 0;
2765}
c9ac0a72
AS		 2766
2767
2768/* Supply register REGNUM from the buffer specified by REGS and LEN
2769 in the register set REGSET to register cache REGCACHE.
2770 REGTABLE specifies where each register can be found in REGS.
2771 If REGNUM is -1, do this for all registers in REGSET. */
2772
2773void
2774sh_corefile_supply_regset (const struct regset *regset,
2775 struct regcache *regcache,
2776 int regnum, const void *regs, size_t len)
2777{
2778 struct gdbarch *gdbarch = get_regcache_arch (regcache);
2779 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2780 const struct sh_corefile_regmap *regmap = (regset == &sh_corefile_gregset
2781 ? tdep->core_gregmap
2782 : tdep->core_fpregmap);
2783 int i;
2784
2785 for (i = 0; regmap[i].regnum != -1; i++)
2786 {
2787 if ((regnum == -1 || regnum == regmap[i].regnum)
2788 && regmap[i].offset + 4 <= len)
2789 regcache_raw_supply (regcache, regmap[i].regnum,
2790 (char *)regs + regmap[i].offset);
2791 }
2792}
2793
2794/* Collect register REGNUM in the register set REGSET from register cache
2795 REGCACHE into the buffer specified by REGS and LEN.
2796 REGTABLE specifies where each register can be found in REGS.
2797 If REGNUM is -1, do this for all registers in REGSET. */
2798
2799void
2800sh_corefile_collect_regset (const struct regset *regset,
2801 const struct regcache *regcache,
2802 int regnum, void *regs, size_t len)
2803{
2804 struct gdbarch *gdbarch = get_regcache_arch (regcache);
2805 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2806 const struct sh_corefile_regmap *regmap = (regset == &sh_corefile_gregset
2807 ? tdep->core_gregmap
2808 : tdep->core_fpregmap);
2809 int i;
2810
2811 for (i = 0; regmap[i].regnum != -1; i++)
2812 {
2813 if ((regnum == -1 || regnum == regmap[i].regnum)
2814 && regmap[i].offset + 4 <= len)
2815 regcache_raw_collect (regcache, regmap[i].regnum,
2816 (char *)regs + regmap[i].offset);
2817 }
2818}
2819
2820/* The following two regsets have the same contents, so it is tempting to
2821 unify them, but they are distiguished by their address, so don't. */
2822
2823struct regset sh_corefile_gregset =
2824{
2825 NULL,
2826 sh_corefile_supply_regset,
2827 sh_corefile_collect_regset
2828};
2829
2830static struct regset sh_corefile_fpregset =
2831{
2832 NULL,
2833 sh_corefile_supply_regset,
2834 sh_corefile_collect_regset
2835};
2836
2837static const struct regset *
2838sh_regset_from_core_section (struct gdbarch *gdbarch, const char *sect_name,
2839 size_t sect_size)
2840{
2841 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2842
2843 if (tdep->core_gregmap && strcmp (sect_name, ".reg") == 0)
2844 return &sh_corefile_gregset;
2845
2846 if (tdep->core_fpregmap && strcmp (sect_name, ".reg2") == 0)
2847 return &sh_corefile_fpregset;
2848
2849 return NULL;
2850}
ccf00f21 2851\f
cc17453a
EZ		 2852
2853static struct gdbarch *
fba45db2 2854sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
cc17453a 2855{
cc17453a 2856 struct gdbarch *gdbarch;
c9ac0a72 2857 struct gdbarch_tdep *tdep;
d658f924 2858
55ff77ac
CV		 2859 sh_show_regs = sh_generic_show_regs;
2860 switch (info.bfd_arch_info->mach)
2861 {
617daa0e
CV		 2862 case bfd_mach_sh2e:
2863 sh_show_regs = sh2e_show_regs;
2864 break;
da962468
CV		 2865 case bfd_mach_sh2a:
2866 sh_show_regs = sh2a_show_regs;
2867 break;
2868 case bfd_mach_sh2a_nofpu:
2869 sh_show_regs = sh2a_nofpu_show_regs;
2870 break;
617daa0e
CV		 2871 case bfd_mach_sh_dsp:
2872 sh_show_regs = sh_dsp_show_regs;
2873 break;
55ff77ac 2874
617daa0e 2875 case bfd_mach_sh3:
46e8a76b
AS		 2876 case bfd_mach_sh3_nommu:
2877 case bfd_mach_sh2a_nofpu_or_sh3_nommu:
617daa0e
CV		 2878 sh_show_regs = sh3_show_regs;
2879 break;
55ff77ac 2880
617daa0e 2881 case bfd_mach_sh3e:
46e8a76b 2882 case bfd_mach_sh2a_or_sh3e:
617daa0e
CV		 2883 sh_show_regs = sh3e_show_regs;
2884 break;
55ff77ac 2885
617daa0e 2886 case bfd_mach_sh3_dsp:
474e5826 2887 case bfd_mach_sh4al_dsp:
617daa0e
CV		 2888 sh_show_regs = sh3_dsp_show_regs;
2889 break;
55ff77ac 2890
617daa0e 2891 case bfd_mach_sh4:
474e5826 2892 case bfd_mach_sh4a:
46e8a76b 2893 case bfd_mach_sh2a_or_sh4:
617daa0e
CV		 2894 sh_show_regs = sh4_show_regs;
2895 break;
55ff77ac 2896
474e5826 2897 case bfd_mach_sh4_nofpu:
46e8a76b 2898 case bfd_mach_sh4_nommu_nofpu:
474e5826 2899 case bfd_mach_sh4a_nofpu:
46e8a76b 2900 case bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu:
474e5826
CV		 2901 sh_show_regs = sh4_nofpu_show_regs;
2902 break;
2903
617daa0e
CV		 2904 case bfd_mach_sh5:
2905 sh_show_regs = sh64_show_regs;
c378eb4e 2906 /* SH5 is handled entirely in sh64-tdep.c. */
617daa0e 2907 return sh64_gdbarch_init (info, arches);
55ff77ac
CV		 2908 }
2909
4be87837
DJ		 2910 /* If there is already a candidate, use it. */
2911 arches = gdbarch_list_lookup_by_info (arches, &info);
2912 if (arches != NULL)
2913 return arches->gdbarch;
cc17453a
EZ		 2914
2915 /* None found, create a new architecture from the information
c378eb4e 2916 provided. */
c9ac0a72
AS		 2917 tdep = XZALLOC (struct gdbarch_tdep);
2918 gdbarch = gdbarch_alloc (&info, tdep);
cc17453a 2919
48db5a3c
CV		 2920 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2921 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
ec920329 2922 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
48db5a3c
CV		 2923 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2924 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2925 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2926 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
a38d2a54 2927 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
48db5a3c 2928
f2ea0907 2929 set_gdbarch_num_regs (gdbarch, SH_NUM_REGS);
a38d2a54 2930 set_gdbarch_sp_regnum (gdbarch, 15);
a38d2a54 2931 set_gdbarch_pc_regnum (gdbarch, 16);
48db5a3c
CV		 2932 set_gdbarch_fp0_regnum (gdbarch, -1);
2933 set_gdbarch_num_pseudo_regs (gdbarch, 0);
2934
1c0159e0 2935 set_gdbarch_register_type (gdbarch, sh_default_register_type);
dda63807 2936 set_gdbarch_register_reggroup_p (gdbarch, sh_register_reggroup_p);
1c0159e0 2937
eaf90c5d 2938 set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc);
48db5a3c 2939
9dae60cc 2940 set_gdbarch_print_insn (gdbarch, print_insn_sh);
2f14585c 2941 set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);
48db5a3c 2942
c0409442 2943 set_gdbarch_return_value (gdbarch, sh_return_value_nofpu);
1c0159e0 2944
48db5a3c
CV		 2945 set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
2946 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
48db5a3c 2947
1c0159e0
CV		 2948 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu);
2949
48db5a3c
CV		 2950 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2951
19f59343 2952 set_gdbarch_frame_align (gdbarch, sh_frame_align);
1c0159e0
CV		 2953 set_gdbarch_unwind_sp (gdbarch, sh_unwind_sp);
2954 set_gdbarch_unwind_pc (gdbarch, sh_unwind_pc);
94afd7a6 2955 set_gdbarch_dummy_id (gdbarch, sh_dummy_id);
1c0159e0
CV		 2956 frame_base_set_default (gdbarch, &sh_frame_base);
2957
617daa0e 2958 set_gdbarch_in_function_epilogue_p (gdbarch, sh_in_function_epilogue_p);
cc17453a 2959
357d3800
AS		 2960 dwarf2_frame_set_init_reg (gdbarch, sh_dwarf2_frame_init_reg);
2961
c9ac0a72
AS		 2962 set_gdbarch_regset_from_core_section (gdbarch, sh_regset_from_core_section);
2963
cc17453a 2964 switch (info.bfd_arch_info->mach)
8db62801 2965 {
cc17453a 2966 case bfd_mach_sh:
48db5a3c 2967 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
cc17453a 2968 break;
1c0159e0 2969
cc17453a 2970 case bfd_mach_sh2:
48db5a3c 2971 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
617daa0e 2972 break;
1c0159e0 2973
2d188dd3 2974 case bfd_mach_sh2e:
c378eb4e 2975 /* doubles on sh2e and sh3e are actually 4 byte. */
48db5a3c
CV		 2976 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2977
2978 set_gdbarch_register_name (gdbarch, sh_sh2e_register_name);
48db5a3c 2979 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
2d188dd3 2980 set_gdbarch_fp0_regnum (gdbarch, 25);
c0409442 2981 set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
6df2bf50 2982 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2d188dd3 2983 break;
1c0159e0 2984
da962468
CV		 2985 case bfd_mach_sh2a:
2986 set_gdbarch_register_name (gdbarch, sh_sh2a_register_name);
2987 set_gdbarch_register_type (gdbarch, sh_sh2a_register_type);
2988 set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno);
2989
2990 set_gdbarch_fp0_regnum (gdbarch, 25);
2991 set_gdbarch_num_pseudo_regs (gdbarch, 9);
2992 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
2993 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
c0409442 2994 set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
da962468
CV		 2995 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2996 break;
2997
2998 case bfd_mach_sh2a_nofpu:
2999 set_gdbarch_register_name (gdbarch, sh_sh2a_nofpu_register_name);
3000 set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno);
3001
3002 set_gdbarch_num_pseudo_regs (gdbarch, 1);
3003 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
3004 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
3005 break;
3006
cc17453a 3007 case bfd_mach_sh_dsp:
48db5a3c 3008 set_gdbarch_register_name (gdbarch, sh_sh_dsp_register_name);
2f14585c 3009 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
cc17453a 3010 break;
1c0159e0 3011
cc17453a 3012 case bfd_mach_sh3:
4e6cbc38
AS		 3013 case bfd_mach_sh3_nommu:
3014 case bfd_mach_sh2a_nofpu_or_sh3_nommu:
48db5a3c 3015 set_gdbarch_register_name (gdbarch, sh_sh3_register_name);
cc17453a 3016 break;
1c0159e0 3017
cc17453a 3018 case bfd_mach_sh3e:
4e6cbc38 3019 case bfd_mach_sh2a_or_sh3e:
c378eb4e 3020 /* doubles on sh2e and sh3e are actually 4 byte. */
48db5a3c
CV		 3021 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
3022
3023 set_gdbarch_register_name (gdbarch, sh_sh3e_register_name);
48db5a3c 3024 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
cc17453a 3025 set_gdbarch_fp0_regnum (gdbarch, 25);
c0409442 3026 set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
6df2bf50 3027 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
cc17453a 3028 break;
1c0159e0 3029
cc17453a 3030 case bfd_mach_sh3_dsp:
48db5a3c 3031 set_gdbarch_register_name (gdbarch, sh_sh3_dsp_register_name);
48db5a3c 3032 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
cc17453a 3033 break;
1c0159e0 3034
cc17453a 3035 case bfd_mach_sh4:
474e5826 3036 case bfd_mach_sh4a:
46e8a76b 3037 case bfd_mach_sh2a_or_sh4:
48db5a3c 3038 set_gdbarch_register_name (gdbarch, sh_sh4_register_name);
48db5a3c 3039 set_gdbarch_register_type (gdbarch, sh_sh4_register_type);
cc17453a 3040 set_gdbarch_fp0_regnum (gdbarch, 25);
da962468 3041 set_gdbarch_num_pseudo_regs (gdbarch, 13);
d8124050
AC		 3042 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
3043 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
c0409442 3044 set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
6df2bf50 3045 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
cc17453a 3046 break;
1c0159e0 3047
474e5826
CV		 3048 case bfd_mach_sh4_nofpu:
3049 case bfd_mach_sh4a_nofpu:
4e6cbc38
AS		 3050 case bfd_mach_sh4_nommu_nofpu:
3051 case bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu:
474e5826
CV		 3052 set_gdbarch_register_name (gdbarch, sh_sh4_nofpu_register_name);
3053 break;
3054
3055 case bfd_mach_sh4al_dsp:
3056 set_gdbarch_register_name (gdbarch, sh_sh4al_dsp_register_name);
3057 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
3058 break;
3059
cc17453a 3060 default:
b58cbbf2 3061 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
cc17453a 3062 break;
8db62801 3063 }
cc17453a 3064
4be87837
DJ		 3065 /* Hook in ABI-specific overrides, if they have been registered. */
3066 gdbarch_init_osabi (info, gdbarch);
d658f924 3067
94afd7a6
UW		 3068 dwarf2_append_unwinders (gdbarch);
3069 frame_unwind_append_unwinder (gdbarch, &sh_frame_unwind);
1c0159e0 3070
cc17453a 3071 return gdbarch;
8db62801
EZ		 3072}
3073
c055b101
CV		 3074static void
3075show_sh_command (char *args, int from_tty)
3076{
3077 help_list (showshcmdlist, "show sh ", all_commands, gdb_stdout);
3078}
3079
3080static void
3081set_sh_command (char *args, int from_tty)
3082{
3083 printf_unfiltered
3084 ("\"set sh\" must be followed by an appropriate subcommand.\n");
3085 help_list (setshcmdlist, "set sh ", all_commands, gdb_stdout);
3086}
3087
c378eb4e 3088extern initialize_file_ftype _initialize_sh_tdep; /* -Wmissing-prototypes */
a78f21af 3089
c906108c 3090void
fba45db2 3091_initialize_sh_tdep (void)
c906108c
SS		 3092{
3093 struct cmd_list_element *c;
617daa0e 3094
f2ea0907 3095 gdbarch_register (bfd_arch_sh, sh_gdbarch_init, NULL);
c906108c 3096
1bedd215 3097 add_com ("regs", class_vars, sh_show_regs_command, _("Print all registers"));
c055b101
CV		 3098
3099 add_prefix_cmd ("sh", no_class, set_sh_command, "SH specific commands.",
3100 &setshcmdlist, "set sh ", 0, &setlist);
3101 add_prefix_cmd ("sh", no_class, show_sh_command, "SH specific commands.",
3102 &showshcmdlist, "show sh ", 0, &showlist);
3103
3104 add_setshow_enum_cmd ("calling-convention", class_vars, sh_cc_enum,
3105 &sh_active_calling_convention,
3106 _("Set calling convention used when calling target "
3107 "functions from GDB."),
3108 _("Show calling convention used when calling target "
3109 "functions from GDB."),
3110 _("gcc - Use GCC calling convention (default).\n"
3111 "renesas - Enforce Renesas calling convention."),
3112 NULL, NULL,
3113 &setshcmdlist, &showshcmdlist);
c906108c 3114}
GDB Binutils - Deliverables
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