Commit | Line | Data |
---|---|---|
85a453d5 | 1 | /* Target-dependent code for Renesas Super-H, for GDB. |
0fd88904 | 2 | |
ecd75fc8 | 3 | Copyright (C) 1993-2014 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 10 | (at your option) any later version. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b | 17 | You should have received a copy of the GNU General Public License |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c | 19 | |
c378eb4e MS |
20 | /* Contributed by Steve Chamberlain |
21 | sac@cygnus.com. */ | |
c906108c SS |
22 | |
23 | #include "defs.h" | |
24 | #include "frame.h" | |
1c0159e0 CV |
25 | #include "frame-base.h" |
26 | #include "frame-unwind.h" | |
27 | #include "dwarf2-frame.h" | |
c906108c | 28 | #include "symtab.h" |
c906108c SS |
29 | #include "gdbtypes.h" |
30 | #include "gdbcmd.h" | |
31 | #include "gdbcore.h" | |
32 | #include "value.h" | |
33 | #include "dis-asm.h" | |
73c1f219 | 34 | #include "inferior.h" |
0e9f083f | 35 | #include <string.h> |
1c0159e0 | 36 | #include "gdb_assert.h" |
b4a20239 | 37 | #include "arch-utils.h" |
fb409745 | 38 | #include "floatformat.h" |
4e052eda | 39 | #include "regcache.h" |
d16aafd8 | 40 | #include "doublest.h" |
4be87837 | 41 | #include "osabi.h" |
dda63807 | 42 | #include "reggroups.h" |
c9ac0a72 | 43 | #include "regset.h" |
cb2cf4ce | 44 | #include "objfiles.h" |
c906108c | 45 | |
ab3b8126 | 46 | #include "sh-tdep.h" |
04dcf5fa | 47 | #include "sh64-tdep.h" |
ab3b8126 | 48 | |
d658f924 | 49 | #include "elf-bfd.h" |
1a8629c7 MS |
50 | #include "solib-svr4.h" |
51 | ||
55ff77ac | 52 | /* sh flags */ |
283150cd | 53 | #include "elf/sh.h" |
fa8f86ff | 54 | #include "dwarf2.h" |
c378eb4e | 55 | /* registers numbers shared with the simulator. */ |
1c922164 | 56 | #include "gdb/sim-sh.h" |
283150cd | 57 | |
c055b101 CV |
58 | /* List of "set sh ..." and "show sh ..." commands. */ |
59 | static struct cmd_list_element *setshcmdlist = NULL; | |
60 | static struct cmd_list_element *showshcmdlist = NULL; | |
61 | ||
62 | static const char sh_cc_gcc[] = "gcc"; | |
63 | static const char sh_cc_renesas[] = "renesas"; | |
40478521 | 64 | static const char *const sh_cc_enum[] = { |
c055b101 CV |
65 | sh_cc_gcc, |
66 | sh_cc_renesas, | |
67 | NULL | |
68 | }; | |
69 | ||
70 | static const char *sh_active_calling_convention = sh_cc_gcc; | |
71 | ||
da962468 | 72 | #define SH_NUM_REGS 67 |
88e04cc1 | 73 | |
1c0159e0 | 74 | struct sh_frame_cache |
cc17453a | 75 | { |
1c0159e0 CV |
76 | /* Base address. */ |
77 | CORE_ADDR base; | |
78 | LONGEST sp_offset; | |
79 | CORE_ADDR pc; | |
80 | ||
c378eb4e | 81 | /* Flag showing that a frame has been created in the prologue code. */ |
1c0159e0 CV |
82 | int uses_fp; |
83 | ||
84 | /* Saved registers. */ | |
85 | CORE_ADDR saved_regs[SH_NUM_REGS]; | |
86 | CORE_ADDR saved_sp; | |
63978407 | 87 | }; |
c906108c | 88 | |
c055b101 CV |
89 | static int |
90 | sh_is_renesas_calling_convention (struct type *func_type) | |
91 | { | |
ca193e27 TS |
92 | int val = 0; |
93 | ||
94 | if (func_type) | |
95 | { | |
96 | func_type = check_typedef (func_type); | |
97 | ||
98 | if (TYPE_CODE (func_type) == TYPE_CODE_PTR) | |
99 | func_type = check_typedef (TYPE_TARGET_TYPE (func_type)); | |
100 | ||
101 | if (TYPE_CODE (func_type) == TYPE_CODE_FUNC | |
102 | && TYPE_CALLING_CONVENTION (func_type) == DW_CC_GNU_renesas_sh) | |
103 | val = 1; | |
104 | } | |
105 | ||
106 | if (sh_active_calling_convention == sh_cc_renesas) | |
107 | val = 1; | |
108 | ||
109 | return val; | |
c055b101 CV |
110 | } |
111 | ||
fa88f677 | 112 | static const char * |
d93859e2 | 113 | sh_sh_register_name (struct gdbarch *gdbarch, int reg_nr) |
cc17453a | 114 | { |
617daa0e CV |
115 | static char *register_names[] = { |
116 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
117 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
118 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
119 | "", "", | |
120 | "", "", "", "", "", "", "", "", | |
121 | "", "", "", "", "", "", "", "", | |
122 | "", "", | |
123 | "", "", "", "", "", "", "", "", | |
124 | "", "", "", "", "", "", "", "", | |
da962468 | 125 | "", "", "", "", "", "", "", "", |
cc17453a EZ |
126 | }; |
127 | if (reg_nr < 0) | |
128 | return NULL; | |
129 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
130 | return NULL; | |
131 | return register_names[reg_nr]; | |
132 | } | |
133 | ||
fa88f677 | 134 | static const char * |
d93859e2 | 135 | sh_sh3_register_name (struct gdbarch *gdbarch, int reg_nr) |
cc17453a | 136 | { |
617daa0e CV |
137 | static char *register_names[] = { |
138 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
139 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
140 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
141 | "", "", | |
142 | "", "", "", "", "", "", "", "", | |
143 | "", "", "", "", "", "", "", "", | |
144 | "ssr", "spc", | |
cc17453a EZ |
145 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", |
146 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1" | |
da962468 | 147 | "", "", "", "", "", "", "", "", |
cc17453a EZ |
148 | }; |
149 | if (reg_nr < 0) | |
150 | return NULL; | |
151 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
152 | return NULL; | |
153 | return register_names[reg_nr]; | |
154 | } | |
155 | ||
fa88f677 | 156 | static const char * |
d93859e2 | 157 | sh_sh3e_register_name (struct gdbarch *gdbarch, int reg_nr) |
cc17453a | 158 | { |
617daa0e CV |
159 | static char *register_names[] = { |
160 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
161 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
162 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
cc17453a | 163 | "fpul", "fpscr", |
617daa0e CV |
164 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", |
165 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
166 | "ssr", "spc", | |
cc17453a EZ |
167 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", |
168 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", | |
da962468 | 169 | "", "", "", "", "", "", "", "", |
cc17453a EZ |
170 | }; |
171 | if (reg_nr < 0) | |
172 | return NULL; | |
173 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
174 | return NULL; | |
175 | return register_names[reg_nr]; | |
176 | } | |
177 | ||
2d188dd3 | 178 | static const char * |
d93859e2 | 179 | sh_sh2e_register_name (struct gdbarch *gdbarch, int reg_nr) |
2d188dd3 | 180 | { |
617daa0e CV |
181 | static char *register_names[] = { |
182 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
183 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
184 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
2d188dd3 | 185 | "fpul", "fpscr", |
617daa0e CV |
186 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", |
187 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
188 | "", "", | |
2d188dd3 NC |
189 | "", "", "", "", "", "", "", "", |
190 | "", "", "", "", "", "", "", "", | |
da962468 CV |
191 | "", "", "", "", "", "", "", "", |
192 | }; | |
193 | if (reg_nr < 0) | |
194 | return NULL; | |
195 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
196 | return NULL; | |
197 | return register_names[reg_nr]; | |
198 | } | |
199 | ||
200 | static const char * | |
d93859e2 | 201 | sh_sh2a_register_name (struct gdbarch *gdbarch, int reg_nr) |
da962468 CV |
202 | { |
203 | static char *register_names[] = { | |
204 | /* general registers 0-15 */ | |
205 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
206 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
207 | /* 16 - 22 */ | |
208 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
209 | /* 23, 24 */ | |
210 | "fpul", "fpscr", | |
211 | /* floating point registers 25 - 40 */ | |
212 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", | |
213 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
214 | /* 41, 42 */ | |
215 | "", "", | |
216 | /* 43 - 62. Banked registers. The bank number used is determined by | |
c378eb4e | 217 | the bank register (63). */ |
da962468 CV |
218 | "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b", |
219 | "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", | |
220 | "machb", "ivnb", "prb", "gbrb", "maclb", | |
221 | /* 63: register bank number, not a real register but used to | |
222 | communicate the register bank currently get/set. This register | |
223 | is hidden to the user, who manipulates it using the pseudo | |
224 | register called "bank" (67). See below. */ | |
225 | "", | |
226 | /* 64 - 66 */ | |
227 | "ibcr", "ibnr", "tbr", | |
228 | /* 67: register bank number, the user visible pseudo register. */ | |
229 | "bank", | |
230 | /* double precision (pseudo) 68 - 75 */ | |
231 | "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", | |
232 | }; | |
233 | if (reg_nr < 0) | |
234 | return NULL; | |
235 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
236 | return NULL; | |
237 | return register_names[reg_nr]; | |
238 | } | |
239 | ||
240 | static const char * | |
d93859e2 | 241 | sh_sh2a_nofpu_register_name (struct gdbarch *gdbarch, int reg_nr) |
da962468 CV |
242 | { |
243 | static char *register_names[] = { | |
244 | /* general registers 0-15 */ | |
245 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
246 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
247 | /* 16 - 22 */ | |
248 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
249 | /* 23, 24 */ | |
250 | "", "", | |
251 | /* floating point registers 25 - 40 */ | |
252 | "", "", "", "", "", "", "", "", | |
253 | "", "", "", "", "", "", "", "", | |
254 | /* 41, 42 */ | |
255 | "", "", | |
256 | /* 43 - 62. Banked registers. The bank number used is determined by | |
c378eb4e | 257 | the bank register (63). */ |
da962468 CV |
258 | "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b", |
259 | "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", | |
260 | "machb", "ivnb", "prb", "gbrb", "maclb", | |
261 | /* 63: register bank number, not a real register but used to | |
262 | communicate the register bank currently get/set. This register | |
263 | is hidden to the user, who manipulates it using the pseudo | |
264 | register called "bank" (67). See below. */ | |
265 | "", | |
266 | /* 64 - 66 */ | |
267 | "ibcr", "ibnr", "tbr", | |
268 | /* 67: register bank number, the user visible pseudo register. */ | |
269 | "bank", | |
270 | /* double precision (pseudo) 68 - 75 */ | |
271 | "", "", "", "", "", "", "", "", | |
2d188dd3 NC |
272 | }; |
273 | if (reg_nr < 0) | |
274 | return NULL; | |
275 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
276 | return NULL; | |
277 | return register_names[reg_nr]; | |
278 | } | |
279 | ||
fa88f677 | 280 | static const char * |
d93859e2 | 281 | sh_sh_dsp_register_name (struct gdbarch *gdbarch, int reg_nr) |
cc17453a | 282 | { |
617daa0e CV |
283 | static char *register_names[] = { |
284 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
285 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
286 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
287 | "", "dsr", | |
288 | "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1", | |
289 | "y0", "y1", "", "", "", "", "", "mod", | |
290 | "", "", | |
291 | "rs", "re", "", "", "", "", "", "", | |
292 | "", "", "", "", "", "", "", "", | |
da962468 | 293 | "", "", "", "", "", "", "", "", |
cc17453a EZ |
294 | }; |
295 | if (reg_nr < 0) | |
296 | return NULL; | |
297 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
298 | return NULL; | |
299 | return register_names[reg_nr]; | |
300 | } | |
301 | ||
fa88f677 | 302 | static const char * |
d93859e2 | 303 | sh_sh3_dsp_register_name (struct gdbarch *gdbarch, int reg_nr) |
cc17453a | 304 | { |
617daa0e CV |
305 | static char *register_names[] = { |
306 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
307 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
308 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
309 | "", "dsr", | |
310 | "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1", | |
311 | "y0", "y1", "", "", "", "", "", "mod", | |
312 | "ssr", "spc", | |
313 | "rs", "re", "", "", "", "", "", "", | |
026a72f8 CV |
314 | "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b", |
315 | "", "", "", "", "", "", "", "", | |
da962468 | 316 | "", "", "", "", "", "", "", "", |
cc17453a EZ |
317 | }; |
318 | if (reg_nr < 0) | |
319 | return NULL; | |
320 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
321 | return NULL; | |
322 | return register_names[reg_nr]; | |
323 | } | |
324 | ||
fa88f677 | 325 | static const char * |
d93859e2 | 326 | sh_sh4_register_name (struct gdbarch *gdbarch, int reg_nr) |
53116e27 | 327 | { |
617daa0e | 328 | static char *register_names[] = { |
a38d2a54 | 329 | /* general registers 0-15 */ |
617daa0e CV |
330 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
331 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
a38d2a54 | 332 | /* 16 - 22 */ |
617daa0e | 333 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", |
a38d2a54 | 334 | /* 23, 24 */ |
53116e27 | 335 | "fpul", "fpscr", |
a38d2a54 | 336 | /* floating point registers 25 - 40 */ |
617daa0e CV |
337 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", |
338 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
a38d2a54 | 339 | /* 41, 42 */ |
617daa0e | 340 | "ssr", "spc", |
a38d2a54 | 341 | /* bank 0 43 - 50 */ |
53116e27 | 342 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", |
a38d2a54 | 343 | /* bank 1 51 - 58 */ |
53116e27 | 344 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", |
a6521d9a | 345 | /* 59 - 66 */ |
da962468 | 346 | "", "", "", "", "", "", "", "", |
c378eb4e | 347 | /* pseudo bank register. */ |
da962468 | 348 | "", |
a6521d9a | 349 | /* double precision (pseudo) 68 - 75 */ |
617daa0e | 350 | "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", |
a6521d9a | 351 | /* vectors (pseudo) 76 - 79 */ |
617daa0e | 352 | "fv0", "fv4", "fv8", "fv12", |
a6521d9a TS |
353 | /* FIXME: missing XF */ |
354 | /* FIXME: missing XD */ | |
53116e27 EZ |
355 | }; |
356 | if (reg_nr < 0) | |
357 | return NULL; | |
358 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
359 | return NULL; | |
360 | return register_names[reg_nr]; | |
361 | } | |
362 | ||
474e5826 | 363 | static const char * |
d93859e2 | 364 | sh_sh4_nofpu_register_name (struct gdbarch *gdbarch, int reg_nr) |
474e5826 CV |
365 | { |
366 | static char *register_names[] = { | |
367 | /* general registers 0-15 */ | |
368 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
369 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
370 | /* 16 - 22 */ | |
371 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
372 | /* 23, 24 */ | |
373 | "", "", | |
374 | /* floating point registers 25 - 40 -- not for nofpu target */ | |
375 | "", "", "", "", "", "", "", "", | |
376 | "", "", "", "", "", "", "", "", | |
377 | /* 41, 42 */ | |
378 | "ssr", "spc", | |
379 | /* bank 0 43 - 50 */ | |
380 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", | |
381 | /* bank 1 51 - 58 */ | |
382 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", | |
a6521d9a | 383 | /* 59 - 66 */ |
da962468 | 384 | "", "", "", "", "", "", "", "", |
c378eb4e | 385 | /* pseudo bank register. */ |
da962468 | 386 | "", |
a6521d9a | 387 | /* double precision (pseudo) 68 - 75 -- not for nofpu target */ |
474e5826 | 388 | "", "", "", "", "", "", "", "", |
a6521d9a | 389 | /* vectors (pseudo) 76 - 79 -- not for nofpu target */ |
474e5826 CV |
390 | "", "", "", "", |
391 | }; | |
392 | if (reg_nr < 0) | |
393 | return NULL; | |
394 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
395 | return NULL; | |
396 | return register_names[reg_nr]; | |
397 | } | |
398 | ||
399 | static const char * | |
d93859e2 | 400 | sh_sh4al_dsp_register_name (struct gdbarch *gdbarch, int reg_nr) |
474e5826 CV |
401 | { |
402 | static char *register_names[] = { | |
403 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
404 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
405 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
406 | "", "dsr", | |
407 | "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1", | |
408 | "y0", "y1", "", "", "", "", "", "mod", | |
409 | "ssr", "spc", | |
410 | "rs", "re", "", "", "", "", "", "", | |
026a72f8 CV |
411 | "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b", |
412 | "", "", "", "", "", "", "", "", | |
da962468 | 413 | "", "", "", "", "", "", "", "", |
474e5826 CV |
414 | }; |
415 | if (reg_nr < 0) | |
416 | return NULL; | |
417 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
418 | return NULL; | |
419 | return register_names[reg_nr]; | |
420 | } | |
421 | ||
3117ed25 | 422 | static const unsigned char * |
67d57894 | 423 | sh_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr) |
cc17453a | 424 | { |
c378eb4e | 425 | /* 0xc3c3 is trapa #c3, and it works in big and little endian modes. */ |
617daa0e CV |
426 | static unsigned char breakpoint[] = { 0xc3, 0xc3 }; |
427 | ||
bac718a6 UW |
428 | /* For remote stub targets, trapa #20 is used. */ |
429 | if (strcmp (target_shortname, "remote") == 0) | |
430 | { | |
431 | static unsigned char big_remote_breakpoint[] = { 0xc3, 0x20 }; | |
432 | static unsigned char little_remote_breakpoint[] = { 0x20, 0xc3 }; | |
433 | ||
67d57894 | 434 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
bac718a6 UW |
435 | { |
436 | *lenptr = sizeof (big_remote_breakpoint); | |
437 | return big_remote_breakpoint; | |
438 | } | |
439 | else | |
440 | { | |
441 | *lenptr = sizeof (little_remote_breakpoint); | |
442 | return little_remote_breakpoint; | |
443 | } | |
444 | } | |
445 | ||
cc17453a EZ |
446 | *lenptr = sizeof (breakpoint); |
447 | return breakpoint; | |
448 | } | |
c906108c SS |
449 | |
450 | /* Prologue looks like | |
1c0159e0 CV |
451 | mov.l r14,@-r15 |
452 | sts.l pr,@-r15 | |
453 | mov.l <regs>,@-r15 | |
454 | sub <room_for_loca_vars>,r15 | |
455 | mov r15,r14 | |
8db62801 | 456 | |
c378eb4e | 457 | Actually it can be more complicated than this but that's it, basically. */ |
c906108c | 458 | |
1c0159e0 CV |
459 | #define GET_SOURCE_REG(x) (((x) >> 4) & 0xf) |
460 | #define GET_TARGET_REG(x) (((x) >> 8) & 0xf) | |
461 | ||
5f883edd FF |
462 | /* JSR @Rm 0100mmmm00001011 */ |
463 | #define IS_JSR(x) (((x) & 0xf0ff) == 0x400b) | |
464 | ||
8db62801 EZ |
465 | /* STS.L PR,@-r15 0100111100100010 |
466 | r15-4-->r15, PR-->(r15) */ | |
c906108c | 467 | #define IS_STS(x) ((x) == 0x4f22) |
8db62801 | 468 | |
03131d99 CV |
469 | /* STS.L MACL,@-r15 0100111100010010 |
470 | r15-4-->r15, MACL-->(r15) */ | |
471 | #define IS_MACL_STS(x) ((x) == 0x4f12) | |
472 | ||
8db62801 EZ |
473 | /* MOV.L Rm,@-r15 00101111mmmm0110 |
474 | r15-4-->r15, Rm-->(R15) */ | |
c906108c | 475 | #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06) |
8db62801 | 476 | |
8db62801 EZ |
477 | /* MOV r15,r14 0110111011110011 |
478 | r15-->r14 */ | |
c906108c | 479 | #define IS_MOV_SP_FP(x) ((x) == 0x6ef3) |
8db62801 EZ |
480 | |
481 | /* ADD #imm,r15 01111111iiiiiiii | |
482 | r15+imm-->r15 */ | |
1c0159e0 | 483 | #define IS_ADD_IMM_SP(x) (((x) & 0xff00) == 0x7f00) |
8db62801 | 484 | |
c906108c SS |
485 | #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00) |
486 | #define IS_SHLL_R3(x) ((x) == 0x4300) | |
8db62801 EZ |
487 | |
488 | /* ADD r3,r15 0011111100111100 | |
489 | r15+r3-->r15 */ | |
c906108c | 490 | #define IS_ADD_R3SP(x) ((x) == 0x3f3c) |
8db62801 EZ |
491 | |
492 | /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011 | |
8db62801 | 493 | FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011 |
8db62801 | 494 | FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */ |
f2ea0907 | 495 | /* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to |
c378eb4e | 496 | make this entirely clear. */ |
1c0159e0 CV |
497 | /* #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) */ |
498 | #define IS_FPUSH(x) (((x) & 0xff0f) == 0xff0b) | |
499 | ||
500 | /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 4 <= m <= 7 */ | |
501 | #define IS_MOV_ARG_TO_REG(x) \ | |
502 | (((x) & 0xf00f) == 0x6003 && \ | |
503 | ((x) & 0x00f0) >= 0x0040 && \ | |
504 | ((x) & 0x00f0) <= 0x0070) | |
505 | /* MOV.L Rm,@Rn 0010nnnnmmmm0010 n = 14, 4 <= m <= 7 */ | |
506 | #define IS_MOV_ARG_TO_IND_R14(x) \ | |
507 | (((x) & 0xff0f) == 0x2e02 && \ | |
508 | ((x) & 0x00f0) >= 0x0040 && \ | |
509 | ((x) & 0x00f0) <= 0x0070) | |
510 | /* MOV.L Rm,@(disp*4,Rn) 00011110mmmmdddd n = 14, 4 <= m <= 7 */ | |
511 | #define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \ | |
512 | (((x) & 0xff00) == 0x1e00 && \ | |
513 | ((x) & 0x00f0) >= 0x0040 && \ | |
514 | ((x) & 0x00f0) <= 0x0070) | |
515 | ||
516 | /* MOV.W @(disp*2,PC),Rn 1001nnnndddddddd */ | |
517 | #define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000) | |
518 | /* MOV.L @(disp*4,PC),Rn 1101nnnndddddddd */ | |
519 | #define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000) | |
03131d99 CV |
520 | /* MOVI20 #imm20,Rn 0000nnnniiii0000 */ |
521 | #define IS_MOVI20(x) (((x) & 0xf00f) == 0x0000) | |
1c0159e0 CV |
522 | /* SUB Rn,R15 00111111nnnn1000 */ |
523 | #define IS_SUB_REG_FROM_SP(x) (((x) & 0xff0f) == 0x3f08) | |
8db62801 | 524 | |
1c0159e0 | 525 | #define FPSCR_SZ (1 << 20) |
cc17453a | 526 | |
c378eb4e | 527 | /* The following instructions are used for epilogue testing. */ |
1c0159e0 CV |
528 | #define IS_RESTORE_FP(x) ((x) == 0x6ef6) |
529 | #define IS_RTS(x) ((x) == 0x000b) | |
530 | #define IS_LDS(x) ((x) == 0x4f26) | |
03131d99 | 531 | #define IS_MACL_LDS(x) ((x) == 0x4f16) |
1c0159e0 CV |
532 | #define IS_MOV_FP_SP(x) ((x) == 0x6fe3) |
533 | #define IS_ADD_REG_TO_FP(x) (((x) & 0xff0f) == 0x3e0c) | |
534 | #define IS_ADD_IMM_FP(x) (((x) & 0xff00) == 0x7e00) | |
cc17453a | 535 | |
cc17453a | 536 | static CORE_ADDR |
e17a4113 | 537 | sh_analyze_prologue (struct gdbarch *gdbarch, |
5cbb9812 | 538 | CORE_ADDR pc, CORE_ADDR limit_pc, |
d2ca4222 | 539 | struct sh_frame_cache *cache, ULONGEST fpscr) |
617daa0e | 540 | { |
e17a4113 | 541 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1c0159e0 | 542 | ULONGEST inst; |
1c0159e0 CV |
543 | int offset; |
544 | int sav_offset = 0; | |
c906108c | 545 | int r3_val = 0; |
1c0159e0 | 546 | int reg, sav_reg = -1; |
cc17453a | 547 | |
1c0159e0 | 548 | cache->uses_fp = 0; |
5cbb9812 | 549 | for (; pc < limit_pc; pc += 2) |
cc17453a | 550 | { |
e17a4113 | 551 | inst = read_memory_unsigned_integer (pc, 2, byte_order); |
c378eb4e | 552 | /* See where the registers will be saved to. */ |
f2ea0907 | 553 | if (IS_PUSH (inst)) |
cc17453a | 554 | { |
1c0159e0 CV |
555 | cache->saved_regs[GET_SOURCE_REG (inst)] = cache->sp_offset; |
556 | cache->sp_offset += 4; | |
cc17453a | 557 | } |
f2ea0907 | 558 | else if (IS_STS (inst)) |
cc17453a | 559 | { |
1c0159e0 CV |
560 | cache->saved_regs[PR_REGNUM] = cache->sp_offset; |
561 | cache->sp_offset += 4; | |
cc17453a | 562 | } |
03131d99 CV |
563 | else if (IS_MACL_STS (inst)) |
564 | { | |
565 | cache->saved_regs[MACL_REGNUM] = cache->sp_offset; | |
566 | cache->sp_offset += 4; | |
567 | } | |
f2ea0907 | 568 | else if (IS_MOV_R3 (inst)) |
cc17453a | 569 | { |
f2ea0907 | 570 | r3_val = ((inst & 0xff) ^ 0x80) - 0x80; |
cc17453a | 571 | } |
f2ea0907 | 572 | else if (IS_SHLL_R3 (inst)) |
cc17453a EZ |
573 | { |
574 | r3_val <<= 1; | |
575 | } | |
f2ea0907 | 576 | else if (IS_ADD_R3SP (inst)) |
cc17453a | 577 | { |
1c0159e0 | 578 | cache->sp_offset += -r3_val; |
cc17453a | 579 | } |
f2ea0907 | 580 | else if (IS_ADD_IMM_SP (inst)) |
cc17453a | 581 | { |
1c0159e0 CV |
582 | offset = ((inst & 0xff) ^ 0x80) - 0x80; |
583 | cache->sp_offset -= offset; | |
c906108c | 584 | } |
1c0159e0 | 585 | else if (IS_MOVW_PCREL_TO_REG (inst)) |
617daa0e | 586 | { |
1c0159e0 CV |
587 | if (sav_reg < 0) |
588 | { | |
589 | reg = GET_TARGET_REG (inst); | |
590 | if (reg < 14) | |
591 | { | |
592 | sav_reg = reg; | |
a2b4a96c | 593 | offset = (inst & 0xff) << 1; |
1c0159e0 | 594 | sav_offset = |
e17a4113 | 595 | read_memory_integer ((pc + 4) + offset, 2, byte_order); |
1c0159e0 CV |
596 | } |
597 | } | |
c906108c | 598 | } |
1c0159e0 | 599 | else if (IS_MOVL_PCREL_TO_REG (inst)) |
617daa0e | 600 | { |
1c0159e0 CV |
601 | if (sav_reg < 0) |
602 | { | |
a2b4a96c | 603 | reg = GET_TARGET_REG (inst); |
1c0159e0 CV |
604 | if (reg < 14) |
605 | { | |
606 | sav_reg = reg; | |
a2b4a96c | 607 | offset = (inst & 0xff) << 2; |
1c0159e0 | 608 | sav_offset = |
e17a4113 UW |
609 | read_memory_integer (((pc & 0xfffffffc) + 4) + offset, |
610 | 4, byte_order); | |
1c0159e0 CV |
611 | } |
612 | } | |
c906108c | 613 | } |
5cbb9812 TS |
614 | else if (IS_MOVI20 (inst) |
615 | && (pc + 2 < limit_pc)) | |
03131d99 CV |
616 | { |
617 | if (sav_reg < 0) | |
618 | { | |
619 | reg = GET_TARGET_REG (inst); | |
620 | if (reg < 14) | |
621 | { | |
622 | sav_reg = reg; | |
623 | sav_offset = GET_SOURCE_REG (inst) << 16; | |
c378eb4e | 624 | /* MOVI20 is a 32 bit instruction! */ |
03131d99 | 625 | pc += 2; |
e17a4113 UW |
626 | sav_offset |
627 | |= read_memory_unsigned_integer (pc, 2, byte_order); | |
03131d99 CV |
628 | /* Now sav_offset contains an unsigned 20 bit value. |
629 | It must still get sign extended. */ | |
630 | if (sav_offset & 0x00080000) | |
631 | sav_offset |= 0xfff00000; | |
632 | } | |
633 | } | |
634 | } | |
1c0159e0 | 635 | else if (IS_SUB_REG_FROM_SP (inst)) |
617daa0e | 636 | { |
1c0159e0 CV |
637 | reg = GET_SOURCE_REG (inst); |
638 | if (sav_reg > 0 && reg == sav_reg) | |
639 | { | |
640 | sav_reg = -1; | |
641 | } | |
642 | cache->sp_offset += sav_offset; | |
c906108c | 643 | } |
f2ea0907 | 644 | else if (IS_FPUSH (inst)) |
c906108c | 645 | { |
d2ca4222 | 646 | if (fpscr & FPSCR_SZ) |
c906108c | 647 | { |
1c0159e0 | 648 | cache->sp_offset += 8; |
c906108c SS |
649 | } |
650 | else | |
651 | { | |
1c0159e0 | 652 | cache->sp_offset += 4; |
c906108c SS |
653 | } |
654 | } | |
f2ea0907 | 655 | else if (IS_MOV_SP_FP (inst)) |
617daa0e | 656 | { |
5cbb9812 TS |
657 | pc += 2; |
658 | /* Don't go any further than six more instructions. */ | |
659 | limit_pc = min (limit_pc, pc + (2 * 6)); | |
660 | ||
960ccd7d | 661 | cache->uses_fp = 1; |
1c0159e0 CV |
662 | /* At this point, only allow argument register moves to other |
663 | registers or argument register moves to @(X,fp) which are | |
664 | moving the register arguments onto the stack area allocated | |
665 | by a former add somenumber to SP call. Don't allow moving | |
c378eb4e | 666 | to an fp indirect address above fp + cache->sp_offset. */ |
5cbb9812 | 667 | for (; pc < limit_pc; pc += 2) |
1c0159e0 | 668 | { |
e17a4113 | 669 | inst = read_memory_integer (pc, 2, byte_order); |
1c0159e0 | 670 | if (IS_MOV_ARG_TO_IND_R14 (inst)) |
617daa0e | 671 | { |
1c0159e0 CV |
672 | reg = GET_SOURCE_REG (inst); |
673 | if (cache->sp_offset > 0) | |
617daa0e | 674 | cache->saved_regs[reg] = cache->sp_offset; |
1c0159e0 CV |
675 | } |
676 | else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst)) | |
617daa0e | 677 | { |
1c0159e0 CV |
678 | reg = GET_SOURCE_REG (inst); |
679 | offset = (inst & 0xf) * 4; | |
680 | if (cache->sp_offset > offset) | |
681 | cache->saved_regs[reg] = cache->sp_offset - offset; | |
682 | } | |
683 | else if (IS_MOV_ARG_TO_REG (inst)) | |
617daa0e | 684 | continue; |
1c0159e0 CV |
685 | else |
686 | break; | |
687 | } | |
688 | break; | |
689 | } | |
5f883edd FF |
690 | else if (IS_JSR (inst)) |
691 | { | |
692 | /* We have found a jsr that has been scheduled into the prologue. | |
693 | If we continue the scan and return a pc someplace after this, | |
694 | then setting a breakpoint on this function will cause it to | |
695 | appear to be called after the function it is calling via the | |
696 | jsr, which will be very confusing. Most likely the next | |
697 | instruction is going to be IS_MOV_SP_FP in the delay slot. If | |
c378eb4e | 698 | so, note that before returning the current pc. */ |
5cbb9812 TS |
699 | if (pc + 2 < limit_pc) |
700 | { | |
701 | inst = read_memory_integer (pc + 2, 2, byte_order); | |
702 | if (IS_MOV_SP_FP (inst)) | |
703 | cache->uses_fp = 1; | |
704 | } | |
5f883edd FF |
705 | break; |
706 | } | |
c378eb4e MS |
707 | #if 0 /* This used to just stop when it found an instruction |
708 | that was not considered part of the prologue. Now, | |
709 | we just keep going looking for likely | |
710 | instructions. */ | |
c906108c SS |
711 | else |
712 | break; | |
2bfa91ee | 713 | #endif |
c906108c SS |
714 | } |
715 | ||
1c0159e0 CV |
716 | return pc; |
717 | } | |
c906108c | 718 | |
c378eb4e | 719 | /* Skip any prologue before the guts of a function. */ |
1c0159e0 | 720 | static CORE_ADDR |
8a8bc27f | 721 | sh_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
c906108c | 722 | { |
5cbb9812 | 723 | CORE_ADDR post_prologue_pc, func_addr, func_end_addr, limit_pc; |
1c0159e0 CV |
724 | struct sh_frame_cache cache; |
725 | ||
726 | /* See if we can determine the end of the prologue via the symbol table. | |
727 | If so, then return either PC, or the PC after the prologue, whichever | |
728 | is greater. */ | |
5cbb9812 | 729 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end_addr)) |
8a8bc27f TS |
730 | { |
731 | post_prologue_pc = skip_prologue_using_sal (gdbarch, func_addr); | |
732 | if (post_prologue_pc != 0) | |
733 | return max (pc, post_prologue_pc); | |
734 | } | |
cc17453a | 735 | |
8a8bc27f TS |
736 | /* Can't determine prologue from the symbol table, need to examine |
737 | instructions. */ | |
c906108c | 738 | |
5cbb9812 TS |
739 | /* Find an upper limit on the function prologue using the debug |
740 | information. If the debug information could not be used to provide | |
741 | that bound, then use an arbitrary large number as the upper bound. */ | |
742 | limit_pc = skip_prologue_using_sal (gdbarch, pc); | |
743 | if (limit_pc == 0) | |
744 | /* Don't go any further than 28 instructions. */ | |
745 | limit_pc = pc + (2 * 28); | |
746 | ||
747 | /* Do not allow limit_pc to be past the function end, if we know | |
748 | where that end is... */ | |
749 | if (func_end_addr != 0) | |
750 | limit_pc = min (limit_pc, func_end_addr); | |
751 | ||
1c0159e0 | 752 | cache.sp_offset = -4; |
5cbb9812 | 753 | post_prologue_pc = sh_analyze_prologue (gdbarch, pc, limit_pc, &cache, 0); |
8a8bc27f TS |
754 | if (cache.uses_fp) |
755 | pc = post_prologue_pc; | |
c906108c | 756 | |
1c0159e0 CV |
757 | return pc; |
758 | } | |
759 | ||
2e952408 | 760 | /* The ABI says: |
9a5cef92 EZ |
761 | |
762 | Aggregate types not bigger than 8 bytes that have the same size and | |
763 | alignment as one of the integer scalar types are returned in the | |
764 | same registers as the integer type they match. | |
765 | ||
766 | For example, a 2-byte aligned structure with size 2 bytes has the | |
767 | same size and alignment as a short int, and will be returned in R0. | |
768 | A 4-byte aligned structure with size 8 bytes has the same size and | |
769 | alignment as a long long int, and will be returned in R0 and R1. | |
770 | ||
771 | When an aggregate type is returned in R0 and R1, R0 contains the | |
772 | first four bytes of the aggregate, and R1 contains the | |
c378eb4e | 773 | remainder. If the size of the aggregate type is not a multiple of 4 |
9a5cef92 | 774 | bytes, the aggregate is tail-padded up to a multiple of 4 |
c378eb4e | 775 | bytes. The value of the padding is undefined. For little-endian |
9a5cef92 EZ |
776 | targets the padding will appear at the most significant end of the |
777 | last element, for big-endian targets the padding appears at the | |
778 | least significant end of the last element. | |
779 | ||
c378eb4e | 780 | All other aggregate types are returned by address. The caller |
9a5cef92 | 781 | function passes the address of an area large enough to hold the |
c378eb4e | 782 | aggregate value in R2. The called function stores the result in |
7fe958be | 783 | this location. |
9a5cef92 EZ |
784 | |
785 | To reiterate, structs smaller than 8 bytes could also be returned | |
786 | in memory, if they don't pass the "same size and alignment as an | |
787 | integer type" rule. | |
788 | ||
789 | For example, in | |
790 | ||
791 | struct s { char c[3]; } wibble; | |
792 | struct s foo(void) { return wibble; } | |
793 | ||
794 | the return value from foo() will be in memory, not | |
795 | in R0, because there is no 3-byte integer type. | |
796 | ||
7fe958be EZ |
797 | Similarly, in |
798 | ||
799 | struct s { char c[2]; } wibble; | |
800 | struct s foo(void) { return wibble; } | |
801 | ||
802 | because a struct containing two chars has alignment 1, that matches | |
803 | type char, but size 2, that matches type short. There's no integer | |
804 | type that has alignment 1 and size 2, so the struct is returned in | |
c378eb4e | 805 | memory. */ |
9a5cef92 | 806 | |
1c0159e0 | 807 | static int |
c055b101 | 808 | sh_use_struct_convention (int renesas_abi, struct type *type) |
1c0159e0 CV |
809 | { |
810 | int len = TYPE_LENGTH (type); | |
811 | int nelem = TYPE_NFIELDS (type); | |
3f997a97 | 812 | |
c055b101 CV |
813 | /* The Renesas ABI returns aggregate types always on stack. */ |
814 | if (renesas_abi && (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
815 | || TYPE_CODE (type) == TYPE_CODE_UNION)) | |
816 | return 1; | |
817 | ||
3f997a97 CV |
818 | /* Non-power of 2 length types and types bigger than 8 bytes (which don't |
819 | fit in two registers anyway) use struct convention. */ | |
820 | if (len != 1 && len != 2 && len != 4 && len != 8) | |
821 | return 1; | |
822 | ||
823 | /* Scalar types and aggregate types with exactly one field are aligned | |
824 | by definition. They are returned in registers. */ | |
825 | if (nelem <= 1) | |
826 | return 0; | |
827 | ||
828 | /* If the first field in the aggregate has the same length as the entire | |
829 | aggregate type, the type is returned in registers. */ | |
830 | if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == len) | |
831 | return 0; | |
832 | ||
833 | /* If the size of the aggregate is 8 bytes and the first field is | |
834 | of size 4 bytes its alignment is equal to long long's alignment, | |
835 | so it's returned in registers. */ | |
836 | if (len == 8 && TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == 4) | |
837 | return 0; | |
838 | ||
839 | /* Otherwise use struct convention. */ | |
840 | return 1; | |
283150cd EZ |
841 | } |
842 | ||
c055b101 CV |
843 | static int |
844 | sh_use_struct_convention_nofpu (int renesas_abi, struct type *type) | |
845 | { | |
846 | /* The Renesas ABI returns long longs/doubles etc. always on stack. */ | |
847 | if (renesas_abi && TYPE_NFIELDS (type) == 0 && TYPE_LENGTH (type) >= 8) | |
848 | return 1; | |
849 | return sh_use_struct_convention (renesas_abi, type); | |
850 | } | |
851 | ||
19f59343 MS |
852 | static CORE_ADDR |
853 | sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp) | |
854 | { | |
855 | return sp & ~3; | |
856 | } | |
857 | ||
55ff77ac | 858 | /* Function: push_dummy_call (formerly push_arguments) |
c906108c SS |
859 | Setup the function arguments for calling a function in the inferior. |
860 | ||
85a453d5 | 861 | On the Renesas SH architecture, there are four registers (R4 to R7) |
c906108c SS |
862 | which are dedicated for passing function arguments. Up to the first |
863 | four arguments (depending on size) may go into these registers. | |
864 | The rest go on the stack. | |
865 | ||
6df2bf50 MS |
866 | MVS: Except on SH variants that have floating point registers. |
867 | In that case, float and double arguments are passed in the same | |
868 | manner, but using FP registers instead of GP registers. | |
869 | ||
c906108c SS |
870 | Arguments that are smaller than 4 bytes will still take up a whole |
871 | register or a whole 32-bit word on the stack, and will be | |
872 | right-justified in the register or the stack word. This includes | |
873 | chars, shorts, and small aggregate types. | |
874 | ||
875 | Arguments that are larger than 4 bytes may be split between two or | |
876 | more registers. If there are not enough registers free, an argument | |
877 | may be passed partly in a register (or registers), and partly on the | |
c378eb4e | 878 | stack. This includes doubles, long longs, and larger aggregates. |
c906108c SS |
879 | As far as I know, there is no upper limit to the size of aggregates |
880 | that will be passed in this way; in other words, the convention of | |
881 | passing a pointer to a large aggregate instead of a copy is not used. | |
882 | ||
6df2bf50 | 883 | MVS: The above appears to be true for the SH variants that do not |
55ff77ac | 884 | have an FPU, however those that have an FPU appear to copy the |
6df2bf50 MS |
885 | aggregate argument onto the stack (and not place it in registers) |
886 | if it is larger than 16 bytes (four GP registers). | |
887 | ||
c906108c SS |
888 | An exceptional case exists for struct arguments (and possibly other |
889 | aggregates such as arrays) if the size is larger than 4 bytes but | |
890 | not a multiple of 4 bytes. In this case the argument is never split | |
891 | between the registers and the stack, but instead is copied in its | |
892 | entirety onto the stack, AND also copied into as many registers as | |
893 | there is room for. In other words, space in registers permitting, | |
894 | two copies of the same argument are passed in. As far as I can tell, | |
895 | only the one on the stack is used, although that may be a function | |
896 | of the level of compiler optimization. I suspect this is a compiler | |
897 | bug. Arguments of these odd sizes are left-justified within the | |
898 | word (as opposed to arguments smaller than 4 bytes, which are | |
899 | right-justified). | |
c5aa993b | 900 | |
c906108c SS |
901 | If the function is to return an aggregate type such as a struct, it |
902 | is either returned in the normal return value register R0 (if its | |
903 | size is no greater than one byte), or else the caller must allocate | |
904 | space into which the callee will copy the return value (if the size | |
905 | is greater than one byte). In this case, a pointer to the return | |
906 | value location is passed into the callee in register R2, which does | |
907 | not displace any of the other arguments passed in via registers R4 | |
c378eb4e | 908 | to R7. */ |
c906108c | 909 | |
c378eb4e | 910 | /* Helper function to justify value in register according to endianess. */ |
948f8e3d | 911 | static const gdb_byte * |
d93859e2 | 912 | sh_justify_value_in_reg (struct gdbarch *gdbarch, struct value *val, int len) |
e5e33cd9 | 913 | { |
948f8e3d | 914 | static gdb_byte valbuf[4]; |
e5e33cd9 | 915 | |
617daa0e | 916 | memset (valbuf, 0, sizeof (valbuf)); |
e5e33cd9 CV |
917 | if (len < 4) |
918 | { | |
c378eb4e | 919 | /* value gets right-justified in the register or stack word. */ |
d93859e2 | 920 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
948f8e3d | 921 | memcpy (valbuf + (4 - len), value_contents (val), len); |
e5e33cd9 | 922 | else |
948f8e3d | 923 | memcpy (valbuf, value_contents (val), len); |
e5e33cd9 CV |
924 | return valbuf; |
925 | } | |
948f8e3d | 926 | return value_contents (val); |
617daa0e | 927 | } |
e5e33cd9 | 928 | |
c378eb4e | 929 | /* Helper function to eval number of bytes to allocate on stack. */ |
e5e33cd9 CV |
930 | static CORE_ADDR |
931 | sh_stack_allocsize (int nargs, struct value **args) | |
932 | { | |
933 | int stack_alloc = 0; | |
934 | while (nargs-- > 0) | |
4991999e | 935 | stack_alloc += ((TYPE_LENGTH (value_type (args[nargs])) + 3) & ~3); |
e5e33cd9 CV |
936 | return stack_alloc; |
937 | } | |
938 | ||
939 | /* Helper functions for getting the float arguments right. Registers usage | |
940 | depends on the ABI and the endianess. The comments should enlighten how | |
c378eb4e | 941 | it's intended to work. */ |
e5e33cd9 | 942 | |
c378eb4e | 943 | /* This array stores which of the float arg registers are already in use. */ |
e5e33cd9 CV |
944 | static int flt_argreg_array[FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM + 1]; |
945 | ||
c378eb4e | 946 | /* This function just resets the above array to "no reg used so far". */ |
e5e33cd9 CV |
947 | static void |
948 | sh_init_flt_argreg (void) | |
949 | { | |
950 | memset (flt_argreg_array, 0, sizeof flt_argreg_array); | |
951 | } | |
952 | ||
953 | /* This function returns the next register to use for float arg passing. | |
954 | It returns either a valid value between FLOAT_ARG0_REGNUM and | |
955 | FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns | |
956 | FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available. | |
957 | ||
958 | Note that register number 0 in flt_argreg_array corresponds with the | |
959 | real float register fr4. In contrast to FLOAT_ARG0_REGNUM (value is | |
960 | 29) the parity of the register number is preserved, which is important | |
c378eb4e | 961 | for the double register passing test (see the "argreg & 1" test below). */ |
e5e33cd9 | 962 | static int |
c055b101 | 963 | sh_next_flt_argreg (struct gdbarch *gdbarch, int len, struct type *func_type) |
e5e33cd9 CV |
964 | { |
965 | int argreg; | |
966 | ||
c378eb4e | 967 | /* First search for the next free register. */ |
617daa0e CV |
968 | for (argreg = 0; argreg <= FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM; |
969 | ++argreg) | |
e5e33cd9 CV |
970 | if (!flt_argreg_array[argreg]) |
971 | break; | |
972 | ||
c378eb4e | 973 | /* No register left? */ |
e5e33cd9 CV |
974 | if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM) |
975 | return FLOAT_ARGLAST_REGNUM + 1; | |
976 | ||
977 | if (len == 8) | |
978 | { | |
c378eb4e | 979 | /* Doubles are always starting in a even register number. */ |
e5e33cd9 | 980 | if (argreg & 1) |
617daa0e | 981 | { |
c055b101 CV |
982 | /* In gcc ABI, the skipped register is lost for further argument |
983 | passing now. Not so in Renesas ABI. */ | |
984 | if (!sh_is_renesas_calling_convention (func_type)) | |
985 | flt_argreg_array[argreg] = 1; | |
e5e33cd9 CV |
986 | |
987 | ++argreg; | |
988 | ||
c378eb4e | 989 | /* No register left? */ |
e5e33cd9 CV |
990 | if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM) |
991 | return FLOAT_ARGLAST_REGNUM + 1; | |
992 | } | |
c378eb4e | 993 | /* Also mark the next register as used. */ |
e5e33cd9 CV |
994 | flt_argreg_array[argreg + 1] = 1; |
995 | } | |
c055b101 CV |
996 | else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE |
997 | && !sh_is_renesas_calling_convention (func_type)) | |
e5e33cd9 | 998 | { |
c378eb4e | 999 | /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */ |
e5e33cd9 CV |
1000 | if (!flt_argreg_array[argreg + 1]) |
1001 | ++argreg; | |
1002 | } | |
1003 | flt_argreg_array[argreg] = 1; | |
1004 | return FLOAT_ARG0_REGNUM + argreg; | |
1005 | } | |
1006 | ||
afce3d2a CV |
1007 | /* Helper function which figures out, if a type is treated like a float type. |
1008 | ||
2e952408 | 1009 | The FPU ABIs have a special way how to treat types as float types. |
afce3d2a CV |
1010 | Structures with exactly one member, which is of type float or double, are |
1011 | treated exactly as the base types float or double: | |
1012 | ||
1013 | struct sf { | |
1014 | float f; | |
1015 | }; | |
1016 | ||
1017 | struct sd { | |
1018 | double d; | |
1019 | }; | |
1020 | ||
1021 | are handled the same way as just | |
1022 | ||
1023 | float f; | |
1024 | ||
1025 | double d; | |
1026 | ||
1027 | As a result, arguments of these struct types are pushed into floating point | |
1028 | registers exactly as floats or doubles, using the same decision algorithm. | |
1029 | ||
1030 | The same is valid if these types are used as function return types. The | |
1031 | above structs are returned in fr0 resp. fr0,fr1 instead of in r0, r0,r1 | |
1032 | or even using struct convention as it is for other structs. */ | |
1033 | ||
1034 | static int | |
1035 | sh_treat_as_flt_p (struct type *type) | |
1036 | { | |
afce3d2a CV |
1037 | /* Ordinary float types are obviously treated as float. */ |
1038 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
1039 | return 1; | |
1040 | /* Otherwise non-struct types are not treated as float. */ | |
1041 | if (TYPE_CODE (type) != TYPE_CODE_STRUCT) | |
1042 | return 0; | |
1043 | /* Otherwise structs with more than one memeber are not treated as float. */ | |
1044 | if (TYPE_NFIELDS (type) != 1) | |
1045 | return 0; | |
1046 | /* Otherwise if the type of that member is float, the whole type is | |
1047 | treated as float. */ | |
1048 | if (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) == TYPE_CODE_FLT) | |
1049 | return 1; | |
1050 | /* Otherwise it's not treated as float. */ | |
1051 | return 0; | |
1052 | } | |
1053 | ||
cc17453a | 1054 | static CORE_ADDR |
617daa0e | 1055 | sh_push_dummy_call_fpu (struct gdbarch *gdbarch, |
7d9b040b | 1056 | struct value *function, |
617daa0e | 1057 | struct regcache *regcache, |
6df2bf50 | 1058 | CORE_ADDR bp_addr, int nargs, |
617daa0e | 1059 | struct value **args, |
6df2bf50 MS |
1060 | CORE_ADDR sp, int struct_return, |
1061 | CORE_ADDR struct_addr) | |
1062 | { | |
e17a4113 | 1063 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
e5e33cd9 CV |
1064 | int stack_offset = 0; |
1065 | int argreg = ARG0_REGNUM; | |
8748518b | 1066 | int flt_argreg = 0; |
6df2bf50 | 1067 | int argnum; |
c055b101 | 1068 | struct type *func_type = value_type (function); |
6df2bf50 MS |
1069 | struct type *type; |
1070 | CORE_ADDR regval; | |
948f8e3d | 1071 | const gdb_byte *val; |
8748518b | 1072 | int len, reg_size = 0; |
afce3d2a CV |
1073 | int pass_on_stack = 0; |
1074 | int treat_as_flt; | |
c055b101 CV |
1075 | int last_reg_arg = INT_MAX; |
1076 | ||
1077 | /* The Renesas ABI expects all varargs arguments, plus the last | |
1078 | non-vararg argument to be on the stack, no matter how many | |
1079 | registers have been used so far. */ | |
1080 | if (sh_is_renesas_calling_convention (func_type) | |
876cecd0 | 1081 | && TYPE_VARARGS (func_type)) |
c055b101 | 1082 | last_reg_arg = TYPE_NFIELDS (func_type) - 2; |
6df2bf50 | 1083 | |
c378eb4e | 1084 | /* First force sp to a 4-byte alignment. */ |
6df2bf50 MS |
1085 | sp = sh_frame_align (gdbarch, sp); |
1086 | ||
c378eb4e | 1087 | /* Make room on stack for args. */ |
e5e33cd9 CV |
1088 | sp -= sh_stack_allocsize (nargs, args); |
1089 | ||
c378eb4e | 1090 | /* Initialize float argument mechanism. */ |
e5e33cd9 | 1091 | sh_init_flt_argreg (); |
6df2bf50 MS |
1092 | |
1093 | /* Now load as many as possible of the first arguments into | |
1094 | registers, and push the rest onto the stack. There are 16 bytes | |
1095 | in four registers available. Loop thru args from first to last. */ | |
e5e33cd9 | 1096 | for (argnum = 0; argnum < nargs; argnum++) |
6df2bf50 | 1097 | { |
4991999e | 1098 | type = value_type (args[argnum]); |
6df2bf50 | 1099 | len = TYPE_LENGTH (type); |
d93859e2 | 1100 | val = sh_justify_value_in_reg (gdbarch, args[argnum], len); |
e5e33cd9 CV |
1101 | |
1102 | /* Some decisions have to be made how various types are handled. | |
c378eb4e | 1103 | This also differs in different ABIs. */ |
e5e33cd9 | 1104 | pass_on_stack = 0; |
e5e33cd9 | 1105 | |
c378eb4e | 1106 | /* Find out the next register to use for a floating point value. */ |
afce3d2a CV |
1107 | treat_as_flt = sh_treat_as_flt_p (type); |
1108 | if (treat_as_flt) | |
c055b101 CV |
1109 | flt_argreg = sh_next_flt_argreg (gdbarch, len, func_type); |
1110 | /* In Renesas ABI, long longs and aggregate types are always passed | |
1111 | on stack. */ | |
1112 | else if (sh_is_renesas_calling_convention (func_type) | |
1113 | && ((TYPE_CODE (type) == TYPE_CODE_INT && len == 8) | |
1114 | || TYPE_CODE (type) == TYPE_CODE_STRUCT | |
1115 | || TYPE_CODE (type) == TYPE_CODE_UNION)) | |
1116 | pass_on_stack = 1; | |
afce3d2a CV |
1117 | /* In contrast to non-FPU CPUs, arguments are never split between |
1118 | registers and stack. If an argument doesn't fit in the remaining | |
1119 | registers it's always pushed entirely on the stack. */ | |
1120 | else if (len > ((ARGLAST_REGNUM - argreg + 1) * 4)) | |
1121 | pass_on_stack = 1; | |
48db5a3c | 1122 | |
6df2bf50 MS |
1123 | while (len > 0) |
1124 | { | |
afce3d2a CV |
1125 | if ((treat_as_flt && flt_argreg > FLOAT_ARGLAST_REGNUM) |
1126 | || (!treat_as_flt && (argreg > ARGLAST_REGNUM | |
c055b101 CV |
1127 | || pass_on_stack)) |
1128 | || argnum > last_reg_arg) | |
617daa0e | 1129 | { |
c378eb4e | 1130 | /* The data goes entirely on the stack, 4-byte aligned. */ |
e5e33cd9 CV |
1131 | reg_size = (len + 3) & ~3; |
1132 | write_memory (sp + stack_offset, val, reg_size); | |
1133 | stack_offset += reg_size; | |
6df2bf50 | 1134 | } |
afce3d2a | 1135 | else if (treat_as_flt && flt_argreg <= FLOAT_ARGLAST_REGNUM) |
6df2bf50 | 1136 | { |
e5e33cd9 CV |
1137 | /* Argument goes in a float argument register. */ |
1138 | reg_size = register_size (gdbarch, flt_argreg); | |
e17a4113 | 1139 | regval = extract_unsigned_integer (val, reg_size, byte_order); |
2e952408 CV |
1140 | /* In little endian mode, float types taking two registers |
1141 | (doubles on sh4, long doubles on sh2e, sh3e and sh4) must | |
1142 | be stored swapped in the argument registers. The below | |
1143 | code first writes the first 32 bits in the next but one | |
1144 | register, increments the val and len values accordingly | |
1145 | and then proceeds as normal by writing the second 32 bits | |
c378eb4e | 1146 | into the next register. */ |
b47193f7 | 1147 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE |
2e952408 CV |
1148 | && TYPE_LENGTH (type) == 2 * reg_size) |
1149 | { | |
1150 | regcache_cooked_write_unsigned (regcache, flt_argreg + 1, | |
1151 | regval); | |
1152 | val += reg_size; | |
1153 | len -= reg_size; | |
c378eb4e MS |
1154 | regval = extract_unsigned_integer (val, reg_size, |
1155 | byte_order); | |
2e952408 | 1156 | } |
6df2bf50 MS |
1157 | regcache_cooked_write_unsigned (regcache, flt_argreg++, regval); |
1158 | } | |
afce3d2a | 1159 | else if (!treat_as_flt && argreg <= ARGLAST_REGNUM) |
e5e33cd9 | 1160 | { |
6df2bf50 | 1161 | /* there's room in a register */ |
e5e33cd9 | 1162 | reg_size = register_size (gdbarch, argreg); |
e17a4113 | 1163 | regval = extract_unsigned_integer (val, reg_size, byte_order); |
6df2bf50 MS |
1164 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
1165 | } | |
c378eb4e MS |
1166 | /* Store the value one register at a time or in one step on |
1167 | stack. */ | |
e5e33cd9 CV |
1168 | len -= reg_size; |
1169 | val += reg_size; | |
6df2bf50 MS |
1170 | } |
1171 | } | |
1172 | ||
c055b101 CV |
1173 | if (struct_return) |
1174 | { | |
1175 | if (sh_is_renesas_calling_convention (func_type)) | |
1176 | /* If the function uses the Renesas ABI, subtract another 4 bytes from | |
1177 | the stack and store the struct return address there. */ | |
e17a4113 | 1178 | write_memory_unsigned_integer (sp -= 4, 4, byte_order, struct_addr); |
c055b101 CV |
1179 | else |
1180 | /* Using the gcc ABI, the "struct return pointer" pseudo-argument has | |
1181 | its own dedicated register. */ | |
1182 | regcache_cooked_write_unsigned (regcache, | |
1183 | STRUCT_RETURN_REGNUM, struct_addr); | |
1184 | } | |
1185 | ||
c378eb4e | 1186 | /* Store return address. */ |
55ff77ac | 1187 | regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr); |
6df2bf50 MS |
1188 | |
1189 | /* Update stack pointer. */ | |
3e8c568d | 1190 | regcache_cooked_write_unsigned (regcache, |
b47193f7 | 1191 | gdbarch_sp_regnum (gdbarch), sp); |
6df2bf50 MS |
1192 | |
1193 | return sp; | |
1194 | } | |
1195 | ||
1196 | static CORE_ADDR | |
617daa0e | 1197 | sh_push_dummy_call_nofpu (struct gdbarch *gdbarch, |
7d9b040b | 1198 | struct value *function, |
617daa0e CV |
1199 | struct regcache *regcache, |
1200 | CORE_ADDR bp_addr, | |
1201 | int nargs, struct value **args, | |
1202 | CORE_ADDR sp, int struct_return, | |
6df2bf50 | 1203 | CORE_ADDR struct_addr) |
c906108c | 1204 | { |
e17a4113 | 1205 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
e5e33cd9 CV |
1206 | int stack_offset = 0; |
1207 | int argreg = ARG0_REGNUM; | |
c906108c | 1208 | int argnum; |
c055b101 | 1209 | struct type *func_type = value_type (function); |
c906108c SS |
1210 | struct type *type; |
1211 | CORE_ADDR regval; | |
948f8e3d | 1212 | const gdb_byte *val; |
c055b101 CV |
1213 | int len, reg_size = 0; |
1214 | int pass_on_stack = 0; | |
1215 | int last_reg_arg = INT_MAX; | |
1216 | ||
1217 | /* The Renesas ABI expects all varargs arguments, plus the last | |
1218 | non-vararg argument to be on the stack, no matter how many | |
1219 | registers have been used so far. */ | |
1220 | if (sh_is_renesas_calling_convention (func_type) | |
876cecd0 | 1221 | && TYPE_VARARGS (func_type)) |
c055b101 | 1222 | last_reg_arg = TYPE_NFIELDS (func_type) - 2; |
c906108c | 1223 | |
c378eb4e | 1224 | /* First force sp to a 4-byte alignment. */ |
19f59343 | 1225 | sp = sh_frame_align (gdbarch, sp); |
c906108c | 1226 | |
c378eb4e | 1227 | /* Make room on stack for args. */ |
e5e33cd9 | 1228 | sp -= sh_stack_allocsize (nargs, args); |
c906108c | 1229 | |
c906108c SS |
1230 | /* Now load as many as possible of the first arguments into |
1231 | registers, and push the rest onto the stack. There are 16 bytes | |
1232 | in four registers available. Loop thru args from first to last. */ | |
e5e33cd9 | 1233 | for (argnum = 0; argnum < nargs; argnum++) |
617daa0e | 1234 | { |
4991999e | 1235 | type = value_type (args[argnum]); |
c5aa993b | 1236 | len = TYPE_LENGTH (type); |
d93859e2 | 1237 | val = sh_justify_value_in_reg (gdbarch, args[argnum], len); |
c906108c | 1238 | |
c055b101 | 1239 | /* Some decisions have to be made how various types are handled. |
c378eb4e | 1240 | This also differs in different ABIs. */ |
c055b101 CV |
1241 | pass_on_stack = 0; |
1242 | /* Renesas ABI pushes doubles and long longs entirely on stack. | |
1243 | Same goes for aggregate types. */ | |
1244 | if (sh_is_renesas_calling_convention (func_type) | |
1245 | && ((TYPE_CODE (type) == TYPE_CODE_INT && len >= 8) | |
1246 | || (TYPE_CODE (type) == TYPE_CODE_FLT && len >= 8) | |
1247 | || TYPE_CODE (type) == TYPE_CODE_STRUCT | |
1248 | || TYPE_CODE (type) == TYPE_CODE_UNION)) | |
1249 | pass_on_stack = 1; | |
c906108c SS |
1250 | while (len > 0) |
1251 | { | |
c055b101 CV |
1252 | if (argreg > ARGLAST_REGNUM || pass_on_stack |
1253 | || argnum > last_reg_arg) | |
617daa0e | 1254 | { |
e5e33cd9 | 1255 | /* The remainder of the data goes entirely on the stack, |
c378eb4e | 1256 | 4-byte aligned. */ |
e5e33cd9 CV |
1257 | reg_size = (len + 3) & ~3; |
1258 | write_memory (sp + stack_offset, val, reg_size); | |
617daa0e | 1259 | stack_offset += reg_size; |
c906108c | 1260 | } |
e5e33cd9 | 1261 | else if (argreg <= ARGLAST_REGNUM) |
617daa0e | 1262 | { |
c378eb4e | 1263 | /* There's room in a register. */ |
e5e33cd9 | 1264 | reg_size = register_size (gdbarch, argreg); |
e17a4113 | 1265 | regval = extract_unsigned_integer (val, reg_size, byte_order); |
48db5a3c | 1266 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
c906108c | 1267 | } |
e5e33cd9 CV |
1268 | /* Store the value reg_size bytes at a time. This means that things |
1269 | larger than reg_size bytes may go partly in registers and partly | |
c906108c | 1270 | on the stack. */ |
e5e33cd9 CV |
1271 | len -= reg_size; |
1272 | val += reg_size; | |
c906108c SS |
1273 | } |
1274 | } | |
48db5a3c | 1275 | |
c055b101 CV |
1276 | if (struct_return) |
1277 | { | |
1278 | if (sh_is_renesas_calling_convention (func_type)) | |
1279 | /* If the function uses the Renesas ABI, subtract another 4 bytes from | |
1280 | the stack and store the struct return address there. */ | |
e17a4113 | 1281 | write_memory_unsigned_integer (sp -= 4, 4, byte_order, struct_addr); |
c055b101 CV |
1282 | else |
1283 | /* Using the gcc ABI, the "struct return pointer" pseudo-argument has | |
1284 | its own dedicated register. */ | |
1285 | regcache_cooked_write_unsigned (regcache, | |
1286 | STRUCT_RETURN_REGNUM, struct_addr); | |
1287 | } | |
1288 | ||
c378eb4e | 1289 | /* Store return address. */ |
55ff77ac | 1290 | regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr); |
48db5a3c CV |
1291 | |
1292 | /* Update stack pointer. */ | |
3e8c568d | 1293 | regcache_cooked_write_unsigned (regcache, |
b47193f7 | 1294 | gdbarch_sp_regnum (gdbarch), sp); |
48db5a3c | 1295 | |
c906108c SS |
1296 | return sp; |
1297 | } | |
1298 | ||
cc17453a EZ |
1299 | /* Find a function's return value in the appropriate registers (in |
1300 | regbuf), and copy it into valbuf. Extract from an array REGBUF | |
1301 | containing the (raw) register state a function return value of type | |
1302 | TYPE, and copy that, in virtual format, into VALBUF. */ | |
1303 | static void | |
3ffc5b9b | 1304 | sh_extract_return_value_nofpu (struct type *type, struct regcache *regcache, |
948f8e3d | 1305 | gdb_byte *valbuf) |
c906108c | 1306 | { |
e17a4113 UW |
1307 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
1308 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
cc17453a | 1309 | int len = TYPE_LENGTH (type); |
3116c80a EZ |
1310 | int return_register = R0_REGNUM; |
1311 | int offset; | |
617daa0e | 1312 | |
cc17453a | 1313 | if (len <= 4) |
3116c80a | 1314 | { |
48db5a3c CV |
1315 | ULONGEST c; |
1316 | ||
1317 | regcache_cooked_read_unsigned (regcache, R0_REGNUM, &c); | |
e17a4113 | 1318 | store_unsigned_integer (valbuf, len, byte_order, c); |
3116c80a | 1319 | } |
48db5a3c | 1320 | else if (len == 8) |
3116c80a | 1321 | { |
48db5a3c CV |
1322 | int i, regnum = R0_REGNUM; |
1323 | for (i = 0; i < len; i += 4) | |
948f8e3d | 1324 | regcache_raw_read (regcache, regnum++, valbuf + i); |
3116c80a EZ |
1325 | } |
1326 | else | |
8a3fe4f8 | 1327 | error (_("bad size for return value")); |
3116c80a EZ |
1328 | } |
1329 | ||
1330 | static void | |
3ffc5b9b | 1331 | sh_extract_return_value_fpu (struct type *type, struct regcache *regcache, |
948f8e3d | 1332 | gdb_byte *valbuf) |
3116c80a | 1333 | { |
d93859e2 | 1334 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
afce3d2a | 1335 | if (sh_treat_as_flt_p (type)) |
3116c80a | 1336 | { |
48db5a3c | 1337 | int len = TYPE_LENGTH (type); |
d93859e2 | 1338 | int i, regnum = gdbarch_fp0_regnum (gdbarch); |
48db5a3c | 1339 | for (i = 0; i < len; i += 4) |
d93859e2 | 1340 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) |
c378eb4e | 1341 | regcache_raw_read (regcache, regnum++, |
948f8e3d | 1342 | valbuf + len - 4 - i); |
2e952408 | 1343 | else |
948f8e3d | 1344 | regcache_raw_read (regcache, regnum++, valbuf + i); |
3116c80a | 1345 | } |
cc17453a | 1346 | else |
3ffc5b9b | 1347 | sh_extract_return_value_nofpu (type, regcache, valbuf); |
cc17453a | 1348 | } |
c906108c | 1349 | |
cc17453a EZ |
1350 | /* Write into appropriate registers a function return value |
1351 | of type TYPE, given in virtual format. | |
1352 | If the architecture is sh4 or sh3e, store a function's return value | |
1353 | in the R0 general register or in the FP0 floating point register, | |
c378eb4e MS |
1354 | depending on the type of the return value. In all the other cases |
1355 | the result is stored in r0, left-justified. */ | |
cc17453a | 1356 | static void |
3ffc5b9b | 1357 | sh_store_return_value_nofpu (struct type *type, struct regcache *regcache, |
948f8e3d | 1358 | const gdb_byte *valbuf) |
cc17453a | 1359 | { |
e17a4113 UW |
1360 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
1361 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
48db5a3c CV |
1362 | ULONGEST val; |
1363 | int len = TYPE_LENGTH (type); | |
d19b71be | 1364 | |
48db5a3c | 1365 | if (len <= 4) |
d19b71be | 1366 | { |
e17a4113 | 1367 | val = extract_unsigned_integer (valbuf, len, byte_order); |
48db5a3c | 1368 | regcache_cooked_write_unsigned (regcache, R0_REGNUM, val); |
d19b71be MS |
1369 | } |
1370 | else | |
48db5a3c CV |
1371 | { |
1372 | int i, regnum = R0_REGNUM; | |
1373 | for (i = 0; i < len; i += 4) | |
948f8e3d | 1374 | regcache_raw_write (regcache, regnum++, valbuf + i); |
48db5a3c | 1375 | } |
cc17453a | 1376 | } |
c906108c | 1377 | |
cc17453a | 1378 | static void |
3ffc5b9b | 1379 | sh_store_return_value_fpu (struct type *type, struct regcache *regcache, |
948f8e3d | 1380 | const gdb_byte *valbuf) |
cc17453a | 1381 | { |
d93859e2 | 1382 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
afce3d2a | 1383 | if (sh_treat_as_flt_p (type)) |
48db5a3c CV |
1384 | { |
1385 | int len = TYPE_LENGTH (type); | |
d93859e2 | 1386 | int i, regnum = gdbarch_fp0_regnum (gdbarch); |
48db5a3c | 1387 | for (i = 0; i < len; i += 4) |
d93859e2 | 1388 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) |
c8a3b559 | 1389 | regcache_raw_write (regcache, regnum++, |
948f8e3d | 1390 | valbuf + len - 4 - i); |
c8a3b559 | 1391 | else |
948f8e3d | 1392 | regcache_raw_write (regcache, regnum++, valbuf + i); |
48db5a3c | 1393 | } |
cc17453a | 1394 | else |
3ffc5b9b | 1395 | sh_store_return_value_nofpu (type, regcache, valbuf); |
c906108c SS |
1396 | } |
1397 | ||
c0409442 | 1398 | static enum return_value_convention |
6a3a010b | 1399 | sh_return_value_nofpu (struct gdbarch *gdbarch, struct value *function, |
c055b101 | 1400 | struct type *type, struct regcache *regcache, |
18cf8b5b | 1401 | gdb_byte *readbuf, const gdb_byte *writebuf) |
c0409442 | 1402 | { |
6a3a010b MR |
1403 | struct type *func_type = function ? value_type (function) : NULL; |
1404 | ||
c055b101 CV |
1405 | if (sh_use_struct_convention_nofpu ( |
1406 | sh_is_renesas_calling_convention (func_type), type)) | |
c0409442 CV |
1407 | return RETURN_VALUE_STRUCT_CONVENTION; |
1408 | if (writebuf) | |
3ffc5b9b | 1409 | sh_store_return_value_nofpu (type, regcache, writebuf); |
c0409442 | 1410 | else if (readbuf) |
3ffc5b9b | 1411 | sh_extract_return_value_nofpu (type, regcache, readbuf); |
c0409442 CV |
1412 | return RETURN_VALUE_REGISTER_CONVENTION; |
1413 | } | |
1414 | ||
1415 | static enum return_value_convention | |
6a3a010b | 1416 | sh_return_value_fpu (struct gdbarch *gdbarch, struct value *function, |
c055b101 | 1417 | struct type *type, struct regcache *regcache, |
18cf8b5b | 1418 | gdb_byte *readbuf, const gdb_byte *writebuf) |
c0409442 | 1419 | { |
6a3a010b MR |
1420 | struct type *func_type = function ? value_type (function) : NULL; |
1421 | ||
c055b101 CV |
1422 | if (sh_use_struct_convention ( |
1423 | sh_is_renesas_calling_convention (func_type), type)) | |
c0409442 CV |
1424 | return RETURN_VALUE_STRUCT_CONVENTION; |
1425 | if (writebuf) | |
3ffc5b9b | 1426 | sh_store_return_value_fpu (type, regcache, writebuf); |
c0409442 | 1427 | else if (readbuf) |
3ffc5b9b | 1428 | sh_extract_return_value_fpu (type, regcache, readbuf); |
c0409442 CV |
1429 | return RETURN_VALUE_REGISTER_CONVENTION; |
1430 | } | |
1431 | ||
da962468 CV |
1432 | static struct type * |
1433 | sh_sh2a_register_type (struct gdbarch *gdbarch, int reg_nr) | |
1434 | { | |
b47193f7 | 1435 | if ((reg_nr >= gdbarch_fp0_regnum (gdbarch) |
da962468 | 1436 | && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM)) |
0dfff4cb | 1437 | return builtin_type (gdbarch)->builtin_float; |
da962468 | 1438 | else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM) |
0dfff4cb | 1439 | return builtin_type (gdbarch)->builtin_double; |
da962468 | 1440 | else |
0dfff4cb | 1441 | return builtin_type (gdbarch)->builtin_int; |
da962468 CV |
1442 | } |
1443 | ||
cc17453a EZ |
1444 | /* Return the GDB type object for the "standard" data type |
1445 | of data in register N. */ | |
cc17453a | 1446 | static struct type * |
48db5a3c | 1447 | sh_sh3e_register_type (struct gdbarch *gdbarch, int reg_nr) |
cc17453a | 1448 | { |
b47193f7 | 1449 | if ((reg_nr >= gdbarch_fp0_regnum (gdbarch) |
617daa0e | 1450 | && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM)) |
0dfff4cb | 1451 | return builtin_type (gdbarch)->builtin_float; |
8db62801 | 1452 | else |
0dfff4cb | 1453 | return builtin_type (gdbarch)->builtin_int; |
cc17453a EZ |
1454 | } |
1455 | ||
7f4dbe94 | 1456 | static struct type * |
0dfff4cb | 1457 | sh_sh4_build_float_register_type (struct gdbarch *gdbarch, int high) |
7f4dbe94 | 1458 | { |
e3506a9f UW |
1459 | return lookup_array_range_type (builtin_type (gdbarch)->builtin_float, |
1460 | 0, high); | |
7f4dbe94 EZ |
1461 | } |
1462 | ||
53116e27 | 1463 | static struct type * |
48db5a3c | 1464 | sh_sh4_register_type (struct gdbarch *gdbarch, int reg_nr) |
53116e27 | 1465 | { |
b47193f7 | 1466 | if ((reg_nr >= gdbarch_fp0_regnum (gdbarch) |
617daa0e | 1467 | && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM)) |
0dfff4cb | 1468 | return builtin_type (gdbarch)->builtin_float; |
617daa0e | 1469 | else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM) |
0dfff4cb | 1470 | return builtin_type (gdbarch)->builtin_double; |
617daa0e | 1471 | else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM) |
0dfff4cb | 1472 | return sh_sh4_build_float_register_type (gdbarch, 3); |
53116e27 | 1473 | else |
0dfff4cb | 1474 | return builtin_type (gdbarch)->builtin_int; |
53116e27 EZ |
1475 | } |
1476 | ||
cc17453a | 1477 | static struct type * |
48db5a3c | 1478 | sh_default_register_type (struct gdbarch *gdbarch, int reg_nr) |
cc17453a | 1479 | { |
0dfff4cb | 1480 | return builtin_type (gdbarch)->builtin_int; |
cc17453a EZ |
1481 | } |
1482 | ||
dda63807 AS |
1483 | /* Is a register in a reggroup? |
1484 | The default code in reggroup.c doesn't identify system registers, some | |
1485 | float registers or any of the vector registers. | |
1486 | TODO: sh2a and dsp registers. */ | |
63807e1d | 1487 | static int |
dda63807 AS |
1488 | sh_register_reggroup_p (struct gdbarch *gdbarch, int regnum, |
1489 | struct reggroup *reggroup) | |
1490 | { | |
b47193f7 UW |
1491 | if (gdbarch_register_name (gdbarch, regnum) == NULL |
1492 | || *gdbarch_register_name (gdbarch, regnum) == '\0') | |
dda63807 AS |
1493 | return 0; |
1494 | ||
1495 | if (reggroup == float_reggroup | |
1496 | && (regnum == FPUL_REGNUM | |
1497 | || regnum == FPSCR_REGNUM)) | |
1498 | return 1; | |
1499 | ||
1500 | if (regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM) | |
1501 | { | |
1502 | if (reggroup == vector_reggroup || reggroup == float_reggroup) | |
1503 | return 1; | |
1504 | if (reggroup == general_reggroup) | |
1505 | return 0; | |
1506 | } | |
1507 | ||
1508 | if (regnum == VBR_REGNUM | |
1509 | || regnum == SR_REGNUM | |
1510 | || regnum == FPSCR_REGNUM | |
1511 | || regnum == SSR_REGNUM | |
1512 | || regnum == SPC_REGNUM) | |
1513 | { | |
1514 | if (reggroup == system_reggroup) | |
1515 | return 1; | |
1516 | if (reggroup == general_reggroup) | |
1517 | return 0; | |
1518 | } | |
1519 | ||
1520 | /* The default code can cope with any other registers. */ | |
1521 | return default_register_reggroup_p (gdbarch, regnum, reggroup); | |
1522 | } | |
1523 | ||
fb409745 | 1524 | /* On the sh4, the DRi pseudo registers are problematic if the target |
c378eb4e | 1525 | is little endian. When the user writes one of those registers, for |
a6521d9a | 1526 | instance with 'set var $dr0=1', we want the double to be stored |
fb409745 | 1527 | like this: |
a6521d9a TS |
1528 | fr0 = 0x00 0x00 0xf0 0x3f |
1529 | fr1 = 0x00 0x00 0x00 0x00 | |
fb409745 EZ |
1530 | |
1531 | This corresponds to little endian byte order & big endian word | |
1532 | order. However if we let gdb write the register w/o conversion, it | |
1533 | will write fr0 and fr1 this way: | |
a6521d9a TS |
1534 | fr0 = 0x00 0x00 0x00 0x00 |
1535 | fr1 = 0x00 0x00 0xf0 0x3f | |
fb409745 EZ |
1536 | because it will consider fr0 and fr1 as a single LE stretch of memory. |
1537 | ||
1538 | To achieve what we want we must force gdb to store things in | |
1539 | floatformat_ieee_double_littlebyte_bigword (which is defined in | |
1540 | include/floatformat.h and libiberty/floatformat.c. | |
1541 | ||
1542 | In case the target is big endian, there is no problem, the | |
1543 | raw bytes will look like: | |
a6521d9a TS |
1544 | fr0 = 0x3f 0xf0 0x00 0x00 |
1545 | fr1 = 0x00 0x00 0x00 0x00 | |
fb409745 EZ |
1546 | |
1547 | The other pseudo registers (the FVs) also don't pose a problem | |
c378eb4e | 1548 | because they are stored as 4 individual FP elements. */ |
fb409745 | 1549 | |
7bd872fe | 1550 | static void |
a6521d9a | 1551 | sh_register_convert_to_virtual (struct gdbarch *gdbarch, int regnum, |
948f8e3d | 1552 | struct type *type, gdb_byte *from, gdb_byte *to) |
55ff77ac | 1553 | { |
a6521d9a TS |
1554 | if (gdbarch_byte_order (gdbarch) != BFD_ENDIAN_LITTLE) |
1555 | { | |
1556 | /* It is a no-op. */ | |
1557 | memcpy (to, from, register_size (gdbarch, regnum)); | |
1558 | return; | |
1559 | } | |
1560 | ||
617daa0e | 1561 | if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM) |
283150cd EZ |
1562 | { |
1563 | DOUBLEST val; | |
617daa0e CV |
1564 | floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, |
1565 | from, &val); | |
55ff77ac | 1566 | store_typed_floating (to, type, val); |
283150cd EZ |
1567 | } |
1568 | else | |
617daa0e CV |
1569 | error |
1570 | ("sh_register_convert_to_virtual called with non DR register number"); | |
283150cd EZ |
1571 | } |
1572 | ||
1573 | static void | |
a6521d9a | 1574 | sh_register_convert_to_raw (struct gdbarch *gdbarch, struct type *type, |
948f8e3d | 1575 | int regnum, const gdb_byte *from, gdb_byte *to) |
283150cd | 1576 | { |
a6521d9a TS |
1577 | if (gdbarch_byte_order (gdbarch) != BFD_ENDIAN_LITTLE) |
1578 | { | |
1579 | /* It is a no-op. */ | |
1580 | memcpy (to, from, register_size (gdbarch, regnum)); | |
1581 | return; | |
1582 | } | |
1583 | ||
617daa0e | 1584 | if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM) |
283150cd | 1585 | { |
48db5a3c | 1586 | DOUBLEST val = extract_typed_floating (from, type); |
617daa0e CV |
1587 | floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword, |
1588 | &val, to); | |
283150cd EZ |
1589 | } |
1590 | else | |
8a3fe4f8 | 1591 | error (_("sh_register_convert_to_raw called with non DR register number")); |
283150cd EZ |
1592 | } |
1593 | ||
c378eb4e | 1594 | /* For vectors of 4 floating point registers. */ |
1c0159e0 | 1595 | static int |
d93859e2 | 1596 | fv_reg_base_num (struct gdbarch *gdbarch, int fv_regnum) |
1c0159e0 CV |
1597 | { |
1598 | int fp_regnum; | |
1599 | ||
d93859e2 | 1600 | fp_regnum = gdbarch_fp0_regnum (gdbarch) |
3e8c568d | 1601 | + (fv_regnum - FV0_REGNUM) * 4; |
1c0159e0 CV |
1602 | return fp_regnum; |
1603 | } | |
1604 | ||
c378eb4e | 1605 | /* For double precision floating point registers, i.e 2 fp regs. */ |
1c0159e0 | 1606 | static int |
d93859e2 | 1607 | dr_reg_base_num (struct gdbarch *gdbarch, int dr_regnum) |
1c0159e0 CV |
1608 | { |
1609 | int fp_regnum; | |
1610 | ||
d93859e2 | 1611 | fp_regnum = gdbarch_fp0_regnum (gdbarch) |
3e8c568d | 1612 | + (dr_regnum - DR0_REGNUM) * 2; |
1c0159e0 CV |
1613 | return fp_regnum; |
1614 | } | |
1615 | ||
05d1431c PA |
1616 | /* Concatenate PORTIONS contiguous raw registers starting at |
1617 | BASE_REGNUM into BUFFER. */ | |
1618 | ||
1619 | static enum register_status | |
1620 | pseudo_register_read_portions (struct gdbarch *gdbarch, | |
1621 | struct regcache *regcache, | |
1622 | int portions, | |
1623 | int base_regnum, gdb_byte *buffer) | |
1624 | { | |
1625 | int portion; | |
1626 | ||
1627 | for (portion = 0; portion < portions; portion++) | |
1628 | { | |
1629 | enum register_status status; | |
1630 | gdb_byte *b; | |
1631 | ||
1632 | b = buffer + register_size (gdbarch, base_regnum) * portion; | |
1633 | status = regcache_raw_read (regcache, base_regnum + portion, b); | |
1634 | if (status != REG_VALID) | |
1635 | return status; | |
1636 | } | |
1637 | ||
1638 | return REG_VALID; | |
1639 | } | |
1640 | ||
1641 | static enum register_status | |
d8124050 | 1642 | sh_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, |
18cf8b5b | 1643 | int reg_nr, gdb_byte *buffer) |
53116e27 | 1644 | { |
05d1431c | 1645 | int base_regnum; |
948f8e3d | 1646 | gdb_byte temp_buffer[MAX_REGISTER_SIZE]; |
05d1431c | 1647 | enum register_status status; |
53116e27 | 1648 | |
9bed62d7 | 1649 | if (reg_nr == PSEUDO_BANK_REGNUM) |
05d1431c PA |
1650 | return regcache_raw_read (regcache, BANK_REGNUM, buffer); |
1651 | else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM) | |
7bd872fe | 1652 | { |
d93859e2 | 1653 | base_regnum = dr_reg_base_num (gdbarch, reg_nr); |
7bd872fe | 1654 | |
c378eb4e | 1655 | /* Build the value in the provided buffer. */ |
7bd872fe | 1656 | /* Read the real regs for which this one is an alias. */ |
05d1431c PA |
1657 | status = pseudo_register_read_portions (gdbarch, regcache, |
1658 | 2, base_regnum, temp_buffer); | |
1659 | if (status == REG_VALID) | |
1660 | { | |
1661 | /* We must pay attention to the endiannes. */ | |
a6521d9a | 1662 | sh_register_convert_to_virtual (gdbarch, reg_nr, |
05d1431c PA |
1663 | register_type (gdbarch, reg_nr), |
1664 | temp_buffer, buffer); | |
1665 | } | |
1666 | return status; | |
7bd872fe | 1667 | } |
617daa0e | 1668 | else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM) |
53116e27 | 1669 | { |
d93859e2 | 1670 | base_regnum = fv_reg_base_num (gdbarch, reg_nr); |
7bd872fe EZ |
1671 | |
1672 | /* Read the real regs for which this one is an alias. */ | |
05d1431c PA |
1673 | return pseudo_register_read_portions (gdbarch, regcache, |
1674 | 4, base_regnum, buffer); | |
53116e27 | 1675 | } |
05d1431c PA |
1676 | else |
1677 | gdb_assert_not_reached ("invalid pseudo register number"); | |
53116e27 EZ |
1678 | } |
1679 | ||
a78f21af | 1680 | static void |
d8124050 | 1681 | sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, |
18cf8b5b | 1682 | int reg_nr, const gdb_byte *buffer) |
53116e27 EZ |
1683 | { |
1684 | int base_regnum, portion; | |
948f8e3d | 1685 | gdb_byte temp_buffer[MAX_REGISTER_SIZE]; |
53116e27 | 1686 | |
9bed62d7 CV |
1687 | if (reg_nr == PSEUDO_BANK_REGNUM) |
1688 | { | |
1689 | /* When the bank register is written to, the whole register bank | |
1690 | is switched and all values in the bank registers must be read | |
c378eb4e | 1691 | from the target/sim again. We're just invalidating the regcache |
9bed62d7 CV |
1692 | so that a re-read happens next time it's necessary. */ |
1693 | int bregnum; | |
1694 | ||
1695 | regcache_raw_write (regcache, BANK_REGNUM, buffer); | |
1696 | for (bregnum = R0_BANK0_REGNUM; bregnum < MACLB_REGNUM; ++bregnum) | |
9c5ea4d9 | 1697 | regcache_invalidate (regcache, bregnum); |
9bed62d7 CV |
1698 | } |
1699 | else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM) | |
53116e27 | 1700 | { |
d93859e2 | 1701 | base_regnum = dr_reg_base_num (gdbarch, reg_nr); |
53116e27 | 1702 | |
c378eb4e | 1703 | /* We must pay attention to the endiannes. */ |
a6521d9a | 1704 | sh_register_convert_to_raw (gdbarch, register_type (gdbarch, reg_nr), |
b66ba949 | 1705 | reg_nr, buffer, temp_buffer); |
7bd872fe | 1706 | |
53116e27 EZ |
1707 | /* Write the real regs for which this one is an alias. */ |
1708 | for (portion = 0; portion < 2; portion++) | |
617daa0e | 1709 | regcache_raw_write (regcache, base_regnum + portion, |
0818c12a | 1710 | (temp_buffer |
617daa0e CV |
1711 | + register_size (gdbarch, |
1712 | base_regnum) * portion)); | |
53116e27 | 1713 | } |
617daa0e | 1714 | else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM) |
53116e27 | 1715 | { |
d93859e2 | 1716 | base_regnum = fv_reg_base_num (gdbarch, reg_nr); |
53116e27 EZ |
1717 | |
1718 | /* Write the real regs for which this one is an alias. */ | |
1719 | for (portion = 0; portion < 4; portion++) | |
d8124050 | 1720 | regcache_raw_write (regcache, base_regnum + portion, |
948f8e3d | 1721 | (buffer |
617daa0e CV |
1722 | + register_size (gdbarch, |
1723 | base_regnum) * portion)); | |
53116e27 EZ |
1724 | } |
1725 | } | |
1726 | ||
2f14585c | 1727 | static int |
e7faf938 | 1728 | sh_dsp_register_sim_regno (struct gdbarch *gdbarch, int nr) |
2f14585c | 1729 | { |
e7faf938 MD |
1730 | if (legacy_register_sim_regno (gdbarch, nr) < 0) |
1731 | return legacy_register_sim_regno (gdbarch, nr); | |
f2ea0907 CV |
1732 | if (nr >= DSR_REGNUM && nr <= Y1_REGNUM) |
1733 | return nr - DSR_REGNUM + SIM_SH_DSR_REGNUM; | |
1734 | if (nr == MOD_REGNUM) | |
2f14585c | 1735 | return SIM_SH_MOD_REGNUM; |
f2ea0907 | 1736 | if (nr == RS_REGNUM) |
2f14585c | 1737 | return SIM_SH_RS_REGNUM; |
f2ea0907 | 1738 | if (nr == RE_REGNUM) |
2f14585c | 1739 | return SIM_SH_RE_REGNUM; |
76cd2bd9 CV |
1740 | if (nr >= DSP_R0_BANK_REGNUM && nr <= DSP_R7_BANK_REGNUM) |
1741 | return nr - DSP_R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM; | |
2f14585c JR |
1742 | return nr; |
1743 | } | |
1c0159e0 | 1744 | |
da962468 | 1745 | static int |
e7faf938 | 1746 | sh_sh2a_register_sim_regno (struct gdbarch *gdbarch, int nr) |
da962468 CV |
1747 | { |
1748 | switch (nr) | |
1749 | { | |
1750 | case TBR_REGNUM: | |
1751 | return SIM_SH_TBR_REGNUM; | |
1752 | case IBNR_REGNUM: | |
1753 | return SIM_SH_IBNR_REGNUM; | |
1754 | case IBCR_REGNUM: | |
1755 | return SIM_SH_IBCR_REGNUM; | |
1756 | case BANK_REGNUM: | |
1757 | return SIM_SH_BANK_REGNUM; | |
1758 | case MACLB_REGNUM: | |
1759 | return SIM_SH_BANK_MACL_REGNUM; | |
1760 | case GBRB_REGNUM: | |
1761 | return SIM_SH_BANK_GBR_REGNUM; | |
1762 | case PRB_REGNUM: | |
1763 | return SIM_SH_BANK_PR_REGNUM; | |
1764 | case IVNB_REGNUM: | |
1765 | return SIM_SH_BANK_IVN_REGNUM; | |
1766 | case MACHB_REGNUM: | |
1767 | return SIM_SH_BANK_MACH_REGNUM; | |
1768 | default: | |
1769 | break; | |
1770 | } | |
e7faf938 | 1771 | return legacy_register_sim_regno (gdbarch, nr); |
da962468 CV |
1772 | } |
1773 | ||
357d3800 AS |
1774 | /* Set up the register unwinding such that call-clobbered registers are |
1775 | not displayed in frames >0 because the true value is not certain. | |
1776 | The 'undefined' registers will show up as 'not available' unless the | |
1777 | CFI says otherwise. | |
1778 | ||
1779 | This function is currently set up for SH4 and compatible only. */ | |
1780 | ||
1781 | static void | |
1782 | sh_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
aff37fc1 | 1783 | struct dwarf2_frame_state_reg *reg, |
4a4e5149 | 1784 | struct frame_info *this_frame) |
357d3800 AS |
1785 | { |
1786 | /* Mark the PC as the destination for the return address. */ | |
b47193f7 | 1787 | if (regnum == gdbarch_pc_regnum (gdbarch)) |
357d3800 AS |
1788 | reg->how = DWARF2_FRAME_REG_RA; |
1789 | ||
1790 | /* Mark the stack pointer as the call frame address. */ | |
b47193f7 | 1791 | else if (regnum == gdbarch_sp_regnum (gdbarch)) |
357d3800 AS |
1792 | reg->how = DWARF2_FRAME_REG_CFA; |
1793 | ||
1794 | /* The above was taken from the default init_reg in dwarf2-frame.c | |
1795 | while the below is SH specific. */ | |
1796 | ||
1797 | /* Caller save registers. */ | |
1798 | else if ((regnum >= R0_REGNUM && regnum <= R0_REGNUM+7) | |
1799 | || (regnum >= FR0_REGNUM && regnum <= FR0_REGNUM+11) | |
1800 | || (regnum >= DR0_REGNUM && regnum <= DR0_REGNUM+5) | |
1801 | || (regnum >= FV0_REGNUM && regnum <= FV0_REGNUM+2) | |
1802 | || (regnum == MACH_REGNUM) | |
1803 | || (regnum == MACL_REGNUM) | |
1804 | || (regnum == FPUL_REGNUM) | |
1805 | || (regnum == SR_REGNUM)) | |
1806 | reg->how = DWARF2_FRAME_REG_UNDEFINED; | |
1807 | ||
1808 | /* Callee save registers. */ | |
1809 | else if ((regnum >= R0_REGNUM+8 && regnum <= R0_REGNUM+15) | |
1810 | || (regnum >= FR0_REGNUM+12 && regnum <= FR0_REGNUM+15) | |
1811 | || (regnum >= DR0_REGNUM+6 && regnum <= DR0_REGNUM+8) | |
1812 | || (regnum == FV0_REGNUM+3)) | |
1813 | reg->how = DWARF2_FRAME_REG_SAME_VALUE; | |
1814 | ||
1815 | /* Other registers. These are not in the ABI and may or may not | |
1816 | mean anything in frames >0 so don't show them. */ | |
1817 | else if ((regnum >= R0_BANK0_REGNUM && regnum <= R0_BANK0_REGNUM+15) | |
1818 | || (regnum == GBR_REGNUM) | |
1819 | || (regnum == VBR_REGNUM) | |
1820 | || (regnum == FPSCR_REGNUM) | |
1821 | || (regnum == SSR_REGNUM) | |
1822 | || (regnum == SPC_REGNUM)) | |
1823 | reg->how = DWARF2_FRAME_REG_UNDEFINED; | |
1824 | } | |
1825 | ||
1c0159e0 CV |
1826 | static struct sh_frame_cache * |
1827 | sh_alloc_frame_cache (void) | |
1828 | { | |
1829 | struct sh_frame_cache *cache; | |
1830 | int i; | |
1831 | ||
1832 | cache = FRAME_OBSTACK_ZALLOC (struct sh_frame_cache); | |
1833 | ||
1834 | /* Base address. */ | |
1835 | cache->base = 0; | |
1836 | cache->saved_sp = 0; | |
1837 | cache->sp_offset = 0; | |
1838 | cache->pc = 0; | |
1839 | ||
1840 | /* Frameless until proven otherwise. */ | |
1841 | cache->uses_fp = 0; | |
617daa0e | 1842 | |
1c0159e0 CV |
1843 | /* Saved registers. We initialize these to -1 since zero is a valid |
1844 | offset (that's where fp is supposed to be stored). */ | |
1845 | for (i = 0; i < SH_NUM_REGS; i++) | |
1846 | { | |
1847 | cache->saved_regs[i] = -1; | |
1848 | } | |
617daa0e | 1849 | |
1c0159e0 | 1850 | return cache; |
617daa0e | 1851 | } |
1c0159e0 CV |
1852 | |
1853 | static struct sh_frame_cache * | |
94afd7a6 | 1854 | sh_frame_cache (struct frame_info *this_frame, void **this_cache) |
1c0159e0 | 1855 | { |
e17a4113 | 1856 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1c0159e0 CV |
1857 | struct sh_frame_cache *cache; |
1858 | CORE_ADDR current_pc; | |
1859 | int i; | |
1860 | ||
1861 | if (*this_cache) | |
1862 | return *this_cache; | |
1863 | ||
1864 | cache = sh_alloc_frame_cache (); | |
1865 | *this_cache = cache; | |
1866 | ||
1867 | /* In principle, for normal frames, fp holds the frame pointer, | |
1868 | which holds the base address for the current stack frame. | |
1869 | However, for functions that don't need it, the frame pointer is | |
1870 | optional. For these "frameless" functions the frame pointer is | |
c378eb4e | 1871 | actually the frame pointer of the calling frame. */ |
94afd7a6 | 1872 | cache->base = get_frame_register_unsigned (this_frame, FP_REGNUM); |
1c0159e0 CV |
1873 | if (cache->base == 0) |
1874 | return cache; | |
1875 | ||
94afd7a6 UW |
1876 | cache->pc = get_frame_func (this_frame); |
1877 | current_pc = get_frame_pc (this_frame); | |
1c0159e0 | 1878 | if (cache->pc != 0) |
d2ca4222 UW |
1879 | { |
1880 | ULONGEST fpscr; | |
9fc05685 KB |
1881 | |
1882 | /* Check for the existence of the FPSCR register. If it exists, | |
1883 | fetch its value for use in prologue analysis. Passing a zero | |
1884 | value is the best choice for architecture variants upon which | |
1885 | there's no FPSCR register. */ | |
1886 | if (gdbarch_register_reggroup_p (gdbarch, FPSCR_REGNUM, all_reggroup)) | |
1887 | fpscr = get_frame_register_unsigned (this_frame, FPSCR_REGNUM); | |
1888 | else | |
1889 | fpscr = 0; | |
1890 | ||
e17a4113 | 1891 | sh_analyze_prologue (gdbarch, cache->pc, current_pc, cache, fpscr); |
d2ca4222 | 1892 | } |
617daa0e | 1893 | |
1c0159e0 CV |
1894 | if (!cache->uses_fp) |
1895 | { | |
1896 | /* We didn't find a valid frame, which means that CACHE->base | |
1897 | currently holds the frame pointer for our calling frame. If | |
1898 | we're at the start of a function, or somewhere half-way its | |
1899 | prologue, the function's frame probably hasn't been fully | |
1900 | setup yet. Try to reconstruct the base address for the stack | |
1901 | frame by looking at the stack pointer. For truly "frameless" | |
1902 | functions this might work too. */ | |
94afd7a6 | 1903 | cache->base = get_frame_register_unsigned |
e17a4113 | 1904 | (this_frame, gdbarch_sp_regnum (gdbarch)); |
1c0159e0 CV |
1905 | } |
1906 | ||
1907 | /* Now that we have the base address for the stack frame we can | |
1908 | calculate the value of sp in the calling frame. */ | |
1909 | cache->saved_sp = cache->base + cache->sp_offset; | |
1910 | ||
1911 | /* Adjust all the saved registers such that they contain addresses | |
1912 | instead of offsets. */ | |
1913 | for (i = 0; i < SH_NUM_REGS; i++) | |
1914 | if (cache->saved_regs[i] != -1) | |
1915 | cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i] - 4; | |
1916 | ||
1917 | return cache; | |
1918 | } | |
1919 | ||
94afd7a6 UW |
1920 | static struct value * |
1921 | sh_frame_prev_register (struct frame_info *this_frame, | |
1922 | void **this_cache, int regnum) | |
1c0159e0 | 1923 | { |
94afd7a6 UW |
1924 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1925 | struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache); | |
1c0159e0 CV |
1926 | |
1927 | gdb_assert (regnum >= 0); | |
1928 | ||
b47193f7 | 1929 | if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp) |
94afd7a6 | 1930 | return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp); |
1c0159e0 CV |
1931 | |
1932 | /* The PC of the previous frame is stored in the PR register of | |
1933 | the current frame. Frob regnum so that we pull the value from | |
1934 | the correct place. */ | |
b47193f7 | 1935 | if (regnum == gdbarch_pc_regnum (gdbarch)) |
1c0159e0 CV |
1936 | regnum = PR_REGNUM; |
1937 | ||
1938 | if (regnum < SH_NUM_REGS && cache->saved_regs[regnum] != -1) | |
94afd7a6 UW |
1939 | return frame_unwind_got_memory (this_frame, regnum, |
1940 | cache->saved_regs[regnum]); | |
1c0159e0 | 1941 | |
94afd7a6 | 1942 | return frame_unwind_got_register (this_frame, regnum, regnum); |
1c0159e0 CV |
1943 | } |
1944 | ||
1945 | static void | |
94afd7a6 | 1946 | sh_frame_this_id (struct frame_info *this_frame, void **this_cache, |
617daa0e CV |
1947 | struct frame_id *this_id) |
1948 | { | |
94afd7a6 | 1949 | struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache); |
1c0159e0 CV |
1950 | |
1951 | /* This marks the outermost frame. */ | |
1952 | if (cache->base == 0) | |
1953 | return; | |
1954 | ||
1955 | *this_id = frame_id_build (cache->saved_sp, cache->pc); | |
617daa0e | 1956 | } |
1c0159e0 | 1957 | |
617daa0e | 1958 | static const struct frame_unwind sh_frame_unwind = { |
1c0159e0 | 1959 | NORMAL_FRAME, |
8fbca658 | 1960 | default_frame_unwind_stop_reason, |
1c0159e0 | 1961 | sh_frame_this_id, |
94afd7a6 UW |
1962 | sh_frame_prev_register, |
1963 | NULL, | |
1964 | default_frame_sniffer | |
1c0159e0 CV |
1965 | }; |
1966 | ||
1c0159e0 CV |
1967 | static CORE_ADDR |
1968 | sh_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1969 | { | |
3e8c568d | 1970 | return frame_unwind_register_unsigned (next_frame, |
b47193f7 | 1971 | gdbarch_sp_regnum (gdbarch)); |
1c0159e0 CV |
1972 | } |
1973 | ||
1974 | static CORE_ADDR | |
1975 | sh_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1976 | { | |
3e8c568d | 1977 | return frame_unwind_register_unsigned (next_frame, |
b47193f7 | 1978 | gdbarch_pc_regnum (gdbarch)); |
1c0159e0 CV |
1979 | } |
1980 | ||
1981 | static struct frame_id | |
94afd7a6 | 1982 | sh_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
1c0159e0 | 1983 | { |
94afd7a6 UW |
1984 | CORE_ADDR sp = get_frame_register_unsigned (this_frame, |
1985 | gdbarch_sp_regnum (gdbarch)); | |
1986 | return frame_id_build (sp, get_frame_pc (this_frame)); | |
1c0159e0 CV |
1987 | } |
1988 | ||
1989 | static CORE_ADDR | |
94afd7a6 | 1990 | sh_frame_base_address (struct frame_info *this_frame, void **this_cache) |
617daa0e | 1991 | { |
94afd7a6 | 1992 | struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache); |
617daa0e | 1993 | |
1c0159e0 CV |
1994 | return cache->base; |
1995 | } | |
617daa0e CV |
1996 | |
1997 | static const struct frame_base sh_frame_base = { | |
1c0159e0 CV |
1998 | &sh_frame_unwind, |
1999 | sh_frame_base_address, | |
2000 | sh_frame_base_address, | |
2001 | sh_frame_base_address | |
617daa0e | 2002 | }; |
1c0159e0 | 2003 | |
cb2cf4ce TS |
2004 | static struct sh_frame_cache * |
2005 | sh_make_stub_cache (struct frame_info *this_frame) | |
2006 | { | |
2007 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2008 | struct sh_frame_cache *cache; | |
2009 | ||
2010 | cache = sh_alloc_frame_cache (); | |
2011 | ||
2012 | cache->saved_sp | |
2013 | = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch)); | |
2014 | ||
2015 | return cache; | |
2016 | } | |
2017 | ||
2018 | static void | |
2019 | sh_stub_this_id (struct frame_info *this_frame, void **this_cache, | |
2020 | struct frame_id *this_id) | |
2021 | { | |
2022 | struct sh_frame_cache *cache; | |
2023 | ||
2024 | if (*this_cache == NULL) | |
2025 | *this_cache = sh_make_stub_cache (this_frame); | |
2026 | cache = *this_cache; | |
2027 | ||
2028 | *this_id = frame_id_build (cache->saved_sp, get_frame_pc (this_frame)); | |
2029 | } | |
2030 | ||
2031 | static int | |
2032 | sh_stub_unwind_sniffer (const struct frame_unwind *self, | |
2033 | struct frame_info *this_frame, | |
2034 | void **this_prologue_cache) | |
2035 | { | |
2036 | CORE_ADDR addr_in_block; | |
2037 | ||
2038 | addr_in_block = get_frame_address_in_block (this_frame); | |
3e5d3a5a | 2039 | if (in_plt_section (addr_in_block)) |
cb2cf4ce TS |
2040 | return 1; |
2041 | ||
2042 | return 0; | |
2043 | } | |
2044 | ||
2045 | static const struct frame_unwind sh_stub_unwind = | |
2046 | { | |
2047 | NORMAL_FRAME, | |
2048 | default_frame_unwind_stop_reason, | |
2049 | sh_stub_this_id, | |
2050 | sh_frame_prev_register, | |
2051 | NULL, | |
2052 | sh_stub_unwind_sniffer | |
2053 | }; | |
2054 | ||
1c0159e0 CV |
2055 | /* The epilogue is defined here as the area at the end of a function, |
2056 | either on the `ret' instruction itself or after an instruction which | |
c378eb4e | 2057 | destroys the function's stack frame. */ |
1c0159e0 CV |
2058 | static int |
2059 | sh_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
2060 | { | |
e17a4113 | 2061 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1c0159e0 CV |
2062 | CORE_ADDR func_addr = 0, func_end = 0; |
2063 | ||
2064 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
2065 | { | |
2066 | ULONGEST inst; | |
2067 | /* The sh epilogue is max. 14 bytes long. Give another 14 bytes | |
2068 | for a nop and some fixed data (e.g. big offsets) which are | |
617daa0e | 2069 | unfortunately also treated as part of the function (which |
c378eb4e | 2070 | means, they are below func_end. */ |
1c0159e0 CV |
2071 | CORE_ADDR addr = func_end - 28; |
2072 | if (addr < func_addr + 4) | |
617daa0e | 2073 | addr = func_addr + 4; |
1c0159e0 CV |
2074 | if (pc < addr) |
2075 | return 0; | |
2076 | ||
c378eb4e | 2077 | /* First search forward until hitting an rts. */ |
1c0159e0 | 2078 | while (addr < func_end |
e17a4113 | 2079 | && !IS_RTS (read_memory_unsigned_integer (addr, 2, byte_order))) |
1c0159e0 CV |
2080 | addr += 2; |
2081 | if (addr >= func_end) | |
617daa0e | 2082 | return 0; |
1c0159e0 CV |
2083 | |
2084 | /* At this point we should find a mov.l @r15+,r14 instruction, | |
2085 | either before or after the rts. If not, then the function has | |
c378eb4e | 2086 | probably no "normal" epilogue and we bail out here. */ |
e17a4113 UW |
2087 | inst = read_memory_unsigned_integer (addr - 2, 2, byte_order); |
2088 | if (IS_RESTORE_FP (read_memory_unsigned_integer (addr - 2, 2, | |
2089 | byte_order))) | |
617daa0e | 2090 | addr -= 2; |
e17a4113 UW |
2091 | else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr + 2, 2, |
2092 | byte_order))) | |
1c0159e0 CV |
2093 | return 0; |
2094 | ||
e17a4113 | 2095 | inst = read_memory_unsigned_integer (addr - 2, 2, byte_order); |
03131d99 | 2096 | |
c378eb4e | 2097 | /* Step over possible lds.l @r15+,macl. */ |
03131d99 CV |
2098 | if (IS_MACL_LDS (inst)) |
2099 | { | |
2100 | addr -= 2; | |
e17a4113 | 2101 | inst = read_memory_unsigned_integer (addr - 2, 2, byte_order); |
03131d99 CV |
2102 | } |
2103 | ||
c378eb4e | 2104 | /* Step over possible lds.l @r15+,pr. */ |
1c0159e0 | 2105 | if (IS_LDS (inst)) |
617daa0e | 2106 | { |
1c0159e0 | 2107 | addr -= 2; |
e17a4113 | 2108 | inst = read_memory_unsigned_integer (addr - 2, 2, byte_order); |
1c0159e0 CV |
2109 | } |
2110 | ||
c378eb4e | 2111 | /* Step over possible mov r14,r15. */ |
1c0159e0 | 2112 | if (IS_MOV_FP_SP (inst)) |
617daa0e | 2113 | { |
1c0159e0 | 2114 | addr -= 2; |
e17a4113 | 2115 | inst = read_memory_unsigned_integer (addr - 2, 2, byte_order); |
1c0159e0 CV |
2116 | } |
2117 | ||
2118 | /* Now check for FP adjustments, using add #imm,r14 or add rX, r14 | |
c378eb4e | 2119 | instructions. */ |
1c0159e0 | 2120 | while (addr > func_addr + 4 |
617daa0e | 2121 | && (IS_ADD_REG_TO_FP (inst) || IS_ADD_IMM_FP (inst))) |
1c0159e0 CV |
2122 | { |
2123 | addr -= 2; | |
e17a4113 | 2124 | inst = read_memory_unsigned_integer (addr - 2, 2, byte_order); |
1c0159e0 CV |
2125 | } |
2126 | ||
03131d99 CV |
2127 | /* On SH2a check if the previous instruction was perhaps a MOVI20. |
2128 | That's allowed for the epilogue. */ | |
2129 | if ((gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a | |
2130 | || gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a_nofpu) | |
2131 | && addr > func_addr + 6 | |
e17a4113 UW |
2132 | && IS_MOVI20 (read_memory_unsigned_integer (addr - 4, 2, |
2133 | byte_order))) | |
03131d99 CV |
2134 | addr -= 4; |
2135 | ||
1c0159e0 CV |
2136 | if (pc >= addr) |
2137 | return 1; | |
2138 | } | |
2139 | return 0; | |
2140 | } | |
c9ac0a72 AS |
2141 | |
2142 | ||
2143 | /* Supply register REGNUM from the buffer specified by REGS and LEN | |
2144 | in the register set REGSET to register cache REGCACHE. | |
2145 | REGTABLE specifies where each register can be found in REGS. | |
2146 | If REGNUM is -1, do this for all registers in REGSET. */ | |
2147 | ||
2148 | void | |
2149 | sh_corefile_supply_regset (const struct regset *regset, | |
2150 | struct regcache *regcache, | |
2151 | int regnum, const void *regs, size_t len) | |
2152 | { | |
2153 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
2154 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2155 | const struct sh_corefile_regmap *regmap = (regset == &sh_corefile_gregset | |
2156 | ? tdep->core_gregmap | |
2157 | : tdep->core_fpregmap); | |
2158 | int i; | |
2159 | ||
2160 | for (i = 0; regmap[i].regnum != -1; i++) | |
2161 | { | |
2162 | if ((regnum == -1 || regnum == regmap[i].regnum) | |
2163 | && regmap[i].offset + 4 <= len) | |
2164 | regcache_raw_supply (regcache, regmap[i].regnum, | |
2165 | (char *)regs + regmap[i].offset); | |
2166 | } | |
2167 | } | |
2168 | ||
2169 | /* Collect register REGNUM in the register set REGSET from register cache | |
2170 | REGCACHE into the buffer specified by REGS and LEN. | |
2171 | REGTABLE specifies where each register can be found in REGS. | |
2172 | If REGNUM is -1, do this for all registers in REGSET. */ | |
2173 | ||
2174 | void | |
2175 | sh_corefile_collect_regset (const struct regset *regset, | |
2176 | const struct regcache *regcache, | |
2177 | int regnum, void *regs, size_t len) | |
2178 | { | |
2179 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
2180 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2181 | const struct sh_corefile_regmap *regmap = (regset == &sh_corefile_gregset | |
2182 | ? tdep->core_gregmap | |
2183 | : tdep->core_fpregmap); | |
2184 | int i; | |
2185 | ||
2186 | for (i = 0; regmap[i].regnum != -1; i++) | |
2187 | { | |
2188 | if ((regnum == -1 || regnum == regmap[i].regnum) | |
2189 | && regmap[i].offset + 4 <= len) | |
2190 | regcache_raw_collect (regcache, regmap[i].regnum, | |
2191 | (char *)regs + regmap[i].offset); | |
2192 | } | |
2193 | } | |
2194 | ||
2195 | /* The following two regsets have the same contents, so it is tempting to | |
2196 | unify them, but they are distiguished by their address, so don't. */ | |
2197 | ||
2198 | struct regset sh_corefile_gregset = | |
2199 | { | |
2200 | NULL, | |
2201 | sh_corefile_supply_regset, | |
2202 | sh_corefile_collect_regset | |
2203 | }; | |
2204 | ||
2205 | static struct regset sh_corefile_fpregset = | |
2206 | { | |
2207 | NULL, | |
2208 | sh_corefile_supply_regset, | |
2209 | sh_corefile_collect_regset | |
2210 | }; | |
2211 | ||
2212 | static const struct regset * | |
2213 | sh_regset_from_core_section (struct gdbarch *gdbarch, const char *sect_name, | |
2214 | size_t sect_size) | |
2215 | { | |
2216 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2217 | ||
2218 | if (tdep->core_gregmap && strcmp (sect_name, ".reg") == 0) | |
2219 | return &sh_corefile_gregset; | |
2220 | ||
2221 | if (tdep->core_fpregmap && strcmp (sect_name, ".reg2") == 0) | |
2222 | return &sh_corefile_fpregset; | |
2223 | ||
2224 | return NULL; | |
2225 | } | |
18648a37 YQ |
2226 | |
2227 | /* This is the implementation of gdbarch method | |
2228 | return_in_first_hidden_param_p. */ | |
2229 | ||
2230 | static int | |
2231 | sh_return_in_first_hidden_param_p (struct gdbarch *gdbarch, | |
2232 | struct type *type) | |
2233 | { | |
2234 | return 0; | |
2235 | } | |
2236 | ||
ccf00f21 | 2237 | \f |
cc17453a EZ |
2238 | |
2239 | static struct gdbarch * | |
fba45db2 | 2240 | sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
cc17453a | 2241 | { |
cc17453a | 2242 | struct gdbarch *gdbarch; |
c9ac0a72 | 2243 | struct gdbarch_tdep *tdep; |
d658f924 | 2244 | |
2d4c29c5 TS |
2245 | /* SH5 is handled entirely in sh64-tdep.c. */ |
2246 | if (info.bfd_arch_info->mach == bfd_mach_sh5) | |
2247 | return sh64_gdbarch_init (info, arches); | |
55ff77ac | 2248 | |
4be87837 DJ |
2249 | /* If there is already a candidate, use it. */ |
2250 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
2251 | if (arches != NULL) | |
2252 | return arches->gdbarch; | |
cc17453a EZ |
2253 | |
2254 | /* None found, create a new architecture from the information | |
c378eb4e | 2255 | provided. */ |
c9ac0a72 AS |
2256 | tdep = XZALLOC (struct gdbarch_tdep); |
2257 | gdbarch = gdbarch_alloc (&info, tdep); | |
cc17453a | 2258 | |
48db5a3c CV |
2259 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); |
2260 | set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
ec920329 | 2261 | set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
48db5a3c CV |
2262 | set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); |
2263 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
2264 | set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
2265 | set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
a38d2a54 | 2266 | set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
48db5a3c | 2267 | |
f2ea0907 | 2268 | set_gdbarch_num_regs (gdbarch, SH_NUM_REGS); |
a38d2a54 | 2269 | set_gdbarch_sp_regnum (gdbarch, 15); |
a38d2a54 | 2270 | set_gdbarch_pc_regnum (gdbarch, 16); |
48db5a3c CV |
2271 | set_gdbarch_fp0_regnum (gdbarch, -1); |
2272 | set_gdbarch_num_pseudo_regs (gdbarch, 0); | |
2273 | ||
1c0159e0 | 2274 | set_gdbarch_register_type (gdbarch, sh_default_register_type); |
dda63807 | 2275 | set_gdbarch_register_reggroup_p (gdbarch, sh_register_reggroup_p); |
1c0159e0 | 2276 | |
eaf90c5d | 2277 | set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc); |
48db5a3c | 2278 | |
9dae60cc | 2279 | set_gdbarch_print_insn (gdbarch, print_insn_sh); |
2f14585c | 2280 | set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno); |
48db5a3c | 2281 | |
c0409442 | 2282 | set_gdbarch_return_value (gdbarch, sh_return_value_nofpu); |
1c0159e0 | 2283 | |
48db5a3c CV |
2284 | set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue); |
2285 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
48db5a3c | 2286 | |
1c0159e0 | 2287 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu); |
18648a37 YQ |
2288 | set_gdbarch_return_in_first_hidden_param_p (gdbarch, |
2289 | sh_return_in_first_hidden_param_p); | |
1c0159e0 | 2290 | |
48db5a3c CV |
2291 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); |
2292 | ||
19f59343 | 2293 | set_gdbarch_frame_align (gdbarch, sh_frame_align); |
1c0159e0 CV |
2294 | set_gdbarch_unwind_sp (gdbarch, sh_unwind_sp); |
2295 | set_gdbarch_unwind_pc (gdbarch, sh_unwind_pc); | |
94afd7a6 | 2296 | set_gdbarch_dummy_id (gdbarch, sh_dummy_id); |
1c0159e0 CV |
2297 | frame_base_set_default (gdbarch, &sh_frame_base); |
2298 | ||
617daa0e | 2299 | set_gdbarch_in_function_epilogue_p (gdbarch, sh_in_function_epilogue_p); |
cc17453a | 2300 | |
357d3800 AS |
2301 | dwarf2_frame_set_init_reg (gdbarch, sh_dwarf2_frame_init_reg); |
2302 | ||
c9ac0a72 AS |
2303 | set_gdbarch_regset_from_core_section (gdbarch, sh_regset_from_core_section); |
2304 | ||
cc17453a | 2305 | switch (info.bfd_arch_info->mach) |
8db62801 | 2306 | { |
cc17453a | 2307 | case bfd_mach_sh: |
48db5a3c | 2308 | set_gdbarch_register_name (gdbarch, sh_sh_register_name); |
cc17453a | 2309 | break; |
1c0159e0 | 2310 | |
cc17453a | 2311 | case bfd_mach_sh2: |
48db5a3c | 2312 | set_gdbarch_register_name (gdbarch, sh_sh_register_name); |
617daa0e | 2313 | break; |
1c0159e0 | 2314 | |
2d188dd3 | 2315 | case bfd_mach_sh2e: |
c378eb4e | 2316 | /* doubles on sh2e and sh3e are actually 4 byte. */ |
48db5a3c | 2317 | set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
f92589cb | 2318 | set_gdbarch_double_format (gdbarch, floatformats_ieee_single); |
48db5a3c CV |
2319 | |
2320 | set_gdbarch_register_name (gdbarch, sh_sh2e_register_name); | |
48db5a3c | 2321 | set_gdbarch_register_type (gdbarch, sh_sh3e_register_type); |
2d188dd3 | 2322 | set_gdbarch_fp0_regnum (gdbarch, 25); |
c0409442 | 2323 | set_gdbarch_return_value (gdbarch, sh_return_value_fpu); |
6df2bf50 | 2324 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); |
2d188dd3 | 2325 | break; |
1c0159e0 | 2326 | |
da962468 CV |
2327 | case bfd_mach_sh2a: |
2328 | set_gdbarch_register_name (gdbarch, sh_sh2a_register_name); | |
2329 | set_gdbarch_register_type (gdbarch, sh_sh2a_register_type); | |
2330 | set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno); | |
2331 | ||
2332 | set_gdbarch_fp0_regnum (gdbarch, 25); | |
2333 | set_gdbarch_num_pseudo_regs (gdbarch, 9); | |
2334 | set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read); | |
2335 | set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write); | |
c0409442 | 2336 | set_gdbarch_return_value (gdbarch, sh_return_value_fpu); |
da962468 CV |
2337 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); |
2338 | break; | |
2339 | ||
2340 | case bfd_mach_sh2a_nofpu: | |
2341 | set_gdbarch_register_name (gdbarch, sh_sh2a_nofpu_register_name); | |
2342 | set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno); | |
2343 | ||
2344 | set_gdbarch_num_pseudo_regs (gdbarch, 1); | |
2345 | set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read); | |
2346 | set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write); | |
2347 | break; | |
2348 | ||
cc17453a | 2349 | case bfd_mach_sh_dsp: |
48db5a3c | 2350 | set_gdbarch_register_name (gdbarch, sh_sh_dsp_register_name); |
2f14585c | 2351 | set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno); |
cc17453a | 2352 | break; |
1c0159e0 | 2353 | |
cc17453a | 2354 | case bfd_mach_sh3: |
4e6cbc38 AS |
2355 | case bfd_mach_sh3_nommu: |
2356 | case bfd_mach_sh2a_nofpu_or_sh3_nommu: | |
48db5a3c | 2357 | set_gdbarch_register_name (gdbarch, sh_sh3_register_name); |
cc17453a | 2358 | break; |
1c0159e0 | 2359 | |
cc17453a | 2360 | case bfd_mach_sh3e: |
4e6cbc38 | 2361 | case bfd_mach_sh2a_or_sh3e: |
c378eb4e | 2362 | /* doubles on sh2e and sh3e are actually 4 byte. */ |
48db5a3c | 2363 | set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
f92589cb | 2364 | set_gdbarch_double_format (gdbarch, floatformats_ieee_single); |
48db5a3c CV |
2365 | |
2366 | set_gdbarch_register_name (gdbarch, sh_sh3e_register_name); | |
48db5a3c | 2367 | set_gdbarch_register_type (gdbarch, sh_sh3e_register_type); |
cc17453a | 2368 | set_gdbarch_fp0_regnum (gdbarch, 25); |
c0409442 | 2369 | set_gdbarch_return_value (gdbarch, sh_return_value_fpu); |
6df2bf50 | 2370 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); |
cc17453a | 2371 | break; |
1c0159e0 | 2372 | |
cc17453a | 2373 | case bfd_mach_sh3_dsp: |
48db5a3c | 2374 | set_gdbarch_register_name (gdbarch, sh_sh3_dsp_register_name); |
48db5a3c | 2375 | set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno); |
cc17453a | 2376 | break; |
1c0159e0 | 2377 | |
cc17453a | 2378 | case bfd_mach_sh4: |
474e5826 | 2379 | case bfd_mach_sh4a: |
46e8a76b | 2380 | case bfd_mach_sh2a_or_sh4: |
48db5a3c | 2381 | set_gdbarch_register_name (gdbarch, sh_sh4_register_name); |
48db5a3c | 2382 | set_gdbarch_register_type (gdbarch, sh_sh4_register_type); |
cc17453a | 2383 | set_gdbarch_fp0_regnum (gdbarch, 25); |
da962468 | 2384 | set_gdbarch_num_pseudo_regs (gdbarch, 13); |
d8124050 AC |
2385 | set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read); |
2386 | set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write); | |
c0409442 | 2387 | set_gdbarch_return_value (gdbarch, sh_return_value_fpu); |
6df2bf50 | 2388 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); |
cc17453a | 2389 | break; |
1c0159e0 | 2390 | |
474e5826 CV |
2391 | case bfd_mach_sh4_nofpu: |
2392 | case bfd_mach_sh4a_nofpu: | |
4e6cbc38 AS |
2393 | case bfd_mach_sh4_nommu_nofpu: |
2394 | case bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu: | |
474e5826 CV |
2395 | set_gdbarch_register_name (gdbarch, sh_sh4_nofpu_register_name); |
2396 | break; | |
2397 | ||
2398 | case bfd_mach_sh4al_dsp: | |
2399 | set_gdbarch_register_name (gdbarch, sh_sh4al_dsp_register_name); | |
2400 | set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno); | |
2401 | break; | |
2402 | ||
cc17453a | 2403 | default: |
b58cbbf2 | 2404 | set_gdbarch_register_name (gdbarch, sh_sh_register_name); |
cc17453a | 2405 | break; |
8db62801 | 2406 | } |
cc17453a | 2407 | |
4be87837 DJ |
2408 | /* Hook in ABI-specific overrides, if they have been registered. */ |
2409 | gdbarch_init_osabi (info, gdbarch); | |
d658f924 | 2410 | |
94afd7a6 | 2411 | dwarf2_append_unwinders (gdbarch); |
cb2cf4ce | 2412 | frame_unwind_append_unwinder (gdbarch, &sh_stub_unwind); |
94afd7a6 | 2413 | frame_unwind_append_unwinder (gdbarch, &sh_frame_unwind); |
1c0159e0 | 2414 | |
cc17453a | 2415 | return gdbarch; |
8db62801 EZ |
2416 | } |
2417 | ||
c055b101 CV |
2418 | static void |
2419 | show_sh_command (char *args, int from_tty) | |
2420 | { | |
2421 | help_list (showshcmdlist, "show sh ", all_commands, gdb_stdout); | |
2422 | } | |
2423 | ||
2424 | static void | |
2425 | set_sh_command (char *args, int from_tty) | |
2426 | { | |
2427 | printf_unfiltered | |
2428 | ("\"set sh\" must be followed by an appropriate subcommand.\n"); | |
2429 | help_list (setshcmdlist, "set sh ", all_commands, gdb_stdout); | |
2430 | } | |
2431 | ||
c378eb4e | 2432 | extern initialize_file_ftype _initialize_sh_tdep; /* -Wmissing-prototypes */ |
a78f21af | 2433 | |
c906108c | 2434 | void |
fba45db2 | 2435 | _initialize_sh_tdep (void) |
c906108c | 2436 | { |
f2ea0907 | 2437 | gdbarch_register (bfd_arch_sh, sh_gdbarch_init, NULL); |
c906108c | 2438 | |
c055b101 CV |
2439 | add_prefix_cmd ("sh", no_class, set_sh_command, "SH specific commands.", |
2440 | &setshcmdlist, "set sh ", 0, &setlist); | |
2441 | add_prefix_cmd ("sh", no_class, show_sh_command, "SH specific commands.", | |
2442 | &showshcmdlist, "show sh ", 0, &showlist); | |
2443 | ||
2444 | add_setshow_enum_cmd ("calling-convention", class_vars, sh_cc_enum, | |
2445 | &sh_active_calling_convention, | |
2446 | _("Set calling convention used when calling target " | |
2447 | "functions from GDB."), | |
2448 | _("Show calling convention used when calling target " | |
2449 | "functions from GDB."), | |
2450 | _("gcc - Use GCC calling convention (default).\n" | |
2451 | "renesas - Enforce Renesas calling convention."), | |
2452 | NULL, NULL, | |
2453 | &setshcmdlist, &showshcmdlist); | |
c906108c | 2454 | } |