Commit | Line | Data |
---|---|---|
85a453d5 | 1 | /* Target-dependent code for Renesas Super-H, for GDB. |
0fd88904 | 2 | |
6aba47ca | 3 | Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
9b254dd1 | 4 | 2003, 2004, 2005, 2007, 2008 Free Software Foundation, Inc. |
c906108c | 5 | |
c5aa993b | 6 | This file is part of GDB. |
c906108c | 7 | |
c5aa993b JM |
8 | This program is free software; you can redistribute it and/or modify |
9 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 10 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 11 | (at your option) any later version. |
c906108c | 12 | |
c5aa993b JM |
13 | This program is distributed in the hope that it will be useful, |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
c906108c | 17 | |
c5aa993b | 18 | You should have received a copy of the GNU General Public License |
a9762ec7 | 19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
20 | |
21 | /* | |
c5aa993b JM |
22 | Contributed by Steve Chamberlain |
23 | sac@cygnus.com | |
c906108c SS |
24 | */ |
25 | ||
26 | #include "defs.h" | |
27 | #include "frame.h" | |
1c0159e0 CV |
28 | #include "frame-base.h" |
29 | #include "frame-unwind.h" | |
30 | #include "dwarf2-frame.h" | |
c906108c | 31 | #include "symtab.h" |
c906108c SS |
32 | #include "gdbtypes.h" |
33 | #include "gdbcmd.h" | |
34 | #include "gdbcore.h" | |
35 | #include "value.h" | |
36 | #include "dis-asm.h" | |
73c1f219 | 37 | #include "inferior.h" |
c906108c | 38 | #include "gdb_string.h" |
1c0159e0 | 39 | #include "gdb_assert.h" |
b4a20239 | 40 | #include "arch-utils.h" |
fb409745 | 41 | #include "floatformat.h" |
4e052eda | 42 | #include "regcache.h" |
d16aafd8 | 43 | #include "doublest.h" |
4be87837 | 44 | #include "osabi.h" |
dda63807 | 45 | #include "reggroups.h" |
c906108c | 46 | |
ab3b8126 JT |
47 | #include "sh-tdep.h" |
48 | ||
d658f924 | 49 | #include "elf-bfd.h" |
1a8629c7 MS |
50 | #include "solib-svr4.h" |
51 | ||
55ff77ac | 52 | /* sh flags */ |
283150cd | 53 | #include "elf/sh.h" |
c055b101 | 54 | #include "elf/dwarf2.h" |
283150cd | 55 | /* registers numbers shared with the simulator */ |
1c922164 | 56 | #include "gdb/sim-sh.h" |
283150cd | 57 | |
c055b101 CV |
58 | /* List of "set sh ..." and "show sh ..." commands. */ |
59 | static struct cmd_list_element *setshcmdlist = NULL; | |
60 | static struct cmd_list_element *showshcmdlist = NULL; | |
61 | ||
62 | static const char sh_cc_gcc[] = "gcc"; | |
63 | static const char sh_cc_renesas[] = "renesas"; | |
64 | static const char *sh_cc_enum[] = { | |
65 | sh_cc_gcc, | |
66 | sh_cc_renesas, | |
67 | NULL | |
68 | }; | |
69 | ||
70 | static const char *sh_active_calling_convention = sh_cc_gcc; | |
71 | ||
c458d6db | 72 | static void (*sh_show_regs) (struct frame_info *); |
cc17453a | 73 | |
da962468 | 74 | #define SH_NUM_REGS 67 |
88e04cc1 | 75 | |
1c0159e0 | 76 | struct sh_frame_cache |
cc17453a | 77 | { |
1c0159e0 CV |
78 | /* Base address. */ |
79 | CORE_ADDR base; | |
80 | LONGEST sp_offset; | |
81 | CORE_ADDR pc; | |
82 | ||
83 | /* Flag showing that a frame has been created in the prologue code. */ | |
84 | int uses_fp; | |
85 | ||
86 | /* Saved registers. */ | |
87 | CORE_ADDR saved_regs[SH_NUM_REGS]; | |
88 | CORE_ADDR saved_sp; | |
63978407 | 89 | }; |
c906108c | 90 | |
c055b101 CV |
91 | static int |
92 | sh_is_renesas_calling_convention (struct type *func_type) | |
93 | { | |
94 | return ((func_type | |
95 | && TYPE_CALLING_CONVENTION (func_type) == DW_CC_GNU_renesas_sh) | |
96 | || sh_active_calling_convention == sh_cc_renesas); | |
97 | } | |
98 | ||
fa88f677 | 99 | static const char * |
d93859e2 | 100 | sh_sh_register_name (struct gdbarch *gdbarch, int reg_nr) |
cc17453a | 101 | { |
617daa0e CV |
102 | static char *register_names[] = { |
103 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
104 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
105 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
106 | "", "", | |
107 | "", "", "", "", "", "", "", "", | |
108 | "", "", "", "", "", "", "", "", | |
109 | "", "", | |
110 | "", "", "", "", "", "", "", "", | |
111 | "", "", "", "", "", "", "", "", | |
da962468 | 112 | "", "", "", "", "", "", "", "", |
cc17453a EZ |
113 | }; |
114 | if (reg_nr < 0) | |
115 | return NULL; | |
116 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
117 | return NULL; | |
118 | return register_names[reg_nr]; | |
119 | } | |
120 | ||
fa88f677 | 121 | static const char * |
d93859e2 | 122 | sh_sh3_register_name (struct gdbarch *gdbarch, int reg_nr) |
cc17453a | 123 | { |
617daa0e CV |
124 | static char *register_names[] = { |
125 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
126 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
127 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
128 | "", "", | |
129 | "", "", "", "", "", "", "", "", | |
130 | "", "", "", "", "", "", "", "", | |
131 | "ssr", "spc", | |
cc17453a EZ |
132 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", |
133 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1" | |
da962468 | 134 | "", "", "", "", "", "", "", "", |
cc17453a EZ |
135 | }; |
136 | if (reg_nr < 0) | |
137 | return NULL; | |
138 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
139 | return NULL; | |
140 | return register_names[reg_nr]; | |
141 | } | |
142 | ||
fa88f677 | 143 | static const char * |
d93859e2 | 144 | sh_sh3e_register_name (struct gdbarch *gdbarch, int reg_nr) |
cc17453a | 145 | { |
617daa0e CV |
146 | static char *register_names[] = { |
147 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
148 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
149 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
cc17453a | 150 | "fpul", "fpscr", |
617daa0e CV |
151 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", |
152 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
153 | "ssr", "spc", | |
cc17453a EZ |
154 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", |
155 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", | |
da962468 | 156 | "", "", "", "", "", "", "", "", |
cc17453a EZ |
157 | }; |
158 | if (reg_nr < 0) | |
159 | return NULL; | |
160 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
161 | return NULL; | |
162 | return register_names[reg_nr]; | |
163 | } | |
164 | ||
2d188dd3 | 165 | static const char * |
d93859e2 | 166 | sh_sh2e_register_name (struct gdbarch *gdbarch, int reg_nr) |
2d188dd3 | 167 | { |
617daa0e CV |
168 | static char *register_names[] = { |
169 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
170 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
171 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
2d188dd3 | 172 | "fpul", "fpscr", |
617daa0e CV |
173 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", |
174 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
175 | "", "", | |
2d188dd3 NC |
176 | "", "", "", "", "", "", "", "", |
177 | "", "", "", "", "", "", "", "", | |
da962468 CV |
178 | "", "", "", "", "", "", "", "", |
179 | }; | |
180 | if (reg_nr < 0) | |
181 | return NULL; | |
182 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
183 | return NULL; | |
184 | return register_names[reg_nr]; | |
185 | } | |
186 | ||
187 | static const char * | |
d93859e2 | 188 | sh_sh2a_register_name (struct gdbarch *gdbarch, int reg_nr) |
da962468 CV |
189 | { |
190 | static char *register_names[] = { | |
191 | /* general registers 0-15 */ | |
192 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
193 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
194 | /* 16 - 22 */ | |
195 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
196 | /* 23, 24 */ | |
197 | "fpul", "fpscr", | |
198 | /* floating point registers 25 - 40 */ | |
199 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", | |
200 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
201 | /* 41, 42 */ | |
202 | "", "", | |
203 | /* 43 - 62. Banked registers. The bank number used is determined by | |
204 | the bank register (63). */ | |
205 | "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b", | |
206 | "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", | |
207 | "machb", "ivnb", "prb", "gbrb", "maclb", | |
208 | /* 63: register bank number, not a real register but used to | |
209 | communicate the register bank currently get/set. This register | |
210 | is hidden to the user, who manipulates it using the pseudo | |
211 | register called "bank" (67). See below. */ | |
212 | "", | |
213 | /* 64 - 66 */ | |
214 | "ibcr", "ibnr", "tbr", | |
215 | /* 67: register bank number, the user visible pseudo register. */ | |
216 | "bank", | |
217 | /* double precision (pseudo) 68 - 75 */ | |
218 | "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", | |
219 | }; | |
220 | if (reg_nr < 0) | |
221 | return NULL; | |
222 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
223 | return NULL; | |
224 | return register_names[reg_nr]; | |
225 | } | |
226 | ||
227 | static const char * | |
d93859e2 | 228 | sh_sh2a_nofpu_register_name (struct gdbarch *gdbarch, int reg_nr) |
da962468 CV |
229 | { |
230 | static char *register_names[] = { | |
231 | /* general registers 0-15 */ | |
232 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
233 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
234 | /* 16 - 22 */ | |
235 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
236 | /* 23, 24 */ | |
237 | "", "", | |
238 | /* floating point registers 25 - 40 */ | |
239 | "", "", "", "", "", "", "", "", | |
240 | "", "", "", "", "", "", "", "", | |
241 | /* 41, 42 */ | |
242 | "", "", | |
243 | /* 43 - 62. Banked registers. The bank number used is determined by | |
244 | the bank register (63). */ | |
245 | "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b", | |
246 | "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", | |
247 | "machb", "ivnb", "prb", "gbrb", "maclb", | |
248 | /* 63: register bank number, not a real register but used to | |
249 | communicate the register bank currently get/set. This register | |
250 | is hidden to the user, who manipulates it using the pseudo | |
251 | register called "bank" (67). See below. */ | |
252 | "", | |
253 | /* 64 - 66 */ | |
254 | "ibcr", "ibnr", "tbr", | |
255 | /* 67: register bank number, the user visible pseudo register. */ | |
256 | "bank", | |
257 | /* double precision (pseudo) 68 - 75 */ | |
258 | "", "", "", "", "", "", "", "", | |
2d188dd3 NC |
259 | }; |
260 | if (reg_nr < 0) | |
261 | return NULL; | |
262 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
263 | return NULL; | |
264 | return register_names[reg_nr]; | |
265 | } | |
266 | ||
fa88f677 | 267 | static const char * |
d93859e2 | 268 | sh_sh_dsp_register_name (struct gdbarch *gdbarch, int reg_nr) |
cc17453a | 269 | { |
617daa0e CV |
270 | static char *register_names[] = { |
271 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
272 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
273 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
274 | "", "dsr", | |
275 | "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1", | |
276 | "y0", "y1", "", "", "", "", "", "mod", | |
277 | "", "", | |
278 | "rs", "re", "", "", "", "", "", "", | |
279 | "", "", "", "", "", "", "", "", | |
da962468 | 280 | "", "", "", "", "", "", "", "", |
cc17453a EZ |
281 | }; |
282 | if (reg_nr < 0) | |
283 | return NULL; | |
284 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
285 | return NULL; | |
286 | return register_names[reg_nr]; | |
287 | } | |
288 | ||
fa88f677 | 289 | static const char * |
d93859e2 | 290 | sh_sh3_dsp_register_name (struct gdbarch *gdbarch, int reg_nr) |
cc17453a | 291 | { |
617daa0e CV |
292 | static char *register_names[] = { |
293 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
294 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
295 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
296 | "", "dsr", | |
297 | "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1", | |
298 | "y0", "y1", "", "", "", "", "", "mod", | |
299 | "ssr", "spc", | |
300 | "rs", "re", "", "", "", "", "", "", | |
026a72f8 CV |
301 | "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b", |
302 | "", "", "", "", "", "", "", "", | |
da962468 | 303 | "", "", "", "", "", "", "", "", |
cc17453a EZ |
304 | }; |
305 | if (reg_nr < 0) | |
306 | return NULL; | |
307 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
308 | return NULL; | |
309 | return register_names[reg_nr]; | |
310 | } | |
311 | ||
fa88f677 | 312 | static const char * |
d93859e2 | 313 | sh_sh4_register_name (struct gdbarch *gdbarch, int reg_nr) |
53116e27 | 314 | { |
617daa0e | 315 | static char *register_names[] = { |
a38d2a54 | 316 | /* general registers 0-15 */ |
617daa0e CV |
317 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
318 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
a38d2a54 | 319 | /* 16 - 22 */ |
617daa0e | 320 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", |
a38d2a54 | 321 | /* 23, 24 */ |
53116e27 | 322 | "fpul", "fpscr", |
a38d2a54 | 323 | /* floating point registers 25 - 40 */ |
617daa0e CV |
324 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", |
325 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
a38d2a54 | 326 | /* 41, 42 */ |
617daa0e | 327 | "ssr", "spc", |
a38d2a54 | 328 | /* bank 0 43 - 50 */ |
53116e27 | 329 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", |
a38d2a54 | 330 | /* bank 1 51 - 58 */ |
53116e27 | 331 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", |
da962468 CV |
332 | "", "", "", "", "", "", "", "", |
333 | /* pseudo bank register. */ | |
334 | "", | |
a38d2a54 | 335 | /* double precision (pseudo) 59 - 66 */ |
617daa0e | 336 | "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", |
a38d2a54 | 337 | /* vectors (pseudo) 67 - 70 */ |
617daa0e | 338 | "fv0", "fv4", "fv8", "fv12", |
a38d2a54 EZ |
339 | /* FIXME: missing XF 71 - 86 */ |
340 | /* FIXME: missing XD 87 - 94 */ | |
53116e27 EZ |
341 | }; |
342 | if (reg_nr < 0) | |
343 | return NULL; | |
344 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
345 | return NULL; | |
346 | return register_names[reg_nr]; | |
347 | } | |
348 | ||
474e5826 | 349 | static const char * |
d93859e2 | 350 | sh_sh4_nofpu_register_name (struct gdbarch *gdbarch, int reg_nr) |
474e5826 CV |
351 | { |
352 | static char *register_names[] = { | |
353 | /* general registers 0-15 */ | |
354 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
355 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
356 | /* 16 - 22 */ | |
357 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
358 | /* 23, 24 */ | |
359 | "", "", | |
360 | /* floating point registers 25 - 40 -- not for nofpu target */ | |
361 | "", "", "", "", "", "", "", "", | |
362 | "", "", "", "", "", "", "", "", | |
363 | /* 41, 42 */ | |
364 | "ssr", "spc", | |
365 | /* bank 0 43 - 50 */ | |
366 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", | |
367 | /* bank 1 51 - 58 */ | |
368 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", | |
da962468 CV |
369 | "", "", "", "", "", "", "", "", |
370 | /* pseudo bank register. */ | |
371 | "", | |
474e5826 CV |
372 | /* double precision (pseudo) 59 - 66 -- not for nofpu target */ |
373 | "", "", "", "", "", "", "", "", | |
374 | /* vectors (pseudo) 67 - 70 -- not for nofpu target */ | |
375 | "", "", "", "", | |
376 | }; | |
377 | if (reg_nr < 0) | |
378 | return NULL; | |
379 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
380 | return NULL; | |
381 | return register_names[reg_nr]; | |
382 | } | |
383 | ||
384 | static const char * | |
d93859e2 | 385 | sh_sh4al_dsp_register_name (struct gdbarch *gdbarch, int reg_nr) |
474e5826 CV |
386 | { |
387 | static char *register_names[] = { | |
388 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
389 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
390 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
391 | "", "dsr", | |
392 | "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1", | |
393 | "y0", "y1", "", "", "", "", "", "mod", | |
394 | "ssr", "spc", | |
395 | "rs", "re", "", "", "", "", "", "", | |
026a72f8 CV |
396 | "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b", |
397 | "", "", "", "", "", "", "", "", | |
da962468 | 398 | "", "", "", "", "", "", "", "", |
474e5826 CV |
399 | }; |
400 | if (reg_nr < 0) | |
401 | return NULL; | |
402 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
403 | return NULL; | |
404 | return register_names[reg_nr]; | |
405 | } | |
406 | ||
3117ed25 | 407 | static const unsigned char * |
67d57894 | 408 | sh_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr) |
cc17453a EZ |
409 | { |
410 | /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */ | |
617daa0e CV |
411 | static unsigned char breakpoint[] = { 0xc3, 0xc3 }; |
412 | ||
bac718a6 UW |
413 | /* For remote stub targets, trapa #20 is used. */ |
414 | if (strcmp (target_shortname, "remote") == 0) | |
415 | { | |
416 | static unsigned char big_remote_breakpoint[] = { 0xc3, 0x20 }; | |
417 | static unsigned char little_remote_breakpoint[] = { 0x20, 0xc3 }; | |
418 | ||
67d57894 | 419 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
bac718a6 UW |
420 | { |
421 | *lenptr = sizeof (big_remote_breakpoint); | |
422 | return big_remote_breakpoint; | |
423 | } | |
424 | else | |
425 | { | |
426 | *lenptr = sizeof (little_remote_breakpoint); | |
427 | return little_remote_breakpoint; | |
428 | } | |
429 | } | |
430 | ||
cc17453a EZ |
431 | *lenptr = sizeof (breakpoint); |
432 | return breakpoint; | |
433 | } | |
c906108c SS |
434 | |
435 | /* Prologue looks like | |
1c0159e0 CV |
436 | mov.l r14,@-r15 |
437 | sts.l pr,@-r15 | |
438 | mov.l <regs>,@-r15 | |
439 | sub <room_for_loca_vars>,r15 | |
440 | mov r15,r14 | |
8db62801 | 441 | |
1c0159e0 | 442 | Actually it can be more complicated than this but that's it, basically. |
c5aa993b | 443 | */ |
c906108c | 444 | |
1c0159e0 CV |
445 | #define GET_SOURCE_REG(x) (((x) >> 4) & 0xf) |
446 | #define GET_TARGET_REG(x) (((x) >> 8) & 0xf) | |
447 | ||
5f883edd FF |
448 | /* JSR @Rm 0100mmmm00001011 */ |
449 | #define IS_JSR(x) (((x) & 0xf0ff) == 0x400b) | |
450 | ||
8db62801 EZ |
451 | /* STS.L PR,@-r15 0100111100100010 |
452 | r15-4-->r15, PR-->(r15) */ | |
c906108c | 453 | #define IS_STS(x) ((x) == 0x4f22) |
8db62801 | 454 | |
03131d99 CV |
455 | /* STS.L MACL,@-r15 0100111100010010 |
456 | r15-4-->r15, MACL-->(r15) */ | |
457 | #define IS_MACL_STS(x) ((x) == 0x4f12) | |
458 | ||
8db62801 EZ |
459 | /* MOV.L Rm,@-r15 00101111mmmm0110 |
460 | r15-4-->r15, Rm-->(R15) */ | |
c906108c | 461 | #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06) |
8db62801 | 462 | |
8db62801 EZ |
463 | /* MOV r15,r14 0110111011110011 |
464 | r15-->r14 */ | |
c906108c | 465 | #define IS_MOV_SP_FP(x) ((x) == 0x6ef3) |
8db62801 EZ |
466 | |
467 | /* ADD #imm,r15 01111111iiiiiiii | |
468 | r15+imm-->r15 */ | |
1c0159e0 | 469 | #define IS_ADD_IMM_SP(x) (((x) & 0xff00) == 0x7f00) |
8db62801 | 470 | |
c906108c SS |
471 | #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00) |
472 | #define IS_SHLL_R3(x) ((x) == 0x4300) | |
8db62801 EZ |
473 | |
474 | /* ADD r3,r15 0011111100111100 | |
475 | r15+r3-->r15 */ | |
c906108c | 476 | #define IS_ADD_R3SP(x) ((x) == 0x3f3c) |
8db62801 EZ |
477 | |
478 | /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011 | |
8db62801 | 479 | FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011 |
8db62801 | 480 | FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */ |
f2ea0907 CV |
481 | /* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to |
482 | make this entirely clear. */ | |
1c0159e0 CV |
483 | /* #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) */ |
484 | #define IS_FPUSH(x) (((x) & 0xff0f) == 0xff0b) | |
485 | ||
486 | /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 4 <= m <= 7 */ | |
487 | #define IS_MOV_ARG_TO_REG(x) \ | |
488 | (((x) & 0xf00f) == 0x6003 && \ | |
489 | ((x) & 0x00f0) >= 0x0040 && \ | |
490 | ((x) & 0x00f0) <= 0x0070) | |
491 | /* MOV.L Rm,@Rn 0010nnnnmmmm0010 n = 14, 4 <= m <= 7 */ | |
492 | #define IS_MOV_ARG_TO_IND_R14(x) \ | |
493 | (((x) & 0xff0f) == 0x2e02 && \ | |
494 | ((x) & 0x00f0) >= 0x0040 && \ | |
495 | ((x) & 0x00f0) <= 0x0070) | |
496 | /* MOV.L Rm,@(disp*4,Rn) 00011110mmmmdddd n = 14, 4 <= m <= 7 */ | |
497 | #define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \ | |
498 | (((x) & 0xff00) == 0x1e00 && \ | |
499 | ((x) & 0x00f0) >= 0x0040 && \ | |
500 | ((x) & 0x00f0) <= 0x0070) | |
501 | ||
502 | /* MOV.W @(disp*2,PC),Rn 1001nnnndddddddd */ | |
503 | #define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000) | |
504 | /* MOV.L @(disp*4,PC),Rn 1101nnnndddddddd */ | |
505 | #define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000) | |
03131d99 CV |
506 | /* MOVI20 #imm20,Rn 0000nnnniiii0000 */ |
507 | #define IS_MOVI20(x) (((x) & 0xf00f) == 0x0000) | |
1c0159e0 CV |
508 | /* SUB Rn,R15 00111111nnnn1000 */ |
509 | #define IS_SUB_REG_FROM_SP(x) (((x) & 0xff0f) == 0x3f08) | |
8db62801 | 510 | |
1c0159e0 | 511 | #define FPSCR_SZ (1 << 20) |
cc17453a | 512 | |
1c0159e0 CV |
513 | /* The following instructions are used for epilogue testing. */ |
514 | #define IS_RESTORE_FP(x) ((x) == 0x6ef6) | |
515 | #define IS_RTS(x) ((x) == 0x000b) | |
516 | #define IS_LDS(x) ((x) == 0x4f26) | |
03131d99 | 517 | #define IS_MACL_LDS(x) ((x) == 0x4f16) |
1c0159e0 CV |
518 | #define IS_MOV_FP_SP(x) ((x) == 0x6fe3) |
519 | #define IS_ADD_REG_TO_FP(x) (((x) & 0xff0f) == 0x3e0c) | |
520 | #define IS_ADD_IMM_FP(x) (((x) & 0xff00) == 0x7e00) | |
cc17453a | 521 | |
cc17453a EZ |
522 | /* Disassemble an instruction. */ |
523 | static int | |
617daa0e | 524 | gdb_print_insn_sh (bfd_vma memaddr, disassemble_info * info) |
c906108c | 525 | { |
4c6b5505 | 526 | info->endian = gdbarch_byte_order (current_gdbarch); |
1c509ca8 | 527 | return print_insn_sh (memaddr, info); |
283150cd EZ |
528 | } |
529 | ||
cc17453a | 530 | static CORE_ADDR |
1c0159e0 | 531 | sh_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc, |
d2ca4222 | 532 | struct sh_frame_cache *cache, ULONGEST fpscr) |
617daa0e | 533 | { |
1c0159e0 CV |
534 | ULONGEST inst; |
535 | CORE_ADDR opc; | |
536 | int offset; | |
537 | int sav_offset = 0; | |
c906108c | 538 | int r3_val = 0; |
1c0159e0 | 539 | int reg, sav_reg = -1; |
cc17453a | 540 | |
1c0159e0 CV |
541 | if (pc >= current_pc) |
542 | return current_pc; | |
cc17453a | 543 | |
1c0159e0 | 544 | cache->uses_fp = 0; |
cc17453a EZ |
545 | for (opc = pc + (2 * 28); pc < opc; pc += 2) |
546 | { | |
1c0159e0 | 547 | inst = read_memory_unsigned_integer (pc, 2); |
cc17453a | 548 | /* See where the registers will be saved to */ |
f2ea0907 | 549 | if (IS_PUSH (inst)) |
cc17453a | 550 | { |
1c0159e0 CV |
551 | cache->saved_regs[GET_SOURCE_REG (inst)] = cache->sp_offset; |
552 | cache->sp_offset += 4; | |
cc17453a | 553 | } |
f2ea0907 | 554 | else if (IS_STS (inst)) |
cc17453a | 555 | { |
1c0159e0 CV |
556 | cache->saved_regs[PR_REGNUM] = cache->sp_offset; |
557 | cache->sp_offset += 4; | |
cc17453a | 558 | } |
03131d99 CV |
559 | else if (IS_MACL_STS (inst)) |
560 | { | |
561 | cache->saved_regs[MACL_REGNUM] = cache->sp_offset; | |
562 | cache->sp_offset += 4; | |
563 | } | |
f2ea0907 | 564 | else if (IS_MOV_R3 (inst)) |
cc17453a | 565 | { |
f2ea0907 | 566 | r3_val = ((inst & 0xff) ^ 0x80) - 0x80; |
cc17453a | 567 | } |
f2ea0907 | 568 | else if (IS_SHLL_R3 (inst)) |
cc17453a EZ |
569 | { |
570 | r3_val <<= 1; | |
571 | } | |
f2ea0907 | 572 | else if (IS_ADD_R3SP (inst)) |
cc17453a | 573 | { |
1c0159e0 | 574 | cache->sp_offset += -r3_val; |
cc17453a | 575 | } |
f2ea0907 | 576 | else if (IS_ADD_IMM_SP (inst)) |
cc17453a | 577 | { |
1c0159e0 CV |
578 | offset = ((inst & 0xff) ^ 0x80) - 0x80; |
579 | cache->sp_offset -= offset; | |
c906108c | 580 | } |
1c0159e0 | 581 | else if (IS_MOVW_PCREL_TO_REG (inst)) |
617daa0e | 582 | { |
1c0159e0 CV |
583 | if (sav_reg < 0) |
584 | { | |
585 | reg = GET_TARGET_REG (inst); | |
586 | if (reg < 14) | |
587 | { | |
588 | sav_reg = reg; | |
a2b4a96c | 589 | offset = (inst & 0xff) << 1; |
1c0159e0 | 590 | sav_offset = |
a2b4a96c | 591 | read_memory_integer ((pc + 4) + offset, 2); |
1c0159e0 CV |
592 | } |
593 | } | |
c906108c | 594 | } |
1c0159e0 | 595 | else if (IS_MOVL_PCREL_TO_REG (inst)) |
617daa0e | 596 | { |
1c0159e0 CV |
597 | if (sav_reg < 0) |
598 | { | |
a2b4a96c | 599 | reg = GET_TARGET_REG (inst); |
1c0159e0 CV |
600 | if (reg < 14) |
601 | { | |
602 | sav_reg = reg; | |
a2b4a96c | 603 | offset = (inst & 0xff) << 2; |
1c0159e0 | 604 | sav_offset = |
a2b4a96c | 605 | read_memory_integer (((pc & 0xfffffffc) + 4) + offset, 4); |
1c0159e0 CV |
606 | } |
607 | } | |
c906108c | 608 | } |
03131d99 CV |
609 | else if (IS_MOVI20 (inst)) |
610 | { | |
611 | if (sav_reg < 0) | |
612 | { | |
613 | reg = GET_TARGET_REG (inst); | |
614 | if (reg < 14) | |
615 | { | |
616 | sav_reg = reg; | |
617 | sav_offset = GET_SOURCE_REG (inst) << 16; | |
618 | /* MOVI20 is a 32 bit instruction! */ | |
619 | pc += 2; | |
620 | sav_offset |= read_memory_unsigned_integer (pc, 2); | |
621 | /* Now sav_offset contains an unsigned 20 bit value. | |
622 | It must still get sign extended. */ | |
623 | if (sav_offset & 0x00080000) | |
624 | sav_offset |= 0xfff00000; | |
625 | } | |
626 | } | |
627 | } | |
1c0159e0 | 628 | else if (IS_SUB_REG_FROM_SP (inst)) |
617daa0e | 629 | { |
1c0159e0 CV |
630 | reg = GET_SOURCE_REG (inst); |
631 | if (sav_reg > 0 && reg == sav_reg) | |
632 | { | |
633 | sav_reg = -1; | |
634 | } | |
635 | cache->sp_offset += sav_offset; | |
c906108c | 636 | } |
f2ea0907 | 637 | else if (IS_FPUSH (inst)) |
c906108c | 638 | { |
d2ca4222 | 639 | if (fpscr & FPSCR_SZ) |
c906108c | 640 | { |
1c0159e0 | 641 | cache->sp_offset += 8; |
c906108c SS |
642 | } |
643 | else | |
644 | { | |
1c0159e0 | 645 | cache->sp_offset += 4; |
c906108c SS |
646 | } |
647 | } | |
f2ea0907 | 648 | else if (IS_MOV_SP_FP (inst)) |
617daa0e | 649 | { |
960ccd7d | 650 | cache->uses_fp = 1; |
1c0159e0 CV |
651 | /* At this point, only allow argument register moves to other |
652 | registers or argument register moves to @(X,fp) which are | |
653 | moving the register arguments onto the stack area allocated | |
654 | by a former add somenumber to SP call. Don't allow moving | |
655 | to an fp indirect address above fp + cache->sp_offset. */ | |
656 | pc += 2; | |
657 | for (opc = pc + 12; pc < opc; pc += 2) | |
658 | { | |
659 | inst = read_memory_integer (pc, 2); | |
660 | if (IS_MOV_ARG_TO_IND_R14 (inst)) | |
617daa0e | 661 | { |
1c0159e0 CV |
662 | reg = GET_SOURCE_REG (inst); |
663 | if (cache->sp_offset > 0) | |
617daa0e | 664 | cache->saved_regs[reg] = cache->sp_offset; |
1c0159e0 CV |
665 | } |
666 | else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst)) | |
617daa0e | 667 | { |
1c0159e0 CV |
668 | reg = GET_SOURCE_REG (inst); |
669 | offset = (inst & 0xf) * 4; | |
670 | if (cache->sp_offset > offset) | |
671 | cache->saved_regs[reg] = cache->sp_offset - offset; | |
672 | } | |
673 | else if (IS_MOV_ARG_TO_REG (inst)) | |
617daa0e | 674 | continue; |
1c0159e0 CV |
675 | else |
676 | break; | |
677 | } | |
678 | break; | |
679 | } | |
5f883edd FF |
680 | else if (IS_JSR (inst)) |
681 | { | |
682 | /* We have found a jsr that has been scheduled into the prologue. | |
683 | If we continue the scan and return a pc someplace after this, | |
684 | then setting a breakpoint on this function will cause it to | |
685 | appear to be called after the function it is calling via the | |
686 | jsr, which will be very confusing. Most likely the next | |
687 | instruction is going to be IS_MOV_SP_FP in the delay slot. If | |
688 | so, note that before returning the current pc. */ | |
689 | inst = read_memory_integer (pc + 2, 2); | |
690 | if (IS_MOV_SP_FP (inst)) | |
691 | cache->uses_fp = 1; | |
692 | break; | |
693 | } | |
617daa0e CV |
694 | #if 0 /* This used to just stop when it found an instruction that |
695 | was not considered part of the prologue. Now, we just | |
696 | keep going looking for likely instructions. */ | |
c906108c SS |
697 | else |
698 | break; | |
2bfa91ee | 699 | #endif |
c906108c SS |
700 | } |
701 | ||
1c0159e0 CV |
702 | return pc; |
703 | } | |
c906108c | 704 | |
1c0159e0 | 705 | /* Skip any prologue before the guts of a function */ |
c906108c | 706 | |
1c0159e0 CV |
707 | /* Skip the prologue using the debug information. If this fails we'll |
708 | fall back on the 'guess' method below. */ | |
709 | static CORE_ADDR | |
710 | after_prologue (CORE_ADDR pc) | |
711 | { | |
712 | struct symtab_and_line sal; | |
713 | CORE_ADDR func_addr, func_end; | |
c906108c | 714 | |
1c0159e0 CV |
715 | /* If we can not find the symbol in the partial symbol table, then |
716 | there is no hope we can determine the function's start address | |
717 | with this code. */ | |
718 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
719 | return 0; | |
c906108c | 720 | |
1c0159e0 CV |
721 | /* Get the line associated with FUNC_ADDR. */ |
722 | sal = find_pc_line (func_addr, 0); | |
723 | ||
724 | /* There are only two cases to consider. First, the end of the source line | |
725 | is within the function bounds. In that case we return the end of the | |
726 | source line. Second is the end of the source line extends beyond the | |
727 | bounds of the current function. We need to use the slow code to | |
728 | examine instructions in that case. */ | |
729 | if (sal.end < func_end) | |
730 | return sal.end; | |
731 | else | |
732 | return 0; | |
c906108c SS |
733 | } |
734 | ||
1c0159e0 | 735 | static CORE_ADDR |
6093d2eb | 736 | sh_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
c906108c | 737 | { |
1c0159e0 CV |
738 | CORE_ADDR pc; |
739 | struct sh_frame_cache cache; | |
740 | ||
741 | /* See if we can determine the end of the prologue via the symbol table. | |
742 | If so, then return either PC, or the PC after the prologue, whichever | |
743 | is greater. */ | |
744 | pc = after_prologue (start_pc); | |
cc17453a | 745 | |
1c0159e0 CV |
746 | /* If after_prologue returned a useful address, then use it. Else |
747 | fall back on the instruction skipping code. */ | |
748 | if (pc) | |
749 | return max (pc, start_pc); | |
c906108c | 750 | |
1c0159e0 | 751 | cache.sp_offset = -4; |
d2ca4222 | 752 | pc = sh_analyze_prologue (start_pc, (CORE_ADDR) -1, &cache, 0); |
1c0159e0 CV |
753 | if (!cache.uses_fp) |
754 | return start_pc; | |
c906108c | 755 | |
1c0159e0 CV |
756 | return pc; |
757 | } | |
758 | ||
2e952408 | 759 | /* The ABI says: |
9a5cef92 EZ |
760 | |
761 | Aggregate types not bigger than 8 bytes that have the same size and | |
762 | alignment as one of the integer scalar types are returned in the | |
763 | same registers as the integer type they match. | |
764 | ||
765 | For example, a 2-byte aligned structure with size 2 bytes has the | |
766 | same size and alignment as a short int, and will be returned in R0. | |
767 | A 4-byte aligned structure with size 8 bytes has the same size and | |
768 | alignment as a long long int, and will be returned in R0 and R1. | |
769 | ||
770 | When an aggregate type is returned in R0 and R1, R0 contains the | |
771 | first four bytes of the aggregate, and R1 contains the | |
772 | remainder. If the size of the aggregate type is not a multiple of 4 | |
773 | bytes, the aggregate is tail-padded up to a multiple of 4 | |
774 | bytes. The value of the padding is undefined. For little-endian | |
775 | targets the padding will appear at the most significant end of the | |
776 | last element, for big-endian targets the padding appears at the | |
777 | least significant end of the last element. | |
778 | ||
779 | All other aggregate types are returned by address. The caller | |
780 | function passes the address of an area large enough to hold the | |
781 | aggregate value in R2. The called function stores the result in | |
7fe958be | 782 | this location. |
9a5cef92 EZ |
783 | |
784 | To reiterate, structs smaller than 8 bytes could also be returned | |
785 | in memory, if they don't pass the "same size and alignment as an | |
786 | integer type" rule. | |
787 | ||
788 | For example, in | |
789 | ||
790 | struct s { char c[3]; } wibble; | |
791 | struct s foo(void) { return wibble; } | |
792 | ||
793 | the return value from foo() will be in memory, not | |
794 | in R0, because there is no 3-byte integer type. | |
795 | ||
7fe958be EZ |
796 | Similarly, in |
797 | ||
798 | struct s { char c[2]; } wibble; | |
799 | struct s foo(void) { return wibble; } | |
800 | ||
801 | because a struct containing two chars has alignment 1, that matches | |
802 | type char, but size 2, that matches type short. There's no integer | |
803 | type that has alignment 1 and size 2, so the struct is returned in | |
804 | memory. | |
805 | ||
9a5cef92 EZ |
806 | */ |
807 | ||
1c0159e0 | 808 | static int |
c055b101 | 809 | sh_use_struct_convention (int renesas_abi, struct type *type) |
1c0159e0 CV |
810 | { |
811 | int len = TYPE_LENGTH (type); | |
812 | int nelem = TYPE_NFIELDS (type); | |
3f997a97 | 813 | |
c055b101 CV |
814 | /* The Renesas ABI returns aggregate types always on stack. */ |
815 | if (renesas_abi && (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
816 | || TYPE_CODE (type) == TYPE_CODE_UNION)) | |
817 | return 1; | |
818 | ||
3f997a97 CV |
819 | /* Non-power of 2 length types and types bigger than 8 bytes (which don't |
820 | fit in two registers anyway) use struct convention. */ | |
821 | if (len != 1 && len != 2 && len != 4 && len != 8) | |
822 | return 1; | |
823 | ||
824 | /* Scalar types and aggregate types with exactly one field are aligned | |
825 | by definition. They are returned in registers. */ | |
826 | if (nelem <= 1) | |
827 | return 0; | |
828 | ||
829 | /* If the first field in the aggregate has the same length as the entire | |
830 | aggregate type, the type is returned in registers. */ | |
831 | if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == len) | |
832 | return 0; | |
833 | ||
834 | /* If the size of the aggregate is 8 bytes and the first field is | |
835 | of size 4 bytes its alignment is equal to long long's alignment, | |
836 | so it's returned in registers. */ | |
837 | if (len == 8 && TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == 4) | |
838 | return 0; | |
839 | ||
840 | /* Otherwise use struct convention. */ | |
841 | return 1; | |
283150cd EZ |
842 | } |
843 | ||
c055b101 CV |
844 | static int |
845 | sh_use_struct_convention_nofpu (int renesas_abi, struct type *type) | |
846 | { | |
847 | /* The Renesas ABI returns long longs/doubles etc. always on stack. */ | |
848 | if (renesas_abi && TYPE_NFIELDS (type) == 0 && TYPE_LENGTH (type) >= 8) | |
849 | return 1; | |
850 | return sh_use_struct_convention (renesas_abi, type); | |
851 | } | |
852 | ||
19f59343 MS |
853 | static CORE_ADDR |
854 | sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp) | |
855 | { | |
856 | return sp & ~3; | |
857 | } | |
858 | ||
55ff77ac | 859 | /* Function: push_dummy_call (formerly push_arguments) |
c906108c SS |
860 | Setup the function arguments for calling a function in the inferior. |
861 | ||
85a453d5 | 862 | On the Renesas SH architecture, there are four registers (R4 to R7) |
c906108c SS |
863 | which are dedicated for passing function arguments. Up to the first |
864 | four arguments (depending on size) may go into these registers. | |
865 | The rest go on the stack. | |
866 | ||
6df2bf50 MS |
867 | MVS: Except on SH variants that have floating point registers. |
868 | In that case, float and double arguments are passed in the same | |
869 | manner, but using FP registers instead of GP registers. | |
870 | ||
c906108c SS |
871 | Arguments that are smaller than 4 bytes will still take up a whole |
872 | register or a whole 32-bit word on the stack, and will be | |
873 | right-justified in the register or the stack word. This includes | |
874 | chars, shorts, and small aggregate types. | |
875 | ||
876 | Arguments that are larger than 4 bytes may be split between two or | |
877 | more registers. If there are not enough registers free, an argument | |
878 | may be passed partly in a register (or registers), and partly on the | |
879 | stack. This includes doubles, long longs, and larger aggregates. | |
880 | As far as I know, there is no upper limit to the size of aggregates | |
881 | that will be passed in this way; in other words, the convention of | |
882 | passing a pointer to a large aggregate instead of a copy is not used. | |
883 | ||
6df2bf50 | 884 | MVS: The above appears to be true for the SH variants that do not |
55ff77ac | 885 | have an FPU, however those that have an FPU appear to copy the |
6df2bf50 MS |
886 | aggregate argument onto the stack (and not place it in registers) |
887 | if it is larger than 16 bytes (four GP registers). | |
888 | ||
c906108c SS |
889 | An exceptional case exists for struct arguments (and possibly other |
890 | aggregates such as arrays) if the size is larger than 4 bytes but | |
891 | not a multiple of 4 bytes. In this case the argument is never split | |
892 | between the registers and the stack, but instead is copied in its | |
893 | entirety onto the stack, AND also copied into as many registers as | |
894 | there is room for. In other words, space in registers permitting, | |
895 | two copies of the same argument are passed in. As far as I can tell, | |
896 | only the one on the stack is used, although that may be a function | |
897 | of the level of compiler optimization. I suspect this is a compiler | |
898 | bug. Arguments of these odd sizes are left-justified within the | |
899 | word (as opposed to arguments smaller than 4 bytes, which are | |
900 | right-justified). | |
c5aa993b | 901 | |
c906108c SS |
902 | If the function is to return an aggregate type such as a struct, it |
903 | is either returned in the normal return value register R0 (if its | |
904 | size is no greater than one byte), or else the caller must allocate | |
905 | space into which the callee will copy the return value (if the size | |
906 | is greater than one byte). In this case, a pointer to the return | |
907 | value location is passed into the callee in register R2, which does | |
908 | not displace any of the other arguments passed in via registers R4 | |
909 | to R7. */ | |
910 | ||
e5e33cd9 CV |
911 | /* Helper function to justify value in register according to endianess. */ |
912 | static char * | |
d93859e2 | 913 | sh_justify_value_in_reg (struct gdbarch *gdbarch, struct value *val, int len) |
e5e33cd9 CV |
914 | { |
915 | static char valbuf[4]; | |
916 | ||
617daa0e | 917 | memset (valbuf, 0, sizeof (valbuf)); |
e5e33cd9 CV |
918 | if (len < 4) |
919 | { | |
920 | /* value gets right-justified in the register or stack word */ | |
d93859e2 | 921 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
0fd88904 | 922 | memcpy (valbuf + (4 - len), (char *) value_contents (val), len); |
e5e33cd9 | 923 | else |
0fd88904 | 924 | memcpy (valbuf, (char *) value_contents (val), len); |
e5e33cd9 CV |
925 | return valbuf; |
926 | } | |
0fd88904 | 927 | return (char *) value_contents (val); |
617daa0e | 928 | } |
e5e33cd9 CV |
929 | |
930 | /* Helper function to eval number of bytes to allocate on stack. */ | |
931 | static CORE_ADDR | |
932 | sh_stack_allocsize (int nargs, struct value **args) | |
933 | { | |
934 | int stack_alloc = 0; | |
935 | while (nargs-- > 0) | |
4991999e | 936 | stack_alloc += ((TYPE_LENGTH (value_type (args[nargs])) + 3) & ~3); |
e5e33cd9 CV |
937 | return stack_alloc; |
938 | } | |
939 | ||
940 | /* Helper functions for getting the float arguments right. Registers usage | |
941 | depends on the ABI and the endianess. The comments should enlighten how | |
942 | it's intended to work. */ | |
943 | ||
944 | /* This array stores which of the float arg registers are already in use. */ | |
945 | static int flt_argreg_array[FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM + 1]; | |
946 | ||
947 | /* This function just resets the above array to "no reg used so far". */ | |
948 | static void | |
949 | sh_init_flt_argreg (void) | |
950 | { | |
951 | memset (flt_argreg_array, 0, sizeof flt_argreg_array); | |
952 | } | |
953 | ||
954 | /* This function returns the next register to use for float arg passing. | |
955 | It returns either a valid value between FLOAT_ARG0_REGNUM and | |
956 | FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns | |
957 | FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available. | |
958 | ||
959 | Note that register number 0 in flt_argreg_array corresponds with the | |
960 | real float register fr4. In contrast to FLOAT_ARG0_REGNUM (value is | |
961 | 29) the parity of the register number is preserved, which is important | |
962 | for the double register passing test (see the "argreg & 1" test below). */ | |
963 | static int | |
c055b101 | 964 | sh_next_flt_argreg (struct gdbarch *gdbarch, int len, struct type *func_type) |
e5e33cd9 CV |
965 | { |
966 | int argreg; | |
967 | ||
968 | /* First search for the next free register. */ | |
617daa0e CV |
969 | for (argreg = 0; argreg <= FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM; |
970 | ++argreg) | |
e5e33cd9 CV |
971 | if (!flt_argreg_array[argreg]) |
972 | break; | |
973 | ||
974 | /* No register left? */ | |
975 | if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM) | |
976 | return FLOAT_ARGLAST_REGNUM + 1; | |
977 | ||
978 | if (len == 8) | |
979 | { | |
980 | /* Doubles are always starting in a even register number. */ | |
981 | if (argreg & 1) | |
617daa0e | 982 | { |
c055b101 CV |
983 | /* In gcc ABI, the skipped register is lost for further argument |
984 | passing now. Not so in Renesas ABI. */ | |
985 | if (!sh_is_renesas_calling_convention (func_type)) | |
986 | flt_argreg_array[argreg] = 1; | |
e5e33cd9 CV |
987 | |
988 | ++argreg; | |
989 | ||
617daa0e | 990 | /* No register left? */ |
e5e33cd9 CV |
991 | if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM) |
992 | return FLOAT_ARGLAST_REGNUM + 1; | |
993 | } | |
994 | /* Also mark the next register as used. */ | |
995 | flt_argreg_array[argreg + 1] = 1; | |
996 | } | |
c055b101 CV |
997 | else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE |
998 | && !sh_is_renesas_calling_convention (func_type)) | |
e5e33cd9 CV |
999 | { |
1000 | /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */ | |
1001 | if (!flt_argreg_array[argreg + 1]) | |
1002 | ++argreg; | |
1003 | } | |
1004 | flt_argreg_array[argreg] = 1; | |
1005 | return FLOAT_ARG0_REGNUM + argreg; | |
1006 | } | |
1007 | ||
afce3d2a CV |
1008 | /* Helper function which figures out, if a type is treated like a float type. |
1009 | ||
2e952408 | 1010 | The FPU ABIs have a special way how to treat types as float types. |
afce3d2a CV |
1011 | Structures with exactly one member, which is of type float or double, are |
1012 | treated exactly as the base types float or double: | |
1013 | ||
1014 | struct sf { | |
1015 | float f; | |
1016 | }; | |
1017 | ||
1018 | struct sd { | |
1019 | double d; | |
1020 | }; | |
1021 | ||
1022 | are handled the same way as just | |
1023 | ||
1024 | float f; | |
1025 | ||
1026 | double d; | |
1027 | ||
1028 | As a result, arguments of these struct types are pushed into floating point | |
1029 | registers exactly as floats or doubles, using the same decision algorithm. | |
1030 | ||
1031 | The same is valid if these types are used as function return types. The | |
1032 | above structs are returned in fr0 resp. fr0,fr1 instead of in r0, r0,r1 | |
1033 | or even using struct convention as it is for other structs. */ | |
1034 | ||
1035 | static int | |
1036 | sh_treat_as_flt_p (struct type *type) | |
1037 | { | |
1038 | int len = TYPE_LENGTH (type); | |
1039 | ||
1040 | /* Ordinary float types are obviously treated as float. */ | |
1041 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
1042 | return 1; | |
1043 | /* Otherwise non-struct types are not treated as float. */ | |
1044 | if (TYPE_CODE (type) != TYPE_CODE_STRUCT) | |
1045 | return 0; | |
1046 | /* Otherwise structs with more than one memeber are not treated as float. */ | |
1047 | if (TYPE_NFIELDS (type) != 1) | |
1048 | return 0; | |
1049 | /* Otherwise if the type of that member is float, the whole type is | |
1050 | treated as float. */ | |
1051 | if (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) == TYPE_CODE_FLT) | |
1052 | return 1; | |
1053 | /* Otherwise it's not treated as float. */ | |
1054 | return 0; | |
1055 | } | |
1056 | ||
cc17453a | 1057 | static CORE_ADDR |
617daa0e | 1058 | sh_push_dummy_call_fpu (struct gdbarch *gdbarch, |
7d9b040b | 1059 | struct value *function, |
617daa0e | 1060 | struct regcache *regcache, |
6df2bf50 | 1061 | CORE_ADDR bp_addr, int nargs, |
617daa0e | 1062 | struct value **args, |
6df2bf50 MS |
1063 | CORE_ADDR sp, int struct_return, |
1064 | CORE_ADDR struct_addr) | |
1065 | { | |
e5e33cd9 CV |
1066 | int stack_offset = 0; |
1067 | int argreg = ARG0_REGNUM; | |
8748518b | 1068 | int flt_argreg = 0; |
6df2bf50 | 1069 | int argnum; |
c055b101 | 1070 | struct type *func_type = value_type (function); |
6df2bf50 MS |
1071 | struct type *type; |
1072 | CORE_ADDR regval; | |
1073 | char *val; | |
8748518b | 1074 | int len, reg_size = 0; |
afce3d2a CV |
1075 | int pass_on_stack = 0; |
1076 | int treat_as_flt; | |
c055b101 CV |
1077 | int last_reg_arg = INT_MAX; |
1078 | ||
1079 | /* The Renesas ABI expects all varargs arguments, plus the last | |
1080 | non-vararg argument to be on the stack, no matter how many | |
1081 | registers have been used so far. */ | |
1082 | if (sh_is_renesas_calling_convention (func_type) | |
1083 | && (TYPE_FLAGS (func_type) & TYPE_FLAG_VARARGS)) | |
1084 | last_reg_arg = TYPE_NFIELDS (func_type) - 2; | |
6df2bf50 MS |
1085 | |
1086 | /* first force sp to a 4-byte alignment */ | |
1087 | sp = sh_frame_align (gdbarch, sp); | |
1088 | ||
e5e33cd9 CV |
1089 | /* make room on stack for args */ |
1090 | sp -= sh_stack_allocsize (nargs, args); | |
1091 | ||
1092 | /* Initialize float argument mechanism. */ | |
1093 | sh_init_flt_argreg (); | |
6df2bf50 MS |
1094 | |
1095 | /* Now load as many as possible of the first arguments into | |
1096 | registers, and push the rest onto the stack. There are 16 bytes | |
1097 | in four registers available. Loop thru args from first to last. */ | |
e5e33cd9 | 1098 | for (argnum = 0; argnum < nargs; argnum++) |
6df2bf50 | 1099 | { |
4991999e | 1100 | type = value_type (args[argnum]); |
6df2bf50 | 1101 | len = TYPE_LENGTH (type); |
d93859e2 | 1102 | val = sh_justify_value_in_reg (gdbarch, args[argnum], len); |
e5e33cd9 CV |
1103 | |
1104 | /* Some decisions have to be made how various types are handled. | |
1105 | This also differs in different ABIs. */ | |
1106 | pass_on_stack = 0; | |
e5e33cd9 CV |
1107 | |
1108 | /* Find out the next register to use for a floating point value. */ | |
afce3d2a CV |
1109 | treat_as_flt = sh_treat_as_flt_p (type); |
1110 | if (treat_as_flt) | |
c055b101 CV |
1111 | flt_argreg = sh_next_flt_argreg (gdbarch, len, func_type); |
1112 | /* In Renesas ABI, long longs and aggregate types are always passed | |
1113 | on stack. */ | |
1114 | else if (sh_is_renesas_calling_convention (func_type) | |
1115 | && ((TYPE_CODE (type) == TYPE_CODE_INT && len == 8) | |
1116 | || TYPE_CODE (type) == TYPE_CODE_STRUCT | |
1117 | || TYPE_CODE (type) == TYPE_CODE_UNION)) | |
1118 | pass_on_stack = 1; | |
afce3d2a CV |
1119 | /* In contrast to non-FPU CPUs, arguments are never split between |
1120 | registers and stack. If an argument doesn't fit in the remaining | |
1121 | registers it's always pushed entirely on the stack. */ | |
1122 | else if (len > ((ARGLAST_REGNUM - argreg + 1) * 4)) | |
1123 | pass_on_stack = 1; | |
48db5a3c | 1124 | |
6df2bf50 MS |
1125 | while (len > 0) |
1126 | { | |
afce3d2a CV |
1127 | if ((treat_as_flt && flt_argreg > FLOAT_ARGLAST_REGNUM) |
1128 | || (!treat_as_flt && (argreg > ARGLAST_REGNUM | |
c055b101 CV |
1129 | || pass_on_stack)) |
1130 | || argnum > last_reg_arg) | |
617daa0e | 1131 | { |
afce3d2a | 1132 | /* The data goes entirely on the stack, 4-byte aligned. */ |
e5e33cd9 CV |
1133 | reg_size = (len + 3) & ~3; |
1134 | write_memory (sp + stack_offset, val, reg_size); | |
1135 | stack_offset += reg_size; | |
6df2bf50 | 1136 | } |
afce3d2a | 1137 | else if (treat_as_flt && flt_argreg <= FLOAT_ARGLAST_REGNUM) |
6df2bf50 | 1138 | { |
e5e33cd9 CV |
1139 | /* Argument goes in a float argument register. */ |
1140 | reg_size = register_size (gdbarch, flt_argreg); | |
1141 | regval = extract_unsigned_integer (val, reg_size); | |
2e952408 CV |
1142 | /* In little endian mode, float types taking two registers |
1143 | (doubles on sh4, long doubles on sh2e, sh3e and sh4) must | |
1144 | be stored swapped in the argument registers. The below | |
1145 | code first writes the first 32 bits in the next but one | |
1146 | register, increments the val and len values accordingly | |
1147 | and then proceeds as normal by writing the second 32 bits | |
1148 | into the next register. */ | |
b47193f7 | 1149 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE |
2e952408 CV |
1150 | && TYPE_LENGTH (type) == 2 * reg_size) |
1151 | { | |
1152 | regcache_cooked_write_unsigned (regcache, flt_argreg + 1, | |
1153 | regval); | |
1154 | val += reg_size; | |
1155 | len -= reg_size; | |
1156 | regval = extract_unsigned_integer (val, reg_size); | |
1157 | } | |
6df2bf50 MS |
1158 | regcache_cooked_write_unsigned (regcache, flt_argreg++, regval); |
1159 | } | |
afce3d2a | 1160 | else if (!treat_as_flt && argreg <= ARGLAST_REGNUM) |
e5e33cd9 | 1161 | { |
6df2bf50 | 1162 | /* there's room in a register */ |
e5e33cd9 CV |
1163 | reg_size = register_size (gdbarch, argreg); |
1164 | regval = extract_unsigned_integer (val, reg_size); | |
6df2bf50 MS |
1165 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
1166 | } | |
afce3d2a | 1167 | /* Store the value one register at a time or in one step on stack. */ |
e5e33cd9 CV |
1168 | len -= reg_size; |
1169 | val += reg_size; | |
6df2bf50 MS |
1170 | } |
1171 | } | |
1172 | ||
c055b101 CV |
1173 | if (struct_return) |
1174 | { | |
1175 | if (sh_is_renesas_calling_convention (func_type)) | |
1176 | /* If the function uses the Renesas ABI, subtract another 4 bytes from | |
1177 | the stack and store the struct return address there. */ | |
1178 | write_memory_unsigned_integer (sp -= 4, 4, struct_addr); | |
1179 | else | |
1180 | /* Using the gcc ABI, the "struct return pointer" pseudo-argument has | |
1181 | its own dedicated register. */ | |
1182 | regcache_cooked_write_unsigned (regcache, | |
1183 | STRUCT_RETURN_REGNUM, struct_addr); | |
1184 | } | |
1185 | ||
6df2bf50 | 1186 | /* Store return address. */ |
55ff77ac | 1187 | regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr); |
6df2bf50 MS |
1188 | |
1189 | /* Update stack pointer. */ | |
3e8c568d | 1190 | regcache_cooked_write_unsigned (regcache, |
b47193f7 | 1191 | gdbarch_sp_regnum (gdbarch), sp); |
6df2bf50 MS |
1192 | |
1193 | return sp; | |
1194 | } | |
1195 | ||
1196 | static CORE_ADDR | |
617daa0e | 1197 | sh_push_dummy_call_nofpu (struct gdbarch *gdbarch, |
7d9b040b | 1198 | struct value *function, |
617daa0e CV |
1199 | struct regcache *regcache, |
1200 | CORE_ADDR bp_addr, | |
1201 | int nargs, struct value **args, | |
1202 | CORE_ADDR sp, int struct_return, | |
6df2bf50 | 1203 | CORE_ADDR struct_addr) |
c906108c | 1204 | { |
e5e33cd9 CV |
1205 | int stack_offset = 0; |
1206 | int argreg = ARG0_REGNUM; | |
c906108c | 1207 | int argnum; |
c055b101 | 1208 | struct type *func_type = value_type (function); |
c906108c SS |
1209 | struct type *type; |
1210 | CORE_ADDR regval; | |
1211 | char *val; | |
c055b101 CV |
1212 | int len, reg_size = 0; |
1213 | int pass_on_stack = 0; | |
1214 | int last_reg_arg = INT_MAX; | |
1215 | ||
1216 | /* The Renesas ABI expects all varargs arguments, plus the last | |
1217 | non-vararg argument to be on the stack, no matter how many | |
1218 | registers have been used so far. */ | |
1219 | if (sh_is_renesas_calling_convention (func_type) | |
1220 | && (TYPE_FLAGS (func_type) & TYPE_FLAG_VARARGS)) | |
1221 | last_reg_arg = TYPE_NFIELDS (func_type) - 2; | |
c906108c SS |
1222 | |
1223 | /* first force sp to a 4-byte alignment */ | |
19f59343 | 1224 | sp = sh_frame_align (gdbarch, sp); |
c906108c | 1225 | |
e5e33cd9 CV |
1226 | /* make room on stack for args */ |
1227 | sp -= sh_stack_allocsize (nargs, args); | |
c906108c | 1228 | |
c906108c SS |
1229 | /* Now load as many as possible of the first arguments into |
1230 | registers, and push the rest onto the stack. There are 16 bytes | |
1231 | in four registers available. Loop thru args from first to last. */ | |
e5e33cd9 | 1232 | for (argnum = 0; argnum < nargs; argnum++) |
617daa0e | 1233 | { |
4991999e | 1234 | type = value_type (args[argnum]); |
c5aa993b | 1235 | len = TYPE_LENGTH (type); |
d93859e2 | 1236 | val = sh_justify_value_in_reg (gdbarch, args[argnum], len); |
c906108c | 1237 | |
c055b101 CV |
1238 | /* Some decisions have to be made how various types are handled. |
1239 | This also differs in different ABIs. */ | |
1240 | pass_on_stack = 0; | |
1241 | /* Renesas ABI pushes doubles and long longs entirely on stack. | |
1242 | Same goes for aggregate types. */ | |
1243 | if (sh_is_renesas_calling_convention (func_type) | |
1244 | && ((TYPE_CODE (type) == TYPE_CODE_INT && len >= 8) | |
1245 | || (TYPE_CODE (type) == TYPE_CODE_FLT && len >= 8) | |
1246 | || TYPE_CODE (type) == TYPE_CODE_STRUCT | |
1247 | || TYPE_CODE (type) == TYPE_CODE_UNION)) | |
1248 | pass_on_stack = 1; | |
c906108c SS |
1249 | while (len > 0) |
1250 | { | |
c055b101 CV |
1251 | if (argreg > ARGLAST_REGNUM || pass_on_stack |
1252 | || argnum > last_reg_arg) | |
617daa0e | 1253 | { |
e5e33cd9 CV |
1254 | /* The remainder of the data goes entirely on the stack, |
1255 | 4-byte aligned. */ | |
1256 | reg_size = (len + 3) & ~3; | |
1257 | write_memory (sp + stack_offset, val, reg_size); | |
617daa0e | 1258 | stack_offset += reg_size; |
c906108c | 1259 | } |
e5e33cd9 | 1260 | else if (argreg <= ARGLAST_REGNUM) |
617daa0e | 1261 | { |
3bbfbb92 | 1262 | /* there's room in a register */ |
e5e33cd9 CV |
1263 | reg_size = register_size (gdbarch, argreg); |
1264 | regval = extract_unsigned_integer (val, reg_size); | |
48db5a3c | 1265 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
c906108c | 1266 | } |
e5e33cd9 CV |
1267 | /* Store the value reg_size bytes at a time. This means that things |
1268 | larger than reg_size bytes may go partly in registers and partly | |
c906108c | 1269 | on the stack. */ |
e5e33cd9 CV |
1270 | len -= reg_size; |
1271 | val += reg_size; | |
c906108c SS |
1272 | } |
1273 | } | |
48db5a3c | 1274 | |
c055b101 CV |
1275 | if (struct_return) |
1276 | { | |
1277 | if (sh_is_renesas_calling_convention (func_type)) | |
1278 | /* If the function uses the Renesas ABI, subtract another 4 bytes from | |
1279 | the stack and store the struct return address there. */ | |
1280 | write_memory_unsigned_integer (sp -= 4, 4, struct_addr); | |
1281 | else | |
1282 | /* Using the gcc ABI, the "struct return pointer" pseudo-argument has | |
1283 | its own dedicated register. */ | |
1284 | regcache_cooked_write_unsigned (regcache, | |
1285 | STRUCT_RETURN_REGNUM, struct_addr); | |
1286 | } | |
1287 | ||
48db5a3c | 1288 | /* Store return address. */ |
55ff77ac | 1289 | regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr); |
48db5a3c CV |
1290 | |
1291 | /* Update stack pointer. */ | |
3e8c568d | 1292 | regcache_cooked_write_unsigned (regcache, |
b47193f7 | 1293 | gdbarch_sp_regnum (gdbarch), sp); |
48db5a3c | 1294 | |
c906108c SS |
1295 | return sp; |
1296 | } | |
1297 | ||
cc17453a EZ |
1298 | /* Find a function's return value in the appropriate registers (in |
1299 | regbuf), and copy it into valbuf. Extract from an array REGBUF | |
1300 | containing the (raw) register state a function return value of type | |
1301 | TYPE, and copy that, in virtual format, into VALBUF. */ | |
1302 | static void | |
3ffc5b9b CV |
1303 | sh_extract_return_value_nofpu (struct type *type, struct regcache *regcache, |
1304 | void *valbuf) | |
c906108c | 1305 | { |
cc17453a | 1306 | int len = TYPE_LENGTH (type); |
3116c80a EZ |
1307 | int return_register = R0_REGNUM; |
1308 | int offset; | |
617daa0e | 1309 | |
cc17453a | 1310 | if (len <= 4) |
3116c80a | 1311 | { |
48db5a3c CV |
1312 | ULONGEST c; |
1313 | ||
1314 | regcache_cooked_read_unsigned (regcache, R0_REGNUM, &c); | |
1315 | store_unsigned_integer (valbuf, len, c); | |
3116c80a | 1316 | } |
48db5a3c | 1317 | else if (len == 8) |
3116c80a | 1318 | { |
48db5a3c CV |
1319 | int i, regnum = R0_REGNUM; |
1320 | for (i = 0; i < len; i += 4) | |
617daa0e | 1321 | regcache_raw_read (regcache, regnum++, (char *) valbuf + i); |
3116c80a EZ |
1322 | } |
1323 | else | |
8a3fe4f8 | 1324 | error (_("bad size for return value")); |
3116c80a EZ |
1325 | } |
1326 | ||
1327 | static void | |
3ffc5b9b CV |
1328 | sh_extract_return_value_fpu (struct type *type, struct regcache *regcache, |
1329 | void *valbuf) | |
3116c80a | 1330 | { |
d93859e2 | 1331 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
afce3d2a | 1332 | if (sh_treat_as_flt_p (type)) |
3116c80a | 1333 | { |
48db5a3c | 1334 | int len = TYPE_LENGTH (type); |
d93859e2 | 1335 | int i, regnum = gdbarch_fp0_regnum (gdbarch); |
48db5a3c | 1336 | for (i = 0; i < len; i += 4) |
d93859e2 | 1337 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) |
2e952408 CV |
1338 | regcache_raw_read (regcache, regnum++, (char *) valbuf + len - 4 - i); |
1339 | else | |
1340 | regcache_raw_read (regcache, regnum++, (char *) valbuf + i); | |
3116c80a | 1341 | } |
cc17453a | 1342 | else |
3ffc5b9b | 1343 | sh_extract_return_value_nofpu (type, regcache, valbuf); |
cc17453a | 1344 | } |
c906108c | 1345 | |
cc17453a EZ |
1346 | /* Write into appropriate registers a function return value |
1347 | of type TYPE, given in virtual format. | |
1348 | If the architecture is sh4 or sh3e, store a function's return value | |
1349 | in the R0 general register or in the FP0 floating point register, | |
1350 | depending on the type of the return value. In all the other cases | |
3bbfbb92 | 1351 | the result is stored in r0, left-justified. */ |
cc17453a | 1352 | static void |
3ffc5b9b CV |
1353 | sh_store_return_value_nofpu (struct type *type, struct regcache *regcache, |
1354 | const void *valbuf) | |
cc17453a | 1355 | { |
48db5a3c CV |
1356 | ULONGEST val; |
1357 | int len = TYPE_LENGTH (type); | |
d19b71be | 1358 | |
48db5a3c | 1359 | if (len <= 4) |
d19b71be | 1360 | { |
48db5a3c CV |
1361 | val = extract_unsigned_integer (valbuf, len); |
1362 | regcache_cooked_write_unsigned (regcache, R0_REGNUM, val); | |
d19b71be MS |
1363 | } |
1364 | else | |
48db5a3c CV |
1365 | { |
1366 | int i, regnum = R0_REGNUM; | |
1367 | for (i = 0; i < len; i += 4) | |
617daa0e | 1368 | regcache_raw_write (regcache, regnum++, (char *) valbuf + i); |
48db5a3c | 1369 | } |
cc17453a | 1370 | } |
c906108c | 1371 | |
cc17453a | 1372 | static void |
3ffc5b9b CV |
1373 | sh_store_return_value_fpu (struct type *type, struct regcache *regcache, |
1374 | const void *valbuf) | |
cc17453a | 1375 | { |
d93859e2 | 1376 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
afce3d2a | 1377 | if (sh_treat_as_flt_p (type)) |
48db5a3c CV |
1378 | { |
1379 | int len = TYPE_LENGTH (type); | |
d93859e2 | 1380 | int i, regnum = gdbarch_fp0_regnum (gdbarch); |
48db5a3c | 1381 | for (i = 0; i < len; i += 4) |
d93859e2 | 1382 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) |
c8a3b559 CV |
1383 | regcache_raw_write (regcache, regnum++, |
1384 | (char *) valbuf + len - 4 - i); | |
1385 | else | |
1386 | regcache_raw_write (regcache, regnum++, (char *) valbuf + i); | |
48db5a3c | 1387 | } |
cc17453a | 1388 | else |
3ffc5b9b | 1389 | sh_store_return_value_nofpu (type, regcache, valbuf); |
c906108c SS |
1390 | } |
1391 | ||
c0409442 | 1392 | static enum return_value_convention |
c055b101 CV |
1393 | sh_return_value_nofpu (struct gdbarch *gdbarch, struct type *func_type, |
1394 | struct type *type, struct regcache *regcache, | |
18cf8b5b | 1395 | gdb_byte *readbuf, const gdb_byte *writebuf) |
c0409442 | 1396 | { |
c055b101 CV |
1397 | if (sh_use_struct_convention_nofpu ( |
1398 | sh_is_renesas_calling_convention (func_type), type)) | |
c0409442 CV |
1399 | return RETURN_VALUE_STRUCT_CONVENTION; |
1400 | if (writebuf) | |
3ffc5b9b | 1401 | sh_store_return_value_nofpu (type, regcache, writebuf); |
c0409442 | 1402 | else if (readbuf) |
3ffc5b9b | 1403 | sh_extract_return_value_nofpu (type, regcache, readbuf); |
c0409442 CV |
1404 | return RETURN_VALUE_REGISTER_CONVENTION; |
1405 | } | |
1406 | ||
1407 | static enum return_value_convention | |
c055b101 CV |
1408 | sh_return_value_fpu (struct gdbarch *gdbarch, struct type *func_type, |
1409 | struct type *type, struct regcache *regcache, | |
18cf8b5b | 1410 | gdb_byte *readbuf, const gdb_byte *writebuf) |
c0409442 | 1411 | { |
c055b101 CV |
1412 | if (sh_use_struct_convention ( |
1413 | sh_is_renesas_calling_convention (func_type), type)) | |
c0409442 CV |
1414 | return RETURN_VALUE_STRUCT_CONVENTION; |
1415 | if (writebuf) | |
3ffc5b9b | 1416 | sh_store_return_value_fpu (type, regcache, writebuf); |
c0409442 | 1417 | else if (readbuf) |
3ffc5b9b | 1418 | sh_extract_return_value_fpu (type, regcache, readbuf); |
c0409442 CV |
1419 | return RETURN_VALUE_REGISTER_CONVENTION; |
1420 | } | |
1421 | ||
c906108c SS |
1422 | /* Print the registers in a form similar to the E7000 */ |
1423 | ||
1424 | static void | |
c458d6db | 1425 | sh_generic_show_regs (struct frame_info *frame) |
c906108c | 1426 | { |
c458d6db UW |
1427 | printf_filtered |
1428 | (" PC %s SR %08lx PR %08lx MACH %08lx\n", | |
3e8c568d | 1429 | paddr (get_frame_register_unsigned (frame, |
b47193f7 UW |
1430 | gdbarch_pc_regnum |
1431 | (get_frame_arch (frame)))), | |
c458d6db UW |
1432 | (long) get_frame_register_unsigned (frame, SR_REGNUM), |
1433 | (long) get_frame_register_unsigned (frame, PR_REGNUM), | |
1434 | (long) get_frame_register_unsigned (frame, MACH_REGNUM)); | |
cc17453a | 1435 | |
c458d6db UW |
1436 | printf_filtered |
1437 | (" GBR %08lx VBR %08lx MACL %08lx\n", | |
1438 | (long) get_frame_register_unsigned (frame, GBR_REGNUM), | |
1439 | (long) get_frame_register_unsigned (frame, VBR_REGNUM), | |
1440 | (long) get_frame_register_unsigned (frame, MACL_REGNUM)); | |
cc17453a | 1441 | |
617daa0e | 1442 | printf_filtered |
a6b0a3f3 | 1443 | ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
c458d6db UW |
1444 | (long) get_frame_register_unsigned (frame, 0), |
1445 | (long) get_frame_register_unsigned (frame, 1), | |
1446 | (long) get_frame_register_unsigned (frame, 2), | |
1447 | (long) get_frame_register_unsigned (frame, 3), | |
1448 | (long) get_frame_register_unsigned (frame, 4), | |
1449 | (long) get_frame_register_unsigned (frame, 5), | |
1450 | (long) get_frame_register_unsigned (frame, 6), | |
1451 | (long) get_frame_register_unsigned (frame, 7)); | |
1452 | printf_filtered | |
1453 | ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1454 | (long) get_frame_register_unsigned (frame, 8), | |
1455 | (long) get_frame_register_unsigned (frame, 9), | |
1456 | (long) get_frame_register_unsigned (frame, 10), | |
1457 | (long) get_frame_register_unsigned (frame, 11), | |
1458 | (long) get_frame_register_unsigned (frame, 12), | |
1459 | (long) get_frame_register_unsigned (frame, 13), | |
1460 | (long) get_frame_register_unsigned (frame, 14), | |
1461 | (long) get_frame_register_unsigned (frame, 15)); | |
cc17453a | 1462 | } |
c906108c | 1463 | |
cc17453a | 1464 | static void |
c458d6db | 1465 | sh3_show_regs (struct frame_info *frame) |
cc17453a | 1466 | { |
c458d6db UW |
1467 | printf_filtered |
1468 | (" PC %s SR %08lx PR %08lx MACH %08lx\n", | |
3e8c568d | 1469 | paddr (get_frame_register_unsigned (frame, |
b47193f7 UW |
1470 | gdbarch_pc_regnum |
1471 | (get_frame_arch (frame)))), | |
c458d6db UW |
1472 | (long) get_frame_register_unsigned (frame, SR_REGNUM), |
1473 | (long) get_frame_register_unsigned (frame, PR_REGNUM), | |
1474 | (long) get_frame_register_unsigned (frame, MACH_REGNUM)); | |
1475 | ||
1476 | printf_filtered | |
1477 | (" GBR %08lx VBR %08lx MACL %08lx\n", | |
1478 | (long) get_frame_register_unsigned (frame, GBR_REGNUM), | |
1479 | (long) get_frame_register_unsigned (frame, VBR_REGNUM), | |
1480 | (long) get_frame_register_unsigned (frame, MACL_REGNUM)); | |
1481 | printf_filtered | |
1482 | (" SSR %08lx SPC %08lx\n", | |
1483 | (long) get_frame_register_unsigned (frame, SSR_REGNUM), | |
1484 | (long) get_frame_register_unsigned (frame, SPC_REGNUM)); | |
c906108c | 1485 | |
617daa0e | 1486 | printf_filtered |
a6b0a3f3 | 1487 | ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
c458d6db UW |
1488 | (long) get_frame_register_unsigned (frame, 0), |
1489 | (long) get_frame_register_unsigned (frame, 1), | |
1490 | (long) get_frame_register_unsigned (frame, 2), | |
1491 | (long) get_frame_register_unsigned (frame, 3), | |
1492 | (long) get_frame_register_unsigned (frame, 4), | |
1493 | (long) get_frame_register_unsigned (frame, 5), | |
1494 | (long) get_frame_register_unsigned (frame, 6), | |
1495 | (long) get_frame_register_unsigned (frame, 7)); | |
1496 | printf_filtered | |
1497 | ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1498 | (long) get_frame_register_unsigned (frame, 8), | |
1499 | (long) get_frame_register_unsigned (frame, 9), | |
1500 | (long) get_frame_register_unsigned (frame, 10), | |
1501 | (long) get_frame_register_unsigned (frame, 11), | |
1502 | (long) get_frame_register_unsigned (frame, 12), | |
1503 | (long) get_frame_register_unsigned (frame, 13), | |
1504 | (long) get_frame_register_unsigned (frame, 14), | |
1505 | (long) get_frame_register_unsigned (frame, 15)); | |
c906108c SS |
1506 | } |
1507 | ||
2d188dd3 | 1508 | static void |
c458d6db | 1509 | sh2e_show_regs (struct frame_info *frame) |
2d188dd3 | 1510 | { |
b47193f7 | 1511 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c458d6db UW |
1512 | printf_filtered |
1513 | (" PC %s SR %08lx PR %08lx MACH %08lx\n", | |
3e8c568d | 1514 | paddr (get_frame_register_unsigned (frame, |
b47193f7 | 1515 | gdbarch_pc_regnum (gdbarch))), |
c458d6db UW |
1516 | (long) get_frame_register_unsigned (frame, SR_REGNUM), |
1517 | (long) get_frame_register_unsigned (frame, PR_REGNUM), | |
1518 | (long) get_frame_register_unsigned (frame, MACH_REGNUM)); | |
1519 | ||
1520 | printf_filtered | |
1521 | (" GBR %08lx VBR %08lx MACL %08lx\n", | |
1522 | (long) get_frame_register_unsigned (frame, GBR_REGNUM), | |
1523 | (long) get_frame_register_unsigned (frame, VBR_REGNUM), | |
1524 | (long) get_frame_register_unsigned (frame, MACL_REGNUM)); | |
1525 | printf_filtered | |
1526 | (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n", | |
1527 | (long) get_frame_register_unsigned (frame, SSR_REGNUM), | |
1528 | (long) get_frame_register_unsigned (frame, SPC_REGNUM), | |
1529 | (long) get_frame_register_unsigned (frame, FPUL_REGNUM), | |
1530 | (long) get_frame_register_unsigned (frame, FPSCR_REGNUM)); | |
617daa0e CV |
1531 | |
1532 | printf_filtered | |
a6b0a3f3 | 1533 | ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
c458d6db UW |
1534 | (long) get_frame_register_unsigned (frame, 0), |
1535 | (long) get_frame_register_unsigned (frame, 1), | |
1536 | (long) get_frame_register_unsigned (frame, 2), | |
1537 | (long) get_frame_register_unsigned (frame, 3), | |
1538 | (long) get_frame_register_unsigned (frame, 4), | |
1539 | (long) get_frame_register_unsigned (frame, 5), | |
1540 | (long) get_frame_register_unsigned (frame, 6), | |
1541 | (long) get_frame_register_unsigned (frame, 7)); | |
1542 | printf_filtered | |
1543 | ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1544 | (long) get_frame_register_unsigned (frame, 8), | |
1545 | (long) get_frame_register_unsigned (frame, 9), | |
1546 | (long) get_frame_register_unsigned (frame, 10), | |
1547 | (long) get_frame_register_unsigned (frame, 11), | |
1548 | (long) get_frame_register_unsigned (frame, 12), | |
1549 | (long) get_frame_register_unsigned (frame, 13), | |
1550 | (long) get_frame_register_unsigned (frame, 14), | |
1551 | (long) get_frame_register_unsigned (frame, 15)); | |
1552 | ||
1553 | printf_filtered | |
1554 | ("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
3e8c568d | 1555 | (long) get_frame_register_unsigned |
b47193f7 | 1556 | (frame, gdbarch_fp0_regnum (gdbarch) + 0), |
3e8c568d | 1557 | (long) get_frame_register_unsigned |
b47193f7 | 1558 | (frame, gdbarch_fp0_regnum (gdbarch) + 1), |
3e8c568d | 1559 | (long) get_frame_register_unsigned |
b47193f7 | 1560 | (frame, gdbarch_fp0_regnum (gdbarch) + 2), |
3e8c568d | 1561 | (long) get_frame_register_unsigned |
b47193f7 | 1562 | (frame, gdbarch_fp0_regnum (gdbarch) + 3), |
3e8c568d | 1563 | (long) get_frame_register_unsigned |
b47193f7 | 1564 | (frame, gdbarch_fp0_regnum (gdbarch) + 4), |
3e8c568d | 1565 | (long) get_frame_register_unsigned |
b47193f7 | 1566 | (frame, gdbarch_fp0_regnum (gdbarch) + 5), |
3e8c568d | 1567 | (long) get_frame_register_unsigned |
b47193f7 | 1568 | (frame, gdbarch_fp0_regnum (gdbarch) + 6), |
3e8c568d | 1569 | (long) get_frame_register_unsigned |
b47193f7 | 1570 | (frame, gdbarch_fp0_regnum (gdbarch) + 7)); |
c458d6db UW |
1571 | printf_filtered |
1572 | ("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
3e8c568d | 1573 | (long) get_frame_register_unsigned |
b47193f7 | 1574 | (frame, gdbarch_fp0_regnum (gdbarch) + 8), |
3e8c568d | 1575 | (long) get_frame_register_unsigned |
b47193f7 | 1576 | (frame, gdbarch_fp0_regnum (gdbarch) + 9), |
3e8c568d | 1577 | (long) get_frame_register_unsigned |
b47193f7 | 1578 | (frame, gdbarch_fp0_regnum (gdbarch) + 10), |
3e8c568d | 1579 | (long) get_frame_register_unsigned |
b47193f7 | 1580 | (frame, gdbarch_fp0_regnum (gdbarch) + 11), |
3e8c568d | 1581 | (long) get_frame_register_unsigned |
b47193f7 | 1582 | (frame, gdbarch_fp0_regnum (gdbarch) + 12), |
3e8c568d | 1583 | (long) get_frame_register_unsigned |
b47193f7 | 1584 | (frame, gdbarch_fp0_regnum (gdbarch) + 13), |
3e8c568d | 1585 | (long) get_frame_register_unsigned |
b47193f7 | 1586 | (frame, gdbarch_fp0_regnum (gdbarch) + 14), |
3e8c568d | 1587 | (long) get_frame_register_unsigned |
b47193f7 | 1588 | (frame, gdbarch_fp0_regnum (gdbarch) + 15)); |
2d188dd3 NC |
1589 | } |
1590 | ||
da962468 | 1591 | static void |
c458d6db | 1592 | sh2a_show_regs (struct frame_info *frame) |
da962468 | 1593 | { |
b47193f7 | 1594 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c458d6db UW |
1595 | int pr = get_frame_register_unsigned (frame, FPSCR_REGNUM) & 0x80000; |
1596 | ||
1597 | printf_filtered | |
1598 | (" PC %s SR %08lx PR %08lx MACH %08lx\n", | |
3e8c568d | 1599 | paddr (get_frame_register_unsigned (frame, |
b47193f7 | 1600 | gdbarch_pc_regnum (gdbarch))), |
c458d6db UW |
1601 | (long) get_frame_register_unsigned (frame, SR_REGNUM), |
1602 | (long) get_frame_register_unsigned (frame, PR_REGNUM), | |
1603 | (long) get_frame_register_unsigned (frame, MACH_REGNUM)); | |
1604 | ||
1605 | printf_filtered | |
1606 | (" GBR %08lx VBR %08lx TBR %08lx MACL %08lx\n", | |
1607 | (long) get_frame_register_unsigned (frame, GBR_REGNUM), | |
1608 | (long) get_frame_register_unsigned (frame, VBR_REGNUM), | |
1609 | (long) get_frame_register_unsigned (frame, TBR_REGNUM), | |
1610 | (long) get_frame_register_unsigned (frame, MACL_REGNUM)); | |
1611 | printf_filtered | |
1612 | (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n", | |
1613 | (long) get_frame_register_unsigned (frame, SSR_REGNUM), | |
1614 | (long) get_frame_register_unsigned (frame, SPC_REGNUM), | |
1615 | (long) get_frame_register_unsigned (frame, FPUL_REGNUM), | |
1616 | (long) get_frame_register_unsigned (frame, FPSCR_REGNUM)); | |
1617 | ||
1618 | printf_filtered | |
1619 | ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1620 | (long) get_frame_register_unsigned (frame, 0), | |
1621 | (long) get_frame_register_unsigned (frame, 1), | |
1622 | (long) get_frame_register_unsigned (frame, 2), | |
1623 | (long) get_frame_register_unsigned (frame, 3), | |
1624 | (long) get_frame_register_unsigned (frame, 4), | |
1625 | (long) get_frame_register_unsigned (frame, 5), | |
1626 | (long) get_frame_register_unsigned (frame, 6), | |
1627 | (long) get_frame_register_unsigned (frame, 7)); | |
1628 | printf_filtered | |
1629 | ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1630 | (long) get_frame_register_unsigned (frame, 8), | |
1631 | (long) get_frame_register_unsigned (frame, 9), | |
1632 | (long) get_frame_register_unsigned (frame, 10), | |
1633 | (long) get_frame_register_unsigned (frame, 11), | |
1634 | (long) get_frame_register_unsigned (frame, 12), | |
1635 | (long) get_frame_register_unsigned (frame, 13), | |
1636 | (long) get_frame_register_unsigned (frame, 14), | |
1637 | (long) get_frame_register_unsigned (frame, 15)); | |
1638 | ||
1639 | printf_filtered | |
1640 | (pr ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n" | |
1641 | : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
3e8c568d | 1642 | (long) get_frame_register_unsigned |
b47193f7 | 1643 | (frame, gdbarch_fp0_regnum (gdbarch) + 0), |
3e8c568d | 1644 | (long) get_frame_register_unsigned |
b47193f7 | 1645 | (frame, gdbarch_fp0_regnum (gdbarch) + 1), |
3e8c568d | 1646 | (long) get_frame_register_unsigned |
b47193f7 | 1647 | (frame, gdbarch_fp0_regnum (gdbarch) + 2), |
3e8c568d | 1648 | (long) get_frame_register_unsigned |
b47193f7 | 1649 | (frame, gdbarch_fp0_regnum (gdbarch) + 3), |
3e8c568d | 1650 | (long) get_frame_register_unsigned |
b47193f7 | 1651 | (frame, gdbarch_fp0_regnum (gdbarch) + 4), |
3e8c568d | 1652 | (long) get_frame_register_unsigned |
b47193f7 | 1653 | (frame, gdbarch_fp0_regnum (gdbarch) + 5), |
3e8c568d | 1654 | (long) get_frame_register_unsigned |
b47193f7 | 1655 | (frame, gdbarch_fp0_regnum (gdbarch) + 6), |
3e8c568d | 1656 | (long) get_frame_register_unsigned |
b47193f7 | 1657 | (frame, gdbarch_fp0_regnum (gdbarch) + 7)); |
c458d6db UW |
1658 | printf_filtered |
1659 | (pr ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n" | |
1660 | : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
3e8c568d | 1661 | (long) get_frame_register_unsigned |
b47193f7 | 1662 | (frame, gdbarch_fp0_regnum (gdbarch) + 8), |
3e8c568d | 1663 | (long) get_frame_register_unsigned |
b47193f7 | 1664 | (frame, gdbarch_fp0_regnum (gdbarch) + 9), |
3e8c568d | 1665 | (long) get_frame_register_unsigned |
b47193f7 | 1666 | (frame, gdbarch_fp0_regnum (gdbarch) + 10), |
3e8c568d | 1667 | (long) get_frame_register_unsigned |
b47193f7 | 1668 | (frame, gdbarch_fp0_regnum (gdbarch) + 11), |
3e8c568d | 1669 | (long) get_frame_register_unsigned |
b47193f7 | 1670 | (frame, gdbarch_fp0_regnum (gdbarch) + 12), |
3e8c568d | 1671 | (long) get_frame_register_unsigned |
b47193f7 | 1672 | (frame, gdbarch_fp0_regnum (gdbarch) + 13), |
3e8c568d | 1673 | (long) get_frame_register_unsigned |
b47193f7 | 1674 | (frame, gdbarch_fp0_regnum (gdbarch) + 14), |
3e8c568d | 1675 | (long) get_frame_register_unsigned |
b47193f7 | 1676 | (frame, gdbarch_fp0_regnum (gdbarch) + 15)); |
c458d6db UW |
1677 | printf_filtered |
1678 | ("BANK=%-3d\n", (int) get_frame_register_unsigned (frame, BANK_REGNUM)); | |
1679 | printf_filtered | |
1680 | ("R0b-R7b %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1681 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 0), | |
1682 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 1), | |
1683 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 2), | |
1684 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 3), | |
1685 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 4), | |
1686 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 5), | |
1687 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 6), | |
1688 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 7)); | |
1689 | printf_filtered | |
1690 | ("R8b-R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1691 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 8), | |
1692 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 9), | |
1693 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 10), | |
1694 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 11), | |
1695 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 12), | |
1696 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 13), | |
1697 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 14)); | |
1698 | printf_filtered | |
1699 | ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n", | |
1700 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 15), | |
1701 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 16), | |
1702 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 17), | |
1703 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 18), | |
1704 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 19)); | |
da962468 CV |
1705 | } |
1706 | ||
1707 | static void | |
c458d6db | 1708 | sh2a_nofpu_show_regs (struct frame_info *frame) |
da962468 | 1709 | { |
c458d6db UW |
1710 | int pr = get_frame_register_unsigned (frame, FPSCR_REGNUM) & 0x80000; |
1711 | ||
1712 | printf_filtered | |
1713 | (" PC %s SR %08lx PR %08lx MACH %08lx\n", | |
3e8c568d | 1714 | paddr (get_frame_register_unsigned (frame, |
b47193f7 UW |
1715 | gdbarch_pc_regnum |
1716 | (get_frame_arch (frame)))), | |
c458d6db UW |
1717 | (long) get_frame_register_unsigned (frame, SR_REGNUM), |
1718 | (long) get_frame_register_unsigned (frame, PR_REGNUM), | |
1719 | (long) get_frame_register_unsigned (frame, MACH_REGNUM)); | |
1720 | ||
1721 | printf_filtered | |
1722 | (" GBR %08lx VBR %08lx TBR %08lx MACL %08lx\n", | |
1723 | (long) get_frame_register_unsigned (frame, GBR_REGNUM), | |
1724 | (long) get_frame_register_unsigned (frame, VBR_REGNUM), | |
1725 | (long) get_frame_register_unsigned (frame, TBR_REGNUM), | |
1726 | (long) get_frame_register_unsigned (frame, MACL_REGNUM)); | |
1727 | printf_filtered | |
1728 | (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n", | |
1729 | (long) get_frame_register_unsigned (frame, SSR_REGNUM), | |
1730 | (long) get_frame_register_unsigned (frame, SPC_REGNUM), | |
1731 | (long) get_frame_register_unsigned (frame, FPUL_REGNUM), | |
1732 | (long) get_frame_register_unsigned (frame, FPSCR_REGNUM)); | |
1733 | ||
1734 | printf_filtered | |
1735 | ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1736 | (long) get_frame_register_unsigned (frame, 0), | |
1737 | (long) get_frame_register_unsigned (frame, 1), | |
1738 | (long) get_frame_register_unsigned (frame, 2), | |
1739 | (long) get_frame_register_unsigned (frame, 3), | |
1740 | (long) get_frame_register_unsigned (frame, 4), | |
1741 | (long) get_frame_register_unsigned (frame, 5), | |
1742 | (long) get_frame_register_unsigned (frame, 6), | |
1743 | (long) get_frame_register_unsigned (frame, 7)); | |
1744 | printf_filtered | |
1745 | ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1746 | (long) get_frame_register_unsigned (frame, 8), | |
1747 | (long) get_frame_register_unsigned (frame, 9), | |
1748 | (long) get_frame_register_unsigned (frame, 10), | |
1749 | (long) get_frame_register_unsigned (frame, 11), | |
1750 | (long) get_frame_register_unsigned (frame, 12), | |
1751 | (long) get_frame_register_unsigned (frame, 13), | |
1752 | (long) get_frame_register_unsigned (frame, 14), | |
1753 | (long) get_frame_register_unsigned (frame, 15)); | |
1754 | ||
1755 | printf_filtered | |
1756 | ("BANK=%-3d\n", (int) get_frame_register_unsigned (frame, BANK_REGNUM)); | |
1757 | printf_filtered | |
1758 | ("R0b-R7b %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1759 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 0), | |
1760 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 1), | |
1761 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 2), | |
1762 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 3), | |
1763 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 4), | |
1764 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 5), | |
1765 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 6), | |
1766 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 7)); | |
1767 | printf_filtered | |
1768 | ("R8b-R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1769 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 8), | |
1770 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 9), | |
1771 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 10), | |
1772 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 11), | |
1773 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 12), | |
1774 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 13), | |
1775 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 14)); | |
1776 | printf_filtered | |
1777 | ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n", | |
1778 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 15), | |
1779 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 16), | |
1780 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 17), | |
1781 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 18), | |
1782 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 19)); | |
da962468 CV |
1783 | } |
1784 | ||
cc17453a | 1785 | static void |
c458d6db | 1786 | sh3e_show_regs (struct frame_info *frame) |
cc17453a | 1787 | { |
b47193f7 | 1788 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c458d6db UW |
1789 | printf_filtered |
1790 | (" PC %s SR %08lx PR %08lx MACH %08lx\n", | |
3e8c568d | 1791 | paddr (get_frame_register_unsigned (frame, |
b47193f7 | 1792 | gdbarch_pc_regnum (gdbarch))), |
c458d6db UW |
1793 | (long) get_frame_register_unsigned (frame, SR_REGNUM), |
1794 | (long) get_frame_register_unsigned (frame, PR_REGNUM), | |
1795 | (long) get_frame_register_unsigned (frame, MACH_REGNUM)); | |
1796 | ||
1797 | printf_filtered | |
1798 | (" GBR %08lx VBR %08lx MACL %08lx\n", | |
1799 | (long) get_frame_register_unsigned (frame, GBR_REGNUM), | |
1800 | (long) get_frame_register_unsigned (frame, VBR_REGNUM), | |
1801 | (long) get_frame_register_unsigned (frame, MACL_REGNUM)); | |
1802 | printf_filtered | |
1803 | (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n", | |
1804 | (long) get_frame_register_unsigned (frame, SSR_REGNUM), | |
1805 | (long) get_frame_register_unsigned (frame, SPC_REGNUM), | |
1806 | (long) get_frame_register_unsigned (frame, FPUL_REGNUM), | |
1807 | (long) get_frame_register_unsigned (frame, FPSCR_REGNUM)); | |
c906108c | 1808 | |
617daa0e | 1809 | printf_filtered |
a6b0a3f3 | 1810 | ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
c458d6db UW |
1811 | (long) get_frame_register_unsigned (frame, 0), |
1812 | (long) get_frame_register_unsigned (frame, 1), | |
1813 | (long) get_frame_register_unsigned (frame, 2), | |
1814 | (long) get_frame_register_unsigned (frame, 3), | |
1815 | (long) get_frame_register_unsigned (frame, 4), | |
1816 | (long) get_frame_register_unsigned (frame, 5), | |
1817 | (long) get_frame_register_unsigned (frame, 6), | |
1818 | (long) get_frame_register_unsigned (frame, 7)); | |
1819 | printf_filtered | |
1820 | ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1821 | (long) get_frame_register_unsigned (frame, 8), | |
1822 | (long) get_frame_register_unsigned (frame, 9), | |
1823 | (long) get_frame_register_unsigned (frame, 10), | |
1824 | (long) get_frame_register_unsigned (frame, 11), | |
1825 | (long) get_frame_register_unsigned (frame, 12), | |
1826 | (long) get_frame_register_unsigned (frame, 13), | |
1827 | (long) get_frame_register_unsigned (frame, 14), | |
1828 | (long) get_frame_register_unsigned (frame, 15)); | |
1829 | ||
1830 | printf_filtered | |
1831 | ("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
3e8c568d | 1832 | (long) get_frame_register_unsigned |
b47193f7 | 1833 | (frame, gdbarch_fp0_regnum (gdbarch) + 0), |
3e8c568d | 1834 | (long) get_frame_register_unsigned |
b47193f7 | 1835 | (frame, gdbarch_fp0_regnum (gdbarch) + 1), |
3e8c568d | 1836 | (long) get_frame_register_unsigned |
b47193f7 | 1837 | (frame, gdbarch_fp0_regnum (gdbarch) + 2), |
3e8c568d | 1838 | (long) get_frame_register_unsigned |
b47193f7 | 1839 | (frame, gdbarch_fp0_regnum (gdbarch) + 3), |
3e8c568d | 1840 | (long) get_frame_register_unsigned |
b47193f7 | 1841 | (frame, gdbarch_fp0_regnum (gdbarch) + 4), |
3e8c568d | 1842 | (long) get_frame_register_unsigned |
b47193f7 | 1843 | (frame, gdbarch_fp0_regnum (gdbarch) + 5), |
3e8c568d | 1844 | (long) get_frame_register_unsigned |
b47193f7 | 1845 | (frame, gdbarch_fp0_regnum (gdbarch) + 6), |
3e8c568d | 1846 | (long) get_frame_register_unsigned |
b47193f7 | 1847 | (frame, gdbarch_fp0_regnum (gdbarch) + 7)); |
c458d6db UW |
1848 | printf_filtered |
1849 | ("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
3e8c568d | 1850 | (long) get_frame_register_unsigned |
b47193f7 | 1851 | (frame, gdbarch_fp0_regnum (gdbarch) + 8), |
3e8c568d | 1852 | (long) get_frame_register_unsigned |
b47193f7 | 1853 | (frame, gdbarch_fp0_regnum (gdbarch) + 9), |
3e8c568d | 1854 | (long) get_frame_register_unsigned |
b47193f7 | 1855 | (frame, gdbarch_fp0_regnum (gdbarch) + 10), |
3e8c568d | 1856 | (long) get_frame_register_unsigned |
b47193f7 | 1857 | (frame, gdbarch_fp0_regnum (gdbarch) + 11), |
3e8c568d | 1858 | (long) get_frame_register_unsigned |
b47193f7 | 1859 | (frame, gdbarch_fp0_regnum (gdbarch) + 12), |
3e8c568d | 1860 | (long) get_frame_register_unsigned |
b47193f7 | 1861 | (frame, gdbarch_fp0_regnum (gdbarch) + 13), |
3e8c568d | 1862 | (long) get_frame_register_unsigned |
b47193f7 | 1863 | (frame, gdbarch_fp0_regnum (gdbarch) + 14), |
3e8c568d | 1864 | (long) get_frame_register_unsigned |
b47193f7 | 1865 | (frame, gdbarch_fp0_regnum (gdbarch) + 15)); |
cc17453a EZ |
1866 | } |
1867 | ||
1868 | static void | |
c458d6db | 1869 | sh3_dsp_show_regs (struct frame_info *frame) |
c906108c | 1870 | { |
c458d6db UW |
1871 | printf_filtered |
1872 | (" PC %s SR %08lx PR %08lx MACH %08lx\n", | |
3e8c568d | 1873 | paddr (get_frame_register_unsigned (frame, |
b47193f7 UW |
1874 | gdbarch_pc_regnum |
1875 | (get_frame_arch (frame)))), | |
c458d6db UW |
1876 | (long) get_frame_register_unsigned (frame, SR_REGNUM), |
1877 | (long) get_frame_register_unsigned (frame, PR_REGNUM), | |
1878 | (long) get_frame_register_unsigned (frame, MACH_REGNUM)); | |
c906108c | 1879 | |
c458d6db UW |
1880 | printf_filtered |
1881 | (" GBR %08lx VBR %08lx MACL %08lx\n", | |
1882 | (long) get_frame_register_unsigned (frame, GBR_REGNUM), | |
1883 | (long) get_frame_register_unsigned (frame, VBR_REGNUM), | |
1884 | (long) get_frame_register_unsigned (frame, MACL_REGNUM)); | |
cc17453a | 1885 | |
c458d6db UW |
1886 | printf_filtered |
1887 | (" SSR %08lx SPC %08lx DSR %08lx\n", | |
1888 | (long) get_frame_register_unsigned (frame, SSR_REGNUM), | |
1889 | (long) get_frame_register_unsigned (frame, SPC_REGNUM), | |
1890 | (long) get_frame_register_unsigned (frame, DSR_REGNUM)); | |
617daa0e CV |
1891 | |
1892 | printf_filtered | |
a6b0a3f3 | 1893 | ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
c458d6db UW |
1894 | (long) get_frame_register_unsigned (frame, 0), |
1895 | (long) get_frame_register_unsigned (frame, 1), | |
1896 | (long) get_frame_register_unsigned (frame, 2), | |
1897 | (long) get_frame_register_unsigned (frame, 3), | |
1898 | (long) get_frame_register_unsigned (frame, 4), | |
1899 | (long) get_frame_register_unsigned (frame, 5), | |
1900 | (long) get_frame_register_unsigned (frame, 6), | |
1901 | (long) get_frame_register_unsigned (frame, 7)); | |
1902 | printf_filtered | |
1903 | ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1904 | (long) get_frame_register_unsigned (frame, 8), | |
1905 | (long) get_frame_register_unsigned (frame, 9), | |
1906 | (long) get_frame_register_unsigned (frame, 10), | |
1907 | (long) get_frame_register_unsigned (frame, 11), | |
1908 | (long) get_frame_register_unsigned (frame, 12), | |
1909 | (long) get_frame_register_unsigned (frame, 13), | |
1910 | (long) get_frame_register_unsigned (frame, 14), | |
1911 | (long) get_frame_register_unsigned (frame, 15)); | |
617daa0e CV |
1912 | |
1913 | printf_filtered | |
1914 | ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n", | |
c458d6db UW |
1915 | (long) get_frame_register_unsigned (frame, A0G_REGNUM) & 0xff, |
1916 | (long) get_frame_register_unsigned (frame, A0_REGNUM), | |
1917 | (long) get_frame_register_unsigned (frame, M0_REGNUM), | |
1918 | (long) get_frame_register_unsigned (frame, X0_REGNUM), | |
1919 | (long) get_frame_register_unsigned (frame, Y0_REGNUM), | |
1920 | (long) get_frame_register_unsigned (frame, RS_REGNUM), | |
1921 | (long) get_frame_register_unsigned (frame, MOD_REGNUM)); | |
1922 | printf_filtered | |
1923 | ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n", | |
1924 | (long) get_frame_register_unsigned (frame, A1G_REGNUM) & 0xff, | |
1925 | (long) get_frame_register_unsigned (frame, A1_REGNUM), | |
1926 | (long) get_frame_register_unsigned (frame, M1_REGNUM), | |
1927 | (long) get_frame_register_unsigned (frame, X1_REGNUM), | |
1928 | (long) get_frame_register_unsigned (frame, Y1_REGNUM), | |
1929 | (long) get_frame_register_unsigned (frame, RE_REGNUM)); | |
c906108c SS |
1930 | } |
1931 | ||
cc17453a | 1932 | static void |
c458d6db | 1933 | sh4_show_regs (struct frame_info *frame) |
cc17453a | 1934 | { |
b47193f7 | 1935 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c458d6db UW |
1936 | int pr = get_frame_register_unsigned (frame, FPSCR_REGNUM) & 0x80000; |
1937 | ||
1938 | printf_filtered | |
1939 | (" PC %s SR %08lx PR %08lx MACH %08lx\n", | |
3e8c568d | 1940 | paddr (get_frame_register_unsigned (frame, |
b47193f7 | 1941 | gdbarch_pc_regnum (gdbarch))), |
c458d6db UW |
1942 | (long) get_frame_register_unsigned (frame, SR_REGNUM), |
1943 | (long) get_frame_register_unsigned (frame, PR_REGNUM), | |
1944 | (long) get_frame_register_unsigned (frame, MACH_REGNUM)); | |
1945 | ||
1946 | printf_filtered | |
1947 | (" GBR %08lx VBR %08lx MACL %08lx\n", | |
1948 | (long) get_frame_register_unsigned (frame, GBR_REGNUM), | |
1949 | (long) get_frame_register_unsigned (frame, VBR_REGNUM), | |
1950 | (long) get_frame_register_unsigned (frame, MACL_REGNUM)); | |
1951 | printf_filtered | |
1952 | (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n", | |
1953 | (long) get_frame_register_unsigned (frame, SSR_REGNUM), | |
1954 | (long) get_frame_register_unsigned (frame, SPC_REGNUM), | |
1955 | (long) get_frame_register_unsigned (frame, FPUL_REGNUM), | |
1956 | (long) get_frame_register_unsigned (frame, FPSCR_REGNUM)); | |
1957 | ||
1958 | printf_filtered | |
1959 | ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1960 | (long) get_frame_register_unsigned (frame, 0), | |
1961 | (long) get_frame_register_unsigned (frame, 1), | |
1962 | (long) get_frame_register_unsigned (frame, 2), | |
1963 | (long) get_frame_register_unsigned (frame, 3), | |
1964 | (long) get_frame_register_unsigned (frame, 4), | |
1965 | (long) get_frame_register_unsigned (frame, 5), | |
1966 | (long) get_frame_register_unsigned (frame, 6), | |
1967 | (long) get_frame_register_unsigned (frame, 7)); | |
1968 | printf_filtered | |
1969 | ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1970 | (long) get_frame_register_unsigned (frame, 8), | |
1971 | (long) get_frame_register_unsigned (frame, 9), | |
1972 | (long) get_frame_register_unsigned (frame, 10), | |
1973 | (long) get_frame_register_unsigned (frame, 11), | |
1974 | (long) get_frame_register_unsigned (frame, 12), | |
1975 | (long) get_frame_register_unsigned (frame, 13), | |
1976 | (long) get_frame_register_unsigned (frame, 14), | |
1977 | (long) get_frame_register_unsigned (frame, 15)); | |
1978 | ||
1979 | printf_filtered | |
1980 | (pr ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n" | |
1981 | : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
3e8c568d | 1982 | (long) get_frame_register_unsigned |
b47193f7 | 1983 | (frame, gdbarch_fp0_regnum (gdbarch) + 0), |
3e8c568d | 1984 | (long) get_frame_register_unsigned |
b47193f7 | 1985 | (frame, gdbarch_fp0_regnum (gdbarch) + 1), |
3e8c568d | 1986 | (long) get_frame_register_unsigned |
b47193f7 | 1987 | (frame, gdbarch_fp0_regnum (gdbarch) + 2), |
3e8c568d | 1988 | (long) get_frame_register_unsigned |
b47193f7 | 1989 | (frame, gdbarch_fp0_regnum (gdbarch) + 3), |
3e8c568d | 1990 | (long) get_frame_register_unsigned |
b47193f7 | 1991 | (frame, gdbarch_fp0_regnum (gdbarch) + 4), |
3e8c568d | 1992 | (long) get_frame_register_unsigned |
b47193f7 | 1993 | (frame, gdbarch_fp0_regnum (gdbarch) + 5), |
3e8c568d | 1994 | (long) get_frame_register_unsigned |
b47193f7 | 1995 | (frame, gdbarch_fp0_regnum (gdbarch) + 6), |
3e8c568d | 1996 | (long) get_frame_register_unsigned |
b47193f7 | 1997 | (frame, gdbarch_fp0_regnum (gdbarch) + 7)); |
c458d6db UW |
1998 | printf_filtered |
1999 | (pr ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n" | |
2000 | : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
3e8c568d | 2001 | (long) get_frame_register_unsigned |
b47193f7 | 2002 | (frame, gdbarch_fp0_regnum (gdbarch) + 8), |
3e8c568d | 2003 | (long) get_frame_register_unsigned |
b47193f7 | 2004 | (frame, gdbarch_fp0_regnum (gdbarch) + 9), |
3e8c568d | 2005 | (long) get_frame_register_unsigned |
b47193f7 | 2006 | (frame, gdbarch_fp0_regnum (gdbarch) + 10), |
3e8c568d | 2007 | (long) get_frame_register_unsigned |
b47193f7 | 2008 | (frame, gdbarch_fp0_regnum (gdbarch) + 11), |
3e8c568d | 2009 | (long) get_frame_register_unsigned |
b47193f7 | 2010 | (frame, gdbarch_fp0_regnum (gdbarch) + 12), |
3e8c568d | 2011 | (long) get_frame_register_unsigned |
b47193f7 | 2012 | (frame, gdbarch_fp0_regnum (gdbarch) + 13), |
3e8c568d | 2013 | (long) get_frame_register_unsigned |
b47193f7 | 2014 | (frame, gdbarch_fp0_regnum (gdbarch) + 14), |
3e8c568d | 2015 | (long) get_frame_register_unsigned |
b47193f7 | 2016 | (frame, gdbarch_fp0_regnum (gdbarch) + 15)); |
cc17453a EZ |
2017 | } |
2018 | ||
474e5826 | 2019 | static void |
c458d6db | 2020 | sh4_nofpu_show_regs (struct frame_info *frame) |
474e5826 | 2021 | { |
c458d6db UW |
2022 | printf_filtered |
2023 | (" PC %s SR %08lx PR %08lx MACH %08lx\n", | |
3e8c568d | 2024 | paddr (get_frame_register_unsigned (frame, |
b47193f7 UW |
2025 | gdbarch_pc_regnum |
2026 | (get_frame_arch (frame)))), | |
c458d6db UW |
2027 | (long) get_frame_register_unsigned (frame, SR_REGNUM), |
2028 | (long) get_frame_register_unsigned (frame, PR_REGNUM), | |
2029 | (long) get_frame_register_unsigned (frame, MACH_REGNUM)); | |
2030 | ||
2031 | printf_filtered | |
2032 | (" GBR %08lx VBR %08lx MACL %08lx\n", | |
2033 | (long) get_frame_register_unsigned (frame, GBR_REGNUM), | |
2034 | (long) get_frame_register_unsigned (frame, VBR_REGNUM), | |
2035 | (long) get_frame_register_unsigned (frame, MACL_REGNUM)); | |
2036 | printf_filtered | |
2037 | (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n", | |
2038 | (long) get_frame_register_unsigned (frame, SSR_REGNUM), | |
2039 | (long) get_frame_register_unsigned (frame, SPC_REGNUM), | |
2040 | (long) get_frame_register_unsigned (frame, FPUL_REGNUM), | |
2041 | (long) get_frame_register_unsigned (frame, FPSCR_REGNUM)); | |
2042 | ||
2043 | printf_filtered | |
2044 | ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
2045 | (long) get_frame_register_unsigned (frame, 0), | |
2046 | (long) get_frame_register_unsigned (frame, 1), | |
2047 | (long) get_frame_register_unsigned (frame, 2), | |
2048 | (long) get_frame_register_unsigned (frame, 3), | |
2049 | (long) get_frame_register_unsigned (frame, 4), | |
2050 | (long) get_frame_register_unsigned (frame, 5), | |
2051 | (long) get_frame_register_unsigned (frame, 6), | |
2052 | (long) get_frame_register_unsigned (frame, 7)); | |
2053 | printf_filtered | |
2054 | ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
2055 | (long) get_frame_register_unsigned (frame, 8), | |
2056 | (long) get_frame_register_unsigned (frame, 9), | |
2057 | (long) get_frame_register_unsigned (frame, 10), | |
2058 | (long) get_frame_register_unsigned (frame, 11), | |
2059 | (long) get_frame_register_unsigned (frame, 12), | |
2060 | (long) get_frame_register_unsigned (frame, 13), | |
2061 | (long) get_frame_register_unsigned (frame, 14), | |
2062 | (long) get_frame_register_unsigned (frame, 15)); | |
474e5826 CV |
2063 | } |
2064 | ||
cc17453a | 2065 | static void |
c458d6db | 2066 | sh_dsp_show_regs (struct frame_info *frame) |
cc17453a | 2067 | { |
c458d6db UW |
2068 | printf_filtered |
2069 | (" PC %s SR %08lx PR %08lx MACH %08lx\n", | |
3e8c568d | 2070 | paddr (get_frame_register_unsigned (frame, |
b47193f7 UW |
2071 | gdbarch_pc_regnum |
2072 | (get_frame_arch (frame)))), | |
c458d6db UW |
2073 | (long) get_frame_register_unsigned (frame, SR_REGNUM), |
2074 | (long) get_frame_register_unsigned (frame, PR_REGNUM), | |
2075 | (long) get_frame_register_unsigned (frame, MACH_REGNUM)); | |
a6b0a3f3 | 2076 | |
c458d6db UW |
2077 | printf_filtered |
2078 | (" GBR %08lx VBR %08lx DSR %08lx MACL %08lx\n", | |
2079 | (long) get_frame_register_unsigned (frame, GBR_REGNUM), | |
2080 | (long) get_frame_register_unsigned (frame, VBR_REGNUM), | |
2081 | (long) get_frame_register_unsigned (frame, DSR_REGNUM), | |
2082 | (long) get_frame_register_unsigned (frame, MACL_REGNUM)); | |
617daa0e CV |
2083 | |
2084 | printf_filtered | |
a6b0a3f3 | 2085 | ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
c458d6db UW |
2086 | (long) get_frame_register_unsigned (frame, 0), |
2087 | (long) get_frame_register_unsigned (frame, 1), | |
2088 | (long) get_frame_register_unsigned (frame, 2), | |
2089 | (long) get_frame_register_unsigned (frame, 3), | |
2090 | (long) get_frame_register_unsigned (frame, 4), | |
2091 | (long) get_frame_register_unsigned (frame, 5), | |
2092 | (long) get_frame_register_unsigned (frame, 6), | |
2093 | (long) get_frame_register_unsigned (frame, 7)); | |
2094 | printf_filtered | |
2095 | ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
2096 | (long) get_frame_register_unsigned (frame, 8), | |
2097 | (long) get_frame_register_unsigned (frame, 9), | |
2098 | (long) get_frame_register_unsigned (frame, 10), | |
2099 | (long) get_frame_register_unsigned (frame, 11), | |
2100 | (long) get_frame_register_unsigned (frame, 12), | |
2101 | (long) get_frame_register_unsigned (frame, 13), | |
2102 | (long) get_frame_register_unsigned (frame, 14), | |
2103 | (long) get_frame_register_unsigned (frame, 15)); | |
617daa0e CV |
2104 | |
2105 | printf_filtered | |
2106 | ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n", | |
c458d6db UW |
2107 | (long) get_frame_register_unsigned (frame, A0G_REGNUM) & 0xff, |
2108 | (long) get_frame_register_unsigned (frame, A0_REGNUM), | |
2109 | (long) get_frame_register_unsigned (frame, M0_REGNUM), | |
2110 | (long) get_frame_register_unsigned (frame, X0_REGNUM), | |
2111 | (long) get_frame_register_unsigned (frame, Y0_REGNUM), | |
2112 | (long) get_frame_register_unsigned (frame, RS_REGNUM), | |
2113 | (long) get_frame_register_unsigned (frame, MOD_REGNUM)); | |
cc17453a | 2114 | printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n", |
c458d6db UW |
2115 | (long) get_frame_register_unsigned (frame, A1G_REGNUM) & 0xff, |
2116 | (long) get_frame_register_unsigned (frame, A1_REGNUM), | |
2117 | (long) get_frame_register_unsigned (frame, M1_REGNUM), | |
2118 | (long) get_frame_register_unsigned (frame, X1_REGNUM), | |
2119 | (long) get_frame_register_unsigned (frame, Y1_REGNUM), | |
2120 | (long) get_frame_register_unsigned (frame, RE_REGNUM)); | |
cc17453a EZ |
2121 | } |
2122 | ||
a78f21af AC |
2123 | static void |
2124 | sh_show_regs_command (char *args, int from_tty) | |
53116e27 EZ |
2125 | { |
2126 | if (sh_show_regs) | |
c458d6db | 2127 | (*sh_show_regs) (get_current_frame ()); |
53116e27 EZ |
2128 | } |
2129 | ||
da962468 CV |
2130 | static struct type * |
2131 | sh_sh2a_register_type (struct gdbarch *gdbarch, int reg_nr) | |
2132 | { | |
b47193f7 | 2133 | if ((reg_nr >= gdbarch_fp0_regnum (gdbarch) |
da962468 CV |
2134 | && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM)) |
2135 | return builtin_type_float; | |
2136 | else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM) | |
2137 | return builtin_type_double; | |
2138 | else | |
2139 | return builtin_type_int; | |
2140 | } | |
2141 | ||
cc17453a EZ |
2142 | /* Return the GDB type object for the "standard" data type |
2143 | of data in register N. */ | |
cc17453a | 2144 | static struct type * |
48db5a3c | 2145 | sh_sh3e_register_type (struct gdbarch *gdbarch, int reg_nr) |
cc17453a | 2146 | { |
b47193f7 | 2147 | if ((reg_nr >= gdbarch_fp0_regnum (gdbarch) |
617daa0e | 2148 | && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM)) |
cc17453a | 2149 | return builtin_type_float; |
8db62801 | 2150 | else |
cc17453a EZ |
2151 | return builtin_type_int; |
2152 | } | |
2153 | ||
7f4dbe94 EZ |
2154 | static struct type * |
2155 | sh_sh4_build_float_register_type (int high) | |
2156 | { | |
2157 | struct type *temp; | |
2158 | ||
2159 | temp = create_range_type (NULL, builtin_type_int, 0, high); | |
2160 | return create_array_type (NULL, builtin_type_float, temp); | |
2161 | } | |
2162 | ||
53116e27 | 2163 | static struct type * |
48db5a3c | 2164 | sh_sh4_register_type (struct gdbarch *gdbarch, int reg_nr) |
53116e27 | 2165 | { |
b47193f7 | 2166 | if ((reg_nr >= gdbarch_fp0_regnum (gdbarch) |
617daa0e | 2167 | && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM)) |
53116e27 | 2168 | return builtin_type_float; |
617daa0e | 2169 | else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM) |
53116e27 | 2170 | return builtin_type_double; |
617daa0e | 2171 | else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM) |
53116e27 EZ |
2172 | return sh_sh4_build_float_register_type (3); |
2173 | else | |
2174 | return builtin_type_int; | |
2175 | } | |
2176 | ||
cc17453a | 2177 | static struct type * |
48db5a3c | 2178 | sh_default_register_type (struct gdbarch *gdbarch, int reg_nr) |
cc17453a EZ |
2179 | { |
2180 | return builtin_type_int; | |
2181 | } | |
2182 | ||
dda63807 AS |
2183 | /* Is a register in a reggroup? |
2184 | The default code in reggroup.c doesn't identify system registers, some | |
2185 | float registers or any of the vector registers. | |
2186 | TODO: sh2a and dsp registers. */ | |
2187 | int | |
2188 | sh_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
2189 | struct reggroup *reggroup) | |
2190 | { | |
b47193f7 UW |
2191 | if (gdbarch_register_name (gdbarch, regnum) == NULL |
2192 | || *gdbarch_register_name (gdbarch, regnum) == '\0') | |
dda63807 AS |
2193 | return 0; |
2194 | ||
2195 | if (reggroup == float_reggroup | |
2196 | && (regnum == FPUL_REGNUM | |
2197 | || regnum == FPSCR_REGNUM)) | |
2198 | return 1; | |
2199 | ||
2200 | if (regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM) | |
2201 | { | |
2202 | if (reggroup == vector_reggroup || reggroup == float_reggroup) | |
2203 | return 1; | |
2204 | if (reggroup == general_reggroup) | |
2205 | return 0; | |
2206 | } | |
2207 | ||
2208 | if (regnum == VBR_REGNUM | |
2209 | || regnum == SR_REGNUM | |
2210 | || regnum == FPSCR_REGNUM | |
2211 | || regnum == SSR_REGNUM | |
2212 | || regnum == SPC_REGNUM) | |
2213 | { | |
2214 | if (reggroup == system_reggroup) | |
2215 | return 1; | |
2216 | if (reggroup == general_reggroup) | |
2217 | return 0; | |
2218 | } | |
2219 | ||
2220 | /* The default code can cope with any other registers. */ | |
2221 | return default_register_reggroup_p (gdbarch, regnum, reggroup); | |
2222 | } | |
2223 | ||
fb409745 EZ |
2224 | /* On the sh4, the DRi pseudo registers are problematic if the target |
2225 | is little endian. When the user writes one of those registers, for | |
2226 | instance with 'ser var $dr0=1', we want the double to be stored | |
2227 | like this: | |
2228 | fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f | |
2229 | fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00 | |
2230 | ||
2231 | This corresponds to little endian byte order & big endian word | |
2232 | order. However if we let gdb write the register w/o conversion, it | |
2233 | will write fr0 and fr1 this way: | |
2234 | fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00 | |
2235 | fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f | |
2236 | because it will consider fr0 and fr1 as a single LE stretch of memory. | |
2237 | ||
2238 | To achieve what we want we must force gdb to store things in | |
2239 | floatformat_ieee_double_littlebyte_bigword (which is defined in | |
2240 | include/floatformat.h and libiberty/floatformat.c. | |
2241 | ||
2242 | In case the target is big endian, there is no problem, the | |
2243 | raw bytes will look like: | |
2244 | fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00 | |
2245 | fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00 | |
2246 | ||
2247 | The other pseudo registers (the FVs) also don't pose a problem | |
2248 | because they are stored as 4 individual FP elements. */ | |
2249 | ||
7bd872fe | 2250 | static void |
b66ba949 CV |
2251 | sh_register_convert_to_virtual (int regnum, struct type *type, |
2252 | char *from, char *to) | |
55ff77ac | 2253 | { |
617daa0e | 2254 | if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM) |
283150cd EZ |
2255 | { |
2256 | DOUBLEST val; | |
617daa0e CV |
2257 | floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, |
2258 | from, &val); | |
55ff77ac | 2259 | store_typed_floating (to, type, val); |
283150cd EZ |
2260 | } |
2261 | else | |
617daa0e CV |
2262 | error |
2263 | ("sh_register_convert_to_virtual called with non DR register number"); | |
283150cd EZ |
2264 | } |
2265 | ||
2266 | static void | |
b66ba949 CV |
2267 | sh_register_convert_to_raw (struct type *type, int regnum, |
2268 | const void *from, void *to) | |
283150cd | 2269 | { |
617daa0e | 2270 | if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM) |
283150cd | 2271 | { |
48db5a3c | 2272 | DOUBLEST val = extract_typed_floating (from, type); |
617daa0e CV |
2273 | floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword, |
2274 | &val, to); | |
283150cd EZ |
2275 | } |
2276 | else | |
8a3fe4f8 | 2277 | error (_("sh_register_convert_to_raw called with non DR register number")); |
283150cd EZ |
2278 | } |
2279 | ||
1c0159e0 CV |
2280 | /* For vectors of 4 floating point registers. */ |
2281 | static int | |
d93859e2 | 2282 | fv_reg_base_num (struct gdbarch *gdbarch, int fv_regnum) |
1c0159e0 CV |
2283 | { |
2284 | int fp_regnum; | |
2285 | ||
d93859e2 | 2286 | fp_regnum = gdbarch_fp0_regnum (gdbarch) |
3e8c568d | 2287 | + (fv_regnum - FV0_REGNUM) * 4; |
1c0159e0 CV |
2288 | return fp_regnum; |
2289 | } | |
2290 | ||
2291 | /* For double precision floating point registers, i.e 2 fp regs.*/ | |
2292 | static int | |
d93859e2 | 2293 | dr_reg_base_num (struct gdbarch *gdbarch, int dr_regnum) |
1c0159e0 CV |
2294 | { |
2295 | int fp_regnum; | |
2296 | ||
d93859e2 | 2297 | fp_regnum = gdbarch_fp0_regnum (gdbarch) |
3e8c568d | 2298 | + (dr_regnum - DR0_REGNUM) * 2; |
1c0159e0 CV |
2299 | return fp_regnum; |
2300 | } | |
2301 | ||
a78f21af | 2302 | static void |
d8124050 | 2303 | sh_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, |
18cf8b5b | 2304 | int reg_nr, gdb_byte *buffer) |
53116e27 EZ |
2305 | { |
2306 | int base_regnum, portion; | |
d9d9c31f | 2307 | char temp_buffer[MAX_REGISTER_SIZE]; |
53116e27 | 2308 | |
9bed62d7 CV |
2309 | if (reg_nr == PSEUDO_BANK_REGNUM) |
2310 | regcache_raw_read (regcache, BANK_REGNUM, buffer); | |
2311 | else | |
617daa0e | 2312 | if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM) |
7bd872fe | 2313 | { |
d93859e2 | 2314 | base_regnum = dr_reg_base_num (gdbarch, reg_nr); |
7bd872fe | 2315 | |
617daa0e | 2316 | /* Build the value in the provided buffer. */ |
7bd872fe EZ |
2317 | /* Read the real regs for which this one is an alias. */ |
2318 | for (portion = 0; portion < 2; portion++) | |
617daa0e | 2319 | regcache_raw_read (regcache, base_regnum + portion, |
0818c12a | 2320 | (temp_buffer |
617daa0e CV |
2321 | + register_size (gdbarch, |
2322 | base_regnum) * portion)); | |
7bd872fe | 2323 | /* We must pay attention to the endiannes. */ |
b66ba949 | 2324 | sh_register_convert_to_virtual (reg_nr, |
7b9ee6a8 | 2325 | register_type (gdbarch, reg_nr), |
b66ba949 | 2326 | temp_buffer, buffer); |
7bd872fe | 2327 | } |
617daa0e | 2328 | else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM) |
53116e27 | 2329 | { |
d93859e2 | 2330 | base_regnum = fv_reg_base_num (gdbarch, reg_nr); |
7bd872fe EZ |
2331 | |
2332 | /* Read the real regs for which this one is an alias. */ | |
2333 | for (portion = 0; portion < 4; portion++) | |
617daa0e | 2334 | regcache_raw_read (regcache, base_regnum + portion, |
d8124050 | 2335 | ((char *) buffer |
617daa0e CV |
2336 | + register_size (gdbarch, |
2337 | base_regnum) * portion)); | |
53116e27 EZ |
2338 | } |
2339 | } | |
2340 | ||
a78f21af | 2341 | static void |
d8124050 | 2342 | sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, |
18cf8b5b | 2343 | int reg_nr, const gdb_byte *buffer) |
53116e27 EZ |
2344 | { |
2345 | int base_regnum, portion; | |
d9d9c31f | 2346 | char temp_buffer[MAX_REGISTER_SIZE]; |
53116e27 | 2347 | |
9bed62d7 CV |
2348 | if (reg_nr == PSEUDO_BANK_REGNUM) |
2349 | { | |
2350 | /* When the bank register is written to, the whole register bank | |
2351 | is switched and all values in the bank registers must be read | |
2352 | from the target/sim again. We're just invalidating the regcache | |
2353 | so that a re-read happens next time it's necessary. */ | |
2354 | int bregnum; | |
2355 | ||
2356 | regcache_raw_write (regcache, BANK_REGNUM, buffer); | |
2357 | for (bregnum = R0_BANK0_REGNUM; bregnum < MACLB_REGNUM; ++bregnum) | |
9c5ea4d9 | 2358 | regcache_invalidate (regcache, bregnum); |
9bed62d7 CV |
2359 | } |
2360 | else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM) | |
53116e27 | 2361 | { |
d93859e2 | 2362 | base_regnum = dr_reg_base_num (gdbarch, reg_nr); |
53116e27 | 2363 | |
7bd872fe | 2364 | /* We must pay attention to the endiannes. */ |
7b9ee6a8 | 2365 | sh_register_convert_to_raw (register_type (gdbarch, reg_nr), |
b66ba949 | 2366 | reg_nr, buffer, temp_buffer); |
7bd872fe | 2367 | |
53116e27 EZ |
2368 | /* Write the real regs for which this one is an alias. */ |
2369 | for (portion = 0; portion < 2; portion++) | |
617daa0e | 2370 | regcache_raw_write (regcache, base_regnum + portion, |
0818c12a | 2371 | (temp_buffer |
617daa0e CV |
2372 | + register_size (gdbarch, |
2373 | base_regnum) * portion)); | |
53116e27 | 2374 | } |
617daa0e | 2375 | else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM) |
53116e27 | 2376 | { |
d93859e2 | 2377 | base_regnum = fv_reg_base_num (gdbarch, reg_nr); |
53116e27 EZ |
2378 | |
2379 | /* Write the real regs for which this one is an alias. */ | |
2380 | for (portion = 0; portion < 4; portion++) | |
d8124050 AC |
2381 | regcache_raw_write (regcache, base_regnum + portion, |
2382 | ((char *) buffer | |
617daa0e CV |
2383 | + register_size (gdbarch, |
2384 | base_regnum) * portion)); | |
53116e27 EZ |
2385 | } |
2386 | } | |
2387 | ||
2f14585c | 2388 | static int |
e7faf938 | 2389 | sh_dsp_register_sim_regno (struct gdbarch *gdbarch, int nr) |
2f14585c | 2390 | { |
e7faf938 MD |
2391 | if (legacy_register_sim_regno (gdbarch, nr) < 0) |
2392 | return legacy_register_sim_regno (gdbarch, nr); | |
f2ea0907 CV |
2393 | if (nr >= DSR_REGNUM && nr <= Y1_REGNUM) |
2394 | return nr - DSR_REGNUM + SIM_SH_DSR_REGNUM; | |
2395 | if (nr == MOD_REGNUM) | |
2f14585c | 2396 | return SIM_SH_MOD_REGNUM; |
f2ea0907 | 2397 | if (nr == RS_REGNUM) |
2f14585c | 2398 | return SIM_SH_RS_REGNUM; |
f2ea0907 | 2399 | if (nr == RE_REGNUM) |
2f14585c | 2400 | return SIM_SH_RE_REGNUM; |
76cd2bd9 CV |
2401 | if (nr >= DSP_R0_BANK_REGNUM && nr <= DSP_R7_BANK_REGNUM) |
2402 | return nr - DSP_R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM; | |
2f14585c JR |
2403 | return nr; |
2404 | } | |
1c0159e0 | 2405 | |
da962468 | 2406 | static int |
e7faf938 | 2407 | sh_sh2a_register_sim_regno (struct gdbarch *gdbarch, int nr) |
da962468 CV |
2408 | { |
2409 | switch (nr) | |
2410 | { | |
2411 | case TBR_REGNUM: | |
2412 | return SIM_SH_TBR_REGNUM; | |
2413 | case IBNR_REGNUM: | |
2414 | return SIM_SH_IBNR_REGNUM; | |
2415 | case IBCR_REGNUM: | |
2416 | return SIM_SH_IBCR_REGNUM; | |
2417 | case BANK_REGNUM: | |
2418 | return SIM_SH_BANK_REGNUM; | |
2419 | case MACLB_REGNUM: | |
2420 | return SIM_SH_BANK_MACL_REGNUM; | |
2421 | case GBRB_REGNUM: | |
2422 | return SIM_SH_BANK_GBR_REGNUM; | |
2423 | case PRB_REGNUM: | |
2424 | return SIM_SH_BANK_PR_REGNUM; | |
2425 | case IVNB_REGNUM: | |
2426 | return SIM_SH_BANK_IVN_REGNUM; | |
2427 | case MACHB_REGNUM: | |
2428 | return SIM_SH_BANK_MACH_REGNUM; | |
2429 | default: | |
2430 | break; | |
2431 | } | |
e7faf938 | 2432 | return legacy_register_sim_regno (gdbarch, nr); |
da962468 CV |
2433 | } |
2434 | ||
357d3800 AS |
2435 | /* Set up the register unwinding such that call-clobbered registers are |
2436 | not displayed in frames >0 because the true value is not certain. | |
2437 | The 'undefined' registers will show up as 'not available' unless the | |
2438 | CFI says otherwise. | |
2439 | ||
2440 | This function is currently set up for SH4 and compatible only. */ | |
2441 | ||
2442 | static void | |
2443 | sh_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
aff37fc1 | 2444 | struct dwarf2_frame_state_reg *reg, |
4a4e5149 | 2445 | struct frame_info *this_frame) |
357d3800 AS |
2446 | { |
2447 | /* Mark the PC as the destination for the return address. */ | |
b47193f7 | 2448 | if (regnum == gdbarch_pc_regnum (gdbarch)) |
357d3800 AS |
2449 | reg->how = DWARF2_FRAME_REG_RA; |
2450 | ||
2451 | /* Mark the stack pointer as the call frame address. */ | |
b47193f7 | 2452 | else if (regnum == gdbarch_sp_regnum (gdbarch)) |
357d3800 AS |
2453 | reg->how = DWARF2_FRAME_REG_CFA; |
2454 | ||
2455 | /* The above was taken from the default init_reg in dwarf2-frame.c | |
2456 | while the below is SH specific. */ | |
2457 | ||
2458 | /* Caller save registers. */ | |
2459 | else if ((regnum >= R0_REGNUM && regnum <= R0_REGNUM+7) | |
2460 | || (regnum >= FR0_REGNUM && regnum <= FR0_REGNUM+11) | |
2461 | || (regnum >= DR0_REGNUM && regnum <= DR0_REGNUM+5) | |
2462 | || (regnum >= FV0_REGNUM && regnum <= FV0_REGNUM+2) | |
2463 | || (regnum == MACH_REGNUM) | |
2464 | || (regnum == MACL_REGNUM) | |
2465 | || (regnum == FPUL_REGNUM) | |
2466 | || (regnum == SR_REGNUM)) | |
2467 | reg->how = DWARF2_FRAME_REG_UNDEFINED; | |
2468 | ||
2469 | /* Callee save registers. */ | |
2470 | else if ((regnum >= R0_REGNUM+8 && regnum <= R0_REGNUM+15) | |
2471 | || (regnum >= FR0_REGNUM+12 && regnum <= FR0_REGNUM+15) | |
2472 | || (regnum >= DR0_REGNUM+6 && regnum <= DR0_REGNUM+8) | |
2473 | || (regnum == FV0_REGNUM+3)) | |
2474 | reg->how = DWARF2_FRAME_REG_SAME_VALUE; | |
2475 | ||
2476 | /* Other registers. These are not in the ABI and may or may not | |
2477 | mean anything in frames >0 so don't show them. */ | |
2478 | else if ((regnum >= R0_BANK0_REGNUM && regnum <= R0_BANK0_REGNUM+15) | |
2479 | || (regnum == GBR_REGNUM) | |
2480 | || (regnum == VBR_REGNUM) | |
2481 | || (regnum == FPSCR_REGNUM) | |
2482 | || (regnum == SSR_REGNUM) | |
2483 | || (regnum == SPC_REGNUM)) | |
2484 | reg->how = DWARF2_FRAME_REG_UNDEFINED; | |
2485 | } | |
2486 | ||
1c0159e0 CV |
2487 | static struct sh_frame_cache * |
2488 | sh_alloc_frame_cache (void) | |
2489 | { | |
2490 | struct sh_frame_cache *cache; | |
2491 | int i; | |
2492 | ||
2493 | cache = FRAME_OBSTACK_ZALLOC (struct sh_frame_cache); | |
2494 | ||
2495 | /* Base address. */ | |
2496 | cache->base = 0; | |
2497 | cache->saved_sp = 0; | |
2498 | cache->sp_offset = 0; | |
2499 | cache->pc = 0; | |
2500 | ||
2501 | /* Frameless until proven otherwise. */ | |
2502 | cache->uses_fp = 0; | |
617daa0e | 2503 | |
1c0159e0 CV |
2504 | /* Saved registers. We initialize these to -1 since zero is a valid |
2505 | offset (that's where fp is supposed to be stored). */ | |
2506 | for (i = 0; i < SH_NUM_REGS; i++) | |
2507 | { | |
2508 | cache->saved_regs[i] = -1; | |
2509 | } | |
617daa0e | 2510 | |
1c0159e0 | 2511 | return cache; |
617daa0e | 2512 | } |
1c0159e0 CV |
2513 | |
2514 | static struct sh_frame_cache * | |
2515 | sh_frame_cache (struct frame_info *next_frame, void **this_cache) | |
2516 | { | |
2517 | struct sh_frame_cache *cache; | |
2518 | CORE_ADDR current_pc; | |
2519 | int i; | |
2520 | ||
2521 | if (*this_cache) | |
2522 | return *this_cache; | |
2523 | ||
2524 | cache = sh_alloc_frame_cache (); | |
2525 | *this_cache = cache; | |
2526 | ||
2527 | /* In principle, for normal frames, fp holds the frame pointer, | |
2528 | which holds the base address for the current stack frame. | |
2529 | However, for functions that don't need it, the frame pointer is | |
2530 | optional. For these "frameless" functions the frame pointer is | |
2531 | actually the frame pointer of the calling frame. */ | |
2532 | cache->base = frame_unwind_register_unsigned (next_frame, FP_REGNUM); | |
2533 | if (cache->base == 0) | |
2534 | return cache; | |
2535 | ||
93d42b30 | 2536 | cache->pc = frame_func_unwind (next_frame, NORMAL_FRAME); |
1c0159e0 CV |
2537 | current_pc = frame_pc_unwind (next_frame); |
2538 | if (cache->pc != 0) | |
d2ca4222 UW |
2539 | { |
2540 | ULONGEST fpscr; | |
2541 | fpscr = frame_unwind_register_unsigned (next_frame, FPSCR_REGNUM); | |
2542 | sh_analyze_prologue (cache->pc, current_pc, cache, fpscr); | |
2543 | } | |
617daa0e | 2544 | |
1c0159e0 CV |
2545 | if (!cache->uses_fp) |
2546 | { | |
2547 | /* We didn't find a valid frame, which means that CACHE->base | |
2548 | currently holds the frame pointer for our calling frame. If | |
2549 | we're at the start of a function, or somewhere half-way its | |
2550 | prologue, the function's frame probably hasn't been fully | |
2551 | setup yet. Try to reconstruct the base address for the stack | |
2552 | frame by looking at the stack pointer. For truly "frameless" | |
2553 | functions this might work too. */ | |
3e8c568d | 2554 | cache->base = frame_unwind_register_unsigned |
b47193f7 UW |
2555 | (next_frame, |
2556 | gdbarch_sp_regnum (get_frame_arch (next_frame))); | |
1c0159e0 CV |
2557 | } |
2558 | ||
2559 | /* Now that we have the base address for the stack frame we can | |
2560 | calculate the value of sp in the calling frame. */ | |
2561 | cache->saved_sp = cache->base + cache->sp_offset; | |
2562 | ||
2563 | /* Adjust all the saved registers such that they contain addresses | |
2564 | instead of offsets. */ | |
2565 | for (i = 0; i < SH_NUM_REGS; i++) | |
2566 | if (cache->saved_regs[i] != -1) | |
2567 | cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i] - 4; | |
2568 | ||
2569 | return cache; | |
2570 | } | |
2571 | ||
2572 | static void | |
2573 | sh_frame_prev_register (struct frame_info *next_frame, void **this_cache, | |
2574 | int regnum, int *optimizedp, | |
2575 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
18cf8b5b | 2576 | int *realnump, gdb_byte *valuep) |
1c0159e0 | 2577 | { |
b47193f7 | 2578 | struct gdbarch *gdbarch = get_frame_arch (next_frame); |
1c0159e0 CV |
2579 | struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache); |
2580 | ||
2581 | gdb_assert (regnum >= 0); | |
2582 | ||
b47193f7 | 2583 | if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp) |
1c0159e0 CV |
2584 | { |
2585 | *optimizedp = 0; | |
2586 | *lvalp = not_lval; | |
2587 | *addrp = 0; | |
2588 | *realnump = -1; | |
2589 | if (valuep) | |
617daa0e CV |
2590 | { |
2591 | /* Store the value. */ | |
2592 | store_unsigned_integer (valuep, 4, cache->saved_sp); | |
2593 | } | |
1c0159e0 CV |
2594 | return; |
2595 | } | |
2596 | ||
2597 | /* The PC of the previous frame is stored in the PR register of | |
2598 | the current frame. Frob regnum so that we pull the value from | |
2599 | the correct place. */ | |
b47193f7 | 2600 | if (regnum == gdbarch_pc_regnum (gdbarch)) |
1c0159e0 CV |
2601 | regnum = PR_REGNUM; |
2602 | ||
2603 | if (regnum < SH_NUM_REGS && cache->saved_regs[regnum] != -1) | |
2604 | { | |
2605 | *optimizedp = 0; | |
2606 | *lvalp = lval_memory; | |
2607 | *addrp = cache->saved_regs[regnum]; | |
2608 | *realnump = -1; | |
2609 | if (valuep) | |
617daa0e CV |
2610 | { |
2611 | /* Read the value in from memory. */ | |
2612 | read_memory (*addrp, valuep, | |
b47193f7 | 2613 | register_size (gdbarch, regnum)); |
617daa0e | 2614 | } |
1c0159e0 CV |
2615 | return; |
2616 | } | |
2617 | ||
00b25ff3 AC |
2618 | *optimizedp = 0; |
2619 | *lvalp = lval_register; | |
2620 | *addrp = 0; | |
2621 | *realnump = regnum; | |
2622 | if (valuep) | |
2623 | frame_unwind_register (next_frame, (*realnump), valuep); | |
1c0159e0 CV |
2624 | } |
2625 | ||
2626 | static void | |
2627 | sh_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
617daa0e CV |
2628 | struct frame_id *this_id) |
2629 | { | |
1c0159e0 CV |
2630 | struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache); |
2631 | ||
2632 | /* This marks the outermost frame. */ | |
2633 | if (cache->base == 0) | |
2634 | return; | |
2635 | ||
2636 | *this_id = frame_id_build (cache->saved_sp, cache->pc); | |
617daa0e | 2637 | } |
1c0159e0 | 2638 | |
617daa0e | 2639 | static const struct frame_unwind sh_frame_unwind = { |
1c0159e0 CV |
2640 | NORMAL_FRAME, |
2641 | sh_frame_this_id, | |
2642 | sh_frame_prev_register | |
2643 | }; | |
2644 | ||
2645 | static const struct frame_unwind * | |
2646 | sh_frame_sniffer (struct frame_info *next_frame) | |
2647 | { | |
2648 | return &sh_frame_unwind; | |
2649 | } | |
2650 | ||
2651 | static CORE_ADDR | |
2652 | sh_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
2653 | { | |
3e8c568d | 2654 | return frame_unwind_register_unsigned (next_frame, |
b47193f7 | 2655 | gdbarch_sp_regnum (gdbarch)); |
1c0159e0 CV |
2656 | } |
2657 | ||
2658 | static CORE_ADDR | |
2659 | sh_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
2660 | { | |
3e8c568d | 2661 | return frame_unwind_register_unsigned (next_frame, |
b47193f7 | 2662 | gdbarch_pc_regnum (gdbarch)); |
1c0159e0 CV |
2663 | } |
2664 | ||
2665 | static struct frame_id | |
2666 | sh_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
2667 | { | |
2668 | return frame_id_build (sh_unwind_sp (gdbarch, next_frame), | |
2669 | frame_pc_unwind (next_frame)); | |
2670 | } | |
2671 | ||
2672 | static CORE_ADDR | |
2673 | sh_frame_base_address (struct frame_info *next_frame, void **this_cache) | |
617daa0e | 2674 | { |
1c0159e0 | 2675 | struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache); |
617daa0e | 2676 | |
1c0159e0 CV |
2677 | return cache->base; |
2678 | } | |
617daa0e CV |
2679 | |
2680 | static const struct frame_base sh_frame_base = { | |
1c0159e0 CV |
2681 | &sh_frame_unwind, |
2682 | sh_frame_base_address, | |
2683 | sh_frame_base_address, | |
2684 | sh_frame_base_address | |
617daa0e | 2685 | }; |
1c0159e0 CV |
2686 | |
2687 | /* The epilogue is defined here as the area at the end of a function, | |
2688 | either on the `ret' instruction itself or after an instruction which | |
2689 | destroys the function's stack frame. */ | |
2690 | static int | |
2691 | sh_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
2692 | { | |
2693 | CORE_ADDR func_addr = 0, func_end = 0; | |
2694 | ||
2695 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
2696 | { | |
2697 | ULONGEST inst; | |
2698 | /* The sh epilogue is max. 14 bytes long. Give another 14 bytes | |
2699 | for a nop and some fixed data (e.g. big offsets) which are | |
617daa0e CV |
2700 | unfortunately also treated as part of the function (which |
2701 | means, they are below func_end. */ | |
1c0159e0 CV |
2702 | CORE_ADDR addr = func_end - 28; |
2703 | if (addr < func_addr + 4) | |
617daa0e | 2704 | addr = func_addr + 4; |
1c0159e0 CV |
2705 | if (pc < addr) |
2706 | return 0; | |
2707 | ||
2708 | /* First search forward until hitting an rts. */ | |
2709 | while (addr < func_end | |
617daa0e | 2710 | && !IS_RTS (read_memory_unsigned_integer (addr, 2))) |
1c0159e0 CV |
2711 | addr += 2; |
2712 | if (addr >= func_end) | |
617daa0e | 2713 | return 0; |
1c0159e0 CV |
2714 | |
2715 | /* At this point we should find a mov.l @r15+,r14 instruction, | |
2716 | either before or after the rts. If not, then the function has | |
617daa0e | 2717 | probably no "normal" epilogue and we bail out here. */ |
1c0159e0 CV |
2718 | inst = read_memory_unsigned_integer (addr - 2, 2); |
2719 | if (IS_RESTORE_FP (read_memory_unsigned_integer (addr - 2, 2))) | |
617daa0e | 2720 | addr -= 2; |
1c0159e0 CV |
2721 | else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr + 2, 2))) |
2722 | return 0; | |
2723 | ||
1c0159e0 | 2724 | inst = read_memory_unsigned_integer (addr - 2, 2); |
03131d99 CV |
2725 | |
2726 | /* Step over possible lds.l @r15+,macl. */ | |
2727 | if (IS_MACL_LDS (inst)) | |
2728 | { | |
2729 | addr -= 2; | |
2730 | inst = read_memory_unsigned_integer (addr - 2, 2); | |
2731 | } | |
2732 | ||
2733 | /* Step over possible lds.l @r15+,pr. */ | |
1c0159e0 | 2734 | if (IS_LDS (inst)) |
617daa0e | 2735 | { |
1c0159e0 CV |
2736 | addr -= 2; |
2737 | inst = read_memory_unsigned_integer (addr - 2, 2); | |
2738 | } | |
2739 | ||
2740 | /* Step over possible mov r14,r15. */ | |
2741 | if (IS_MOV_FP_SP (inst)) | |
617daa0e | 2742 | { |
1c0159e0 CV |
2743 | addr -= 2; |
2744 | inst = read_memory_unsigned_integer (addr - 2, 2); | |
2745 | } | |
2746 | ||
2747 | /* Now check for FP adjustments, using add #imm,r14 or add rX, r14 | |
2748 | instructions. */ | |
2749 | while (addr > func_addr + 4 | |
617daa0e | 2750 | && (IS_ADD_REG_TO_FP (inst) || IS_ADD_IMM_FP (inst))) |
1c0159e0 CV |
2751 | { |
2752 | addr -= 2; | |
2753 | inst = read_memory_unsigned_integer (addr - 2, 2); | |
2754 | } | |
2755 | ||
03131d99 CV |
2756 | /* On SH2a check if the previous instruction was perhaps a MOVI20. |
2757 | That's allowed for the epilogue. */ | |
2758 | if ((gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a | |
2759 | || gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a_nofpu) | |
2760 | && addr > func_addr + 6 | |
2761 | && IS_MOVI20 (read_memory_unsigned_integer (addr - 4, 2))) | |
2762 | addr -= 4; | |
2763 | ||
1c0159e0 CV |
2764 | if (pc >= addr) |
2765 | return 1; | |
2766 | } | |
2767 | return 0; | |
2768 | } | |
ccf00f21 | 2769 | \f |
cc17453a EZ |
2770 | |
2771 | static struct gdbarch * | |
fba45db2 | 2772 | sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
cc17453a | 2773 | { |
cc17453a | 2774 | struct gdbarch *gdbarch; |
d658f924 | 2775 | |
55ff77ac CV |
2776 | sh_show_regs = sh_generic_show_regs; |
2777 | switch (info.bfd_arch_info->mach) | |
2778 | { | |
617daa0e CV |
2779 | case bfd_mach_sh2e: |
2780 | sh_show_regs = sh2e_show_regs; | |
2781 | break; | |
da962468 CV |
2782 | case bfd_mach_sh2a: |
2783 | sh_show_regs = sh2a_show_regs; | |
2784 | break; | |
2785 | case bfd_mach_sh2a_nofpu: | |
2786 | sh_show_regs = sh2a_nofpu_show_regs; | |
2787 | break; | |
617daa0e CV |
2788 | case bfd_mach_sh_dsp: |
2789 | sh_show_regs = sh_dsp_show_regs; | |
2790 | break; | |
55ff77ac | 2791 | |
617daa0e CV |
2792 | case bfd_mach_sh3: |
2793 | sh_show_regs = sh3_show_regs; | |
2794 | break; | |
55ff77ac | 2795 | |
617daa0e CV |
2796 | case bfd_mach_sh3e: |
2797 | sh_show_regs = sh3e_show_regs; | |
2798 | break; | |
55ff77ac | 2799 | |
617daa0e | 2800 | case bfd_mach_sh3_dsp: |
474e5826 | 2801 | case bfd_mach_sh4al_dsp: |
617daa0e CV |
2802 | sh_show_regs = sh3_dsp_show_regs; |
2803 | break; | |
55ff77ac | 2804 | |
617daa0e | 2805 | case bfd_mach_sh4: |
474e5826 | 2806 | case bfd_mach_sh4a: |
617daa0e CV |
2807 | sh_show_regs = sh4_show_regs; |
2808 | break; | |
55ff77ac | 2809 | |
474e5826 CV |
2810 | case bfd_mach_sh4_nofpu: |
2811 | case bfd_mach_sh4a_nofpu: | |
2812 | sh_show_regs = sh4_nofpu_show_regs; | |
2813 | break; | |
2814 | ||
617daa0e CV |
2815 | case bfd_mach_sh5: |
2816 | sh_show_regs = sh64_show_regs; | |
2817 | /* SH5 is handled entirely in sh64-tdep.c */ | |
2818 | return sh64_gdbarch_init (info, arches); | |
55ff77ac CV |
2819 | } |
2820 | ||
4be87837 DJ |
2821 | /* If there is already a candidate, use it. */ |
2822 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
2823 | if (arches != NULL) | |
2824 | return arches->gdbarch; | |
cc17453a EZ |
2825 | |
2826 | /* None found, create a new architecture from the information | |
2827 | provided. */ | |
f2ea0907 | 2828 | gdbarch = gdbarch_alloc (&info, NULL); |
cc17453a | 2829 | |
48db5a3c CV |
2830 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); |
2831 | set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
ec920329 | 2832 | set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
48db5a3c CV |
2833 | set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); |
2834 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
2835 | set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
2836 | set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
a38d2a54 | 2837 | set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
48db5a3c | 2838 | |
f2ea0907 | 2839 | set_gdbarch_num_regs (gdbarch, SH_NUM_REGS); |
a38d2a54 | 2840 | set_gdbarch_sp_regnum (gdbarch, 15); |
a38d2a54 | 2841 | set_gdbarch_pc_regnum (gdbarch, 16); |
48db5a3c CV |
2842 | set_gdbarch_fp0_regnum (gdbarch, -1); |
2843 | set_gdbarch_num_pseudo_regs (gdbarch, 0); | |
2844 | ||
1c0159e0 | 2845 | set_gdbarch_register_type (gdbarch, sh_default_register_type); |
dda63807 | 2846 | set_gdbarch_register_reggroup_p (gdbarch, sh_register_reggroup_p); |
1c0159e0 | 2847 | |
eaf90c5d | 2848 | set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc); |
48db5a3c | 2849 | |
2bf0cb65 | 2850 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_sh); |
2f14585c | 2851 | set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno); |
48db5a3c | 2852 | |
c0409442 | 2853 | set_gdbarch_return_value (gdbarch, sh_return_value_nofpu); |
1c0159e0 | 2854 | |
48db5a3c CV |
2855 | set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue); |
2856 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
48db5a3c | 2857 | |
1c0159e0 CV |
2858 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu); |
2859 | ||
48db5a3c CV |
2860 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); |
2861 | ||
19f59343 | 2862 | set_gdbarch_frame_align (gdbarch, sh_frame_align); |
1c0159e0 CV |
2863 | set_gdbarch_unwind_sp (gdbarch, sh_unwind_sp); |
2864 | set_gdbarch_unwind_pc (gdbarch, sh_unwind_pc); | |
2865 | set_gdbarch_unwind_dummy_id (gdbarch, sh_unwind_dummy_id); | |
2866 | frame_base_set_default (gdbarch, &sh_frame_base); | |
2867 | ||
617daa0e | 2868 | set_gdbarch_in_function_epilogue_p (gdbarch, sh_in_function_epilogue_p); |
cc17453a | 2869 | |
357d3800 AS |
2870 | dwarf2_frame_set_init_reg (gdbarch, sh_dwarf2_frame_init_reg); |
2871 | ||
cc17453a | 2872 | switch (info.bfd_arch_info->mach) |
8db62801 | 2873 | { |
cc17453a | 2874 | case bfd_mach_sh: |
48db5a3c | 2875 | set_gdbarch_register_name (gdbarch, sh_sh_register_name); |
cc17453a | 2876 | break; |
1c0159e0 | 2877 | |
cc17453a | 2878 | case bfd_mach_sh2: |
48db5a3c | 2879 | set_gdbarch_register_name (gdbarch, sh_sh_register_name); |
617daa0e | 2880 | break; |
1c0159e0 | 2881 | |
2d188dd3 | 2882 | case bfd_mach_sh2e: |
48db5a3c CV |
2883 | /* doubles on sh2e and sh3e are actually 4 byte. */ |
2884 | set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
2885 | ||
2886 | set_gdbarch_register_name (gdbarch, sh_sh2e_register_name); | |
48db5a3c | 2887 | set_gdbarch_register_type (gdbarch, sh_sh3e_register_type); |
2d188dd3 | 2888 | set_gdbarch_fp0_regnum (gdbarch, 25); |
c0409442 | 2889 | set_gdbarch_return_value (gdbarch, sh_return_value_fpu); |
6df2bf50 | 2890 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); |
2d188dd3 | 2891 | break; |
1c0159e0 | 2892 | |
da962468 CV |
2893 | case bfd_mach_sh2a: |
2894 | set_gdbarch_register_name (gdbarch, sh_sh2a_register_name); | |
2895 | set_gdbarch_register_type (gdbarch, sh_sh2a_register_type); | |
2896 | set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno); | |
2897 | ||
2898 | set_gdbarch_fp0_regnum (gdbarch, 25); | |
2899 | set_gdbarch_num_pseudo_regs (gdbarch, 9); | |
2900 | set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read); | |
2901 | set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write); | |
c0409442 | 2902 | set_gdbarch_return_value (gdbarch, sh_return_value_fpu); |
da962468 CV |
2903 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); |
2904 | break; | |
2905 | ||
2906 | case bfd_mach_sh2a_nofpu: | |
2907 | set_gdbarch_register_name (gdbarch, sh_sh2a_nofpu_register_name); | |
2908 | set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno); | |
2909 | ||
2910 | set_gdbarch_num_pseudo_regs (gdbarch, 1); | |
2911 | set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read); | |
2912 | set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write); | |
2913 | break; | |
2914 | ||
cc17453a | 2915 | case bfd_mach_sh_dsp: |
48db5a3c | 2916 | set_gdbarch_register_name (gdbarch, sh_sh_dsp_register_name); |
2f14585c | 2917 | set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno); |
cc17453a | 2918 | break; |
1c0159e0 | 2919 | |
cc17453a | 2920 | case bfd_mach_sh3: |
4e6cbc38 AS |
2921 | case bfd_mach_sh3_nommu: |
2922 | case bfd_mach_sh2a_nofpu_or_sh3_nommu: | |
48db5a3c | 2923 | set_gdbarch_register_name (gdbarch, sh_sh3_register_name); |
cc17453a | 2924 | break; |
1c0159e0 | 2925 | |
cc17453a | 2926 | case bfd_mach_sh3e: |
4e6cbc38 | 2927 | case bfd_mach_sh2a_or_sh3e: |
48db5a3c CV |
2928 | /* doubles on sh2e and sh3e are actually 4 byte. */ |
2929 | set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
2930 | ||
2931 | set_gdbarch_register_name (gdbarch, sh_sh3e_register_name); | |
48db5a3c | 2932 | set_gdbarch_register_type (gdbarch, sh_sh3e_register_type); |
cc17453a | 2933 | set_gdbarch_fp0_regnum (gdbarch, 25); |
c0409442 | 2934 | set_gdbarch_return_value (gdbarch, sh_return_value_fpu); |
6df2bf50 | 2935 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); |
cc17453a | 2936 | break; |
1c0159e0 | 2937 | |
cc17453a | 2938 | case bfd_mach_sh3_dsp: |
48db5a3c | 2939 | set_gdbarch_register_name (gdbarch, sh_sh3_dsp_register_name); |
48db5a3c | 2940 | set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno); |
cc17453a | 2941 | break; |
1c0159e0 | 2942 | |
cc17453a | 2943 | case bfd_mach_sh4: |
474e5826 | 2944 | case bfd_mach_sh4a: |
48db5a3c | 2945 | set_gdbarch_register_name (gdbarch, sh_sh4_register_name); |
48db5a3c | 2946 | set_gdbarch_register_type (gdbarch, sh_sh4_register_type); |
cc17453a | 2947 | set_gdbarch_fp0_regnum (gdbarch, 25); |
da962468 | 2948 | set_gdbarch_num_pseudo_regs (gdbarch, 13); |
d8124050 AC |
2949 | set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read); |
2950 | set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write); | |
c0409442 | 2951 | set_gdbarch_return_value (gdbarch, sh_return_value_fpu); |
6df2bf50 | 2952 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); |
cc17453a | 2953 | break; |
1c0159e0 | 2954 | |
474e5826 CV |
2955 | case bfd_mach_sh4_nofpu: |
2956 | case bfd_mach_sh4a_nofpu: | |
4e6cbc38 AS |
2957 | case bfd_mach_sh4_nommu_nofpu: |
2958 | case bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu: | |
2959 | case bfd_mach_sh2a_or_sh4: | |
474e5826 CV |
2960 | set_gdbarch_register_name (gdbarch, sh_sh4_nofpu_register_name); |
2961 | break; | |
2962 | ||
2963 | case bfd_mach_sh4al_dsp: | |
2964 | set_gdbarch_register_name (gdbarch, sh_sh4al_dsp_register_name); | |
2965 | set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno); | |
2966 | break; | |
2967 | ||
cc17453a | 2968 | default: |
b58cbbf2 | 2969 | set_gdbarch_register_name (gdbarch, sh_sh_register_name); |
cc17453a | 2970 | break; |
8db62801 | 2971 | } |
cc17453a | 2972 | |
4be87837 DJ |
2973 | /* Hook in ABI-specific overrides, if they have been registered. */ |
2974 | gdbarch_init_osabi (info, gdbarch); | |
d658f924 | 2975 | |
1c0159e0 CV |
2976 | frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer); |
2977 | frame_unwind_append_sniffer (gdbarch, sh_frame_sniffer); | |
2978 | ||
cc17453a | 2979 | return gdbarch; |
8db62801 EZ |
2980 | } |
2981 | ||
c055b101 CV |
2982 | static void |
2983 | show_sh_command (char *args, int from_tty) | |
2984 | { | |
2985 | help_list (showshcmdlist, "show sh ", all_commands, gdb_stdout); | |
2986 | } | |
2987 | ||
2988 | static void | |
2989 | set_sh_command (char *args, int from_tty) | |
2990 | { | |
2991 | printf_unfiltered | |
2992 | ("\"set sh\" must be followed by an appropriate subcommand.\n"); | |
2993 | help_list (setshcmdlist, "set sh ", all_commands, gdb_stdout); | |
2994 | } | |
2995 | ||
617daa0e | 2996 | extern initialize_file_ftype _initialize_sh_tdep; /* -Wmissing-prototypes */ |
a78f21af | 2997 | |
c906108c | 2998 | void |
fba45db2 | 2999 | _initialize_sh_tdep (void) |
c906108c SS |
3000 | { |
3001 | struct cmd_list_element *c; | |
617daa0e | 3002 | |
f2ea0907 | 3003 | gdbarch_register (bfd_arch_sh, sh_gdbarch_init, NULL); |
c906108c | 3004 | |
1bedd215 | 3005 | add_com ("regs", class_vars, sh_show_regs_command, _("Print all registers")); |
c055b101 CV |
3006 | |
3007 | add_prefix_cmd ("sh", no_class, set_sh_command, "SH specific commands.", | |
3008 | &setshcmdlist, "set sh ", 0, &setlist); | |
3009 | add_prefix_cmd ("sh", no_class, show_sh_command, "SH specific commands.", | |
3010 | &showshcmdlist, "show sh ", 0, &showlist); | |
3011 | ||
3012 | add_setshow_enum_cmd ("calling-convention", class_vars, sh_cc_enum, | |
3013 | &sh_active_calling_convention, | |
3014 | _("Set calling convention used when calling target " | |
3015 | "functions from GDB."), | |
3016 | _("Show calling convention used when calling target " | |
3017 | "functions from GDB."), | |
3018 | _("gcc - Use GCC calling convention (default).\n" | |
3019 | "renesas - Enforce Renesas calling convention."), | |
3020 | NULL, NULL, | |
3021 | &setshcmdlist, &showshcmdlist); | |
c906108c | 3022 | } |