Commit | Line | Data |
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c906108c | 1 | /* Target-dependent code for Hitachi Super-H, for GDB. |
b6ba6518 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001 |
3116c80a | 3 | Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b JM |
17 | You should have received a copy of the GNU General Public License |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
21 | |
22 | /* | |
c5aa993b JM |
23 | Contributed by Steve Chamberlain |
24 | sac@cygnus.com | |
c906108c SS |
25 | */ |
26 | ||
27 | #include "defs.h" | |
28 | #include "frame.h" | |
29 | #include "obstack.h" | |
30 | #include "symtab.h" | |
31 | #include "symfile.h" | |
32 | #include "gdbtypes.h" | |
33 | #include "gdbcmd.h" | |
34 | #include "gdbcore.h" | |
35 | #include "value.h" | |
36 | #include "dis-asm.h" | |
37 | #include "inferior.h" /* for BEFORE_TEXT_END etc. */ | |
38 | #include "gdb_string.h" | |
b4a20239 | 39 | #include "arch-utils.h" |
fb409745 | 40 | #include "floatformat.h" |
4e052eda | 41 | #include "regcache.h" |
c906108c | 42 | |
1a8629c7 MS |
43 | #include "solib-svr4.h" |
44 | ||
cc17453a EZ |
45 | #undef XMALLOC |
46 | #define XMALLOC(TYPE) ((TYPE*) xmalloc (sizeof (TYPE))) | |
47 | ||
53116e27 | 48 | void (*sh_show_regs) (void); |
e6c42fda | 49 | int (*print_sh_insn) (bfd_vma, disassemble_info*); |
3bbfbb92 EZ |
50 | CORE_ADDR (*skip_prologue_hard_way) (CORE_ADDR); |
51 | void (*do_pseudo_register) (int); | |
cc17453a | 52 | |
cc17453a EZ |
53 | /* Define other aspects of the stack frame. |
54 | we keep a copy of the worked out return pc lying around, since it | |
55 | is a useful bit of info */ | |
56 | ||
57 | struct frame_extra_info | |
58 | { | |
59 | CORE_ADDR return_pc; | |
60 | int leaf_function; | |
61 | int f_offset; | |
63978407 | 62 | }; |
c906108c | 63 | |
cc17453a EZ |
64 | static char * |
65 | sh_generic_register_name (int reg_nr) | |
c5aa993b | 66 | { |
cc17453a | 67 | static char *register_names[] = |
c5aa993b | 68 | { |
cc17453a EZ |
69 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
70 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
71 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
72 | "fpul", "fpscr", | |
73 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", | |
74 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
75 | "ssr", "spc", | |
76 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", | |
77 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", | |
78 | }; | |
79 | if (reg_nr < 0) | |
80 | return NULL; | |
81 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
82 | return NULL; | |
83 | return register_names[reg_nr]; | |
84 | } | |
85 | ||
86 | static char * | |
87 | sh_sh_register_name (int reg_nr) | |
88 | { | |
89 | static char *register_names[] = | |
63978407 | 90 | { |
cc17453a EZ |
91 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
92 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
93 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
94 | "", "", | |
95 | "", "", "", "", "", "", "", "", | |
96 | "", "", "", "", "", "", "", "", | |
97 | "", "", | |
98 | "", "", "", "", "", "", "", "", | |
99 | "", "", "", "", "", "", "", "", | |
100 | }; | |
101 | if (reg_nr < 0) | |
102 | return NULL; | |
103 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
104 | return NULL; | |
105 | return register_names[reg_nr]; | |
106 | } | |
107 | ||
108 | static char * | |
109 | sh_sh3_register_name (int reg_nr) | |
110 | { | |
111 | static char *register_names[] = | |
c5aa993b | 112 | { |
cc17453a EZ |
113 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
114 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
115 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
116 | "", "", | |
117 | "", "", "", "", "", "", "", "", | |
118 | "", "", "", "", "", "", "", "", | |
119 | "ssr", "spc", | |
120 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", | |
121 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1" | |
122 | }; | |
123 | if (reg_nr < 0) | |
124 | return NULL; | |
125 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
126 | return NULL; | |
127 | return register_names[reg_nr]; | |
128 | } | |
129 | ||
130 | static char * | |
131 | sh_sh3e_register_name (int reg_nr) | |
132 | { | |
133 | static char *register_names[] = | |
63978407 | 134 | { |
cc17453a EZ |
135 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
136 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
137 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
138 | "fpul", "fpscr", | |
139 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", | |
140 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
141 | "ssr", "spc", | |
142 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", | |
143 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", | |
144 | }; | |
145 | if (reg_nr < 0) | |
146 | return NULL; | |
147 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
148 | return NULL; | |
149 | return register_names[reg_nr]; | |
150 | } | |
151 | ||
152 | static char * | |
153 | sh_sh_dsp_register_name (int reg_nr) | |
154 | { | |
155 | static char *register_names[] = | |
c5aa993b | 156 | { |
cc17453a EZ |
157 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
158 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
159 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
160 | "", "dsr", | |
161 | "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1", | |
162 | "y0", "y1", "", "", "", "", "", "mod", | |
163 | "", "", | |
164 | "rs", "re", "", "", "", "", "", "", | |
165 | "", "", "", "", "", "", "", "", | |
166 | }; | |
167 | if (reg_nr < 0) | |
168 | return NULL; | |
169 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
170 | return NULL; | |
171 | return register_names[reg_nr]; | |
172 | } | |
173 | ||
174 | static char * | |
175 | sh_sh3_dsp_register_name (int reg_nr) | |
176 | { | |
177 | static char *register_names[] = | |
c5aa993b | 178 | { |
cc17453a EZ |
179 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
180 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
181 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
182 | "", "dsr", | |
183 | "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1", | |
184 | "y0", "y1", "", "", "", "", "", "mod", | |
185 | "ssr", "spc", | |
186 | "rs", "re", "", "", "", "", "", "", | |
187 | "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b" | |
188 | "", "", "", "", "", "", "", "", | |
189 | }; | |
190 | if (reg_nr < 0) | |
191 | return NULL; | |
192 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
193 | return NULL; | |
194 | return register_names[reg_nr]; | |
195 | } | |
196 | ||
53116e27 EZ |
197 | static char * |
198 | sh_sh4_register_name (int reg_nr) | |
199 | { | |
200 | static char *register_names[] = | |
201 | { | |
a38d2a54 | 202 | /* general registers 0-15 */ |
53116e27 EZ |
203 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
204 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
a38d2a54 | 205 | /* 16 - 22 */ |
53116e27 | 206 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", |
a38d2a54 | 207 | /* 23, 24 */ |
53116e27 | 208 | "fpul", "fpscr", |
a38d2a54 | 209 | /* floating point registers 25 - 40 */ |
53116e27 EZ |
210 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", |
211 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
a38d2a54 | 212 | /* 41, 42 */ |
53116e27 | 213 | "ssr", "spc", |
a38d2a54 | 214 | /* bank 0 43 - 50 */ |
53116e27 | 215 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", |
a38d2a54 | 216 | /* bank 1 51 - 58 */ |
53116e27 | 217 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", |
a38d2a54 | 218 | /* double precision (pseudo) 59 - 66 */ |
fe9f384f | 219 | "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", |
a38d2a54 | 220 | /* vectors (pseudo) 67 - 70 */ |
fe9f384f | 221 | "fv0", "fv4", "fv8", "fv12", |
a38d2a54 EZ |
222 | /* FIXME: missing XF 71 - 86 */ |
223 | /* FIXME: missing XD 87 - 94 */ | |
53116e27 EZ |
224 | }; |
225 | if (reg_nr < 0) | |
226 | return NULL; | |
227 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
228 | return NULL; | |
229 | return register_names[reg_nr]; | |
230 | } | |
231 | ||
cc17453a | 232 | static unsigned char * |
fba45db2 | 233 | sh_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
cc17453a EZ |
234 | { |
235 | /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */ | |
236 | static unsigned char breakpoint[] = {0xc3, 0xc3}; | |
237 | ||
238 | *lenptr = sizeof (breakpoint); | |
239 | return breakpoint; | |
240 | } | |
c906108c SS |
241 | |
242 | /* Prologue looks like | |
c5aa993b JM |
243 | [mov.l <regs>,@-r15]... |
244 | [sts.l pr,@-r15] | |
245 | [mov.l r14,@-r15] | |
246 | [mov r15,r14] | |
8db62801 EZ |
247 | |
248 | Actually it can be more complicated than this. For instance, with | |
249 | newer gcc's: | |
250 | ||
251 | mov.l r14,@-r15 | |
252 | add #-12,r15 | |
253 | mov r15,r14 | |
254 | mov r4,r1 | |
255 | mov r5,r2 | |
256 | mov.l r6,@(4,r14) | |
257 | mov.l r7,@(8,r14) | |
258 | mov.b r1,@r14 | |
259 | mov r14,r1 | |
260 | mov r14,r1 | |
261 | add #2,r1 | |
262 | mov.w r2,@r1 | |
263 | ||
c5aa993b | 264 | */ |
c906108c | 265 | |
8db62801 EZ |
266 | /* STS.L PR,@-r15 0100111100100010 |
267 | r15-4-->r15, PR-->(r15) */ | |
c906108c | 268 | #define IS_STS(x) ((x) == 0x4f22) |
8db62801 EZ |
269 | |
270 | /* MOV.L Rm,@-r15 00101111mmmm0110 | |
271 | r15-4-->r15, Rm-->(R15) */ | |
c906108c | 272 | #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06) |
8db62801 | 273 | |
c906108c | 274 | #define GET_PUSHED_REG(x) (((x) >> 4) & 0xf) |
8db62801 EZ |
275 | |
276 | /* MOV r15,r14 0110111011110011 | |
277 | r15-->r14 */ | |
c906108c | 278 | #define IS_MOV_SP_FP(x) ((x) == 0x6ef3) |
8db62801 EZ |
279 | |
280 | /* ADD #imm,r15 01111111iiiiiiii | |
281 | r15+imm-->r15 */ | |
c906108c | 282 | #define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00) |
8db62801 | 283 | |
c906108c SS |
284 | #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00) |
285 | #define IS_SHLL_R3(x) ((x) == 0x4300) | |
8db62801 EZ |
286 | |
287 | /* ADD r3,r15 0011111100111100 | |
288 | r15+r3-->r15 */ | |
c906108c | 289 | #define IS_ADD_R3SP(x) ((x) == 0x3f3c) |
8db62801 EZ |
290 | |
291 | /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011 | |
8db62801 | 292 | FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011 |
8db62801 | 293 | FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */ |
c906108c | 294 | #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) |
c906108c | 295 | |
8db62801 | 296 | /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 |
8db62801 | 297 | MOV.L Rm,@(disp,Rn) Rm-->(dispx4+Rn) 0001nnnnmmmmdddd |
8db62801 EZ |
298 | MOV.L Rm,@Rn Rm-->(Rn) 0010nnnnmmmm0010 |
299 | where Rm is one of r4,r5,r6,r7 which are the argument registers. */ | |
300 | #define IS_ARG_MOV(x) \ | |
301 | (((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) \ | |
cc17453a EZ |
302 | || ((((x) & 0xf000) == 0x1000) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) \ |
303 | || ((((x) & 0xf00f) == 0x2002) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070))) | |
8db62801 EZ |
304 | |
305 | /* MOV.L Rm,@(disp,r14) 00011110mmmmdddd | |
306 | Rm-->(dispx4+r14) where Rm is one of r4,r5,r6,r7 */ | |
3bbfbb92 | 307 | #define IS_MOV_TO_R14(x) \ |
cc17453a | 308 | ((((x) & 0xff00) == 0x1e) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) |
8db62801 EZ |
309 | |
310 | #define FPSCR_SZ (1 << 20) | |
c906108c | 311 | |
c906108c SS |
312 | /* Skip any prologue before the guts of a function */ |
313 | ||
8db62801 EZ |
314 | /* Skip the prologue using the debug information. If this fails we'll |
315 | fall back on the 'guess' method below. */ | |
316 | static CORE_ADDR | |
fba45db2 | 317 | after_prologue (CORE_ADDR pc) |
8db62801 EZ |
318 | { |
319 | struct symtab_and_line sal; | |
320 | CORE_ADDR func_addr, func_end; | |
321 | ||
322 | /* If we can not find the symbol in the partial symbol table, then | |
323 | there is no hope we can determine the function's start address | |
324 | with this code. */ | |
325 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
326 | return 0; | |
327 | ||
328 | /* Get the line associated with FUNC_ADDR. */ | |
329 | sal = find_pc_line (func_addr, 0); | |
330 | ||
331 | /* There are only two cases to consider. First, the end of the source line | |
332 | is within the function bounds. In that case we return the end of the | |
333 | source line. Second is the end of the source line extends beyond the | |
334 | bounds of the current function. We need to use the slow code to | |
335 | examine instructions in that case. */ | |
336 | if (sal.end < func_end) | |
337 | return sal.end; | |
338 | else | |
339 | return 0; | |
340 | } | |
341 | ||
342 | /* Here we look at each instruction in the function, and try to guess | |
343 | where the prologue ends. Unfortunately this is not always | |
344 | accurate. */ | |
345 | static CORE_ADDR | |
3bbfbb92 | 346 | sh_skip_prologue_hard_way (CORE_ADDR start_pc) |
c906108c | 347 | { |
2bfa91ee | 348 | CORE_ADDR here, end; |
8db62801 | 349 | int updated_fp = 0; |
2bfa91ee EZ |
350 | |
351 | if (!start_pc) | |
352 | return 0; | |
353 | ||
354 | for (here = start_pc, end = start_pc + (2 * 28); here < end;) | |
c906108c | 355 | { |
2bfa91ee EZ |
356 | int w = read_memory_integer (here, 2); |
357 | here += 2; | |
358 | if (IS_FMOV (w) || IS_PUSH (w) || IS_STS (w) || IS_MOV_R3 (w) | |
8db62801 | 359 | || IS_ADD_R3SP (w) || IS_ADD_SP (w) || IS_SHLL_R3 (w) |
3bbfbb92 | 360 | || IS_ARG_MOV (w) || IS_MOV_TO_R14 (w)) |
2bfa91ee EZ |
361 | { |
362 | start_pc = here; | |
2bfa91ee | 363 | } |
8db62801 EZ |
364 | else if (IS_MOV_SP_FP (w)) |
365 | { | |
366 | start_pc = here; | |
367 | updated_fp = 1; | |
368 | } | |
369 | else | |
370 | /* Don't bail out yet, if we are before the copy of sp. */ | |
371 | if (updated_fp) | |
372 | break; | |
c906108c SS |
373 | } |
374 | ||
375 | return start_pc; | |
376 | } | |
377 | ||
cc17453a | 378 | static CORE_ADDR |
fba45db2 | 379 | sh_skip_prologue (CORE_ADDR pc) |
8db62801 EZ |
380 | { |
381 | CORE_ADDR post_prologue_pc; | |
382 | ||
383 | /* See if we can determine the end of the prologue via the symbol table. | |
384 | If so, then return either PC, or the PC after the prologue, whichever | |
385 | is greater. */ | |
8db62801 EZ |
386 | post_prologue_pc = after_prologue (pc); |
387 | ||
388 | /* If after_prologue returned a useful address, then use it. Else | |
389 | fall back on the instruction skipping code. */ | |
390 | if (post_prologue_pc != 0) | |
391 | return max (pc, post_prologue_pc); | |
392 | else | |
393 | return (skip_prologue_hard_way (pc)); | |
394 | } | |
395 | ||
cc17453a EZ |
396 | /* Immediately after a function call, return the saved pc. |
397 | Can't always go through the frames for this because on some machines | |
398 | the new frame is not set up until the new function executes | |
399 | some instructions. | |
400 | ||
401 | The return address is the value saved in the PR register + 4 */ | |
402 | static CORE_ADDR | |
fba45db2 | 403 | sh_saved_pc_after_call (struct frame_info *frame) |
cc17453a | 404 | { |
3bbfbb92 | 405 | return (ADDR_BITS_REMOVE (read_register (gdbarch_tdep (current_gdbarch)->PR_REGNUM))); |
cc17453a EZ |
406 | } |
407 | ||
408 | /* Should call_function allocate stack space for a struct return? */ | |
409 | static int | |
fba45db2 | 410 | sh_use_struct_convention (int gcc_p, struct type *type) |
cc17453a EZ |
411 | { |
412 | return (TYPE_LENGTH (type) > 1); | |
413 | } | |
414 | ||
415 | /* Store the address of the place in which to copy the structure the | |
416 | subroutine will return. This is called from call_function. | |
417 | ||
3bbfbb92 | 418 | We store structs through a pointer passed in R2 */ |
cc17453a | 419 | static void |
fba45db2 | 420 | sh_store_struct_return (CORE_ADDR addr, CORE_ADDR sp) |
cc17453a EZ |
421 | { |
422 | write_register (STRUCT_RETURN_REGNUM, (addr)); | |
423 | } | |
c906108c | 424 | |
cc17453a EZ |
425 | /* Disassemble an instruction. */ |
426 | static int | |
fba45db2 | 427 | gdb_print_insn_sh (bfd_vma memaddr, disassemble_info *info) |
c906108c SS |
428 | { |
429 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
430 | return print_insn_sh (memaddr, info); | |
431 | else | |
432 | return print_insn_shl (memaddr, info); | |
433 | } | |
434 | ||
435 | /* Given a GDB frame, determine the address of the calling function's frame. | |
436 | This will be used to create a new GDB frame struct, and then | |
437 | INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame. | |
438 | ||
439 | For us, the frame address is its stack pointer value, so we look up | |
440 | the function prologue to determine the caller's sp value, and return it. */ | |
cc17453a | 441 | static CORE_ADDR |
fba45db2 | 442 | sh_frame_chain (struct frame_info *frame) |
c906108c SS |
443 | { |
444 | if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame)) | |
445 | return frame->frame; /* dummy frame same as caller's frame */ | |
2bfa91ee | 446 | if (frame->pc && !inside_entry_file (frame->pc)) |
cc17453a | 447 | return read_memory_integer (FRAME_FP (frame) + frame->extra_info->f_offset, 4); |
c906108c SS |
448 | else |
449 | return 0; | |
450 | } | |
451 | ||
452 | /* Find REGNUM on the stack. Otherwise, it's in an active register. One thing | |
453 | we might want to do here is to check REGNUM against the clobber mask, and | |
454 | somehow flag it as invalid if it isn't saved on the stack somewhere. This | |
455 | would provide a graceful failure mode when trying to get the value of | |
456 | caller-saves registers for an inner frame. */ | |
cc17453a | 457 | static CORE_ADDR |
fba45db2 | 458 | sh_find_callers_reg (struct frame_info *fi, int regnum) |
c906108c | 459 | { |
c906108c SS |
460 | for (; fi; fi = fi->next) |
461 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) | |
462 | /* When the caller requests PR from the dummy frame, we return PC because | |
c5aa993b | 463 | that's where the previous routine appears to have done a call from. */ |
c906108c | 464 | return generic_read_register_dummy (fi->pc, fi->frame, regnum); |
c5aa993b | 465 | else |
c906108c | 466 | { |
cc17453a | 467 | FRAME_INIT_SAVED_REGS (fi); |
2bfa91ee EZ |
468 | if (!fi->pc) |
469 | return 0; | |
cc17453a EZ |
470 | if (fi->saved_regs[regnum] != 0) |
471 | return read_memory_integer (fi->saved_regs[regnum], | |
c5aa993b | 472 | REGISTER_RAW_SIZE (regnum)); |
c906108c SS |
473 | } |
474 | return read_register (regnum); | |
475 | } | |
476 | ||
477 | /* Put here the code to store, into a struct frame_saved_regs, the | |
478 | addresses of the saved registers of frame described by FRAME_INFO. | |
479 | This includes special registers such as pc and fp saved in special | |
480 | ways in the stack frame. sp is even more special: the address we | |
481 | return for it IS the sp for the next frame. */ | |
cc17453a | 482 | static void |
fba45db2 | 483 | sh_nofp_frame_init_saved_regs (struct frame_info *fi) |
c906108c SS |
484 | { |
485 | int where[NUM_REGS]; | |
486 | int rn; | |
487 | int have_fp = 0; | |
488 | int depth; | |
489 | int pc; | |
490 | int opc; | |
491 | int insn; | |
492 | int r3_val = 0; | |
c5aa993b | 493 | char *dummy_regs = generic_find_dummy_frame (fi->pc, fi->frame); |
cc17453a EZ |
494 | |
495 | if (fi->saved_regs == NULL) | |
496 | frame_saved_regs_zalloc (fi); | |
497 | else | |
498 | memset (fi->saved_regs, 0, SIZEOF_FRAME_SAVED_REGS); | |
499 | ||
500 | if (dummy_regs) | |
501 | { | |
502 | /* DANGER! This is ONLY going to work if the char buffer format of | |
503 | the saved registers is byte-for-byte identical to the | |
504 | CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */ | |
505 | memcpy (fi->saved_regs, dummy_regs, sizeof (fi->saved_regs)); | |
506 | return; | |
507 | } | |
508 | ||
509 | fi->extra_info->leaf_function = 1; | |
510 | fi->extra_info->f_offset = 0; | |
511 | ||
512 | for (rn = 0; rn < NUM_REGS; rn++) | |
513 | where[rn] = -1; | |
514 | ||
515 | depth = 0; | |
516 | ||
517 | /* Loop around examining the prologue insns until we find something | |
518 | that does not appear to be part of the prologue. But give up | |
519 | after 20 of them, since we're getting silly then. */ | |
520 | ||
521 | pc = get_pc_function_start (fi->pc); | |
522 | if (!pc) | |
523 | { | |
524 | fi->pc = 0; | |
525 | return; | |
526 | } | |
527 | ||
528 | for (opc = pc + (2 * 28); pc < opc; pc += 2) | |
529 | { | |
530 | insn = read_memory_integer (pc, 2); | |
531 | /* See where the registers will be saved to */ | |
532 | if (IS_PUSH (insn)) | |
533 | { | |
534 | rn = GET_PUSHED_REG (insn); | |
535 | where[rn] = depth; | |
536 | depth += 4; | |
537 | } | |
538 | else if (IS_STS (insn)) | |
539 | { | |
3bbfbb92 | 540 | where[gdbarch_tdep (current_gdbarch)->PR_REGNUM] = depth; |
cc17453a EZ |
541 | /* If we're storing the pr then this isn't a leaf */ |
542 | fi->extra_info->leaf_function = 0; | |
543 | depth += 4; | |
544 | } | |
545 | else if (IS_MOV_R3 (insn)) | |
546 | { | |
547 | r3_val = ((insn & 0xff) ^ 0x80) - 0x80; | |
548 | } | |
549 | else if (IS_SHLL_R3 (insn)) | |
550 | { | |
551 | r3_val <<= 1; | |
552 | } | |
553 | else if (IS_ADD_R3SP (insn)) | |
554 | { | |
555 | depth += -r3_val; | |
556 | } | |
557 | else if (IS_ADD_SP (insn)) | |
558 | { | |
559 | depth -= ((insn & 0xff) ^ 0x80) - 0x80; | |
560 | } | |
561 | else if (IS_MOV_SP_FP (insn)) | |
562 | break; | |
563 | #if 0 /* This used to just stop when it found an instruction that | |
564 | was not considered part of the prologue. Now, we just | |
565 | keep going looking for likely instructions. */ | |
566 | else | |
567 | break; | |
568 | #endif | |
569 | } | |
570 | ||
571 | /* Now we know how deep things are, we can work out their addresses */ | |
572 | ||
573 | for (rn = 0; rn < NUM_REGS; rn++) | |
574 | { | |
575 | if (where[rn] >= 0) | |
576 | { | |
577 | if (rn == FP_REGNUM) | |
578 | have_fp = 1; | |
c906108c | 579 | |
cc17453a EZ |
580 | fi->saved_regs[rn] = fi->frame - where[rn] + depth - 4; |
581 | } | |
582 | else | |
583 | { | |
584 | fi->saved_regs[rn] = 0; | |
585 | } | |
586 | } | |
587 | ||
588 | if (have_fp) | |
589 | { | |
590 | fi->saved_regs[SP_REGNUM] = read_memory_integer (fi->saved_regs[FP_REGNUM], 4); | |
591 | } | |
592 | else | |
593 | { | |
594 | fi->saved_regs[SP_REGNUM] = fi->frame - 4; | |
595 | } | |
596 | ||
597 | fi->extra_info->f_offset = depth - where[FP_REGNUM] - 4; | |
598 | /* Work out the return pc - either from the saved pr or the pr | |
599 | value */ | |
600 | } | |
601 | ||
3bbfbb92 EZ |
602 | /* For vectors of 4 floating point registers. */ |
603 | static int | |
604 | fv_reg_base_num (int fv_regnum) | |
605 | { | |
606 | int fp_regnum; | |
607 | ||
608 | fp_regnum = FP0_REGNUM + | |
609 | (fv_regnum - gdbarch_tdep (current_gdbarch)->FV0_REGNUM) * 4; | |
610 | return fp_regnum; | |
611 | } | |
612 | ||
613 | /* For double precision floating point registers, i.e 2 fp regs.*/ | |
614 | static int | |
615 | dr_reg_base_num (int dr_regnum) | |
616 | { | |
617 | int fp_regnum; | |
618 | ||
619 | fp_regnum = FP0_REGNUM + | |
620 | (dr_regnum - gdbarch_tdep (current_gdbarch)->DR0_REGNUM) * 2; | |
621 | return fp_regnum; | |
622 | } | |
623 | ||
cc17453a | 624 | static void |
fba45db2 | 625 | sh_fp_frame_init_saved_regs (struct frame_info *fi) |
cc17453a EZ |
626 | { |
627 | int where[NUM_REGS]; | |
628 | int rn; | |
629 | int have_fp = 0; | |
630 | int depth; | |
631 | int pc; | |
632 | int opc; | |
633 | int insn; | |
634 | int r3_val = 0; | |
635 | char *dummy_regs = generic_find_dummy_frame (fi->pc, fi->frame); | |
636 | ||
637 | if (fi->saved_regs == NULL) | |
638 | frame_saved_regs_zalloc (fi); | |
639 | else | |
640 | memset (fi->saved_regs, 0, SIZEOF_FRAME_SAVED_REGS); | |
641 | ||
c906108c SS |
642 | if (dummy_regs) |
643 | { | |
644 | /* DANGER! This is ONLY going to work if the char buffer format of | |
c5aa993b JM |
645 | the saved registers is byte-for-byte identical to the |
646 | CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */ | |
cc17453a | 647 | memcpy (fi->saved_regs, dummy_regs, sizeof (fi->saved_regs)); |
c906108c SS |
648 | return; |
649 | } | |
650 | ||
cc17453a EZ |
651 | fi->extra_info->leaf_function = 1; |
652 | fi->extra_info->f_offset = 0; | |
c906108c SS |
653 | |
654 | for (rn = 0; rn < NUM_REGS; rn++) | |
655 | where[rn] = -1; | |
656 | ||
657 | depth = 0; | |
658 | ||
659 | /* Loop around examining the prologue insns until we find something | |
660 | that does not appear to be part of the prologue. But give up | |
661 | after 20 of them, since we're getting silly then. */ | |
662 | ||
2bfa91ee EZ |
663 | pc = get_pc_function_start (fi->pc); |
664 | if (!pc) | |
c906108c | 665 | { |
2bfa91ee EZ |
666 | fi->pc = 0; |
667 | return; | |
668 | } | |
669 | ||
670 | for (opc = pc + (2 * 28); pc < opc; pc += 2) | |
671 | { | |
672 | insn = read_memory_integer (pc, 2); | |
c906108c SS |
673 | /* See where the registers will be saved to */ |
674 | if (IS_PUSH (insn)) | |
675 | { | |
c906108c SS |
676 | rn = GET_PUSHED_REG (insn); |
677 | where[rn] = depth; | |
c906108c SS |
678 | depth += 4; |
679 | } | |
680 | else if (IS_STS (insn)) | |
681 | { | |
3bbfbb92 | 682 | where[gdbarch_tdep (current_gdbarch)->PR_REGNUM] = depth; |
c906108c | 683 | /* If we're storing the pr then this isn't a leaf */ |
cc17453a | 684 | fi->extra_info->leaf_function = 0; |
c906108c SS |
685 | depth += 4; |
686 | } | |
687 | else if (IS_MOV_R3 (insn)) | |
688 | { | |
689 | r3_val = ((insn & 0xff) ^ 0x80) - 0x80; | |
c906108c SS |
690 | } |
691 | else if (IS_SHLL_R3 (insn)) | |
692 | { | |
693 | r3_val <<= 1; | |
c906108c SS |
694 | } |
695 | else if (IS_ADD_R3SP (insn)) | |
696 | { | |
697 | depth += -r3_val; | |
c906108c SS |
698 | } |
699 | else if (IS_ADD_SP (insn)) | |
700 | { | |
c906108c | 701 | depth -= ((insn & 0xff) ^ 0x80) - 0x80; |
c906108c SS |
702 | } |
703 | else if (IS_FMOV (insn)) | |
704 | { | |
cc17453a | 705 | if (read_register (gdbarch_tdep (current_gdbarch)->FPSCR_REGNUM) & FPSCR_SZ) |
c906108c SS |
706 | { |
707 | depth += 8; | |
708 | } | |
709 | else | |
710 | { | |
711 | depth += 4; | |
712 | } | |
713 | } | |
2bfa91ee EZ |
714 | else if (IS_MOV_SP_FP (insn)) |
715 | break; | |
716 | #if 0 /* This used to just stop when it found an instruction that | |
717 | was not considered part of the prologue. Now, we just | |
718 | keep going looking for likely instructions. */ | |
c906108c SS |
719 | else |
720 | break; | |
2bfa91ee | 721 | #endif |
c906108c SS |
722 | } |
723 | ||
724 | /* Now we know how deep things are, we can work out their addresses */ | |
725 | ||
726 | for (rn = 0; rn < NUM_REGS; rn++) | |
727 | { | |
728 | if (where[rn] >= 0) | |
729 | { | |
730 | if (rn == FP_REGNUM) | |
731 | have_fp = 1; | |
732 | ||
cc17453a | 733 | fi->saved_regs[rn] = fi->frame - where[rn] + depth - 4; |
c906108c SS |
734 | } |
735 | else | |
736 | { | |
cc17453a | 737 | fi->saved_regs[rn] = 0; |
c906108c SS |
738 | } |
739 | } | |
740 | ||
741 | if (have_fp) | |
742 | { | |
cc17453a | 743 | fi->saved_regs[SP_REGNUM] = read_memory_integer (fi->saved_regs[FP_REGNUM], 4); |
c906108c SS |
744 | } |
745 | else | |
746 | { | |
cc17453a | 747 | fi->saved_regs[SP_REGNUM] = fi->frame - 4; |
c906108c SS |
748 | } |
749 | ||
cc17453a | 750 | fi->extra_info->f_offset = depth - where[FP_REGNUM] - 4; |
c906108c SS |
751 | /* Work out the return pc - either from the saved pr or the pr |
752 | value */ | |
753 | } | |
754 | ||
cc17453a EZ |
755 | /* Initialize the extra info saved in a FRAME */ |
756 | static void | |
fba45db2 | 757 | sh_init_extra_frame_info (int fromleaf, struct frame_info *fi) |
c906108c | 758 | { |
cc17453a EZ |
759 | |
760 | fi->extra_info = (struct frame_extra_info *) | |
761 | frame_obstack_alloc (sizeof (struct frame_extra_info)); | |
c906108c SS |
762 | |
763 | if (fi->next) | |
764 | fi->pc = FRAME_SAVED_PC (fi->next); | |
765 | ||
766 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) | |
767 | { | |
768 | /* We need to setup fi->frame here because run_stack_dummy gets it wrong | |
c5aa993b JM |
769 | by assuming it's always FP. */ |
770 | fi->frame = generic_read_register_dummy (fi->pc, fi->frame, | |
771 | SP_REGNUM); | |
cc17453a EZ |
772 | fi->extra_info->return_pc = generic_read_register_dummy (fi->pc, fi->frame, |
773 | PC_REGNUM); | |
774 | fi->extra_info->f_offset = -(CALL_DUMMY_LENGTH + 4); | |
775 | fi->extra_info->leaf_function = 0; | |
c906108c SS |
776 | return; |
777 | } | |
778 | else | |
779 | { | |
cc17453a | 780 | FRAME_INIT_SAVED_REGS (fi); |
3bbfbb92 | 781 | fi->extra_info->return_pc = sh_find_callers_reg (fi, gdbarch_tdep (current_gdbarch)->PR_REGNUM); |
c906108c SS |
782 | } |
783 | } | |
784 | ||
cc17453a EZ |
785 | /* Extract from an array REGBUF containing the (raw) register state |
786 | the address in which a function should return its structure value, | |
787 | as a CORE_ADDR (or an expression that can be used as one). */ | |
b3df3fff | 788 | static CORE_ADDR |
0c8053b6 | 789 | sh_extract_struct_value_address (char *regbuf) |
cc17453a EZ |
790 | { |
791 | return (extract_address ((regbuf), REGISTER_RAW_SIZE (0))); | |
792 | } | |
793 | ||
794 | static CORE_ADDR | |
fba45db2 | 795 | sh_frame_saved_pc (struct frame_info *frame) |
cc17453a EZ |
796 | { |
797 | return ((frame)->extra_info->return_pc); | |
798 | } | |
799 | ||
c906108c SS |
800 | /* Discard from the stack the innermost frame, |
801 | restoring all saved registers. */ | |
cc17453a | 802 | static void |
fba45db2 | 803 | sh_pop_frame (void) |
c906108c SS |
804 | { |
805 | register struct frame_info *frame = get_current_frame (); | |
806 | register CORE_ADDR fp; | |
807 | register int regnum; | |
c906108c SS |
808 | |
809 | if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame)) | |
810 | generic_pop_dummy_frame (); | |
811 | else | |
c5aa993b JM |
812 | { |
813 | fp = FRAME_FP (frame); | |
cc17453a | 814 | FRAME_INIT_SAVED_REGS (frame); |
c906108c | 815 | |
c5aa993b JM |
816 | /* Copy regs from where they were saved in the frame */ |
817 | for (regnum = 0; regnum < NUM_REGS; regnum++) | |
cc17453a EZ |
818 | if (frame->saved_regs[regnum]) |
819 | write_register (regnum, read_memory_integer (frame->saved_regs[regnum], 4)); | |
c906108c | 820 | |
cc17453a | 821 | write_register (PC_REGNUM, frame->extra_info->return_pc); |
c5aa993b JM |
822 | write_register (SP_REGNUM, fp + 4); |
823 | } | |
c906108c SS |
824 | flush_cached_frames (); |
825 | } | |
826 | ||
827 | /* Function: push_arguments | |
828 | Setup the function arguments for calling a function in the inferior. | |
829 | ||
830 | On the Hitachi SH architecture, there are four registers (R4 to R7) | |
831 | which are dedicated for passing function arguments. Up to the first | |
832 | four arguments (depending on size) may go into these registers. | |
833 | The rest go on the stack. | |
834 | ||
835 | Arguments that are smaller than 4 bytes will still take up a whole | |
836 | register or a whole 32-bit word on the stack, and will be | |
837 | right-justified in the register or the stack word. This includes | |
838 | chars, shorts, and small aggregate types. | |
839 | ||
840 | Arguments that are larger than 4 bytes may be split between two or | |
841 | more registers. If there are not enough registers free, an argument | |
842 | may be passed partly in a register (or registers), and partly on the | |
843 | stack. This includes doubles, long longs, and larger aggregates. | |
844 | As far as I know, there is no upper limit to the size of aggregates | |
845 | that will be passed in this way; in other words, the convention of | |
846 | passing a pointer to a large aggregate instead of a copy is not used. | |
847 | ||
848 | An exceptional case exists for struct arguments (and possibly other | |
849 | aggregates such as arrays) if the size is larger than 4 bytes but | |
850 | not a multiple of 4 bytes. In this case the argument is never split | |
851 | between the registers and the stack, but instead is copied in its | |
852 | entirety onto the stack, AND also copied into as many registers as | |
853 | there is room for. In other words, space in registers permitting, | |
854 | two copies of the same argument are passed in. As far as I can tell, | |
855 | only the one on the stack is used, although that may be a function | |
856 | of the level of compiler optimization. I suspect this is a compiler | |
857 | bug. Arguments of these odd sizes are left-justified within the | |
858 | word (as opposed to arguments smaller than 4 bytes, which are | |
859 | right-justified). | |
c5aa993b | 860 | |
c906108c SS |
861 | If the function is to return an aggregate type such as a struct, it |
862 | is either returned in the normal return value register R0 (if its | |
863 | size is no greater than one byte), or else the caller must allocate | |
864 | space into which the callee will copy the return value (if the size | |
865 | is greater than one byte). In this case, a pointer to the return | |
866 | value location is passed into the callee in register R2, which does | |
867 | not displace any of the other arguments passed in via registers R4 | |
868 | to R7. */ | |
869 | ||
cc17453a | 870 | static CORE_ADDR |
34e9d9bb | 871 | sh_push_arguments (int nargs, struct value **args, CORE_ADDR sp, |
3bbfbb92 | 872 | int struct_return, CORE_ADDR struct_addr) |
c906108c SS |
873 | { |
874 | int stack_offset, stack_alloc; | |
875 | int argreg; | |
876 | int argnum; | |
877 | struct type *type; | |
878 | CORE_ADDR regval; | |
879 | char *val; | |
880 | char valbuf[4]; | |
881 | int len; | |
882 | int odd_sized_struct; | |
883 | ||
884 | /* first force sp to a 4-byte alignment */ | |
885 | sp = sp & ~3; | |
886 | ||
887 | /* The "struct return pointer" pseudo-argument has its own dedicated | |
888 | register */ | |
889 | if (struct_return) | |
c5aa993b | 890 | write_register (STRUCT_RETURN_REGNUM, struct_addr); |
c906108c SS |
891 | |
892 | /* Now make sure there's space on the stack */ | |
cc17453a | 893 | for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++) |
c5aa993b JM |
894 | stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 3) & ~3); |
895 | sp -= stack_alloc; /* make room on stack for args */ | |
c906108c | 896 | |
c906108c SS |
897 | /* Now load as many as possible of the first arguments into |
898 | registers, and push the rest onto the stack. There are 16 bytes | |
899 | in four registers available. Loop thru args from first to last. */ | |
900 | ||
3bbfbb92 | 901 | argreg = gdbarch_tdep (current_gdbarch)->ARG0_REGNUM; |
c906108c SS |
902 | for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++) |
903 | { | |
904 | type = VALUE_TYPE (args[argnum]); | |
c5aa993b JM |
905 | len = TYPE_LENGTH (type); |
906 | memset (valbuf, 0, sizeof (valbuf)); | |
c906108c | 907 | if (len < 4) |
cc17453a EZ |
908 | { |
909 | /* value gets right-justified in the register or stack word */ | |
c5aa993b JM |
910 | memcpy (valbuf + (4 - len), |
911 | (char *) VALUE_CONTENTS (args[argnum]), len); | |
912 | val = valbuf; | |
913 | } | |
c906108c | 914 | else |
c5aa993b | 915 | val = (char *) VALUE_CONTENTS (args[argnum]); |
c906108c SS |
916 | |
917 | if (len > 4 && (len & 3) != 0) | |
c5aa993b JM |
918 | odd_sized_struct = 1; /* such structs go entirely on stack */ |
919 | else | |
c906108c SS |
920 | odd_sized_struct = 0; |
921 | while (len > 0) | |
922 | { | |
3bbfbb92 EZ |
923 | if (argreg > gdbarch_tdep (current_gdbarch)->ARGLAST_REGNUM |
924 | || odd_sized_struct) | |
925 | { | |
926 | /* must go on the stack */ | |
c906108c SS |
927 | write_memory (sp + stack_offset, val, 4); |
928 | stack_offset += 4; | |
929 | } | |
930 | /* NOTE WELL!!!!! This is not an "else if" clause!!! | |
931 | That's because some *&^%$ things get passed on the stack | |
932 | AND in the registers! */ | |
3bbfbb92 EZ |
933 | if (argreg <= gdbarch_tdep (current_gdbarch)->ARGLAST_REGNUM) |
934 | { | |
935 | /* there's room in a register */ | |
c5aa993b | 936 | regval = extract_address (val, REGISTER_RAW_SIZE (argreg)); |
c906108c SS |
937 | write_register (argreg++, regval); |
938 | } | |
939 | /* Store the value 4 bytes at a time. This means that things | |
940 | larger than 4 bytes may go partly in registers and partly | |
941 | on the stack. */ | |
c5aa993b JM |
942 | len -= REGISTER_RAW_SIZE (argreg); |
943 | val += REGISTER_RAW_SIZE (argreg); | |
c906108c SS |
944 | } |
945 | } | |
946 | return sp; | |
947 | } | |
948 | ||
949 | /* Function: push_return_address (pc) | |
950 | Set up the return address for the inferior function call. | |
951 | Needed for targets where we don't actually execute a JSR/BSR instruction */ | |
952 | ||
cc17453a | 953 | static CORE_ADDR |
fba45db2 | 954 | sh_push_return_address (CORE_ADDR pc, CORE_ADDR sp) |
c906108c | 955 | { |
3bbfbb92 | 956 | write_register (gdbarch_tdep (current_gdbarch)->PR_REGNUM, CALL_DUMMY_ADDRESS ()); |
c906108c SS |
957 | return sp; |
958 | } | |
959 | ||
960 | /* Function: fix_call_dummy | |
961 | Poke the callee function's address into the destination part of | |
962 | the CALL_DUMMY. The address is actually stored in a data word | |
963 | following the actualy CALL_DUMMY instructions, which will load | |
964 | it into a register using PC-relative addressing. This function | |
965 | expects the CALL_DUMMY to look like this: | |
966 | ||
c5aa993b JM |
967 | mov.w @(2,PC), R8 |
968 | jsr @R8 | |
969 | nop | |
970 | trap | |
971 | <destination> | |
972 | */ | |
c906108c SS |
973 | |
974 | #if 0 | |
975 | void | |
fba45db2 | 976 | sh_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, int nargs, |
ea7c478f | 977 | struct value **args, struct type *type, int gcc_p) |
c906108c SS |
978 | { |
979 | *(unsigned long *) (dummy + 8) = fun; | |
980 | } | |
981 | #endif | |
982 | ||
cc17453a EZ |
983 | static int |
984 | sh_coerce_float_to_double (struct type *formal, struct type *actual) | |
985 | { | |
986 | return 1; | |
987 | } | |
c906108c | 988 | |
cc17453a EZ |
989 | /* Find a function's return value in the appropriate registers (in |
990 | regbuf), and copy it into valbuf. Extract from an array REGBUF | |
991 | containing the (raw) register state a function return value of type | |
992 | TYPE, and copy that, in virtual format, into VALBUF. */ | |
993 | static void | |
fba45db2 | 994 | sh_extract_return_value (struct type *type, char *regbuf, char *valbuf) |
c906108c | 995 | { |
cc17453a | 996 | int len = TYPE_LENGTH (type); |
3116c80a EZ |
997 | int return_register = R0_REGNUM; |
998 | int offset; | |
999 | ||
cc17453a | 1000 | if (len <= 4) |
3116c80a EZ |
1001 | { |
1002 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
1003 | offset = REGISTER_BYTE (return_register) + 4 - len; | |
1004 | else | |
1005 | offset = REGISTER_BYTE (return_register); | |
1006 | memcpy (valbuf, regbuf + offset, len); | |
1007 | } | |
cc17453a | 1008 | else if (len <= 8) |
3116c80a EZ |
1009 | { |
1010 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
1011 | offset = REGISTER_BYTE (return_register) + 8 - len; | |
1012 | else | |
1013 | offset = REGISTER_BYTE (return_register); | |
1014 | memcpy (valbuf, regbuf + offset, len); | |
1015 | } | |
1016 | else | |
1017 | error ("bad size for return value"); | |
1018 | } | |
1019 | ||
1020 | static void | |
1021 | sh3e_sh4_extract_return_value (struct type *type, char *regbuf, char *valbuf) | |
1022 | { | |
1023 | int return_register; | |
1024 | int offset; | |
1025 | int len = TYPE_LENGTH (type); | |
1026 | ||
1027 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
1028 | return_register = FP0_REGNUM; | |
1029 | else | |
1030 | return_register = R0_REGNUM; | |
1031 | ||
1032 | if (len == 8 && TYPE_CODE (type) == TYPE_CODE_FLT) | |
1033 | { | |
1034 | DOUBLEST val; | |
1035 | if (TARGET_BYTE_ORDER == LITTLE_ENDIAN) | |
1036 | floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, | |
1037 | (char *) regbuf + REGISTER_BYTE (return_register), | |
1038 | &val); | |
1039 | else | |
1040 | floatformat_to_doublest (&floatformat_ieee_double_big, | |
1041 | (char *) regbuf + REGISTER_BYTE (return_register), | |
1042 | &val); | |
1043 | store_floating (valbuf, len, val); | |
1044 | } | |
1045 | else if (len <= 4) | |
1046 | { | |
1047 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
1048 | offset = REGISTER_BYTE (return_register) + 4 - len; | |
1049 | else | |
1050 | offset = REGISTER_BYTE (return_register); | |
1051 | memcpy (valbuf, regbuf + offset, len); | |
1052 | } | |
1053 | else if (len <= 8) | |
1054 | { | |
1055 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
1056 | offset = REGISTER_BYTE (return_register) + 8 - len; | |
1057 | else | |
1058 | offset = REGISTER_BYTE (return_register); | |
1059 | memcpy (valbuf, regbuf + offset, len); | |
1060 | } | |
cc17453a EZ |
1061 | else |
1062 | error ("bad size for return value"); | |
1063 | } | |
c906108c | 1064 | |
cc17453a EZ |
1065 | /* Write into appropriate registers a function return value |
1066 | of type TYPE, given in virtual format. | |
1067 | If the architecture is sh4 or sh3e, store a function's return value | |
1068 | in the R0 general register or in the FP0 floating point register, | |
1069 | depending on the type of the return value. In all the other cases | |
3bbfbb92 | 1070 | the result is stored in r0, left-justified. */ |
cc17453a EZ |
1071 | static void |
1072 | sh_default_store_return_value (struct type *type, char *valbuf) | |
1073 | { | |
d19b71be MS |
1074 | char buf[32]; /* more than enough... */ |
1075 | ||
1076 | if (TYPE_LENGTH (type) < REGISTER_RAW_SIZE (R0_REGNUM)) | |
1077 | { | |
1078 | /* Add leading zeros to the value. */ | |
1079 | memset (buf, 0, REGISTER_RAW_SIZE (R0_REGNUM)); | |
1080 | memcpy (buf + REGISTER_RAW_SIZE (R0_REGNUM) - TYPE_LENGTH (type), | |
1081 | valbuf, TYPE_LENGTH (type)); | |
1082 | write_register_bytes (REGISTER_BYTE (R0_REGNUM), buf, | |
1083 | REGISTER_RAW_SIZE (R0_REGNUM)); | |
1084 | } | |
1085 | else | |
1086 | write_register_bytes (REGISTER_BYTE (R0_REGNUM), valbuf, | |
1087 | TYPE_LENGTH (type)); | |
cc17453a | 1088 | } |
c906108c | 1089 | |
cc17453a EZ |
1090 | static void |
1091 | sh3e_sh4_store_return_value (struct type *type, char *valbuf) | |
1092 | { | |
1093 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
1094 | write_register_bytes (REGISTER_BYTE (FP0_REGNUM), | |
1095 | valbuf, TYPE_LENGTH (type)); | |
1096 | else | |
d19b71be | 1097 | sh_default_store_return_value (type, valbuf); |
c906108c SS |
1098 | } |
1099 | ||
1100 | /* Print the registers in a form similar to the E7000 */ | |
1101 | ||
1102 | static void | |
fba45db2 | 1103 | sh_generic_show_regs (void) |
c906108c | 1104 | { |
cc17453a EZ |
1105 | printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", |
1106 | paddr (read_register (PC_REGNUM)), | |
c62a7c7b | 1107 | (long) read_register (gdbarch_tdep (current_gdbarch)->SR_REGNUM), |
3bbfbb92 | 1108 | (long) read_register (gdbarch_tdep (current_gdbarch)->PR_REGNUM), |
cc17453a EZ |
1109 | (long) read_register (MACH_REGNUM), |
1110 | (long) read_register (MACL_REGNUM)); | |
1111 | ||
1112 | printf_filtered ("GBR=%08lx VBR=%08lx", | |
1113 | (long) read_register (GBR_REGNUM), | |
1114 | (long) read_register (VBR_REGNUM)); | |
1115 | ||
1116 | printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1117 | (long) read_register (0), | |
1118 | (long) read_register (1), | |
1119 | (long) read_register (2), | |
1120 | (long) read_register (3), | |
1121 | (long) read_register (4), | |
1122 | (long) read_register (5), | |
1123 | (long) read_register (6), | |
1124 | (long) read_register (7)); | |
1125 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1126 | (long) read_register (8), | |
1127 | (long) read_register (9), | |
1128 | (long) read_register (10), | |
1129 | (long) read_register (11), | |
1130 | (long) read_register (12), | |
1131 | (long) read_register (13), | |
1132 | (long) read_register (14), | |
1133 | (long) read_register (15)); | |
1134 | } | |
c906108c | 1135 | |
cc17453a | 1136 | static void |
fba45db2 | 1137 | sh3_show_regs (void) |
cc17453a | 1138 | { |
d4f3574e SS |
1139 | printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", |
1140 | paddr (read_register (PC_REGNUM)), | |
c62a7c7b | 1141 | (long) read_register (gdbarch_tdep (current_gdbarch)->SR_REGNUM), |
3bbfbb92 | 1142 | (long) read_register (gdbarch_tdep (current_gdbarch)->PR_REGNUM), |
d4f3574e SS |
1143 | (long) read_register (MACH_REGNUM), |
1144 | (long) read_register (MACL_REGNUM)); | |
1145 | ||
1146 | printf_filtered ("GBR=%08lx VBR=%08lx", | |
1147 | (long) read_register (GBR_REGNUM), | |
1148 | (long) read_register (VBR_REGNUM)); | |
cc17453a EZ |
1149 | printf_filtered (" SSR=%08lx SPC=%08lx", |
1150 | (long) read_register (gdbarch_tdep (current_gdbarch)->SSR_REGNUM), | |
1151 | (long) read_register (gdbarch_tdep (current_gdbarch)->SPC_REGNUM)); | |
c906108c | 1152 | |
d4f3574e SS |
1153 | printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
1154 | (long) read_register (0), | |
1155 | (long) read_register (1), | |
1156 | (long) read_register (2), | |
1157 | (long) read_register (3), | |
1158 | (long) read_register (4), | |
1159 | (long) read_register (5), | |
1160 | (long) read_register (6), | |
1161 | (long) read_register (7)); | |
1162 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1163 | (long) read_register (8), | |
1164 | (long) read_register (9), | |
1165 | (long) read_register (10), | |
1166 | (long) read_register (11), | |
1167 | (long) read_register (12), | |
1168 | (long) read_register (13), | |
1169 | (long) read_register (14), | |
1170 | (long) read_register (15)); | |
c906108c SS |
1171 | } |
1172 | ||
53116e27 | 1173 | |
cc17453a | 1174 | static void |
fba45db2 | 1175 | sh3e_show_regs (void) |
cc17453a EZ |
1176 | { |
1177 | printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", | |
1178 | paddr (read_register (PC_REGNUM)), | |
c62a7c7b | 1179 | (long) read_register (gdbarch_tdep (current_gdbarch)->SR_REGNUM), |
3bbfbb92 | 1180 | (long) read_register (gdbarch_tdep (current_gdbarch)->PR_REGNUM), |
cc17453a EZ |
1181 | (long) read_register (MACH_REGNUM), |
1182 | (long) read_register (MACL_REGNUM)); | |
1183 | ||
1184 | printf_filtered ("GBR=%08lx VBR=%08lx", | |
1185 | (long) read_register (GBR_REGNUM), | |
1186 | (long) read_register (VBR_REGNUM)); | |
1187 | printf_filtered (" SSR=%08lx SPC=%08lx", | |
1188 | (long) read_register (gdbarch_tdep (current_gdbarch)->SSR_REGNUM), | |
1189 | (long) read_register (gdbarch_tdep (current_gdbarch)->SPC_REGNUM)); | |
1190 | printf_filtered (" FPUL=%08lx FPSCR=%08lx", | |
1191 | (long) read_register (gdbarch_tdep (current_gdbarch)->FPUL_REGNUM), | |
1192 | (long) read_register (gdbarch_tdep (current_gdbarch)->FPSCR_REGNUM)); | |
c906108c | 1193 | |
cc17453a EZ |
1194 | printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
1195 | (long) read_register (0), | |
1196 | (long) read_register (1), | |
1197 | (long) read_register (2), | |
1198 | (long) read_register (3), | |
1199 | (long) read_register (4), | |
1200 | (long) read_register (5), | |
1201 | (long) read_register (6), | |
1202 | (long) read_register (7)); | |
1203 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1204 | (long) read_register (8), | |
1205 | (long) read_register (9), | |
1206 | (long) read_register (10), | |
1207 | (long) read_register (11), | |
1208 | (long) read_register (12), | |
1209 | (long) read_register (13), | |
1210 | (long) read_register (14), | |
1211 | (long) read_register (15)); | |
1212 | ||
1213 | printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), | |
1214 | (long) read_register (FP0_REGNUM + 0), | |
1215 | (long) read_register (FP0_REGNUM + 1), | |
1216 | (long) read_register (FP0_REGNUM + 2), | |
1217 | (long) read_register (FP0_REGNUM + 3), | |
1218 | (long) read_register (FP0_REGNUM + 4), | |
1219 | (long) read_register (FP0_REGNUM + 5), | |
1220 | (long) read_register (FP0_REGNUM + 6), | |
1221 | (long) read_register (FP0_REGNUM + 7)); | |
1222 | printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), | |
1223 | (long) read_register (FP0_REGNUM + 8), | |
1224 | (long) read_register (FP0_REGNUM + 9), | |
1225 | (long) read_register (FP0_REGNUM + 10), | |
1226 | (long) read_register (FP0_REGNUM + 11), | |
1227 | (long) read_register (FP0_REGNUM + 12), | |
1228 | (long) read_register (FP0_REGNUM + 13), | |
1229 | (long) read_register (FP0_REGNUM + 14), | |
1230 | (long) read_register (FP0_REGNUM + 15)); | |
1231 | } | |
1232 | ||
1233 | static void | |
fba45db2 | 1234 | sh3_dsp_show_regs (void) |
c906108c | 1235 | { |
cc17453a EZ |
1236 | printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", |
1237 | paddr (read_register (PC_REGNUM)), | |
c62a7c7b | 1238 | (long) read_register (gdbarch_tdep (current_gdbarch)->SR_REGNUM), |
3bbfbb92 | 1239 | (long) read_register (gdbarch_tdep (current_gdbarch)->PR_REGNUM), |
cc17453a EZ |
1240 | (long) read_register (MACH_REGNUM), |
1241 | (long) read_register (MACL_REGNUM)); | |
c906108c | 1242 | |
cc17453a EZ |
1243 | printf_filtered ("GBR=%08lx VBR=%08lx", |
1244 | (long) read_register (GBR_REGNUM), | |
1245 | (long) read_register (VBR_REGNUM)); | |
1246 | ||
1247 | printf_filtered (" SSR=%08lx SPC=%08lx", | |
1248 | (long) read_register (gdbarch_tdep (current_gdbarch)->SSR_REGNUM), | |
1249 | (long) read_register (gdbarch_tdep (current_gdbarch)->SPC_REGNUM)); | |
1250 | ||
1251 | printf_filtered (" DSR=%08lx", | |
1252 | (long) read_register (gdbarch_tdep (current_gdbarch)->DSR_REGNUM)); | |
1253 | ||
1254 | printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1255 | (long) read_register (0), | |
1256 | (long) read_register (1), | |
1257 | (long) read_register (2), | |
1258 | (long) read_register (3), | |
1259 | (long) read_register (4), | |
1260 | (long) read_register (5), | |
1261 | (long) read_register (6), | |
1262 | (long) read_register (7)); | |
1263 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1264 | (long) read_register (8), | |
1265 | (long) read_register (9), | |
1266 | (long) read_register (10), | |
1267 | (long) read_register (11), | |
1268 | (long) read_register (12), | |
1269 | (long) read_register (13), | |
1270 | (long) read_register (14), | |
1271 | (long) read_register (15)); | |
1272 | ||
1273 | printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n", | |
1274 | (long) read_register (gdbarch_tdep (current_gdbarch)->A0G_REGNUM) & 0xff, | |
1275 | (long) read_register (gdbarch_tdep (current_gdbarch)->A0_REGNUM), | |
1276 | (long) read_register (gdbarch_tdep (current_gdbarch)->M0_REGNUM), | |
1277 | (long) read_register (gdbarch_tdep (current_gdbarch)->X0_REGNUM), | |
1278 | (long) read_register (gdbarch_tdep (current_gdbarch)->Y0_REGNUM), | |
1279 | (long) read_register (gdbarch_tdep (current_gdbarch)->RS_REGNUM), | |
1280 | (long) read_register (gdbarch_tdep (current_gdbarch)->MOD_REGNUM)); | |
1281 | printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n", | |
1282 | (long) read_register (gdbarch_tdep (current_gdbarch)->A1G_REGNUM) & 0xff, | |
1283 | (long) read_register (gdbarch_tdep (current_gdbarch)->A1_REGNUM), | |
1284 | (long) read_register (gdbarch_tdep (current_gdbarch)->M1_REGNUM), | |
1285 | (long) read_register (gdbarch_tdep (current_gdbarch)->X1_REGNUM), | |
1286 | (long) read_register (gdbarch_tdep (current_gdbarch)->Y1_REGNUM), | |
1287 | (long) read_register (gdbarch_tdep (current_gdbarch)->RE_REGNUM)); | |
c906108c SS |
1288 | } |
1289 | ||
cc17453a | 1290 | static void |
fba45db2 | 1291 | sh4_show_regs (void) |
cc17453a EZ |
1292 | { |
1293 | int pr = read_register (gdbarch_tdep (current_gdbarch)->FPSCR_REGNUM) & 0x80000; | |
1294 | printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", | |
1295 | paddr (read_register (PC_REGNUM)), | |
c62a7c7b | 1296 | (long) read_register (gdbarch_tdep (current_gdbarch)->SR_REGNUM), |
3bbfbb92 | 1297 | (long) read_register (gdbarch_tdep (current_gdbarch)->PR_REGNUM), |
cc17453a EZ |
1298 | (long) read_register (MACH_REGNUM), |
1299 | (long) read_register (MACL_REGNUM)); | |
1300 | ||
1301 | printf_filtered ("GBR=%08lx VBR=%08lx", | |
1302 | (long) read_register (GBR_REGNUM), | |
1303 | (long) read_register (VBR_REGNUM)); | |
1304 | printf_filtered (" SSR=%08lx SPC=%08lx", | |
1305 | (long) read_register (gdbarch_tdep (current_gdbarch)->SSR_REGNUM), | |
1306 | (long) read_register (gdbarch_tdep (current_gdbarch)->SPC_REGNUM)); | |
1307 | printf_filtered (" FPUL=%08lx FPSCR=%08lx", | |
1308 | (long) read_register (gdbarch_tdep (current_gdbarch)->FPUL_REGNUM), | |
1309 | (long) read_register (gdbarch_tdep (current_gdbarch)->FPSCR_REGNUM)); | |
1310 | ||
1311 | printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1312 | (long) read_register (0), | |
1313 | (long) read_register (1), | |
1314 | (long) read_register (2), | |
1315 | (long) read_register (3), | |
1316 | (long) read_register (4), | |
1317 | (long) read_register (5), | |
1318 | (long) read_register (6), | |
1319 | (long) read_register (7)); | |
1320 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1321 | (long) read_register (8), | |
1322 | (long) read_register (9), | |
1323 | (long) read_register (10), | |
1324 | (long) read_register (11), | |
1325 | (long) read_register (12), | |
1326 | (long) read_register (13), | |
1327 | (long) read_register (14), | |
1328 | (long) read_register (15)); | |
1329 | ||
1330 | printf_filtered ((pr | |
1331 | ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n" | |
1332 | : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), | |
1333 | (long) read_register (FP0_REGNUM + 0), | |
1334 | (long) read_register (FP0_REGNUM + 1), | |
1335 | (long) read_register (FP0_REGNUM + 2), | |
1336 | (long) read_register (FP0_REGNUM + 3), | |
1337 | (long) read_register (FP0_REGNUM + 4), | |
1338 | (long) read_register (FP0_REGNUM + 5), | |
1339 | (long) read_register (FP0_REGNUM + 6), | |
1340 | (long) read_register (FP0_REGNUM + 7)); | |
1341 | printf_filtered ((pr | |
1342 | ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n" | |
1343 | : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), | |
1344 | (long) read_register (FP0_REGNUM + 8), | |
1345 | (long) read_register (FP0_REGNUM + 9), | |
1346 | (long) read_register (FP0_REGNUM + 10), | |
1347 | (long) read_register (FP0_REGNUM + 11), | |
1348 | (long) read_register (FP0_REGNUM + 12), | |
1349 | (long) read_register (FP0_REGNUM + 13), | |
1350 | (long) read_register (FP0_REGNUM + 14), | |
1351 | (long) read_register (FP0_REGNUM + 15)); | |
1352 | } | |
1353 | ||
1354 | static void | |
fba45db2 | 1355 | sh_dsp_show_regs (void) |
cc17453a EZ |
1356 | { |
1357 | printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", | |
1358 | paddr (read_register (PC_REGNUM)), | |
c62a7c7b | 1359 | (long) read_register (gdbarch_tdep (current_gdbarch)->SR_REGNUM), |
3bbfbb92 | 1360 | (long) read_register (gdbarch_tdep (current_gdbarch)->PR_REGNUM), |
cc17453a EZ |
1361 | (long) read_register (MACH_REGNUM), |
1362 | (long) read_register (MACL_REGNUM)); | |
1363 | ||
1364 | printf_filtered ("GBR=%08lx VBR=%08lx", | |
1365 | (long) read_register (GBR_REGNUM), | |
1366 | (long) read_register (VBR_REGNUM)); | |
1367 | ||
1368 | printf_filtered (" DSR=%08lx", | |
1369 | (long) read_register (gdbarch_tdep (current_gdbarch)->DSR_REGNUM)); | |
1370 | ||
1371 | printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1372 | (long) read_register (0), | |
1373 | (long) read_register (1), | |
1374 | (long) read_register (2), | |
1375 | (long) read_register (3), | |
1376 | (long) read_register (4), | |
1377 | (long) read_register (5), | |
1378 | (long) read_register (6), | |
1379 | (long) read_register (7)); | |
1380 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1381 | (long) read_register (8), | |
1382 | (long) read_register (9), | |
1383 | (long) read_register (10), | |
1384 | (long) read_register (11), | |
1385 | (long) read_register (12), | |
1386 | (long) read_register (13), | |
1387 | (long) read_register (14), | |
1388 | (long) read_register (15)); | |
1389 | ||
1390 | printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n", | |
1391 | (long) read_register (gdbarch_tdep (current_gdbarch)->A0G_REGNUM) & 0xff, | |
1392 | (long) read_register (gdbarch_tdep (current_gdbarch)->A0_REGNUM), | |
1393 | (long) read_register (gdbarch_tdep (current_gdbarch)->M0_REGNUM), | |
1394 | (long) read_register (gdbarch_tdep (current_gdbarch)->X0_REGNUM), | |
1395 | (long) read_register (gdbarch_tdep (current_gdbarch)->Y0_REGNUM), | |
1396 | (long) read_register (gdbarch_tdep (current_gdbarch)->RS_REGNUM), | |
1397 | (long) read_register (gdbarch_tdep (current_gdbarch)->MOD_REGNUM)); | |
1398 | printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n", | |
1399 | (long) read_register (gdbarch_tdep (current_gdbarch)->A1G_REGNUM) & 0xff, | |
1400 | (long) read_register (gdbarch_tdep (current_gdbarch)->A1_REGNUM), | |
1401 | (long) read_register (gdbarch_tdep (current_gdbarch)->M1_REGNUM), | |
1402 | (long) read_register (gdbarch_tdep (current_gdbarch)->X1_REGNUM), | |
1403 | (long) read_register (gdbarch_tdep (current_gdbarch)->Y1_REGNUM), | |
1404 | (long) read_register (gdbarch_tdep (current_gdbarch)->RE_REGNUM)); | |
1405 | } | |
1406 | ||
53116e27 EZ |
1407 | void sh_show_regs_command (char *args, int from_tty) |
1408 | { | |
1409 | if (sh_show_regs) | |
1410 | (*sh_show_regs)(); | |
1411 | } | |
1412 | ||
cc17453a EZ |
1413 | /* Index within `registers' of the first byte of the space for |
1414 | register N. */ | |
1415 | static int | |
fba45db2 | 1416 | sh_default_register_byte (int reg_nr) |
8db62801 | 1417 | { |
cc17453a EZ |
1418 | return (reg_nr * 4); |
1419 | } | |
1420 | ||
53116e27 | 1421 | static int |
fba45db2 | 1422 | sh_sh4_register_byte (int reg_nr) |
53116e27 EZ |
1423 | { |
1424 | if (reg_nr >= gdbarch_tdep (current_gdbarch)->DR0_REGNUM | |
e6c42fda | 1425 | && reg_nr <= gdbarch_tdep (current_gdbarch)->DR_LAST_REGNUM) |
53116e27 EZ |
1426 | return (dr_reg_base_num (reg_nr) * 4); |
1427 | else if (reg_nr >= gdbarch_tdep (current_gdbarch)->FV0_REGNUM | |
e6c42fda | 1428 | && reg_nr <= gdbarch_tdep (current_gdbarch)->FV_LAST_REGNUM) |
53116e27 EZ |
1429 | return (fv_reg_base_num (reg_nr) * 4); |
1430 | else | |
1431 | return (reg_nr * 4); | |
1432 | } | |
1433 | ||
cc17453a EZ |
1434 | /* Number of bytes of storage in the actual machine representation for |
1435 | register REG_NR. */ | |
1436 | static int | |
fba45db2 | 1437 | sh_default_register_raw_size (int reg_nr) |
cc17453a EZ |
1438 | { |
1439 | return 4; | |
1440 | } | |
1441 | ||
53116e27 | 1442 | static int |
fba45db2 | 1443 | sh_sh4_register_raw_size (int reg_nr) |
53116e27 EZ |
1444 | { |
1445 | if (reg_nr >= gdbarch_tdep (current_gdbarch)->DR0_REGNUM | |
e6c42fda | 1446 | && reg_nr <= gdbarch_tdep (current_gdbarch)->DR_LAST_REGNUM) |
53116e27 EZ |
1447 | return 8; |
1448 | else if (reg_nr >= gdbarch_tdep (current_gdbarch)->FV0_REGNUM | |
e6c42fda | 1449 | && reg_nr <= gdbarch_tdep (current_gdbarch)->FV_LAST_REGNUM) |
53116e27 EZ |
1450 | return 16; |
1451 | else | |
1452 | return 4; | |
1453 | } | |
1454 | ||
cc17453a EZ |
1455 | /* Number of bytes of storage in the program's representation |
1456 | for register N. */ | |
1457 | static int | |
fba45db2 | 1458 | sh_register_virtual_size (int reg_nr) |
cc17453a EZ |
1459 | { |
1460 | return 4; | |
1461 | } | |
1462 | ||
1463 | /* Return the GDB type object for the "standard" data type | |
1464 | of data in register N. */ | |
cc17453a | 1465 | static struct type * |
fba45db2 | 1466 | sh_sh3e_register_virtual_type (int reg_nr) |
cc17453a EZ |
1467 | { |
1468 | if ((reg_nr >= FP0_REGNUM | |
e6c42fda | 1469 | && (reg_nr <= gdbarch_tdep (current_gdbarch)->FP_LAST_REGNUM)) |
cc17453a EZ |
1470 | || (reg_nr == gdbarch_tdep (current_gdbarch)->FPUL_REGNUM)) |
1471 | return builtin_type_float; | |
8db62801 | 1472 | else |
cc17453a EZ |
1473 | return builtin_type_int; |
1474 | } | |
1475 | ||
7f4dbe94 EZ |
1476 | static struct type * |
1477 | sh_sh4_build_float_register_type (int high) | |
1478 | { | |
1479 | struct type *temp; | |
1480 | ||
1481 | temp = create_range_type (NULL, builtin_type_int, 0, high); | |
1482 | return create_array_type (NULL, builtin_type_float, temp); | |
1483 | } | |
1484 | ||
53116e27 | 1485 | static struct type * |
fba45db2 | 1486 | sh_sh4_register_virtual_type (int reg_nr) |
53116e27 EZ |
1487 | { |
1488 | if ((reg_nr >= FP0_REGNUM | |
e6c42fda | 1489 | && (reg_nr <= gdbarch_tdep (current_gdbarch)->FP_LAST_REGNUM)) |
53116e27 EZ |
1490 | || (reg_nr == gdbarch_tdep (current_gdbarch)->FPUL_REGNUM)) |
1491 | return builtin_type_float; | |
1492 | else if (reg_nr >= gdbarch_tdep (current_gdbarch)->DR0_REGNUM | |
e6c42fda | 1493 | && reg_nr <= gdbarch_tdep (current_gdbarch)->DR_LAST_REGNUM) |
53116e27 EZ |
1494 | return builtin_type_double; |
1495 | else if (reg_nr >= gdbarch_tdep (current_gdbarch)->FV0_REGNUM | |
e6c42fda | 1496 | && reg_nr <= gdbarch_tdep (current_gdbarch)->FV_LAST_REGNUM) |
53116e27 EZ |
1497 | return sh_sh4_build_float_register_type (3); |
1498 | else | |
1499 | return builtin_type_int; | |
1500 | } | |
1501 | ||
cc17453a | 1502 | static struct type * |
fba45db2 | 1503 | sh_default_register_virtual_type (int reg_nr) |
cc17453a EZ |
1504 | { |
1505 | return builtin_type_int; | |
1506 | } | |
1507 | ||
fb409745 EZ |
1508 | /* On the sh4, the DRi pseudo registers are problematic if the target |
1509 | is little endian. When the user writes one of those registers, for | |
1510 | instance with 'ser var $dr0=1', we want the double to be stored | |
1511 | like this: | |
1512 | fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f | |
1513 | fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00 | |
1514 | ||
1515 | This corresponds to little endian byte order & big endian word | |
1516 | order. However if we let gdb write the register w/o conversion, it | |
1517 | will write fr0 and fr1 this way: | |
1518 | fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00 | |
1519 | fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f | |
1520 | because it will consider fr0 and fr1 as a single LE stretch of memory. | |
1521 | ||
1522 | To achieve what we want we must force gdb to store things in | |
1523 | floatformat_ieee_double_littlebyte_bigword (which is defined in | |
1524 | include/floatformat.h and libiberty/floatformat.c. | |
1525 | ||
1526 | In case the target is big endian, there is no problem, the | |
1527 | raw bytes will look like: | |
1528 | fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00 | |
1529 | fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00 | |
1530 | ||
1531 | The other pseudo registers (the FVs) also don't pose a problem | |
1532 | because they are stored as 4 individual FP elements. */ | |
1533 | ||
1534 | int | |
1535 | sh_sh4_register_convertible (int nr) | |
1536 | { | |
1537 | if (TARGET_BYTE_ORDER == LITTLE_ENDIAN) | |
1538 | return (gdbarch_tdep (current_gdbarch)->DR0_REGNUM <= nr | |
e6c42fda | 1539 | && nr <= gdbarch_tdep (current_gdbarch)->DR_LAST_REGNUM); |
fb409745 EZ |
1540 | else |
1541 | return 0; | |
1542 | } | |
1543 | ||
1544 | void | |
1545 | sh_sh4_register_convert_to_virtual (int regnum, struct type *type, | |
1546 | char *from, char *to) | |
1547 | { | |
1548 | if (regnum >= gdbarch_tdep (current_gdbarch)->DR0_REGNUM | |
e6c42fda | 1549 | && regnum <= gdbarch_tdep (current_gdbarch)->DR_LAST_REGNUM) |
fb409745 EZ |
1550 | { |
1551 | DOUBLEST val; | |
1552 | floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, from, &val); | |
3bbfbb92 | 1553 | store_floating (to, TYPE_LENGTH (type), val); |
fb409745 EZ |
1554 | } |
1555 | else | |
3bbfbb92 | 1556 | error ("sh_register_convert_to_virtual called with non DR register number"); |
fb409745 EZ |
1557 | } |
1558 | ||
1559 | void | |
1560 | sh_sh4_register_convert_to_raw (struct type *type, int regnum, | |
1561 | char *from, char *to) | |
1562 | { | |
1563 | if (regnum >= gdbarch_tdep (current_gdbarch)->DR0_REGNUM | |
e6c42fda | 1564 | && regnum <= gdbarch_tdep (current_gdbarch)->DR_LAST_REGNUM) |
fb409745 EZ |
1565 | { |
1566 | DOUBLEST val = extract_floating (from, TYPE_LENGTH(type)); | |
1567 | floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword, &val, to); | |
1568 | } | |
1569 | else | |
1570 | error("sh_register_convert_to_raw called with non DR register number"); | |
1571 | } | |
1572 | ||
53116e27 EZ |
1573 | void |
1574 | sh_fetch_pseudo_register (int reg_nr) | |
1575 | { | |
1576 | int base_regnum, portion; | |
1577 | ||
1578 | if (!register_cached (reg_nr)) | |
1579 | { | |
1580 | if (reg_nr >= gdbarch_tdep (current_gdbarch)->DR0_REGNUM | |
e6c42fda | 1581 | && reg_nr <= gdbarch_tdep (current_gdbarch)->DR_LAST_REGNUM) |
53116e27 EZ |
1582 | { |
1583 | base_regnum = dr_reg_base_num (reg_nr); | |
1584 | ||
1585 | /* Read the real regs for which this one is an alias. */ | |
1586 | for (portion = 0; portion < 2; portion++) | |
1587 | if (!register_cached (base_regnum + portion)) | |
1588 | target_fetch_registers (base_regnum + portion); | |
1589 | } | |
1590 | else if (reg_nr >= gdbarch_tdep (current_gdbarch)->FV0_REGNUM | |
e6c42fda | 1591 | && reg_nr <= gdbarch_tdep (current_gdbarch)->FV_LAST_REGNUM) |
53116e27 EZ |
1592 | { |
1593 | base_regnum = fv_reg_base_num (reg_nr); | |
1594 | ||
1595 | /* Read the real regs for which this one is an alias. */ | |
1596 | for (portion = 0; portion < 4; portion++) | |
1597 | if (!register_cached (base_regnum + portion)) | |
1598 | target_fetch_registers (base_regnum + portion); | |
53116e27 EZ |
1599 | } |
1600 | register_valid [reg_nr] = 1; | |
1601 | } | |
1602 | } | |
1603 | ||
1604 | void | |
1605 | sh_store_pseudo_register (int reg_nr) | |
1606 | { | |
1607 | int base_regnum, portion; | |
1608 | ||
1609 | if (reg_nr >= gdbarch_tdep (current_gdbarch)->DR0_REGNUM | |
e6c42fda | 1610 | && reg_nr <= gdbarch_tdep (current_gdbarch)->DR_LAST_REGNUM) |
53116e27 EZ |
1611 | { |
1612 | base_regnum = dr_reg_base_num (reg_nr); | |
1613 | ||
1614 | /* Write the real regs for which this one is an alias. */ | |
1615 | for (portion = 0; portion < 2; portion++) | |
1616 | { | |
1617 | register_valid[base_regnum + portion] = 1; | |
1618 | target_store_registers (base_regnum + portion); | |
1619 | } | |
1620 | } | |
1621 | else if (reg_nr >= gdbarch_tdep (current_gdbarch)->FV0_REGNUM | |
e6c42fda | 1622 | && reg_nr <= gdbarch_tdep (current_gdbarch)->FV_LAST_REGNUM) |
53116e27 EZ |
1623 | { |
1624 | base_regnum = fv_reg_base_num (reg_nr); | |
1625 | ||
1626 | /* Write the real regs for which this one is an alias. */ | |
1627 | for (portion = 0; portion < 4; portion++) | |
1628 | { | |
1629 | register_valid[base_regnum + portion] = 1; | |
1630 | target_store_registers (base_regnum + portion); | |
1631 | } | |
1632 | } | |
1633 | } | |
1634 | ||
3bbfbb92 | 1635 | /* Floating point vector of 4 float registers. */ |
53116e27 EZ |
1636 | static void |
1637 | do_fv_register_info (int fv_regnum) | |
1638 | { | |
1639 | int first_fp_reg_num = fv_reg_base_num (fv_regnum); | |
1640 | printf_filtered ("fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n", | |
1641 | fv_regnum - gdbarch_tdep (current_gdbarch)->FV0_REGNUM, | |
1642 | (int) read_register (first_fp_reg_num), | |
1643 | (int) read_register (first_fp_reg_num + 1), | |
1644 | (int) read_register (first_fp_reg_num + 2), | |
1645 | (int) read_register (first_fp_reg_num + 3)); | |
1646 | } | |
1647 | ||
3bbfbb92 | 1648 | /* Double precision registers. */ |
53116e27 EZ |
1649 | static void |
1650 | do_dr_register_info (int dr_regnum) | |
1651 | { | |
1652 | int first_fp_reg_num = dr_reg_base_num (dr_regnum); | |
1653 | ||
1654 | printf_filtered ("dr%d\t0x%08x%08x\n", | |
1655 | dr_regnum - gdbarch_tdep (current_gdbarch)->DR0_REGNUM, | |
1656 | (int) read_register (first_fp_reg_num), | |
1657 | (int) read_register (first_fp_reg_num + 1)); | |
1658 | } | |
1659 | ||
1660 | static void | |
1661 | sh_do_pseudo_register (int regnum) | |
1662 | { | |
1663 | if (regnum < NUM_REGS || regnum >= NUM_REGS + NUM_PSEUDO_REGS) | |
8e65ff28 AC |
1664 | internal_error (__FILE__, __LINE__, |
1665 | "Invalid pseudo register number %d\n", regnum); | |
a38d2a54 EZ |
1666 | else if (regnum >= gdbarch_tdep (current_gdbarch)->DR0_REGNUM |
1667 | && regnum < gdbarch_tdep (current_gdbarch)->DR_LAST_REGNUM) | |
53116e27 | 1668 | do_dr_register_info (regnum); |
a38d2a54 EZ |
1669 | else if (regnum >= gdbarch_tdep (current_gdbarch)->FV0_REGNUM |
1670 | && regnum <= gdbarch_tdep (current_gdbarch)->FV_LAST_REGNUM) | |
53116e27 EZ |
1671 | do_fv_register_info (regnum); |
1672 | } | |
1673 | ||
53116e27 EZ |
1674 | static void |
1675 | sh_do_fp_register (int regnum) | |
1676 | { /* do values for FP (float) regs */ | |
1677 | char *raw_buffer; | |
1678 | double flt; /* double extracted from raw hex data */ | |
1679 | int inv; | |
1680 | int j; | |
1681 | ||
1682 | /* Allocate space for the float. */ | |
1683 | raw_buffer = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM)); | |
1684 | ||
1685 | /* Get the data in raw format. */ | |
1686 | if (read_relative_register_raw_bytes (regnum, raw_buffer)) | |
1687 | error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum)); | |
1688 | ||
1689 | /* Get the register as a number */ | |
1690 | flt = unpack_double (builtin_type_float, raw_buffer, &inv); | |
1691 | ||
1692 | /* Print the name and some spaces. */ | |
1693 | fputs_filtered (REGISTER_NAME (regnum), gdb_stdout); | |
1694 | print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), gdb_stdout); | |
1695 | ||
1696 | /* Print the value. */ | |
93d56215 AC |
1697 | if (inv) |
1698 | printf_filtered ("<invalid float>"); | |
1699 | else | |
1700 | printf_filtered ("%-10.9g", flt); | |
53116e27 EZ |
1701 | |
1702 | /* Print the fp register as hex. */ | |
1703 | printf_filtered ("\t(raw 0x"); | |
1704 | for (j = 0; j < REGISTER_RAW_SIZE (regnum); j++) | |
1705 | { | |
1706 | register int idx = TARGET_BYTE_ORDER == BIG_ENDIAN ? j | |
1707 | : REGISTER_RAW_SIZE (regnum) - 1 - j; | |
1708 | printf_filtered ("%02x", (unsigned char) raw_buffer[idx]); | |
1709 | } | |
1710 | printf_filtered (")"); | |
1711 | printf_filtered ("\n"); | |
1712 | } | |
1713 | ||
1714 | static void | |
1715 | sh_do_register (int regnum) | |
1716 | { | |
1717 | char raw_buffer[MAX_REGISTER_RAW_SIZE]; | |
1718 | ||
1719 | fputs_filtered (REGISTER_NAME (regnum), gdb_stdout); | |
1720 | print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), gdb_stdout); | |
1721 | ||
1722 | /* Get the data in raw format. */ | |
1723 | if (read_relative_register_raw_bytes (regnum, raw_buffer)) | |
1724 | printf_filtered ("*value not available*\n"); | |
1725 | ||
1726 | val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, 0, | |
1727 | gdb_stdout, 'x', 1, 0, Val_pretty_default); | |
1728 | printf_filtered ("\t"); | |
1729 | val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, 0, | |
1730 | gdb_stdout, 0, 1, 0, Val_pretty_default); | |
1731 | printf_filtered ("\n"); | |
1732 | } | |
1733 | ||
1734 | static void | |
1735 | sh_print_register (int regnum) | |
1736 | { | |
1737 | if (regnum < 0 || regnum >= NUM_REGS + NUM_PSEUDO_REGS) | |
8e65ff28 AC |
1738 | internal_error (__FILE__, __LINE__, |
1739 | "Invalid register number %d\n", regnum); | |
53116e27 | 1740 | |
e30839fe | 1741 | else if (regnum >= 0 && regnum < NUM_REGS) |
53116e27 EZ |
1742 | { |
1743 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) | |
1744 | sh_do_fp_register (regnum); /* FP regs */ | |
1745 | else | |
1746 | sh_do_register (regnum); /* All other regs */ | |
1747 | } | |
1748 | ||
1749 | else if (regnum < NUM_REGS + NUM_PSEUDO_REGS) | |
3bbfbb92 | 1750 | do_pseudo_register (regnum); |
53116e27 EZ |
1751 | } |
1752 | ||
1753 | void | |
1754 | sh_do_registers_info (int regnum, int fpregs) | |
1755 | { | |
1756 | if (regnum != -1) /* do one specified register */ | |
1757 | { | |
1758 | if (*(REGISTER_NAME (regnum)) == '\0') | |
1759 | error ("Not a valid register for the current processor type"); | |
1760 | ||
1761 | sh_print_register (regnum); | |
1762 | } | |
1763 | else | |
1764 | /* do all (or most) registers */ | |
1765 | { | |
1766 | regnum = 0; | |
1767 | while (regnum < NUM_REGS) | |
1768 | { | |
1769 | /* If the register name is empty, it is undefined for this | |
1770 | processor, so don't display anything. */ | |
1771 | if (REGISTER_NAME (regnum) == NULL | |
1772 | || *(REGISTER_NAME (regnum)) == '\0') | |
1773 | { | |
1774 | regnum++; | |
1775 | continue; | |
1776 | } | |
1777 | ||
1778 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) | |
1779 | { | |
1780 | if (fpregs) | |
1781 | { | |
1782 | /* true for "INFO ALL-REGISTERS" command */ | |
1783 | sh_do_fp_register (regnum); /* FP regs */ | |
1784 | regnum ++; | |
1785 | } | |
1786 | else | |
e6c42fda | 1787 | regnum += (gdbarch_tdep (current_gdbarch)->FP_LAST_REGNUM - FP0_REGNUM); /* skip FP regs */ |
53116e27 EZ |
1788 | } |
1789 | else | |
1790 | { | |
1791 | sh_do_register (regnum); /* All other regs */ | |
1792 | regnum++; | |
1793 | } | |
1794 | } | |
1795 | ||
1796 | if (fpregs) | |
1797 | while (regnum < NUM_REGS + NUM_PSEUDO_REGS) | |
1798 | { | |
3bbfbb92 | 1799 | do_pseudo_register (regnum); |
53116e27 EZ |
1800 | regnum++; |
1801 | } | |
1802 | } | |
1803 | } | |
1804 | ||
1a8629c7 MS |
1805 | #ifdef SVR4_SHARED_LIBS |
1806 | ||
1807 | /* Fetch (and possibly build) an appropriate link_map_offsets structure | |
1808 | for native i386 linux targets using the struct offsets defined in | |
1809 | link.h (but without actual reference to that file). | |
1810 | ||
1811 | This makes it possible to access i386-linux shared libraries from | |
1812 | a gdb that was not built on an i386-linux host (for cross debugging). | |
1813 | */ | |
1814 | ||
1815 | struct link_map_offsets * | |
1816 | sh_linux_svr4_fetch_link_map_offsets (void) | |
1817 | { | |
1818 | static struct link_map_offsets lmo; | |
1819 | static struct link_map_offsets *lmp = 0; | |
1820 | ||
1821 | if (lmp == 0) | |
1822 | { | |
1823 | lmp = &lmo; | |
1824 | ||
1825 | lmo.r_debug_size = 8; /* 20 not actual size but all we need */ | |
1826 | ||
1827 | lmo.r_map_offset = 4; | |
1828 | lmo.r_map_size = 4; | |
1829 | ||
1830 | lmo.link_map_size = 20; /* 552 not actual size but all we need */ | |
1831 | ||
1832 | lmo.l_addr_offset = 0; | |
1833 | lmo.l_addr_size = 4; | |
1834 | ||
1835 | lmo.l_name_offset = 4; | |
1836 | lmo.l_name_size = 4; | |
1837 | ||
1838 | lmo.l_next_offset = 12; | |
1839 | lmo.l_next_size = 4; | |
1840 | ||
1841 | lmo.l_prev_offset = 16; | |
1842 | lmo.l_prev_size = 4; | |
1843 | } | |
1844 | ||
1845 | return lmp; | |
1846 | } | |
1847 | #endif /* SVR4_SHARED_LIBS */ | |
1848 | ||
cc17453a EZ |
1849 | static gdbarch_init_ftype sh_gdbarch_init; |
1850 | ||
1851 | static struct gdbarch * | |
fba45db2 | 1852 | sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
cc17453a EZ |
1853 | { |
1854 | static LONGEST sh_call_dummy_words[] = {0}; | |
1855 | struct gdbarch *gdbarch; | |
1856 | struct gdbarch_tdep *tdep; | |
1857 | gdbarch_register_name_ftype *sh_register_name; | |
1858 | gdbarch_store_return_value_ftype *sh_store_return_value; | |
1859 | gdbarch_register_virtual_type_ftype *sh_register_virtual_type; | |
1860 | ||
1861 | /* Find a candidate among the list of pre-declared architectures. */ | |
1862 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
1863 | if (arches != NULL) | |
1864 | return arches->gdbarch; | |
1865 | ||
1866 | /* None found, create a new architecture from the information | |
1867 | provided. */ | |
1868 | tdep = XMALLOC (struct gdbarch_tdep); | |
1869 | gdbarch = gdbarch_alloc (&info, tdep); | |
1870 | ||
1871 | /* Initialize the register numbers that are not common to all the | |
1872 | variants to -1, if necessary thse will be overwritten in the case | |
1873 | statement below. */ | |
1874 | tdep->FPUL_REGNUM = -1; | |
1875 | tdep->FPSCR_REGNUM = -1; | |
3bbfbb92 | 1876 | tdep->PR_REGNUM = 17; |
c62a7c7b | 1877 | tdep->SR_REGNUM = 22; |
cc17453a | 1878 | tdep->DSR_REGNUM = -1; |
e6c42fda | 1879 | tdep->FP_LAST_REGNUM = -1; |
cc17453a EZ |
1880 | tdep->A0G_REGNUM = -1; |
1881 | tdep->A0_REGNUM = -1; | |
1882 | tdep->A1G_REGNUM = -1; | |
1883 | tdep->A1_REGNUM = -1; | |
1884 | tdep->M0_REGNUM = -1; | |
1885 | tdep->M1_REGNUM = -1; | |
1886 | tdep->X0_REGNUM = -1; | |
1887 | tdep->X1_REGNUM = -1; | |
1888 | tdep->Y0_REGNUM = -1; | |
1889 | tdep->Y1_REGNUM = -1; | |
1890 | tdep->MOD_REGNUM = -1; | |
1891 | tdep->RS_REGNUM = -1; | |
1892 | tdep->RE_REGNUM = -1; | |
1893 | tdep->SSR_REGNUM = -1; | |
1894 | tdep->SPC_REGNUM = -1; | |
53116e27 | 1895 | tdep->DR0_REGNUM = -1; |
e6c42fda | 1896 | tdep->DR_LAST_REGNUM = -1; |
53116e27 | 1897 | tdep->FV0_REGNUM = -1; |
e6c42fda | 1898 | tdep->FV_LAST_REGNUM = -1; |
3bbfbb92 EZ |
1899 | tdep->ARG0_REGNUM = 4; |
1900 | tdep->ARGLAST_REGNUM = 7; | |
1901 | tdep->RETURN_REGNUM = 0; | |
1902 | tdep->FLOAT_ARGLAST_REGNUM = -1; | |
a38d2a54 | 1903 | |
cc17453a | 1904 | set_gdbarch_fp0_regnum (gdbarch, -1); |
53116e27 EZ |
1905 | set_gdbarch_num_pseudo_regs (gdbarch, 0); |
1906 | set_gdbarch_max_register_raw_size (gdbarch, 4); | |
1907 | set_gdbarch_max_register_virtual_size (gdbarch, 4); | |
a38d2a54 EZ |
1908 | set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
1909 | set_gdbarch_num_regs (gdbarch, 59); | |
1910 | set_gdbarch_sp_regnum (gdbarch, 15); | |
1911 | set_gdbarch_fp_regnum (gdbarch, 14); | |
1912 | set_gdbarch_pc_regnum (gdbarch, 16); | |
1913 | set_gdbarch_register_size (gdbarch, 4); | |
1914 | set_gdbarch_register_bytes (gdbarch, NUM_REGS * 4); | |
1915 | set_gdbarch_fetch_pseudo_register (gdbarch, sh_fetch_pseudo_register); | |
1916 | set_gdbarch_store_pseudo_register (gdbarch, sh_store_pseudo_register); | |
c5f7d19c | 1917 | set_gdbarch_do_registers_info (gdbarch, sh_do_registers_info); |
eaf90c5d | 1918 | set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc); |
3bbfbb92 EZ |
1919 | set_gdbarch_frame_chain (gdbarch, sh_frame_chain); |
1920 | set_gdbarch_get_saved_register (gdbarch, generic_get_saved_register); | |
1921 | set_gdbarch_init_extra_frame_info (gdbarch, sh_init_extra_frame_info); | |
3116c80a | 1922 | set_gdbarch_extract_return_value (gdbarch, sh_extract_return_value); |
3bbfbb92 EZ |
1923 | set_gdbarch_push_arguments (gdbarch, sh_push_arguments); |
1924 | set_gdbarch_store_struct_return (gdbarch, sh_store_struct_return); | |
1925 | set_gdbarch_use_struct_convention (gdbarch, sh_use_struct_convention); | |
1926 | set_gdbarch_extract_struct_value_address (gdbarch, sh_extract_struct_value_address); | |
1927 | set_gdbarch_pop_frame (gdbarch, sh_pop_frame); | |
e6c42fda | 1928 | print_sh_insn = gdb_print_insn_sh; |
3bbfbb92 EZ |
1929 | skip_prologue_hard_way = sh_skip_prologue_hard_way; |
1930 | do_pseudo_register = sh_do_pseudo_register; | |
cc17453a EZ |
1931 | |
1932 | switch (info.bfd_arch_info->mach) | |
8db62801 | 1933 | { |
cc17453a EZ |
1934 | case bfd_mach_sh: |
1935 | sh_register_name = sh_sh_register_name; | |
1936 | sh_show_regs = sh_generic_show_regs; | |
1937 | sh_store_return_value = sh_default_store_return_value; | |
1938 | sh_register_virtual_type = sh_default_register_virtual_type; | |
1939 | set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs); | |
53116e27 EZ |
1940 | set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size); |
1941 | set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size); | |
1942 | set_gdbarch_register_byte (gdbarch, sh_default_register_byte); | |
cc17453a EZ |
1943 | break; |
1944 | case bfd_mach_sh2: | |
1945 | sh_register_name = sh_sh_register_name; | |
1946 | sh_show_regs = sh_generic_show_regs; | |
1947 | sh_store_return_value = sh_default_store_return_value; | |
1948 | sh_register_virtual_type = sh_default_register_virtual_type; | |
1949 | set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs); | |
53116e27 EZ |
1950 | set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size); |
1951 | set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size); | |
1952 | set_gdbarch_register_byte (gdbarch, sh_default_register_byte); | |
cc17453a EZ |
1953 | break; |
1954 | case bfd_mach_sh_dsp: | |
1955 | sh_register_name = sh_sh_dsp_register_name; | |
1956 | sh_show_regs = sh_dsp_show_regs; | |
1957 | sh_store_return_value = sh_default_store_return_value; | |
1958 | sh_register_virtual_type = sh_default_register_virtual_type; | |
1959 | set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs); | |
53116e27 EZ |
1960 | set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size); |
1961 | set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size); | |
1962 | set_gdbarch_register_byte (gdbarch, sh_default_register_byte); | |
cc17453a EZ |
1963 | tdep->DSR_REGNUM = 24; |
1964 | tdep->A0G_REGNUM = 25; | |
1965 | tdep->A0_REGNUM = 26; | |
1966 | tdep->A1G_REGNUM = 27; | |
1967 | tdep->A1_REGNUM = 28; | |
1968 | tdep->M0_REGNUM = 29; | |
1969 | tdep->M1_REGNUM = 30; | |
1970 | tdep->X0_REGNUM = 31; | |
1971 | tdep->X1_REGNUM = 32; | |
1972 | tdep->Y0_REGNUM = 33; | |
1973 | tdep->Y1_REGNUM = 34; | |
1974 | tdep->MOD_REGNUM = 40; | |
1975 | tdep->RS_REGNUM = 43; | |
1976 | tdep->RE_REGNUM = 44; | |
1977 | break; | |
1978 | case bfd_mach_sh3: | |
1979 | sh_register_name = sh_sh3_register_name; | |
1980 | sh_show_regs = sh3_show_regs; | |
1981 | sh_store_return_value = sh_default_store_return_value; | |
1982 | sh_register_virtual_type = sh_default_register_virtual_type; | |
1983 | set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs); | |
53116e27 EZ |
1984 | set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size); |
1985 | set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size); | |
1986 | set_gdbarch_register_byte (gdbarch, sh_default_register_byte); | |
cc17453a EZ |
1987 | tdep->SSR_REGNUM = 41; |
1988 | tdep->SPC_REGNUM = 42; | |
1989 | break; | |
1990 | case bfd_mach_sh3e: | |
1991 | sh_register_name = sh_sh3e_register_name; | |
1992 | sh_show_regs = sh3e_show_regs; | |
1993 | sh_store_return_value = sh3e_sh4_store_return_value; | |
1994 | sh_register_virtual_type = sh_sh3e_register_virtual_type; | |
1995 | set_gdbarch_frame_init_saved_regs (gdbarch, sh_fp_frame_init_saved_regs); | |
53116e27 EZ |
1996 | set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size); |
1997 | set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size); | |
1998 | set_gdbarch_register_byte (gdbarch, sh_default_register_byte); | |
3bbfbb92 | 1999 | set_gdbarch_extract_return_value (gdbarch, sh3e_sh4_extract_return_value); |
cc17453a EZ |
2000 | set_gdbarch_fp0_regnum (gdbarch, 25); |
2001 | tdep->FPUL_REGNUM = 23; | |
2002 | tdep->FPSCR_REGNUM = 24; | |
e6c42fda | 2003 | tdep->FP_LAST_REGNUM = 40; |
cc17453a EZ |
2004 | tdep->SSR_REGNUM = 41; |
2005 | tdep->SPC_REGNUM = 42; | |
2006 | break; | |
2007 | case bfd_mach_sh3_dsp: | |
2008 | sh_register_name = sh_sh3_dsp_register_name; | |
2009 | sh_show_regs = sh3_dsp_show_regs; | |
2010 | sh_store_return_value = sh_default_store_return_value; | |
2011 | sh_register_virtual_type = sh_default_register_virtual_type; | |
2012 | set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs); | |
53116e27 EZ |
2013 | set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size); |
2014 | set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size); | |
2015 | set_gdbarch_register_byte (gdbarch, sh_default_register_byte); | |
cc17453a EZ |
2016 | tdep->DSR_REGNUM = 24; |
2017 | tdep->A0G_REGNUM = 25; | |
2018 | tdep->A0_REGNUM = 26; | |
2019 | tdep->A1G_REGNUM = 27; | |
2020 | tdep->A1_REGNUM = 28; | |
2021 | tdep->M0_REGNUM = 29; | |
2022 | tdep->M1_REGNUM = 30; | |
2023 | tdep->X0_REGNUM = 31; | |
2024 | tdep->X1_REGNUM = 32; | |
2025 | tdep->Y0_REGNUM = 33; | |
2026 | tdep->Y1_REGNUM = 34; | |
2027 | tdep->MOD_REGNUM = 40; | |
2028 | tdep->RS_REGNUM = 43; | |
2029 | tdep->RE_REGNUM = 44; | |
2030 | tdep->SSR_REGNUM = 41; | |
2031 | tdep->SPC_REGNUM = 42; | |
2032 | break; | |
2033 | case bfd_mach_sh4: | |
53116e27 EZ |
2034 | sh_register_name = sh_sh4_register_name; |
2035 | sh_show_regs = sh4_show_regs; | |
cc17453a | 2036 | sh_store_return_value = sh3e_sh4_store_return_value; |
53116e27 | 2037 | sh_register_virtual_type = sh_sh4_register_virtual_type; |
cc17453a | 2038 | set_gdbarch_frame_init_saved_regs (gdbarch, sh_fp_frame_init_saved_regs); |
3bbfbb92 | 2039 | set_gdbarch_extract_return_value (gdbarch, sh3e_sh4_extract_return_value); |
cc17453a | 2040 | set_gdbarch_fp0_regnum (gdbarch, 25); |
53116e27 EZ |
2041 | set_gdbarch_register_raw_size (gdbarch, sh_sh4_register_raw_size); |
2042 | set_gdbarch_register_virtual_size (gdbarch, sh_sh4_register_raw_size); | |
2043 | set_gdbarch_register_byte (gdbarch, sh_sh4_register_byte); | |
2044 | set_gdbarch_num_pseudo_regs (gdbarch, 12); | |
2045 | set_gdbarch_max_register_raw_size (gdbarch, 4 * 4); | |
2046 | set_gdbarch_max_register_virtual_size (gdbarch, 4 * 4); | |
fb409745 EZ |
2047 | set_gdbarch_register_convert_to_raw (gdbarch, sh_sh4_register_convert_to_raw); |
2048 | set_gdbarch_register_convert_to_virtual (gdbarch, sh_sh4_register_convert_to_virtual); | |
2049 | set_gdbarch_register_convertible (gdbarch, sh_sh4_register_convertible); | |
cc17453a EZ |
2050 | tdep->FPUL_REGNUM = 23; |
2051 | tdep->FPSCR_REGNUM = 24; | |
e6c42fda | 2052 | tdep->FP_LAST_REGNUM = 40; |
cc17453a EZ |
2053 | tdep->SSR_REGNUM = 41; |
2054 | tdep->SPC_REGNUM = 42; | |
53116e27 | 2055 | tdep->DR0_REGNUM = 59; |
e6c42fda | 2056 | tdep->DR_LAST_REGNUM = 66; |
53116e27 | 2057 | tdep->FV0_REGNUM = 67; |
e6c42fda | 2058 | tdep->FV_LAST_REGNUM = 70; |
cc17453a EZ |
2059 | break; |
2060 | default: | |
2061 | sh_register_name = sh_generic_register_name; | |
2062 | sh_show_regs = sh_generic_show_regs; | |
2063 | sh_store_return_value = sh_default_store_return_value; | |
2064 | sh_register_virtual_type = sh_default_register_virtual_type; | |
2065 | set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs); | |
53116e27 EZ |
2066 | set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size); |
2067 | set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size); | |
2068 | set_gdbarch_register_byte (gdbarch, sh_default_register_byte); | |
cc17453a | 2069 | break; |
8db62801 | 2070 | } |
cc17453a EZ |
2071 | |
2072 | set_gdbarch_read_pc (gdbarch, generic_target_read_pc); | |
2073 | set_gdbarch_write_pc (gdbarch, generic_target_write_pc); | |
2074 | set_gdbarch_read_fp (gdbarch, generic_target_read_fp); | |
2075 | set_gdbarch_write_fp (gdbarch, generic_target_write_fp); | |
2076 | set_gdbarch_read_sp (gdbarch, generic_target_read_sp); | |
2077 | set_gdbarch_write_sp (gdbarch, generic_target_write_sp); | |
2078 | ||
cc17453a | 2079 | set_gdbarch_register_name (gdbarch, sh_register_name); |
cc17453a EZ |
2080 | set_gdbarch_register_virtual_type (gdbarch, sh_register_virtual_type); |
2081 | ||
cc17453a EZ |
2082 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); |
2083 | set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
2084 | set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
2085 | set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
2086 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
2087 | set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
a38d2a54 | 2088 | set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT);/*??should be 8?*/ |
cc17453a EZ |
2089 | |
2090 | set_gdbarch_use_generic_dummy_frames (gdbarch, 1); | |
2091 | set_gdbarch_call_dummy_length (gdbarch, 0); | |
2092 | set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT); | |
2093 | set_gdbarch_call_dummy_address (gdbarch, entry_point_address); | |
2094 | set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1); /*???*/ | |
2095 | set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0); | |
2096 | set_gdbarch_call_dummy_start_offset (gdbarch, 0); | |
2097 | set_gdbarch_pc_in_call_dummy (gdbarch, generic_pc_in_call_dummy); | |
2098 | set_gdbarch_call_dummy_words (gdbarch, sh_call_dummy_words); | |
2099 | set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (sh_call_dummy_words)); | |
2100 | set_gdbarch_call_dummy_p (gdbarch, 1); | |
2101 | set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0); | |
cc17453a EZ |
2102 | set_gdbarch_fix_call_dummy (gdbarch, generic_fix_call_dummy); |
2103 | set_gdbarch_coerce_float_to_double (gdbarch, | |
2104 | sh_coerce_float_to_double); | |
2105 | ||
cc17453a EZ |
2106 | set_gdbarch_push_dummy_frame (gdbarch, generic_push_dummy_frame); |
2107 | set_gdbarch_push_return_address (gdbarch, sh_push_return_address); | |
2108 | ||
cc17453a | 2109 | set_gdbarch_store_return_value (gdbarch, sh_store_return_value); |
cc17453a EZ |
2110 | set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue); |
2111 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
2112 | set_gdbarch_decr_pc_after_break (gdbarch, 0); | |
2113 | set_gdbarch_function_start_offset (gdbarch, 0); | |
cc17453a EZ |
2114 | |
2115 | set_gdbarch_frame_args_skip (gdbarch, 0); | |
2116 | set_gdbarch_frameless_function_invocation (gdbarch, frameless_look_for_prologue); | |
cc17453a EZ |
2117 | set_gdbarch_frame_chain_valid (gdbarch, generic_file_frame_chain_valid); |
2118 | set_gdbarch_frame_saved_pc (gdbarch, sh_frame_saved_pc); | |
c347ee3e MS |
2119 | set_gdbarch_frame_args_address (gdbarch, default_frame_address); |
2120 | set_gdbarch_frame_locals_address (gdbarch, default_frame_address); | |
cc17453a EZ |
2121 | set_gdbarch_saved_pc_after_call (gdbarch, sh_saved_pc_after_call); |
2122 | set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown); | |
2123 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); | |
2124 | set_gdbarch_ieee_float (gdbarch, 1); | |
a38d2a54 | 2125 | tm_print_insn = print_sh_insn; |
cc17453a EZ |
2126 | |
2127 | return gdbarch; | |
8db62801 EZ |
2128 | } |
2129 | ||
c906108c | 2130 | void |
fba45db2 | 2131 | _initialize_sh_tdep (void) |
c906108c SS |
2132 | { |
2133 | struct cmd_list_element *c; | |
cc17453a EZ |
2134 | |
2135 | register_gdbarch_init (bfd_arch_sh, sh_gdbarch_init); | |
c906108c | 2136 | |
53116e27 | 2137 | add_com ("regs", class_vars, sh_show_regs_command, "Print all registers"); |
c906108c | 2138 | } |