Commit | Line | Data |
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85a453d5 | 1 | /* Target-dependent code for Renesas Super-H, for GDB. |
0fd88904 | 2 | |
0b302171 | 3 | Copyright (C) 1993-2005, 2007-2012 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 10 | (at your option) any later version. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b | 17 | You should have received a copy of the GNU General Public License |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c | 19 | |
c378eb4e MS |
20 | /* Contributed by Steve Chamberlain |
21 | sac@cygnus.com. */ | |
c906108c SS |
22 | |
23 | #include "defs.h" | |
24 | #include "frame.h" | |
1c0159e0 CV |
25 | #include "frame-base.h" |
26 | #include "frame-unwind.h" | |
27 | #include "dwarf2-frame.h" | |
c906108c | 28 | #include "symtab.h" |
c906108c SS |
29 | #include "gdbtypes.h" |
30 | #include "gdbcmd.h" | |
31 | #include "gdbcore.h" | |
32 | #include "value.h" | |
33 | #include "dis-asm.h" | |
73c1f219 | 34 | #include "inferior.h" |
c906108c | 35 | #include "gdb_string.h" |
1c0159e0 | 36 | #include "gdb_assert.h" |
b4a20239 | 37 | #include "arch-utils.h" |
fb409745 | 38 | #include "floatformat.h" |
4e052eda | 39 | #include "regcache.h" |
d16aafd8 | 40 | #include "doublest.h" |
4be87837 | 41 | #include "osabi.h" |
dda63807 | 42 | #include "reggroups.h" |
c9ac0a72 | 43 | #include "regset.h" |
cb2cf4ce | 44 | #include "objfiles.h" |
c906108c | 45 | |
ab3b8126 | 46 | #include "sh-tdep.h" |
04dcf5fa | 47 | #include "sh64-tdep.h" |
ab3b8126 | 48 | |
d658f924 | 49 | #include "elf-bfd.h" |
1a8629c7 MS |
50 | #include "solib-svr4.h" |
51 | ||
55ff77ac | 52 | /* sh flags */ |
283150cd | 53 | #include "elf/sh.h" |
fa8f86ff | 54 | #include "dwarf2.h" |
c378eb4e | 55 | /* registers numbers shared with the simulator. */ |
1c922164 | 56 | #include "gdb/sim-sh.h" |
283150cd | 57 | |
c055b101 CV |
58 | /* List of "set sh ..." and "show sh ..." commands. */ |
59 | static struct cmd_list_element *setshcmdlist = NULL; | |
60 | static struct cmd_list_element *showshcmdlist = NULL; | |
61 | ||
62 | static const char sh_cc_gcc[] = "gcc"; | |
63 | static const char sh_cc_renesas[] = "renesas"; | |
40478521 | 64 | static const char *const sh_cc_enum[] = { |
c055b101 CV |
65 | sh_cc_gcc, |
66 | sh_cc_renesas, | |
67 | NULL | |
68 | }; | |
69 | ||
70 | static const char *sh_active_calling_convention = sh_cc_gcc; | |
71 | ||
da962468 | 72 | #define SH_NUM_REGS 67 |
88e04cc1 | 73 | |
1c0159e0 | 74 | struct sh_frame_cache |
cc17453a | 75 | { |
1c0159e0 CV |
76 | /* Base address. */ |
77 | CORE_ADDR base; | |
78 | LONGEST sp_offset; | |
79 | CORE_ADDR pc; | |
80 | ||
c378eb4e | 81 | /* Flag showing that a frame has been created in the prologue code. */ |
1c0159e0 CV |
82 | int uses_fp; |
83 | ||
84 | /* Saved registers. */ | |
85 | CORE_ADDR saved_regs[SH_NUM_REGS]; | |
86 | CORE_ADDR saved_sp; | |
63978407 | 87 | }; |
c906108c | 88 | |
c055b101 CV |
89 | static int |
90 | sh_is_renesas_calling_convention (struct type *func_type) | |
91 | { | |
ca193e27 TS |
92 | int val = 0; |
93 | ||
94 | if (func_type) | |
95 | { | |
96 | func_type = check_typedef (func_type); | |
97 | ||
98 | if (TYPE_CODE (func_type) == TYPE_CODE_PTR) | |
99 | func_type = check_typedef (TYPE_TARGET_TYPE (func_type)); | |
100 | ||
101 | if (TYPE_CODE (func_type) == TYPE_CODE_FUNC | |
102 | && TYPE_CALLING_CONVENTION (func_type) == DW_CC_GNU_renesas_sh) | |
103 | val = 1; | |
104 | } | |
105 | ||
106 | if (sh_active_calling_convention == sh_cc_renesas) | |
107 | val = 1; | |
108 | ||
109 | return val; | |
c055b101 CV |
110 | } |
111 | ||
fa88f677 | 112 | static const char * |
d93859e2 | 113 | sh_sh_register_name (struct gdbarch *gdbarch, int reg_nr) |
cc17453a | 114 | { |
617daa0e CV |
115 | static char *register_names[] = { |
116 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
117 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
118 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
119 | "", "", | |
120 | "", "", "", "", "", "", "", "", | |
121 | "", "", "", "", "", "", "", "", | |
122 | "", "", | |
123 | "", "", "", "", "", "", "", "", | |
124 | "", "", "", "", "", "", "", "", | |
da962468 | 125 | "", "", "", "", "", "", "", "", |
cc17453a EZ |
126 | }; |
127 | if (reg_nr < 0) | |
128 | return NULL; | |
129 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
130 | return NULL; | |
131 | return register_names[reg_nr]; | |
132 | } | |
133 | ||
fa88f677 | 134 | static const char * |
d93859e2 | 135 | sh_sh3_register_name (struct gdbarch *gdbarch, int reg_nr) |
cc17453a | 136 | { |
617daa0e CV |
137 | static char *register_names[] = { |
138 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
139 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
140 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
141 | "", "", | |
142 | "", "", "", "", "", "", "", "", | |
143 | "", "", "", "", "", "", "", "", | |
144 | "ssr", "spc", | |
cc17453a EZ |
145 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", |
146 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1" | |
da962468 | 147 | "", "", "", "", "", "", "", "", |
cc17453a EZ |
148 | }; |
149 | if (reg_nr < 0) | |
150 | return NULL; | |
151 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
152 | return NULL; | |
153 | return register_names[reg_nr]; | |
154 | } | |
155 | ||
fa88f677 | 156 | static const char * |
d93859e2 | 157 | sh_sh3e_register_name (struct gdbarch *gdbarch, int reg_nr) |
cc17453a | 158 | { |
617daa0e CV |
159 | static char *register_names[] = { |
160 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
161 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
162 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
cc17453a | 163 | "fpul", "fpscr", |
617daa0e CV |
164 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", |
165 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
166 | "ssr", "spc", | |
cc17453a EZ |
167 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", |
168 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", | |
da962468 | 169 | "", "", "", "", "", "", "", "", |
cc17453a EZ |
170 | }; |
171 | if (reg_nr < 0) | |
172 | return NULL; | |
173 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
174 | return NULL; | |
175 | return register_names[reg_nr]; | |
176 | } | |
177 | ||
2d188dd3 | 178 | static const char * |
d93859e2 | 179 | sh_sh2e_register_name (struct gdbarch *gdbarch, int reg_nr) |
2d188dd3 | 180 | { |
617daa0e CV |
181 | static char *register_names[] = { |
182 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
183 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
184 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
2d188dd3 | 185 | "fpul", "fpscr", |
617daa0e CV |
186 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", |
187 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
188 | "", "", | |
2d188dd3 NC |
189 | "", "", "", "", "", "", "", "", |
190 | "", "", "", "", "", "", "", "", | |
da962468 CV |
191 | "", "", "", "", "", "", "", "", |
192 | }; | |
193 | if (reg_nr < 0) | |
194 | return NULL; | |
195 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
196 | return NULL; | |
197 | return register_names[reg_nr]; | |
198 | } | |
199 | ||
200 | static const char * | |
d93859e2 | 201 | sh_sh2a_register_name (struct gdbarch *gdbarch, int reg_nr) |
da962468 CV |
202 | { |
203 | static char *register_names[] = { | |
204 | /* general registers 0-15 */ | |
205 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
206 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
207 | /* 16 - 22 */ | |
208 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
209 | /* 23, 24 */ | |
210 | "fpul", "fpscr", | |
211 | /* floating point registers 25 - 40 */ | |
212 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", | |
213 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
214 | /* 41, 42 */ | |
215 | "", "", | |
216 | /* 43 - 62. Banked registers. The bank number used is determined by | |
c378eb4e | 217 | the bank register (63). */ |
da962468 CV |
218 | "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b", |
219 | "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", | |
220 | "machb", "ivnb", "prb", "gbrb", "maclb", | |
221 | /* 63: register bank number, not a real register but used to | |
222 | communicate the register bank currently get/set. This register | |
223 | is hidden to the user, who manipulates it using the pseudo | |
224 | register called "bank" (67). See below. */ | |
225 | "", | |
226 | /* 64 - 66 */ | |
227 | "ibcr", "ibnr", "tbr", | |
228 | /* 67: register bank number, the user visible pseudo register. */ | |
229 | "bank", | |
230 | /* double precision (pseudo) 68 - 75 */ | |
231 | "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", | |
232 | }; | |
233 | if (reg_nr < 0) | |
234 | return NULL; | |
235 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
236 | return NULL; | |
237 | return register_names[reg_nr]; | |
238 | } | |
239 | ||
240 | static const char * | |
d93859e2 | 241 | sh_sh2a_nofpu_register_name (struct gdbarch *gdbarch, int reg_nr) |
da962468 CV |
242 | { |
243 | static char *register_names[] = { | |
244 | /* general registers 0-15 */ | |
245 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
246 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
247 | /* 16 - 22 */ | |
248 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
249 | /* 23, 24 */ | |
250 | "", "", | |
251 | /* floating point registers 25 - 40 */ | |
252 | "", "", "", "", "", "", "", "", | |
253 | "", "", "", "", "", "", "", "", | |
254 | /* 41, 42 */ | |
255 | "", "", | |
256 | /* 43 - 62. Banked registers. The bank number used is determined by | |
c378eb4e | 257 | the bank register (63). */ |
da962468 CV |
258 | "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b", |
259 | "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", | |
260 | "machb", "ivnb", "prb", "gbrb", "maclb", | |
261 | /* 63: register bank number, not a real register but used to | |
262 | communicate the register bank currently get/set. This register | |
263 | is hidden to the user, who manipulates it using the pseudo | |
264 | register called "bank" (67). See below. */ | |
265 | "", | |
266 | /* 64 - 66 */ | |
267 | "ibcr", "ibnr", "tbr", | |
268 | /* 67: register bank number, the user visible pseudo register. */ | |
269 | "bank", | |
270 | /* double precision (pseudo) 68 - 75 */ | |
271 | "", "", "", "", "", "", "", "", | |
2d188dd3 NC |
272 | }; |
273 | if (reg_nr < 0) | |
274 | return NULL; | |
275 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
276 | return NULL; | |
277 | return register_names[reg_nr]; | |
278 | } | |
279 | ||
fa88f677 | 280 | static const char * |
d93859e2 | 281 | sh_sh_dsp_register_name (struct gdbarch *gdbarch, int reg_nr) |
cc17453a | 282 | { |
617daa0e CV |
283 | static char *register_names[] = { |
284 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
285 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
286 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
287 | "", "dsr", | |
288 | "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1", | |
289 | "y0", "y1", "", "", "", "", "", "mod", | |
290 | "", "", | |
291 | "rs", "re", "", "", "", "", "", "", | |
292 | "", "", "", "", "", "", "", "", | |
da962468 | 293 | "", "", "", "", "", "", "", "", |
cc17453a EZ |
294 | }; |
295 | if (reg_nr < 0) | |
296 | return NULL; | |
297 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
298 | return NULL; | |
299 | return register_names[reg_nr]; | |
300 | } | |
301 | ||
fa88f677 | 302 | static const char * |
d93859e2 | 303 | sh_sh3_dsp_register_name (struct gdbarch *gdbarch, int reg_nr) |
cc17453a | 304 | { |
617daa0e CV |
305 | static char *register_names[] = { |
306 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
307 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
308 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
309 | "", "dsr", | |
310 | "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1", | |
311 | "y0", "y1", "", "", "", "", "", "mod", | |
312 | "ssr", "spc", | |
313 | "rs", "re", "", "", "", "", "", "", | |
026a72f8 CV |
314 | "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b", |
315 | "", "", "", "", "", "", "", "", | |
da962468 | 316 | "", "", "", "", "", "", "", "", |
cc17453a EZ |
317 | }; |
318 | if (reg_nr < 0) | |
319 | return NULL; | |
320 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
321 | return NULL; | |
322 | return register_names[reg_nr]; | |
323 | } | |
324 | ||
fa88f677 | 325 | static const char * |
d93859e2 | 326 | sh_sh4_register_name (struct gdbarch *gdbarch, int reg_nr) |
53116e27 | 327 | { |
617daa0e | 328 | static char *register_names[] = { |
a38d2a54 | 329 | /* general registers 0-15 */ |
617daa0e CV |
330 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
331 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
a38d2a54 | 332 | /* 16 - 22 */ |
617daa0e | 333 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", |
a38d2a54 | 334 | /* 23, 24 */ |
53116e27 | 335 | "fpul", "fpscr", |
a38d2a54 | 336 | /* floating point registers 25 - 40 */ |
617daa0e CV |
337 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", |
338 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
a38d2a54 | 339 | /* 41, 42 */ |
617daa0e | 340 | "ssr", "spc", |
a38d2a54 | 341 | /* bank 0 43 - 50 */ |
53116e27 | 342 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", |
a38d2a54 | 343 | /* bank 1 51 - 58 */ |
53116e27 | 344 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", |
da962468 | 345 | "", "", "", "", "", "", "", "", |
c378eb4e | 346 | /* pseudo bank register. */ |
da962468 | 347 | "", |
a38d2a54 | 348 | /* double precision (pseudo) 59 - 66 */ |
617daa0e | 349 | "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", |
a38d2a54 | 350 | /* vectors (pseudo) 67 - 70 */ |
617daa0e | 351 | "fv0", "fv4", "fv8", "fv12", |
a38d2a54 EZ |
352 | /* FIXME: missing XF 71 - 86 */ |
353 | /* FIXME: missing XD 87 - 94 */ | |
53116e27 EZ |
354 | }; |
355 | if (reg_nr < 0) | |
356 | return NULL; | |
357 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
358 | return NULL; | |
359 | return register_names[reg_nr]; | |
360 | } | |
361 | ||
474e5826 | 362 | static const char * |
d93859e2 | 363 | sh_sh4_nofpu_register_name (struct gdbarch *gdbarch, int reg_nr) |
474e5826 CV |
364 | { |
365 | static char *register_names[] = { | |
366 | /* general registers 0-15 */ | |
367 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
368 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
369 | /* 16 - 22 */ | |
370 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
371 | /* 23, 24 */ | |
372 | "", "", | |
373 | /* floating point registers 25 - 40 -- not for nofpu target */ | |
374 | "", "", "", "", "", "", "", "", | |
375 | "", "", "", "", "", "", "", "", | |
376 | /* 41, 42 */ | |
377 | "ssr", "spc", | |
378 | /* bank 0 43 - 50 */ | |
379 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", | |
380 | /* bank 1 51 - 58 */ | |
381 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", | |
da962468 | 382 | "", "", "", "", "", "", "", "", |
c378eb4e | 383 | /* pseudo bank register. */ |
da962468 | 384 | "", |
474e5826 CV |
385 | /* double precision (pseudo) 59 - 66 -- not for nofpu target */ |
386 | "", "", "", "", "", "", "", "", | |
387 | /* vectors (pseudo) 67 - 70 -- not for nofpu target */ | |
388 | "", "", "", "", | |
389 | }; | |
390 | if (reg_nr < 0) | |
391 | return NULL; | |
392 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
393 | return NULL; | |
394 | return register_names[reg_nr]; | |
395 | } | |
396 | ||
397 | static const char * | |
d93859e2 | 398 | sh_sh4al_dsp_register_name (struct gdbarch *gdbarch, int reg_nr) |
474e5826 CV |
399 | { |
400 | static char *register_names[] = { | |
401 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
402 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
403 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
404 | "", "dsr", | |
405 | "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1", | |
406 | "y0", "y1", "", "", "", "", "", "mod", | |
407 | "ssr", "spc", | |
408 | "rs", "re", "", "", "", "", "", "", | |
026a72f8 CV |
409 | "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b", |
410 | "", "", "", "", "", "", "", "", | |
da962468 | 411 | "", "", "", "", "", "", "", "", |
474e5826 CV |
412 | }; |
413 | if (reg_nr < 0) | |
414 | return NULL; | |
415 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
416 | return NULL; | |
417 | return register_names[reg_nr]; | |
418 | } | |
419 | ||
3117ed25 | 420 | static const unsigned char * |
67d57894 | 421 | sh_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr) |
cc17453a | 422 | { |
c378eb4e | 423 | /* 0xc3c3 is trapa #c3, and it works in big and little endian modes. */ |
617daa0e CV |
424 | static unsigned char breakpoint[] = { 0xc3, 0xc3 }; |
425 | ||
bac718a6 UW |
426 | /* For remote stub targets, trapa #20 is used. */ |
427 | if (strcmp (target_shortname, "remote") == 0) | |
428 | { | |
429 | static unsigned char big_remote_breakpoint[] = { 0xc3, 0x20 }; | |
430 | static unsigned char little_remote_breakpoint[] = { 0x20, 0xc3 }; | |
431 | ||
67d57894 | 432 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
bac718a6 UW |
433 | { |
434 | *lenptr = sizeof (big_remote_breakpoint); | |
435 | return big_remote_breakpoint; | |
436 | } | |
437 | else | |
438 | { | |
439 | *lenptr = sizeof (little_remote_breakpoint); | |
440 | return little_remote_breakpoint; | |
441 | } | |
442 | } | |
443 | ||
cc17453a EZ |
444 | *lenptr = sizeof (breakpoint); |
445 | return breakpoint; | |
446 | } | |
c906108c SS |
447 | |
448 | /* Prologue looks like | |
1c0159e0 CV |
449 | mov.l r14,@-r15 |
450 | sts.l pr,@-r15 | |
451 | mov.l <regs>,@-r15 | |
452 | sub <room_for_loca_vars>,r15 | |
453 | mov r15,r14 | |
8db62801 | 454 | |
c378eb4e | 455 | Actually it can be more complicated than this but that's it, basically. */ |
c906108c | 456 | |
1c0159e0 CV |
457 | #define GET_SOURCE_REG(x) (((x) >> 4) & 0xf) |
458 | #define GET_TARGET_REG(x) (((x) >> 8) & 0xf) | |
459 | ||
5f883edd FF |
460 | /* JSR @Rm 0100mmmm00001011 */ |
461 | #define IS_JSR(x) (((x) & 0xf0ff) == 0x400b) | |
462 | ||
8db62801 EZ |
463 | /* STS.L PR,@-r15 0100111100100010 |
464 | r15-4-->r15, PR-->(r15) */ | |
c906108c | 465 | #define IS_STS(x) ((x) == 0x4f22) |
8db62801 | 466 | |
03131d99 CV |
467 | /* STS.L MACL,@-r15 0100111100010010 |
468 | r15-4-->r15, MACL-->(r15) */ | |
469 | #define IS_MACL_STS(x) ((x) == 0x4f12) | |
470 | ||
8db62801 EZ |
471 | /* MOV.L Rm,@-r15 00101111mmmm0110 |
472 | r15-4-->r15, Rm-->(R15) */ | |
c906108c | 473 | #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06) |
8db62801 | 474 | |
8db62801 EZ |
475 | /* MOV r15,r14 0110111011110011 |
476 | r15-->r14 */ | |
c906108c | 477 | #define IS_MOV_SP_FP(x) ((x) == 0x6ef3) |
8db62801 EZ |
478 | |
479 | /* ADD #imm,r15 01111111iiiiiiii | |
480 | r15+imm-->r15 */ | |
1c0159e0 | 481 | #define IS_ADD_IMM_SP(x) (((x) & 0xff00) == 0x7f00) |
8db62801 | 482 | |
c906108c SS |
483 | #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00) |
484 | #define IS_SHLL_R3(x) ((x) == 0x4300) | |
8db62801 EZ |
485 | |
486 | /* ADD r3,r15 0011111100111100 | |
487 | r15+r3-->r15 */ | |
c906108c | 488 | #define IS_ADD_R3SP(x) ((x) == 0x3f3c) |
8db62801 EZ |
489 | |
490 | /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011 | |
8db62801 | 491 | FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011 |
8db62801 | 492 | FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */ |
f2ea0907 | 493 | /* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to |
c378eb4e | 494 | make this entirely clear. */ |
1c0159e0 CV |
495 | /* #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) */ |
496 | #define IS_FPUSH(x) (((x) & 0xff0f) == 0xff0b) | |
497 | ||
498 | /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 4 <= m <= 7 */ | |
499 | #define IS_MOV_ARG_TO_REG(x) \ | |
500 | (((x) & 0xf00f) == 0x6003 && \ | |
501 | ((x) & 0x00f0) >= 0x0040 && \ | |
502 | ((x) & 0x00f0) <= 0x0070) | |
503 | /* MOV.L Rm,@Rn 0010nnnnmmmm0010 n = 14, 4 <= m <= 7 */ | |
504 | #define IS_MOV_ARG_TO_IND_R14(x) \ | |
505 | (((x) & 0xff0f) == 0x2e02 && \ | |
506 | ((x) & 0x00f0) >= 0x0040 && \ | |
507 | ((x) & 0x00f0) <= 0x0070) | |
508 | /* MOV.L Rm,@(disp*4,Rn) 00011110mmmmdddd n = 14, 4 <= m <= 7 */ | |
509 | #define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \ | |
510 | (((x) & 0xff00) == 0x1e00 && \ | |
511 | ((x) & 0x00f0) >= 0x0040 && \ | |
512 | ((x) & 0x00f0) <= 0x0070) | |
513 | ||
514 | /* MOV.W @(disp*2,PC),Rn 1001nnnndddddddd */ | |
515 | #define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000) | |
516 | /* MOV.L @(disp*4,PC),Rn 1101nnnndddddddd */ | |
517 | #define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000) | |
03131d99 CV |
518 | /* MOVI20 #imm20,Rn 0000nnnniiii0000 */ |
519 | #define IS_MOVI20(x) (((x) & 0xf00f) == 0x0000) | |
1c0159e0 CV |
520 | /* SUB Rn,R15 00111111nnnn1000 */ |
521 | #define IS_SUB_REG_FROM_SP(x) (((x) & 0xff0f) == 0x3f08) | |
8db62801 | 522 | |
1c0159e0 | 523 | #define FPSCR_SZ (1 << 20) |
cc17453a | 524 | |
c378eb4e | 525 | /* The following instructions are used for epilogue testing. */ |
1c0159e0 CV |
526 | #define IS_RESTORE_FP(x) ((x) == 0x6ef6) |
527 | #define IS_RTS(x) ((x) == 0x000b) | |
528 | #define IS_LDS(x) ((x) == 0x4f26) | |
03131d99 | 529 | #define IS_MACL_LDS(x) ((x) == 0x4f16) |
1c0159e0 CV |
530 | #define IS_MOV_FP_SP(x) ((x) == 0x6fe3) |
531 | #define IS_ADD_REG_TO_FP(x) (((x) & 0xff0f) == 0x3e0c) | |
532 | #define IS_ADD_IMM_FP(x) (((x) & 0xff00) == 0x7e00) | |
cc17453a | 533 | |
cc17453a | 534 | static CORE_ADDR |
e17a4113 | 535 | sh_analyze_prologue (struct gdbarch *gdbarch, |
5cbb9812 | 536 | CORE_ADDR pc, CORE_ADDR limit_pc, |
d2ca4222 | 537 | struct sh_frame_cache *cache, ULONGEST fpscr) |
617daa0e | 538 | { |
e17a4113 | 539 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1c0159e0 | 540 | ULONGEST inst; |
1c0159e0 CV |
541 | int offset; |
542 | int sav_offset = 0; | |
c906108c | 543 | int r3_val = 0; |
1c0159e0 | 544 | int reg, sav_reg = -1; |
cc17453a | 545 | |
1c0159e0 | 546 | cache->uses_fp = 0; |
5cbb9812 | 547 | for (; pc < limit_pc; pc += 2) |
cc17453a | 548 | { |
e17a4113 | 549 | inst = read_memory_unsigned_integer (pc, 2, byte_order); |
c378eb4e | 550 | /* See where the registers will be saved to. */ |
f2ea0907 | 551 | if (IS_PUSH (inst)) |
cc17453a | 552 | { |
1c0159e0 CV |
553 | cache->saved_regs[GET_SOURCE_REG (inst)] = cache->sp_offset; |
554 | cache->sp_offset += 4; | |
cc17453a | 555 | } |
f2ea0907 | 556 | else if (IS_STS (inst)) |
cc17453a | 557 | { |
1c0159e0 CV |
558 | cache->saved_regs[PR_REGNUM] = cache->sp_offset; |
559 | cache->sp_offset += 4; | |
cc17453a | 560 | } |
03131d99 CV |
561 | else if (IS_MACL_STS (inst)) |
562 | { | |
563 | cache->saved_regs[MACL_REGNUM] = cache->sp_offset; | |
564 | cache->sp_offset += 4; | |
565 | } | |
f2ea0907 | 566 | else if (IS_MOV_R3 (inst)) |
cc17453a | 567 | { |
f2ea0907 | 568 | r3_val = ((inst & 0xff) ^ 0x80) - 0x80; |
cc17453a | 569 | } |
f2ea0907 | 570 | else if (IS_SHLL_R3 (inst)) |
cc17453a EZ |
571 | { |
572 | r3_val <<= 1; | |
573 | } | |
f2ea0907 | 574 | else if (IS_ADD_R3SP (inst)) |
cc17453a | 575 | { |
1c0159e0 | 576 | cache->sp_offset += -r3_val; |
cc17453a | 577 | } |
f2ea0907 | 578 | else if (IS_ADD_IMM_SP (inst)) |
cc17453a | 579 | { |
1c0159e0 CV |
580 | offset = ((inst & 0xff) ^ 0x80) - 0x80; |
581 | cache->sp_offset -= offset; | |
c906108c | 582 | } |
1c0159e0 | 583 | else if (IS_MOVW_PCREL_TO_REG (inst)) |
617daa0e | 584 | { |
1c0159e0 CV |
585 | if (sav_reg < 0) |
586 | { | |
587 | reg = GET_TARGET_REG (inst); | |
588 | if (reg < 14) | |
589 | { | |
590 | sav_reg = reg; | |
a2b4a96c | 591 | offset = (inst & 0xff) << 1; |
1c0159e0 | 592 | sav_offset = |
e17a4113 | 593 | read_memory_integer ((pc + 4) + offset, 2, byte_order); |
1c0159e0 CV |
594 | } |
595 | } | |
c906108c | 596 | } |
1c0159e0 | 597 | else if (IS_MOVL_PCREL_TO_REG (inst)) |
617daa0e | 598 | { |
1c0159e0 CV |
599 | if (sav_reg < 0) |
600 | { | |
a2b4a96c | 601 | reg = GET_TARGET_REG (inst); |
1c0159e0 CV |
602 | if (reg < 14) |
603 | { | |
604 | sav_reg = reg; | |
a2b4a96c | 605 | offset = (inst & 0xff) << 2; |
1c0159e0 | 606 | sav_offset = |
e17a4113 UW |
607 | read_memory_integer (((pc & 0xfffffffc) + 4) + offset, |
608 | 4, byte_order); | |
1c0159e0 CV |
609 | } |
610 | } | |
c906108c | 611 | } |
5cbb9812 TS |
612 | else if (IS_MOVI20 (inst) |
613 | && (pc + 2 < limit_pc)) | |
03131d99 CV |
614 | { |
615 | if (sav_reg < 0) | |
616 | { | |
617 | reg = GET_TARGET_REG (inst); | |
618 | if (reg < 14) | |
619 | { | |
620 | sav_reg = reg; | |
621 | sav_offset = GET_SOURCE_REG (inst) << 16; | |
c378eb4e | 622 | /* MOVI20 is a 32 bit instruction! */ |
03131d99 | 623 | pc += 2; |
e17a4113 UW |
624 | sav_offset |
625 | |= read_memory_unsigned_integer (pc, 2, byte_order); | |
03131d99 CV |
626 | /* Now sav_offset contains an unsigned 20 bit value. |
627 | It must still get sign extended. */ | |
628 | if (sav_offset & 0x00080000) | |
629 | sav_offset |= 0xfff00000; | |
630 | } | |
631 | } | |
632 | } | |
1c0159e0 | 633 | else if (IS_SUB_REG_FROM_SP (inst)) |
617daa0e | 634 | { |
1c0159e0 CV |
635 | reg = GET_SOURCE_REG (inst); |
636 | if (sav_reg > 0 && reg == sav_reg) | |
637 | { | |
638 | sav_reg = -1; | |
639 | } | |
640 | cache->sp_offset += sav_offset; | |
c906108c | 641 | } |
f2ea0907 | 642 | else if (IS_FPUSH (inst)) |
c906108c | 643 | { |
d2ca4222 | 644 | if (fpscr & FPSCR_SZ) |
c906108c | 645 | { |
1c0159e0 | 646 | cache->sp_offset += 8; |
c906108c SS |
647 | } |
648 | else | |
649 | { | |
1c0159e0 | 650 | cache->sp_offset += 4; |
c906108c SS |
651 | } |
652 | } | |
f2ea0907 | 653 | else if (IS_MOV_SP_FP (inst)) |
617daa0e | 654 | { |
5cbb9812 TS |
655 | pc += 2; |
656 | /* Don't go any further than six more instructions. */ | |
657 | limit_pc = min (limit_pc, pc + (2 * 6)); | |
658 | ||
960ccd7d | 659 | cache->uses_fp = 1; |
1c0159e0 CV |
660 | /* At this point, only allow argument register moves to other |
661 | registers or argument register moves to @(X,fp) which are | |
662 | moving the register arguments onto the stack area allocated | |
663 | by a former add somenumber to SP call. Don't allow moving | |
c378eb4e | 664 | to an fp indirect address above fp + cache->sp_offset. */ |
5cbb9812 | 665 | for (; pc < limit_pc; pc += 2) |
1c0159e0 | 666 | { |
e17a4113 | 667 | inst = read_memory_integer (pc, 2, byte_order); |
1c0159e0 | 668 | if (IS_MOV_ARG_TO_IND_R14 (inst)) |
617daa0e | 669 | { |
1c0159e0 CV |
670 | reg = GET_SOURCE_REG (inst); |
671 | if (cache->sp_offset > 0) | |
617daa0e | 672 | cache->saved_regs[reg] = cache->sp_offset; |
1c0159e0 CV |
673 | } |
674 | else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst)) | |
617daa0e | 675 | { |
1c0159e0 CV |
676 | reg = GET_SOURCE_REG (inst); |
677 | offset = (inst & 0xf) * 4; | |
678 | if (cache->sp_offset > offset) | |
679 | cache->saved_regs[reg] = cache->sp_offset - offset; | |
680 | } | |
681 | else if (IS_MOV_ARG_TO_REG (inst)) | |
617daa0e | 682 | continue; |
1c0159e0 CV |
683 | else |
684 | break; | |
685 | } | |
686 | break; | |
687 | } | |
5f883edd FF |
688 | else if (IS_JSR (inst)) |
689 | { | |
690 | /* We have found a jsr that has been scheduled into the prologue. | |
691 | If we continue the scan and return a pc someplace after this, | |
692 | then setting a breakpoint on this function will cause it to | |
693 | appear to be called after the function it is calling via the | |
694 | jsr, which will be very confusing. Most likely the next | |
695 | instruction is going to be IS_MOV_SP_FP in the delay slot. If | |
c378eb4e | 696 | so, note that before returning the current pc. */ |
5cbb9812 TS |
697 | if (pc + 2 < limit_pc) |
698 | { | |
699 | inst = read_memory_integer (pc + 2, 2, byte_order); | |
700 | if (IS_MOV_SP_FP (inst)) | |
701 | cache->uses_fp = 1; | |
702 | } | |
5f883edd FF |
703 | break; |
704 | } | |
c378eb4e MS |
705 | #if 0 /* This used to just stop when it found an instruction |
706 | that was not considered part of the prologue. Now, | |
707 | we just keep going looking for likely | |
708 | instructions. */ | |
c906108c SS |
709 | else |
710 | break; | |
2bfa91ee | 711 | #endif |
c906108c SS |
712 | } |
713 | ||
1c0159e0 CV |
714 | return pc; |
715 | } | |
c906108c | 716 | |
c378eb4e | 717 | /* Skip any prologue before the guts of a function. */ |
1c0159e0 | 718 | static CORE_ADDR |
8a8bc27f | 719 | sh_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
c906108c | 720 | { |
5cbb9812 | 721 | CORE_ADDR post_prologue_pc, func_addr, func_end_addr, limit_pc; |
1c0159e0 CV |
722 | struct sh_frame_cache cache; |
723 | ||
724 | /* See if we can determine the end of the prologue via the symbol table. | |
725 | If so, then return either PC, or the PC after the prologue, whichever | |
726 | is greater. */ | |
5cbb9812 | 727 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end_addr)) |
8a8bc27f TS |
728 | { |
729 | post_prologue_pc = skip_prologue_using_sal (gdbarch, func_addr); | |
730 | if (post_prologue_pc != 0) | |
731 | return max (pc, post_prologue_pc); | |
732 | } | |
cc17453a | 733 | |
8a8bc27f TS |
734 | /* Can't determine prologue from the symbol table, need to examine |
735 | instructions. */ | |
c906108c | 736 | |
5cbb9812 TS |
737 | /* Find an upper limit on the function prologue using the debug |
738 | information. If the debug information could not be used to provide | |
739 | that bound, then use an arbitrary large number as the upper bound. */ | |
740 | limit_pc = skip_prologue_using_sal (gdbarch, pc); | |
741 | if (limit_pc == 0) | |
742 | /* Don't go any further than 28 instructions. */ | |
743 | limit_pc = pc + (2 * 28); | |
744 | ||
745 | /* Do not allow limit_pc to be past the function end, if we know | |
746 | where that end is... */ | |
747 | if (func_end_addr != 0) | |
748 | limit_pc = min (limit_pc, func_end_addr); | |
749 | ||
1c0159e0 | 750 | cache.sp_offset = -4; |
5cbb9812 | 751 | post_prologue_pc = sh_analyze_prologue (gdbarch, pc, limit_pc, &cache, 0); |
8a8bc27f TS |
752 | if (cache.uses_fp) |
753 | pc = post_prologue_pc; | |
c906108c | 754 | |
1c0159e0 CV |
755 | return pc; |
756 | } | |
757 | ||
2e952408 | 758 | /* The ABI says: |
9a5cef92 EZ |
759 | |
760 | Aggregate types not bigger than 8 bytes that have the same size and | |
761 | alignment as one of the integer scalar types are returned in the | |
762 | same registers as the integer type they match. | |
763 | ||
764 | For example, a 2-byte aligned structure with size 2 bytes has the | |
765 | same size and alignment as a short int, and will be returned in R0. | |
766 | A 4-byte aligned structure with size 8 bytes has the same size and | |
767 | alignment as a long long int, and will be returned in R0 and R1. | |
768 | ||
769 | When an aggregate type is returned in R0 and R1, R0 contains the | |
770 | first four bytes of the aggregate, and R1 contains the | |
c378eb4e | 771 | remainder. If the size of the aggregate type is not a multiple of 4 |
9a5cef92 | 772 | bytes, the aggregate is tail-padded up to a multiple of 4 |
c378eb4e | 773 | bytes. The value of the padding is undefined. For little-endian |
9a5cef92 EZ |
774 | targets the padding will appear at the most significant end of the |
775 | last element, for big-endian targets the padding appears at the | |
776 | least significant end of the last element. | |
777 | ||
c378eb4e | 778 | All other aggregate types are returned by address. The caller |
9a5cef92 | 779 | function passes the address of an area large enough to hold the |
c378eb4e | 780 | aggregate value in R2. The called function stores the result in |
7fe958be | 781 | this location. |
9a5cef92 EZ |
782 | |
783 | To reiterate, structs smaller than 8 bytes could also be returned | |
784 | in memory, if they don't pass the "same size and alignment as an | |
785 | integer type" rule. | |
786 | ||
787 | For example, in | |
788 | ||
789 | struct s { char c[3]; } wibble; | |
790 | struct s foo(void) { return wibble; } | |
791 | ||
792 | the return value from foo() will be in memory, not | |
793 | in R0, because there is no 3-byte integer type. | |
794 | ||
7fe958be EZ |
795 | Similarly, in |
796 | ||
797 | struct s { char c[2]; } wibble; | |
798 | struct s foo(void) { return wibble; } | |
799 | ||
800 | because a struct containing two chars has alignment 1, that matches | |
801 | type char, but size 2, that matches type short. There's no integer | |
802 | type that has alignment 1 and size 2, so the struct is returned in | |
c378eb4e | 803 | memory. */ |
9a5cef92 | 804 | |
1c0159e0 | 805 | static int |
c055b101 | 806 | sh_use_struct_convention (int renesas_abi, struct type *type) |
1c0159e0 CV |
807 | { |
808 | int len = TYPE_LENGTH (type); | |
809 | int nelem = TYPE_NFIELDS (type); | |
3f997a97 | 810 | |
c055b101 CV |
811 | /* The Renesas ABI returns aggregate types always on stack. */ |
812 | if (renesas_abi && (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
813 | || TYPE_CODE (type) == TYPE_CODE_UNION)) | |
814 | return 1; | |
815 | ||
3f997a97 CV |
816 | /* Non-power of 2 length types and types bigger than 8 bytes (which don't |
817 | fit in two registers anyway) use struct convention. */ | |
818 | if (len != 1 && len != 2 && len != 4 && len != 8) | |
819 | return 1; | |
820 | ||
821 | /* Scalar types and aggregate types with exactly one field are aligned | |
822 | by definition. They are returned in registers. */ | |
823 | if (nelem <= 1) | |
824 | return 0; | |
825 | ||
826 | /* If the first field in the aggregate has the same length as the entire | |
827 | aggregate type, the type is returned in registers. */ | |
828 | if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == len) | |
829 | return 0; | |
830 | ||
831 | /* If the size of the aggregate is 8 bytes and the first field is | |
832 | of size 4 bytes its alignment is equal to long long's alignment, | |
833 | so it's returned in registers. */ | |
834 | if (len == 8 && TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == 4) | |
835 | return 0; | |
836 | ||
837 | /* Otherwise use struct convention. */ | |
838 | return 1; | |
283150cd EZ |
839 | } |
840 | ||
c055b101 CV |
841 | static int |
842 | sh_use_struct_convention_nofpu (int renesas_abi, struct type *type) | |
843 | { | |
844 | /* The Renesas ABI returns long longs/doubles etc. always on stack. */ | |
845 | if (renesas_abi && TYPE_NFIELDS (type) == 0 && TYPE_LENGTH (type) >= 8) | |
846 | return 1; | |
847 | return sh_use_struct_convention (renesas_abi, type); | |
848 | } | |
849 | ||
19f59343 MS |
850 | static CORE_ADDR |
851 | sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp) | |
852 | { | |
853 | return sp & ~3; | |
854 | } | |
855 | ||
55ff77ac | 856 | /* Function: push_dummy_call (formerly push_arguments) |
c906108c SS |
857 | Setup the function arguments for calling a function in the inferior. |
858 | ||
85a453d5 | 859 | On the Renesas SH architecture, there are four registers (R4 to R7) |
c906108c SS |
860 | which are dedicated for passing function arguments. Up to the first |
861 | four arguments (depending on size) may go into these registers. | |
862 | The rest go on the stack. | |
863 | ||
6df2bf50 MS |
864 | MVS: Except on SH variants that have floating point registers. |
865 | In that case, float and double arguments are passed in the same | |
866 | manner, but using FP registers instead of GP registers. | |
867 | ||
c906108c SS |
868 | Arguments that are smaller than 4 bytes will still take up a whole |
869 | register or a whole 32-bit word on the stack, and will be | |
870 | right-justified in the register or the stack word. This includes | |
871 | chars, shorts, and small aggregate types. | |
872 | ||
873 | Arguments that are larger than 4 bytes may be split between two or | |
874 | more registers. If there are not enough registers free, an argument | |
875 | may be passed partly in a register (or registers), and partly on the | |
c378eb4e | 876 | stack. This includes doubles, long longs, and larger aggregates. |
c906108c SS |
877 | As far as I know, there is no upper limit to the size of aggregates |
878 | that will be passed in this way; in other words, the convention of | |
879 | passing a pointer to a large aggregate instead of a copy is not used. | |
880 | ||
6df2bf50 | 881 | MVS: The above appears to be true for the SH variants that do not |
55ff77ac | 882 | have an FPU, however those that have an FPU appear to copy the |
6df2bf50 MS |
883 | aggregate argument onto the stack (and not place it in registers) |
884 | if it is larger than 16 bytes (four GP registers). | |
885 | ||
c906108c SS |
886 | An exceptional case exists for struct arguments (and possibly other |
887 | aggregates such as arrays) if the size is larger than 4 bytes but | |
888 | not a multiple of 4 bytes. In this case the argument is never split | |
889 | between the registers and the stack, but instead is copied in its | |
890 | entirety onto the stack, AND also copied into as many registers as | |
891 | there is room for. In other words, space in registers permitting, | |
892 | two copies of the same argument are passed in. As far as I can tell, | |
893 | only the one on the stack is used, although that may be a function | |
894 | of the level of compiler optimization. I suspect this is a compiler | |
895 | bug. Arguments of these odd sizes are left-justified within the | |
896 | word (as opposed to arguments smaller than 4 bytes, which are | |
897 | right-justified). | |
c5aa993b | 898 | |
c906108c SS |
899 | If the function is to return an aggregate type such as a struct, it |
900 | is either returned in the normal return value register R0 (if its | |
901 | size is no greater than one byte), or else the caller must allocate | |
902 | space into which the callee will copy the return value (if the size | |
903 | is greater than one byte). In this case, a pointer to the return | |
904 | value location is passed into the callee in register R2, which does | |
905 | not displace any of the other arguments passed in via registers R4 | |
c378eb4e | 906 | to R7. */ |
c906108c | 907 | |
c378eb4e | 908 | /* Helper function to justify value in register according to endianess. */ |
e5e33cd9 | 909 | static char * |
d93859e2 | 910 | sh_justify_value_in_reg (struct gdbarch *gdbarch, struct value *val, int len) |
e5e33cd9 CV |
911 | { |
912 | static char valbuf[4]; | |
913 | ||
617daa0e | 914 | memset (valbuf, 0, sizeof (valbuf)); |
e5e33cd9 CV |
915 | if (len < 4) |
916 | { | |
c378eb4e | 917 | /* value gets right-justified in the register or stack word. */ |
d93859e2 | 918 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
0fd88904 | 919 | memcpy (valbuf + (4 - len), (char *) value_contents (val), len); |
e5e33cd9 | 920 | else |
0fd88904 | 921 | memcpy (valbuf, (char *) value_contents (val), len); |
e5e33cd9 CV |
922 | return valbuf; |
923 | } | |
0fd88904 | 924 | return (char *) value_contents (val); |
617daa0e | 925 | } |
e5e33cd9 | 926 | |
c378eb4e | 927 | /* Helper function to eval number of bytes to allocate on stack. */ |
e5e33cd9 CV |
928 | static CORE_ADDR |
929 | sh_stack_allocsize (int nargs, struct value **args) | |
930 | { | |
931 | int stack_alloc = 0; | |
932 | while (nargs-- > 0) | |
4991999e | 933 | stack_alloc += ((TYPE_LENGTH (value_type (args[nargs])) + 3) & ~3); |
e5e33cd9 CV |
934 | return stack_alloc; |
935 | } | |
936 | ||
937 | /* Helper functions for getting the float arguments right. Registers usage | |
938 | depends on the ABI and the endianess. The comments should enlighten how | |
c378eb4e | 939 | it's intended to work. */ |
e5e33cd9 | 940 | |
c378eb4e | 941 | /* This array stores which of the float arg registers are already in use. */ |
e5e33cd9 CV |
942 | static int flt_argreg_array[FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM + 1]; |
943 | ||
c378eb4e | 944 | /* This function just resets the above array to "no reg used so far". */ |
e5e33cd9 CV |
945 | static void |
946 | sh_init_flt_argreg (void) | |
947 | { | |
948 | memset (flt_argreg_array, 0, sizeof flt_argreg_array); | |
949 | } | |
950 | ||
951 | /* This function returns the next register to use for float arg passing. | |
952 | It returns either a valid value between FLOAT_ARG0_REGNUM and | |
953 | FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns | |
954 | FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available. | |
955 | ||
956 | Note that register number 0 in flt_argreg_array corresponds with the | |
957 | real float register fr4. In contrast to FLOAT_ARG0_REGNUM (value is | |
958 | 29) the parity of the register number is preserved, which is important | |
c378eb4e | 959 | for the double register passing test (see the "argreg & 1" test below). */ |
e5e33cd9 | 960 | static int |
c055b101 | 961 | sh_next_flt_argreg (struct gdbarch *gdbarch, int len, struct type *func_type) |
e5e33cd9 CV |
962 | { |
963 | int argreg; | |
964 | ||
c378eb4e | 965 | /* First search for the next free register. */ |
617daa0e CV |
966 | for (argreg = 0; argreg <= FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM; |
967 | ++argreg) | |
e5e33cd9 CV |
968 | if (!flt_argreg_array[argreg]) |
969 | break; | |
970 | ||
c378eb4e | 971 | /* No register left? */ |
e5e33cd9 CV |
972 | if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM) |
973 | return FLOAT_ARGLAST_REGNUM + 1; | |
974 | ||
975 | if (len == 8) | |
976 | { | |
c378eb4e | 977 | /* Doubles are always starting in a even register number. */ |
e5e33cd9 | 978 | if (argreg & 1) |
617daa0e | 979 | { |
c055b101 CV |
980 | /* In gcc ABI, the skipped register is lost for further argument |
981 | passing now. Not so in Renesas ABI. */ | |
982 | if (!sh_is_renesas_calling_convention (func_type)) | |
983 | flt_argreg_array[argreg] = 1; | |
e5e33cd9 CV |
984 | |
985 | ++argreg; | |
986 | ||
c378eb4e | 987 | /* No register left? */ |
e5e33cd9 CV |
988 | if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM) |
989 | return FLOAT_ARGLAST_REGNUM + 1; | |
990 | } | |
c378eb4e | 991 | /* Also mark the next register as used. */ |
e5e33cd9 CV |
992 | flt_argreg_array[argreg + 1] = 1; |
993 | } | |
c055b101 CV |
994 | else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE |
995 | && !sh_is_renesas_calling_convention (func_type)) | |
e5e33cd9 | 996 | { |
c378eb4e | 997 | /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */ |
e5e33cd9 CV |
998 | if (!flt_argreg_array[argreg + 1]) |
999 | ++argreg; | |
1000 | } | |
1001 | flt_argreg_array[argreg] = 1; | |
1002 | return FLOAT_ARG0_REGNUM + argreg; | |
1003 | } | |
1004 | ||
afce3d2a CV |
1005 | /* Helper function which figures out, if a type is treated like a float type. |
1006 | ||
2e952408 | 1007 | The FPU ABIs have a special way how to treat types as float types. |
afce3d2a CV |
1008 | Structures with exactly one member, which is of type float or double, are |
1009 | treated exactly as the base types float or double: | |
1010 | ||
1011 | struct sf { | |
1012 | float f; | |
1013 | }; | |
1014 | ||
1015 | struct sd { | |
1016 | double d; | |
1017 | }; | |
1018 | ||
1019 | are handled the same way as just | |
1020 | ||
1021 | float f; | |
1022 | ||
1023 | double d; | |
1024 | ||
1025 | As a result, arguments of these struct types are pushed into floating point | |
1026 | registers exactly as floats or doubles, using the same decision algorithm. | |
1027 | ||
1028 | The same is valid if these types are used as function return types. The | |
1029 | above structs are returned in fr0 resp. fr0,fr1 instead of in r0, r0,r1 | |
1030 | or even using struct convention as it is for other structs. */ | |
1031 | ||
1032 | static int | |
1033 | sh_treat_as_flt_p (struct type *type) | |
1034 | { | |
1035 | int len = TYPE_LENGTH (type); | |
1036 | ||
1037 | /* Ordinary float types are obviously treated as float. */ | |
1038 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
1039 | return 1; | |
1040 | /* Otherwise non-struct types are not treated as float. */ | |
1041 | if (TYPE_CODE (type) != TYPE_CODE_STRUCT) | |
1042 | return 0; | |
1043 | /* Otherwise structs with more than one memeber are not treated as float. */ | |
1044 | if (TYPE_NFIELDS (type) != 1) | |
1045 | return 0; | |
1046 | /* Otherwise if the type of that member is float, the whole type is | |
1047 | treated as float. */ | |
1048 | if (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) == TYPE_CODE_FLT) | |
1049 | return 1; | |
1050 | /* Otherwise it's not treated as float. */ | |
1051 | return 0; | |
1052 | } | |
1053 | ||
cc17453a | 1054 | static CORE_ADDR |
617daa0e | 1055 | sh_push_dummy_call_fpu (struct gdbarch *gdbarch, |
7d9b040b | 1056 | struct value *function, |
617daa0e | 1057 | struct regcache *regcache, |
6df2bf50 | 1058 | CORE_ADDR bp_addr, int nargs, |
617daa0e | 1059 | struct value **args, |
6df2bf50 MS |
1060 | CORE_ADDR sp, int struct_return, |
1061 | CORE_ADDR struct_addr) | |
1062 | { | |
e17a4113 | 1063 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
e5e33cd9 CV |
1064 | int stack_offset = 0; |
1065 | int argreg = ARG0_REGNUM; | |
8748518b | 1066 | int flt_argreg = 0; |
6df2bf50 | 1067 | int argnum; |
c055b101 | 1068 | struct type *func_type = value_type (function); |
6df2bf50 MS |
1069 | struct type *type; |
1070 | CORE_ADDR regval; | |
1071 | char *val; | |
8748518b | 1072 | int len, reg_size = 0; |
afce3d2a CV |
1073 | int pass_on_stack = 0; |
1074 | int treat_as_flt; | |
c055b101 CV |
1075 | int last_reg_arg = INT_MAX; |
1076 | ||
1077 | /* The Renesas ABI expects all varargs arguments, plus the last | |
1078 | non-vararg argument to be on the stack, no matter how many | |
1079 | registers have been used so far. */ | |
1080 | if (sh_is_renesas_calling_convention (func_type) | |
876cecd0 | 1081 | && TYPE_VARARGS (func_type)) |
c055b101 | 1082 | last_reg_arg = TYPE_NFIELDS (func_type) - 2; |
6df2bf50 | 1083 | |
c378eb4e | 1084 | /* First force sp to a 4-byte alignment. */ |
6df2bf50 MS |
1085 | sp = sh_frame_align (gdbarch, sp); |
1086 | ||
c378eb4e | 1087 | /* Make room on stack for args. */ |
e5e33cd9 CV |
1088 | sp -= sh_stack_allocsize (nargs, args); |
1089 | ||
c378eb4e | 1090 | /* Initialize float argument mechanism. */ |
e5e33cd9 | 1091 | sh_init_flt_argreg (); |
6df2bf50 MS |
1092 | |
1093 | /* Now load as many as possible of the first arguments into | |
1094 | registers, and push the rest onto the stack. There are 16 bytes | |
1095 | in four registers available. Loop thru args from first to last. */ | |
e5e33cd9 | 1096 | for (argnum = 0; argnum < nargs; argnum++) |
6df2bf50 | 1097 | { |
4991999e | 1098 | type = value_type (args[argnum]); |
6df2bf50 | 1099 | len = TYPE_LENGTH (type); |
d93859e2 | 1100 | val = sh_justify_value_in_reg (gdbarch, args[argnum], len); |
e5e33cd9 CV |
1101 | |
1102 | /* Some decisions have to be made how various types are handled. | |
c378eb4e | 1103 | This also differs in different ABIs. */ |
e5e33cd9 | 1104 | pass_on_stack = 0; |
e5e33cd9 | 1105 | |
c378eb4e | 1106 | /* Find out the next register to use for a floating point value. */ |
afce3d2a CV |
1107 | treat_as_flt = sh_treat_as_flt_p (type); |
1108 | if (treat_as_flt) | |
c055b101 CV |
1109 | flt_argreg = sh_next_flt_argreg (gdbarch, len, func_type); |
1110 | /* In Renesas ABI, long longs and aggregate types are always passed | |
1111 | on stack. */ | |
1112 | else if (sh_is_renesas_calling_convention (func_type) | |
1113 | && ((TYPE_CODE (type) == TYPE_CODE_INT && len == 8) | |
1114 | || TYPE_CODE (type) == TYPE_CODE_STRUCT | |
1115 | || TYPE_CODE (type) == TYPE_CODE_UNION)) | |
1116 | pass_on_stack = 1; | |
afce3d2a CV |
1117 | /* In contrast to non-FPU CPUs, arguments are never split between |
1118 | registers and stack. If an argument doesn't fit in the remaining | |
1119 | registers it's always pushed entirely on the stack. */ | |
1120 | else if (len > ((ARGLAST_REGNUM - argreg + 1) * 4)) | |
1121 | pass_on_stack = 1; | |
48db5a3c | 1122 | |
6df2bf50 MS |
1123 | while (len > 0) |
1124 | { | |
afce3d2a CV |
1125 | if ((treat_as_flt && flt_argreg > FLOAT_ARGLAST_REGNUM) |
1126 | || (!treat_as_flt && (argreg > ARGLAST_REGNUM | |
c055b101 CV |
1127 | || pass_on_stack)) |
1128 | || argnum > last_reg_arg) | |
617daa0e | 1129 | { |
c378eb4e | 1130 | /* The data goes entirely on the stack, 4-byte aligned. */ |
e5e33cd9 CV |
1131 | reg_size = (len + 3) & ~3; |
1132 | write_memory (sp + stack_offset, val, reg_size); | |
1133 | stack_offset += reg_size; | |
6df2bf50 | 1134 | } |
afce3d2a | 1135 | else if (treat_as_flt && flt_argreg <= FLOAT_ARGLAST_REGNUM) |
6df2bf50 | 1136 | { |
e5e33cd9 CV |
1137 | /* Argument goes in a float argument register. */ |
1138 | reg_size = register_size (gdbarch, flt_argreg); | |
e17a4113 | 1139 | regval = extract_unsigned_integer (val, reg_size, byte_order); |
2e952408 CV |
1140 | /* In little endian mode, float types taking two registers |
1141 | (doubles on sh4, long doubles on sh2e, sh3e and sh4) must | |
1142 | be stored swapped in the argument registers. The below | |
1143 | code first writes the first 32 bits in the next but one | |
1144 | register, increments the val and len values accordingly | |
1145 | and then proceeds as normal by writing the second 32 bits | |
c378eb4e | 1146 | into the next register. */ |
b47193f7 | 1147 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE |
2e952408 CV |
1148 | && TYPE_LENGTH (type) == 2 * reg_size) |
1149 | { | |
1150 | regcache_cooked_write_unsigned (regcache, flt_argreg + 1, | |
1151 | regval); | |
1152 | val += reg_size; | |
1153 | len -= reg_size; | |
c378eb4e MS |
1154 | regval = extract_unsigned_integer (val, reg_size, |
1155 | byte_order); | |
2e952408 | 1156 | } |
6df2bf50 MS |
1157 | regcache_cooked_write_unsigned (regcache, flt_argreg++, regval); |
1158 | } | |
afce3d2a | 1159 | else if (!treat_as_flt && argreg <= ARGLAST_REGNUM) |
e5e33cd9 | 1160 | { |
6df2bf50 | 1161 | /* there's room in a register */ |
e5e33cd9 | 1162 | reg_size = register_size (gdbarch, argreg); |
e17a4113 | 1163 | regval = extract_unsigned_integer (val, reg_size, byte_order); |
6df2bf50 MS |
1164 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
1165 | } | |
c378eb4e MS |
1166 | /* Store the value one register at a time or in one step on |
1167 | stack. */ | |
e5e33cd9 CV |
1168 | len -= reg_size; |
1169 | val += reg_size; | |
6df2bf50 MS |
1170 | } |
1171 | } | |
1172 | ||
c055b101 CV |
1173 | if (struct_return) |
1174 | { | |
1175 | if (sh_is_renesas_calling_convention (func_type)) | |
1176 | /* If the function uses the Renesas ABI, subtract another 4 bytes from | |
1177 | the stack and store the struct return address there. */ | |
e17a4113 | 1178 | write_memory_unsigned_integer (sp -= 4, 4, byte_order, struct_addr); |
c055b101 CV |
1179 | else |
1180 | /* Using the gcc ABI, the "struct return pointer" pseudo-argument has | |
1181 | its own dedicated register. */ | |
1182 | regcache_cooked_write_unsigned (regcache, | |
1183 | STRUCT_RETURN_REGNUM, struct_addr); | |
1184 | } | |
1185 | ||
c378eb4e | 1186 | /* Store return address. */ |
55ff77ac | 1187 | regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr); |
6df2bf50 MS |
1188 | |
1189 | /* Update stack pointer. */ | |
3e8c568d | 1190 | regcache_cooked_write_unsigned (regcache, |
b47193f7 | 1191 | gdbarch_sp_regnum (gdbarch), sp); |
6df2bf50 MS |
1192 | |
1193 | return sp; | |
1194 | } | |
1195 | ||
1196 | static CORE_ADDR | |
617daa0e | 1197 | sh_push_dummy_call_nofpu (struct gdbarch *gdbarch, |
7d9b040b | 1198 | struct value *function, |
617daa0e CV |
1199 | struct regcache *regcache, |
1200 | CORE_ADDR bp_addr, | |
1201 | int nargs, struct value **args, | |
1202 | CORE_ADDR sp, int struct_return, | |
6df2bf50 | 1203 | CORE_ADDR struct_addr) |
c906108c | 1204 | { |
e17a4113 | 1205 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
e5e33cd9 CV |
1206 | int stack_offset = 0; |
1207 | int argreg = ARG0_REGNUM; | |
c906108c | 1208 | int argnum; |
c055b101 | 1209 | struct type *func_type = value_type (function); |
c906108c SS |
1210 | struct type *type; |
1211 | CORE_ADDR regval; | |
1212 | char *val; | |
c055b101 CV |
1213 | int len, reg_size = 0; |
1214 | int pass_on_stack = 0; | |
1215 | int last_reg_arg = INT_MAX; | |
1216 | ||
1217 | /* The Renesas ABI expects all varargs arguments, plus the last | |
1218 | non-vararg argument to be on the stack, no matter how many | |
1219 | registers have been used so far. */ | |
1220 | if (sh_is_renesas_calling_convention (func_type) | |
876cecd0 | 1221 | && TYPE_VARARGS (func_type)) |
c055b101 | 1222 | last_reg_arg = TYPE_NFIELDS (func_type) - 2; |
c906108c | 1223 | |
c378eb4e | 1224 | /* First force sp to a 4-byte alignment. */ |
19f59343 | 1225 | sp = sh_frame_align (gdbarch, sp); |
c906108c | 1226 | |
c378eb4e | 1227 | /* Make room on stack for args. */ |
e5e33cd9 | 1228 | sp -= sh_stack_allocsize (nargs, args); |
c906108c | 1229 | |
c906108c SS |
1230 | /* Now load as many as possible of the first arguments into |
1231 | registers, and push the rest onto the stack. There are 16 bytes | |
1232 | in four registers available. Loop thru args from first to last. */ | |
e5e33cd9 | 1233 | for (argnum = 0; argnum < nargs; argnum++) |
617daa0e | 1234 | { |
4991999e | 1235 | type = value_type (args[argnum]); |
c5aa993b | 1236 | len = TYPE_LENGTH (type); |
d93859e2 | 1237 | val = sh_justify_value_in_reg (gdbarch, args[argnum], len); |
c906108c | 1238 | |
c055b101 | 1239 | /* Some decisions have to be made how various types are handled. |
c378eb4e | 1240 | This also differs in different ABIs. */ |
c055b101 CV |
1241 | pass_on_stack = 0; |
1242 | /* Renesas ABI pushes doubles and long longs entirely on stack. | |
1243 | Same goes for aggregate types. */ | |
1244 | if (sh_is_renesas_calling_convention (func_type) | |
1245 | && ((TYPE_CODE (type) == TYPE_CODE_INT && len >= 8) | |
1246 | || (TYPE_CODE (type) == TYPE_CODE_FLT && len >= 8) | |
1247 | || TYPE_CODE (type) == TYPE_CODE_STRUCT | |
1248 | || TYPE_CODE (type) == TYPE_CODE_UNION)) | |
1249 | pass_on_stack = 1; | |
c906108c SS |
1250 | while (len > 0) |
1251 | { | |
c055b101 CV |
1252 | if (argreg > ARGLAST_REGNUM || pass_on_stack |
1253 | || argnum > last_reg_arg) | |
617daa0e | 1254 | { |
e5e33cd9 | 1255 | /* The remainder of the data goes entirely on the stack, |
c378eb4e | 1256 | 4-byte aligned. */ |
e5e33cd9 CV |
1257 | reg_size = (len + 3) & ~3; |
1258 | write_memory (sp + stack_offset, val, reg_size); | |
617daa0e | 1259 | stack_offset += reg_size; |
c906108c | 1260 | } |
e5e33cd9 | 1261 | else if (argreg <= ARGLAST_REGNUM) |
617daa0e | 1262 | { |
c378eb4e | 1263 | /* There's room in a register. */ |
e5e33cd9 | 1264 | reg_size = register_size (gdbarch, argreg); |
e17a4113 | 1265 | regval = extract_unsigned_integer (val, reg_size, byte_order); |
48db5a3c | 1266 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
c906108c | 1267 | } |
e5e33cd9 CV |
1268 | /* Store the value reg_size bytes at a time. This means that things |
1269 | larger than reg_size bytes may go partly in registers and partly | |
c906108c | 1270 | on the stack. */ |
e5e33cd9 CV |
1271 | len -= reg_size; |
1272 | val += reg_size; | |
c906108c SS |
1273 | } |
1274 | } | |
48db5a3c | 1275 | |
c055b101 CV |
1276 | if (struct_return) |
1277 | { | |
1278 | if (sh_is_renesas_calling_convention (func_type)) | |
1279 | /* If the function uses the Renesas ABI, subtract another 4 bytes from | |
1280 | the stack and store the struct return address there. */ | |
e17a4113 | 1281 | write_memory_unsigned_integer (sp -= 4, 4, byte_order, struct_addr); |
c055b101 CV |
1282 | else |
1283 | /* Using the gcc ABI, the "struct return pointer" pseudo-argument has | |
1284 | its own dedicated register. */ | |
1285 | regcache_cooked_write_unsigned (regcache, | |
1286 | STRUCT_RETURN_REGNUM, struct_addr); | |
1287 | } | |
1288 | ||
c378eb4e | 1289 | /* Store return address. */ |
55ff77ac | 1290 | regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr); |
48db5a3c CV |
1291 | |
1292 | /* Update stack pointer. */ | |
3e8c568d | 1293 | regcache_cooked_write_unsigned (regcache, |
b47193f7 | 1294 | gdbarch_sp_regnum (gdbarch), sp); |
48db5a3c | 1295 | |
c906108c SS |
1296 | return sp; |
1297 | } | |
1298 | ||
cc17453a EZ |
1299 | /* Find a function's return value in the appropriate registers (in |
1300 | regbuf), and copy it into valbuf. Extract from an array REGBUF | |
1301 | containing the (raw) register state a function return value of type | |
1302 | TYPE, and copy that, in virtual format, into VALBUF. */ | |
1303 | static void | |
3ffc5b9b CV |
1304 | sh_extract_return_value_nofpu (struct type *type, struct regcache *regcache, |
1305 | void *valbuf) | |
c906108c | 1306 | { |
e17a4113 UW |
1307 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
1308 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
cc17453a | 1309 | int len = TYPE_LENGTH (type); |
3116c80a EZ |
1310 | int return_register = R0_REGNUM; |
1311 | int offset; | |
617daa0e | 1312 | |
cc17453a | 1313 | if (len <= 4) |
3116c80a | 1314 | { |
48db5a3c CV |
1315 | ULONGEST c; |
1316 | ||
1317 | regcache_cooked_read_unsigned (regcache, R0_REGNUM, &c); | |
e17a4113 | 1318 | store_unsigned_integer (valbuf, len, byte_order, c); |
3116c80a | 1319 | } |
48db5a3c | 1320 | else if (len == 8) |
3116c80a | 1321 | { |
48db5a3c CV |
1322 | int i, regnum = R0_REGNUM; |
1323 | for (i = 0; i < len; i += 4) | |
617daa0e | 1324 | regcache_raw_read (regcache, regnum++, (char *) valbuf + i); |
3116c80a EZ |
1325 | } |
1326 | else | |
8a3fe4f8 | 1327 | error (_("bad size for return value")); |
3116c80a EZ |
1328 | } |
1329 | ||
1330 | static void | |
3ffc5b9b CV |
1331 | sh_extract_return_value_fpu (struct type *type, struct regcache *regcache, |
1332 | void *valbuf) | |
3116c80a | 1333 | { |
d93859e2 | 1334 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
afce3d2a | 1335 | if (sh_treat_as_flt_p (type)) |
3116c80a | 1336 | { |
48db5a3c | 1337 | int len = TYPE_LENGTH (type); |
d93859e2 | 1338 | int i, regnum = gdbarch_fp0_regnum (gdbarch); |
48db5a3c | 1339 | for (i = 0; i < len; i += 4) |
d93859e2 | 1340 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) |
c378eb4e MS |
1341 | regcache_raw_read (regcache, regnum++, |
1342 | (char *) valbuf + len - 4 - i); | |
2e952408 CV |
1343 | else |
1344 | regcache_raw_read (regcache, regnum++, (char *) valbuf + i); | |
3116c80a | 1345 | } |
cc17453a | 1346 | else |
3ffc5b9b | 1347 | sh_extract_return_value_nofpu (type, regcache, valbuf); |
cc17453a | 1348 | } |
c906108c | 1349 | |
cc17453a EZ |
1350 | /* Write into appropriate registers a function return value |
1351 | of type TYPE, given in virtual format. | |
1352 | If the architecture is sh4 or sh3e, store a function's return value | |
1353 | in the R0 general register or in the FP0 floating point register, | |
c378eb4e MS |
1354 | depending on the type of the return value. In all the other cases |
1355 | the result is stored in r0, left-justified. */ | |
cc17453a | 1356 | static void |
3ffc5b9b CV |
1357 | sh_store_return_value_nofpu (struct type *type, struct regcache *regcache, |
1358 | const void *valbuf) | |
cc17453a | 1359 | { |
e17a4113 UW |
1360 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
1361 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
48db5a3c CV |
1362 | ULONGEST val; |
1363 | int len = TYPE_LENGTH (type); | |
d19b71be | 1364 | |
48db5a3c | 1365 | if (len <= 4) |
d19b71be | 1366 | { |
e17a4113 | 1367 | val = extract_unsigned_integer (valbuf, len, byte_order); |
48db5a3c | 1368 | regcache_cooked_write_unsigned (regcache, R0_REGNUM, val); |
d19b71be MS |
1369 | } |
1370 | else | |
48db5a3c CV |
1371 | { |
1372 | int i, regnum = R0_REGNUM; | |
1373 | for (i = 0; i < len; i += 4) | |
617daa0e | 1374 | regcache_raw_write (regcache, regnum++, (char *) valbuf + i); |
48db5a3c | 1375 | } |
cc17453a | 1376 | } |
c906108c | 1377 | |
cc17453a | 1378 | static void |
3ffc5b9b CV |
1379 | sh_store_return_value_fpu (struct type *type, struct regcache *regcache, |
1380 | const void *valbuf) | |
cc17453a | 1381 | { |
d93859e2 | 1382 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
afce3d2a | 1383 | if (sh_treat_as_flt_p (type)) |
48db5a3c CV |
1384 | { |
1385 | int len = TYPE_LENGTH (type); | |
d93859e2 | 1386 | int i, regnum = gdbarch_fp0_regnum (gdbarch); |
48db5a3c | 1387 | for (i = 0; i < len; i += 4) |
d93859e2 | 1388 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) |
c8a3b559 CV |
1389 | regcache_raw_write (regcache, regnum++, |
1390 | (char *) valbuf + len - 4 - i); | |
1391 | else | |
1392 | regcache_raw_write (regcache, regnum++, (char *) valbuf + i); | |
48db5a3c | 1393 | } |
cc17453a | 1394 | else |
3ffc5b9b | 1395 | sh_store_return_value_nofpu (type, regcache, valbuf); |
c906108c SS |
1396 | } |
1397 | ||
c0409442 | 1398 | static enum return_value_convention |
6a3a010b | 1399 | sh_return_value_nofpu (struct gdbarch *gdbarch, struct value *function, |
c055b101 | 1400 | struct type *type, struct regcache *regcache, |
18cf8b5b | 1401 | gdb_byte *readbuf, const gdb_byte *writebuf) |
c0409442 | 1402 | { |
6a3a010b MR |
1403 | struct type *func_type = function ? value_type (function) : NULL; |
1404 | ||
c055b101 CV |
1405 | if (sh_use_struct_convention_nofpu ( |
1406 | sh_is_renesas_calling_convention (func_type), type)) | |
c0409442 CV |
1407 | return RETURN_VALUE_STRUCT_CONVENTION; |
1408 | if (writebuf) | |
3ffc5b9b | 1409 | sh_store_return_value_nofpu (type, regcache, writebuf); |
c0409442 | 1410 | else if (readbuf) |
3ffc5b9b | 1411 | sh_extract_return_value_nofpu (type, regcache, readbuf); |
c0409442 CV |
1412 | return RETURN_VALUE_REGISTER_CONVENTION; |
1413 | } | |
1414 | ||
1415 | static enum return_value_convention | |
6a3a010b | 1416 | sh_return_value_fpu (struct gdbarch *gdbarch, struct value *function, |
c055b101 | 1417 | struct type *type, struct regcache *regcache, |
18cf8b5b | 1418 | gdb_byte *readbuf, const gdb_byte *writebuf) |
c0409442 | 1419 | { |
6a3a010b MR |
1420 | struct type *func_type = function ? value_type (function) : NULL; |
1421 | ||
c055b101 CV |
1422 | if (sh_use_struct_convention ( |
1423 | sh_is_renesas_calling_convention (func_type), type)) | |
c0409442 CV |
1424 | return RETURN_VALUE_STRUCT_CONVENTION; |
1425 | if (writebuf) | |
3ffc5b9b | 1426 | sh_store_return_value_fpu (type, regcache, writebuf); |
c0409442 | 1427 | else if (readbuf) |
3ffc5b9b | 1428 | sh_extract_return_value_fpu (type, regcache, readbuf); |
c0409442 CV |
1429 | return RETURN_VALUE_REGISTER_CONVENTION; |
1430 | } | |
1431 | ||
da962468 CV |
1432 | static struct type * |
1433 | sh_sh2a_register_type (struct gdbarch *gdbarch, int reg_nr) | |
1434 | { | |
b47193f7 | 1435 | if ((reg_nr >= gdbarch_fp0_regnum (gdbarch) |
da962468 | 1436 | && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM)) |
0dfff4cb | 1437 | return builtin_type (gdbarch)->builtin_float; |
da962468 | 1438 | else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM) |
0dfff4cb | 1439 | return builtin_type (gdbarch)->builtin_double; |
da962468 | 1440 | else |
0dfff4cb | 1441 | return builtin_type (gdbarch)->builtin_int; |
da962468 CV |
1442 | } |
1443 | ||
cc17453a EZ |
1444 | /* Return the GDB type object for the "standard" data type |
1445 | of data in register N. */ | |
cc17453a | 1446 | static struct type * |
48db5a3c | 1447 | sh_sh3e_register_type (struct gdbarch *gdbarch, int reg_nr) |
cc17453a | 1448 | { |
b47193f7 | 1449 | if ((reg_nr >= gdbarch_fp0_regnum (gdbarch) |
617daa0e | 1450 | && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM)) |
0dfff4cb | 1451 | return builtin_type (gdbarch)->builtin_float; |
8db62801 | 1452 | else |
0dfff4cb | 1453 | return builtin_type (gdbarch)->builtin_int; |
cc17453a EZ |
1454 | } |
1455 | ||
7f4dbe94 | 1456 | static struct type * |
0dfff4cb | 1457 | sh_sh4_build_float_register_type (struct gdbarch *gdbarch, int high) |
7f4dbe94 | 1458 | { |
e3506a9f UW |
1459 | return lookup_array_range_type (builtin_type (gdbarch)->builtin_float, |
1460 | 0, high); | |
7f4dbe94 EZ |
1461 | } |
1462 | ||
53116e27 | 1463 | static struct type * |
48db5a3c | 1464 | sh_sh4_register_type (struct gdbarch *gdbarch, int reg_nr) |
53116e27 | 1465 | { |
b47193f7 | 1466 | if ((reg_nr >= gdbarch_fp0_regnum (gdbarch) |
617daa0e | 1467 | && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM)) |
0dfff4cb | 1468 | return builtin_type (gdbarch)->builtin_float; |
617daa0e | 1469 | else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM) |
0dfff4cb | 1470 | return builtin_type (gdbarch)->builtin_double; |
617daa0e | 1471 | else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM) |
0dfff4cb | 1472 | return sh_sh4_build_float_register_type (gdbarch, 3); |
53116e27 | 1473 | else |
0dfff4cb | 1474 | return builtin_type (gdbarch)->builtin_int; |
53116e27 EZ |
1475 | } |
1476 | ||
cc17453a | 1477 | static struct type * |
48db5a3c | 1478 | sh_default_register_type (struct gdbarch *gdbarch, int reg_nr) |
cc17453a | 1479 | { |
0dfff4cb | 1480 | return builtin_type (gdbarch)->builtin_int; |
cc17453a EZ |
1481 | } |
1482 | ||
dda63807 AS |
1483 | /* Is a register in a reggroup? |
1484 | The default code in reggroup.c doesn't identify system registers, some | |
1485 | float registers or any of the vector registers. | |
1486 | TODO: sh2a and dsp registers. */ | |
63807e1d | 1487 | static int |
dda63807 AS |
1488 | sh_register_reggroup_p (struct gdbarch *gdbarch, int regnum, |
1489 | struct reggroup *reggroup) | |
1490 | { | |
b47193f7 UW |
1491 | if (gdbarch_register_name (gdbarch, regnum) == NULL |
1492 | || *gdbarch_register_name (gdbarch, regnum) == '\0') | |
dda63807 AS |
1493 | return 0; |
1494 | ||
1495 | if (reggroup == float_reggroup | |
1496 | && (regnum == FPUL_REGNUM | |
1497 | || regnum == FPSCR_REGNUM)) | |
1498 | return 1; | |
1499 | ||
1500 | if (regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM) | |
1501 | { | |
1502 | if (reggroup == vector_reggroup || reggroup == float_reggroup) | |
1503 | return 1; | |
1504 | if (reggroup == general_reggroup) | |
1505 | return 0; | |
1506 | } | |
1507 | ||
1508 | if (regnum == VBR_REGNUM | |
1509 | || regnum == SR_REGNUM | |
1510 | || regnum == FPSCR_REGNUM | |
1511 | || regnum == SSR_REGNUM | |
1512 | || regnum == SPC_REGNUM) | |
1513 | { | |
1514 | if (reggroup == system_reggroup) | |
1515 | return 1; | |
1516 | if (reggroup == general_reggroup) | |
1517 | return 0; | |
1518 | } | |
1519 | ||
1520 | /* The default code can cope with any other registers. */ | |
1521 | return default_register_reggroup_p (gdbarch, regnum, reggroup); | |
1522 | } | |
1523 | ||
fb409745 | 1524 | /* On the sh4, the DRi pseudo registers are problematic if the target |
c378eb4e | 1525 | is little endian. When the user writes one of those registers, for |
fb409745 EZ |
1526 | instance with 'ser var $dr0=1', we want the double to be stored |
1527 | like this: | |
1528 | fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f | |
1529 | fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00 | |
1530 | ||
1531 | This corresponds to little endian byte order & big endian word | |
1532 | order. However if we let gdb write the register w/o conversion, it | |
1533 | will write fr0 and fr1 this way: | |
1534 | fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00 | |
1535 | fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f | |
1536 | because it will consider fr0 and fr1 as a single LE stretch of memory. | |
1537 | ||
1538 | To achieve what we want we must force gdb to store things in | |
1539 | floatformat_ieee_double_littlebyte_bigword (which is defined in | |
1540 | include/floatformat.h and libiberty/floatformat.c. | |
1541 | ||
1542 | In case the target is big endian, there is no problem, the | |
1543 | raw bytes will look like: | |
1544 | fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00 | |
1545 | fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00 | |
1546 | ||
1547 | The other pseudo registers (the FVs) also don't pose a problem | |
c378eb4e | 1548 | because they are stored as 4 individual FP elements. */ |
fb409745 | 1549 | |
7bd872fe | 1550 | static void |
b66ba949 CV |
1551 | sh_register_convert_to_virtual (int regnum, struct type *type, |
1552 | char *from, char *to) | |
55ff77ac | 1553 | { |
617daa0e | 1554 | if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM) |
283150cd EZ |
1555 | { |
1556 | DOUBLEST val; | |
617daa0e CV |
1557 | floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, |
1558 | from, &val); | |
55ff77ac | 1559 | store_typed_floating (to, type, val); |
283150cd EZ |
1560 | } |
1561 | else | |
617daa0e CV |
1562 | error |
1563 | ("sh_register_convert_to_virtual called with non DR register number"); | |
283150cd EZ |
1564 | } |
1565 | ||
1566 | static void | |
b66ba949 CV |
1567 | sh_register_convert_to_raw (struct type *type, int regnum, |
1568 | const void *from, void *to) | |
283150cd | 1569 | { |
617daa0e | 1570 | if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM) |
283150cd | 1571 | { |
48db5a3c | 1572 | DOUBLEST val = extract_typed_floating (from, type); |
617daa0e CV |
1573 | floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword, |
1574 | &val, to); | |
283150cd EZ |
1575 | } |
1576 | else | |
8a3fe4f8 | 1577 | error (_("sh_register_convert_to_raw called with non DR register number")); |
283150cd EZ |
1578 | } |
1579 | ||
c378eb4e | 1580 | /* For vectors of 4 floating point registers. */ |
1c0159e0 | 1581 | static int |
d93859e2 | 1582 | fv_reg_base_num (struct gdbarch *gdbarch, int fv_regnum) |
1c0159e0 CV |
1583 | { |
1584 | int fp_regnum; | |
1585 | ||
d93859e2 | 1586 | fp_regnum = gdbarch_fp0_regnum (gdbarch) |
3e8c568d | 1587 | + (fv_regnum - FV0_REGNUM) * 4; |
1c0159e0 CV |
1588 | return fp_regnum; |
1589 | } | |
1590 | ||
c378eb4e | 1591 | /* For double precision floating point registers, i.e 2 fp regs. */ |
1c0159e0 | 1592 | static int |
d93859e2 | 1593 | dr_reg_base_num (struct gdbarch *gdbarch, int dr_regnum) |
1c0159e0 CV |
1594 | { |
1595 | int fp_regnum; | |
1596 | ||
d93859e2 | 1597 | fp_regnum = gdbarch_fp0_regnum (gdbarch) |
3e8c568d | 1598 | + (dr_regnum - DR0_REGNUM) * 2; |
1c0159e0 CV |
1599 | return fp_regnum; |
1600 | } | |
1601 | ||
05d1431c PA |
1602 | /* Concatenate PORTIONS contiguous raw registers starting at |
1603 | BASE_REGNUM into BUFFER. */ | |
1604 | ||
1605 | static enum register_status | |
1606 | pseudo_register_read_portions (struct gdbarch *gdbarch, | |
1607 | struct regcache *regcache, | |
1608 | int portions, | |
1609 | int base_regnum, gdb_byte *buffer) | |
1610 | { | |
1611 | int portion; | |
1612 | ||
1613 | for (portion = 0; portion < portions; portion++) | |
1614 | { | |
1615 | enum register_status status; | |
1616 | gdb_byte *b; | |
1617 | ||
1618 | b = buffer + register_size (gdbarch, base_regnum) * portion; | |
1619 | status = regcache_raw_read (regcache, base_regnum + portion, b); | |
1620 | if (status != REG_VALID) | |
1621 | return status; | |
1622 | } | |
1623 | ||
1624 | return REG_VALID; | |
1625 | } | |
1626 | ||
1627 | static enum register_status | |
d8124050 | 1628 | sh_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, |
18cf8b5b | 1629 | int reg_nr, gdb_byte *buffer) |
53116e27 | 1630 | { |
05d1431c | 1631 | int base_regnum; |
d9d9c31f | 1632 | char temp_buffer[MAX_REGISTER_SIZE]; |
05d1431c | 1633 | enum register_status status; |
53116e27 | 1634 | |
9bed62d7 | 1635 | if (reg_nr == PSEUDO_BANK_REGNUM) |
05d1431c PA |
1636 | return regcache_raw_read (regcache, BANK_REGNUM, buffer); |
1637 | else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM) | |
7bd872fe | 1638 | { |
d93859e2 | 1639 | base_regnum = dr_reg_base_num (gdbarch, reg_nr); |
7bd872fe | 1640 | |
c378eb4e | 1641 | /* Build the value in the provided buffer. */ |
7bd872fe | 1642 | /* Read the real regs for which this one is an alias. */ |
05d1431c PA |
1643 | status = pseudo_register_read_portions (gdbarch, regcache, |
1644 | 2, base_regnum, temp_buffer); | |
1645 | if (status == REG_VALID) | |
1646 | { | |
1647 | /* We must pay attention to the endiannes. */ | |
1648 | sh_register_convert_to_virtual (reg_nr, | |
1649 | register_type (gdbarch, reg_nr), | |
1650 | temp_buffer, buffer); | |
1651 | } | |
1652 | return status; | |
7bd872fe | 1653 | } |
617daa0e | 1654 | else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM) |
53116e27 | 1655 | { |
d93859e2 | 1656 | base_regnum = fv_reg_base_num (gdbarch, reg_nr); |
7bd872fe EZ |
1657 | |
1658 | /* Read the real regs for which this one is an alias. */ | |
05d1431c PA |
1659 | return pseudo_register_read_portions (gdbarch, regcache, |
1660 | 4, base_regnum, buffer); | |
53116e27 | 1661 | } |
05d1431c PA |
1662 | else |
1663 | gdb_assert_not_reached ("invalid pseudo register number"); | |
53116e27 EZ |
1664 | } |
1665 | ||
a78f21af | 1666 | static void |
d8124050 | 1667 | sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, |
18cf8b5b | 1668 | int reg_nr, const gdb_byte *buffer) |
53116e27 EZ |
1669 | { |
1670 | int base_regnum, portion; | |
d9d9c31f | 1671 | char temp_buffer[MAX_REGISTER_SIZE]; |
53116e27 | 1672 | |
9bed62d7 CV |
1673 | if (reg_nr == PSEUDO_BANK_REGNUM) |
1674 | { | |
1675 | /* When the bank register is written to, the whole register bank | |
1676 | is switched and all values in the bank registers must be read | |
c378eb4e | 1677 | from the target/sim again. We're just invalidating the regcache |
9bed62d7 CV |
1678 | so that a re-read happens next time it's necessary. */ |
1679 | int bregnum; | |
1680 | ||
1681 | regcache_raw_write (regcache, BANK_REGNUM, buffer); | |
1682 | for (bregnum = R0_BANK0_REGNUM; bregnum < MACLB_REGNUM; ++bregnum) | |
9c5ea4d9 | 1683 | regcache_invalidate (regcache, bregnum); |
9bed62d7 CV |
1684 | } |
1685 | else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM) | |
53116e27 | 1686 | { |
d93859e2 | 1687 | base_regnum = dr_reg_base_num (gdbarch, reg_nr); |
53116e27 | 1688 | |
c378eb4e | 1689 | /* We must pay attention to the endiannes. */ |
7b9ee6a8 | 1690 | sh_register_convert_to_raw (register_type (gdbarch, reg_nr), |
b66ba949 | 1691 | reg_nr, buffer, temp_buffer); |
7bd872fe | 1692 | |
53116e27 EZ |
1693 | /* Write the real regs for which this one is an alias. */ |
1694 | for (portion = 0; portion < 2; portion++) | |
617daa0e | 1695 | regcache_raw_write (regcache, base_regnum + portion, |
0818c12a | 1696 | (temp_buffer |
617daa0e CV |
1697 | + register_size (gdbarch, |
1698 | base_regnum) * portion)); | |
53116e27 | 1699 | } |
617daa0e | 1700 | else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM) |
53116e27 | 1701 | { |
d93859e2 | 1702 | base_regnum = fv_reg_base_num (gdbarch, reg_nr); |
53116e27 EZ |
1703 | |
1704 | /* Write the real regs for which this one is an alias. */ | |
1705 | for (portion = 0; portion < 4; portion++) | |
d8124050 AC |
1706 | regcache_raw_write (regcache, base_regnum + portion, |
1707 | ((char *) buffer | |
617daa0e CV |
1708 | + register_size (gdbarch, |
1709 | base_regnum) * portion)); | |
53116e27 EZ |
1710 | } |
1711 | } | |
1712 | ||
2f14585c | 1713 | static int |
e7faf938 | 1714 | sh_dsp_register_sim_regno (struct gdbarch *gdbarch, int nr) |
2f14585c | 1715 | { |
e7faf938 MD |
1716 | if (legacy_register_sim_regno (gdbarch, nr) < 0) |
1717 | return legacy_register_sim_regno (gdbarch, nr); | |
f2ea0907 CV |
1718 | if (nr >= DSR_REGNUM && nr <= Y1_REGNUM) |
1719 | return nr - DSR_REGNUM + SIM_SH_DSR_REGNUM; | |
1720 | if (nr == MOD_REGNUM) | |
2f14585c | 1721 | return SIM_SH_MOD_REGNUM; |
f2ea0907 | 1722 | if (nr == RS_REGNUM) |
2f14585c | 1723 | return SIM_SH_RS_REGNUM; |
f2ea0907 | 1724 | if (nr == RE_REGNUM) |
2f14585c | 1725 | return SIM_SH_RE_REGNUM; |
76cd2bd9 CV |
1726 | if (nr >= DSP_R0_BANK_REGNUM && nr <= DSP_R7_BANK_REGNUM) |
1727 | return nr - DSP_R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM; | |
2f14585c JR |
1728 | return nr; |
1729 | } | |
1c0159e0 | 1730 | |
da962468 | 1731 | static int |
e7faf938 | 1732 | sh_sh2a_register_sim_regno (struct gdbarch *gdbarch, int nr) |
da962468 CV |
1733 | { |
1734 | switch (nr) | |
1735 | { | |
1736 | case TBR_REGNUM: | |
1737 | return SIM_SH_TBR_REGNUM; | |
1738 | case IBNR_REGNUM: | |
1739 | return SIM_SH_IBNR_REGNUM; | |
1740 | case IBCR_REGNUM: | |
1741 | return SIM_SH_IBCR_REGNUM; | |
1742 | case BANK_REGNUM: | |
1743 | return SIM_SH_BANK_REGNUM; | |
1744 | case MACLB_REGNUM: | |
1745 | return SIM_SH_BANK_MACL_REGNUM; | |
1746 | case GBRB_REGNUM: | |
1747 | return SIM_SH_BANK_GBR_REGNUM; | |
1748 | case PRB_REGNUM: | |
1749 | return SIM_SH_BANK_PR_REGNUM; | |
1750 | case IVNB_REGNUM: | |
1751 | return SIM_SH_BANK_IVN_REGNUM; | |
1752 | case MACHB_REGNUM: | |
1753 | return SIM_SH_BANK_MACH_REGNUM; | |
1754 | default: | |
1755 | break; | |
1756 | } | |
e7faf938 | 1757 | return legacy_register_sim_regno (gdbarch, nr); |
da962468 CV |
1758 | } |
1759 | ||
357d3800 AS |
1760 | /* Set up the register unwinding such that call-clobbered registers are |
1761 | not displayed in frames >0 because the true value is not certain. | |
1762 | The 'undefined' registers will show up as 'not available' unless the | |
1763 | CFI says otherwise. | |
1764 | ||
1765 | This function is currently set up for SH4 and compatible only. */ | |
1766 | ||
1767 | static void | |
1768 | sh_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
aff37fc1 | 1769 | struct dwarf2_frame_state_reg *reg, |
4a4e5149 | 1770 | struct frame_info *this_frame) |
357d3800 AS |
1771 | { |
1772 | /* Mark the PC as the destination for the return address. */ | |
b47193f7 | 1773 | if (regnum == gdbarch_pc_regnum (gdbarch)) |
357d3800 AS |
1774 | reg->how = DWARF2_FRAME_REG_RA; |
1775 | ||
1776 | /* Mark the stack pointer as the call frame address. */ | |
b47193f7 | 1777 | else if (regnum == gdbarch_sp_regnum (gdbarch)) |
357d3800 AS |
1778 | reg->how = DWARF2_FRAME_REG_CFA; |
1779 | ||
1780 | /* The above was taken from the default init_reg in dwarf2-frame.c | |
1781 | while the below is SH specific. */ | |
1782 | ||
1783 | /* Caller save registers. */ | |
1784 | else if ((regnum >= R0_REGNUM && regnum <= R0_REGNUM+7) | |
1785 | || (regnum >= FR0_REGNUM && regnum <= FR0_REGNUM+11) | |
1786 | || (regnum >= DR0_REGNUM && regnum <= DR0_REGNUM+5) | |
1787 | || (regnum >= FV0_REGNUM && regnum <= FV0_REGNUM+2) | |
1788 | || (regnum == MACH_REGNUM) | |
1789 | || (regnum == MACL_REGNUM) | |
1790 | || (regnum == FPUL_REGNUM) | |
1791 | || (regnum == SR_REGNUM)) | |
1792 | reg->how = DWARF2_FRAME_REG_UNDEFINED; | |
1793 | ||
1794 | /* Callee save registers. */ | |
1795 | else if ((regnum >= R0_REGNUM+8 && regnum <= R0_REGNUM+15) | |
1796 | || (regnum >= FR0_REGNUM+12 && regnum <= FR0_REGNUM+15) | |
1797 | || (regnum >= DR0_REGNUM+6 && regnum <= DR0_REGNUM+8) | |
1798 | || (regnum == FV0_REGNUM+3)) | |
1799 | reg->how = DWARF2_FRAME_REG_SAME_VALUE; | |
1800 | ||
1801 | /* Other registers. These are not in the ABI and may or may not | |
1802 | mean anything in frames >0 so don't show them. */ | |
1803 | else if ((regnum >= R0_BANK0_REGNUM && regnum <= R0_BANK0_REGNUM+15) | |
1804 | || (regnum == GBR_REGNUM) | |
1805 | || (regnum == VBR_REGNUM) | |
1806 | || (regnum == FPSCR_REGNUM) | |
1807 | || (regnum == SSR_REGNUM) | |
1808 | || (regnum == SPC_REGNUM)) | |
1809 | reg->how = DWARF2_FRAME_REG_UNDEFINED; | |
1810 | } | |
1811 | ||
1c0159e0 CV |
1812 | static struct sh_frame_cache * |
1813 | sh_alloc_frame_cache (void) | |
1814 | { | |
1815 | struct sh_frame_cache *cache; | |
1816 | int i; | |
1817 | ||
1818 | cache = FRAME_OBSTACK_ZALLOC (struct sh_frame_cache); | |
1819 | ||
1820 | /* Base address. */ | |
1821 | cache->base = 0; | |
1822 | cache->saved_sp = 0; | |
1823 | cache->sp_offset = 0; | |
1824 | cache->pc = 0; | |
1825 | ||
1826 | /* Frameless until proven otherwise. */ | |
1827 | cache->uses_fp = 0; | |
617daa0e | 1828 | |
1c0159e0 CV |
1829 | /* Saved registers. We initialize these to -1 since zero is a valid |
1830 | offset (that's where fp is supposed to be stored). */ | |
1831 | for (i = 0; i < SH_NUM_REGS; i++) | |
1832 | { | |
1833 | cache->saved_regs[i] = -1; | |
1834 | } | |
617daa0e | 1835 | |
1c0159e0 | 1836 | return cache; |
617daa0e | 1837 | } |
1c0159e0 CV |
1838 | |
1839 | static struct sh_frame_cache * | |
94afd7a6 | 1840 | sh_frame_cache (struct frame_info *this_frame, void **this_cache) |
1c0159e0 | 1841 | { |
e17a4113 | 1842 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1c0159e0 CV |
1843 | struct sh_frame_cache *cache; |
1844 | CORE_ADDR current_pc; | |
1845 | int i; | |
1846 | ||
1847 | if (*this_cache) | |
1848 | return *this_cache; | |
1849 | ||
1850 | cache = sh_alloc_frame_cache (); | |
1851 | *this_cache = cache; | |
1852 | ||
1853 | /* In principle, for normal frames, fp holds the frame pointer, | |
1854 | which holds the base address for the current stack frame. | |
1855 | However, for functions that don't need it, the frame pointer is | |
1856 | optional. For these "frameless" functions the frame pointer is | |
c378eb4e | 1857 | actually the frame pointer of the calling frame. */ |
94afd7a6 | 1858 | cache->base = get_frame_register_unsigned (this_frame, FP_REGNUM); |
1c0159e0 CV |
1859 | if (cache->base == 0) |
1860 | return cache; | |
1861 | ||
94afd7a6 UW |
1862 | cache->pc = get_frame_func (this_frame); |
1863 | current_pc = get_frame_pc (this_frame); | |
1c0159e0 | 1864 | if (cache->pc != 0) |
d2ca4222 UW |
1865 | { |
1866 | ULONGEST fpscr; | |
9fc05685 KB |
1867 | |
1868 | /* Check for the existence of the FPSCR register. If it exists, | |
1869 | fetch its value for use in prologue analysis. Passing a zero | |
1870 | value is the best choice for architecture variants upon which | |
1871 | there's no FPSCR register. */ | |
1872 | if (gdbarch_register_reggroup_p (gdbarch, FPSCR_REGNUM, all_reggroup)) | |
1873 | fpscr = get_frame_register_unsigned (this_frame, FPSCR_REGNUM); | |
1874 | else | |
1875 | fpscr = 0; | |
1876 | ||
e17a4113 | 1877 | sh_analyze_prologue (gdbarch, cache->pc, current_pc, cache, fpscr); |
d2ca4222 | 1878 | } |
617daa0e | 1879 | |
1c0159e0 CV |
1880 | if (!cache->uses_fp) |
1881 | { | |
1882 | /* We didn't find a valid frame, which means that CACHE->base | |
1883 | currently holds the frame pointer for our calling frame. If | |
1884 | we're at the start of a function, or somewhere half-way its | |
1885 | prologue, the function's frame probably hasn't been fully | |
1886 | setup yet. Try to reconstruct the base address for the stack | |
1887 | frame by looking at the stack pointer. For truly "frameless" | |
1888 | functions this might work too. */ | |
94afd7a6 | 1889 | cache->base = get_frame_register_unsigned |
e17a4113 | 1890 | (this_frame, gdbarch_sp_regnum (gdbarch)); |
1c0159e0 CV |
1891 | } |
1892 | ||
1893 | /* Now that we have the base address for the stack frame we can | |
1894 | calculate the value of sp in the calling frame. */ | |
1895 | cache->saved_sp = cache->base + cache->sp_offset; | |
1896 | ||
1897 | /* Adjust all the saved registers such that they contain addresses | |
1898 | instead of offsets. */ | |
1899 | for (i = 0; i < SH_NUM_REGS; i++) | |
1900 | if (cache->saved_regs[i] != -1) | |
1901 | cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i] - 4; | |
1902 | ||
1903 | return cache; | |
1904 | } | |
1905 | ||
94afd7a6 UW |
1906 | static struct value * |
1907 | sh_frame_prev_register (struct frame_info *this_frame, | |
1908 | void **this_cache, int regnum) | |
1c0159e0 | 1909 | { |
94afd7a6 UW |
1910 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1911 | struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache); | |
1c0159e0 CV |
1912 | |
1913 | gdb_assert (regnum >= 0); | |
1914 | ||
b47193f7 | 1915 | if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp) |
94afd7a6 | 1916 | return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp); |
1c0159e0 CV |
1917 | |
1918 | /* The PC of the previous frame is stored in the PR register of | |
1919 | the current frame. Frob regnum so that we pull the value from | |
1920 | the correct place. */ | |
b47193f7 | 1921 | if (regnum == gdbarch_pc_regnum (gdbarch)) |
1c0159e0 CV |
1922 | regnum = PR_REGNUM; |
1923 | ||
1924 | if (regnum < SH_NUM_REGS && cache->saved_regs[regnum] != -1) | |
94afd7a6 UW |
1925 | return frame_unwind_got_memory (this_frame, regnum, |
1926 | cache->saved_regs[regnum]); | |
1c0159e0 | 1927 | |
94afd7a6 | 1928 | return frame_unwind_got_register (this_frame, regnum, regnum); |
1c0159e0 CV |
1929 | } |
1930 | ||
1931 | static void | |
94afd7a6 | 1932 | sh_frame_this_id (struct frame_info *this_frame, void **this_cache, |
617daa0e CV |
1933 | struct frame_id *this_id) |
1934 | { | |
94afd7a6 | 1935 | struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache); |
1c0159e0 CV |
1936 | |
1937 | /* This marks the outermost frame. */ | |
1938 | if (cache->base == 0) | |
1939 | return; | |
1940 | ||
1941 | *this_id = frame_id_build (cache->saved_sp, cache->pc); | |
617daa0e | 1942 | } |
1c0159e0 | 1943 | |
617daa0e | 1944 | static const struct frame_unwind sh_frame_unwind = { |
1c0159e0 | 1945 | NORMAL_FRAME, |
8fbca658 | 1946 | default_frame_unwind_stop_reason, |
1c0159e0 | 1947 | sh_frame_this_id, |
94afd7a6 UW |
1948 | sh_frame_prev_register, |
1949 | NULL, | |
1950 | default_frame_sniffer | |
1c0159e0 CV |
1951 | }; |
1952 | ||
1c0159e0 CV |
1953 | static CORE_ADDR |
1954 | sh_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1955 | { | |
3e8c568d | 1956 | return frame_unwind_register_unsigned (next_frame, |
b47193f7 | 1957 | gdbarch_sp_regnum (gdbarch)); |
1c0159e0 CV |
1958 | } |
1959 | ||
1960 | static CORE_ADDR | |
1961 | sh_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1962 | { | |
3e8c568d | 1963 | return frame_unwind_register_unsigned (next_frame, |
b47193f7 | 1964 | gdbarch_pc_regnum (gdbarch)); |
1c0159e0 CV |
1965 | } |
1966 | ||
1967 | static struct frame_id | |
94afd7a6 | 1968 | sh_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
1c0159e0 | 1969 | { |
94afd7a6 UW |
1970 | CORE_ADDR sp = get_frame_register_unsigned (this_frame, |
1971 | gdbarch_sp_regnum (gdbarch)); | |
1972 | return frame_id_build (sp, get_frame_pc (this_frame)); | |
1c0159e0 CV |
1973 | } |
1974 | ||
1975 | static CORE_ADDR | |
94afd7a6 | 1976 | sh_frame_base_address (struct frame_info *this_frame, void **this_cache) |
617daa0e | 1977 | { |
94afd7a6 | 1978 | struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache); |
617daa0e | 1979 | |
1c0159e0 CV |
1980 | return cache->base; |
1981 | } | |
617daa0e CV |
1982 | |
1983 | static const struct frame_base sh_frame_base = { | |
1c0159e0 CV |
1984 | &sh_frame_unwind, |
1985 | sh_frame_base_address, | |
1986 | sh_frame_base_address, | |
1987 | sh_frame_base_address | |
617daa0e | 1988 | }; |
1c0159e0 | 1989 | |
cb2cf4ce TS |
1990 | static struct sh_frame_cache * |
1991 | sh_make_stub_cache (struct frame_info *this_frame) | |
1992 | { | |
1993 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
1994 | struct sh_frame_cache *cache; | |
1995 | ||
1996 | cache = sh_alloc_frame_cache (); | |
1997 | ||
1998 | cache->saved_sp | |
1999 | = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch)); | |
2000 | ||
2001 | return cache; | |
2002 | } | |
2003 | ||
2004 | static void | |
2005 | sh_stub_this_id (struct frame_info *this_frame, void **this_cache, | |
2006 | struct frame_id *this_id) | |
2007 | { | |
2008 | struct sh_frame_cache *cache; | |
2009 | ||
2010 | if (*this_cache == NULL) | |
2011 | *this_cache = sh_make_stub_cache (this_frame); | |
2012 | cache = *this_cache; | |
2013 | ||
2014 | *this_id = frame_id_build (cache->saved_sp, get_frame_pc (this_frame)); | |
2015 | } | |
2016 | ||
2017 | static int | |
2018 | sh_stub_unwind_sniffer (const struct frame_unwind *self, | |
2019 | struct frame_info *this_frame, | |
2020 | void **this_prologue_cache) | |
2021 | { | |
2022 | CORE_ADDR addr_in_block; | |
2023 | ||
2024 | addr_in_block = get_frame_address_in_block (this_frame); | |
2025 | if (in_plt_section (addr_in_block, NULL)) | |
2026 | return 1; | |
2027 | ||
2028 | return 0; | |
2029 | } | |
2030 | ||
2031 | static const struct frame_unwind sh_stub_unwind = | |
2032 | { | |
2033 | NORMAL_FRAME, | |
2034 | default_frame_unwind_stop_reason, | |
2035 | sh_stub_this_id, | |
2036 | sh_frame_prev_register, | |
2037 | NULL, | |
2038 | sh_stub_unwind_sniffer | |
2039 | }; | |
2040 | ||
1c0159e0 CV |
2041 | /* The epilogue is defined here as the area at the end of a function, |
2042 | either on the `ret' instruction itself or after an instruction which | |
c378eb4e | 2043 | destroys the function's stack frame. */ |
1c0159e0 CV |
2044 | static int |
2045 | sh_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
2046 | { | |
e17a4113 | 2047 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1c0159e0 CV |
2048 | CORE_ADDR func_addr = 0, func_end = 0; |
2049 | ||
2050 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
2051 | { | |
2052 | ULONGEST inst; | |
2053 | /* The sh epilogue is max. 14 bytes long. Give another 14 bytes | |
2054 | for a nop and some fixed data (e.g. big offsets) which are | |
617daa0e | 2055 | unfortunately also treated as part of the function (which |
c378eb4e | 2056 | means, they are below func_end. */ |
1c0159e0 CV |
2057 | CORE_ADDR addr = func_end - 28; |
2058 | if (addr < func_addr + 4) | |
617daa0e | 2059 | addr = func_addr + 4; |
1c0159e0 CV |
2060 | if (pc < addr) |
2061 | return 0; | |
2062 | ||
c378eb4e | 2063 | /* First search forward until hitting an rts. */ |
1c0159e0 | 2064 | while (addr < func_end |
e17a4113 | 2065 | && !IS_RTS (read_memory_unsigned_integer (addr, 2, byte_order))) |
1c0159e0 CV |
2066 | addr += 2; |
2067 | if (addr >= func_end) | |
617daa0e | 2068 | return 0; |
1c0159e0 CV |
2069 | |
2070 | /* At this point we should find a mov.l @r15+,r14 instruction, | |
2071 | either before or after the rts. If not, then the function has | |
c378eb4e | 2072 | probably no "normal" epilogue and we bail out here. */ |
e17a4113 UW |
2073 | inst = read_memory_unsigned_integer (addr - 2, 2, byte_order); |
2074 | if (IS_RESTORE_FP (read_memory_unsigned_integer (addr - 2, 2, | |
2075 | byte_order))) | |
617daa0e | 2076 | addr -= 2; |
e17a4113 UW |
2077 | else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr + 2, 2, |
2078 | byte_order))) | |
1c0159e0 CV |
2079 | return 0; |
2080 | ||
e17a4113 | 2081 | inst = read_memory_unsigned_integer (addr - 2, 2, byte_order); |
03131d99 | 2082 | |
c378eb4e | 2083 | /* Step over possible lds.l @r15+,macl. */ |
03131d99 CV |
2084 | if (IS_MACL_LDS (inst)) |
2085 | { | |
2086 | addr -= 2; | |
e17a4113 | 2087 | inst = read_memory_unsigned_integer (addr - 2, 2, byte_order); |
03131d99 CV |
2088 | } |
2089 | ||
c378eb4e | 2090 | /* Step over possible lds.l @r15+,pr. */ |
1c0159e0 | 2091 | if (IS_LDS (inst)) |
617daa0e | 2092 | { |
1c0159e0 | 2093 | addr -= 2; |
e17a4113 | 2094 | inst = read_memory_unsigned_integer (addr - 2, 2, byte_order); |
1c0159e0 CV |
2095 | } |
2096 | ||
c378eb4e | 2097 | /* Step over possible mov r14,r15. */ |
1c0159e0 | 2098 | if (IS_MOV_FP_SP (inst)) |
617daa0e | 2099 | { |
1c0159e0 | 2100 | addr -= 2; |
e17a4113 | 2101 | inst = read_memory_unsigned_integer (addr - 2, 2, byte_order); |
1c0159e0 CV |
2102 | } |
2103 | ||
2104 | /* Now check for FP adjustments, using add #imm,r14 or add rX, r14 | |
c378eb4e | 2105 | instructions. */ |
1c0159e0 | 2106 | while (addr > func_addr + 4 |
617daa0e | 2107 | && (IS_ADD_REG_TO_FP (inst) || IS_ADD_IMM_FP (inst))) |
1c0159e0 CV |
2108 | { |
2109 | addr -= 2; | |
e17a4113 | 2110 | inst = read_memory_unsigned_integer (addr - 2, 2, byte_order); |
1c0159e0 CV |
2111 | } |
2112 | ||
03131d99 CV |
2113 | /* On SH2a check if the previous instruction was perhaps a MOVI20. |
2114 | That's allowed for the epilogue. */ | |
2115 | if ((gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a | |
2116 | || gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a_nofpu) | |
2117 | && addr > func_addr + 6 | |
e17a4113 UW |
2118 | && IS_MOVI20 (read_memory_unsigned_integer (addr - 4, 2, |
2119 | byte_order))) | |
03131d99 CV |
2120 | addr -= 4; |
2121 | ||
1c0159e0 CV |
2122 | if (pc >= addr) |
2123 | return 1; | |
2124 | } | |
2125 | return 0; | |
2126 | } | |
c9ac0a72 AS |
2127 | |
2128 | ||
2129 | /* Supply register REGNUM from the buffer specified by REGS and LEN | |
2130 | in the register set REGSET to register cache REGCACHE. | |
2131 | REGTABLE specifies where each register can be found in REGS. | |
2132 | If REGNUM is -1, do this for all registers in REGSET. */ | |
2133 | ||
2134 | void | |
2135 | sh_corefile_supply_regset (const struct regset *regset, | |
2136 | struct regcache *regcache, | |
2137 | int regnum, const void *regs, size_t len) | |
2138 | { | |
2139 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
2140 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2141 | const struct sh_corefile_regmap *regmap = (regset == &sh_corefile_gregset | |
2142 | ? tdep->core_gregmap | |
2143 | : tdep->core_fpregmap); | |
2144 | int i; | |
2145 | ||
2146 | for (i = 0; regmap[i].regnum != -1; i++) | |
2147 | { | |
2148 | if ((regnum == -1 || regnum == regmap[i].regnum) | |
2149 | && regmap[i].offset + 4 <= len) | |
2150 | regcache_raw_supply (regcache, regmap[i].regnum, | |
2151 | (char *)regs + regmap[i].offset); | |
2152 | } | |
2153 | } | |
2154 | ||
2155 | /* Collect register REGNUM in the register set REGSET from register cache | |
2156 | REGCACHE into the buffer specified by REGS and LEN. | |
2157 | REGTABLE specifies where each register can be found in REGS. | |
2158 | If REGNUM is -1, do this for all registers in REGSET. */ | |
2159 | ||
2160 | void | |
2161 | sh_corefile_collect_regset (const struct regset *regset, | |
2162 | const struct regcache *regcache, | |
2163 | int regnum, void *regs, size_t len) | |
2164 | { | |
2165 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
2166 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2167 | const struct sh_corefile_regmap *regmap = (regset == &sh_corefile_gregset | |
2168 | ? tdep->core_gregmap | |
2169 | : tdep->core_fpregmap); | |
2170 | int i; | |
2171 | ||
2172 | for (i = 0; regmap[i].regnum != -1; i++) | |
2173 | { | |
2174 | if ((regnum == -1 || regnum == regmap[i].regnum) | |
2175 | && regmap[i].offset + 4 <= len) | |
2176 | regcache_raw_collect (regcache, regmap[i].regnum, | |
2177 | (char *)regs + regmap[i].offset); | |
2178 | } | |
2179 | } | |
2180 | ||
2181 | /* The following two regsets have the same contents, so it is tempting to | |
2182 | unify them, but they are distiguished by their address, so don't. */ | |
2183 | ||
2184 | struct regset sh_corefile_gregset = | |
2185 | { | |
2186 | NULL, | |
2187 | sh_corefile_supply_regset, | |
2188 | sh_corefile_collect_regset | |
2189 | }; | |
2190 | ||
2191 | static struct regset sh_corefile_fpregset = | |
2192 | { | |
2193 | NULL, | |
2194 | sh_corefile_supply_regset, | |
2195 | sh_corefile_collect_regset | |
2196 | }; | |
2197 | ||
2198 | static const struct regset * | |
2199 | sh_regset_from_core_section (struct gdbarch *gdbarch, const char *sect_name, | |
2200 | size_t sect_size) | |
2201 | { | |
2202 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2203 | ||
2204 | if (tdep->core_gregmap && strcmp (sect_name, ".reg") == 0) | |
2205 | return &sh_corefile_gregset; | |
2206 | ||
2207 | if (tdep->core_fpregmap && strcmp (sect_name, ".reg2") == 0) | |
2208 | return &sh_corefile_fpregset; | |
2209 | ||
2210 | return NULL; | |
2211 | } | |
18648a37 YQ |
2212 | |
2213 | /* This is the implementation of gdbarch method | |
2214 | return_in_first_hidden_param_p. */ | |
2215 | ||
2216 | static int | |
2217 | sh_return_in_first_hidden_param_p (struct gdbarch *gdbarch, | |
2218 | struct type *type) | |
2219 | { | |
2220 | return 0; | |
2221 | } | |
2222 | ||
ccf00f21 | 2223 | \f |
cc17453a EZ |
2224 | |
2225 | static struct gdbarch * | |
fba45db2 | 2226 | sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
cc17453a | 2227 | { |
cc17453a | 2228 | struct gdbarch *gdbarch; |
c9ac0a72 | 2229 | struct gdbarch_tdep *tdep; |
d658f924 | 2230 | |
2d4c29c5 TS |
2231 | /* SH5 is handled entirely in sh64-tdep.c. */ |
2232 | if (info.bfd_arch_info->mach == bfd_mach_sh5) | |
2233 | return sh64_gdbarch_init (info, arches); | |
55ff77ac | 2234 | |
4be87837 DJ |
2235 | /* If there is already a candidate, use it. */ |
2236 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
2237 | if (arches != NULL) | |
2238 | return arches->gdbarch; | |
cc17453a EZ |
2239 | |
2240 | /* None found, create a new architecture from the information | |
c378eb4e | 2241 | provided. */ |
c9ac0a72 AS |
2242 | tdep = XZALLOC (struct gdbarch_tdep); |
2243 | gdbarch = gdbarch_alloc (&info, tdep); | |
cc17453a | 2244 | |
48db5a3c CV |
2245 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); |
2246 | set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
ec920329 | 2247 | set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
48db5a3c CV |
2248 | set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); |
2249 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
2250 | set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
2251 | set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
a38d2a54 | 2252 | set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
48db5a3c | 2253 | |
f2ea0907 | 2254 | set_gdbarch_num_regs (gdbarch, SH_NUM_REGS); |
a38d2a54 | 2255 | set_gdbarch_sp_regnum (gdbarch, 15); |
a38d2a54 | 2256 | set_gdbarch_pc_regnum (gdbarch, 16); |
48db5a3c CV |
2257 | set_gdbarch_fp0_regnum (gdbarch, -1); |
2258 | set_gdbarch_num_pseudo_regs (gdbarch, 0); | |
2259 | ||
1c0159e0 | 2260 | set_gdbarch_register_type (gdbarch, sh_default_register_type); |
dda63807 | 2261 | set_gdbarch_register_reggroup_p (gdbarch, sh_register_reggroup_p); |
1c0159e0 | 2262 | |
eaf90c5d | 2263 | set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc); |
48db5a3c | 2264 | |
9dae60cc | 2265 | set_gdbarch_print_insn (gdbarch, print_insn_sh); |
2f14585c | 2266 | set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno); |
48db5a3c | 2267 | |
c0409442 | 2268 | set_gdbarch_return_value (gdbarch, sh_return_value_nofpu); |
1c0159e0 | 2269 | |
48db5a3c CV |
2270 | set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue); |
2271 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
48db5a3c | 2272 | |
1c0159e0 | 2273 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu); |
18648a37 YQ |
2274 | set_gdbarch_return_in_first_hidden_param_p (gdbarch, |
2275 | sh_return_in_first_hidden_param_p); | |
1c0159e0 | 2276 | |
48db5a3c CV |
2277 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); |
2278 | ||
19f59343 | 2279 | set_gdbarch_frame_align (gdbarch, sh_frame_align); |
1c0159e0 CV |
2280 | set_gdbarch_unwind_sp (gdbarch, sh_unwind_sp); |
2281 | set_gdbarch_unwind_pc (gdbarch, sh_unwind_pc); | |
94afd7a6 | 2282 | set_gdbarch_dummy_id (gdbarch, sh_dummy_id); |
1c0159e0 CV |
2283 | frame_base_set_default (gdbarch, &sh_frame_base); |
2284 | ||
617daa0e | 2285 | set_gdbarch_in_function_epilogue_p (gdbarch, sh_in_function_epilogue_p); |
cc17453a | 2286 | |
357d3800 AS |
2287 | dwarf2_frame_set_init_reg (gdbarch, sh_dwarf2_frame_init_reg); |
2288 | ||
c9ac0a72 AS |
2289 | set_gdbarch_regset_from_core_section (gdbarch, sh_regset_from_core_section); |
2290 | ||
cc17453a | 2291 | switch (info.bfd_arch_info->mach) |
8db62801 | 2292 | { |
cc17453a | 2293 | case bfd_mach_sh: |
48db5a3c | 2294 | set_gdbarch_register_name (gdbarch, sh_sh_register_name); |
cc17453a | 2295 | break; |
1c0159e0 | 2296 | |
cc17453a | 2297 | case bfd_mach_sh2: |
48db5a3c | 2298 | set_gdbarch_register_name (gdbarch, sh_sh_register_name); |
617daa0e | 2299 | break; |
1c0159e0 | 2300 | |
2d188dd3 | 2301 | case bfd_mach_sh2e: |
c378eb4e | 2302 | /* doubles on sh2e and sh3e are actually 4 byte. */ |
48db5a3c CV |
2303 | set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
2304 | ||
2305 | set_gdbarch_register_name (gdbarch, sh_sh2e_register_name); | |
48db5a3c | 2306 | set_gdbarch_register_type (gdbarch, sh_sh3e_register_type); |
2d188dd3 | 2307 | set_gdbarch_fp0_regnum (gdbarch, 25); |
c0409442 | 2308 | set_gdbarch_return_value (gdbarch, sh_return_value_fpu); |
6df2bf50 | 2309 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); |
2d188dd3 | 2310 | break; |
1c0159e0 | 2311 | |
da962468 CV |
2312 | case bfd_mach_sh2a: |
2313 | set_gdbarch_register_name (gdbarch, sh_sh2a_register_name); | |
2314 | set_gdbarch_register_type (gdbarch, sh_sh2a_register_type); | |
2315 | set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno); | |
2316 | ||
2317 | set_gdbarch_fp0_regnum (gdbarch, 25); | |
2318 | set_gdbarch_num_pseudo_regs (gdbarch, 9); | |
2319 | set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read); | |
2320 | set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write); | |
c0409442 | 2321 | set_gdbarch_return_value (gdbarch, sh_return_value_fpu); |
da962468 CV |
2322 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); |
2323 | break; | |
2324 | ||
2325 | case bfd_mach_sh2a_nofpu: | |
2326 | set_gdbarch_register_name (gdbarch, sh_sh2a_nofpu_register_name); | |
2327 | set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno); | |
2328 | ||
2329 | set_gdbarch_num_pseudo_regs (gdbarch, 1); | |
2330 | set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read); | |
2331 | set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write); | |
2332 | break; | |
2333 | ||
cc17453a | 2334 | case bfd_mach_sh_dsp: |
48db5a3c | 2335 | set_gdbarch_register_name (gdbarch, sh_sh_dsp_register_name); |
2f14585c | 2336 | set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno); |
cc17453a | 2337 | break; |
1c0159e0 | 2338 | |
cc17453a | 2339 | case bfd_mach_sh3: |
4e6cbc38 AS |
2340 | case bfd_mach_sh3_nommu: |
2341 | case bfd_mach_sh2a_nofpu_or_sh3_nommu: | |
48db5a3c | 2342 | set_gdbarch_register_name (gdbarch, sh_sh3_register_name); |
cc17453a | 2343 | break; |
1c0159e0 | 2344 | |
cc17453a | 2345 | case bfd_mach_sh3e: |
4e6cbc38 | 2346 | case bfd_mach_sh2a_or_sh3e: |
c378eb4e | 2347 | /* doubles on sh2e and sh3e are actually 4 byte. */ |
48db5a3c CV |
2348 | set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
2349 | ||
2350 | set_gdbarch_register_name (gdbarch, sh_sh3e_register_name); | |
48db5a3c | 2351 | set_gdbarch_register_type (gdbarch, sh_sh3e_register_type); |
cc17453a | 2352 | set_gdbarch_fp0_regnum (gdbarch, 25); |
c0409442 | 2353 | set_gdbarch_return_value (gdbarch, sh_return_value_fpu); |
6df2bf50 | 2354 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); |
cc17453a | 2355 | break; |
1c0159e0 | 2356 | |
cc17453a | 2357 | case bfd_mach_sh3_dsp: |
48db5a3c | 2358 | set_gdbarch_register_name (gdbarch, sh_sh3_dsp_register_name); |
48db5a3c | 2359 | set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno); |
cc17453a | 2360 | break; |
1c0159e0 | 2361 | |
cc17453a | 2362 | case bfd_mach_sh4: |
474e5826 | 2363 | case bfd_mach_sh4a: |
46e8a76b | 2364 | case bfd_mach_sh2a_or_sh4: |
48db5a3c | 2365 | set_gdbarch_register_name (gdbarch, sh_sh4_register_name); |
48db5a3c | 2366 | set_gdbarch_register_type (gdbarch, sh_sh4_register_type); |
cc17453a | 2367 | set_gdbarch_fp0_regnum (gdbarch, 25); |
da962468 | 2368 | set_gdbarch_num_pseudo_regs (gdbarch, 13); |
d8124050 AC |
2369 | set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read); |
2370 | set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write); | |
c0409442 | 2371 | set_gdbarch_return_value (gdbarch, sh_return_value_fpu); |
6df2bf50 | 2372 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); |
cc17453a | 2373 | break; |
1c0159e0 | 2374 | |
474e5826 CV |
2375 | case bfd_mach_sh4_nofpu: |
2376 | case bfd_mach_sh4a_nofpu: | |
4e6cbc38 AS |
2377 | case bfd_mach_sh4_nommu_nofpu: |
2378 | case bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu: | |
474e5826 CV |
2379 | set_gdbarch_register_name (gdbarch, sh_sh4_nofpu_register_name); |
2380 | break; | |
2381 | ||
2382 | case bfd_mach_sh4al_dsp: | |
2383 | set_gdbarch_register_name (gdbarch, sh_sh4al_dsp_register_name); | |
2384 | set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno); | |
2385 | break; | |
2386 | ||
cc17453a | 2387 | default: |
b58cbbf2 | 2388 | set_gdbarch_register_name (gdbarch, sh_sh_register_name); |
cc17453a | 2389 | break; |
8db62801 | 2390 | } |
cc17453a | 2391 | |
4be87837 DJ |
2392 | /* Hook in ABI-specific overrides, if they have been registered. */ |
2393 | gdbarch_init_osabi (info, gdbarch); | |
d658f924 | 2394 | |
94afd7a6 | 2395 | dwarf2_append_unwinders (gdbarch); |
cb2cf4ce | 2396 | frame_unwind_append_unwinder (gdbarch, &sh_stub_unwind); |
94afd7a6 | 2397 | frame_unwind_append_unwinder (gdbarch, &sh_frame_unwind); |
1c0159e0 | 2398 | |
cc17453a | 2399 | return gdbarch; |
8db62801 EZ |
2400 | } |
2401 | ||
c055b101 CV |
2402 | static void |
2403 | show_sh_command (char *args, int from_tty) | |
2404 | { | |
2405 | help_list (showshcmdlist, "show sh ", all_commands, gdb_stdout); | |
2406 | } | |
2407 | ||
2408 | static void | |
2409 | set_sh_command (char *args, int from_tty) | |
2410 | { | |
2411 | printf_unfiltered | |
2412 | ("\"set sh\" must be followed by an appropriate subcommand.\n"); | |
2413 | help_list (setshcmdlist, "set sh ", all_commands, gdb_stdout); | |
2414 | } | |
2415 | ||
c378eb4e | 2416 | extern initialize_file_ftype _initialize_sh_tdep; /* -Wmissing-prototypes */ |
a78f21af | 2417 | |
c906108c | 2418 | void |
fba45db2 | 2419 | _initialize_sh_tdep (void) |
c906108c SS |
2420 | { |
2421 | struct cmd_list_element *c; | |
617daa0e | 2422 | |
f2ea0907 | 2423 | gdbarch_register (bfd_arch_sh, sh_gdbarch_init, NULL); |
c906108c | 2424 | |
2d4c29c5 TS |
2425 | /* We can't use an alias here because 'info registers' has not yet been |
2426 | registered. */ | |
2427 | c = add_com ("regs", class_vars, all_registers_info, | |
2428 | _("Print all registers")); | |
2429 | deprecate_cmd (c, "info all-registers"); | |
2430 | ||
c055b101 CV |
2431 | add_prefix_cmd ("sh", no_class, set_sh_command, "SH specific commands.", |
2432 | &setshcmdlist, "set sh ", 0, &setlist); | |
2433 | add_prefix_cmd ("sh", no_class, show_sh_command, "SH specific commands.", | |
2434 | &showshcmdlist, "show sh ", 0, &showlist); | |
2435 | ||
2436 | add_setshow_enum_cmd ("calling-convention", class_vars, sh_cc_enum, | |
2437 | &sh_active_calling_convention, | |
2438 | _("Set calling convention used when calling target " | |
2439 | "functions from GDB."), | |
2440 | _("Show calling convention used when calling target " | |
2441 | "functions from GDB."), | |
2442 | _("gcc - Use GCC calling convention (default).\n" | |
2443 | "renesas - Enforce Renesas calling convention."), | |
2444 | NULL, NULL, | |
2445 | &setshcmdlist, &showshcmdlist); | |
c906108c | 2446 | } |