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[deliverable/binutils-gdb.git] / gdb / sh-tdep.c
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c906108c 1/* Target-dependent code for Hitachi Super-H, for GDB.
538a76d6 2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
3116c80a 3 Free Software Foundation, Inc.
c906108c 4
c5aa993b 5 This file is part of GDB.
c906108c 6
c5aa993b
JM		 7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
c906108c 11
c5aa993b
JM		 12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
c906108c 16
c5aa993b
JM		 17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
c906108c
SS		 21
22/*
c5aa993b
JM		 23 Contributed by Steve Chamberlain
24 sac@cygnus.com
c906108c
SS		 25 */
26
27#include "defs.h"
28#include "frame.h"
29#include "obstack.h"
30#include "symtab.h"
31#include "symfile.h"
32#include "gdbtypes.h"
33#include "gdbcmd.h"
34#include "gdbcore.h"
35#include "value.h"
36#include "dis-asm.h"
37#include "inferior.h" /* for BEFORE_TEXT_END etc. */
38#include "gdb_string.h"
b4a20239 39#include "arch-utils.h"
fb409745 40#include "floatformat.h"
4e052eda 41#include "regcache.h"
d16aafd8 42#include "doublest.h"
c906108c 43
1a8629c7
MS		 44#include "solib-svr4.h"
45
cc17453a
EZ		 46#undef XMALLOC
47#define XMALLOC(TYPE) ((TYPE*) xmalloc (sizeof (TYPE)))
48
53116e27 49void (*sh_show_regs) (void);
3bbfbb92
EZ		 50CORE_ADDR (*skip_prologue_hard_way) (CORE_ADDR);
51void (*do_pseudo_register) (int);
cc17453a 52
88e04cc1
EZ		 53#define SH_DEFAULT_NUM_REGS 59
54
cc17453a
EZ		 55/* Define other aspects of the stack frame.
56 we keep a copy of the worked out return pc lying around, since it
57 is a useful bit of info */
58
59struct frame_extra_info
60{
61 CORE_ADDR return_pc;
62 int leaf_function;
63 int f_offset;
63978407 64};
c906108c 65
cc17453a
EZ		 66static char *
67sh_generic_register_name (int reg_nr)
c5aa993b 68{
cc17453a 69 static char *register_names[] =
c5aa993b 70 {
cc17453a
EZ		 71 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
72 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
73 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
74 "fpul", "fpscr",
75 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
76 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
77 "ssr", "spc",
78 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
79 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
80 };
81 if (reg_nr < 0)
82 return NULL;
83 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
84 return NULL;
85 return register_names[reg_nr];
86}
87
88static char *
89sh_sh_register_name (int reg_nr)
90{
91 static char *register_names[] =
63978407 92 {
cc17453a
EZ		 93 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
94 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
95 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
96 "", "",
97 "", "", "", "", "", "", "", "",
98 "", "", "", "", "", "", "", "",
99 "", "",
100 "", "", "", "", "", "", "", "",
101 "", "", "", "", "", "", "", "",
102 };
103 if (reg_nr < 0)
104 return NULL;
105 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
106 return NULL;
107 return register_names[reg_nr];
108}
109
110static char *
111sh_sh3_register_name (int reg_nr)
112{
113 static char *register_names[] =
c5aa993b 114 {
cc17453a
EZ		 115 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
116 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
117 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
118 "", "",
119 "", "", "", "", "", "", "", "",
120 "", "", "", "", "", "", "", "",
121 "ssr", "spc",
122 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
123 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
124 };
125 if (reg_nr < 0)
126 return NULL;
127 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
128 return NULL;
129 return register_names[reg_nr];
130}
131
132static char *
133sh_sh3e_register_name (int reg_nr)
134{
135 static char *register_names[] =
63978407 136 {
cc17453a
EZ		 137 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
138 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
139 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
140 "fpul", "fpscr",
141 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
142 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
143 "ssr", "spc",
144 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
145 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
146 };
147 if (reg_nr < 0)
148 return NULL;
149 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
150 return NULL;
151 return register_names[reg_nr];
152}
153
154static char *
155sh_sh_dsp_register_name (int reg_nr)
156{
157 static char *register_names[] =
c5aa993b 158 {
cc17453a
EZ		 159 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
160 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
161 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
162 "", "dsr",
163 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
164 "y0", "y1", "", "", "", "", "", "mod",
165 "", "",
166 "rs", "re", "", "", "", "", "", "",
167 "", "", "", "", "", "", "", "",
168 };
169 if (reg_nr < 0)
170 return NULL;
171 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
172 return NULL;
173 return register_names[reg_nr];
174}
175
176static char *
177sh_sh3_dsp_register_name (int reg_nr)
178{
179 static char *register_names[] =
c5aa993b 180 {
cc17453a
EZ		 181 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
182 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
183 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
184 "", "dsr",
185 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
186 "y0", "y1", "", "", "", "", "", "mod",
187 "ssr", "spc",
188 "rs", "re", "", "", "", "", "", "",
189 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b"
190 "", "", "", "", "", "", "", "",
191 };
192 if (reg_nr < 0)
193 return NULL;
194 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
195 return NULL;
196 return register_names[reg_nr];
197}
198
53116e27
EZ		 199static char *
200sh_sh4_register_name (int reg_nr)
201{
202 static char *register_names[] =
203 {
a38d2a54 204 /* general registers 0-15 */
53116e27
EZ		 205 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
206 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
a38d2a54 207 /* 16 - 22 */
53116e27 208 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
a38d2a54 209 /* 23, 24 */
53116e27 210 "fpul", "fpscr",
a38d2a54 211 /* floating point registers 25 - 40 */
53116e27
EZ		 212 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
213 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
a38d2a54 214 /* 41, 42 */
53116e27 215 "ssr", "spc",
a38d2a54 216 /* bank 0 43 - 50 */
53116e27 217 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
a38d2a54 218 /* bank 1 51 - 58 */
53116e27 219 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
a38d2a54 220 /* double precision (pseudo) 59 - 66 */
fe9f384f 221 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
a38d2a54 222 /* vectors (pseudo) 67 - 70 */
fe9f384f 223 "fv0", "fv4", "fv8", "fv12",
a38d2a54
EZ		 224 /* FIXME: missing XF 71 - 86 */
225 /* FIXME: missing XD 87 - 94 */
53116e27
EZ		 226 };
227 if (reg_nr < 0)
228 return NULL;
229 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
230 return NULL;
231 return register_names[reg_nr];
232}
233
cc17453a 234static unsigned char *
fba45db2 235sh_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
cc17453a
EZ		 236{
237 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */
238 static unsigned char breakpoint[] = {0xc3, 0xc3};
239
240 *lenptr = sizeof (breakpoint);
241 return breakpoint;
242}
c906108c
SS		 243
244/* Prologue looks like
c5aa993b
JM		 245 [mov.l <regs>,@-r15]...
246 [sts.l pr,@-r15]
247 [mov.l r14,@-r15]
248 [mov r15,r14]
8db62801
EZ		 249
250 Actually it can be more complicated than this. For instance, with
251 newer gcc's:
252
253 mov.l r14,@-r15
254 add #-12,r15
255 mov r15,r14
256 mov r4,r1
257 mov r5,r2
258 mov.l r6,@(4,r14)
259 mov.l r7,@(8,r14)
260 mov.b r1,@r14
261 mov r14,r1
262 mov r14,r1
263 add #2,r1
264 mov.w r2,@r1
265
c5aa993b 266 */
c906108c 267
8db62801
EZ		 268/* STS.L PR,@-r15 0100111100100010
269 r15-4-->r15, PR-->(r15) */
c906108c 270#define IS_STS(x) ((x) == 0x4f22)
8db62801
EZ		 271
272/* MOV.L Rm,@-r15 00101111mmmm0110
273 r15-4-->r15, Rm-->(R15) */
c906108c 274#define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
8db62801 275
c906108c 276#define GET_PUSHED_REG(x) (((x) >> 4) & 0xf)
8db62801
EZ		 277
278/* MOV r15,r14 0110111011110011
279 r15-->r14 */
c906108c 280#define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
8db62801
EZ		 281
282/* ADD #imm,r15 01111111iiiiiiii
283 r15+imm-->r15 */
c906108c 284#define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00)
8db62801 285
c906108c
SS		 286#define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
287#define IS_SHLL_R3(x) ((x) == 0x4300)
8db62801
EZ		 288
289/* ADD r3,r15 0011111100111100
290 r15+r3-->r15 */
c906108c 291#define IS_ADD_R3SP(x) ((x) == 0x3f3c)
8db62801
EZ		 292
293/* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
8db62801 294 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
8db62801 295 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
c906108c 296#define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b)
c906108c 297
8db62801 298/* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011
8db62801 299 MOV.L Rm,@(disp,Rn) Rm-->(dispx4+Rn) 0001nnnnmmmmdddd
8db62801
EZ		 300 MOV.L Rm,@Rn Rm-->(Rn) 0010nnnnmmmm0010
301 where Rm is one of r4,r5,r6,r7 which are the argument registers. */
302#define IS_ARG_MOV(x) \
303(((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) \
cc17453a
EZ		 304 || ((((x) & 0xf000) == 0x1000) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) \
305 || ((((x) & 0xf00f) == 0x2002) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)))
8db62801
EZ		 306
307/* MOV.L Rm,@(disp,r14) 00011110mmmmdddd
308 Rm-->(dispx4+r14) where Rm is one of r4,r5,r6,r7 */
3bbfbb92 309#define IS_MOV_TO_R14(x) \
cc17453a 310 ((((x) & 0xff00) == 0x1e) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070))
8db62801
EZ		 311
312#define FPSCR_SZ (1 << 20)
c906108c 313
c906108c
SS		 314/* Skip any prologue before the guts of a function */
315
8db62801
EZ		 316/* Skip the prologue using the debug information. If this fails we'll
317 fall back on the 'guess' method below. */
318static CORE_ADDR
fba45db2 319after_prologue (CORE_ADDR pc)
8db62801
EZ		 320{
321 struct symtab_and_line sal;
322 CORE_ADDR func_addr, func_end;
323
324 /* If we can not find the symbol in the partial symbol table, then
325 there is no hope we can determine the function's start address
326 with this code. */
327 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
328 return 0;
329
330 /* Get the line associated with FUNC_ADDR. */
331 sal = find_pc_line (func_addr, 0);
332
333 /* There are only two cases to consider. First, the end of the source line
334 is within the function bounds. In that case we return the end of the
335 source line. Second is the end of the source line extends beyond the
336 bounds of the current function. We need to use the slow code to
337 examine instructions in that case. */
338 if (sal.end < func_end)
339 return sal.end;
340 else
341 return 0;
342}
343
344/* Here we look at each instruction in the function, and try to guess
345 where the prologue ends. Unfortunately this is not always
346 accurate. */
347static CORE_ADDR
3bbfbb92 348sh_skip_prologue_hard_way (CORE_ADDR start_pc)
c906108c 349{
2bfa91ee 350 CORE_ADDR here, end;
8db62801 351 int updated_fp = 0;
2bfa91ee
EZ		 352
353 if (!start_pc)
354 return 0;
355
356 for (here = start_pc, end = start_pc + (2 * 28); here < end;)
c906108c 357 {
2bfa91ee
EZ		 358 int w = read_memory_integer (here, 2);
359 here += 2;
360 if (IS_FMOV (w) || IS_PUSH (w) || IS_STS (w) || IS_MOV_R3 (w)
8db62801 361 || IS_ADD_R3SP (w) || IS_ADD_SP (w) || IS_SHLL_R3 (w)
3bbfbb92 362 || IS_ARG_MOV (w) || IS_MOV_TO_R14 (w))
2bfa91ee
EZ		 363 {
364 start_pc = here;
2bfa91ee 365 }
8db62801
EZ		 366 else if (IS_MOV_SP_FP (w))
367 {
368 start_pc = here;
369 updated_fp = 1;
370 }
371 else
372 /* Don't bail out yet, if we are before the copy of sp. */
373 if (updated_fp)
374 break;
c906108c
SS		 375 }
376
377 return start_pc;
378}
379
cc17453a 380static CORE_ADDR
fba45db2 381sh_skip_prologue (CORE_ADDR pc)
8db62801
EZ		 382{
383 CORE_ADDR post_prologue_pc;
384
385 /* See if we can determine the end of the prologue via the symbol table.
386 If so, then return either PC, or the PC after the prologue, whichever
387 is greater. */
8db62801
EZ		 388 post_prologue_pc = after_prologue (pc);
389
390 /* If after_prologue returned a useful address, then use it. Else
391 fall back on the instruction skipping code. */
392 if (post_prologue_pc != 0)
393 return max (pc, post_prologue_pc);
394 else
395 return (skip_prologue_hard_way (pc));
396}
397
cc17453a
EZ		 398/* Immediately after a function call, return the saved pc.
399 Can't always go through the frames for this because on some machines
400 the new frame is not set up until the new function executes
401 some instructions.
402
403 The return address is the value saved in the PR register + 4 */
404static CORE_ADDR
fba45db2 405sh_saved_pc_after_call (struct frame_info *frame)
cc17453a 406{
3bbfbb92 407 return (ADDR_BITS_REMOVE (read_register (gdbarch_tdep (current_gdbarch)->PR_REGNUM)));
cc17453a
EZ		 408}
409
410/* Should call_function allocate stack space for a struct return? */
411static int
fba45db2 412sh_use_struct_convention (int gcc_p, struct type *type)
cc17453a
EZ		 413{
414 return (TYPE_LENGTH (type) > 1);
415}
416
417/* Store the address of the place in which to copy the structure the
418 subroutine will return. This is called from call_function.
419
3bbfbb92 420 We store structs through a pointer passed in R2 */
cc17453a 421static void
fba45db2 422sh_store_struct_return (CORE_ADDR addr, CORE_ADDR sp)
cc17453a
EZ		 423{
424 write_register (STRUCT_RETURN_REGNUM, (addr));
425}
c906108c 426
cc17453a
EZ		 427/* Disassemble an instruction. */
428static int
fba45db2 429gdb_print_insn_sh (bfd_vma memaddr, disassemble_info *info)
c906108c 430{
d7449b42 431 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
c906108c
SS		 432 return print_insn_sh (memaddr, info);
433 else
434 return print_insn_shl (memaddr, info);
435}
436
437/* Given a GDB frame, determine the address of the calling function's frame.
438 This will be used to create a new GDB frame struct, and then
439 INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame.
440
441 For us, the frame address is its stack pointer value, so we look up
442 the function prologue to determine the caller's sp value, and return it. */
cc17453a 443static CORE_ADDR
fba45db2 444sh_frame_chain (struct frame_info *frame)
c906108c
SS		 445{
446 if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame))
447 return frame->frame; /* dummy frame same as caller's frame */
2bfa91ee 448 if (frame->pc && !inside_entry_file (frame->pc))
cc17453a 449 return read_memory_integer (FRAME_FP (frame) + frame->extra_info->f_offset, 4);
c906108c
SS		 450 else
451 return 0;
452}
453
454/* Find REGNUM on the stack. Otherwise, it's in an active register. One thing
455 we might want to do here is to check REGNUM against the clobber mask, and
456 somehow flag it as invalid if it isn't saved on the stack somewhere. This
457 would provide a graceful failure mode when trying to get the value of
458 caller-saves registers for an inner frame. */
cc17453a 459static CORE_ADDR
fba45db2 460sh_find_callers_reg (struct frame_info *fi, int regnum)
c906108c 461{
c906108c
SS		 462 for (; fi; fi = fi->next)
463 if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
464 /* When the caller requests PR from the dummy frame, we return PC because
c5aa993b 465 that's where the previous routine appears to have done a call from. */
c906108c 466 return generic_read_register_dummy (fi->pc, fi->frame, regnum);
c5aa993b 467 else
c906108c 468 {
cc17453a 469 FRAME_INIT_SAVED_REGS (fi);
2bfa91ee
EZ		 470 if (!fi->pc)
471 return 0;
cc17453a
EZ		 472 if (fi->saved_regs[regnum] != 0)
473 return read_memory_integer (fi->saved_regs[regnum],
c5aa993b 474 REGISTER_RAW_SIZE (regnum));
c906108c
SS		 475 }
476 return read_register (regnum);
477}
478
479/* Put here the code to store, into a struct frame_saved_regs, the
480 addresses of the saved registers of frame described by FRAME_INFO.
481 This includes special registers such as pc and fp saved in special
482 ways in the stack frame. sp is even more special: the address we
483 return for it IS the sp for the next frame. */
cc17453a 484static void
fba45db2 485sh_nofp_frame_init_saved_regs (struct frame_info *fi)
c906108c
SS		 486{
487 int where[NUM_REGS];
488 int rn;
489 int have_fp = 0;
490 int depth;
491 int pc;
492 int opc;
493 int insn;
494 int r3_val = 0;
c5aa993b 495 char *dummy_regs = generic_find_dummy_frame (fi->pc, fi->frame);
cc17453a
EZ		 496
497 if (fi->saved_regs == NULL)
498 frame_saved_regs_zalloc (fi);
499 else
500 memset (fi->saved_regs, 0, SIZEOF_FRAME_SAVED_REGS);
501
502 if (dummy_regs)
503 {
504 /* DANGER! This is ONLY going to work if the char buffer format of
505 the saved registers is byte-for-byte identical to the
506 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
507 memcpy (fi->saved_regs, dummy_regs, sizeof (fi->saved_regs));
508 return;
509 }
510
511 fi->extra_info->leaf_function = 1;
512 fi->extra_info->f_offset = 0;
513
514 for (rn = 0; rn < NUM_REGS; rn++)
515 where[rn] = -1;
516
517 depth = 0;
518
519 /* Loop around examining the prologue insns until we find something
520 that does not appear to be part of the prologue. But give up
521 after 20 of them, since we're getting silly then. */
522
523 pc = get_pc_function_start (fi->pc);
524 if (!pc)
525 {
526 fi->pc = 0;
527 return;
528 }
529
530 for (opc = pc + (2 * 28); pc < opc; pc += 2)
531 {
532 insn = read_memory_integer (pc, 2);
533 /* See where the registers will be saved to */
534 if (IS_PUSH (insn))
535 {
536 rn = GET_PUSHED_REG (insn);
537 where[rn] = depth;
538 depth += 4;
539 }
540 else if (IS_STS (insn))
541 {
3bbfbb92 542 where[gdbarch_tdep (current_gdbarch)->PR_REGNUM] = depth;
cc17453a
EZ		 543 /* If we're storing the pr then this isn't a leaf */
544 fi->extra_info->leaf_function = 0;
545 depth += 4;
546 }
547 else if (IS_MOV_R3 (insn))
548 {
549 r3_val = ((insn & 0xff) ^ 0x80) - 0x80;
550 }
551 else if (IS_SHLL_R3 (insn))
552 {
553 r3_val <<= 1;
554 }
555 else if (IS_ADD_R3SP (insn))
556 {
557 depth += -r3_val;
558 }
559 else if (IS_ADD_SP (insn))
560 {
561 depth -= ((insn & 0xff) ^ 0x80) - 0x80;
562 }
563 else if (IS_MOV_SP_FP (insn))
564 break;
565#if 0 /* This used to just stop when it found an instruction that
566 was not considered part of the prologue. Now, we just
567 keep going looking for likely instructions. */
568 else
569 break;
570#endif
571 }
572
573 /* Now we know how deep things are, we can work out their addresses */
574
575 for (rn = 0; rn < NUM_REGS; rn++)
576 {
577 if (where[rn] >= 0)
578 {
579 if (rn == FP_REGNUM)
580 have_fp = 1;
c906108c 581
cc17453a
EZ		 582 fi->saved_regs[rn] = fi->frame - where[rn] + depth - 4;
583 }
584 else
585 {
586 fi->saved_regs[rn] = 0;
587 }
588 }
589
590 if (have_fp)
591 {
592 fi->saved_regs[SP_REGNUM] = read_memory_integer (fi->saved_regs[FP_REGNUM], 4);
593 }
594 else
595 {
596 fi->saved_regs[SP_REGNUM] = fi->frame - 4;
597 }
598
599 fi->extra_info->f_offset = depth - where[FP_REGNUM] - 4;
600 /* Work out the return pc - either from the saved pr or the pr
601 value */
602}
603
3bbfbb92
EZ		 604/* For vectors of 4 floating point registers. */
605static int
606fv_reg_base_num (int fv_regnum)
607{
608 int fp_regnum;
609
610 fp_regnum = FP0_REGNUM +
611 (fv_regnum - gdbarch_tdep (current_gdbarch)->FV0_REGNUM) * 4;
612 return fp_regnum;
613}
614
615/* For double precision floating point registers, i.e 2 fp regs.*/
616static int
617dr_reg_base_num (int dr_regnum)
618{
619 int fp_regnum;
620
621 fp_regnum = FP0_REGNUM +
622 (dr_regnum - gdbarch_tdep (current_gdbarch)->DR0_REGNUM) * 2;
623 return fp_regnum;
624}
625
cc17453a 626static void
fba45db2 627sh_fp_frame_init_saved_regs (struct frame_info *fi)
cc17453a
EZ		 628{
629 int where[NUM_REGS];
630 int rn;
631 int have_fp = 0;
632 int depth;
633 int pc;
634 int opc;
635 int insn;
636 int r3_val = 0;
637 char *dummy_regs = generic_find_dummy_frame (fi->pc, fi->frame);
f81353e4 638 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
cc17453a
EZ		 639
640 if (fi->saved_regs == NULL)
641 frame_saved_regs_zalloc (fi);
642 else
643 memset (fi->saved_regs, 0, SIZEOF_FRAME_SAVED_REGS);
644
c906108c
SS		 645 if (dummy_regs)
646 {
647 /* DANGER! This is ONLY going to work if the char buffer format of
c5aa993b
JM		 648 the saved registers is byte-for-byte identical to the
649 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
cc17453a 650 memcpy (fi->saved_regs, dummy_regs, sizeof (fi->saved_regs));
c906108c
SS		 651 return;
652 }
653
cc17453a
EZ		 654 fi->extra_info->leaf_function = 1;
655 fi->extra_info->f_offset = 0;
c906108c
SS		 656
657 for (rn = 0; rn < NUM_REGS; rn++)
658 where[rn] = -1;
659
660 depth = 0;
661
662 /* Loop around examining the prologue insns until we find something
663 that does not appear to be part of the prologue. But give up
664 after 20 of them, since we're getting silly then. */
665
2bfa91ee
EZ		 666 pc = get_pc_function_start (fi->pc);
667 if (!pc)
c906108c 668 {
2bfa91ee
EZ		 669 fi->pc = 0;
670 return;
671 }
672
673 for (opc = pc + (2 * 28); pc < opc; pc += 2)
674 {
675 insn = read_memory_integer (pc, 2);
c906108c
SS		 676 /* See where the registers will be saved to */
677 if (IS_PUSH (insn))
678 {
c906108c
SS		 679 rn = GET_PUSHED_REG (insn);
680 where[rn] = depth;
c906108c
SS		 681 depth += 4;
682 }
683 else if (IS_STS (insn))
684 {
f81353e4 685 where[tdep->PR_REGNUM] = depth;
c906108c 686 /* If we're storing the pr then this isn't a leaf */
cc17453a 687 fi->extra_info->leaf_function = 0;
c906108c
SS		 688 depth += 4;
689 }
690 else if (IS_MOV_R3 (insn))
691 {
692 r3_val = ((insn & 0xff) ^ 0x80) - 0x80;
c906108c
SS		 693 }
694 else if (IS_SHLL_R3 (insn))
695 {
696 r3_val <<= 1;
c906108c
SS		 697 }
698 else if (IS_ADD_R3SP (insn))
699 {
700 depth += -r3_val;
c906108c
SS		 701 }
702 else if (IS_ADD_SP (insn))
703 {
c906108c 704 depth -= ((insn & 0xff) ^ 0x80) - 0x80;
c906108c
SS		 705 }
706 else if (IS_FMOV (insn))
707 {
f81353e4 708 if (read_register (tdep->FPSCR_REGNUM) & FPSCR_SZ)
c906108c
SS		 709 {
710 depth += 8;
711 }
712 else
713 {
714 depth += 4;
715 }
716 }
2bfa91ee
EZ		 717 else if (IS_MOV_SP_FP (insn))
718 break;
719#if 0 /* This used to just stop when it found an instruction that
720 was not considered part of the prologue. Now, we just
721 keep going looking for likely instructions. */
c906108c
SS		 722 else
723 break;
2bfa91ee 724#endif
c906108c
SS		 725 }
726
727 /* Now we know how deep things are, we can work out their addresses */
728
729 for (rn = 0; rn < NUM_REGS; rn++)
730 {
731 if (where[rn] >= 0)
732 {
733 if (rn == FP_REGNUM)
734 have_fp = 1;
735
cc17453a 736 fi->saved_regs[rn] = fi->frame - where[rn] + depth - 4;
c906108c
SS		 737 }
738 else
739 {
cc17453a 740 fi->saved_regs[rn] = 0;
c906108c
SS		 741 }
742 }
743
744 if (have_fp)
745 {
cc17453a 746 fi->saved_regs[SP_REGNUM] = read_memory_integer (fi->saved_regs[FP_REGNUM], 4);
c906108c
SS		 747 }
748 else
749 {
cc17453a 750 fi->saved_regs[SP_REGNUM] = fi->frame - 4;
c906108c
SS		 751 }
752
cc17453a 753 fi->extra_info->f_offset = depth - where[FP_REGNUM] - 4;
c906108c
SS		 754 /* Work out the return pc - either from the saved pr or the pr
755 value */
756}
757
cc17453a
EZ		 758/* Initialize the extra info saved in a FRAME */
759static void
fba45db2 760sh_init_extra_frame_info (int fromleaf, struct frame_info *fi)
c906108c 761{
cc17453a
EZ		 762
763 fi->extra_info = (struct frame_extra_info *)
764 frame_obstack_alloc (sizeof (struct frame_extra_info));
c906108c
SS		 765
766 if (fi->next)
767 fi->pc = FRAME_SAVED_PC (fi->next);
768
769 if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
770 {
771 /* We need to setup fi->frame here because run_stack_dummy gets it wrong
c5aa993b
JM		 772 by assuming it's always FP. */
773 fi->frame = generic_read_register_dummy (fi->pc, fi->frame,
774 SP_REGNUM);
cc17453a
EZ		 775 fi->extra_info->return_pc = generic_read_register_dummy (fi->pc, fi->frame,
776 PC_REGNUM);
777 fi->extra_info->f_offset = -(CALL_DUMMY_LENGTH + 4);
778 fi->extra_info->leaf_function = 0;
c906108c
SS		 779 return;
780 }
781 else
782 {
cc17453a 783 FRAME_INIT_SAVED_REGS (fi);
3bbfbb92 784 fi->extra_info->return_pc = sh_find_callers_reg (fi, gdbarch_tdep (current_gdbarch)->PR_REGNUM);
c906108c
SS		 785 }
786}
787
cc17453a
EZ		 788/* Extract from an array REGBUF containing the (raw) register state
789 the address in which a function should return its structure value,
790 as a CORE_ADDR (or an expression that can be used as one). */
b3df3fff 791static CORE_ADDR
0c8053b6 792sh_extract_struct_value_address (char *regbuf)
cc17453a
EZ		 793{
794 return (extract_address ((regbuf), REGISTER_RAW_SIZE (0)));
795}
796
797static CORE_ADDR
fba45db2 798sh_frame_saved_pc (struct frame_info *frame)
cc17453a
EZ		 799{
800 return ((frame)->extra_info->return_pc);
801}
802
c906108c
SS		 803/* Discard from the stack the innermost frame,
804 restoring all saved registers. */
cc17453a 805static void
fba45db2 806sh_pop_frame (void)
c906108c
SS		 807{
808 register struct frame_info *frame = get_current_frame ();
809 register CORE_ADDR fp;
810 register int regnum;
c906108c
SS		 811
812 if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame))
813 generic_pop_dummy_frame ();
814 else
c5aa993b
JM		 815 {
816 fp = FRAME_FP (frame);
cc17453a 817 FRAME_INIT_SAVED_REGS (frame);
c906108c 818
c5aa993b
JM		 819 /* Copy regs from where they were saved in the frame */
820 for (regnum = 0; regnum < NUM_REGS; regnum++)
cc17453a
EZ		 821 if (frame->saved_regs[regnum])
822 write_register (regnum, read_memory_integer (frame->saved_regs[regnum], 4));
c906108c 823
cc17453a 824 write_register (PC_REGNUM, frame->extra_info->return_pc);
c5aa993b
JM		 825 write_register (SP_REGNUM, fp + 4);
826 }
c906108c
SS		 827 flush_cached_frames ();
828}
829
830/* Function: push_arguments
831 Setup the function arguments for calling a function in the inferior.
832
833 On the Hitachi SH architecture, there are four registers (R4 to R7)
834 which are dedicated for passing function arguments. Up to the first
835 four arguments (depending on size) may go into these registers.
836 The rest go on the stack.
837
838 Arguments that are smaller than 4 bytes will still take up a whole
839 register or a whole 32-bit word on the stack, and will be
840 right-justified in the register or the stack word. This includes
841 chars, shorts, and small aggregate types.
842
843 Arguments that are larger than 4 bytes may be split between two or
844 more registers. If there are not enough registers free, an argument
845 may be passed partly in a register (or registers), and partly on the
846 stack. This includes doubles, long longs, and larger aggregates.
847 As far as I know, there is no upper limit to the size of aggregates
848 that will be passed in this way; in other words, the convention of
849 passing a pointer to a large aggregate instead of a copy is not used.
850
851 An exceptional case exists for struct arguments (and possibly other
852 aggregates such as arrays) if the size is larger than 4 bytes but
853 not a multiple of 4 bytes. In this case the argument is never split
854 between the registers and the stack, but instead is copied in its
855 entirety onto the stack, AND also copied into as many registers as
856 there is room for. In other words, space in registers permitting,
857 two copies of the same argument are passed in. As far as I can tell,
858 only the one on the stack is used, although that may be a function
859 of the level of compiler optimization. I suspect this is a compiler
860 bug. Arguments of these odd sizes are left-justified within the
861 word (as opposed to arguments smaller than 4 bytes, which are
862 right-justified).
c5aa993b 863
c906108c
SS		 864 If the function is to return an aggregate type such as a struct, it
865 is either returned in the normal return value register R0 (if its
866 size is no greater than one byte), or else the caller must allocate
867 space into which the callee will copy the return value (if the size
868 is greater than one byte). In this case, a pointer to the return
869 value location is passed into the callee in register R2, which does
870 not displace any of the other arguments passed in via registers R4
871 to R7. */
872
cc17453a 873static CORE_ADDR
34e9d9bb 874sh_push_arguments (int nargs, struct value **args, CORE_ADDR sp,
3bbfbb92 875 int struct_return, CORE_ADDR struct_addr)
c906108c
SS		 876{
877 int stack_offset, stack_alloc;
878 int argreg;
879 int argnum;
880 struct type *type;
881 CORE_ADDR regval;
882 char *val;
883 char valbuf[4];
884 int len;
885 int odd_sized_struct;
f81353e4 886 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
c906108c
SS		 887
888 /* first force sp to a 4-byte alignment */
889 sp = sp & ~3;
890
891 /* The "struct return pointer" pseudo-argument has its own dedicated
892 register */
893 if (struct_return)
c5aa993b 894 write_register (STRUCT_RETURN_REGNUM, struct_addr);
c906108c
SS		 895
896 /* Now make sure there's space on the stack */
cc17453a 897 for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++)
c5aa993b
JM		 898 stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 3) & ~3);
899 sp -= stack_alloc; /* make room on stack for args */
c906108c 900
c906108c
SS		 901 /* Now load as many as possible of the first arguments into
902 registers, and push the rest onto the stack. There are 16 bytes
903 in four registers available. Loop thru args from first to last. */
904
f81353e4 905 argreg = tdep->ARG0_REGNUM;
c906108c
SS		 906 for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
907 {
908 type = VALUE_TYPE (args[argnum]);
c5aa993b
JM		 909 len = TYPE_LENGTH (type);
910 memset (valbuf, 0, sizeof (valbuf));
c906108c 911 if (len < 4)
cc17453a
EZ		 912 {
913 /* value gets right-justified in the register or stack word */
c5aa993b
JM		 914 memcpy (valbuf + (4 - len),
915 (char *) VALUE_CONTENTS (args[argnum]), len);
916 val = valbuf;
917 }
c906108c 918 else
c5aa993b 919 val = (char *) VALUE_CONTENTS (args[argnum]);
c906108c
SS		 920
921 if (len > 4 && (len & 3) != 0)
c5aa993b
JM		 922 odd_sized_struct = 1; /* such structs go entirely on stack */
923 else
c906108c
SS		 924 odd_sized_struct = 0;
925 while (len > 0)
926 {
f81353e4 927 if (argreg > tdep->ARGLAST_REGNUM
3bbfbb92
EZ		 928 || odd_sized_struct)
929 {
930 /* must go on the stack */
c906108c
SS		 931 write_memory (sp + stack_offset, val, 4);
932 stack_offset += 4;
933 }
934 /* NOTE WELL!!!!! This is not an "else if" clause!!!
935 That's because some *&^%$ things get passed on the stack
936 AND in the registers! */
f81353e4 937 if (argreg <= tdep->ARGLAST_REGNUM)
3bbfbb92
EZ		 938 {
939 /* there's room in a register */
c5aa993b 940 regval = extract_address (val, REGISTER_RAW_SIZE (argreg));
c906108c
SS		 941 write_register (argreg++, regval);
942 }
943 /* Store the value 4 bytes at a time. This means that things
944 larger than 4 bytes may go partly in registers and partly
945 on the stack. */
c5aa993b
JM		 946 len -= REGISTER_RAW_SIZE (argreg);
947 val += REGISTER_RAW_SIZE (argreg);
c906108c
SS		 948 }
949 }
950 return sp;
951}
952
953/* Function: push_return_address (pc)
954 Set up the return address for the inferior function call.
955 Needed for targets where we don't actually execute a JSR/BSR instruction */
956
cc17453a 957static CORE_ADDR
fba45db2 958sh_push_return_address (CORE_ADDR pc, CORE_ADDR sp)
c906108c 959{
3bbfbb92 960 write_register (gdbarch_tdep (current_gdbarch)->PR_REGNUM, CALL_DUMMY_ADDRESS ());
c906108c
SS		 961 return sp;
962}
963
964/* Function: fix_call_dummy
965 Poke the callee function's address into the destination part of
966 the CALL_DUMMY. The address is actually stored in a data word
967 following the actualy CALL_DUMMY instructions, which will load
968 it into a register using PC-relative addressing. This function
969 expects the CALL_DUMMY to look like this:
970
c5aa993b
JM		 971 mov.w @(2,PC), R8
972 jsr @R8
973 nop
974 trap
975 <destination>
976 */
c906108c
SS		 977
978#if 0
979void
fba45db2 980sh_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, int nargs,
ea7c478f 981 struct value **args, struct type *type, int gcc_p)
c906108c
SS		 982{
983 *(unsigned long *) (dummy + 8) = fun;
984}
985#endif
986
cc17453a
EZ		 987static int
988sh_coerce_float_to_double (struct type *formal, struct type *actual)
989{
990 return 1;
991}
c906108c 992
cc17453a
EZ		 993/* Find a function's return value in the appropriate registers (in
994 regbuf), and copy it into valbuf. Extract from an array REGBUF
995 containing the (raw) register state a function return value of type
996 TYPE, and copy that, in virtual format, into VALBUF. */
997static void
fba45db2 998sh_extract_return_value (struct type *type, char *regbuf, char *valbuf)
c906108c 999{
cc17453a 1000 int len = TYPE_LENGTH (type);
3116c80a
EZ		 1001 int return_register = R0_REGNUM;
1002 int offset;
1003
cc17453a 1004 if (len <= 4)
3116c80a 1005 {
d7449b42 1006 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3116c80a
EZ		 1007 offset = REGISTER_BYTE (return_register) + 4 - len;
1008 else
1009 offset = REGISTER_BYTE (return_register);
1010 memcpy (valbuf, regbuf + offset, len);
1011 }
cc17453a 1012 else if (len <= 8)
3116c80a 1013 {
d7449b42 1014 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3116c80a
EZ		 1015 offset = REGISTER_BYTE (return_register) + 8 - len;
1016 else
1017 offset = REGISTER_BYTE (return_register);
1018 memcpy (valbuf, regbuf + offset, len);
1019 }
1020 else
1021 error ("bad size for return value");
1022}
1023
1024static void
1025sh3e_sh4_extract_return_value (struct type *type, char *regbuf, char *valbuf)
1026{
1027 int return_register;
1028 int offset;
1029 int len = TYPE_LENGTH (type);
1030
1031 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1032 return_register = FP0_REGNUM;
1033 else
1034 return_register = R0_REGNUM;
1035
1036 if (len == 8 && TYPE_CODE (type) == TYPE_CODE_FLT)
1037 {
1038 DOUBLEST val;
778eb05e 1039 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
3116c80a
EZ		 1040 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
1041 (char *) regbuf + REGISTER_BYTE (return_register),
1042 &val);
1043 else
1044 floatformat_to_doublest (&floatformat_ieee_double_big,
1045 (char *) regbuf + REGISTER_BYTE (return_register),
1046 &val);
1047 store_floating (valbuf, len, val);
1048 }
1049 else if (len <= 4)
1050 {
d7449b42 1051 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3116c80a
EZ		 1052 offset = REGISTER_BYTE (return_register) + 4 - len;
1053 else
1054 offset = REGISTER_BYTE (return_register);
1055 memcpy (valbuf, regbuf + offset, len);
1056 }
1057 else if (len <= 8)
1058 {
d7449b42 1059 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3116c80a
EZ		 1060 offset = REGISTER_BYTE (return_register) + 8 - len;
1061 else
1062 offset = REGISTER_BYTE (return_register);
1063 memcpy (valbuf, regbuf + offset, len);
1064 }
cc17453a
EZ		 1065 else
1066 error ("bad size for return value");
1067}
c906108c 1068
cc17453a
EZ		 1069/* Write into appropriate registers a function return value
1070 of type TYPE, given in virtual format.
1071 If the architecture is sh4 or sh3e, store a function's return value
1072 in the R0 general register or in the FP0 floating point register,
1073 depending on the type of the return value. In all the other cases
3bbfbb92 1074 the result is stored in r0, left-justified. */
cc17453a
EZ		 1075static void
1076sh_default_store_return_value (struct type *type, char *valbuf)
1077{
d19b71be
MS		 1078 char buf[32]; /* more than enough... */
1079
1080 if (TYPE_LENGTH (type) < REGISTER_RAW_SIZE (R0_REGNUM))
1081 {
1082 /* Add leading zeros to the value. */
1083 memset (buf, 0, REGISTER_RAW_SIZE (R0_REGNUM));
1084 memcpy (buf + REGISTER_RAW_SIZE (R0_REGNUM) - TYPE_LENGTH (type),
1085 valbuf, TYPE_LENGTH (type));
1086 write_register_bytes (REGISTER_BYTE (R0_REGNUM), buf,
1087 REGISTER_RAW_SIZE (R0_REGNUM));
1088 }
1089 else
1090 write_register_bytes (REGISTER_BYTE (R0_REGNUM), valbuf,
1091 TYPE_LENGTH (type));
cc17453a 1092}
c906108c 1093
cc17453a
EZ		 1094static void
1095sh3e_sh4_store_return_value (struct type *type, char *valbuf)
1096{
1097 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1098 write_register_bytes (REGISTER_BYTE (FP0_REGNUM),
1099 valbuf, TYPE_LENGTH (type));
1100 else
d19b71be 1101 sh_default_store_return_value (type, valbuf);
c906108c
SS		 1102}
1103
1104/* Print the registers in a form similar to the E7000 */
1105
1106static void
fba45db2 1107sh_generic_show_regs (void)
c906108c 1108{
f81353e4
EZ		 1109 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1110
cc17453a
EZ		 1111 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1112 paddr (read_register (PC_REGNUM)),
f81353e4
EZ		 1113 (long) read_register (tdep->SR_REGNUM),
1114 (long) read_register (tdep->PR_REGNUM),
cc17453a
EZ		 1115 (long) read_register (MACH_REGNUM),
1116 (long) read_register (MACL_REGNUM));
1117
1118 printf_filtered ("GBR=%08lx VBR=%08lx",
1119 (long) read_register (GBR_REGNUM),
1120 (long) read_register (VBR_REGNUM));
1121
1122 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1123 (long) read_register (0),
1124 (long) read_register (1),
1125 (long) read_register (2),
1126 (long) read_register (3),
1127 (long) read_register (4),
1128 (long) read_register (5),
1129 (long) read_register (6),
1130 (long) read_register (7));
1131 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1132 (long) read_register (8),
1133 (long) read_register (9),
1134 (long) read_register (10),
1135 (long) read_register (11),
1136 (long) read_register (12),
1137 (long) read_register (13),
1138 (long) read_register (14),
1139 (long) read_register (15));
1140}
c906108c 1141
cc17453a 1142static void
fba45db2 1143sh3_show_regs (void)
cc17453a 1144{
f81353e4
EZ		 1145 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1146
d4f3574e
SS		 1147 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1148 paddr (read_register (PC_REGNUM)),
f81353e4
EZ		 1149 (long) read_register (tdep->SR_REGNUM),
1150 (long) read_register (tdep->PR_REGNUM),
d4f3574e
SS		 1151 (long) read_register (MACH_REGNUM),
1152 (long) read_register (MACL_REGNUM));
1153
1154 printf_filtered ("GBR=%08lx VBR=%08lx",
1155 (long) read_register (GBR_REGNUM),
1156 (long) read_register (VBR_REGNUM));
cc17453a 1157 printf_filtered (" SSR=%08lx SPC=%08lx",
f81353e4
EZ		 1158 (long) read_register (tdep->SSR_REGNUM),
1159 (long) read_register (tdep->SPC_REGNUM));
c906108c 1160
d4f3574e
SS		 1161 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1162 (long) read_register (0),
1163 (long) read_register (1),
1164 (long) read_register (2),
1165 (long) read_register (3),
1166 (long) read_register (4),
1167 (long) read_register (5),
1168 (long) read_register (6),
1169 (long) read_register (7));
1170 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1171 (long) read_register (8),
1172 (long) read_register (9),
1173 (long) read_register (10),
1174 (long) read_register (11),
1175 (long) read_register (12),
1176 (long) read_register (13),
1177 (long) read_register (14),
1178 (long) read_register (15));
c906108c
SS		 1179}
1180
53116e27 1181
cc17453a 1182static void
fba45db2 1183sh3e_show_regs (void)
cc17453a 1184{
f81353e4
EZ		 1185 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1186
cc17453a
EZ		 1187 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1188 paddr (read_register (PC_REGNUM)),
f81353e4
EZ		 1189 (long) read_register (tdep->SR_REGNUM),
1190 (long) read_register (tdep->PR_REGNUM),
cc17453a
EZ		 1191 (long) read_register (MACH_REGNUM),
1192 (long) read_register (MACL_REGNUM));
1193
1194 printf_filtered ("GBR=%08lx VBR=%08lx",
1195 (long) read_register (GBR_REGNUM),
1196 (long) read_register (VBR_REGNUM));
1197 printf_filtered (" SSR=%08lx SPC=%08lx",
f81353e4
EZ		 1198 (long) read_register (tdep->SSR_REGNUM),
1199 (long) read_register (tdep->SPC_REGNUM));
cc17453a 1200 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
f81353e4
EZ		 1201 (long) read_register (tdep->FPUL_REGNUM),
1202 (long) read_register (tdep->FPSCR_REGNUM));
c906108c 1203
cc17453a
EZ		 1204 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1205 (long) read_register (0),
1206 (long) read_register (1),
1207 (long) read_register (2),
1208 (long) read_register (3),
1209 (long) read_register (4),
1210 (long) read_register (5),
1211 (long) read_register (6),
1212 (long) read_register (7));
1213 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1214 (long) read_register (8),
1215 (long) read_register (9),
1216 (long) read_register (10),
1217 (long) read_register (11),
1218 (long) read_register (12),
1219 (long) read_register (13),
1220 (long) read_register (14),
1221 (long) read_register (15));
1222
1223 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1224 (long) read_register (FP0_REGNUM + 0),
1225 (long) read_register (FP0_REGNUM + 1),
1226 (long) read_register (FP0_REGNUM + 2),
1227 (long) read_register (FP0_REGNUM + 3),
1228 (long) read_register (FP0_REGNUM + 4),
1229 (long) read_register (FP0_REGNUM + 5),
1230 (long) read_register (FP0_REGNUM + 6),
1231 (long) read_register (FP0_REGNUM + 7));
1232 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1233 (long) read_register (FP0_REGNUM + 8),
1234 (long) read_register (FP0_REGNUM + 9),
1235 (long) read_register (FP0_REGNUM + 10),
1236 (long) read_register (FP0_REGNUM + 11),
1237 (long) read_register (FP0_REGNUM + 12),
1238 (long) read_register (FP0_REGNUM + 13),
1239 (long) read_register (FP0_REGNUM + 14),
1240 (long) read_register (FP0_REGNUM + 15));
1241}
1242
1243static void
fba45db2 1244sh3_dsp_show_regs (void)
c906108c 1245{
f81353e4
EZ		 1246 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1247
cc17453a
EZ		 1248 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1249 paddr (read_register (PC_REGNUM)),
f81353e4
EZ		 1250 (long) read_register (tdep->SR_REGNUM),
1251 (long) read_register (tdep->PR_REGNUM),
cc17453a
EZ		 1252 (long) read_register (MACH_REGNUM),
1253 (long) read_register (MACL_REGNUM));
c906108c 1254
cc17453a
EZ		 1255 printf_filtered ("GBR=%08lx VBR=%08lx",
1256 (long) read_register (GBR_REGNUM),
1257 (long) read_register (VBR_REGNUM));
1258
1259 printf_filtered (" SSR=%08lx SPC=%08lx",
f81353e4
EZ		 1260 (long) read_register (tdep->SSR_REGNUM),
1261 (long) read_register (tdep->SPC_REGNUM));
cc17453a
EZ		 1262
1263 printf_filtered (" DSR=%08lx",
f81353e4 1264 (long) read_register (tdep->DSR_REGNUM));
cc17453a
EZ		 1265
1266 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1267 (long) read_register (0),
1268 (long) read_register (1),
1269 (long) read_register (2),
1270 (long) read_register (3),
1271 (long) read_register (4),
1272 (long) read_register (5),
1273 (long) read_register (6),
1274 (long) read_register (7));
1275 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1276 (long) read_register (8),
1277 (long) read_register (9),
1278 (long) read_register (10),
1279 (long) read_register (11),
1280 (long) read_register (12),
1281 (long) read_register (13),
1282 (long) read_register (14),
1283 (long) read_register (15));
1284
1285 printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
f81353e4
EZ		 1286 (long) read_register (tdep->A0G_REGNUM) & 0xff,
1287 (long) read_register (tdep->A0_REGNUM),
1288 (long) read_register (tdep->M0_REGNUM),
1289 (long) read_register (tdep->X0_REGNUM),
1290 (long) read_register (tdep->Y0_REGNUM),
1291 (long) read_register (tdep->RS_REGNUM),
1292 (long) read_register (tdep->MOD_REGNUM));
cc17453a 1293 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
f81353e4
EZ		 1294 (long) read_register (tdep->A1G_REGNUM) & 0xff,
1295 (long) read_register (tdep->A1_REGNUM),
1296 (long) read_register (tdep->M1_REGNUM),
1297 (long) read_register (tdep->X1_REGNUM),
1298 (long) read_register (tdep->Y1_REGNUM),
1299 (long) read_register (tdep->RE_REGNUM));
c906108c
SS		 1300}
1301
cc17453a 1302static void
fba45db2 1303sh4_show_regs (void)
cc17453a 1304{
f81353e4
EZ		 1305 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1306
1307 int pr = read_register (tdep->FPSCR_REGNUM) & 0x80000;
cc17453a
EZ		 1308 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1309 paddr (read_register (PC_REGNUM)),
f81353e4
EZ		 1310 (long) read_register (tdep->SR_REGNUM),
1311 (long) read_register (tdep->PR_REGNUM),
cc17453a
EZ		 1312 (long) read_register (MACH_REGNUM),
1313 (long) read_register (MACL_REGNUM));
1314
1315 printf_filtered ("GBR=%08lx VBR=%08lx",
1316 (long) read_register (GBR_REGNUM),
1317 (long) read_register (VBR_REGNUM));
1318 printf_filtered (" SSR=%08lx SPC=%08lx",
f81353e4
EZ		 1319 (long) read_register (tdep->SSR_REGNUM),
1320 (long) read_register (tdep->SPC_REGNUM));
cc17453a 1321 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
f81353e4
EZ		 1322 (long) read_register (tdep->FPUL_REGNUM),
1323 (long) read_register (tdep->FPSCR_REGNUM));
cc17453a
EZ		 1324
1325 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1326 (long) read_register (0),
1327 (long) read_register (1),
1328 (long) read_register (2),
1329 (long) read_register (3),
1330 (long) read_register (4),
1331 (long) read_register (5),
1332 (long) read_register (6),
1333 (long) read_register (7));
1334 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1335 (long) read_register (8),
1336 (long) read_register (9),
1337 (long) read_register (10),
1338 (long) read_register (11),
1339 (long) read_register (12),
1340 (long) read_register (13),
1341 (long) read_register (14),
1342 (long) read_register (15));
1343
1344 printf_filtered ((pr
1345 ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1346 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1347 (long) read_register (FP0_REGNUM + 0),
1348 (long) read_register (FP0_REGNUM + 1),
1349 (long) read_register (FP0_REGNUM + 2),
1350 (long) read_register (FP0_REGNUM + 3),
1351 (long) read_register (FP0_REGNUM + 4),
1352 (long) read_register (FP0_REGNUM + 5),
1353 (long) read_register (FP0_REGNUM + 6),
1354 (long) read_register (FP0_REGNUM + 7));
1355 printf_filtered ((pr
1356 ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1357 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1358 (long) read_register (FP0_REGNUM + 8),
1359 (long) read_register (FP0_REGNUM + 9),
1360 (long) read_register (FP0_REGNUM + 10),
1361 (long) read_register (FP0_REGNUM + 11),
1362 (long) read_register (FP0_REGNUM + 12),
1363 (long) read_register (FP0_REGNUM + 13),
1364 (long) read_register (FP0_REGNUM + 14),
1365 (long) read_register (FP0_REGNUM + 15));
1366}
1367
1368static void
fba45db2 1369sh_dsp_show_regs (void)
cc17453a 1370{
f81353e4
EZ		 1371 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1372
cc17453a
EZ		 1373 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1374 paddr (read_register (PC_REGNUM)),
f81353e4
EZ		 1375 (long) read_register (tdep->SR_REGNUM),
1376 (long) read_register (tdep->PR_REGNUM),
cc17453a
EZ		 1377 (long) read_register (MACH_REGNUM),
1378 (long) read_register (MACL_REGNUM));
1379
1380 printf_filtered ("GBR=%08lx VBR=%08lx",
1381 (long) read_register (GBR_REGNUM),
1382 (long) read_register (VBR_REGNUM));
1383
1384 printf_filtered (" DSR=%08lx",
f81353e4 1385 (long) read_register (tdep->DSR_REGNUM));
cc17453a
EZ		 1386
1387 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1388 (long) read_register (0),
1389 (long) read_register (1),
1390 (long) read_register (2),
1391 (long) read_register (3),
1392 (long) read_register (4),
1393 (long) read_register (5),
1394 (long) read_register (6),
1395 (long) read_register (7));
1396 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1397 (long) read_register (8),
1398 (long) read_register (9),
1399 (long) read_register (10),
1400 (long) read_register (11),
1401 (long) read_register (12),
1402 (long) read_register (13),
1403 (long) read_register (14),
1404 (long) read_register (15));
1405
1406 printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
f81353e4
EZ		 1407 (long) read_register (tdep->A0G_REGNUM) & 0xff,
1408 (long) read_register (tdep->A0_REGNUM),
1409 (long) read_register (tdep->M0_REGNUM),
1410 (long) read_register (tdep->X0_REGNUM),
1411 (long) read_register (tdep->Y0_REGNUM),
1412 (long) read_register (tdep->RS_REGNUM),
1413 (long) read_register (tdep->MOD_REGNUM));
cc17453a 1414 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
f81353e4
EZ		 1415 (long) read_register (tdep->A1G_REGNUM) & 0xff,
1416 (long) read_register (tdep->A1_REGNUM),
1417 (long) read_register (tdep->M1_REGNUM),
1418 (long) read_register (tdep->X1_REGNUM),
1419 (long) read_register (tdep->Y1_REGNUM),
1420 (long) read_register (tdep->RE_REGNUM));
cc17453a
EZ		 1421}
1422
53116e27
EZ		 1423void sh_show_regs_command (char *args, int from_tty)
1424{
1425 if (sh_show_regs)
1426 (*sh_show_regs)();
1427}
1428
cc17453a
EZ		 1429/* Index within `registers' of the first byte of the space for
1430 register N. */
1431static int
fba45db2 1432sh_default_register_byte (int reg_nr)
8db62801 1433{
cc17453a
EZ		 1434 return (reg_nr * 4);
1435}
1436
53116e27 1437static int
fba45db2 1438sh_sh4_register_byte (int reg_nr)
53116e27 1439{
f81353e4
EZ		 1440 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1441
1442 if (reg_nr >= tdep->DR0_REGNUM
1443 && reg_nr <= tdep->DR_LAST_REGNUM)
53116e27 1444 return (dr_reg_base_num (reg_nr) * 4);
f81353e4
EZ		 1445 else if (reg_nr >= tdep->FV0_REGNUM
1446 && reg_nr <= tdep->FV_LAST_REGNUM)
53116e27
EZ		 1447 return (fv_reg_base_num (reg_nr) * 4);
1448 else
1449 return (reg_nr * 4);
1450}
1451
cc17453a
EZ		 1452/* Number of bytes of storage in the actual machine representation for
1453 register REG_NR. */
1454static int
fba45db2 1455sh_default_register_raw_size (int reg_nr)
cc17453a
EZ		 1456{
1457 return 4;
1458}
1459
53116e27 1460static int
fba45db2 1461sh_sh4_register_raw_size (int reg_nr)
53116e27 1462{
f81353e4
EZ		 1463 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1464
1465 if (reg_nr >= tdep->DR0_REGNUM
1466 && reg_nr <= tdep->DR_LAST_REGNUM)
53116e27 1467 return 8;
f81353e4
EZ		 1468 else if (reg_nr >= tdep->FV0_REGNUM
1469 && reg_nr <= tdep->FV_LAST_REGNUM)
53116e27
EZ		 1470 return 16;
1471 else
1472 return 4;
1473}
1474
cc17453a
EZ		 1475/* Number of bytes of storage in the program's representation
1476 for register N. */
1477static int
fba45db2 1478sh_register_virtual_size (int reg_nr)
cc17453a
EZ		 1479{
1480 return 4;
1481}
1482
1483/* Return the GDB type object for the "standard" data type
1484 of data in register N. */
cc17453a 1485static struct type *
fba45db2 1486sh_sh3e_register_virtual_type (int reg_nr)
cc17453a 1487{
f81353e4
EZ		 1488 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1489
cc17453a 1490 if ((reg_nr >= FP0_REGNUM
f81353e4
EZ		 1491 && (reg_nr <= tdep->FP_LAST_REGNUM))
1492 || (reg_nr == tdep->FPUL_REGNUM))
cc17453a 1493 return builtin_type_float;
8db62801 1494 else
cc17453a
EZ		 1495 return builtin_type_int;
1496}
1497
7f4dbe94
EZ		 1498static struct type *
1499sh_sh4_build_float_register_type (int high)
1500{
1501 struct type *temp;
1502
1503 temp = create_range_type (NULL, builtin_type_int, 0, high);
1504 return create_array_type (NULL, builtin_type_float, temp);
1505}
1506
53116e27 1507static struct type *
fba45db2 1508sh_sh4_register_virtual_type (int reg_nr)
53116e27 1509{
f81353e4
EZ		 1510 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1511
53116e27 1512 if ((reg_nr >= FP0_REGNUM
f81353e4
EZ		 1513 && (reg_nr <= tdep->FP_LAST_REGNUM))
1514 || (reg_nr == tdep->FPUL_REGNUM))
53116e27 1515 return builtin_type_float;
f81353e4
EZ		 1516 else if (reg_nr >= tdep->DR0_REGNUM
1517 && reg_nr <= tdep->DR_LAST_REGNUM)
53116e27 1518 return builtin_type_double;
f81353e4
EZ		 1519 else if (reg_nr >= tdep->FV0_REGNUM
1520 && reg_nr <= tdep->FV_LAST_REGNUM)
53116e27
EZ		 1521 return sh_sh4_build_float_register_type (3);
1522 else
1523 return builtin_type_int;
1524}
1525
cc17453a 1526static struct type *
fba45db2 1527sh_default_register_virtual_type (int reg_nr)
cc17453a
EZ		 1528{
1529 return builtin_type_int;
1530}
1531
fb409745
EZ		 1532/* On the sh4, the DRi pseudo registers are problematic if the target
1533 is little endian. When the user writes one of those registers, for
1534 instance with 'ser var $dr0=1', we want the double to be stored
1535 like this:
1536 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
1537 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1538
1539 This corresponds to little endian byte order & big endian word
1540 order. However if we let gdb write the register w/o conversion, it
1541 will write fr0 and fr1 this way:
1542 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1543 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
1544 because it will consider fr0 and fr1 as a single LE stretch of memory.
1545
1546 To achieve what we want we must force gdb to store things in
1547 floatformat_ieee_double_littlebyte_bigword (which is defined in
1548 include/floatformat.h and libiberty/floatformat.c.
1549
1550 In case the target is big endian, there is no problem, the
1551 raw bytes will look like:
1552 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
1553 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1554
1555 The other pseudo registers (the FVs) also don't pose a problem
1556 because they are stored as 4 individual FP elements. */
1557
7bd872fe 1558static void
fb409745
EZ		 1559sh_sh4_register_convert_to_virtual (int regnum, struct type *type,
1560 char *from, char *to)
1561{
f81353e4
EZ		 1562 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1563
1564 if (regnum >= tdep->DR0_REGNUM
1565 && regnum <= tdep->DR_LAST_REGNUM)
fb409745
EZ		 1566 {
1567 DOUBLEST val;
1568 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, from, &val);
3bbfbb92 1569 store_floating (to, TYPE_LENGTH (type), val);
fb409745
EZ		 1570 }
1571 else
3bbfbb92 1572 error ("sh_register_convert_to_virtual called with non DR register number");
fb409745
EZ		 1573}
1574
7bd872fe 1575static void
fb409745 1576sh_sh4_register_convert_to_raw (struct type *type, int regnum,
7bd872fe 1577 char *from, char *to)
fb409745 1578{
f81353e4
EZ		 1579 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1580
1581 if (regnum >= tdep->DR0_REGNUM
1582 && regnum <= tdep->DR_LAST_REGNUM)
fb409745
EZ		 1583 {
1584 DOUBLEST val = extract_floating (from, TYPE_LENGTH(type));
1585 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword, &val, to);
1586 }
1587 else
1588 error("sh_register_convert_to_raw called with non DR register number");
1589}
1590
53116e27 1591void
7bd872fe 1592sh_pseudo_register_read (int reg_nr, char *buffer)
53116e27
EZ		 1593{
1594 int base_regnum, portion;
7bd872fe 1595 char *temp_buffer = (char*) alloca (MAX_REGISTER_RAW_SIZE);
f81353e4 1596 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
53116e27 1597
7bd872fe
EZ		 1598 if (reg_nr >= tdep->DR0_REGNUM
1599 && reg_nr <= tdep->DR_LAST_REGNUM)
1600 {
1601 base_regnum = dr_reg_base_num (reg_nr);
1602
1603 /* Build the value in the provided buffer. */
1604 /* Read the real regs for which this one is an alias. */
1605 for (portion = 0; portion < 2; portion++)
1606 regcache_read (base_regnum + portion,
1607 temp_buffer
1608 + REGISTER_RAW_SIZE (base_regnum) * portion);
1609 /* We must pay attention to the endiannes. */
1610 sh_sh4_register_convert_to_virtual (reg_nr,
1611 REGISTER_VIRTUAL_TYPE (reg_nr),
1612 temp_buffer, buffer);
1613 }
1614 else if (reg_nr >= tdep->FV0_REGNUM
1615 && reg_nr <= tdep->FV_LAST_REGNUM)
53116e27 1616 {
7bd872fe
EZ		 1617 base_regnum = fv_reg_base_num (reg_nr);
1618
1619 /* Read the real regs for which this one is an alias. */
1620 for (portion = 0; portion < 4; portion++)
1621 regcache_read (base_regnum + portion,
1622 buffer + REGISTER_RAW_SIZE (base_regnum) * portion);
53116e27
EZ		 1623 }
1624}
1625
7bd872fe
EZ		 1626static void
1627sh4_register_read (struct gdbarch *gdbarch, int reg_nr, char *buffer)
1628{
1629 if (reg_nr >= 0 && reg_nr < gdbarch_tdep (current_gdbarch)->DR0_REGNUM)
1630 /* It is a regular register. */
1631 regcache_read (reg_nr, buffer);
1632 else
1633 /* It is a pseudo register and we need to construct its value */
1634 sh_pseudo_register_read (reg_nr, buffer);
1635}
1636
53116e27 1637void
7bd872fe 1638sh_pseudo_register_write (int reg_nr, char *buffer)
53116e27
EZ		 1639{
1640 int base_regnum, portion;
7bd872fe 1641 char *temp_buffer = (char*) alloca (MAX_REGISTER_RAW_SIZE);
f81353e4 1642 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
53116e27 1643
f81353e4
EZ		 1644 if (reg_nr >= tdep->DR0_REGNUM
1645 && reg_nr <= tdep->DR_LAST_REGNUM)
53116e27
EZ		 1646 {
1647 base_regnum = dr_reg_base_num (reg_nr);
1648
7bd872fe
EZ		 1649 /* We must pay attention to the endiannes. */
1650 sh_sh4_register_convert_to_raw (REGISTER_VIRTUAL_TYPE (reg_nr), reg_nr,
1651 buffer, temp_buffer);
1652
53116e27
EZ		 1653 /* Write the real regs for which this one is an alias. */
1654 for (portion = 0; portion < 2; portion++)
7bd872fe
EZ		 1655 regcache_write (base_regnum + portion,
1656 temp_buffer + REGISTER_RAW_SIZE (base_regnum) * portion);
53116e27 1657 }
f81353e4
EZ		 1658 else if (reg_nr >= tdep->FV0_REGNUM
1659 && reg_nr <= tdep->FV_LAST_REGNUM)
53116e27
EZ		 1660 {
1661 base_regnum = fv_reg_base_num (reg_nr);
1662
1663 /* Write the real regs for which this one is an alias. */
1664 for (portion = 0; portion < 4; portion++)
7bd872fe
EZ		 1665 regcache_write (base_regnum + portion,
1666 buffer + REGISTER_RAW_SIZE (base_regnum) * portion);
53116e27
EZ		 1667 }
1668}
1669
7bd872fe
EZ		 1670static void
1671sh4_register_write (struct gdbarch *gdbarch, int reg_nr, char *buffer)
1672{
1673 if (reg_nr >= 0 && reg_nr < gdbarch_tdep (current_gdbarch)->DR0_REGNUM)
1674 /* It is a regular register. */
1675 regcache_write (reg_nr, buffer);
1676 else
1677 /* It is a pseudo register and we need to construct its value */
1678 sh_pseudo_register_write (reg_nr, buffer);
1679}
1680
3bbfbb92 1681/* Floating point vector of 4 float registers. */
53116e27
EZ		 1682static void
1683do_fv_register_info (int fv_regnum)
1684{
1685 int first_fp_reg_num = fv_reg_base_num (fv_regnum);
1686 printf_filtered ("fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
1687 fv_regnum - gdbarch_tdep (current_gdbarch)->FV0_REGNUM,
1688 (int) read_register (first_fp_reg_num),
1689 (int) read_register (first_fp_reg_num + 1),
1690 (int) read_register (first_fp_reg_num + 2),
1691 (int) read_register (first_fp_reg_num + 3));
1692}
1693
3bbfbb92 1694/* Double precision registers. */
53116e27
EZ		 1695static void
1696do_dr_register_info (int dr_regnum)
1697{
1698 int first_fp_reg_num = dr_reg_base_num (dr_regnum);
1699
1700 printf_filtered ("dr%d\t0x%08x%08x\n",
1701 dr_regnum - gdbarch_tdep (current_gdbarch)->DR0_REGNUM,
1702 (int) read_register (first_fp_reg_num),
1703 (int) read_register (first_fp_reg_num + 1));
1704}
1705
1706static void
1707sh_do_pseudo_register (int regnum)
1708{
f81353e4
EZ		 1709 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1710
53116e27 1711 if (regnum < NUM_REGS || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
8e65ff28
AC		 1712 internal_error (__FILE__, __LINE__,
1713 "Invalid pseudo register number %d\n", regnum);
f81353e4
EZ		 1714 else if (regnum >= tdep->DR0_REGNUM
1715 && regnum < tdep->DR_LAST_REGNUM)
53116e27 1716 do_dr_register_info (regnum);
f81353e4
EZ		 1717 else if (regnum >= tdep->FV0_REGNUM
1718 && regnum <= tdep->FV_LAST_REGNUM)
53116e27
EZ		 1719 do_fv_register_info (regnum);
1720}
1721
53116e27
EZ		 1722static void
1723sh_do_fp_register (int regnum)
1724{ /* do values for FP (float) regs */
1725 char *raw_buffer;
1726 double flt; /* double extracted from raw hex data */
1727 int inv;
1728 int j;
1729
1730 /* Allocate space for the float. */
1731 raw_buffer = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM));
1732
1733 /* Get the data in raw format. */
1734 if (read_relative_register_raw_bytes (regnum, raw_buffer))
1735 error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
1736
1737 /* Get the register as a number */
1738 flt = unpack_double (builtin_type_float, raw_buffer, &inv);
1739
1740 /* Print the name and some spaces. */
1741 fputs_filtered (REGISTER_NAME (regnum), gdb_stdout);
1742 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), gdb_stdout);
1743
1744 /* Print the value. */
93d56215
AC		 1745 if (inv)
1746 printf_filtered ("<invalid float>");
1747 else
1748 printf_filtered ("%-10.9g", flt);
53116e27
EZ		 1749
1750 /* Print the fp register as hex. */
1751 printf_filtered ("\t(raw 0x");
1752 for (j = 0; j < REGISTER_RAW_SIZE (regnum); j++)
1753 {
d7449b42 1754 register int idx = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? j
53116e27
EZ		 1755 : REGISTER_RAW_SIZE (regnum) - 1 - j;
1756 printf_filtered ("%02x", (unsigned char) raw_buffer[idx]);
1757 }
1758 printf_filtered (")");
1759 printf_filtered ("\n");
1760}
1761
1762static void
1763sh_do_register (int regnum)
1764{
1765 char raw_buffer[MAX_REGISTER_RAW_SIZE];
1766
1767 fputs_filtered (REGISTER_NAME (regnum), gdb_stdout);
1768 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), gdb_stdout);
1769
1770 /* Get the data in raw format. */
1771 if (read_relative_register_raw_bytes (regnum, raw_buffer))
1772 printf_filtered ("*value not available*\n");
1773
1774 val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, 0,
1775 gdb_stdout, 'x', 1, 0, Val_pretty_default);
1776 printf_filtered ("\t");
1777 val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, 0,
1778 gdb_stdout, 0, 1, 0, Val_pretty_default);
1779 printf_filtered ("\n");
1780}
1781
1782static void
1783sh_print_register (int regnum)
1784{
1785 if (regnum < 0 || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
8e65ff28
AC		 1786 internal_error (__FILE__, __LINE__,
1787 "Invalid register number %d\n", regnum);
53116e27 1788
e30839fe 1789 else if (regnum >= 0 && regnum < NUM_REGS)
53116e27
EZ		 1790 {
1791 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
1792 sh_do_fp_register (regnum); /* FP regs */
1793 else
1794 sh_do_register (regnum); /* All other regs */
1795 }
1796
1797 else if (regnum < NUM_REGS + NUM_PSEUDO_REGS)
3bbfbb92 1798 do_pseudo_register (regnum);
53116e27
EZ		 1799}
1800
1801void
1802sh_do_registers_info (int regnum, int fpregs)
1803{
1804 if (regnum != -1) /* do one specified register */
1805 {
1806 if (*(REGISTER_NAME (regnum)) == '\0')
1807 error ("Not a valid register for the current processor type");
1808
1809 sh_print_register (regnum);
1810 }
1811 else
1812 /* do all (or most) registers */
1813 {
1814 regnum = 0;
1815 while (regnum < NUM_REGS)
1816 {
1817 /* If the register name is empty, it is undefined for this
1818 processor, so don't display anything. */
1819 if (REGISTER_NAME (regnum) == NULL
1820 || *(REGISTER_NAME (regnum)) == '\0')
1821 {
1822 regnum++;
1823 continue;
1824 }
1825
1826 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
1827 {
1828 if (fpregs)
1829 {
1830 /* true for "INFO ALL-REGISTERS" command */
1831 sh_do_fp_register (regnum); /* FP regs */
1832 regnum ++;
1833 }
1834 else
e6c42fda 1835 regnum += (gdbarch_tdep (current_gdbarch)->FP_LAST_REGNUM - FP0_REGNUM); /* skip FP regs */
53116e27
EZ		 1836 }
1837 else
1838 {
1839 sh_do_register (regnum); /* All other regs */
1840 regnum++;
1841 }
1842 }
1843
1844 if (fpregs)
1845 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
1846 {
3bbfbb92 1847 do_pseudo_register (regnum);
53116e27
EZ		 1848 regnum++;
1849 }
1850 }
1851}
1852
1a8629c7
MS		 1853#ifdef SVR4_SHARED_LIBS
1854
1855/* Fetch (and possibly build) an appropriate link_map_offsets structure
1856 for native i386 linux targets using the struct offsets defined in
1857 link.h (but without actual reference to that file).
1858
1859 This makes it possible to access i386-linux shared libraries from
1860 a gdb that was not built on an i386-linux host (for cross debugging).
1861 */
1862
1863struct link_map_offsets *
1864sh_linux_svr4_fetch_link_map_offsets (void)
1865{
1866 static struct link_map_offsets lmo;
1867 static struct link_map_offsets *lmp = 0;
1868
1869 if (lmp == 0)
1870 {
1871 lmp = &lmo;
1872
1873 lmo.r_debug_size = 8; /* 20 not actual size but all we need */
1874
1875 lmo.r_map_offset = 4;
1876 lmo.r_map_size = 4;
1877
1878 lmo.link_map_size = 20; /* 552 not actual size but all we need */
1879
1880 lmo.l_addr_offset = 0;
1881 lmo.l_addr_size = 4;
1882
1883 lmo.l_name_offset = 4;
1884 lmo.l_name_size = 4;
1885
1886 lmo.l_next_offset = 12;
1887 lmo.l_next_size = 4;
1888
1889 lmo.l_prev_offset = 16;
1890 lmo.l_prev_size = 4;
1891 }
1892
1893 return lmp;
1894}
1895#endif /* SVR4_SHARED_LIBS */
1896
cc17453a
EZ		 1897static gdbarch_init_ftype sh_gdbarch_init;
1898
1899static struct gdbarch *
fba45db2 1900sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
cc17453a
EZ		 1901{
1902 static LONGEST sh_call_dummy_words[] = {0};
1903 struct gdbarch *gdbarch;
1904 struct gdbarch_tdep *tdep;
1905 gdbarch_register_name_ftype *sh_register_name;
1906 gdbarch_store_return_value_ftype *sh_store_return_value;
1907 gdbarch_register_virtual_type_ftype *sh_register_virtual_type;
1908
1909 /* Find a candidate among the list of pre-declared architectures. */
1910 arches = gdbarch_list_lookup_by_info (arches, &info);
1911 if (arches != NULL)
1912 return arches->gdbarch;
1913
1914 /* None found, create a new architecture from the information
1915 provided. */
1916 tdep = XMALLOC (struct gdbarch_tdep);
1917 gdbarch = gdbarch_alloc (&info, tdep);
1918
1919 /* Initialize the register numbers that are not common to all the
1920 variants to -1, if necessary thse will be overwritten in the case
1921 statement below. */
1922 tdep->FPUL_REGNUM = -1;
1923 tdep->FPSCR_REGNUM = -1;
3bbfbb92 1924 tdep->PR_REGNUM = 17;
c62a7c7b 1925 tdep->SR_REGNUM = 22;
cc17453a 1926 tdep->DSR_REGNUM = -1;
e6c42fda 1927 tdep->FP_LAST_REGNUM = -1;
cc17453a
EZ		 1928 tdep->A0G_REGNUM = -1;
1929 tdep->A0_REGNUM = -1;
1930 tdep->A1G_REGNUM = -1;
1931 tdep->A1_REGNUM = -1;
1932 tdep->M0_REGNUM = -1;
1933 tdep->M1_REGNUM = -1;
1934 tdep->X0_REGNUM = -1;
1935 tdep->X1_REGNUM = -1;
1936 tdep->Y0_REGNUM = -1;
1937 tdep->Y1_REGNUM = -1;
1938 tdep->MOD_REGNUM = -1;
1939 tdep->RS_REGNUM = -1;
1940 tdep->RE_REGNUM = -1;
1941 tdep->SSR_REGNUM = -1;
1942 tdep->SPC_REGNUM = -1;
53116e27 1943 tdep->DR0_REGNUM = -1;
e6c42fda 1944 tdep->DR_LAST_REGNUM = -1;
53116e27 1945 tdep->FV0_REGNUM = -1;
e6c42fda 1946 tdep->FV_LAST_REGNUM = -1;
3bbfbb92
EZ		 1947 tdep->ARG0_REGNUM = 4;
1948 tdep->ARGLAST_REGNUM = 7;
1949 tdep->RETURN_REGNUM = 0;
1950 tdep->FLOAT_ARGLAST_REGNUM = -1;
a38d2a54 1951
cc17453a 1952 set_gdbarch_fp0_regnum (gdbarch, -1);
53116e27
EZ		 1953 set_gdbarch_num_pseudo_regs (gdbarch, 0);
1954 set_gdbarch_max_register_raw_size (gdbarch, 4);
1955 set_gdbarch_max_register_virtual_size (gdbarch, 4);
ec920329 1956 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
a38d2a54 1957 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
88e04cc1 1958 set_gdbarch_num_regs (gdbarch, SH_DEFAULT_NUM_REGS);
a38d2a54
EZ		 1959 set_gdbarch_sp_regnum (gdbarch, 15);
1960 set_gdbarch_fp_regnum (gdbarch, 14);
1961 set_gdbarch_pc_regnum (gdbarch, 16);
1962 set_gdbarch_register_size (gdbarch, 4);
88e04cc1 1963 set_gdbarch_register_bytes (gdbarch, SH_DEFAULT_NUM_REGS * 4);
c5f7d19c 1964 set_gdbarch_do_registers_info (gdbarch, sh_do_registers_info);
eaf90c5d 1965 set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc);
3bbfbb92
EZ		 1966 set_gdbarch_frame_chain (gdbarch, sh_frame_chain);
1967 set_gdbarch_get_saved_register (gdbarch, generic_get_saved_register);
1968 set_gdbarch_init_extra_frame_info (gdbarch, sh_init_extra_frame_info);
3116c80a 1969 set_gdbarch_extract_return_value (gdbarch, sh_extract_return_value);
3bbfbb92
EZ		 1970 set_gdbarch_push_arguments (gdbarch, sh_push_arguments);
1971 set_gdbarch_store_struct_return (gdbarch, sh_store_struct_return);
1972 set_gdbarch_use_struct_convention (gdbarch, sh_use_struct_convention);
1973 set_gdbarch_extract_struct_value_address (gdbarch, sh_extract_struct_value_address);
1974 set_gdbarch_pop_frame (gdbarch, sh_pop_frame);
2bf0cb65 1975 set_gdbarch_print_insn (gdbarch, gdb_print_insn_sh);
3bbfbb92
EZ		 1976 skip_prologue_hard_way = sh_skip_prologue_hard_way;
1977 do_pseudo_register = sh_do_pseudo_register;
cc17453a
EZ		 1978
1979 switch (info.bfd_arch_info->mach)
8db62801 1980 {
cc17453a
EZ		 1981 case bfd_mach_sh:
1982 sh_register_name = sh_sh_register_name;
1983 sh_show_regs = sh_generic_show_regs;
1984 sh_store_return_value = sh_default_store_return_value;
1985 sh_register_virtual_type = sh_default_register_virtual_type;
1986 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 1987 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
1988 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
1989 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a
EZ		 1990 break;
1991 case bfd_mach_sh2:
1992 sh_register_name = sh_sh_register_name;
1993 sh_show_regs = sh_generic_show_regs;
1994 sh_store_return_value = sh_default_store_return_value;
1995 sh_register_virtual_type = sh_default_register_virtual_type;
1996 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 1997 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
1998 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
1999 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a
EZ		 2000 break;
2001 case bfd_mach_sh_dsp:
2002 sh_register_name = sh_sh_dsp_register_name;
2003 sh_show_regs = sh_dsp_show_regs;
2004 sh_store_return_value = sh_default_store_return_value;
2005 sh_register_virtual_type = sh_default_register_virtual_type;
2006 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 2007 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
2008 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
2009 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a
EZ		 2010 tdep->DSR_REGNUM = 24;
2011 tdep->A0G_REGNUM = 25;
2012 tdep->A0_REGNUM = 26;
2013 tdep->A1G_REGNUM = 27;
2014 tdep->A1_REGNUM = 28;
2015 tdep->M0_REGNUM = 29;
2016 tdep->M1_REGNUM = 30;
2017 tdep->X0_REGNUM = 31;
2018 tdep->X1_REGNUM = 32;
2019 tdep->Y0_REGNUM = 33;
2020 tdep->Y1_REGNUM = 34;
2021 tdep->MOD_REGNUM = 40;
2022 tdep->RS_REGNUM = 43;
2023 tdep->RE_REGNUM = 44;
2024 break;
2025 case bfd_mach_sh3:
2026 sh_register_name = sh_sh3_register_name;
2027 sh_show_regs = sh3_show_regs;
2028 sh_store_return_value = sh_default_store_return_value;
2029 sh_register_virtual_type = sh_default_register_virtual_type;
2030 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 2031 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
2032 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
2033 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a
EZ		 2034 tdep->SSR_REGNUM = 41;
2035 tdep->SPC_REGNUM = 42;
2036 break;
2037 case bfd_mach_sh3e:
2038 sh_register_name = sh_sh3e_register_name;
2039 sh_show_regs = sh3e_show_regs;
2040 sh_store_return_value = sh3e_sh4_store_return_value;
2041 sh_register_virtual_type = sh_sh3e_register_virtual_type;
2042 set_gdbarch_frame_init_saved_regs (gdbarch, sh_fp_frame_init_saved_regs);
53116e27
EZ		 2043 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
2044 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
2045 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
3bbfbb92 2046 set_gdbarch_extract_return_value (gdbarch, sh3e_sh4_extract_return_value);
cc17453a
EZ		 2047 set_gdbarch_fp0_regnum (gdbarch, 25);
2048 tdep->FPUL_REGNUM = 23;
2049 tdep->FPSCR_REGNUM = 24;
e6c42fda 2050 tdep->FP_LAST_REGNUM = 40;
cc17453a
EZ		 2051 tdep->SSR_REGNUM = 41;
2052 tdep->SPC_REGNUM = 42;
2053 break;
2054 case bfd_mach_sh3_dsp:
2055 sh_register_name = sh_sh3_dsp_register_name;
2056 sh_show_regs = sh3_dsp_show_regs;
2057 sh_store_return_value = sh_default_store_return_value;
2058 sh_register_virtual_type = sh_default_register_virtual_type;
2059 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 2060 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
2061 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
2062 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a
EZ		 2063 tdep->DSR_REGNUM = 24;
2064 tdep->A0G_REGNUM = 25;
2065 tdep->A0_REGNUM = 26;
2066 tdep->A1G_REGNUM = 27;
2067 tdep->A1_REGNUM = 28;
2068 tdep->M0_REGNUM = 29;
2069 tdep->M1_REGNUM = 30;
2070 tdep->X0_REGNUM = 31;
2071 tdep->X1_REGNUM = 32;
2072 tdep->Y0_REGNUM = 33;
2073 tdep->Y1_REGNUM = 34;
2074 tdep->MOD_REGNUM = 40;
2075 tdep->RS_REGNUM = 43;
2076 tdep->RE_REGNUM = 44;
2077 tdep->SSR_REGNUM = 41;
2078 tdep->SPC_REGNUM = 42;
2079 break;
2080 case bfd_mach_sh4:
53116e27
EZ		 2081 sh_register_name = sh_sh4_register_name;
2082 sh_show_regs = sh4_show_regs;
cc17453a 2083 sh_store_return_value = sh3e_sh4_store_return_value;
53116e27 2084 sh_register_virtual_type = sh_sh4_register_virtual_type;
cc17453a 2085 set_gdbarch_frame_init_saved_regs (gdbarch, sh_fp_frame_init_saved_regs);
3bbfbb92 2086 set_gdbarch_extract_return_value (gdbarch, sh3e_sh4_extract_return_value);
cc17453a 2087 set_gdbarch_fp0_regnum (gdbarch, 25);
53116e27
EZ		 2088 set_gdbarch_register_raw_size (gdbarch, sh_sh4_register_raw_size);
2089 set_gdbarch_register_virtual_size (gdbarch, sh_sh4_register_raw_size);
2090 set_gdbarch_register_byte (gdbarch, sh_sh4_register_byte);
2091 set_gdbarch_num_pseudo_regs (gdbarch, 12);
2092 set_gdbarch_max_register_raw_size (gdbarch, 4 * 4);
2093 set_gdbarch_max_register_virtual_size (gdbarch, 4 * 4);
7bd872fe
EZ		 2094 set_gdbarch_register_read (gdbarch, sh4_register_read);
2095 set_gdbarch_register_write (gdbarch, sh4_register_write);
cc17453a
EZ		 2096 tdep->FPUL_REGNUM = 23;
2097 tdep->FPSCR_REGNUM = 24;
e6c42fda 2098 tdep->FP_LAST_REGNUM = 40;
cc17453a
EZ		 2099 tdep->SSR_REGNUM = 41;
2100 tdep->SPC_REGNUM = 42;
53116e27 2101 tdep->DR0_REGNUM = 59;
e6c42fda 2102 tdep->DR_LAST_REGNUM = 66;
53116e27 2103 tdep->FV0_REGNUM = 67;
e6c42fda 2104 tdep->FV_LAST_REGNUM = 70;
cc17453a
EZ		 2105 break;
2106 default:
2107 sh_register_name = sh_generic_register_name;
2108 sh_show_regs = sh_generic_show_regs;
2109 sh_store_return_value = sh_default_store_return_value;
2110 sh_register_virtual_type = sh_default_register_virtual_type;
2111 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 2112 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
2113 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
2114 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a 2115 break;
8db62801 2116 }
cc17453a
EZ		 2117
2118 set_gdbarch_read_pc (gdbarch, generic_target_read_pc);
2119 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
2120 set_gdbarch_read_fp (gdbarch, generic_target_read_fp);
2121 set_gdbarch_write_fp (gdbarch, generic_target_write_fp);
2122 set_gdbarch_read_sp (gdbarch, generic_target_read_sp);
2123 set_gdbarch_write_sp (gdbarch, generic_target_write_sp);
2124
cc17453a 2125 set_gdbarch_register_name (gdbarch, sh_register_name);
cc17453a
EZ		 2126 set_gdbarch_register_virtual_type (gdbarch, sh_register_virtual_type);
2127
cc17453a
EZ		 2128 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2129 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
cc17453a
EZ		 2130 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2131 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2132 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
a38d2a54 2133 set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT);/*??should be 8?*/
cc17453a
EZ		 2134
2135 set_gdbarch_use_generic_dummy_frames (gdbarch, 1);
2136 set_gdbarch_call_dummy_length (gdbarch, 0);
2137 set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT);
2138 set_gdbarch_call_dummy_address (gdbarch, entry_point_address);
2139 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1); /*???*/
2140 set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0);
2141 set_gdbarch_call_dummy_start_offset (gdbarch, 0);
2142 set_gdbarch_pc_in_call_dummy (gdbarch, generic_pc_in_call_dummy);
2143 set_gdbarch_call_dummy_words (gdbarch, sh_call_dummy_words);
2144 set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (sh_call_dummy_words));
2145 set_gdbarch_call_dummy_p (gdbarch, 1);
2146 set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0);
cc17453a
EZ		 2147 set_gdbarch_fix_call_dummy (gdbarch, generic_fix_call_dummy);
2148 set_gdbarch_coerce_float_to_double (gdbarch,
2149 sh_coerce_float_to_double);
2150
cc17453a
EZ		 2151 set_gdbarch_push_dummy_frame (gdbarch, generic_push_dummy_frame);
2152 set_gdbarch_push_return_address (gdbarch, sh_push_return_address);
2153
cc17453a 2154 set_gdbarch_store_return_value (gdbarch, sh_store_return_value);
cc17453a
EZ		 2155 set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
2156 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2157 set_gdbarch_decr_pc_after_break (gdbarch, 0);
2158 set_gdbarch_function_start_offset (gdbarch, 0);
cc17453a
EZ		 2159
2160 set_gdbarch_frame_args_skip (gdbarch, 0);
2161 set_gdbarch_frameless_function_invocation (gdbarch, frameless_look_for_prologue);
cc17453a
EZ		 2162 set_gdbarch_frame_chain_valid (gdbarch, generic_file_frame_chain_valid);
2163 set_gdbarch_frame_saved_pc (gdbarch, sh_frame_saved_pc);
c347ee3e
MS		 2164 set_gdbarch_frame_args_address (gdbarch, default_frame_address);
2165 set_gdbarch_frame_locals_address (gdbarch, default_frame_address);
cc17453a
EZ		 2166 set_gdbarch_saved_pc_after_call (gdbarch, sh_saved_pc_after_call);
2167 set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown);
2168 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
cc17453a
EZ		 2169
2170 return gdbarch;
8db62801
EZ		 2171}
2172
c906108c 2173void
fba45db2 2174_initialize_sh_tdep (void)
c906108c
SS		 2175{
2176 struct cmd_list_element *c;
cc17453a
EZ		 2177
2178 register_gdbarch_init (bfd_arch_sh, sh_gdbarch_init);
c906108c 2179
53116e27 2180 add_com ("regs", class_vars, sh_show_regs_command, "Print all registers");
c906108c 2181}
GDB Binutils - Deliverables
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