Commit | Line | Data |
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66d05e03 | 1 | /* Target-dependent code for Hitachi Super-H, for GDB. |
00dd4fd9 | 2 | Copyright (C) 1993, 1994, 1995, 1996 Free Software Foundation, Inc. |
9faacb92 SC |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2 of the License, or | |
9 | (at your option) any later version. | |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program; if not, write to the Free Software | |
6c9638b4 | 18 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ |
9faacb92 SC |
19 | |
20 | /* | |
21 | Contributed by Steve Chamberlain | |
22 | sac@cygnus.com | |
23 | */ | |
24 | ||
25 | #include "defs.h" | |
26 | #include "frame.h" | |
27 | #include "obstack.h" | |
28 | #include "symtab.h" | |
cf2b165e | 29 | #include "symfile.h" |
9faacb92 SC |
30 | #include "gdbtypes.h" |
31 | #include "gdbcmd.h" | |
66d05e03 | 32 | #include "gdbcore.h" |
9faacb92 SC |
33 | #include "value.h" |
34 | #include "dis-asm.h" | |
69992fc8 | 35 | #include "inferior.h" /* for BEFORE_TEXT_END etc. */ |
cf2b165e | 36 | #include "gdb_string.h" |
5f2f2809 | 37 | |
cd21cbc4 MA |
38 | extern int remote_write_size; /* in remote.c */ |
39 | ||
00dd4fd9 SS |
40 | /* Default to the original SH. */ |
41 | ||
42 | #define DEFAULT_SH_TYPE "sh" | |
43 | ||
44 | /* This value is the model of SH in use. */ | |
45 | ||
46 | char *sh_processor_type; | |
47 | ||
48 | char *tmp_sh_processor_type; | |
49 | ||
50 | /* A set of original names, to be used when restoring back to generic | |
51 | registers from a specific set. */ | |
52 | ||
53 | char *sh_generic_reg_names[] = REGISTER_NAMES; | |
54 | ||
55 | char *sh_reg_names[] = { | |
12ffa10c SS |
56 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
57 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
58 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
59 | "", "", | |
60 | "", "", "", "", "", "", "", "", | |
61 | "", "", "", "", "", "", "", "", | |
62 | "", "", | |
63 | "", "", "", "", "", "", "", "", | |
64 | "", "", "", "", "", "", "", "", | |
00dd4fd9 SS |
65 | }; |
66 | ||
67 | char *sh3_reg_names[] = { | |
12ffa10c SS |
68 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
69 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
70 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
71 | "", "", | |
72 | "", "", "", "", "", "", "", "", | |
73 | "", "", "", "", "", "", "", "", | |
74 | "ssr", "spc", | |
05535e79 | 75 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", |
12ffa10c | 76 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1" |
05535e79 SS |
77 | }; |
78 | ||
79 | char *sh3e_reg_names[] = { | |
12ffa10c SS |
80 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
81 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
82 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
83 | "fpul", "fpscr", | |
84 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", | |
85 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
86 | "ssr", "spc", | |
05535e79 SS |
87 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", |
88 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", | |
00dd4fd9 SS |
89 | }; |
90 | ||
91 | struct { | |
92 | char *name; | |
93 | char **regnames; | |
94 | } sh_processor_type_table[] = { | |
95 | { "sh", sh_reg_names }, | |
96 | { "sh3", sh3_reg_names }, | |
05535e79 | 97 | { "sh3e", sh3e_reg_names }, |
00dd4fd9 SS |
98 | { NULL, NULL } |
99 | }; | |
100 | ||
9faacb92 SC |
101 | /* Prologue looks like |
102 | [mov.l <regs>,@-r15]... | |
103 | [sts.l pr,@-r15] | |
104 | [mov.l r14,@-r15] | |
105 | [mov r15,r14] | |
106 | */ | |
107 | ||
108 | #define IS_STS(x) ((x) == 0x4f22) | |
109 | #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06) | |
110 | #define GET_PUSHED_REG(x) (((x) >> 4) & 0xf) | |
111 | #define IS_MOV_SP_FP(x) ((x) == 0x6ef3) | |
112 | #define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00) | |
c4deed18 SC |
113 | #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00) |
114 | #define IS_SHLL_R3(x) ((x) == 0x4300) | |
115 | #define IS_ADD_R3SP(x) ((x) == 0x3f3c) | |
4a9d4495 FF |
116 | /* start-sanitize-sh4 */ |
117 | #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) | |
118 | #define FPSCR_SZ (1 << 20) | |
119 | /* end-sanitize-sh4 */ | |
9faacb92 SC |
120 | |
121 | /* Skip any prologue before the guts of a function */ | |
122 | ||
123 | CORE_ADDR | |
124 | sh_skip_prologue (start_pc) | |
125 | CORE_ADDR start_pc; | |
9faacb92 SC |
126 | { |
127 | int w; | |
128 | ||
129 | w = read_memory_integer (start_pc, 2); | |
130 | while (IS_STS (w) | |
4a9d4495 FF |
131 | /* start-sanitize-sh4 */ |
132 | || IS_FMOV (w) | |
133 | /* end-sanitize-sh4 */ | |
9faacb92 | 134 | || IS_PUSH (w) |
c4deed18 | 135 | || IS_MOV_SP_FP (w) |
5f2f2809 SC |
136 | || IS_MOV_R3 (w) |
137 | || IS_ADD_R3SP (w) | |
138 | || IS_ADD_SP (w) | |
139 | || IS_SHLL_R3 (w)) | |
9faacb92 SC |
140 | { |
141 | start_pc += 2; | |
142 | w = read_memory_integer (start_pc, 2); | |
143 | } | |
144 | ||
145 | return start_pc; | |
146 | } | |
147 | ||
18b46e7c | 148 | /* Disassemble an instruction. */ |
9faacb92 SC |
149 | |
150 | int | |
18b46e7c SS |
151 | gdb_print_insn_sh (memaddr, info) |
152 | bfd_vma memaddr; | |
153 | disassemble_info *info; | |
9faacb92 | 154 | { |
5f2f2809 | 155 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) |
5076ecd0 | 156 | return print_insn_sh (memaddr, info); |
5f2f2809 | 157 | else |
5076ecd0 | 158 | return print_insn_shl (memaddr, info); |
9faacb92 | 159 | } |
18b46e7c | 160 | |
9faacb92 SC |
161 | /* Given a GDB frame, determine the address of the calling function's frame. |
162 | This will be used to create a new GDB frame struct, and then | |
163 | INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame. | |
164 | ||
165 | For us, the frame address is its stack pointer value, so we look up | |
166 | the function prologue to determine the caller's sp value, and return it. */ | |
167 | ||
669caa9c SS |
168 | CORE_ADDR |
169 | sh_frame_chain (frame) | |
170 | struct frame_info *frame; | |
9faacb92 | 171 | { |
69992fc8 MS |
172 | if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame)) |
173 | return frame->frame; /* dummy frame same as caller's frame */ | |
669caa9c SS |
174 | if (!inside_entry_file (frame->pc)) |
175 | return read_memory_integer (FRAME_FP (frame) + frame->f_offset, 4); | |
9faacb92 SC |
176 | else |
177 | return 0; | |
178 | } | |
179 | ||
69992fc8 MS |
180 | /* Find REGNUM on the stack. Otherwise, it's in an active register. One thing |
181 | we might want to do here is to check REGNUM against the clobber mask, and | |
182 | somehow flag it as invalid if it isn't saved on the stack somewhere. This | |
183 | would provide a graceful failure mode when trying to get the value of | |
184 | caller-saves registers for an inner frame. */ | |
185 | ||
186 | CORE_ADDR | |
187 | sh_find_callers_reg (fi, regnum) | |
188 | struct frame_info *fi; | |
189 | int regnum; | |
190 | { | |
191 | struct frame_saved_regs fsr; | |
192 | ||
193 | for (; fi; fi = fi->next) | |
194 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) | |
195 | /* When the caller requests PR from the dummy frame, we return PC because | |
196 | that's where the previous routine appears to have done a call from. */ | |
dc1b349d | 197 | return generic_read_register_dummy (fi->pc, fi->frame, regnum); |
69992fc8 MS |
198 | else |
199 | { | |
200 | FRAME_FIND_SAVED_REGS(fi, fsr); | |
201 | if (fsr.regs[regnum] != 0) | |
202 | return read_memory_integer (fsr.regs[regnum], | |
203 | REGISTER_RAW_SIZE(regnum)); | |
204 | } | |
205 | return read_register (regnum); | |
206 | } | |
207 | ||
66d05e03 SS |
208 | /* Put here the code to store, into a struct frame_saved_regs, the |
209 | addresses of the saved registers of frame described by FRAME_INFO. | |
9faacb92 | 210 | This includes special registers such as pc and fp saved in special |
66d05e03 SS |
211 | ways in the stack frame. sp is even more special: the address we |
212 | return for it IS the sp for the next frame. */ | |
9faacb92 SC |
213 | |
214 | void | |
69992fc8 | 215 | sh_frame_find_saved_regs (fi, fsr) |
9faacb92 SC |
216 | struct frame_info *fi; |
217 | struct frame_saved_regs *fsr; | |
218 | { | |
7ccb1e44 | 219 | int where[NUM_REGS]; |
9faacb92 SC |
220 | int rn; |
221 | int have_fp = 0; | |
222 | int depth; | |
223 | int pc; | |
224 | int opc; | |
225 | int insn; | |
c4deed18 | 226 | int r3_val = 0; |
dc1b349d | 227 | char * dummy_regs = generic_find_dummy_frame (fi->pc, fi->frame); |
69992fc8 MS |
228 | |
229 | if (dummy_regs) | |
230 | { | |
231 | /* DANGER! This is ONLY going to work if the char buffer format of | |
232 | the saved registers is byte-for-byte identical to the | |
233 | CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */ | |
234 | memcpy (&fsr->regs, dummy_regs, sizeof(fsr)); | |
235 | return; | |
236 | } | |
9faacb92 SC |
237 | |
238 | opc = pc = get_pc_function_start (fi->pc); | |
239 | ||
240 | insn = read_memory_integer (pc, 2); | |
241 | ||
c4deed18 SC |
242 | fi->leaf_function = 1; |
243 | fi->f_offset = 0; | |
244 | ||
9faacb92 SC |
245 | for (rn = 0; rn < NUM_REGS; rn++) |
246 | where[rn] = -1; | |
247 | ||
248 | depth = 0; | |
249 | ||
4a9d4495 FF |
250 | /* Loop around examining the prologue insns until we find something |
251 | that does not appear to be part of the prologue. But give up | |
252 | after 20 of them, since we're getting silly then. */ | |
253 | ||
254 | while (pc < opc + 20 * 2) | |
9faacb92 SC |
255 | { |
256 | /* See where the registers will be saved to */ | |
257 | if (IS_PUSH (insn)) | |
258 | { | |
259 | pc += 2; | |
260 | rn = GET_PUSHED_REG (insn); | |
261 | where[rn] = depth; | |
262 | insn = read_memory_integer (pc, 2); | |
263 | depth += 4; | |
264 | } | |
265 | else if (IS_STS (insn)) | |
266 | { | |
267 | pc += 2; | |
268 | where[PR_REGNUM] = depth; | |
269 | insn = read_memory_integer (pc, 2); | |
c4deed18 SC |
270 | /* If we're storing the pr then this isn't a leaf */ |
271 | fi->leaf_function = 0; | |
9faacb92 SC |
272 | depth += 4; |
273 | } | |
c4deed18 SC |
274 | else if (IS_MOV_R3 (insn)) |
275 | { | |
0a325463 | 276 | r3_val = ((insn & 0xff) ^ 0x80) - 0x80; |
5f2f2809 | 277 | pc += 2; |
c4deed18 SC |
278 | insn = read_memory_integer (pc, 2); |
279 | } | |
280 | else if (IS_SHLL_R3 (insn)) | |
281 | { | |
5f2f2809 SC |
282 | r3_val <<= 1; |
283 | pc += 2; | |
c4deed18 SC |
284 | insn = read_memory_integer (pc, 2); |
285 | } | |
286 | else if (IS_ADD_R3SP (insn)) | |
287 | { | |
288 | depth += -r3_val; | |
5f2f2809 | 289 | pc += 2; |
c4deed18 SC |
290 | insn = read_memory_integer (pc, 2); |
291 | } | |
9faacb92 SC |
292 | else if (IS_ADD_SP (insn)) |
293 | { | |
294 | pc += 2; | |
0a325463 | 295 | depth -= ((insn & 0xff) ^ 0x80) - 0x80; |
9faacb92 SC |
296 | insn = read_memory_integer (pc, 2); |
297 | } | |
4a9d4495 FF |
298 | /* start-sanitize-sh4 */ |
299 | else if (IS_FMOV (insn)) | |
300 | { | |
301 | pc += 2; | |
302 | insn = read_memory_integer (pc, 2); | |
303 | if (read_register (FPSCR_REGNUM) & FPSCR_SZ) | |
304 | { | |
305 | depth += 8; | |
306 | } | |
307 | else | |
308 | { | |
309 | depth += 4; | |
310 | } | |
311 | } | |
312 | /* end-sanitize-sh4 */ | |
df14b38b SC |
313 | else |
314 | break; | |
9faacb92 SC |
315 | } |
316 | ||
317 | /* Now we know how deep things are, we can work out their addresses */ | |
318 | ||
319 | for (rn = 0; rn < NUM_REGS; rn++) | |
320 | { | |
321 | if (where[rn] >= 0) | |
322 | { | |
323 | if (rn == FP_REGNUM) | |
324 | have_fp = 1; | |
325 | ||
326 | fsr->regs[rn] = fi->frame - where[rn] + depth - 4; | |
327 | } | |
328 | else | |
329 | { | |
330 | fsr->regs[rn] = 0; | |
331 | } | |
332 | } | |
333 | ||
334 | if (have_fp) | |
335 | { | |
9faacb92 SC |
336 | fsr->regs[SP_REGNUM] = read_memory_integer (fsr->regs[FP_REGNUM], 4); |
337 | } | |
338 | else | |
339 | { | |
340 | fsr->regs[SP_REGNUM] = fi->frame - 4; | |
341 | } | |
342 | ||
c4deed18 | 343 | fi->f_offset = depth - where[FP_REGNUM] - 4; |
9faacb92 SC |
344 | /* Work out the return pc - either from the saved pr or the pr |
345 | value */ | |
9faacb92 SC |
346 | } |
347 | ||
348 | /* initialize the extra info saved in a FRAME */ | |
349 | ||
350 | void | |
69992fc8 | 351 | sh_init_extra_frame_info (fromleaf, fi) |
9faacb92 SC |
352 | int fromleaf; |
353 | struct frame_info *fi; | |
354 | { | |
69992fc8 | 355 | struct frame_saved_regs fsr; |
66d05e03 | 356 | |
5c8ba017 | 357 | if (fi->next) |
69992fc8 | 358 | fi->pc = FRAME_SAVED_PC (fi->next); |
5c8ba017 | 359 | |
69992fc8 MS |
360 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) |
361 | { | |
362 | /* We need to setup fi->frame here because run_stack_dummy gets it wrong | |
363 | by assuming it's always FP. */ | |
dc1b349d MS |
364 | fi->frame = generic_read_register_dummy (fi->pc, fi->frame, |
365 | SP_REGNUM); | |
366 | fi->return_pc = generic_read_register_dummy (fi->pc, fi->frame, | |
367 | PC_REGNUM); | |
69992fc8 MS |
368 | fi->f_offset = -(CALL_DUMMY_LENGTH + 4); |
369 | fi->leaf_function = 0; | |
370 | return; | |
371 | } | |
372 | else | |
373 | { | |
374 | FRAME_FIND_SAVED_REGS (fi, fsr); | |
375 | fi->return_pc = sh_find_callers_reg (fi, PR_REGNUM); | |
376 | } | |
9faacb92 SC |
377 | } |
378 | ||
9faacb92 SC |
379 | /* Discard from the stack the innermost frame, |
380 | restoring all saved registers. */ | |
381 | ||
382 | void | |
69992fc8 | 383 | sh_pop_frame () |
9faacb92 | 384 | { |
669caa9c | 385 | register struct frame_info *frame = get_current_frame (); |
9faacb92 SC |
386 | register CORE_ADDR fp; |
387 | register int regnum; | |
388 | struct frame_saved_regs fsr; | |
9faacb92 | 389 | |
69992fc8 MS |
390 | if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame)) |
391 | generic_pop_dummy_frame (); | |
392 | else | |
393 | { | |
394 | fp = FRAME_FP (frame); | |
395 | get_frame_saved_regs (frame, &fsr); | |
9faacb92 | 396 | |
69992fc8 MS |
397 | /* Copy regs from where they were saved in the frame */ |
398 | for (regnum = 0; regnum < NUM_REGS; regnum++) | |
9faacb92 | 399 | if (fsr.regs[regnum]) |
69992fc8 MS |
400 | write_register (regnum, read_memory_integer (fsr.regs[regnum], 4)); |
401 | ||
402 | write_register (PC_REGNUM, frame->return_pc); | |
403 | write_register (SP_REGNUM, fp + 4); | |
404 | } | |
405 | flush_cached_frames (); | |
406 | } | |
407 | ||
408 | /* Function: push_arguments | |
409 | Setup the function arguments for calling a function in the inferior. | |
410 | ||
411 | On the Hitachi SH architecture, there are four registers (R4 to R7) | |
412 | which are dedicated for passing function arguments. Up to the first | |
413 | four arguments (depending on size) may go into these registers. | |
414 | The rest go on the stack. | |
415 | ||
416 | Arguments that are smaller than 4 bytes will still take up a whole | |
417 | register or a whole 32-bit word on the stack, and will be | |
418 | right-justified in the register or the stack word. This includes | |
419 | chars, shorts, and small aggregate types. | |
420 | ||
421 | Arguments that are larger than 4 bytes may be split between two or | |
422 | more registers. If there are not enough registers free, an argument | |
423 | may be passed partly in a register (or registers), and partly on the | |
424 | stack. This includes doubles, long longs, and larger aggregates. | |
425 | As far as I know, there is no upper limit to the size of aggregates | |
426 | that will be passed in this way; in other words, the convention of | |
427 | passing a pointer to a large aggregate instead of a copy is not used. | |
428 | ||
429 | An exceptional case exists for struct arguments (and possibly other | |
430 | aggregates such as arrays) if the size is larger than 4 bytes but | |
431 | not a multiple of 4 bytes. In this case the argument is never split | |
432 | between the registers and the stack, but instead is copied in its | |
433 | entirety onto the stack, AND also copied into as many registers as | |
434 | there is room for. In other words, space in registers permitting, | |
435 | two copies of the same argument are passed in. As far as I can tell, | |
436 | only the one on the stack is used, although that may be a function | |
437 | of the level of compiler optimization. I suspect this is a compiler | |
438 | bug. Arguments of these odd sizes are left-justified within the | |
439 | word (as opposed to arguments smaller than 4 bytes, which are | |
440 | right-justified). | |
441 | ||
442 | ||
443 | If the function is to return an aggregate type such as a struct, it | |
444 | is either returned in the normal return value register R0 (if its | |
445 | size is no greater than one byte), or else the caller must allocate | |
446 | space into which the callee will copy the return value (if the size | |
447 | is greater than one byte). In this case, a pointer to the return | |
448 | value location is passed into the callee in register R2, which does | |
449 | not displace any of the other arguments passed in via registers R4 | |
450 | to R7. */ | |
451 | ||
452 | CORE_ADDR | |
453 | sh_push_arguments (nargs, args, sp, struct_return, struct_addr) | |
454 | int nargs; | |
455 | value_ptr *args; | |
456 | CORE_ADDR sp; | |
457 | unsigned char struct_return; | |
458 | CORE_ADDR struct_addr; | |
459 | { | |
dc1b349d | 460 | int stack_offset, stack_alloc; |
69992fc8 MS |
461 | int argreg; |
462 | int argnum; | |
dc1b349d | 463 | struct type *type; |
69992fc8 MS |
464 | CORE_ADDR regval; |
465 | char *val; | |
466 | char valbuf[4]; | |
467 | int len; | |
dc1b349d | 468 | int odd_sized_struct; |
69992fc8 MS |
469 | |
470 | /* first force sp to a 4-byte alignment */ | |
471 | sp = sp & ~3; | |
472 | ||
473 | /* The "struct return pointer" pseudo-argument has its own dedicated | |
474 | register */ | |
475 | if (struct_return) | |
476 | write_register (STRUCT_RETURN_REGNUM, struct_addr); | |
477 | ||
dc1b349d MS |
478 | /* Now make sure there's space on the stack */ |
479 | for (argnum = 0, stack_alloc = 0; | |
480 | argnum < nargs; argnum++) | |
481 | stack_alloc += ((TYPE_LENGTH(VALUE_TYPE(args[argnum])) + 3) & ~3); | |
482 | sp -= stack_alloc; /* make room on stack for args */ | |
483 | ||
484 | ||
485 | /* Now load as many as possible of the first arguments into | |
486 | registers, and push the rest onto the stack. There are 16 bytes | |
487 | in four registers available. Loop thru args from first to last. */ | |
488 | ||
489 | argreg = ARG0_REGNUM; | |
490 | for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++) | |
69992fc8 | 491 | { |
dc1b349d MS |
492 | type = VALUE_TYPE (args[argnum]); |
493 | len = TYPE_LENGTH (type); | |
494 | memset(valbuf, 0, sizeof(valbuf)); | |
69992fc8 | 495 | if (len < 4) |
dc1b349d MS |
496 | { /* value gets right-justified in the register or stack word */ |
497 | memcpy(valbuf + (4 - len), | |
69992fc8 | 498 | (char *) VALUE_CONTENTS (args[argnum]), len); |
dc1b349d MS |
499 | val = valbuf; |
500 | } | |
69992fc8 | 501 | else |
dc1b349d | 502 | val = (char *) VALUE_CONTENTS (args[argnum]); |
69992fc8 | 503 | |
dc1b349d MS |
504 | if (len > 4 && (len & 3) != 0) |
505 | odd_sized_struct = 1; /* such structs go entirely on stack */ | |
506 | else | |
507 | odd_sized_struct = 0; | |
69992fc8 | 508 | while (len > 0) |
9faacb92 | 509 | { |
dc1b349d | 510 | if (argreg > ARGLAST_REGNUM || odd_sized_struct) |
409f64ae | 511 | { /* must go on the stack */ |
dc1b349d MS |
512 | write_memory (sp + stack_offset, val, 4); |
513 | stack_offset += 4; | |
69992fc8 | 514 | } |
dc1b349d MS |
515 | /* NOTE WELL!!!!! This is not an "else if" clause!!! |
516 | That's because some *&^%$ things get passed on the stack | |
517 | AND in the registers! */ | |
518 | if (argreg <= ARGLAST_REGNUM) | |
409f64ae | 519 | { /* there's room in a register */ |
dc1b349d MS |
520 | regval = extract_address (val, REGISTER_RAW_SIZE(argreg)); |
521 | write_register (argreg++, regval); | |
522 | } | |
523 | /* Store the value 4 bytes at a time. This means that things | |
524 | larger than 4 bytes may go partly in registers and partly | |
525 | on the stack. */ | |
526 | len -= REGISTER_RAW_SIZE(argreg); | |
527 | val += REGISTER_RAW_SIZE(argreg); | |
9faacb92 SC |
528 | } |
529 | } | |
dc1b349d MS |
530 | return sp; |
531 | } | |
9faacb92 | 532 | |
dc1b349d MS |
533 | /* Function: push_return_address (pc) |
534 | Set up the return address for the inferior function call. | |
535 | Needed for targets where we don't actually execute a JSR/BSR instruction */ | |
69992fc8 | 536 | |
dc1b349d MS |
537 | CORE_ADDR |
538 | sh_push_return_address (pc, sp) | |
539 | CORE_ADDR pc; | |
540 | CORE_ADDR sp; | |
541 | { | |
409f64ae | 542 | write_register (PR_REGNUM, CALL_DUMMY_ADDRESS ()); |
dc1b349d MS |
543 | return sp; |
544 | } | |
69992fc8 | 545 | |
dc1b349d MS |
546 | /* Function: fix_call_dummy |
547 | Poke the callee function's address into the destination part of | |
548 | the CALL_DUMMY. The address is actually stored in a data word | |
549 | following the actualy CALL_DUMMY instructions, which will load | |
550 | it into a register using PC-relative addressing. This function | |
551 | expects the CALL_DUMMY to look like this: | |
69992fc8 | 552 | |
dc1b349d MS |
553 | mov.w @(2,PC), R8 |
554 | jsr @R8 | |
555 | nop | |
556 | trap | |
557 | <destination> | |
558 | */ | |
559 | ||
cf2b165e FF |
560 | #if 0 |
561 | void | |
dc1b349d MS |
562 | sh_fix_call_dummy (dummy, pc, fun, nargs, args, type, gcc_p) |
563 | char *dummy; | |
564 | CORE_ADDR pc; | |
565 | CORE_ADDR fun; | |
566 | int nargs; | |
567 | value_ptr *args; | |
568 | struct type *type; | |
569 | int gcc_p; | |
570 | { | |
571 | *(unsigned long *) (dummy + 8) = fun; | |
69992fc8 | 572 | } |
cf2b165e | 573 | #endif |
69992fc8 | 574 | |
dc1b349d MS |
575 | /* Function: get_saved_register |
576 | Just call the generic_get_saved_register function. */ | |
69992fc8 MS |
577 | |
578 | void | |
dc1b349d MS |
579 | get_saved_register (raw_buffer, optimized, addrp, frame, regnum, lval) |
580 | char *raw_buffer; | |
581 | int *optimized; | |
582 | CORE_ADDR *addrp; | |
583 | struct frame_info *frame; | |
584 | int regnum; | |
585 | enum lval_type *lval; | |
69992fc8 | 586 | { |
dc1b349d MS |
587 | generic_get_saved_register (raw_buffer, optimized, addrp, |
588 | frame, regnum, lval); | |
9faacb92 | 589 | } |
edd01519 | 590 | |
dc1b349d | 591 | |
00dd4fd9 SS |
592 | /* Command to set the processor type. */ |
593 | ||
594 | void | |
595 | sh_set_processor_type_command (args, from_tty) | |
596 | char *args; | |
597 | int from_tty; | |
598 | { | |
599 | int i; | |
600 | char *temp; | |
601 | ||
602 | /* The `set' commands work by setting the value, then calling the hook, | |
603 | so we let the general command modify a scratch location, then decide | |
604 | here if we really want to modify the processor type. */ | |
605 | if (tmp_sh_processor_type == NULL || *tmp_sh_processor_type == '\0') | |
606 | { | |
607 | printf_unfiltered ("The known SH processor types are as follows:\n\n"); | |
608 | for (i = 0; sh_processor_type_table[i].name != NULL; ++i) | |
609 | printf_unfiltered ("%s\n", sh_processor_type_table[i].name); | |
610 | ||
611 | /* Restore the value. */ | |
612 | tmp_sh_processor_type = strsave (sh_processor_type); | |
613 | ||
614 | return; | |
615 | } | |
616 | ||
617 | if (!sh_set_processor_type (tmp_sh_processor_type)) | |
618 | { | |
619 | /* Restore to a valid value before erroring out. */ | |
620 | temp = tmp_sh_processor_type; | |
621 | tmp_sh_processor_type = strsave (sh_processor_type); | |
622 | error ("Unknown processor type `%s'.", temp); | |
623 | } | |
624 | } | |
625 | ||
12ffa10c SS |
626 | /* This is a dummy not actually run. */ |
627 | ||
00dd4fd9 SS |
628 | static void |
629 | sh_show_processor_type_command (args, from_tty) | |
630 | char *args; | |
631 | int from_tty; | |
632 | { | |
633 | } | |
634 | ||
635 | /* Modify the actual processor type. */ | |
636 | ||
637 | int | |
638 | sh_set_processor_type (str) | |
639 | char *str; | |
640 | { | |
641 | int i, j; | |
642 | ||
643 | if (str == NULL) | |
644 | return 0; | |
645 | ||
646 | for (i = 0; sh_processor_type_table[i].name != NULL; ++i) | |
647 | { | |
648 | if (strcasecmp (str, sh_processor_type_table[i].name) == 0) | |
649 | { | |
650 | sh_processor_type = str; | |
651 | ||
652 | for (j = 0; j < NUM_REGS; ++j) | |
653 | reg_names[j] = sh_processor_type_table[i].regnames[j]; | |
654 | ||
655 | return 1; | |
656 | } | |
657 | } | |
658 | ||
659 | return 0; | |
660 | } | |
661 | ||
edd01519 | 662 | /* Print the registers in a form similar to the E7000 */ |
669caa9c | 663 | |
edd01519 | 664 | static void |
69992fc8 | 665 | sh_show_regs (args, from_tty) |
669caa9c SS |
666 | char *args; |
667 | int from_tty; | |
edd01519 | 668 | { |
1e6479d4 KS |
669 | int cpu = 0; |
670 | ||
671 | if (strcmp (sh_processor_type, "sh3") == 0) | |
672 | cpu = 1; | |
673 | else if (strcmp (sh_processor_type, "sh3e") == 0) | |
674 | cpu = 2; | |
675 | ||
5f2f2809 SC |
676 | printf_filtered ("PC=%08x SR=%08x PR=%08x MACH=%08x MACHL=%08x\n", |
677 | read_register (PC_REGNUM), | |
678 | read_register (SR_REGNUM), | |
679 | read_register (PR_REGNUM), | |
680 | read_register (MACH_REGNUM), | |
681 | read_register (MACL_REGNUM)); | |
682 | ||
1e6479d4 KS |
683 | printf_filtered ("GBR=%08x VBR=%08x", |
684 | read_register (GBR_REGNUM), | |
685 | read_register (VBR_REGNUM)); | |
686 | if (cpu == 1 || cpu == 2) | |
687 | { | |
688 | printf_filtered (" SSR=%08x SPC=%08x", | |
689 | read_register (SSR_REGNUM), | |
690 | read_register (SPC_REGNUM)); | |
691 | if (cpu ==2) | |
692 | { | |
693 | printf_filtered (" FPUL=%08x FPSCR=%08x", | |
694 | read_register (FPUL_REGNUM), | |
695 | read_register (FPSCR_REGNUM)); | |
696 | } | |
697 | } | |
698 | ||
699 | printf_filtered ("\nR0-R7 %08x %08x %08x %08x %08x %08x %08x %08x\n", | |
5f2f2809 SC |
700 | read_register (0), |
701 | read_register (1), | |
702 | read_register (2), | |
703 | read_register (3), | |
704 | read_register (4), | |
705 | read_register (5), | |
706 | read_register (6), | |
707 | read_register (7)); | |
708 | printf_filtered ("R8-R15 %08x %08x %08x %08x %08x %08x %08x %08x\n", | |
709 | read_register (8), | |
710 | read_register (9), | |
711 | read_register (10), | |
712 | read_register (11), | |
713 | read_register (12), | |
714 | read_register (13), | |
715 | read_register (14), | |
716 | read_register (15)); | |
1e6479d4 KS |
717 | if (cpu == 2) |
718 | { | |
719 | printf_filtered ("FP0-FP7 %08x %08x %08x %08x %08x %08x %08x %08x\n", | |
720 | read_register (FP0_REGNUM + 0), | |
721 | read_register (FP0_REGNUM + 1), | |
722 | read_register (FP0_REGNUM + 2), | |
723 | read_register (FP0_REGNUM + 3), | |
724 | read_register (FP0_REGNUM + 4), | |
725 | read_register (FP0_REGNUM + 5), | |
726 | read_register (FP0_REGNUM + 6), | |
727 | read_register (FP0_REGNUM + 7)); | |
728 | printf_filtered ("FP8-FP15 %08x %08x %08x %08x %08x %08x %08x %08x\n", | |
729 | read_register (FP0_REGNUM + 8), | |
730 | read_register (FP0_REGNUM + 9), | |
731 | read_register (FP0_REGNUM + 10), | |
732 | read_register (FP0_REGNUM + 11), | |
733 | read_register (FP0_REGNUM + 12), | |
734 | read_register (FP0_REGNUM + 13), | |
735 | read_register (FP0_REGNUM + 14), | |
736 | read_register (FP0_REGNUM + 15)); | |
737 | } | |
edd01519 | 738 | } |
69992fc8 | 739 | |
dc1b349d MS |
740 | /* Function: extract_return_value |
741 | Find a function's return value in the appropriate registers (in regbuf), | |
742 | and copy it into valbuf. */ | |
743 | ||
69992fc8 MS |
744 | void |
745 | sh_extract_return_value (type, regbuf, valbuf) | |
746 | struct type *type; | |
747 | void *regbuf; | |
748 | void *valbuf; | |
749 | { | |
750 | int len = TYPE_LENGTH(type); | |
751 | ||
752 | if (len <= 4) | |
753 | memcpy (valbuf, ((char *) regbuf) + 4 - len, len); | |
754 | else if (len <= 8) | |
755 | memcpy (valbuf, ((char *) regbuf) + 8 - len, len); | |
756 | else | |
757 | error ("bad size for return value"); | |
758 | } | |
759 | ||
976bb0be | 760 | void |
df14b38b SC |
761 | _initialize_sh_tdep () |
762 | { | |
00dd4fd9 SS |
763 | struct cmd_list_element *c; |
764 | ||
18b46e7c SS |
765 | tm_print_insn = gdb_print_insn_sh; |
766 | ||
00dd4fd9 SS |
767 | c = add_set_cmd ("processor", class_support, var_string_noescape, |
768 | (char *) &tmp_sh_processor_type, | |
769 | "Set the type of SH processor in use.\n\ | |
770 | Set this to be able to access processor-type-specific registers.\n\ | |
771 | ", | |
772 | &setlist); | |
773 | c->function.cfunc = sh_set_processor_type_command; | |
774 | c = add_show_from_set (c, &showlist); | |
775 | c->function.cfunc = sh_show_processor_type_command; | |
776 | ||
777 | tmp_sh_processor_type = strsave (DEFAULT_SH_TYPE); | |
778 | sh_set_processor_type_command (strsave (DEFAULT_SH_TYPE), 0); | |
779 | ||
69992fc8 | 780 | add_com ("regs", class_vars, sh_show_regs, "Print all registers"); |
df14b38b | 781 | } |