Commit | Line | Data |
---|---|---|
c906108c | 1 | /* Target-dependent code for Hitachi Super-H, for GDB. |
538a76d6 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002 |
3116c80a | 3 | Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b JM |
17 | You should have received a copy of the GNU General Public License |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
21 | |
22 | /* | |
c5aa993b JM |
23 | Contributed by Steve Chamberlain |
24 | sac@cygnus.com | |
c906108c SS |
25 | */ |
26 | ||
27 | #include "defs.h" | |
28 | #include "frame.h" | |
c906108c SS |
29 | #include "symtab.h" |
30 | #include "symfile.h" | |
31 | #include "gdbtypes.h" | |
32 | #include "gdbcmd.h" | |
33 | #include "gdbcore.h" | |
34 | #include "value.h" | |
35 | #include "dis-asm.h" | |
36 | #include "inferior.h" /* for BEFORE_TEXT_END etc. */ | |
37 | #include "gdb_string.h" | |
b4a20239 | 38 | #include "arch-utils.h" |
fb409745 | 39 | #include "floatformat.h" |
4e052eda | 40 | #include "regcache.h" |
d16aafd8 | 41 | #include "doublest.h" |
c906108c | 42 | |
ab3b8126 JT |
43 | #include "sh-tdep.h" |
44 | ||
d658f924 | 45 | #include "elf-bfd.h" |
1a8629c7 MS |
46 | #include "solib-svr4.h" |
47 | ||
283150cd EZ |
48 | /* sh64 flags */ |
49 | #include "elf/sh.h" | |
50 | /* registers numbers shared with the simulator */ | |
1c922164 | 51 | #include "gdb/sim-sh.h" |
283150cd | 52 | |
53116e27 | 53 | void (*sh_show_regs) (void); |
3bbfbb92 EZ |
54 | CORE_ADDR (*skip_prologue_hard_way) (CORE_ADDR); |
55 | void (*do_pseudo_register) (int); | |
cc17453a | 56 | |
88e04cc1 EZ |
57 | #define SH_DEFAULT_NUM_REGS 59 |
58 | ||
cc17453a EZ |
59 | /* Define other aspects of the stack frame. |
60 | we keep a copy of the worked out return pc lying around, since it | |
61 | is a useful bit of info */ | |
62 | ||
63 | struct frame_extra_info | |
64 | { | |
65 | CORE_ADDR return_pc; | |
66 | int leaf_function; | |
67 | int f_offset; | |
63978407 | 68 | }; |
c906108c | 69 | |
fa88f677 | 70 | static const char * |
cc17453a | 71 | sh_generic_register_name (int reg_nr) |
c5aa993b | 72 | { |
cc17453a | 73 | static char *register_names[] = |
c5aa993b | 74 | { |
cc17453a EZ |
75 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
76 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
77 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
78 | "fpul", "fpscr", | |
79 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", | |
80 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
81 | "ssr", "spc", | |
82 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", | |
83 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", | |
84 | }; | |
85 | if (reg_nr < 0) | |
86 | return NULL; | |
87 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
88 | return NULL; | |
89 | return register_names[reg_nr]; | |
90 | } | |
91 | ||
fa88f677 | 92 | static const char * |
cc17453a EZ |
93 | sh_sh_register_name (int reg_nr) |
94 | { | |
95 | static char *register_names[] = | |
63978407 | 96 | { |
cc17453a EZ |
97 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
98 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
99 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
100 | "", "", | |
101 | "", "", "", "", "", "", "", "", | |
102 | "", "", "", "", "", "", "", "", | |
103 | "", "", | |
104 | "", "", "", "", "", "", "", "", | |
105 | "", "", "", "", "", "", "", "", | |
106 | }; | |
107 | if (reg_nr < 0) | |
108 | return NULL; | |
109 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
110 | return NULL; | |
111 | return register_names[reg_nr]; | |
112 | } | |
113 | ||
fa88f677 | 114 | static const char * |
cc17453a EZ |
115 | sh_sh3_register_name (int reg_nr) |
116 | { | |
117 | static char *register_names[] = | |
c5aa993b | 118 | { |
cc17453a EZ |
119 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
120 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
121 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
122 | "", "", | |
123 | "", "", "", "", "", "", "", "", | |
124 | "", "", "", "", "", "", "", "", | |
125 | "ssr", "spc", | |
126 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", | |
127 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1" | |
128 | }; | |
129 | if (reg_nr < 0) | |
130 | return NULL; | |
131 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
132 | return NULL; | |
133 | return register_names[reg_nr]; | |
134 | } | |
135 | ||
fa88f677 | 136 | static const char * |
cc17453a EZ |
137 | sh_sh3e_register_name (int reg_nr) |
138 | { | |
139 | static char *register_names[] = | |
63978407 | 140 | { |
cc17453a EZ |
141 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
142 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
143 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
144 | "fpul", "fpscr", | |
145 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", | |
146 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
147 | "ssr", "spc", | |
148 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", | |
149 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", | |
150 | }; | |
151 | if (reg_nr < 0) | |
152 | return NULL; | |
153 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
154 | return NULL; | |
155 | return register_names[reg_nr]; | |
156 | } | |
157 | ||
fa88f677 | 158 | static const char * |
cc17453a EZ |
159 | sh_sh_dsp_register_name (int reg_nr) |
160 | { | |
161 | static char *register_names[] = | |
c5aa993b | 162 | { |
cc17453a EZ |
163 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
164 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
165 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
166 | "", "dsr", | |
167 | "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1", | |
168 | "y0", "y1", "", "", "", "", "", "mod", | |
169 | "", "", | |
170 | "rs", "re", "", "", "", "", "", "", | |
171 | "", "", "", "", "", "", "", "", | |
172 | }; | |
173 | if (reg_nr < 0) | |
174 | return NULL; | |
175 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
176 | return NULL; | |
177 | return register_names[reg_nr]; | |
178 | } | |
179 | ||
fa88f677 | 180 | static const char * |
cc17453a EZ |
181 | sh_sh3_dsp_register_name (int reg_nr) |
182 | { | |
183 | static char *register_names[] = | |
c5aa993b | 184 | { |
cc17453a EZ |
185 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
186 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
187 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
188 | "", "dsr", | |
189 | "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1", | |
190 | "y0", "y1", "", "", "", "", "", "mod", | |
191 | "ssr", "spc", | |
192 | "rs", "re", "", "", "", "", "", "", | |
193 | "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b" | |
194 | "", "", "", "", "", "", "", "", | |
195 | }; | |
196 | if (reg_nr < 0) | |
197 | return NULL; | |
198 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
199 | return NULL; | |
200 | return register_names[reg_nr]; | |
201 | } | |
202 | ||
fa88f677 | 203 | static const char * |
53116e27 EZ |
204 | sh_sh4_register_name (int reg_nr) |
205 | { | |
206 | static char *register_names[] = | |
207 | { | |
a38d2a54 | 208 | /* general registers 0-15 */ |
53116e27 EZ |
209 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
210 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
a38d2a54 | 211 | /* 16 - 22 */ |
53116e27 | 212 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", |
a38d2a54 | 213 | /* 23, 24 */ |
53116e27 | 214 | "fpul", "fpscr", |
a38d2a54 | 215 | /* floating point registers 25 - 40 */ |
53116e27 EZ |
216 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", |
217 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
a38d2a54 | 218 | /* 41, 42 */ |
53116e27 | 219 | "ssr", "spc", |
a38d2a54 | 220 | /* bank 0 43 - 50 */ |
53116e27 | 221 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", |
a38d2a54 | 222 | /* bank 1 51 - 58 */ |
53116e27 | 223 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", |
a38d2a54 | 224 | /* double precision (pseudo) 59 - 66 */ |
fe9f384f | 225 | "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", |
a38d2a54 | 226 | /* vectors (pseudo) 67 - 70 */ |
fe9f384f | 227 | "fv0", "fv4", "fv8", "fv12", |
a38d2a54 EZ |
228 | /* FIXME: missing XF 71 - 86 */ |
229 | /* FIXME: missing XD 87 - 94 */ | |
53116e27 EZ |
230 | }; |
231 | if (reg_nr < 0) | |
232 | return NULL; | |
233 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
234 | return NULL; | |
235 | return register_names[reg_nr]; | |
236 | } | |
237 | ||
fa88f677 | 238 | static const char * |
283150cd EZ |
239 | sh_sh64_register_name (int reg_nr) |
240 | { | |
241 | static char *register_names[] = | |
242 | { | |
243 | /* SH MEDIA MODE (ISA 32) */ | |
244 | /* general registers (64-bit) 0-63 */ | |
245 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
246 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
247 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
248 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", | |
249 | "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", | |
250 | "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", | |
251 | "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", | |
252 | "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", | |
253 | ||
254 | /* pc (64-bit) 64 */ | |
255 | "pc", | |
256 | ||
257 | /* status reg., saved status reg., saved pc reg. (64-bit) 65-67 */ | |
258 | "sr", "ssr", "spc", | |
259 | ||
260 | /* target registers (64-bit) 68-75*/ | |
261 | "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", | |
262 | ||
263 | /* floating point state control register (32-bit) 76 */ | |
264 | "fpscr", | |
265 | ||
266 | /* single precision floating point registers (32-bit) 77-140*/ | |
267 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", | |
268 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
269 | "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", | |
270 | "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", | |
271 | "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", | |
272 | "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", | |
273 | "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", | |
274 | "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", | |
275 | ||
276 | /* double precision registers (pseudo) 141-172 */ | |
277 | "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", | |
278 | "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", | |
279 | "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", | |
280 | "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62", | |
281 | ||
282 | /* floating point pairs (pseudo) 173-204*/ | |
283 | "fp0", "fp2", "fp4", "fp6", "fp8", "fp10", "fp12", "fp14", | |
284 | "fp16", "fp18", "fp20", "fp22", "fp24", "fp26", "fp28", "fp30", | |
285 | "fp32", "fp34", "fp36", "fp38", "fp40", "fp42", "fp44", "fp46", | |
286 | "fp48", "fp50", "fp52", "fp54", "fp56", "fp58", "fp60", "fp62", | |
287 | ||
288 | /* floating point vectors (4 floating point regs) (pseudo) 205-220*/ | |
289 | "fv0", "fv4", "fv8", "fv12", "fv16", "fv20", "fv24", "fv28", | |
290 | "fv32", "fv36", "fv40", "fv44", "fv48", "fv52", "fv56", "fv60", | |
291 | ||
292 | /* SH COMPACT MODE (ISA 16) (all pseudo) 221-272*/ | |
293 | "r0_c", "r1_c", "r2_c", "r3_c", "r4_c", "r5_c", "r6_c", "r7_c", | |
294 | "r8_c", "r9_c", "r10_c", "r11_c", "r12_c", "r13_c", "r14_c", "r15_c", | |
295 | "pc_c", | |
296 | "gbr_c", "mach_c", "macl_c", "pr_c", "t_c", | |
297 | "fpscr_c", "fpul_c", | |
298 | "fr0_c", "fr1_c", "fr2_c", "fr3_c", "fr4_c", "fr5_c", "fr6_c", "fr7_c", | |
299 | "fr8_c", "fr9_c", "fr10_c", "fr11_c", "fr12_c", "fr13_c", "fr14_c", "fr15_c", | |
300 | "dr0_c", "dr2_c", "dr4_c", "dr6_c", "dr8_c", "dr10_c", "dr12_c", "dr14_c", | |
301 | "fv0_c", "fv4_c", "fv8_c", "fv12_c", | |
302 | /* FIXME!!!! XF0 XF15, XD0 XD14 ?????*/ | |
303 | }; | |
304 | ||
305 | if (reg_nr < 0) | |
306 | return NULL; | |
307 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
308 | return NULL; | |
309 | return register_names[reg_nr]; | |
310 | } | |
311 | ||
312 | #define NUM_PSEUDO_REGS_SH_MEDIA 80 | |
313 | #define NUM_PSEUDO_REGS_SH_COMPACT 51 | |
314 | ||
3117ed25 | 315 | static const unsigned char * |
fba45db2 | 316 | sh_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
cc17453a EZ |
317 | { |
318 | /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */ | |
319 | static unsigned char breakpoint[] = {0xc3, 0xc3}; | |
320 | ||
321 | *lenptr = sizeof (breakpoint); | |
322 | return breakpoint; | |
323 | } | |
c906108c | 324 | |
283150cd EZ |
325 | /* Macros and functions for setting and testing a bit in a minimal |
326 | symbol that marks it as 32-bit function. The MSB of the minimal | |
327 | symbol's "info" field is used for this purpose. This field is | |
328 | already being used to store the symbol size, so the assumption is | |
329 | that the symbol size cannot exceed 2^31. | |
330 | ||
331 | ELF_MAKE_MSYMBOL_SPECIAL | |
332 | tests whether an ELF symbol is "special", i.e. refers | |
333 | to a 32-bit function, and sets a "special" bit in a | |
334 | minimal symbol to mark it as a 32-bit function | |
335 | MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol | |
336 | MSYMBOL_SIZE returns the size of the minimal symbol, i.e. | |
337 | the "info" field with the "special" bit masked out */ | |
338 | ||
339 | #define MSYMBOL_IS_SPECIAL(msym) \ | |
340 | (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0) | |
341 | ||
342 | void | |
343 | sh64_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym) | |
344 | { | |
345 | if (msym == NULL) | |
346 | return; | |
347 | ||
348 | if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_SH5_ISA32) | |
349 | { | |
350 | MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) | 0x80000000); | |
351 | SYMBOL_VALUE_ADDRESS (msym) |= 1; | |
352 | } | |
353 | } | |
354 | ||
355 | /* ISA32 (shmedia) function addresses are odd (bit 0 is set). Here | |
356 | are some macros to test, set, or clear bit 0 of addresses. */ | |
357 | #define IS_ISA32_ADDR(addr) ((addr) & 1) | |
358 | #define MAKE_ISA32_ADDR(addr) ((addr) | 1) | |
359 | #define UNMAKE_ISA32_ADDR(addr) ((addr) & ~1) | |
360 | ||
361 | static int | |
362 | pc_is_isa32 (bfd_vma memaddr) | |
363 | { | |
364 | struct minimal_symbol *sym; | |
365 | ||
366 | /* If bit 0 of the address is set, assume this is a | |
367 | ISA32 (shmedia) address. */ | |
368 | if (IS_ISA32_ADDR (memaddr)) | |
369 | return 1; | |
370 | ||
371 | /* A flag indicating that this is a ISA32 function is stored by elfread.c in | |
372 | the high bit of the info field. Use this to decide if the function is | |
373 | ISA16 or ISA32. */ | |
374 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
375 | if (sym) | |
376 | return MSYMBOL_IS_SPECIAL (sym); | |
377 | else | |
378 | return 0; | |
379 | } | |
380 | ||
381 | static const unsigned char * | |
382 | sh_sh64_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) | |
383 | { | |
384 | /* The BRK instruction for shmedia is | |
385 | 01101111 11110101 11111111 11110000 | |
386 | which translates in big endian mode to 0x6f, 0xf5, 0xff, 0xf0 | |
387 | and in little endian mode to 0xf0, 0xff, 0xf5, 0x6f */ | |
388 | ||
389 | /* The BRK instruction for shcompact is | |
390 | 00000000 00111011 | |
391 | which translates in big endian mode to 0x0, 0x3b | |
392 | and in little endian mode to 0x3b, 0x0*/ | |
393 | ||
394 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
395 | { | |
396 | if (pc_is_isa32 (*pcptr)) | |
397 | { | |
398 | static unsigned char big_breakpoint_media[] = {0x6f, 0xf5, 0xff, 0xf0}; | |
399 | *pcptr = UNMAKE_ISA32_ADDR (*pcptr); | |
400 | *lenptr = sizeof (big_breakpoint_media); | |
401 | return big_breakpoint_media; | |
402 | } | |
403 | else | |
404 | { | |
405 | static unsigned char big_breakpoint_compact[] = {0x0, 0x3b}; | |
406 | *lenptr = sizeof (big_breakpoint_compact); | |
407 | return big_breakpoint_compact; | |
408 | } | |
409 | } | |
410 | else | |
411 | { | |
412 | if (pc_is_isa32 (*pcptr)) | |
413 | { | |
414 | static unsigned char little_breakpoint_media[] = {0xf0, 0xff, 0xf5, 0x6f}; | |
415 | *pcptr = UNMAKE_ISA32_ADDR (*pcptr); | |
416 | *lenptr = sizeof (little_breakpoint_media); | |
417 | return little_breakpoint_media; | |
418 | } | |
419 | else | |
420 | { | |
421 | static unsigned char little_breakpoint_compact[] = {0x3b, 0x0}; | |
422 | *lenptr = sizeof (little_breakpoint_compact); | |
423 | return little_breakpoint_compact; | |
424 | } | |
425 | } | |
426 | } | |
427 | ||
c906108c | 428 | /* Prologue looks like |
c5aa993b JM |
429 | [mov.l <regs>,@-r15]... |
430 | [sts.l pr,@-r15] | |
431 | [mov.l r14,@-r15] | |
432 | [mov r15,r14] | |
8db62801 EZ |
433 | |
434 | Actually it can be more complicated than this. For instance, with | |
435 | newer gcc's: | |
436 | ||
437 | mov.l r14,@-r15 | |
438 | add #-12,r15 | |
439 | mov r15,r14 | |
440 | mov r4,r1 | |
441 | mov r5,r2 | |
442 | mov.l r6,@(4,r14) | |
443 | mov.l r7,@(8,r14) | |
444 | mov.b r1,@r14 | |
445 | mov r14,r1 | |
446 | mov r14,r1 | |
447 | add #2,r1 | |
448 | mov.w r2,@r1 | |
449 | ||
c5aa993b | 450 | */ |
c906108c | 451 | |
283150cd EZ |
452 | /* PTABS/L Rn, TRa 0110101111110001nnnnnnl00aaa0000 |
453 | with l=1 and n = 18 0110101111110001010010100aaa0000 */ | |
454 | #define IS_PTABSL_R18(x) (((x) & 0xffffff8f) == 0x6bf14a00) | |
455 | ||
456 | /* STS.L PR,@-r0 0100000000100010 | |
457 | r0-4-->r0, PR-->(r0) */ | |
458 | #define IS_STS_R0(x) ((x) == 0x4022) | |
459 | ||
460 | /* STS PR, Rm 0000mmmm00101010 | |
461 | PR-->Rm */ | |
462 | #define IS_STS_PR(x) (((x) & 0xf0ff) == 0x2a) | |
463 | ||
464 | /* MOV.L Rm,@(disp,r15) 00011111mmmmdddd | |
465 | Rm-->(dispx4+r15) */ | |
466 | #define IS_MOV_TO_R15(x) (((x) & 0xff00) == 0x1f00) | |
467 | ||
468 | /* MOV.L R14,@(disp,r15) 000111111110dddd | |
469 | R14-->(dispx4+r15) */ | |
470 | #define IS_MOV_R14(x) (((x) & 0xfff0) == 0x1fe0) | |
471 | ||
472 | /* ST.Q R14, disp, R18 101011001110dddddddddd0100100000 | |
473 | R18-->(dispx8+R14) */ | |
474 | #define IS_STQ_R18_R14(x) (((x) & 0xfff003ff) == 0xace00120) | |
475 | ||
476 | /* ST.Q R15, disp, R18 101011001111dddddddddd0100100000 | |
477 | R18-->(dispx8+R15) */ | |
478 | #define IS_STQ_R18_R15(x) (((x) & 0xfff003ff) == 0xacf00120) | |
479 | ||
480 | /* ST.L R15, disp, R18 101010001111dddddddddd0100100000 | |
481 | R18-->(dispx4+R15) */ | |
482 | #define IS_STL_R18_R15(x) (((x) & 0xfff003ff) == 0xa8f00120) | |
483 | ||
484 | /* ST.Q R15, disp, R14 1010 1100 1111 dddd dddd dd00 1110 0000 | |
485 | R14-->(dispx8+R15) */ | |
486 | #define IS_STQ_R14_R15(x) (((x) & 0xfff003ff) == 0xacf000e0) | |
487 | ||
488 | /* ST.L R15, disp, R14 1010 1000 1111 dddd dddd dd00 1110 0000 | |
489 | R14-->(dispx4+R15) */ | |
490 | #define IS_STL_R14_R15(x) (((x) & 0xfff003ff) == 0xa8f000e0) | |
491 | ||
492 | /* ADDI.L R15,imm,R15 1101 0100 1111 ssss ssss ss00 1111 0000 | |
493 | R15 + imm --> R15 */ | |
494 | #define IS_ADDIL_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd4f000f0) | |
495 | ||
496 | /* ADDI R15,imm,R15 1101 0000 1111 ssss ssss ss00 1111 0000 | |
497 | R15 + imm --> R15 */ | |
498 | #define IS_ADDI_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd0f000f0) | |
499 | ||
500 | /* ADD.L R15,R63,R14 0000 0000 1111 1000 1111 1100 1110 0000 | |
501 | R15 + R63 --> R14 */ | |
502 | #define IS_ADDL_SP_FP_MEDIA(x) ((x) == 0x00f8fce0) | |
503 | ||
504 | /* ADD R15,R63,R14 0000 0000 1111 1001 1111 1100 1110 0000 | |
505 | R15 + R63 --> R14 */ | |
506 | #define IS_ADD_SP_FP_MEDIA(x) ((x) == 0x00f9fce0) | |
507 | ||
508 | #define IS_MOV_SP_FP_MEDIA(x) (IS_ADDL_SP_FP_MEDIA(x) || IS_ADD_SP_FP_MEDIA(x)) | |
509 | ||
510 | /* MOV #imm, R0 1110 0000 ssss ssss | |
511 | #imm-->R0 */ | |
512 | #define IS_MOV_R0(x) (((x) & 0xff00) == 0xe000) | |
513 | ||
514 | /* MOV.L @(disp,PC), R0 1101 0000 iiii iiii */ | |
515 | #define IS_MOVL_R0(x) (((x) & 0xff00) == 0xd000) | |
516 | ||
517 | /* ADD r15,r0 0011 0000 1111 1100 | |
518 | r15+r0-->r0 */ | |
519 | #define IS_ADD_SP_R0(x) ((x) == 0x30fc) | |
520 | ||
521 | /* MOV.L R14 @-R0 0010 0000 1110 0110 | |
522 | R14-->(R0-4), R0-4-->R0 */ | |
523 | #define IS_MOV_R14_R0(x) ((x) == 0x20e6) | |
524 | ||
525 | /* ADD Rm,R63,Rn Rm+R63-->Rn 0000 00mm mmmm 1001 1111 11nn nnnn 0000 | |
526 | where Rm is one of r2-r9 which are the argument registers. */ | |
527 | /* FIXME: Recognize the float and double register moves too! */ | |
528 | #define IS_MEDIA_IND_ARG_MOV(x) \ | |
529 | ((((x) & 0xfc0ffc0f) == 0x0009fc00) && (((x) & 0x03f00000) >= 0x00200000 && ((x) & 0x03f00000) <= 0x00900000)) | |
530 | ||
531 | /* ST.Q Rn,0,Rm Rm-->Rn+0 1010 11nn nnnn 0000 0000 00mm mmmm 0000 | |
532 | or ST.L Rn,0,Rm Rm-->Rn+0 1010 10nn nnnn 0000 0000 00mm mmmm 0000 | |
533 | where Rm is one of r2-r9 which are the argument registers. */ | |
534 | #define IS_MEDIA_ARG_MOV(x) \ | |
535 | (((((x) & 0xfc0ffc0f) == 0xac000000) || (((x) & 0xfc0ffc0f) == 0xa8000000)) \ | |
536 | && (((x) & 0x000003f0) >= 0x00000020 && ((x) & 0x000003f0) <= 0x00000090)) | |
537 | ||
538 | /* ST.B R14,0,Rn Rn-->(R14+0) 1010 0000 1110 0000 0000 00nn nnnn 0000*/ | |
539 | /* ST.W R14,0,Rn Rn-->(R14+0) 1010 0100 1110 0000 0000 00nn nnnn 0000*/ | |
540 | /* ST.L R14,0,Rn Rn-->(R14+0) 1010 1000 1110 0000 0000 00nn nnnn 0000*/ | |
541 | /* FST.S R14,0,FRn Rn-->(R14+0) 1011 0100 1110 0000 0000 00nn nnnn 0000*/ | |
542 | /* FST.D R14,0,DRn Rn-->(R14+0) 1011 1100 1110 0000 0000 00nn nnnn 0000*/ | |
543 | #define IS_MEDIA_MOV_TO_R14(x) \ | |
544 | ((((x) & 0xfffffc0f) == 0xa0e00000) \ | |
545 | || (((x) & 0xfffffc0f) == 0xa4e00000) \ | |
546 | || (((x) & 0xfffffc0f) == 0xa8e00000) \ | |
547 | || (((x) & 0xfffffc0f) == 0xb4e00000) \ | |
548 | || (((x) & 0xfffffc0f) == 0xbce00000)) | |
549 | ||
550 | /* MOV Rm, Rn Rm-->Rn 0110 nnnn mmmm 0011 | |
551 | where Rm is r2-r9 */ | |
552 | #define IS_COMPACT_IND_ARG_MOV(x) \ | |
553 | ((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0020) && (((x) & 0x00f0) <= 0x0090)) | |
554 | ||
555 | /* compact direct arg move! | |
556 | MOV.L Rn, @r14 0010 1110 mmmm 0010 */ | |
557 | #define IS_COMPACT_ARG_MOV(x) \ | |
558 | (((((x) & 0xff0f) == 0x2e02) && (((x) & 0x00f0) >= 0x0020) && ((x) & 0x00f0) <= 0x0090)) | |
559 | ||
560 | /* MOV.B Rm, @R14 0010 1110 mmmm 0000 | |
561 | MOV.W Rm, @R14 0010 1110 mmmm 0001 */ | |
562 | #define IS_COMPACT_MOV_TO_R14(x) \ | |
563 | ((((x) & 0xff0f) == 0x2e00) || (((x) & 0xff0f) == 0x2e01)) | |
564 | ||
565 | #define IS_JSR_R0(x) ((x) == 0x400b) | |
566 | #define IS_NOP(x) ((x) == 0x0009) | |
567 | ||
568 | ||
8db62801 EZ |
569 | /* STS.L PR,@-r15 0100111100100010 |
570 | r15-4-->r15, PR-->(r15) */ | |
c906108c | 571 | #define IS_STS(x) ((x) == 0x4f22) |
8db62801 EZ |
572 | |
573 | /* MOV.L Rm,@-r15 00101111mmmm0110 | |
574 | r15-4-->r15, Rm-->(R15) */ | |
c906108c | 575 | #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06) |
8db62801 | 576 | |
c906108c | 577 | #define GET_PUSHED_REG(x) (((x) >> 4) & 0xf) |
8db62801 EZ |
578 | |
579 | /* MOV r15,r14 0110111011110011 | |
580 | r15-->r14 */ | |
c906108c | 581 | #define IS_MOV_SP_FP(x) ((x) == 0x6ef3) |
8db62801 EZ |
582 | |
583 | /* ADD #imm,r15 01111111iiiiiiii | |
584 | r15+imm-->r15 */ | |
c906108c | 585 | #define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00) |
8db62801 | 586 | |
c906108c SS |
587 | #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00) |
588 | #define IS_SHLL_R3(x) ((x) == 0x4300) | |
8db62801 EZ |
589 | |
590 | /* ADD r3,r15 0011111100111100 | |
591 | r15+r3-->r15 */ | |
c906108c | 592 | #define IS_ADD_R3SP(x) ((x) == 0x3f3c) |
8db62801 EZ |
593 | |
594 | /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011 | |
8db62801 | 595 | FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011 |
8db62801 | 596 | FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */ |
c906108c | 597 | #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) |
c906108c | 598 | |
8db62801 | 599 | /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 |
8db62801 | 600 | MOV.L Rm,@(disp,Rn) Rm-->(dispx4+Rn) 0001nnnnmmmmdddd |
8db62801 EZ |
601 | MOV.L Rm,@Rn Rm-->(Rn) 0010nnnnmmmm0010 |
602 | where Rm is one of r4,r5,r6,r7 which are the argument registers. */ | |
603 | #define IS_ARG_MOV(x) \ | |
604 | (((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) \ | |
cc17453a EZ |
605 | || ((((x) & 0xf000) == 0x1000) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) \ |
606 | || ((((x) & 0xf00f) == 0x2002) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070))) | |
8db62801 EZ |
607 | |
608 | /* MOV.L Rm,@(disp,r14) 00011110mmmmdddd | |
609 | Rm-->(dispx4+r14) where Rm is one of r4,r5,r6,r7 */ | |
3bbfbb92 | 610 | #define IS_MOV_TO_R14(x) \ |
cc17453a | 611 | ((((x) & 0xff00) == 0x1e) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) |
8db62801 EZ |
612 | |
613 | #define FPSCR_SZ (1 << 20) | |
c906108c | 614 | |
c906108c SS |
615 | /* Skip any prologue before the guts of a function */ |
616 | ||
8db62801 EZ |
617 | /* Skip the prologue using the debug information. If this fails we'll |
618 | fall back on the 'guess' method below. */ | |
619 | static CORE_ADDR | |
fba45db2 | 620 | after_prologue (CORE_ADDR pc) |
8db62801 EZ |
621 | { |
622 | struct symtab_and_line sal; | |
623 | CORE_ADDR func_addr, func_end; | |
624 | ||
625 | /* If we can not find the symbol in the partial symbol table, then | |
626 | there is no hope we can determine the function's start address | |
627 | with this code. */ | |
628 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
629 | return 0; | |
630 | ||
631 | /* Get the line associated with FUNC_ADDR. */ | |
632 | sal = find_pc_line (func_addr, 0); | |
633 | ||
634 | /* There are only two cases to consider. First, the end of the source line | |
635 | is within the function bounds. In that case we return the end of the | |
636 | source line. Second is the end of the source line extends beyond the | |
637 | bounds of the current function. We need to use the slow code to | |
638 | examine instructions in that case. */ | |
639 | if (sal.end < func_end) | |
640 | return sal.end; | |
641 | else | |
642 | return 0; | |
643 | } | |
644 | ||
645 | /* Here we look at each instruction in the function, and try to guess | |
646 | where the prologue ends. Unfortunately this is not always | |
647 | accurate. */ | |
648 | static CORE_ADDR | |
3bbfbb92 | 649 | sh_skip_prologue_hard_way (CORE_ADDR start_pc) |
c906108c | 650 | { |
2bfa91ee | 651 | CORE_ADDR here, end; |
8db62801 | 652 | int updated_fp = 0; |
2bfa91ee EZ |
653 | |
654 | if (!start_pc) | |
655 | return 0; | |
656 | ||
657 | for (here = start_pc, end = start_pc + (2 * 28); here < end;) | |
c906108c | 658 | { |
2bfa91ee EZ |
659 | int w = read_memory_integer (here, 2); |
660 | here += 2; | |
661 | if (IS_FMOV (w) || IS_PUSH (w) || IS_STS (w) || IS_MOV_R3 (w) | |
8db62801 | 662 | || IS_ADD_R3SP (w) || IS_ADD_SP (w) || IS_SHLL_R3 (w) |
3bbfbb92 | 663 | || IS_ARG_MOV (w) || IS_MOV_TO_R14 (w)) |
2bfa91ee EZ |
664 | { |
665 | start_pc = here; | |
2bfa91ee | 666 | } |
8db62801 EZ |
667 | else if (IS_MOV_SP_FP (w)) |
668 | { | |
669 | start_pc = here; | |
670 | updated_fp = 1; | |
671 | } | |
672 | else | |
673 | /* Don't bail out yet, if we are before the copy of sp. */ | |
674 | if (updated_fp) | |
675 | break; | |
c906108c SS |
676 | } |
677 | ||
678 | return start_pc; | |
679 | } | |
680 | ||
283150cd EZ |
681 | static CORE_ADDR |
682 | look_for_args_moves (CORE_ADDR start_pc, int media_mode) | |
683 | { | |
684 | CORE_ADDR here, end; | |
685 | int w; | |
686 | int insn_size = (media_mode ? 4 : 2); | |
687 | ||
688 | for (here = start_pc, end = start_pc + (insn_size * 28); here < end;) | |
689 | { | |
690 | if (media_mode) | |
691 | { | |
692 | w = read_memory_integer (UNMAKE_ISA32_ADDR (here), insn_size); | |
693 | here += insn_size; | |
694 | if (IS_MEDIA_IND_ARG_MOV (w)) | |
695 | { | |
696 | /* This must be followed by a store to r14, so the argument | |
697 | is where the debug info says it is. This can happen after | |
698 | the SP has been saved, unfortunately. */ | |
699 | ||
700 | int next_insn = read_memory_integer (UNMAKE_ISA32_ADDR (here), | |
701 | insn_size); | |
702 | here += insn_size; | |
703 | if (IS_MEDIA_MOV_TO_R14 (next_insn)) | |
704 | start_pc = here; | |
705 | } | |
706 | else if (IS_MEDIA_ARG_MOV (w)) | |
707 | { | |
708 | /* These instructions store directly the argument in r14. */ | |
709 | start_pc = here; | |
710 | } | |
711 | else | |
712 | break; | |
713 | } | |
714 | else | |
715 | { | |
716 | w = read_memory_integer (here, insn_size); | |
717 | w = w & 0xffff; | |
718 | here += insn_size; | |
719 | if (IS_COMPACT_IND_ARG_MOV (w)) | |
720 | { | |
721 | /* This must be followed by a store to r14, so the argument | |
722 | is where the debug info says it is. This can happen after | |
723 | the SP has been saved, unfortunately. */ | |
724 | ||
725 | int next_insn = 0xffff & read_memory_integer (here, insn_size); | |
726 | here += insn_size; | |
727 | if (IS_COMPACT_MOV_TO_R14 (next_insn)) | |
728 | start_pc = here; | |
729 | } | |
730 | else if (IS_COMPACT_ARG_MOV (w)) | |
731 | { | |
732 | /* These instructions store directly the argument in r14. */ | |
733 | start_pc = here; | |
734 | } | |
735 | else if (IS_MOVL_R0 (w)) | |
736 | { | |
737 | /* There is a function that gcc calls to get the arguments | |
738 | passed correctly to the function. Only after this | |
739 | function call the arguments will be found at the place | |
740 | where they are supposed to be. This happens in case the | |
741 | argument has to be stored into a 64-bit register (for | |
742 | instance doubles, long longs). SHcompact doesn't have | |
743 | access to the full 64-bits, so we store the register in | |
744 | stack slot and store the address of the stack slot in | |
745 | the register, then do a call through a wrapper that | |
746 | loads the memory value into the register. A SHcompact | |
747 | callee calls an argument decoder | |
748 | (GCC_shcompact_incoming_args) that stores the 64-bit | |
749 | value in a stack slot and stores the address of the | |
750 | stack slot in the register. GCC thinks the argument is | |
751 | just passed by transparent reference, but this is only | |
752 | true after the argument decoder is called. Such a call | |
753 | needs to be considered part of the prologue. */ | |
754 | ||
755 | /* This must be followed by a JSR @r0 instruction and by | |
756 | a NOP instruction. After these, the prologue is over! */ | |
757 | ||
758 | int next_insn = 0xffff & read_memory_integer (here, insn_size); | |
759 | here += insn_size; | |
760 | if (IS_JSR_R0 (next_insn)) | |
761 | { | |
762 | next_insn = 0xffff & read_memory_integer (here, insn_size); | |
763 | here += insn_size; | |
764 | ||
765 | if (IS_NOP (next_insn)) | |
766 | start_pc = here; | |
767 | } | |
768 | } | |
769 | else | |
770 | break; | |
771 | } | |
772 | } | |
773 | ||
774 | return start_pc; | |
775 | } | |
776 | ||
777 | static CORE_ADDR | |
778 | sh64_skip_prologue_hard_way (CORE_ADDR start_pc) | |
779 | { | |
780 | CORE_ADDR here, end; | |
781 | int updated_fp = 0; | |
782 | int insn_size = 4; | |
783 | int media_mode = 1; | |
784 | ||
785 | if (!start_pc) | |
786 | return 0; | |
787 | ||
788 | if (pc_is_isa32 (start_pc) == 0) | |
789 | { | |
790 | insn_size = 2; | |
791 | media_mode = 0; | |
792 | } | |
793 | ||
794 | for (here = start_pc, end = start_pc + (insn_size * 28); here < end;) | |
795 | { | |
796 | ||
797 | if (media_mode) | |
798 | { | |
799 | int w = read_memory_integer (UNMAKE_ISA32_ADDR (here), insn_size); | |
800 | here += insn_size; | |
801 | if (IS_STQ_R18_R14 (w) || IS_STQ_R18_R15 (w) || IS_STQ_R14_R15 (w) | |
802 | || IS_STL_R14_R15 (w) || IS_STL_R18_R15 (w) | |
803 | || IS_ADDIL_SP_MEDIA (w) || IS_ADDI_SP_MEDIA (w) || IS_PTABSL_R18 (w)) | |
804 | { | |
805 | start_pc = here; | |
806 | } | |
807 | else if (IS_MOV_SP_FP (w) || IS_MOV_SP_FP_MEDIA(w)) | |
808 | { | |
809 | start_pc = here; | |
810 | updated_fp = 1; | |
811 | } | |
812 | else | |
813 | if (updated_fp) | |
814 | { | |
815 | /* Don't bail out yet, we may have arguments stored in | |
816 | registers here, according to the debug info, so that | |
817 | gdb can print the frames correctly. */ | |
818 | start_pc = look_for_args_moves (here - insn_size, media_mode); | |
819 | break; | |
820 | } | |
821 | } | |
822 | else | |
823 | { | |
824 | int w = 0xffff & read_memory_integer (here, insn_size); | |
825 | here += insn_size; | |
826 | ||
827 | if (IS_STS_R0 (w) || IS_STS_PR (w) | |
828 | || IS_MOV_TO_R15 (w) || IS_MOV_R14 (w) | |
829 | || IS_MOV_R0 (w) || IS_ADD_SP_R0 (w) || IS_MOV_R14_R0 (w)) | |
830 | { | |
831 | start_pc = here; | |
832 | } | |
833 | else if (IS_MOV_SP_FP (w)) | |
834 | { | |
835 | start_pc = here; | |
836 | updated_fp = 1; | |
837 | } | |
838 | else | |
839 | if (updated_fp) | |
840 | { | |
841 | /* Don't bail out yet, we may have arguments stored in | |
842 | registers here, according to the debug info, so that | |
843 | gdb can print the frames correctly. */ | |
844 | start_pc = look_for_args_moves (here - insn_size, media_mode); | |
845 | break; | |
846 | } | |
847 | } | |
848 | } | |
849 | ||
850 | return start_pc; | |
851 | } | |
852 | ||
cc17453a | 853 | static CORE_ADDR |
fba45db2 | 854 | sh_skip_prologue (CORE_ADDR pc) |
8db62801 EZ |
855 | { |
856 | CORE_ADDR post_prologue_pc; | |
857 | ||
858 | /* See if we can determine the end of the prologue via the symbol table. | |
859 | If so, then return either PC, or the PC after the prologue, whichever | |
860 | is greater. */ | |
8db62801 EZ |
861 | post_prologue_pc = after_prologue (pc); |
862 | ||
863 | /* If after_prologue returned a useful address, then use it. Else | |
864 | fall back on the instruction skipping code. */ | |
865 | if (post_prologue_pc != 0) | |
866 | return max (pc, post_prologue_pc); | |
867 | else | |
868 | return (skip_prologue_hard_way (pc)); | |
869 | } | |
870 | ||
cc17453a EZ |
871 | /* Immediately after a function call, return the saved pc. |
872 | Can't always go through the frames for this because on some machines | |
873 | the new frame is not set up until the new function executes | |
874 | some instructions. | |
875 | ||
876 | The return address is the value saved in the PR register + 4 */ | |
877 | static CORE_ADDR | |
fba45db2 | 878 | sh_saved_pc_after_call (struct frame_info *frame) |
cc17453a | 879 | { |
3bbfbb92 | 880 | return (ADDR_BITS_REMOVE (read_register (gdbarch_tdep (current_gdbarch)->PR_REGNUM))); |
cc17453a EZ |
881 | } |
882 | ||
883 | /* Should call_function allocate stack space for a struct return? */ | |
884 | static int | |
fba45db2 | 885 | sh_use_struct_convention (int gcc_p, struct type *type) |
cc17453a | 886 | { |
7079c36c | 887 | #if 0 |
cc17453a | 888 | return (TYPE_LENGTH (type) > 1); |
7079c36c CV |
889 | #else |
890 | int len = TYPE_LENGTH (type); | |
891 | int nelem = TYPE_NFIELDS (type); | |
892 | return ((len != 1 && len != 2 && len != 4 && len != 8) || nelem != 1) && | |
893 | (len != 8 || TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) != 4); | |
894 | #endif | |
cc17453a EZ |
895 | } |
896 | ||
283150cd EZ |
897 | static int |
898 | sh64_use_struct_convention (int gcc_p, struct type *type) | |
899 | { | |
900 | return (TYPE_LENGTH (type) > 8); | |
901 | } | |
902 | ||
cc17453a EZ |
903 | /* Store the address of the place in which to copy the structure the |
904 | subroutine will return. This is called from call_function. | |
905 | ||
3bbfbb92 | 906 | We store structs through a pointer passed in R2 */ |
cc17453a | 907 | static void |
fba45db2 | 908 | sh_store_struct_return (CORE_ADDR addr, CORE_ADDR sp) |
cc17453a EZ |
909 | { |
910 | write_register (STRUCT_RETURN_REGNUM, (addr)); | |
911 | } | |
c906108c | 912 | |
cc17453a EZ |
913 | /* Disassemble an instruction. */ |
914 | static int | |
fba45db2 | 915 | gdb_print_insn_sh (bfd_vma memaddr, disassemble_info *info) |
c906108c | 916 | { |
1c509ca8 JR |
917 | info->endian = TARGET_BYTE_ORDER; |
918 | return print_insn_sh (memaddr, info); | |
283150cd EZ |
919 | } |
920 | ||
c906108c SS |
921 | /* Given a GDB frame, determine the address of the calling function's frame. |
922 | This will be used to create a new GDB frame struct, and then | |
923 | INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame. | |
924 | ||
925 | For us, the frame address is its stack pointer value, so we look up | |
926 | the function prologue to determine the caller's sp value, and return it. */ | |
cc17453a | 927 | static CORE_ADDR |
fba45db2 | 928 | sh_frame_chain (struct frame_info *frame) |
c906108c SS |
929 | { |
930 | if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame)) | |
931 | return frame->frame; /* dummy frame same as caller's frame */ | |
2bfa91ee | 932 | if (frame->pc && !inside_entry_file (frame->pc)) |
cc17453a | 933 | return read_memory_integer (FRAME_FP (frame) + frame->extra_info->f_offset, 4); |
c906108c SS |
934 | else |
935 | return 0; | |
936 | } | |
937 | ||
283150cd EZ |
938 | /* Given a register number RN as it appears in an assembly |
939 | instruction, find the corresponding register number in the GDB | |
940 | scheme. */ | |
941 | static int | |
942 | translate_insn_rn (int rn, int media_mode) | |
943 | { | |
944 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
945 | ||
946 | /* FIXME: this assumes that the number rn is for a not pseudo | |
947 | register only. */ | |
948 | if (media_mode) | |
949 | return rn; | |
950 | else | |
951 | { | |
952 | /* These registers don't have a corresponding compact one. */ | |
953 | /* FIXME: This is probably not enough. */ | |
954 | #if 0 | |
955 | if ((rn >= 16 && rn <= 63) || (rn >= 93 && rn <= 140)) | |
956 | return rn; | |
957 | #endif | |
958 | if (rn >= 0 && rn <= tdep->R0_C_REGNUM) | |
959 | return tdep->R0_C_REGNUM + rn; | |
960 | else | |
961 | return rn; | |
962 | } | |
963 | } | |
964 | ||
965 | static CORE_ADDR | |
966 | sh64_frame_chain (struct frame_info *frame) | |
967 | { | |
968 | if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame)) | |
969 | return frame->frame; /* dummy frame same as caller's frame */ | |
970 | if (frame->pc && !inside_entry_file (frame->pc)) | |
971 | { | |
972 | int media_mode = pc_is_isa32 (frame->pc); | |
973 | int size; | |
974 | if (gdbarch_tdep (current_gdbarch)->sh_abi == SH_ABI_32) | |
975 | size = 4; | |
976 | else | |
977 | size = REGISTER_RAW_SIZE (translate_insn_rn (FP_REGNUM, media_mode)); | |
978 | return read_memory_integer (FRAME_FP (frame) + frame->extra_info->f_offset, size); | |
979 | } | |
980 | else | |
981 | return 0; | |
982 | } | |
983 | ||
c906108c SS |
984 | /* Find REGNUM on the stack. Otherwise, it's in an active register. One thing |
985 | we might want to do here is to check REGNUM against the clobber mask, and | |
986 | somehow flag it as invalid if it isn't saved on the stack somewhere. This | |
987 | would provide a graceful failure mode when trying to get the value of | |
988 | caller-saves registers for an inner frame. */ | |
cc17453a | 989 | static CORE_ADDR |
fba45db2 | 990 | sh_find_callers_reg (struct frame_info *fi, int regnum) |
c906108c | 991 | { |
c906108c SS |
992 | for (; fi; fi = fi->next) |
993 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) | |
994 | /* When the caller requests PR from the dummy frame, we return PC because | |
c5aa993b | 995 | that's where the previous routine appears to have done a call from. */ |
135c175f | 996 | return deprecated_read_register_dummy (fi->pc, fi->frame, regnum); |
c5aa993b | 997 | else |
c906108c | 998 | { |
cc17453a | 999 | FRAME_INIT_SAVED_REGS (fi); |
2bfa91ee EZ |
1000 | if (!fi->pc) |
1001 | return 0; | |
cc17453a EZ |
1002 | if (fi->saved_regs[regnum] != 0) |
1003 | return read_memory_integer (fi->saved_regs[regnum], | |
c5aa993b | 1004 | REGISTER_RAW_SIZE (regnum)); |
c906108c SS |
1005 | } |
1006 | return read_register (regnum); | |
1007 | } | |
1008 | ||
283150cd EZ |
1009 | static CORE_ADDR |
1010 | sh64_get_saved_pr (struct frame_info *fi, int pr_regnum) | |
1011 | { | |
1012 | int media_mode = 0; | |
1013 | ||
1014 | for (; fi; fi = fi->next) | |
1015 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) | |
1016 | /* When the caller requests PR from the dummy frame, we return PC because | |
1017 | that's where the previous routine appears to have done a call from. */ | |
135c175f | 1018 | return deprecated_read_register_dummy (fi->pc, fi->frame, pr_regnum); |
283150cd EZ |
1019 | else |
1020 | { | |
1021 | FRAME_INIT_SAVED_REGS (fi); | |
1022 | if (!fi->pc) | |
1023 | return 0; | |
1024 | ||
1025 | media_mode = pc_is_isa32 (fi->pc); | |
1026 | ||
1027 | if (fi->saved_regs[pr_regnum] != 0) | |
1028 | { | |
1029 | int gdb_reg_num = translate_insn_rn (pr_regnum, media_mode); | |
1030 | int size = ((gdbarch_tdep (current_gdbarch)->sh_abi == SH_ABI_32) | |
1031 | ? 4 | |
1032 | : REGISTER_RAW_SIZE (gdb_reg_num)); | |
1033 | return read_memory_integer (fi->saved_regs[pr_regnum], size); | |
1034 | } | |
1035 | } | |
1036 | return read_register (pr_regnum); | |
1037 | } | |
1038 | ||
c906108c SS |
1039 | /* Put here the code to store, into a struct frame_saved_regs, the |
1040 | addresses of the saved registers of frame described by FRAME_INFO. | |
1041 | This includes special registers such as pc and fp saved in special | |
1042 | ways in the stack frame. sp is even more special: the address we | |
1043 | return for it IS the sp for the next frame. */ | |
cc17453a | 1044 | static void |
fba45db2 | 1045 | sh_nofp_frame_init_saved_regs (struct frame_info *fi) |
c906108c | 1046 | { |
e7d717c0 | 1047 | int *where = (int *) alloca ((NUM_REGS + NUM_PSEUDO_REGS) * sizeof(int)); |
c906108c SS |
1048 | int rn; |
1049 | int have_fp = 0; | |
1050 | int depth; | |
1051 | int pc; | |
1052 | int opc; | |
1053 | int insn; | |
1054 | int r3_val = 0; | |
da130f98 | 1055 | char *dummy_regs = deprecated_generic_find_dummy_frame (fi->pc, fi->frame); |
cc17453a EZ |
1056 | |
1057 | if (fi->saved_regs == NULL) | |
1058 | frame_saved_regs_zalloc (fi); | |
1059 | else | |
1060 | memset (fi->saved_regs, 0, SIZEOF_FRAME_SAVED_REGS); | |
1061 | ||
1062 | if (dummy_regs) | |
1063 | { | |
1064 | /* DANGER! This is ONLY going to work if the char buffer format of | |
1065 | the saved registers is byte-for-byte identical to the | |
1066 | CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */ | |
1067 | memcpy (fi->saved_regs, dummy_regs, sizeof (fi->saved_regs)); | |
1068 | return; | |
1069 | } | |
1070 | ||
1071 | fi->extra_info->leaf_function = 1; | |
1072 | fi->extra_info->f_offset = 0; | |
1073 | ||
cd4bffcf | 1074 | for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++) |
cc17453a EZ |
1075 | where[rn] = -1; |
1076 | ||
1077 | depth = 0; | |
1078 | ||
1079 | /* Loop around examining the prologue insns until we find something | |
1080 | that does not appear to be part of the prologue. But give up | |
1081 | after 20 of them, since we're getting silly then. */ | |
1082 | ||
1083 | pc = get_pc_function_start (fi->pc); | |
1084 | if (!pc) | |
1085 | { | |
1086 | fi->pc = 0; | |
1087 | return; | |
1088 | } | |
1089 | ||
1090 | for (opc = pc + (2 * 28); pc < opc; pc += 2) | |
1091 | { | |
1092 | insn = read_memory_integer (pc, 2); | |
1093 | /* See where the registers will be saved to */ | |
1094 | if (IS_PUSH (insn)) | |
1095 | { | |
1096 | rn = GET_PUSHED_REG (insn); | |
1097 | where[rn] = depth; | |
1098 | depth += 4; | |
1099 | } | |
1100 | else if (IS_STS (insn)) | |
1101 | { | |
3bbfbb92 | 1102 | where[gdbarch_tdep (current_gdbarch)->PR_REGNUM] = depth; |
cc17453a EZ |
1103 | /* If we're storing the pr then this isn't a leaf */ |
1104 | fi->extra_info->leaf_function = 0; | |
1105 | depth += 4; | |
1106 | } | |
1107 | else if (IS_MOV_R3 (insn)) | |
1108 | { | |
1109 | r3_val = ((insn & 0xff) ^ 0x80) - 0x80; | |
1110 | } | |
1111 | else if (IS_SHLL_R3 (insn)) | |
1112 | { | |
1113 | r3_val <<= 1; | |
1114 | } | |
1115 | else if (IS_ADD_R3SP (insn)) | |
1116 | { | |
1117 | depth += -r3_val; | |
1118 | } | |
1119 | else if (IS_ADD_SP (insn)) | |
1120 | { | |
1121 | depth -= ((insn & 0xff) ^ 0x80) - 0x80; | |
1122 | } | |
1123 | else if (IS_MOV_SP_FP (insn)) | |
1124 | break; | |
1125 | #if 0 /* This used to just stop when it found an instruction that | |
1126 | was not considered part of the prologue. Now, we just | |
1127 | keep going looking for likely instructions. */ | |
1128 | else | |
1129 | break; | |
1130 | #endif | |
1131 | } | |
1132 | ||
1133 | /* Now we know how deep things are, we can work out their addresses */ | |
1134 | ||
cd4bffcf | 1135 | for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++) |
cc17453a EZ |
1136 | { |
1137 | if (where[rn] >= 0) | |
1138 | { | |
1139 | if (rn == FP_REGNUM) | |
1140 | have_fp = 1; | |
c906108c | 1141 | |
cc17453a EZ |
1142 | fi->saved_regs[rn] = fi->frame - where[rn] + depth - 4; |
1143 | } | |
1144 | else | |
1145 | { | |
1146 | fi->saved_regs[rn] = 0; | |
1147 | } | |
1148 | } | |
1149 | ||
1150 | if (have_fp) | |
1151 | { | |
1152 | fi->saved_regs[SP_REGNUM] = read_memory_integer (fi->saved_regs[FP_REGNUM], 4); | |
1153 | } | |
1154 | else | |
1155 | { | |
1156 | fi->saved_regs[SP_REGNUM] = fi->frame - 4; | |
1157 | } | |
1158 | ||
1159 | fi->extra_info->f_offset = depth - where[FP_REGNUM] - 4; | |
1160 | /* Work out the return pc - either from the saved pr or the pr | |
1161 | value */ | |
1162 | } | |
1163 | ||
3bbfbb92 EZ |
1164 | /* For vectors of 4 floating point registers. */ |
1165 | static int | |
1166 | fv_reg_base_num (int fv_regnum) | |
1167 | { | |
1168 | int fp_regnum; | |
1169 | ||
1170 | fp_regnum = FP0_REGNUM + | |
1171 | (fv_regnum - gdbarch_tdep (current_gdbarch)->FV0_REGNUM) * 4; | |
1172 | return fp_regnum; | |
1173 | } | |
1174 | ||
1175 | /* For double precision floating point registers, i.e 2 fp regs.*/ | |
1176 | static int | |
1177 | dr_reg_base_num (int dr_regnum) | |
1178 | { | |
1179 | int fp_regnum; | |
1180 | ||
1181 | fp_regnum = FP0_REGNUM + | |
1182 | (dr_regnum - gdbarch_tdep (current_gdbarch)->DR0_REGNUM) * 2; | |
1183 | return fp_regnum; | |
1184 | } | |
1185 | ||
283150cd EZ |
1186 | /* For pairs of floating point registers */ |
1187 | static int | |
1188 | fpp_reg_base_num (int fpp_regnum) | |
1189 | { | |
1190 | int fp_regnum; | |
1191 | ||
1192 | fp_regnum = FP0_REGNUM + | |
1193 | (fpp_regnum - gdbarch_tdep (current_gdbarch)->FPP0_REGNUM) * 2; | |
1194 | return fp_regnum; | |
1195 | } | |
1196 | ||
1197 | static int | |
1198 | is_media_pseudo (int rn) | |
1199 | { | |
1200 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
1201 | ||
1202 | return (rn >= tdep->DR0_REGNUM | |
1203 | && rn <= tdep->FV_LAST_REGNUM); | |
1204 | } | |
1205 | ||
1206 | int | |
1207 | sh64_get_gdb_regnum (int gcc_regnum, CORE_ADDR pc) | |
1208 | { | |
1209 | return translate_insn_rn (gcc_regnum, pc_is_isa32 (pc)); | |
1210 | } | |
1211 | ||
1212 | static int | |
1213 | sh64_media_reg_base_num (int reg_nr) | |
1214 | { | |
1215 | int base_regnum = -1; | |
1216 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
1217 | ||
1218 | if (reg_nr >= tdep->DR0_REGNUM | |
1219 | && reg_nr <= tdep->DR_LAST_REGNUM) | |
1220 | base_regnum = dr_reg_base_num (reg_nr); | |
1221 | ||
1222 | else if (reg_nr >= tdep->FPP0_REGNUM | |
1223 | && reg_nr <= tdep->FPP_LAST_REGNUM) | |
1224 | base_regnum = fpp_reg_base_num (reg_nr); | |
1225 | ||
1226 | else if (reg_nr >= tdep->FV0_REGNUM | |
1227 | && reg_nr <= tdep->FV_LAST_REGNUM) | |
1228 | base_regnum = fv_reg_base_num (reg_nr); | |
1229 | ||
1230 | return base_regnum; | |
1231 | } | |
1232 | ||
1233 | /* *INDENT-OFF* */ | |
1234 | /* | |
1235 | SH COMPACT MODE (ISA 16) (all pseudo) 221-272 | |
1236 | GDB_REGNUM BASE_REGNUM | |
1237 | r0_c 221 0 | |
1238 | r1_c 222 1 | |
1239 | r2_c 223 2 | |
1240 | r3_c 224 3 | |
1241 | r4_c 225 4 | |
1242 | r5_c 226 5 | |
1243 | r6_c 227 6 | |
1244 | r7_c 228 7 | |
1245 | r8_c 229 8 | |
1246 | r9_c 230 9 | |
1247 | r10_c 231 10 | |
1248 | r11_c 232 11 | |
1249 | r12_c 233 12 | |
1250 | r13_c 234 13 | |
1251 | r14_c 235 14 | |
1252 | r15_c 236 15 | |
1253 | ||
1254 | pc_c 237 64 | |
1255 | gbr_c 238 16 | |
1256 | mach_c 239 17 | |
1257 | macl_c 240 17 | |
1258 | pr_c 241 18 | |
1259 | t_c 242 19 | |
1260 | fpscr_c 243 76 | |
1261 | fpul_c 244 109 | |
1262 | ||
1263 | fr0_c 245 77 | |
1264 | fr1_c 246 78 | |
1265 | fr2_c 247 79 | |
1266 | fr3_c 248 80 | |
1267 | fr4_c 249 81 | |
1268 | fr5_c 250 82 | |
1269 | fr6_c 251 83 | |
1270 | fr7_c 252 84 | |
1271 | fr8_c 253 85 | |
1272 | fr9_c 254 86 | |
1273 | fr10_c 255 87 | |
1274 | fr11_c 256 88 | |
1275 | fr12_c 257 89 | |
1276 | fr13_c 258 90 | |
1277 | fr14_c 259 91 | |
1278 | fr15_c 260 92 | |
1279 | ||
1280 | dr0_c 261 77 | |
1281 | dr2_c 262 79 | |
1282 | dr4_c 263 81 | |
1283 | dr6_c 264 83 | |
1284 | dr8_c 265 85 | |
1285 | dr10_c 266 87 | |
1286 | dr12_c 267 89 | |
1287 | dr14_c 268 91 | |
1288 | ||
1289 | fv0_c 269 77 | |
1290 | fv4_c 270 81 | |
1291 | fv8_c 271 85 | |
1292 | fv12_c 272 91 | |
1293 | */ | |
1294 | /* *INDENT-ON* */ | |
1295 | static int | |
1296 | sh64_compact_reg_base_num (int reg_nr) | |
1297 | { | |
1298 | int base_regnum = -1; | |
1299 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
1300 | ||
1301 | /* general register N maps to general register N */ | |
1302 | if (reg_nr >= tdep->R0_C_REGNUM | |
1303 | && reg_nr <= tdep->R_LAST_C_REGNUM) | |
1304 | base_regnum = reg_nr - tdep->R0_C_REGNUM; | |
1305 | ||
1306 | /* floating point register N maps to floating point register N */ | |
1307 | else if (reg_nr >= tdep->FP0_C_REGNUM | |
1308 | && reg_nr <= tdep->FP_LAST_C_REGNUM) | |
1309 | base_regnum = reg_nr - tdep->FP0_C_REGNUM + FP0_REGNUM; | |
1310 | ||
1311 | /* double prec register N maps to base regnum for double prec register N */ | |
1312 | else if (reg_nr >= tdep->DR0_C_REGNUM | |
1313 | && reg_nr <= tdep->DR_LAST_C_REGNUM) | |
1314 | base_regnum = dr_reg_base_num (tdep->DR0_REGNUM | |
1315 | + reg_nr - tdep->DR0_C_REGNUM); | |
1316 | ||
1317 | /* vector N maps to base regnum for vector register N */ | |
1318 | else if (reg_nr >= tdep->FV0_C_REGNUM | |
1319 | && reg_nr <= tdep->FV_LAST_C_REGNUM) | |
1320 | base_regnum = fv_reg_base_num (tdep->FV0_REGNUM | |
1321 | + reg_nr - tdep->FV0_C_REGNUM); | |
1322 | ||
1323 | else if (reg_nr == tdep->PC_C_REGNUM) | |
1324 | base_regnum = PC_REGNUM; | |
1325 | ||
1326 | else if (reg_nr == tdep->GBR_C_REGNUM) | |
1327 | base_regnum = 16; | |
1328 | ||
1329 | else if (reg_nr == tdep->MACH_C_REGNUM | |
1330 | || reg_nr == tdep->MACL_C_REGNUM) | |
1331 | base_regnum = 17; | |
1332 | ||
1333 | else if (reg_nr == tdep->PR_C_REGNUM) | |
1334 | base_regnum = 18; | |
1335 | ||
1336 | else if (reg_nr == tdep->T_C_REGNUM) | |
1337 | base_regnum = 19; | |
1338 | ||
1339 | else if (reg_nr == tdep->FPSCR_C_REGNUM) | |
1340 | base_regnum = tdep->FPSCR_REGNUM; /*???? this register is a mess. */ | |
1341 | ||
1342 | else if (reg_nr == tdep->FPUL_C_REGNUM) | |
1343 | base_regnum = FP0_REGNUM + 32; | |
1344 | ||
1345 | return base_regnum; | |
1346 | } | |
1347 | ||
1348 | /* Given a register number RN (according to the gdb scheme) , return | |
1349 | its corresponding architectural register. In media mode, only a | |
1350 | subset of the registers is pseudo registers. For compact mode, all | |
1351 | the registers are pseudo. */ | |
1352 | static int | |
1353 | translate_rn_to_arch_reg_num (int rn, int media_mode) | |
1354 | { | |
1355 | ||
1356 | if (media_mode) | |
1357 | { | |
1358 | if (!is_media_pseudo (rn)) | |
1359 | return rn; | |
1360 | else | |
1361 | return sh64_media_reg_base_num (rn); | |
1362 | } | |
1363 | else | |
1364 | /* All compact registers are pseudo. */ | |
1365 | return sh64_compact_reg_base_num (rn); | |
1366 | } | |
1367 | ||
1368 | static int | |
1369 | sign_extend (int value, int bits) | |
1370 | { | |
1371 | value = value & ((1 << bits) - 1); | |
1372 | return (value & (1 << (bits - 1)) | |
1373 | ? value | (~((1 << bits) - 1)) | |
1374 | : value); | |
1375 | } | |
1376 | ||
cc17453a | 1377 | static void |
283150cd | 1378 | sh64_nofp_frame_init_saved_regs (struct frame_info *fi) |
cc17453a | 1379 | { |
ddde02bd | 1380 | int *where = (int *) alloca ((NUM_REGS + NUM_PSEUDO_REGS) * sizeof (int)); |
cc17453a EZ |
1381 | int rn; |
1382 | int have_fp = 0; | |
283150cd EZ |
1383 | int fp_regnum; |
1384 | int sp_regnum; | |
1385 | int depth; | |
1386 | int pc; | |
1387 | int opc; | |
1388 | int insn; | |
1389 | int r0_val = 0; | |
1390 | int media_mode = 0; | |
1391 | int insn_size; | |
1392 | int gdb_register_number; | |
1393 | int register_number; | |
da130f98 | 1394 | char *dummy_regs = deprecated_generic_find_dummy_frame (fi->pc, fi->frame); |
283150cd EZ |
1395 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
1396 | ||
1397 | if (fi->saved_regs == NULL) | |
1398 | frame_saved_regs_zalloc (fi); | |
1399 | else | |
1400 | memset (fi->saved_regs, 0, SIZEOF_FRAME_SAVED_REGS); | |
1401 | ||
1402 | if (dummy_regs) | |
1403 | { | |
1404 | /* DANGER! This is ONLY going to work if the char buffer format of | |
1405 | the saved registers is byte-for-byte identical to the | |
1406 | CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */ | |
1407 | memcpy (fi->saved_regs, dummy_regs, sizeof (fi->saved_regs)); | |
1408 | return; | |
1409 | } | |
1410 | ||
1411 | fi->extra_info->leaf_function = 1; | |
1412 | fi->extra_info->f_offset = 0; | |
1413 | ||
1414 | for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++) | |
1415 | where[rn] = -1; | |
1416 | ||
1417 | depth = 0; | |
1418 | ||
1419 | /* Loop around examining the prologue insns until we find something | |
1420 | that does not appear to be part of the prologue. But give up | |
1421 | after 20 of them, since we're getting silly then. */ | |
1422 | ||
1423 | pc = get_pc_function_start (fi->pc); | |
1424 | if (!pc) | |
1425 | { | |
1426 | fi->pc = 0; | |
1427 | return; | |
1428 | } | |
1429 | ||
1430 | if (pc_is_isa32 (pc)) | |
1431 | { | |
1432 | media_mode = 1; | |
1433 | insn_size = 4; | |
1434 | } | |
1435 | else | |
1436 | { | |
1437 | media_mode = 0; | |
1438 | insn_size = 2; | |
1439 | } | |
1440 | ||
1441 | /* The frame pointer register is general register 14 in shmedia and | |
1442 | shcompact modes. In sh compact it is a pseudo register. Same goes | |
1443 | for the stack pointer register, which is register 15. */ | |
1444 | fp_regnum = translate_insn_rn (FP_REGNUM, media_mode); | |
1445 | sp_regnum = translate_insn_rn (SP_REGNUM, media_mode); | |
1446 | ||
1447 | for (opc = pc + (insn_size * 28); pc < opc; pc += insn_size) | |
1448 | { | |
1449 | insn = read_memory_integer (media_mode ? UNMAKE_ISA32_ADDR (pc) : pc, | |
1450 | insn_size); | |
1451 | ||
1452 | if (media_mode == 0) | |
1453 | { | |
1454 | if (IS_STS_PR (insn)) | |
1455 | { | |
1456 | int next_insn = read_memory_integer (pc + insn_size, insn_size); | |
1457 | if (IS_MOV_TO_R15 (next_insn)) | |
1458 | { | |
1459 | int reg_nr = tdep->PR_C_REGNUM; | |
1460 | ||
1461 | where[reg_nr] = depth - ((((next_insn & 0xf) ^ 0x8) - 0x8) << 2); | |
1462 | fi->extra_info->leaf_function = 0; | |
1463 | pc += insn_size; | |
1464 | } | |
1465 | } | |
1466 | else if (IS_MOV_R14 (insn)) | |
1467 | { | |
1468 | where[fp_regnum] = depth - ((((insn & 0xf) ^ 0x8) - 0x8) << 2); | |
1469 | } | |
1470 | ||
1471 | else if (IS_MOV_R0 (insn)) | |
1472 | { | |
1473 | /* Put in R0 the offset from SP at which to store some | |
1474 | registers. We are interested in this value, because it | |
1475 | will tell us where the given registers are stored within | |
1476 | the frame. */ | |
1477 | r0_val = ((insn & 0xff) ^ 0x80) - 0x80; | |
1478 | } | |
1479 | else if (IS_ADD_SP_R0 (insn)) | |
1480 | { | |
1481 | /* This instruction still prepares r0, but we don't care. | |
1482 | We already have the offset in r0_val. */ | |
1483 | } | |
1484 | else if (IS_STS_R0 (insn)) | |
1485 | { | |
1486 | /* Store PR at r0_val-4 from SP. Decrement r0 by 4*/ | |
1487 | int reg_nr = tdep->PR_C_REGNUM; | |
1488 | where[reg_nr] = depth - (r0_val - 4); | |
1489 | r0_val -= 4; | |
1490 | fi->extra_info->leaf_function = 0; | |
1491 | } | |
1492 | else if (IS_MOV_R14_R0 (insn)) | |
1493 | { | |
1494 | /* Store R14 at r0_val-4 from SP. Decrement r0 by 4 */ | |
1495 | where[fp_regnum] = depth - (r0_val - 4); | |
1496 | r0_val -= 4; | |
1497 | } | |
1498 | ||
1499 | else if (IS_ADD_SP (insn)) | |
1500 | { | |
1501 | depth -= ((insn & 0xff) ^ 0x80) - 0x80; | |
1502 | } | |
1503 | else if (IS_MOV_SP_FP (insn)) | |
1504 | break; | |
1505 | } | |
1506 | else | |
1507 | { | |
1508 | if (IS_ADDIL_SP_MEDIA (insn) | |
1509 | || IS_ADDI_SP_MEDIA (insn)) | |
1510 | { | |
1511 | depth -= sign_extend ((((insn & 0xffc00) ^ 0x80000) - 0x80000) >> 10, 9); | |
1512 | } | |
1513 | ||
1514 | else if (IS_STQ_R18_R15 (insn)) | |
1515 | { | |
1516 | where[tdep->PR_REGNUM] = | |
1517 | depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 3); | |
1518 | fi->extra_info->leaf_function = 0; | |
1519 | } | |
1520 | ||
1521 | else if (IS_STL_R18_R15 (insn)) | |
1522 | { | |
1523 | where[tdep->PR_REGNUM] = | |
1524 | depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 2); | |
1525 | fi->extra_info->leaf_function = 0; | |
1526 | } | |
1527 | ||
1528 | else if (IS_STQ_R14_R15 (insn)) | |
1529 | { | |
1530 | where[fp_regnum] = depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 3); | |
1531 | } | |
1532 | ||
1533 | else if (IS_STL_R14_R15 (insn)) | |
1534 | { | |
1535 | where[fp_regnum] = depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 2); | |
1536 | } | |
1537 | ||
1538 | else if (IS_MOV_SP_FP_MEDIA (insn)) | |
1539 | break; | |
1540 | } | |
1541 | } | |
1542 | ||
1543 | /* Now we know how deep things are, we can work out their addresses. */ | |
1544 | for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++) | |
1545 | { | |
1546 | register_number = translate_rn_to_arch_reg_num (rn, media_mode); | |
1547 | ||
1548 | if (where[rn] >= 0) | |
1549 | { | |
1550 | if (rn == fp_regnum) | |
1551 | have_fp = 1; | |
1552 | ||
1553 | /* Watch out! saved_regs is only for the real registers, and | |
1554 | doesn't include space for the pseudo registers. */ | |
1555 | fi->saved_regs[register_number]= fi->frame - where[rn] + depth; | |
1556 | ||
1557 | } | |
1558 | else | |
1559 | fi->saved_regs[register_number] = 0; | |
1560 | } | |
1561 | ||
1562 | if (have_fp) | |
1563 | { | |
1564 | /* SP_REGNUM is 15. For shmedia 15 is the real register. For | |
1565 | shcompact 15 is the arch register corresponding to the pseudo | |
1566 | register r15 which still is the SP register. */ | |
1567 | /* The place on the stack where fp is stored contains the sp of | |
1568 | the caller. */ | |
1569 | /* Again, saved_registers contains only space for the real registers, | |
1570 | so we store in FP_REGNUM position. */ | |
1571 | int size; | |
1572 | if (tdep->sh_abi == SH_ABI_32) | |
1573 | size = 4; | |
1574 | else | |
1575 | size = REGISTER_RAW_SIZE (fp_regnum); | |
1576 | fi->saved_regs[sp_regnum] = read_memory_integer (fi->saved_regs[fp_regnum], size); | |
1577 | } | |
1578 | else | |
1579 | fi->saved_regs[sp_regnum] = fi->frame; | |
1580 | ||
1581 | fi->extra_info->f_offset = depth - where[fp_regnum]; | |
1582 | } | |
1583 | ||
1584 | static void | |
1585 | sh_fp_frame_init_saved_regs (struct frame_info *fi) | |
1586 | { | |
ddde02bd | 1587 | int *where = (int *) alloca ((NUM_REGS + NUM_PSEUDO_REGS) * sizeof (int)); |
283150cd EZ |
1588 | int rn; |
1589 | int have_fp = 0; | |
cc17453a EZ |
1590 | int depth; |
1591 | int pc; | |
1592 | int opc; | |
1593 | int insn; | |
1594 | int r3_val = 0; | |
da130f98 | 1595 | char *dummy_regs = deprecated_generic_find_dummy_frame (fi->pc, fi->frame); |
f81353e4 | 1596 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
cc17453a EZ |
1597 | |
1598 | if (fi->saved_regs == NULL) | |
1599 | frame_saved_regs_zalloc (fi); | |
1600 | else | |
1601 | memset (fi->saved_regs, 0, SIZEOF_FRAME_SAVED_REGS); | |
1602 | ||
c906108c SS |
1603 | if (dummy_regs) |
1604 | { | |
1605 | /* DANGER! This is ONLY going to work if the char buffer format of | |
c5aa993b JM |
1606 | the saved registers is byte-for-byte identical to the |
1607 | CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */ | |
cc17453a | 1608 | memcpy (fi->saved_regs, dummy_regs, sizeof (fi->saved_regs)); |
c906108c SS |
1609 | return; |
1610 | } | |
1611 | ||
cc17453a EZ |
1612 | fi->extra_info->leaf_function = 1; |
1613 | fi->extra_info->f_offset = 0; | |
c906108c | 1614 | |
cd4bffcf | 1615 | for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++) |
c906108c SS |
1616 | where[rn] = -1; |
1617 | ||
1618 | depth = 0; | |
1619 | ||
1620 | /* Loop around examining the prologue insns until we find something | |
1621 | that does not appear to be part of the prologue. But give up | |
1622 | after 20 of them, since we're getting silly then. */ | |
1623 | ||
2bfa91ee EZ |
1624 | pc = get_pc_function_start (fi->pc); |
1625 | if (!pc) | |
c906108c | 1626 | { |
2bfa91ee EZ |
1627 | fi->pc = 0; |
1628 | return; | |
1629 | } | |
1630 | ||
1631 | for (opc = pc + (2 * 28); pc < opc; pc += 2) | |
1632 | { | |
1633 | insn = read_memory_integer (pc, 2); | |
c906108c SS |
1634 | /* See where the registers will be saved to */ |
1635 | if (IS_PUSH (insn)) | |
1636 | { | |
c906108c SS |
1637 | rn = GET_PUSHED_REG (insn); |
1638 | where[rn] = depth; | |
c906108c SS |
1639 | depth += 4; |
1640 | } | |
1641 | else if (IS_STS (insn)) | |
1642 | { | |
f81353e4 | 1643 | where[tdep->PR_REGNUM] = depth; |
c906108c | 1644 | /* If we're storing the pr then this isn't a leaf */ |
cc17453a | 1645 | fi->extra_info->leaf_function = 0; |
c906108c SS |
1646 | depth += 4; |
1647 | } | |
1648 | else if (IS_MOV_R3 (insn)) | |
1649 | { | |
1650 | r3_val = ((insn & 0xff) ^ 0x80) - 0x80; | |
c906108c SS |
1651 | } |
1652 | else if (IS_SHLL_R3 (insn)) | |
1653 | { | |
1654 | r3_val <<= 1; | |
c906108c SS |
1655 | } |
1656 | else if (IS_ADD_R3SP (insn)) | |
1657 | { | |
1658 | depth += -r3_val; | |
c906108c SS |
1659 | } |
1660 | else if (IS_ADD_SP (insn)) | |
1661 | { | |
c906108c | 1662 | depth -= ((insn & 0xff) ^ 0x80) - 0x80; |
c906108c SS |
1663 | } |
1664 | else if (IS_FMOV (insn)) | |
1665 | { | |
f81353e4 | 1666 | if (read_register (tdep->FPSCR_REGNUM) & FPSCR_SZ) |
c906108c SS |
1667 | { |
1668 | depth += 8; | |
1669 | } | |
1670 | else | |
1671 | { | |
1672 | depth += 4; | |
1673 | } | |
1674 | } | |
2bfa91ee EZ |
1675 | else if (IS_MOV_SP_FP (insn)) |
1676 | break; | |
1677 | #if 0 /* This used to just stop when it found an instruction that | |
1678 | was not considered part of the prologue. Now, we just | |
1679 | keep going looking for likely instructions. */ | |
c906108c SS |
1680 | else |
1681 | break; | |
2bfa91ee | 1682 | #endif |
c906108c SS |
1683 | } |
1684 | ||
1685 | /* Now we know how deep things are, we can work out their addresses */ | |
1686 | ||
cd4bffcf | 1687 | for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++) |
c906108c SS |
1688 | { |
1689 | if (where[rn] >= 0) | |
1690 | { | |
1691 | if (rn == FP_REGNUM) | |
1692 | have_fp = 1; | |
1693 | ||
cc17453a | 1694 | fi->saved_regs[rn] = fi->frame - where[rn] + depth - 4; |
c906108c SS |
1695 | } |
1696 | else | |
1697 | { | |
cc17453a | 1698 | fi->saved_regs[rn] = 0; |
c906108c SS |
1699 | } |
1700 | } | |
1701 | ||
1702 | if (have_fp) | |
1703 | { | |
cd4bffcf EZ |
1704 | fi->saved_regs[SP_REGNUM] = |
1705 | read_memory_integer (fi->saved_regs[FP_REGNUM], 4); | |
c906108c SS |
1706 | } |
1707 | else | |
1708 | { | |
cc17453a | 1709 | fi->saved_regs[SP_REGNUM] = fi->frame - 4; |
c906108c SS |
1710 | } |
1711 | ||
cc17453a | 1712 | fi->extra_info->f_offset = depth - where[FP_REGNUM] - 4; |
c906108c SS |
1713 | /* Work out the return pc - either from the saved pr or the pr |
1714 | value */ | |
1715 | } | |
1716 | ||
cc17453a EZ |
1717 | /* Initialize the extra info saved in a FRAME */ |
1718 | static void | |
fba45db2 | 1719 | sh_init_extra_frame_info (int fromleaf, struct frame_info *fi) |
c906108c | 1720 | { |
cc17453a EZ |
1721 | |
1722 | fi->extra_info = (struct frame_extra_info *) | |
1723 | frame_obstack_alloc (sizeof (struct frame_extra_info)); | |
c906108c SS |
1724 | |
1725 | if (fi->next) | |
1726 | fi->pc = FRAME_SAVED_PC (fi->next); | |
1727 | ||
1728 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) | |
1729 | { | |
1730 | /* We need to setup fi->frame here because run_stack_dummy gets it wrong | |
c5aa993b | 1731 | by assuming it's always FP. */ |
135c175f AC |
1732 | fi->frame = deprecated_read_register_dummy (fi->pc, fi->frame, |
1733 | SP_REGNUM); | |
1734 | fi->extra_info->return_pc = deprecated_read_register_dummy (fi->pc, | |
1735 | fi->frame, | |
1736 | PC_REGNUM); | |
cc17453a EZ |
1737 | fi->extra_info->f_offset = -(CALL_DUMMY_LENGTH + 4); |
1738 | fi->extra_info->leaf_function = 0; | |
c906108c SS |
1739 | return; |
1740 | } | |
1741 | else | |
1742 | { | |
cc17453a | 1743 | FRAME_INIT_SAVED_REGS (fi); |
cd4bffcf EZ |
1744 | fi->extra_info->return_pc = |
1745 | sh_find_callers_reg (fi, gdbarch_tdep (current_gdbarch)->PR_REGNUM); | |
c906108c SS |
1746 | } |
1747 | } | |
1748 | ||
283150cd EZ |
1749 | static void |
1750 | sh64_init_extra_frame_info (int fromleaf, struct frame_info *fi) | |
1751 | { | |
1752 | int media_mode = pc_is_isa32 (fi->pc); | |
1753 | ||
1754 | fi->extra_info = (struct frame_extra_info *) | |
1755 | frame_obstack_alloc (sizeof (struct frame_extra_info)); | |
1756 | ||
1757 | if (fi->next) | |
1758 | fi->pc = FRAME_SAVED_PC (fi->next); | |
1759 | ||
1760 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) | |
1761 | { | |
1762 | /* We need to setup fi->frame here because run_stack_dummy gets it wrong | |
1763 | by assuming it's always FP. */ | |
135c175f AC |
1764 | fi->frame = deprecated_read_register_dummy (fi->pc, fi->frame, |
1765 | SP_REGNUM); | |
283150cd | 1766 | fi->extra_info->return_pc = |
135c175f | 1767 | deprecated_read_register_dummy (fi->pc, fi->frame, PC_REGNUM); |
283150cd EZ |
1768 | fi->extra_info->f_offset = -(CALL_DUMMY_LENGTH + 4); |
1769 | fi->extra_info->leaf_function = 0; | |
1770 | return; | |
1771 | } | |
1772 | else | |
1773 | { | |
1774 | FRAME_INIT_SAVED_REGS (fi); | |
1775 | fi->extra_info->return_pc = | |
1776 | sh64_get_saved_pr (fi, gdbarch_tdep (current_gdbarch)->PR_REGNUM); | |
1777 | } | |
1778 | } | |
1779 | ||
1780 | void | |
1781 | sh64_get_saved_register (char *raw_buffer, int *optimized, CORE_ADDR *addrp, | |
1782 | struct frame_info *frame, int regnum, | |
1783 | enum lval_type *lval) | |
1784 | { | |
1785 | int media_mode; | |
1786 | int live_regnum = regnum; | |
1787 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
1788 | ||
1789 | if (!target_has_registers) | |
1790 | error ("No registers."); | |
1791 | ||
1792 | /* Normal systems don't optimize out things with register numbers. */ | |
1793 | if (optimized != NULL) | |
1794 | *optimized = 0; | |
1795 | ||
1796 | if (addrp) /* default assumption: not found in memory */ | |
1797 | *addrp = 0; | |
1798 | ||
1799 | if (raw_buffer) | |
1800 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
1801 | ||
1802 | /* We must do this here, before the following while loop changes | |
1803 | frame, and makes it NULL. If this is a media register number, | |
1804 | but we are in compact mode, it will become the corresponding | |
1805 | compact pseudo register. If there is no corresponding compact | |
1806 | pseudo-register what do we do?*/ | |
1807 | media_mode = pc_is_isa32 (frame->pc); | |
1808 | live_regnum = translate_insn_rn (regnum, media_mode); | |
1809 | ||
1810 | /* Note: since the current frame's registers could only have been | |
1811 | saved by frames INTERIOR TO the current frame, we skip examining | |
1812 | the current frame itself: otherwise, we would be getting the | |
1813 | previous frame's registers which were saved by the current frame. */ | |
1814 | ||
1815 | while (frame && ((frame = frame->next) != NULL)) | |
1816 | { | |
1817 | if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame)) | |
1818 | { | |
1819 | if (lval) /* found it in a CALL_DUMMY frame */ | |
1820 | *lval = not_lval; | |
1821 | if (raw_buffer) | |
1822 | memcpy (raw_buffer, | |
da130f98 AC |
1823 | (deprecated_generic_find_dummy_frame (frame->pc, frame->frame) |
1824 | + REGISTER_BYTE (regnum)), | |
283150cd EZ |
1825 | REGISTER_RAW_SIZE (regnum)); |
1826 | return; | |
1827 | } | |
1828 | ||
1829 | FRAME_INIT_SAVED_REGS (frame); | |
1830 | if (frame->saved_regs != NULL | |
1831 | && frame->saved_regs[regnum] != 0) | |
1832 | { | |
1833 | if (lval) /* found it saved on the stack */ | |
1834 | *lval = lval_memory; | |
1835 | if (regnum == SP_REGNUM) | |
1836 | { | |
1837 | if (raw_buffer) /* SP register treated specially */ | |
1838 | store_address (raw_buffer, REGISTER_RAW_SIZE (regnum), | |
1839 | frame->saved_regs[regnum]); | |
1840 | } | |
1841 | else | |
1842 | { /* any other register */ | |
1843 | ||
1844 | if (addrp) | |
1845 | *addrp = frame->saved_regs[regnum]; | |
1846 | if (raw_buffer) | |
1847 | { | |
1848 | int size; | |
1849 | if (tdep->sh_abi == SH_ABI_32 | |
1850 | && (live_regnum == FP_REGNUM | |
1851 | || live_regnum == tdep->PR_REGNUM)) | |
1852 | size = 4; | |
1853 | else | |
1854 | size = REGISTER_RAW_SIZE (live_regnum); | |
1855 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) | |
1856 | read_memory (frame->saved_regs[regnum], raw_buffer, size); | |
1857 | else | |
1858 | read_memory (frame->saved_regs[regnum], | |
1859 | raw_buffer | |
1860 | + REGISTER_RAW_SIZE (live_regnum) | |
1861 | - size, | |
1862 | size); | |
1863 | } | |
1864 | } | |
1865 | return; | |
1866 | } | |
1867 | } | |
1868 | ||
1869 | /* If we get thru the loop to this point, it means the register was | |
1870 | not saved in any frame. Return the actual live-register value. */ | |
1871 | ||
1872 | if (lval) /* found it in a live register */ | |
1873 | *lval = lval_register; | |
1874 | if (addrp) | |
1875 | *addrp = REGISTER_BYTE (live_regnum); | |
1876 | if (raw_buffer) | |
1877 | read_register_gen (live_regnum, raw_buffer); | |
1878 | } | |
1879 | ||
cc17453a EZ |
1880 | /* Extract from an array REGBUF containing the (raw) register state |
1881 | the address in which a function should return its structure value, | |
1882 | as a CORE_ADDR (or an expression that can be used as one). */ | |
b3df3fff | 1883 | static CORE_ADDR |
0c8053b6 | 1884 | sh_extract_struct_value_address (char *regbuf) |
cc17453a EZ |
1885 | { |
1886 | return (extract_address ((regbuf), REGISTER_RAW_SIZE (0))); | |
1887 | } | |
1888 | ||
283150cd EZ |
1889 | static CORE_ADDR |
1890 | sh64_extract_struct_value_address (char *regbuf) | |
1891 | { | |
1892 | return (extract_address ((regbuf + REGISTER_BYTE (STRUCT_RETURN_REGNUM)), | |
1893 | REGISTER_RAW_SIZE (STRUCT_RETURN_REGNUM))); | |
1894 | } | |
1895 | ||
cc17453a | 1896 | static CORE_ADDR |
fba45db2 | 1897 | sh_frame_saved_pc (struct frame_info *frame) |
cc17453a EZ |
1898 | { |
1899 | return ((frame)->extra_info->return_pc); | |
1900 | } | |
1901 | ||
c906108c SS |
1902 | /* Discard from the stack the innermost frame, |
1903 | restoring all saved registers. */ | |
cc17453a | 1904 | static void |
fba45db2 | 1905 | sh_pop_frame (void) |
c906108c SS |
1906 | { |
1907 | register struct frame_info *frame = get_current_frame (); | |
1908 | register CORE_ADDR fp; | |
1909 | register int regnum; | |
c906108c SS |
1910 | |
1911 | if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame)) | |
1912 | generic_pop_dummy_frame (); | |
1913 | else | |
c5aa993b JM |
1914 | { |
1915 | fp = FRAME_FP (frame); | |
cc17453a | 1916 | FRAME_INIT_SAVED_REGS (frame); |
c906108c | 1917 | |
c5aa993b | 1918 | /* Copy regs from where they were saved in the frame */ |
cd4bffcf | 1919 | for (regnum = 0; regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++) |
cc17453a | 1920 | if (frame->saved_regs[regnum]) |
cd4bffcf EZ |
1921 | write_register (regnum, |
1922 | read_memory_integer (frame->saved_regs[regnum], 4)); | |
c906108c | 1923 | |
cc17453a | 1924 | write_register (PC_REGNUM, frame->extra_info->return_pc); |
c5aa993b JM |
1925 | write_register (SP_REGNUM, fp + 4); |
1926 | } | |
c906108c SS |
1927 | flush_cached_frames (); |
1928 | } | |
1929 | ||
283150cd EZ |
1930 | /* Used in the 'return' command. */ |
1931 | static void | |
1932 | sh64_pop_frame (void) | |
1933 | { | |
1934 | register struct frame_info *frame = get_current_frame (); | |
1935 | register CORE_ADDR fp; | |
1936 | register int regnum; | |
1937 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
1938 | ||
1939 | int media_mode = pc_is_isa32 (frame->pc); | |
1940 | ||
1941 | if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame)) | |
1942 | generic_pop_dummy_frame (); | |
1943 | else | |
1944 | { | |
1945 | fp = FRAME_FP (frame); | |
1946 | FRAME_INIT_SAVED_REGS (frame); | |
1947 | ||
1948 | /* Copy regs from where they were saved in the frame */ | |
1949 | for (regnum = 0; regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++) | |
1950 | if (frame->saved_regs[regnum]) | |
1951 | { | |
1952 | int size; | |
1953 | if (tdep->sh_abi == SH_ABI_32 | |
1954 | && (regnum == FP_REGNUM | |
1955 | || regnum == tdep->PR_REGNUM)) | |
1956 | size = 4; | |
1957 | else | |
1958 | size = REGISTER_RAW_SIZE (translate_insn_rn (regnum, | |
1959 | media_mode)); | |
1960 | write_register (regnum, | |
1961 | read_memory_integer (frame->saved_regs[regnum], | |
1962 | size)); | |
1963 | } | |
1964 | ||
1965 | write_register (PC_REGNUM, frame->extra_info->return_pc); | |
1966 | write_register (SP_REGNUM, fp + 8); | |
1967 | } | |
1968 | flush_cached_frames (); | |
1969 | } | |
1970 | ||
c906108c SS |
1971 | /* Function: push_arguments |
1972 | Setup the function arguments for calling a function in the inferior. | |
1973 | ||
1974 | On the Hitachi SH architecture, there are four registers (R4 to R7) | |
1975 | which are dedicated for passing function arguments. Up to the first | |
1976 | four arguments (depending on size) may go into these registers. | |
1977 | The rest go on the stack. | |
1978 | ||
1979 | Arguments that are smaller than 4 bytes will still take up a whole | |
1980 | register or a whole 32-bit word on the stack, and will be | |
1981 | right-justified in the register or the stack word. This includes | |
1982 | chars, shorts, and small aggregate types. | |
1983 | ||
1984 | Arguments that are larger than 4 bytes may be split between two or | |
1985 | more registers. If there are not enough registers free, an argument | |
1986 | may be passed partly in a register (or registers), and partly on the | |
1987 | stack. This includes doubles, long longs, and larger aggregates. | |
1988 | As far as I know, there is no upper limit to the size of aggregates | |
1989 | that will be passed in this way; in other words, the convention of | |
1990 | passing a pointer to a large aggregate instead of a copy is not used. | |
1991 | ||
1992 | An exceptional case exists for struct arguments (and possibly other | |
1993 | aggregates such as arrays) if the size is larger than 4 bytes but | |
1994 | not a multiple of 4 bytes. In this case the argument is never split | |
1995 | between the registers and the stack, but instead is copied in its | |
1996 | entirety onto the stack, AND also copied into as many registers as | |
1997 | there is room for. In other words, space in registers permitting, | |
1998 | two copies of the same argument are passed in. As far as I can tell, | |
1999 | only the one on the stack is used, although that may be a function | |
2000 | of the level of compiler optimization. I suspect this is a compiler | |
2001 | bug. Arguments of these odd sizes are left-justified within the | |
2002 | word (as opposed to arguments smaller than 4 bytes, which are | |
2003 | right-justified). | |
c5aa993b | 2004 | |
c906108c SS |
2005 | If the function is to return an aggregate type such as a struct, it |
2006 | is either returned in the normal return value register R0 (if its | |
2007 | size is no greater than one byte), or else the caller must allocate | |
2008 | space into which the callee will copy the return value (if the size | |
2009 | is greater than one byte). In this case, a pointer to the return | |
2010 | value location is passed into the callee in register R2, which does | |
2011 | not displace any of the other arguments passed in via registers R4 | |
2012 | to R7. */ | |
2013 | ||
cc17453a | 2014 | static CORE_ADDR |
34e9d9bb | 2015 | sh_push_arguments (int nargs, struct value **args, CORE_ADDR sp, |
3bbfbb92 | 2016 | int struct_return, CORE_ADDR struct_addr) |
c906108c SS |
2017 | { |
2018 | int stack_offset, stack_alloc; | |
2019 | int argreg; | |
2020 | int argnum; | |
2021 | struct type *type; | |
2022 | CORE_ADDR regval; | |
2023 | char *val; | |
2024 | char valbuf[4]; | |
2025 | int len; | |
2026 | int odd_sized_struct; | |
f81353e4 | 2027 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
c906108c SS |
2028 | |
2029 | /* first force sp to a 4-byte alignment */ | |
2030 | sp = sp & ~3; | |
2031 | ||
2032 | /* The "struct return pointer" pseudo-argument has its own dedicated | |
2033 | register */ | |
2034 | if (struct_return) | |
c5aa993b | 2035 | write_register (STRUCT_RETURN_REGNUM, struct_addr); |
c906108c SS |
2036 | |
2037 | /* Now make sure there's space on the stack */ | |
cc17453a | 2038 | for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++) |
c5aa993b JM |
2039 | stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 3) & ~3); |
2040 | sp -= stack_alloc; /* make room on stack for args */ | |
c906108c | 2041 | |
c906108c SS |
2042 | /* Now load as many as possible of the first arguments into |
2043 | registers, and push the rest onto the stack. There are 16 bytes | |
2044 | in four registers available. Loop thru args from first to last. */ | |
2045 | ||
f81353e4 | 2046 | argreg = tdep->ARG0_REGNUM; |
c906108c SS |
2047 | for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++) |
2048 | { | |
2049 | type = VALUE_TYPE (args[argnum]); | |
c5aa993b JM |
2050 | len = TYPE_LENGTH (type); |
2051 | memset (valbuf, 0, sizeof (valbuf)); | |
c906108c | 2052 | if (len < 4) |
cc17453a EZ |
2053 | { |
2054 | /* value gets right-justified in the register or stack word */ | |
7079c36c CV |
2055 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
2056 | memcpy (valbuf + (4 - len), | |
2057 | (char *) VALUE_CONTENTS (args[argnum]), len); | |
2058 | else | |
2059 | memcpy (valbuf, (char *) VALUE_CONTENTS (args[argnum]), len); | |
c5aa993b JM |
2060 | val = valbuf; |
2061 | } | |
c906108c | 2062 | else |
c5aa993b | 2063 | val = (char *) VALUE_CONTENTS (args[argnum]); |
c906108c SS |
2064 | |
2065 | if (len > 4 && (len & 3) != 0) | |
c5aa993b JM |
2066 | odd_sized_struct = 1; /* such structs go entirely on stack */ |
2067 | else | |
c906108c SS |
2068 | odd_sized_struct = 0; |
2069 | while (len > 0) | |
2070 | { | |
f81353e4 | 2071 | if (argreg > tdep->ARGLAST_REGNUM |
3bbfbb92 EZ |
2072 | || odd_sized_struct) |
2073 | { | |
2074 | /* must go on the stack */ | |
c906108c SS |
2075 | write_memory (sp + stack_offset, val, 4); |
2076 | stack_offset += 4; | |
2077 | } | |
2078 | /* NOTE WELL!!!!! This is not an "else if" clause!!! | |
2079 | That's because some *&^%$ things get passed on the stack | |
2080 | AND in the registers! */ | |
f81353e4 | 2081 | if (argreg <= tdep->ARGLAST_REGNUM) |
3bbfbb92 EZ |
2082 | { |
2083 | /* there's room in a register */ | |
c5aa993b | 2084 | regval = extract_address (val, REGISTER_RAW_SIZE (argreg)); |
c906108c SS |
2085 | write_register (argreg++, regval); |
2086 | } | |
2087 | /* Store the value 4 bytes at a time. This means that things | |
2088 | larger than 4 bytes may go partly in registers and partly | |
2089 | on the stack. */ | |
c5aa993b JM |
2090 | len -= REGISTER_RAW_SIZE (argreg); |
2091 | val += REGISTER_RAW_SIZE (argreg); | |
c906108c SS |
2092 | } |
2093 | } | |
2094 | return sp; | |
2095 | } | |
2096 | ||
283150cd EZ |
2097 | /* R2-R9 for integer types and integer equivalent (char, pointers) and |
2098 | non-scalar (struct, union) elements (even if the elements are | |
2099 | floats). | |
2100 | FR0-FR11 for single precision floating point (float) | |
2101 | DR0-DR10 for double precision floating point (double) | |
2102 | ||
2103 | If a float is argument number 3 (for instance) and arguments number | |
2104 | 1,2, and 4 are integer, the mapping will be: | |
2105 | arg1 -->R2, arg2 --> R3, arg3 -->FR0, arg4 --> R5. I.e. R4 is not used. | |
2106 | ||
2107 | If a float is argument number 10 (for instance) and arguments number | |
2108 | 1 through 10 are integer, the mapping will be: | |
2109 | arg1->R2, arg2->R3, arg3->R4, arg4->R5, arg5->R6, arg6->R7, arg7->R8, | |
2110 | arg8->R9, arg9->(0,SP)stack(8-byte aligned), arg10->FR0, arg11->stack(16,SP). | |
2111 | I.e. there is hole in the stack. | |
2112 | ||
2113 | Different rules apply for variable arguments functions, and for functions | |
2114 | for which the prototype is not known. */ | |
2115 | ||
2116 | static CORE_ADDR | |
2117 | sh64_push_arguments (int nargs, struct value **args, CORE_ADDR sp, | |
2118 | int struct_return, CORE_ADDR struct_addr) | |
2119 | { | |
2120 | int stack_offset, stack_alloc; | |
2121 | int int_argreg; | |
2122 | int float_argreg; | |
2123 | int double_argreg; | |
2124 | int float_arg_index = 0; | |
2125 | int double_arg_index = 0; | |
2126 | int argnum; | |
2127 | struct type *type; | |
2128 | CORE_ADDR regval; | |
2129 | char *val; | |
2130 | char valbuf[8]; | |
2131 | char valbuf_tmp[8]; | |
2132 | int len; | |
2133 | int argreg_size; | |
2134 | int fp_args[12]; | |
2135 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2136 | ||
2137 | memset (fp_args, 0, sizeof (fp_args)); | |
2138 | ||
2139 | /* first force sp to a 8-byte alignment */ | |
2140 | sp = sp & ~7; | |
2141 | ||
2142 | /* The "struct return pointer" pseudo-argument has its own dedicated | |
2143 | register */ | |
2144 | ||
2145 | if (struct_return) | |
2146 | write_register (STRUCT_RETURN_REGNUM, struct_addr); | |
2147 | ||
2148 | /* Now make sure there's space on the stack */ | |
2149 | for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++) | |
2150 | stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 7) & ~7); | |
2151 | sp -= stack_alloc; /* make room on stack for args */ | |
2152 | ||
2153 | /* Now load as many as possible of the first arguments into | |
2154 | registers, and push the rest onto the stack. There are 64 bytes | |
2155 | in eight registers available. Loop thru args from first to last. */ | |
2156 | ||
2157 | int_argreg = tdep->ARG0_REGNUM; | |
2158 | float_argreg = FP0_REGNUM; | |
2159 | double_argreg = tdep->DR0_REGNUM; | |
2160 | ||
2161 | for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++) | |
2162 | { | |
2163 | type = VALUE_TYPE (args[argnum]); | |
2164 | len = TYPE_LENGTH (type); | |
2165 | memset (valbuf, 0, sizeof (valbuf)); | |
2166 | ||
2167 | if (TYPE_CODE (type) != TYPE_CODE_FLT) | |
2168 | { | |
2169 | argreg_size = REGISTER_RAW_SIZE (int_argreg); | |
2170 | ||
2171 | if (len < argreg_size) | |
2172 | { | |
2173 | /* value gets right-justified in the register or stack word */ | |
2174 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
2175 | memcpy (valbuf + argreg_size - len, | |
2176 | (char *) VALUE_CONTENTS (args[argnum]), len); | |
2177 | else | |
2178 | memcpy (valbuf, (char *) VALUE_CONTENTS (args[argnum]), len); | |
2179 | ||
2180 | val = valbuf; | |
2181 | } | |
2182 | else | |
2183 | val = (char *) VALUE_CONTENTS (args[argnum]); | |
2184 | ||
2185 | while (len > 0) | |
2186 | { | |
2187 | if (int_argreg > tdep->ARGLAST_REGNUM) | |
2188 | { | |
2189 | /* must go on the stack */ | |
2190 | write_memory (sp + stack_offset, val, argreg_size); | |
2191 | stack_offset += 8;/*argreg_size;*/ | |
2192 | } | |
2193 | /* NOTE WELL!!!!! This is not an "else if" clause!!! | |
2194 | That's because some *&^%$ things get passed on the stack | |
2195 | AND in the registers! */ | |
2196 | if (int_argreg <= tdep->ARGLAST_REGNUM) | |
2197 | { | |
2198 | /* there's room in a register */ | |
2199 | regval = extract_address (val, argreg_size); | |
2200 | write_register (int_argreg, regval); | |
2201 | } | |
2202 | /* Store the value 8 bytes at a time. This means that | |
2203 | things larger than 8 bytes may go partly in registers | |
2204 | and partly on the stack. FIXME: argreg is incremented | |
2205 | before we use its size. */ | |
2206 | len -= argreg_size; | |
2207 | val += argreg_size; | |
2208 | int_argreg++; | |
2209 | } | |
2210 | } | |
2211 | else | |
2212 | { | |
2213 | val = (char *) VALUE_CONTENTS (args[argnum]); | |
2214 | if (len == 4) | |
2215 | { | |
2216 | /* Where is it going to be stored? */ | |
2217 | while (fp_args[float_arg_index]) | |
2218 | float_arg_index ++; | |
2219 | ||
2220 | /* Now float_argreg points to the register where it | |
2221 | should be stored. Are we still within the allowed | |
2222 | register set? */ | |
2223 | if (float_arg_index <= tdep->FLOAT_ARGLAST_REGNUM) | |
2224 | { | |
2225 | /* Goes in FR0...FR11 */ | |
2226 | write_register_gen (FP0_REGNUM + float_arg_index, val); | |
2227 | fp_args[float_arg_index] = 1; | |
2228 | /* Skip the corresponding general argument register. */ | |
2229 | int_argreg ++; | |
2230 | } | |
2231 | else | |
2232 | ; | |
2233 | /* Store it as the integers, 8 bytes at the time, if | |
2234 | necessary spilling on the stack. */ | |
2235 | ||
2236 | } | |
2237 | else if (len == 8) | |
2238 | { | |
2239 | /* Where is it going to be stored? */ | |
2240 | while (fp_args[double_arg_index]) | |
2241 | double_arg_index += 2; | |
2242 | /* Now double_argreg points to the register | |
2243 | where it should be stored. | |
2244 | Are we still within the allowed register set? */ | |
2245 | if (double_arg_index < tdep->FLOAT_ARGLAST_REGNUM) | |
2246 | { | |
2247 | /* Goes in DR0...DR10 */ | |
2248 | /* The numbering of the DRi registers is consecutive, | |
2249 | i.e. includes odd numbers. */ | |
2250 | int double_register_offset = double_arg_index / 2; | |
2251 | int regnum = tdep->DR0_REGNUM + | |
2252 | double_register_offset; | |
2253 | #if 0 | |
2254 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) | |
2255 | { | |
2256 | memset (valbuf_tmp, 0, sizeof (valbuf_tmp)); | |
2257 | REGISTER_CONVERT_TO_VIRTUAL (regnum, | |
2258 | type, val, valbuf_tmp); | |
2259 | val = valbuf_tmp; | |
2260 | } | |
2261 | #endif | |
2262 | /* Note: must use write_register_gen here instead | |
0818c12a AC |
2263 | of regcache_raw_write, because |
2264 | regcache_raw_write works only for real | |
2265 | registers, not pseudo. write_register_gen will | |
2266 | call the gdbarch function to do register | |
2267 | writes, and that will properly know how to deal | |
2268 | with pseudoregs. */ | |
283150cd EZ |
2269 | write_register_gen (regnum, val); |
2270 | fp_args[double_arg_index] = 1; | |
2271 | fp_args[double_arg_index + 1] = 1; | |
2272 | /* Skip the corresponding general argument register. */ | |
2273 | int_argreg ++; | |
2274 | } | |
2275 | else | |
2276 | ; | |
2277 | /* Store it as the integers, 8 bytes at the time, if | |
2278 | necessary spilling on the stack. */ | |
2279 | } | |
2280 | } | |
2281 | } | |
2282 | return sp; | |
2283 | } | |
2284 | ||
c906108c SS |
2285 | /* Function: push_return_address (pc) |
2286 | Set up the return address for the inferior function call. | |
2287 | Needed for targets where we don't actually execute a JSR/BSR instruction */ | |
2288 | ||
cc17453a | 2289 | static CORE_ADDR |
fba45db2 | 2290 | sh_push_return_address (CORE_ADDR pc, CORE_ADDR sp) |
c906108c | 2291 | { |
283150cd EZ |
2292 | write_register (gdbarch_tdep (current_gdbarch)->PR_REGNUM, |
2293 | CALL_DUMMY_ADDRESS ()); | |
c906108c SS |
2294 | return sp; |
2295 | } | |
2296 | ||
2297 | /* Function: fix_call_dummy | |
2298 | Poke the callee function's address into the destination part of | |
2299 | the CALL_DUMMY. The address is actually stored in a data word | |
2300 | following the actualy CALL_DUMMY instructions, which will load | |
2301 | it into a register using PC-relative addressing. This function | |
2302 | expects the CALL_DUMMY to look like this: | |
2303 | ||
c5aa993b JM |
2304 | mov.w @(2,PC), R8 |
2305 | jsr @R8 | |
2306 | nop | |
2307 | trap | |
2308 | <destination> | |
2309 | */ | |
c906108c SS |
2310 | |
2311 | #if 0 | |
2312 | void | |
fba45db2 | 2313 | sh_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, int nargs, |
ea7c478f | 2314 | struct value **args, struct type *type, int gcc_p) |
c906108c SS |
2315 | { |
2316 | *(unsigned long *) (dummy + 8) = fun; | |
2317 | } | |
2318 | #endif | |
2319 | ||
cc17453a EZ |
2320 | static int |
2321 | sh_coerce_float_to_double (struct type *formal, struct type *actual) | |
2322 | { | |
2323 | return 1; | |
2324 | } | |
c906108c | 2325 | |
cc17453a EZ |
2326 | /* Find a function's return value in the appropriate registers (in |
2327 | regbuf), and copy it into valbuf. Extract from an array REGBUF | |
2328 | containing the (raw) register state a function return value of type | |
2329 | TYPE, and copy that, in virtual format, into VALBUF. */ | |
2330 | static void | |
fba45db2 | 2331 | sh_extract_return_value (struct type *type, char *regbuf, char *valbuf) |
c906108c | 2332 | { |
cc17453a | 2333 | int len = TYPE_LENGTH (type); |
3116c80a EZ |
2334 | int return_register = R0_REGNUM; |
2335 | int offset; | |
2336 | ||
cc17453a | 2337 | if (len <= 4) |
3116c80a | 2338 | { |
d7449b42 | 2339 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
3116c80a EZ |
2340 | offset = REGISTER_BYTE (return_register) + 4 - len; |
2341 | else | |
2342 | offset = REGISTER_BYTE (return_register); | |
2343 | memcpy (valbuf, regbuf + offset, len); | |
2344 | } | |
cc17453a | 2345 | else if (len <= 8) |
3116c80a | 2346 | { |
d7449b42 | 2347 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
3116c80a EZ |
2348 | offset = REGISTER_BYTE (return_register) + 8 - len; |
2349 | else | |
2350 | offset = REGISTER_BYTE (return_register); | |
2351 | memcpy (valbuf, regbuf + offset, len); | |
2352 | } | |
2353 | else | |
2354 | error ("bad size for return value"); | |
2355 | } | |
2356 | ||
2357 | static void | |
2358 | sh3e_sh4_extract_return_value (struct type *type, char *regbuf, char *valbuf) | |
2359 | { | |
2360 | int return_register; | |
2361 | int offset; | |
2362 | int len = TYPE_LENGTH (type); | |
2363 | ||
2364 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
2365 | return_register = FP0_REGNUM; | |
2366 | else | |
2367 | return_register = R0_REGNUM; | |
2368 | ||
2369 | if (len == 8 && TYPE_CODE (type) == TYPE_CODE_FLT) | |
2370 | { | |
2371 | DOUBLEST val; | |
778eb05e | 2372 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) |
3116c80a EZ |
2373 | floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, |
2374 | (char *) regbuf + REGISTER_BYTE (return_register), | |
2375 | &val); | |
2376 | else | |
2377 | floatformat_to_doublest (&floatformat_ieee_double_big, | |
2378 | (char *) regbuf + REGISTER_BYTE (return_register), | |
2379 | &val); | |
2380 | store_floating (valbuf, len, val); | |
2381 | } | |
2382 | else if (len <= 4) | |
2383 | { | |
d7449b42 | 2384 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
3116c80a EZ |
2385 | offset = REGISTER_BYTE (return_register) + 4 - len; |
2386 | else | |
2387 | offset = REGISTER_BYTE (return_register); | |
2388 | memcpy (valbuf, regbuf + offset, len); | |
2389 | } | |
2390 | else if (len <= 8) | |
2391 | { | |
d7449b42 | 2392 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
3116c80a EZ |
2393 | offset = REGISTER_BYTE (return_register) + 8 - len; |
2394 | else | |
2395 | offset = REGISTER_BYTE (return_register); | |
2396 | memcpy (valbuf, regbuf + offset, len); | |
2397 | } | |
cc17453a EZ |
2398 | else |
2399 | error ("bad size for return value"); | |
2400 | } | |
c906108c | 2401 | |
283150cd EZ |
2402 | static void |
2403 | sh64_extract_return_value (struct type *type, char *regbuf, char *valbuf) | |
2404 | { | |
2405 | int offset; | |
2406 | int return_register; | |
2407 | int len = TYPE_LENGTH (type); | |
2408 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2409 | ||
2410 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
2411 | { | |
2412 | if (len == 4) | |
2413 | { | |
2414 | /* Return value stored in FP0_REGNUM */ | |
2415 | return_register = FP0_REGNUM; | |
2416 | offset = REGISTER_BYTE (return_register); | |
2417 | memcpy (valbuf, (char *) regbuf + offset, len); | |
2418 | } | |
2419 | else if (len == 8) | |
2420 | { | |
2421 | /* return value stored in DR0_REGNUM */ | |
2422 | DOUBLEST val; | |
2423 | ||
2424 | return_register = tdep->DR0_REGNUM; | |
2425 | offset = REGISTER_BYTE (return_register); | |
2426 | ||
2427 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) | |
2428 | floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, | |
2429 | (char *) regbuf + offset, &val); | |
2430 | else | |
2431 | floatformat_to_doublest (&floatformat_ieee_double_big, | |
2432 | (char *) regbuf + offset, &val); | |
2433 | store_floating (valbuf, len, val); | |
2434 | } | |
2435 | } | |
2436 | else | |
2437 | { | |
2438 | if (len <= 8) | |
2439 | { | |
2440 | /* Result is in register 2. If smaller than 8 bytes, it is padded | |
2441 | at the most significant end. */ | |
2442 | return_register = tdep->RETURN_REGNUM; | |
2443 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
2444 | offset = REGISTER_BYTE (return_register) + | |
2445 | REGISTER_RAW_SIZE (return_register) - len; | |
2446 | else | |
2447 | offset = REGISTER_BYTE (return_register); | |
2448 | memcpy (valbuf, (char *) regbuf + offset, len); | |
2449 | } | |
2450 | else | |
2451 | error ("bad size for return value"); | |
2452 | } | |
2453 | } | |
2454 | ||
cc17453a EZ |
2455 | /* Write into appropriate registers a function return value |
2456 | of type TYPE, given in virtual format. | |
2457 | If the architecture is sh4 or sh3e, store a function's return value | |
2458 | in the R0 general register or in the FP0 floating point register, | |
2459 | depending on the type of the return value. In all the other cases | |
3bbfbb92 | 2460 | the result is stored in r0, left-justified. */ |
cc17453a EZ |
2461 | static void |
2462 | sh_default_store_return_value (struct type *type, char *valbuf) | |
2463 | { | |
d19b71be MS |
2464 | char buf[32]; /* more than enough... */ |
2465 | ||
2466 | if (TYPE_LENGTH (type) < REGISTER_RAW_SIZE (R0_REGNUM)) | |
2467 | { | |
2468 | /* Add leading zeros to the value. */ | |
2469 | memset (buf, 0, REGISTER_RAW_SIZE (R0_REGNUM)); | |
7079c36c CV |
2470 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
2471 | memcpy (buf + REGISTER_RAW_SIZE (R0_REGNUM) - TYPE_LENGTH (type), | |
2472 | valbuf, TYPE_LENGTH (type)); | |
2473 | else | |
2474 | memcpy (buf, valbuf, TYPE_LENGTH (type)); | |
d19b71be MS |
2475 | write_register_bytes (REGISTER_BYTE (R0_REGNUM), buf, |
2476 | REGISTER_RAW_SIZE (R0_REGNUM)); | |
2477 | } | |
2478 | else | |
2479 | write_register_bytes (REGISTER_BYTE (R0_REGNUM), valbuf, | |
2480 | TYPE_LENGTH (type)); | |
cc17453a | 2481 | } |
c906108c | 2482 | |
cc17453a EZ |
2483 | static void |
2484 | sh3e_sh4_store_return_value (struct type *type, char *valbuf) | |
2485 | { | |
2486 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
2487 | write_register_bytes (REGISTER_BYTE (FP0_REGNUM), | |
2488 | valbuf, TYPE_LENGTH (type)); | |
2489 | else | |
d19b71be | 2490 | sh_default_store_return_value (type, valbuf); |
c906108c SS |
2491 | } |
2492 | ||
283150cd EZ |
2493 | static void |
2494 | sh64_store_return_value (struct type *type, char *valbuf) | |
2495 | { | |
2496 | char buf[64]; /* more than enough... */ | |
2497 | int len = TYPE_LENGTH (type); | |
2498 | ||
2499 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
2500 | { | |
2501 | if (len == 4) | |
2502 | { | |
2503 | /* Return value stored in FP0_REGNUM */ | |
2504 | write_register_gen (FP0_REGNUM, valbuf); | |
2505 | } | |
2506 | if (len == 8) | |
2507 | { | |
2508 | /* return value stored in DR0_REGNUM */ | |
2509 | /* FIXME: Implement */ | |
2510 | } | |
2511 | } | |
2512 | else | |
2513 | { | |
2514 | int return_register = gdbarch_tdep (current_gdbarch)->RETURN_REGNUM; | |
2515 | int offset = 0; | |
2516 | ||
2517 | if (len <= REGISTER_RAW_SIZE (return_register)) | |
2518 | { | |
2519 | /* Pad with zeros. */ | |
2520 | memset (buf, 0, REGISTER_RAW_SIZE (return_register)); | |
2521 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) | |
2522 | offset = 0; /*REGISTER_RAW_SIZE (return_register) - len;*/ | |
2523 | else | |
2524 | offset = REGISTER_RAW_SIZE (return_register) - len; | |
2525 | ||
2526 | memcpy (buf + offset, valbuf, len); | |
2527 | write_register_gen (return_register, buf); | |
2528 | } | |
2529 | else | |
2530 | write_register_gen (return_register, valbuf); | |
2531 | } | |
2532 | } | |
2533 | ||
c906108c SS |
2534 | /* Print the registers in a form similar to the E7000 */ |
2535 | ||
2536 | static void | |
fba45db2 | 2537 | sh_generic_show_regs (void) |
c906108c | 2538 | { |
f81353e4 EZ |
2539 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2540 | ||
cc17453a EZ |
2541 | printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", |
2542 | paddr (read_register (PC_REGNUM)), | |
f81353e4 EZ |
2543 | (long) read_register (tdep->SR_REGNUM), |
2544 | (long) read_register (tdep->PR_REGNUM), | |
cc17453a EZ |
2545 | (long) read_register (MACH_REGNUM), |
2546 | (long) read_register (MACL_REGNUM)); | |
2547 | ||
2548 | printf_filtered ("GBR=%08lx VBR=%08lx", | |
2549 | (long) read_register (GBR_REGNUM), | |
2550 | (long) read_register (VBR_REGNUM)); | |
2551 | ||
2552 | printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
2553 | (long) read_register (0), | |
2554 | (long) read_register (1), | |
2555 | (long) read_register (2), | |
2556 | (long) read_register (3), | |
2557 | (long) read_register (4), | |
2558 | (long) read_register (5), | |
2559 | (long) read_register (6), | |
2560 | (long) read_register (7)); | |
2561 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
2562 | (long) read_register (8), | |
2563 | (long) read_register (9), | |
2564 | (long) read_register (10), | |
2565 | (long) read_register (11), | |
2566 | (long) read_register (12), | |
2567 | (long) read_register (13), | |
2568 | (long) read_register (14), | |
2569 | (long) read_register (15)); | |
2570 | } | |
c906108c | 2571 | |
cc17453a | 2572 | static void |
fba45db2 | 2573 | sh3_show_regs (void) |
cc17453a | 2574 | { |
f81353e4 EZ |
2575 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2576 | ||
d4f3574e SS |
2577 | printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", |
2578 | paddr (read_register (PC_REGNUM)), | |
f81353e4 EZ |
2579 | (long) read_register (tdep->SR_REGNUM), |
2580 | (long) read_register (tdep->PR_REGNUM), | |
d4f3574e SS |
2581 | (long) read_register (MACH_REGNUM), |
2582 | (long) read_register (MACL_REGNUM)); | |
2583 | ||
2584 | printf_filtered ("GBR=%08lx VBR=%08lx", | |
2585 | (long) read_register (GBR_REGNUM), | |
2586 | (long) read_register (VBR_REGNUM)); | |
cc17453a | 2587 | printf_filtered (" SSR=%08lx SPC=%08lx", |
f81353e4 EZ |
2588 | (long) read_register (tdep->SSR_REGNUM), |
2589 | (long) read_register (tdep->SPC_REGNUM)); | |
c906108c | 2590 | |
d4f3574e SS |
2591 | printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
2592 | (long) read_register (0), | |
2593 | (long) read_register (1), | |
2594 | (long) read_register (2), | |
2595 | (long) read_register (3), | |
2596 | (long) read_register (4), | |
2597 | (long) read_register (5), | |
2598 | (long) read_register (6), | |
2599 | (long) read_register (7)); | |
2600 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
2601 | (long) read_register (8), | |
2602 | (long) read_register (9), | |
2603 | (long) read_register (10), | |
2604 | (long) read_register (11), | |
2605 | (long) read_register (12), | |
2606 | (long) read_register (13), | |
2607 | (long) read_register (14), | |
2608 | (long) read_register (15)); | |
c906108c SS |
2609 | } |
2610 | ||
53116e27 | 2611 | |
cc17453a | 2612 | static void |
fba45db2 | 2613 | sh3e_show_regs (void) |
cc17453a | 2614 | { |
f81353e4 EZ |
2615 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2616 | ||
cc17453a EZ |
2617 | printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", |
2618 | paddr (read_register (PC_REGNUM)), | |
f81353e4 EZ |
2619 | (long) read_register (tdep->SR_REGNUM), |
2620 | (long) read_register (tdep->PR_REGNUM), | |
cc17453a EZ |
2621 | (long) read_register (MACH_REGNUM), |
2622 | (long) read_register (MACL_REGNUM)); | |
2623 | ||
2624 | printf_filtered ("GBR=%08lx VBR=%08lx", | |
2625 | (long) read_register (GBR_REGNUM), | |
2626 | (long) read_register (VBR_REGNUM)); | |
2627 | printf_filtered (" SSR=%08lx SPC=%08lx", | |
f81353e4 EZ |
2628 | (long) read_register (tdep->SSR_REGNUM), |
2629 | (long) read_register (tdep->SPC_REGNUM)); | |
cc17453a | 2630 | printf_filtered (" FPUL=%08lx FPSCR=%08lx", |
f81353e4 EZ |
2631 | (long) read_register (tdep->FPUL_REGNUM), |
2632 | (long) read_register (tdep->FPSCR_REGNUM)); | |
c906108c | 2633 | |
cc17453a EZ |
2634 | printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
2635 | (long) read_register (0), | |
2636 | (long) read_register (1), | |
2637 | (long) read_register (2), | |
2638 | (long) read_register (3), | |
2639 | (long) read_register (4), | |
2640 | (long) read_register (5), | |
2641 | (long) read_register (6), | |
2642 | (long) read_register (7)); | |
2643 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
2644 | (long) read_register (8), | |
2645 | (long) read_register (9), | |
2646 | (long) read_register (10), | |
2647 | (long) read_register (11), | |
2648 | (long) read_register (12), | |
2649 | (long) read_register (13), | |
2650 | (long) read_register (14), | |
2651 | (long) read_register (15)); | |
2652 | ||
2653 | printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), | |
2654 | (long) read_register (FP0_REGNUM + 0), | |
2655 | (long) read_register (FP0_REGNUM + 1), | |
2656 | (long) read_register (FP0_REGNUM + 2), | |
2657 | (long) read_register (FP0_REGNUM + 3), | |
2658 | (long) read_register (FP0_REGNUM + 4), | |
2659 | (long) read_register (FP0_REGNUM + 5), | |
2660 | (long) read_register (FP0_REGNUM + 6), | |
2661 | (long) read_register (FP0_REGNUM + 7)); | |
2662 | printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), | |
2663 | (long) read_register (FP0_REGNUM + 8), | |
2664 | (long) read_register (FP0_REGNUM + 9), | |
2665 | (long) read_register (FP0_REGNUM + 10), | |
2666 | (long) read_register (FP0_REGNUM + 11), | |
2667 | (long) read_register (FP0_REGNUM + 12), | |
2668 | (long) read_register (FP0_REGNUM + 13), | |
2669 | (long) read_register (FP0_REGNUM + 14), | |
2670 | (long) read_register (FP0_REGNUM + 15)); | |
2671 | } | |
2672 | ||
2673 | static void | |
fba45db2 | 2674 | sh3_dsp_show_regs (void) |
c906108c | 2675 | { |
f81353e4 EZ |
2676 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2677 | ||
cc17453a EZ |
2678 | printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", |
2679 | paddr (read_register (PC_REGNUM)), | |
f81353e4 EZ |
2680 | (long) read_register (tdep->SR_REGNUM), |
2681 | (long) read_register (tdep->PR_REGNUM), | |
cc17453a EZ |
2682 | (long) read_register (MACH_REGNUM), |
2683 | (long) read_register (MACL_REGNUM)); | |
c906108c | 2684 | |
cc17453a EZ |
2685 | printf_filtered ("GBR=%08lx VBR=%08lx", |
2686 | (long) read_register (GBR_REGNUM), | |
2687 | (long) read_register (VBR_REGNUM)); | |
2688 | ||
2689 | printf_filtered (" SSR=%08lx SPC=%08lx", | |
f81353e4 EZ |
2690 | (long) read_register (tdep->SSR_REGNUM), |
2691 | (long) read_register (tdep->SPC_REGNUM)); | |
cc17453a EZ |
2692 | |
2693 | printf_filtered (" DSR=%08lx", | |
f81353e4 | 2694 | (long) read_register (tdep->DSR_REGNUM)); |
cc17453a EZ |
2695 | |
2696 | printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
2697 | (long) read_register (0), | |
2698 | (long) read_register (1), | |
2699 | (long) read_register (2), | |
2700 | (long) read_register (3), | |
2701 | (long) read_register (4), | |
2702 | (long) read_register (5), | |
2703 | (long) read_register (6), | |
2704 | (long) read_register (7)); | |
2705 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
2706 | (long) read_register (8), | |
2707 | (long) read_register (9), | |
2708 | (long) read_register (10), | |
2709 | (long) read_register (11), | |
2710 | (long) read_register (12), | |
2711 | (long) read_register (13), | |
2712 | (long) read_register (14), | |
2713 | (long) read_register (15)); | |
2714 | ||
2715 | printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n", | |
f81353e4 EZ |
2716 | (long) read_register (tdep->A0G_REGNUM) & 0xff, |
2717 | (long) read_register (tdep->A0_REGNUM), | |
2718 | (long) read_register (tdep->M0_REGNUM), | |
2719 | (long) read_register (tdep->X0_REGNUM), | |
2720 | (long) read_register (tdep->Y0_REGNUM), | |
2721 | (long) read_register (tdep->RS_REGNUM), | |
2722 | (long) read_register (tdep->MOD_REGNUM)); | |
cc17453a | 2723 | printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n", |
f81353e4 EZ |
2724 | (long) read_register (tdep->A1G_REGNUM) & 0xff, |
2725 | (long) read_register (tdep->A1_REGNUM), | |
2726 | (long) read_register (tdep->M1_REGNUM), | |
2727 | (long) read_register (tdep->X1_REGNUM), | |
2728 | (long) read_register (tdep->Y1_REGNUM), | |
2729 | (long) read_register (tdep->RE_REGNUM)); | |
c906108c SS |
2730 | } |
2731 | ||
cc17453a | 2732 | static void |
fba45db2 | 2733 | sh4_show_regs (void) |
cc17453a | 2734 | { |
f81353e4 EZ |
2735 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2736 | ||
2737 | int pr = read_register (tdep->FPSCR_REGNUM) & 0x80000; | |
cc17453a EZ |
2738 | printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", |
2739 | paddr (read_register (PC_REGNUM)), | |
f81353e4 EZ |
2740 | (long) read_register (tdep->SR_REGNUM), |
2741 | (long) read_register (tdep->PR_REGNUM), | |
cc17453a EZ |
2742 | (long) read_register (MACH_REGNUM), |
2743 | (long) read_register (MACL_REGNUM)); | |
2744 | ||
2745 | printf_filtered ("GBR=%08lx VBR=%08lx", | |
2746 | (long) read_register (GBR_REGNUM), | |
2747 | (long) read_register (VBR_REGNUM)); | |
2748 | printf_filtered (" SSR=%08lx SPC=%08lx", | |
f81353e4 EZ |
2749 | (long) read_register (tdep->SSR_REGNUM), |
2750 | (long) read_register (tdep->SPC_REGNUM)); | |
cc17453a | 2751 | printf_filtered (" FPUL=%08lx FPSCR=%08lx", |
f81353e4 EZ |
2752 | (long) read_register (tdep->FPUL_REGNUM), |
2753 | (long) read_register (tdep->FPSCR_REGNUM)); | |
cc17453a EZ |
2754 | |
2755 | printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
2756 | (long) read_register (0), | |
2757 | (long) read_register (1), | |
2758 | (long) read_register (2), | |
2759 | (long) read_register (3), | |
2760 | (long) read_register (4), | |
2761 | (long) read_register (5), | |
2762 | (long) read_register (6), | |
2763 | (long) read_register (7)); | |
2764 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
2765 | (long) read_register (8), | |
2766 | (long) read_register (9), | |
2767 | (long) read_register (10), | |
2768 | (long) read_register (11), | |
2769 | (long) read_register (12), | |
2770 | (long) read_register (13), | |
2771 | (long) read_register (14), | |
2772 | (long) read_register (15)); | |
2773 | ||
2774 | printf_filtered ((pr | |
2775 | ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n" | |
2776 | : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), | |
2777 | (long) read_register (FP0_REGNUM + 0), | |
2778 | (long) read_register (FP0_REGNUM + 1), | |
2779 | (long) read_register (FP0_REGNUM + 2), | |
2780 | (long) read_register (FP0_REGNUM + 3), | |
2781 | (long) read_register (FP0_REGNUM + 4), | |
2782 | (long) read_register (FP0_REGNUM + 5), | |
2783 | (long) read_register (FP0_REGNUM + 6), | |
2784 | (long) read_register (FP0_REGNUM + 7)); | |
2785 | printf_filtered ((pr | |
2786 | ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n" | |
2787 | : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), | |
2788 | (long) read_register (FP0_REGNUM + 8), | |
2789 | (long) read_register (FP0_REGNUM + 9), | |
2790 | (long) read_register (FP0_REGNUM + 10), | |
2791 | (long) read_register (FP0_REGNUM + 11), | |
2792 | (long) read_register (FP0_REGNUM + 12), | |
2793 | (long) read_register (FP0_REGNUM + 13), | |
2794 | (long) read_register (FP0_REGNUM + 14), | |
2795 | (long) read_register (FP0_REGNUM + 15)); | |
2796 | } | |
2797 | ||
2798 | static void | |
fba45db2 | 2799 | sh_dsp_show_regs (void) |
cc17453a | 2800 | { |
f81353e4 EZ |
2801 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2802 | ||
cc17453a EZ |
2803 | printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", |
2804 | paddr (read_register (PC_REGNUM)), | |
f81353e4 EZ |
2805 | (long) read_register (tdep->SR_REGNUM), |
2806 | (long) read_register (tdep->PR_REGNUM), | |
cc17453a EZ |
2807 | (long) read_register (MACH_REGNUM), |
2808 | (long) read_register (MACL_REGNUM)); | |
2809 | ||
2810 | printf_filtered ("GBR=%08lx VBR=%08lx", | |
2811 | (long) read_register (GBR_REGNUM), | |
2812 | (long) read_register (VBR_REGNUM)); | |
2813 | ||
2814 | printf_filtered (" DSR=%08lx", | |
f81353e4 | 2815 | (long) read_register (tdep->DSR_REGNUM)); |
cc17453a EZ |
2816 | |
2817 | printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
2818 | (long) read_register (0), | |
2819 | (long) read_register (1), | |
2820 | (long) read_register (2), | |
2821 | (long) read_register (3), | |
2822 | (long) read_register (4), | |
2823 | (long) read_register (5), | |
2824 | (long) read_register (6), | |
2825 | (long) read_register (7)); | |
2826 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
2827 | (long) read_register (8), | |
2828 | (long) read_register (9), | |
2829 | (long) read_register (10), | |
2830 | (long) read_register (11), | |
2831 | (long) read_register (12), | |
2832 | (long) read_register (13), | |
2833 | (long) read_register (14), | |
2834 | (long) read_register (15)); | |
2835 | ||
2836 | printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n", | |
f81353e4 EZ |
2837 | (long) read_register (tdep->A0G_REGNUM) & 0xff, |
2838 | (long) read_register (tdep->A0_REGNUM), | |
2839 | (long) read_register (tdep->M0_REGNUM), | |
2840 | (long) read_register (tdep->X0_REGNUM), | |
2841 | (long) read_register (tdep->Y0_REGNUM), | |
2842 | (long) read_register (tdep->RS_REGNUM), | |
2843 | (long) read_register (tdep->MOD_REGNUM)); | |
cc17453a | 2844 | printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n", |
f81353e4 EZ |
2845 | (long) read_register (tdep->A1G_REGNUM) & 0xff, |
2846 | (long) read_register (tdep->A1_REGNUM), | |
2847 | (long) read_register (tdep->M1_REGNUM), | |
2848 | (long) read_register (tdep->X1_REGNUM), | |
2849 | (long) read_register (tdep->Y1_REGNUM), | |
2850 | (long) read_register (tdep->RE_REGNUM)); | |
cc17453a EZ |
2851 | } |
2852 | ||
283150cd EZ |
2853 | static void |
2854 | sh64_show_media_regs (void) | |
2855 | { | |
2856 | int i; | |
2857 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2858 | ||
2859 | printf_filtered ("PC=%s SR=%016llx \n", | |
2860 | paddr (read_register (PC_REGNUM)), | |
2861 | (long long) read_register (tdep->SR_REGNUM)); | |
2862 | ||
2863 | printf_filtered ("SSR=%016llx SPC=%016llx \n", | |
2864 | (long long) read_register (tdep->SSR_REGNUM), | |
2865 | (long long) read_register (tdep->SPC_REGNUM)); | |
2866 | printf_filtered ("FPSCR=%016lx\n ", | |
2867 | (long) read_register (tdep->FPSCR_REGNUM)); | |
2868 | ||
2869 | for (i = 0; i < 64; i = i + 4) | |
2870 | printf_filtered ("\nR%d-R%d %016llx %016llx %016llx %016llx\n", | |
2871 | i, i + 3, | |
2872 | (long long) read_register (i + 0), | |
2873 | (long long) read_register (i + 1), | |
2874 | (long long) read_register (i + 2), | |
2875 | (long long) read_register (i + 3)); | |
2876 | ||
2877 | printf_filtered ("\n"); | |
2878 | ||
2879 | for (i = 0; i < 64; i = i + 8) | |
2880 | printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
2881 | i, i + 7, | |
2882 | (long) read_register (FP0_REGNUM + i + 0), | |
2883 | (long) read_register (FP0_REGNUM + i + 1), | |
2884 | (long) read_register (FP0_REGNUM + i + 2), | |
2885 | (long) read_register (FP0_REGNUM + i + 3), | |
2886 | (long) read_register (FP0_REGNUM + i + 4), | |
2887 | (long) read_register (FP0_REGNUM + i + 5), | |
2888 | (long) read_register (FP0_REGNUM + i + 6), | |
2889 | (long) read_register (FP0_REGNUM + i + 7)); | |
2890 | } | |
2891 | ||
2892 | static void | |
2893 | sh64_show_compact_regs (void) | |
2894 | { | |
2895 | int i; | |
2896 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2897 | ||
2898 | printf_filtered ("PC=%s \n", | |
2899 | paddr (read_register (tdep->PC_C_REGNUM))); | |
2900 | ||
2901 | printf_filtered ("GBR=%08lx MACH=%08lx MACL=%08lx PR=%08lx T=%08lx\n", | |
2902 | (long) read_register (tdep->GBR_C_REGNUM), | |
2903 | (long) read_register (tdep->MACH_C_REGNUM), | |
2904 | (long) read_register (tdep->MACL_C_REGNUM), | |
2905 | (long) read_register (tdep->PR_C_REGNUM), | |
2906 | (long) read_register (tdep->T_C_REGNUM)); | |
2907 | printf_filtered ("FPSCR=%08lx FPUL=%08lx\n", | |
2908 | (long) read_register (tdep->FPSCR_REGNUM), | |
2909 | (long) read_register (tdep->FPUL_REGNUM)); | |
2910 | ||
2911 | for (i = 0; i < 16; i = i + 4) | |
2912 | printf_filtered ("\nR%d-R%d %08lx %08lx %08lx %08lx\n", | |
2913 | i, i + 3, | |
2914 | (long) read_register (i + 0), | |
2915 | (long) read_register (i + 1), | |
2916 | (long) read_register (i + 2), | |
2917 | (long) read_register (i + 3)); | |
2918 | ||
2919 | printf_filtered ("\n"); | |
2920 | ||
2921 | for (i = 0; i < 16; i = i + 8) | |
2922 | printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
2923 | i, i + 7, | |
2924 | (long) read_register (FP0_REGNUM + i + 0), | |
2925 | (long) read_register (FP0_REGNUM + i + 1), | |
2926 | (long) read_register (FP0_REGNUM + i + 2), | |
2927 | (long) read_register (FP0_REGNUM + i + 3), | |
2928 | (long) read_register (FP0_REGNUM + i + 4), | |
2929 | (long) read_register (FP0_REGNUM + i + 5), | |
2930 | (long) read_register (FP0_REGNUM + i + 6), | |
2931 | (long) read_register (FP0_REGNUM + i + 7)); | |
2932 | } | |
2933 | ||
2934 | /*FIXME!!! This only shows the registers for shmedia, excluding the | |
2935 | pseudo registers. */ | |
2936 | static void | |
2937 | sh64_show_regs (void) | |
2938 | { | |
2939 | if (pc_is_isa32 (selected_frame->pc)) | |
2940 | sh64_show_media_regs (); | |
2941 | else | |
2942 | sh64_show_compact_regs (); | |
2943 | } | |
2944 | ||
53116e27 EZ |
2945 | void sh_show_regs_command (char *args, int from_tty) |
2946 | { | |
2947 | if (sh_show_regs) | |
2948 | (*sh_show_regs)(); | |
2949 | } | |
2950 | ||
cc17453a EZ |
2951 | /* Index within `registers' of the first byte of the space for |
2952 | register N. */ | |
2953 | static int | |
fba45db2 | 2954 | sh_default_register_byte (int reg_nr) |
8db62801 | 2955 | { |
cc17453a EZ |
2956 | return (reg_nr * 4); |
2957 | } | |
2958 | ||
53116e27 | 2959 | static int |
fba45db2 | 2960 | sh_sh4_register_byte (int reg_nr) |
53116e27 | 2961 | { |
f81353e4 EZ |
2962 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
2963 | ||
2964 | if (reg_nr >= tdep->DR0_REGNUM | |
2965 | && reg_nr <= tdep->DR_LAST_REGNUM) | |
53116e27 | 2966 | return (dr_reg_base_num (reg_nr) * 4); |
f81353e4 EZ |
2967 | else if (reg_nr >= tdep->FV0_REGNUM |
2968 | && reg_nr <= tdep->FV_LAST_REGNUM) | |
53116e27 EZ |
2969 | return (fv_reg_base_num (reg_nr) * 4); |
2970 | else | |
2971 | return (reg_nr * 4); | |
2972 | } | |
2973 | ||
283150cd EZ |
2974 | /* *INDENT-OFF* */ |
2975 | /* | |
2976 | SH MEDIA MODE (ISA 32) | |
2977 | general registers (64-bit) 0-63 | |
2978 | 0 r0, r1, r2, r3, r4, r5, r6, r7, | |
2979 | 64 r8, r9, r10, r11, r12, r13, r14, r15, | |
2980 | 128 r16, r17, r18, r19, r20, r21, r22, r23, | |
2981 | 192 r24, r25, r26, r27, r28, r29, r30, r31, | |
2982 | 256 r32, r33, r34, r35, r36, r37, r38, r39, | |
2983 | 320 r40, r41, r42, r43, r44, r45, r46, r47, | |
2984 | 384 r48, r49, r50, r51, r52, r53, r54, r55, | |
2985 | 448 r56, r57, r58, r59, r60, r61, r62, r63, | |
2986 | ||
2987 | pc (64-bit) 64 | |
2988 | 512 pc, | |
2989 | ||
2990 | status reg., saved status reg., saved pc reg. (64-bit) 65-67 | |
2991 | 520 sr, ssr, spc, | |
2992 | ||
2993 | target registers (64-bit) 68-75 | |
2994 | 544 tr0, tr1, tr2, tr3, tr4, tr5, tr6, tr7, | |
2995 | ||
2996 | floating point state control register (32-bit) 76 | |
2997 | 608 fpscr, | |
2998 | ||
2999 | single precision floating point registers (32-bit) 77-140 | |
3000 | 612 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7, | |
3001 | 644 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15, | |
3002 | 676 fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23, | |
3003 | 708 fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31, | |
3004 | 740 fr32, fr33, fr34, fr35, fr36, fr37, fr38, fr39, | |
3005 | 772 fr40, fr41, fr42, fr43, fr44, fr45, fr46, fr47, | |
3006 | 804 fr48, fr49, fr50, fr51, fr52, fr53, fr54, fr55, | |
3007 | 836 fr56, fr57, fr58, fr59, fr60, fr61, fr62, fr63, | |
3008 | ||
3009 | TOTAL SPACE FOR REGISTERS: 868 bytes | |
3010 | ||
3011 | From here on they are all pseudo registers: no memory allocated. | |
3012 | REGISTER_BYTE returns the register byte for the base register. | |
3013 | ||
3014 | double precision registers (pseudo) 141-172 | |
3015 | dr0, dr2, dr4, dr6, dr8, dr10, dr12, dr14, | |
3016 | dr16, dr18, dr20, dr22, dr24, dr26, dr28, dr30, | |
3017 | dr32, dr34, dr36, dr38, dr40, dr42, dr44, dr46, | |
3018 | dr48, dr50, dr52, dr54, dr56, dr58, dr60, dr62, | |
3019 | ||
3020 | floating point pairs (pseudo) 173-204 | |
3021 | fp0, fp2, fp4, fp6, fp8, fp10, fp12, fp14, | |
3022 | fp16, fp18, fp20, fp22, fp24, fp26, fp28, fp30, | |
3023 | fp32, fp34, fp36, fp38, fp40, fp42, fp44, fp46, | |
3024 | fp48, fp50, fp52, fp54, fp56, fp58, fp60, fp62, | |
3025 | ||
3026 | floating point vectors (4 floating point regs) (pseudo) 205-220 | |
3027 | fv0, fv4, fv8, fv12, fv16, fv20, fv24, fv28, | |
3028 | fv32, fv36, fv40, fv44, fv48, fv52, fv56, fv60, | |
3029 | ||
3030 | SH COMPACT MODE (ISA 16) (all pseudo) 221-272 | |
3031 | r0_c, r1_c, r2_c, r3_c, r4_c, r5_c, r6_c, r7_c, | |
3032 | r8_c, r9_c, r10_c, r11_c, r12_c, r13_c, r14_c, r15_c, | |
3033 | pc_c, | |
3034 | gbr_c, mach_c, macl_c, pr_c, t_c, | |
3035 | fpscr_c, fpul_c, | |
3036 | fr0_c, fr1_c, fr2_c, fr3_c, fr4_c, fr5_c, fr6_c, fr7_c, | |
3037 | fr8_c, fr9_c, fr10_c, fr11_c, fr12_c, fr13_c, fr14_c, fr15_c | |
3038 | dr0_c, dr2_c, dr4_c, dr6_c, dr8_c, dr10_c, dr12_c, dr14_c | |
3039 | fv0_c, fv4_c, fv8_c, fv12_c | |
3040 | */ | |
3041 | /* *INDENT-ON* */ | |
3042 | static int | |
3043 | sh_sh64_register_byte (int reg_nr) | |
3044 | { | |
3045 | int base_regnum = -1; | |
3046 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3047 | ||
3048 | /* If it is a pseudo register, get the number of the first floating | |
3049 | point register that is part of it. */ | |
3050 | if (reg_nr >= tdep->DR0_REGNUM | |
3051 | && reg_nr <= tdep->DR_LAST_REGNUM) | |
3052 | base_regnum = dr_reg_base_num (reg_nr); | |
3053 | ||
3054 | else if (reg_nr >= tdep->FPP0_REGNUM | |
3055 | && reg_nr <= tdep->FPP_LAST_REGNUM) | |
3056 | base_regnum = fpp_reg_base_num (reg_nr); | |
3057 | ||
3058 | else if (reg_nr >= tdep->FV0_REGNUM | |
3059 | && reg_nr <= tdep->FV_LAST_REGNUM) | |
3060 | base_regnum = fv_reg_base_num (reg_nr); | |
3061 | ||
3062 | /* sh compact pseudo register. FPSCR is a pathological case, need to | |
3063 | treat it as special. */ | |
3064 | else if ((reg_nr >= tdep->R0_C_REGNUM | |
3065 | && reg_nr <= tdep->FV_LAST_C_REGNUM) | |
3066 | && reg_nr != tdep->FPSCR_C_REGNUM) | |
3067 | base_regnum = sh64_compact_reg_base_num (reg_nr); | |
3068 | ||
3069 | /* Now return the offset in bytes within the register cache. */ | |
3070 | /* sh media pseudo register, i.e. any of DR, FFP, FV registers. */ | |
3071 | if (reg_nr >= tdep->DR0_REGNUM | |
3072 | && reg_nr <= tdep->FV_LAST_REGNUM) | |
3073 | return (base_regnum - FP0_REGNUM + 1) * 4 | |
3074 | + (tdep->TR7_REGNUM + 1) * 8; | |
3075 | ||
3076 | /* sh compact pseudo register: general register */ | |
3077 | if ((reg_nr >= tdep->R0_C_REGNUM | |
3078 | && reg_nr <= tdep->R_LAST_C_REGNUM)) | |
3079 | return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
3080 | ? base_regnum * 8 + 4 | |
3081 | : base_regnum * 8); | |
3082 | ||
3083 | /* sh compact pseudo register: */ | |
3084 | if (reg_nr == tdep->PC_C_REGNUM | |
3085 | || reg_nr == tdep->GBR_C_REGNUM | |
3086 | || reg_nr == tdep->MACL_C_REGNUM | |
3087 | || reg_nr == tdep->PR_C_REGNUM) | |
3088 | return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
3089 | ? base_regnum * 8 + 4 | |
3090 | : base_regnum * 8); | |
3091 | ||
3092 | if (reg_nr == tdep->MACH_C_REGNUM) | |
3093 | return base_regnum * 8; | |
3094 | ||
3095 | if (reg_nr == tdep->T_C_REGNUM) | |
3096 | return base_regnum * 8; /* FIXME??? how do we get bit 0? Do we have to? */ | |
3097 | ||
3098 | /* sh compact pseudo register: floating point register */ | |
3099 | else if (reg_nr >=tdep->FP0_C_REGNUM | |
3100 | && reg_nr <= tdep->FV_LAST_C_REGNUM) | |
3101 | return (base_regnum - FP0_REGNUM) * 4 | |
3102 | + (tdep->TR7_REGNUM + 1) * 8 + 4; | |
3103 | ||
3104 | else if (reg_nr == tdep->FPSCR_C_REGNUM) | |
3105 | /* This is complicated, for now return the beginning of the | |
3106 | architectural FPSCR register. */ | |
3107 | return (tdep->TR7_REGNUM + 1) * 8; | |
3108 | ||
3109 | else if (reg_nr == tdep->FPUL_C_REGNUM) | |
3110 | return ((base_regnum - FP0_REGNUM) * 4 + | |
3111 | (tdep->TR7_REGNUM + 1) * 8 + 4); | |
3112 | ||
3113 | /* It is not a pseudo register. */ | |
3114 | /* It is a 64 bit register. */ | |
3115 | else if (reg_nr <= tdep->TR7_REGNUM) | |
3116 | return reg_nr * 8; | |
3117 | ||
3118 | /* It is a 32 bit register. */ | |
3119 | else | |
3120 | if (reg_nr == tdep->FPSCR_REGNUM) | |
3121 | return (tdep->FPSCR_REGNUM * 8); | |
3122 | ||
3123 | /* It is floating point 32-bit register */ | |
3124 | else | |
3125 | return ((tdep->TR7_REGNUM + 1) * 8 | |
3126 | + (reg_nr - FP0_REGNUM + 1) * 4); | |
3127 | } | |
3128 | ||
cc17453a EZ |
3129 | /* Number of bytes of storage in the actual machine representation for |
3130 | register REG_NR. */ | |
3131 | static int | |
fba45db2 | 3132 | sh_default_register_raw_size (int reg_nr) |
cc17453a EZ |
3133 | { |
3134 | return 4; | |
3135 | } | |
3136 | ||
53116e27 | 3137 | static int |
fba45db2 | 3138 | sh_sh4_register_raw_size (int reg_nr) |
53116e27 | 3139 | { |
f81353e4 EZ |
3140 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
3141 | ||
3142 | if (reg_nr >= tdep->DR0_REGNUM | |
3143 | && reg_nr <= tdep->DR_LAST_REGNUM) | |
53116e27 | 3144 | return 8; |
f81353e4 EZ |
3145 | else if (reg_nr >= tdep->FV0_REGNUM |
3146 | && reg_nr <= tdep->FV_LAST_REGNUM) | |
53116e27 EZ |
3147 | return 16; |
3148 | else | |
3149 | return 4; | |
3150 | } | |
3151 | ||
283150cd EZ |
3152 | static int |
3153 | sh_sh64_register_raw_size (int reg_nr) | |
3154 | { | |
3155 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3156 | ||
3157 | if ((reg_nr >= tdep->DR0_REGNUM | |
3158 | && reg_nr <= tdep->DR_LAST_REGNUM) | |
3159 | || (reg_nr >= tdep->FPP0_REGNUM | |
3160 | && reg_nr <= tdep->FPP_LAST_REGNUM) | |
3161 | || (reg_nr >= tdep->DR0_C_REGNUM | |
3162 | && reg_nr <= tdep->DR_LAST_C_REGNUM) | |
3163 | || (reg_nr <= tdep->TR7_REGNUM)) | |
3164 | return 8; | |
3165 | ||
3166 | else if ((reg_nr >= tdep->FV0_REGNUM | |
3167 | && reg_nr <= tdep->FV_LAST_REGNUM) | |
3168 | || (reg_nr >= tdep->FV0_C_REGNUM | |
3169 | && reg_nr <= tdep->FV_LAST_C_REGNUM)) | |
3170 | return 16; | |
3171 | ||
3172 | else /* this covers also the 32-bit SH compact registers. */ | |
3173 | return 4; | |
3174 | } | |
3175 | ||
cc17453a EZ |
3176 | /* Number of bytes of storage in the program's representation |
3177 | for register N. */ | |
3178 | static int | |
fba45db2 | 3179 | sh_register_virtual_size (int reg_nr) |
cc17453a EZ |
3180 | { |
3181 | return 4; | |
3182 | } | |
3183 | ||
283150cd EZ |
3184 | /* ??????? FIXME */ |
3185 | static int | |
3186 | sh_sh64_register_virtual_size (int reg_nr) | |
3187 | { | |
3188 | if (reg_nr >= FP0_REGNUM | |
3189 | && reg_nr <= gdbarch_tdep (current_gdbarch)->FP_LAST_REGNUM) | |
3190 | return 4; | |
3191 | else | |
3192 | return 8; | |
3193 | } | |
3194 | ||
cc17453a EZ |
3195 | /* Return the GDB type object for the "standard" data type |
3196 | of data in register N. */ | |
cc17453a | 3197 | static struct type * |
fba45db2 | 3198 | sh_sh3e_register_virtual_type (int reg_nr) |
cc17453a | 3199 | { |
f81353e4 EZ |
3200 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
3201 | ||
cc17453a | 3202 | if ((reg_nr >= FP0_REGNUM |
f81353e4 EZ |
3203 | && (reg_nr <= tdep->FP_LAST_REGNUM)) |
3204 | || (reg_nr == tdep->FPUL_REGNUM)) | |
cc17453a | 3205 | return builtin_type_float; |
8db62801 | 3206 | else |
cc17453a EZ |
3207 | return builtin_type_int; |
3208 | } | |
3209 | ||
7f4dbe94 EZ |
3210 | static struct type * |
3211 | sh_sh4_build_float_register_type (int high) | |
3212 | { | |
3213 | struct type *temp; | |
3214 | ||
3215 | temp = create_range_type (NULL, builtin_type_int, 0, high); | |
3216 | return create_array_type (NULL, builtin_type_float, temp); | |
3217 | } | |
3218 | ||
53116e27 | 3219 | static struct type * |
fba45db2 | 3220 | sh_sh4_register_virtual_type (int reg_nr) |
53116e27 | 3221 | { |
f81353e4 EZ |
3222 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
3223 | ||
53116e27 | 3224 | if ((reg_nr >= FP0_REGNUM |
f81353e4 EZ |
3225 | && (reg_nr <= tdep->FP_LAST_REGNUM)) |
3226 | || (reg_nr == tdep->FPUL_REGNUM)) | |
53116e27 | 3227 | return builtin_type_float; |
f81353e4 EZ |
3228 | else if (reg_nr >= tdep->DR0_REGNUM |
3229 | && reg_nr <= tdep->DR_LAST_REGNUM) | |
53116e27 | 3230 | return builtin_type_double; |
f81353e4 EZ |
3231 | else if (reg_nr >= tdep->FV0_REGNUM |
3232 | && reg_nr <= tdep->FV_LAST_REGNUM) | |
53116e27 EZ |
3233 | return sh_sh4_build_float_register_type (3); |
3234 | else | |
3235 | return builtin_type_int; | |
3236 | } | |
3237 | ||
283150cd EZ |
3238 | static struct type * |
3239 | sh_sh64_register_virtual_type (int reg_nr) | |
3240 | { | |
3241 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3242 | ||
3243 | if ((reg_nr >= FP0_REGNUM | |
3244 | && reg_nr <= tdep->FP_LAST_REGNUM) | |
3245 | || (reg_nr >= tdep->FP0_C_REGNUM | |
3246 | && reg_nr <= tdep->FP_LAST_C_REGNUM)) | |
3247 | return builtin_type_float; | |
3248 | else if ((reg_nr >= tdep->DR0_REGNUM | |
3249 | && reg_nr <= tdep->DR_LAST_REGNUM) | |
3250 | || (reg_nr >= tdep->DR0_C_REGNUM | |
3251 | && reg_nr <= tdep->DR_LAST_C_REGNUM)) | |
3252 | return builtin_type_double; | |
3253 | else if (reg_nr >= tdep->FPP0_REGNUM | |
3254 | && reg_nr <= tdep->FPP_LAST_REGNUM) | |
3255 | return sh_sh4_build_float_register_type (1); | |
3256 | else if ((reg_nr >= tdep->FV0_REGNUM | |
3257 | && reg_nr <= tdep->FV_LAST_REGNUM) | |
3258 | ||(reg_nr >= tdep->FV0_C_REGNUM | |
3259 | && reg_nr <= tdep->FV_LAST_C_REGNUM)) | |
3260 | return sh_sh4_build_float_register_type (3); | |
3261 | else if (reg_nr == tdep->FPSCR_REGNUM) | |
3262 | return builtin_type_int; | |
3263 | else if (reg_nr >= tdep->R0_C_REGNUM | |
3264 | && reg_nr < tdep->FP0_C_REGNUM) | |
3265 | return builtin_type_int; | |
3266 | else | |
3267 | return builtin_type_long_long; | |
3268 | } | |
3269 | ||
cc17453a | 3270 | static struct type * |
fba45db2 | 3271 | sh_default_register_virtual_type (int reg_nr) |
cc17453a EZ |
3272 | { |
3273 | return builtin_type_int; | |
3274 | } | |
3275 | ||
fb409745 EZ |
3276 | /* On the sh4, the DRi pseudo registers are problematic if the target |
3277 | is little endian. When the user writes one of those registers, for | |
3278 | instance with 'ser var $dr0=1', we want the double to be stored | |
3279 | like this: | |
3280 | fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f | |
3281 | fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00 | |
3282 | ||
3283 | This corresponds to little endian byte order & big endian word | |
3284 | order. However if we let gdb write the register w/o conversion, it | |
3285 | will write fr0 and fr1 this way: | |
3286 | fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00 | |
3287 | fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f | |
3288 | because it will consider fr0 and fr1 as a single LE stretch of memory. | |
3289 | ||
3290 | To achieve what we want we must force gdb to store things in | |
3291 | floatformat_ieee_double_littlebyte_bigword (which is defined in | |
3292 | include/floatformat.h and libiberty/floatformat.c. | |
3293 | ||
3294 | In case the target is big endian, there is no problem, the | |
3295 | raw bytes will look like: | |
3296 | fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00 | |
3297 | fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00 | |
3298 | ||
3299 | The other pseudo registers (the FVs) also don't pose a problem | |
3300 | because they are stored as 4 individual FP elements. */ | |
3301 | ||
7bd872fe | 3302 | static void |
fb409745 EZ |
3303 | sh_sh4_register_convert_to_virtual (int regnum, struct type *type, |
3304 | char *from, char *to) | |
3305 | { | |
f81353e4 EZ |
3306 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
3307 | ||
3308 | if (regnum >= tdep->DR0_REGNUM | |
3309 | && regnum <= tdep->DR_LAST_REGNUM) | |
fb409745 EZ |
3310 | { |
3311 | DOUBLEST val; | |
3312 | floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, from, &val); | |
3bbfbb92 | 3313 | store_floating (to, TYPE_LENGTH (type), val); |
fb409745 EZ |
3314 | } |
3315 | else | |
3bbfbb92 | 3316 | error ("sh_register_convert_to_virtual called with non DR register number"); |
fb409745 EZ |
3317 | } |
3318 | ||
283150cd EZ |
3319 | void |
3320 | sh_sh64_register_convert_to_virtual (int regnum, struct type *type, | |
3321 | char *from, char *to) | |
3322 | { | |
3323 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3324 | ||
3325 | if (TARGET_BYTE_ORDER != BFD_ENDIAN_LITTLE) | |
3326 | { | |
3327 | /* It is a no-op. */ | |
3328 | memcpy (to, from, REGISTER_RAW_SIZE (regnum)); | |
3329 | return; | |
3330 | } | |
3331 | ||
3332 | if ((regnum >= tdep->DR0_REGNUM | |
3333 | && regnum <= tdep->DR_LAST_REGNUM) | |
3334 | || (regnum >= tdep->DR0_C_REGNUM | |
3335 | && regnum <= tdep->DR_LAST_C_REGNUM)) | |
3336 | { | |
3337 | DOUBLEST val; | |
3338 | floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, from, &val); | |
3339 | store_floating(to, TYPE_LENGTH(type), val); | |
3340 | } | |
3341 | else | |
3342 | error("sh_register_convert_to_virtual called with non DR register number"); | |
3343 | } | |
3344 | ||
3345 | static void | |
3346 | sh_sh4_register_convert_to_raw (struct type *type, int regnum, | |
d8124050 | 3347 | const void *from, void *to) |
283150cd EZ |
3348 | { |
3349 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3350 | ||
3351 | if (regnum >= tdep->DR0_REGNUM | |
3352 | && regnum <= tdep->DR_LAST_REGNUM) | |
3353 | { | |
3354 | DOUBLEST val = extract_floating (from, TYPE_LENGTH(type)); | |
3355 | floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword, &val, to); | |
3356 | } | |
3357 | else | |
3358 | error("sh_register_convert_to_raw called with non DR register number"); | |
3359 | } | |
3360 | ||
3361 | void | |
3362 | sh_sh64_register_convert_to_raw (struct type *type, int regnum, | |
d8124050 | 3363 | const void *from, void *to) |
fb409745 | 3364 | { |
f81353e4 EZ |
3365 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
3366 | ||
283150cd EZ |
3367 | if (TARGET_BYTE_ORDER != BFD_ENDIAN_LITTLE) |
3368 | { | |
3369 | /* It is a no-op. */ | |
3370 | memcpy (to, from, REGISTER_RAW_SIZE (regnum)); | |
3371 | return; | |
3372 | } | |
3373 | ||
3374 | if ((regnum >= tdep->DR0_REGNUM | |
3375 | && regnum <= tdep->DR_LAST_REGNUM) | |
3376 | || (regnum >= tdep->DR0_C_REGNUM | |
3377 | && regnum <= tdep->DR_LAST_C_REGNUM)) | |
fb409745 EZ |
3378 | { |
3379 | DOUBLEST val = extract_floating (from, TYPE_LENGTH(type)); | |
3380 | floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword, &val, to); | |
3381 | } | |
3382 | else | |
3383 | error("sh_register_convert_to_raw called with non DR register number"); | |
3384 | } | |
3385 | ||
53116e27 | 3386 | void |
d8124050 AC |
3387 | sh_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, |
3388 | int reg_nr, void *buffer) | |
53116e27 EZ |
3389 | { |
3390 | int base_regnum, portion; | |
7bd872fe | 3391 | char *temp_buffer = (char*) alloca (MAX_REGISTER_RAW_SIZE); |
d8124050 | 3392 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
53116e27 | 3393 | |
7bd872fe EZ |
3394 | if (reg_nr >= tdep->DR0_REGNUM |
3395 | && reg_nr <= tdep->DR_LAST_REGNUM) | |
3396 | { | |
3397 | base_regnum = dr_reg_base_num (reg_nr); | |
3398 | ||
3399 | /* Build the value in the provided buffer. */ | |
3400 | /* Read the real regs for which this one is an alias. */ | |
3401 | for (portion = 0; portion < 2; portion++) | |
d8124050 | 3402 | regcache_raw_read (regcache, base_regnum + portion, |
0818c12a AC |
3403 | (temp_buffer |
3404 | + REGISTER_RAW_SIZE (base_regnum) * portion)); | |
7bd872fe EZ |
3405 | /* We must pay attention to the endiannes. */ |
3406 | sh_sh4_register_convert_to_virtual (reg_nr, | |
3407 | REGISTER_VIRTUAL_TYPE (reg_nr), | |
3408 | temp_buffer, buffer); | |
3409 | } | |
3410 | else if (reg_nr >= tdep->FV0_REGNUM | |
3411 | && reg_nr <= tdep->FV_LAST_REGNUM) | |
53116e27 | 3412 | { |
7bd872fe EZ |
3413 | base_regnum = fv_reg_base_num (reg_nr); |
3414 | ||
3415 | /* Read the real regs for which this one is an alias. */ | |
3416 | for (portion = 0; portion < 4; portion++) | |
d8124050 AC |
3417 | regcache_raw_read (regcache, base_regnum + portion, |
3418 | ((char *) buffer | |
3419 | + REGISTER_RAW_SIZE (base_regnum) * portion)); | |
53116e27 EZ |
3420 | } |
3421 | } | |
3422 | ||
7bd872fe | 3423 | static void |
d8124050 AC |
3424 | sh64_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, |
3425 | int reg_nr, void *buffer) | |
283150cd EZ |
3426 | { |
3427 | int base_regnum; | |
3428 | int portion; | |
3429 | int offset = 0; | |
3430 | char *temp_buffer = (char*) alloca (MAX_REGISTER_RAW_SIZE); | |
d8124050 | 3431 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
283150cd EZ |
3432 | |
3433 | if (reg_nr >= tdep->DR0_REGNUM | |
3434 | && reg_nr <= tdep->DR_LAST_REGNUM) | |
3435 | { | |
3436 | base_regnum = dr_reg_base_num (reg_nr); | |
3437 | ||
3438 | /* Build the value in the provided buffer. */ | |
3439 | /* DR regs are double precision registers obtained by | |
3440 | concatenating 2 single precision floating point registers. */ | |
3441 | for (portion = 0; portion < 2; portion++) | |
d8124050 | 3442 | regcache_raw_read (regcache, base_regnum + portion, |
0818c12a AC |
3443 | (temp_buffer |
3444 | + REGISTER_RAW_SIZE (base_regnum) * portion)); | |
283150cd EZ |
3445 | |
3446 | /* We must pay attention to the endiannes. */ | |
3447 | sh_sh64_register_convert_to_virtual (reg_nr, REGISTER_VIRTUAL_TYPE (reg_nr), | |
3448 | temp_buffer, buffer); | |
3449 | ||
3450 | } | |
3451 | ||
3452 | else if (reg_nr >= tdep->FPP0_REGNUM | |
3453 | && reg_nr <= tdep->FPP_LAST_REGNUM) | |
3454 | { | |
3455 | base_regnum = fpp_reg_base_num (reg_nr); | |
3456 | ||
3457 | /* Build the value in the provided buffer. */ | |
3458 | /* FPP regs are pairs of single precision registers obtained by | |
3459 | concatenating 2 single precision floating point registers. */ | |
3460 | for (portion = 0; portion < 2; portion++) | |
d8124050 AC |
3461 | regcache_raw_read (regcache, base_regnum + portion, |
3462 | ((char *) buffer | |
0818c12a | 3463 | + REGISTER_RAW_SIZE (base_regnum) * portion)); |
283150cd EZ |
3464 | } |
3465 | ||
3466 | else if (reg_nr >= tdep->FV0_REGNUM | |
3467 | && reg_nr <= tdep->FV_LAST_REGNUM) | |
3468 | { | |
3469 | base_regnum = fv_reg_base_num (reg_nr); | |
3470 | ||
3471 | /* Build the value in the provided buffer. */ | |
3472 | /* FV regs are vectors of single precision registers obtained by | |
3473 | concatenating 4 single precision floating point registers. */ | |
3474 | for (portion = 0; portion < 4; portion++) | |
d8124050 AC |
3475 | regcache_raw_read (regcache, base_regnum + portion, |
3476 | ((char *) buffer | |
0818c12a | 3477 | + REGISTER_RAW_SIZE (base_regnum) * portion)); |
283150cd EZ |
3478 | } |
3479 | ||
3480 | /* sh compact pseudo registers. 1-to-1 with a shmedia register */ | |
3481 | else if (reg_nr >= tdep->R0_C_REGNUM | |
3482 | && reg_nr <= tdep->T_C_REGNUM) | |
3483 | { | |
3484 | base_regnum = sh64_compact_reg_base_num (reg_nr); | |
3485 | ||
3486 | /* Build the value in the provided buffer. */ | |
d8124050 | 3487 | regcache_raw_read (regcache, base_regnum, temp_buffer); |
283150cd EZ |
3488 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
3489 | offset = 4; | |
3490 | memcpy (buffer, temp_buffer + offset, 4); /* get LOWER 32 bits only????*/ | |
3491 | } | |
3492 | ||
3493 | else if (reg_nr >= tdep->FP0_C_REGNUM | |
3494 | && reg_nr <= tdep->FP_LAST_C_REGNUM) | |
3495 | { | |
3496 | base_regnum = sh64_compact_reg_base_num (reg_nr); | |
3497 | ||
3498 | /* Build the value in the provided buffer. */ | |
3499 | /* Floating point registers map 1-1 to the media fp regs, | |
3500 | they have the same size and endienness. */ | |
d8124050 | 3501 | regcache_raw_read (regcache, base_regnum, buffer); |
283150cd EZ |
3502 | } |
3503 | ||
3504 | else if (reg_nr >= tdep->DR0_C_REGNUM | |
3505 | && reg_nr <= tdep->DR_LAST_C_REGNUM) | |
3506 | { | |
3507 | base_regnum = sh64_compact_reg_base_num (reg_nr); | |
3508 | ||
3509 | /* DR_C regs are double precision registers obtained by | |
3510 | concatenating 2 single precision floating point registers. */ | |
3511 | for (portion = 0; portion < 2; portion++) | |
d8124050 | 3512 | regcache_raw_read (regcache, base_regnum + portion, |
0818c12a AC |
3513 | (temp_buffer |
3514 | + REGISTER_RAW_SIZE (base_regnum) * portion)); | |
283150cd EZ |
3515 | |
3516 | /* We must pay attention to the endiannes. */ | |
3517 | sh_sh64_register_convert_to_virtual (reg_nr, REGISTER_VIRTUAL_TYPE (reg_nr), | |
3518 | temp_buffer, buffer); | |
3519 | } | |
3520 | ||
3521 | else if (reg_nr >= tdep->FV0_C_REGNUM | |
3522 | && reg_nr <= tdep->FV_LAST_C_REGNUM) | |
3523 | { | |
3524 | base_regnum = sh64_compact_reg_base_num (reg_nr); | |
3525 | ||
3526 | /* Build the value in the provided buffer. */ | |
3527 | /* FV_C regs are vectors of single precision registers obtained by | |
3528 | concatenating 4 single precision floating point registers. */ | |
3529 | for (portion = 0; portion < 4; portion++) | |
d8124050 AC |
3530 | regcache_raw_read (regcache, base_regnum + portion, |
3531 | ((char *) buffer | |
0818c12a | 3532 | + REGISTER_RAW_SIZE (base_regnum) * portion)); |
283150cd EZ |
3533 | } |
3534 | ||
3535 | else if (reg_nr == tdep->FPSCR_C_REGNUM) | |
3536 | { | |
3537 | int fpscr_base_regnum; | |
3538 | int sr_base_regnum; | |
3539 | unsigned int fpscr_value; | |
3540 | unsigned int sr_value; | |
3541 | unsigned int fpscr_c_value; | |
3542 | unsigned int fpscr_c_part1_value; | |
3543 | unsigned int fpscr_c_part2_value; | |
3544 | ||
3545 | fpscr_base_regnum = tdep->FPSCR_REGNUM; | |
3546 | sr_base_regnum = tdep->SR_REGNUM; | |
3547 | ||
3548 | /* Build the value in the provided buffer. */ | |
3549 | /* FPSCR_C is a very weird register that contains sparse bits | |
3550 | from the FPSCR and the SR architectural registers. | |
3551 | Specifically: */ | |
3552 | /* *INDENT-OFF* */ | |
3553 | /* | |
3554 | FPSRC_C bit | |
3555 | 0 Bit 0 of FPSCR | |
3556 | 1 reserved | |
3557 | 2-17 Bit 2-18 of FPSCR | |
3558 | 18-20 Bits 12,13,14 of SR | |
3559 | 21-31 reserved | |
3560 | */ | |
3561 | /* *INDENT-ON* */ | |
3562 | /* Get FPSCR into a local buffer */ | |
d8124050 | 3563 | regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer); |
283150cd EZ |
3564 | /* Get value as an int. */ |
3565 | fpscr_value = extract_unsigned_integer (temp_buffer, 4); | |
3566 | /* Get SR into a local buffer */ | |
d8124050 | 3567 | regcache_raw_read (regcache, sr_base_regnum, temp_buffer); |
283150cd EZ |
3568 | /* Get value as an int. */ |
3569 | sr_value = extract_unsigned_integer (temp_buffer, 4); | |
3570 | /* Build the new value. */ | |
3571 | fpscr_c_part1_value = fpscr_value & 0x3fffd; | |
3572 | fpscr_c_part2_value = (sr_value & 0x7000) << 6; | |
3573 | fpscr_c_value = fpscr_c_part1_value | fpscr_c_part2_value; | |
3574 | /* Store that in out buffer!!! */ | |
3575 | store_unsigned_integer (buffer, 4, fpscr_c_value); | |
3576 | /* FIXME There is surely an endianness gotcha here. */ | |
3577 | } | |
3578 | ||
3579 | else if (reg_nr == tdep->FPUL_C_REGNUM) | |
3580 | { | |
3581 | base_regnum = sh64_compact_reg_base_num (reg_nr); | |
3582 | ||
3583 | /* FPUL_C register is floating point register 32, | |
3584 | same size, same endianness. */ | |
d8124050 | 3585 | regcache_raw_read (regcache, base_regnum, buffer); |
283150cd EZ |
3586 | } |
3587 | } | |
3588 | ||
53116e27 | 3589 | void |
d8124050 AC |
3590 | sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, |
3591 | int reg_nr, const void *buffer) | |
53116e27 EZ |
3592 | { |
3593 | int base_regnum, portion; | |
7bd872fe | 3594 | char *temp_buffer = (char*) alloca (MAX_REGISTER_RAW_SIZE); |
d8124050 | 3595 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
53116e27 | 3596 | |
f81353e4 EZ |
3597 | if (reg_nr >= tdep->DR0_REGNUM |
3598 | && reg_nr <= tdep->DR_LAST_REGNUM) | |
53116e27 EZ |
3599 | { |
3600 | base_regnum = dr_reg_base_num (reg_nr); | |
3601 | ||
7bd872fe EZ |
3602 | /* We must pay attention to the endiannes. */ |
3603 | sh_sh4_register_convert_to_raw (REGISTER_VIRTUAL_TYPE (reg_nr), reg_nr, | |
3604 | buffer, temp_buffer); | |
3605 | ||
53116e27 EZ |
3606 | /* Write the real regs for which this one is an alias. */ |
3607 | for (portion = 0; portion < 2; portion++) | |
d8124050 | 3608 | regcache_raw_write (regcache, base_regnum + portion, |
0818c12a AC |
3609 | (temp_buffer |
3610 | + REGISTER_RAW_SIZE (base_regnum) * portion)); | |
53116e27 | 3611 | } |
f81353e4 EZ |
3612 | else if (reg_nr >= tdep->FV0_REGNUM |
3613 | && reg_nr <= tdep->FV_LAST_REGNUM) | |
53116e27 EZ |
3614 | { |
3615 | base_regnum = fv_reg_base_num (reg_nr); | |
3616 | ||
3617 | /* Write the real regs for which this one is an alias. */ | |
3618 | for (portion = 0; portion < 4; portion++) | |
d8124050 AC |
3619 | regcache_raw_write (regcache, base_regnum + portion, |
3620 | ((char *) buffer | |
0818c12a | 3621 | + REGISTER_RAW_SIZE (base_regnum) * portion)); |
53116e27 EZ |
3622 | } |
3623 | } | |
3624 | ||
283150cd | 3625 | void |
d8124050 AC |
3626 | sh64_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, |
3627 | int reg_nr, const void *buffer) | |
283150cd EZ |
3628 | { |
3629 | int base_regnum, portion; | |
3630 | int offset; | |
3631 | char *temp_buffer = (char*) alloca (MAX_REGISTER_RAW_SIZE); | |
d8124050 | 3632 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
283150cd EZ |
3633 | |
3634 | if (reg_nr >= tdep->DR0_REGNUM | |
3635 | && reg_nr <= tdep->DR_LAST_REGNUM) | |
3636 | { | |
3637 | base_regnum = dr_reg_base_num (reg_nr); | |
3638 | /* We must pay attention to the endiannes. */ | |
3639 | sh_sh64_register_convert_to_raw (REGISTER_VIRTUAL_TYPE (reg_nr), reg_nr, | |
3640 | buffer, temp_buffer); | |
3641 | ||
3642 | ||
3643 | /* Write the real regs for which this one is an alias. */ | |
3644 | for (portion = 0; portion < 2; portion++) | |
d8124050 | 3645 | regcache_raw_write (regcache, base_regnum + portion, |
0818c12a AC |
3646 | (temp_buffer |
3647 | + REGISTER_RAW_SIZE (base_regnum) * portion)); | |
283150cd EZ |
3648 | } |
3649 | ||
3650 | else if (reg_nr >= tdep->FPP0_REGNUM | |
3651 | && reg_nr <= tdep->FPP_LAST_REGNUM) | |
3652 | { | |
3653 | base_regnum = fpp_reg_base_num (reg_nr); | |
3654 | ||
3655 | /* Write the real regs for which this one is an alias. */ | |
3656 | for (portion = 0; portion < 2; portion++) | |
d8124050 AC |
3657 | regcache_raw_write (regcache, base_regnum + portion, |
3658 | ((char *) buffer | |
0818c12a | 3659 | + REGISTER_RAW_SIZE (base_regnum) * portion)); |
283150cd EZ |
3660 | } |
3661 | ||
3662 | else if (reg_nr >= tdep->FV0_REGNUM | |
3663 | && reg_nr <= tdep->FV_LAST_REGNUM) | |
3664 | { | |
3665 | base_regnum = fv_reg_base_num (reg_nr); | |
3666 | ||
3667 | /* Write the real regs for which this one is an alias. */ | |
3668 | for (portion = 0; portion < 4; portion++) | |
d8124050 AC |
3669 | regcache_raw_write (regcache, base_regnum + portion, |
3670 | ((char *) buffer | |
0818c12a | 3671 | + REGISTER_RAW_SIZE (base_regnum) * portion)); |
283150cd EZ |
3672 | } |
3673 | ||
3674 | /* sh compact general pseudo registers. 1-to-1 with a shmedia | |
3675 | register but only 4 bytes of it. */ | |
3676 | else if (reg_nr >= tdep->R0_C_REGNUM | |
3677 | && reg_nr <= tdep->T_C_REGNUM) | |
3678 | { | |
3679 | base_regnum = sh64_compact_reg_base_num (reg_nr); | |
3680 | /* reg_nr is 32 bit here, and base_regnum is 64 bits. */ | |
3681 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
3682 | offset = 4; | |
3683 | else | |
3684 | offset = 0; | |
3685 | /* Let's read the value of the base register into a temporary | |
3686 | buffer, so that overwriting the last four bytes with the new | |
3687 | value of the pseudo will leave the upper 4 bytes unchanged. */ | |
d8124050 | 3688 | regcache_raw_read (regcache, base_regnum, temp_buffer); |
283150cd EZ |
3689 | /* Write as an 8 byte quantity */ |
3690 | memcpy (temp_buffer + offset, buffer, 4); | |
d8124050 | 3691 | regcache_raw_write (regcache, base_regnum, temp_buffer); |
283150cd EZ |
3692 | } |
3693 | ||
3694 | /* sh floating point compact pseudo registers. 1-to-1 with a shmedia | |
3695 | registers. Both are 4 bytes. */ | |
3696 | else if (reg_nr >= tdep->FP0_C_REGNUM | |
3697 | && reg_nr <= tdep->FP_LAST_C_REGNUM) | |
3698 | { | |
3699 | base_regnum = sh64_compact_reg_base_num (reg_nr); | |
d8124050 | 3700 | regcache_raw_write (regcache, base_regnum, buffer); |
283150cd EZ |
3701 | } |
3702 | ||
3703 | else if (reg_nr >= tdep->DR0_C_REGNUM | |
3704 | && reg_nr <= tdep->DR_LAST_C_REGNUM) | |
3705 | { | |
3706 | base_regnum = sh64_compact_reg_base_num (reg_nr); | |
3707 | for (portion = 0; portion < 2; portion++) | |
3708 | { | |
3709 | /* We must pay attention to the endiannes. */ | |
3710 | sh_sh64_register_convert_to_raw (REGISTER_VIRTUAL_TYPE (reg_nr), reg_nr, | |
3711 | buffer, temp_buffer); | |
3712 | ||
d8124050 | 3713 | regcache_raw_write (regcache, base_regnum + portion, |
0818c12a AC |
3714 | (temp_buffer |
3715 | + REGISTER_RAW_SIZE (base_regnum) * portion)); | |
283150cd EZ |
3716 | } |
3717 | } | |
3718 | ||
3719 | else if (reg_nr >= tdep->FV0_C_REGNUM | |
3720 | && reg_nr <= tdep->FV_LAST_C_REGNUM) | |
3721 | { | |
3722 | base_regnum = sh64_compact_reg_base_num (reg_nr); | |
3723 | ||
3724 | for (portion = 0; portion < 4; portion++) | |
3725 | { | |
d8124050 AC |
3726 | regcache_raw_write (regcache, base_regnum + portion, |
3727 | ((char *) buffer | |
0818c12a | 3728 | + REGISTER_RAW_SIZE (base_regnum) * portion)); |
283150cd EZ |
3729 | } |
3730 | } | |
3731 | ||
3732 | else if (reg_nr == tdep->FPSCR_C_REGNUM) | |
3733 | { | |
3734 | int fpscr_base_regnum; | |
3735 | int sr_base_regnum; | |
3736 | unsigned int fpscr_value; | |
3737 | unsigned int sr_value; | |
3738 | unsigned int old_fpscr_value; | |
3739 | unsigned int old_sr_value; | |
3740 | unsigned int fpscr_c_value; | |
3741 | unsigned int fpscr_mask; | |
3742 | unsigned int sr_mask; | |
3743 | ||
3744 | fpscr_base_regnum = tdep->FPSCR_REGNUM; | |
3745 | sr_base_regnum = tdep->SR_REGNUM; | |
3746 | ||
3747 | /* FPSCR_C is a very weird register that contains sparse bits | |
3748 | from the FPSCR and the SR architectural registers. | |
3749 | Specifically: */ | |
3750 | /* *INDENT-OFF* */ | |
3751 | /* | |
3752 | FPSRC_C bit | |
3753 | 0 Bit 0 of FPSCR | |
3754 | 1 reserved | |
3755 | 2-17 Bit 2-18 of FPSCR | |
3756 | 18-20 Bits 12,13,14 of SR | |
3757 | 21-31 reserved | |
3758 | */ | |
3759 | /* *INDENT-ON* */ | |
3760 | /* Get value as an int. */ | |
3761 | fpscr_c_value = extract_unsigned_integer (buffer, 4); | |
3762 | ||
3763 | /* Build the new values. */ | |
3764 | fpscr_mask = 0x0003fffd; | |
3765 | sr_mask = 0x001c0000; | |
3766 | ||
3767 | fpscr_value = fpscr_c_value & fpscr_mask; | |
3768 | sr_value = (fpscr_value & sr_mask) >> 6; | |
3769 | ||
d8124050 | 3770 | regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer); |
283150cd EZ |
3771 | old_fpscr_value = extract_unsigned_integer (temp_buffer, 4); |
3772 | old_fpscr_value &= 0xfffc0002; | |
3773 | fpscr_value |= old_fpscr_value; | |
3774 | store_unsigned_integer (temp_buffer, 4, fpscr_value); | |
d8124050 | 3775 | regcache_raw_write (regcache, fpscr_base_regnum, temp_buffer); |
283150cd | 3776 | |
d8124050 | 3777 | regcache_raw_read (regcache, sr_base_regnum, temp_buffer); |
283150cd EZ |
3778 | old_sr_value = extract_unsigned_integer (temp_buffer, 4); |
3779 | old_sr_value &= 0xffff8fff; | |
3780 | sr_value |= old_sr_value; | |
3781 | store_unsigned_integer (temp_buffer, 4, sr_value); | |
d8124050 | 3782 | regcache_raw_write (regcache, sr_base_regnum, temp_buffer); |
283150cd EZ |
3783 | } |
3784 | ||
3785 | else if (reg_nr == tdep->FPUL_C_REGNUM) | |
3786 | { | |
3787 | base_regnum = sh64_compact_reg_base_num (reg_nr); | |
d8124050 | 3788 | regcache_raw_write (regcache, base_regnum, buffer); |
283150cd EZ |
3789 | } |
3790 | } | |
3791 | ||
3bbfbb92 | 3792 | /* Floating point vector of 4 float registers. */ |
53116e27 EZ |
3793 | static void |
3794 | do_fv_register_info (int fv_regnum) | |
3795 | { | |
3796 | int first_fp_reg_num = fv_reg_base_num (fv_regnum); | |
3797 | printf_filtered ("fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n", | |
3798 | fv_regnum - gdbarch_tdep (current_gdbarch)->FV0_REGNUM, | |
3799 | (int) read_register (first_fp_reg_num), | |
3800 | (int) read_register (first_fp_reg_num + 1), | |
3801 | (int) read_register (first_fp_reg_num + 2), | |
3802 | (int) read_register (first_fp_reg_num + 3)); | |
3803 | } | |
3804 | ||
283150cd EZ |
3805 | /* Floating point vector of 4 float registers, compact mode. */ |
3806 | static void | |
3807 | do_fv_c_register_info (int fv_regnum) | |
3808 | { | |
3809 | int first_fp_reg_num = sh64_compact_reg_base_num (fv_regnum); | |
3810 | printf_filtered ("fv%d_c\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n", | |
3811 | fv_regnum - gdbarch_tdep (current_gdbarch)->FV0_C_REGNUM, | |
3812 | (int) read_register (first_fp_reg_num), | |
3813 | (int) read_register (first_fp_reg_num + 1), | |
3814 | (int) read_register (first_fp_reg_num + 2), | |
3815 | (int) read_register (first_fp_reg_num + 3)); | |
3816 | } | |
3817 | ||
3818 | /* Pairs of single regs. The DR are instead double precision | |
3819 | registers. */ | |
3820 | static void | |
3821 | do_fpp_register_info (int fpp_regnum) | |
3822 | { | |
3823 | int first_fp_reg_num = fpp_reg_base_num (fpp_regnum); | |
3824 | ||
3825 | printf_filtered ("fpp%d\t0x%08x\t0x%08x\n", | |
3826 | fpp_regnum - gdbarch_tdep (current_gdbarch)->FPP0_REGNUM, | |
3827 | (int) read_register (first_fp_reg_num), | |
3828 | (int) read_register (first_fp_reg_num + 1)); | |
3829 | } | |
3830 | ||
3bbfbb92 | 3831 | /* Double precision registers. */ |
53116e27 EZ |
3832 | static void |
3833 | do_dr_register_info (int dr_regnum) | |
3834 | { | |
3835 | int first_fp_reg_num = dr_reg_base_num (dr_regnum); | |
3836 | ||
3837 | printf_filtered ("dr%d\t0x%08x%08x\n", | |
3838 | dr_regnum - gdbarch_tdep (current_gdbarch)->DR0_REGNUM, | |
3839 | (int) read_register (first_fp_reg_num), | |
3840 | (int) read_register (first_fp_reg_num + 1)); | |
3841 | } | |
3842 | ||
283150cd EZ |
3843 | /* Double precision registers, compact mode. */ |
3844 | static void | |
3845 | do_dr_c_register_info (int dr_regnum) | |
3846 | { | |
3847 | int first_fp_reg_num = sh64_compact_reg_base_num (dr_regnum); | |
3848 | ||
3849 | printf_filtered ("dr%d_c\t0x%08x%08x\n", | |
3850 | dr_regnum - gdbarch_tdep (current_gdbarch)->DR0_C_REGNUM, | |
3851 | (int) read_register (first_fp_reg_num), | |
3852 | (int) read_register (first_fp_reg_num +1)); | |
3853 | } | |
3854 | ||
3855 | /* General register in compact mode. */ | |
3856 | static void | |
3857 | do_r_c_register_info (int r_c_regnum) | |
3858 | { | |
3859 | int regnum = sh64_compact_reg_base_num (r_c_regnum); | |
3860 | ||
3861 | printf_filtered ("r%d_c\t0x%08x\n", | |
3862 | r_c_regnum - gdbarch_tdep (current_gdbarch)->R0_C_REGNUM, | |
3863 | /*FIXME!!!*/ (int) read_register (regnum)); | |
3864 | } | |
3865 | ||
3866 | /* FIXME:!! THIS SHOULD TAKE CARE OF GETTING THE RIGHT PORTION OF THE | |
3867 | shmedia REGISTERS. */ | |
3868 | /* Control registers, compact mode. */ | |
3869 | static void | |
3870 | do_cr_c_register_info (int cr_c_regnum) | |
3871 | { | |
3872 | switch (cr_c_regnum) | |
3873 | { | |
3874 | case 237: printf_filtered ("pc_c\t0x%08x\n", (int) read_register (cr_c_regnum)); | |
3875 | break; | |
3876 | case 238: printf_filtered ("gbr_c\t0x%08x\n", (int) read_register (cr_c_regnum)); | |
3877 | break; | |
3878 | case 239: printf_filtered ("mach_c\t0x%08x\n", (int) read_register (cr_c_regnum)); | |
3879 | break; | |
3880 | case 240: printf_filtered ("macl_c\t0x%08x\n", (int) read_register (cr_c_regnum)); | |
3881 | break; | |
3882 | case 241: printf_filtered ("pr_c\t0x%08x\n", (int) read_register (cr_c_regnum)); | |
3883 | break; | |
3884 | case 242: printf_filtered ("t_c\t0x%08x\n", (int) read_register (cr_c_regnum)); | |
3885 | break; | |
3886 | case 243: printf_filtered ("fpscr_c\t0x%08x\n", (int) read_register (cr_c_regnum)); | |
3887 | break; | |
3888 | case 244: printf_filtered ("fpul_c\t0x%08x\n", (int)read_register (cr_c_regnum)); | |
3889 | break; | |
3890 | } | |
3891 | } | |
3892 | ||
53116e27 EZ |
3893 | static void |
3894 | sh_do_pseudo_register (int regnum) | |
3895 | { | |
f81353e4 EZ |
3896 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
3897 | ||
53116e27 | 3898 | if (regnum < NUM_REGS || regnum >= NUM_REGS + NUM_PSEUDO_REGS) |
8e65ff28 AC |
3899 | internal_error (__FILE__, __LINE__, |
3900 | "Invalid pseudo register number %d\n", regnum); | |
f81353e4 EZ |
3901 | else if (regnum >= tdep->DR0_REGNUM |
3902 | && regnum < tdep->DR_LAST_REGNUM) | |
53116e27 | 3903 | do_dr_register_info (regnum); |
f81353e4 EZ |
3904 | else if (regnum >= tdep->FV0_REGNUM |
3905 | && regnum <= tdep->FV_LAST_REGNUM) | |
53116e27 EZ |
3906 | do_fv_register_info (regnum); |
3907 | } | |
3908 | ||
53116e27 EZ |
3909 | static void |
3910 | sh_do_fp_register (int regnum) | |
3911 | { /* do values for FP (float) regs */ | |
3912 | char *raw_buffer; | |
3913 | double flt; /* double extracted from raw hex data */ | |
3914 | int inv; | |
3915 | int j; | |
3916 | ||
3917 | /* Allocate space for the float. */ | |
3918 | raw_buffer = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM)); | |
3919 | ||
3920 | /* Get the data in raw format. */ | |
cda5a58a | 3921 | if (!frame_register_read (selected_frame, regnum, raw_buffer)) |
53116e27 EZ |
3922 | error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum)); |
3923 | ||
3924 | /* Get the register as a number */ | |
3925 | flt = unpack_double (builtin_type_float, raw_buffer, &inv); | |
3926 | ||
3927 | /* Print the name and some spaces. */ | |
3928 | fputs_filtered (REGISTER_NAME (regnum), gdb_stdout); | |
3929 | print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), gdb_stdout); | |
3930 | ||
3931 | /* Print the value. */ | |
93d56215 AC |
3932 | if (inv) |
3933 | printf_filtered ("<invalid float>"); | |
3934 | else | |
3935 | printf_filtered ("%-10.9g", flt); | |
53116e27 EZ |
3936 | |
3937 | /* Print the fp register as hex. */ | |
3938 | printf_filtered ("\t(raw 0x"); | |
3939 | for (j = 0; j < REGISTER_RAW_SIZE (regnum); j++) | |
3940 | { | |
d7449b42 | 3941 | register int idx = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? j |
53116e27 EZ |
3942 | : REGISTER_RAW_SIZE (regnum) - 1 - j; |
3943 | printf_filtered ("%02x", (unsigned char) raw_buffer[idx]); | |
3944 | } | |
3945 | printf_filtered (")"); | |
3946 | printf_filtered ("\n"); | |
3947 | } | |
3948 | ||
283150cd EZ |
3949 | static void |
3950 | sh64_do_pseudo_register (int regnum) | |
3951 | { | |
3952 | /* All the sh64-compact mode registers are pseudo registers. */ | |
3953 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
3954 | ||
3955 | if (regnum < NUM_REGS | |
3956 | || regnum >= NUM_REGS + NUM_PSEUDO_REGS_SH_MEDIA + NUM_PSEUDO_REGS_SH_COMPACT) | |
3957 | internal_error (__FILE__, __LINE__, | |
3958 | "Invalid pseudo register number %d\n", regnum); | |
3959 | ||
3960 | else if ((regnum >= tdep->DR0_REGNUM | |
3961 | && regnum <= tdep->DR_LAST_REGNUM)) | |
3962 | do_dr_register_info (regnum); | |
3963 | ||
3964 | else if ((regnum >= tdep->DR0_C_REGNUM | |
3965 | && regnum <= tdep->DR_LAST_C_REGNUM)) | |
3966 | do_dr_c_register_info (regnum); | |
3967 | ||
3968 | else if ((regnum >= tdep->FV0_REGNUM | |
3969 | && regnum <= tdep->FV_LAST_REGNUM)) | |
3970 | do_fv_register_info (regnum); | |
3971 | ||
3972 | else if ((regnum >= tdep->FV0_C_REGNUM | |
3973 | && regnum <= tdep->FV_LAST_C_REGNUM)) | |
3974 | do_fv_c_register_info (regnum); | |
3975 | ||
3976 | else if (regnum >= tdep->FPP0_REGNUM | |
3977 | && regnum <= tdep->FPP_LAST_REGNUM) | |
3978 | do_fpp_register_info (regnum); | |
3979 | ||
3980 | else if (regnum >= tdep->R0_C_REGNUM | |
3981 | && regnum <= tdep->R_LAST_C_REGNUM) | |
3982 | do_r_c_register_info (regnum); /* FIXME, this function will not print the right format */ | |
3983 | ||
3984 | else if (regnum >= tdep->FP0_C_REGNUM | |
3985 | && regnum <= tdep->FP_LAST_C_REGNUM) | |
3986 | sh_do_fp_register (regnum); /* this should work also for pseudoregs */ | |
3987 | ||
3988 | else if (regnum >= tdep->PC_C_REGNUM | |
3989 | && regnum <= tdep->FPUL_C_REGNUM) | |
3990 | do_cr_c_register_info (regnum); | |
3991 | ||
3992 | } | |
3993 | ||
53116e27 EZ |
3994 | static void |
3995 | sh_do_register (int regnum) | |
3996 | { | |
3997 | char raw_buffer[MAX_REGISTER_RAW_SIZE]; | |
3998 | ||
3999 | fputs_filtered (REGISTER_NAME (regnum), gdb_stdout); | |
4000 | print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), gdb_stdout); | |
4001 | ||
4002 | /* Get the data in raw format. */ | |
cda5a58a | 4003 | if (!frame_register_read (selected_frame, regnum, raw_buffer)) |
53116e27 EZ |
4004 | printf_filtered ("*value not available*\n"); |
4005 | ||
4006 | val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, 0, | |
4007 | gdb_stdout, 'x', 1, 0, Val_pretty_default); | |
4008 | printf_filtered ("\t"); | |
4009 | val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, 0, | |
4010 | gdb_stdout, 0, 1, 0, Val_pretty_default); | |
4011 | printf_filtered ("\n"); | |
4012 | } | |
4013 | ||
4014 | static void | |
4015 | sh_print_register (int regnum) | |
4016 | { | |
4017 | if (regnum < 0 || regnum >= NUM_REGS + NUM_PSEUDO_REGS) | |
8e65ff28 AC |
4018 | internal_error (__FILE__, __LINE__, |
4019 | "Invalid register number %d\n", regnum); | |
53116e27 | 4020 | |
e30839fe | 4021 | else if (regnum >= 0 && regnum < NUM_REGS) |
53116e27 EZ |
4022 | { |
4023 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) | |
4024 | sh_do_fp_register (regnum); /* FP regs */ | |
4025 | else | |
4026 | sh_do_register (regnum); /* All other regs */ | |
4027 | } | |
4028 | ||
4029 | else if (regnum < NUM_REGS + NUM_PSEUDO_REGS) | |
3bbfbb92 | 4030 | do_pseudo_register (regnum); |
53116e27 EZ |
4031 | } |
4032 | ||
4033 | void | |
4034 | sh_do_registers_info (int regnum, int fpregs) | |
4035 | { | |
4036 | if (regnum != -1) /* do one specified register */ | |
4037 | { | |
4038 | if (*(REGISTER_NAME (regnum)) == '\0') | |
4039 | error ("Not a valid register for the current processor type"); | |
4040 | ||
4041 | sh_print_register (regnum); | |
4042 | } | |
4043 | else | |
4044 | /* do all (or most) registers */ | |
4045 | { | |
4046 | regnum = 0; | |
4047 | while (regnum < NUM_REGS) | |
4048 | { | |
4049 | /* If the register name is empty, it is undefined for this | |
4050 | processor, so don't display anything. */ | |
4051 | if (REGISTER_NAME (regnum) == NULL | |
4052 | || *(REGISTER_NAME (regnum)) == '\0') | |
4053 | { | |
4054 | regnum++; | |
4055 | continue; | |
4056 | } | |
4057 | ||
4058 | if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT) | |
4059 | { | |
4060 | if (fpregs) | |
4061 | { | |
4062 | /* true for "INFO ALL-REGISTERS" command */ | |
4063 | sh_do_fp_register (regnum); /* FP regs */ | |
4064 | regnum ++; | |
4065 | } | |
4066 | else | |
e6c42fda | 4067 | regnum += (gdbarch_tdep (current_gdbarch)->FP_LAST_REGNUM - FP0_REGNUM); /* skip FP regs */ |
53116e27 EZ |
4068 | } |
4069 | else | |
4070 | { | |
4071 | sh_do_register (regnum); /* All other regs */ | |
4072 | regnum++; | |
4073 | } | |
4074 | } | |
4075 | ||
4076 | if (fpregs) | |
4077 | while (regnum < NUM_REGS + NUM_PSEUDO_REGS) | |
4078 | { | |
3bbfbb92 | 4079 | do_pseudo_register (regnum); |
53116e27 EZ |
4080 | regnum++; |
4081 | } | |
4082 | } | |
4083 | } | |
4084 | ||
283150cd EZ |
4085 | void |
4086 | sh_compact_do_registers_info (int regnum, int fpregs) | |
4087 | { | |
4088 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
4089 | if (regnum != -1) /* do one specified register */ | |
4090 | { | |
4091 | if (*(REGISTER_NAME (regnum)) == '\0') | |
4092 | error ("Not a valid register for the current processor type"); | |
4093 | ||
4094 | if (regnum >= 0 && regnum < tdep->R0_C_REGNUM) | |
4095 | error ("Not a valid register for the current processor mode."); | |
4096 | ||
4097 | sh_print_register (regnum); | |
4098 | } | |
4099 | else | |
4100 | /* do all compact registers */ | |
4101 | { | |
4102 | regnum = tdep->R0_C_REGNUM; | |
4103 | while (regnum < NUM_REGS + NUM_PSEUDO_REGS) | |
4104 | { | |
4105 | do_pseudo_register (regnum); | |
4106 | regnum++; | |
4107 | } | |
4108 | } | |
4109 | } | |
4110 | ||
4111 | void | |
4112 | sh64_do_registers_info (int regnum, int fpregs) | |
4113 | { | |
4114 | if (pc_is_isa32 (selected_frame->pc)) | |
4115 | sh_do_registers_info (regnum, fpregs); | |
4116 | else | |
4117 | sh_compact_do_registers_info (regnum, fpregs); | |
4118 | } | |
4119 | ||
1a8629c7 MS |
4120 | #ifdef SVR4_SHARED_LIBS |
4121 | ||
4122 | /* Fetch (and possibly build) an appropriate link_map_offsets structure | |
4123 | for native i386 linux targets using the struct offsets defined in | |
4124 | link.h (but without actual reference to that file). | |
4125 | ||
4126 | This makes it possible to access i386-linux shared libraries from | |
4127 | a gdb that was not built on an i386-linux host (for cross debugging). | |
4128 | */ | |
4129 | ||
4130 | struct link_map_offsets * | |
4131 | sh_linux_svr4_fetch_link_map_offsets (void) | |
4132 | { | |
4133 | static struct link_map_offsets lmo; | |
4134 | static struct link_map_offsets *lmp = 0; | |
4135 | ||
4136 | if (lmp == 0) | |
4137 | { | |
4138 | lmp = &lmo; | |
4139 | ||
4140 | lmo.r_debug_size = 8; /* 20 not actual size but all we need */ | |
4141 | ||
4142 | lmo.r_map_offset = 4; | |
4143 | lmo.r_map_size = 4; | |
4144 | ||
4145 | lmo.link_map_size = 20; /* 552 not actual size but all we need */ | |
4146 | ||
4147 | lmo.l_addr_offset = 0; | |
4148 | lmo.l_addr_size = 4; | |
4149 | ||
4150 | lmo.l_name_offset = 4; | |
4151 | lmo.l_name_size = 4; | |
4152 | ||
4153 | lmo.l_next_offset = 12; | |
4154 | lmo.l_next_size = 4; | |
4155 | ||
4156 | lmo.l_prev_offset = 16; | |
4157 | lmo.l_prev_size = 4; | |
4158 | } | |
4159 | ||
4160 | return lmp; | |
4161 | } | |
4162 | #endif /* SVR4_SHARED_LIBS */ | |
4163 | ||
2f14585c JR |
4164 | \f |
4165 | enum | |
4166 | { | |
4167 | DSP_DSR_REGNUM = 24, | |
4168 | DSP_A0G_REGNUM, | |
4169 | DSP_A0_REGNUM, | |
4170 | DSP_A1G_REGNUM, | |
4171 | DSP_A1_REGNUM, | |
4172 | DSP_M0_REGNUM, | |
4173 | DSP_M1_REGNUM, | |
4174 | DSP_X0_REGNUM, | |
4175 | DSP_X1_REGNUM, | |
4176 | DSP_Y0_REGNUM, | |
4177 | DSP_Y1_REGNUM, | |
4178 | ||
4179 | DSP_MOD_REGNUM = 40, | |
4180 | ||
4181 | DSP_RS_REGNUM = 43, | |
4182 | DSP_RE_REGNUM, | |
4183 | ||
4184 | DSP_R0_BANK_REGNUM = 51, | |
4185 | DSP_R7_BANK_REGNUM = DSP_R0_BANK_REGNUM + 7 | |
4186 | }; | |
4187 | ||
4188 | static int | |
4189 | sh_dsp_register_sim_regno (int nr) | |
4190 | { | |
4191 | if (legacy_register_sim_regno (nr) < 0) | |
4192 | return legacy_register_sim_regno (nr); | |
4193 | if (nr >= DSP_DSR_REGNUM && nr < DSP_Y1_REGNUM) | |
4194 | return nr - DSP_DSR_REGNUM + SIM_SH_DSR_REGNUM; | |
4195 | if (nr == DSP_MOD_REGNUM) | |
4196 | return SIM_SH_MOD_REGNUM; | |
4197 | if (nr == DSP_RS_REGNUM) | |
4198 | return SIM_SH_RS_REGNUM; | |
4199 | if (nr == DSP_RE_REGNUM) | |
4200 | return SIM_SH_RE_REGNUM; | |
4201 | if (nr >= DSP_R0_BANK_REGNUM && nr <= DSP_R7_BANK_REGNUM) | |
4202 | return nr - DSP_R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM; | |
4203 | return nr; | |
4204 | } | |
d658f924 | 4205 | \f |
cc17453a EZ |
4206 | static gdbarch_init_ftype sh_gdbarch_init; |
4207 | ||
4208 | static struct gdbarch * | |
fba45db2 | 4209 | sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
cc17453a EZ |
4210 | { |
4211 | static LONGEST sh_call_dummy_words[] = {0}; | |
4212 | struct gdbarch *gdbarch; | |
4213 | struct gdbarch_tdep *tdep; | |
4214 | gdbarch_register_name_ftype *sh_register_name; | |
ebba8386 | 4215 | gdbarch_deprecated_store_return_value_ftype *sh_store_return_value; |
cc17453a | 4216 | gdbarch_register_virtual_type_ftype *sh_register_virtual_type; |
70f80edf | 4217 | enum gdb_osabi osabi = GDB_OSABI_UNKNOWN; |
d658f924 JT |
4218 | |
4219 | /* Try to determine the ABI of the object we are loading. */ | |
4220 | ||
4221 | if (info.abfd != NULL) | |
4222 | { | |
70f80edf JT |
4223 | osabi = gdbarch_lookup_osabi (info.abfd); |
4224 | /* If we get "unknown" back, just leave it that way. */ | |
d658f924 | 4225 | } |
cc17453a EZ |
4226 | |
4227 | /* Find a candidate among the list of pre-declared architectures. */ | |
d658f924 JT |
4228 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
4229 | arches != NULL; | |
4230 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
4231 | { | |
4232 | /* Make sure the ABI selection matches. */ | |
4233 | tdep = gdbarch_tdep (arches->gdbarch); | |
70f80edf | 4234 | if (tdep && tdep->osabi == osabi) |
d658f924 JT |
4235 | return arches->gdbarch; |
4236 | } | |
cc17453a EZ |
4237 | |
4238 | /* None found, create a new architecture from the information | |
4239 | provided. */ | |
4240 | tdep = XMALLOC (struct gdbarch_tdep); | |
4241 | gdbarch = gdbarch_alloc (&info, tdep); | |
4242 | ||
70f80edf | 4243 | tdep->osabi = osabi; |
d658f924 | 4244 | |
cc17453a EZ |
4245 | /* Initialize the register numbers that are not common to all the |
4246 | variants to -1, if necessary thse will be overwritten in the case | |
4247 | statement below. */ | |
4248 | tdep->FPUL_REGNUM = -1; | |
4249 | tdep->FPSCR_REGNUM = -1; | |
3bbfbb92 | 4250 | tdep->PR_REGNUM = 17; |
c62a7c7b | 4251 | tdep->SR_REGNUM = 22; |
cc17453a | 4252 | tdep->DSR_REGNUM = -1; |
e6c42fda | 4253 | tdep->FP_LAST_REGNUM = -1; |
cc17453a EZ |
4254 | tdep->A0G_REGNUM = -1; |
4255 | tdep->A0_REGNUM = -1; | |
4256 | tdep->A1G_REGNUM = -1; | |
4257 | tdep->A1_REGNUM = -1; | |
4258 | tdep->M0_REGNUM = -1; | |
4259 | tdep->M1_REGNUM = -1; | |
4260 | tdep->X0_REGNUM = -1; | |
4261 | tdep->X1_REGNUM = -1; | |
4262 | tdep->Y0_REGNUM = -1; | |
4263 | tdep->Y1_REGNUM = -1; | |
4264 | tdep->MOD_REGNUM = -1; | |
4265 | tdep->RS_REGNUM = -1; | |
4266 | tdep->RE_REGNUM = -1; | |
4267 | tdep->SSR_REGNUM = -1; | |
4268 | tdep->SPC_REGNUM = -1; | |
53116e27 | 4269 | tdep->DR0_REGNUM = -1; |
e6c42fda | 4270 | tdep->DR_LAST_REGNUM = -1; |
53116e27 | 4271 | tdep->FV0_REGNUM = -1; |
e6c42fda | 4272 | tdep->FV_LAST_REGNUM = -1; |
3bbfbb92 EZ |
4273 | tdep->ARG0_REGNUM = 4; |
4274 | tdep->ARGLAST_REGNUM = 7; | |
4275 | tdep->RETURN_REGNUM = 0; | |
4276 | tdep->FLOAT_ARGLAST_REGNUM = -1; | |
a38d2a54 | 4277 | |
283150cd EZ |
4278 | tdep->sh_abi = SH_ABI_UNKNOWN; |
4279 | ||
cc17453a | 4280 | set_gdbarch_fp0_regnum (gdbarch, -1); |
53116e27 EZ |
4281 | set_gdbarch_num_pseudo_regs (gdbarch, 0); |
4282 | set_gdbarch_max_register_raw_size (gdbarch, 4); | |
4283 | set_gdbarch_max_register_virtual_size (gdbarch, 4); | |
ec920329 | 4284 | set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
a38d2a54 | 4285 | set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
88e04cc1 | 4286 | set_gdbarch_num_regs (gdbarch, SH_DEFAULT_NUM_REGS); |
a38d2a54 EZ |
4287 | set_gdbarch_sp_regnum (gdbarch, 15); |
4288 | set_gdbarch_fp_regnum (gdbarch, 14); | |
4289 | set_gdbarch_pc_regnum (gdbarch, 16); | |
4290 | set_gdbarch_register_size (gdbarch, 4); | |
88e04cc1 | 4291 | set_gdbarch_register_bytes (gdbarch, SH_DEFAULT_NUM_REGS * 4); |
c5f7d19c | 4292 | set_gdbarch_do_registers_info (gdbarch, sh_do_registers_info); |
eaf90c5d | 4293 | set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc); |
3bbfbb92 EZ |
4294 | set_gdbarch_frame_chain (gdbarch, sh_frame_chain); |
4295 | set_gdbarch_get_saved_register (gdbarch, generic_get_saved_register); | |
4296 | set_gdbarch_init_extra_frame_info (gdbarch, sh_init_extra_frame_info); | |
26e9b323 | 4297 | set_gdbarch_deprecated_extract_return_value (gdbarch, sh_extract_return_value); |
3bbfbb92 EZ |
4298 | set_gdbarch_push_arguments (gdbarch, sh_push_arguments); |
4299 | set_gdbarch_store_struct_return (gdbarch, sh_store_struct_return); | |
4300 | set_gdbarch_use_struct_convention (gdbarch, sh_use_struct_convention); | |
26e9b323 | 4301 | set_gdbarch_deprecated_extract_struct_value_address (gdbarch, sh_extract_struct_value_address); |
3bbfbb92 | 4302 | set_gdbarch_pop_frame (gdbarch, sh_pop_frame); |
2bf0cb65 | 4303 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_sh); |
2f14585c | 4304 | set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno); |
3bbfbb92 EZ |
4305 | skip_prologue_hard_way = sh_skip_prologue_hard_way; |
4306 | do_pseudo_register = sh_do_pseudo_register; | |
cc17453a EZ |
4307 | |
4308 | switch (info.bfd_arch_info->mach) | |
8db62801 | 4309 | { |
cc17453a EZ |
4310 | case bfd_mach_sh: |
4311 | sh_register_name = sh_sh_register_name; | |
4312 | sh_show_regs = sh_generic_show_regs; | |
4313 | sh_store_return_value = sh_default_store_return_value; | |
4314 | sh_register_virtual_type = sh_default_register_virtual_type; | |
4315 | set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs); | |
53116e27 EZ |
4316 | set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size); |
4317 | set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size); | |
4318 | set_gdbarch_register_byte (gdbarch, sh_default_register_byte); | |
cc17453a EZ |
4319 | break; |
4320 | case bfd_mach_sh2: | |
4321 | sh_register_name = sh_sh_register_name; | |
4322 | sh_show_regs = sh_generic_show_regs; | |
4323 | sh_store_return_value = sh_default_store_return_value; | |
4324 | sh_register_virtual_type = sh_default_register_virtual_type; | |
4325 | set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs); | |
53116e27 EZ |
4326 | set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size); |
4327 | set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size); | |
4328 | set_gdbarch_register_byte (gdbarch, sh_default_register_byte); | |
cc17453a EZ |
4329 | break; |
4330 | case bfd_mach_sh_dsp: | |
4331 | sh_register_name = sh_sh_dsp_register_name; | |
4332 | sh_show_regs = sh_dsp_show_regs; | |
4333 | sh_store_return_value = sh_default_store_return_value; | |
4334 | sh_register_virtual_type = sh_default_register_virtual_type; | |
4335 | set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs); | |
53116e27 EZ |
4336 | set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size); |
4337 | set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size); | |
4338 | set_gdbarch_register_byte (gdbarch, sh_default_register_byte); | |
2f14585c | 4339 | set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno); |
cc17453a EZ |
4340 | tdep->DSR_REGNUM = 24; |
4341 | tdep->A0G_REGNUM = 25; | |
4342 | tdep->A0_REGNUM = 26; | |
4343 | tdep->A1G_REGNUM = 27; | |
4344 | tdep->A1_REGNUM = 28; | |
4345 | tdep->M0_REGNUM = 29; | |
4346 | tdep->M1_REGNUM = 30; | |
4347 | tdep->X0_REGNUM = 31; | |
4348 | tdep->X1_REGNUM = 32; | |
4349 | tdep->Y0_REGNUM = 33; | |
4350 | tdep->Y1_REGNUM = 34; | |
4351 | tdep->MOD_REGNUM = 40; | |
4352 | tdep->RS_REGNUM = 43; | |
4353 | tdep->RE_REGNUM = 44; | |
4354 | break; | |
4355 | case bfd_mach_sh3: | |
4356 | sh_register_name = sh_sh3_register_name; | |
4357 | sh_show_regs = sh3_show_regs; | |
4358 | sh_store_return_value = sh_default_store_return_value; | |
4359 | sh_register_virtual_type = sh_default_register_virtual_type; | |
4360 | set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs); | |
53116e27 EZ |
4361 | set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size); |
4362 | set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size); | |
4363 | set_gdbarch_register_byte (gdbarch, sh_default_register_byte); | |
cc17453a EZ |
4364 | tdep->SSR_REGNUM = 41; |
4365 | tdep->SPC_REGNUM = 42; | |
4366 | break; | |
4367 | case bfd_mach_sh3e: | |
4368 | sh_register_name = sh_sh3e_register_name; | |
4369 | sh_show_regs = sh3e_show_regs; | |
4370 | sh_store_return_value = sh3e_sh4_store_return_value; | |
4371 | sh_register_virtual_type = sh_sh3e_register_virtual_type; | |
4372 | set_gdbarch_frame_init_saved_regs (gdbarch, sh_fp_frame_init_saved_regs); | |
53116e27 EZ |
4373 | set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size); |
4374 | set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size); | |
4375 | set_gdbarch_register_byte (gdbarch, sh_default_register_byte); | |
26e9b323 | 4376 | set_gdbarch_deprecated_extract_return_value (gdbarch, sh3e_sh4_extract_return_value); |
cc17453a EZ |
4377 | set_gdbarch_fp0_regnum (gdbarch, 25); |
4378 | tdep->FPUL_REGNUM = 23; | |
4379 | tdep->FPSCR_REGNUM = 24; | |
e6c42fda | 4380 | tdep->FP_LAST_REGNUM = 40; |
cc17453a EZ |
4381 | tdep->SSR_REGNUM = 41; |
4382 | tdep->SPC_REGNUM = 42; | |
4383 | break; | |
4384 | case bfd_mach_sh3_dsp: | |
4385 | sh_register_name = sh_sh3_dsp_register_name; | |
4386 | sh_show_regs = sh3_dsp_show_regs; | |
4387 | sh_store_return_value = sh_default_store_return_value; | |
4388 | sh_register_virtual_type = sh_default_register_virtual_type; | |
4389 | set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs); | |
53116e27 EZ |
4390 | set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size); |
4391 | set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size); | |
4392 | set_gdbarch_register_byte (gdbarch, sh_default_register_byte); | |
cc17453a EZ |
4393 | tdep->DSR_REGNUM = 24; |
4394 | tdep->A0G_REGNUM = 25; | |
4395 | tdep->A0_REGNUM = 26; | |
4396 | tdep->A1G_REGNUM = 27; | |
4397 | tdep->A1_REGNUM = 28; | |
4398 | tdep->M0_REGNUM = 29; | |
4399 | tdep->M1_REGNUM = 30; | |
4400 | tdep->X0_REGNUM = 31; | |
4401 | tdep->X1_REGNUM = 32; | |
4402 | tdep->Y0_REGNUM = 33; | |
4403 | tdep->Y1_REGNUM = 34; | |
4404 | tdep->MOD_REGNUM = 40; | |
4405 | tdep->RS_REGNUM = 43; | |
4406 | tdep->RE_REGNUM = 44; | |
4407 | tdep->SSR_REGNUM = 41; | |
4408 | tdep->SPC_REGNUM = 42; | |
4409 | break; | |
4410 | case bfd_mach_sh4: | |
53116e27 EZ |
4411 | sh_register_name = sh_sh4_register_name; |
4412 | sh_show_regs = sh4_show_regs; | |
cc17453a | 4413 | sh_store_return_value = sh3e_sh4_store_return_value; |
53116e27 | 4414 | sh_register_virtual_type = sh_sh4_register_virtual_type; |
cc17453a | 4415 | set_gdbarch_frame_init_saved_regs (gdbarch, sh_fp_frame_init_saved_regs); |
26e9b323 | 4416 | set_gdbarch_deprecated_extract_return_value (gdbarch, sh3e_sh4_extract_return_value); |
cc17453a | 4417 | set_gdbarch_fp0_regnum (gdbarch, 25); |
53116e27 EZ |
4418 | set_gdbarch_register_raw_size (gdbarch, sh_sh4_register_raw_size); |
4419 | set_gdbarch_register_virtual_size (gdbarch, sh_sh4_register_raw_size); | |
4420 | set_gdbarch_register_byte (gdbarch, sh_sh4_register_byte); | |
4421 | set_gdbarch_num_pseudo_regs (gdbarch, 12); | |
4422 | set_gdbarch_max_register_raw_size (gdbarch, 4 * 4); | |
4423 | set_gdbarch_max_register_virtual_size (gdbarch, 4 * 4); | |
d8124050 AC |
4424 | set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read); |
4425 | set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write); | |
cc17453a EZ |
4426 | tdep->FPUL_REGNUM = 23; |
4427 | tdep->FPSCR_REGNUM = 24; | |
e6c42fda | 4428 | tdep->FP_LAST_REGNUM = 40; |
cc17453a EZ |
4429 | tdep->SSR_REGNUM = 41; |
4430 | tdep->SPC_REGNUM = 42; | |
53116e27 | 4431 | tdep->DR0_REGNUM = 59; |
e6c42fda | 4432 | tdep->DR_LAST_REGNUM = 66; |
53116e27 | 4433 | tdep->FV0_REGNUM = 67; |
e6c42fda | 4434 | tdep->FV_LAST_REGNUM = 70; |
cc17453a | 4435 | break; |
283150cd EZ |
4436 | case bfd_mach_sh5: |
4437 | tdep->PR_REGNUM = 18; | |
4438 | tdep->SR_REGNUM = 65; | |
4439 | tdep->FPSCR_REGNUM = SIM_SH64_FPCSR_REGNUM; | |
4440 | tdep->FP_LAST_REGNUM = SIM_SH64_FR0_REGNUM + SIM_SH64_NR_FP_REGS - 1; | |
4441 | tdep->SSR_REGNUM = SIM_SH64_SSR_REGNUM; | |
4442 | tdep->SPC_REGNUM = SIM_SH64_SPC_REGNUM; | |
4443 | tdep->TR7_REGNUM = SIM_SH64_TR0_REGNUM + 7; | |
4444 | tdep->FPP0_REGNUM = 173; | |
4445 | tdep->FPP_LAST_REGNUM = 204; | |
4446 | tdep->DR0_REGNUM = 141; | |
4447 | tdep->DR_LAST_REGNUM = 172; | |
4448 | tdep->FV0_REGNUM = 205; | |
4449 | tdep->FV_LAST_REGNUM = 220; | |
4450 | tdep->R0_C_REGNUM = 221; | |
4451 | tdep->R_LAST_C_REGNUM = 236; | |
4452 | tdep->PC_C_REGNUM = 237; | |
4453 | tdep->GBR_C_REGNUM = 238; | |
4454 | tdep->MACH_C_REGNUM = 239; | |
4455 | tdep->MACL_C_REGNUM = 240; | |
4456 | tdep->PR_C_REGNUM = 241; | |
4457 | tdep->T_C_REGNUM = 242; | |
4458 | tdep->FPSCR_C_REGNUM = 243; | |
4459 | tdep->FPUL_C_REGNUM = 244; | |
4460 | tdep->FP0_C_REGNUM = 245; | |
4461 | tdep->FP_LAST_C_REGNUM = 260; | |
4462 | tdep->DR0_C_REGNUM = 261; | |
4463 | tdep->DR_LAST_C_REGNUM = 268; | |
4464 | tdep->FV0_C_REGNUM = 269; | |
4465 | tdep->FV_LAST_C_REGNUM = 272; | |
4466 | tdep->ARG0_REGNUM = 2; | |
4467 | tdep->ARGLAST_REGNUM = 9; | |
4468 | tdep->RETURN_REGNUM = 2; | |
4469 | tdep->FLOAT_ARGLAST_REGNUM = 11; | |
4470 | ||
4471 | set_gdbarch_num_pseudo_regs (gdbarch, NUM_PSEUDO_REGS_SH_MEDIA + NUM_PSEUDO_REGS_SH_COMPACT); | |
4472 | set_gdbarch_fp0_regnum (gdbarch, SIM_SH64_FR0_REGNUM); | |
4473 | set_gdbarch_pc_regnum (gdbarch, 64); | |
4474 | ||
4475 | /* Determine the ABI */ | |
4476 | if (bfd_get_arch_size (info.abfd) == 64) | |
4477 | { | |
4478 | /* If the ABI is the 64-bit one, it can only be sh-media. */ | |
4479 | tdep->sh_abi = SH_ABI_64; | |
4480 | set_gdbarch_ptr_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
4481 | set_gdbarch_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
4482 | } | |
4483 | else | |
4484 | { | |
4485 | /* If the ABI is the 32-bit one it could be either media or | |
4486 | compact. */ | |
4487 | tdep->sh_abi = SH_ABI_32; | |
4488 | set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
4489 | set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
4490 | } | |
4491 | ||
4492 | /* the number of real registers is the same whether we are in | |
4493 | ISA16(compact) or ISA32(media). */ | |
4494 | set_gdbarch_num_regs (gdbarch, SIM_SH64_NR_REGS); | |
4495 | set_gdbarch_register_size (gdbarch, 8); /*????*/ | |
4496 | set_gdbarch_register_bytes (gdbarch, | |
4497 | ((SIM_SH64_NR_FP_REGS + 1) * 4) | |
4498 | + (SIM_SH64_NR_REGS - SIM_SH64_NR_FP_REGS -1) * 8); | |
4499 | ||
4500 | sh_register_name = sh_sh64_register_name; | |
4501 | sh_show_regs = sh64_show_regs; | |
4502 | sh_register_virtual_type = sh_sh64_register_virtual_type; | |
4503 | sh_store_return_value = sh64_store_return_value; | |
4504 | skip_prologue_hard_way = sh64_skip_prologue_hard_way; | |
4505 | do_pseudo_register = sh64_do_pseudo_register; | |
283150cd EZ |
4506 | set_gdbarch_register_raw_size (gdbarch, sh_sh64_register_raw_size); |
4507 | set_gdbarch_register_virtual_size (gdbarch, sh_sh64_register_raw_size); | |
4508 | set_gdbarch_register_byte (gdbarch, sh_sh64_register_byte); | |
4509 | /* This seems awfully wrong!*/ | |
4510 | /*set_gdbarch_max_register_raw_size (gdbarch, 8);*/ | |
4511 | /* should include the size of the pseudo regs. */ | |
4512 | set_gdbarch_max_register_raw_size (gdbarch, 4 * 4); | |
4513 | /* Or should that go in the virtual_size? */ | |
4514 | /*set_gdbarch_max_register_virtual_size (gdbarch, 8);*/ | |
4515 | set_gdbarch_max_register_virtual_size (gdbarch, 4 * 4); | |
d8124050 AC |
4516 | set_gdbarch_pseudo_register_read (gdbarch, sh64_pseudo_register_read); |
4517 | set_gdbarch_pseudo_register_write (gdbarch, sh64_pseudo_register_write); | |
283150cd EZ |
4518 | |
4519 | set_gdbarch_do_registers_info (gdbarch, sh64_do_registers_info); | |
4520 | set_gdbarch_frame_init_saved_regs (gdbarch, sh64_nofp_frame_init_saved_regs); | |
4521 | set_gdbarch_breakpoint_from_pc (gdbarch, sh_sh64_breakpoint_from_pc); | |
4522 | set_gdbarch_init_extra_frame_info (gdbarch, sh64_init_extra_frame_info); | |
4523 | set_gdbarch_frame_chain (gdbarch, sh64_frame_chain); | |
4524 | set_gdbarch_get_saved_register (gdbarch, sh64_get_saved_register); | |
26e9b323 | 4525 | set_gdbarch_deprecated_extract_return_value (gdbarch, sh64_extract_return_value); |
283150cd EZ |
4526 | set_gdbarch_push_arguments (gdbarch, sh64_push_arguments); |
4527 | /*set_gdbarch_store_struct_return (gdbarch, sh64_store_struct_return);*/ | |
26e9b323 | 4528 | set_gdbarch_deprecated_extract_struct_value_address (gdbarch, sh64_extract_struct_value_address); |
283150cd EZ |
4529 | set_gdbarch_use_struct_convention (gdbarch, sh64_use_struct_convention); |
4530 | set_gdbarch_pop_frame (gdbarch, sh64_pop_frame); | |
4531 | set_gdbarch_elf_make_msymbol_special (gdbarch, | |
4532 | sh64_elf_make_msymbol_special); | |
4533 | break; | |
cc17453a EZ |
4534 | default: |
4535 | sh_register_name = sh_generic_register_name; | |
4536 | sh_show_regs = sh_generic_show_regs; | |
4537 | sh_store_return_value = sh_default_store_return_value; | |
4538 | sh_register_virtual_type = sh_default_register_virtual_type; | |
4539 | set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs); | |
53116e27 EZ |
4540 | set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size); |
4541 | set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size); | |
4542 | set_gdbarch_register_byte (gdbarch, sh_default_register_byte); | |
cc17453a | 4543 | break; |
8db62801 | 4544 | } |
cc17453a EZ |
4545 | |
4546 | set_gdbarch_read_pc (gdbarch, generic_target_read_pc); | |
4547 | set_gdbarch_write_pc (gdbarch, generic_target_write_pc); | |
4548 | set_gdbarch_read_fp (gdbarch, generic_target_read_fp); | |
cc17453a EZ |
4549 | set_gdbarch_read_sp (gdbarch, generic_target_read_sp); |
4550 | set_gdbarch_write_sp (gdbarch, generic_target_write_sp); | |
4551 | ||
cc17453a | 4552 | set_gdbarch_register_name (gdbarch, sh_register_name); |
cc17453a EZ |
4553 | set_gdbarch_register_virtual_type (gdbarch, sh_register_virtual_type); |
4554 | ||
cc17453a EZ |
4555 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); |
4556 | set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
cc17453a EZ |
4557 | set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); |
4558 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
4559 | set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
7079c36c | 4560 | set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); |
cc17453a EZ |
4561 | |
4562 | set_gdbarch_use_generic_dummy_frames (gdbarch, 1); | |
4563 | set_gdbarch_call_dummy_length (gdbarch, 0); | |
4564 | set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT); | |
4565 | set_gdbarch_call_dummy_address (gdbarch, entry_point_address); | |
4566 | set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1); /*???*/ | |
4567 | set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0); | |
4568 | set_gdbarch_call_dummy_start_offset (gdbarch, 0); | |
4569 | set_gdbarch_pc_in_call_dummy (gdbarch, generic_pc_in_call_dummy); | |
4570 | set_gdbarch_call_dummy_words (gdbarch, sh_call_dummy_words); | |
4571 | set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (sh_call_dummy_words)); | |
4572 | set_gdbarch_call_dummy_p (gdbarch, 1); | |
4573 | set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0); | |
cc17453a EZ |
4574 | set_gdbarch_fix_call_dummy (gdbarch, generic_fix_call_dummy); |
4575 | set_gdbarch_coerce_float_to_double (gdbarch, | |
4576 | sh_coerce_float_to_double); | |
4577 | ||
cc17453a EZ |
4578 | set_gdbarch_push_dummy_frame (gdbarch, generic_push_dummy_frame); |
4579 | set_gdbarch_push_return_address (gdbarch, sh_push_return_address); | |
4580 | ||
ebba8386 | 4581 | set_gdbarch_deprecated_store_return_value (gdbarch, sh_store_return_value); |
cc17453a EZ |
4582 | set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue); |
4583 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
4584 | set_gdbarch_decr_pc_after_break (gdbarch, 0); | |
4585 | set_gdbarch_function_start_offset (gdbarch, 0); | |
cc17453a EZ |
4586 | |
4587 | set_gdbarch_frame_args_skip (gdbarch, 0); | |
4588 | set_gdbarch_frameless_function_invocation (gdbarch, frameless_look_for_prologue); | |
cc17453a EZ |
4589 | set_gdbarch_frame_chain_valid (gdbarch, generic_file_frame_chain_valid); |
4590 | set_gdbarch_frame_saved_pc (gdbarch, sh_frame_saved_pc); | |
c347ee3e MS |
4591 | set_gdbarch_frame_args_address (gdbarch, default_frame_address); |
4592 | set_gdbarch_frame_locals_address (gdbarch, default_frame_address); | |
cc17453a EZ |
4593 | set_gdbarch_saved_pc_after_call (gdbarch, sh_saved_pc_after_call); |
4594 | set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown); | |
4595 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); | |
cc17453a | 4596 | |
70f80edf | 4597 | /* Hook in ABI-specific overrides, if they have been registered. |
d658f924 | 4598 | |
70f80edf JT |
4599 | FIXME: if the ABI is unknown, this is probably an embedded target, |
4600 | so we should not warn about this situation. */ | |
4601 | gdbarch_init_osabi (info, gdbarch, osabi); | |
d658f924 | 4602 | |
cc17453a | 4603 | return gdbarch; |
8db62801 EZ |
4604 | } |
4605 | ||
d658f924 JT |
4606 | static void |
4607 | sh_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) | |
4608 | { | |
4609 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
4610 | ||
4611 | if (tdep == NULL) | |
4612 | return; | |
4613 | ||
70f80edf JT |
4614 | fprintf_unfiltered (file, "sh_dump_tdep: OS ABI = %s\n", |
4615 | gdbarch_osabi_name (tdep->osabi)); | |
d658f924 JT |
4616 | } |
4617 | ||
c906108c | 4618 | void |
fba45db2 | 4619 | _initialize_sh_tdep (void) |
c906108c SS |
4620 | { |
4621 | struct cmd_list_element *c; | |
cc17453a | 4622 | |
d658f924 | 4623 | gdbarch_register (bfd_arch_sh, sh_gdbarch_init, sh_dump_tdep); |
c906108c | 4624 | |
53116e27 | 4625 | add_com ("regs", class_vars, sh_show_regs_command, "Print all registers"); |
c906108c | 4626 | } |