projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Oops. missed a line.
[deliverable/binutils-gdb.git] / gdb / sh-tdep.c
CommitLineData
85a453d5 1/* Target-dependent code for Renesas Super-H, for GDB.
1e698235 2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
3116c80a 3 Free Software Foundation, Inc.
c906108c 4
c5aa993b 5 This file is part of GDB.
c906108c 6
c5aa993b
JM		 7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
c906108c 11
c5aa993b
JM		 12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
c906108c 16
c5aa993b
JM		 17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
c906108c
SS		 21
22/*
c5aa993b
JM		 23 Contributed by Steve Chamberlain
24 sac@cygnus.com
c906108c
SS		 25 */
26
27#include "defs.h"
28#include "frame.h"
1c0159e0
CV		 29#include "frame-base.h"
30#include "frame-unwind.h"
31#include "dwarf2-frame.h"
c906108c
SS		 32#include "symtab.h"
33#include "symfile.h"
34#include "gdbtypes.h"
35#include "gdbcmd.h"
36#include "gdbcore.h"
37#include "value.h"
38#include "dis-asm.h"
73c1f219 39#include "inferior.h"
c906108c 40#include "gdb_string.h"
1c0159e0 41#include "gdb_assert.h"
b4a20239 42#include "arch-utils.h"
fb409745 43#include "floatformat.h"
4e052eda 44#include "regcache.h"
d16aafd8 45#include "doublest.h"
4be87837 46#include "osabi.h"
c906108c 47
ab3b8126
JT		 48#include "sh-tdep.h"
49
d658f924 50#include "elf-bfd.h"
1a8629c7
MS		 51#include "solib-svr4.h"
52
55ff77ac 53/* sh flags */
283150cd
EZ		 54#include "elf/sh.h"
55/* registers numbers shared with the simulator */
1c922164 56#include "gdb/sim-sh.h"
283150cd 57
55ff77ac 58static void (*sh_show_regs) (void);
cc17453a 59
f2ea0907 60#define SH_NUM_REGS 59
88e04cc1 61
1c0159e0 62struct sh_frame_cache
cc17453a 63{
1c0159e0
CV		 64 /* Base address. */
65 CORE_ADDR base;
66 LONGEST sp_offset;
67 CORE_ADDR pc;
68
69 /* Flag showing that a frame has been created in the prologue code. */
70 int uses_fp;
71
72 /* Saved registers. */
73 CORE_ADDR saved_regs[SH_NUM_REGS];
74 CORE_ADDR saved_sp;
63978407 75};
c906108c 76
fa88f677 77static const char *
cc17453a 78sh_generic_register_name (int reg_nr)
c5aa993b 79{
617daa0e
CV		 80 static char *register_names[] = {
81 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
82 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
83 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
cc17453a 84 "fpul", "fpscr",
617daa0e
CV		 85 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
86 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
87 "ssr", "spc",
cc17453a
EZ		 88 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
89 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
90 };
91 if (reg_nr < 0)
92 return NULL;
93 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
94 return NULL;
95 return register_names[reg_nr];
96}
97
fa88f677 98static const char *
cc17453a
EZ		 99sh_sh_register_name (int reg_nr)
100{
617daa0e
CV		 101 static char *register_names[] = {
102 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
103 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
104 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
105 "", "",
106 "", "", "", "", "", "", "", "",
107 "", "", "", "", "", "", "", "",
108 "", "",
109 "", "", "", "", "", "", "", "",
110 "", "", "", "", "", "", "", "",
cc17453a
EZ		 111 };
112 if (reg_nr < 0)
113 return NULL;
114 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
115 return NULL;
116 return register_names[reg_nr];
117}
118
fa88f677 119static const char *
cc17453a
EZ		 120sh_sh3_register_name (int reg_nr)
121{
617daa0e
CV		 122 static char *register_names[] = {
123 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
124 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
125 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
126 "", "",
127 "", "", "", "", "", "", "", "",
128 "", "", "", "", "", "", "", "",
129 "ssr", "spc",
cc17453a
EZ		 130 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
131 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
132 };
133 if (reg_nr < 0)
134 return NULL;
135 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
136 return NULL;
137 return register_names[reg_nr];
138}
139
fa88f677 140static const char *
cc17453a
EZ		 141sh_sh3e_register_name (int reg_nr)
142{
617daa0e
CV		 143 static char *register_names[] = {
144 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
145 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
146 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
cc17453a 147 "fpul", "fpscr",
617daa0e
CV		 148 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
149 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
150 "ssr", "spc",
cc17453a
EZ		 151 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
152 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
153 };
154 if (reg_nr < 0)
155 return NULL;
156 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
157 return NULL;
158 return register_names[reg_nr];
159}
160
2d188dd3
NC		 161static const char *
162sh_sh2e_register_name (int reg_nr)
163{
617daa0e
CV		 164 static char *register_names[] = {
165 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
166 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
167 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
2d188dd3 168 "fpul", "fpscr",
617daa0e
CV		 169 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
170 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
171 "", "",
2d188dd3
NC		 172 "", "", "", "", "", "", "", "",
173 "", "", "", "", "", "", "", "",
174 };
175 if (reg_nr < 0)
176 return NULL;
177 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
178 return NULL;
179 return register_names[reg_nr];
180}
181
fa88f677 182static const char *
cc17453a
EZ		 183sh_sh_dsp_register_name (int reg_nr)
184{
617daa0e
CV		 185 static char *register_names[] = {
186 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
187 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
188 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
189 "", "dsr",
190 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
191 "y0", "y1", "", "", "", "", "", "mod",
192 "", "",
193 "rs", "re", "", "", "", "", "", "",
194 "", "", "", "", "", "", "", "",
cc17453a
EZ		 195 };
196 if (reg_nr < 0)
197 return NULL;
198 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
199 return NULL;
200 return register_names[reg_nr];
201}
202
fa88f677 203static const char *
cc17453a
EZ		 204sh_sh3_dsp_register_name (int reg_nr)
205{
617daa0e
CV		 206 static char *register_names[] = {
207 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
208 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
209 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
210 "", "dsr",
211 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
212 "y0", "y1", "", "", "", "", "", "mod",
213 "ssr", "spc",
214 "rs", "re", "", "", "", "", "", "",
215 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b"
216 "", "", "", "", "", "", "", "",
cc17453a
EZ		 217 };
218 if (reg_nr < 0)
219 return NULL;
220 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
221 return NULL;
222 return register_names[reg_nr];
223}
224
fa88f677 225static const char *
53116e27
EZ		 226sh_sh4_register_name (int reg_nr)
227{
617daa0e 228 static char *register_names[] = {
a38d2a54 229 /* general registers 0-15 */
617daa0e
CV		 230 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
231 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
a38d2a54 232 /* 16 - 22 */
617daa0e 233 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
a38d2a54 234 /* 23, 24 */
53116e27 235 "fpul", "fpscr",
a38d2a54 236 /* floating point registers 25 - 40 */
617daa0e
CV		 237 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
238 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
a38d2a54 239 /* 41, 42 */
617daa0e 240 "ssr", "spc",
a38d2a54 241 /* bank 0 43 - 50 */
53116e27 242 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
a38d2a54 243 /* bank 1 51 - 58 */
53116e27 244 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
a38d2a54 245 /* double precision (pseudo) 59 - 66 */
617daa0e 246 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
a38d2a54 247 /* vectors (pseudo) 67 - 70 */
617daa0e 248 "fv0", "fv4", "fv8", "fv12",
a38d2a54
EZ		 249 /* FIXME: missing XF 71 - 86 */
250 /* FIXME: missing XD 87 - 94 */
53116e27
EZ		 251 };
252 if (reg_nr < 0)
253 return NULL;
254 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
255 return NULL;
256 return register_names[reg_nr];
257}
258
3117ed25 259static const unsigned char *
fba45db2 260sh_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
cc17453a
EZ		 261{
262 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */
617daa0e
CV		 263 static unsigned char breakpoint[] = { 0xc3, 0xc3 };
264
cc17453a
EZ		 265 *lenptr = sizeof (breakpoint);
266 return breakpoint;
267}
c906108c
SS		 268
269/* Prologue looks like
1c0159e0
CV		 270 mov.l r14,@-r15
271 sts.l pr,@-r15
272 mov.l <regs>,@-r15
273 sub <room_for_loca_vars>,r15
274 mov r15,r14
8db62801 275
1c0159e0 276 Actually it can be more complicated than this but that's it, basically.
c5aa993b 277 */
c906108c 278
1c0159e0
CV		 279#define GET_SOURCE_REG(x) (((x) >> 4) & 0xf)
280#define GET_TARGET_REG(x) (((x) >> 8) & 0xf)
281
8db62801
EZ		 282/* STS.L PR,@-r15 0100111100100010
283 r15-4-->r15, PR-->(r15) */
c906108c 284#define IS_STS(x) ((x) == 0x4f22)
8db62801
EZ		 285
286/* MOV.L Rm,@-r15 00101111mmmm0110
287 r15-4-->r15, Rm-->(R15) */
c906108c 288#define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
8db62801 289
8db62801
EZ		 290/* MOV r15,r14 0110111011110011
291 r15-->r14 */
c906108c 292#define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
8db62801
EZ		 293
294/* ADD #imm,r15 01111111iiiiiiii
295 r15+imm-->r15 */
1c0159e0 296#define IS_ADD_IMM_SP(x) (((x) & 0xff00) == 0x7f00)
8db62801 297
c906108c
SS		 298#define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
299#define IS_SHLL_R3(x) ((x) == 0x4300)
8db62801
EZ		 300
301/* ADD r3,r15 0011111100111100
302 r15+r3-->r15 */
c906108c 303#define IS_ADD_R3SP(x) ((x) == 0x3f3c)
8db62801
EZ		 304
305/* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
8db62801 306 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
8db62801 307 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
f2ea0907
CV		 308/* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to
309 make this entirely clear. */
1c0159e0
CV		 310/* #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) */
311#define IS_FPUSH(x) (((x) & 0xff0f) == 0xff0b)
312
313/* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 4 <= m <= 7 */
314#define IS_MOV_ARG_TO_REG(x) \
315 (((x) & 0xf00f) == 0x6003 && \
316 ((x) & 0x00f0) >= 0x0040 && \
317 ((x) & 0x00f0) <= 0x0070)
318/* MOV.L Rm,@Rn 0010nnnnmmmm0010 n = 14, 4 <= m <= 7 */
319#define IS_MOV_ARG_TO_IND_R14(x) \
320 (((x) & 0xff0f) == 0x2e02 && \
321 ((x) & 0x00f0) >= 0x0040 && \
322 ((x) & 0x00f0) <= 0x0070)
323/* MOV.L Rm,@(disp*4,Rn) 00011110mmmmdddd n = 14, 4 <= m <= 7 */
324#define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \
325 (((x) & 0xff00) == 0x1e00 && \
326 ((x) & 0x00f0) >= 0x0040 && \
327 ((x) & 0x00f0) <= 0x0070)
328
329/* MOV.W @(disp*2,PC),Rn 1001nnnndddddddd */
330#define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000)
331/* MOV.L @(disp*4,PC),Rn 1101nnnndddddddd */
332#define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000)
333/* SUB Rn,R15 00111111nnnn1000 */
334#define IS_SUB_REG_FROM_SP(x) (((x) & 0xff0f) == 0x3f08)
8db62801 335
1c0159e0 336#define FPSCR_SZ (1 << 20)
cc17453a 337
1c0159e0
CV		 338/* The following instructions are used for epilogue testing. */
339#define IS_RESTORE_FP(x) ((x) == 0x6ef6)
340#define IS_RTS(x) ((x) == 0x000b)
341#define IS_LDS(x) ((x) == 0x4f26)
342#define IS_MOV_FP_SP(x) ((x) == 0x6fe3)
343#define IS_ADD_REG_TO_FP(x) (((x) & 0xff0f) == 0x3e0c)
344#define IS_ADD_IMM_FP(x) (((x) & 0xff00) == 0x7e00)
cc17453a 345
cc17453a
EZ		 346/* Disassemble an instruction. */
347static int
617daa0e 348gdb_print_insn_sh (bfd_vma memaddr, disassemble_info * info)
c906108c 349{
1c509ca8
JR		 350 info->endian = TARGET_BYTE_ORDER;
351 return print_insn_sh (memaddr, info);
283150cd
EZ		 352}
353
cc17453a 354static CORE_ADDR
1c0159e0
CV		 355sh_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc,
356 struct sh_frame_cache *cache)
617daa0e 357{
1c0159e0
CV		 358 ULONGEST inst;
359 CORE_ADDR opc;
360 int offset;
361 int sav_offset = 0;
c906108c 362 int r3_val = 0;
1c0159e0 363 int reg, sav_reg = -1;
cc17453a 364
1c0159e0
CV		 365 if (pc >= current_pc)
366 return current_pc;
cc17453a 367
1c0159e0 368 cache->uses_fp = 0;
cc17453a
EZ		 369 for (opc = pc + (2 * 28); pc < opc; pc += 2)
370 {
1c0159e0 371 inst = read_memory_unsigned_integer (pc, 2);
cc17453a 372 /* See where the registers will be saved to */
f2ea0907 373 if (IS_PUSH (inst))
cc17453a 374 {
1c0159e0
CV		 375 cache->saved_regs[GET_SOURCE_REG (inst)] = cache->sp_offset;
376 cache->sp_offset += 4;
cc17453a 377 }
f2ea0907 378 else if (IS_STS (inst))
cc17453a 379 {
1c0159e0
CV		 380 cache->saved_regs[PR_REGNUM] = cache->sp_offset;
381 cache->sp_offset += 4;
cc17453a 382 }
f2ea0907 383 else if (IS_MOV_R3 (inst))
cc17453a 384 {
f2ea0907 385 r3_val = ((inst & 0xff) ^ 0x80) - 0x80;
cc17453a 386 }
f2ea0907 387 else if (IS_SHLL_R3 (inst))
cc17453a
EZ		 388 {
389 r3_val <<= 1;
390 }
f2ea0907 391 else if (IS_ADD_R3SP (inst))
cc17453a 392 {
1c0159e0 393 cache->sp_offset += -r3_val;
cc17453a 394 }
f2ea0907 395 else if (IS_ADD_IMM_SP (inst))
cc17453a 396 {
1c0159e0
CV		 397 offset = ((inst & 0xff) ^ 0x80) - 0x80;
398 cache->sp_offset -= offset;
c906108c 399 }
1c0159e0 400 else if (IS_MOVW_PCREL_TO_REG (inst))
617daa0e 401 {
1c0159e0
CV		 402 if (sav_reg < 0)
403 {
404 reg = GET_TARGET_REG (inst);
405 if (reg < 14)
406 {
407 sav_reg = reg;
408 offset = (((inst & 0xff) ^ 0x80) - 0x80) << 1;
409 sav_offset =
617daa0e 410 read_memory_integer (((pc + 4) & ~3) + offset, 2);
1c0159e0
CV		 411 }
412 }
c906108c 413 }
1c0159e0 414 else if (IS_MOVL_PCREL_TO_REG (inst))
617daa0e 415 {
1c0159e0
CV		 416 if (sav_reg < 0)
417 {
418 reg = (inst & 0x0f00) >> 8;
419 if (reg < 14)
420 {
421 sav_reg = reg;
422 offset = (((inst & 0xff) ^ 0x80) - 0x80) << 1;
423 sav_offset =
617daa0e 424 read_memory_integer (((pc + 4) & ~3) + offset, 4);
1c0159e0
CV		 425 }
426 }
c906108c 427 }
1c0159e0 428 else if (IS_SUB_REG_FROM_SP (inst))
617daa0e 429 {
1c0159e0
CV		 430 reg = GET_SOURCE_REG (inst);
431 if (sav_reg > 0 && reg == sav_reg)
432 {
433 sav_reg = -1;
434 }
435 cache->sp_offset += sav_offset;
c906108c 436 }
f2ea0907 437 else if (IS_FPUSH (inst))
c906108c 438 {
f2ea0907 439 if (read_register (FPSCR_REGNUM) & FPSCR_SZ)
c906108c 440 {
1c0159e0 441 cache->sp_offset += 8;
c906108c
SS		 442 }
443 else
444 {
1c0159e0 445 cache->sp_offset += 4;
c906108c
SS		 446 }
447 }
f2ea0907 448 else if (IS_MOV_SP_FP (inst))
617daa0e 449 {
1c0159e0
CV		 450 if (!cache->uses_fp)
451 cache->uses_fp = 1;
452 /* At this point, only allow argument register moves to other
453 registers or argument register moves to @(X,fp) which are
454 moving the register arguments onto the stack area allocated
455 by a former add somenumber to SP call. Don't allow moving
456 to an fp indirect address above fp + cache->sp_offset. */
457 pc += 2;
458 for (opc = pc + 12; pc < opc; pc += 2)
459 {
460 inst = read_memory_integer (pc, 2);
461 if (IS_MOV_ARG_TO_IND_R14 (inst))
617daa0e 462 {
1c0159e0
CV		 463 reg = GET_SOURCE_REG (inst);
464 if (cache->sp_offset > 0)
617daa0e 465 cache->saved_regs[reg] = cache->sp_offset;
1c0159e0
CV		 466 }
467 else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst))
617daa0e 468 {
1c0159e0
CV		 469 reg = GET_SOURCE_REG (inst);
470 offset = (inst & 0xf) * 4;
471 if (cache->sp_offset > offset)
472 cache->saved_regs[reg] = cache->sp_offset - offset;
473 }
474 else if (IS_MOV_ARG_TO_REG (inst))
617daa0e 475 continue;
1c0159e0
CV		 476 else
477 break;
478 }
479 break;
480 }
617daa0e
CV		 481#if 0 /* This used to just stop when it found an instruction that
482 was not considered part of the prologue. Now, we just
483 keep going looking for likely instructions. */
c906108c
SS		 484 else
485 break;
2bfa91ee 486#endif
c906108c
SS		 487 }
488
1c0159e0
CV		 489 return pc;
490}
c906108c 491
1c0159e0 492/* Skip any prologue before the guts of a function */
c906108c 493
1c0159e0
CV		 494/* Skip the prologue using the debug information. If this fails we'll
495 fall back on the 'guess' method below. */
496static CORE_ADDR
497after_prologue (CORE_ADDR pc)
498{
499 struct symtab_and_line sal;
500 CORE_ADDR func_addr, func_end;
c906108c 501
1c0159e0
CV		 502 /* If we can not find the symbol in the partial symbol table, then
503 there is no hope we can determine the function's start address
504 with this code. */
505 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
506 return 0;
c906108c 507
1c0159e0
CV		 508 /* Get the line associated with FUNC_ADDR. */
509 sal = find_pc_line (func_addr, 0);
510
511 /* There are only two cases to consider. First, the end of the source line
512 is within the function bounds. In that case we return the end of the
513 source line. Second is the end of the source line extends beyond the
514 bounds of the current function. We need to use the slow code to
515 examine instructions in that case. */
516 if (sal.end < func_end)
517 return sal.end;
518 else
519 return 0;
c906108c
SS		 520}
521
1c0159e0
CV		 522static CORE_ADDR
523sh_skip_prologue (CORE_ADDR start_pc)
c906108c 524{
1c0159e0
CV		 525 CORE_ADDR pc;
526 struct sh_frame_cache cache;
527
528 /* See if we can determine the end of the prologue via the symbol table.
529 If so, then return either PC, or the PC after the prologue, whichever
530 is greater. */
531 pc = after_prologue (start_pc);
cc17453a 532
1c0159e0
CV		 533 /* If after_prologue returned a useful address, then use it. Else
534 fall back on the instruction skipping code. */
535 if (pc)
536 return max (pc, start_pc);
c906108c 537
1c0159e0
CV		 538 cache.sp_offset = -4;
539 pc = sh_analyze_prologue (start_pc, (CORE_ADDR) -1, &cache);
540 if (!cache.uses_fp)
541 return start_pc;
c906108c 542
1c0159e0
CV		 543 return pc;
544}
545
9a5cef92
EZ		 546/* Should call_function allocate stack space for a struct return?
547
548 The ABI says:
549
550 Aggregate types not bigger than 8 bytes that have the same size and
551 alignment as one of the integer scalar types are returned in the
552 same registers as the integer type they match.
553
554 For example, a 2-byte aligned structure with size 2 bytes has the
555 same size and alignment as a short int, and will be returned in R0.
556 A 4-byte aligned structure with size 8 bytes has the same size and
557 alignment as a long long int, and will be returned in R0 and R1.
558
559 When an aggregate type is returned in R0 and R1, R0 contains the
560 first four bytes of the aggregate, and R1 contains the
561 remainder. If the size of the aggregate type is not a multiple of 4
562 bytes, the aggregate is tail-padded up to a multiple of 4
563 bytes. The value of the padding is undefined. For little-endian
564 targets the padding will appear at the most significant end of the
565 last element, for big-endian targets the padding appears at the
566 least significant end of the last element.
567
568 All other aggregate types are returned by address. The caller
569 function passes the address of an area large enough to hold the
570 aggregate value in R2. The called function stores the result in
7fe958be 571 this location.
9a5cef92
EZ		 572
573 To reiterate, structs smaller than 8 bytes could also be returned
574 in memory, if they don't pass the "same size and alignment as an
575 integer type" rule.
576
577 For example, in
578
579 struct s { char c[3]; } wibble;
580 struct s foo(void) { return wibble; }
581
582 the return value from foo() will be in memory, not
583 in R0, because there is no 3-byte integer type.
584
7fe958be
EZ		 585 Similarly, in
586
587 struct s { char c[2]; } wibble;
588 struct s foo(void) { return wibble; }
589
590 because a struct containing two chars has alignment 1, that matches
591 type char, but size 2, that matches type short. There's no integer
592 type that has alignment 1 and size 2, so the struct is returned in
593 memory.
594
9a5cef92
EZ		 595*/
596
1c0159e0
CV		 597static int
598sh_use_struct_convention (int gcc_p, struct type *type)
599{
600 int len = TYPE_LENGTH (type);
601 int nelem = TYPE_NFIELDS (type);
3f997a97
CV		 602
603 /* Non-power of 2 length types and types bigger than 8 bytes (which don't
604 fit in two registers anyway) use struct convention. */
605 if (len != 1 && len != 2 && len != 4 && len != 8)
606 return 1;
607
608 /* Scalar types and aggregate types with exactly one field are aligned
609 by definition. They are returned in registers. */
610 if (nelem <= 1)
611 return 0;
612
613 /* If the first field in the aggregate has the same length as the entire
614 aggregate type, the type is returned in registers. */
615 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == len)
616 return 0;
617
618 /* If the size of the aggregate is 8 bytes and the first field is
619 of size 4 bytes its alignment is equal to long long's alignment,
620 so it's returned in registers. */
621 if (len == 8 && TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == 4)
622 return 0;
623
624 /* Otherwise use struct convention. */
625 return 1;
283150cd
EZ		 626}
627
cc17453a
EZ		 628/* Extract from an array REGBUF containing the (raw) register state
629 the address in which a function should return its structure value,
630 as a CORE_ADDR (or an expression that can be used as one). */
b3df3fff 631static CORE_ADDR
48db5a3c 632sh_extract_struct_value_address (struct regcache *regcache)
cc17453a 633{
48db5a3c 634 ULONGEST addr;
1c0159e0 635
48db5a3c
CV		 636 regcache_cooked_read_unsigned (regcache, STRUCT_RETURN_REGNUM, &addr);
637 return addr;
cc17453a
EZ		 638}
639
19f59343
MS		 640static CORE_ADDR
641sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
642{
643 return sp & ~3;
644}
645
55ff77ac 646/* Function: push_dummy_call (formerly push_arguments)
c906108c
SS		 647 Setup the function arguments for calling a function in the inferior.
648
85a453d5 649 On the Renesas SH architecture, there are four registers (R4 to R7)
c906108c
SS		 650 which are dedicated for passing function arguments. Up to the first
651 four arguments (depending on size) may go into these registers.
652 The rest go on the stack.
653
6df2bf50
MS		 654 MVS: Except on SH variants that have floating point registers.
655 In that case, float and double arguments are passed in the same
656 manner, but using FP registers instead of GP registers.
657
c906108c
SS		 658 Arguments that are smaller than 4 bytes will still take up a whole
659 register or a whole 32-bit word on the stack, and will be
660 right-justified in the register or the stack word. This includes
661 chars, shorts, and small aggregate types.
662
663 Arguments that are larger than 4 bytes may be split between two or
664 more registers. If there are not enough registers free, an argument
665 may be passed partly in a register (or registers), and partly on the
666 stack. This includes doubles, long longs, and larger aggregates.
667 As far as I know, there is no upper limit to the size of aggregates
668 that will be passed in this way; in other words, the convention of
669 passing a pointer to a large aggregate instead of a copy is not used.
670
6df2bf50 671 MVS: The above appears to be true for the SH variants that do not
55ff77ac 672 have an FPU, however those that have an FPU appear to copy the
6df2bf50
MS		 673 aggregate argument onto the stack (and not place it in registers)
674 if it is larger than 16 bytes (four GP registers).
675
c906108c
SS		 676 An exceptional case exists for struct arguments (and possibly other
677 aggregates such as arrays) if the size is larger than 4 bytes but
678 not a multiple of 4 bytes. In this case the argument is never split
679 between the registers and the stack, but instead is copied in its
680 entirety onto the stack, AND also copied into as many registers as
681 there is room for. In other words, space in registers permitting,
682 two copies of the same argument are passed in. As far as I can tell,
683 only the one on the stack is used, although that may be a function
684 of the level of compiler optimization. I suspect this is a compiler
685 bug. Arguments of these odd sizes are left-justified within the
686 word (as opposed to arguments smaller than 4 bytes, which are
687 right-justified).
c5aa993b 688
c906108c
SS		 689 If the function is to return an aggregate type such as a struct, it
690 is either returned in the normal return value register R0 (if its
691 size is no greater than one byte), or else the caller must allocate
692 space into which the callee will copy the return value (if the size
693 is greater than one byte). In this case, a pointer to the return
694 value location is passed into the callee in register R2, which does
695 not displace any of the other arguments passed in via registers R4
696 to R7. */
697
e5e33cd9
CV		 698/* Helper function to justify value in register according to endianess. */
699static char *
700sh_justify_value_in_reg (struct value *val, int len)
701{
702 static char valbuf[4];
703
617daa0e 704 memset (valbuf, 0, sizeof (valbuf));
e5e33cd9
CV		 705 if (len < 4)
706 {
707 /* value gets right-justified in the register or stack word */
708 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
709 memcpy (valbuf + (4 - len), (char *) VALUE_CONTENTS (val), len);
710 else
711 memcpy (valbuf, (char *) VALUE_CONTENTS (val), len);
712 return valbuf;
713 }
714 return (char *) VALUE_CONTENTS (val);
617daa0e 715}
e5e33cd9
CV		 716
717/* Helper function to eval number of bytes to allocate on stack. */
718static CORE_ADDR
719sh_stack_allocsize (int nargs, struct value **args)
720{
721 int stack_alloc = 0;
722 while (nargs-- > 0)
723 stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[nargs])) + 3) & ~3);
724 return stack_alloc;
725}
726
727/* Helper functions for getting the float arguments right. Registers usage
728 depends on the ABI and the endianess. The comments should enlighten how
729 it's intended to work. */
730
731/* This array stores which of the float arg registers are already in use. */
732static int flt_argreg_array[FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM + 1];
733
734/* This function just resets the above array to "no reg used so far". */
735static void
736sh_init_flt_argreg (void)
737{
738 memset (flt_argreg_array, 0, sizeof flt_argreg_array);
739}
740
741/* This function returns the next register to use for float arg passing.
742 It returns either a valid value between FLOAT_ARG0_REGNUM and
743 FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns
744 FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available.
745
746 Note that register number 0 in flt_argreg_array corresponds with the
747 real float register fr4. In contrast to FLOAT_ARG0_REGNUM (value is
748 29) the parity of the register number is preserved, which is important
749 for the double register passing test (see the "argreg & 1" test below). */
750static int
751sh_next_flt_argreg (int len)
752{
753 int argreg;
754
755 /* First search for the next free register. */
617daa0e
CV		 756 for (argreg = 0; argreg <= FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM;
757 ++argreg)
e5e33cd9
CV		 758 if (!flt_argreg_array[argreg])
759 break;
760
761 /* No register left? */
762 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
763 return FLOAT_ARGLAST_REGNUM + 1;
764
765 if (len == 8)
766 {
767 /* Doubles are always starting in a even register number. */
768 if (argreg & 1)
617daa0e 769 {
e5e33cd9
CV		 770 flt_argreg_array[argreg] = 1;
771
772 ++argreg;
773
617daa0e 774 /* No register left? */
e5e33cd9
CV		 775 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
776 return FLOAT_ARGLAST_REGNUM + 1;
777 }
778 /* Also mark the next register as used. */
779 flt_argreg_array[argreg + 1] = 1;
780 }
781 else if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
782 {
783 /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */
784 if (!flt_argreg_array[argreg + 1])
785 ++argreg;
786 }
787 flt_argreg_array[argreg] = 1;
788 return FLOAT_ARG0_REGNUM + argreg;
789}
790
afce3d2a
CV		 791/* Helper function which figures out, if a type is treated like a float type.
792
793 Second, the FPU ABIs have a special way how to treat types as float types.
794 Structures with exactly one member, which is of type float or double, are
795 treated exactly as the base types float or double:
796
797 struct sf {
798 float f;
799 };
800
801 struct sd {
802 double d;
803 };
804
805 are handled the same way as just
806
807 float f;
808
809 double d;
810
811 As a result, arguments of these struct types are pushed into floating point
812 registers exactly as floats or doubles, using the same decision algorithm.
813
814 The same is valid if these types are used as function return types. The
815 above structs are returned in fr0 resp. fr0,fr1 instead of in r0, r0,r1
816 or even using struct convention as it is for other structs. */
817
818static int
819sh_treat_as_flt_p (struct type *type)
820{
821 int len = TYPE_LENGTH (type);
822
823 /* Ordinary float types are obviously treated as float. */
824 if (TYPE_CODE (type) == TYPE_CODE_FLT)
825 return 1;
826 /* Otherwise non-struct types are not treated as float. */
827 if (TYPE_CODE (type) != TYPE_CODE_STRUCT)
828 return 0;
829 /* Otherwise structs with more than one memeber are not treated as float. */
830 if (TYPE_NFIELDS (type) != 1)
831 return 0;
832 /* Otherwise if the type of that member is float, the whole type is
833 treated as float. */
834 if (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) == TYPE_CODE_FLT)
835 return 1;
836 /* Otherwise it's not treated as float. */
837 return 0;
838}
839
cc17453a 840static CORE_ADDR
617daa0e 841sh_push_dummy_call_fpu (struct gdbarch *gdbarch,
6df2bf50 842 CORE_ADDR func_addr,
617daa0e 843 struct regcache *regcache,
6df2bf50 844 CORE_ADDR bp_addr, int nargs,
617daa0e 845 struct value **args,
6df2bf50
MS		 846 CORE_ADDR sp, int struct_return,
847 CORE_ADDR struct_addr)
848{
e5e33cd9
CV		 849 int stack_offset = 0;
850 int argreg = ARG0_REGNUM;
8748518b 851 int flt_argreg = 0;
6df2bf50
MS		 852 int argnum;
853 struct type *type;
854 CORE_ADDR regval;
855 char *val;
8748518b 856 int len, reg_size = 0;
afce3d2a
CV		 857 int pass_on_stack = 0;
858 int treat_as_flt;
6df2bf50
MS		 859
860 /* first force sp to a 4-byte alignment */
861 sp = sh_frame_align (gdbarch, sp);
862
6df2bf50 863 if (struct_return)
1c0159e0 864 regcache_cooked_write_unsigned (regcache,
617daa0e 865 STRUCT_RETURN_REGNUM, struct_addr);
6df2bf50 866
e5e33cd9
CV		 867 /* make room on stack for args */
868 sp -= sh_stack_allocsize (nargs, args);
869
870 /* Initialize float argument mechanism. */
871 sh_init_flt_argreg ();
6df2bf50
MS		 872
873 /* Now load as many as possible of the first arguments into
874 registers, and push the rest onto the stack. There are 16 bytes
875 in four registers available. Loop thru args from first to last. */
e5e33cd9 876 for (argnum = 0; argnum < nargs; argnum++)
6df2bf50
MS		 877 {
878 type = VALUE_TYPE (args[argnum]);
879 len = TYPE_LENGTH (type);
e5e33cd9
CV		 880 val = sh_justify_value_in_reg (args[argnum], len);
881
882 /* Some decisions have to be made how various types are handled.
883 This also differs in different ABIs. */
884 pass_on_stack = 0;
e5e33cd9
CV		 885
886 /* Find out the next register to use for a floating point value. */
afce3d2a
CV		 887 treat_as_flt = sh_treat_as_flt_p (type);
888 if (treat_as_flt)
617daa0e 889 flt_argreg = sh_next_flt_argreg (len);
afce3d2a
CV		 890 /* In contrast to non-FPU CPUs, arguments are never split between
891 registers and stack. If an argument doesn't fit in the remaining
892 registers it's always pushed entirely on the stack. */
893 else if (len > ((ARGLAST_REGNUM - argreg + 1) * 4))
894 pass_on_stack = 1;
48db5a3c 895
6df2bf50
MS		 896 while (len > 0)
897 {
afce3d2a
CV		 898 if ((treat_as_flt && flt_argreg > FLOAT_ARGLAST_REGNUM)
899 || (!treat_as_flt && (argreg > ARGLAST_REGNUM
900 || pass_on_stack)))
617daa0e 901 {
afce3d2a 902 /* The data goes entirely on the stack, 4-byte aligned. */
e5e33cd9
CV		 903 reg_size = (len + 3) & ~3;
904 write_memory (sp + stack_offset, val, reg_size);
905 stack_offset += reg_size;
6df2bf50 906 }
afce3d2a 907 else if (treat_as_flt && flt_argreg <= FLOAT_ARGLAST_REGNUM)
6df2bf50 908 {
e5e33cd9
CV		 909 /* Argument goes in a float argument register. */
910 reg_size = register_size (gdbarch, flt_argreg);
911 regval = extract_unsigned_integer (val, reg_size);
6df2bf50
MS		 912 regcache_cooked_write_unsigned (regcache, flt_argreg++, regval);
913 }
afce3d2a 914 else if (!treat_as_flt && argreg <= ARGLAST_REGNUM)
e5e33cd9 915 {
6df2bf50 916 /* there's room in a register */
e5e33cd9
CV		 917 reg_size = register_size (gdbarch, argreg);
918 regval = extract_unsigned_integer (val, reg_size);
6df2bf50
MS		 919 regcache_cooked_write_unsigned (regcache, argreg++, regval);
920 }
afce3d2a 921 /* Store the value one register at a time or in one step on stack. */
e5e33cd9
CV		 922 len -= reg_size;
923 val += reg_size;
6df2bf50
MS		 924 }
925 }
926
927 /* Store return address. */
55ff77ac 928 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
6df2bf50
MS		 929
930 /* Update stack pointer. */
931 regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp);
932
933 return sp;
934}
935
936static CORE_ADDR
617daa0e 937sh_push_dummy_call_nofpu (struct gdbarch *gdbarch,
6df2bf50 938 CORE_ADDR func_addr,
617daa0e
CV		 939 struct regcache *regcache,
940 CORE_ADDR bp_addr,
941 int nargs, struct value **args,
942 CORE_ADDR sp, int struct_return,
6df2bf50 943 CORE_ADDR struct_addr)
c906108c 944{
e5e33cd9
CV		 945 int stack_offset = 0;
946 int argreg = ARG0_REGNUM;
c906108c
SS		 947 int argnum;
948 struct type *type;
949 CORE_ADDR regval;
950 char *val;
e5e33cd9 951 int len, reg_size;
c906108c
SS		 952
953 /* first force sp to a 4-byte alignment */
19f59343 954 sp = sh_frame_align (gdbarch, sp);
c906108c 955
c906108c 956 if (struct_return)
55ff77ac 957 regcache_cooked_write_unsigned (regcache,
617daa0e 958 STRUCT_RETURN_REGNUM, struct_addr);
c906108c 959
e5e33cd9
CV		 960 /* make room on stack for args */
961 sp -= sh_stack_allocsize (nargs, args);
c906108c 962
c906108c
SS		 963 /* Now load as many as possible of the first arguments into
964 registers, and push the rest onto the stack. There are 16 bytes
965 in four registers available. Loop thru args from first to last. */
e5e33cd9 966 for (argnum = 0; argnum < nargs; argnum++)
617daa0e 967 {
c906108c 968 type = VALUE_TYPE (args[argnum]);
c5aa993b 969 len = TYPE_LENGTH (type);
e5e33cd9 970 val = sh_justify_value_in_reg (args[argnum], len);
c906108c 971
c906108c
SS		 972 while (len > 0)
973 {
e5e33cd9 974 if (argreg > ARGLAST_REGNUM)
617daa0e 975 {
e5e33cd9
CV		 976 /* The remainder of the data goes entirely on the stack,
977 4-byte aligned. */
978 reg_size = (len + 3) & ~3;
979 write_memory (sp + stack_offset, val, reg_size);
617daa0e 980 stack_offset += reg_size;
c906108c 981 }
e5e33cd9 982 else if (argreg <= ARGLAST_REGNUM)
617daa0e 983 {
3bbfbb92 984 /* there's room in a register */
e5e33cd9
CV		 985 reg_size = register_size (gdbarch, argreg);
986 regval = extract_unsigned_integer (val, reg_size);
48db5a3c 987 regcache_cooked_write_unsigned (regcache, argreg++, regval);
c906108c 988 }
e5e33cd9
CV		 989 /* Store the value reg_size bytes at a time. This means that things
990 larger than reg_size bytes may go partly in registers and partly
c906108c 991 on the stack. */
e5e33cd9
CV		 992 len -= reg_size;
993 val += reg_size;
c906108c
SS		 994 }
995 }
48db5a3c
CV		 996
997 /* Store return address. */
55ff77ac 998 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
48db5a3c
CV		 999
1000 /* Update stack pointer. */
1001 regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp);
1002
c906108c
SS		 1003 return sp;
1004}
1005
cc17453a
EZ		 1006/* Find a function's return value in the appropriate registers (in
1007 regbuf), and copy it into valbuf. Extract from an array REGBUF
1008 containing the (raw) register state a function return value of type
1009 TYPE, and copy that, in virtual format, into VALBUF. */
1010static void
48db5a3c
CV		 1011sh_default_extract_return_value (struct type *type, struct regcache *regcache,
1012 void *valbuf)
c906108c 1013{
cc17453a 1014 int len = TYPE_LENGTH (type);
3116c80a
EZ		 1015 int return_register = R0_REGNUM;
1016 int offset;
617daa0e 1017
cc17453a 1018 if (len <= 4)
3116c80a 1019 {
48db5a3c
CV		 1020 ULONGEST c;
1021
1022 regcache_cooked_read_unsigned (regcache, R0_REGNUM, &c);
1023 store_unsigned_integer (valbuf, len, c);
3116c80a 1024 }
48db5a3c 1025 else if (len == 8)
3116c80a 1026 {
48db5a3c
CV		 1027 int i, regnum = R0_REGNUM;
1028 for (i = 0; i < len; i += 4)
617daa0e 1029 regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
3116c80a
EZ		 1030 }
1031 else
1032 error ("bad size for return value");
1033}
1034
1035static void
48db5a3c
CV		 1036sh3e_sh4_extract_return_value (struct type *type, struct regcache *regcache,
1037 void *valbuf)
3116c80a 1038{
afce3d2a 1039 if (sh_treat_as_flt_p (type))
3116c80a 1040 {
48db5a3c
CV		 1041 int len = TYPE_LENGTH (type);
1042 int i, regnum = FP0_REGNUM;
1043 for (i = 0; i < len; i += 4)
617daa0e 1044 regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
3116c80a 1045 }
cc17453a 1046 else
48db5a3c 1047 sh_default_extract_return_value (type, regcache, valbuf);
cc17453a 1048}
c906108c 1049
cc17453a
EZ		 1050/* Write into appropriate registers a function return value
1051 of type TYPE, given in virtual format.
1052 If the architecture is sh4 or sh3e, store a function's return value
1053 in the R0 general register or in the FP0 floating point register,
1054 depending on the type of the return value. In all the other cases
3bbfbb92 1055 the result is stored in r0, left-justified. */
cc17453a 1056static void
48db5a3c
CV		 1057sh_default_store_return_value (struct type *type, struct regcache *regcache,
1058 const void *valbuf)
cc17453a 1059{
48db5a3c
CV		 1060 ULONGEST val;
1061 int len = TYPE_LENGTH (type);
d19b71be 1062
48db5a3c 1063 if (len <= 4)
d19b71be 1064 {
48db5a3c
CV		 1065 val = extract_unsigned_integer (valbuf, len);
1066 regcache_cooked_write_unsigned (regcache, R0_REGNUM, val);
d19b71be
MS		 1067 }
1068 else
48db5a3c
CV		 1069 {
1070 int i, regnum = R0_REGNUM;
1071 for (i = 0; i < len; i += 4)
617daa0e 1072 regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
48db5a3c 1073 }
cc17453a 1074}
c906108c 1075
cc17453a 1076static void
48db5a3c
CV		 1077sh3e_sh4_store_return_value (struct type *type, struct regcache *regcache,
1078 const void *valbuf)
cc17453a 1079{
afce3d2a 1080 if (sh_treat_as_flt_p (type))
48db5a3c
CV		 1081 {
1082 int len = TYPE_LENGTH (type);
1083 int i, regnum = FP0_REGNUM;
1084 for (i = 0; i < len; i += 4)
617daa0e 1085 regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
48db5a3c 1086 }
cc17453a 1087 else
48db5a3c 1088 sh_default_store_return_value (type, regcache, valbuf);
c906108c
SS		 1089}
1090
1091/* Print the registers in a form similar to the E7000 */
1092
1093static void
fba45db2 1094sh_generic_show_regs (void)
c906108c 1095{
cc17453a
EZ		 1096 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1097 paddr (read_register (PC_REGNUM)),
55ff77ac
CV		 1098 (long) read_register (SR_REGNUM),
1099 (long) read_register (PR_REGNUM),
cc17453a
EZ		 1100 (long) read_register (MACH_REGNUM),
1101 (long) read_register (MACL_REGNUM));
1102
1103 printf_filtered ("GBR=%08lx VBR=%08lx",
1104 (long) read_register (GBR_REGNUM),
1105 (long) read_register (VBR_REGNUM));
1106
617daa0e
CV		 1107 printf_filtered
1108 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1109 (long) read_register (0), (long) read_register (1),
1110 (long) read_register (2), (long) read_register (3),
1111 (long) read_register (4), (long) read_register (5),
1112 (long) read_register (6), (long) read_register (7));
cc17453a 1113 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
617daa0e
CV		 1114 (long) read_register (8), (long) read_register (9),
1115 (long) read_register (10), (long) read_register (11),
1116 (long) read_register (12), (long) read_register (13),
1117 (long) read_register (14), (long) read_register (15));
cc17453a 1118}
c906108c 1119
cc17453a 1120static void
fba45db2 1121sh3_show_regs (void)
cc17453a 1122{
d4f3574e
SS		 1123 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1124 paddr (read_register (PC_REGNUM)),
55ff77ac
CV		 1125 (long) read_register (SR_REGNUM),
1126 (long) read_register (PR_REGNUM),
d4f3574e
SS		 1127 (long) read_register (MACH_REGNUM),
1128 (long) read_register (MACL_REGNUM));
1129
1130 printf_filtered ("GBR=%08lx VBR=%08lx",
1131 (long) read_register (GBR_REGNUM),
1132 (long) read_register (VBR_REGNUM));
cc17453a 1133 printf_filtered (" SSR=%08lx SPC=%08lx",
617daa0e 1134 (long) read_register (SSR_REGNUM),
f2ea0907 1135 (long) read_register (SPC_REGNUM));
c906108c 1136
617daa0e
CV		 1137 printf_filtered
1138 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1139 (long) read_register (0), (long) read_register (1),
1140 (long) read_register (2), (long) read_register (3),
1141 (long) read_register (4), (long) read_register (5),
1142 (long) read_register (6), (long) read_register (7));
d4f3574e 1143 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
617daa0e
CV		 1144 (long) read_register (8), (long) read_register (9),
1145 (long) read_register (10), (long) read_register (11),
1146 (long) read_register (12), (long) read_register (13),
1147 (long) read_register (14), (long) read_register (15));
c906108c
SS		 1148}
1149
53116e27 1150
2d188dd3
NC		 1151static void
1152sh2e_show_regs (void)
1153{
1154 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1155 paddr (read_register (PC_REGNUM)),
1156 (long) read_register (SR_REGNUM),
1157 (long) read_register (PR_REGNUM),
1158 (long) read_register (MACH_REGNUM),
1159 (long) read_register (MACL_REGNUM));
1160
1161 printf_filtered ("GBR=%08lx VBR=%08lx",
1162 (long) read_register (GBR_REGNUM),
1163 (long) read_register (VBR_REGNUM));
1164 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
617daa0e
CV		 1165 (long) read_register (FPUL_REGNUM),
1166 (long) read_register (FPSCR_REGNUM));
1167
1168 printf_filtered
1169 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1170 (long) read_register (0), (long) read_register (1),
1171 (long) read_register (2), (long) read_register (3),
1172 (long) read_register (4), (long) read_register (5),
1173 (long) read_register (6), (long) read_register (7));
2d188dd3 1174 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
617daa0e
CV		 1175 (long) read_register (8), (long) read_register (9),
1176 (long) read_register (10), (long) read_register (11),
1177 (long) read_register (12), (long) read_register (13),
1178 (long) read_register (14), (long) read_register (15));
1179
1180 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 0), (long) read_register (FP0_REGNUM + 1), (long) read_register (FP0_REGNUM + 2), (long) read_register (FP0_REGNUM + 3), (long) read_register (FP0_REGNUM + 4), (long) read_register (FP0_REGNUM + 5), (long) read_register (FP0_REGNUM + 6), (long) read_register (FP0_REGNUM + 7));
1181 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 8), (long) read_register (FP0_REGNUM + 9), (long) read_register (FP0_REGNUM + 10), (long) read_register (FP0_REGNUM + 11), (long) read_register (FP0_REGNUM + 12), (long) read_register (FP0_REGNUM + 13), (long) read_register (FP0_REGNUM + 14), (long) read_register (FP0_REGNUM + 15));
2d188dd3
NC		 1182}
1183
cc17453a 1184static void
fba45db2 1185sh3e_show_regs (void)
cc17453a
EZ		 1186{
1187 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1188 paddr (read_register (PC_REGNUM)),
55ff77ac
CV		 1189 (long) read_register (SR_REGNUM),
1190 (long) read_register (PR_REGNUM),
cc17453a
EZ		 1191 (long) read_register (MACH_REGNUM),
1192 (long) read_register (MACL_REGNUM));
1193
1194 printf_filtered ("GBR=%08lx VBR=%08lx",
1195 (long) read_register (GBR_REGNUM),
1196 (long) read_register (VBR_REGNUM));
1197 printf_filtered (" SSR=%08lx SPC=%08lx",
f2ea0907
CV		 1198 (long) read_register (SSR_REGNUM),
1199 (long) read_register (SPC_REGNUM));
cc17453a 1200 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
f2ea0907
CV		 1201 (long) read_register (FPUL_REGNUM),
1202 (long) read_register (FPSCR_REGNUM));
c906108c 1203
617daa0e
CV		 1204 printf_filtered
1205 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1206 (long) read_register (0), (long) read_register (1),
1207 (long) read_register (2), (long) read_register (3),
1208 (long) read_register (4), (long) read_register (5),
1209 (long) read_register (6), (long) read_register (7));
cc17453a 1210 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
617daa0e
CV		 1211 (long) read_register (8), (long) read_register (9),
1212 (long) read_register (10), (long) read_register (11),
1213 (long) read_register (12), (long) read_register (13),
1214 (long) read_register (14), (long) read_register (15));
1215
1216 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 0), (long) read_register (FP0_REGNUM + 1), (long) read_register (FP0_REGNUM + 2), (long) read_register (FP0_REGNUM + 3), (long) read_register (FP0_REGNUM + 4), (long) read_register (FP0_REGNUM + 5), (long) read_register (FP0_REGNUM + 6), (long) read_register (FP0_REGNUM + 7));
1217 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 8), (long) read_register (FP0_REGNUM + 9), (long) read_register (FP0_REGNUM + 10), (long) read_register (FP0_REGNUM + 11), (long) read_register (FP0_REGNUM + 12), (long) read_register (FP0_REGNUM + 13), (long) read_register (FP0_REGNUM + 14), (long) read_register (FP0_REGNUM + 15));
cc17453a
EZ		 1218}
1219
1220static void
fba45db2 1221sh3_dsp_show_regs (void)
c906108c 1222{
cc17453a
EZ		 1223 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1224 paddr (read_register (PC_REGNUM)),
55ff77ac
CV		 1225 (long) read_register (SR_REGNUM),
1226 (long) read_register (PR_REGNUM),
cc17453a
EZ		 1227 (long) read_register (MACH_REGNUM),
1228 (long) read_register (MACL_REGNUM));
c906108c 1229
cc17453a
EZ		 1230 printf_filtered ("GBR=%08lx VBR=%08lx",
1231 (long) read_register (GBR_REGNUM),
1232 (long) read_register (VBR_REGNUM));
1233
1234 printf_filtered (" SSR=%08lx SPC=%08lx",
f2ea0907
CV		 1235 (long) read_register (SSR_REGNUM),
1236 (long) read_register (SPC_REGNUM));
cc17453a 1237
617daa0e
CV		 1238 printf_filtered (" DSR=%08lx", (long) read_register (DSR_REGNUM));
1239
1240 printf_filtered
1241 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1242 (long) read_register (0), (long) read_register (1),
1243 (long) read_register (2), (long) read_register (3),
1244 (long) read_register (4), (long) read_register (5),
1245 (long) read_register (6), (long) read_register (7));
cc17453a 1246 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
617daa0e
CV		 1247 (long) read_register (8), (long) read_register (9),
1248 (long) read_register (10), (long) read_register (11),
1249 (long) read_register (12), (long) read_register (13),
1250 (long) read_register (14), (long) read_register (15));
1251
1252 printf_filtered
1253 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1254 (long) read_register (A0G_REGNUM) & 0xff,
1255 (long) read_register (A0_REGNUM), (long) read_register (M0_REGNUM),
1256 (long) read_register (X0_REGNUM), (long) read_register (Y0_REGNUM),
1257 (long) read_register (RS_REGNUM), (long) read_register (MOD_REGNUM));
cc17453a 1258 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
f2ea0907
CV		 1259 (long) read_register (A1G_REGNUM) & 0xff,
1260 (long) read_register (A1_REGNUM),
1261 (long) read_register (M1_REGNUM),
1262 (long) read_register (X1_REGNUM),
1263 (long) read_register (Y1_REGNUM),
1264 (long) read_register (RE_REGNUM));
c906108c
SS		 1265}
1266
cc17453a 1267static void
fba45db2 1268sh4_show_regs (void)
cc17453a 1269{
f2ea0907 1270 int pr = read_register (FPSCR_REGNUM) & 0x80000;
cc17453a
EZ		 1271 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1272 paddr (read_register (PC_REGNUM)),
55ff77ac
CV		 1273 (long) read_register (SR_REGNUM),
1274 (long) read_register (PR_REGNUM),
cc17453a
EZ		 1275 (long) read_register (MACH_REGNUM),
1276 (long) read_register (MACL_REGNUM));
1277
1278 printf_filtered ("GBR=%08lx VBR=%08lx",
1279 (long) read_register (GBR_REGNUM),
1280 (long) read_register (VBR_REGNUM));
1281 printf_filtered (" SSR=%08lx SPC=%08lx",
f2ea0907
CV		 1282 (long) read_register (SSR_REGNUM),
1283 (long) read_register (SPC_REGNUM));
cc17453a 1284 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
f2ea0907
CV		 1285 (long) read_register (FPUL_REGNUM),
1286 (long) read_register (FPSCR_REGNUM));
cc17453a 1287
617daa0e
CV		 1288 printf_filtered
1289 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1290 (long) read_register (0), (long) read_register (1),
1291 (long) read_register (2), (long) read_register (3),
1292 (long) read_register (4), (long) read_register (5),
1293 (long) read_register (6), (long) read_register (7));
cc17453a 1294 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
617daa0e
CV		 1295 (long) read_register (8), (long) read_register (9),
1296 (long) read_register (10), (long) read_register (11),
1297 (long) read_register (12), (long) read_register (13),
1298 (long) read_register (14), (long) read_register (15));
cc17453a
EZ		 1299
1300 printf_filtered ((pr
1301 ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
617daa0e
CV		 1302 :
1303 "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
cc17453a
EZ		 1304 (long) read_register (FP0_REGNUM + 0),
1305 (long) read_register (FP0_REGNUM + 1),
1306 (long) read_register (FP0_REGNUM + 2),
1307 (long) read_register (FP0_REGNUM + 3),
1308 (long) read_register (FP0_REGNUM + 4),
1309 (long) read_register (FP0_REGNUM + 5),
1310 (long) read_register (FP0_REGNUM + 6),
1311 (long) read_register (FP0_REGNUM + 7));
617daa0e
CV		 1312 printf_filtered ((pr ?
1313 "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n" :
1314 "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
cc17453a
EZ		 1315 (long) read_register (FP0_REGNUM + 8),
1316 (long) read_register (FP0_REGNUM + 9),
1317 (long) read_register (FP0_REGNUM + 10),
1318 (long) read_register (FP0_REGNUM + 11),
1319 (long) read_register (FP0_REGNUM + 12),
1320 (long) read_register (FP0_REGNUM + 13),
1321 (long) read_register (FP0_REGNUM + 14),
1322 (long) read_register (FP0_REGNUM + 15));
1323}
1324
1325static void
fba45db2 1326sh_dsp_show_regs (void)
cc17453a
EZ		 1327{
1328 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1329 paddr (read_register (PC_REGNUM)),
55ff77ac
CV		 1330 (long) read_register (SR_REGNUM),
1331 (long) read_register (PR_REGNUM),
cc17453a
EZ		 1332 (long) read_register (MACH_REGNUM),
1333 (long) read_register (MACL_REGNUM));
1334
1335 printf_filtered ("GBR=%08lx VBR=%08lx",
1336 (long) read_register (GBR_REGNUM),
1337 (long) read_register (VBR_REGNUM));
1338
617daa0e
CV		 1339 printf_filtered (" DSR=%08lx", (long) read_register (DSR_REGNUM));
1340
1341 printf_filtered
1342 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1343 (long) read_register (0), (long) read_register (1),
1344 (long) read_register (2), (long) read_register (3),
1345 (long) read_register (4), (long) read_register (5),
1346 (long) read_register (6), (long) read_register (7));
cc17453a 1347 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
617daa0e
CV		 1348 (long) read_register (8), (long) read_register (9),
1349 (long) read_register (10), (long) read_register (11),
1350 (long) read_register (12), (long) read_register (13),
1351 (long) read_register (14), (long) read_register (15));
1352
1353 printf_filtered
1354 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1355 (long) read_register (A0G_REGNUM) & 0xff,
1356 (long) read_register (A0_REGNUM), (long) read_register (M0_REGNUM),
1357 (long) read_register (X0_REGNUM), (long) read_register (Y0_REGNUM),
1358 (long) read_register (RS_REGNUM), (long) read_register (MOD_REGNUM));
cc17453a 1359 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
f2ea0907
CV		 1360 (long) read_register (A1G_REGNUM) & 0xff,
1361 (long) read_register (A1_REGNUM),
1362 (long) read_register (M1_REGNUM),
1363 (long) read_register (X1_REGNUM),
1364 (long) read_register (Y1_REGNUM),
1365 (long) read_register (RE_REGNUM));
cc17453a
EZ		 1366}
1367
a78f21af
AC		 1368static void
1369sh_show_regs_command (char *args, int from_tty)
53116e27
EZ		 1370{
1371 if (sh_show_regs)
617daa0e 1372 (*sh_show_regs) ();
53116e27
EZ		 1373}
1374
cc17453a
EZ		 1375/* Return the GDB type object for the "standard" data type
1376 of data in register N. */
cc17453a 1377static struct type *
48db5a3c 1378sh_sh3e_register_type (struct gdbarch *gdbarch, int reg_nr)
cc17453a
EZ		 1379{
1380 if ((reg_nr >= FP0_REGNUM
617daa0e 1381 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
cc17453a 1382 return builtin_type_float;
8db62801 1383 else
cc17453a
EZ		 1384 return builtin_type_int;
1385}
1386
7f4dbe94
EZ		 1387static struct type *
1388sh_sh4_build_float_register_type (int high)
1389{
1390 struct type *temp;
1391
1392 temp = create_range_type (NULL, builtin_type_int, 0, high);
1393 return create_array_type (NULL, builtin_type_float, temp);
1394}
1395
53116e27 1396static struct type *
48db5a3c 1397sh_sh4_register_type (struct gdbarch *gdbarch, int reg_nr)
53116e27
EZ		 1398{
1399 if ((reg_nr >= FP0_REGNUM
617daa0e 1400 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
53116e27 1401 return builtin_type_float;
617daa0e 1402 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
53116e27 1403 return builtin_type_double;
617daa0e 1404 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
53116e27
EZ		 1405 return sh_sh4_build_float_register_type (3);
1406 else
1407 return builtin_type_int;
1408}
1409
cc17453a 1410static struct type *
48db5a3c 1411sh_default_register_type (struct gdbarch *gdbarch, int reg_nr)
cc17453a
EZ		 1412{
1413 return builtin_type_int;
1414}
1415
fb409745
EZ		 1416/* On the sh4, the DRi pseudo registers are problematic if the target
1417 is little endian. When the user writes one of those registers, for
1418 instance with 'ser var $dr0=1', we want the double to be stored
1419 like this:
1420 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
1421 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1422
1423 This corresponds to little endian byte order & big endian word
1424 order. However if we let gdb write the register w/o conversion, it
1425 will write fr0 and fr1 this way:
1426 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1427 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
1428 because it will consider fr0 and fr1 as a single LE stretch of memory.
1429
1430 To achieve what we want we must force gdb to store things in
1431 floatformat_ieee_double_littlebyte_bigword (which is defined in
1432 include/floatformat.h and libiberty/floatformat.c.
1433
1434 In case the target is big endian, there is no problem, the
1435 raw bytes will look like:
1436 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
1437 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1438
1439 The other pseudo registers (the FVs) also don't pose a problem
1440 because they are stored as 4 individual FP elements. */
1441
7bd872fe 1442static void
fb409745 1443sh_sh4_register_convert_to_virtual (int regnum, struct type *type,
617daa0e 1444 char *from, char *to)
55ff77ac 1445{
617daa0e 1446 if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
283150cd
EZ		 1447 {
1448 DOUBLEST val;
617daa0e
CV		 1449 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
1450 from, &val);
55ff77ac 1451 store_typed_floating (to, type, val);
283150cd
EZ		 1452 }
1453 else
617daa0e
CV		 1454 error
1455 ("sh_register_convert_to_virtual called with non DR register number");
283150cd
EZ		 1456}
1457
1458static void
1459sh_sh4_register_convert_to_raw (struct type *type, int regnum,
d8124050 1460 const void *from, void *to)
283150cd 1461{
617daa0e 1462 if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
283150cd 1463 {
48db5a3c 1464 DOUBLEST val = extract_typed_floating (from, type);
617daa0e
CV		 1465 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword,
1466 &val, to);
283150cd
EZ		 1467 }
1468 else
617daa0e 1469 error ("sh_register_convert_to_raw called with non DR register number");
283150cd
EZ		 1470}
1471
1c0159e0
CV		 1472/* For vectors of 4 floating point registers. */
1473static int
1474fv_reg_base_num (int fv_regnum)
1475{
1476 int fp_regnum;
1477
617daa0e 1478 fp_regnum = FP0_REGNUM + (fv_regnum - FV0_REGNUM) * 4;
1c0159e0
CV		 1479 return fp_regnum;
1480}
1481
1482/* For double precision floating point registers, i.e 2 fp regs.*/
1483static int
1484dr_reg_base_num (int dr_regnum)
1485{
1486 int fp_regnum;
1487
617daa0e 1488 fp_regnum = FP0_REGNUM + (dr_regnum - DR0_REGNUM) * 2;
1c0159e0
CV		 1489 return fp_regnum;
1490}
1491
a78f21af 1492static void
d8124050
AC		 1493sh_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
1494 int reg_nr, void *buffer)
53116e27
EZ		 1495{
1496 int base_regnum, portion;
d9d9c31f 1497 char temp_buffer[MAX_REGISTER_SIZE];
53116e27 1498
617daa0e 1499 if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
7bd872fe
EZ		 1500 {
1501 base_regnum = dr_reg_base_num (reg_nr);
1502
617daa0e 1503 /* Build the value in the provided buffer. */
7bd872fe
EZ		 1504 /* Read the real regs for which this one is an alias. */
1505 for (portion = 0; portion < 2; portion++)
617daa0e 1506 regcache_raw_read (regcache, base_regnum + portion,
0818c12a 1507 (temp_buffer
617daa0e
CV		 1508 + register_size (gdbarch,
1509 base_regnum) * portion));
7bd872fe
EZ		 1510 /* We must pay attention to the endiannes. */
1511 sh_sh4_register_convert_to_virtual (reg_nr,
617daa0e
CV		 1512 gdbarch_register_type (gdbarch,
1513 reg_nr),
7bd872fe
EZ		 1514 temp_buffer, buffer);
1515 }
617daa0e 1516 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
53116e27 1517 {
7bd872fe
EZ		 1518 base_regnum = fv_reg_base_num (reg_nr);
1519
1520 /* Read the real regs for which this one is an alias. */
1521 for (portion = 0; portion < 4; portion++)
617daa0e 1522 regcache_raw_read (regcache, base_regnum + portion,
d8124050 1523 ((char *) buffer
617daa0e
CV		 1524 + register_size (gdbarch,
1525 base_regnum) * portion));
53116e27
EZ		 1526 }
1527}
1528
a78f21af 1529static void
d8124050
AC		 1530sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
1531 int reg_nr, const void *buffer)
53116e27
EZ		 1532{
1533 int base_regnum, portion;
d9d9c31f 1534 char temp_buffer[MAX_REGISTER_SIZE];
53116e27 1535
617daa0e 1536 if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
53116e27
EZ		 1537 {
1538 base_regnum = dr_reg_base_num (reg_nr);
1539
7bd872fe 1540 /* We must pay attention to the endiannes. */
617daa0e
CV		 1541 sh_sh4_register_convert_to_raw (gdbarch_register_type (gdbarch, reg_nr),
1542 reg_nr, buffer, temp_buffer);
7bd872fe 1543
53116e27
EZ		 1544 /* Write the real regs for which this one is an alias. */
1545 for (portion = 0; portion < 2; portion++)
617daa0e 1546 regcache_raw_write (regcache, base_regnum + portion,
0818c12a 1547 (temp_buffer
617daa0e
CV		 1548 + register_size (gdbarch,
1549 base_regnum) * portion));
53116e27 1550 }
617daa0e 1551 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
53116e27
EZ		 1552 {
1553 base_regnum = fv_reg_base_num (reg_nr);
1554
1555 /* Write the real regs for which this one is an alias. */
1556 for (portion = 0; portion < 4; portion++)
d8124050
AC		 1557 regcache_raw_write (regcache, base_regnum + portion,
1558 ((char *) buffer
617daa0e
CV		 1559 + register_size (gdbarch,
1560 base_regnum) * portion));
53116e27
EZ		 1561 }
1562}
1563
3bbfbb92 1564/* Floating point vector of 4 float registers. */
53116e27 1565static void
48db5a3c
CV		 1566do_fv_register_info (struct gdbarch *gdbarch, struct ui_file *file,
1567 int fv_regnum)
53116e27
EZ		 1568{
1569 int first_fp_reg_num = fv_reg_base_num (fv_regnum);
617daa0e
CV		 1570 fprintf_filtered (file, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
1571 fv_regnum - FV0_REGNUM,
1572 (int) read_register (first_fp_reg_num),
1573 (int) read_register (first_fp_reg_num + 1),
1574 (int) read_register (first_fp_reg_num + 2),
1575 (int) read_register (first_fp_reg_num + 3));
53116e27
EZ		 1576}
1577
3bbfbb92 1578/* Double precision registers. */
53116e27 1579static void
48db5a3c
CV		 1580do_dr_register_info (struct gdbarch *gdbarch, struct ui_file *file,
1581 int dr_regnum)
53116e27
EZ		 1582{
1583 int first_fp_reg_num = dr_reg_base_num (dr_regnum);
1584
617daa0e
CV		 1585 fprintf_filtered (file, "dr%d\t0x%08x%08x\n",
1586 dr_regnum - DR0_REGNUM,
53116e27
EZ		 1587 (int) read_register (first_fp_reg_num),
1588 (int) read_register (first_fp_reg_num + 1));
1589}
1590
1591static void
48db5a3c
CV		 1592sh_print_pseudo_register (struct gdbarch *gdbarch, struct ui_file *file,
1593 int regnum)
53116e27
EZ		 1594{
1595 if (regnum < NUM_REGS || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
8e65ff28
AC		 1596 internal_error (__FILE__, __LINE__,
1597 "Invalid pseudo register number %d\n", regnum);
617daa0e 1598 else if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
48db5a3c 1599 do_dr_register_info (gdbarch, file, regnum);
617daa0e 1600 else if (regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM)
48db5a3c 1601 do_fv_register_info (gdbarch, file, regnum);
53116e27
EZ		 1602}
1603
53116e27 1604static void
48db5a3c 1605sh_do_fp_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
53116e27
EZ		 1606{ /* do values for FP (float) regs */
1607 char *raw_buffer;
617daa0e 1608 double flt; /* double extracted from raw hex data */
53116e27
EZ		 1609 int inv;
1610 int j;
1611
1612 /* Allocate space for the float. */
48db5a3c 1613 raw_buffer = (char *) alloca (register_size (gdbarch, FP0_REGNUM));
53116e27
EZ		 1614
1615 /* Get the data in raw format. */
48db5a3c 1616 if (!frame_register_read (get_selected_frame (), regnum, raw_buffer))
53116e27
EZ		 1617 error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
1618
617daa0e 1619 /* Get the register as a number */
53116e27
EZ		 1620 flt = unpack_double (builtin_type_float, raw_buffer, &inv);
1621
1622 /* Print the name and some spaces. */
48db5a3c
CV		 1623 fputs_filtered (REGISTER_NAME (regnum), file);
1624 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file);
53116e27
EZ		 1625
1626 /* Print the value. */
93d56215 1627 if (inv)
48db5a3c 1628 fprintf_filtered (file, "<invalid float>");
93d56215 1629 else
48db5a3c 1630 fprintf_filtered (file, "%-10.9g", flt);
53116e27
EZ		 1631
1632 /* Print the fp register as hex. */
48db5a3c
CV		 1633 fprintf_filtered (file, "\t(raw 0x");
1634 for (j = 0; j < register_size (gdbarch, regnum); j++)
53116e27 1635 {
221c12ff
AC		 1636 int idx = (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
1637 ? j
1638 : register_size (gdbarch, regnum) - 1 - j);
48db5a3c 1639 fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[idx]);
53116e27 1640 }
48db5a3c
CV		 1641 fprintf_filtered (file, ")");
1642 fprintf_filtered (file, "\n");
53116e27
EZ		 1643}
1644
1645static void
48db5a3c 1646sh_do_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
53116e27 1647{
123a958e 1648 char raw_buffer[MAX_REGISTER_SIZE];
53116e27 1649
48db5a3c
CV		 1650 fputs_filtered (REGISTER_NAME (regnum), file);
1651 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file);
53116e27
EZ		 1652
1653 /* Get the data in raw format. */
48db5a3c
CV		 1654 if (!frame_register_read (get_selected_frame (), regnum, raw_buffer))
1655 fprintf_filtered (file, "*value not available*\n");
617daa0e 1656
48db5a3c
CV		 1657 val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0,
1658 file, 'x', 1, 0, Val_pretty_default);
1659 fprintf_filtered (file, "\t");
1660 val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0,
1661 file, 0, 1, 0, Val_pretty_default);
1662 fprintf_filtered (file, "\n");
53116e27
EZ		 1663}
1664
1665static void
48db5a3c 1666sh_print_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
53116e27
EZ		 1667{
1668 if (regnum < 0 || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
8e65ff28
AC		 1669 internal_error (__FILE__, __LINE__,
1670 "Invalid register number %d\n", regnum);
53116e27 1671
e30839fe 1672 else if (regnum >= 0 && regnum < NUM_REGS)
53116e27 1673 {
617daa0e
CV		 1674 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) ==
1675 TYPE_CODE_FLT)
48db5a3c 1676 sh_do_fp_register (gdbarch, file, regnum); /* FP regs */
53116e27 1677 else
48db5a3c 1678 sh_do_register (gdbarch, file, regnum); /* All other regs */
53116e27
EZ		 1679 }
1680
1681 else if (regnum < NUM_REGS + NUM_PSEUDO_REGS)
48db5a3c 1682 {
55ff77ac 1683 sh_print_pseudo_register (gdbarch, file, regnum);
48db5a3c 1684 }
53116e27
EZ		 1685}
1686
a78f21af 1687static void
48db5a3c
CV		 1688sh_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
1689 struct frame_info *frame, int regnum, int fpregs)
53116e27
EZ		 1690{
1691 if (regnum != -1) /* do one specified register */
1692 {
1693 if (*(REGISTER_NAME (regnum)) == '\0')
1694 error ("Not a valid register for the current processor type");
1695
48db5a3c 1696 sh_print_register (gdbarch, file, regnum);
53116e27
EZ		 1697 }
1698 else
1699 /* do all (or most) registers */
1700 {
1701 regnum = 0;
1702 while (regnum < NUM_REGS)
1703 {
1704 /* If the register name is empty, it is undefined for this
1705 processor, so don't display anything. */
1706 if (REGISTER_NAME (regnum) == NULL
1707 || *(REGISTER_NAME (regnum)) == '\0')
617daa0e 1708 {
53116e27
EZ		 1709 regnum++;
1710 continue;
1711 }
1712
617daa0e
CV		 1713 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) ==
1714 TYPE_CODE_FLT)
53116e27
EZ		 1715 {
1716 if (fpregs)
1717 {
1718 /* true for "INFO ALL-REGISTERS" command */
48db5a3c 1719 sh_do_fp_register (gdbarch, file, regnum); /* FP regs */
617daa0e 1720 regnum++;
53116e27
EZ		 1721 }
1722 else
f2ea0907 1723 regnum += (FP_LAST_REGNUM - FP0_REGNUM); /* skip FP regs */
53116e27
EZ		 1724 }
1725 else
1726 {
48db5a3c 1727 sh_do_register (gdbarch, file, regnum); /* All other regs */
53116e27
EZ		 1728 regnum++;
1729 }
1730 }
1731
1732 if (fpregs)
1733 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
1734 {
55ff77ac 1735 sh_print_pseudo_register (gdbarch, file, regnum);
53116e27
EZ		 1736 regnum++;
1737 }
1738 }
1739}
1740
1a8629c7
MS		 1741#ifdef SVR4_SHARED_LIBS
1742
1743/* Fetch (and possibly build) an appropriate link_map_offsets structure
1744 for native i386 linux targets using the struct offsets defined in
1745 link.h (but without actual reference to that file).
1746
1747 This makes it possible to access i386-linux shared libraries from
1748 a gdb that was not built on an i386-linux host (for cross debugging).
1749 */
1750
1751struct link_map_offsets *
1752sh_linux_svr4_fetch_link_map_offsets (void)
1753{
1754 static struct link_map_offsets lmo;
1755 static struct link_map_offsets *lmp = 0;
1756
1757 if (lmp == 0)
1758 {
1759 lmp = &lmo;
1760
1761 lmo.r_debug_size = 8; /* 20 not actual size but all we need */
1762
1763 lmo.r_map_offset = 4;
617daa0e 1764 lmo.r_map_size = 4;
1a8629c7
MS		 1765
1766 lmo.link_map_size = 20; /* 552 not actual size but all we need */
1767
1768 lmo.l_addr_offset = 0;
617daa0e 1769 lmo.l_addr_size = 4;
1a8629c7
MS		 1770
1771 lmo.l_name_offset = 4;
617daa0e 1772 lmo.l_name_size = 4;
1a8629c7
MS		 1773
1774 lmo.l_next_offset = 12;
617daa0e 1775 lmo.l_next_size = 4;
1a8629c7
MS		 1776
1777 lmo.l_prev_offset = 16;
617daa0e 1778 lmo.l_prev_size = 4;
1a8629c7
MS		 1779 }
1780
617daa0e 1781 return lmp;
1a8629c7
MS		 1782}
1783#endif /* SVR4_SHARED_LIBS */
1784
2f14585c
JR		 1785static int
1786sh_dsp_register_sim_regno (int nr)
1787{
1788 if (legacy_register_sim_regno (nr) < 0)
1789 return legacy_register_sim_regno (nr);
f2ea0907
CV		 1790 if (nr >= DSR_REGNUM && nr <= Y1_REGNUM)
1791 return nr - DSR_REGNUM + SIM_SH_DSR_REGNUM;
1792 if (nr == MOD_REGNUM)
2f14585c 1793 return SIM_SH_MOD_REGNUM;
f2ea0907 1794 if (nr == RS_REGNUM)
2f14585c 1795 return SIM_SH_RS_REGNUM;
f2ea0907 1796 if (nr == RE_REGNUM)
2f14585c 1797 return SIM_SH_RE_REGNUM;
f2ea0907
CV		 1798 if (nr >= R0_BANK_REGNUM && nr <= R7_BANK_REGNUM)
1799 return nr - R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM;
2f14585c
JR		 1800 return nr;
1801}
1c0159e0
CV		 1802
1803static struct sh_frame_cache *
1804sh_alloc_frame_cache (void)
1805{
1806 struct sh_frame_cache *cache;
1807 int i;
1808
1809 cache = FRAME_OBSTACK_ZALLOC (struct sh_frame_cache);
1810
1811 /* Base address. */
1812 cache->base = 0;
1813 cache->saved_sp = 0;
1814 cache->sp_offset = 0;
1815 cache->pc = 0;
1816
1817 /* Frameless until proven otherwise. */
1818 cache->uses_fp = 0;
617daa0e 1819
1c0159e0
CV		 1820 /* Saved registers. We initialize these to -1 since zero is a valid
1821 offset (that's where fp is supposed to be stored). */
1822 for (i = 0; i < SH_NUM_REGS; i++)
1823 {
1824 cache->saved_regs[i] = -1;
1825 }
617daa0e 1826
1c0159e0 1827 return cache;
617daa0e 1828}
1c0159e0
CV		 1829
1830static struct sh_frame_cache *
1831sh_frame_cache (struct frame_info *next_frame, void **this_cache)
1832{
1833 struct sh_frame_cache *cache;
1834 CORE_ADDR current_pc;
1835 int i;
1836
1837 if (*this_cache)
1838 return *this_cache;
1839
1840 cache = sh_alloc_frame_cache ();
1841 *this_cache = cache;
1842
1843 /* In principle, for normal frames, fp holds the frame pointer,
1844 which holds the base address for the current stack frame.
1845 However, for functions that don't need it, the frame pointer is
1846 optional. For these "frameless" functions the frame pointer is
1847 actually the frame pointer of the calling frame. */
1848 cache->base = frame_unwind_register_unsigned (next_frame, FP_REGNUM);
1849 if (cache->base == 0)
1850 return cache;
1851
1852 cache->pc = frame_func_unwind (next_frame);
1853 current_pc = frame_pc_unwind (next_frame);
1854 if (cache->pc != 0)
1855 sh_analyze_prologue (cache->pc, current_pc, cache);
617daa0e 1856
1c0159e0
CV		 1857 if (!cache->uses_fp)
1858 {
1859 /* We didn't find a valid frame, which means that CACHE->base
1860 currently holds the frame pointer for our calling frame. If
1861 we're at the start of a function, or somewhere half-way its
1862 prologue, the function's frame probably hasn't been fully
1863 setup yet. Try to reconstruct the base address for the stack
1864 frame by looking at the stack pointer. For truly "frameless"
1865 functions this might work too. */
1866 cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
1867 }
1868
1869 /* Now that we have the base address for the stack frame we can
1870 calculate the value of sp in the calling frame. */
1871 cache->saved_sp = cache->base + cache->sp_offset;
1872
1873 /* Adjust all the saved registers such that they contain addresses
1874 instead of offsets. */
1875 for (i = 0; i < SH_NUM_REGS; i++)
1876 if (cache->saved_regs[i] != -1)
1877 cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i] - 4;
1878
1879 return cache;
1880}
1881
1882static void
1883sh_frame_prev_register (struct frame_info *next_frame, void **this_cache,
1884 int regnum, int *optimizedp,
1885 enum lval_type *lvalp, CORE_ADDR *addrp,
1886 int *realnump, void *valuep)
1887{
1888 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
1889
1890 gdb_assert (regnum >= 0);
1891
1892 if (regnum == SP_REGNUM && cache->saved_sp)
1893 {
1894 *optimizedp = 0;
1895 *lvalp = not_lval;
1896 *addrp = 0;
1897 *realnump = -1;
1898 if (valuep)
617daa0e
CV		 1899 {
1900 /* Store the value. */
1901 store_unsigned_integer (valuep, 4, cache->saved_sp);
1902 }
1c0159e0
CV		 1903 return;
1904 }
1905
1906 /* The PC of the previous frame is stored in the PR register of
1907 the current frame. Frob regnum so that we pull the value from
1908 the correct place. */
1909 if (regnum == PC_REGNUM)
1910 regnum = PR_REGNUM;
1911
1912 if (regnum < SH_NUM_REGS && cache->saved_regs[regnum] != -1)
1913 {
1914 *optimizedp = 0;
1915 *lvalp = lval_memory;
1916 *addrp = cache->saved_regs[regnum];
1917 *realnump = -1;
1918 if (valuep)
617daa0e
CV		 1919 {
1920 /* Read the value in from memory. */
1921 read_memory (*addrp, valuep,
1922 register_size (current_gdbarch, regnum));
1923 }
1c0159e0
CV		 1924 return;
1925 }
1926
1927 frame_register_unwind (next_frame, regnum,
617daa0e 1928 optimizedp, lvalp, addrp, realnump, valuep);
1c0159e0
CV		 1929}
1930
1931static void
1932sh_frame_this_id (struct frame_info *next_frame, void **this_cache,
617daa0e
CV		 1933 struct frame_id *this_id)
1934{
1c0159e0
CV		 1935 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
1936
1937 /* This marks the outermost frame. */
1938 if (cache->base == 0)
1939 return;
1940
1941 *this_id = frame_id_build (cache->saved_sp, cache->pc);
617daa0e 1942}
1c0159e0 1943
617daa0e 1944static const struct frame_unwind sh_frame_unwind = {
1c0159e0
CV		 1945 NORMAL_FRAME,
1946 sh_frame_this_id,
1947 sh_frame_prev_register
1948};
1949
1950static const struct frame_unwind *
1951sh_frame_sniffer (struct frame_info *next_frame)
1952{
1953 return &sh_frame_unwind;
1954}
1955
1956static CORE_ADDR
1957sh_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1958{
1959 return frame_unwind_register_unsigned (next_frame, SP_REGNUM);
1960}
1961
1962static CORE_ADDR
1963sh_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1964{
1965 return frame_unwind_register_unsigned (next_frame, PC_REGNUM);
1966}
1967
1968static struct frame_id
1969sh_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
1970{
1971 return frame_id_build (sh_unwind_sp (gdbarch, next_frame),
1972 frame_pc_unwind (next_frame));
1973}
1974
1975static CORE_ADDR
1976sh_frame_base_address (struct frame_info *next_frame, void **this_cache)
617daa0e 1977{
1c0159e0 1978 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
617daa0e 1979
1c0159e0
CV		 1980 return cache->base;
1981}
617daa0e
CV		 1982
1983static const struct frame_base sh_frame_base = {
1c0159e0
CV		 1984 &sh_frame_unwind,
1985 sh_frame_base_address,
1986 sh_frame_base_address,
1987 sh_frame_base_address
617daa0e 1988};
1c0159e0
CV		 1989
1990/* The epilogue is defined here as the area at the end of a function,
1991 either on the `ret' instruction itself or after an instruction which
1992 destroys the function's stack frame. */
1993static int
1994sh_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
1995{
1996 CORE_ADDR func_addr = 0, func_end = 0;
1997
1998 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
1999 {
2000 ULONGEST inst;
2001 /* The sh epilogue is max. 14 bytes long. Give another 14 bytes
2002 for a nop and some fixed data (e.g. big offsets) which are
617daa0e
CV		 2003 unfortunately also treated as part of the function (which
2004 means, they are below func_end. */
1c0159e0
CV		 2005 CORE_ADDR addr = func_end - 28;
2006 if (addr < func_addr + 4)
617daa0e 2007 addr = func_addr + 4;
1c0159e0
CV		 2008 if (pc < addr)
2009 return 0;
2010
2011 /* First search forward until hitting an rts. */
2012 while (addr < func_end
617daa0e 2013 && !IS_RTS (read_memory_unsigned_integer (addr, 2)))
1c0159e0
CV		 2014 addr += 2;
2015 if (addr >= func_end)
617daa0e 2016 return 0;
1c0159e0
CV		 2017
2018 /* At this point we should find a mov.l @r15+,r14 instruction,
2019 either before or after the rts. If not, then the function has
617daa0e 2020 probably no "normal" epilogue and we bail out here. */
1c0159e0
CV		 2021 inst = read_memory_unsigned_integer (addr - 2, 2);
2022 if (IS_RESTORE_FP (read_memory_unsigned_integer (addr - 2, 2)))
617daa0e 2023 addr -= 2;
1c0159e0
CV		 2024 else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr + 2, 2)))
2025 return 0;
2026
2027 /* Step over possible lds.l @r15+,pr. */
2028 inst = read_memory_unsigned_integer (addr - 2, 2);
2029 if (IS_LDS (inst))
617daa0e 2030 {
1c0159e0
CV		 2031 addr -= 2;
2032 inst = read_memory_unsigned_integer (addr - 2, 2);
2033 }
2034
2035 /* Step over possible mov r14,r15. */
2036 if (IS_MOV_FP_SP (inst))
617daa0e 2037 {
1c0159e0
CV		 2038 addr -= 2;
2039 inst = read_memory_unsigned_integer (addr - 2, 2);
2040 }
2041
2042 /* Now check for FP adjustments, using add #imm,r14 or add rX, r14
2043 instructions. */
2044 while (addr > func_addr + 4
617daa0e 2045 && (IS_ADD_REG_TO_FP (inst) || IS_ADD_IMM_FP (inst)))
1c0159e0
CV		 2046 {
2047 addr -= 2;
2048 inst = read_memory_unsigned_integer (addr - 2, 2);
2049 }
2050
2051 if (pc >= addr)
2052 return 1;
2053 }
2054 return 0;
2055}
2056
cc17453a
EZ		 2057static gdbarch_init_ftype sh_gdbarch_init;
2058
2059static struct gdbarch *
fba45db2 2060sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
cc17453a 2061{
cc17453a 2062 struct gdbarch *gdbarch;
d658f924 2063
55ff77ac
CV		 2064 sh_show_regs = sh_generic_show_regs;
2065 switch (info.bfd_arch_info->mach)
2066 {
617daa0e
CV		 2067 case bfd_mach_sh2e:
2068 sh_show_regs = sh2e_show_regs;
2069 break;
2070 case bfd_mach_sh_dsp:
2071 sh_show_regs = sh_dsp_show_regs;
2072 break;
55ff77ac 2073
617daa0e
CV		 2074 case bfd_mach_sh3:
2075 sh_show_regs = sh3_show_regs;
2076 break;
55ff77ac 2077
617daa0e
CV		 2078 case bfd_mach_sh3e:
2079 sh_show_regs = sh3e_show_regs;
2080 break;
55ff77ac 2081
617daa0e
CV		 2082 case bfd_mach_sh3_dsp:
2083 sh_show_regs = sh3_dsp_show_regs;
2084 break;
55ff77ac 2085
617daa0e
CV		 2086 case bfd_mach_sh4:
2087 sh_show_regs = sh4_show_regs;
2088 break;
55ff77ac 2089
617daa0e
CV		 2090 case bfd_mach_sh5:
2091 sh_show_regs = sh64_show_regs;
2092 /* SH5 is handled entirely in sh64-tdep.c */
2093 return sh64_gdbarch_init (info, arches);
55ff77ac
CV		 2094 }
2095
4be87837
DJ		 2096 /* If there is already a candidate, use it. */
2097 arches = gdbarch_list_lookup_by_info (arches, &info);
2098 if (arches != NULL)
2099 return arches->gdbarch;
cc17453a
EZ		 2100
2101 /* None found, create a new architecture from the information
2102 provided. */
f2ea0907 2103 gdbarch = gdbarch_alloc (&info, NULL);
cc17453a 2104
48db5a3c
CV		 2105 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2106 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
ec920329 2107 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
48db5a3c
CV		 2108 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2109 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2110 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2111 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
a38d2a54 2112 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
48db5a3c 2113
f2ea0907 2114 set_gdbarch_num_regs (gdbarch, SH_NUM_REGS);
a38d2a54 2115 set_gdbarch_sp_regnum (gdbarch, 15);
a38d2a54 2116 set_gdbarch_pc_regnum (gdbarch, 16);
48db5a3c
CV		 2117 set_gdbarch_fp0_regnum (gdbarch, -1);
2118 set_gdbarch_num_pseudo_regs (gdbarch, 0);
2119
1c0159e0
CV		 2120 set_gdbarch_register_type (gdbarch, sh_default_register_type);
2121
2122 set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info);
2123
eaf90c5d 2124 set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc);
3bbfbb92 2125 set_gdbarch_use_struct_convention (gdbarch, sh_use_struct_convention);
48db5a3c 2126
2bf0cb65 2127 set_gdbarch_print_insn (gdbarch, gdb_print_insn_sh);
2f14585c 2128 set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);
48db5a3c
CV		 2129
2130 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
2131
1c0159e0
CV		 2132 set_gdbarch_store_return_value (gdbarch, sh_default_store_return_value);
2133 set_gdbarch_extract_return_value (gdbarch, sh_default_extract_return_value);
2134 set_gdbarch_extract_struct_value_address (gdbarch,
2135 sh_extract_struct_value_address);
2136
48db5a3c
CV		 2137 set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
2138 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2139 set_gdbarch_decr_pc_after_break (gdbarch, 0);
2140 set_gdbarch_function_start_offset (gdbarch, 0);
2141
1c0159e0
CV		 2142 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu);
2143
48db5a3c 2144 set_gdbarch_frame_args_skip (gdbarch, 0);
1c0159e0
CV		 2145 set_gdbarch_frameless_function_invocation (gdbarch,
2146 frameless_look_for_prologue);
48db5a3c
CV		 2147 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2148
19f59343 2149 set_gdbarch_frame_align (gdbarch, sh_frame_align);
1c0159e0
CV		 2150 set_gdbarch_unwind_sp (gdbarch, sh_unwind_sp);
2151 set_gdbarch_unwind_pc (gdbarch, sh_unwind_pc);
2152 set_gdbarch_unwind_dummy_id (gdbarch, sh_unwind_dummy_id);
2153 frame_base_set_default (gdbarch, &sh_frame_base);
2154
617daa0e 2155 set_gdbarch_in_function_epilogue_p (gdbarch, sh_in_function_epilogue_p);
cc17453a
EZ		 2156
2157 switch (info.bfd_arch_info->mach)
8db62801 2158 {
cc17453a 2159 case bfd_mach_sh:
48db5a3c 2160 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
cc17453a 2161 break;
1c0159e0 2162
cc17453a 2163 case bfd_mach_sh2:
48db5a3c 2164 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
617daa0e 2165 break;
1c0159e0 2166
2d188dd3 2167 case bfd_mach_sh2e:
48db5a3c
CV		 2168 /* doubles on sh2e and sh3e are actually 4 byte. */
2169 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2170
2171 set_gdbarch_register_name (gdbarch, sh_sh2e_register_name);
48db5a3c 2172 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
2d188dd3 2173 set_gdbarch_fp0_regnum (gdbarch, 25);
48db5a3c 2174 set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
617daa0e
CV		 2175 set_gdbarch_extract_return_value (gdbarch,
2176 sh3e_sh4_extract_return_value);
6df2bf50 2177 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2d188dd3 2178 break;
1c0159e0 2179
cc17453a 2180 case bfd_mach_sh_dsp:
48db5a3c 2181 set_gdbarch_register_name (gdbarch, sh_sh_dsp_register_name);
2f14585c 2182 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
cc17453a 2183 break;
1c0159e0 2184
cc17453a 2185 case bfd_mach_sh3:
48db5a3c 2186 set_gdbarch_register_name (gdbarch, sh_sh3_register_name);
cc17453a 2187 break;
1c0159e0 2188
cc17453a 2189 case bfd_mach_sh3e:
48db5a3c
CV		 2190 /* doubles on sh2e and sh3e are actually 4 byte. */
2191 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2192
2193 set_gdbarch_register_name (gdbarch, sh_sh3e_register_name);
48db5a3c 2194 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
cc17453a 2195 set_gdbarch_fp0_regnum (gdbarch, 25);
48db5a3c 2196 set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
617daa0e
CV		 2197 set_gdbarch_extract_return_value (gdbarch,
2198 sh3e_sh4_extract_return_value);
6df2bf50 2199 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
cc17453a 2200 break;
1c0159e0 2201
cc17453a 2202 case bfd_mach_sh3_dsp:
48db5a3c 2203 set_gdbarch_register_name (gdbarch, sh_sh3_dsp_register_name);
48db5a3c 2204 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
cc17453a 2205 break;
1c0159e0 2206
cc17453a 2207 case bfd_mach_sh4:
48db5a3c 2208 set_gdbarch_register_name (gdbarch, sh_sh4_register_name);
48db5a3c 2209 set_gdbarch_register_type (gdbarch, sh_sh4_register_type);
cc17453a 2210 set_gdbarch_fp0_regnum (gdbarch, 25);
53116e27 2211 set_gdbarch_num_pseudo_regs (gdbarch, 12);
d8124050
AC		 2212 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
2213 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
48db5a3c 2214 set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
617daa0e
CV		 2215 set_gdbarch_extract_return_value (gdbarch,
2216 sh3e_sh4_extract_return_value);
6df2bf50 2217 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
cc17453a 2218 break;
1c0159e0 2219
cc17453a 2220 default:
48db5a3c 2221 set_gdbarch_register_name (gdbarch, sh_generic_register_name);
cc17453a 2222 break;
8db62801 2223 }
cc17453a 2224
4be87837
DJ		 2225 /* Hook in ABI-specific overrides, if they have been registered. */
2226 gdbarch_init_osabi (info, gdbarch);
d658f924 2227
1c0159e0
CV		 2228 frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer);
2229 frame_unwind_append_sniffer (gdbarch, sh_frame_sniffer);
2230
cc17453a 2231 return gdbarch;
8db62801
EZ		 2232}
2233
617daa0e 2234extern initialize_file_ftype _initialize_sh_tdep; /* -Wmissing-prototypes */
a78f21af 2235
c906108c 2236void
fba45db2 2237_initialize_sh_tdep (void)
c906108c
SS		 2238{
2239 struct cmd_list_element *c;
617daa0e 2240
f2ea0907 2241 gdbarch_register (bfd_arch_sh, sh_gdbarch_init, NULL);
c906108c 2242
53116e27 2243 add_com ("regs", class_vars, sh_show_regs_command, "Print all registers");
c906108c 2244}
GDB Binutils - Deliverables
This page took 0.532521 seconds and 4 git commands to generate.