Commit | Line | Data |
---|---|---|
85a453d5 | 1 | /* Target-dependent code for Renesas Super-H, for GDB. |
0fd88904 | 2 | |
6aba47ca | 3 | Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
7b6bb8da JB |
4 | 2003, 2004, 2005, 2007, 2008, 2009, 2010, 2011 |
5 | Free Software Foundation, Inc. | |
c906108c | 6 | |
c5aa993b | 7 | This file is part of GDB. |
c906108c | 8 | |
c5aa993b JM |
9 | This program is free software; you can redistribute it and/or modify |
10 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 11 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 12 | (at your option) any later version. |
c906108c | 13 | |
c5aa993b JM |
14 | This program is distributed in the hope that it will be useful, |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
c906108c | 18 | |
c5aa993b | 19 | You should have received a copy of the GNU General Public License |
a9762ec7 | 20 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c | 21 | |
c378eb4e MS |
22 | /* Contributed by Steve Chamberlain |
23 | sac@cygnus.com. */ | |
c906108c SS |
24 | |
25 | #include "defs.h" | |
26 | #include "frame.h" | |
1c0159e0 CV |
27 | #include "frame-base.h" |
28 | #include "frame-unwind.h" | |
29 | #include "dwarf2-frame.h" | |
c906108c | 30 | #include "symtab.h" |
c906108c SS |
31 | #include "gdbtypes.h" |
32 | #include "gdbcmd.h" | |
33 | #include "gdbcore.h" | |
34 | #include "value.h" | |
35 | #include "dis-asm.h" | |
73c1f219 | 36 | #include "inferior.h" |
c906108c | 37 | #include "gdb_string.h" |
1c0159e0 | 38 | #include "gdb_assert.h" |
b4a20239 | 39 | #include "arch-utils.h" |
fb409745 | 40 | #include "floatformat.h" |
4e052eda | 41 | #include "regcache.h" |
d16aafd8 | 42 | #include "doublest.h" |
4be87837 | 43 | #include "osabi.h" |
dda63807 | 44 | #include "reggroups.h" |
c9ac0a72 | 45 | #include "regset.h" |
c906108c | 46 | |
ab3b8126 JT |
47 | #include "sh-tdep.h" |
48 | ||
d658f924 | 49 | #include "elf-bfd.h" |
1a8629c7 MS |
50 | #include "solib-svr4.h" |
51 | ||
55ff77ac | 52 | /* sh flags */ |
283150cd | 53 | #include "elf/sh.h" |
fa8f86ff | 54 | #include "dwarf2.h" |
c378eb4e | 55 | /* registers numbers shared with the simulator. */ |
1c922164 | 56 | #include "gdb/sim-sh.h" |
283150cd | 57 | |
c055b101 CV |
58 | /* List of "set sh ..." and "show sh ..." commands. */ |
59 | static struct cmd_list_element *setshcmdlist = NULL; | |
60 | static struct cmd_list_element *showshcmdlist = NULL; | |
61 | ||
62 | static const char sh_cc_gcc[] = "gcc"; | |
63 | static const char sh_cc_renesas[] = "renesas"; | |
64 | static const char *sh_cc_enum[] = { | |
65 | sh_cc_gcc, | |
66 | sh_cc_renesas, | |
67 | NULL | |
68 | }; | |
69 | ||
70 | static const char *sh_active_calling_convention = sh_cc_gcc; | |
71 | ||
c458d6db | 72 | static void (*sh_show_regs) (struct frame_info *); |
cc17453a | 73 | |
da962468 | 74 | #define SH_NUM_REGS 67 |
88e04cc1 | 75 | |
1c0159e0 | 76 | struct sh_frame_cache |
cc17453a | 77 | { |
1c0159e0 CV |
78 | /* Base address. */ |
79 | CORE_ADDR base; | |
80 | LONGEST sp_offset; | |
81 | CORE_ADDR pc; | |
82 | ||
c378eb4e | 83 | /* Flag showing that a frame has been created in the prologue code. */ |
1c0159e0 CV |
84 | int uses_fp; |
85 | ||
86 | /* Saved registers. */ | |
87 | CORE_ADDR saved_regs[SH_NUM_REGS]; | |
88 | CORE_ADDR saved_sp; | |
63978407 | 89 | }; |
c906108c | 90 | |
c055b101 CV |
91 | static int |
92 | sh_is_renesas_calling_convention (struct type *func_type) | |
93 | { | |
94 | return ((func_type | |
95 | && TYPE_CALLING_CONVENTION (func_type) == DW_CC_GNU_renesas_sh) | |
96 | || sh_active_calling_convention == sh_cc_renesas); | |
97 | } | |
98 | ||
fa88f677 | 99 | static const char * |
d93859e2 | 100 | sh_sh_register_name (struct gdbarch *gdbarch, int reg_nr) |
cc17453a | 101 | { |
617daa0e CV |
102 | static char *register_names[] = { |
103 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
104 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
105 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
106 | "", "", | |
107 | "", "", "", "", "", "", "", "", | |
108 | "", "", "", "", "", "", "", "", | |
109 | "", "", | |
110 | "", "", "", "", "", "", "", "", | |
111 | "", "", "", "", "", "", "", "", | |
da962468 | 112 | "", "", "", "", "", "", "", "", |
cc17453a EZ |
113 | }; |
114 | if (reg_nr < 0) | |
115 | return NULL; | |
116 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
117 | return NULL; | |
118 | return register_names[reg_nr]; | |
119 | } | |
120 | ||
fa88f677 | 121 | static const char * |
d93859e2 | 122 | sh_sh3_register_name (struct gdbarch *gdbarch, int reg_nr) |
cc17453a | 123 | { |
617daa0e CV |
124 | static char *register_names[] = { |
125 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
126 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
127 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
128 | "", "", | |
129 | "", "", "", "", "", "", "", "", | |
130 | "", "", "", "", "", "", "", "", | |
131 | "ssr", "spc", | |
cc17453a EZ |
132 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", |
133 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1" | |
da962468 | 134 | "", "", "", "", "", "", "", "", |
cc17453a EZ |
135 | }; |
136 | if (reg_nr < 0) | |
137 | return NULL; | |
138 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
139 | return NULL; | |
140 | return register_names[reg_nr]; | |
141 | } | |
142 | ||
fa88f677 | 143 | static const char * |
d93859e2 | 144 | sh_sh3e_register_name (struct gdbarch *gdbarch, int reg_nr) |
cc17453a | 145 | { |
617daa0e CV |
146 | static char *register_names[] = { |
147 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
148 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
149 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
cc17453a | 150 | "fpul", "fpscr", |
617daa0e CV |
151 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", |
152 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
153 | "ssr", "spc", | |
cc17453a EZ |
154 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", |
155 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", | |
da962468 | 156 | "", "", "", "", "", "", "", "", |
cc17453a EZ |
157 | }; |
158 | if (reg_nr < 0) | |
159 | return NULL; | |
160 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
161 | return NULL; | |
162 | return register_names[reg_nr]; | |
163 | } | |
164 | ||
2d188dd3 | 165 | static const char * |
d93859e2 | 166 | sh_sh2e_register_name (struct gdbarch *gdbarch, int reg_nr) |
2d188dd3 | 167 | { |
617daa0e CV |
168 | static char *register_names[] = { |
169 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
170 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
171 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
2d188dd3 | 172 | "fpul", "fpscr", |
617daa0e CV |
173 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", |
174 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
175 | "", "", | |
2d188dd3 NC |
176 | "", "", "", "", "", "", "", "", |
177 | "", "", "", "", "", "", "", "", | |
da962468 CV |
178 | "", "", "", "", "", "", "", "", |
179 | }; | |
180 | if (reg_nr < 0) | |
181 | return NULL; | |
182 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
183 | return NULL; | |
184 | return register_names[reg_nr]; | |
185 | } | |
186 | ||
187 | static const char * | |
d93859e2 | 188 | sh_sh2a_register_name (struct gdbarch *gdbarch, int reg_nr) |
da962468 CV |
189 | { |
190 | static char *register_names[] = { | |
191 | /* general registers 0-15 */ | |
192 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
193 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
194 | /* 16 - 22 */ | |
195 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
196 | /* 23, 24 */ | |
197 | "fpul", "fpscr", | |
198 | /* floating point registers 25 - 40 */ | |
199 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", | |
200 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
201 | /* 41, 42 */ | |
202 | "", "", | |
203 | /* 43 - 62. Banked registers. The bank number used is determined by | |
c378eb4e | 204 | the bank register (63). */ |
da962468 CV |
205 | "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b", |
206 | "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", | |
207 | "machb", "ivnb", "prb", "gbrb", "maclb", | |
208 | /* 63: register bank number, not a real register but used to | |
209 | communicate the register bank currently get/set. This register | |
210 | is hidden to the user, who manipulates it using the pseudo | |
211 | register called "bank" (67). See below. */ | |
212 | "", | |
213 | /* 64 - 66 */ | |
214 | "ibcr", "ibnr", "tbr", | |
215 | /* 67: register bank number, the user visible pseudo register. */ | |
216 | "bank", | |
217 | /* double precision (pseudo) 68 - 75 */ | |
218 | "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", | |
219 | }; | |
220 | if (reg_nr < 0) | |
221 | return NULL; | |
222 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
223 | return NULL; | |
224 | return register_names[reg_nr]; | |
225 | } | |
226 | ||
227 | static const char * | |
d93859e2 | 228 | sh_sh2a_nofpu_register_name (struct gdbarch *gdbarch, int reg_nr) |
da962468 CV |
229 | { |
230 | static char *register_names[] = { | |
231 | /* general registers 0-15 */ | |
232 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
233 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
234 | /* 16 - 22 */ | |
235 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
236 | /* 23, 24 */ | |
237 | "", "", | |
238 | /* floating point registers 25 - 40 */ | |
239 | "", "", "", "", "", "", "", "", | |
240 | "", "", "", "", "", "", "", "", | |
241 | /* 41, 42 */ | |
242 | "", "", | |
243 | /* 43 - 62. Banked registers. The bank number used is determined by | |
c378eb4e | 244 | the bank register (63). */ |
da962468 CV |
245 | "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b", |
246 | "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", | |
247 | "machb", "ivnb", "prb", "gbrb", "maclb", | |
248 | /* 63: register bank number, not a real register but used to | |
249 | communicate the register bank currently get/set. This register | |
250 | is hidden to the user, who manipulates it using the pseudo | |
251 | register called "bank" (67). See below. */ | |
252 | "", | |
253 | /* 64 - 66 */ | |
254 | "ibcr", "ibnr", "tbr", | |
255 | /* 67: register bank number, the user visible pseudo register. */ | |
256 | "bank", | |
257 | /* double precision (pseudo) 68 - 75 */ | |
258 | "", "", "", "", "", "", "", "", | |
2d188dd3 NC |
259 | }; |
260 | if (reg_nr < 0) | |
261 | return NULL; | |
262 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
263 | return NULL; | |
264 | return register_names[reg_nr]; | |
265 | } | |
266 | ||
fa88f677 | 267 | static const char * |
d93859e2 | 268 | sh_sh_dsp_register_name (struct gdbarch *gdbarch, int reg_nr) |
cc17453a | 269 | { |
617daa0e CV |
270 | static char *register_names[] = { |
271 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
272 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
273 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
274 | "", "dsr", | |
275 | "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1", | |
276 | "y0", "y1", "", "", "", "", "", "mod", | |
277 | "", "", | |
278 | "rs", "re", "", "", "", "", "", "", | |
279 | "", "", "", "", "", "", "", "", | |
da962468 | 280 | "", "", "", "", "", "", "", "", |
cc17453a EZ |
281 | }; |
282 | if (reg_nr < 0) | |
283 | return NULL; | |
284 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
285 | return NULL; | |
286 | return register_names[reg_nr]; | |
287 | } | |
288 | ||
fa88f677 | 289 | static const char * |
d93859e2 | 290 | sh_sh3_dsp_register_name (struct gdbarch *gdbarch, int reg_nr) |
cc17453a | 291 | { |
617daa0e CV |
292 | static char *register_names[] = { |
293 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
294 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
295 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
296 | "", "dsr", | |
297 | "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1", | |
298 | "y0", "y1", "", "", "", "", "", "mod", | |
299 | "ssr", "spc", | |
300 | "rs", "re", "", "", "", "", "", "", | |
026a72f8 CV |
301 | "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b", |
302 | "", "", "", "", "", "", "", "", | |
da962468 | 303 | "", "", "", "", "", "", "", "", |
cc17453a EZ |
304 | }; |
305 | if (reg_nr < 0) | |
306 | return NULL; | |
307 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
308 | return NULL; | |
309 | return register_names[reg_nr]; | |
310 | } | |
311 | ||
fa88f677 | 312 | static const char * |
d93859e2 | 313 | sh_sh4_register_name (struct gdbarch *gdbarch, int reg_nr) |
53116e27 | 314 | { |
617daa0e | 315 | static char *register_names[] = { |
a38d2a54 | 316 | /* general registers 0-15 */ |
617daa0e CV |
317 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
318 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
a38d2a54 | 319 | /* 16 - 22 */ |
617daa0e | 320 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", |
a38d2a54 | 321 | /* 23, 24 */ |
53116e27 | 322 | "fpul", "fpscr", |
a38d2a54 | 323 | /* floating point registers 25 - 40 */ |
617daa0e CV |
324 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", |
325 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
a38d2a54 | 326 | /* 41, 42 */ |
617daa0e | 327 | "ssr", "spc", |
a38d2a54 | 328 | /* bank 0 43 - 50 */ |
53116e27 | 329 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", |
a38d2a54 | 330 | /* bank 1 51 - 58 */ |
53116e27 | 331 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", |
da962468 | 332 | "", "", "", "", "", "", "", "", |
c378eb4e | 333 | /* pseudo bank register. */ |
da962468 | 334 | "", |
a38d2a54 | 335 | /* double precision (pseudo) 59 - 66 */ |
617daa0e | 336 | "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", |
a38d2a54 | 337 | /* vectors (pseudo) 67 - 70 */ |
617daa0e | 338 | "fv0", "fv4", "fv8", "fv12", |
a38d2a54 EZ |
339 | /* FIXME: missing XF 71 - 86 */ |
340 | /* FIXME: missing XD 87 - 94 */ | |
53116e27 EZ |
341 | }; |
342 | if (reg_nr < 0) | |
343 | return NULL; | |
344 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
345 | return NULL; | |
346 | return register_names[reg_nr]; | |
347 | } | |
348 | ||
474e5826 | 349 | static const char * |
d93859e2 | 350 | sh_sh4_nofpu_register_name (struct gdbarch *gdbarch, int reg_nr) |
474e5826 CV |
351 | { |
352 | static char *register_names[] = { | |
353 | /* general registers 0-15 */ | |
354 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
355 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
356 | /* 16 - 22 */ | |
357 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
358 | /* 23, 24 */ | |
359 | "", "", | |
360 | /* floating point registers 25 - 40 -- not for nofpu target */ | |
361 | "", "", "", "", "", "", "", "", | |
362 | "", "", "", "", "", "", "", "", | |
363 | /* 41, 42 */ | |
364 | "ssr", "spc", | |
365 | /* bank 0 43 - 50 */ | |
366 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", | |
367 | /* bank 1 51 - 58 */ | |
368 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", | |
da962468 | 369 | "", "", "", "", "", "", "", "", |
c378eb4e | 370 | /* pseudo bank register. */ |
da962468 | 371 | "", |
474e5826 CV |
372 | /* double precision (pseudo) 59 - 66 -- not for nofpu target */ |
373 | "", "", "", "", "", "", "", "", | |
374 | /* vectors (pseudo) 67 - 70 -- not for nofpu target */ | |
375 | "", "", "", "", | |
376 | }; | |
377 | if (reg_nr < 0) | |
378 | return NULL; | |
379 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
380 | return NULL; | |
381 | return register_names[reg_nr]; | |
382 | } | |
383 | ||
384 | static const char * | |
d93859e2 | 385 | sh_sh4al_dsp_register_name (struct gdbarch *gdbarch, int reg_nr) |
474e5826 CV |
386 | { |
387 | static char *register_names[] = { | |
388 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
389 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
390 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
391 | "", "dsr", | |
392 | "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1", | |
393 | "y0", "y1", "", "", "", "", "", "mod", | |
394 | "ssr", "spc", | |
395 | "rs", "re", "", "", "", "", "", "", | |
026a72f8 CV |
396 | "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b", |
397 | "", "", "", "", "", "", "", "", | |
da962468 | 398 | "", "", "", "", "", "", "", "", |
474e5826 CV |
399 | }; |
400 | if (reg_nr < 0) | |
401 | return NULL; | |
402 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
403 | return NULL; | |
404 | return register_names[reg_nr]; | |
405 | } | |
406 | ||
3117ed25 | 407 | static const unsigned char * |
67d57894 | 408 | sh_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr) |
cc17453a | 409 | { |
c378eb4e | 410 | /* 0xc3c3 is trapa #c3, and it works in big and little endian modes. */ |
617daa0e CV |
411 | static unsigned char breakpoint[] = { 0xc3, 0xc3 }; |
412 | ||
bac718a6 UW |
413 | /* For remote stub targets, trapa #20 is used. */ |
414 | if (strcmp (target_shortname, "remote") == 0) | |
415 | { | |
416 | static unsigned char big_remote_breakpoint[] = { 0xc3, 0x20 }; | |
417 | static unsigned char little_remote_breakpoint[] = { 0x20, 0xc3 }; | |
418 | ||
67d57894 | 419 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
bac718a6 UW |
420 | { |
421 | *lenptr = sizeof (big_remote_breakpoint); | |
422 | return big_remote_breakpoint; | |
423 | } | |
424 | else | |
425 | { | |
426 | *lenptr = sizeof (little_remote_breakpoint); | |
427 | return little_remote_breakpoint; | |
428 | } | |
429 | } | |
430 | ||
cc17453a EZ |
431 | *lenptr = sizeof (breakpoint); |
432 | return breakpoint; | |
433 | } | |
c906108c SS |
434 | |
435 | /* Prologue looks like | |
1c0159e0 CV |
436 | mov.l r14,@-r15 |
437 | sts.l pr,@-r15 | |
438 | mov.l <regs>,@-r15 | |
439 | sub <room_for_loca_vars>,r15 | |
440 | mov r15,r14 | |
8db62801 | 441 | |
c378eb4e | 442 | Actually it can be more complicated than this but that's it, basically. */ |
c906108c | 443 | |
1c0159e0 CV |
444 | #define GET_SOURCE_REG(x) (((x) >> 4) & 0xf) |
445 | #define GET_TARGET_REG(x) (((x) >> 8) & 0xf) | |
446 | ||
5f883edd FF |
447 | /* JSR @Rm 0100mmmm00001011 */ |
448 | #define IS_JSR(x) (((x) & 0xf0ff) == 0x400b) | |
449 | ||
8db62801 EZ |
450 | /* STS.L PR,@-r15 0100111100100010 |
451 | r15-4-->r15, PR-->(r15) */ | |
c906108c | 452 | #define IS_STS(x) ((x) == 0x4f22) |
8db62801 | 453 | |
03131d99 CV |
454 | /* STS.L MACL,@-r15 0100111100010010 |
455 | r15-4-->r15, MACL-->(r15) */ | |
456 | #define IS_MACL_STS(x) ((x) == 0x4f12) | |
457 | ||
8db62801 EZ |
458 | /* MOV.L Rm,@-r15 00101111mmmm0110 |
459 | r15-4-->r15, Rm-->(R15) */ | |
c906108c | 460 | #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06) |
8db62801 | 461 | |
8db62801 EZ |
462 | /* MOV r15,r14 0110111011110011 |
463 | r15-->r14 */ | |
c906108c | 464 | #define IS_MOV_SP_FP(x) ((x) == 0x6ef3) |
8db62801 EZ |
465 | |
466 | /* ADD #imm,r15 01111111iiiiiiii | |
467 | r15+imm-->r15 */ | |
1c0159e0 | 468 | #define IS_ADD_IMM_SP(x) (((x) & 0xff00) == 0x7f00) |
8db62801 | 469 | |
c906108c SS |
470 | #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00) |
471 | #define IS_SHLL_R3(x) ((x) == 0x4300) | |
8db62801 EZ |
472 | |
473 | /* ADD r3,r15 0011111100111100 | |
474 | r15+r3-->r15 */ | |
c906108c | 475 | #define IS_ADD_R3SP(x) ((x) == 0x3f3c) |
8db62801 EZ |
476 | |
477 | /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011 | |
8db62801 | 478 | FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011 |
8db62801 | 479 | FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */ |
f2ea0907 | 480 | /* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to |
c378eb4e | 481 | make this entirely clear. */ |
1c0159e0 CV |
482 | /* #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) */ |
483 | #define IS_FPUSH(x) (((x) & 0xff0f) == 0xff0b) | |
484 | ||
485 | /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 4 <= m <= 7 */ | |
486 | #define IS_MOV_ARG_TO_REG(x) \ | |
487 | (((x) & 0xf00f) == 0x6003 && \ | |
488 | ((x) & 0x00f0) >= 0x0040 && \ | |
489 | ((x) & 0x00f0) <= 0x0070) | |
490 | /* MOV.L Rm,@Rn 0010nnnnmmmm0010 n = 14, 4 <= m <= 7 */ | |
491 | #define IS_MOV_ARG_TO_IND_R14(x) \ | |
492 | (((x) & 0xff0f) == 0x2e02 && \ | |
493 | ((x) & 0x00f0) >= 0x0040 && \ | |
494 | ((x) & 0x00f0) <= 0x0070) | |
495 | /* MOV.L Rm,@(disp*4,Rn) 00011110mmmmdddd n = 14, 4 <= m <= 7 */ | |
496 | #define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \ | |
497 | (((x) & 0xff00) == 0x1e00 && \ | |
498 | ((x) & 0x00f0) >= 0x0040 && \ | |
499 | ((x) & 0x00f0) <= 0x0070) | |
500 | ||
501 | /* MOV.W @(disp*2,PC),Rn 1001nnnndddddddd */ | |
502 | #define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000) | |
503 | /* MOV.L @(disp*4,PC),Rn 1101nnnndddddddd */ | |
504 | #define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000) | |
03131d99 CV |
505 | /* MOVI20 #imm20,Rn 0000nnnniiii0000 */ |
506 | #define IS_MOVI20(x) (((x) & 0xf00f) == 0x0000) | |
1c0159e0 CV |
507 | /* SUB Rn,R15 00111111nnnn1000 */ |
508 | #define IS_SUB_REG_FROM_SP(x) (((x) & 0xff0f) == 0x3f08) | |
8db62801 | 509 | |
1c0159e0 | 510 | #define FPSCR_SZ (1 << 20) |
cc17453a | 511 | |
c378eb4e | 512 | /* The following instructions are used for epilogue testing. */ |
1c0159e0 CV |
513 | #define IS_RESTORE_FP(x) ((x) == 0x6ef6) |
514 | #define IS_RTS(x) ((x) == 0x000b) | |
515 | #define IS_LDS(x) ((x) == 0x4f26) | |
03131d99 | 516 | #define IS_MACL_LDS(x) ((x) == 0x4f16) |
1c0159e0 CV |
517 | #define IS_MOV_FP_SP(x) ((x) == 0x6fe3) |
518 | #define IS_ADD_REG_TO_FP(x) (((x) & 0xff0f) == 0x3e0c) | |
519 | #define IS_ADD_IMM_FP(x) (((x) & 0xff00) == 0x7e00) | |
cc17453a | 520 | |
cc17453a | 521 | static CORE_ADDR |
e17a4113 UW |
522 | sh_analyze_prologue (struct gdbarch *gdbarch, |
523 | CORE_ADDR pc, CORE_ADDR current_pc, | |
d2ca4222 | 524 | struct sh_frame_cache *cache, ULONGEST fpscr) |
617daa0e | 525 | { |
e17a4113 | 526 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1c0159e0 CV |
527 | ULONGEST inst; |
528 | CORE_ADDR opc; | |
529 | int offset; | |
530 | int sav_offset = 0; | |
c906108c | 531 | int r3_val = 0; |
1c0159e0 | 532 | int reg, sav_reg = -1; |
cc17453a | 533 | |
1c0159e0 CV |
534 | if (pc >= current_pc) |
535 | return current_pc; | |
cc17453a | 536 | |
1c0159e0 | 537 | cache->uses_fp = 0; |
cc17453a EZ |
538 | for (opc = pc + (2 * 28); pc < opc; pc += 2) |
539 | { | |
e17a4113 | 540 | inst = read_memory_unsigned_integer (pc, 2, byte_order); |
c378eb4e | 541 | /* See where the registers will be saved to. */ |
f2ea0907 | 542 | if (IS_PUSH (inst)) |
cc17453a | 543 | { |
1c0159e0 CV |
544 | cache->saved_regs[GET_SOURCE_REG (inst)] = cache->sp_offset; |
545 | cache->sp_offset += 4; | |
cc17453a | 546 | } |
f2ea0907 | 547 | else if (IS_STS (inst)) |
cc17453a | 548 | { |
1c0159e0 CV |
549 | cache->saved_regs[PR_REGNUM] = cache->sp_offset; |
550 | cache->sp_offset += 4; | |
cc17453a | 551 | } |
03131d99 CV |
552 | else if (IS_MACL_STS (inst)) |
553 | { | |
554 | cache->saved_regs[MACL_REGNUM] = cache->sp_offset; | |
555 | cache->sp_offset += 4; | |
556 | } | |
f2ea0907 | 557 | else if (IS_MOV_R3 (inst)) |
cc17453a | 558 | { |
f2ea0907 | 559 | r3_val = ((inst & 0xff) ^ 0x80) - 0x80; |
cc17453a | 560 | } |
f2ea0907 | 561 | else if (IS_SHLL_R3 (inst)) |
cc17453a EZ |
562 | { |
563 | r3_val <<= 1; | |
564 | } | |
f2ea0907 | 565 | else if (IS_ADD_R3SP (inst)) |
cc17453a | 566 | { |
1c0159e0 | 567 | cache->sp_offset += -r3_val; |
cc17453a | 568 | } |
f2ea0907 | 569 | else if (IS_ADD_IMM_SP (inst)) |
cc17453a | 570 | { |
1c0159e0 CV |
571 | offset = ((inst & 0xff) ^ 0x80) - 0x80; |
572 | cache->sp_offset -= offset; | |
c906108c | 573 | } |
1c0159e0 | 574 | else if (IS_MOVW_PCREL_TO_REG (inst)) |
617daa0e | 575 | { |
1c0159e0 CV |
576 | if (sav_reg < 0) |
577 | { | |
578 | reg = GET_TARGET_REG (inst); | |
579 | if (reg < 14) | |
580 | { | |
581 | sav_reg = reg; | |
a2b4a96c | 582 | offset = (inst & 0xff) << 1; |
1c0159e0 | 583 | sav_offset = |
e17a4113 | 584 | read_memory_integer ((pc + 4) + offset, 2, byte_order); |
1c0159e0 CV |
585 | } |
586 | } | |
c906108c | 587 | } |
1c0159e0 | 588 | else if (IS_MOVL_PCREL_TO_REG (inst)) |
617daa0e | 589 | { |
1c0159e0 CV |
590 | if (sav_reg < 0) |
591 | { | |
a2b4a96c | 592 | reg = GET_TARGET_REG (inst); |
1c0159e0 CV |
593 | if (reg < 14) |
594 | { | |
595 | sav_reg = reg; | |
a2b4a96c | 596 | offset = (inst & 0xff) << 2; |
1c0159e0 | 597 | sav_offset = |
e17a4113 UW |
598 | read_memory_integer (((pc & 0xfffffffc) + 4) + offset, |
599 | 4, byte_order); | |
1c0159e0 CV |
600 | } |
601 | } | |
c906108c | 602 | } |
03131d99 CV |
603 | else if (IS_MOVI20 (inst)) |
604 | { | |
605 | if (sav_reg < 0) | |
606 | { | |
607 | reg = GET_TARGET_REG (inst); | |
608 | if (reg < 14) | |
609 | { | |
610 | sav_reg = reg; | |
611 | sav_offset = GET_SOURCE_REG (inst) << 16; | |
c378eb4e | 612 | /* MOVI20 is a 32 bit instruction! */ |
03131d99 | 613 | pc += 2; |
e17a4113 UW |
614 | sav_offset |
615 | |= read_memory_unsigned_integer (pc, 2, byte_order); | |
03131d99 CV |
616 | /* Now sav_offset contains an unsigned 20 bit value. |
617 | It must still get sign extended. */ | |
618 | if (sav_offset & 0x00080000) | |
619 | sav_offset |= 0xfff00000; | |
620 | } | |
621 | } | |
622 | } | |
1c0159e0 | 623 | else if (IS_SUB_REG_FROM_SP (inst)) |
617daa0e | 624 | { |
1c0159e0 CV |
625 | reg = GET_SOURCE_REG (inst); |
626 | if (sav_reg > 0 && reg == sav_reg) | |
627 | { | |
628 | sav_reg = -1; | |
629 | } | |
630 | cache->sp_offset += sav_offset; | |
c906108c | 631 | } |
f2ea0907 | 632 | else if (IS_FPUSH (inst)) |
c906108c | 633 | { |
d2ca4222 | 634 | if (fpscr & FPSCR_SZ) |
c906108c | 635 | { |
1c0159e0 | 636 | cache->sp_offset += 8; |
c906108c SS |
637 | } |
638 | else | |
639 | { | |
1c0159e0 | 640 | cache->sp_offset += 4; |
c906108c SS |
641 | } |
642 | } | |
f2ea0907 | 643 | else if (IS_MOV_SP_FP (inst)) |
617daa0e | 644 | { |
960ccd7d | 645 | cache->uses_fp = 1; |
1c0159e0 CV |
646 | /* At this point, only allow argument register moves to other |
647 | registers or argument register moves to @(X,fp) which are | |
648 | moving the register arguments onto the stack area allocated | |
649 | by a former add somenumber to SP call. Don't allow moving | |
c378eb4e | 650 | to an fp indirect address above fp + cache->sp_offset. */ |
1c0159e0 CV |
651 | pc += 2; |
652 | for (opc = pc + 12; pc < opc; pc += 2) | |
653 | { | |
e17a4113 | 654 | inst = read_memory_integer (pc, 2, byte_order); |
1c0159e0 | 655 | if (IS_MOV_ARG_TO_IND_R14 (inst)) |
617daa0e | 656 | { |
1c0159e0 CV |
657 | reg = GET_SOURCE_REG (inst); |
658 | if (cache->sp_offset > 0) | |
617daa0e | 659 | cache->saved_regs[reg] = cache->sp_offset; |
1c0159e0 CV |
660 | } |
661 | else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst)) | |
617daa0e | 662 | { |
1c0159e0 CV |
663 | reg = GET_SOURCE_REG (inst); |
664 | offset = (inst & 0xf) * 4; | |
665 | if (cache->sp_offset > offset) | |
666 | cache->saved_regs[reg] = cache->sp_offset - offset; | |
667 | } | |
668 | else if (IS_MOV_ARG_TO_REG (inst)) | |
617daa0e | 669 | continue; |
1c0159e0 CV |
670 | else |
671 | break; | |
672 | } | |
673 | break; | |
674 | } | |
5f883edd FF |
675 | else if (IS_JSR (inst)) |
676 | { | |
677 | /* We have found a jsr that has been scheduled into the prologue. | |
678 | If we continue the scan and return a pc someplace after this, | |
679 | then setting a breakpoint on this function will cause it to | |
680 | appear to be called after the function it is calling via the | |
681 | jsr, which will be very confusing. Most likely the next | |
682 | instruction is going to be IS_MOV_SP_FP in the delay slot. If | |
c378eb4e | 683 | so, note that before returning the current pc. */ |
e17a4113 | 684 | inst = read_memory_integer (pc + 2, 2, byte_order); |
5f883edd FF |
685 | if (IS_MOV_SP_FP (inst)) |
686 | cache->uses_fp = 1; | |
687 | break; | |
688 | } | |
c378eb4e MS |
689 | #if 0 /* This used to just stop when it found an instruction |
690 | that was not considered part of the prologue. Now, | |
691 | we just keep going looking for likely | |
692 | instructions. */ | |
c906108c SS |
693 | else |
694 | break; | |
2bfa91ee | 695 | #endif |
c906108c SS |
696 | } |
697 | ||
1c0159e0 CV |
698 | return pc; |
699 | } | |
c906108c | 700 | |
c378eb4e | 701 | /* Skip any prologue before the guts of a function. */ |
c906108c | 702 | |
c378eb4e MS |
703 | /* Skip the prologue using the debug information. If this fails we'll |
704 | fall back on the 'guess' method below. */ | |
1c0159e0 CV |
705 | static CORE_ADDR |
706 | after_prologue (CORE_ADDR pc) | |
707 | { | |
708 | struct symtab_and_line sal; | |
709 | CORE_ADDR func_addr, func_end; | |
c906108c | 710 | |
1c0159e0 CV |
711 | /* If we can not find the symbol in the partial symbol table, then |
712 | there is no hope we can determine the function's start address | |
713 | with this code. */ | |
714 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
715 | return 0; | |
c906108c | 716 | |
1c0159e0 CV |
717 | /* Get the line associated with FUNC_ADDR. */ |
718 | sal = find_pc_line (func_addr, 0); | |
719 | ||
720 | /* There are only two cases to consider. First, the end of the source line | |
721 | is within the function bounds. In that case we return the end of the | |
722 | source line. Second is the end of the source line extends beyond the | |
723 | bounds of the current function. We need to use the slow code to | |
724 | examine instructions in that case. */ | |
725 | if (sal.end < func_end) | |
726 | return sal.end; | |
727 | else | |
728 | return 0; | |
c906108c SS |
729 | } |
730 | ||
1c0159e0 | 731 | static CORE_ADDR |
6093d2eb | 732 | sh_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
c906108c | 733 | { |
1c0159e0 CV |
734 | CORE_ADDR pc; |
735 | struct sh_frame_cache cache; | |
736 | ||
737 | /* See if we can determine the end of the prologue via the symbol table. | |
738 | If so, then return either PC, or the PC after the prologue, whichever | |
739 | is greater. */ | |
740 | pc = after_prologue (start_pc); | |
cc17453a | 741 | |
1c0159e0 | 742 | /* If after_prologue returned a useful address, then use it. Else |
c378eb4e | 743 | fall back on the instruction skipping code. */ |
1c0159e0 CV |
744 | if (pc) |
745 | return max (pc, start_pc); | |
c906108c | 746 | |
1c0159e0 | 747 | cache.sp_offset = -4; |
e17a4113 | 748 | pc = sh_analyze_prologue (gdbarch, start_pc, (CORE_ADDR) -1, &cache, 0); |
1c0159e0 CV |
749 | if (!cache.uses_fp) |
750 | return start_pc; | |
c906108c | 751 | |
1c0159e0 CV |
752 | return pc; |
753 | } | |
754 | ||
2e952408 | 755 | /* The ABI says: |
9a5cef92 EZ |
756 | |
757 | Aggregate types not bigger than 8 bytes that have the same size and | |
758 | alignment as one of the integer scalar types are returned in the | |
759 | same registers as the integer type they match. | |
760 | ||
761 | For example, a 2-byte aligned structure with size 2 bytes has the | |
762 | same size and alignment as a short int, and will be returned in R0. | |
763 | A 4-byte aligned structure with size 8 bytes has the same size and | |
764 | alignment as a long long int, and will be returned in R0 and R1. | |
765 | ||
766 | When an aggregate type is returned in R0 and R1, R0 contains the | |
767 | first four bytes of the aggregate, and R1 contains the | |
c378eb4e | 768 | remainder. If the size of the aggregate type is not a multiple of 4 |
9a5cef92 | 769 | bytes, the aggregate is tail-padded up to a multiple of 4 |
c378eb4e | 770 | bytes. The value of the padding is undefined. For little-endian |
9a5cef92 EZ |
771 | targets the padding will appear at the most significant end of the |
772 | last element, for big-endian targets the padding appears at the | |
773 | least significant end of the last element. | |
774 | ||
c378eb4e | 775 | All other aggregate types are returned by address. The caller |
9a5cef92 | 776 | function passes the address of an area large enough to hold the |
c378eb4e | 777 | aggregate value in R2. The called function stores the result in |
7fe958be | 778 | this location. |
9a5cef92 EZ |
779 | |
780 | To reiterate, structs smaller than 8 bytes could also be returned | |
781 | in memory, if they don't pass the "same size and alignment as an | |
782 | integer type" rule. | |
783 | ||
784 | For example, in | |
785 | ||
786 | struct s { char c[3]; } wibble; | |
787 | struct s foo(void) { return wibble; } | |
788 | ||
789 | the return value from foo() will be in memory, not | |
790 | in R0, because there is no 3-byte integer type. | |
791 | ||
7fe958be EZ |
792 | Similarly, in |
793 | ||
794 | struct s { char c[2]; } wibble; | |
795 | struct s foo(void) { return wibble; } | |
796 | ||
797 | because a struct containing two chars has alignment 1, that matches | |
798 | type char, but size 2, that matches type short. There's no integer | |
799 | type that has alignment 1 and size 2, so the struct is returned in | |
c378eb4e | 800 | memory. */ |
9a5cef92 | 801 | |
1c0159e0 | 802 | static int |
c055b101 | 803 | sh_use_struct_convention (int renesas_abi, struct type *type) |
1c0159e0 CV |
804 | { |
805 | int len = TYPE_LENGTH (type); | |
806 | int nelem = TYPE_NFIELDS (type); | |
3f997a97 | 807 | |
c055b101 CV |
808 | /* The Renesas ABI returns aggregate types always on stack. */ |
809 | if (renesas_abi && (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
810 | || TYPE_CODE (type) == TYPE_CODE_UNION)) | |
811 | return 1; | |
812 | ||
3f997a97 CV |
813 | /* Non-power of 2 length types and types bigger than 8 bytes (which don't |
814 | fit in two registers anyway) use struct convention. */ | |
815 | if (len != 1 && len != 2 && len != 4 && len != 8) | |
816 | return 1; | |
817 | ||
818 | /* Scalar types and aggregate types with exactly one field are aligned | |
819 | by definition. They are returned in registers. */ | |
820 | if (nelem <= 1) | |
821 | return 0; | |
822 | ||
823 | /* If the first field in the aggregate has the same length as the entire | |
824 | aggregate type, the type is returned in registers. */ | |
825 | if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == len) | |
826 | return 0; | |
827 | ||
828 | /* If the size of the aggregate is 8 bytes and the first field is | |
829 | of size 4 bytes its alignment is equal to long long's alignment, | |
830 | so it's returned in registers. */ | |
831 | if (len == 8 && TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == 4) | |
832 | return 0; | |
833 | ||
834 | /* Otherwise use struct convention. */ | |
835 | return 1; | |
283150cd EZ |
836 | } |
837 | ||
c055b101 CV |
838 | static int |
839 | sh_use_struct_convention_nofpu (int renesas_abi, struct type *type) | |
840 | { | |
841 | /* The Renesas ABI returns long longs/doubles etc. always on stack. */ | |
842 | if (renesas_abi && TYPE_NFIELDS (type) == 0 && TYPE_LENGTH (type) >= 8) | |
843 | return 1; | |
844 | return sh_use_struct_convention (renesas_abi, type); | |
845 | } | |
846 | ||
19f59343 MS |
847 | static CORE_ADDR |
848 | sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp) | |
849 | { | |
850 | return sp & ~3; | |
851 | } | |
852 | ||
55ff77ac | 853 | /* Function: push_dummy_call (formerly push_arguments) |
c906108c SS |
854 | Setup the function arguments for calling a function in the inferior. |
855 | ||
85a453d5 | 856 | On the Renesas SH architecture, there are four registers (R4 to R7) |
c906108c SS |
857 | which are dedicated for passing function arguments. Up to the first |
858 | four arguments (depending on size) may go into these registers. | |
859 | The rest go on the stack. | |
860 | ||
6df2bf50 MS |
861 | MVS: Except on SH variants that have floating point registers. |
862 | In that case, float and double arguments are passed in the same | |
863 | manner, but using FP registers instead of GP registers. | |
864 | ||
c906108c SS |
865 | Arguments that are smaller than 4 bytes will still take up a whole |
866 | register or a whole 32-bit word on the stack, and will be | |
867 | right-justified in the register or the stack word. This includes | |
868 | chars, shorts, and small aggregate types. | |
869 | ||
870 | Arguments that are larger than 4 bytes may be split between two or | |
871 | more registers. If there are not enough registers free, an argument | |
872 | may be passed partly in a register (or registers), and partly on the | |
c378eb4e | 873 | stack. This includes doubles, long longs, and larger aggregates. |
c906108c SS |
874 | As far as I know, there is no upper limit to the size of aggregates |
875 | that will be passed in this way; in other words, the convention of | |
876 | passing a pointer to a large aggregate instead of a copy is not used. | |
877 | ||
6df2bf50 | 878 | MVS: The above appears to be true for the SH variants that do not |
55ff77ac | 879 | have an FPU, however those that have an FPU appear to copy the |
6df2bf50 MS |
880 | aggregate argument onto the stack (and not place it in registers) |
881 | if it is larger than 16 bytes (four GP registers). | |
882 | ||
c906108c SS |
883 | An exceptional case exists for struct arguments (and possibly other |
884 | aggregates such as arrays) if the size is larger than 4 bytes but | |
885 | not a multiple of 4 bytes. In this case the argument is never split | |
886 | between the registers and the stack, but instead is copied in its | |
887 | entirety onto the stack, AND also copied into as many registers as | |
888 | there is room for. In other words, space in registers permitting, | |
889 | two copies of the same argument are passed in. As far as I can tell, | |
890 | only the one on the stack is used, although that may be a function | |
891 | of the level of compiler optimization. I suspect this is a compiler | |
892 | bug. Arguments of these odd sizes are left-justified within the | |
893 | word (as opposed to arguments smaller than 4 bytes, which are | |
894 | right-justified). | |
c5aa993b | 895 | |
c906108c SS |
896 | If the function is to return an aggregate type such as a struct, it |
897 | is either returned in the normal return value register R0 (if its | |
898 | size is no greater than one byte), or else the caller must allocate | |
899 | space into which the callee will copy the return value (if the size | |
900 | is greater than one byte). In this case, a pointer to the return | |
901 | value location is passed into the callee in register R2, which does | |
902 | not displace any of the other arguments passed in via registers R4 | |
c378eb4e | 903 | to R7. */ |
c906108c | 904 | |
c378eb4e | 905 | /* Helper function to justify value in register according to endianess. */ |
e5e33cd9 | 906 | static char * |
d93859e2 | 907 | sh_justify_value_in_reg (struct gdbarch *gdbarch, struct value *val, int len) |
e5e33cd9 CV |
908 | { |
909 | static char valbuf[4]; | |
910 | ||
617daa0e | 911 | memset (valbuf, 0, sizeof (valbuf)); |
e5e33cd9 CV |
912 | if (len < 4) |
913 | { | |
c378eb4e | 914 | /* value gets right-justified in the register or stack word. */ |
d93859e2 | 915 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
0fd88904 | 916 | memcpy (valbuf + (4 - len), (char *) value_contents (val), len); |
e5e33cd9 | 917 | else |
0fd88904 | 918 | memcpy (valbuf, (char *) value_contents (val), len); |
e5e33cd9 CV |
919 | return valbuf; |
920 | } | |
0fd88904 | 921 | return (char *) value_contents (val); |
617daa0e | 922 | } |
e5e33cd9 | 923 | |
c378eb4e | 924 | /* Helper function to eval number of bytes to allocate on stack. */ |
e5e33cd9 CV |
925 | static CORE_ADDR |
926 | sh_stack_allocsize (int nargs, struct value **args) | |
927 | { | |
928 | int stack_alloc = 0; | |
929 | while (nargs-- > 0) | |
4991999e | 930 | stack_alloc += ((TYPE_LENGTH (value_type (args[nargs])) + 3) & ~3); |
e5e33cd9 CV |
931 | return stack_alloc; |
932 | } | |
933 | ||
934 | /* Helper functions for getting the float arguments right. Registers usage | |
935 | depends on the ABI and the endianess. The comments should enlighten how | |
c378eb4e | 936 | it's intended to work. */ |
e5e33cd9 | 937 | |
c378eb4e | 938 | /* This array stores which of the float arg registers are already in use. */ |
e5e33cd9 CV |
939 | static int flt_argreg_array[FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM + 1]; |
940 | ||
c378eb4e | 941 | /* This function just resets the above array to "no reg used so far". */ |
e5e33cd9 CV |
942 | static void |
943 | sh_init_flt_argreg (void) | |
944 | { | |
945 | memset (flt_argreg_array, 0, sizeof flt_argreg_array); | |
946 | } | |
947 | ||
948 | /* This function returns the next register to use for float arg passing. | |
949 | It returns either a valid value between FLOAT_ARG0_REGNUM and | |
950 | FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns | |
951 | FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available. | |
952 | ||
953 | Note that register number 0 in flt_argreg_array corresponds with the | |
954 | real float register fr4. In contrast to FLOAT_ARG0_REGNUM (value is | |
955 | 29) the parity of the register number is preserved, which is important | |
c378eb4e | 956 | for the double register passing test (see the "argreg & 1" test below). */ |
e5e33cd9 | 957 | static int |
c055b101 | 958 | sh_next_flt_argreg (struct gdbarch *gdbarch, int len, struct type *func_type) |
e5e33cd9 CV |
959 | { |
960 | int argreg; | |
961 | ||
c378eb4e | 962 | /* First search for the next free register. */ |
617daa0e CV |
963 | for (argreg = 0; argreg <= FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM; |
964 | ++argreg) | |
e5e33cd9 CV |
965 | if (!flt_argreg_array[argreg]) |
966 | break; | |
967 | ||
c378eb4e | 968 | /* No register left? */ |
e5e33cd9 CV |
969 | if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM) |
970 | return FLOAT_ARGLAST_REGNUM + 1; | |
971 | ||
972 | if (len == 8) | |
973 | { | |
c378eb4e | 974 | /* Doubles are always starting in a even register number. */ |
e5e33cd9 | 975 | if (argreg & 1) |
617daa0e | 976 | { |
c055b101 CV |
977 | /* In gcc ABI, the skipped register is lost for further argument |
978 | passing now. Not so in Renesas ABI. */ | |
979 | if (!sh_is_renesas_calling_convention (func_type)) | |
980 | flt_argreg_array[argreg] = 1; | |
e5e33cd9 CV |
981 | |
982 | ++argreg; | |
983 | ||
c378eb4e | 984 | /* No register left? */ |
e5e33cd9 CV |
985 | if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM) |
986 | return FLOAT_ARGLAST_REGNUM + 1; | |
987 | } | |
c378eb4e | 988 | /* Also mark the next register as used. */ |
e5e33cd9 CV |
989 | flt_argreg_array[argreg + 1] = 1; |
990 | } | |
c055b101 CV |
991 | else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE |
992 | && !sh_is_renesas_calling_convention (func_type)) | |
e5e33cd9 | 993 | { |
c378eb4e | 994 | /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */ |
e5e33cd9 CV |
995 | if (!flt_argreg_array[argreg + 1]) |
996 | ++argreg; | |
997 | } | |
998 | flt_argreg_array[argreg] = 1; | |
999 | return FLOAT_ARG0_REGNUM + argreg; | |
1000 | } | |
1001 | ||
afce3d2a CV |
1002 | /* Helper function which figures out, if a type is treated like a float type. |
1003 | ||
2e952408 | 1004 | The FPU ABIs have a special way how to treat types as float types. |
afce3d2a CV |
1005 | Structures with exactly one member, which is of type float or double, are |
1006 | treated exactly as the base types float or double: | |
1007 | ||
1008 | struct sf { | |
1009 | float f; | |
1010 | }; | |
1011 | ||
1012 | struct sd { | |
1013 | double d; | |
1014 | }; | |
1015 | ||
1016 | are handled the same way as just | |
1017 | ||
1018 | float f; | |
1019 | ||
1020 | double d; | |
1021 | ||
1022 | As a result, arguments of these struct types are pushed into floating point | |
1023 | registers exactly as floats or doubles, using the same decision algorithm. | |
1024 | ||
1025 | The same is valid if these types are used as function return types. The | |
1026 | above structs are returned in fr0 resp. fr0,fr1 instead of in r0, r0,r1 | |
1027 | or even using struct convention as it is for other structs. */ | |
1028 | ||
1029 | static int | |
1030 | sh_treat_as_flt_p (struct type *type) | |
1031 | { | |
1032 | int len = TYPE_LENGTH (type); | |
1033 | ||
1034 | /* Ordinary float types are obviously treated as float. */ | |
1035 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
1036 | return 1; | |
1037 | /* Otherwise non-struct types are not treated as float. */ | |
1038 | if (TYPE_CODE (type) != TYPE_CODE_STRUCT) | |
1039 | return 0; | |
1040 | /* Otherwise structs with more than one memeber are not treated as float. */ | |
1041 | if (TYPE_NFIELDS (type) != 1) | |
1042 | return 0; | |
1043 | /* Otherwise if the type of that member is float, the whole type is | |
1044 | treated as float. */ | |
1045 | if (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) == TYPE_CODE_FLT) | |
1046 | return 1; | |
1047 | /* Otherwise it's not treated as float. */ | |
1048 | return 0; | |
1049 | } | |
1050 | ||
cc17453a | 1051 | static CORE_ADDR |
617daa0e | 1052 | sh_push_dummy_call_fpu (struct gdbarch *gdbarch, |
7d9b040b | 1053 | struct value *function, |
617daa0e | 1054 | struct regcache *regcache, |
6df2bf50 | 1055 | CORE_ADDR bp_addr, int nargs, |
617daa0e | 1056 | struct value **args, |
6df2bf50 MS |
1057 | CORE_ADDR sp, int struct_return, |
1058 | CORE_ADDR struct_addr) | |
1059 | { | |
e17a4113 | 1060 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
e5e33cd9 CV |
1061 | int stack_offset = 0; |
1062 | int argreg = ARG0_REGNUM; | |
8748518b | 1063 | int flt_argreg = 0; |
6df2bf50 | 1064 | int argnum; |
c055b101 | 1065 | struct type *func_type = value_type (function); |
6df2bf50 MS |
1066 | struct type *type; |
1067 | CORE_ADDR regval; | |
1068 | char *val; | |
8748518b | 1069 | int len, reg_size = 0; |
afce3d2a CV |
1070 | int pass_on_stack = 0; |
1071 | int treat_as_flt; | |
c055b101 CV |
1072 | int last_reg_arg = INT_MAX; |
1073 | ||
1074 | /* The Renesas ABI expects all varargs arguments, plus the last | |
1075 | non-vararg argument to be on the stack, no matter how many | |
1076 | registers have been used so far. */ | |
1077 | if (sh_is_renesas_calling_convention (func_type) | |
876cecd0 | 1078 | && TYPE_VARARGS (func_type)) |
c055b101 | 1079 | last_reg_arg = TYPE_NFIELDS (func_type) - 2; |
6df2bf50 | 1080 | |
c378eb4e | 1081 | /* First force sp to a 4-byte alignment. */ |
6df2bf50 MS |
1082 | sp = sh_frame_align (gdbarch, sp); |
1083 | ||
c378eb4e | 1084 | /* Make room on stack for args. */ |
e5e33cd9 CV |
1085 | sp -= sh_stack_allocsize (nargs, args); |
1086 | ||
c378eb4e | 1087 | /* Initialize float argument mechanism. */ |
e5e33cd9 | 1088 | sh_init_flt_argreg (); |
6df2bf50 MS |
1089 | |
1090 | /* Now load as many as possible of the first arguments into | |
1091 | registers, and push the rest onto the stack. There are 16 bytes | |
1092 | in four registers available. Loop thru args from first to last. */ | |
e5e33cd9 | 1093 | for (argnum = 0; argnum < nargs; argnum++) |
6df2bf50 | 1094 | { |
4991999e | 1095 | type = value_type (args[argnum]); |
6df2bf50 | 1096 | len = TYPE_LENGTH (type); |
d93859e2 | 1097 | val = sh_justify_value_in_reg (gdbarch, args[argnum], len); |
e5e33cd9 CV |
1098 | |
1099 | /* Some decisions have to be made how various types are handled. | |
c378eb4e | 1100 | This also differs in different ABIs. */ |
e5e33cd9 | 1101 | pass_on_stack = 0; |
e5e33cd9 | 1102 | |
c378eb4e | 1103 | /* Find out the next register to use for a floating point value. */ |
afce3d2a CV |
1104 | treat_as_flt = sh_treat_as_flt_p (type); |
1105 | if (treat_as_flt) | |
c055b101 CV |
1106 | flt_argreg = sh_next_flt_argreg (gdbarch, len, func_type); |
1107 | /* In Renesas ABI, long longs and aggregate types are always passed | |
1108 | on stack. */ | |
1109 | else if (sh_is_renesas_calling_convention (func_type) | |
1110 | && ((TYPE_CODE (type) == TYPE_CODE_INT && len == 8) | |
1111 | || TYPE_CODE (type) == TYPE_CODE_STRUCT | |
1112 | || TYPE_CODE (type) == TYPE_CODE_UNION)) | |
1113 | pass_on_stack = 1; | |
afce3d2a CV |
1114 | /* In contrast to non-FPU CPUs, arguments are never split between |
1115 | registers and stack. If an argument doesn't fit in the remaining | |
1116 | registers it's always pushed entirely on the stack. */ | |
1117 | else if (len > ((ARGLAST_REGNUM - argreg + 1) * 4)) | |
1118 | pass_on_stack = 1; | |
48db5a3c | 1119 | |
6df2bf50 MS |
1120 | while (len > 0) |
1121 | { | |
afce3d2a CV |
1122 | if ((treat_as_flt && flt_argreg > FLOAT_ARGLAST_REGNUM) |
1123 | || (!treat_as_flt && (argreg > ARGLAST_REGNUM | |
c055b101 CV |
1124 | || pass_on_stack)) |
1125 | || argnum > last_reg_arg) | |
617daa0e | 1126 | { |
c378eb4e | 1127 | /* The data goes entirely on the stack, 4-byte aligned. */ |
e5e33cd9 CV |
1128 | reg_size = (len + 3) & ~3; |
1129 | write_memory (sp + stack_offset, val, reg_size); | |
1130 | stack_offset += reg_size; | |
6df2bf50 | 1131 | } |
afce3d2a | 1132 | else if (treat_as_flt && flt_argreg <= FLOAT_ARGLAST_REGNUM) |
6df2bf50 | 1133 | { |
e5e33cd9 CV |
1134 | /* Argument goes in a float argument register. */ |
1135 | reg_size = register_size (gdbarch, flt_argreg); | |
e17a4113 | 1136 | regval = extract_unsigned_integer (val, reg_size, byte_order); |
2e952408 CV |
1137 | /* In little endian mode, float types taking two registers |
1138 | (doubles on sh4, long doubles on sh2e, sh3e and sh4) must | |
1139 | be stored swapped in the argument registers. The below | |
1140 | code first writes the first 32 bits in the next but one | |
1141 | register, increments the val and len values accordingly | |
1142 | and then proceeds as normal by writing the second 32 bits | |
c378eb4e | 1143 | into the next register. */ |
b47193f7 | 1144 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE |
2e952408 CV |
1145 | && TYPE_LENGTH (type) == 2 * reg_size) |
1146 | { | |
1147 | regcache_cooked_write_unsigned (regcache, flt_argreg + 1, | |
1148 | regval); | |
1149 | val += reg_size; | |
1150 | len -= reg_size; | |
c378eb4e MS |
1151 | regval = extract_unsigned_integer (val, reg_size, |
1152 | byte_order); | |
2e952408 | 1153 | } |
6df2bf50 MS |
1154 | regcache_cooked_write_unsigned (regcache, flt_argreg++, regval); |
1155 | } | |
afce3d2a | 1156 | else if (!treat_as_flt && argreg <= ARGLAST_REGNUM) |
e5e33cd9 | 1157 | { |
6df2bf50 | 1158 | /* there's room in a register */ |
e5e33cd9 | 1159 | reg_size = register_size (gdbarch, argreg); |
e17a4113 | 1160 | regval = extract_unsigned_integer (val, reg_size, byte_order); |
6df2bf50 MS |
1161 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
1162 | } | |
c378eb4e MS |
1163 | /* Store the value one register at a time or in one step on |
1164 | stack. */ | |
e5e33cd9 CV |
1165 | len -= reg_size; |
1166 | val += reg_size; | |
6df2bf50 MS |
1167 | } |
1168 | } | |
1169 | ||
c055b101 CV |
1170 | if (struct_return) |
1171 | { | |
1172 | if (sh_is_renesas_calling_convention (func_type)) | |
1173 | /* If the function uses the Renesas ABI, subtract another 4 bytes from | |
1174 | the stack and store the struct return address there. */ | |
e17a4113 | 1175 | write_memory_unsigned_integer (sp -= 4, 4, byte_order, struct_addr); |
c055b101 CV |
1176 | else |
1177 | /* Using the gcc ABI, the "struct return pointer" pseudo-argument has | |
1178 | its own dedicated register. */ | |
1179 | regcache_cooked_write_unsigned (regcache, | |
1180 | STRUCT_RETURN_REGNUM, struct_addr); | |
1181 | } | |
1182 | ||
c378eb4e | 1183 | /* Store return address. */ |
55ff77ac | 1184 | regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr); |
6df2bf50 MS |
1185 | |
1186 | /* Update stack pointer. */ | |
3e8c568d | 1187 | regcache_cooked_write_unsigned (regcache, |
b47193f7 | 1188 | gdbarch_sp_regnum (gdbarch), sp); |
6df2bf50 MS |
1189 | |
1190 | return sp; | |
1191 | } | |
1192 | ||
1193 | static CORE_ADDR | |
617daa0e | 1194 | sh_push_dummy_call_nofpu (struct gdbarch *gdbarch, |
7d9b040b | 1195 | struct value *function, |
617daa0e CV |
1196 | struct regcache *regcache, |
1197 | CORE_ADDR bp_addr, | |
1198 | int nargs, struct value **args, | |
1199 | CORE_ADDR sp, int struct_return, | |
6df2bf50 | 1200 | CORE_ADDR struct_addr) |
c906108c | 1201 | { |
e17a4113 | 1202 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
e5e33cd9 CV |
1203 | int stack_offset = 0; |
1204 | int argreg = ARG0_REGNUM; | |
c906108c | 1205 | int argnum; |
c055b101 | 1206 | struct type *func_type = value_type (function); |
c906108c SS |
1207 | struct type *type; |
1208 | CORE_ADDR regval; | |
1209 | char *val; | |
c055b101 CV |
1210 | int len, reg_size = 0; |
1211 | int pass_on_stack = 0; | |
1212 | int last_reg_arg = INT_MAX; | |
1213 | ||
1214 | /* The Renesas ABI expects all varargs arguments, plus the last | |
1215 | non-vararg argument to be on the stack, no matter how many | |
1216 | registers have been used so far. */ | |
1217 | if (sh_is_renesas_calling_convention (func_type) | |
876cecd0 | 1218 | && TYPE_VARARGS (func_type)) |
c055b101 | 1219 | last_reg_arg = TYPE_NFIELDS (func_type) - 2; |
c906108c | 1220 | |
c378eb4e | 1221 | /* First force sp to a 4-byte alignment. */ |
19f59343 | 1222 | sp = sh_frame_align (gdbarch, sp); |
c906108c | 1223 | |
c378eb4e | 1224 | /* Make room on stack for args. */ |
e5e33cd9 | 1225 | sp -= sh_stack_allocsize (nargs, args); |
c906108c | 1226 | |
c906108c SS |
1227 | /* Now load as many as possible of the first arguments into |
1228 | registers, and push the rest onto the stack. There are 16 bytes | |
1229 | in four registers available. Loop thru args from first to last. */ | |
e5e33cd9 | 1230 | for (argnum = 0; argnum < nargs; argnum++) |
617daa0e | 1231 | { |
4991999e | 1232 | type = value_type (args[argnum]); |
c5aa993b | 1233 | len = TYPE_LENGTH (type); |
d93859e2 | 1234 | val = sh_justify_value_in_reg (gdbarch, args[argnum], len); |
c906108c | 1235 | |
c055b101 | 1236 | /* Some decisions have to be made how various types are handled. |
c378eb4e | 1237 | This also differs in different ABIs. */ |
c055b101 CV |
1238 | pass_on_stack = 0; |
1239 | /* Renesas ABI pushes doubles and long longs entirely on stack. | |
1240 | Same goes for aggregate types. */ | |
1241 | if (sh_is_renesas_calling_convention (func_type) | |
1242 | && ((TYPE_CODE (type) == TYPE_CODE_INT && len >= 8) | |
1243 | || (TYPE_CODE (type) == TYPE_CODE_FLT && len >= 8) | |
1244 | || TYPE_CODE (type) == TYPE_CODE_STRUCT | |
1245 | || TYPE_CODE (type) == TYPE_CODE_UNION)) | |
1246 | pass_on_stack = 1; | |
c906108c SS |
1247 | while (len > 0) |
1248 | { | |
c055b101 CV |
1249 | if (argreg > ARGLAST_REGNUM || pass_on_stack |
1250 | || argnum > last_reg_arg) | |
617daa0e | 1251 | { |
e5e33cd9 | 1252 | /* The remainder of the data goes entirely on the stack, |
c378eb4e | 1253 | 4-byte aligned. */ |
e5e33cd9 CV |
1254 | reg_size = (len + 3) & ~3; |
1255 | write_memory (sp + stack_offset, val, reg_size); | |
617daa0e | 1256 | stack_offset += reg_size; |
c906108c | 1257 | } |
e5e33cd9 | 1258 | else if (argreg <= ARGLAST_REGNUM) |
617daa0e | 1259 | { |
c378eb4e | 1260 | /* There's room in a register. */ |
e5e33cd9 | 1261 | reg_size = register_size (gdbarch, argreg); |
e17a4113 | 1262 | regval = extract_unsigned_integer (val, reg_size, byte_order); |
48db5a3c | 1263 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
c906108c | 1264 | } |
e5e33cd9 CV |
1265 | /* Store the value reg_size bytes at a time. This means that things |
1266 | larger than reg_size bytes may go partly in registers and partly | |
c906108c | 1267 | on the stack. */ |
e5e33cd9 CV |
1268 | len -= reg_size; |
1269 | val += reg_size; | |
c906108c SS |
1270 | } |
1271 | } | |
48db5a3c | 1272 | |
c055b101 CV |
1273 | if (struct_return) |
1274 | { | |
1275 | if (sh_is_renesas_calling_convention (func_type)) | |
1276 | /* If the function uses the Renesas ABI, subtract another 4 bytes from | |
1277 | the stack and store the struct return address there. */ | |
e17a4113 | 1278 | write_memory_unsigned_integer (sp -= 4, 4, byte_order, struct_addr); |
c055b101 CV |
1279 | else |
1280 | /* Using the gcc ABI, the "struct return pointer" pseudo-argument has | |
1281 | its own dedicated register. */ | |
1282 | regcache_cooked_write_unsigned (regcache, | |
1283 | STRUCT_RETURN_REGNUM, struct_addr); | |
1284 | } | |
1285 | ||
c378eb4e | 1286 | /* Store return address. */ |
55ff77ac | 1287 | regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr); |
48db5a3c CV |
1288 | |
1289 | /* Update stack pointer. */ | |
3e8c568d | 1290 | regcache_cooked_write_unsigned (regcache, |
b47193f7 | 1291 | gdbarch_sp_regnum (gdbarch), sp); |
48db5a3c | 1292 | |
c906108c SS |
1293 | return sp; |
1294 | } | |
1295 | ||
cc17453a EZ |
1296 | /* Find a function's return value in the appropriate registers (in |
1297 | regbuf), and copy it into valbuf. Extract from an array REGBUF | |
1298 | containing the (raw) register state a function return value of type | |
1299 | TYPE, and copy that, in virtual format, into VALBUF. */ | |
1300 | static void | |
3ffc5b9b CV |
1301 | sh_extract_return_value_nofpu (struct type *type, struct regcache *regcache, |
1302 | void *valbuf) | |
c906108c | 1303 | { |
e17a4113 UW |
1304 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
1305 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
cc17453a | 1306 | int len = TYPE_LENGTH (type); |
3116c80a EZ |
1307 | int return_register = R0_REGNUM; |
1308 | int offset; | |
617daa0e | 1309 | |
cc17453a | 1310 | if (len <= 4) |
3116c80a | 1311 | { |
48db5a3c CV |
1312 | ULONGEST c; |
1313 | ||
1314 | regcache_cooked_read_unsigned (regcache, R0_REGNUM, &c); | |
e17a4113 | 1315 | store_unsigned_integer (valbuf, len, byte_order, c); |
3116c80a | 1316 | } |
48db5a3c | 1317 | else if (len == 8) |
3116c80a | 1318 | { |
48db5a3c CV |
1319 | int i, regnum = R0_REGNUM; |
1320 | for (i = 0; i < len; i += 4) | |
617daa0e | 1321 | regcache_raw_read (regcache, regnum++, (char *) valbuf + i); |
3116c80a EZ |
1322 | } |
1323 | else | |
8a3fe4f8 | 1324 | error (_("bad size for return value")); |
3116c80a EZ |
1325 | } |
1326 | ||
1327 | static void | |
3ffc5b9b CV |
1328 | sh_extract_return_value_fpu (struct type *type, struct regcache *regcache, |
1329 | void *valbuf) | |
3116c80a | 1330 | { |
d93859e2 | 1331 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
afce3d2a | 1332 | if (sh_treat_as_flt_p (type)) |
3116c80a | 1333 | { |
48db5a3c | 1334 | int len = TYPE_LENGTH (type); |
d93859e2 | 1335 | int i, regnum = gdbarch_fp0_regnum (gdbarch); |
48db5a3c | 1336 | for (i = 0; i < len; i += 4) |
d93859e2 | 1337 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) |
c378eb4e MS |
1338 | regcache_raw_read (regcache, regnum++, |
1339 | (char *) valbuf + len - 4 - i); | |
2e952408 CV |
1340 | else |
1341 | regcache_raw_read (regcache, regnum++, (char *) valbuf + i); | |
3116c80a | 1342 | } |
cc17453a | 1343 | else |
3ffc5b9b | 1344 | sh_extract_return_value_nofpu (type, regcache, valbuf); |
cc17453a | 1345 | } |
c906108c | 1346 | |
cc17453a EZ |
1347 | /* Write into appropriate registers a function return value |
1348 | of type TYPE, given in virtual format. | |
1349 | If the architecture is sh4 or sh3e, store a function's return value | |
1350 | in the R0 general register or in the FP0 floating point register, | |
c378eb4e MS |
1351 | depending on the type of the return value. In all the other cases |
1352 | the result is stored in r0, left-justified. */ | |
cc17453a | 1353 | static void |
3ffc5b9b CV |
1354 | sh_store_return_value_nofpu (struct type *type, struct regcache *regcache, |
1355 | const void *valbuf) | |
cc17453a | 1356 | { |
e17a4113 UW |
1357 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
1358 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
48db5a3c CV |
1359 | ULONGEST val; |
1360 | int len = TYPE_LENGTH (type); | |
d19b71be | 1361 | |
48db5a3c | 1362 | if (len <= 4) |
d19b71be | 1363 | { |
e17a4113 | 1364 | val = extract_unsigned_integer (valbuf, len, byte_order); |
48db5a3c | 1365 | regcache_cooked_write_unsigned (regcache, R0_REGNUM, val); |
d19b71be MS |
1366 | } |
1367 | else | |
48db5a3c CV |
1368 | { |
1369 | int i, regnum = R0_REGNUM; | |
1370 | for (i = 0; i < len; i += 4) | |
617daa0e | 1371 | regcache_raw_write (regcache, regnum++, (char *) valbuf + i); |
48db5a3c | 1372 | } |
cc17453a | 1373 | } |
c906108c | 1374 | |
cc17453a | 1375 | static void |
3ffc5b9b CV |
1376 | sh_store_return_value_fpu (struct type *type, struct regcache *regcache, |
1377 | const void *valbuf) | |
cc17453a | 1378 | { |
d93859e2 | 1379 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
afce3d2a | 1380 | if (sh_treat_as_flt_p (type)) |
48db5a3c CV |
1381 | { |
1382 | int len = TYPE_LENGTH (type); | |
d93859e2 | 1383 | int i, regnum = gdbarch_fp0_regnum (gdbarch); |
48db5a3c | 1384 | for (i = 0; i < len; i += 4) |
d93859e2 | 1385 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) |
c8a3b559 CV |
1386 | regcache_raw_write (regcache, regnum++, |
1387 | (char *) valbuf + len - 4 - i); | |
1388 | else | |
1389 | regcache_raw_write (regcache, regnum++, (char *) valbuf + i); | |
48db5a3c | 1390 | } |
cc17453a | 1391 | else |
3ffc5b9b | 1392 | sh_store_return_value_nofpu (type, regcache, valbuf); |
c906108c SS |
1393 | } |
1394 | ||
c0409442 | 1395 | static enum return_value_convention |
c055b101 CV |
1396 | sh_return_value_nofpu (struct gdbarch *gdbarch, struct type *func_type, |
1397 | struct type *type, struct regcache *regcache, | |
18cf8b5b | 1398 | gdb_byte *readbuf, const gdb_byte *writebuf) |
c0409442 | 1399 | { |
c055b101 CV |
1400 | if (sh_use_struct_convention_nofpu ( |
1401 | sh_is_renesas_calling_convention (func_type), type)) | |
c0409442 CV |
1402 | return RETURN_VALUE_STRUCT_CONVENTION; |
1403 | if (writebuf) | |
3ffc5b9b | 1404 | sh_store_return_value_nofpu (type, regcache, writebuf); |
c0409442 | 1405 | else if (readbuf) |
3ffc5b9b | 1406 | sh_extract_return_value_nofpu (type, regcache, readbuf); |
c0409442 CV |
1407 | return RETURN_VALUE_REGISTER_CONVENTION; |
1408 | } | |
1409 | ||
1410 | static enum return_value_convention | |
c055b101 CV |
1411 | sh_return_value_fpu (struct gdbarch *gdbarch, struct type *func_type, |
1412 | struct type *type, struct regcache *regcache, | |
18cf8b5b | 1413 | gdb_byte *readbuf, const gdb_byte *writebuf) |
c0409442 | 1414 | { |
c055b101 CV |
1415 | if (sh_use_struct_convention ( |
1416 | sh_is_renesas_calling_convention (func_type), type)) | |
c0409442 CV |
1417 | return RETURN_VALUE_STRUCT_CONVENTION; |
1418 | if (writebuf) | |
3ffc5b9b | 1419 | sh_store_return_value_fpu (type, regcache, writebuf); |
c0409442 | 1420 | else if (readbuf) |
3ffc5b9b | 1421 | sh_extract_return_value_fpu (type, regcache, readbuf); |
c0409442 CV |
1422 | return RETURN_VALUE_REGISTER_CONVENTION; |
1423 | } | |
1424 | ||
c378eb4e | 1425 | /* Print the registers in a form similar to the E7000. */ |
c906108c SS |
1426 | |
1427 | static void | |
c458d6db | 1428 | sh_generic_show_regs (struct frame_info *frame) |
c906108c | 1429 | { |
c458d6db UW |
1430 | printf_filtered |
1431 | (" PC %s SR %08lx PR %08lx MACH %08lx\n", | |
5af949e3 UW |
1432 | phex (get_frame_register_unsigned (frame, |
1433 | gdbarch_pc_regnum | |
1434 | (get_frame_arch (frame))), 4), | |
c458d6db UW |
1435 | (long) get_frame_register_unsigned (frame, SR_REGNUM), |
1436 | (long) get_frame_register_unsigned (frame, PR_REGNUM), | |
1437 | (long) get_frame_register_unsigned (frame, MACH_REGNUM)); | |
cc17453a | 1438 | |
c458d6db UW |
1439 | printf_filtered |
1440 | (" GBR %08lx VBR %08lx MACL %08lx\n", | |
1441 | (long) get_frame_register_unsigned (frame, GBR_REGNUM), | |
1442 | (long) get_frame_register_unsigned (frame, VBR_REGNUM), | |
1443 | (long) get_frame_register_unsigned (frame, MACL_REGNUM)); | |
cc17453a | 1444 | |
617daa0e | 1445 | printf_filtered |
a6b0a3f3 | 1446 | ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
c458d6db UW |
1447 | (long) get_frame_register_unsigned (frame, 0), |
1448 | (long) get_frame_register_unsigned (frame, 1), | |
1449 | (long) get_frame_register_unsigned (frame, 2), | |
1450 | (long) get_frame_register_unsigned (frame, 3), | |
1451 | (long) get_frame_register_unsigned (frame, 4), | |
1452 | (long) get_frame_register_unsigned (frame, 5), | |
1453 | (long) get_frame_register_unsigned (frame, 6), | |
1454 | (long) get_frame_register_unsigned (frame, 7)); | |
1455 | printf_filtered | |
1456 | ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1457 | (long) get_frame_register_unsigned (frame, 8), | |
1458 | (long) get_frame_register_unsigned (frame, 9), | |
1459 | (long) get_frame_register_unsigned (frame, 10), | |
1460 | (long) get_frame_register_unsigned (frame, 11), | |
1461 | (long) get_frame_register_unsigned (frame, 12), | |
1462 | (long) get_frame_register_unsigned (frame, 13), | |
1463 | (long) get_frame_register_unsigned (frame, 14), | |
1464 | (long) get_frame_register_unsigned (frame, 15)); | |
cc17453a | 1465 | } |
c906108c | 1466 | |
cc17453a | 1467 | static void |
c458d6db | 1468 | sh3_show_regs (struct frame_info *frame) |
cc17453a | 1469 | { |
c458d6db UW |
1470 | printf_filtered |
1471 | (" PC %s SR %08lx PR %08lx MACH %08lx\n", | |
5af949e3 UW |
1472 | phex (get_frame_register_unsigned (frame, |
1473 | gdbarch_pc_regnum | |
1474 | (get_frame_arch (frame))), 4), | |
c458d6db UW |
1475 | (long) get_frame_register_unsigned (frame, SR_REGNUM), |
1476 | (long) get_frame_register_unsigned (frame, PR_REGNUM), | |
1477 | (long) get_frame_register_unsigned (frame, MACH_REGNUM)); | |
1478 | ||
1479 | printf_filtered | |
1480 | (" GBR %08lx VBR %08lx MACL %08lx\n", | |
1481 | (long) get_frame_register_unsigned (frame, GBR_REGNUM), | |
1482 | (long) get_frame_register_unsigned (frame, VBR_REGNUM), | |
1483 | (long) get_frame_register_unsigned (frame, MACL_REGNUM)); | |
1484 | printf_filtered | |
1485 | (" SSR %08lx SPC %08lx\n", | |
1486 | (long) get_frame_register_unsigned (frame, SSR_REGNUM), | |
1487 | (long) get_frame_register_unsigned (frame, SPC_REGNUM)); | |
c906108c | 1488 | |
617daa0e | 1489 | printf_filtered |
a6b0a3f3 | 1490 | ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
c458d6db UW |
1491 | (long) get_frame_register_unsigned (frame, 0), |
1492 | (long) get_frame_register_unsigned (frame, 1), | |
1493 | (long) get_frame_register_unsigned (frame, 2), | |
1494 | (long) get_frame_register_unsigned (frame, 3), | |
1495 | (long) get_frame_register_unsigned (frame, 4), | |
1496 | (long) get_frame_register_unsigned (frame, 5), | |
1497 | (long) get_frame_register_unsigned (frame, 6), | |
1498 | (long) get_frame_register_unsigned (frame, 7)); | |
1499 | printf_filtered | |
1500 | ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1501 | (long) get_frame_register_unsigned (frame, 8), | |
1502 | (long) get_frame_register_unsigned (frame, 9), | |
1503 | (long) get_frame_register_unsigned (frame, 10), | |
1504 | (long) get_frame_register_unsigned (frame, 11), | |
1505 | (long) get_frame_register_unsigned (frame, 12), | |
1506 | (long) get_frame_register_unsigned (frame, 13), | |
1507 | (long) get_frame_register_unsigned (frame, 14), | |
1508 | (long) get_frame_register_unsigned (frame, 15)); | |
c906108c SS |
1509 | } |
1510 | ||
2d188dd3 | 1511 | static void |
c458d6db | 1512 | sh2e_show_regs (struct frame_info *frame) |
2d188dd3 | 1513 | { |
b47193f7 | 1514 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c458d6db UW |
1515 | printf_filtered |
1516 | (" PC %s SR %08lx PR %08lx MACH %08lx\n", | |
5af949e3 UW |
1517 | phex (get_frame_register_unsigned (frame, |
1518 | gdbarch_pc_regnum (gdbarch)), 4), | |
c458d6db UW |
1519 | (long) get_frame_register_unsigned (frame, SR_REGNUM), |
1520 | (long) get_frame_register_unsigned (frame, PR_REGNUM), | |
1521 | (long) get_frame_register_unsigned (frame, MACH_REGNUM)); | |
1522 | ||
1523 | printf_filtered | |
1524 | (" GBR %08lx VBR %08lx MACL %08lx\n", | |
1525 | (long) get_frame_register_unsigned (frame, GBR_REGNUM), | |
1526 | (long) get_frame_register_unsigned (frame, VBR_REGNUM), | |
1527 | (long) get_frame_register_unsigned (frame, MACL_REGNUM)); | |
1528 | printf_filtered | |
1529 | (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n", | |
1530 | (long) get_frame_register_unsigned (frame, SSR_REGNUM), | |
1531 | (long) get_frame_register_unsigned (frame, SPC_REGNUM), | |
1532 | (long) get_frame_register_unsigned (frame, FPUL_REGNUM), | |
1533 | (long) get_frame_register_unsigned (frame, FPSCR_REGNUM)); | |
617daa0e CV |
1534 | |
1535 | printf_filtered | |
a6b0a3f3 | 1536 | ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
c458d6db UW |
1537 | (long) get_frame_register_unsigned (frame, 0), |
1538 | (long) get_frame_register_unsigned (frame, 1), | |
1539 | (long) get_frame_register_unsigned (frame, 2), | |
1540 | (long) get_frame_register_unsigned (frame, 3), | |
1541 | (long) get_frame_register_unsigned (frame, 4), | |
1542 | (long) get_frame_register_unsigned (frame, 5), | |
1543 | (long) get_frame_register_unsigned (frame, 6), | |
1544 | (long) get_frame_register_unsigned (frame, 7)); | |
1545 | printf_filtered | |
1546 | ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1547 | (long) get_frame_register_unsigned (frame, 8), | |
1548 | (long) get_frame_register_unsigned (frame, 9), | |
1549 | (long) get_frame_register_unsigned (frame, 10), | |
1550 | (long) get_frame_register_unsigned (frame, 11), | |
1551 | (long) get_frame_register_unsigned (frame, 12), | |
1552 | (long) get_frame_register_unsigned (frame, 13), | |
1553 | (long) get_frame_register_unsigned (frame, 14), | |
1554 | (long) get_frame_register_unsigned (frame, 15)); | |
1555 | ||
1556 | printf_filtered | |
1557 | ("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
3e8c568d | 1558 | (long) get_frame_register_unsigned |
b47193f7 | 1559 | (frame, gdbarch_fp0_regnum (gdbarch) + 0), |
3e8c568d | 1560 | (long) get_frame_register_unsigned |
b47193f7 | 1561 | (frame, gdbarch_fp0_regnum (gdbarch) + 1), |
3e8c568d | 1562 | (long) get_frame_register_unsigned |
b47193f7 | 1563 | (frame, gdbarch_fp0_regnum (gdbarch) + 2), |
3e8c568d | 1564 | (long) get_frame_register_unsigned |
b47193f7 | 1565 | (frame, gdbarch_fp0_regnum (gdbarch) + 3), |
3e8c568d | 1566 | (long) get_frame_register_unsigned |
b47193f7 | 1567 | (frame, gdbarch_fp0_regnum (gdbarch) + 4), |
3e8c568d | 1568 | (long) get_frame_register_unsigned |
b47193f7 | 1569 | (frame, gdbarch_fp0_regnum (gdbarch) + 5), |
3e8c568d | 1570 | (long) get_frame_register_unsigned |
b47193f7 | 1571 | (frame, gdbarch_fp0_regnum (gdbarch) + 6), |
3e8c568d | 1572 | (long) get_frame_register_unsigned |
b47193f7 | 1573 | (frame, gdbarch_fp0_regnum (gdbarch) + 7)); |
c458d6db UW |
1574 | printf_filtered |
1575 | ("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
3e8c568d | 1576 | (long) get_frame_register_unsigned |
b47193f7 | 1577 | (frame, gdbarch_fp0_regnum (gdbarch) + 8), |
3e8c568d | 1578 | (long) get_frame_register_unsigned |
b47193f7 | 1579 | (frame, gdbarch_fp0_regnum (gdbarch) + 9), |
3e8c568d | 1580 | (long) get_frame_register_unsigned |
b47193f7 | 1581 | (frame, gdbarch_fp0_regnum (gdbarch) + 10), |
3e8c568d | 1582 | (long) get_frame_register_unsigned |
b47193f7 | 1583 | (frame, gdbarch_fp0_regnum (gdbarch) + 11), |
3e8c568d | 1584 | (long) get_frame_register_unsigned |
b47193f7 | 1585 | (frame, gdbarch_fp0_regnum (gdbarch) + 12), |
3e8c568d | 1586 | (long) get_frame_register_unsigned |
b47193f7 | 1587 | (frame, gdbarch_fp0_regnum (gdbarch) + 13), |
3e8c568d | 1588 | (long) get_frame_register_unsigned |
b47193f7 | 1589 | (frame, gdbarch_fp0_regnum (gdbarch) + 14), |
3e8c568d | 1590 | (long) get_frame_register_unsigned |
b47193f7 | 1591 | (frame, gdbarch_fp0_regnum (gdbarch) + 15)); |
2d188dd3 NC |
1592 | } |
1593 | ||
da962468 | 1594 | static void |
c458d6db | 1595 | sh2a_show_regs (struct frame_info *frame) |
da962468 | 1596 | { |
b47193f7 | 1597 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c458d6db UW |
1598 | int pr = get_frame_register_unsigned (frame, FPSCR_REGNUM) & 0x80000; |
1599 | ||
1600 | printf_filtered | |
1601 | (" PC %s SR %08lx PR %08lx MACH %08lx\n", | |
5af949e3 UW |
1602 | phex (get_frame_register_unsigned (frame, |
1603 | gdbarch_pc_regnum (gdbarch)), 4), | |
c458d6db UW |
1604 | (long) get_frame_register_unsigned (frame, SR_REGNUM), |
1605 | (long) get_frame_register_unsigned (frame, PR_REGNUM), | |
1606 | (long) get_frame_register_unsigned (frame, MACH_REGNUM)); | |
1607 | ||
1608 | printf_filtered | |
1609 | (" GBR %08lx VBR %08lx TBR %08lx MACL %08lx\n", | |
1610 | (long) get_frame_register_unsigned (frame, GBR_REGNUM), | |
1611 | (long) get_frame_register_unsigned (frame, VBR_REGNUM), | |
1612 | (long) get_frame_register_unsigned (frame, TBR_REGNUM), | |
1613 | (long) get_frame_register_unsigned (frame, MACL_REGNUM)); | |
1614 | printf_filtered | |
1615 | (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n", | |
1616 | (long) get_frame_register_unsigned (frame, SSR_REGNUM), | |
1617 | (long) get_frame_register_unsigned (frame, SPC_REGNUM), | |
1618 | (long) get_frame_register_unsigned (frame, FPUL_REGNUM), | |
1619 | (long) get_frame_register_unsigned (frame, FPSCR_REGNUM)); | |
1620 | ||
1621 | printf_filtered | |
1622 | ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1623 | (long) get_frame_register_unsigned (frame, 0), | |
1624 | (long) get_frame_register_unsigned (frame, 1), | |
1625 | (long) get_frame_register_unsigned (frame, 2), | |
1626 | (long) get_frame_register_unsigned (frame, 3), | |
1627 | (long) get_frame_register_unsigned (frame, 4), | |
1628 | (long) get_frame_register_unsigned (frame, 5), | |
1629 | (long) get_frame_register_unsigned (frame, 6), | |
1630 | (long) get_frame_register_unsigned (frame, 7)); | |
1631 | printf_filtered | |
1632 | ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1633 | (long) get_frame_register_unsigned (frame, 8), | |
1634 | (long) get_frame_register_unsigned (frame, 9), | |
1635 | (long) get_frame_register_unsigned (frame, 10), | |
1636 | (long) get_frame_register_unsigned (frame, 11), | |
1637 | (long) get_frame_register_unsigned (frame, 12), | |
1638 | (long) get_frame_register_unsigned (frame, 13), | |
1639 | (long) get_frame_register_unsigned (frame, 14), | |
1640 | (long) get_frame_register_unsigned (frame, 15)); | |
1641 | ||
1642 | printf_filtered | |
1643 | (pr ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n" | |
1644 | : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
3e8c568d | 1645 | (long) get_frame_register_unsigned |
b47193f7 | 1646 | (frame, gdbarch_fp0_regnum (gdbarch) + 0), |
3e8c568d | 1647 | (long) get_frame_register_unsigned |
b47193f7 | 1648 | (frame, gdbarch_fp0_regnum (gdbarch) + 1), |
3e8c568d | 1649 | (long) get_frame_register_unsigned |
b47193f7 | 1650 | (frame, gdbarch_fp0_regnum (gdbarch) + 2), |
3e8c568d | 1651 | (long) get_frame_register_unsigned |
b47193f7 | 1652 | (frame, gdbarch_fp0_regnum (gdbarch) + 3), |
3e8c568d | 1653 | (long) get_frame_register_unsigned |
b47193f7 | 1654 | (frame, gdbarch_fp0_regnum (gdbarch) + 4), |
3e8c568d | 1655 | (long) get_frame_register_unsigned |
b47193f7 | 1656 | (frame, gdbarch_fp0_regnum (gdbarch) + 5), |
3e8c568d | 1657 | (long) get_frame_register_unsigned |
b47193f7 | 1658 | (frame, gdbarch_fp0_regnum (gdbarch) + 6), |
3e8c568d | 1659 | (long) get_frame_register_unsigned |
b47193f7 | 1660 | (frame, gdbarch_fp0_regnum (gdbarch) + 7)); |
c458d6db UW |
1661 | printf_filtered |
1662 | (pr ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n" | |
1663 | : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
3e8c568d | 1664 | (long) get_frame_register_unsigned |
b47193f7 | 1665 | (frame, gdbarch_fp0_regnum (gdbarch) + 8), |
3e8c568d | 1666 | (long) get_frame_register_unsigned |
b47193f7 | 1667 | (frame, gdbarch_fp0_regnum (gdbarch) + 9), |
3e8c568d | 1668 | (long) get_frame_register_unsigned |
b47193f7 | 1669 | (frame, gdbarch_fp0_regnum (gdbarch) + 10), |
3e8c568d | 1670 | (long) get_frame_register_unsigned |
b47193f7 | 1671 | (frame, gdbarch_fp0_regnum (gdbarch) + 11), |
3e8c568d | 1672 | (long) get_frame_register_unsigned |
b47193f7 | 1673 | (frame, gdbarch_fp0_regnum (gdbarch) + 12), |
3e8c568d | 1674 | (long) get_frame_register_unsigned |
b47193f7 | 1675 | (frame, gdbarch_fp0_regnum (gdbarch) + 13), |
3e8c568d | 1676 | (long) get_frame_register_unsigned |
b47193f7 | 1677 | (frame, gdbarch_fp0_regnum (gdbarch) + 14), |
3e8c568d | 1678 | (long) get_frame_register_unsigned |
b47193f7 | 1679 | (frame, gdbarch_fp0_regnum (gdbarch) + 15)); |
c458d6db UW |
1680 | printf_filtered |
1681 | ("BANK=%-3d\n", (int) get_frame_register_unsigned (frame, BANK_REGNUM)); | |
1682 | printf_filtered | |
1683 | ("R0b-R7b %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1684 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 0), | |
1685 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 1), | |
1686 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 2), | |
1687 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 3), | |
1688 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 4), | |
1689 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 5), | |
1690 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 6), | |
1691 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 7)); | |
1692 | printf_filtered | |
1693 | ("R8b-R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1694 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 8), | |
1695 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 9), | |
1696 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 10), | |
1697 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 11), | |
1698 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 12), | |
1699 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 13), | |
1700 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 14)); | |
1701 | printf_filtered | |
1702 | ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n", | |
1703 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 15), | |
1704 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 16), | |
1705 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 17), | |
1706 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 18), | |
1707 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 19)); | |
da962468 CV |
1708 | } |
1709 | ||
1710 | static void | |
c458d6db | 1711 | sh2a_nofpu_show_regs (struct frame_info *frame) |
da962468 | 1712 | { |
c458d6db UW |
1713 | int pr = get_frame_register_unsigned (frame, FPSCR_REGNUM) & 0x80000; |
1714 | ||
1715 | printf_filtered | |
1716 | (" PC %s SR %08lx PR %08lx MACH %08lx\n", | |
5af949e3 UW |
1717 | phex (get_frame_register_unsigned (frame, |
1718 | gdbarch_pc_regnum | |
1719 | (get_frame_arch (frame))), 4), | |
c458d6db UW |
1720 | (long) get_frame_register_unsigned (frame, SR_REGNUM), |
1721 | (long) get_frame_register_unsigned (frame, PR_REGNUM), | |
1722 | (long) get_frame_register_unsigned (frame, MACH_REGNUM)); | |
1723 | ||
1724 | printf_filtered | |
1725 | (" GBR %08lx VBR %08lx TBR %08lx MACL %08lx\n", | |
1726 | (long) get_frame_register_unsigned (frame, GBR_REGNUM), | |
1727 | (long) get_frame_register_unsigned (frame, VBR_REGNUM), | |
1728 | (long) get_frame_register_unsigned (frame, TBR_REGNUM), | |
1729 | (long) get_frame_register_unsigned (frame, MACL_REGNUM)); | |
1730 | printf_filtered | |
1731 | (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n", | |
1732 | (long) get_frame_register_unsigned (frame, SSR_REGNUM), | |
1733 | (long) get_frame_register_unsigned (frame, SPC_REGNUM), | |
1734 | (long) get_frame_register_unsigned (frame, FPUL_REGNUM), | |
1735 | (long) get_frame_register_unsigned (frame, FPSCR_REGNUM)); | |
1736 | ||
1737 | printf_filtered | |
1738 | ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1739 | (long) get_frame_register_unsigned (frame, 0), | |
1740 | (long) get_frame_register_unsigned (frame, 1), | |
1741 | (long) get_frame_register_unsigned (frame, 2), | |
1742 | (long) get_frame_register_unsigned (frame, 3), | |
1743 | (long) get_frame_register_unsigned (frame, 4), | |
1744 | (long) get_frame_register_unsigned (frame, 5), | |
1745 | (long) get_frame_register_unsigned (frame, 6), | |
1746 | (long) get_frame_register_unsigned (frame, 7)); | |
1747 | printf_filtered | |
1748 | ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1749 | (long) get_frame_register_unsigned (frame, 8), | |
1750 | (long) get_frame_register_unsigned (frame, 9), | |
1751 | (long) get_frame_register_unsigned (frame, 10), | |
1752 | (long) get_frame_register_unsigned (frame, 11), | |
1753 | (long) get_frame_register_unsigned (frame, 12), | |
1754 | (long) get_frame_register_unsigned (frame, 13), | |
1755 | (long) get_frame_register_unsigned (frame, 14), | |
1756 | (long) get_frame_register_unsigned (frame, 15)); | |
1757 | ||
1758 | printf_filtered | |
1759 | ("BANK=%-3d\n", (int) get_frame_register_unsigned (frame, BANK_REGNUM)); | |
1760 | printf_filtered | |
1761 | ("R0b-R7b %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1762 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 0), | |
1763 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 1), | |
1764 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 2), | |
1765 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 3), | |
1766 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 4), | |
1767 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 5), | |
1768 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 6), | |
1769 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 7)); | |
1770 | printf_filtered | |
1771 | ("R8b-R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1772 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 8), | |
1773 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 9), | |
1774 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 10), | |
1775 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 11), | |
1776 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 12), | |
1777 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 13), | |
1778 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 14)); | |
1779 | printf_filtered | |
1780 | ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n", | |
1781 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 15), | |
1782 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 16), | |
1783 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 17), | |
1784 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 18), | |
1785 | (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 19)); | |
da962468 CV |
1786 | } |
1787 | ||
cc17453a | 1788 | static void |
c458d6db | 1789 | sh3e_show_regs (struct frame_info *frame) |
cc17453a | 1790 | { |
b47193f7 | 1791 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c458d6db UW |
1792 | printf_filtered |
1793 | (" PC %s SR %08lx PR %08lx MACH %08lx\n", | |
5af949e3 UW |
1794 | phex (get_frame_register_unsigned (frame, |
1795 | gdbarch_pc_regnum (gdbarch)), 4), | |
c458d6db UW |
1796 | (long) get_frame_register_unsigned (frame, SR_REGNUM), |
1797 | (long) get_frame_register_unsigned (frame, PR_REGNUM), | |
1798 | (long) get_frame_register_unsigned (frame, MACH_REGNUM)); | |
1799 | ||
1800 | printf_filtered | |
1801 | (" GBR %08lx VBR %08lx MACL %08lx\n", | |
1802 | (long) get_frame_register_unsigned (frame, GBR_REGNUM), | |
1803 | (long) get_frame_register_unsigned (frame, VBR_REGNUM), | |
1804 | (long) get_frame_register_unsigned (frame, MACL_REGNUM)); | |
1805 | printf_filtered | |
1806 | (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n", | |
1807 | (long) get_frame_register_unsigned (frame, SSR_REGNUM), | |
1808 | (long) get_frame_register_unsigned (frame, SPC_REGNUM), | |
1809 | (long) get_frame_register_unsigned (frame, FPUL_REGNUM), | |
1810 | (long) get_frame_register_unsigned (frame, FPSCR_REGNUM)); | |
c906108c | 1811 | |
617daa0e | 1812 | printf_filtered |
a6b0a3f3 | 1813 | ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
c458d6db UW |
1814 | (long) get_frame_register_unsigned (frame, 0), |
1815 | (long) get_frame_register_unsigned (frame, 1), | |
1816 | (long) get_frame_register_unsigned (frame, 2), | |
1817 | (long) get_frame_register_unsigned (frame, 3), | |
1818 | (long) get_frame_register_unsigned (frame, 4), | |
1819 | (long) get_frame_register_unsigned (frame, 5), | |
1820 | (long) get_frame_register_unsigned (frame, 6), | |
1821 | (long) get_frame_register_unsigned (frame, 7)); | |
1822 | printf_filtered | |
1823 | ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1824 | (long) get_frame_register_unsigned (frame, 8), | |
1825 | (long) get_frame_register_unsigned (frame, 9), | |
1826 | (long) get_frame_register_unsigned (frame, 10), | |
1827 | (long) get_frame_register_unsigned (frame, 11), | |
1828 | (long) get_frame_register_unsigned (frame, 12), | |
1829 | (long) get_frame_register_unsigned (frame, 13), | |
1830 | (long) get_frame_register_unsigned (frame, 14), | |
1831 | (long) get_frame_register_unsigned (frame, 15)); | |
1832 | ||
1833 | printf_filtered | |
1834 | ("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
3e8c568d | 1835 | (long) get_frame_register_unsigned |
b47193f7 | 1836 | (frame, gdbarch_fp0_regnum (gdbarch) + 0), |
3e8c568d | 1837 | (long) get_frame_register_unsigned |
b47193f7 | 1838 | (frame, gdbarch_fp0_regnum (gdbarch) + 1), |
3e8c568d | 1839 | (long) get_frame_register_unsigned |
b47193f7 | 1840 | (frame, gdbarch_fp0_regnum (gdbarch) + 2), |
3e8c568d | 1841 | (long) get_frame_register_unsigned |
b47193f7 | 1842 | (frame, gdbarch_fp0_regnum (gdbarch) + 3), |
3e8c568d | 1843 | (long) get_frame_register_unsigned |
b47193f7 | 1844 | (frame, gdbarch_fp0_regnum (gdbarch) + 4), |
3e8c568d | 1845 | (long) get_frame_register_unsigned |
b47193f7 | 1846 | (frame, gdbarch_fp0_regnum (gdbarch) + 5), |
3e8c568d | 1847 | (long) get_frame_register_unsigned |
b47193f7 | 1848 | (frame, gdbarch_fp0_regnum (gdbarch) + 6), |
3e8c568d | 1849 | (long) get_frame_register_unsigned |
b47193f7 | 1850 | (frame, gdbarch_fp0_regnum (gdbarch) + 7)); |
c458d6db UW |
1851 | printf_filtered |
1852 | ("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
3e8c568d | 1853 | (long) get_frame_register_unsigned |
b47193f7 | 1854 | (frame, gdbarch_fp0_regnum (gdbarch) + 8), |
3e8c568d | 1855 | (long) get_frame_register_unsigned |
b47193f7 | 1856 | (frame, gdbarch_fp0_regnum (gdbarch) + 9), |
3e8c568d | 1857 | (long) get_frame_register_unsigned |
b47193f7 | 1858 | (frame, gdbarch_fp0_regnum (gdbarch) + 10), |
3e8c568d | 1859 | (long) get_frame_register_unsigned |
b47193f7 | 1860 | (frame, gdbarch_fp0_regnum (gdbarch) + 11), |
3e8c568d | 1861 | (long) get_frame_register_unsigned |
b47193f7 | 1862 | (frame, gdbarch_fp0_regnum (gdbarch) + 12), |
3e8c568d | 1863 | (long) get_frame_register_unsigned |
b47193f7 | 1864 | (frame, gdbarch_fp0_regnum (gdbarch) + 13), |
3e8c568d | 1865 | (long) get_frame_register_unsigned |
b47193f7 | 1866 | (frame, gdbarch_fp0_regnum (gdbarch) + 14), |
3e8c568d | 1867 | (long) get_frame_register_unsigned |
b47193f7 | 1868 | (frame, gdbarch_fp0_regnum (gdbarch) + 15)); |
cc17453a EZ |
1869 | } |
1870 | ||
1871 | static void | |
c458d6db | 1872 | sh3_dsp_show_regs (struct frame_info *frame) |
c906108c | 1873 | { |
c458d6db UW |
1874 | printf_filtered |
1875 | (" PC %s SR %08lx PR %08lx MACH %08lx\n", | |
5af949e3 UW |
1876 | phex (get_frame_register_unsigned (frame, |
1877 | gdbarch_pc_regnum | |
1878 | (get_frame_arch (frame))), 4), | |
c458d6db UW |
1879 | (long) get_frame_register_unsigned (frame, SR_REGNUM), |
1880 | (long) get_frame_register_unsigned (frame, PR_REGNUM), | |
1881 | (long) get_frame_register_unsigned (frame, MACH_REGNUM)); | |
c906108c | 1882 | |
c458d6db UW |
1883 | printf_filtered |
1884 | (" GBR %08lx VBR %08lx MACL %08lx\n", | |
1885 | (long) get_frame_register_unsigned (frame, GBR_REGNUM), | |
1886 | (long) get_frame_register_unsigned (frame, VBR_REGNUM), | |
1887 | (long) get_frame_register_unsigned (frame, MACL_REGNUM)); | |
cc17453a | 1888 | |
c458d6db UW |
1889 | printf_filtered |
1890 | (" SSR %08lx SPC %08lx DSR %08lx\n", | |
1891 | (long) get_frame_register_unsigned (frame, SSR_REGNUM), | |
1892 | (long) get_frame_register_unsigned (frame, SPC_REGNUM), | |
1893 | (long) get_frame_register_unsigned (frame, DSR_REGNUM)); | |
617daa0e CV |
1894 | |
1895 | printf_filtered | |
a6b0a3f3 | 1896 | ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
c458d6db UW |
1897 | (long) get_frame_register_unsigned (frame, 0), |
1898 | (long) get_frame_register_unsigned (frame, 1), | |
1899 | (long) get_frame_register_unsigned (frame, 2), | |
1900 | (long) get_frame_register_unsigned (frame, 3), | |
1901 | (long) get_frame_register_unsigned (frame, 4), | |
1902 | (long) get_frame_register_unsigned (frame, 5), | |
1903 | (long) get_frame_register_unsigned (frame, 6), | |
1904 | (long) get_frame_register_unsigned (frame, 7)); | |
1905 | printf_filtered | |
1906 | ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1907 | (long) get_frame_register_unsigned (frame, 8), | |
1908 | (long) get_frame_register_unsigned (frame, 9), | |
1909 | (long) get_frame_register_unsigned (frame, 10), | |
1910 | (long) get_frame_register_unsigned (frame, 11), | |
1911 | (long) get_frame_register_unsigned (frame, 12), | |
1912 | (long) get_frame_register_unsigned (frame, 13), | |
1913 | (long) get_frame_register_unsigned (frame, 14), | |
1914 | (long) get_frame_register_unsigned (frame, 15)); | |
617daa0e CV |
1915 | |
1916 | printf_filtered | |
1917 | ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n", | |
c458d6db UW |
1918 | (long) get_frame_register_unsigned (frame, A0G_REGNUM) & 0xff, |
1919 | (long) get_frame_register_unsigned (frame, A0_REGNUM), | |
1920 | (long) get_frame_register_unsigned (frame, M0_REGNUM), | |
1921 | (long) get_frame_register_unsigned (frame, X0_REGNUM), | |
1922 | (long) get_frame_register_unsigned (frame, Y0_REGNUM), | |
1923 | (long) get_frame_register_unsigned (frame, RS_REGNUM), | |
1924 | (long) get_frame_register_unsigned (frame, MOD_REGNUM)); | |
1925 | printf_filtered | |
1926 | ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n", | |
1927 | (long) get_frame_register_unsigned (frame, A1G_REGNUM) & 0xff, | |
1928 | (long) get_frame_register_unsigned (frame, A1_REGNUM), | |
1929 | (long) get_frame_register_unsigned (frame, M1_REGNUM), | |
1930 | (long) get_frame_register_unsigned (frame, X1_REGNUM), | |
1931 | (long) get_frame_register_unsigned (frame, Y1_REGNUM), | |
1932 | (long) get_frame_register_unsigned (frame, RE_REGNUM)); | |
c906108c SS |
1933 | } |
1934 | ||
cc17453a | 1935 | static void |
c458d6db | 1936 | sh4_show_regs (struct frame_info *frame) |
cc17453a | 1937 | { |
b47193f7 | 1938 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c458d6db UW |
1939 | int pr = get_frame_register_unsigned (frame, FPSCR_REGNUM) & 0x80000; |
1940 | ||
1941 | printf_filtered | |
1942 | (" PC %s SR %08lx PR %08lx MACH %08lx\n", | |
5af949e3 UW |
1943 | phex (get_frame_register_unsigned (frame, |
1944 | gdbarch_pc_regnum (gdbarch)), 4), | |
c458d6db UW |
1945 | (long) get_frame_register_unsigned (frame, SR_REGNUM), |
1946 | (long) get_frame_register_unsigned (frame, PR_REGNUM), | |
1947 | (long) get_frame_register_unsigned (frame, MACH_REGNUM)); | |
1948 | ||
1949 | printf_filtered | |
1950 | (" GBR %08lx VBR %08lx MACL %08lx\n", | |
1951 | (long) get_frame_register_unsigned (frame, GBR_REGNUM), | |
1952 | (long) get_frame_register_unsigned (frame, VBR_REGNUM), | |
1953 | (long) get_frame_register_unsigned (frame, MACL_REGNUM)); | |
1954 | printf_filtered | |
1955 | (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n", | |
1956 | (long) get_frame_register_unsigned (frame, SSR_REGNUM), | |
1957 | (long) get_frame_register_unsigned (frame, SPC_REGNUM), | |
1958 | (long) get_frame_register_unsigned (frame, FPUL_REGNUM), | |
1959 | (long) get_frame_register_unsigned (frame, FPSCR_REGNUM)); | |
1960 | ||
1961 | printf_filtered | |
1962 | ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1963 | (long) get_frame_register_unsigned (frame, 0), | |
1964 | (long) get_frame_register_unsigned (frame, 1), | |
1965 | (long) get_frame_register_unsigned (frame, 2), | |
1966 | (long) get_frame_register_unsigned (frame, 3), | |
1967 | (long) get_frame_register_unsigned (frame, 4), | |
1968 | (long) get_frame_register_unsigned (frame, 5), | |
1969 | (long) get_frame_register_unsigned (frame, 6), | |
1970 | (long) get_frame_register_unsigned (frame, 7)); | |
1971 | printf_filtered | |
1972 | ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1973 | (long) get_frame_register_unsigned (frame, 8), | |
1974 | (long) get_frame_register_unsigned (frame, 9), | |
1975 | (long) get_frame_register_unsigned (frame, 10), | |
1976 | (long) get_frame_register_unsigned (frame, 11), | |
1977 | (long) get_frame_register_unsigned (frame, 12), | |
1978 | (long) get_frame_register_unsigned (frame, 13), | |
1979 | (long) get_frame_register_unsigned (frame, 14), | |
1980 | (long) get_frame_register_unsigned (frame, 15)); | |
1981 | ||
1982 | printf_filtered | |
1983 | (pr ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n" | |
1984 | : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
3e8c568d | 1985 | (long) get_frame_register_unsigned |
b47193f7 | 1986 | (frame, gdbarch_fp0_regnum (gdbarch) + 0), |
3e8c568d | 1987 | (long) get_frame_register_unsigned |
b47193f7 | 1988 | (frame, gdbarch_fp0_regnum (gdbarch) + 1), |
3e8c568d | 1989 | (long) get_frame_register_unsigned |
b47193f7 | 1990 | (frame, gdbarch_fp0_regnum (gdbarch) + 2), |
3e8c568d | 1991 | (long) get_frame_register_unsigned |
b47193f7 | 1992 | (frame, gdbarch_fp0_regnum (gdbarch) + 3), |
3e8c568d | 1993 | (long) get_frame_register_unsigned |
b47193f7 | 1994 | (frame, gdbarch_fp0_regnum (gdbarch) + 4), |
3e8c568d | 1995 | (long) get_frame_register_unsigned |
b47193f7 | 1996 | (frame, gdbarch_fp0_regnum (gdbarch) + 5), |
3e8c568d | 1997 | (long) get_frame_register_unsigned |
b47193f7 | 1998 | (frame, gdbarch_fp0_regnum (gdbarch) + 6), |
3e8c568d | 1999 | (long) get_frame_register_unsigned |
b47193f7 | 2000 | (frame, gdbarch_fp0_regnum (gdbarch) + 7)); |
c458d6db UW |
2001 | printf_filtered |
2002 | (pr ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n" | |
2003 | : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
3e8c568d | 2004 | (long) get_frame_register_unsigned |
b47193f7 | 2005 | (frame, gdbarch_fp0_regnum (gdbarch) + 8), |
3e8c568d | 2006 | (long) get_frame_register_unsigned |
b47193f7 | 2007 | (frame, gdbarch_fp0_regnum (gdbarch) + 9), |
3e8c568d | 2008 | (long) get_frame_register_unsigned |
b47193f7 | 2009 | (frame, gdbarch_fp0_regnum (gdbarch) + 10), |
3e8c568d | 2010 | (long) get_frame_register_unsigned |
b47193f7 | 2011 | (frame, gdbarch_fp0_regnum (gdbarch) + 11), |
3e8c568d | 2012 | (long) get_frame_register_unsigned |
b47193f7 | 2013 | (frame, gdbarch_fp0_regnum (gdbarch) + 12), |
3e8c568d | 2014 | (long) get_frame_register_unsigned |
b47193f7 | 2015 | (frame, gdbarch_fp0_regnum (gdbarch) + 13), |
3e8c568d | 2016 | (long) get_frame_register_unsigned |
b47193f7 | 2017 | (frame, gdbarch_fp0_regnum (gdbarch) + 14), |
3e8c568d | 2018 | (long) get_frame_register_unsigned |
b47193f7 | 2019 | (frame, gdbarch_fp0_regnum (gdbarch) + 15)); |
cc17453a EZ |
2020 | } |
2021 | ||
474e5826 | 2022 | static void |
c458d6db | 2023 | sh4_nofpu_show_regs (struct frame_info *frame) |
474e5826 | 2024 | { |
c458d6db UW |
2025 | printf_filtered |
2026 | (" PC %s SR %08lx PR %08lx MACH %08lx\n", | |
5af949e3 UW |
2027 | phex (get_frame_register_unsigned (frame, |
2028 | gdbarch_pc_regnum | |
2029 | (get_frame_arch (frame))), 4), | |
c458d6db UW |
2030 | (long) get_frame_register_unsigned (frame, SR_REGNUM), |
2031 | (long) get_frame_register_unsigned (frame, PR_REGNUM), | |
2032 | (long) get_frame_register_unsigned (frame, MACH_REGNUM)); | |
2033 | ||
2034 | printf_filtered | |
2035 | (" GBR %08lx VBR %08lx MACL %08lx\n", | |
2036 | (long) get_frame_register_unsigned (frame, GBR_REGNUM), | |
2037 | (long) get_frame_register_unsigned (frame, VBR_REGNUM), | |
2038 | (long) get_frame_register_unsigned (frame, MACL_REGNUM)); | |
2039 | printf_filtered | |
2040 | (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n", | |
2041 | (long) get_frame_register_unsigned (frame, SSR_REGNUM), | |
2042 | (long) get_frame_register_unsigned (frame, SPC_REGNUM), | |
2043 | (long) get_frame_register_unsigned (frame, FPUL_REGNUM), | |
2044 | (long) get_frame_register_unsigned (frame, FPSCR_REGNUM)); | |
2045 | ||
2046 | printf_filtered | |
2047 | ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
2048 | (long) get_frame_register_unsigned (frame, 0), | |
2049 | (long) get_frame_register_unsigned (frame, 1), | |
2050 | (long) get_frame_register_unsigned (frame, 2), | |
2051 | (long) get_frame_register_unsigned (frame, 3), | |
2052 | (long) get_frame_register_unsigned (frame, 4), | |
2053 | (long) get_frame_register_unsigned (frame, 5), | |
2054 | (long) get_frame_register_unsigned (frame, 6), | |
2055 | (long) get_frame_register_unsigned (frame, 7)); | |
2056 | printf_filtered | |
2057 | ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
2058 | (long) get_frame_register_unsigned (frame, 8), | |
2059 | (long) get_frame_register_unsigned (frame, 9), | |
2060 | (long) get_frame_register_unsigned (frame, 10), | |
2061 | (long) get_frame_register_unsigned (frame, 11), | |
2062 | (long) get_frame_register_unsigned (frame, 12), | |
2063 | (long) get_frame_register_unsigned (frame, 13), | |
2064 | (long) get_frame_register_unsigned (frame, 14), | |
2065 | (long) get_frame_register_unsigned (frame, 15)); | |
474e5826 CV |
2066 | } |
2067 | ||
cc17453a | 2068 | static void |
c458d6db | 2069 | sh_dsp_show_regs (struct frame_info *frame) |
cc17453a | 2070 | { |
c458d6db UW |
2071 | printf_filtered |
2072 | (" PC %s SR %08lx PR %08lx MACH %08lx\n", | |
5af949e3 UW |
2073 | phex (get_frame_register_unsigned (frame, |
2074 | gdbarch_pc_regnum | |
2075 | (get_frame_arch (frame))), 4), | |
c458d6db UW |
2076 | (long) get_frame_register_unsigned (frame, SR_REGNUM), |
2077 | (long) get_frame_register_unsigned (frame, PR_REGNUM), | |
2078 | (long) get_frame_register_unsigned (frame, MACH_REGNUM)); | |
a6b0a3f3 | 2079 | |
c458d6db UW |
2080 | printf_filtered |
2081 | (" GBR %08lx VBR %08lx DSR %08lx MACL %08lx\n", | |
2082 | (long) get_frame_register_unsigned (frame, GBR_REGNUM), | |
2083 | (long) get_frame_register_unsigned (frame, VBR_REGNUM), | |
2084 | (long) get_frame_register_unsigned (frame, DSR_REGNUM), | |
2085 | (long) get_frame_register_unsigned (frame, MACL_REGNUM)); | |
617daa0e CV |
2086 | |
2087 | printf_filtered | |
a6b0a3f3 | 2088 | ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
c458d6db UW |
2089 | (long) get_frame_register_unsigned (frame, 0), |
2090 | (long) get_frame_register_unsigned (frame, 1), | |
2091 | (long) get_frame_register_unsigned (frame, 2), | |
2092 | (long) get_frame_register_unsigned (frame, 3), | |
2093 | (long) get_frame_register_unsigned (frame, 4), | |
2094 | (long) get_frame_register_unsigned (frame, 5), | |
2095 | (long) get_frame_register_unsigned (frame, 6), | |
2096 | (long) get_frame_register_unsigned (frame, 7)); | |
2097 | printf_filtered | |
2098 | ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
2099 | (long) get_frame_register_unsigned (frame, 8), | |
2100 | (long) get_frame_register_unsigned (frame, 9), | |
2101 | (long) get_frame_register_unsigned (frame, 10), | |
2102 | (long) get_frame_register_unsigned (frame, 11), | |
2103 | (long) get_frame_register_unsigned (frame, 12), | |
2104 | (long) get_frame_register_unsigned (frame, 13), | |
2105 | (long) get_frame_register_unsigned (frame, 14), | |
2106 | (long) get_frame_register_unsigned (frame, 15)); | |
617daa0e CV |
2107 | |
2108 | printf_filtered | |
2109 | ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n", | |
c458d6db UW |
2110 | (long) get_frame_register_unsigned (frame, A0G_REGNUM) & 0xff, |
2111 | (long) get_frame_register_unsigned (frame, A0_REGNUM), | |
2112 | (long) get_frame_register_unsigned (frame, M0_REGNUM), | |
2113 | (long) get_frame_register_unsigned (frame, X0_REGNUM), | |
2114 | (long) get_frame_register_unsigned (frame, Y0_REGNUM), | |
2115 | (long) get_frame_register_unsigned (frame, RS_REGNUM), | |
2116 | (long) get_frame_register_unsigned (frame, MOD_REGNUM)); | |
cc17453a | 2117 | printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n", |
c458d6db UW |
2118 | (long) get_frame_register_unsigned (frame, A1G_REGNUM) & 0xff, |
2119 | (long) get_frame_register_unsigned (frame, A1_REGNUM), | |
2120 | (long) get_frame_register_unsigned (frame, M1_REGNUM), | |
2121 | (long) get_frame_register_unsigned (frame, X1_REGNUM), | |
2122 | (long) get_frame_register_unsigned (frame, Y1_REGNUM), | |
2123 | (long) get_frame_register_unsigned (frame, RE_REGNUM)); | |
cc17453a EZ |
2124 | } |
2125 | ||
a78f21af AC |
2126 | static void |
2127 | sh_show_regs_command (char *args, int from_tty) | |
53116e27 EZ |
2128 | { |
2129 | if (sh_show_regs) | |
c458d6db | 2130 | (*sh_show_regs) (get_current_frame ()); |
53116e27 EZ |
2131 | } |
2132 | ||
da962468 CV |
2133 | static struct type * |
2134 | sh_sh2a_register_type (struct gdbarch *gdbarch, int reg_nr) | |
2135 | { | |
b47193f7 | 2136 | if ((reg_nr >= gdbarch_fp0_regnum (gdbarch) |
da962468 | 2137 | && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM)) |
0dfff4cb | 2138 | return builtin_type (gdbarch)->builtin_float; |
da962468 | 2139 | else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM) |
0dfff4cb | 2140 | return builtin_type (gdbarch)->builtin_double; |
da962468 | 2141 | else |
0dfff4cb | 2142 | return builtin_type (gdbarch)->builtin_int; |
da962468 CV |
2143 | } |
2144 | ||
cc17453a EZ |
2145 | /* Return the GDB type object for the "standard" data type |
2146 | of data in register N. */ | |
cc17453a | 2147 | static struct type * |
48db5a3c | 2148 | sh_sh3e_register_type (struct gdbarch *gdbarch, int reg_nr) |
cc17453a | 2149 | { |
b47193f7 | 2150 | if ((reg_nr >= gdbarch_fp0_regnum (gdbarch) |
617daa0e | 2151 | && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM)) |
0dfff4cb | 2152 | return builtin_type (gdbarch)->builtin_float; |
8db62801 | 2153 | else |
0dfff4cb | 2154 | return builtin_type (gdbarch)->builtin_int; |
cc17453a EZ |
2155 | } |
2156 | ||
7f4dbe94 | 2157 | static struct type * |
0dfff4cb | 2158 | sh_sh4_build_float_register_type (struct gdbarch *gdbarch, int high) |
7f4dbe94 | 2159 | { |
e3506a9f UW |
2160 | return lookup_array_range_type (builtin_type (gdbarch)->builtin_float, |
2161 | 0, high); | |
7f4dbe94 EZ |
2162 | } |
2163 | ||
53116e27 | 2164 | static struct type * |
48db5a3c | 2165 | sh_sh4_register_type (struct gdbarch *gdbarch, int reg_nr) |
53116e27 | 2166 | { |
b47193f7 | 2167 | if ((reg_nr >= gdbarch_fp0_regnum (gdbarch) |
617daa0e | 2168 | && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM)) |
0dfff4cb | 2169 | return builtin_type (gdbarch)->builtin_float; |
617daa0e | 2170 | else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM) |
0dfff4cb | 2171 | return builtin_type (gdbarch)->builtin_double; |
617daa0e | 2172 | else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM) |
0dfff4cb | 2173 | return sh_sh4_build_float_register_type (gdbarch, 3); |
53116e27 | 2174 | else |
0dfff4cb | 2175 | return builtin_type (gdbarch)->builtin_int; |
53116e27 EZ |
2176 | } |
2177 | ||
cc17453a | 2178 | static struct type * |
48db5a3c | 2179 | sh_default_register_type (struct gdbarch *gdbarch, int reg_nr) |
cc17453a | 2180 | { |
0dfff4cb | 2181 | return builtin_type (gdbarch)->builtin_int; |
cc17453a EZ |
2182 | } |
2183 | ||
dda63807 AS |
2184 | /* Is a register in a reggroup? |
2185 | The default code in reggroup.c doesn't identify system registers, some | |
2186 | float registers or any of the vector registers. | |
2187 | TODO: sh2a and dsp registers. */ | |
63807e1d | 2188 | static int |
dda63807 AS |
2189 | sh_register_reggroup_p (struct gdbarch *gdbarch, int regnum, |
2190 | struct reggroup *reggroup) | |
2191 | { | |
b47193f7 UW |
2192 | if (gdbarch_register_name (gdbarch, regnum) == NULL |
2193 | || *gdbarch_register_name (gdbarch, regnum) == '\0') | |
dda63807 AS |
2194 | return 0; |
2195 | ||
2196 | if (reggroup == float_reggroup | |
2197 | && (regnum == FPUL_REGNUM | |
2198 | || regnum == FPSCR_REGNUM)) | |
2199 | return 1; | |
2200 | ||
2201 | if (regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM) | |
2202 | { | |
2203 | if (reggroup == vector_reggroup || reggroup == float_reggroup) | |
2204 | return 1; | |
2205 | if (reggroup == general_reggroup) | |
2206 | return 0; | |
2207 | } | |
2208 | ||
2209 | if (regnum == VBR_REGNUM | |
2210 | || regnum == SR_REGNUM | |
2211 | || regnum == FPSCR_REGNUM | |
2212 | || regnum == SSR_REGNUM | |
2213 | || regnum == SPC_REGNUM) | |
2214 | { | |
2215 | if (reggroup == system_reggroup) | |
2216 | return 1; | |
2217 | if (reggroup == general_reggroup) | |
2218 | return 0; | |
2219 | } | |
2220 | ||
2221 | /* The default code can cope with any other registers. */ | |
2222 | return default_register_reggroup_p (gdbarch, regnum, reggroup); | |
2223 | } | |
2224 | ||
fb409745 | 2225 | /* On the sh4, the DRi pseudo registers are problematic if the target |
c378eb4e | 2226 | is little endian. When the user writes one of those registers, for |
fb409745 EZ |
2227 | instance with 'ser var $dr0=1', we want the double to be stored |
2228 | like this: | |
2229 | fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f | |
2230 | fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00 | |
2231 | ||
2232 | This corresponds to little endian byte order & big endian word | |
2233 | order. However if we let gdb write the register w/o conversion, it | |
2234 | will write fr0 and fr1 this way: | |
2235 | fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00 | |
2236 | fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f | |
2237 | because it will consider fr0 and fr1 as a single LE stretch of memory. | |
2238 | ||
2239 | To achieve what we want we must force gdb to store things in | |
2240 | floatformat_ieee_double_littlebyte_bigword (which is defined in | |
2241 | include/floatformat.h and libiberty/floatformat.c. | |
2242 | ||
2243 | In case the target is big endian, there is no problem, the | |
2244 | raw bytes will look like: | |
2245 | fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00 | |
2246 | fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00 | |
2247 | ||
2248 | The other pseudo registers (the FVs) also don't pose a problem | |
c378eb4e | 2249 | because they are stored as 4 individual FP elements. */ |
fb409745 | 2250 | |
7bd872fe | 2251 | static void |
b66ba949 CV |
2252 | sh_register_convert_to_virtual (int regnum, struct type *type, |
2253 | char *from, char *to) | |
55ff77ac | 2254 | { |
617daa0e | 2255 | if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM) |
283150cd EZ |
2256 | { |
2257 | DOUBLEST val; | |
617daa0e CV |
2258 | floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, |
2259 | from, &val); | |
55ff77ac | 2260 | store_typed_floating (to, type, val); |
283150cd EZ |
2261 | } |
2262 | else | |
617daa0e CV |
2263 | error |
2264 | ("sh_register_convert_to_virtual called with non DR register number"); | |
283150cd EZ |
2265 | } |
2266 | ||
2267 | static void | |
b66ba949 CV |
2268 | sh_register_convert_to_raw (struct type *type, int regnum, |
2269 | const void *from, void *to) | |
283150cd | 2270 | { |
617daa0e | 2271 | if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM) |
283150cd | 2272 | { |
48db5a3c | 2273 | DOUBLEST val = extract_typed_floating (from, type); |
617daa0e CV |
2274 | floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword, |
2275 | &val, to); | |
283150cd EZ |
2276 | } |
2277 | else | |
8a3fe4f8 | 2278 | error (_("sh_register_convert_to_raw called with non DR register number")); |
283150cd EZ |
2279 | } |
2280 | ||
c378eb4e | 2281 | /* For vectors of 4 floating point registers. */ |
1c0159e0 | 2282 | static int |
d93859e2 | 2283 | fv_reg_base_num (struct gdbarch *gdbarch, int fv_regnum) |
1c0159e0 CV |
2284 | { |
2285 | int fp_regnum; | |
2286 | ||
d93859e2 | 2287 | fp_regnum = gdbarch_fp0_regnum (gdbarch) |
3e8c568d | 2288 | + (fv_regnum - FV0_REGNUM) * 4; |
1c0159e0 CV |
2289 | return fp_regnum; |
2290 | } | |
2291 | ||
c378eb4e | 2292 | /* For double precision floating point registers, i.e 2 fp regs. */ |
1c0159e0 | 2293 | static int |
d93859e2 | 2294 | dr_reg_base_num (struct gdbarch *gdbarch, int dr_regnum) |
1c0159e0 CV |
2295 | { |
2296 | int fp_regnum; | |
2297 | ||
d93859e2 | 2298 | fp_regnum = gdbarch_fp0_regnum (gdbarch) |
3e8c568d | 2299 | + (dr_regnum - DR0_REGNUM) * 2; |
1c0159e0 CV |
2300 | return fp_regnum; |
2301 | } | |
2302 | ||
05d1431c PA |
2303 | /* Concatenate PORTIONS contiguous raw registers starting at |
2304 | BASE_REGNUM into BUFFER. */ | |
2305 | ||
2306 | static enum register_status | |
2307 | pseudo_register_read_portions (struct gdbarch *gdbarch, | |
2308 | struct regcache *regcache, | |
2309 | int portions, | |
2310 | int base_regnum, gdb_byte *buffer) | |
2311 | { | |
2312 | int portion; | |
2313 | ||
2314 | for (portion = 0; portion < portions; portion++) | |
2315 | { | |
2316 | enum register_status status; | |
2317 | gdb_byte *b; | |
2318 | ||
2319 | b = buffer + register_size (gdbarch, base_regnum) * portion; | |
2320 | status = regcache_raw_read (regcache, base_regnum + portion, b); | |
2321 | if (status != REG_VALID) | |
2322 | return status; | |
2323 | } | |
2324 | ||
2325 | return REG_VALID; | |
2326 | } | |
2327 | ||
2328 | static enum register_status | |
d8124050 | 2329 | sh_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, |
18cf8b5b | 2330 | int reg_nr, gdb_byte *buffer) |
53116e27 | 2331 | { |
05d1431c | 2332 | int base_regnum; |
d9d9c31f | 2333 | char temp_buffer[MAX_REGISTER_SIZE]; |
05d1431c | 2334 | enum register_status status; |
53116e27 | 2335 | |
9bed62d7 | 2336 | if (reg_nr == PSEUDO_BANK_REGNUM) |
05d1431c PA |
2337 | return regcache_raw_read (regcache, BANK_REGNUM, buffer); |
2338 | else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM) | |
7bd872fe | 2339 | { |
d93859e2 | 2340 | base_regnum = dr_reg_base_num (gdbarch, reg_nr); |
7bd872fe | 2341 | |
c378eb4e | 2342 | /* Build the value in the provided buffer. */ |
7bd872fe | 2343 | /* Read the real regs for which this one is an alias. */ |
05d1431c PA |
2344 | status = pseudo_register_read_portions (gdbarch, regcache, |
2345 | 2, base_regnum, temp_buffer); | |
2346 | if (status == REG_VALID) | |
2347 | { | |
2348 | /* We must pay attention to the endiannes. */ | |
2349 | sh_register_convert_to_virtual (reg_nr, | |
2350 | register_type (gdbarch, reg_nr), | |
2351 | temp_buffer, buffer); | |
2352 | } | |
2353 | return status; | |
7bd872fe | 2354 | } |
617daa0e | 2355 | else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM) |
53116e27 | 2356 | { |
d93859e2 | 2357 | base_regnum = fv_reg_base_num (gdbarch, reg_nr); |
7bd872fe EZ |
2358 | |
2359 | /* Read the real regs for which this one is an alias. */ | |
05d1431c PA |
2360 | return pseudo_register_read_portions (gdbarch, regcache, |
2361 | 4, base_regnum, buffer); | |
53116e27 | 2362 | } |
05d1431c PA |
2363 | else |
2364 | gdb_assert_not_reached ("invalid pseudo register number"); | |
53116e27 EZ |
2365 | } |
2366 | ||
a78f21af | 2367 | static void |
d8124050 | 2368 | sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, |
18cf8b5b | 2369 | int reg_nr, const gdb_byte *buffer) |
53116e27 EZ |
2370 | { |
2371 | int base_regnum, portion; | |
d9d9c31f | 2372 | char temp_buffer[MAX_REGISTER_SIZE]; |
53116e27 | 2373 | |
9bed62d7 CV |
2374 | if (reg_nr == PSEUDO_BANK_REGNUM) |
2375 | { | |
2376 | /* When the bank register is written to, the whole register bank | |
2377 | is switched and all values in the bank registers must be read | |
c378eb4e | 2378 | from the target/sim again. We're just invalidating the regcache |
9bed62d7 CV |
2379 | so that a re-read happens next time it's necessary. */ |
2380 | int bregnum; | |
2381 | ||
2382 | regcache_raw_write (regcache, BANK_REGNUM, buffer); | |
2383 | for (bregnum = R0_BANK0_REGNUM; bregnum < MACLB_REGNUM; ++bregnum) | |
9c5ea4d9 | 2384 | regcache_invalidate (regcache, bregnum); |
9bed62d7 CV |
2385 | } |
2386 | else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM) | |
53116e27 | 2387 | { |
d93859e2 | 2388 | base_regnum = dr_reg_base_num (gdbarch, reg_nr); |
53116e27 | 2389 | |
c378eb4e | 2390 | /* We must pay attention to the endiannes. */ |
7b9ee6a8 | 2391 | sh_register_convert_to_raw (register_type (gdbarch, reg_nr), |
b66ba949 | 2392 | reg_nr, buffer, temp_buffer); |
7bd872fe | 2393 | |
53116e27 EZ |
2394 | /* Write the real regs for which this one is an alias. */ |
2395 | for (portion = 0; portion < 2; portion++) | |
617daa0e | 2396 | regcache_raw_write (regcache, base_regnum + portion, |
0818c12a | 2397 | (temp_buffer |
617daa0e CV |
2398 | + register_size (gdbarch, |
2399 | base_regnum) * portion)); | |
53116e27 | 2400 | } |
617daa0e | 2401 | else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM) |
53116e27 | 2402 | { |
d93859e2 | 2403 | base_regnum = fv_reg_base_num (gdbarch, reg_nr); |
53116e27 EZ |
2404 | |
2405 | /* Write the real regs for which this one is an alias. */ | |
2406 | for (portion = 0; portion < 4; portion++) | |
d8124050 AC |
2407 | regcache_raw_write (regcache, base_regnum + portion, |
2408 | ((char *) buffer | |
617daa0e CV |
2409 | + register_size (gdbarch, |
2410 | base_regnum) * portion)); | |
53116e27 EZ |
2411 | } |
2412 | } | |
2413 | ||
2f14585c | 2414 | static int |
e7faf938 | 2415 | sh_dsp_register_sim_regno (struct gdbarch *gdbarch, int nr) |
2f14585c | 2416 | { |
e7faf938 MD |
2417 | if (legacy_register_sim_regno (gdbarch, nr) < 0) |
2418 | return legacy_register_sim_regno (gdbarch, nr); | |
f2ea0907 CV |
2419 | if (nr >= DSR_REGNUM && nr <= Y1_REGNUM) |
2420 | return nr - DSR_REGNUM + SIM_SH_DSR_REGNUM; | |
2421 | if (nr == MOD_REGNUM) | |
2f14585c | 2422 | return SIM_SH_MOD_REGNUM; |
f2ea0907 | 2423 | if (nr == RS_REGNUM) |
2f14585c | 2424 | return SIM_SH_RS_REGNUM; |
f2ea0907 | 2425 | if (nr == RE_REGNUM) |
2f14585c | 2426 | return SIM_SH_RE_REGNUM; |
76cd2bd9 CV |
2427 | if (nr >= DSP_R0_BANK_REGNUM && nr <= DSP_R7_BANK_REGNUM) |
2428 | return nr - DSP_R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM; | |
2f14585c JR |
2429 | return nr; |
2430 | } | |
1c0159e0 | 2431 | |
da962468 | 2432 | static int |
e7faf938 | 2433 | sh_sh2a_register_sim_regno (struct gdbarch *gdbarch, int nr) |
da962468 CV |
2434 | { |
2435 | switch (nr) | |
2436 | { | |
2437 | case TBR_REGNUM: | |
2438 | return SIM_SH_TBR_REGNUM; | |
2439 | case IBNR_REGNUM: | |
2440 | return SIM_SH_IBNR_REGNUM; | |
2441 | case IBCR_REGNUM: | |
2442 | return SIM_SH_IBCR_REGNUM; | |
2443 | case BANK_REGNUM: | |
2444 | return SIM_SH_BANK_REGNUM; | |
2445 | case MACLB_REGNUM: | |
2446 | return SIM_SH_BANK_MACL_REGNUM; | |
2447 | case GBRB_REGNUM: | |
2448 | return SIM_SH_BANK_GBR_REGNUM; | |
2449 | case PRB_REGNUM: | |
2450 | return SIM_SH_BANK_PR_REGNUM; | |
2451 | case IVNB_REGNUM: | |
2452 | return SIM_SH_BANK_IVN_REGNUM; | |
2453 | case MACHB_REGNUM: | |
2454 | return SIM_SH_BANK_MACH_REGNUM; | |
2455 | default: | |
2456 | break; | |
2457 | } | |
e7faf938 | 2458 | return legacy_register_sim_regno (gdbarch, nr); |
da962468 CV |
2459 | } |
2460 | ||
357d3800 AS |
2461 | /* Set up the register unwinding such that call-clobbered registers are |
2462 | not displayed in frames >0 because the true value is not certain. | |
2463 | The 'undefined' registers will show up as 'not available' unless the | |
2464 | CFI says otherwise. | |
2465 | ||
2466 | This function is currently set up for SH4 and compatible only. */ | |
2467 | ||
2468 | static void | |
2469 | sh_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
aff37fc1 | 2470 | struct dwarf2_frame_state_reg *reg, |
4a4e5149 | 2471 | struct frame_info *this_frame) |
357d3800 AS |
2472 | { |
2473 | /* Mark the PC as the destination for the return address. */ | |
b47193f7 | 2474 | if (regnum == gdbarch_pc_regnum (gdbarch)) |
357d3800 AS |
2475 | reg->how = DWARF2_FRAME_REG_RA; |
2476 | ||
2477 | /* Mark the stack pointer as the call frame address. */ | |
b47193f7 | 2478 | else if (regnum == gdbarch_sp_regnum (gdbarch)) |
357d3800 AS |
2479 | reg->how = DWARF2_FRAME_REG_CFA; |
2480 | ||
2481 | /* The above was taken from the default init_reg in dwarf2-frame.c | |
2482 | while the below is SH specific. */ | |
2483 | ||
2484 | /* Caller save registers. */ | |
2485 | else if ((regnum >= R0_REGNUM && regnum <= R0_REGNUM+7) | |
2486 | || (regnum >= FR0_REGNUM && regnum <= FR0_REGNUM+11) | |
2487 | || (regnum >= DR0_REGNUM && regnum <= DR0_REGNUM+5) | |
2488 | || (regnum >= FV0_REGNUM && regnum <= FV0_REGNUM+2) | |
2489 | || (regnum == MACH_REGNUM) | |
2490 | || (regnum == MACL_REGNUM) | |
2491 | || (regnum == FPUL_REGNUM) | |
2492 | || (regnum == SR_REGNUM)) | |
2493 | reg->how = DWARF2_FRAME_REG_UNDEFINED; | |
2494 | ||
2495 | /* Callee save registers. */ | |
2496 | else if ((regnum >= R0_REGNUM+8 && regnum <= R0_REGNUM+15) | |
2497 | || (regnum >= FR0_REGNUM+12 && regnum <= FR0_REGNUM+15) | |
2498 | || (regnum >= DR0_REGNUM+6 && regnum <= DR0_REGNUM+8) | |
2499 | || (regnum == FV0_REGNUM+3)) | |
2500 | reg->how = DWARF2_FRAME_REG_SAME_VALUE; | |
2501 | ||
2502 | /* Other registers. These are not in the ABI and may or may not | |
2503 | mean anything in frames >0 so don't show them. */ | |
2504 | else if ((regnum >= R0_BANK0_REGNUM && regnum <= R0_BANK0_REGNUM+15) | |
2505 | || (regnum == GBR_REGNUM) | |
2506 | || (regnum == VBR_REGNUM) | |
2507 | || (regnum == FPSCR_REGNUM) | |
2508 | || (regnum == SSR_REGNUM) | |
2509 | || (regnum == SPC_REGNUM)) | |
2510 | reg->how = DWARF2_FRAME_REG_UNDEFINED; | |
2511 | } | |
2512 | ||
1c0159e0 CV |
2513 | static struct sh_frame_cache * |
2514 | sh_alloc_frame_cache (void) | |
2515 | { | |
2516 | struct sh_frame_cache *cache; | |
2517 | int i; | |
2518 | ||
2519 | cache = FRAME_OBSTACK_ZALLOC (struct sh_frame_cache); | |
2520 | ||
2521 | /* Base address. */ | |
2522 | cache->base = 0; | |
2523 | cache->saved_sp = 0; | |
2524 | cache->sp_offset = 0; | |
2525 | cache->pc = 0; | |
2526 | ||
2527 | /* Frameless until proven otherwise. */ | |
2528 | cache->uses_fp = 0; | |
617daa0e | 2529 | |
1c0159e0 CV |
2530 | /* Saved registers. We initialize these to -1 since zero is a valid |
2531 | offset (that's where fp is supposed to be stored). */ | |
2532 | for (i = 0; i < SH_NUM_REGS; i++) | |
2533 | { | |
2534 | cache->saved_regs[i] = -1; | |
2535 | } | |
617daa0e | 2536 | |
1c0159e0 | 2537 | return cache; |
617daa0e | 2538 | } |
1c0159e0 CV |
2539 | |
2540 | static struct sh_frame_cache * | |
94afd7a6 | 2541 | sh_frame_cache (struct frame_info *this_frame, void **this_cache) |
1c0159e0 | 2542 | { |
e17a4113 | 2543 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1c0159e0 CV |
2544 | struct sh_frame_cache *cache; |
2545 | CORE_ADDR current_pc; | |
2546 | int i; | |
2547 | ||
2548 | if (*this_cache) | |
2549 | return *this_cache; | |
2550 | ||
2551 | cache = sh_alloc_frame_cache (); | |
2552 | *this_cache = cache; | |
2553 | ||
2554 | /* In principle, for normal frames, fp holds the frame pointer, | |
2555 | which holds the base address for the current stack frame. | |
2556 | However, for functions that don't need it, the frame pointer is | |
2557 | optional. For these "frameless" functions the frame pointer is | |
c378eb4e | 2558 | actually the frame pointer of the calling frame. */ |
94afd7a6 | 2559 | cache->base = get_frame_register_unsigned (this_frame, FP_REGNUM); |
1c0159e0 CV |
2560 | if (cache->base == 0) |
2561 | return cache; | |
2562 | ||
94afd7a6 UW |
2563 | cache->pc = get_frame_func (this_frame); |
2564 | current_pc = get_frame_pc (this_frame); | |
1c0159e0 | 2565 | if (cache->pc != 0) |
d2ca4222 UW |
2566 | { |
2567 | ULONGEST fpscr; | |
94afd7a6 | 2568 | fpscr = get_frame_register_unsigned (this_frame, FPSCR_REGNUM); |
e17a4113 | 2569 | sh_analyze_prologue (gdbarch, cache->pc, current_pc, cache, fpscr); |
d2ca4222 | 2570 | } |
617daa0e | 2571 | |
1c0159e0 CV |
2572 | if (!cache->uses_fp) |
2573 | { | |
2574 | /* We didn't find a valid frame, which means that CACHE->base | |
2575 | currently holds the frame pointer for our calling frame. If | |
2576 | we're at the start of a function, or somewhere half-way its | |
2577 | prologue, the function's frame probably hasn't been fully | |
2578 | setup yet. Try to reconstruct the base address for the stack | |
2579 | frame by looking at the stack pointer. For truly "frameless" | |
2580 | functions this might work too. */ | |
94afd7a6 | 2581 | cache->base = get_frame_register_unsigned |
e17a4113 | 2582 | (this_frame, gdbarch_sp_regnum (gdbarch)); |
1c0159e0 CV |
2583 | } |
2584 | ||
2585 | /* Now that we have the base address for the stack frame we can | |
2586 | calculate the value of sp in the calling frame. */ | |
2587 | cache->saved_sp = cache->base + cache->sp_offset; | |
2588 | ||
2589 | /* Adjust all the saved registers such that they contain addresses | |
2590 | instead of offsets. */ | |
2591 | for (i = 0; i < SH_NUM_REGS; i++) | |
2592 | if (cache->saved_regs[i] != -1) | |
2593 | cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i] - 4; | |
2594 | ||
2595 | return cache; | |
2596 | } | |
2597 | ||
94afd7a6 UW |
2598 | static struct value * |
2599 | sh_frame_prev_register (struct frame_info *this_frame, | |
2600 | void **this_cache, int regnum) | |
1c0159e0 | 2601 | { |
94afd7a6 UW |
2602 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
2603 | struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache); | |
1c0159e0 CV |
2604 | |
2605 | gdb_assert (regnum >= 0); | |
2606 | ||
b47193f7 | 2607 | if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp) |
94afd7a6 | 2608 | return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp); |
1c0159e0 CV |
2609 | |
2610 | /* The PC of the previous frame is stored in the PR register of | |
2611 | the current frame. Frob regnum so that we pull the value from | |
2612 | the correct place. */ | |
b47193f7 | 2613 | if (regnum == gdbarch_pc_regnum (gdbarch)) |
1c0159e0 CV |
2614 | regnum = PR_REGNUM; |
2615 | ||
2616 | if (regnum < SH_NUM_REGS && cache->saved_regs[regnum] != -1) | |
94afd7a6 UW |
2617 | return frame_unwind_got_memory (this_frame, regnum, |
2618 | cache->saved_regs[regnum]); | |
1c0159e0 | 2619 | |
94afd7a6 | 2620 | return frame_unwind_got_register (this_frame, regnum, regnum); |
1c0159e0 CV |
2621 | } |
2622 | ||
2623 | static void | |
94afd7a6 | 2624 | sh_frame_this_id (struct frame_info *this_frame, void **this_cache, |
617daa0e CV |
2625 | struct frame_id *this_id) |
2626 | { | |
94afd7a6 | 2627 | struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache); |
1c0159e0 CV |
2628 | |
2629 | /* This marks the outermost frame. */ | |
2630 | if (cache->base == 0) | |
2631 | return; | |
2632 | ||
2633 | *this_id = frame_id_build (cache->saved_sp, cache->pc); | |
617daa0e | 2634 | } |
1c0159e0 | 2635 | |
617daa0e | 2636 | static const struct frame_unwind sh_frame_unwind = { |
1c0159e0 | 2637 | NORMAL_FRAME, |
8fbca658 | 2638 | default_frame_unwind_stop_reason, |
1c0159e0 | 2639 | sh_frame_this_id, |
94afd7a6 UW |
2640 | sh_frame_prev_register, |
2641 | NULL, | |
2642 | default_frame_sniffer | |
1c0159e0 CV |
2643 | }; |
2644 | ||
1c0159e0 CV |
2645 | static CORE_ADDR |
2646 | sh_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
2647 | { | |
3e8c568d | 2648 | return frame_unwind_register_unsigned (next_frame, |
b47193f7 | 2649 | gdbarch_sp_regnum (gdbarch)); |
1c0159e0 CV |
2650 | } |
2651 | ||
2652 | static CORE_ADDR | |
2653 | sh_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
2654 | { | |
3e8c568d | 2655 | return frame_unwind_register_unsigned (next_frame, |
b47193f7 | 2656 | gdbarch_pc_regnum (gdbarch)); |
1c0159e0 CV |
2657 | } |
2658 | ||
2659 | static struct frame_id | |
94afd7a6 | 2660 | sh_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
1c0159e0 | 2661 | { |
94afd7a6 UW |
2662 | CORE_ADDR sp = get_frame_register_unsigned (this_frame, |
2663 | gdbarch_sp_regnum (gdbarch)); | |
2664 | return frame_id_build (sp, get_frame_pc (this_frame)); | |
1c0159e0 CV |
2665 | } |
2666 | ||
2667 | static CORE_ADDR | |
94afd7a6 | 2668 | sh_frame_base_address (struct frame_info *this_frame, void **this_cache) |
617daa0e | 2669 | { |
94afd7a6 | 2670 | struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache); |
617daa0e | 2671 | |
1c0159e0 CV |
2672 | return cache->base; |
2673 | } | |
617daa0e CV |
2674 | |
2675 | static const struct frame_base sh_frame_base = { | |
1c0159e0 CV |
2676 | &sh_frame_unwind, |
2677 | sh_frame_base_address, | |
2678 | sh_frame_base_address, | |
2679 | sh_frame_base_address | |
617daa0e | 2680 | }; |
1c0159e0 CV |
2681 | |
2682 | /* The epilogue is defined here as the area at the end of a function, | |
2683 | either on the `ret' instruction itself or after an instruction which | |
c378eb4e | 2684 | destroys the function's stack frame. */ |
1c0159e0 CV |
2685 | static int |
2686 | sh_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
2687 | { | |
e17a4113 | 2688 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1c0159e0 CV |
2689 | CORE_ADDR func_addr = 0, func_end = 0; |
2690 | ||
2691 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
2692 | { | |
2693 | ULONGEST inst; | |
2694 | /* The sh epilogue is max. 14 bytes long. Give another 14 bytes | |
2695 | for a nop and some fixed data (e.g. big offsets) which are | |
617daa0e | 2696 | unfortunately also treated as part of the function (which |
c378eb4e | 2697 | means, they are below func_end. */ |
1c0159e0 CV |
2698 | CORE_ADDR addr = func_end - 28; |
2699 | if (addr < func_addr + 4) | |
617daa0e | 2700 | addr = func_addr + 4; |
1c0159e0 CV |
2701 | if (pc < addr) |
2702 | return 0; | |
2703 | ||
c378eb4e | 2704 | /* First search forward until hitting an rts. */ |
1c0159e0 | 2705 | while (addr < func_end |
e17a4113 | 2706 | && !IS_RTS (read_memory_unsigned_integer (addr, 2, byte_order))) |
1c0159e0 CV |
2707 | addr += 2; |
2708 | if (addr >= func_end) | |
617daa0e | 2709 | return 0; |
1c0159e0 CV |
2710 | |
2711 | /* At this point we should find a mov.l @r15+,r14 instruction, | |
2712 | either before or after the rts. If not, then the function has | |
c378eb4e | 2713 | probably no "normal" epilogue and we bail out here. */ |
e17a4113 UW |
2714 | inst = read_memory_unsigned_integer (addr - 2, 2, byte_order); |
2715 | if (IS_RESTORE_FP (read_memory_unsigned_integer (addr - 2, 2, | |
2716 | byte_order))) | |
617daa0e | 2717 | addr -= 2; |
e17a4113 UW |
2718 | else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr + 2, 2, |
2719 | byte_order))) | |
1c0159e0 CV |
2720 | return 0; |
2721 | ||
e17a4113 | 2722 | inst = read_memory_unsigned_integer (addr - 2, 2, byte_order); |
03131d99 | 2723 | |
c378eb4e | 2724 | /* Step over possible lds.l @r15+,macl. */ |
03131d99 CV |
2725 | if (IS_MACL_LDS (inst)) |
2726 | { | |
2727 | addr -= 2; | |
e17a4113 | 2728 | inst = read_memory_unsigned_integer (addr - 2, 2, byte_order); |
03131d99 CV |
2729 | } |
2730 | ||
c378eb4e | 2731 | /* Step over possible lds.l @r15+,pr. */ |
1c0159e0 | 2732 | if (IS_LDS (inst)) |
617daa0e | 2733 | { |
1c0159e0 | 2734 | addr -= 2; |
e17a4113 | 2735 | inst = read_memory_unsigned_integer (addr - 2, 2, byte_order); |
1c0159e0 CV |
2736 | } |
2737 | ||
c378eb4e | 2738 | /* Step over possible mov r14,r15. */ |
1c0159e0 | 2739 | if (IS_MOV_FP_SP (inst)) |
617daa0e | 2740 | { |
1c0159e0 | 2741 | addr -= 2; |
e17a4113 | 2742 | inst = read_memory_unsigned_integer (addr - 2, 2, byte_order); |
1c0159e0 CV |
2743 | } |
2744 | ||
2745 | /* Now check for FP adjustments, using add #imm,r14 or add rX, r14 | |
c378eb4e | 2746 | instructions. */ |
1c0159e0 | 2747 | while (addr > func_addr + 4 |
617daa0e | 2748 | && (IS_ADD_REG_TO_FP (inst) || IS_ADD_IMM_FP (inst))) |
1c0159e0 CV |
2749 | { |
2750 | addr -= 2; | |
e17a4113 | 2751 | inst = read_memory_unsigned_integer (addr - 2, 2, byte_order); |
1c0159e0 CV |
2752 | } |
2753 | ||
03131d99 CV |
2754 | /* On SH2a check if the previous instruction was perhaps a MOVI20. |
2755 | That's allowed for the epilogue. */ | |
2756 | if ((gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a | |
2757 | || gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a_nofpu) | |
2758 | && addr > func_addr + 6 | |
e17a4113 UW |
2759 | && IS_MOVI20 (read_memory_unsigned_integer (addr - 4, 2, |
2760 | byte_order))) | |
03131d99 CV |
2761 | addr -= 4; |
2762 | ||
1c0159e0 CV |
2763 | if (pc >= addr) |
2764 | return 1; | |
2765 | } | |
2766 | return 0; | |
2767 | } | |
c9ac0a72 AS |
2768 | |
2769 | ||
2770 | /* Supply register REGNUM from the buffer specified by REGS and LEN | |
2771 | in the register set REGSET to register cache REGCACHE. | |
2772 | REGTABLE specifies where each register can be found in REGS. | |
2773 | If REGNUM is -1, do this for all registers in REGSET. */ | |
2774 | ||
2775 | void | |
2776 | sh_corefile_supply_regset (const struct regset *regset, | |
2777 | struct regcache *regcache, | |
2778 | int regnum, const void *regs, size_t len) | |
2779 | { | |
2780 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
2781 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2782 | const struct sh_corefile_regmap *regmap = (regset == &sh_corefile_gregset | |
2783 | ? tdep->core_gregmap | |
2784 | : tdep->core_fpregmap); | |
2785 | int i; | |
2786 | ||
2787 | for (i = 0; regmap[i].regnum != -1; i++) | |
2788 | { | |
2789 | if ((regnum == -1 || regnum == regmap[i].regnum) | |
2790 | && regmap[i].offset + 4 <= len) | |
2791 | regcache_raw_supply (regcache, regmap[i].regnum, | |
2792 | (char *)regs + regmap[i].offset); | |
2793 | } | |
2794 | } | |
2795 | ||
2796 | /* Collect register REGNUM in the register set REGSET from register cache | |
2797 | REGCACHE into the buffer specified by REGS and LEN. | |
2798 | REGTABLE specifies where each register can be found in REGS. | |
2799 | If REGNUM is -1, do this for all registers in REGSET. */ | |
2800 | ||
2801 | void | |
2802 | sh_corefile_collect_regset (const struct regset *regset, | |
2803 | const struct regcache *regcache, | |
2804 | int regnum, void *regs, size_t len) | |
2805 | { | |
2806 | struct gdbarch *gdbarch = get_regcache_arch (regcache); | |
2807 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2808 | const struct sh_corefile_regmap *regmap = (regset == &sh_corefile_gregset | |
2809 | ? tdep->core_gregmap | |
2810 | : tdep->core_fpregmap); | |
2811 | int i; | |
2812 | ||
2813 | for (i = 0; regmap[i].regnum != -1; i++) | |
2814 | { | |
2815 | if ((regnum == -1 || regnum == regmap[i].regnum) | |
2816 | && regmap[i].offset + 4 <= len) | |
2817 | regcache_raw_collect (regcache, regmap[i].regnum, | |
2818 | (char *)regs + regmap[i].offset); | |
2819 | } | |
2820 | } | |
2821 | ||
2822 | /* The following two regsets have the same contents, so it is tempting to | |
2823 | unify them, but they are distiguished by their address, so don't. */ | |
2824 | ||
2825 | struct regset sh_corefile_gregset = | |
2826 | { | |
2827 | NULL, | |
2828 | sh_corefile_supply_regset, | |
2829 | sh_corefile_collect_regset | |
2830 | }; | |
2831 | ||
2832 | static struct regset sh_corefile_fpregset = | |
2833 | { | |
2834 | NULL, | |
2835 | sh_corefile_supply_regset, | |
2836 | sh_corefile_collect_regset | |
2837 | }; | |
2838 | ||
2839 | static const struct regset * | |
2840 | sh_regset_from_core_section (struct gdbarch *gdbarch, const char *sect_name, | |
2841 | size_t sect_size) | |
2842 | { | |
2843 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2844 | ||
2845 | if (tdep->core_gregmap && strcmp (sect_name, ".reg") == 0) | |
2846 | return &sh_corefile_gregset; | |
2847 | ||
2848 | if (tdep->core_fpregmap && strcmp (sect_name, ".reg2") == 0) | |
2849 | return &sh_corefile_fpregset; | |
2850 | ||
2851 | return NULL; | |
2852 | } | |
ccf00f21 | 2853 | \f |
cc17453a EZ |
2854 | |
2855 | static struct gdbarch * | |
fba45db2 | 2856 | sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
cc17453a | 2857 | { |
cc17453a | 2858 | struct gdbarch *gdbarch; |
c9ac0a72 | 2859 | struct gdbarch_tdep *tdep; |
d658f924 | 2860 | |
55ff77ac CV |
2861 | sh_show_regs = sh_generic_show_regs; |
2862 | switch (info.bfd_arch_info->mach) | |
2863 | { | |
617daa0e CV |
2864 | case bfd_mach_sh2e: |
2865 | sh_show_regs = sh2e_show_regs; | |
2866 | break; | |
da962468 CV |
2867 | case bfd_mach_sh2a: |
2868 | sh_show_regs = sh2a_show_regs; | |
2869 | break; | |
2870 | case bfd_mach_sh2a_nofpu: | |
2871 | sh_show_regs = sh2a_nofpu_show_regs; | |
2872 | break; | |
617daa0e CV |
2873 | case bfd_mach_sh_dsp: |
2874 | sh_show_regs = sh_dsp_show_regs; | |
2875 | break; | |
55ff77ac | 2876 | |
617daa0e | 2877 | case bfd_mach_sh3: |
46e8a76b AS |
2878 | case bfd_mach_sh3_nommu: |
2879 | case bfd_mach_sh2a_nofpu_or_sh3_nommu: | |
617daa0e CV |
2880 | sh_show_regs = sh3_show_regs; |
2881 | break; | |
55ff77ac | 2882 | |
617daa0e | 2883 | case bfd_mach_sh3e: |
46e8a76b | 2884 | case bfd_mach_sh2a_or_sh3e: |
617daa0e CV |
2885 | sh_show_regs = sh3e_show_regs; |
2886 | break; | |
55ff77ac | 2887 | |
617daa0e | 2888 | case bfd_mach_sh3_dsp: |
474e5826 | 2889 | case bfd_mach_sh4al_dsp: |
617daa0e CV |
2890 | sh_show_regs = sh3_dsp_show_regs; |
2891 | break; | |
55ff77ac | 2892 | |
617daa0e | 2893 | case bfd_mach_sh4: |
474e5826 | 2894 | case bfd_mach_sh4a: |
46e8a76b | 2895 | case bfd_mach_sh2a_or_sh4: |
617daa0e CV |
2896 | sh_show_regs = sh4_show_regs; |
2897 | break; | |
55ff77ac | 2898 | |
474e5826 | 2899 | case bfd_mach_sh4_nofpu: |
46e8a76b | 2900 | case bfd_mach_sh4_nommu_nofpu: |
474e5826 | 2901 | case bfd_mach_sh4a_nofpu: |
46e8a76b | 2902 | case bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu: |
474e5826 CV |
2903 | sh_show_regs = sh4_nofpu_show_regs; |
2904 | break; | |
2905 | ||
617daa0e CV |
2906 | case bfd_mach_sh5: |
2907 | sh_show_regs = sh64_show_regs; | |
c378eb4e | 2908 | /* SH5 is handled entirely in sh64-tdep.c. */ |
617daa0e | 2909 | return sh64_gdbarch_init (info, arches); |
55ff77ac CV |
2910 | } |
2911 | ||
4be87837 DJ |
2912 | /* If there is already a candidate, use it. */ |
2913 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
2914 | if (arches != NULL) | |
2915 | return arches->gdbarch; | |
cc17453a EZ |
2916 | |
2917 | /* None found, create a new architecture from the information | |
c378eb4e | 2918 | provided. */ |
c9ac0a72 AS |
2919 | tdep = XZALLOC (struct gdbarch_tdep); |
2920 | gdbarch = gdbarch_alloc (&info, tdep); | |
cc17453a | 2921 | |
48db5a3c CV |
2922 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); |
2923 | set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
ec920329 | 2924 | set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
48db5a3c CV |
2925 | set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); |
2926 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
2927 | set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
2928 | set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
a38d2a54 | 2929 | set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
48db5a3c | 2930 | |
f2ea0907 | 2931 | set_gdbarch_num_regs (gdbarch, SH_NUM_REGS); |
a38d2a54 | 2932 | set_gdbarch_sp_regnum (gdbarch, 15); |
a38d2a54 | 2933 | set_gdbarch_pc_regnum (gdbarch, 16); |
48db5a3c CV |
2934 | set_gdbarch_fp0_regnum (gdbarch, -1); |
2935 | set_gdbarch_num_pseudo_regs (gdbarch, 0); | |
2936 | ||
1c0159e0 | 2937 | set_gdbarch_register_type (gdbarch, sh_default_register_type); |
dda63807 | 2938 | set_gdbarch_register_reggroup_p (gdbarch, sh_register_reggroup_p); |
1c0159e0 | 2939 | |
eaf90c5d | 2940 | set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc); |
48db5a3c | 2941 | |
9dae60cc | 2942 | set_gdbarch_print_insn (gdbarch, print_insn_sh); |
2f14585c | 2943 | set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno); |
48db5a3c | 2944 | |
c0409442 | 2945 | set_gdbarch_return_value (gdbarch, sh_return_value_nofpu); |
1c0159e0 | 2946 | |
48db5a3c CV |
2947 | set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue); |
2948 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
48db5a3c | 2949 | |
1c0159e0 CV |
2950 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu); |
2951 | ||
48db5a3c CV |
2952 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); |
2953 | ||
19f59343 | 2954 | set_gdbarch_frame_align (gdbarch, sh_frame_align); |
1c0159e0 CV |
2955 | set_gdbarch_unwind_sp (gdbarch, sh_unwind_sp); |
2956 | set_gdbarch_unwind_pc (gdbarch, sh_unwind_pc); | |
94afd7a6 | 2957 | set_gdbarch_dummy_id (gdbarch, sh_dummy_id); |
1c0159e0 CV |
2958 | frame_base_set_default (gdbarch, &sh_frame_base); |
2959 | ||
617daa0e | 2960 | set_gdbarch_in_function_epilogue_p (gdbarch, sh_in_function_epilogue_p); |
cc17453a | 2961 | |
357d3800 AS |
2962 | dwarf2_frame_set_init_reg (gdbarch, sh_dwarf2_frame_init_reg); |
2963 | ||
c9ac0a72 AS |
2964 | set_gdbarch_regset_from_core_section (gdbarch, sh_regset_from_core_section); |
2965 | ||
cc17453a | 2966 | switch (info.bfd_arch_info->mach) |
8db62801 | 2967 | { |
cc17453a | 2968 | case bfd_mach_sh: |
48db5a3c | 2969 | set_gdbarch_register_name (gdbarch, sh_sh_register_name); |
cc17453a | 2970 | break; |
1c0159e0 | 2971 | |
cc17453a | 2972 | case bfd_mach_sh2: |
48db5a3c | 2973 | set_gdbarch_register_name (gdbarch, sh_sh_register_name); |
617daa0e | 2974 | break; |
1c0159e0 | 2975 | |
2d188dd3 | 2976 | case bfd_mach_sh2e: |
c378eb4e | 2977 | /* doubles on sh2e and sh3e are actually 4 byte. */ |
48db5a3c CV |
2978 | set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
2979 | ||
2980 | set_gdbarch_register_name (gdbarch, sh_sh2e_register_name); | |
48db5a3c | 2981 | set_gdbarch_register_type (gdbarch, sh_sh3e_register_type); |
2d188dd3 | 2982 | set_gdbarch_fp0_regnum (gdbarch, 25); |
c0409442 | 2983 | set_gdbarch_return_value (gdbarch, sh_return_value_fpu); |
6df2bf50 | 2984 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); |
2d188dd3 | 2985 | break; |
1c0159e0 | 2986 | |
da962468 CV |
2987 | case bfd_mach_sh2a: |
2988 | set_gdbarch_register_name (gdbarch, sh_sh2a_register_name); | |
2989 | set_gdbarch_register_type (gdbarch, sh_sh2a_register_type); | |
2990 | set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno); | |
2991 | ||
2992 | set_gdbarch_fp0_regnum (gdbarch, 25); | |
2993 | set_gdbarch_num_pseudo_regs (gdbarch, 9); | |
2994 | set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read); | |
2995 | set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write); | |
c0409442 | 2996 | set_gdbarch_return_value (gdbarch, sh_return_value_fpu); |
da962468 CV |
2997 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); |
2998 | break; | |
2999 | ||
3000 | case bfd_mach_sh2a_nofpu: | |
3001 | set_gdbarch_register_name (gdbarch, sh_sh2a_nofpu_register_name); | |
3002 | set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno); | |
3003 | ||
3004 | set_gdbarch_num_pseudo_regs (gdbarch, 1); | |
3005 | set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read); | |
3006 | set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write); | |
3007 | break; | |
3008 | ||
cc17453a | 3009 | case bfd_mach_sh_dsp: |
48db5a3c | 3010 | set_gdbarch_register_name (gdbarch, sh_sh_dsp_register_name); |
2f14585c | 3011 | set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno); |
cc17453a | 3012 | break; |
1c0159e0 | 3013 | |
cc17453a | 3014 | case bfd_mach_sh3: |
4e6cbc38 AS |
3015 | case bfd_mach_sh3_nommu: |
3016 | case bfd_mach_sh2a_nofpu_or_sh3_nommu: | |
48db5a3c | 3017 | set_gdbarch_register_name (gdbarch, sh_sh3_register_name); |
cc17453a | 3018 | break; |
1c0159e0 | 3019 | |
cc17453a | 3020 | case bfd_mach_sh3e: |
4e6cbc38 | 3021 | case bfd_mach_sh2a_or_sh3e: |
c378eb4e | 3022 | /* doubles on sh2e and sh3e are actually 4 byte. */ |
48db5a3c CV |
3023 | set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
3024 | ||
3025 | set_gdbarch_register_name (gdbarch, sh_sh3e_register_name); | |
48db5a3c | 3026 | set_gdbarch_register_type (gdbarch, sh_sh3e_register_type); |
cc17453a | 3027 | set_gdbarch_fp0_regnum (gdbarch, 25); |
c0409442 | 3028 | set_gdbarch_return_value (gdbarch, sh_return_value_fpu); |
6df2bf50 | 3029 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); |
cc17453a | 3030 | break; |
1c0159e0 | 3031 | |
cc17453a | 3032 | case bfd_mach_sh3_dsp: |
48db5a3c | 3033 | set_gdbarch_register_name (gdbarch, sh_sh3_dsp_register_name); |
48db5a3c | 3034 | set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno); |
cc17453a | 3035 | break; |
1c0159e0 | 3036 | |
cc17453a | 3037 | case bfd_mach_sh4: |
474e5826 | 3038 | case bfd_mach_sh4a: |
46e8a76b | 3039 | case bfd_mach_sh2a_or_sh4: |
48db5a3c | 3040 | set_gdbarch_register_name (gdbarch, sh_sh4_register_name); |
48db5a3c | 3041 | set_gdbarch_register_type (gdbarch, sh_sh4_register_type); |
cc17453a | 3042 | set_gdbarch_fp0_regnum (gdbarch, 25); |
da962468 | 3043 | set_gdbarch_num_pseudo_regs (gdbarch, 13); |
d8124050 AC |
3044 | set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read); |
3045 | set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write); | |
c0409442 | 3046 | set_gdbarch_return_value (gdbarch, sh_return_value_fpu); |
6df2bf50 | 3047 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); |
cc17453a | 3048 | break; |
1c0159e0 | 3049 | |
474e5826 CV |
3050 | case bfd_mach_sh4_nofpu: |
3051 | case bfd_mach_sh4a_nofpu: | |
4e6cbc38 AS |
3052 | case bfd_mach_sh4_nommu_nofpu: |
3053 | case bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu: | |
474e5826 CV |
3054 | set_gdbarch_register_name (gdbarch, sh_sh4_nofpu_register_name); |
3055 | break; | |
3056 | ||
3057 | case bfd_mach_sh4al_dsp: | |
3058 | set_gdbarch_register_name (gdbarch, sh_sh4al_dsp_register_name); | |
3059 | set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno); | |
3060 | break; | |
3061 | ||
cc17453a | 3062 | default: |
b58cbbf2 | 3063 | set_gdbarch_register_name (gdbarch, sh_sh_register_name); |
cc17453a | 3064 | break; |
8db62801 | 3065 | } |
cc17453a | 3066 | |
4be87837 DJ |
3067 | /* Hook in ABI-specific overrides, if they have been registered. */ |
3068 | gdbarch_init_osabi (info, gdbarch); | |
d658f924 | 3069 | |
94afd7a6 UW |
3070 | dwarf2_append_unwinders (gdbarch); |
3071 | frame_unwind_append_unwinder (gdbarch, &sh_frame_unwind); | |
1c0159e0 | 3072 | |
cc17453a | 3073 | return gdbarch; |
8db62801 EZ |
3074 | } |
3075 | ||
c055b101 CV |
3076 | static void |
3077 | show_sh_command (char *args, int from_tty) | |
3078 | { | |
3079 | help_list (showshcmdlist, "show sh ", all_commands, gdb_stdout); | |
3080 | } | |
3081 | ||
3082 | static void | |
3083 | set_sh_command (char *args, int from_tty) | |
3084 | { | |
3085 | printf_unfiltered | |
3086 | ("\"set sh\" must be followed by an appropriate subcommand.\n"); | |
3087 | help_list (setshcmdlist, "set sh ", all_commands, gdb_stdout); | |
3088 | } | |
3089 | ||
c378eb4e | 3090 | extern initialize_file_ftype _initialize_sh_tdep; /* -Wmissing-prototypes */ |
a78f21af | 3091 | |
c906108c | 3092 | void |
fba45db2 | 3093 | _initialize_sh_tdep (void) |
c906108c SS |
3094 | { |
3095 | struct cmd_list_element *c; | |
617daa0e | 3096 | |
f2ea0907 | 3097 | gdbarch_register (bfd_arch_sh, sh_gdbarch_init, NULL); |
c906108c | 3098 | |
1bedd215 | 3099 | add_com ("regs", class_vars, sh_show_regs_command, _("Print all registers")); |
c055b101 CV |
3100 | |
3101 | add_prefix_cmd ("sh", no_class, set_sh_command, "SH specific commands.", | |
3102 | &setshcmdlist, "set sh ", 0, &setlist); | |
3103 | add_prefix_cmd ("sh", no_class, show_sh_command, "SH specific commands.", | |
3104 | &showshcmdlist, "show sh ", 0, &showlist); | |
3105 | ||
3106 | add_setshow_enum_cmd ("calling-convention", class_vars, sh_cc_enum, | |
3107 | &sh_active_calling_convention, | |
3108 | _("Set calling convention used when calling target " | |
3109 | "functions from GDB."), | |
3110 | _("Show calling convention used when calling target " | |
3111 | "functions from GDB."), | |
3112 | _("gcc - Use GCC calling convention (default).\n" | |
3113 | "renesas - Enforce Renesas calling convention."), | |
3114 | NULL, NULL, | |
3115 | &setshcmdlist, &showshcmdlist); | |
c906108c | 3116 | } |