Commit | Line | Data |
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85a453d5 | 1 | /* Target-dependent code for Renesas Super-H, for GDB. |
9ab9195f EZ |
2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
3 | 2003, 2004 Free Software Foundation, Inc. | |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b JM |
17 | You should have received a copy of the GNU General Public License |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
21 | |
22 | /* | |
c5aa993b JM |
23 | Contributed by Steve Chamberlain |
24 | sac@cygnus.com | |
c906108c SS |
25 | */ |
26 | ||
27 | #include "defs.h" | |
28 | #include "frame.h" | |
1c0159e0 CV |
29 | #include "frame-base.h" |
30 | #include "frame-unwind.h" | |
31 | #include "dwarf2-frame.h" | |
c906108c | 32 | #include "symtab.h" |
c906108c SS |
33 | #include "gdbtypes.h" |
34 | #include "gdbcmd.h" | |
35 | #include "gdbcore.h" | |
36 | #include "value.h" | |
37 | #include "dis-asm.h" | |
73c1f219 | 38 | #include "inferior.h" |
c906108c | 39 | #include "gdb_string.h" |
1c0159e0 | 40 | #include "gdb_assert.h" |
b4a20239 | 41 | #include "arch-utils.h" |
fb409745 | 42 | #include "floatformat.h" |
4e052eda | 43 | #include "regcache.h" |
d16aafd8 | 44 | #include "doublest.h" |
4be87837 | 45 | #include "osabi.h" |
c906108c | 46 | |
ab3b8126 JT |
47 | #include "sh-tdep.h" |
48 | ||
d658f924 | 49 | #include "elf-bfd.h" |
1a8629c7 MS |
50 | #include "solib-svr4.h" |
51 | ||
55ff77ac | 52 | /* sh flags */ |
283150cd EZ |
53 | #include "elf/sh.h" |
54 | /* registers numbers shared with the simulator */ | |
1c922164 | 55 | #include "gdb/sim-sh.h" |
283150cd | 56 | |
55ff77ac | 57 | static void (*sh_show_regs) (void); |
cc17453a | 58 | |
da962468 | 59 | #define SH_NUM_REGS 67 |
88e04cc1 | 60 | |
1c0159e0 | 61 | struct sh_frame_cache |
cc17453a | 62 | { |
1c0159e0 CV |
63 | /* Base address. */ |
64 | CORE_ADDR base; | |
65 | LONGEST sp_offset; | |
66 | CORE_ADDR pc; | |
67 | ||
68 | /* Flag showing that a frame has been created in the prologue code. */ | |
69 | int uses_fp; | |
70 | ||
71 | /* Saved registers. */ | |
72 | CORE_ADDR saved_regs[SH_NUM_REGS]; | |
73 | CORE_ADDR saved_sp; | |
63978407 | 74 | }; |
c906108c | 75 | |
fa88f677 | 76 | static const char * |
cc17453a EZ |
77 | sh_sh_register_name (int reg_nr) |
78 | { | |
617daa0e CV |
79 | static char *register_names[] = { |
80 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
81 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
82 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
83 | "", "", | |
84 | "", "", "", "", "", "", "", "", | |
85 | "", "", "", "", "", "", "", "", | |
86 | "", "", | |
87 | "", "", "", "", "", "", "", "", | |
88 | "", "", "", "", "", "", "", "", | |
da962468 | 89 | "", "", "", "", "", "", "", "", |
cc17453a EZ |
90 | }; |
91 | if (reg_nr < 0) | |
92 | return NULL; | |
93 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
94 | return NULL; | |
95 | return register_names[reg_nr]; | |
96 | } | |
97 | ||
fa88f677 | 98 | static const char * |
cc17453a EZ |
99 | sh_sh3_register_name (int reg_nr) |
100 | { | |
617daa0e CV |
101 | static char *register_names[] = { |
102 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
103 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
104 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
105 | "", "", | |
106 | "", "", "", "", "", "", "", "", | |
107 | "", "", "", "", "", "", "", "", | |
108 | "ssr", "spc", | |
cc17453a EZ |
109 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", |
110 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1" | |
da962468 | 111 | "", "", "", "", "", "", "", "", |
cc17453a EZ |
112 | }; |
113 | if (reg_nr < 0) | |
114 | return NULL; | |
115 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
116 | return NULL; | |
117 | return register_names[reg_nr]; | |
118 | } | |
119 | ||
fa88f677 | 120 | static const char * |
cc17453a EZ |
121 | sh_sh3e_register_name (int reg_nr) |
122 | { | |
617daa0e CV |
123 | static char *register_names[] = { |
124 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
125 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
126 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
cc17453a | 127 | "fpul", "fpscr", |
617daa0e CV |
128 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", |
129 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
130 | "ssr", "spc", | |
cc17453a EZ |
131 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", |
132 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", | |
da962468 | 133 | "", "", "", "", "", "", "", "", |
cc17453a EZ |
134 | }; |
135 | if (reg_nr < 0) | |
136 | return NULL; | |
137 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
138 | return NULL; | |
139 | return register_names[reg_nr]; | |
140 | } | |
141 | ||
2d188dd3 NC |
142 | static const char * |
143 | sh_sh2e_register_name (int reg_nr) | |
144 | { | |
617daa0e CV |
145 | static char *register_names[] = { |
146 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
147 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
148 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
2d188dd3 | 149 | "fpul", "fpscr", |
617daa0e CV |
150 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", |
151 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
152 | "", "", | |
2d188dd3 NC |
153 | "", "", "", "", "", "", "", "", |
154 | "", "", "", "", "", "", "", "", | |
da962468 CV |
155 | "", "", "", "", "", "", "", "", |
156 | }; | |
157 | if (reg_nr < 0) | |
158 | return NULL; | |
159 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
160 | return NULL; | |
161 | return register_names[reg_nr]; | |
162 | } | |
163 | ||
164 | static const char * | |
165 | sh_sh2a_register_name (int reg_nr) | |
166 | { | |
167 | static char *register_names[] = { | |
168 | /* general registers 0-15 */ | |
169 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
170 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
171 | /* 16 - 22 */ | |
172 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
173 | /* 23, 24 */ | |
174 | "fpul", "fpscr", | |
175 | /* floating point registers 25 - 40 */ | |
176 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", | |
177 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
178 | /* 41, 42 */ | |
179 | "", "", | |
180 | /* 43 - 62. Banked registers. The bank number used is determined by | |
181 | the bank register (63). */ | |
182 | "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b", | |
183 | "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", | |
184 | "machb", "ivnb", "prb", "gbrb", "maclb", | |
185 | /* 63: register bank number, not a real register but used to | |
186 | communicate the register bank currently get/set. This register | |
187 | is hidden to the user, who manipulates it using the pseudo | |
188 | register called "bank" (67). See below. */ | |
189 | "", | |
190 | /* 64 - 66 */ | |
191 | "ibcr", "ibnr", "tbr", | |
192 | /* 67: register bank number, the user visible pseudo register. */ | |
193 | "bank", | |
194 | /* double precision (pseudo) 68 - 75 */ | |
195 | "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", | |
196 | }; | |
197 | if (reg_nr < 0) | |
198 | return NULL; | |
199 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
200 | return NULL; | |
201 | return register_names[reg_nr]; | |
202 | } | |
203 | ||
204 | static const char * | |
205 | sh_sh2a_nofpu_register_name (int reg_nr) | |
206 | { | |
207 | static char *register_names[] = { | |
208 | /* general registers 0-15 */ | |
209 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
210 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
211 | /* 16 - 22 */ | |
212 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
213 | /* 23, 24 */ | |
214 | "", "", | |
215 | /* floating point registers 25 - 40 */ | |
216 | "", "", "", "", "", "", "", "", | |
217 | "", "", "", "", "", "", "", "", | |
218 | /* 41, 42 */ | |
219 | "", "", | |
220 | /* 43 - 62. Banked registers. The bank number used is determined by | |
221 | the bank register (63). */ | |
222 | "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b", | |
223 | "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", | |
224 | "machb", "ivnb", "prb", "gbrb", "maclb", | |
225 | /* 63: register bank number, not a real register but used to | |
226 | communicate the register bank currently get/set. This register | |
227 | is hidden to the user, who manipulates it using the pseudo | |
228 | register called "bank" (67). See below. */ | |
229 | "", | |
230 | /* 64 - 66 */ | |
231 | "ibcr", "ibnr", "tbr", | |
232 | /* 67: register bank number, the user visible pseudo register. */ | |
233 | "bank", | |
234 | /* double precision (pseudo) 68 - 75 */ | |
235 | "", "", "", "", "", "", "", "", | |
2d188dd3 NC |
236 | }; |
237 | if (reg_nr < 0) | |
238 | return NULL; | |
239 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
240 | return NULL; | |
241 | return register_names[reg_nr]; | |
242 | } | |
243 | ||
fa88f677 | 244 | static const char * |
cc17453a EZ |
245 | sh_sh_dsp_register_name (int reg_nr) |
246 | { | |
617daa0e CV |
247 | static char *register_names[] = { |
248 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
249 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
250 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
251 | "", "dsr", | |
252 | "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1", | |
253 | "y0", "y1", "", "", "", "", "", "mod", | |
254 | "", "", | |
255 | "rs", "re", "", "", "", "", "", "", | |
256 | "", "", "", "", "", "", "", "", | |
da962468 | 257 | "", "", "", "", "", "", "", "", |
cc17453a EZ |
258 | }; |
259 | if (reg_nr < 0) | |
260 | return NULL; | |
261 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
262 | return NULL; | |
263 | return register_names[reg_nr]; | |
264 | } | |
265 | ||
fa88f677 | 266 | static const char * |
cc17453a EZ |
267 | sh_sh3_dsp_register_name (int reg_nr) |
268 | { | |
617daa0e CV |
269 | static char *register_names[] = { |
270 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
271 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
272 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
273 | "", "dsr", | |
274 | "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1", | |
275 | "y0", "y1", "", "", "", "", "", "mod", | |
276 | "ssr", "spc", | |
277 | "rs", "re", "", "", "", "", "", "", | |
026a72f8 CV |
278 | "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b", |
279 | "", "", "", "", "", "", "", "", | |
da962468 | 280 | "", "", "", "", "", "", "", "", |
cc17453a EZ |
281 | }; |
282 | if (reg_nr < 0) | |
283 | return NULL; | |
284 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
285 | return NULL; | |
286 | return register_names[reg_nr]; | |
287 | } | |
288 | ||
fa88f677 | 289 | static const char * |
53116e27 EZ |
290 | sh_sh4_register_name (int reg_nr) |
291 | { | |
617daa0e | 292 | static char *register_names[] = { |
a38d2a54 | 293 | /* general registers 0-15 */ |
617daa0e CV |
294 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
295 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
a38d2a54 | 296 | /* 16 - 22 */ |
617daa0e | 297 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", |
a38d2a54 | 298 | /* 23, 24 */ |
53116e27 | 299 | "fpul", "fpscr", |
a38d2a54 | 300 | /* floating point registers 25 - 40 */ |
617daa0e CV |
301 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", |
302 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
a38d2a54 | 303 | /* 41, 42 */ |
617daa0e | 304 | "ssr", "spc", |
a38d2a54 | 305 | /* bank 0 43 - 50 */ |
53116e27 | 306 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", |
a38d2a54 | 307 | /* bank 1 51 - 58 */ |
53116e27 | 308 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", |
da962468 CV |
309 | "", "", "", "", "", "", "", "", |
310 | /* pseudo bank register. */ | |
311 | "", | |
a38d2a54 | 312 | /* double precision (pseudo) 59 - 66 */ |
617daa0e | 313 | "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", |
a38d2a54 | 314 | /* vectors (pseudo) 67 - 70 */ |
617daa0e | 315 | "fv0", "fv4", "fv8", "fv12", |
a38d2a54 EZ |
316 | /* FIXME: missing XF 71 - 86 */ |
317 | /* FIXME: missing XD 87 - 94 */ | |
53116e27 EZ |
318 | }; |
319 | if (reg_nr < 0) | |
320 | return NULL; | |
321 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
322 | return NULL; | |
323 | return register_names[reg_nr]; | |
324 | } | |
325 | ||
474e5826 CV |
326 | static const char * |
327 | sh_sh4_nofpu_register_name (int reg_nr) | |
328 | { | |
329 | static char *register_names[] = { | |
330 | /* general registers 0-15 */ | |
331 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
332 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
333 | /* 16 - 22 */ | |
334 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
335 | /* 23, 24 */ | |
336 | "", "", | |
337 | /* floating point registers 25 - 40 -- not for nofpu target */ | |
338 | "", "", "", "", "", "", "", "", | |
339 | "", "", "", "", "", "", "", "", | |
340 | /* 41, 42 */ | |
341 | "ssr", "spc", | |
342 | /* bank 0 43 - 50 */ | |
343 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", | |
344 | /* bank 1 51 - 58 */ | |
345 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", | |
da962468 CV |
346 | "", "", "", "", "", "", "", "", |
347 | /* pseudo bank register. */ | |
348 | "", | |
474e5826 CV |
349 | /* double precision (pseudo) 59 - 66 -- not for nofpu target */ |
350 | "", "", "", "", "", "", "", "", | |
351 | /* vectors (pseudo) 67 - 70 -- not for nofpu target */ | |
352 | "", "", "", "", | |
353 | }; | |
354 | if (reg_nr < 0) | |
355 | return NULL; | |
356 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
357 | return NULL; | |
358 | return register_names[reg_nr]; | |
359 | } | |
360 | ||
361 | static const char * | |
362 | sh_sh4al_dsp_register_name (int reg_nr) | |
363 | { | |
364 | static char *register_names[] = { | |
365 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
366 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
367 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
368 | "", "dsr", | |
369 | "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1", | |
370 | "y0", "y1", "", "", "", "", "", "mod", | |
371 | "ssr", "spc", | |
372 | "rs", "re", "", "", "", "", "", "", | |
026a72f8 CV |
373 | "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b", |
374 | "", "", "", "", "", "", "", "", | |
da962468 | 375 | "", "", "", "", "", "", "", "", |
474e5826 CV |
376 | }; |
377 | if (reg_nr < 0) | |
378 | return NULL; | |
379 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
380 | return NULL; | |
381 | return register_names[reg_nr]; | |
382 | } | |
383 | ||
3117ed25 | 384 | static const unsigned char * |
fba45db2 | 385 | sh_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
cc17453a EZ |
386 | { |
387 | /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */ | |
617daa0e CV |
388 | static unsigned char breakpoint[] = { 0xc3, 0xc3 }; |
389 | ||
cc17453a EZ |
390 | *lenptr = sizeof (breakpoint); |
391 | return breakpoint; | |
392 | } | |
c906108c SS |
393 | |
394 | /* Prologue looks like | |
1c0159e0 CV |
395 | mov.l r14,@-r15 |
396 | sts.l pr,@-r15 | |
397 | mov.l <regs>,@-r15 | |
398 | sub <room_for_loca_vars>,r15 | |
399 | mov r15,r14 | |
8db62801 | 400 | |
1c0159e0 | 401 | Actually it can be more complicated than this but that's it, basically. |
c5aa993b | 402 | */ |
c906108c | 403 | |
1c0159e0 CV |
404 | #define GET_SOURCE_REG(x) (((x) >> 4) & 0xf) |
405 | #define GET_TARGET_REG(x) (((x) >> 8) & 0xf) | |
406 | ||
5f883edd FF |
407 | /* JSR @Rm 0100mmmm00001011 */ |
408 | #define IS_JSR(x) (((x) & 0xf0ff) == 0x400b) | |
409 | ||
8db62801 EZ |
410 | /* STS.L PR,@-r15 0100111100100010 |
411 | r15-4-->r15, PR-->(r15) */ | |
c906108c | 412 | #define IS_STS(x) ((x) == 0x4f22) |
8db62801 | 413 | |
03131d99 CV |
414 | /* STS.L MACL,@-r15 0100111100010010 |
415 | r15-4-->r15, MACL-->(r15) */ | |
416 | #define IS_MACL_STS(x) ((x) == 0x4f12) | |
417 | ||
8db62801 EZ |
418 | /* MOV.L Rm,@-r15 00101111mmmm0110 |
419 | r15-4-->r15, Rm-->(R15) */ | |
c906108c | 420 | #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06) |
8db62801 | 421 | |
8db62801 EZ |
422 | /* MOV r15,r14 0110111011110011 |
423 | r15-->r14 */ | |
c906108c | 424 | #define IS_MOV_SP_FP(x) ((x) == 0x6ef3) |
8db62801 EZ |
425 | |
426 | /* ADD #imm,r15 01111111iiiiiiii | |
427 | r15+imm-->r15 */ | |
1c0159e0 | 428 | #define IS_ADD_IMM_SP(x) (((x) & 0xff00) == 0x7f00) |
8db62801 | 429 | |
c906108c SS |
430 | #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00) |
431 | #define IS_SHLL_R3(x) ((x) == 0x4300) | |
8db62801 EZ |
432 | |
433 | /* ADD r3,r15 0011111100111100 | |
434 | r15+r3-->r15 */ | |
c906108c | 435 | #define IS_ADD_R3SP(x) ((x) == 0x3f3c) |
8db62801 EZ |
436 | |
437 | /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011 | |
8db62801 | 438 | FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011 |
8db62801 | 439 | FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */ |
f2ea0907 CV |
440 | /* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to |
441 | make this entirely clear. */ | |
1c0159e0 CV |
442 | /* #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) */ |
443 | #define IS_FPUSH(x) (((x) & 0xff0f) == 0xff0b) | |
444 | ||
445 | /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 4 <= m <= 7 */ | |
446 | #define IS_MOV_ARG_TO_REG(x) \ | |
447 | (((x) & 0xf00f) == 0x6003 && \ | |
448 | ((x) & 0x00f0) >= 0x0040 && \ | |
449 | ((x) & 0x00f0) <= 0x0070) | |
450 | /* MOV.L Rm,@Rn 0010nnnnmmmm0010 n = 14, 4 <= m <= 7 */ | |
451 | #define IS_MOV_ARG_TO_IND_R14(x) \ | |
452 | (((x) & 0xff0f) == 0x2e02 && \ | |
453 | ((x) & 0x00f0) >= 0x0040 && \ | |
454 | ((x) & 0x00f0) <= 0x0070) | |
455 | /* MOV.L Rm,@(disp*4,Rn) 00011110mmmmdddd n = 14, 4 <= m <= 7 */ | |
456 | #define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \ | |
457 | (((x) & 0xff00) == 0x1e00 && \ | |
458 | ((x) & 0x00f0) >= 0x0040 && \ | |
459 | ((x) & 0x00f0) <= 0x0070) | |
460 | ||
461 | /* MOV.W @(disp*2,PC),Rn 1001nnnndddddddd */ | |
462 | #define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000) | |
463 | /* MOV.L @(disp*4,PC),Rn 1101nnnndddddddd */ | |
464 | #define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000) | |
03131d99 CV |
465 | /* MOVI20 #imm20,Rn 0000nnnniiii0000 */ |
466 | #define IS_MOVI20(x) (((x) & 0xf00f) == 0x0000) | |
1c0159e0 CV |
467 | /* SUB Rn,R15 00111111nnnn1000 */ |
468 | #define IS_SUB_REG_FROM_SP(x) (((x) & 0xff0f) == 0x3f08) | |
8db62801 | 469 | |
1c0159e0 | 470 | #define FPSCR_SZ (1 << 20) |
cc17453a | 471 | |
1c0159e0 CV |
472 | /* The following instructions are used for epilogue testing. */ |
473 | #define IS_RESTORE_FP(x) ((x) == 0x6ef6) | |
474 | #define IS_RTS(x) ((x) == 0x000b) | |
475 | #define IS_LDS(x) ((x) == 0x4f26) | |
03131d99 | 476 | #define IS_MACL_LDS(x) ((x) == 0x4f16) |
1c0159e0 CV |
477 | #define IS_MOV_FP_SP(x) ((x) == 0x6fe3) |
478 | #define IS_ADD_REG_TO_FP(x) (((x) & 0xff0f) == 0x3e0c) | |
479 | #define IS_ADD_IMM_FP(x) (((x) & 0xff00) == 0x7e00) | |
cc17453a | 480 | |
cc17453a EZ |
481 | /* Disassemble an instruction. */ |
482 | static int | |
617daa0e | 483 | gdb_print_insn_sh (bfd_vma memaddr, disassemble_info * info) |
c906108c | 484 | { |
1c509ca8 JR |
485 | info->endian = TARGET_BYTE_ORDER; |
486 | return print_insn_sh (memaddr, info); | |
283150cd EZ |
487 | } |
488 | ||
cc17453a | 489 | static CORE_ADDR |
1c0159e0 CV |
490 | sh_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc, |
491 | struct sh_frame_cache *cache) | |
617daa0e | 492 | { |
1c0159e0 CV |
493 | ULONGEST inst; |
494 | CORE_ADDR opc; | |
495 | int offset; | |
496 | int sav_offset = 0; | |
c906108c | 497 | int r3_val = 0; |
1c0159e0 | 498 | int reg, sav_reg = -1; |
cc17453a | 499 | |
1c0159e0 CV |
500 | if (pc >= current_pc) |
501 | return current_pc; | |
cc17453a | 502 | |
1c0159e0 | 503 | cache->uses_fp = 0; |
cc17453a EZ |
504 | for (opc = pc + (2 * 28); pc < opc; pc += 2) |
505 | { | |
1c0159e0 | 506 | inst = read_memory_unsigned_integer (pc, 2); |
cc17453a | 507 | /* See where the registers will be saved to */ |
f2ea0907 | 508 | if (IS_PUSH (inst)) |
cc17453a | 509 | { |
1c0159e0 CV |
510 | cache->saved_regs[GET_SOURCE_REG (inst)] = cache->sp_offset; |
511 | cache->sp_offset += 4; | |
cc17453a | 512 | } |
f2ea0907 | 513 | else if (IS_STS (inst)) |
cc17453a | 514 | { |
1c0159e0 CV |
515 | cache->saved_regs[PR_REGNUM] = cache->sp_offset; |
516 | cache->sp_offset += 4; | |
cc17453a | 517 | } |
03131d99 CV |
518 | else if (IS_MACL_STS (inst)) |
519 | { | |
520 | cache->saved_regs[MACL_REGNUM] = cache->sp_offset; | |
521 | cache->sp_offset += 4; | |
522 | } | |
f2ea0907 | 523 | else if (IS_MOV_R3 (inst)) |
cc17453a | 524 | { |
f2ea0907 | 525 | r3_val = ((inst & 0xff) ^ 0x80) - 0x80; |
cc17453a | 526 | } |
f2ea0907 | 527 | else if (IS_SHLL_R3 (inst)) |
cc17453a EZ |
528 | { |
529 | r3_val <<= 1; | |
530 | } | |
f2ea0907 | 531 | else if (IS_ADD_R3SP (inst)) |
cc17453a | 532 | { |
1c0159e0 | 533 | cache->sp_offset += -r3_val; |
cc17453a | 534 | } |
f2ea0907 | 535 | else if (IS_ADD_IMM_SP (inst)) |
cc17453a | 536 | { |
1c0159e0 CV |
537 | offset = ((inst & 0xff) ^ 0x80) - 0x80; |
538 | cache->sp_offset -= offset; | |
c906108c | 539 | } |
1c0159e0 | 540 | else if (IS_MOVW_PCREL_TO_REG (inst)) |
617daa0e | 541 | { |
1c0159e0 CV |
542 | if (sav_reg < 0) |
543 | { | |
544 | reg = GET_TARGET_REG (inst); | |
545 | if (reg < 14) | |
546 | { | |
547 | sav_reg = reg; | |
a2b4a96c | 548 | offset = (inst & 0xff) << 1; |
1c0159e0 | 549 | sav_offset = |
a2b4a96c | 550 | read_memory_integer ((pc + 4) + offset, 2); |
1c0159e0 CV |
551 | } |
552 | } | |
c906108c | 553 | } |
1c0159e0 | 554 | else if (IS_MOVL_PCREL_TO_REG (inst)) |
617daa0e | 555 | { |
1c0159e0 CV |
556 | if (sav_reg < 0) |
557 | { | |
a2b4a96c | 558 | reg = GET_TARGET_REG (inst); |
1c0159e0 CV |
559 | if (reg < 14) |
560 | { | |
561 | sav_reg = reg; | |
a2b4a96c | 562 | offset = (inst & 0xff) << 2; |
1c0159e0 | 563 | sav_offset = |
a2b4a96c | 564 | read_memory_integer (((pc & 0xfffffffc) + 4) + offset, 4); |
1c0159e0 CV |
565 | } |
566 | } | |
c906108c | 567 | } |
03131d99 CV |
568 | else if (IS_MOVI20 (inst)) |
569 | { | |
570 | if (sav_reg < 0) | |
571 | { | |
572 | reg = GET_TARGET_REG (inst); | |
573 | if (reg < 14) | |
574 | { | |
575 | sav_reg = reg; | |
576 | sav_offset = GET_SOURCE_REG (inst) << 16; | |
577 | /* MOVI20 is a 32 bit instruction! */ | |
578 | pc += 2; | |
579 | sav_offset |= read_memory_unsigned_integer (pc, 2); | |
580 | /* Now sav_offset contains an unsigned 20 bit value. | |
581 | It must still get sign extended. */ | |
582 | if (sav_offset & 0x00080000) | |
583 | sav_offset |= 0xfff00000; | |
584 | } | |
585 | } | |
586 | } | |
1c0159e0 | 587 | else if (IS_SUB_REG_FROM_SP (inst)) |
617daa0e | 588 | { |
1c0159e0 CV |
589 | reg = GET_SOURCE_REG (inst); |
590 | if (sav_reg > 0 && reg == sav_reg) | |
591 | { | |
592 | sav_reg = -1; | |
593 | } | |
594 | cache->sp_offset += sav_offset; | |
c906108c | 595 | } |
f2ea0907 | 596 | else if (IS_FPUSH (inst)) |
c906108c | 597 | { |
f2ea0907 | 598 | if (read_register (FPSCR_REGNUM) & FPSCR_SZ) |
c906108c | 599 | { |
1c0159e0 | 600 | cache->sp_offset += 8; |
c906108c SS |
601 | } |
602 | else | |
603 | { | |
1c0159e0 | 604 | cache->sp_offset += 4; |
c906108c SS |
605 | } |
606 | } | |
f2ea0907 | 607 | else if (IS_MOV_SP_FP (inst)) |
617daa0e | 608 | { |
960ccd7d | 609 | cache->uses_fp = 1; |
1c0159e0 CV |
610 | /* At this point, only allow argument register moves to other |
611 | registers or argument register moves to @(X,fp) which are | |
612 | moving the register arguments onto the stack area allocated | |
613 | by a former add somenumber to SP call. Don't allow moving | |
614 | to an fp indirect address above fp + cache->sp_offset. */ | |
615 | pc += 2; | |
616 | for (opc = pc + 12; pc < opc; pc += 2) | |
617 | { | |
618 | inst = read_memory_integer (pc, 2); | |
619 | if (IS_MOV_ARG_TO_IND_R14 (inst)) | |
617daa0e | 620 | { |
1c0159e0 CV |
621 | reg = GET_SOURCE_REG (inst); |
622 | if (cache->sp_offset > 0) | |
617daa0e | 623 | cache->saved_regs[reg] = cache->sp_offset; |
1c0159e0 CV |
624 | } |
625 | else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst)) | |
617daa0e | 626 | { |
1c0159e0 CV |
627 | reg = GET_SOURCE_REG (inst); |
628 | offset = (inst & 0xf) * 4; | |
629 | if (cache->sp_offset > offset) | |
630 | cache->saved_regs[reg] = cache->sp_offset - offset; | |
631 | } | |
632 | else if (IS_MOV_ARG_TO_REG (inst)) | |
617daa0e | 633 | continue; |
1c0159e0 CV |
634 | else |
635 | break; | |
636 | } | |
637 | break; | |
638 | } | |
5f883edd FF |
639 | else if (IS_JSR (inst)) |
640 | { | |
641 | /* We have found a jsr that has been scheduled into the prologue. | |
642 | If we continue the scan and return a pc someplace after this, | |
643 | then setting a breakpoint on this function will cause it to | |
644 | appear to be called after the function it is calling via the | |
645 | jsr, which will be very confusing. Most likely the next | |
646 | instruction is going to be IS_MOV_SP_FP in the delay slot. If | |
647 | so, note that before returning the current pc. */ | |
648 | inst = read_memory_integer (pc + 2, 2); | |
649 | if (IS_MOV_SP_FP (inst)) | |
650 | cache->uses_fp = 1; | |
651 | break; | |
652 | } | |
617daa0e CV |
653 | #if 0 /* This used to just stop when it found an instruction that |
654 | was not considered part of the prologue. Now, we just | |
655 | keep going looking for likely instructions. */ | |
c906108c SS |
656 | else |
657 | break; | |
2bfa91ee | 658 | #endif |
c906108c SS |
659 | } |
660 | ||
1c0159e0 CV |
661 | return pc; |
662 | } | |
c906108c | 663 | |
1c0159e0 | 664 | /* Skip any prologue before the guts of a function */ |
c906108c | 665 | |
1c0159e0 CV |
666 | /* Skip the prologue using the debug information. If this fails we'll |
667 | fall back on the 'guess' method below. */ | |
668 | static CORE_ADDR | |
669 | after_prologue (CORE_ADDR pc) | |
670 | { | |
671 | struct symtab_and_line sal; | |
672 | CORE_ADDR func_addr, func_end; | |
c906108c | 673 | |
1c0159e0 CV |
674 | /* If we can not find the symbol in the partial symbol table, then |
675 | there is no hope we can determine the function's start address | |
676 | with this code. */ | |
677 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
678 | return 0; | |
c906108c | 679 | |
1c0159e0 CV |
680 | /* Get the line associated with FUNC_ADDR. */ |
681 | sal = find_pc_line (func_addr, 0); | |
682 | ||
683 | /* There are only two cases to consider. First, the end of the source line | |
684 | is within the function bounds. In that case we return the end of the | |
685 | source line. Second is the end of the source line extends beyond the | |
686 | bounds of the current function. We need to use the slow code to | |
687 | examine instructions in that case. */ | |
688 | if (sal.end < func_end) | |
689 | return sal.end; | |
690 | else | |
691 | return 0; | |
c906108c SS |
692 | } |
693 | ||
1c0159e0 CV |
694 | static CORE_ADDR |
695 | sh_skip_prologue (CORE_ADDR start_pc) | |
c906108c | 696 | { |
1c0159e0 CV |
697 | CORE_ADDR pc; |
698 | struct sh_frame_cache cache; | |
699 | ||
700 | /* See if we can determine the end of the prologue via the symbol table. | |
701 | If so, then return either PC, or the PC after the prologue, whichever | |
702 | is greater. */ | |
703 | pc = after_prologue (start_pc); | |
cc17453a | 704 | |
1c0159e0 CV |
705 | /* If after_prologue returned a useful address, then use it. Else |
706 | fall back on the instruction skipping code. */ | |
707 | if (pc) | |
708 | return max (pc, start_pc); | |
c906108c | 709 | |
1c0159e0 CV |
710 | cache.sp_offset = -4; |
711 | pc = sh_analyze_prologue (start_pc, (CORE_ADDR) -1, &cache); | |
712 | if (!cache.uses_fp) | |
713 | return start_pc; | |
c906108c | 714 | |
1c0159e0 CV |
715 | return pc; |
716 | } | |
717 | ||
2e952408 | 718 | /* The ABI says: |
9a5cef92 EZ |
719 | |
720 | Aggregate types not bigger than 8 bytes that have the same size and | |
721 | alignment as one of the integer scalar types are returned in the | |
722 | same registers as the integer type they match. | |
723 | ||
724 | For example, a 2-byte aligned structure with size 2 bytes has the | |
725 | same size and alignment as a short int, and will be returned in R0. | |
726 | A 4-byte aligned structure with size 8 bytes has the same size and | |
727 | alignment as a long long int, and will be returned in R0 and R1. | |
728 | ||
729 | When an aggregate type is returned in R0 and R1, R0 contains the | |
730 | first four bytes of the aggregate, and R1 contains the | |
731 | remainder. If the size of the aggregate type is not a multiple of 4 | |
732 | bytes, the aggregate is tail-padded up to a multiple of 4 | |
733 | bytes. The value of the padding is undefined. For little-endian | |
734 | targets the padding will appear at the most significant end of the | |
735 | last element, for big-endian targets the padding appears at the | |
736 | least significant end of the last element. | |
737 | ||
738 | All other aggregate types are returned by address. The caller | |
739 | function passes the address of an area large enough to hold the | |
740 | aggregate value in R2. The called function stores the result in | |
7fe958be | 741 | this location. |
9a5cef92 EZ |
742 | |
743 | To reiterate, structs smaller than 8 bytes could also be returned | |
744 | in memory, if they don't pass the "same size and alignment as an | |
745 | integer type" rule. | |
746 | ||
747 | For example, in | |
748 | ||
749 | struct s { char c[3]; } wibble; | |
750 | struct s foo(void) { return wibble; } | |
751 | ||
752 | the return value from foo() will be in memory, not | |
753 | in R0, because there is no 3-byte integer type. | |
754 | ||
7fe958be EZ |
755 | Similarly, in |
756 | ||
757 | struct s { char c[2]; } wibble; | |
758 | struct s foo(void) { return wibble; } | |
759 | ||
760 | because a struct containing two chars has alignment 1, that matches | |
761 | type char, but size 2, that matches type short. There's no integer | |
762 | type that has alignment 1 and size 2, so the struct is returned in | |
763 | memory. | |
764 | ||
9a5cef92 EZ |
765 | */ |
766 | ||
1c0159e0 CV |
767 | static int |
768 | sh_use_struct_convention (int gcc_p, struct type *type) | |
769 | { | |
770 | int len = TYPE_LENGTH (type); | |
771 | int nelem = TYPE_NFIELDS (type); | |
3f997a97 CV |
772 | |
773 | /* Non-power of 2 length types and types bigger than 8 bytes (which don't | |
774 | fit in two registers anyway) use struct convention. */ | |
775 | if (len != 1 && len != 2 && len != 4 && len != 8) | |
776 | return 1; | |
777 | ||
778 | /* Scalar types and aggregate types with exactly one field are aligned | |
779 | by definition. They are returned in registers. */ | |
780 | if (nelem <= 1) | |
781 | return 0; | |
782 | ||
783 | /* If the first field in the aggregate has the same length as the entire | |
784 | aggregate type, the type is returned in registers. */ | |
785 | if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == len) | |
786 | return 0; | |
787 | ||
788 | /* If the size of the aggregate is 8 bytes and the first field is | |
789 | of size 4 bytes its alignment is equal to long long's alignment, | |
790 | so it's returned in registers. */ | |
791 | if (len == 8 && TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == 4) | |
792 | return 0; | |
793 | ||
794 | /* Otherwise use struct convention. */ | |
795 | return 1; | |
283150cd EZ |
796 | } |
797 | ||
cc17453a EZ |
798 | /* Extract from an array REGBUF containing the (raw) register state |
799 | the address in which a function should return its structure value, | |
800 | as a CORE_ADDR (or an expression that can be used as one). */ | |
b3df3fff | 801 | static CORE_ADDR |
48db5a3c | 802 | sh_extract_struct_value_address (struct regcache *regcache) |
cc17453a | 803 | { |
48db5a3c | 804 | ULONGEST addr; |
1c0159e0 | 805 | |
48db5a3c CV |
806 | regcache_cooked_read_unsigned (regcache, STRUCT_RETURN_REGNUM, &addr); |
807 | return addr; | |
cc17453a EZ |
808 | } |
809 | ||
19f59343 MS |
810 | static CORE_ADDR |
811 | sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp) | |
812 | { | |
813 | return sp & ~3; | |
814 | } | |
815 | ||
55ff77ac | 816 | /* Function: push_dummy_call (formerly push_arguments) |
c906108c SS |
817 | Setup the function arguments for calling a function in the inferior. |
818 | ||
85a453d5 | 819 | On the Renesas SH architecture, there are four registers (R4 to R7) |
c906108c SS |
820 | which are dedicated for passing function arguments. Up to the first |
821 | four arguments (depending on size) may go into these registers. | |
822 | The rest go on the stack. | |
823 | ||
6df2bf50 MS |
824 | MVS: Except on SH variants that have floating point registers. |
825 | In that case, float and double arguments are passed in the same | |
826 | manner, but using FP registers instead of GP registers. | |
827 | ||
c906108c SS |
828 | Arguments that are smaller than 4 bytes will still take up a whole |
829 | register or a whole 32-bit word on the stack, and will be | |
830 | right-justified in the register or the stack word. This includes | |
831 | chars, shorts, and small aggregate types. | |
832 | ||
833 | Arguments that are larger than 4 bytes may be split between two or | |
834 | more registers. If there are not enough registers free, an argument | |
835 | may be passed partly in a register (or registers), and partly on the | |
836 | stack. This includes doubles, long longs, and larger aggregates. | |
837 | As far as I know, there is no upper limit to the size of aggregates | |
838 | that will be passed in this way; in other words, the convention of | |
839 | passing a pointer to a large aggregate instead of a copy is not used. | |
840 | ||
6df2bf50 | 841 | MVS: The above appears to be true for the SH variants that do not |
55ff77ac | 842 | have an FPU, however those that have an FPU appear to copy the |
6df2bf50 MS |
843 | aggregate argument onto the stack (and not place it in registers) |
844 | if it is larger than 16 bytes (four GP registers). | |
845 | ||
c906108c SS |
846 | An exceptional case exists for struct arguments (and possibly other |
847 | aggregates such as arrays) if the size is larger than 4 bytes but | |
848 | not a multiple of 4 bytes. In this case the argument is never split | |
849 | between the registers and the stack, but instead is copied in its | |
850 | entirety onto the stack, AND also copied into as many registers as | |
851 | there is room for. In other words, space in registers permitting, | |
852 | two copies of the same argument are passed in. As far as I can tell, | |
853 | only the one on the stack is used, although that may be a function | |
854 | of the level of compiler optimization. I suspect this is a compiler | |
855 | bug. Arguments of these odd sizes are left-justified within the | |
856 | word (as opposed to arguments smaller than 4 bytes, which are | |
857 | right-justified). | |
c5aa993b | 858 | |
c906108c SS |
859 | If the function is to return an aggregate type such as a struct, it |
860 | is either returned in the normal return value register R0 (if its | |
861 | size is no greater than one byte), or else the caller must allocate | |
862 | space into which the callee will copy the return value (if the size | |
863 | is greater than one byte). In this case, a pointer to the return | |
864 | value location is passed into the callee in register R2, which does | |
865 | not displace any of the other arguments passed in via registers R4 | |
866 | to R7. */ | |
867 | ||
e5e33cd9 CV |
868 | /* Helper function to justify value in register according to endianess. */ |
869 | static char * | |
870 | sh_justify_value_in_reg (struct value *val, int len) | |
871 | { | |
872 | static char valbuf[4]; | |
873 | ||
617daa0e | 874 | memset (valbuf, 0, sizeof (valbuf)); |
e5e33cd9 CV |
875 | if (len < 4) |
876 | { | |
877 | /* value gets right-justified in the register or stack word */ | |
878 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
879 | memcpy (valbuf + (4 - len), (char *) VALUE_CONTENTS (val), len); | |
880 | else | |
881 | memcpy (valbuf, (char *) VALUE_CONTENTS (val), len); | |
882 | return valbuf; | |
883 | } | |
884 | return (char *) VALUE_CONTENTS (val); | |
617daa0e | 885 | } |
e5e33cd9 CV |
886 | |
887 | /* Helper function to eval number of bytes to allocate on stack. */ | |
888 | static CORE_ADDR | |
889 | sh_stack_allocsize (int nargs, struct value **args) | |
890 | { | |
891 | int stack_alloc = 0; | |
892 | while (nargs-- > 0) | |
893 | stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[nargs])) + 3) & ~3); | |
894 | return stack_alloc; | |
895 | } | |
896 | ||
897 | /* Helper functions for getting the float arguments right. Registers usage | |
898 | depends on the ABI and the endianess. The comments should enlighten how | |
899 | it's intended to work. */ | |
900 | ||
901 | /* This array stores which of the float arg registers are already in use. */ | |
902 | static int flt_argreg_array[FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM + 1]; | |
903 | ||
904 | /* This function just resets the above array to "no reg used so far". */ | |
905 | static void | |
906 | sh_init_flt_argreg (void) | |
907 | { | |
908 | memset (flt_argreg_array, 0, sizeof flt_argreg_array); | |
909 | } | |
910 | ||
911 | /* This function returns the next register to use for float arg passing. | |
912 | It returns either a valid value between FLOAT_ARG0_REGNUM and | |
913 | FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns | |
914 | FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available. | |
915 | ||
916 | Note that register number 0 in flt_argreg_array corresponds with the | |
917 | real float register fr4. In contrast to FLOAT_ARG0_REGNUM (value is | |
918 | 29) the parity of the register number is preserved, which is important | |
919 | for the double register passing test (see the "argreg & 1" test below). */ | |
920 | static int | |
921 | sh_next_flt_argreg (int len) | |
922 | { | |
923 | int argreg; | |
924 | ||
925 | /* First search for the next free register. */ | |
617daa0e CV |
926 | for (argreg = 0; argreg <= FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM; |
927 | ++argreg) | |
e5e33cd9 CV |
928 | if (!flt_argreg_array[argreg]) |
929 | break; | |
930 | ||
931 | /* No register left? */ | |
932 | if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM) | |
933 | return FLOAT_ARGLAST_REGNUM + 1; | |
934 | ||
935 | if (len == 8) | |
936 | { | |
937 | /* Doubles are always starting in a even register number. */ | |
938 | if (argreg & 1) | |
617daa0e | 939 | { |
e5e33cd9 CV |
940 | flt_argreg_array[argreg] = 1; |
941 | ||
942 | ++argreg; | |
943 | ||
617daa0e | 944 | /* No register left? */ |
e5e33cd9 CV |
945 | if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM) |
946 | return FLOAT_ARGLAST_REGNUM + 1; | |
947 | } | |
948 | /* Also mark the next register as used. */ | |
949 | flt_argreg_array[argreg + 1] = 1; | |
950 | } | |
951 | else if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) | |
952 | { | |
953 | /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */ | |
954 | if (!flt_argreg_array[argreg + 1]) | |
955 | ++argreg; | |
956 | } | |
957 | flt_argreg_array[argreg] = 1; | |
958 | return FLOAT_ARG0_REGNUM + argreg; | |
959 | } | |
960 | ||
afce3d2a CV |
961 | /* Helper function which figures out, if a type is treated like a float type. |
962 | ||
2e952408 | 963 | The FPU ABIs have a special way how to treat types as float types. |
afce3d2a CV |
964 | Structures with exactly one member, which is of type float or double, are |
965 | treated exactly as the base types float or double: | |
966 | ||
967 | struct sf { | |
968 | float f; | |
969 | }; | |
970 | ||
971 | struct sd { | |
972 | double d; | |
973 | }; | |
974 | ||
975 | are handled the same way as just | |
976 | ||
977 | float f; | |
978 | ||
979 | double d; | |
980 | ||
981 | As a result, arguments of these struct types are pushed into floating point | |
982 | registers exactly as floats or doubles, using the same decision algorithm. | |
983 | ||
984 | The same is valid if these types are used as function return types. The | |
985 | above structs are returned in fr0 resp. fr0,fr1 instead of in r0, r0,r1 | |
986 | or even using struct convention as it is for other structs. */ | |
987 | ||
988 | static int | |
989 | sh_treat_as_flt_p (struct type *type) | |
990 | { | |
991 | int len = TYPE_LENGTH (type); | |
992 | ||
993 | /* Ordinary float types are obviously treated as float. */ | |
994 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
995 | return 1; | |
996 | /* Otherwise non-struct types are not treated as float. */ | |
997 | if (TYPE_CODE (type) != TYPE_CODE_STRUCT) | |
998 | return 0; | |
999 | /* Otherwise structs with more than one memeber are not treated as float. */ | |
1000 | if (TYPE_NFIELDS (type) != 1) | |
1001 | return 0; | |
1002 | /* Otherwise if the type of that member is float, the whole type is | |
1003 | treated as float. */ | |
1004 | if (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) == TYPE_CODE_FLT) | |
1005 | return 1; | |
1006 | /* Otherwise it's not treated as float. */ | |
1007 | return 0; | |
1008 | } | |
1009 | ||
cc17453a | 1010 | static CORE_ADDR |
617daa0e | 1011 | sh_push_dummy_call_fpu (struct gdbarch *gdbarch, |
7d9b040b | 1012 | struct value *function, |
617daa0e | 1013 | struct regcache *regcache, |
6df2bf50 | 1014 | CORE_ADDR bp_addr, int nargs, |
617daa0e | 1015 | struct value **args, |
6df2bf50 MS |
1016 | CORE_ADDR sp, int struct_return, |
1017 | CORE_ADDR struct_addr) | |
1018 | { | |
e5e33cd9 CV |
1019 | int stack_offset = 0; |
1020 | int argreg = ARG0_REGNUM; | |
8748518b | 1021 | int flt_argreg = 0; |
6df2bf50 MS |
1022 | int argnum; |
1023 | struct type *type; | |
1024 | CORE_ADDR regval; | |
1025 | char *val; | |
8748518b | 1026 | int len, reg_size = 0; |
afce3d2a CV |
1027 | int pass_on_stack = 0; |
1028 | int treat_as_flt; | |
6df2bf50 MS |
1029 | |
1030 | /* first force sp to a 4-byte alignment */ | |
1031 | sp = sh_frame_align (gdbarch, sp); | |
1032 | ||
6df2bf50 | 1033 | if (struct_return) |
1c0159e0 | 1034 | regcache_cooked_write_unsigned (regcache, |
617daa0e | 1035 | STRUCT_RETURN_REGNUM, struct_addr); |
6df2bf50 | 1036 | |
e5e33cd9 CV |
1037 | /* make room on stack for args */ |
1038 | sp -= sh_stack_allocsize (nargs, args); | |
1039 | ||
1040 | /* Initialize float argument mechanism. */ | |
1041 | sh_init_flt_argreg (); | |
6df2bf50 MS |
1042 | |
1043 | /* Now load as many as possible of the first arguments into | |
1044 | registers, and push the rest onto the stack. There are 16 bytes | |
1045 | in four registers available. Loop thru args from first to last. */ | |
e5e33cd9 | 1046 | for (argnum = 0; argnum < nargs; argnum++) |
6df2bf50 MS |
1047 | { |
1048 | type = VALUE_TYPE (args[argnum]); | |
1049 | len = TYPE_LENGTH (type); | |
e5e33cd9 CV |
1050 | val = sh_justify_value_in_reg (args[argnum], len); |
1051 | ||
1052 | /* Some decisions have to be made how various types are handled. | |
1053 | This also differs in different ABIs. */ | |
1054 | pass_on_stack = 0; | |
e5e33cd9 CV |
1055 | |
1056 | /* Find out the next register to use for a floating point value. */ | |
afce3d2a CV |
1057 | treat_as_flt = sh_treat_as_flt_p (type); |
1058 | if (treat_as_flt) | |
617daa0e | 1059 | flt_argreg = sh_next_flt_argreg (len); |
afce3d2a CV |
1060 | /* In contrast to non-FPU CPUs, arguments are never split between |
1061 | registers and stack. If an argument doesn't fit in the remaining | |
1062 | registers it's always pushed entirely on the stack. */ | |
1063 | else if (len > ((ARGLAST_REGNUM - argreg + 1) * 4)) | |
1064 | pass_on_stack = 1; | |
48db5a3c | 1065 | |
6df2bf50 MS |
1066 | while (len > 0) |
1067 | { | |
afce3d2a CV |
1068 | if ((treat_as_flt && flt_argreg > FLOAT_ARGLAST_REGNUM) |
1069 | || (!treat_as_flt && (argreg > ARGLAST_REGNUM | |
1070 | || pass_on_stack))) | |
617daa0e | 1071 | { |
afce3d2a | 1072 | /* The data goes entirely on the stack, 4-byte aligned. */ |
e5e33cd9 CV |
1073 | reg_size = (len + 3) & ~3; |
1074 | write_memory (sp + stack_offset, val, reg_size); | |
1075 | stack_offset += reg_size; | |
6df2bf50 | 1076 | } |
afce3d2a | 1077 | else if (treat_as_flt && flt_argreg <= FLOAT_ARGLAST_REGNUM) |
6df2bf50 | 1078 | { |
e5e33cd9 CV |
1079 | /* Argument goes in a float argument register. */ |
1080 | reg_size = register_size (gdbarch, flt_argreg); | |
1081 | regval = extract_unsigned_integer (val, reg_size); | |
2e952408 CV |
1082 | /* In little endian mode, float types taking two registers |
1083 | (doubles on sh4, long doubles on sh2e, sh3e and sh4) must | |
1084 | be stored swapped in the argument registers. The below | |
1085 | code first writes the first 32 bits in the next but one | |
1086 | register, increments the val and len values accordingly | |
1087 | and then proceeds as normal by writing the second 32 bits | |
1088 | into the next register. */ | |
1089 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE | |
1090 | && TYPE_LENGTH (type) == 2 * reg_size) | |
1091 | { | |
1092 | regcache_cooked_write_unsigned (regcache, flt_argreg + 1, | |
1093 | regval); | |
1094 | val += reg_size; | |
1095 | len -= reg_size; | |
1096 | regval = extract_unsigned_integer (val, reg_size); | |
1097 | } | |
6df2bf50 MS |
1098 | regcache_cooked_write_unsigned (regcache, flt_argreg++, regval); |
1099 | } | |
afce3d2a | 1100 | else if (!treat_as_flt && argreg <= ARGLAST_REGNUM) |
e5e33cd9 | 1101 | { |
6df2bf50 | 1102 | /* there's room in a register */ |
e5e33cd9 CV |
1103 | reg_size = register_size (gdbarch, argreg); |
1104 | regval = extract_unsigned_integer (val, reg_size); | |
6df2bf50 MS |
1105 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
1106 | } | |
afce3d2a | 1107 | /* Store the value one register at a time or in one step on stack. */ |
e5e33cd9 CV |
1108 | len -= reg_size; |
1109 | val += reg_size; | |
6df2bf50 MS |
1110 | } |
1111 | } | |
1112 | ||
1113 | /* Store return address. */ | |
55ff77ac | 1114 | regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr); |
6df2bf50 MS |
1115 | |
1116 | /* Update stack pointer. */ | |
1117 | regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp); | |
1118 | ||
1119 | return sp; | |
1120 | } | |
1121 | ||
1122 | static CORE_ADDR | |
617daa0e | 1123 | sh_push_dummy_call_nofpu (struct gdbarch *gdbarch, |
7d9b040b | 1124 | struct value *function, |
617daa0e CV |
1125 | struct regcache *regcache, |
1126 | CORE_ADDR bp_addr, | |
1127 | int nargs, struct value **args, | |
1128 | CORE_ADDR sp, int struct_return, | |
6df2bf50 | 1129 | CORE_ADDR struct_addr) |
c906108c | 1130 | { |
e5e33cd9 CV |
1131 | int stack_offset = 0; |
1132 | int argreg = ARG0_REGNUM; | |
c906108c SS |
1133 | int argnum; |
1134 | struct type *type; | |
1135 | CORE_ADDR regval; | |
1136 | char *val; | |
e5e33cd9 | 1137 | int len, reg_size; |
c906108c SS |
1138 | |
1139 | /* first force sp to a 4-byte alignment */ | |
19f59343 | 1140 | sp = sh_frame_align (gdbarch, sp); |
c906108c | 1141 | |
c906108c | 1142 | if (struct_return) |
55ff77ac | 1143 | regcache_cooked_write_unsigned (regcache, |
617daa0e | 1144 | STRUCT_RETURN_REGNUM, struct_addr); |
c906108c | 1145 | |
e5e33cd9 CV |
1146 | /* make room on stack for args */ |
1147 | sp -= sh_stack_allocsize (nargs, args); | |
c906108c | 1148 | |
c906108c SS |
1149 | /* Now load as many as possible of the first arguments into |
1150 | registers, and push the rest onto the stack. There are 16 bytes | |
1151 | in four registers available. Loop thru args from first to last. */ | |
e5e33cd9 | 1152 | for (argnum = 0; argnum < nargs; argnum++) |
617daa0e | 1153 | { |
c906108c | 1154 | type = VALUE_TYPE (args[argnum]); |
c5aa993b | 1155 | len = TYPE_LENGTH (type); |
e5e33cd9 | 1156 | val = sh_justify_value_in_reg (args[argnum], len); |
c906108c | 1157 | |
c906108c SS |
1158 | while (len > 0) |
1159 | { | |
e5e33cd9 | 1160 | if (argreg > ARGLAST_REGNUM) |
617daa0e | 1161 | { |
e5e33cd9 CV |
1162 | /* The remainder of the data goes entirely on the stack, |
1163 | 4-byte aligned. */ | |
1164 | reg_size = (len + 3) & ~3; | |
1165 | write_memory (sp + stack_offset, val, reg_size); | |
617daa0e | 1166 | stack_offset += reg_size; |
c906108c | 1167 | } |
e5e33cd9 | 1168 | else if (argreg <= ARGLAST_REGNUM) |
617daa0e | 1169 | { |
3bbfbb92 | 1170 | /* there's room in a register */ |
e5e33cd9 CV |
1171 | reg_size = register_size (gdbarch, argreg); |
1172 | regval = extract_unsigned_integer (val, reg_size); | |
48db5a3c | 1173 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
c906108c | 1174 | } |
e5e33cd9 CV |
1175 | /* Store the value reg_size bytes at a time. This means that things |
1176 | larger than reg_size bytes may go partly in registers and partly | |
c906108c | 1177 | on the stack. */ |
e5e33cd9 CV |
1178 | len -= reg_size; |
1179 | val += reg_size; | |
c906108c SS |
1180 | } |
1181 | } | |
48db5a3c CV |
1182 | |
1183 | /* Store return address. */ | |
55ff77ac | 1184 | regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr); |
48db5a3c CV |
1185 | |
1186 | /* Update stack pointer. */ | |
1187 | regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp); | |
1188 | ||
c906108c SS |
1189 | return sp; |
1190 | } | |
1191 | ||
cc17453a EZ |
1192 | /* Find a function's return value in the appropriate registers (in |
1193 | regbuf), and copy it into valbuf. Extract from an array REGBUF | |
1194 | containing the (raw) register state a function return value of type | |
1195 | TYPE, and copy that, in virtual format, into VALBUF. */ | |
1196 | static void | |
48db5a3c CV |
1197 | sh_default_extract_return_value (struct type *type, struct regcache *regcache, |
1198 | void *valbuf) | |
c906108c | 1199 | { |
cc17453a | 1200 | int len = TYPE_LENGTH (type); |
3116c80a EZ |
1201 | int return_register = R0_REGNUM; |
1202 | int offset; | |
617daa0e | 1203 | |
cc17453a | 1204 | if (len <= 4) |
3116c80a | 1205 | { |
48db5a3c CV |
1206 | ULONGEST c; |
1207 | ||
1208 | regcache_cooked_read_unsigned (regcache, R0_REGNUM, &c); | |
1209 | store_unsigned_integer (valbuf, len, c); | |
3116c80a | 1210 | } |
48db5a3c | 1211 | else if (len == 8) |
3116c80a | 1212 | { |
48db5a3c CV |
1213 | int i, regnum = R0_REGNUM; |
1214 | for (i = 0; i < len; i += 4) | |
617daa0e | 1215 | regcache_raw_read (regcache, regnum++, (char *) valbuf + i); |
3116c80a EZ |
1216 | } |
1217 | else | |
1218 | error ("bad size for return value"); | |
1219 | } | |
1220 | ||
1221 | static void | |
48db5a3c CV |
1222 | sh3e_sh4_extract_return_value (struct type *type, struct regcache *regcache, |
1223 | void *valbuf) | |
3116c80a | 1224 | { |
afce3d2a | 1225 | if (sh_treat_as_flt_p (type)) |
3116c80a | 1226 | { |
48db5a3c CV |
1227 | int len = TYPE_LENGTH (type); |
1228 | int i, regnum = FP0_REGNUM; | |
1229 | for (i = 0; i < len; i += 4) | |
2e952408 CV |
1230 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) |
1231 | regcache_raw_read (regcache, regnum++, (char *) valbuf + len - 4 - i); | |
1232 | else | |
1233 | regcache_raw_read (regcache, regnum++, (char *) valbuf + i); | |
3116c80a | 1234 | } |
cc17453a | 1235 | else |
48db5a3c | 1236 | sh_default_extract_return_value (type, regcache, valbuf); |
cc17453a | 1237 | } |
c906108c | 1238 | |
cc17453a EZ |
1239 | /* Write into appropriate registers a function return value |
1240 | of type TYPE, given in virtual format. | |
1241 | If the architecture is sh4 or sh3e, store a function's return value | |
1242 | in the R0 general register or in the FP0 floating point register, | |
1243 | depending on the type of the return value. In all the other cases | |
3bbfbb92 | 1244 | the result is stored in r0, left-justified. */ |
cc17453a | 1245 | static void |
48db5a3c CV |
1246 | sh_default_store_return_value (struct type *type, struct regcache *regcache, |
1247 | const void *valbuf) | |
cc17453a | 1248 | { |
48db5a3c CV |
1249 | ULONGEST val; |
1250 | int len = TYPE_LENGTH (type); | |
d19b71be | 1251 | |
48db5a3c | 1252 | if (len <= 4) |
d19b71be | 1253 | { |
48db5a3c CV |
1254 | val = extract_unsigned_integer (valbuf, len); |
1255 | regcache_cooked_write_unsigned (regcache, R0_REGNUM, val); | |
d19b71be MS |
1256 | } |
1257 | else | |
48db5a3c CV |
1258 | { |
1259 | int i, regnum = R0_REGNUM; | |
1260 | for (i = 0; i < len; i += 4) | |
617daa0e | 1261 | regcache_raw_write (regcache, regnum++, (char *) valbuf + i); |
48db5a3c | 1262 | } |
cc17453a | 1263 | } |
c906108c | 1264 | |
cc17453a | 1265 | static void |
48db5a3c CV |
1266 | sh3e_sh4_store_return_value (struct type *type, struct regcache *regcache, |
1267 | const void *valbuf) | |
cc17453a | 1268 | { |
afce3d2a | 1269 | if (sh_treat_as_flt_p (type)) |
48db5a3c CV |
1270 | { |
1271 | int len = TYPE_LENGTH (type); | |
1272 | int i, regnum = FP0_REGNUM; | |
1273 | for (i = 0; i < len; i += 4) | |
c8a3b559 CV |
1274 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) |
1275 | regcache_raw_write (regcache, regnum++, | |
1276 | (char *) valbuf + len - 4 - i); | |
1277 | else | |
1278 | regcache_raw_write (regcache, regnum++, (char *) valbuf + i); | |
48db5a3c | 1279 | } |
cc17453a | 1280 | else |
48db5a3c | 1281 | sh_default_store_return_value (type, regcache, valbuf); |
c906108c SS |
1282 | } |
1283 | ||
c0409442 CV |
1284 | static enum return_value_convention |
1285 | sh_return_value_nofpu (struct gdbarch *gdbarch, struct type *type, | |
1286 | struct regcache *regcache, | |
1287 | void *readbuf, const void *writebuf) | |
1288 | { | |
1289 | if (sh_use_struct_convention (0, type)) | |
1290 | return RETURN_VALUE_STRUCT_CONVENTION; | |
1291 | if (writebuf) | |
1292 | sh_default_store_return_value (type, regcache, writebuf); | |
1293 | else if (readbuf) | |
1294 | sh_default_extract_return_value (type, regcache, readbuf); | |
1295 | return RETURN_VALUE_REGISTER_CONVENTION; | |
1296 | } | |
1297 | ||
1298 | static enum return_value_convention | |
1299 | sh_return_value_fpu (struct gdbarch *gdbarch, struct type *type, | |
1300 | struct regcache *regcache, | |
1301 | void *readbuf, const void *writebuf) | |
1302 | { | |
1303 | if (sh_use_struct_convention (0, type)) | |
1304 | return RETURN_VALUE_STRUCT_CONVENTION; | |
1305 | if (writebuf) | |
1306 | sh3e_sh4_store_return_value (type, regcache, writebuf); | |
1307 | else if (readbuf) | |
1308 | sh3e_sh4_extract_return_value (type, regcache, readbuf); | |
1309 | return RETURN_VALUE_REGISTER_CONVENTION; | |
1310 | } | |
1311 | ||
c906108c SS |
1312 | /* Print the registers in a form similar to the E7000 */ |
1313 | ||
1314 | static void | |
fba45db2 | 1315 | sh_generic_show_regs (void) |
c906108c | 1316 | { |
cc17453a EZ |
1317 | printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", |
1318 | paddr (read_register (PC_REGNUM)), | |
55ff77ac CV |
1319 | (long) read_register (SR_REGNUM), |
1320 | (long) read_register (PR_REGNUM), | |
cc17453a EZ |
1321 | (long) read_register (MACH_REGNUM), |
1322 | (long) read_register (MACL_REGNUM)); | |
1323 | ||
1324 | printf_filtered ("GBR=%08lx VBR=%08lx", | |
1325 | (long) read_register (GBR_REGNUM), | |
1326 | (long) read_register (VBR_REGNUM)); | |
1327 | ||
617daa0e CV |
1328 | printf_filtered |
1329 | ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1330 | (long) read_register (0), (long) read_register (1), | |
1331 | (long) read_register (2), (long) read_register (3), | |
1332 | (long) read_register (4), (long) read_register (5), | |
1333 | (long) read_register (6), (long) read_register (7)); | |
cc17453a | 1334 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
617daa0e CV |
1335 | (long) read_register (8), (long) read_register (9), |
1336 | (long) read_register (10), (long) read_register (11), | |
1337 | (long) read_register (12), (long) read_register (13), | |
1338 | (long) read_register (14), (long) read_register (15)); | |
cc17453a | 1339 | } |
c906108c | 1340 | |
cc17453a | 1341 | static void |
fba45db2 | 1342 | sh3_show_regs (void) |
cc17453a | 1343 | { |
d4f3574e SS |
1344 | printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", |
1345 | paddr (read_register (PC_REGNUM)), | |
55ff77ac CV |
1346 | (long) read_register (SR_REGNUM), |
1347 | (long) read_register (PR_REGNUM), | |
d4f3574e SS |
1348 | (long) read_register (MACH_REGNUM), |
1349 | (long) read_register (MACL_REGNUM)); | |
1350 | ||
1351 | printf_filtered ("GBR=%08lx VBR=%08lx", | |
1352 | (long) read_register (GBR_REGNUM), | |
1353 | (long) read_register (VBR_REGNUM)); | |
cc17453a | 1354 | printf_filtered (" SSR=%08lx SPC=%08lx", |
617daa0e | 1355 | (long) read_register (SSR_REGNUM), |
f2ea0907 | 1356 | (long) read_register (SPC_REGNUM)); |
c906108c | 1357 | |
617daa0e CV |
1358 | printf_filtered |
1359 | ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1360 | (long) read_register (0), (long) read_register (1), | |
1361 | (long) read_register (2), (long) read_register (3), | |
1362 | (long) read_register (4), (long) read_register (5), | |
1363 | (long) read_register (6), (long) read_register (7)); | |
d4f3574e | 1364 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
617daa0e CV |
1365 | (long) read_register (8), (long) read_register (9), |
1366 | (long) read_register (10), (long) read_register (11), | |
1367 | (long) read_register (12), (long) read_register (13), | |
1368 | (long) read_register (14), (long) read_register (15)); | |
c906108c SS |
1369 | } |
1370 | ||
53116e27 | 1371 | |
2d188dd3 NC |
1372 | static void |
1373 | sh2e_show_regs (void) | |
1374 | { | |
1375 | printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", | |
1376 | paddr (read_register (PC_REGNUM)), | |
1377 | (long) read_register (SR_REGNUM), | |
1378 | (long) read_register (PR_REGNUM), | |
1379 | (long) read_register (MACH_REGNUM), | |
1380 | (long) read_register (MACL_REGNUM)); | |
1381 | ||
1382 | printf_filtered ("GBR=%08lx VBR=%08lx", | |
1383 | (long) read_register (GBR_REGNUM), | |
1384 | (long) read_register (VBR_REGNUM)); | |
1385 | printf_filtered (" FPUL=%08lx FPSCR=%08lx", | |
617daa0e CV |
1386 | (long) read_register (FPUL_REGNUM), |
1387 | (long) read_register (FPSCR_REGNUM)); | |
1388 | ||
1389 | printf_filtered | |
1390 | ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1391 | (long) read_register (0), (long) read_register (1), | |
1392 | (long) read_register (2), (long) read_register (3), | |
1393 | (long) read_register (4), (long) read_register (5), | |
1394 | (long) read_register (6), (long) read_register (7)); | |
2d188dd3 | 1395 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
617daa0e CV |
1396 | (long) read_register (8), (long) read_register (9), |
1397 | (long) read_register (10), (long) read_register (11), | |
1398 | (long) read_register (12), (long) read_register (13), | |
1399 | (long) read_register (14), (long) read_register (15)); | |
1400 | ||
1401 | printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 0), (long) read_register (FP0_REGNUM + 1), (long) read_register (FP0_REGNUM + 2), (long) read_register (FP0_REGNUM + 3), (long) read_register (FP0_REGNUM + 4), (long) read_register (FP0_REGNUM + 5), (long) read_register (FP0_REGNUM + 6), (long) read_register (FP0_REGNUM + 7)); | |
1402 | printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 8), (long) read_register (FP0_REGNUM + 9), (long) read_register (FP0_REGNUM + 10), (long) read_register (FP0_REGNUM + 11), (long) read_register (FP0_REGNUM + 12), (long) read_register (FP0_REGNUM + 13), (long) read_register (FP0_REGNUM + 14), (long) read_register (FP0_REGNUM + 15)); | |
2d188dd3 NC |
1403 | } |
1404 | ||
da962468 CV |
1405 | static void |
1406 | sh2a_show_regs (void) | |
1407 | { | |
1408 | int pr = read_register (FPSCR_REGNUM) & 0x80000; | |
1409 | printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", | |
1410 | paddr (read_register (PC_REGNUM)), | |
1411 | (long) read_register (SR_REGNUM), | |
1412 | (long) read_register (PR_REGNUM), | |
1413 | (long) read_register (MACH_REGNUM), | |
1414 | (long) read_register (MACL_REGNUM)); | |
1415 | ||
1416 | printf_filtered ("GBR=%08lx VBR=%08lx TBR=%08lx", | |
1417 | (long) read_register (GBR_REGNUM), | |
1418 | (long) read_register (VBR_REGNUM), | |
1419 | (long) read_register (TBR_REGNUM)); | |
1420 | printf_filtered (" FPUL=%08lx FPSCR=%08lx\n", | |
1421 | (long) read_register (FPUL_REGNUM), | |
1422 | (long) read_register (FPSCR_REGNUM)); | |
1423 | ||
1424 | printf_filtered ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1425 | (long) read_register (0), (long) read_register (1), | |
1426 | (long) read_register (2), (long) read_register (3), | |
1427 | (long) read_register (4), (long) read_register (5), | |
1428 | (long) read_register (6), (long) read_register (7)); | |
1429 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1430 | (long) read_register (8), (long) read_register (9), | |
1431 | (long) read_register (10), (long) read_register (11), | |
1432 | (long) read_register (12), (long) read_register (13), | |
1433 | (long) read_register (14), (long) read_register (15)); | |
1434 | ||
1435 | printf_filtered ((pr | |
1436 | ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n" | |
1437 | : | |
1438 | "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), | |
1439 | (long) read_register (FP0_REGNUM + 0), | |
1440 | (long) read_register (FP0_REGNUM + 1), | |
1441 | (long) read_register (FP0_REGNUM + 2), | |
1442 | (long) read_register (FP0_REGNUM + 3), | |
1443 | (long) read_register (FP0_REGNUM + 4), | |
1444 | (long) read_register (FP0_REGNUM + 5), | |
1445 | (long) read_register (FP0_REGNUM + 6), | |
1446 | (long) read_register (FP0_REGNUM + 7)); | |
1447 | printf_filtered ((pr ? | |
1448 | "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n" : | |
1449 | "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), | |
1450 | (long) read_register (FP0_REGNUM + 8), | |
1451 | (long) read_register (FP0_REGNUM + 9), | |
1452 | (long) read_register (FP0_REGNUM + 10), | |
1453 | (long) read_register (FP0_REGNUM + 11), | |
1454 | (long) read_register (FP0_REGNUM + 12), | |
1455 | (long) read_register (FP0_REGNUM + 13), | |
1456 | (long) read_register (FP0_REGNUM + 14), | |
1457 | (long) read_register (FP0_REGNUM + 15)); | |
1458 | printf_filtered ("BANK=%-3d\n", (int) read_register (BANK_REGNUM)); | |
1459 | printf_filtered ("R0b - R7b %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1460 | (long) read_register (R0_BANK0_REGNUM + 0), | |
1461 | (long) read_register (R0_BANK0_REGNUM + 1), | |
1462 | (long) read_register (R0_BANK0_REGNUM + 2), | |
1463 | (long) read_register (R0_BANK0_REGNUM + 3), | |
1464 | (long) read_register (R0_BANK0_REGNUM + 4), | |
1465 | (long) read_register (R0_BANK0_REGNUM + 5), | |
1466 | (long) read_register (R0_BANK0_REGNUM + 6), | |
1467 | (long) read_register (R0_BANK0_REGNUM + 7)); | |
1468 | printf_filtered ("R8b - R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1469 | (long) read_register (R0_BANK0_REGNUM + 8), | |
1470 | (long) read_register (R0_BANK0_REGNUM + 9), | |
1471 | (long) read_register (R0_BANK0_REGNUM + 10), | |
1472 | (long) read_register (R0_BANK0_REGNUM + 11), | |
1473 | (long) read_register (R0_BANK0_REGNUM + 12), | |
1474 | (long) read_register (R0_BANK0_REGNUM + 13), | |
1475 | (long) read_register (R0_BANK0_REGNUM + 14)); | |
1476 | printf_filtered ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n", | |
1477 | (long) read_register (R0_BANK0_REGNUM + 15), | |
1478 | (long) read_register (R0_BANK0_REGNUM + 16), | |
1479 | (long) read_register (R0_BANK0_REGNUM + 17), | |
1480 | (long) read_register (R0_BANK0_REGNUM + 18), | |
1481 | (long) read_register (R0_BANK0_REGNUM + 19)); | |
1482 | } | |
1483 | ||
1484 | static void | |
1485 | sh2a_nofpu_show_regs (void) | |
1486 | { | |
1487 | int pr = read_register (FPSCR_REGNUM) & 0x80000; | |
1488 | printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", | |
1489 | paddr (read_register (PC_REGNUM)), | |
1490 | (long) read_register (SR_REGNUM), | |
1491 | (long) read_register (PR_REGNUM), | |
1492 | (long) read_register (MACH_REGNUM), | |
1493 | (long) read_register (MACL_REGNUM)); | |
1494 | ||
1495 | printf_filtered ("GBR=%08lx VBR=%08lx TBR=%08lx", | |
1496 | (long) read_register (GBR_REGNUM), | |
1497 | (long) read_register (VBR_REGNUM), | |
1498 | (long) read_register (TBR_REGNUM)); | |
1499 | printf_filtered (" FPUL=%08lx FPSCR=%08lx\n", | |
1500 | (long) read_register (FPUL_REGNUM), | |
1501 | (long) read_register (FPSCR_REGNUM)); | |
1502 | ||
1503 | printf_filtered ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1504 | (long) read_register (0), (long) read_register (1), | |
1505 | (long) read_register (2), (long) read_register (3), | |
1506 | (long) read_register (4), (long) read_register (5), | |
1507 | (long) read_register (6), (long) read_register (7)); | |
1508 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1509 | (long) read_register (8), (long) read_register (9), | |
1510 | (long) read_register (10), (long) read_register (11), | |
1511 | (long) read_register (12), (long) read_register (13), | |
1512 | (long) read_register (14), (long) read_register (15)); | |
1513 | ||
1514 | printf_filtered ("BANK=%-3d\n", (int) read_register (BANK_REGNUM)); | |
1515 | printf_filtered ("R0b - R7b %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1516 | (long) read_register (R0_BANK0_REGNUM + 0), | |
1517 | (long) read_register (R0_BANK0_REGNUM + 1), | |
1518 | (long) read_register (R0_BANK0_REGNUM + 2), | |
1519 | (long) read_register (R0_BANK0_REGNUM + 3), | |
1520 | (long) read_register (R0_BANK0_REGNUM + 4), | |
1521 | (long) read_register (R0_BANK0_REGNUM + 5), | |
1522 | (long) read_register (R0_BANK0_REGNUM + 6), | |
1523 | (long) read_register (R0_BANK0_REGNUM + 7)); | |
1524 | printf_filtered ("R8b - R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1525 | (long) read_register (R0_BANK0_REGNUM + 8), | |
1526 | (long) read_register (R0_BANK0_REGNUM + 9), | |
1527 | (long) read_register (R0_BANK0_REGNUM + 10), | |
1528 | (long) read_register (R0_BANK0_REGNUM + 11), | |
1529 | (long) read_register (R0_BANK0_REGNUM + 12), | |
1530 | (long) read_register (R0_BANK0_REGNUM + 13), | |
1531 | (long) read_register (R0_BANK0_REGNUM + 14)); | |
1532 | printf_filtered ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n", | |
1533 | (long) read_register (R0_BANK0_REGNUM + 15), | |
1534 | (long) read_register (R0_BANK0_REGNUM + 16), | |
1535 | (long) read_register (R0_BANK0_REGNUM + 17), | |
1536 | (long) read_register (R0_BANK0_REGNUM + 18), | |
1537 | (long) read_register (R0_BANK0_REGNUM + 19)); | |
1538 | } | |
1539 | ||
cc17453a | 1540 | static void |
fba45db2 | 1541 | sh3e_show_regs (void) |
cc17453a EZ |
1542 | { |
1543 | printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", | |
1544 | paddr (read_register (PC_REGNUM)), | |
55ff77ac CV |
1545 | (long) read_register (SR_REGNUM), |
1546 | (long) read_register (PR_REGNUM), | |
cc17453a EZ |
1547 | (long) read_register (MACH_REGNUM), |
1548 | (long) read_register (MACL_REGNUM)); | |
1549 | ||
1550 | printf_filtered ("GBR=%08lx VBR=%08lx", | |
1551 | (long) read_register (GBR_REGNUM), | |
1552 | (long) read_register (VBR_REGNUM)); | |
1553 | printf_filtered (" SSR=%08lx SPC=%08lx", | |
f2ea0907 CV |
1554 | (long) read_register (SSR_REGNUM), |
1555 | (long) read_register (SPC_REGNUM)); | |
cc17453a | 1556 | printf_filtered (" FPUL=%08lx FPSCR=%08lx", |
f2ea0907 CV |
1557 | (long) read_register (FPUL_REGNUM), |
1558 | (long) read_register (FPSCR_REGNUM)); | |
c906108c | 1559 | |
617daa0e CV |
1560 | printf_filtered |
1561 | ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1562 | (long) read_register (0), (long) read_register (1), | |
1563 | (long) read_register (2), (long) read_register (3), | |
1564 | (long) read_register (4), (long) read_register (5), | |
1565 | (long) read_register (6), (long) read_register (7)); | |
cc17453a | 1566 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
617daa0e CV |
1567 | (long) read_register (8), (long) read_register (9), |
1568 | (long) read_register (10), (long) read_register (11), | |
1569 | (long) read_register (12), (long) read_register (13), | |
1570 | (long) read_register (14), (long) read_register (15)); | |
1571 | ||
1572 | printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 0), (long) read_register (FP0_REGNUM + 1), (long) read_register (FP0_REGNUM + 2), (long) read_register (FP0_REGNUM + 3), (long) read_register (FP0_REGNUM + 4), (long) read_register (FP0_REGNUM + 5), (long) read_register (FP0_REGNUM + 6), (long) read_register (FP0_REGNUM + 7)); | |
1573 | printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 8), (long) read_register (FP0_REGNUM + 9), (long) read_register (FP0_REGNUM + 10), (long) read_register (FP0_REGNUM + 11), (long) read_register (FP0_REGNUM + 12), (long) read_register (FP0_REGNUM + 13), (long) read_register (FP0_REGNUM + 14), (long) read_register (FP0_REGNUM + 15)); | |
cc17453a EZ |
1574 | } |
1575 | ||
1576 | static void | |
fba45db2 | 1577 | sh3_dsp_show_regs (void) |
c906108c | 1578 | { |
cc17453a EZ |
1579 | printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", |
1580 | paddr (read_register (PC_REGNUM)), | |
55ff77ac CV |
1581 | (long) read_register (SR_REGNUM), |
1582 | (long) read_register (PR_REGNUM), | |
cc17453a EZ |
1583 | (long) read_register (MACH_REGNUM), |
1584 | (long) read_register (MACL_REGNUM)); | |
c906108c | 1585 | |
cc17453a EZ |
1586 | printf_filtered ("GBR=%08lx VBR=%08lx", |
1587 | (long) read_register (GBR_REGNUM), | |
1588 | (long) read_register (VBR_REGNUM)); | |
1589 | ||
1590 | printf_filtered (" SSR=%08lx SPC=%08lx", | |
f2ea0907 CV |
1591 | (long) read_register (SSR_REGNUM), |
1592 | (long) read_register (SPC_REGNUM)); | |
cc17453a | 1593 | |
617daa0e CV |
1594 | printf_filtered (" DSR=%08lx", (long) read_register (DSR_REGNUM)); |
1595 | ||
1596 | printf_filtered | |
1597 | ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1598 | (long) read_register (0), (long) read_register (1), | |
1599 | (long) read_register (2), (long) read_register (3), | |
1600 | (long) read_register (4), (long) read_register (5), | |
1601 | (long) read_register (6), (long) read_register (7)); | |
cc17453a | 1602 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
617daa0e CV |
1603 | (long) read_register (8), (long) read_register (9), |
1604 | (long) read_register (10), (long) read_register (11), | |
1605 | (long) read_register (12), (long) read_register (13), | |
1606 | (long) read_register (14), (long) read_register (15)); | |
1607 | ||
1608 | printf_filtered | |
1609 | ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n", | |
1610 | (long) read_register (A0G_REGNUM) & 0xff, | |
1611 | (long) read_register (A0_REGNUM), (long) read_register (M0_REGNUM), | |
1612 | (long) read_register (X0_REGNUM), (long) read_register (Y0_REGNUM), | |
1613 | (long) read_register (RS_REGNUM), (long) read_register (MOD_REGNUM)); | |
cc17453a | 1614 | printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n", |
f2ea0907 CV |
1615 | (long) read_register (A1G_REGNUM) & 0xff, |
1616 | (long) read_register (A1_REGNUM), | |
1617 | (long) read_register (M1_REGNUM), | |
1618 | (long) read_register (X1_REGNUM), | |
1619 | (long) read_register (Y1_REGNUM), | |
1620 | (long) read_register (RE_REGNUM)); | |
c906108c SS |
1621 | } |
1622 | ||
cc17453a | 1623 | static void |
fba45db2 | 1624 | sh4_show_regs (void) |
cc17453a | 1625 | { |
f2ea0907 | 1626 | int pr = read_register (FPSCR_REGNUM) & 0x80000; |
cc17453a EZ |
1627 | printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", |
1628 | paddr (read_register (PC_REGNUM)), | |
55ff77ac CV |
1629 | (long) read_register (SR_REGNUM), |
1630 | (long) read_register (PR_REGNUM), | |
cc17453a EZ |
1631 | (long) read_register (MACH_REGNUM), |
1632 | (long) read_register (MACL_REGNUM)); | |
1633 | ||
1634 | printf_filtered ("GBR=%08lx VBR=%08lx", | |
1635 | (long) read_register (GBR_REGNUM), | |
1636 | (long) read_register (VBR_REGNUM)); | |
1637 | printf_filtered (" SSR=%08lx SPC=%08lx", | |
f2ea0907 CV |
1638 | (long) read_register (SSR_REGNUM), |
1639 | (long) read_register (SPC_REGNUM)); | |
cc17453a | 1640 | printf_filtered (" FPUL=%08lx FPSCR=%08lx", |
f2ea0907 CV |
1641 | (long) read_register (FPUL_REGNUM), |
1642 | (long) read_register (FPSCR_REGNUM)); | |
cc17453a | 1643 | |
617daa0e CV |
1644 | printf_filtered |
1645 | ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1646 | (long) read_register (0), (long) read_register (1), | |
1647 | (long) read_register (2), (long) read_register (3), | |
1648 | (long) read_register (4), (long) read_register (5), | |
1649 | (long) read_register (6), (long) read_register (7)); | |
cc17453a | 1650 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
617daa0e CV |
1651 | (long) read_register (8), (long) read_register (9), |
1652 | (long) read_register (10), (long) read_register (11), | |
1653 | (long) read_register (12), (long) read_register (13), | |
1654 | (long) read_register (14), (long) read_register (15)); | |
cc17453a EZ |
1655 | |
1656 | printf_filtered ((pr | |
1657 | ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n" | |
617daa0e CV |
1658 | : |
1659 | "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), | |
cc17453a EZ |
1660 | (long) read_register (FP0_REGNUM + 0), |
1661 | (long) read_register (FP0_REGNUM + 1), | |
1662 | (long) read_register (FP0_REGNUM + 2), | |
1663 | (long) read_register (FP0_REGNUM + 3), | |
1664 | (long) read_register (FP0_REGNUM + 4), | |
1665 | (long) read_register (FP0_REGNUM + 5), | |
1666 | (long) read_register (FP0_REGNUM + 6), | |
1667 | (long) read_register (FP0_REGNUM + 7)); | |
617daa0e CV |
1668 | printf_filtered ((pr ? |
1669 | "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n" : | |
1670 | "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), | |
cc17453a EZ |
1671 | (long) read_register (FP0_REGNUM + 8), |
1672 | (long) read_register (FP0_REGNUM + 9), | |
1673 | (long) read_register (FP0_REGNUM + 10), | |
1674 | (long) read_register (FP0_REGNUM + 11), | |
1675 | (long) read_register (FP0_REGNUM + 12), | |
1676 | (long) read_register (FP0_REGNUM + 13), | |
1677 | (long) read_register (FP0_REGNUM + 14), | |
1678 | (long) read_register (FP0_REGNUM + 15)); | |
1679 | } | |
1680 | ||
474e5826 CV |
1681 | static void |
1682 | sh4_nofpu_show_regs (void) | |
1683 | { | |
1684 | printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", | |
1685 | paddr (read_register (PC_REGNUM)), | |
1686 | (long) read_register (SR_REGNUM), | |
1687 | (long) read_register (PR_REGNUM), | |
1688 | (long) read_register (MACH_REGNUM), | |
1689 | (long) read_register (MACL_REGNUM)); | |
1690 | ||
1691 | printf_filtered ("GBR=%08lx VBR=%08lx", | |
1692 | (long) read_register (GBR_REGNUM), | |
1693 | (long) read_register (VBR_REGNUM)); | |
1694 | printf_filtered (" SSR=%08lx SPC=%08lx", | |
1695 | (long) read_register (SSR_REGNUM), | |
1696 | (long) read_register (SPC_REGNUM)); | |
1697 | ||
1698 | printf_filtered | |
1699 | ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1700 | (long) read_register (0), (long) read_register (1), | |
1701 | (long) read_register (2), (long) read_register (3), | |
1702 | (long) read_register (4), (long) read_register (5), | |
1703 | (long) read_register (6), (long) read_register (7)); | |
1704 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1705 | (long) read_register (8), (long) read_register (9), | |
1706 | (long) read_register (10), (long) read_register (11), | |
1707 | (long) read_register (12), (long) read_register (13), | |
1708 | (long) read_register (14), (long) read_register (15)); | |
1709 | } | |
1710 | ||
cc17453a | 1711 | static void |
fba45db2 | 1712 | sh_dsp_show_regs (void) |
cc17453a EZ |
1713 | { |
1714 | printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", | |
1715 | paddr (read_register (PC_REGNUM)), | |
55ff77ac CV |
1716 | (long) read_register (SR_REGNUM), |
1717 | (long) read_register (PR_REGNUM), | |
cc17453a EZ |
1718 | (long) read_register (MACH_REGNUM), |
1719 | (long) read_register (MACL_REGNUM)); | |
1720 | ||
1721 | printf_filtered ("GBR=%08lx VBR=%08lx", | |
1722 | (long) read_register (GBR_REGNUM), | |
1723 | (long) read_register (VBR_REGNUM)); | |
1724 | ||
617daa0e CV |
1725 | printf_filtered (" DSR=%08lx", (long) read_register (DSR_REGNUM)); |
1726 | ||
1727 | printf_filtered | |
1728 | ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1729 | (long) read_register (0), (long) read_register (1), | |
1730 | (long) read_register (2), (long) read_register (3), | |
1731 | (long) read_register (4), (long) read_register (5), | |
1732 | (long) read_register (6), (long) read_register (7)); | |
cc17453a | 1733 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
617daa0e CV |
1734 | (long) read_register (8), (long) read_register (9), |
1735 | (long) read_register (10), (long) read_register (11), | |
1736 | (long) read_register (12), (long) read_register (13), | |
1737 | (long) read_register (14), (long) read_register (15)); | |
1738 | ||
1739 | printf_filtered | |
1740 | ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n", | |
1741 | (long) read_register (A0G_REGNUM) & 0xff, | |
1742 | (long) read_register (A0_REGNUM), (long) read_register (M0_REGNUM), | |
1743 | (long) read_register (X0_REGNUM), (long) read_register (Y0_REGNUM), | |
1744 | (long) read_register (RS_REGNUM), (long) read_register (MOD_REGNUM)); | |
cc17453a | 1745 | printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n", |
f2ea0907 CV |
1746 | (long) read_register (A1G_REGNUM) & 0xff, |
1747 | (long) read_register (A1_REGNUM), | |
1748 | (long) read_register (M1_REGNUM), | |
1749 | (long) read_register (X1_REGNUM), | |
1750 | (long) read_register (Y1_REGNUM), | |
1751 | (long) read_register (RE_REGNUM)); | |
cc17453a EZ |
1752 | } |
1753 | ||
a78f21af AC |
1754 | static void |
1755 | sh_show_regs_command (char *args, int from_tty) | |
53116e27 EZ |
1756 | { |
1757 | if (sh_show_regs) | |
617daa0e | 1758 | (*sh_show_regs) (); |
53116e27 EZ |
1759 | } |
1760 | ||
da962468 CV |
1761 | static struct type * |
1762 | sh_sh2a_register_type (struct gdbarch *gdbarch, int reg_nr) | |
1763 | { | |
1764 | if ((reg_nr >= FP0_REGNUM | |
1765 | && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM)) | |
1766 | return builtin_type_float; | |
1767 | else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM) | |
1768 | return builtin_type_double; | |
1769 | else | |
1770 | return builtin_type_int; | |
1771 | } | |
1772 | ||
cc17453a EZ |
1773 | /* Return the GDB type object for the "standard" data type |
1774 | of data in register N. */ | |
cc17453a | 1775 | static struct type * |
48db5a3c | 1776 | sh_sh3e_register_type (struct gdbarch *gdbarch, int reg_nr) |
cc17453a EZ |
1777 | { |
1778 | if ((reg_nr >= FP0_REGNUM | |
617daa0e | 1779 | && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM)) |
cc17453a | 1780 | return builtin_type_float; |
8db62801 | 1781 | else |
cc17453a EZ |
1782 | return builtin_type_int; |
1783 | } | |
1784 | ||
7f4dbe94 EZ |
1785 | static struct type * |
1786 | sh_sh4_build_float_register_type (int high) | |
1787 | { | |
1788 | struct type *temp; | |
1789 | ||
1790 | temp = create_range_type (NULL, builtin_type_int, 0, high); | |
1791 | return create_array_type (NULL, builtin_type_float, temp); | |
1792 | } | |
1793 | ||
53116e27 | 1794 | static struct type * |
48db5a3c | 1795 | sh_sh4_register_type (struct gdbarch *gdbarch, int reg_nr) |
53116e27 EZ |
1796 | { |
1797 | if ((reg_nr >= FP0_REGNUM | |
617daa0e | 1798 | && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM)) |
53116e27 | 1799 | return builtin_type_float; |
617daa0e | 1800 | else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM) |
53116e27 | 1801 | return builtin_type_double; |
617daa0e | 1802 | else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM) |
53116e27 EZ |
1803 | return sh_sh4_build_float_register_type (3); |
1804 | else | |
1805 | return builtin_type_int; | |
1806 | } | |
1807 | ||
cc17453a | 1808 | static struct type * |
48db5a3c | 1809 | sh_default_register_type (struct gdbarch *gdbarch, int reg_nr) |
cc17453a EZ |
1810 | { |
1811 | return builtin_type_int; | |
1812 | } | |
1813 | ||
fb409745 EZ |
1814 | /* On the sh4, the DRi pseudo registers are problematic if the target |
1815 | is little endian. When the user writes one of those registers, for | |
1816 | instance with 'ser var $dr0=1', we want the double to be stored | |
1817 | like this: | |
1818 | fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f | |
1819 | fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00 | |
1820 | ||
1821 | This corresponds to little endian byte order & big endian word | |
1822 | order. However if we let gdb write the register w/o conversion, it | |
1823 | will write fr0 and fr1 this way: | |
1824 | fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00 | |
1825 | fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f | |
1826 | because it will consider fr0 and fr1 as a single LE stretch of memory. | |
1827 | ||
1828 | To achieve what we want we must force gdb to store things in | |
1829 | floatformat_ieee_double_littlebyte_bigword (which is defined in | |
1830 | include/floatformat.h and libiberty/floatformat.c. | |
1831 | ||
1832 | In case the target is big endian, there is no problem, the | |
1833 | raw bytes will look like: | |
1834 | fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00 | |
1835 | fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00 | |
1836 | ||
1837 | The other pseudo registers (the FVs) also don't pose a problem | |
1838 | because they are stored as 4 individual FP elements. */ | |
1839 | ||
7bd872fe | 1840 | static void |
b66ba949 CV |
1841 | sh_register_convert_to_virtual (int regnum, struct type *type, |
1842 | char *from, char *to) | |
55ff77ac | 1843 | { |
617daa0e | 1844 | if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM) |
283150cd EZ |
1845 | { |
1846 | DOUBLEST val; | |
617daa0e CV |
1847 | floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, |
1848 | from, &val); | |
55ff77ac | 1849 | store_typed_floating (to, type, val); |
283150cd EZ |
1850 | } |
1851 | else | |
617daa0e CV |
1852 | error |
1853 | ("sh_register_convert_to_virtual called with non DR register number"); | |
283150cd EZ |
1854 | } |
1855 | ||
1856 | static void | |
b66ba949 CV |
1857 | sh_register_convert_to_raw (struct type *type, int regnum, |
1858 | const void *from, void *to) | |
283150cd | 1859 | { |
617daa0e | 1860 | if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM) |
283150cd | 1861 | { |
48db5a3c | 1862 | DOUBLEST val = extract_typed_floating (from, type); |
617daa0e CV |
1863 | floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword, |
1864 | &val, to); | |
283150cd EZ |
1865 | } |
1866 | else | |
617daa0e | 1867 | error ("sh_register_convert_to_raw called with non DR register number"); |
283150cd EZ |
1868 | } |
1869 | ||
1c0159e0 CV |
1870 | /* For vectors of 4 floating point registers. */ |
1871 | static int | |
1872 | fv_reg_base_num (int fv_regnum) | |
1873 | { | |
1874 | int fp_regnum; | |
1875 | ||
617daa0e | 1876 | fp_regnum = FP0_REGNUM + (fv_regnum - FV0_REGNUM) * 4; |
1c0159e0 CV |
1877 | return fp_regnum; |
1878 | } | |
1879 | ||
1880 | /* For double precision floating point registers, i.e 2 fp regs.*/ | |
1881 | static int | |
1882 | dr_reg_base_num (int dr_regnum) | |
1883 | { | |
1884 | int fp_regnum; | |
1885 | ||
617daa0e | 1886 | fp_regnum = FP0_REGNUM + (dr_regnum - DR0_REGNUM) * 2; |
1c0159e0 CV |
1887 | return fp_regnum; |
1888 | } | |
1889 | ||
a78f21af | 1890 | static void |
d8124050 AC |
1891 | sh_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, |
1892 | int reg_nr, void *buffer) | |
53116e27 EZ |
1893 | { |
1894 | int base_regnum, portion; | |
d9d9c31f | 1895 | char temp_buffer[MAX_REGISTER_SIZE]; |
53116e27 | 1896 | |
9bed62d7 CV |
1897 | if (reg_nr == PSEUDO_BANK_REGNUM) |
1898 | regcache_raw_read (regcache, BANK_REGNUM, buffer); | |
1899 | else | |
617daa0e | 1900 | if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM) |
7bd872fe EZ |
1901 | { |
1902 | base_regnum = dr_reg_base_num (reg_nr); | |
1903 | ||
617daa0e | 1904 | /* Build the value in the provided buffer. */ |
7bd872fe EZ |
1905 | /* Read the real regs for which this one is an alias. */ |
1906 | for (portion = 0; portion < 2; portion++) | |
617daa0e | 1907 | regcache_raw_read (regcache, base_regnum + portion, |
0818c12a | 1908 | (temp_buffer |
617daa0e CV |
1909 | + register_size (gdbarch, |
1910 | base_regnum) * portion)); | |
7bd872fe | 1911 | /* We must pay attention to the endiannes. */ |
b66ba949 CV |
1912 | sh_register_convert_to_virtual (reg_nr, |
1913 | gdbarch_register_type (gdbarch, reg_nr), | |
1914 | temp_buffer, buffer); | |
7bd872fe | 1915 | } |
617daa0e | 1916 | else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM) |
53116e27 | 1917 | { |
7bd872fe EZ |
1918 | base_regnum = fv_reg_base_num (reg_nr); |
1919 | ||
1920 | /* Read the real regs for which this one is an alias. */ | |
1921 | for (portion = 0; portion < 4; portion++) | |
617daa0e | 1922 | regcache_raw_read (regcache, base_regnum + portion, |
d8124050 | 1923 | ((char *) buffer |
617daa0e CV |
1924 | + register_size (gdbarch, |
1925 | base_regnum) * portion)); | |
53116e27 EZ |
1926 | } |
1927 | } | |
1928 | ||
a78f21af | 1929 | static void |
d8124050 AC |
1930 | sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, |
1931 | int reg_nr, const void *buffer) | |
53116e27 EZ |
1932 | { |
1933 | int base_regnum, portion; | |
d9d9c31f | 1934 | char temp_buffer[MAX_REGISTER_SIZE]; |
53116e27 | 1935 | |
9bed62d7 CV |
1936 | if (reg_nr == PSEUDO_BANK_REGNUM) |
1937 | { | |
1938 | /* When the bank register is written to, the whole register bank | |
1939 | is switched and all values in the bank registers must be read | |
1940 | from the target/sim again. We're just invalidating the regcache | |
1941 | so that a re-read happens next time it's necessary. */ | |
1942 | int bregnum; | |
1943 | ||
1944 | regcache_raw_write (regcache, BANK_REGNUM, buffer); | |
1945 | for (bregnum = R0_BANK0_REGNUM; bregnum < MACLB_REGNUM; ++bregnum) | |
1946 | set_register_cached (bregnum, 0); | |
1947 | } | |
1948 | else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM) | |
53116e27 EZ |
1949 | { |
1950 | base_regnum = dr_reg_base_num (reg_nr); | |
1951 | ||
7bd872fe | 1952 | /* We must pay attention to the endiannes. */ |
b66ba949 CV |
1953 | sh_register_convert_to_raw (gdbarch_register_type (gdbarch, reg_nr), |
1954 | reg_nr, buffer, temp_buffer); | |
7bd872fe | 1955 | |
53116e27 EZ |
1956 | /* Write the real regs for which this one is an alias. */ |
1957 | for (portion = 0; portion < 2; portion++) | |
617daa0e | 1958 | regcache_raw_write (regcache, base_regnum + portion, |
0818c12a | 1959 | (temp_buffer |
617daa0e CV |
1960 | + register_size (gdbarch, |
1961 | base_regnum) * portion)); | |
53116e27 | 1962 | } |
617daa0e | 1963 | else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM) |
53116e27 EZ |
1964 | { |
1965 | base_regnum = fv_reg_base_num (reg_nr); | |
1966 | ||
1967 | /* Write the real regs for which this one is an alias. */ | |
1968 | for (portion = 0; portion < 4; portion++) | |
d8124050 AC |
1969 | regcache_raw_write (regcache, base_regnum + portion, |
1970 | ((char *) buffer | |
617daa0e CV |
1971 | + register_size (gdbarch, |
1972 | base_regnum) * portion)); | |
53116e27 EZ |
1973 | } |
1974 | } | |
1975 | ||
3bbfbb92 | 1976 | /* Floating point vector of 4 float registers. */ |
53116e27 | 1977 | static void |
48db5a3c CV |
1978 | do_fv_register_info (struct gdbarch *gdbarch, struct ui_file *file, |
1979 | int fv_regnum) | |
53116e27 EZ |
1980 | { |
1981 | int first_fp_reg_num = fv_reg_base_num (fv_regnum); | |
617daa0e CV |
1982 | fprintf_filtered (file, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n", |
1983 | fv_regnum - FV0_REGNUM, | |
1984 | (int) read_register (first_fp_reg_num), | |
1985 | (int) read_register (first_fp_reg_num + 1), | |
1986 | (int) read_register (first_fp_reg_num + 2), | |
1987 | (int) read_register (first_fp_reg_num + 3)); | |
53116e27 EZ |
1988 | } |
1989 | ||
3bbfbb92 | 1990 | /* Double precision registers. */ |
53116e27 | 1991 | static void |
48db5a3c CV |
1992 | do_dr_register_info (struct gdbarch *gdbarch, struct ui_file *file, |
1993 | int dr_regnum) | |
53116e27 EZ |
1994 | { |
1995 | int first_fp_reg_num = dr_reg_base_num (dr_regnum); | |
1996 | ||
617daa0e CV |
1997 | fprintf_filtered (file, "dr%d\t0x%08x%08x\n", |
1998 | dr_regnum - DR0_REGNUM, | |
53116e27 EZ |
1999 | (int) read_register (first_fp_reg_num), |
2000 | (int) read_register (first_fp_reg_num + 1)); | |
2001 | } | |
da962468 CV |
2002 | static void |
2003 | do_bank_register_info (struct gdbarch *gdbarch, struct ui_file *file) | |
2004 | { | |
2005 | fprintf_filtered (file, "bank %d\n", | |
2006 | (int) read_register (BANK_REGNUM)); | |
2007 | } | |
53116e27 EZ |
2008 | |
2009 | static void | |
48db5a3c CV |
2010 | sh_print_pseudo_register (struct gdbarch *gdbarch, struct ui_file *file, |
2011 | int regnum) | |
53116e27 EZ |
2012 | { |
2013 | if (regnum < NUM_REGS || regnum >= NUM_REGS + NUM_PSEUDO_REGS) | |
8e65ff28 AC |
2014 | internal_error (__FILE__, __LINE__, |
2015 | "Invalid pseudo register number %d\n", regnum); | |
da962468 CV |
2016 | else if (regnum == PSEUDO_BANK_REGNUM) |
2017 | do_bank_register_info (gdbarch, file); | |
617daa0e | 2018 | else if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM) |
48db5a3c | 2019 | do_dr_register_info (gdbarch, file, regnum); |
617daa0e | 2020 | else if (regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM) |
48db5a3c | 2021 | do_fv_register_info (gdbarch, file, regnum); |
53116e27 EZ |
2022 | } |
2023 | ||
53116e27 | 2024 | static void |
48db5a3c | 2025 | sh_do_fp_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum) |
53116e27 EZ |
2026 | { /* do values for FP (float) regs */ |
2027 | char *raw_buffer; | |
617daa0e | 2028 | double flt; /* double extracted from raw hex data */ |
53116e27 EZ |
2029 | int inv; |
2030 | int j; | |
2031 | ||
2032 | /* Allocate space for the float. */ | |
48db5a3c | 2033 | raw_buffer = (char *) alloca (register_size (gdbarch, FP0_REGNUM)); |
53116e27 EZ |
2034 | |
2035 | /* Get the data in raw format. */ | |
b04f3ab4 | 2036 | if (!frame_register_read (get_selected_frame (NULL), regnum, raw_buffer)) |
53116e27 EZ |
2037 | error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum)); |
2038 | ||
617daa0e | 2039 | /* Get the register as a number */ |
53116e27 EZ |
2040 | flt = unpack_double (builtin_type_float, raw_buffer, &inv); |
2041 | ||
2042 | /* Print the name and some spaces. */ | |
48db5a3c CV |
2043 | fputs_filtered (REGISTER_NAME (regnum), file); |
2044 | print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file); | |
53116e27 EZ |
2045 | |
2046 | /* Print the value. */ | |
93d56215 | 2047 | if (inv) |
48db5a3c | 2048 | fprintf_filtered (file, "<invalid float>"); |
93d56215 | 2049 | else |
48db5a3c | 2050 | fprintf_filtered (file, "%-10.9g", flt); |
53116e27 EZ |
2051 | |
2052 | /* Print the fp register as hex. */ | |
48db5a3c CV |
2053 | fprintf_filtered (file, "\t(raw 0x"); |
2054 | for (j = 0; j < register_size (gdbarch, regnum); j++) | |
53116e27 | 2055 | { |
221c12ff AC |
2056 | int idx = (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
2057 | ? j | |
2058 | : register_size (gdbarch, regnum) - 1 - j); | |
48db5a3c | 2059 | fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[idx]); |
53116e27 | 2060 | } |
48db5a3c CV |
2061 | fprintf_filtered (file, ")"); |
2062 | fprintf_filtered (file, "\n"); | |
53116e27 EZ |
2063 | } |
2064 | ||
2065 | static void | |
48db5a3c | 2066 | sh_do_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum) |
53116e27 | 2067 | { |
123a958e | 2068 | char raw_buffer[MAX_REGISTER_SIZE]; |
53116e27 | 2069 | |
48db5a3c CV |
2070 | fputs_filtered (REGISTER_NAME (regnum), file); |
2071 | print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file); | |
53116e27 EZ |
2072 | |
2073 | /* Get the data in raw format. */ | |
b04f3ab4 | 2074 | if (!frame_register_read (get_selected_frame (NULL), regnum, raw_buffer)) |
48db5a3c | 2075 | fprintf_filtered (file, "*value not available*\n"); |
617daa0e | 2076 | |
48db5a3c CV |
2077 | val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0, |
2078 | file, 'x', 1, 0, Val_pretty_default); | |
2079 | fprintf_filtered (file, "\t"); | |
2080 | val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0, | |
2081 | file, 0, 1, 0, Val_pretty_default); | |
2082 | fprintf_filtered (file, "\n"); | |
53116e27 EZ |
2083 | } |
2084 | ||
2085 | static void | |
48db5a3c | 2086 | sh_print_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum) |
53116e27 EZ |
2087 | { |
2088 | if (regnum < 0 || regnum >= NUM_REGS + NUM_PSEUDO_REGS) | |
8e65ff28 AC |
2089 | internal_error (__FILE__, __LINE__, |
2090 | "Invalid register number %d\n", regnum); | |
53116e27 | 2091 | |
e30839fe | 2092 | else if (regnum >= 0 && regnum < NUM_REGS) |
53116e27 | 2093 | { |
617daa0e CV |
2094 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == |
2095 | TYPE_CODE_FLT) | |
48db5a3c | 2096 | sh_do_fp_register (gdbarch, file, regnum); /* FP regs */ |
53116e27 | 2097 | else |
48db5a3c | 2098 | sh_do_register (gdbarch, file, regnum); /* All other regs */ |
53116e27 EZ |
2099 | } |
2100 | ||
2101 | else if (regnum < NUM_REGS + NUM_PSEUDO_REGS) | |
48db5a3c | 2102 | { |
55ff77ac | 2103 | sh_print_pseudo_register (gdbarch, file, regnum); |
48db5a3c | 2104 | } |
53116e27 EZ |
2105 | } |
2106 | ||
a78f21af | 2107 | static void |
48db5a3c CV |
2108 | sh_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
2109 | struct frame_info *frame, int regnum, int fpregs) | |
53116e27 EZ |
2110 | { |
2111 | if (regnum != -1) /* do one specified register */ | |
2112 | { | |
2113 | if (*(REGISTER_NAME (regnum)) == '\0') | |
2114 | error ("Not a valid register for the current processor type"); | |
2115 | ||
48db5a3c | 2116 | sh_print_register (gdbarch, file, regnum); |
53116e27 EZ |
2117 | } |
2118 | else | |
2119 | /* do all (or most) registers */ | |
2120 | { | |
3930f270 | 2121 | for (regnum = 0; regnum < NUM_REGS; ++regnum) |
53116e27 EZ |
2122 | { |
2123 | /* If the register name is empty, it is undefined for this | |
2124 | processor, so don't display anything. */ | |
2125 | if (REGISTER_NAME (regnum) == NULL | |
2126 | || *(REGISTER_NAME (regnum)) == '\0') | |
3930f270 | 2127 | continue; |
53116e27 | 2128 | |
617daa0e CV |
2129 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == |
2130 | TYPE_CODE_FLT) | |
53116e27 | 2131 | { |
3930f270 | 2132 | /* true for "INFO ALL-REGISTERS" command */ |
53116e27 | 2133 | if (fpregs) |
3930f270 | 2134 | sh_do_fp_register (gdbarch, file, regnum); /* FP regs */ |
53116e27 EZ |
2135 | } |
2136 | else | |
3930f270 | 2137 | sh_do_register (gdbarch, file, regnum); /* All other regs */ |
53116e27 EZ |
2138 | } |
2139 | ||
da962468 CV |
2140 | if (regnum == PSEUDO_BANK_REGNUM |
2141 | && REGISTER_NAME (regnum) | |
2142 | && *REGISTER_NAME (regnum)) | |
2143 | sh_print_pseudo_register (gdbarch, file, regnum++); | |
2144 | ||
53116e27 EZ |
2145 | if (fpregs) |
2146 | while (regnum < NUM_REGS + NUM_PSEUDO_REGS) | |
2147 | { | |
55ff77ac | 2148 | sh_print_pseudo_register (gdbarch, file, regnum); |
53116e27 EZ |
2149 | regnum++; |
2150 | } | |
2151 | } | |
2152 | } | |
2153 | ||
1a8629c7 MS |
2154 | /* Fetch (and possibly build) an appropriate link_map_offsets structure |
2155 | for native i386 linux targets using the struct offsets defined in | |
2156 | link.h (but without actual reference to that file). | |
2157 | ||
2158 | This makes it possible to access i386-linux shared libraries from | |
2159 | a gdb that was not built on an i386-linux host (for cross debugging). | |
2160 | */ | |
2161 | ||
2162 | struct link_map_offsets * | |
2163 | sh_linux_svr4_fetch_link_map_offsets (void) | |
2164 | { | |
2165 | static struct link_map_offsets lmo; | |
2166 | static struct link_map_offsets *lmp = 0; | |
2167 | ||
2168 | if (lmp == 0) | |
2169 | { | |
2170 | lmp = &lmo; | |
2171 | ||
2172 | lmo.r_debug_size = 8; /* 20 not actual size but all we need */ | |
2173 | ||
2174 | lmo.r_map_offset = 4; | |
617daa0e | 2175 | lmo.r_map_size = 4; |
1a8629c7 MS |
2176 | |
2177 | lmo.link_map_size = 20; /* 552 not actual size but all we need */ | |
2178 | ||
2179 | lmo.l_addr_offset = 0; | |
617daa0e | 2180 | lmo.l_addr_size = 4; |
1a8629c7 MS |
2181 | |
2182 | lmo.l_name_offset = 4; | |
617daa0e | 2183 | lmo.l_name_size = 4; |
1a8629c7 MS |
2184 | |
2185 | lmo.l_next_offset = 12; | |
617daa0e | 2186 | lmo.l_next_size = 4; |
1a8629c7 MS |
2187 | |
2188 | lmo.l_prev_offset = 16; | |
617daa0e | 2189 | lmo.l_prev_size = 4; |
1a8629c7 MS |
2190 | } |
2191 | ||
617daa0e | 2192 | return lmp; |
1a8629c7 | 2193 | } |
1a8629c7 | 2194 | |
2f14585c JR |
2195 | static int |
2196 | sh_dsp_register_sim_regno (int nr) | |
2197 | { | |
2198 | if (legacy_register_sim_regno (nr) < 0) | |
2199 | return legacy_register_sim_regno (nr); | |
f2ea0907 CV |
2200 | if (nr >= DSR_REGNUM && nr <= Y1_REGNUM) |
2201 | return nr - DSR_REGNUM + SIM_SH_DSR_REGNUM; | |
2202 | if (nr == MOD_REGNUM) | |
2f14585c | 2203 | return SIM_SH_MOD_REGNUM; |
f2ea0907 | 2204 | if (nr == RS_REGNUM) |
2f14585c | 2205 | return SIM_SH_RS_REGNUM; |
f2ea0907 | 2206 | if (nr == RE_REGNUM) |
2f14585c | 2207 | return SIM_SH_RE_REGNUM; |
76cd2bd9 CV |
2208 | if (nr >= DSP_R0_BANK_REGNUM && nr <= DSP_R7_BANK_REGNUM) |
2209 | return nr - DSP_R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM; | |
2f14585c JR |
2210 | return nr; |
2211 | } | |
1c0159e0 | 2212 | |
da962468 CV |
2213 | static int |
2214 | sh_sh2a_register_sim_regno (int nr) | |
2215 | { | |
2216 | switch (nr) | |
2217 | { | |
2218 | case TBR_REGNUM: | |
2219 | return SIM_SH_TBR_REGNUM; | |
2220 | case IBNR_REGNUM: | |
2221 | return SIM_SH_IBNR_REGNUM; | |
2222 | case IBCR_REGNUM: | |
2223 | return SIM_SH_IBCR_REGNUM; | |
2224 | case BANK_REGNUM: | |
2225 | return SIM_SH_BANK_REGNUM; | |
2226 | case MACLB_REGNUM: | |
2227 | return SIM_SH_BANK_MACL_REGNUM; | |
2228 | case GBRB_REGNUM: | |
2229 | return SIM_SH_BANK_GBR_REGNUM; | |
2230 | case PRB_REGNUM: | |
2231 | return SIM_SH_BANK_PR_REGNUM; | |
2232 | case IVNB_REGNUM: | |
2233 | return SIM_SH_BANK_IVN_REGNUM; | |
2234 | case MACHB_REGNUM: | |
2235 | return SIM_SH_BANK_MACH_REGNUM; | |
2236 | default: | |
2237 | break; | |
2238 | } | |
2239 | return legacy_register_sim_regno (nr); | |
2240 | } | |
2241 | ||
1c0159e0 CV |
2242 | static struct sh_frame_cache * |
2243 | sh_alloc_frame_cache (void) | |
2244 | { | |
2245 | struct sh_frame_cache *cache; | |
2246 | int i; | |
2247 | ||
2248 | cache = FRAME_OBSTACK_ZALLOC (struct sh_frame_cache); | |
2249 | ||
2250 | /* Base address. */ | |
2251 | cache->base = 0; | |
2252 | cache->saved_sp = 0; | |
2253 | cache->sp_offset = 0; | |
2254 | cache->pc = 0; | |
2255 | ||
2256 | /* Frameless until proven otherwise. */ | |
2257 | cache->uses_fp = 0; | |
617daa0e | 2258 | |
1c0159e0 CV |
2259 | /* Saved registers. We initialize these to -1 since zero is a valid |
2260 | offset (that's where fp is supposed to be stored). */ | |
2261 | for (i = 0; i < SH_NUM_REGS; i++) | |
2262 | { | |
2263 | cache->saved_regs[i] = -1; | |
2264 | } | |
617daa0e | 2265 | |
1c0159e0 | 2266 | return cache; |
617daa0e | 2267 | } |
1c0159e0 CV |
2268 | |
2269 | static struct sh_frame_cache * | |
2270 | sh_frame_cache (struct frame_info *next_frame, void **this_cache) | |
2271 | { | |
2272 | struct sh_frame_cache *cache; | |
2273 | CORE_ADDR current_pc; | |
2274 | int i; | |
2275 | ||
2276 | if (*this_cache) | |
2277 | return *this_cache; | |
2278 | ||
2279 | cache = sh_alloc_frame_cache (); | |
2280 | *this_cache = cache; | |
2281 | ||
2282 | /* In principle, for normal frames, fp holds the frame pointer, | |
2283 | which holds the base address for the current stack frame. | |
2284 | However, for functions that don't need it, the frame pointer is | |
2285 | optional. For these "frameless" functions the frame pointer is | |
2286 | actually the frame pointer of the calling frame. */ | |
2287 | cache->base = frame_unwind_register_unsigned (next_frame, FP_REGNUM); | |
2288 | if (cache->base == 0) | |
2289 | return cache; | |
2290 | ||
2291 | cache->pc = frame_func_unwind (next_frame); | |
2292 | current_pc = frame_pc_unwind (next_frame); | |
2293 | if (cache->pc != 0) | |
2294 | sh_analyze_prologue (cache->pc, current_pc, cache); | |
617daa0e | 2295 | |
1c0159e0 CV |
2296 | if (!cache->uses_fp) |
2297 | { | |
2298 | /* We didn't find a valid frame, which means that CACHE->base | |
2299 | currently holds the frame pointer for our calling frame. If | |
2300 | we're at the start of a function, or somewhere half-way its | |
2301 | prologue, the function's frame probably hasn't been fully | |
2302 | setup yet. Try to reconstruct the base address for the stack | |
2303 | frame by looking at the stack pointer. For truly "frameless" | |
2304 | functions this might work too. */ | |
2305 | cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM); | |
2306 | } | |
2307 | ||
2308 | /* Now that we have the base address for the stack frame we can | |
2309 | calculate the value of sp in the calling frame. */ | |
2310 | cache->saved_sp = cache->base + cache->sp_offset; | |
2311 | ||
2312 | /* Adjust all the saved registers such that they contain addresses | |
2313 | instead of offsets. */ | |
2314 | for (i = 0; i < SH_NUM_REGS; i++) | |
2315 | if (cache->saved_regs[i] != -1) | |
2316 | cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i] - 4; | |
2317 | ||
2318 | return cache; | |
2319 | } | |
2320 | ||
2321 | static void | |
2322 | sh_frame_prev_register (struct frame_info *next_frame, void **this_cache, | |
2323 | int regnum, int *optimizedp, | |
2324 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
2325 | int *realnump, void *valuep) | |
2326 | { | |
2327 | struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache); | |
2328 | ||
2329 | gdb_assert (regnum >= 0); | |
2330 | ||
2331 | if (regnum == SP_REGNUM && cache->saved_sp) | |
2332 | { | |
2333 | *optimizedp = 0; | |
2334 | *lvalp = not_lval; | |
2335 | *addrp = 0; | |
2336 | *realnump = -1; | |
2337 | if (valuep) | |
617daa0e CV |
2338 | { |
2339 | /* Store the value. */ | |
2340 | store_unsigned_integer (valuep, 4, cache->saved_sp); | |
2341 | } | |
1c0159e0 CV |
2342 | return; |
2343 | } | |
2344 | ||
2345 | /* The PC of the previous frame is stored in the PR register of | |
2346 | the current frame. Frob regnum so that we pull the value from | |
2347 | the correct place. */ | |
2348 | if (regnum == PC_REGNUM) | |
2349 | regnum = PR_REGNUM; | |
2350 | ||
2351 | if (regnum < SH_NUM_REGS && cache->saved_regs[regnum] != -1) | |
2352 | { | |
2353 | *optimizedp = 0; | |
2354 | *lvalp = lval_memory; | |
2355 | *addrp = cache->saved_regs[regnum]; | |
2356 | *realnump = -1; | |
2357 | if (valuep) | |
617daa0e CV |
2358 | { |
2359 | /* Read the value in from memory. */ | |
2360 | read_memory (*addrp, valuep, | |
2361 | register_size (current_gdbarch, regnum)); | |
2362 | } | |
1c0159e0 CV |
2363 | return; |
2364 | } | |
2365 | ||
00b25ff3 AC |
2366 | *optimizedp = 0; |
2367 | *lvalp = lval_register; | |
2368 | *addrp = 0; | |
2369 | *realnump = regnum; | |
2370 | if (valuep) | |
2371 | frame_unwind_register (next_frame, (*realnump), valuep); | |
1c0159e0 CV |
2372 | } |
2373 | ||
2374 | static void | |
2375 | sh_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
617daa0e CV |
2376 | struct frame_id *this_id) |
2377 | { | |
1c0159e0 CV |
2378 | struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache); |
2379 | ||
2380 | /* This marks the outermost frame. */ | |
2381 | if (cache->base == 0) | |
2382 | return; | |
2383 | ||
2384 | *this_id = frame_id_build (cache->saved_sp, cache->pc); | |
617daa0e | 2385 | } |
1c0159e0 | 2386 | |
617daa0e | 2387 | static const struct frame_unwind sh_frame_unwind = { |
1c0159e0 CV |
2388 | NORMAL_FRAME, |
2389 | sh_frame_this_id, | |
2390 | sh_frame_prev_register | |
2391 | }; | |
2392 | ||
2393 | static const struct frame_unwind * | |
2394 | sh_frame_sniffer (struct frame_info *next_frame) | |
2395 | { | |
2396 | return &sh_frame_unwind; | |
2397 | } | |
2398 | ||
2399 | static CORE_ADDR | |
2400 | sh_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
2401 | { | |
2402 | return frame_unwind_register_unsigned (next_frame, SP_REGNUM); | |
2403 | } | |
2404 | ||
2405 | static CORE_ADDR | |
2406 | sh_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
2407 | { | |
2408 | return frame_unwind_register_unsigned (next_frame, PC_REGNUM); | |
2409 | } | |
2410 | ||
2411 | static struct frame_id | |
2412 | sh_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
2413 | { | |
2414 | return frame_id_build (sh_unwind_sp (gdbarch, next_frame), | |
2415 | frame_pc_unwind (next_frame)); | |
2416 | } | |
2417 | ||
2418 | static CORE_ADDR | |
2419 | sh_frame_base_address (struct frame_info *next_frame, void **this_cache) | |
617daa0e | 2420 | { |
1c0159e0 | 2421 | struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache); |
617daa0e | 2422 | |
1c0159e0 CV |
2423 | return cache->base; |
2424 | } | |
617daa0e CV |
2425 | |
2426 | static const struct frame_base sh_frame_base = { | |
1c0159e0 CV |
2427 | &sh_frame_unwind, |
2428 | sh_frame_base_address, | |
2429 | sh_frame_base_address, | |
2430 | sh_frame_base_address | |
617daa0e | 2431 | }; |
1c0159e0 CV |
2432 | |
2433 | /* The epilogue is defined here as the area at the end of a function, | |
2434 | either on the `ret' instruction itself or after an instruction which | |
2435 | destroys the function's stack frame. */ | |
2436 | static int | |
2437 | sh_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
2438 | { | |
2439 | CORE_ADDR func_addr = 0, func_end = 0; | |
2440 | ||
2441 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
2442 | { | |
2443 | ULONGEST inst; | |
2444 | /* The sh epilogue is max. 14 bytes long. Give another 14 bytes | |
2445 | for a nop and some fixed data (e.g. big offsets) which are | |
617daa0e CV |
2446 | unfortunately also treated as part of the function (which |
2447 | means, they are below func_end. */ | |
1c0159e0 CV |
2448 | CORE_ADDR addr = func_end - 28; |
2449 | if (addr < func_addr + 4) | |
617daa0e | 2450 | addr = func_addr + 4; |
1c0159e0 CV |
2451 | if (pc < addr) |
2452 | return 0; | |
2453 | ||
2454 | /* First search forward until hitting an rts. */ | |
2455 | while (addr < func_end | |
617daa0e | 2456 | && !IS_RTS (read_memory_unsigned_integer (addr, 2))) |
1c0159e0 CV |
2457 | addr += 2; |
2458 | if (addr >= func_end) | |
617daa0e | 2459 | return 0; |
1c0159e0 CV |
2460 | |
2461 | /* At this point we should find a mov.l @r15+,r14 instruction, | |
2462 | either before or after the rts. If not, then the function has | |
617daa0e | 2463 | probably no "normal" epilogue and we bail out here. */ |
1c0159e0 CV |
2464 | inst = read_memory_unsigned_integer (addr - 2, 2); |
2465 | if (IS_RESTORE_FP (read_memory_unsigned_integer (addr - 2, 2))) | |
617daa0e | 2466 | addr -= 2; |
1c0159e0 CV |
2467 | else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr + 2, 2))) |
2468 | return 0; | |
2469 | ||
1c0159e0 | 2470 | inst = read_memory_unsigned_integer (addr - 2, 2); |
03131d99 CV |
2471 | |
2472 | /* Step over possible lds.l @r15+,macl. */ | |
2473 | if (IS_MACL_LDS (inst)) | |
2474 | { | |
2475 | addr -= 2; | |
2476 | inst = read_memory_unsigned_integer (addr - 2, 2); | |
2477 | } | |
2478 | ||
2479 | /* Step over possible lds.l @r15+,pr. */ | |
1c0159e0 | 2480 | if (IS_LDS (inst)) |
617daa0e | 2481 | { |
1c0159e0 CV |
2482 | addr -= 2; |
2483 | inst = read_memory_unsigned_integer (addr - 2, 2); | |
2484 | } | |
2485 | ||
2486 | /* Step over possible mov r14,r15. */ | |
2487 | if (IS_MOV_FP_SP (inst)) | |
617daa0e | 2488 | { |
1c0159e0 CV |
2489 | addr -= 2; |
2490 | inst = read_memory_unsigned_integer (addr - 2, 2); | |
2491 | } | |
2492 | ||
2493 | /* Now check for FP adjustments, using add #imm,r14 or add rX, r14 | |
2494 | instructions. */ | |
2495 | while (addr > func_addr + 4 | |
617daa0e | 2496 | && (IS_ADD_REG_TO_FP (inst) || IS_ADD_IMM_FP (inst))) |
1c0159e0 CV |
2497 | { |
2498 | addr -= 2; | |
2499 | inst = read_memory_unsigned_integer (addr - 2, 2); | |
2500 | } | |
2501 | ||
03131d99 CV |
2502 | /* On SH2a check if the previous instruction was perhaps a MOVI20. |
2503 | That's allowed for the epilogue. */ | |
2504 | if ((gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a | |
2505 | || gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a_nofpu) | |
2506 | && addr > func_addr + 6 | |
2507 | && IS_MOVI20 (read_memory_unsigned_integer (addr - 4, 2))) | |
2508 | addr -= 4; | |
2509 | ||
1c0159e0 CV |
2510 | if (pc >= addr) |
2511 | return 1; | |
2512 | } | |
2513 | return 0; | |
2514 | } | |
2515 | ||
cc17453a EZ |
2516 | static gdbarch_init_ftype sh_gdbarch_init; |
2517 | ||
2518 | static struct gdbarch * | |
fba45db2 | 2519 | sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
cc17453a | 2520 | { |
cc17453a | 2521 | struct gdbarch *gdbarch; |
d658f924 | 2522 | |
55ff77ac CV |
2523 | sh_show_regs = sh_generic_show_regs; |
2524 | switch (info.bfd_arch_info->mach) | |
2525 | { | |
617daa0e CV |
2526 | case bfd_mach_sh2e: |
2527 | sh_show_regs = sh2e_show_regs; | |
2528 | break; | |
da962468 CV |
2529 | case bfd_mach_sh2a: |
2530 | sh_show_regs = sh2a_show_regs; | |
2531 | break; | |
2532 | case bfd_mach_sh2a_nofpu: | |
2533 | sh_show_regs = sh2a_nofpu_show_regs; | |
2534 | break; | |
617daa0e CV |
2535 | case bfd_mach_sh_dsp: |
2536 | sh_show_regs = sh_dsp_show_regs; | |
2537 | break; | |
55ff77ac | 2538 | |
617daa0e CV |
2539 | case bfd_mach_sh3: |
2540 | sh_show_regs = sh3_show_regs; | |
2541 | break; | |
55ff77ac | 2542 | |
617daa0e CV |
2543 | case bfd_mach_sh3e: |
2544 | sh_show_regs = sh3e_show_regs; | |
2545 | break; | |
55ff77ac | 2546 | |
617daa0e | 2547 | case bfd_mach_sh3_dsp: |
474e5826 | 2548 | case bfd_mach_sh4al_dsp: |
617daa0e CV |
2549 | sh_show_regs = sh3_dsp_show_regs; |
2550 | break; | |
55ff77ac | 2551 | |
617daa0e | 2552 | case bfd_mach_sh4: |
474e5826 | 2553 | case bfd_mach_sh4a: |
617daa0e CV |
2554 | sh_show_regs = sh4_show_regs; |
2555 | break; | |
55ff77ac | 2556 | |
474e5826 CV |
2557 | case bfd_mach_sh4_nofpu: |
2558 | case bfd_mach_sh4a_nofpu: | |
2559 | sh_show_regs = sh4_nofpu_show_regs; | |
2560 | break; | |
2561 | ||
03d363a1 | 2562 | #if 0 |
617daa0e CV |
2563 | case bfd_mach_sh5: |
2564 | sh_show_regs = sh64_show_regs; | |
2565 | /* SH5 is handled entirely in sh64-tdep.c */ | |
2566 | return sh64_gdbarch_init (info, arches); | |
03d363a1 | 2567 | #endif |
55ff77ac CV |
2568 | } |
2569 | ||
4be87837 DJ |
2570 | /* If there is already a candidate, use it. */ |
2571 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
2572 | if (arches != NULL) | |
2573 | return arches->gdbarch; | |
cc17453a EZ |
2574 | |
2575 | /* None found, create a new architecture from the information | |
2576 | provided. */ | |
f2ea0907 | 2577 | gdbarch = gdbarch_alloc (&info, NULL); |
cc17453a | 2578 | |
48db5a3c CV |
2579 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); |
2580 | set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
ec920329 | 2581 | set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
48db5a3c CV |
2582 | set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); |
2583 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
2584 | set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
2585 | set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
a38d2a54 | 2586 | set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
48db5a3c | 2587 | |
f2ea0907 | 2588 | set_gdbarch_num_regs (gdbarch, SH_NUM_REGS); |
a38d2a54 | 2589 | set_gdbarch_sp_regnum (gdbarch, 15); |
a38d2a54 | 2590 | set_gdbarch_pc_regnum (gdbarch, 16); |
48db5a3c CV |
2591 | set_gdbarch_fp0_regnum (gdbarch, -1); |
2592 | set_gdbarch_num_pseudo_regs (gdbarch, 0); | |
2593 | ||
1c0159e0 CV |
2594 | set_gdbarch_register_type (gdbarch, sh_default_register_type); |
2595 | ||
2596 | set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info); | |
2597 | ||
eaf90c5d | 2598 | set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc); |
48db5a3c | 2599 | |
2bf0cb65 | 2600 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_sh); |
2f14585c | 2601 | set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno); |
48db5a3c CV |
2602 | |
2603 | set_gdbarch_write_pc (gdbarch, generic_target_write_pc); | |
2604 | ||
c0409442 CV |
2605 | set_gdbarch_return_value (gdbarch, sh_return_value_nofpu); |
2606 | set_gdbarch_deprecated_extract_struct_value_address (gdbarch, | |
2607 | sh_extract_struct_value_address); | |
1c0159e0 | 2608 | |
48db5a3c CV |
2609 | set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue); |
2610 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
48db5a3c | 2611 | |
1c0159e0 CV |
2612 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu); |
2613 | ||
48db5a3c CV |
2614 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); |
2615 | ||
19f59343 | 2616 | set_gdbarch_frame_align (gdbarch, sh_frame_align); |
1c0159e0 CV |
2617 | set_gdbarch_unwind_sp (gdbarch, sh_unwind_sp); |
2618 | set_gdbarch_unwind_pc (gdbarch, sh_unwind_pc); | |
2619 | set_gdbarch_unwind_dummy_id (gdbarch, sh_unwind_dummy_id); | |
2620 | frame_base_set_default (gdbarch, &sh_frame_base); | |
2621 | ||
617daa0e | 2622 | set_gdbarch_in_function_epilogue_p (gdbarch, sh_in_function_epilogue_p); |
cc17453a EZ |
2623 | |
2624 | switch (info.bfd_arch_info->mach) | |
8db62801 | 2625 | { |
cc17453a | 2626 | case bfd_mach_sh: |
48db5a3c | 2627 | set_gdbarch_register_name (gdbarch, sh_sh_register_name); |
cc17453a | 2628 | break; |
1c0159e0 | 2629 | |
cc17453a | 2630 | case bfd_mach_sh2: |
48db5a3c | 2631 | set_gdbarch_register_name (gdbarch, sh_sh_register_name); |
617daa0e | 2632 | break; |
1c0159e0 | 2633 | |
2d188dd3 | 2634 | case bfd_mach_sh2e: |
48db5a3c CV |
2635 | /* doubles on sh2e and sh3e are actually 4 byte. */ |
2636 | set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
2637 | ||
2638 | set_gdbarch_register_name (gdbarch, sh_sh2e_register_name); | |
48db5a3c | 2639 | set_gdbarch_register_type (gdbarch, sh_sh3e_register_type); |
2d188dd3 | 2640 | set_gdbarch_fp0_regnum (gdbarch, 25); |
c0409442 | 2641 | set_gdbarch_return_value (gdbarch, sh_return_value_fpu); |
6df2bf50 | 2642 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); |
2d188dd3 | 2643 | break; |
1c0159e0 | 2644 | |
da962468 CV |
2645 | case bfd_mach_sh2a: |
2646 | set_gdbarch_register_name (gdbarch, sh_sh2a_register_name); | |
2647 | set_gdbarch_register_type (gdbarch, sh_sh2a_register_type); | |
2648 | set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno); | |
2649 | ||
2650 | set_gdbarch_fp0_regnum (gdbarch, 25); | |
2651 | set_gdbarch_num_pseudo_regs (gdbarch, 9); | |
2652 | set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read); | |
2653 | set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write); | |
c0409442 | 2654 | set_gdbarch_return_value (gdbarch, sh_return_value_fpu); |
da962468 CV |
2655 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); |
2656 | break; | |
2657 | ||
2658 | case bfd_mach_sh2a_nofpu: | |
2659 | set_gdbarch_register_name (gdbarch, sh_sh2a_nofpu_register_name); | |
2660 | set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno); | |
2661 | ||
2662 | set_gdbarch_num_pseudo_regs (gdbarch, 1); | |
2663 | set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read); | |
2664 | set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write); | |
2665 | break; | |
2666 | ||
cc17453a | 2667 | case bfd_mach_sh_dsp: |
48db5a3c | 2668 | set_gdbarch_register_name (gdbarch, sh_sh_dsp_register_name); |
2f14585c | 2669 | set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno); |
cc17453a | 2670 | break; |
1c0159e0 | 2671 | |
cc17453a | 2672 | case bfd_mach_sh3: |
48db5a3c | 2673 | set_gdbarch_register_name (gdbarch, sh_sh3_register_name); |
cc17453a | 2674 | break; |
1c0159e0 | 2675 | |
cc17453a | 2676 | case bfd_mach_sh3e: |
48db5a3c CV |
2677 | /* doubles on sh2e and sh3e are actually 4 byte. */ |
2678 | set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
2679 | ||
2680 | set_gdbarch_register_name (gdbarch, sh_sh3e_register_name); | |
48db5a3c | 2681 | set_gdbarch_register_type (gdbarch, sh_sh3e_register_type); |
cc17453a | 2682 | set_gdbarch_fp0_regnum (gdbarch, 25); |
c0409442 | 2683 | set_gdbarch_return_value (gdbarch, sh_return_value_fpu); |
6df2bf50 | 2684 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); |
cc17453a | 2685 | break; |
1c0159e0 | 2686 | |
cc17453a | 2687 | case bfd_mach_sh3_dsp: |
48db5a3c | 2688 | set_gdbarch_register_name (gdbarch, sh_sh3_dsp_register_name); |
48db5a3c | 2689 | set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno); |
cc17453a | 2690 | break; |
1c0159e0 | 2691 | |
cc17453a | 2692 | case bfd_mach_sh4: |
474e5826 | 2693 | case bfd_mach_sh4a: |
48db5a3c | 2694 | set_gdbarch_register_name (gdbarch, sh_sh4_register_name); |
48db5a3c | 2695 | set_gdbarch_register_type (gdbarch, sh_sh4_register_type); |
cc17453a | 2696 | set_gdbarch_fp0_regnum (gdbarch, 25); |
da962468 | 2697 | set_gdbarch_num_pseudo_regs (gdbarch, 13); |
d8124050 AC |
2698 | set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read); |
2699 | set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write); | |
c0409442 | 2700 | set_gdbarch_return_value (gdbarch, sh_return_value_fpu); |
6df2bf50 | 2701 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); |
cc17453a | 2702 | break; |
1c0159e0 | 2703 | |
474e5826 CV |
2704 | case bfd_mach_sh4_nofpu: |
2705 | case bfd_mach_sh4a_nofpu: | |
2706 | set_gdbarch_register_name (gdbarch, sh_sh4_nofpu_register_name); | |
2707 | break; | |
2708 | ||
2709 | case bfd_mach_sh4al_dsp: | |
2710 | set_gdbarch_register_name (gdbarch, sh_sh4al_dsp_register_name); | |
2711 | set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno); | |
2712 | break; | |
2713 | ||
cc17453a | 2714 | default: |
b58cbbf2 | 2715 | set_gdbarch_register_name (gdbarch, sh_sh_register_name); |
cc17453a | 2716 | break; |
8db62801 | 2717 | } |
cc17453a | 2718 | |
4be87837 DJ |
2719 | /* Hook in ABI-specific overrides, if they have been registered. */ |
2720 | gdbarch_init_osabi (info, gdbarch); | |
d658f924 | 2721 | |
1c0159e0 CV |
2722 | frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer); |
2723 | frame_unwind_append_sniffer (gdbarch, sh_frame_sniffer); | |
2724 | ||
cc17453a | 2725 | return gdbarch; |
8db62801 EZ |
2726 | } |
2727 | ||
617daa0e | 2728 | extern initialize_file_ftype _initialize_sh_tdep; /* -Wmissing-prototypes */ |
a78f21af | 2729 | |
c906108c | 2730 | void |
fba45db2 | 2731 | _initialize_sh_tdep (void) |
c906108c SS |
2732 | { |
2733 | struct cmd_list_element *c; | |
617daa0e | 2734 | |
f2ea0907 | 2735 | gdbarch_register (bfd_arch_sh, sh_gdbarch_init, NULL); |
c906108c | 2736 | |
53116e27 | 2737 | add_com ("regs", class_vars, sh_show_regs_command, "Print all registers"); |
c906108c | 2738 | } |