Commit | Line | Data |
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66d05e03 | 1 | /* Target-dependent code for Hitachi Super-H, for GDB. |
00dd4fd9 | 2 | Copyright (C) 1993, 1994, 1995, 1996 Free Software Foundation, Inc. |
9faacb92 SC |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2 of the License, or | |
9 | (at your option) any later version. | |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program; if not, write to the Free Software | |
6c9638b4 | 18 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ |
9faacb92 SC |
19 | |
20 | /* | |
21 | Contributed by Steve Chamberlain | |
22 | sac@cygnus.com | |
23 | */ | |
24 | ||
25 | #include "defs.h" | |
26 | #include "frame.h" | |
27 | #include "obstack.h" | |
28 | #include "symtab.h" | |
29 | #include "gdbtypes.h" | |
30 | #include "gdbcmd.h" | |
66d05e03 | 31 | #include "gdbcore.h" |
9faacb92 SC |
32 | #include "value.h" |
33 | #include "dis-asm.h" | |
5f2f2809 | 34 | |
00dd4fd9 SS |
35 | /* Default to the original SH. */ |
36 | ||
37 | #define DEFAULT_SH_TYPE "sh" | |
38 | ||
39 | /* This value is the model of SH in use. */ | |
40 | ||
41 | char *sh_processor_type; | |
42 | ||
43 | char *tmp_sh_processor_type; | |
44 | ||
45 | /* A set of original names, to be used when restoring back to generic | |
46 | registers from a specific set. */ | |
47 | ||
48 | char *sh_generic_reg_names[] = REGISTER_NAMES; | |
49 | ||
50 | char *sh_reg_names[] = { | |
51 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
52 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
53 | "pc", "pr", "gbr", "vbr", "mach","macl", "sr", | |
05535e79 | 54 | "", "", |
00dd4fd9 SS |
55 | "", "", "", "", "", "", "", "", |
56 | "", "", "", "", "", "", "", "", | |
05535e79 | 57 | "","", |
00dd4fd9 SS |
58 | "", "", "", "", "", "", "", "", |
59 | "", "", "", "", "", "", "", "" | |
60 | }; | |
61 | ||
62 | char *sh3_reg_names[] = { | |
63 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
64 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
65 | "pc", "pr", "gbr", "vbr", "mach","macl","sr", | |
05535e79 SS |
66 | "ssr", "spc", |
67 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", | |
68 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", | |
69 | "", "", | |
70 | "", "", "", "", "", "", "", "", | |
71 | "", "", "", "", "", "", "", "" | |
72 | }; | |
73 | ||
74 | char *sh3e_reg_names[] = { | |
75 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
76 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
77 | "pc", "pr", "gbr", "vbr", "mach","macl","sr", | |
78 | "ssr", "spc", | |
79 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", | |
80 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", | |
00dd4fd9 SS |
81 | "fpul", "fpscr", |
82 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", | |
05535e79 | 83 | "fr8", "fr9", "fr10","fr11","fr12","fr13","fr14","fr15" |
00dd4fd9 SS |
84 | }; |
85 | ||
86 | struct { | |
87 | char *name; | |
88 | char **regnames; | |
89 | } sh_processor_type_table[] = { | |
90 | { "sh", sh_reg_names }, | |
91 | { "sh3", sh3_reg_names }, | |
05535e79 | 92 | { "sh3e", sh3e_reg_names }, |
00dd4fd9 SS |
93 | { NULL, NULL } |
94 | }; | |
95 | ||
9faacb92 SC |
96 | /* Prologue looks like |
97 | [mov.l <regs>,@-r15]... | |
98 | [sts.l pr,@-r15] | |
99 | [mov.l r14,@-r15] | |
100 | [mov r15,r14] | |
101 | */ | |
102 | ||
103 | #define IS_STS(x) ((x) == 0x4f22) | |
104 | #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06) | |
105 | #define GET_PUSHED_REG(x) (((x) >> 4) & 0xf) | |
106 | #define IS_MOV_SP_FP(x) ((x) == 0x6ef3) | |
107 | #define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00) | |
c4deed18 SC |
108 | #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00) |
109 | #define IS_SHLL_R3(x) ((x) == 0x4300) | |
110 | #define IS_ADD_R3SP(x) ((x) == 0x3f3c) | |
9faacb92 SC |
111 | |
112 | /* Skip any prologue before the guts of a function */ | |
113 | ||
114 | CORE_ADDR | |
115 | sh_skip_prologue (start_pc) | |
116 | CORE_ADDR start_pc; | |
9faacb92 SC |
117 | { |
118 | int w; | |
119 | ||
120 | w = read_memory_integer (start_pc, 2); | |
121 | while (IS_STS (w) | |
122 | || IS_PUSH (w) | |
c4deed18 | 123 | || IS_MOV_SP_FP (w) |
5f2f2809 SC |
124 | || IS_MOV_R3 (w) |
125 | || IS_ADD_R3SP (w) | |
126 | || IS_ADD_SP (w) | |
127 | || IS_SHLL_R3 (w)) | |
9faacb92 SC |
128 | { |
129 | start_pc += 2; | |
130 | w = read_memory_integer (start_pc, 2); | |
131 | } | |
132 | ||
133 | return start_pc; | |
134 | } | |
135 | ||
18b46e7c | 136 | /* Disassemble an instruction. */ |
9faacb92 SC |
137 | |
138 | int | |
18b46e7c SS |
139 | gdb_print_insn_sh (memaddr, info) |
140 | bfd_vma memaddr; | |
141 | disassemble_info *info; | |
9faacb92 | 142 | { |
5f2f2809 | 143 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) |
5076ecd0 | 144 | return print_insn_sh (memaddr, info); |
5f2f2809 | 145 | else |
5076ecd0 | 146 | return print_insn_shl (memaddr, info); |
9faacb92 | 147 | } |
18b46e7c | 148 | |
9faacb92 SC |
149 | /* Given a GDB frame, determine the address of the calling function's frame. |
150 | This will be used to create a new GDB frame struct, and then | |
151 | INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame. | |
152 | ||
153 | For us, the frame address is its stack pointer value, so we look up | |
154 | the function prologue to determine the caller's sp value, and return it. */ | |
155 | ||
669caa9c SS |
156 | CORE_ADDR |
157 | sh_frame_chain (frame) | |
158 | struct frame_info *frame; | |
9faacb92 | 159 | { |
669caa9c SS |
160 | if (!inside_entry_file (frame->pc)) |
161 | return read_memory_integer (FRAME_FP (frame) + frame->f_offset, 4); | |
9faacb92 SC |
162 | else |
163 | return 0; | |
164 | } | |
165 | ||
66d05e03 SS |
166 | /* Put here the code to store, into a struct frame_saved_regs, the |
167 | addresses of the saved registers of frame described by FRAME_INFO. | |
9faacb92 | 168 | This includes special registers such as pc and fp saved in special |
66d05e03 SS |
169 | ways in the stack frame. sp is even more special: the address we |
170 | return for it IS the sp for the next frame. */ | |
9faacb92 SC |
171 | |
172 | void | |
173 | frame_find_saved_regs (fi, fsr) | |
174 | struct frame_info *fi; | |
175 | struct frame_saved_regs *fsr; | |
176 | { | |
7ccb1e44 | 177 | int where[NUM_REGS]; |
9faacb92 SC |
178 | int rn; |
179 | int have_fp = 0; | |
180 | int depth; | |
181 | int pc; | |
182 | int opc; | |
183 | int insn; | |
c4deed18 | 184 | int r3_val = 0; |
9faacb92 SC |
185 | |
186 | opc = pc = get_pc_function_start (fi->pc); | |
187 | ||
188 | insn = read_memory_integer (pc, 2); | |
189 | ||
c4deed18 SC |
190 | fi->leaf_function = 1; |
191 | fi->f_offset = 0; | |
192 | ||
9faacb92 SC |
193 | for (rn = 0; rn < NUM_REGS; rn++) |
194 | where[rn] = -1; | |
195 | ||
196 | depth = 0; | |
197 | ||
198 | /* Loop around examining the prologue insns, but give up | |
199 | after 15 of them, since we're getting silly then */ | |
200 | while (pc < opc + 15 * 2) | |
201 | { | |
202 | /* See where the registers will be saved to */ | |
203 | if (IS_PUSH (insn)) | |
204 | { | |
205 | pc += 2; | |
206 | rn = GET_PUSHED_REG (insn); | |
207 | where[rn] = depth; | |
208 | insn = read_memory_integer (pc, 2); | |
209 | depth += 4; | |
210 | } | |
211 | else if (IS_STS (insn)) | |
212 | { | |
213 | pc += 2; | |
214 | where[PR_REGNUM] = depth; | |
215 | insn = read_memory_integer (pc, 2); | |
c4deed18 SC |
216 | /* If we're storing the pr then this isn't a leaf */ |
217 | fi->leaf_function = 0; | |
9faacb92 SC |
218 | depth += 4; |
219 | } | |
c4deed18 SC |
220 | else if (IS_MOV_R3 (insn)) |
221 | { | |
5f2f2809 SC |
222 | r3_val = (char) (insn & 0xff); |
223 | pc += 2; | |
c4deed18 SC |
224 | insn = read_memory_integer (pc, 2); |
225 | } | |
226 | else if (IS_SHLL_R3 (insn)) | |
227 | { | |
5f2f2809 SC |
228 | r3_val <<= 1; |
229 | pc += 2; | |
c4deed18 SC |
230 | insn = read_memory_integer (pc, 2); |
231 | } | |
232 | else if (IS_ADD_R3SP (insn)) | |
233 | { | |
234 | depth += -r3_val; | |
5f2f2809 | 235 | pc += 2; |
c4deed18 SC |
236 | insn = read_memory_integer (pc, 2); |
237 | } | |
9faacb92 SC |
238 | else if (IS_ADD_SP (insn)) |
239 | { | |
240 | pc += 2; | |
241 | depth += -((char) (insn & 0xff)); | |
242 | insn = read_memory_integer (pc, 2); | |
243 | } | |
df14b38b SC |
244 | else |
245 | break; | |
9faacb92 SC |
246 | } |
247 | ||
248 | /* Now we know how deep things are, we can work out their addresses */ | |
249 | ||
250 | for (rn = 0; rn < NUM_REGS; rn++) | |
251 | { | |
252 | if (where[rn] >= 0) | |
253 | { | |
254 | if (rn == FP_REGNUM) | |
255 | have_fp = 1; | |
256 | ||
257 | fsr->regs[rn] = fi->frame - where[rn] + depth - 4; | |
258 | } | |
259 | else | |
260 | { | |
261 | fsr->regs[rn] = 0; | |
262 | } | |
263 | } | |
264 | ||
265 | if (have_fp) | |
266 | { | |
9faacb92 SC |
267 | fsr->regs[SP_REGNUM] = read_memory_integer (fsr->regs[FP_REGNUM], 4); |
268 | } | |
269 | else | |
270 | { | |
271 | fsr->regs[SP_REGNUM] = fi->frame - 4; | |
272 | } | |
273 | ||
c4deed18 | 274 | fi->f_offset = depth - where[FP_REGNUM] - 4; |
9faacb92 SC |
275 | /* Work out the return pc - either from the saved pr or the pr |
276 | value */ | |
5f2f2809 | 277 | |
5c8ba017 SG |
278 | if (fsr->regs[PR_REGNUM]) |
279 | fi->return_pc = read_memory_integer (fsr->regs[PR_REGNUM], 4); | |
280 | else | |
281 | fi->return_pc = read_register (PR_REGNUM); | |
9faacb92 SC |
282 | } |
283 | ||
284 | /* initialize the extra info saved in a FRAME */ | |
285 | ||
286 | void | |
287 | init_extra_frame_info (fromleaf, fi) | |
288 | int fromleaf; | |
289 | struct frame_info *fi; | |
290 | { | |
291 | struct frame_saved_regs dummy; | |
66d05e03 | 292 | |
5c8ba017 SG |
293 | if (fi->next) |
294 | fi->pc = fi->next->return_pc; | |
295 | ||
9faacb92 SC |
296 | frame_find_saved_regs (fi, &dummy); |
297 | } | |
298 | ||
299 | ||
300 | /* Discard from the stack the innermost frame, | |
301 | restoring all saved registers. */ | |
302 | ||
303 | void | |
304 | pop_frame () | |
305 | { | |
669caa9c | 306 | register struct frame_info *frame = get_current_frame (); |
9faacb92 SC |
307 | register CORE_ADDR fp; |
308 | register int regnum; | |
309 | struct frame_saved_regs fsr; | |
9faacb92 | 310 | |
669caa9c SS |
311 | fp = FRAME_FP (frame); |
312 | get_frame_saved_regs (frame, &fsr); | |
9faacb92 SC |
313 | |
314 | /* Copy regs from where they were saved in the frame */ | |
315 | for (regnum = 0; regnum < NUM_REGS; regnum++) | |
316 | { | |
317 | if (fsr.regs[regnum]) | |
318 | { | |
319 | write_register (regnum, read_memory_integer (fsr.regs[regnum], 4)); | |
320 | } | |
321 | } | |
322 | ||
5f2f2809 | 323 | write_register (PC_REGNUM, frame->return_pc); |
9faacb92 SC |
324 | write_register (SP_REGNUM, fp + 4); |
325 | flush_cached_frames (); | |
9faacb92 | 326 | } |
edd01519 | 327 | |
00dd4fd9 SS |
328 | /* Command to set the processor type. */ |
329 | ||
330 | void | |
331 | sh_set_processor_type_command (args, from_tty) | |
332 | char *args; | |
333 | int from_tty; | |
334 | { | |
335 | int i; | |
336 | char *temp; | |
337 | ||
338 | /* The `set' commands work by setting the value, then calling the hook, | |
339 | so we let the general command modify a scratch location, then decide | |
340 | here if we really want to modify the processor type. */ | |
341 | if (tmp_sh_processor_type == NULL || *tmp_sh_processor_type == '\0') | |
342 | { | |
343 | printf_unfiltered ("The known SH processor types are as follows:\n\n"); | |
344 | for (i = 0; sh_processor_type_table[i].name != NULL; ++i) | |
345 | printf_unfiltered ("%s\n", sh_processor_type_table[i].name); | |
346 | ||
347 | /* Restore the value. */ | |
348 | tmp_sh_processor_type = strsave (sh_processor_type); | |
349 | ||
350 | return; | |
351 | } | |
352 | ||
353 | if (!sh_set_processor_type (tmp_sh_processor_type)) | |
354 | { | |
355 | /* Restore to a valid value before erroring out. */ | |
356 | temp = tmp_sh_processor_type; | |
357 | tmp_sh_processor_type = strsave (sh_processor_type); | |
358 | error ("Unknown processor type `%s'.", temp); | |
359 | } | |
360 | } | |
361 | ||
362 | static void | |
363 | sh_show_processor_type_command (args, from_tty) | |
364 | char *args; | |
365 | int from_tty; | |
366 | { | |
367 | } | |
368 | ||
369 | /* Modify the actual processor type. */ | |
370 | ||
371 | int | |
372 | sh_set_processor_type (str) | |
373 | char *str; | |
374 | { | |
375 | int i, j; | |
376 | ||
377 | if (str == NULL) | |
378 | return 0; | |
379 | ||
380 | for (i = 0; sh_processor_type_table[i].name != NULL; ++i) | |
381 | { | |
382 | if (strcasecmp (str, sh_processor_type_table[i].name) == 0) | |
383 | { | |
384 | sh_processor_type = str; | |
385 | ||
386 | for (j = 0; j < NUM_REGS; ++j) | |
387 | reg_names[j] = sh_processor_type_table[i].regnames[j]; | |
388 | ||
389 | return 1; | |
390 | } | |
391 | } | |
392 | ||
393 | return 0; | |
394 | } | |
395 | ||
edd01519 | 396 | /* Print the registers in a form similar to the E7000 */ |
669caa9c | 397 | |
edd01519 SC |
398 | static void |
399 | show_regs (args, from_tty) | |
669caa9c SS |
400 | char *args; |
401 | int from_tty; | |
edd01519 | 402 | { |
5f2f2809 SC |
403 | printf_filtered ("PC=%08x SR=%08x PR=%08x MACH=%08x MACHL=%08x\n", |
404 | read_register (PC_REGNUM), | |
405 | read_register (SR_REGNUM), | |
406 | read_register (PR_REGNUM), | |
407 | read_register (MACH_REGNUM), | |
408 | read_register (MACL_REGNUM)); | |
409 | ||
410 | printf_filtered ("R0-R7 %08x %08x %08x %08x %08x %08x %08x %08x\n", | |
411 | read_register (0), | |
412 | read_register (1), | |
413 | read_register (2), | |
414 | read_register (3), | |
415 | read_register (4), | |
416 | read_register (5), | |
417 | read_register (6), | |
418 | read_register (7)); | |
419 | printf_filtered ("R8-R15 %08x %08x %08x %08x %08x %08x %08x %08x\n", | |
420 | read_register (8), | |
421 | read_register (9), | |
422 | read_register (10), | |
423 | read_register (11), | |
424 | read_register (12), | |
425 | read_register (13), | |
426 | read_register (14), | |
427 | read_register (15)); | |
edd01519 | 428 | } |
c853c90d | 429 | \f |
976bb0be | 430 | void |
df14b38b SC |
431 | _initialize_sh_tdep () |
432 | { | |
00dd4fd9 SS |
433 | struct cmd_list_element *c; |
434 | ||
18b46e7c SS |
435 | tm_print_insn = gdb_print_insn_sh; |
436 | ||
00dd4fd9 SS |
437 | c = add_set_cmd ("processor", class_support, var_string_noescape, |
438 | (char *) &tmp_sh_processor_type, | |
439 | "Set the type of SH processor in use.\n\ | |
440 | Set this to be able to access processor-type-specific registers.\n\ | |
441 | ", | |
442 | &setlist); | |
443 | c->function.cfunc = sh_set_processor_type_command; | |
444 | c = add_show_from_set (c, &showlist); | |
445 | c->function.cfunc = sh_show_processor_type_command; | |
446 | ||
447 | tmp_sh_processor_type = strsave (DEFAULT_SH_TYPE); | |
448 | sh_set_processor_type_command (strsave (DEFAULT_SH_TYPE), 0); | |
449 | ||
5f2f2809 | 450 | add_com ("regs", class_vars, show_regs, "Print all registers"); |
df14b38b | 451 | } |