Commit | Line | Data |
---|---|---|
85a453d5 | 1 | /* Target-dependent code for Renesas Super-H, for GDB. |
1e698235 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 |
3116c80a | 3 | Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b JM |
17 | You should have received a copy of the GNU General Public License |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
21 | |
22 | /* | |
c5aa993b JM |
23 | Contributed by Steve Chamberlain |
24 | sac@cygnus.com | |
c906108c SS |
25 | */ |
26 | ||
27 | #include "defs.h" | |
28 | #include "frame.h" | |
1c0159e0 CV |
29 | #include "frame-base.h" |
30 | #include "frame-unwind.h" | |
31 | #include "dwarf2-frame.h" | |
c906108c SS |
32 | #include "symtab.h" |
33 | #include "symfile.h" | |
34 | #include "gdbtypes.h" | |
35 | #include "gdbcmd.h" | |
36 | #include "gdbcore.h" | |
37 | #include "value.h" | |
38 | #include "dis-asm.h" | |
73c1f219 | 39 | #include "inferior.h" |
c906108c | 40 | #include "gdb_string.h" |
1c0159e0 | 41 | #include "gdb_assert.h" |
b4a20239 | 42 | #include "arch-utils.h" |
fb409745 | 43 | #include "floatformat.h" |
4e052eda | 44 | #include "regcache.h" |
d16aafd8 | 45 | #include "doublest.h" |
4be87837 | 46 | #include "osabi.h" |
c906108c | 47 | |
ab3b8126 JT |
48 | #include "sh-tdep.h" |
49 | ||
d658f924 | 50 | #include "elf-bfd.h" |
1a8629c7 MS |
51 | #include "solib-svr4.h" |
52 | ||
55ff77ac | 53 | /* sh flags */ |
283150cd EZ |
54 | #include "elf/sh.h" |
55 | /* registers numbers shared with the simulator */ | |
1c922164 | 56 | #include "gdb/sim-sh.h" |
283150cd | 57 | |
55ff77ac | 58 | static void (*sh_show_regs) (void); |
cc17453a | 59 | |
f2ea0907 | 60 | #define SH_NUM_REGS 59 |
88e04cc1 | 61 | |
1c0159e0 | 62 | struct sh_frame_cache |
cc17453a | 63 | { |
1c0159e0 CV |
64 | /* Base address. */ |
65 | CORE_ADDR base; | |
66 | LONGEST sp_offset; | |
67 | CORE_ADDR pc; | |
68 | ||
69 | /* Flag showing that a frame has been created in the prologue code. */ | |
70 | int uses_fp; | |
71 | ||
72 | /* Saved registers. */ | |
73 | CORE_ADDR saved_regs[SH_NUM_REGS]; | |
74 | CORE_ADDR saved_sp; | |
63978407 | 75 | }; |
c906108c | 76 | |
fa88f677 | 77 | static const char * |
cc17453a | 78 | sh_generic_register_name (int reg_nr) |
c5aa993b | 79 | { |
617daa0e CV |
80 | static char *register_names[] = { |
81 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
82 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
83 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
cc17453a | 84 | "fpul", "fpscr", |
617daa0e CV |
85 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", |
86 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
87 | "ssr", "spc", | |
cc17453a EZ |
88 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", |
89 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", | |
90 | }; | |
91 | if (reg_nr < 0) | |
92 | return NULL; | |
93 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
94 | return NULL; | |
95 | return register_names[reg_nr]; | |
96 | } | |
97 | ||
fa88f677 | 98 | static const char * |
cc17453a EZ |
99 | sh_sh_register_name (int reg_nr) |
100 | { | |
617daa0e CV |
101 | static char *register_names[] = { |
102 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
103 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
104 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
105 | "", "", | |
106 | "", "", "", "", "", "", "", "", | |
107 | "", "", "", "", "", "", "", "", | |
108 | "", "", | |
109 | "", "", "", "", "", "", "", "", | |
110 | "", "", "", "", "", "", "", "", | |
cc17453a EZ |
111 | }; |
112 | if (reg_nr < 0) | |
113 | return NULL; | |
114 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
115 | return NULL; | |
116 | return register_names[reg_nr]; | |
117 | } | |
118 | ||
fa88f677 | 119 | static const char * |
cc17453a EZ |
120 | sh_sh3_register_name (int reg_nr) |
121 | { | |
617daa0e CV |
122 | static char *register_names[] = { |
123 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
124 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
125 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
126 | "", "", | |
127 | "", "", "", "", "", "", "", "", | |
128 | "", "", "", "", "", "", "", "", | |
129 | "ssr", "spc", | |
cc17453a EZ |
130 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", |
131 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1" | |
132 | }; | |
133 | if (reg_nr < 0) | |
134 | return NULL; | |
135 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
136 | return NULL; | |
137 | return register_names[reg_nr]; | |
138 | } | |
139 | ||
fa88f677 | 140 | static const char * |
cc17453a EZ |
141 | sh_sh3e_register_name (int reg_nr) |
142 | { | |
617daa0e CV |
143 | static char *register_names[] = { |
144 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
145 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
146 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
cc17453a | 147 | "fpul", "fpscr", |
617daa0e CV |
148 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", |
149 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
150 | "ssr", "spc", | |
cc17453a EZ |
151 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", |
152 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", | |
153 | }; | |
154 | if (reg_nr < 0) | |
155 | return NULL; | |
156 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
157 | return NULL; | |
158 | return register_names[reg_nr]; | |
159 | } | |
160 | ||
2d188dd3 NC |
161 | static const char * |
162 | sh_sh2e_register_name (int reg_nr) | |
163 | { | |
617daa0e CV |
164 | static char *register_names[] = { |
165 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
166 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
167 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
2d188dd3 | 168 | "fpul", "fpscr", |
617daa0e CV |
169 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", |
170 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
171 | "", "", | |
2d188dd3 NC |
172 | "", "", "", "", "", "", "", "", |
173 | "", "", "", "", "", "", "", "", | |
174 | }; | |
175 | if (reg_nr < 0) | |
176 | return NULL; | |
177 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
178 | return NULL; | |
179 | return register_names[reg_nr]; | |
180 | } | |
181 | ||
fa88f677 | 182 | static const char * |
cc17453a EZ |
183 | sh_sh_dsp_register_name (int reg_nr) |
184 | { | |
617daa0e CV |
185 | static char *register_names[] = { |
186 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
187 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
188 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
189 | "", "dsr", | |
190 | "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1", | |
191 | "y0", "y1", "", "", "", "", "", "mod", | |
192 | "", "", | |
193 | "rs", "re", "", "", "", "", "", "", | |
194 | "", "", "", "", "", "", "", "", | |
cc17453a EZ |
195 | }; |
196 | if (reg_nr < 0) | |
197 | return NULL; | |
198 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
199 | return NULL; | |
200 | return register_names[reg_nr]; | |
201 | } | |
202 | ||
fa88f677 | 203 | static const char * |
cc17453a EZ |
204 | sh_sh3_dsp_register_name (int reg_nr) |
205 | { | |
617daa0e CV |
206 | static char *register_names[] = { |
207 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
208 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
209 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
210 | "", "dsr", | |
211 | "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1", | |
212 | "y0", "y1", "", "", "", "", "", "mod", | |
213 | "ssr", "spc", | |
214 | "rs", "re", "", "", "", "", "", "", | |
215 | "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b" | |
216 | "", "", "", "", "", "", "", "", | |
cc17453a EZ |
217 | }; |
218 | if (reg_nr < 0) | |
219 | return NULL; | |
220 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
221 | return NULL; | |
222 | return register_names[reg_nr]; | |
223 | } | |
224 | ||
fa88f677 | 225 | static const char * |
53116e27 EZ |
226 | sh_sh4_register_name (int reg_nr) |
227 | { | |
617daa0e | 228 | static char *register_names[] = { |
a38d2a54 | 229 | /* general registers 0-15 */ |
617daa0e CV |
230 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
231 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
a38d2a54 | 232 | /* 16 - 22 */ |
617daa0e | 233 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", |
a38d2a54 | 234 | /* 23, 24 */ |
53116e27 | 235 | "fpul", "fpscr", |
a38d2a54 | 236 | /* floating point registers 25 - 40 */ |
617daa0e CV |
237 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", |
238 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
a38d2a54 | 239 | /* 41, 42 */ |
617daa0e | 240 | "ssr", "spc", |
a38d2a54 | 241 | /* bank 0 43 - 50 */ |
53116e27 | 242 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", |
a38d2a54 | 243 | /* bank 1 51 - 58 */ |
53116e27 | 244 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", |
a38d2a54 | 245 | /* double precision (pseudo) 59 - 66 */ |
617daa0e | 246 | "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", |
a38d2a54 | 247 | /* vectors (pseudo) 67 - 70 */ |
617daa0e | 248 | "fv0", "fv4", "fv8", "fv12", |
a38d2a54 EZ |
249 | /* FIXME: missing XF 71 - 86 */ |
250 | /* FIXME: missing XD 87 - 94 */ | |
53116e27 EZ |
251 | }; |
252 | if (reg_nr < 0) | |
253 | return NULL; | |
254 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
255 | return NULL; | |
256 | return register_names[reg_nr]; | |
257 | } | |
258 | ||
3117ed25 | 259 | static const unsigned char * |
fba45db2 | 260 | sh_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
cc17453a EZ |
261 | { |
262 | /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */ | |
617daa0e CV |
263 | static unsigned char breakpoint[] = { 0xc3, 0xc3 }; |
264 | ||
cc17453a EZ |
265 | *lenptr = sizeof (breakpoint); |
266 | return breakpoint; | |
267 | } | |
c906108c SS |
268 | |
269 | /* Prologue looks like | |
1c0159e0 CV |
270 | mov.l r14,@-r15 |
271 | sts.l pr,@-r15 | |
272 | mov.l <regs>,@-r15 | |
273 | sub <room_for_loca_vars>,r15 | |
274 | mov r15,r14 | |
8db62801 | 275 | |
1c0159e0 | 276 | Actually it can be more complicated than this but that's it, basically. |
c5aa993b | 277 | */ |
c906108c | 278 | |
1c0159e0 CV |
279 | #define GET_SOURCE_REG(x) (((x) >> 4) & 0xf) |
280 | #define GET_TARGET_REG(x) (((x) >> 8) & 0xf) | |
281 | ||
8db62801 EZ |
282 | /* STS.L PR,@-r15 0100111100100010 |
283 | r15-4-->r15, PR-->(r15) */ | |
c906108c | 284 | #define IS_STS(x) ((x) == 0x4f22) |
8db62801 EZ |
285 | |
286 | /* MOV.L Rm,@-r15 00101111mmmm0110 | |
287 | r15-4-->r15, Rm-->(R15) */ | |
c906108c | 288 | #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06) |
8db62801 | 289 | |
8db62801 EZ |
290 | /* MOV r15,r14 0110111011110011 |
291 | r15-->r14 */ | |
c906108c | 292 | #define IS_MOV_SP_FP(x) ((x) == 0x6ef3) |
8db62801 EZ |
293 | |
294 | /* ADD #imm,r15 01111111iiiiiiii | |
295 | r15+imm-->r15 */ | |
1c0159e0 | 296 | #define IS_ADD_IMM_SP(x) (((x) & 0xff00) == 0x7f00) |
8db62801 | 297 | |
c906108c SS |
298 | #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00) |
299 | #define IS_SHLL_R3(x) ((x) == 0x4300) | |
8db62801 EZ |
300 | |
301 | /* ADD r3,r15 0011111100111100 | |
302 | r15+r3-->r15 */ | |
c906108c | 303 | #define IS_ADD_R3SP(x) ((x) == 0x3f3c) |
8db62801 EZ |
304 | |
305 | /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011 | |
8db62801 | 306 | FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011 |
8db62801 | 307 | FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */ |
f2ea0907 CV |
308 | /* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to |
309 | make this entirely clear. */ | |
1c0159e0 CV |
310 | /* #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) */ |
311 | #define IS_FPUSH(x) (((x) & 0xff0f) == 0xff0b) | |
312 | ||
313 | /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 4 <= m <= 7 */ | |
314 | #define IS_MOV_ARG_TO_REG(x) \ | |
315 | (((x) & 0xf00f) == 0x6003 && \ | |
316 | ((x) & 0x00f0) >= 0x0040 && \ | |
317 | ((x) & 0x00f0) <= 0x0070) | |
318 | /* MOV.L Rm,@Rn 0010nnnnmmmm0010 n = 14, 4 <= m <= 7 */ | |
319 | #define IS_MOV_ARG_TO_IND_R14(x) \ | |
320 | (((x) & 0xff0f) == 0x2e02 && \ | |
321 | ((x) & 0x00f0) >= 0x0040 && \ | |
322 | ((x) & 0x00f0) <= 0x0070) | |
323 | /* MOV.L Rm,@(disp*4,Rn) 00011110mmmmdddd n = 14, 4 <= m <= 7 */ | |
324 | #define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \ | |
325 | (((x) & 0xff00) == 0x1e00 && \ | |
326 | ((x) & 0x00f0) >= 0x0040 && \ | |
327 | ((x) & 0x00f0) <= 0x0070) | |
328 | ||
329 | /* MOV.W @(disp*2,PC),Rn 1001nnnndddddddd */ | |
330 | #define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000) | |
331 | /* MOV.L @(disp*4,PC),Rn 1101nnnndddddddd */ | |
332 | #define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000) | |
333 | /* SUB Rn,R15 00111111nnnn1000 */ | |
334 | #define IS_SUB_REG_FROM_SP(x) (((x) & 0xff0f) == 0x3f08) | |
8db62801 | 335 | |
1c0159e0 | 336 | #define FPSCR_SZ (1 << 20) |
cc17453a | 337 | |
1c0159e0 CV |
338 | /* The following instructions are used for epilogue testing. */ |
339 | #define IS_RESTORE_FP(x) ((x) == 0x6ef6) | |
340 | #define IS_RTS(x) ((x) == 0x000b) | |
341 | #define IS_LDS(x) ((x) == 0x4f26) | |
342 | #define IS_MOV_FP_SP(x) ((x) == 0x6fe3) | |
343 | #define IS_ADD_REG_TO_FP(x) (((x) & 0xff0f) == 0x3e0c) | |
344 | #define IS_ADD_IMM_FP(x) (((x) & 0xff00) == 0x7e00) | |
cc17453a | 345 | |
cc17453a EZ |
346 | /* Disassemble an instruction. */ |
347 | static int | |
617daa0e | 348 | gdb_print_insn_sh (bfd_vma memaddr, disassemble_info * info) |
c906108c | 349 | { |
1c509ca8 JR |
350 | info->endian = TARGET_BYTE_ORDER; |
351 | return print_insn_sh (memaddr, info); | |
283150cd EZ |
352 | } |
353 | ||
cc17453a | 354 | static CORE_ADDR |
1c0159e0 CV |
355 | sh_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc, |
356 | struct sh_frame_cache *cache) | |
617daa0e | 357 | { |
1c0159e0 CV |
358 | ULONGEST inst; |
359 | CORE_ADDR opc; | |
360 | int offset; | |
361 | int sav_offset = 0; | |
c906108c | 362 | int r3_val = 0; |
1c0159e0 | 363 | int reg, sav_reg = -1; |
cc17453a | 364 | |
1c0159e0 CV |
365 | if (pc >= current_pc) |
366 | return current_pc; | |
cc17453a | 367 | |
1c0159e0 | 368 | cache->uses_fp = 0; |
cc17453a EZ |
369 | for (opc = pc + (2 * 28); pc < opc; pc += 2) |
370 | { | |
1c0159e0 | 371 | inst = read_memory_unsigned_integer (pc, 2); |
cc17453a | 372 | /* See where the registers will be saved to */ |
f2ea0907 | 373 | if (IS_PUSH (inst)) |
cc17453a | 374 | { |
1c0159e0 CV |
375 | cache->saved_regs[GET_SOURCE_REG (inst)] = cache->sp_offset; |
376 | cache->sp_offset += 4; | |
cc17453a | 377 | } |
f2ea0907 | 378 | else if (IS_STS (inst)) |
cc17453a | 379 | { |
1c0159e0 CV |
380 | cache->saved_regs[PR_REGNUM] = cache->sp_offset; |
381 | cache->sp_offset += 4; | |
cc17453a | 382 | } |
f2ea0907 | 383 | else if (IS_MOV_R3 (inst)) |
cc17453a | 384 | { |
f2ea0907 | 385 | r3_val = ((inst & 0xff) ^ 0x80) - 0x80; |
cc17453a | 386 | } |
f2ea0907 | 387 | else if (IS_SHLL_R3 (inst)) |
cc17453a EZ |
388 | { |
389 | r3_val <<= 1; | |
390 | } | |
f2ea0907 | 391 | else if (IS_ADD_R3SP (inst)) |
cc17453a | 392 | { |
1c0159e0 | 393 | cache->sp_offset += -r3_val; |
cc17453a | 394 | } |
f2ea0907 | 395 | else if (IS_ADD_IMM_SP (inst)) |
cc17453a | 396 | { |
1c0159e0 CV |
397 | offset = ((inst & 0xff) ^ 0x80) - 0x80; |
398 | cache->sp_offset -= offset; | |
c906108c | 399 | } |
1c0159e0 | 400 | else if (IS_MOVW_PCREL_TO_REG (inst)) |
617daa0e | 401 | { |
1c0159e0 CV |
402 | if (sav_reg < 0) |
403 | { | |
404 | reg = GET_TARGET_REG (inst); | |
405 | if (reg < 14) | |
406 | { | |
407 | sav_reg = reg; | |
408 | offset = (((inst & 0xff) ^ 0x80) - 0x80) << 1; | |
409 | sav_offset = | |
617daa0e | 410 | read_memory_integer (((pc + 4) & ~3) + offset, 2); |
1c0159e0 CV |
411 | } |
412 | } | |
c906108c | 413 | } |
1c0159e0 | 414 | else if (IS_MOVL_PCREL_TO_REG (inst)) |
617daa0e | 415 | { |
1c0159e0 CV |
416 | if (sav_reg < 0) |
417 | { | |
418 | reg = (inst & 0x0f00) >> 8; | |
419 | if (reg < 14) | |
420 | { | |
421 | sav_reg = reg; | |
422 | offset = (((inst & 0xff) ^ 0x80) - 0x80) << 1; | |
423 | sav_offset = | |
617daa0e | 424 | read_memory_integer (((pc + 4) & ~3) + offset, 4); |
1c0159e0 CV |
425 | } |
426 | } | |
c906108c | 427 | } |
1c0159e0 | 428 | else if (IS_SUB_REG_FROM_SP (inst)) |
617daa0e | 429 | { |
1c0159e0 CV |
430 | reg = GET_SOURCE_REG (inst); |
431 | if (sav_reg > 0 && reg == sav_reg) | |
432 | { | |
433 | sav_reg = -1; | |
434 | } | |
435 | cache->sp_offset += sav_offset; | |
c906108c | 436 | } |
f2ea0907 | 437 | else if (IS_FPUSH (inst)) |
c906108c | 438 | { |
f2ea0907 | 439 | if (read_register (FPSCR_REGNUM) & FPSCR_SZ) |
c906108c | 440 | { |
1c0159e0 | 441 | cache->sp_offset += 8; |
c906108c SS |
442 | } |
443 | else | |
444 | { | |
1c0159e0 | 445 | cache->sp_offset += 4; |
c906108c SS |
446 | } |
447 | } | |
f2ea0907 | 448 | else if (IS_MOV_SP_FP (inst)) |
617daa0e | 449 | { |
1c0159e0 CV |
450 | if (!cache->uses_fp) |
451 | cache->uses_fp = 1; | |
452 | /* At this point, only allow argument register moves to other | |
453 | registers or argument register moves to @(X,fp) which are | |
454 | moving the register arguments onto the stack area allocated | |
455 | by a former add somenumber to SP call. Don't allow moving | |
456 | to an fp indirect address above fp + cache->sp_offset. */ | |
457 | pc += 2; | |
458 | for (opc = pc + 12; pc < opc; pc += 2) | |
459 | { | |
460 | inst = read_memory_integer (pc, 2); | |
461 | if (IS_MOV_ARG_TO_IND_R14 (inst)) | |
617daa0e | 462 | { |
1c0159e0 CV |
463 | reg = GET_SOURCE_REG (inst); |
464 | if (cache->sp_offset > 0) | |
617daa0e | 465 | cache->saved_regs[reg] = cache->sp_offset; |
1c0159e0 CV |
466 | } |
467 | else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst)) | |
617daa0e | 468 | { |
1c0159e0 CV |
469 | reg = GET_SOURCE_REG (inst); |
470 | offset = (inst & 0xf) * 4; | |
471 | if (cache->sp_offset > offset) | |
472 | cache->saved_regs[reg] = cache->sp_offset - offset; | |
473 | } | |
474 | else if (IS_MOV_ARG_TO_REG (inst)) | |
617daa0e | 475 | continue; |
1c0159e0 CV |
476 | else |
477 | break; | |
478 | } | |
479 | break; | |
480 | } | |
617daa0e CV |
481 | #if 0 /* This used to just stop when it found an instruction that |
482 | was not considered part of the prologue. Now, we just | |
483 | keep going looking for likely instructions. */ | |
c906108c SS |
484 | else |
485 | break; | |
2bfa91ee | 486 | #endif |
c906108c SS |
487 | } |
488 | ||
1c0159e0 CV |
489 | return pc; |
490 | } | |
c906108c | 491 | |
1c0159e0 | 492 | /* Skip any prologue before the guts of a function */ |
c906108c | 493 | |
1c0159e0 CV |
494 | /* Skip the prologue using the debug information. If this fails we'll |
495 | fall back on the 'guess' method below. */ | |
496 | static CORE_ADDR | |
497 | after_prologue (CORE_ADDR pc) | |
498 | { | |
499 | struct symtab_and_line sal; | |
500 | CORE_ADDR func_addr, func_end; | |
c906108c | 501 | |
1c0159e0 CV |
502 | /* If we can not find the symbol in the partial symbol table, then |
503 | there is no hope we can determine the function's start address | |
504 | with this code. */ | |
505 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
506 | return 0; | |
c906108c | 507 | |
1c0159e0 CV |
508 | /* Get the line associated with FUNC_ADDR. */ |
509 | sal = find_pc_line (func_addr, 0); | |
510 | ||
511 | /* There are only two cases to consider. First, the end of the source line | |
512 | is within the function bounds. In that case we return the end of the | |
513 | source line. Second is the end of the source line extends beyond the | |
514 | bounds of the current function. We need to use the slow code to | |
515 | examine instructions in that case. */ | |
516 | if (sal.end < func_end) | |
517 | return sal.end; | |
518 | else | |
519 | return 0; | |
c906108c SS |
520 | } |
521 | ||
1c0159e0 CV |
522 | static CORE_ADDR |
523 | sh_skip_prologue (CORE_ADDR start_pc) | |
c906108c | 524 | { |
1c0159e0 CV |
525 | CORE_ADDR pc; |
526 | struct sh_frame_cache cache; | |
527 | ||
528 | /* See if we can determine the end of the prologue via the symbol table. | |
529 | If so, then return either PC, or the PC after the prologue, whichever | |
530 | is greater. */ | |
531 | pc = after_prologue (start_pc); | |
cc17453a | 532 | |
1c0159e0 CV |
533 | /* If after_prologue returned a useful address, then use it. Else |
534 | fall back on the instruction skipping code. */ | |
535 | if (pc) | |
536 | return max (pc, start_pc); | |
c906108c | 537 | |
1c0159e0 CV |
538 | cache.sp_offset = -4; |
539 | pc = sh_analyze_prologue (start_pc, (CORE_ADDR) -1, &cache); | |
540 | if (!cache.uses_fp) | |
541 | return start_pc; | |
c906108c | 542 | |
1c0159e0 CV |
543 | return pc; |
544 | } | |
545 | ||
2e952408 | 546 | /* The ABI says: |
9a5cef92 EZ |
547 | |
548 | Aggregate types not bigger than 8 bytes that have the same size and | |
549 | alignment as one of the integer scalar types are returned in the | |
550 | same registers as the integer type they match. | |
551 | ||
552 | For example, a 2-byte aligned structure with size 2 bytes has the | |
553 | same size and alignment as a short int, and will be returned in R0. | |
554 | A 4-byte aligned structure with size 8 bytes has the same size and | |
555 | alignment as a long long int, and will be returned in R0 and R1. | |
556 | ||
557 | When an aggregate type is returned in R0 and R1, R0 contains the | |
558 | first four bytes of the aggregate, and R1 contains the | |
559 | remainder. If the size of the aggregate type is not a multiple of 4 | |
560 | bytes, the aggregate is tail-padded up to a multiple of 4 | |
561 | bytes. The value of the padding is undefined. For little-endian | |
562 | targets the padding will appear at the most significant end of the | |
563 | last element, for big-endian targets the padding appears at the | |
564 | least significant end of the last element. | |
565 | ||
566 | All other aggregate types are returned by address. The caller | |
567 | function passes the address of an area large enough to hold the | |
568 | aggregate value in R2. The called function stores the result in | |
7fe958be | 569 | this location. |
9a5cef92 EZ |
570 | |
571 | To reiterate, structs smaller than 8 bytes could also be returned | |
572 | in memory, if they don't pass the "same size and alignment as an | |
573 | integer type" rule. | |
574 | ||
575 | For example, in | |
576 | ||
577 | struct s { char c[3]; } wibble; | |
578 | struct s foo(void) { return wibble; } | |
579 | ||
580 | the return value from foo() will be in memory, not | |
581 | in R0, because there is no 3-byte integer type. | |
582 | ||
7fe958be EZ |
583 | Similarly, in |
584 | ||
585 | struct s { char c[2]; } wibble; | |
586 | struct s foo(void) { return wibble; } | |
587 | ||
588 | because a struct containing two chars has alignment 1, that matches | |
589 | type char, but size 2, that matches type short. There's no integer | |
590 | type that has alignment 1 and size 2, so the struct is returned in | |
591 | memory. | |
592 | ||
9a5cef92 EZ |
593 | */ |
594 | ||
1c0159e0 CV |
595 | static int |
596 | sh_use_struct_convention (int gcc_p, struct type *type) | |
597 | { | |
598 | int len = TYPE_LENGTH (type); | |
599 | int nelem = TYPE_NFIELDS (type); | |
3f997a97 CV |
600 | |
601 | /* Non-power of 2 length types and types bigger than 8 bytes (which don't | |
602 | fit in two registers anyway) use struct convention. */ | |
603 | if (len != 1 && len != 2 && len != 4 && len != 8) | |
604 | return 1; | |
605 | ||
606 | /* Scalar types and aggregate types with exactly one field are aligned | |
607 | by definition. They are returned in registers. */ | |
608 | if (nelem <= 1) | |
609 | return 0; | |
610 | ||
611 | /* If the first field in the aggregate has the same length as the entire | |
612 | aggregate type, the type is returned in registers. */ | |
613 | if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == len) | |
614 | return 0; | |
615 | ||
616 | /* If the size of the aggregate is 8 bytes and the first field is | |
617 | of size 4 bytes its alignment is equal to long long's alignment, | |
618 | so it's returned in registers. */ | |
619 | if (len == 8 && TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == 4) | |
620 | return 0; | |
621 | ||
622 | /* Otherwise use struct convention. */ | |
623 | return 1; | |
283150cd EZ |
624 | } |
625 | ||
cc17453a EZ |
626 | /* Extract from an array REGBUF containing the (raw) register state |
627 | the address in which a function should return its structure value, | |
628 | as a CORE_ADDR (or an expression that can be used as one). */ | |
b3df3fff | 629 | static CORE_ADDR |
48db5a3c | 630 | sh_extract_struct_value_address (struct regcache *regcache) |
cc17453a | 631 | { |
48db5a3c | 632 | ULONGEST addr; |
1c0159e0 | 633 | |
48db5a3c CV |
634 | regcache_cooked_read_unsigned (regcache, STRUCT_RETURN_REGNUM, &addr); |
635 | return addr; | |
cc17453a EZ |
636 | } |
637 | ||
19f59343 MS |
638 | static CORE_ADDR |
639 | sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp) | |
640 | { | |
641 | return sp & ~3; | |
642 | } | |
643 | ||
55ff77ac | 644 | /* Function: push_dummy_call (formerly push_arguments) |
c906108c SS |
645 | Setup the function arguments for calling a function in the inferior. |
646 | ||
85a453d5 | 647 | On the Renesas SH architecture, there are four registers (R4 to R7) |
c906108c SS |
648 | which are dedicated for passing function arguments. Up to the first |
649 | four arguments (depending on size) may go into these registers. | |
650 | The rest go on the stack. | |
651 | ||
6df2bf50 MS |
652 | MVS: Except on SH variants that have floating point registers. |
653 | In that case, float and double arguments are passed in the same | |
654 | manner, but using FP registers instead of GP registers. | |
655 | ||
c906108c SS |
656 | Arguments that are smaller than 4 bytes will still take up a whole |
657 | register or a whole 32-bit word on the stack, and will be | |
658 | right-justified in the register or the stack word. This includes | |
659 | chars, shorts, and small aggregate types. | |
660 | ||
661 | Arguments that are larger than 4 bytes may be split between two or | |
662 | more registers. If there are not enough registers free, an argument | |
663 | may be passed partly in a register (or registers), and partly on the | |
664 | stack. This includes doubles, long longs, and larger aggregates. | |
665 | As far as I know, there is no upper limit to the size of aggregates | |
666 | that will be passed in this way; in other words, the convention of | |
667 | passing a pointer to a large aggregate instead of a copy is not used. | |
668 | ||
6df2bf50 | 669 | MVS: The above appears to be true for the SH variants that do not |
55ff77ac | 670 | have an FPU, however those that have an FPU appear to copy the |
6df2bf50 MS |
671 | aggregate argument onto the stack (and not place it in registers) |
672 | if it is larger than 16 bytes (four GP registers). | |
673 | ||
c906108c SS |
674 | An exceptional case exists for struct arguments (and possibly other |
675 | aggregates such as arrays) if the size is larger than 4 bytes but | |
676 | not a multiple of 4 bytes. In this case the argument is never split | |
677 | between the registers and the stack, but instead is copied in its | |
678 | entirety onto the stack, AND also copied into as many registers as | |
679 | there is room for. In other words, space in registers permitting, | |
680 | two copies of the same argument are passed in. As far as I can tell, | |
681 | only the one on the stack is used, although that may be a function | |
682 | of the level of compiler optimization. I suspect this is a compiler | |
683 | bug. Arguments of these odd sizes are left-justified within the | |
684 | word (as opposed to arguments smaller than 4 bytes, which are | |
685 | right-justified). | |
c5aa993b | 686 | |
c906108c SS |
687 | If the function is to return an aggregate type such as a struct, it |
688 | is either returned in the normal return value register R0 (if its | |
689 | size is no greater than one byte), or else the caller must allocate | |
690 | space into which the callee will copy the return value (if the size | |
691 | is greater than one byte). In this case, a pointer to the return | |
692 | value location is passed into the callee in register R2, which does | |
693 | not displace any of the other arguments passed in via registers R4 | |
694 | to R7. */ | |
695 | ||
e5e33cd9 CV |
696 | /* Helper function to justify value in register according to endianess. */ |
697 | static char * | |
698 | sh_justify_value_in_reg (struct value *val, int len) | |
699 | { | |
700 | static char valbuf[4]; | |
701 | ||
617daa0e | 702 | memset (valbuf, 0, sizeof (valbuf)); |
e5e33cd9 CV |
703 | if (len < 4) |
704 | { | |
705 | /* value gets right-justified in the register or stack word */ | |
706 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
707 | memcpy (valbuf + (4 - len), (char *) VALUE_CONTENTS (val), len); | |
708 | else | |
709 | memcpy (valbuf, (char *) VALUE_CONTENTS (val), len); | |
710 | return valbuf; | |
711 | } | |
712 | return (char *) VALUE_CONTENTS (val); | |
617daa0e | 713 | } |
e5e33cd9 CV |
714 | |
715 | /* Helper function to eval number of bytes to allocate on stack. */ | |
716 | static CORE_ADDR | |
717 | sh_stack_allocsize (int nargs, struct value **args) | |
718 | { | |
719 | int stack_alloc = 0; | |
720 | while (nargs-- > 0) | |
721 | stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[nargs])) + 3) & ~3); | |
722 | return stack_alloc; | |
723 | } | |
724 | ||
725 | /* Helper functions for getting the float arguments right. Registers usage | |
726 | depends on the ABI and the endianess. The comments should enlighten how | |
727 | it's intended to work. */ | |
728 | ||
729 | /* This array stores which of the float arg registers are already in use. */ | |
730 | static int flt_argreg_array[FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM + 1]; | |
731 | ||
732 | /* This function just resets the above array to "no reg used so far". */ | |
733 | static void | |
734 | sh_init_flt_argreg (void) | |
735 | { | |
736 | memset (flt_argreg_array, 0, sizeof flt_argreg_array); | |
737 | } | |
738 | ||
739 | /* This function returns the next register to use for float arg passing. | |
740 | It returns either a valid value between FLOAT_ARG0_REGNUM and | |
741 | FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns | |
742 | FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available. | |
743 | ||
744 | Note that register number 0 in flt_argreg_array corresponds with the | |
745 | real float register fr4. In contrast to FLOAT_ARG0_REGNUM (value is | |
746 | 29) the parity of the register number is preserved, which is important | |
747 | for the double register passing test (see the "argreg & 1" test below). */ | |
748 | static int | |
749 | sh_next_flt_argreg (int len) | |
750 | { | |
751 | int argreg; | |
752 | ||
753 | /* First search for the next free register. */ | |
617daa0e CV |
754 | for (argreg = 0; argreg <= FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM; |
755 | ++argreg) | |
e5e33cd9 CV |
756 | if (!flt_argreg_array[argreg]) |
757 | break; | |
758 | ||
759 | /* No register left? */ | |
760 | if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM) | |
761 | return FLOAT_ARGLAST_REGNUM + 1; | |
762 | ||
763 | if (len == 8) | |
764 | { | |
765 | /* Doubles are always starting in a even register number. */ | |
766 | if (argreg & 1) | |
617daa0e | 767 | { |
e5e33cd9 CV |
768 | flt_argreg_array[argreg] = 1; |
769 | ||
770 | ++argreg; | |
771 | ||
617daa0e | 772 | /* No register left? */ |
e5e33cd9 CV |
773 | if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM) |
774 | return FLOAT_ARGLAST_REGNUM + 1; | |
775 | } | |
776 | /* Also mark the next register as used. */ | |
777 | flt_argreg_array[argreg + 1] = 1; | |
778 | } | |
779 | else if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) | |
780 | { | |
781 | /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */ | |
782 | if (!flt_argreg_array[argreg + 1]) | |
783 | ++argreg; | |
784 | } | |
785 | flt_argreg_array[argreg] = 1; | |
786 | return FLOAT_ARG0_REGNUM + argreg; | |
787 | } | |
788 | ||
afce3d2a CV |
789 | /* Helper function which figures out, if a type is treated like a float type. |
790 | ||
2e952408 | 791 | The FPU ABIs have a special way how to treat types as float types. |
afce3d2a CV |
792 | Structures with exactly one member, which is of type float or double, are |
793 | treated exactly as the base types float or double: | |
794 | ||
795 | struct sf { | |
796 | float f; | |
797 | }; | |
798 | ||
799 | struct sd { | |
800 | double d; | |
801 | }; | |
802 | ||
803 | are handled the same way as just | |
804 | ||
805 | float f; | |
806 | ||
807 | double d; | |
808 | ||
809 | As a result, arguments of these struct types are pushed into floating point | |
810 | registers exactly as floats or doubles, using the same decision algorithm. | |
811 | ||
812 | The same is valid if these types are used as function return types. The | |
813 | above structs are returned in fr0 resp. fr0,fr1 instead of in r0, r0,r1 | |
814 | or even using struct convention as it is for other structs. */ | |
815 | ||
816 | static int | |
817 | sh_treat_as_flt_p (struct type *type) | |
818 | { | |
819 | int len = TYPE_LENGTH (type); | |
820 | ||
821 | /* Ordinary float types are obviously treated as float. */ | |
822 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
823 | return 1; | |
824 | /* Otherwise non-struct types are not treated as float. */ | |
825 | if (TYPE_CODE (type) != TYPE_CODE_STRUCT) | |
826 | return 0; | |
827 | /* Otherwise structs with more than one memeber are not treated as float. */ | |
828 | if (TYPE_NFIELDS (type) != 1) | |
829 | return 0; | |
830 | /* Otherwise if the type of that member is float, the whole type is | |
831 | treated as float. */ | |
832 | if (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) == TYPE_CODE_FLT) | |
833 | return 1; | |
834 | /* Otherwise it's not treated as float. */ | |
835 | return 0; | |
836 | } | |
837 | ||
cc17453a | 838 | static CORE_ADDR |
617daa0e | 839 | sh_push_dummy_call_fpu (struct gdbarch *gdbarch, |
6df2bf50 | 840 | CORE_ADDR func_addr, |
617daa0e | 841 | struct regcache *regcache, |
6df2bf50 | 842 | CORE_ADDR bp_addr, int nargs, |
617daa0e | 843 | struct value **args, |
6df2bf50 MS |
844 | CORE_ADDR sp, int struct_return, |
845 | CORE_ADDR struct_addr) | |
846 | { | |
e5e33cd9 CV |
847 | int stack_offset = 0; |
848 | int argreg = ARG0_REGNUM; | |
8748518b | 849 | int flt_argreg = 0; |
6df2bf50 MS |
850 | int argnum; |
851 | struct type *type; | |
852 | CORE_ADDR regval; | |
853 | char *val; | |
8748518b | 854 | int len, reg_size = 0; |
afce3d2a CV |
855 | int pass_on_stack = 0; |
856 | int treat_as_flt; | |
6df2bf50 MS |
857 | |
858 | /* first force sp to a 4-byte alignment */ | |
859 | sp = sh_frame_align (gdbarch, sp); | |
860 | ||
6df2bf50 | 861 | if (struct_return) |
1c0159e0 | 862 | regcache_cooked_write_unsigned (regcache, |
617daa0e | 863 | STRUCT_RETURN_REGNUM, struct_addr); |
6df2bf50 | 864 | |
e5e33cd9 CV |
865 | /* make room on stack for args */ |
866 | sp -= sh_stack_allocsize (nargs, args); | |
867 | ||
868 | /* Initialize float argument mechanism. */ | |
869 | sh_init_flt_argreg (); | |
6df2bf50 MS |
870 | |
871 | /* Now load as many as possible of the first arguments into | |
872 | registers, and push the rest onto the stack. There are 16 bytes | |
873 | in four registers available. Loop thru args from first to last. */ | |
e5e33cd9 | 874 | for (argnum = 0; argnum < nargs; argnum++) |
6df2bf50 MS |
875 | { |
876 | type = VALUE_TYPE (args[argnum]); | |
877 | len = TYPE_LENGTH (type); | |
e5e33cd9 CV |
878 | val = sh_justify_value_in_reg (args[argnum], len); |
879 | ||
880 | /* Some decisions have to be made how various types are handled. | |
881 | This also differs in different ABIs. */ | |
882 | pass_on_stack = 0; | |
e5e33cd9 CV |
883 | |
884 | /* Find out the next register to use for a floating point value. */ | |
afce3d2a CV |
885 | treat_as_flt = sh_treat_as_flt_p (type); |
886 | if (treat_as_flt) | |
617daa0e | 887 | flt_argreg = sh_next_flt_argreg (len); |
afce3d2a CV |
888 | /* In contrast to non-FPU CPUs, arguments are never split between |
889 | registers and stack. If an argument doesn't fit in the remaining | |
890 | registers it's always pushed entirely on the stack. */ | |
891 | else if (len > ((ARGLAST_REGNUM - argreg + 1) * 4)) | |
892 | pass_on_stack = 1; | |
48db5a3c | 893 | |
6df2bf50 MS |
894 | while (len > 0) |
895 | { | |
afce3d2a CV |
896 | if ((treat_as_flt && flt_argreg > FLOAT_ARGLAST_REGNUM) |
897 | || (!treat_as_flt && (argreg > ARGLAST_REGNUM | |
898 | || pass_on_stack))) | |
617daa0e | 899 | { |
afce3d2a | 900 | /* The data goes entirely on the stack, 4-byte aligned. */ |
e5e33cd9 CV |
901 | reg_size = (len + 3) & ~3; |
902 | write_memory (sp + stack_offset, val, reg_size); | |
903 | stack_offset += reg_size; | |
6df2bf50 | 904 | } |
afce3d2a | 905 | else if (treat_as_flt && flt_argreg <= FLOAT_ARGLAST_REGNUM) |
6df2bf50 | 906 | { |
e5e33cd9 CV |
907 | /* Argument goes in a float argument register. */ |
908 | reg_size = register_size (gdbarch, flt_argreg); | |
909 | regval = extract_unsigned_integer (val, reg_size); | |
2e952408 CV |
910 | /* In little endian mode, float types taking two registers |
911 | (doubles on sh4, long doubles on sh2e, sh3e and sh4) must | |
912 | be stored swapped in the argument registers. The below | |
913 | code first writes the first 32 bits in the next but one | |
914 | register, increments the val and len values accordingly | |
915 | and then proceeds as normal by writing the second 32 bits | |
916 | into the next register. */ | |
917 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE | |
918 | && TYPE_LENGTH (type) == 2 * reg_size) | |
919 | { | |
920 | regcache_cooked_write_unsigned (regcache, flt_argreg + 1, | |
921 | regval); | |
922 | val += reg_size; | |
923 | len -= reg_size; | |
924 | regval = extract_unsigned_integer (val, reg_size); | |
925 | } | |
6df2bf50 MS |
926 | regcache_cooked_write_unsigned (regcache, flt_argreg++, regval); |
927 | } | |
afce3d2a | 928 | else if (!treat_as_flt && argreg <= ARGLAST_REGNUM) |
e5e33cd9 | 929 | { |
6df2bf50 | 930 | /* there's room in a register */ |
e5e33cd9 CV |
931 | reg_size = register_size (gdbarch, argreg); |
932 | regval = extract_unsigned_integer (val, reg_size); | |
6df2bf50 MS |
933 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
934 | } | |
afce3d2a | 935 | /* Store the value one register at a time or in one step on stack. */ |
e5e33cd9 CV |
936 | len -= reg_size; |
937 | val += reg_size; | |
6df2bf50 MS |
938 | } |
939 | } | |
940 | ||
941 | /* Store return address. */ | |
55ff77ac | 942 | regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr); |
6df2bf50 MS |
943 | |
944 | /* Update stack pointer. */ | |
945 | regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp); | |
946 | ||
947 | return sp; | |
948 | } | |
949 | ||
950 | static CORE_ADDR | |
617daa0e | 951 | sh_push_dummy_call_nofpu (struct gdbarch *gdbarch, |
6df2bf50 | 952 | CORE_ADDR func_addr, |
617daa0e CV |
953 | struct regcache *regcache, |
954 | CORE_ADDR bp_addr, | |
955 | int nargs, struct value **args, | |
956 | CORE_ADDR sp, int struct_return, | |
6df2bf50 | 957 | CORE_ADDR struct_addr) |
c906108c | 958 | { |
e5e33cd9 CV |
959 | int stack_offset = 0; |
960 | int argreg = ARG0_REGNUM; | |
c906108c SS |
961 | int argnum; |
962 | struct type *type; | |
963 | CORE_ADDR regval; | |
964 | char *val; | |
e5e33cd9 | 965 | int len, reg_size; |
c906108c SS |
966 | |
967 | /* first force sp to a 4-byte alignment */ | |
19f59343 | 968 | sp = sh_frame_align (gdbarch, sp); |
c906108c | 969 | |
c906108c | 970 | if (struct_return) |
55ff77ac | 971 | regcache_cooked_write_unsigned (regcache, |
617daa0e | 972 | STRUCT_RETURN_REGNUM, struct_addr); |
c906108c | 973 | |
e5e33cd9 CV |
974 | /* make room on stack for args */ |
975 | sp -= sh_stack_allocsize (nargs, args); | |
c906108c | 976 | |
c906108c SS |
977 | /* Now load as many as possible of the first arguments into |
978 | registers, and push the rest onto the stack. There are 16 bytes | |
979 | in four registers available. Loop thru args from first to last. */ | |
e5e33cd9 | 980 | for (argnum = 0; argnum < nargs; argnum++) |
617daa0e | 981 | { |
c906108c | 982 | type = VALUE_TYPE (args[argnum]); |
c5aa993b | 983 | len = TYPE_LENGTH (type); |
e5e33cd9 | 984 | val = sh_justify_value_in_reg (args[argnum], len); |
c906108c | 985 | |
c906108c SS |
986 | while (len > 0) |
987 | { | |
e5e33cd9 | 988 | if (argreg > ARGLAST_REGNUM) |
617daa0e | 989 | { |
e5e33cd9 CV |
990 | /* The remainder of the data goes entirely on the stack, |
991 | 4-byte aligned. */ | |
992 | reg_size = (len + 3) & ~3; | |
993 | write_memory (sp + stack_offset, val, reg_size); | |
617daa0e | 994 | stack_offset += reg_size; |
c906108c | 995 | } |
e5e33cd9 | 996 | else if (argreg <= ARGLAST_REGNUM) |
617daa0e | 997 | { |
3bbfbb92 | 998 | /* there's room in a register */ |
e5e33cd9 CV |
999 | reg_size = register_size (gdbarch, argreg); |
1000 | regval = extract_unsigned_integer (val, reg_size); | |
48db5a3c | 1001 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
c906108c | 1002 | } |
e5e33cd9 CV |
1003 | /* Store the value reg_size bytes at a time. This means that things |
1004 | larger than reg_size bytes may go partly in registers and partly | |
c906108c | 1005 | on the stack. */ |
e5e33cd9 CV |
1006 | len -= reg_size; |
1007 | val += reg_size; | |
c906108c SS |
1008 | } |
1009 | } | |
48db5a3c CV |
1010 | |
1011 | /* Store return address. */ | |
55ff77ac | 1012 | regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr); |
48db5a3c CV |
1013 | |
1014 | /* Update stack pointer. */ | |
1015 | regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp); | |
1016 | ||
c906108c SS |
1017 | return sp; |
1018 | } | |
1019 | ||
cc17453a EZ |
1020 | /* Find a function's return value in the appropriate registers (in |
1021 | regbuf), and copy it into valbuf. Extract from an array REGBUF | |
1022 | containing the (raw) register state a function return value of type | |
1023 | TYPE, and copy that, in virtual format, into VALBUF. */ | |
1024 | static void | |
48db5a3c CV |
1025 | sh_default_extract_return_value (struct type *type, struct regcache *regcache, |
1026 | void *valbuf) | |
c906108c | 1027 | { |
cc17453a | 1028 | int len = TYPE_LENGTH (type); |
3116c80a EZ |
1029 | int return_register = R0_REGNUM; |
1030 | int offset; | |
617daa0e | 1031 | |
cc17453a | 1032 | if (len <= 4) |
3116c80a | 1033 | { |
48db5a3c CV |
1034 | ULONGEST c; |
1035 | ||
1036 | regcache_cooked_read_unsigned (regcache, R0_REGNUM, &c); | |
1037 | store_unsigned_integer (valbuf, len, c); | |
3116c80a | 1038 | } |
48db5a3c | 1039 | else if (len == 8) |
3116c80a | 1040 | { |
48db5a3c CV |
1041 | int i, regnum = R0_REGNUM; |
1042 | for (i = 0; i < len; i += 4) | |
617daa0e | 1043 | regcache_raw_read (regcache, regnum++, (char *) valbuf + i); |
3116c80a EZ |
1044 | } |
1045 | else | |
1046 | error ("bad size for return value"); | |
1047 | } | |
1048 | ||
1049 | static void | |
48db5a3c CV |
1050 | sh3e_sh4_extract_return_value (struct type *type, struct regcache *regcache, |
1051 | void *valbuf) | |
3116c80a | 1052 | { |
afce3d2a | 1053 | if (sh_treat_as_flt_p (type)) |
3116c80a | 1054 | { |
48db5a3c CV |
1055 | int len = TYPE_LENGTH (type); |
1056 | int i, regnum = FP0_REGNUM; | |
1057 | for (i = 0; i < len; i += 4) | |
2e952408 CV |
1058 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) |
1059 | regcache_raw_read (regcache, regnum++, (char *) valbuf + len - 4 - i); | |
1060 | else | |
1061 | regcache_raw_read (regcache, regnum++, (char *) valbuf + i); | |
3116c80a | 1062 | } |
cc17453a | 1063 | else |
48db5a3c | 1064 | sh_default_extract_return_value (type, regcache, valbuf); |
cc17453a | 1065 | } |
c906108c | 1066 | |
cc17453a EZ |
1067 | /* Write into appropriate registers a function return value |
1068 | of type TYPE, given in virtual format. | |
1069 | If the architecture is sh4 or sh3e, store a function's return value | |
1070 | in the R0 general register or in the FP0 floating point register, | |
1071 | depending on the type of the return value. In all the other cases | |
3bbfbb92 | 1072 | the result is stored in r0, left-justified. */ |
cc17453a | 1073 | static void |
48db5a3c CV |
1074 | sh_default_store_return_value (struct type *type, struct regcache *regcache, |
1075 | const void *valbuf) | |
cc17453a | 1076 | { |
48db5a3c CV |
1077 | ULONGEST val; |
1078 | int len = TYPE_LENGTH (type); | |
d19b71be | 1079 | |
48db5a3c | 1080 | if (len <= 4) |
d19b71be | 1081 | { |
48db5a3c CV |
1082 | val = extract_unsigned_integer (valbuf, len); |
1083 | regcache_cooked_write_unsigned (regcache, R0_REGNUM, val); | |
d19b71be MS |
1084 | } |
1085 | else | |
48db5a3c CV |
1086 | { |
1087 | int i, regnum = R0_REGNUM; | |
1088 | for (i = 0; i < len; i += 4) | |
617daa0e | 1089 | regcache_raw_write (regcache, regnum++, (char *) valbuf + i); |
48db5a3c | 1090 | } |
cc17453a | 1091 | } |
c906108c | 1092 | |
cc17453a | 1093 | static void |
48db5a3c CV |
1094 | sh3e_sh4_store_return_value (struct type *type, struct regcache *regcache, |
1095 | const void *valbuf) | |
cc17453a | 1096 | { |
afce3d2a | 1097 | if (sh_treat_as_flt_p (type)) |
48db5a3c CV |
1098 | { |
1099 | int len = TYPE_LENGTH (type); | |
1100 | int i, regnum = FP0_REGNUM; | |
1101 | for (i = 0; i < len; i += 4) | |
617daa0e | 1102 | regcache_raw_write (regcache, regnum++, (char *) valbuf + i); |
48db5a3c | 1103 | } |
cc17453a | 1104 | else |
48db5a3c | 1105 | sh_default_store_return_value (type, regcache, valbuf); |
c906108c SS |
1106 | } |
1107 | ||
1108 | /* Print the registers in a form similar to the E7000 */ | |
1109 | ||
1110 | static void | |
fba45db2 | 1111 | sh_generic_show_regs (void) |
c906108c | 1112 | { |
cc17453a EZ |
1113 | printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", |
1114 | paddr (read_register (PC_REGNUM)), | |
55ff77ac CV |
1115 | (long) read_register (SR_REGNUM), |
1116 | (long) read_register (PR_REGNUM), | |
cc17453a EZ |
1117 | (long) read_register (MACH_REGNUM), |
1118 | (long) read_register (MACL_REGNUM)); | |
1119 | ||
1120 | printf_filtered ("GBR=%08lx VBR=%08lx", | |
1121 | (long) read_register (GBR_REGNUM), | |
1122 | (long) read_register (VBR_REGNUM)); | |
1123 | ||
617daa0e CV |
1124 | printf_filtered |
1125 | ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1126 | (long) read_register (0), (long) read_register (1), | |
1127 | (long) read_register (2), (long) read_register (3), | |
1128 | (long) read_register (4), (long) read_register (5), | |
1129 | (long) read_register (6), (long) read_register (7)); | |
cc17453a | 1130 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
617daa0e CV |
1131 | (long) read_register (8), (long) read_register (9), |
1132 | (long) read_register (10), (long) read_register (11), | |
1133 | (long) read_register (12), (long) read_register (13), | |
1134 | (long) read_register (14), (long) read_register (15)); | |
cc17453a | 1135 | } |
c906108c | 1136 | |
cc17453a | 1137 | static void |
fba45db2 | 1138 | sh3_show_regs (void) |
cc17453a | 1139 | { |
d4f3574e SS |
1140 | printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", |
1141 | paddr (read_register (PC_REGNUM)), | |
55ff77ac CV |
1142 | (long) read_register (SR_REGNUM), |
1143 | (long) read_register (PR_REGNUM), | |
d4f3574e SS |
1144 | (long) read_register (MACH_REGNUM), |
1145 | (long) read_register (MACL_REGNUM)); | |
1146 | ||
1147 | printf_filtered ("GBR=%08lx VBR=%08lx", | |
1148 | (long) read_register (GBR_REGNUM), | |
1149 | (long) read_register (VBR_REGNUM)); | |
cc17453a | 1150 | printf_filtered (" SSR=%08lx SPC=%08lx", |
617daa0e | 1151 | (long) read_register (SSR_REGNUM), |
f2ea0907 | 1152 | (long) read_register (SPC_REGNUM)); |
c906108c | 1153 | |
617daa0e CV |
1154 | printf_filtered |
1155 | ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1156 | (long) read_register (0), (long) read_register (1), | |
1157 | (long) read_register (2), (long) read_register (3), | |
1158 | (long) read_register (4), (long) read_register (5), | |
1159 | (long) read_register (6), (long) read_register (7)); | |
d4f3574e | 1160 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
617daa0e CV |
1161 | (long) read_register (8), (long) read_register (9), |
1162 | (long) read_register (10), (long) read_register (11), | |
1163 | (long) read_register (12), (long) read_register (13), | |
1164 | (long) read_register (14), (long) read_register (15)); | |
c906108c SS |
1165 | } |
1166 | ||
53116e27 | 1167 | |
2d188dd3 NC |
1168 | static void |
1169 | sh2e_show_regs (void) | |
1170 | { | |
1171 | printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", | |
1172 | paddr (read_register (PC_REGNUM)), | |
1173 | (long) read_register (SR_REGNUM), | |
1174 | (long) read_register (PR_REGNUM), | |
1175 | (long) read_register (MACH_REGNUM), | |
1176 | (long) read_register (MACL_REGNUM)); | |
1177 | ||
1178 | printf_filtered ("GBR=%08lx VBR=%08lx", | |
1179 | (long) read_register (GBR_REGNUM), | |
1180 | (long) read_register (VBR_REGNUM)); | |
1181 | printf_filtered (" FPUL=%08lx FPSCR=%08lx", | |
617daa0e CV |
1182 | (long) read_register (FPUL_REGNUM), |
1183 | (long) read_register (FPSCR_REGNUM)); | |
1184 | ||
1185 | printf_filtered | |
1186 | ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1187 | (long) read_register (0), (long) read_register (1), | |
1188 | (long) read_register (2), (long) read_register (3), | |
1189 | (long) read_register (4), (long) read_register (5), | |
1190 | (long) read_register (6), (long) read_register (7)); | |
2d188dd3 | 1191 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
617daa0e CV |
1192 | (long) read_register (8), (long) read_register (9), |
1193 | (long) read_register (10), (long) read_register (11), | |
1194 | (long) read_register (12), (long) read_register (13), | |
1195 | (long) read_register (14), (long) read_register (15)); | |
1196 | ||
1197 | printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 0), (long) read_register (FP0_REGNUM + 1), (long) read_register (FP0_REGNUM + 2), (long) read_register (FP0_REGNUM + 3), (long) read_register (FP0_REGNUM + 4), (long) read_register (FP0_REGNUM + 5), (long) read_register (FP0_REGNUM + 6), (long) read_register (FP0_REGNUM + 7)); | |
1198 | printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 8), (long) read_register (FP0_REGNUM + 9), (long) read_register (FP0_REGNUM + 10), (long) read_register (FP0_REGNUM + 11), (long) read_register (FP0_REGNUM + 12), (long) read_register (FP0_REGNUM + 13), (long) read_register (FP0_REGNUM + 14), (long) read_register (FP0_REGNUM + 15)); | |
2d188dd3 NC |
1199 | } |
1200 | ||
cc17453a | 1201 | static void |
fba45db2 | 1202 | sh3e_show_regs (void) |
cc17453a EZ |
1203 | { |
1204 | printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", | |
1205 | paddr (read_register (PC_REGNUM)), | |
55ff77ac CV |
1206 | (long) read_register (SR_REGNUM), |
1207 | (long) read_register (PR_REGNUM), | |
cc17453a EZ |
1208 | (long) read_register (MACH_REGNUM), |
1209 | (long) read_register (MACL_REGNUM)); | |
1210 | ||
1211 | printf_filtered ("GBR=%08lx VBR=%08lx", | |
1212 | (long) read_register (GBR_REGNUM), | |
1213 | (long) read_register (VBR_REGNUM)); | |
1214 | printf_filtered (" SSR=%08lx SPC=%08lx", | |
f2ea0907 CV |
1215 | (long) read_register (SSR_REGNUM), |
1216 | (long) read_register (SPC_REGNUM)); | |
cc17453a | 1217 | printf_filtered (" FPUL=%08lx FPSCR=%08lx", |
f2ea0907 CV |
1218 | (long) read_register (FPUL_REGNUM), |
1219 | (long) read_register (FPSCR_REGNUM)); | |
c906108c | 1220 | |
617daa0e CV |
1221 | printf_filtered |
1222 | ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1223 | (long) read_register (0), (long) read_register (1), | |
1224 | (long) read_register (2), (long) read_register (3), | |
1225 | (long) read_register (4), (long) read_register (5), | |
1226 | (long) read_register (6), (long) read_register (7)); | |
cc17453a | 1227 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
617daa0e CV |
1228 | (long) read_register (8), (long) read_register (9), |
1229 | (long) read_register (10), (long) read_register (11), | |
1230 | (long) read_register (12), (long) read_register (13), | |
1231 | (long) read_register (14), (long) read_register (15)); | |
1232 | ||
1233 | printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 0), (long) read_register (FP0_REGNUM + 1), (long) read_register (FP0_REGNUM + 2), (long) read_register (FP0_REGNUM + 3), (long) read_register (FP0_REGNUM + 4), (long) read_register (FP0_REGNUM + 5), (long) read_register (FP0_REGNUM + 6), (long) read_register (FP0_REGNUM + 7)); | |
1234 | printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 8), (long) read_register (FP0_REGNUM + 9), (long) read_register (FP0_REGNUM + 10), (long) read_register (FP0_REGNUM + 11), (long) read_register (FP0_REGNUM + 12), (long) read_register (FP0_REGNUM + 13), (long) read_register (FP0_REGNUM + 14), (long) read_register (FP0_REGNUM + 15)); | |
cc17453a EZ |
1235 | } |
1236 | ||
1237 | static void | |
fba45db2 | 1238 | sh3_dsp_show_regs (void) |
c906108c | 1239 | { |
cc17453a EZ |
1240 | printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", |
1241 | paddr (read_register (PC_REGNUM)), | |
55ff77ac CV |
1242 | (long) read_register (SR_REGNUM), |
1243 | (long) read_register (PR_REGNUM), | |
cc17453a EZ |
1244 | (long) read_register (MACH_REGNUM), |
1245 | (long) read_register (MACL_REGNUM)); | |
c906108c | 1246 | |
cc17453a EZ |
1247 | printf_filtered ("GBR=%08lx VBR=%08lx", |
1248 | (long) read_register (GBR_REGNUM), | |
1249 | (long) read_register (VBR_REGNUM)); | |
1250 | ||
1251 | printf_filtered (" SSR=%08lx SPC=%08lx", | |
f2ea0907 CV |
1252 | (long) read_register (SSR_REGNUM), |
1253 | (long) read_register (SPC_REGNUM)); | |
cc17453a | 1254 | |
617daa0e CV |
1255 | printf_filtered (" DSR=%08lx", (long) read_register (DSR_REGNUM)); |
1256 | ||
1257 | printf_filtered | |
1258 | ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1259 | (long) read_register (0), (long) read_register (1), | |
1260 | (long) read_register (2), (long) read_register (3), | |
1261 | (long) read_register (4), (long) read_register (5), | |
1262 | (long) read_register (6), (long) read_register (7)); | |
cc17453a | 1263 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
617daa0e CV |
1264 | (long) read_register (8), (long) read_register (9), |
1265 | (long) read_register (10), (long) read_register (11), | |
1266 | (long) read_register (12), (long) read_register (13), | |
1267 | (long) read_register (14), (long) read_register (15)); | |
1268 | ||
1269 | printf_filtered | |
1270 | ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n", | |
1271 | (long) read_register (A0G_REGNUM) & 0xff, | |
1272 | (long) read_register (A0_REGNUM), (long) read_register (M0_REGNUM), | |
1273 | (long) read_register (X0_REGNUM), (long) read_register (Y0_REGNUM), | |
1274 | (long) read_register (RS_REGNUM), (long) read_register (MOD_REGNUM)); | |
cc17453a | 1275 | printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n", |
f2ea0907 CV |
1276 | (long) read_register (A1G_REGNUM) & 0xff, |
1277 | (long) read_register (A1_REGNUM), | |
1278 | (long) read_register (M1_REGNUM), | |
1279 | (long) read_register (X1_REGNUM), | |
1280 | (long) read_register (Y1_REGNUM), | |
1281 | (long) read_register (RE_REGNUM)); | |
c906108c SS |
1282 | } |
1283 | ||
cc17453a | 1284 | static void |
fba45db2 | 1285 | sh4_show_regs (void) |
cc17453a | 1286 | { |
f2ea0907 | 1287 | int pr = read_register (FPSCR_REGNUM) & 0x80000; |
cc17453a EZ |
1288 | printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", |
1289 | paddr (read_register (PC_REGNUM)), | |
55ff77ac CV |
1290 | (long) read_register (SR_REGNUM), |
1291 | (long) read_register (PR_REGNUM), | |
cc17453a EZ |
1292 | (long) read_register (MACH_REGNUM), |
1293 | (long) read_register (MACL_REGNUM)); | |
1294 | ||
1295 | printf_filtered ("GBR=%08lx VBR=%08lx", | |
1296 | (long) read_register (GBR_REGNUM), | |
1297 | (long) read_register (VBR_REGNUM)); | |
1298 | printf_filtered (" SSR=%08lx SPC=%08lx", | |
f2ea0907 CV |
1299 | (long) read_register (SSR_REGNUM), |
1300 | (long) read_register (SPC_REGNUM)); | |
cc17453a | 1301 | printf_filtered (" FPUL=%08lx FPSCR=%08lx", |
f2ea0907 CV |
1302 | (long) read_register (FPUL_REGNUM), |
1303 | (long) read_register (FPSCR_REGNUM)); | |
cc17453a | 1304 | |
617daa0e CV |
1305 | printf_filtered |
1306 | ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1307 | (long) read_register (0), (long) read_register (1), | |
1308 | (long) read_register (2), (long) read_register (3), | |
1309 | (long) read_register (4), (long) read_register (5), | |
1310 | (long) read_register (6), (long) read_register (7)); | |
cc17453a | 1311 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
617daa0e CV |
1312 | (long) read_register (8), (long) read_register (9), |
1313 | (long) read_register (10), (long) read_register (11), | |
1314 | (long) read_register (12), (long) read_register (13), | |
1315 | (long) read_register (14), (long) read_register (15)); | |
cc17453a EZ |
1316 | |
1317 | printf_filtered ((pr | |
1318 | ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n" | |
617daa0e CV |
1319 | : |
1320 | "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), | |
cc17453a EZ |
1321 | (long) read_register (FP0_REGNUM + 0), |
1322 | (long) read_register (FP0_REGNUM + 1), | |
1323 | (long) read_register (FP0_REGNUM + 2), | |
1324 | (long) read_register (FP0_REGNUM + 3), | |
1325 | (long) read_register (FP0_REGNUM + 4), | |
1326 | (long) read_register (FP0_REGNUM + 5), | |
1327 | (long) read_register (FP0_REGNUM + 6), | |
1328 | (long) read_register (FP0_REGNUM + 7)); | |
617daa0e CV |
1329 | printf_filtered ((pr ? |
1330 | "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n" : | |
1331 | "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), | |
cc17453a EZ |
1332 | (long) read_register (FP0_REGNUM + 8), |
1333 | (long) read_register (FP0_REGNUM + 9), | |
1334 | (long) read_register (FP0_REGNUM + 10), | |
1335 | (long) read_register (FP0_REGNUM + 11), | |
1336 | (long) read_register (FP0_REGNUM + 12), | |
1337 | (long) read_register (FP0_REGNUM + 13), | |
1338 | (long) read_register (FP0_REGNUM + 14), | |
1339 | (long) read_register (FP0_REGNUM + 15)); | |
1340 | } | |
1341 | ||
1342 | static void | |
fba45db2 | 1343 | sh_dsp_show_regs (void) |
cc17453a EZ |
1344 | { |
1345 | printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n", | |
1346 | paddr (read_register (PC_REGNUM)), | |
55ff77ac CV |
1347 | (long) read_register (SR_REGNUM), |
1348 | (long) read_register (PR_REGNUM), | |
cc17453a EZ |
1349 | (long) read_register (MACH_REGNUM), |
1350 | (long) read_register (MACL_REGNUM)); | |
1351 | ||
1352 | printf_filtered ("GBR=%08lx VBR=%08lx", | |
1353 | (long) read_register (GBR_REGNUM), | |
1354 | (long) read_register (VBR_REGNUM)); | |
1355 | ||
617daa0e CV |
1356 | printf_filtered (" DSR=%08lx", (long) read_register (DSR_REGNUM)); |
1357 | ||
1358 | printf_filtered | |
1359 | ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1360 | (long) read_register (0), (long) read_register (1), | |
1361 | (long) read_register (2), (long) read_register (3), | |
1362 | (long) read_register (4), (long) read_register (5), | |
1363 | (long) read_register (6), (long) read_register (7)); | |
cc17453a | 1364 | printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", |
617daa0e CV |
1365 | (long) read_register (8), (long) read_register (9), |
1366 | (long) read_register (10), (long) read_register (11), | |
1367 | (long) read_register (12), (long) read_register (13), | |
1368 | (long) read_register (14), (long) read_register (15)); | |
1369 | ||
1370 | printf_filtered | |
1371 | ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n", | |
1372 | (long) read_register (A0G_REGNUM) & 0xff, | |
1373 | (long) read_register (A0_REGNUM), (long) read_register (M0_REGNUM), | |
1374 | (long) read_register (X0_REGNUM), (long) read_register (Y0_REGNUM), | |
1375 | (long) read_register (RS_REGNUM), (long) read_register (MOD_REGNUM)); | |
cc17453a | 1376 | printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n", |
f2ea0907 CV |
1377 | (long) read_register (A1G_REGNUM) & 0xff, |
1378 | (long) read_register (A1_REGNUM), | |
1379 | (long) read_register (M1_REGNUM), | |
1380 | (long) read_register (X1_REGNUM), | |
1381 | (long) read_register (Y1_REGNUM), | |
1382 | (long) read_register (RE_REGNUM)); | |
cc17453a EZ |
1383 | } |
1384 | ||
a78f21af AC |
1385 | static void |
1386 | sh_show_regs_command (char *args, int from_tty) | |
53116e27 EZ |
1387 | { |
1388 | if (sh_show_regs) | |
617daa0e | 1389 | (*sh_show_regs) (); |
53116e27 EZ |
1390 | } |
1391 | ||
cc17453a EZ |
1392 | /* Return the GDB type object for the "standard" data type |
1393 | of data in register N. */ | |
cc17453a | 1394 | static struct type * |
48db5a3c | 1395 | sh_sh3e_register_type (struct gdbarch *gdbarch, int reg_nr) |
cc17453a EZ |
1396 | { |
1397 | if ((reg_nr >= FP0_REGNUM | |
617daa0e | 1398 | && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM)) |
cc17453a | 1399 | return builtin_type_float; |
8db62801 | 1400 | else |
cc17453a EZ |
1401 | return builtin_type_int; |
1402 | } | |
1403 | ||
7f4dbe94 EZ |
1404 | static struct type * |
1405 | sh_sh4_build_float_register_type (int high) | |
1406 | { | |
1407 | struct type *temp; | |
1408 | ||
1409 | temp = create_range_type (NULL, builtin_type_int, 0, high); | |
1410 | return create_array_type (NULL, builtin_type_float, temp); | |
1411 | } | |
1412 | ||
53116e27 | 1413 | static struct type * |
48db5a3c | 1414 | sh_sh4_register_type (struct gdbarch *gdbarch, int reg_nr) |
53116e27 EZ |
1415 | { |
1416 | if ((reg_nr >= FP0_REGNUM | |
617daa0e | 1417 | && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM)) |
53116e27 | 1418 | return builtin_type_float; |
617daa0e | 1419 | else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM) |
53116e27 | 1420 | return builtin_type_double; |
617daa0e | 1421 | else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM) |
53116e27 EZ |
1422 | return sh_sh4_build_float_register_type (3); |
1423 | else | |
1424 | return builtin_type_int; | |
1425 | } | |
1426 | ||
cc17453a | 1427 | static struct type * |
48db5a3c | 1428 | sh_default_register_type (struct gdbarch *gdbarch, int reg_nr) |
cc17453a EZ |
1429 | { |
1430 | return builtin_type_int; | |
1431 | } | |
1432 | ||
fb409745 EZ |
1433 | /* On the sh4, the DRi pseudo registers are problematic if the target |
1434 | is little endian. When the user writes one of those registers, for | |
1435 | instance with 'ser var $dr0=1', we want the double to be stored | |
1436 | like this: | |
1437 | fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f | |
1438 | fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00 | |
1439 | ||
1440 | This corresponds to little endian byte order & big endian word | |
1441 | order. However if we let gdb write the register w/o conversion, it | |
1442 | will write fr0 and fr1 this way: | |
1443 | fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00 | |
1444 | fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f | |
1445 | because it will consider fr0 and fr1 as a single LE stretch of memory. | |
1446 | ||
1447 | To achieve what we want we must force gdb to store things in | |
1448 | floatformat_ieee_double_littlebyte_bigword (which is defined in | |
1449 | include/floatformat.h and libiberty/floatformat.c. | |
1450 | ||
1451 | In case the target is big endian, there is no problem, the | |
1452 | raw bytes will look like: | |
1453 | fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00 | |
1454 | fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00 | |
1455 | ||
1456 | The other pseudo registers (the FVs) also don't pose a problem | |
1457 | because they are stored as 4 individual FP elements. */ | |
1458 | ||
7bd872fe | 1459 | static void |
fb409745 | 1460 | sh_sh4_register_convert_to_virtual (int regnum, struct type *type, |
617daa0e | 1461 | char *from, char *to) |
55ff77ac | 1462 | { |
617daa0e | 1463 | if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM) |
283150cd EZ |
1464 | { |
1465 | DOUBLEST val; | |
617daa0e CV |
1466 | floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, |
1467 | from, &val); | |
55ff77ac | 1468 | store_typed_floating (to, type, val); |
283150cd EZ |
1469 | } |
1470 | else | |
617daa0e CV |
1471 | error |
1472 | ("sh_register_convert_to_virtual called with non DR register number"); | |
283150cd EZ |
1473 | } |
1474 | ||
1475 | static void | |
1476 | sh_sh4_register_convert_to_raw (struct type *type, int regnum, | |
d8124050 | 1477 | const void *from, void *to) |
283150cd | 1478 | { |
617daa0e | 1479 | if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM) |
283150cd | 1480 | { |
48db5a3c | 1481 | DOUBLEST val = extract_typed_floating (from, type); |
617daa0e CV |
1482 | floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword, |
1483 | &val, to); | |
283150cd EZ |
1484 | } |
1485 | else | |
617daa0e | 1486 | error ("sh_register_convert_to_raw called with non DR register number"); |
283150cd EZ |
1487 | } |
1488 | ||
1c0159e0 CV |
1489 | /* For vectors of 4 floating point registers. */ |
1490 | static int | |
1491 | fv_reg_base_num (int fv_regnum) | |
1492 | { | |
1493 | int fp_regnum; | |
1494 | ||
617daa0e | 1495 | fp_regnum = FP0_REGNUM + (fv_regnum - FV0_REGNUM) * 4; |
1c0159e0 CV |
1496 | return fp_regnum; |
1497 | } | |
1498 | ||
1499 | /* For double precision floating point registers, i.e 2 fp regs.*/ | |
1500 | static int | |
1501 | dr_reg_base_num (int dr_regnum) | |
1502 | { | |
1503 | int fp_regnum; | |
1504 | ||
617daa0e | 1505 | fp_regnum = FP0_REGNUM + (dr_regnum - DR0_REGNUM) * 2; |
1c0159e0 CV |
1506 | return fp_regnum; |
1507 | } | |
1508 | ||
a78f21af | 1509 | static void |
d8124050 AC |
1510 | sh_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, |
1511 | int reg_nr, void *buffer) | |
53116e27 EZ |
1512 | { |
1513 | int base_regnum, portion; | |
d9d9c31f | 1514 | char temp_buffer[MAX_REGISTER_SIZE]; |
53116e27 | 1515 | |
617daa0e | 1516 | if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM) |
7bd872fe EZ |
1517 | { |
1518 | base_regnum = dr_reg_base_num (reg_nr); | |
1519 | ||
617daa0e | 1520 | /* Build the value in the provided buffer. */ |
7bd872fe EZ |
1521 | /* Read the real regs for which this one is an alias. */ |
1522 | for (portion = 0; portion < 2; portion++) | |
617daa0e | 1523 | regcache_raw_read (regcache, base_regnum + portion, |
0818c12a | 1524 | (temp_buffer |
617daa0e CV |
1525 | + register_size (gdbarch, |
1526 | base_regnum) * portion)); | |
7bd872fe EZ |
1527 | /* We must pay attention to the endiannes. */ |
1528 | sh_sh4_register_convert_to_virtual (reg_nr, | |
617daa0e CV |
1529 | gdbarch_register_type (gdbarch, |
1530 | reg_nr), | |
7bd872fe EZ |
1531 | temp_buffer, buffer); |
1532 | } | |
617daa0e | 1533 | else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM) |
53116e27 | 1534 | { |
7bd872fe EZ |
1535 | base_regnum = fv_reg_base_num (reg_nr); |
1536 | ||
1537 | /* Read the real regs for which this one is an alias. */ | |
1538 | for (portion = 0; portion < 4; portion++) | |
617daa0e | 1539 | regcache_raw_read (regcache, base_regnum + portion, |
d8124050 | 1540 | ((char *) buffer |
617daa0e CV |
1541 | + register_size (gdbarch, |
1542 | base_regnum) * portion)); | |
53116e27 EZ |
1543 | } |
1544 | } | |
1545 | ||
a78f21af | 1546 | static void |
d8124050 AC |
1547 | sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, |
1548 | int reg_nr, const void *buffer) | |
53116e27 EZ |
1549 | { |
1550 | int base_regnum, portion; | |
d9d9c31f | 1551 | char temp_buffer[MAX_REGISTER_SIZE]; |
53116e27 | 1552 | |
617daa0e | 1553 | if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM) |
53116e27 EZ |
1554 | { |
1555 | base_regnum = dr_reg_base_num (reg_nr); | |
1556 | ||
7bd872fe | 1557 | /* We must pay attention to the endiannes. */ |
617daa0e CV |
1558 | sh_sh4_register_convert_to_raw (gdbarch_register_type (gdbarch, reg_nr), |
1559 | reg_nr, buffer, temp_buffer); | |
7bd872fe | 1560 | |
53116e27 EZ |
1561 | /* Write the real regs for which this one is an alias. */ |
1562 | for (portion = 0; portion < 2; portion++) | |
617daa0e | 1563 | regcache_raw_write (regcache, base_regnum + portion, |
0818c12a | 1564 | (temp_buffer |
617daa0e CV |
1565 | + register_size (gdbarch, |
1566 | base_regnum) * portion)); | |
53116e27 | 1567 | } |
617daa0e | 1568 | else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM) |
53116e27 EZ |
1569 | { |
1570 | base_regnum = fv_reg_base_num (reg_nr); | |
1571 | ||
1572 | /* Write the real regs for which this one is an alias. */ | |
1573 | for (portion = 0; portion < 4; portion++) | |
d8124050 AC |
1574 | regcache_raw_write (regcache, base_regnum + portion, |
1575 | ((char *) buffer | |
617daa0e CV |
1576 | + register_size (gdbarch, |
1577 | base_regnum) * portion)); | |
53116e27 EZ |
1578 | } |
1579 | } | |
1580 | ||
3bbfbb92 | 1581 | /* Floating point vector of 4 float registers. */ |
53116e27 | 1582 | static void |
48db5a3c CV |
1583 | do_fv_register_info (struct gdbarch *gdbarch, struct ui_file *file, |
1584 | int fv_regnum) | |
53116e27 EZ |
1585 | { |
1586 | int first_fp_reg_num = fv_reg_base_num (fv_regnum); | |
617daa0e CV |
1587 | fprintf_filtered (file, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n", |
1588 | fv_regnum - FV0_REGNUM, | |
1589 | (int) read_register (first_fp_reg_num), | |
1590 | (int) read_register (first_fp_reg_num + 1), | |
1591 | (int) read_register (first_fp_reg_num + 2), | |
1592 | (int) read_register (first_fp_reg_num + 3)); | |
53116e27 EZ |
1593 | } |
1594 | ||
3bbfbb92 | 1595 | /* Double precision registers. */ |
53116e27 | 1596 | static void |
48db5a3c CV |
1597 | do_dr_register_info (struct gdbarch *gdbarch, struct ui_file *file, |
1598 | int dr_regnum) | |
53116e27 EZ |
1599 | { |
1600 | int first_fp_reg_num = dr_reg_base_num (dr_regnum); | |
1601 | ||
617daa0e CV |
1602 | fprintf_filtered (file, "dr%d\t0x%08x%08x\n", |
1603 | dr_regnum - DR0_REGNUM, | |
53116e27 EZ |
1604 | (int) read_register (first_fp_reg_num), |
1605 | (int) read_register (first_fp_reg_num + 1)); | |
1606 | } | |
1607 | ||
1608 | static void | |
48db5a3c CV |
1609 | sh_print_pseudo_register (struct gdbarch *gdbarch, struct ui_file *file, |
1610 | int regnum) | |
53116e27 EZ |
1611 | { |
1612 | if (regnum < NUM_REGS || regnum >= NUM_REGS + NUM_PSEUDO_REGS) | |
8e65ff28 AC |
1613 | internal_error (__FILE__, __LINE__, |
1614 | "Invalid pseudo register number %d\n", regnum); | |
617daa0e | 1615 | else if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM) |
48db5a3c | 1616 | do_dr_register_info (gdbarch, file, regnum); |
617daa0e | 1617 | else if (regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM) |
48db5a3c | 1618 | do_fv_register_info (gdbarch, file, regnum); |
53116e27 EZ |
1619 | } |
1620 | ||
53116e27 | 1621 | static void |
48db5a3c | 1622 | sh_do_fp_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum) |
53116e27 EZ |
1623 | { /* do values for FP (float) regs */ |
1624 | char *raw_buffer; | |
617daa0e | 1625 | double flt; /* double extracted from raw hex data */ |
53116e27 EZ |
1626 | int inv; |
1627 | int j; | |
1628 | ||
1629 | /* Allocate space for the float. */ | |
48db5a3c | 1630 | raw_buffer = (char *) alloca (register_size (gdbarch, FP0_REGNUM)); |
53116e27 EZ |
1631 | |
1632 | /* Get the data in raw format. */ | |
48db5a3c | 1633 | if (!frame_register_read (get_selected_frame (), regnum, raw_buffer)) |
53116e27 EZ |
1634 | error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum)); |
1635 | ||
617daa0e | 1636 | /* Get the register as a number */ |
53116e27 EZ |
1637 | flt = unpack_double (builtin_type_float, raw_buffer, &inv); |
1638 | ||
1639 | /* Print the name and some spaces. */ | |
48db5a3c CV |
1640 | fputs_filtered (REGISTER_NAME (regnum), file); |
1641 | print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file); | |
53116e27 EZ |
1642 | |
1643 | /* Print the value. */ | |
93d56215 | 1644 | if (inv) |
48db5a3c | 1645 | fprintf_filtered (file, "<invalid float>"); |
93d56215 | 1646 | else |
48db5a3c | 1647 | fprintf_filtered (file, "%-10.9g", flt); |
53116e27 EZ |
1648 | |
1649 | /* Print the fp register as hex. */ | |
48db5a3c CV |
1650 | fprintf_filtered (file, "\t(raw 0x"); |
1651 | for (j = 0; j < register_size (gdbarch, regnum); j++) | |
53116e27 | 1652 | { |
221c12ff AC |
1653 | int idx = (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG |
1654 | ? j | |
1655 | : register_size (gdbarch, regnum) - 1 - j); | |
48db5a3c | 1656 | fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[idx]); |
53116e27 | 1657 | } |
48db5a3c CV |
1658 | fprintf_filtered (file, ")"); |
1659 | fprintf_filtered (file, "\n"); | |
53116e27 EZ |
1660 | } |
1661 | ||
1662 | static void | |
48db5a3c | 1663 | sh_do_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum) |
53116e27 | 1664 | { |
123a958e | 1665 | char raw_buffer[MAX_REGISTER_SIZE]; |
53116e27 | 1666 | |
48db5a3c CV |
1667 | fputs_filtered (REGISTER_NAME (regnum), file); |
1668 | print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file); | |
53116e27 EZ |
1669 | |
1670 | /* Get the data in raw format. */ | |
48db5a3c CV |
1671 | if (!frame_register_read (get_selected_frame (), regnum, raw_buffer)) |
1672 | fprintf_filtered (file, "*value not available*\n"); | |
617daa0e | 1673 | |
48db5a3c CV |
1674 | val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0, |
1675 | file, 'x', 1, 0, Val_pretty_default); | |
1676 | fprintf_filtered (file, "\t"); | |
1677 | val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0, | |
1678 | file, 0, 1, 0, Val_pretty_default); | |
1679 | fprintf_filtered (file, "\n"); | |
53116e27 EZ |
1680 | } |
1681 | ||
1682 | static void | |
48db5a3c | 1683 | sh_print_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum) |
53116e27 EZ |
1684 | { |
1685 | if (regnum < 0 || regnum >= NUM_REGS + NUM_PSEUDO_REGS) | |
8e65ff28 AC |
1686 | internal_error (__FILE__, __LINE__, |
1687 | "Invalid register number %d\n", regnum); | |
53116e27 | 1688 | |
e30839fe | 1689 | else if (regnum >= 0 && regnum < NUM_REGS) |
53116e27 | 1690 | { |
617daa0e CV |
1691 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == |
1692 | TYPE_CODE_FLT) | |
48db5a3c | 1693 | sh_do_fp_register (gdbarch, file, regnum); /* FP regs */ |
53116e27 | 1694 | else |
48db5a3c | 1695 | sh_do_register (gdbarch, file, regnum); /* All other regs */ |
53116e27 EZ |
1696 | } |
1697 | ||
1698 | else if (regnum < NUM_REGS + NUM_PSEUDO_REGS) | |
48db5a3c | 1699 | { |
55ff77ac | 1700 | sh_print_pseudo_register (gdbarch, file, regnum); |
48db5a3c | 1701 | } |
53116e27 EZ |
1702 | } |
1703 | ||
a78f21af | 1704 | static void |
48db5a3c CV |
1705 | sh_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
1706 | struct frame_info *frame, int regnum, int fpregs) | |
53116e27 EZ |
1707 | { |
1708 | if (regnum != -1) /* do one specified register */ | |
1709 | { | |
1710 | if (*(REGISTER_NAME (regnum)) == '\0') | |
1711 | error ("Not a valid register for the current processor type"); | |
1712 | ||
48db5a3c | 1713 | sh_print_register (gdbarch, file, regnum); |
53116e27 EZ |
1714 | } |
1715 | else | |
1716 | /* do all (or most) registers */ | |
1717 | { | |
1718 | regnum = 0; | |
1719 | while (regnum < NUM_REGS) | |
1720 | { | |
1721 | /* If the register name is empty, it is undefined for this | |
1722 | processor, so don't display anything. */ | |
1723 | if (REGISTER_NAME (regnum) == NULL | |
1724 | || *(REGISTER_NAME (regnum)) == '\0') | |
617daa0e | 1725 | { |
53116e27 EZ |
1726 | regnum++; |
1727 | continue; | |
1728 | } | |
1729 | ||
617daa0e CV |
1730 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == |
1731 | TYPE_CODE_FLT) | |
53116e27 EZ |
1732 | { |
1733 | if (fpregs) | |
1734 | { | |
1735 | /* true for "INFO ALL-REGISTERS" command */ | |
48db5a3c | 1736 | sh_do_fp_register (gdbarch, file, regnum); /* FP regs */ |
617daa0e | 1737 | regnum++; |
53116e27 EZ |
1738 | } |
1739 | else | |
f2ea0907 | 1740 | regnum += (FP_LAST_REGNUM - FP0_REGNUM); /* skip FP regs */ |
53116e27 EZ |
1741 | } |
1742 | else | |
1743 | { | |
48db5a3c | 1744 | sh_do_register (gdbarch, file, regnum); /* All other regs */ |
53116e27 EZ |
1745 | regnum++; |
1746 | } | |
1747 | } | |
1748 | ||
1749 | if (fpregs) | |
1750 | while (regnum < NUM_REGS + NUM_PSEUDO_REGS) | |
1751 | { | |
55ff77ac | 1752 | sh_print_pseudo_register (gdbarch, file, regnum); |
53116e27 EZ |
1753 | regnum++; |
1754 | } | |
1755 | } | |
1756 | } | |
1757 | ||
1a8629c7 MS |
1758 | #ifdef SVR4_SHARED_LIBS |
1759 | ||
1760 | /* Fetch (and possibly build) an appropriate link_map_offsets structure | |
1761 | for native i386 linux targets using the struct offsets defined in | |
1762 | link.h (but without actual reference to that file). | |
1763 | ||
1764 | This makes it possible to access i386-linux shared libraries from | |
1765 | a gdb that was not built on an i386-linux host (for cross debugging). | |
1766 | */ | |
1767 | ||
1768 | struct link_map_offsets * | |
1769 | sh_linux_svr4_fetch_link_map_offsets (void) | |
1770 | { | |
1771 | static struct link_map_offsets lmo; | |
1772 | static struct link_map_offsets *lmp = 0; | |
1773 | ||
1774 | if (lmp == 0) | |
1775 | { | |
1776 | lmp = &lmo; | |
1777 | ||
1778 | lmo.r_debug_size = 8; /* 20 not actual size but all we need */ | |
1779 | ||
1780 | lmo.r_map_offset = 4; | |
617daa0e | 1781 | lmo.r_map_size = 4; |
1a8629c7 MS |
1782 | |
1783 | lmo.link_map_size = 20; /* 552 not actual size but all we need */ | |
1784 | ||
1785 | lmo.l_addr_offset = 0; | |
617daa0e | 1786 | lmo.l_addr_size = 4; |
1a8629c7 MS |
1787 | |
1788 | lmo.l_name_offset = 4; | |
617daa0e | 1789 | lmo.l_name_size = 4; |
1a8629c7 MS |
1790 | |
1791 | lmo.l_next_offset = 12; | |
617daa0e | 1792 | lmo.l_next_size = 4; |
1a8629c7 MS |
1793 | |
1794 | lmo.l_prev_offset = 16; | |
617daa0e | 1795 | lmo.l_prev_size = 4; |
1a8629c7 MS |
1796 | } |
1797 | ||
617daa0e | 1798 | return lmp; |
1a8629c7 MS |
1799 | } |
1800 | #endif /* SVR4_SHARED_LIBS */ | |
1801 | ||
2f14585c JR |
1802 | static int |
1803 | sh_dsp_register_sim_regno (int nr) | |
1804 | { | |
1805 | if (legacy_register_sim_regno (nr) < 0) | |
1806 | return legacy_register_sim_regno (nr); | |
f2ea0907 CV |
1807 | if (nr >= DSR_REGNUM && nr <= Y1_REGNUM) |
1808 | return nr - DSR_REGNUM + SIM_SH_DSR_REGNUM; | |
1809 | if (nr == MOD_REGNUM) | |
2f14585c | 1810 | return SIM_SH_MOD_REGNUM; |
f2ea0907 | 1811 | if (nr == RS_REGNUM) |
2f14585c | 1812 | return SIM_SH_RS_REGNUM; |
f2ea0907 | 1813 | if (nr == RE_REGNUM) |
2f14585c | 1814 | return SIM_SH_RE_REGNUM; |
f2ea0907 CV |
1815 | if (nr >= R0_BANK_REGNUM && nr <= R7_BANK_REGNUM) |
1816 | return nr - R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM; | |
2f14585c JR |
1817 | return nr; |
1818 | } | |
1c0159e0 CV |
1819 | |
1820 | static struct sh_frame_cache * | |
1821 | sh_alloc_frame_cache (void) | |
1822 | { | |
1823 | struct sh_frame_cache *cache; | |
1824 | int i; | |
1825 | ||
1826 | cache = FRAME_OBSTACK_ZALLOC (struct sh_frame_cache); | |
1827 | ||
1828 | /* Base address. */ | |
1829 | cache->base = 0; | |
1830 | cache->saved_sp = 0; | |
1831 | cache->sp_offset = 0; | |
1832 | cache->pc = 0; | |
1833 | ||
1834 | /* Frameless until proven otherwise. */ | |
1835 | cache->uses_fp = 0; | |
617daa0e | 1836 | |
1c0159e0 CV |
1837 | /* Saved registers. We initialize these to -1 since zero is a valid |
1838 | offset (that's where fp is supposed to be stored). */ | |
1839 | for (i = 0; i < SH_NUM_REGS; i++) | |
1840 | { | |
1841 | cache->saved_regs[i] = -1; | |
1842 | } | |
617daa0e | 1843 | |
1c0159e0 | 1844 | return cache; |
617daa0e | 1845 | } |
1c0159e0 CV |
1846 | |
1847 | static struct sh_frame_cache * | |
1848 | sh_frame_cache (struct frame_info *next_frame, void **this_cache) | |
1849 | { | |
1850 | struct sh_frame_cache *cache; | |
1851 | CORE_ADDR current_pc; | |
1852 | int i; | |
1853 | ||
1854 | if (*this_cache) | |
1855 | return *this_cache; | |
1856 | ||
1857 | cache = sh_alloc_frame_cache (); | |
1858 | *this_cache = cache; | |
1859 | ||
1860 | /* In principle, for normal frames, fp holds the frame pointer, | |
1861 | which holds the base address for the current stack frame. | |
1862 | However, for functions that don't need it, the frame pointer is | |
1863 | optional. For these "frameless" functions the frame pointer is | |
1864 | actually the frame pointer of the calling frame. */ | |
1865 | cache->base = frame_unwind_register_unsigned (next_frame, FP_REGNUM); | |
1866 | if (cache->base == 0) | |
1867 | return cache; | |
1868 | ||
1869 | cache->pc = frame_func_unwind (next_frame); | |
1870 | current_pc = frame_pc_unwind (next_frame); | |
1871 | if (cache->pc != 0) | |
1872 | sh_analyze_prologue (cache->pc, current_pc, cache); | |
617daa0e | 1873 | |
1c0159e0 CV |
1874 | if (!cache->uses_fp) |
1875 | { | |
1876 | /* We didn't find a valid frame, which means that CACHE->base | |
1877 | currently holds the frame pointer for our calling frame. If | |
1878 | we're at the start of a function, or somewhere half-way its | |
1879 | prologue, the function's frame probably hasn't been fully | |
1880 | setup yet. Try to reconstruct the base address for the stack | |
1881 | frame by looking at the stack pointer. For truly "frameless" | |
1882 | functions this might work too. */ | |
1883 | cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM); | |
1884 | } | |
1885 | ||
1886 | /* Now that we have the base address for the stack frame we can | |
1887 | calculate the value of sp in the calling frame. */ | |
1888 | cache->saved_sp = cache->base + cache->sp_offset; | |
1889 | ||
1890 | /* Adjust all the saved registers such that they contain addresses | |
1891 | instead of offsets. */ | |
1892 | for (i = 0; i < SH_NUM_REGS; i++) | |
1893 | if (cache->saved_regs[i] != -1) | |
1894 | cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i] - 4; | |
1895 | ||
1896 | return cache; | |
1897 | } | |
1898 | ||
1899 | static void | |
1900 | sh_frame_prev_register (struct frame_info *next_frame, void **this_cache, | |
1901 | int regnum, int *optimizedp, | |
1902 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
1903 | int *realnump, void *valuep) | |
1904 | { | |
1905 | struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache); | |
1906 | ||
1907 | gdb_assert (regnum >= 0); | |
1908 | ||
1909 | if (regnum == SP_REGNUM && cache->saved_sp) | |
1910 | { | |
1911 | *optimizedp = 0; | |
1912 | *lvalp = not_lval; | |
1913 | *addrp = 0; | |
1914 | *realnump = -1; | |
1915 | if (valuep) | |
617daa0e CV |
1916 | { |
1917 | /* Store the value. */ | |
1918 | store_unsigned_integer (valuep, 4, cache->saved_sp); | |
1919 | } | |
1c0159e0 CV |
1920 | return; |
1921 | } | |
1922 | ||
1923 | /* The PC of the previous frame is stored in the PR register of | |
1924 | the current frame. Frob regnum so that we pull the value from | |
1925 | the correct place. */ | |
1926 | if (regnum == PC_REGNUM) | |
1927 | regnum = PR_REGNUM; | |
1928 | ||
1929 | if (regnum < SH_NUM_REGS && cache->saved_regs[regnum] != -1) | |
1930 | { | |
1931 | *optimizedp = 0; | |
1932 | *lvalp = lval_memory; | |
1933 | *addrp = cache->saved_regs[regnum]; | |
1934 | *realnump = -1; | |
1935 | if (valuep) | |
617daa0e CV |
1936 | { |
1937 | /* Read the value in from memory. */ | |
1938 | read_memory (*addrp, valuep, | |
1939 | register_size (current_gdbarch, regnum)); | |
1940 | } | |
1c0159e0 CV |
1941 | return; |
1942 | } | |
1943 | ||
1944 | frame_register_unwind (next_frame, regnum, | |
617daa0e | 1945 | optimizedp, lvalp, addrp, realnump, valuep); |
1c0159e0 CV |
1946 | } |
1947 | ||
1948 | static void | |
1949 | sh_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
617daa0e CV |
1950 | struct frame_id *this_id) |
1951 | { | |
1c0159e0 CV |
1952 | struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache); |
1953 | ||
1954 | /* This marks the outermost frame. */ | |
1955 | if (cache->base == 0) | |
1956 | return; | |
1957 | ||
1958 | *this_id = frame_id_build (cache->saved_sp, cache->pc); | |
617daa0e | 1959 | } |
1c0159e0 | 1960 | |
617daa0e | 1961 | static const struct frame_unwind sh_frame_unwind = { |
1c0159e0 CV |
1962 | NORMAL_FRAME, |
1963 | sh_frame_this_id, | |
1964 | sh_frame_prev_register | |
1965 | }; | |
1966 | ||
1967 | static const struct frame_unwind * | |
1968 | sh_frame_sniffer (struct frame_info *next_frame) | |
1969 | { | |
1970 | return &sh_frame_unwind; | |
1971 | } | |
1972 | ||
1973 | static CORE_ADDR | |
1974 | sh_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1975 | { | |
1976 | return frame_unwind_register_unsigned (next_frame, SP_REGNUM); | |
1977 | } | |
1978 | ||
1979 | static CORE_ADDR | |
1980 | sh_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1981 | { | |
1982 | return frame_unwind_register_unsigned (next_frame, PC_REGNUM); | |
1983 | } | |
1984 | ||
1985 | static struct frame_id | |
1986 | sh_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1987 | { | |
1988 | return frame_id_build (sh_unwind_sp (gdbarch, next_frame), | |
1989 | frame_pc_unwind (next_frame)); | |
1990 | } | |
1991 | ||
1992 | static CORE_ADDR | |
1993 | sh_frame_base_address (struct frame_info *next_frame, void **this_cache) | |
617daa0e | 1994 | { |
1c0159e0 | 1995 | struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache); |
617daa0e | 1996 | |
1c0159e0 CV |
1997 | return cache->base; |
1998 | } | |
617daa0e CV |
1999 | |
2000 | static const struct frame_base sh_frame_base = { | |
1c0159e0 CV |
2001 | &sh_frame_unwind, |
2002 | sh_frame_base_address, | |
2003 | sh_frame_base_address, | |
2004 | sh_frame_base_address | |
617daa0e | 2005 | }; |
1c0159e0 CV |
2006 | |
2007 | /* The epilogue is defined here as the area at the end of a function, | |
2008 | either on the `ret' instruction itself or after an instruction which | |
2009 | destroys the function's stack frame. */ | |
2010 | static int | |
2011 | sh_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
2012 | { | |
2013 | CORE_ADDR func_addr = 0, func_end = 0; | |
2014 | ||
2015 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
2016 | { | |
2017 | ULONGEST inst; | |
2018 | /* The sh epilogue is max. 14 bytes long. Give another 14 bytes | |
2019 | for a nop and some fixed data (e.g. big offsets) which are | |
617daa0e CV |
2020 | unfortunately also treated as part of the function (which |
2021 | means, they are below func_end. */ | |
1c0159e0 CV |
2022 | CORE_ADDR addr = func_end - 28; |
2023 | if (addr < func_addr + 4) | |
617daa0e | 2024 | addr = func_addr + 4; |
1c0159e0 CV |
2025 | if (pc < addr) |
2026 | return 0; | |
2027 | ||
2028 | /* First search forward until hitting an rts. */ | |
2029 | while (addr < func_end | |
617daa0e | 2030 | && !IS_RTS (read_memory_unsigned_integer (addr, 2))) |
1c0159e0 CV |
2031 | addr += 2; |
2032 | if (addr >= func_end) | |
617daa0e | 2033 | return 0; |
1c0159e0 CV |
2034 | |
2035 | /* At this point we should find a mov.l @r15+,r14 instruction, | |
2036 | either before or after the rts. If not, then the function has | |
617daa0e | 2037 | probably no "normal" epilogue and we bail out here. */ |
1c0159e0 CV |
2038 | inst = read_memory_unsigned_integer (addr - 2, 2); |
2039 | if (IS_RESTORE_FP (read_memory_unsigned_integer (addr - 2, 2))) | |
617daa0e | 2040 | addr -= 2; |
1c0159e0 CV |
2041 | else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr + 2, 2))) |
2042 | return 0; | |
2043 | ||
2044 | /* Step over possible lds.l @r15+,pr. */ | |
2045 | inst = read_memory_unsigned_integer (addr - 2, 2); | |
2046 | if (IS_LDS (inst)) | |
617daa0e | 2047 | { |
1c0159e0 CV |
2048 | addr -= 2; |
2049 | inst = read_memory_unsigned_integer (addr - 2, 2); | |
2050 | } | |
2051 | ||
2052 | /* Step over possible mov r14,r15. */ | |
2053 | if (IS_MOV_FP_SP (inst)) | |
617daa0e | 2054 | { |
1c0159e0 CV |
2055 | addr -= 2; |
2056 | inst = read_memory_unsigned_integer (addr - 2, 2); | |
2057 | } | |
2058 | ||
2059 | /* Now check for FP adjustments, using add #imm,r14 or add rX, r14 | |
2060 | instructions. */ | |
2061 | while (addr > func_addr + 4 | |
617daa0e | 2062 | && (IS_ADD_REG_TO_FP (inst) || IS_ADD_IMM_FP (inst))) |
1c0159e0 CV |
2063 | { |
2064 | addr -= 2; | |
2065 | inst = read_memory_unsigned_integer (addr - 2, 2); | |
2066 | } | |
2067 | ||
2068 | if (pc >= addr) | |
2069 | return 1; | |
2070 | } | |
2071 | return 0; | |
2072 | } | |
2073 | ||
cc17453a EZ |
2074 | static gdbarch_init_ftype sh_gdbarch_init; |
2075 | ||
2076 | static struct gdbarch * | |
fba45db2 | 2077 | sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
cc17453a | 2078 | { |
cc17453a | 2079 | struct gdbarch *gdbarch; |
d658f924 | 2080 | |
55ff77ac CV |
2081 | sh_show_regs = sh_generic_show_regs; |
2082 | switch (info.bfd_arch_info->mach) | |
2083 | { | |
617daa0e CV |
2084 | case bfd_mach_sh2e: |
2085 | sh_show_regs = sh2e_show_regs; | |
2086 | break; | |
2087 | case bfd_mach_sh_dsp: | |
2088 | sh_show_regs = sh_dsp_show_regs; | |
2089 | break; | |
55ff77ac | 2090 | |
617daa0e CV |
2091 | case bfd_mach_sh3: |
2092 | sh_show_regs = sh3_show_regs; | |
2093 | break; | |
55ff77ac | 2094 | |
617daa0e CV |
2095 | case bfd_mach_sh3e: |
2096 | sh_show_regs = sh3e_show_regs; | |
2097 | break; | |
55ff77ac | 2098 | |
617daa0e CV |
2099 | case bfd_mach_sh3_dsp: |
2100 | sh_show_regs = sh3_dsp_show_regs; | |
2101 | break; | |
55ff77ac | 2102 | |
617daa0e CV |
2103 | case bfd_mach_sh4: |
2104 | sh_show_regs = sh4_show_regs; | |
2105 | break; | |
55ff77ac | 2106 | |
617daa0e CV |
2107 | case bfd_mach_sh5: |
2108 | sh_show_regs = sh64_show_regs; | |
2109 | /* SH5 is handled entirely in sh64-tdep.c */ | |
2110 | return sh64_gdbarch_init (info, arches); | |
55ff77ac CV |
2111 | } |
2112 | ||
4be87837 DJ |
2113 | /* If there is already a candidate, use it. */ |
2114 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
2115 | if (arches != NULL) | |
2116 | return arches->gdbarch; | |
cc17453a EZ |
2117 | |
2118 | /* None found, create a new architecture from the information | |
2119 | provided. */ | |
f2ea0907 | 2120 | gdbarch = gdbarch_alloc (&info, NULL); |
cc17453a | 2121 | |
48db5a3c CV |
2122 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); |
2123 | set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
ec920329 | 2124 | set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
48db5a3c CV |
2125 | set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); |
2126 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
2127 | set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
2128 | set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
a38d2a54 | 2129 | set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
48db5a3c | 2130 | |
f2ea0907 | 2131 | set_gdbarch_num_regs (gdbarch, SH_NUM_REGS); |
a38d2a54 | 2132 | set_gdbarch_sp_regnum (gdbarch, 15); |
a38d2a54 | 2133 | set_gdbarch_pc_regnum (gdbarch, 16); |
48db5a3c CV |
2134 | set_gdbarch_fp0_regnum (gdbarch, -1); |
2135 | set_gdbarch_num_pseudo_regs (gdbarch, 0); | |
2136 | ||
1c0159e0 CV |
2137 | set_gdbarch_register_type (gdbarch, sh_default_register_type); |
2138 | ||
2139 | set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info); | |
2140 | ||
eaf90c5d | 2141 | set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc); |
3bbfbb92 | 2142 | set_gdbarch_use_struct_convention (gdbarch, sh_use_struct_convention); |
48db5a3c | 2143 | |
2bf0cb65 | 2144 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_sh); |
2f14585c | 2145 | set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno); |
48db5a3c CV |
2146 | |
2147 | set_gdbarch_write_pc (gdbarch, generic_target_write_pc); | |
2148 | ||
1c0159e0 CV |
2149 | set_gdbarch_store_return_value (gdbarch, sh_default_store_return_value); |
2150 | set_gdbarch_extract_return_value (gdbarch, sh_default_extract_return_value); | |
2151 | set_gdbarch_extract_struct_value_address (gdbarch, | |
2152 | sh_extract_struct_value_address); | |
2153 | ||
48db5a3c CV |
2154 | set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue); |
2155 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
2156 | set_gdbarch_decr_pc_after_break (gdbarch, 0); | |
2157 | set_gdbarch_function_start_offset (gdbarch, 0); | |
2158 | ||
1c0159e0 CV |
2159 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu); |
2160 | ||
48db5a3c | 2161 | set_gdbarch_frame_args_skip (gdbarch, 0); |
1c0159e0 CV |
2162 | set_gdbarch_frameless_function_invocation (gdbarch, |
2163 | frameless_look_for_prologue); | |
48db5a3c CV |
2164 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); |
2165 | ||
19f59343 | 2166 | set_gdbarch_frame_align (gdbarch, sh_frame_align); |
1c0159e0 CV |
2167 | set_gdbarch_unwind_sp (gdbarch, sh_unwind_sp); |
2168 | set_gdbarch_unwind_pc (gdbarch, sh_unwind_pc); | |
2169 | set_gdbarch_unwind_dummy_id (gdbarch, sh_unwind_dummy_id); | |
2170 | frame_base_set_default (gdbarch, &sh_frame_base); | |
2171 | ||
617daa0e | 2172 | set_gdbarch_in_function_epilogue_p (gdbarch, sh_in_function_epilogue_p); |
cc17453a EZ |
2173 | |
2174 | switch (info.bfd_arch_info->mach) | |
8db62801 | 2175 | { |
cc17453a | 2176 | case bfd_mach_sh: |
48db5a3c | 2177 | set_gdbarch_register_name (gdbarch, sh_sh_register_name); |
cc17453a | 2178 | break; |
1c0159e0 | 2179 | |
cc17453a | 2180 | case bfd_mach_sh2: |
48db5a3c | 2181 | set_gdbarch_register_name (gdbarch, sh_sh_register_name); |
617daa0e | 2182 | break; |
1c0159e0 | 2183 | |
2d188dd3 | 2184 | case bfd_mach_sh2e: |
48db5a3c CV |
2185 | /* doubles on sh2e and sh3e are actually 4 byte. */ |
2186 | set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
2187 | ||
2188 | set_gdbarch_register_name (gdbarch, sh_sh2e_register_name); | |
48db5a3c | 2189 | set_gdbarch_register_type (gdbarch, sh_sh3e_register_type); |
2d188dd3 | 2190 | set_gdbarch_fp0_regnum (gdbarch, 25); |
48db5a3c | 2191 | set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value); |
617daa0e CV |
2192 | set_gdbarch_extract_return_value (gdbarch, |
2193 | sh3e_sh4_extract_return_value); | |
6df2bf50 | 2194 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); |
2d188dd3 | 2195 | break; |
1c0159e0 | 2196 | |
cc17453a | 2197 | case bfd_mach_sh_dsp: |
48db5a3c | 2198 | set_gdbarch_register_name (gdbarch, sh_sh_dsp_register_name); |
2f14585c | 2199 | set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno); |
cc17453a | 2200 | break; |
1c0159e0 | 2201 | |
cc17453a | 2202 | case bfd_mach_sh3: |
48db5a3c | 2203 | set_gdbarch_register_name (gdbarch, sh_sh3_register_name); |
cc17453a | 2204 | break; |
1c0159e0 | 2205 | |
cc17453a | 2206 | case bfd_mach_sh3e: |
48db5a3c CV |
2207 | /* doubles on sh2e and sh3e are actually 4 byte. */ |
2208 | set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
2209 | ||
2210 | set_gdbarch_register_name (gdbarch, sh_sh3e_register_name); | |
48db5a3c | 2211 | set_gdbarch_register_type (gdbarch, sh_sh3e_register_type); |
cc17453a | 2212 | set_gdbarch_fp0_regnum (gdbarch, 25); |
48db5a3c | 2213 | set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value); |
617daa0e CV |
2214 | set_gdbarch_extract_return_value (gdbarch, |
2215 | sh3e_sh4_extract_return_value); | |
6df2bf50 | 2216 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); |
cc17453a | 2217 | break; |
1c0159e0 | 2218 | |
cc17453a | 2219 | case bfd_mach_sh3_dsp: |
48db5a3c | 2220 | set_gdbarch_register_name (gdbarch, sh_sh3_dsp_register_name); |
48db5a3c | 2221 | set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno); |
cc17453a | 2222 | break; |
1c0159e0 | 2223 | |
cc17453a | 2224 | case bfd_mach_sh4: |
48db5a3c | 2225 | set_gdbarch_register_name (gdbarch, sh_sh4_register_name); |
48db5a3c | 2226 | set_gdbarch_register_type (gdbarch, sh_sh4_register_type); |
cc17453a | 2227 | set_gdbarch_fp0_regnum (gdbarch, 25); |
53116e27 | 2228 | set_gdbarch_num_pseudo_regs (gdbarch, 12); |
d8124050 AC |
2229 | set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read); |
2230 | set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write); | |
48db5a3c | 2231 | set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value); |
617daa0e CV |
2232 | set_gdbarch_extract_return_value (gdbarch, |
2233 | sh3e_sh4_extract_return_value); | |
6df2bf50 | 2234 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); |
cc17453a | 2235 | break; |
1c0159e0 | 2236 | |
cc17453a | 2237 | default: |
48db5a3c | 2238 | set_gdbarch_register_name (gdbarch, sh_generic_register_name); |
cc17453a | 2239 | break; |
8db62801 | 2240 | } |
cc17453a | 2241 | |
4be87837 DJ |
2242 | /* Hook in ABI-specific overrides, if they have been registered. */ |
2243 | gdbarch_init_osabi (info, gdbarch); | |
d658f924 | 2244 | |
1c0159e0 CV |
2245 | frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer); |
2246 | frame_unwind_append_sniffer (gdbarch, sh_frame_sniffer); | |
2247 | ||
cc17453a | 2248 | return gdbarch; |
8db62801 EZ |
2249 | } |
2250 | ||
617daa0e | 2251 | extern initialize_file_ftype _initialize_sh_tdep; /* -Wmissing-prototypes */ |
a78f21af | 2252 | |
c906108c | 2253 | void |
fba45db2 | 2254 | _initialize_sh_tdep (void) |
c906108c SS |
2255 | { |
2256 | struct cmd_list_element *c; | |
617daa0e | 2257 | |
f2ea0907 | 2258 | gdbarch_register (bfd_arch_sh, sh_gdbarch_init, NULL); |
c906108c | 2259 | |
53116e27 | 2260 | add_com ("regs", class_vars, sh_show_regs_command, "Print all registers"); |
c906108c | 2261 | } |