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* solib.c (solib_open): If path is relative, look for it
[deliverable/binutils-gdb.git] / gdb / sh-tdep.c
CommitLineData
c906108c 1/* Target-dependent code for Hitachi Super-H, for GDB.
b4a20239
AC		 2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 2000 Free Software
3 Foundation, Inc.
c906108c 4
c5aa993b 5 This file is part of GDB.
c906108c 6
c5aa993b
JM		 7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
c906108c 11
c5aa993b
JM		 12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
c906108c 16
c5aa993b
JM		 17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
c906108c
SS		 21
22/*
c5aa993b
JM		 23 Contributed by Steve Chamberlain
24 sac@cygnus.com
c906108c
SS		 25 */
26
27#include "defs.h"
28#include "frame.h"
29#include "obstack.h"
30#include "symtab.h"
31#include "symfile.h"
32#include "gdbtypes.h"
33#include "gdbcmd.h"
34#include "gdbcore.h"
35#include "value.h"
36#include "dis-asm.h"
37#include "inferior.h" /* for BEFORE_TEXT_END etc. */
38#include "gdb_string.h"
b4a20239 39#include "arch-utils.h"
fb409745 40#include "floatformat.h"
c906108c 41
1a8629c7
MS		 42#include "solib-svr4.h"
43
cc17453a
EZ		 44#undef XMALLOC
45#define XMALLOC(TYPE) ((TYPE*) xmalloc (sizeof (TYPE)))
46
53116e27
EZ		 47
48/* Frame interpretation related functions. */
cc17453a
EZ		 49static gdbarch_breakpoint_from_pc_ftype sh_breakpoint_from_pc;
50static gdbarch_frame_chain_ftype sh_frame_chain;
51static gdbarch_frame_saved_pc_ftype sh_frame_saved_pc;
52static gdbarch_skip_prologue_ftype sh_skip_prologue;
53116e27 53
cc17453a
EZ		 54static gdbarch_frame_init_saved_regs_ftype sh_nofp_frame_init_saved_regs;
55static gdbarch_frame_init_saved_regs_ftype sh_fp_frame_init_saved_regs;
53116e27
EZ		 56static gdbarch_init_extra_frame_info_ftype sh_init_extra_frame_info;
57static gdbarch_pop_frame_ftype sh_pop_frame;
58static gdbarch_saved_pc_after_call_ftype sh_saved_pc_after_call;
59static gdbarch_frame_args_address_ftype sh_frame_args_address;
60static gdbarch_frame_locals_address_ftype sh_frame_locals_address;
61
62/* Function call related functions. */
cc17453a
EZ		 63static gdbarch_extract_return_value_ftype sh_extract_return_value;
64static gdbarch_extract_struct_value_address_ftype sh_extract_struct_value_address;
65static gdbarch_use_struct_convention_ftype sh_use_struct_convention;
cc17453a
EZ		 66static gdbarch_store_struct_return_ftype sh_store_struct_return;
67static gdbarch_push_arguments_ftype sh_push_arguments;
68static gdbarch_push_return_address_ftype sh_push_return_address;
53116e27
EZ		 69static gdbarch_coerce_float_to_double_ftype sh_coerce_float_to_double;
70static gdbarch_store_return_value_ftype sh_default_store_return_value;
71static gdbarch_store_return_value_ftype sh3e_sh4_store_return_value;
cc17453a
EZ		 72
73static gdbarch_register_name_ftype sh_generic_register_name;
74static gdbarch_register_name_ftype sh_sh_register_name;
75static gdbarch_register_name_ftype sh_sh3_register_name;
76static gdbarch_register_name_ftype sh_sh3e_register_name;
77static gdbarch_register_name_ftype sh_sh_dsp_register_name;
78static gdbarch_register_name_ftype sh_sh3_dsp_register_name;
79
53116e27
EZ		 80/* Registers display related functions */
81static gdbarch_register_raw_size_ftype sh_default_register_raw_size;
82static gdbarch_register_raw_size_ftype sh_sh4_register_raw_size;
cc17453a 83
cc17453a 84static gdbarch_register_virtual_size_ftype sh_register_virtual_size;
53116e27
EZ		 85
86static gdbarch_register_byte_ftype sh_default_register_byte;
87static gdbarch_register_byte_ftype sh_sh4_register_byte;
88
cc17453a 89static gdbarch_register_virtual_type_ftype sh_sh3e_register_virtual_type;
53116e27 90static gdbarch_register_virtual_type_ftype sh_sh4_register_virtual_type;
cc17453a
EZ		 91static gdbarch_register_virtual_type_ftype sh_default_register_virtual_type;
92
53116e27
EZ		 93static void sh_generic_show_regs (void);
94static void sh3_show_regs (void);
95static void sh3e_show_regs (void);
96static void sh3_dsp_show_regs (void);
97static void sh_dsp_show_regs (void);
98static void sh4_show_regs (void);
99static void sh_show_regs_command (char *, int);
100
101static struct type *sh_sh4_build_float_register_type (int high);
102
103static gdbarch_fetch_pseudo_register_ftype sh_fetch_pseudo_register;
104static gdbarch_store_pseudo_register_ftype sh_store_pseudo_register;
105static int fv_reg_base_num (int);
106static int dr_reg_base_num (int);
c5f7d19c 107static gdbarch_do_registers_info_ftype sh_do_registers_info;
53116e27
EZ		 108static void do_fv_register_info (int fv_regnum);
109static void do_dr_register_info (int dr_regnum);
110static void sh_do_pseudo_register (int regnum);
111static void sh_do_fp_register (int regnum);
112static void sh_do_register (int regnum);
113static void sh_print_register (int regnum);
114
115void (*sh_show_regs) (void);
e6c42fda 116int (*print_sh_insn) (bfd_vma, disassemble_info*);
cc17453a 117
cc17453a
EZ		 118/* Define other aspects of the stack frame.
119 we keep a copy of the worked out return pc lying around, since it
120 is a useful bit of info */
121
122struct frame_extra_info
123{
124 CORE_ADDR return_pc;
125 int leaf_function;
126 int f_offset;
63978407 127};
c906108c 128
cc17453a 129#if 0
091be84d
CF		 130#ifdef _WIN32_WCE
131char **sh_register_names = sh3_reg_names;
132#else
c906108c 133char **sh_register_names = sh_generic_reg_names;
091be84d 134#endif
cc17453a 135#endif
c906108c 136
cc17453a
EZ		 137static char *
138sh_generic_register_name (int reg_nr)
c5aa993b 139{
cc17453a 140 static char *register_names[] =
c5aa993b 141 {
cc17453a
EZ		 142 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
143 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
144 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
145 "fpul", "fpscr",
146 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
147 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
148 "ssr", "spc",
149 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
150 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
151 };
152 if (reg_nr < 0)
153 return NULL;
154 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
155 return NULL;
156 return register_names[reg_nr];
157}
158
159static char *
160sh_sh_register_name (int reg_nr)
161{
162 static char *register_names[] =
63978407 163 {
cc17453a
EZ		 164 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
165 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
166 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
167 "", "",
168 "", "", "", "", "", "", "", "",
169 "", "", "", "", "", "", "", "",
170 "", "",
171 "", "", "", "", "", "", "", "",
172 "", "", "", "", "", "", "", "",
173 };
174 if (reg_nr < 0)
175 return NULL;
176 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
177 return NULL;
178 return register_names[reg_nr];
179}
180
181static char *
182sh_sh3_register_name (int reg_nr)
183{
184 static char *register_names[] =
c5aa993b 185 {
cc17453a
EZ		 186 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
187 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
188 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
189 "", "",
190 "", "", "", "", "", "", "", "",
191 "", "", "", "", "", "", "", "",
192 "ssr", "spc",
193 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
194 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
195 };
196 if (reg_nr < 0)
197 return NULL;
198 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
199 return NULL;
200 return register_names[reg_nr];
201}
202
203static char *
204sh_sh3e_register_name (int reg_nr)
205{
206 static char *register_names[] =
63978407 207 {
cc17453a
EZ		 208 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
209 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
210 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
211 "fpul", "fpscr",
212 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
213 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
214 "ssr", "spc",
215 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
216 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
217 };
218 if (reg_nr < 0)
219 return NULL;
220 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
221 return NULL;
222 return register_names[reg_nr];
223}
224
225static char *
226sh_sh_dsp_register_name (int reg_nr)
227{
228 static char *register_names[] =
c5aa993b 229 {
cc17453a
EZ		 230 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
231 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
232 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
233 "", "dsr",
234 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
235 "y0", "y1", "", "", "", "", "", "mod",
236 "", "",
237 "rs", "re", "", "", "", "", "", "",
238 "", "", "", "", "", "", "", "",
239 };
240 if (reg_nr < 0)
241 return NULL;
242 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
243 return NULL;
244 return register_names[reg_nr];
245}
246
247static char *
248sh_sh3_dsp_register_name (int reg_nr)
249{
250 static char *register_names[] =
c5aa993b 251 {
cc17453a
EZ		 252 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
253 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
254 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
255 "", "dsr",
256 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
257 "y0", "y1", "", "", "", "", "", "mod",
258 "ssr", "spc",
259 "rs", "re", "", "", "", "", "", "",
260 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b"
261 "", "", "", "", "", "", "", "",
262 };
263 if (reg_nr < 0)
264 return NULL;
265 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
266 return NULL;
267 return register_names[reg_nr];
268}
269
53116e27
EZ		 270static char *
271sh_sh4_register_name (int reg_nr)
272{
273 static char *register_names[] =
274 {
a38d2a54 275 /* general registers 0-15 */
53116e27
EZ		 276 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
277 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
a38d2a54 278 /* 16 - 22 */
53116e27 279 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
a38d2a54 280 /* 23, 24 */
53116e27 281 "fpul", "fpscr",
a38d2a54 282 /* floating point registers 25 - 40 */
53116e27
EZ		 283 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
284 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
a38d2a54 285 /* 41, 42 */
53116e27 286 "ssr", "spc",
a38d2a54 287 /* bank 0 43 - 50 */
53116e27 288 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
a38d2a54 289 /* bank 1 51 - 58 */
53116e27 290 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
a38d2a54 291 /* double precision (pseudo) 59 - 66 */
fe9f384f 292 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
a38d2a54 293 /* vectors (pseudo) 67 - 70 */
fe9f384f 294 "fv0", "fv4", "fv8", "fv12",
a38d2a54
EZ		 295 /* FIXME: missing XF 71 - 86 */
296 /* FIXME: missing XD 87 - 94 */
53116e27
EZ		 297 };
298 if (reg_nr < 0)
299 return NULL;
300 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
301 return NULL;
302 return register_names[reg_nr];
303}
304
cc17453a 305static unsigned char *
fba45db2 306sh_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
cc17453a
EZ		 307{
308 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */
309 static unsigned char breakpoint[] = {0xc3, 0xc3};
310
311 *lenptr = sizeof (breakpoint);
312 return breakpoint;
313}
c906108c
SS		 314
315/* Prologue looks like
c5aa993b
JM		 316 [mov.l <regs>,@-r15]...
317 [sts.l pr,@-r15]
318 [mov.l r14,@-r15]
319 [mov r15,r14]
8db62801
EZ		 320
321 Actually it can be more complicated than this. For instance, with
322 newer gcc's:
323
324 mov.l r14,@-r15
325 add #-12,r15
326 mov r15,r14
327 mov r4,r1
328 mov r5,r2
329 mov.l r6,@(4,r14)
330 mov.l r7,@(8,r14)
331 mov.b r1,@r14
332 mov r14,r1
333 mov r14,r1
334 add #2,r1
335 mov.w r2,@r1
336
c5aa993b 337 */
c906108c 338
8db62801
EZ		 339/* STS.L PR,@-r15 0100111100100010
340 r15-4-->r15, PR-->(r15) */
c906108c 341#define IS_STS(x) ((x) == 0x4f22)
8db62801
EZ		 342
343/* MOV.L Rm,@-r15 00101111mmmm0110
344 r15-4-->r15, Rm-->(R15) */
c906108c 345#define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
8db62801 346
c906108c 347#define GET_PUSHED_REG(x) (((x) >> 4) & 0xf)
8db62801
EZ		 348
349/* MOV r15,r14 0110111011110011
350 r15-->r14 */
c906108c 351#define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
8db62801
EZ		 352
353/* ADD #imm,r15 01111111iiiiiiii
354 r15+imm-->r15 */
c906108c 355#define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00)
8db62801 356
c906108c
SS		 357#define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
358#define IS_SHLL_R3(x) ((x) == 0x4300)
8db62801
EZ		 359
360/* ADD r3,r15 0011111100111100
361 r15+r3-->r15 */
c906108c 362#define IS_ADD_R3SP(x) ((x) == 0x3f3c)
8db62801
EZ		 363
364/* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
8db62801 365 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
8db62801 366 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
c906108c 367#define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b)
c906108c 368
8db62801 369/* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011
8db62801 370 MOV.L Rm,@(disp,Rn) Rm-->(dispx4+Rn) 0001nnnnmmmmdddd
8db62801
EZ		 371 MOV.L Rm,@Rn Rm-->(Rn) 0010nnnnmmmm0010
372 where Rm is one of r4,r5,r6,r7 which are the argument registers. */
373#define IS_ARG_MOV(x) \
374(((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) \
cc17453a
EZ		 375 || ((((x) & 0xf000) == 0x1000) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) \
376 || ((((x) & 0xf00f) == 0x2002) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)))
8db62801
EZ		 377
378/* MOV.L Rm,@(disp,r14) 00011110mmmmdddd
379 Rm-->(dispx4+r14) where Rm is one of r4,r5,r6,r7 */
380#define IS_MOV_R14(x) \
cc17453a 381 ((((x) & 0xff00) == 0x1e) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070))
8db62801
EZ		 382
383#define FPSCR_SZ (1 << 20)
c906108c 384
c906108c
SS		 385/* Skip any prologue before the guts of a function */
386
8db62801
EZ		 387/* Skip the prologue using the debug information. If this fails we'll
388 fall back on the 'guess' method below. */
389static CORE_ADDR
fba45db2 390after_prologue (CORE_ADDR pc)
8db62801
EZ		 391{
392 struct symtab_and_line sal;
393 CORE_ADDR func_addr, func_end;
394
395 /* If we can not find the symbol in the partial symbol table, then
396 there is no hope we can determine the function's start address
397 with this code. */
398 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
399 return 0;
400
401 /* Get the line associated with FUNC_ADDR. */
402 sal = find_pc_line (func_addr, 0);
403
404 /* There are only two cases to consider. First, the end of the source line
405 is within the function bounds. In that case we return the end of the
406 source line. Second is the end of the source line extends beyond the
407 bounds of the current function. We need to use the slow code to
408 examine instructions in that case. */
409 if (sal.end < func_end)
410 return sal.end;
411 else
412 return 0;
413}
414
415/* Here we look at each instruction in the function, and try to guess
416 where the prologue ends. Unfortunately this is not always
417 accurate. */
418static CORE_ADDR
fba45db2 419skip_prologue_hard_way (CORE_ADDR start_pc)
c906108c 420{
2bfa91ee 421 CORE_ADDR here, end;
8db62801 422 int updated_fp = 0;
2bfa91ee
EZ		 423
424 if (!start_pc)
425 return 0;
426
427 for (here = start_pc, end = start_pc + (2 * 28); here < end;)
c906108c 428 {
2bfa91ee
EZ		 429 int w = read_memory_integer (here, 2);
430 here += 2;
431 if (IS_FMOV (w) || IS_PUSH (w) || IS_STS (w) || IS_MOV_R3 (w)
8db62801
EZ		 432 || IS_ADD_R3SP (w) || IS_ADD_SP (w) || IS_SHLL_R3 (w)
433 || IS_ARG_MOV (w) || IS_MOV_R14 (w))
2bfa91ee
EZ		 434 {
435 start_pc = here;
2bfa91ee 436 }
8db62801
EZ		 437 else if (IS_MOV_SP_FP (w))
438 {
439 start_pc = here;
440 updated_fp = 1;
441 }
442 else
443 /* Don't bail out yet, if we are before the copy of sp. */
444 if (updated_fp)
445 break;
c906108c
SS		 446 }
447
448 return start_pc;
449}
450
cc17453a 451static CORE_ADDR
fba45db2 452sh_skip_prologue (CORE_ADDR pc)
8db62801
EZ		 453{
454 CORE_ADDR post_prologue_pc;
455
456 /* See if we can determine the end of the prologue via the symbol table.
457 If so, then return either PC, or the PC after the prologue, whichever
458 is greater. */
459
460 post_prologue_pc = after_prologue (pc);
461
462 /* If after_prologue returned a useful address, then use it. Else
463 fall back on the instruction skipping code. */
464 if (post_prologue_pc != 0)
465 return max (pc, post_prologue_pc);
466 else
467 return (skip_prologue_hard_way (pc));
468}
469
cc17453a
EZ		 470/* Immediately after a function call, return the saved pc.
471 Can't always go through the frames for this because on some machines
472 the new frame is not set up until the new function executes
473 some instructions.
474
475 The return address is the value saved in the PR register + 4 */
476static CORE_ADDR
fba45db2 477sh_saved_pc_after_call (struct frame_info *frame)
cc17453a
EZ		 478{
479 return (ADDR_BITS_REMOVE(read_register(PR_REGNUM)));
480}
481
482/* Should call_function allocate stack space for a struct return? */
483static int
fba45db2 484sh_use_struct_convention (int gcc_p, struct type *type)
cc17453a
EZ		 485{
486 return (TYPE_LENGTH (type) > 1);
487}
488
489/* Store the address of the place in which to copy the structure the
490 subroutine will return. This is called from call_function.
491
492 We store structs through a pointer passed in R0 */
493static void
fba45db2 494sh_store_struct_return (CORE_ADDR addr, CORE_ADDR sp)
cc17453a
EZ		 495{
496 write_register (STRUCT_RETURN_REGNUM, (addr));
497}
c906108c 498
cc17453a
EZ		 499/* Disassemble an instruction. */
500static int
fba45db2 501gdb_print_insn_sh (bfd_vma memaddr, disassemble_info *info)
c906108c
SS		 502{
503 if (TARGET_BYTE_ORDER == BIG_ENDIAN)
504 return print_insn_sh (memaddr, info);
505 else
506 return print_insn_shl (memaddr, info);
507}
508
509/* Given a GDB frame, determine the address of the calling function's frame.
510 This will be used to create a new GDB frame struct, and then
511 INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame.
512
513 For us, the frame address is its stack pointer value, so we look up
514 the function prologue to determine the caller's sp value, and return it. */
cc17453a 515static CORE_ADDR
fba45db2 516sh_frame_chain (struct frame_info *frame)
c906108c
SS		 517{
518 if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame))
519 return frame->frame; /* dummy frame same as caller's frame */
2bfa91ee 520 if (frame->pc && !inside_entry_file (frame->pc))
cc17453a 521 return read_memory_integer (FRAME_FP (frame) + frame->extra_info->f_offset, 4);
c906108c
SS		 522 else
523 return 0;
524}
525
526/* Find REGNUM on the stack. Otherwise, it's in an active register. One thing
527 we might want to do here is to check REGNUM against the clobber mask, and
528 somehow flag it as invalid if it isn't saved on the stack somewhere. This
529 would provide a graceful failure mode when trying to get the value of
530 caller-saves registers for an inner frame. */
531
cc17453a 532static CORE_ADDR
fba45db2 533sh_find_callers_reg (struct frame_info *fi, int regnum)
c906108c 534{
c906108c
SS		 535 for (; fi; fi = fi->next)
536 if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
537 /* When the caller requests PR from the dummy frame, we return PC because
c5aa993b 538 that's where the previous routine appears to have done a call from. */
c906108c 539 return generic_read_register_dummy (fi->pc, fi->frame, regnum);
c5aa993b 540 else
c906108c 541 {
cc17453a 542 FRAME_INIT_SAVED_REGS (fi);
2bfa91ee
EZ		 543 if (!fi->pc)
544 return 0;
cc17453a
EZ		 545 if (fi->saved_regs[regnum] != 0)
546 return read_memory_integer (fi->saved_regs[regnum],
c5aa993b 547 REGISTER_RAW_SIZE (regnum));
c906108c
SS		 548 }
549 return read_register (regnum);
550}
551
552/* Put here the code to store, into a struct frame_saved_regs, the
553 addresses of the saved registers of frame described by FRAME_INFO.
554 This includes special registers such as pc and fp saved in special
555 ways in the stack frame. sp is even more special: the address we
556 return for it IS the sp for the next frame. */
cc17453a 557static void
fba45db2 558sh_nofp_frame_init_saved_regs (struct frame_info *fi)
c906108c
SS		 559{
560 int where[NUM_REGS];
561 int rn;
562 int have_fp = 0;
563 int depth;
564 int pc;
565 int opc;
566 int insn;
567 int r3_val = 0;
c5aa993b 568 char *dummy_regs = generic_find_dummy_frame (fi->pc, fi->frame);
cc17453a
EZ		 569
570 if (fi->saved_regs == NULL)
571 frame_saved_regs_zalloc (fi);
572 else
573 memset (fi->saved_regs, 0, SIZEOF_FRAME_SAVED_REGS);
574
575 if (dummy_regs)
576 {
577 /* DANGER! This is ONLY going to work if the char buffer format of
578 the saved registers is byte-for-byte identical to the
579 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
580 memcpy (fi->saved_regs, dummy_regs, sizeof (fi->saved_regs));
581 return;
582 }
583
584 fi->extra_info->leaf_function = 1;
585 fi->extra_info->f_offset = 0;
586
587 for (rn = 0; rn < NUM_REGS; rn++)
588 where[rn] = -1;
589
590 depth = 0;
591
592 /* Loop around examining the prologue insns until we find something
593 that does not appear to be part of the prologue. But give up
594 after 20 of them, since we're getting silly then. */
595
596 pc = get_pc_function_start (fi->pc);
597 if (!pc)
598 {
599 fi->pc = 0;
600 return;
601 }
602
603 for (opc = pc + (2 * 28); pc < opc; pc += 2)
604 {
605 insn = read_memory_integer (pc, 2);
606 /* See where the registers will be saved to */
607 if (IS_PUSH (insn))
608 {
609 rn = GET_PUSHED_REG (insn);
610 where[rn] = depth;
611 depth += 4;
612 }
613 else if (IS_STS (insn))
614 {
615 where[PR_REGNUM] = depth;
616 /* If we're storing the pr then this isn't a leaf */
617 fi->extra_info->leaf_function = 0;
618 depth += 4;
619 }
620 else if (IS_MOV_R3 (insn))
621 {
622 r3_val = ((insn & 0xff) ^ 0x80) - 0x80;
623 }
624 else if (IS_SHLL_R3 (insn))
625 {
626 r3_val <<= 1;
627 }
628 else if (IS_ADD_R3SP (insn))
629 {
630 depth += -r3_val;
631 }
632 else if (IS_ADD_SP (insn))
633 {
634 depth -= ((insn & 0xff) ^ 0x80) - 0x80;
635 }
636 else if (IS_MOV_SP_FP (insn))
637 break;
638#if 0 /* This used to just stop when it found an instruction that
639 was not considered part of the prologue. Now, we just
640 keep going looking for likely instructions. */
641 else
642 break;
643#endif
644 }
645
646 /* Now we know how deep things are, we can work out their addresses */
647
648 for (rn = 0; rn < NUM_REGS; rn++)
649 {
650 if (where[rn] >= 0)
651 {
652 if (rn == FP_REGNUM)
653 have_fp = 1;
c906108c 654
cc17453a
EZ		 655 fi->saved_regs[rn] = fi->frame - where[rn] + depth - 4;
656 }
657 else
658 {
659 fi->saved_regs[rn] = 0;
660 }
661 }
662
663 if (have_fp)
664 {
665 fi->saved_regs[SP_REGNUM] = read_memory_integer (fi->saved_regs[FP_REGNUM], 4);
666 }
667 else
668 {
669 fi->saved_regs[SP_REGNUM] = fi->frame - 4;
670 }
671
672 fi->extra_info->f_offset = depth - where[FP_REGNUM] - 4;
673 /* Work out the return pc - either from the saved pr or the pr
674 value */
675}
676
677static void
fba45db2 678sh_fp_frame_init_saved_regs (struct frame_info *fi)
cc17453a
EZ		 679{
680 int where[NUM_REGS];
681 int rn;
682 int have_fp = 0;
683 int depth;
684 int pc;
685 int opc;
686 int insn;
687 int r3_val = 0;
688 char *dummy_regs = generic_find_dummy_frame (fi->pc, fi->frame);
689
690 if (fi->saved_regs == NULL)
691 frame_saved_regs_zalloc (fi);
692 else
693 memset (fi->saved_regs, 0, SIZEOF_FRAME_SAVED_REGS);
694
c906108c
SS		 695 if (dummy_regs)
696 {
697 /* DANGER! This is ONLY going to work if the char buffer format of
c5aa993b
JM		 698 the saved registers is byte-for-byte identical to the
699 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
cc17453a 700 memcpy (fi->saved_regs, dummy_regs, sizeof (fi->saved_regs));
c906108c
SS		 701 return;
702 }
703
cc17453a
EZ		 704 fi->extra_info->leaf_function = 1;
705 fi->extra_info->f_offset = 0;
c906108c
SS		 706
707 for (rn = 0; rn < NUM_REGS; rn++)
708 where[rn] = -1;
709
710 depth = 0;
711
712 /* Loop around examining the prologue insns until we find something
713 that does not appear to be part of the prologue. But give up
714 after 20 of them, since we're getting silly then. */
715
2bfa91ee
EZ		 716 pc = get_pc_function_start (fi->pc);
717 if (!pc)
c906108c 718 {
2bfa91ee
EZ		 719 fi->pc = 0;
720 return;
721 }
722
723 for (opc = pc + (2 * 28); pc < opc; pc += 2)
724 {
725 insn = read_memory_integer (pc, 2);
c906108c
SS		 726 /* See where the registers will be saved to */
727 if (IS_PUSH (insn))
728 {
c906108c
SS		 729 rn = GET_PUSHED_REG (insn);
730 where[rn] = depth;
c906108c
SS		 731 depth += 4;
732 }
733 else if (IS_STS (insn))
734 {
c906108c 735 where[PR_REGNUM] = depth;
c906108c 736 /* If we're storing the pr then this isn't a leaf */
cc17453a 737 fi->extra_info->leaf_function = 0;
c906108c
SS		 738 depth += 4;
739 }
740 else if (IS_MOV_R3 (insn))
741 {
742 r3_val = ((insn & 0xff) ^ 0x80) - 0x80;
c906108c
SS		 743 }
744 else if (IS_SHLL_R3 (insn))
745 {
746 r3_val <<= 1;
c906108c
SS		 747 }
748 else if (IS_ADD_R3SP (insn))
749 {
750 depth += -r3_val;
c906108c
SS		 751 }
752 else if (IS_ADD_SP (insn))
753 {
c906108c 754 depth -= ((insn & 0xff) ^ 0x80) - 0x80;
c906108c
SS		 755 }
756 else if (IS_FMOV (insn))
757 {
cc17453a 758 if (read_register (gdbarch_tdep (current_gdbarch)->FPSCR_REGNUM) & FPSCR_SZ)
c906108c
SS		 759 {
760 depth += 8;
761 }
762 else
763 {
764 depth += 4;
765 }
766 }
2bfa91ee
EZ		 767 else if (IS_MOV_SP_FP (insn))
768 break;
769#if 0 /* This used to just stop when it found an instruction that
770 was not considered part of the prologue. Now, we just
771 keep going looking for likely instructions. */
c906108c
SS		 772 else
773 break;
2bfa91ee 774#endif
c906108c
SS		 775 }
776
777 /* Now we know how deep things are, we can work out their addresses */
778
779 for (rn = 0; rn < NUM_REGS; rn++)
780 {
781 if (where[rn] >= 0)
782 {
783 if (rn == FP_REGNUM)
784 have_fp = 1;
785
cc17453a 786 fi->saved_regs[rn] = fi->frame - where[rn] + depth - 4;
c906108c
SS		 787 }
788 else
789 {
cc17453a 790 fi->saved_regs[rn] = 0;
c906108c
SS		 791 }
792 }
793
794 if (have_fp)
795 {
cc17453a 796 fi->saved_regs[SP_REGNUM] = read_memory_integer (fi->saved_regs[FP_REGNUM], 4);
c906108c
SS		 797 }
798 else
799 {
cc17453a 800 fi->saved_regs[SP_REGNUM] = fi->frame - 4;
c906108c
SS		 801 }
802
cc17453a 803 fi->extra_info->f_offset = depth - where[FP_REGNUM] - 4;
c906108c
SS		 804 /* Work out the return pc - either from the saved pr or the pr
805 value */
806}
807
cc17453a
EZ		 808/* Initialize the extra info saved in a FRAME */
809static void
fba45db2 810sh_init_extra_frame_info (int fromleaf, struct frame_info *fi)
c906108c 811{
cc17453a
EZ		 812
813 fi->extra_info = (struct frame_extra_info *)
814 frame_obstack_alloc (sizeof (struct frame_extra_info));
c906108c
SS		 815
816 if (fi->next)
817 fi->pc = FRAME_SAVED_PC (fi->next);
818
819 if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
820 {
821 /* We need to setup fi->frame here because run_stack_dummy gets it wrong
c5aa993b
JM		 822 by assuming it's always FP. */
823 fi->frame = generic_read_register_dummy (fi->pc, fi->frame,
824 SP_REGNUM);
cc17453a
EZ		 825 fi->extra_info->return_pc = generic_read_register_dummy (fi->pc, fi->frame,
826 PC_REGNUM);
827 fi->extra_info->f_offset = -(CALL_DUMMY_LENGTH + 4);
828 fi->extra_info->leaf_function = 0;
c906108c
SS		 829 return;
830 }
831 else
832 {
cc17453a
EZ		 833 FRAME_INIT_SAVED_REGS (fi);
834 fi->extra_info->return_pc = sh_find_callers_reg (fi, PR_REGNUM);
c906108c
SS		 835 }
836}
837
cc17453a
EZ		 838/* Extract from an array REGBUF containing the (raw) register state
839 the address in which a function should return its structure value,
840 as a CORE_ADDR (or an expression that can be used as one). */
b3df3fff 841static CORE_ADDR
0c8053b6 842sh_extract_struct_value_address (char *regbuf)
cc17453a
EZ		 843{
844 return (extract_address ((regbuf), REGISTER_RAW_SIZE (0)));
845}
846
847static CORE_ADDR
fba45db2 848sh_frame_saved_pc (struct frame_info *frame)
cc17453a
EZ		 849{
850 return ((frame)->extra_info->return_pc);
851}
852
853static CORE_ADDR
fba45db2 854sh_frame_args_address (struct frame_info *fi)
cc17453a
EZ		 855{
856 return (fi)->frame;
857}
858
859static CORE_ADDR
fba45db2 860sh_frame_locals_address (struct frame_info *fi)
cc17453a
EZ		 861{
862 return (fi)->frame;
863}
864
c906108c
SS		 865/* Discard from the stack the innermost frame,
866 restoring all saved registers. */
cc17453a 867static void
fba45db2 868sh_pop_frame (void)
c906108c
SS		 869{
870 register struct frame_info *frame = get_current_frame ();
871 register CORE_ADDR fp;
872 register int regnum;
c906108c
SS		 873
874 if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame))
875 generic_pop_dummy_frame ();
876 else
c5aa993b
JM		 877 {
878 fp = FRAME_FP (frame);
cc17453a 879 FRAME_INIT_SAVED_REGS (frame);
c906108c 880
c5aa993b
JM		 881 /* Copy regs from where they were saved in the frame */
882 for (regnum = 0; regnum < NUM_REGS; regnum++)
cc17453a
EZ		 883 if (frame->saved_regs[regnum])
884 write_register (regnum, read_memory_integer (frame->saved_regs[regnum], 4));
c906108c 885
cc17453a 886 write_register (PC_REGNUM, frame->extra_info->return_pc);
c5aa993b
JM		 887 write_register (SP_REGNUM, fp + 4);
888 }
c906108c
SS		 889 flush_cached_frames ();
890}
891
892/* Function: push_arguments
893 Setup the function arguments for calling a function in the inferior.
894
895 On the Hitachi SH architecture, there are four registers (R4 to R7)
896 which are dedicated for passing function arguments. Up to the first
897 four arguments (depending on size) may go into these registers.
898 The rest go on the stack.
899
900 Arguments that are smaller than 4 bytes will still take up a whole
901 register or a whole 32-bit word on the stack, and will be
902 right-justified in the register or the stack word. This includes
903 chars, shorts, and small aggregate types.
904
905 Arguments that are larger than 4 bytes may be split between two or
906 more registers. If there are not enough registers free, an argument
907 may be passed partly in a register (or registers), and partly on the
908 stack. This includes doubles, long longs, and larger aggregates.
909 As far as I know, there is no upper limit to the size of aggregates
910 that will be passed in this way; in other words, the convention of
911 passing a pointer to a large aggregate instead of a copy is not used.
912
913 An exceptional case exists for struct arguments (and possibly other
914 aggregates such as arrays) if the size is larger than 4 bytes but
915 not a multiple of 4 bytes. In this case the argument is never split
916 between the registers and the stack, but instead is copied in its
917 entirety onto the stack, AND also copied into as many registers as
918 there is room for. In other words, space in registers permitting,
919 two copies of the same argument are passed in. As far as I can tell,
920 only the one on the stack is used, although that may be a function
921 of the level of compiler optimization. I suspect this is a compiler
922 bug. Arguments of these odd sizes are left-justified within the
923 word (as opposed to arguments smaller than 4 bytes, which are
924 right-justified).
c5aa993b 925
c906108c
SS		 926 If the function is to return an aggregate type such as a struct, it
927 is either returned in the normal return value register R0 (if its
928 size is no greater than one byte), or else the caller must allocate
929 space into which the callee will copy the return value (if the size
930 is greater than one byte). In this case, a pointer to the return
931 value location is passed into the callee in register R2, which does
932 not displace any of the other arguments passed in via registers R4
933 to R7. */
934
cc17453a 935static CORE_ADDR
34e9d9bb
EZ		 936sh_push_arguments (int nargs, struct value **args, CORE_ADDR sp,
937 int struct_return, CORE_ADDR struct_addr)
c906108c
SS		 938{
939 int stack_offset, stack_alloc;
940 int argreg;
941 int argnum;
942 struct type *type;
943 CORE_ADDR regval;
944 char *val;
945 char valbuf[4];
946 int len;
947 int odd_sized_struct;
948
949 /* first force sp to a 4-byte alignment */
950 sp = sp & ~3;
951
952 /* The "struct return pointer" pseudo-argument has its own dedicated
953 register */
954 if (struct_return)
c5aa993b 955 write_register (STRUCT_RETURN_REGNUM, struct_addr);
c906108c
SS		 956
957 /* Now make sure there's space on the stack */
cc17453a 958 for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++)
c5aa993b
JM		 959 stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 3) & ~3);
960 sp -= stack_alloc; /* make room on stack for args */
c906108c 961
c906108c
SS		 962 /* Now load as many as possible of the first arguments into
963 registers, and push the rest onto the stack. There are 16 bytes
964 in four registers available. Loop thru args from first to last. */
965
966 argreg = ARG0_REGNUM;
967 for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
968 {
969 type = VALUE_TYPE (args[argnum]);
c5aa993b
JM		 970 len = TYPE_LENGTH (type);
971 memset (valbuf, 0, sizeof (valbuf));
c906108c 972 if (len < 4)
cc17453a
EZ		 973 {
974 /* value gets right-justified in the register or stack word */
c5aa993b
JM		 975 memcpy (valbuf + (4 - len),
976 (char *) VALUE_CONTENTS (args[argnum]), len);
977 val = valbuf;
978 }
c906108c 979 else
c5aa993b 980 val = (char *) VALUE_CONTENTS (args[argnum]);
c906108c
SS		 981
982 if (len > 4 && (len & 3) != 0)
c5aa993b
JM		 983 odd_sized_struct = 1; /* such structs go entirely on stack */
984 else
c906108c
SS		 985 odd_sized_struct = 0;
986 while (len > 0)
987 {
988 if (argreg > ARGLAST_REGNUM || odd_sized_struct)
c5aa993b 989 { /* must go on the stack */
c906108c
SS		 990 write_memory (sp + stack_offset, val, 4);
991 stack_offset += 4;
992 }
993 /* NOTE WELL!!!!! This is not an "else if" clause!!!
994 That's because some *&^%$ things get passed on the stack
995 AND in the registers! */
996 if (argreg <= ARGLAST_REGNUM)
c5aa993b
JM		 997 { /* there's room in a register */
998 regval = extract_address (val, REGISTER_RAW_SIZE (argreg));
c906108c
SS		 999 write_register (argreg++, regval);
1000 }
1001 /* Store the value 4 bytes at a time. This means that things
1002 larger than 4 bytes may go partly in registers and partly
1003 on the stack. */
c5aa993b
JM		 1004 len -= REGISTER_RAW_SIZE (argreg);
1005 val += REGISTER_RAW_SIZE (argreg);
c906108c
SS		 1006 }
1007 }
1008 return sp;
1009}
1010
1011/* Function: push_return_address (pc)
1012 Set up the return address for the inferior function call.
1013 Needed for targets where we don't actually execute a JSR/BSR instruction */
1014
cc17453a 1015static CORE_ADDR
fba45db2 1016sh_push_return_address (CORE_ADDR pc, CORE_ADDR sp)
c906108c
SS		 1017{
1018 write_register (PR_REGNUM, CALL_DUMMY_ADDRESS ());
1019 return sp;
1020}
1021
1022/* Function: fix_call_dummy
1023 Poke the callee function's address into the destination part of
1024 the CALL_DUMMY. The address is actually stored in a data word
1025 following the actualy CALL_DUMMY instructions, which will load
1026 it into a register using PC-relative addressing. This function
1027 expects the CALL_DUMMY to look like this:
1028
c5aa993b
JM		 1029 mov.w @(2,PC), R8
1030 jsr @R8
1031 nop
1032 trap
1033 <destination>
1034 */
c906108c
SS		 1035
1036#if 0
1037void
fba45db2
KB		 1038sh_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, int nargs,
1039 value_ptr *args, struct type *type, int gcc_p)
c906108c
SS		 1040{
1041 *(unsigned long *) (dummy + 8) = fun;
1042}
1043#endif
1044
cc17453a
EZ		 1045static int
1046sh_coerce_float_to_double (struct type *formal, struct type *actual)
1047{
1048 return 1;
1049}
c906108c 1050
cc17453a
EZ		 1051/* Find a function's return value in the appropriate registers (in
1052 regbuf), and copy it into valbuf. Extract from an array REGBUF
1053 containing the (raw) register state a function return value of type
1054 TYPE, and copy that, in virtual format, into VALBUF. */
1055static void
fba45db2 1056sh_extract_return_value (struct type *type, char *regbuf, char *valbuf)
c906108c 1057{
cc17453a 1058 int len = TYPE_LENGTH (type);
c906108c 1059
cc17453a
EZ		 1060 if (len <= 4)
1061 memcpy (valbuf, ((char *) regbuf) + 4 - len, len);
1062 else if (len <= 8)
1063 memcpy (valbuf, ((char *) regbuf) + 8 - len, len);
1064 else
1065 error ("bad size for return value");
1066}
c906108c 1067
cc17453a
EZ		 1068/* Write into appropriate registers a function return value
1069 of type TYPE, given in virtual format.
1070 If the architecture is sh4 or sh3e, store a function's return value
1071 in the R0 general register or in the FP0 floating point register,
1072 depending on the type of the return value. In all the other cases
1073 the result is stored in r0. */
1074static void
1075sh_default_store_return_value (struct type *type, char *valbuf)
1076{
1077 write_register_bytes (REGISTER_BYTE (0),
1078 valbuf, TYPE_LENGTH (type));
1079}
c906108c 1080
cc17453a
EZ		 1081static void
1082sh3e_sh4_store_return_value (struct type *type, char *valbuf)
1083{
1084 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1085 write_register_bytes (REGISTER_BYTE (FP0_REGNUM),
1086 valbuf, TYPE_LENGTH (type));
1087 else
1088 write_register_bytes (REGISTER_BYTE (0),
1089 valbuf, TYPE_LENGTH (type));
c906108c
SS		 1090}
1091
cc17453a 1092
c906108c
SS		 1093/* Print the registers in a form similar to the E7000 */
1094
1095static void
fba45db2 1096sh_generic_show_regs (void)
c906108c 1097{
cc17453a
EZ		 1098 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1099 paddr (read_register (PC_REGNUM)),
c62a7c7b 1100 (long) read_register (gdbarch_tdep (current_gdbarch)->SR_REGNUM),
cc17453a
EZ		 1101 (long) read_register (PR_REGNUM),
1102 (long) read_register (MACH_REGNUM),
1103 (long) read_register (MACL_REGNUM));
1104
1105 printf_filtered ("GBR=%08lx VBR=%08lx",
1106 (long) read_register (GBR_REGNUM),
1107 (long) read_register (VBR_REGNUM));
1108
1109 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1110 (long) read_register (0),
1111 (long) read_register (1),
1112 (long) read_register (2),
1113 (long) read_register (3),
1114 (long) read_register (4),
1115 (long) read_register (5),
1116 (long) read_register (6),
1117 (long) read_register (7));
1118 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1119 (long) read_register (8),
1120 (long) read_register (9),
1121 (long) read_register (10),
1122 (long) read_register (11),
1123 (long) read_register (12),
1124 (long) read_register (13),
1125 (long) read_register (14),
1126 (long) read_register (15));
1127}
c906108c 1128
cc17453a 1129static void
fba45db2 1130sh3_show_regs (void)
cc17453a 1131{
d4f3574e
SS		 1132 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1133 paddr (read_register (PC_REGNUM)),
c62a7c7b 1134 (long) read_register (gdbarch_tdep (current_gdbarch)->SR_REGNUM),
d4f3574e
SS		 1135 (long) read_register (PR_REGNUM),
1136 (long) read_register (MACH_REGNUM),
1137 (long) read_register (MACL_REGNUM));
1138
1139 printf_filtered ("GBR=%08lx VBR=%08lx",
1140 (long) read_register (GBR_REGNUM),
1141 (long) read_register (VBR_REGNUM));
cc17453a
EZ		 1142 printf_filtered (" SSR=%08lx SPC=%08lx",
1143 (long) read_register (gdbarch_tdep (current_gdbarch)->SSR_REGNUM),
1144 (long) read_register (gdbarch_tdep (current_gdbarch)->SPC_REGNUM));
c906108c 1145
d4f3574e
SS		 1146 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1147 (long) read_register (0),
1148 (long) read_register (1),
1149 (long) read_register (2),
1150 (long) read_register (3),
1151 (long) read_register (4),
1152 (long) read_register (5),
1153 (long) read_register (6),
1154 (long) read_register (7));
1155 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1156 (long) read_register (8),
1157 (long) read_register (9),
1158 (long) read_register (10),
1159 (long) read_register (11),
1160 (long) read_register (12),
1161 (long) read_register (13),
1162 (long) read_register (14),
1163 (long) read_register (15));
c906108c
SS		 1164}
1165
53116e27 1166
cc17453a 1167static void
fba45db2 1168sh3e_show_regs (void)
cc17453a
EZ		 1169{
1170 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1171 paddr (read_register (PC_REGNUM)),
c62a7c7b 1172 (long) read_register (gdbarch_tdep (current_gdbarch)->SR_REGNUM),
cc17453a
EZ		 1173 (long) read_register (PR_REGNUM),
1174 (long) read_register (MACH_REGNUM),
1175 (long) read_register (MACL_REGNUM));
1176
1177 printf_filtered ("GBR=%08lx VBR=%08lx",
1178 (long) read_register (GBR_REGNUM),
1179 (long) read_register (VBR_REGNUM));
1180 printf_filtered (" SSR=%08lx SPC=%08lx",
1181 (long) read_register (gdbarch_tdep (current_gdbarch)->SSR_REGNUM),
1182 (long) read_register (gdbarch_tdep (current_gdbarch)->SPC_REGNUM));
1183 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1184 (long) read_register (gdbarch_tdep (current_gdbarch)->FPUL_REGNUM),
1185 (long) read_register (gdbarch_tdep (current_gdbarch)->FPSCR_REGNUM));
c906108c 1186
cc17453a
EZ		 1187 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1188 (long) read_register (0),
1189 (long) read_register (1),
1190 (long) read_register (2),
1191 (long) read_register (3),
1192 (long) read_register (4),
1193 (long) read_register (5),
1194 (long) read_register (6),
1195 (long) read_register (7));
1196 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1197 (long) read_register (8),
1198 (long) read_register (9),
1199 (long) read_register (10),
1200 (long) read_register (11),
1201 (long) read_register (12),
1202 (long) read_register (13),
1203 (long) read_register (14),
1204 (long) read_register (15));
1205
1206 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1207 (long) read_register (FP0_REGNUM + 0),
1208 (long) read_register (FP0_REGNUM + 1),
1209 (long) read_register (FP0_REGNUM + 2),
1210 (long) read_register (FP0_REGNUM + 3),
1211 (long) read_register (FP0_REGNUM + 4),
1212 (long) read_register (FP0_REGNUM + 5),
1213 (long) read_register (FP0_REGNUM + 6),
1214 (long) read_register (FP0_REGNUM + 7));
1215 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1216 (long) read_register (FP0_REGNUM + 8),
1217 (long) read_register (FP0_REGNUM + 9),
1218 (long) read_register (FP0_REGNUM + 10),
1219 (long) read_register (FP0_REGNUM + 11),
1220 (long) read_register (FP0_REGNUM + 12),
1221 (long) read_register (FP0_REGNUM + 13),
1222 (long) read_register (FP0_REGNUM + 14),
1223 (long) read_register (FP0_REGNUM + 15));
1224}
1225
1226static void
fba45db2 1227sh3_dsp_show_regs (void)
c906108c 1228{
cc17453a
EZ		 1229 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1230 paddr (read_register (PC_REGNUM)),
c62a7c7b 1231 (long) read_register (gdbarch_tdep (current_gdbarch)->SR_REGNUM),
cc17453a
EZ		 1232 (long) read_register (PR_REGNUM),
1233 (long) read_register (MACH_REGNUM),
1234 (long) read_register (MACL_REGNUM));
c906108c 1235
cc17453a
EZ		 1236 printf_filtered ("GBR=%08lx VBR=%08lx",
1237 (long) read_register (GBR_REGNUM),
1238 (long) read_register (VBR_REGNUM));
1239
1240 printf_filtered (" SSR=%08lx SPC=%08lx",
1241 (long) read_register (gdbarch_tdep (current_gdbarch)->SSR_REGNUM),
1242 (long) read_register (gdbarch_tdep (current_gdbarch)->SPC_REGNUM));
1243
1244 printf_filtered (" DSR=%08lx",
1245 (long) read_register (gdbarch_tdep (current_gdbarch)->DSR_REGNUM));
1246
1247 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1248 (long) read_register (0),
1249 (long) read_register (1),
1250 (long) read_register (2),
1251 (long) read_register (3),
1252 (long) read_register (4),
1253 (long) read_register (5),
1254 (long) read_register (6),
1255 (long) read_register (7));
1256 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1257 (long) read_register (8),
1258 (long) read_register (9),
1259 (long) read_register (10),
1260 (long) read_register (11),
1261 (long) read_register (12),
1262 (long) read_register (13),
1263 (long) read_register (14),
1264 (long) read_register (15));
1265
1266 printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1267 (long) read_register (gdbarch_tdep (current_gdbarch)->A0G_REGNUM) & 0xff,
1268 (long) read_register (gdbarch_tdep (current_gdbarch)->A0_REGNUM),
1269 (long) read_register (gdbarch_tdep (current_gdbarch)->M0_REGNUM),
1270 (long) read_register (gdbarch_tdep (current_gdbarch)->X0_REGNUM),
1271 (long) read_register (gdbarch_tdep (current_gdbarch)->Y0_REGNUM),
1272 (long) read_register (gdbarch_tdep (current_gdbarch)->RS_REGNUM),
1273 (long) read_register (gdbarch_tdep (current_gdbarch)->MOD_REGNUM));
1274 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1275 (long) read_register (gdbarch_tdep (current_gdbarch)->A1G_REGNUM) & 0xff,
1276 (long) read_register (gdbarch_tdep (current_gdbarch)->A1_REGNUM),
1277 (long) read_register (gdbarch_tdep (current_gdbarch)->M1_REGNUM),
1278 (long) read_register (gdbarch_tdep (current_gdbarch)->X1_REGNUM),
1279 (long) read_register (gdbarch_tdep (current_gdbarch)->Y1_REGNUM),
1280 (long) read_register (gdbarch_tdep (current_gdbarch)->RE_REGNUM));
c906108c
SS		 1281}
1282
cc17453a 1283static void
fba45db2 1284sh4_show_regs (void)
cc17453a
EZ		 1285{
1286 int pr = read_register (gdbarch_tdep (current_gdbarch)->FPSCR_REGNUM) & 0x80000;
1287 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1288 paddr (read_register (PC_REGNUM)),
c62a7c7b 1289 (long) read_register (gdbarch_tdep (current_gdbarch)->SR_REGNUM),
cc17453a
EZ		 1290 (long) read_register (PR_REGNUM),
1291 (long) read_register (MACH_REGNUM),
1292 (long) read_register (MACL_REGNUM));
1293
1294 printf_filtered ("GBR=%08lx VBR=%08lx",
1295 (long) read_register (GBR_REGNUM),
1296 (long) read_register (VBR_REGNUM));
1297 printf_filtered (" SSR=%08lx SPC=%08lx",
1298 (long) read_register (gdbarch_tdep (current_gdbarch)->SSR_REGNUM),
1299 (long) read_register (gdbarch_tdep (current_gdbarch)->SPC_REGNUM));
1300 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1301 (long) read_register (gdbarch_tdep (current_gdbarch)->FPUL_REGNUM),
1302 (long) read_register (gdbarch_tdep (current_gdbarch)->FPSCR_REGNUM));
1303
1304 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1305 (long) read_register (0),
1306 (long) read_register (1),
1307 (long) read_register (2),
1308 (long) read_register (3),
1309 (long) read_register (4),
1310 (long) read_register (5),
1311 (long) read_register (6),
1312 (long) read_register (7));
1313 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1314 (long) read_register (8),
1315 (long) read_register (9),
1316 (long) read_register (10),
1317 (long) read_register (11),
1318 (long) read_register (12),
1319 (long) read_register (13),
1320 (long) read_register (14),
1321 (long) read_register (15));
1322
1323 printf_filtered ((pr
1324 ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1325 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1326 (long) read_register (FP0_REGNUM + 0),
1327 (long) read_register (FP0_REGNUM + 1),
1328 (long) read_register (FP0_REGNUM + 2),
1329 (long) read_register (FP0_REGNUM + 3),
1330 (long) read_register (FP0_REGNUM + 4),
1331 (long) read_register (FP0_REGNUM + 5),
1332 (long) read_register (FP0_REGNUM + 6),
1333 (long) read_register (FP0_REGNUM + 7));
1334 printf_filtered ((pr
1335 ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1336 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1337 (long) read_register (FP0_REGNUM + 8),
1338 (long) read_register (FP0_REGNUM + 9),
1339 (long) read_register (FP0_REGNUM + 10),
1340 (long) read_register (FP0_REGNUM + 11),
1341 (long) read_register (FP0_REGNUM + 12),
1342 (long) read_register (FP0_REGNUM + 13),
1343 (long) read_register (FP0_REGNUM + 14),
1344 (long) read_register (FP0_REGNUM + 15));
1345}
1346
1347static void
fba45db2 1348sh_dsp_show_regs (void)
cc17453a
EZ		 1349{
1350 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1351 paddr (read_register (PC_REGNUM)),
c62a7c7b 1352 (long) read_register (gdbarch_tdep (current_gdbarch)->SR_REGNUM),
cc17453a
EZ		 1353 (long) read_register (PR_REGNUM),
1354 (long) read_register (MACH_REGNUM),
1355 (long) read_register (MACL_REGNUM));
1356
1357 printf_filtered ("GBR=%08lx VBR=%08lx",
1358 (long) read_register (GBR_REGNUM),
1359 (long) read_register (VBR_REGNUM));
1360
1361 printf_filtered (" DSR=%08lx",
1362 (long) read_register (gdbarch_tdep (current_gdbarch)->DSR_REGNUM));
1363
1364 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1365 (long) read_register (0),
1366 (long) read_register (1),
1367 (long) read_register (2),
1368 (long) read_register (3),
1369 (long) read_register (4),
1370 (long) read_register (5),
1371 (long) read_register (6),
1372 (long) read_register (7));
1373 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1374 (long) read_register (8),
1375 (long) read_register (9),
1376 (long) read_register (10),
1377 (long) read_register (11),
1378 (long) read_register (12),
1379 (long) read_register (13),
1380 (long) read_register (14),
1381 (long) read_register (15));
1382
1383 printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1384 (long) read_register (gdbarch_tdep (current_gdbarch)->A0G_REGNUM) & 0xff,
1385 (long) read_register (gdbarch_tdep (current_gdbarch)->A0_REGNUM),
1386 (long) read_register (gdbarch_tdep (current_gdbarch)->M0_REGNUM),
1387 (long) read_register (gdbarch_tdep (current_gdbarch)->X0_REGNUM),
1388 (long) read_register (gdbarch_tdep (current_gdbarch)->Y0_REGNUM),
1389 (long) read_register (gdbarch_tdep (current_gdbarch)->RS_REGNUM),
1390 (long) read_register (gdbarch_tdep (current_gdbarch)->MOD_REGNUM));
1391 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1392 (long) read_register (gdbarch_tdep (current_gdbarch)->A1G_REGNUM) & 0xff,
1393 (long) read_register (gdbarch_tdep (current_gdbarch)->A1_REGNUM),
1394 (long) read_register (gdbarch_tdep (current_gdbarch)->M1_REGNUM),
1395 (long) read_register (gdbarch_tdep (current_gdbarch)->X1_REGNUM),
1396 (long) read_register (gdbarch_tdep (current_gdbarch)->Y1_REGNUM),
1397 (long) read_register (gdbarch_tdep (current_gdbarch)->RE_REGNUM));
1398}
1399
53116e27
EZ		 1400void sh_show_regs_command (char *args, int from_tty)
1401{
1402 if (sh_show_regs)
1403 (*sh_show_regs)();
1404}
1405
cc17453a
EZ		 1406/* Index within `registers' of the first byte of the space for
1407 register N. */
1408static int
fba45db2 1409sh_default_register_byte (int reg_nr)
8db62801 1410{
cc17453a
EZ		 1411 return (reg_nr * 4);
1412}
1413
53116e27 1414static int
fba45db2 1415sh_sh4_register_byte (int reg_nr)
53116e27
EZ		 1416{
1417 if (reg_nr >= gdbarch_tdep (current_gdbarch)->DR0_REGNUM
e6c42fda 1418 && reg_nr <= gdbarch_tdep (current_gdbarch)->DR_LAST_REGNUM)
53116e27
EZ		 1419 return (dr_reg_base_num (reg_nr) * 4);
1420 else if (reg_nr >= gdbarch_tdep (current_gdbarch)->FV0_REGNUM
e6c42fda 1421 && reg_nr <= gdbarch_tdep (current_gdbarch)->FV_LAST_REGNUM)
53116e27
EZ		 1422 return (fv_reg_base_num (reg_nr) * 4);
1423 else
1424 return (reg_nr * 4);
1425}
1426
cc17453a
EZ		 1427/* Number of bytes of storage in the actual machine representation for
1428 register REG_NR. */
1429static int
fba45db2 1430sh_default_register_raw_size (int reg_nr)
cc17453a
EZ		 1431{
1432 return 4;
1433}
1434
53116e27 1435static int
fba45db2 1436sh_sh4_register_raw_size (int reg_nr)
53116e27
EZ		 1437{
1438 if (reg_nr >= gdbarch_tdep (current_gdbarch)->DR0_REGNUM
e6c42fda 1439 && reg_nr <= gdbarch_tdep (current_gdbarch)->DR_LAST_REGNUM)
53116e27
EZ		 1440 return 8;
1441 else if (reg_nr >= gdbarch_tdep (current_gdbarch)->FV0_REGNUM
e6c42fda 1442 && reg_nr <= gdbarch_tdep (current_gdbarch)->FV_LAST_REGNUM)
53116e27
EZ		 1443 return 16;
1444 else
1445 return 4;
1446}
1447
cc17453a
EZ		 1448/* Number of bytes of storage in the program's representation
1449 for register N. */
1450static int
fba45db2 1451sh_register_virtual_size (int reg_nr)
cc17453a
EZ		 1452{
1453 return 4;
1454}
1455
1456/* Return the GDB type object for the "standard" data type
1457 of data in register N. */
1458
1459static struct type *
fba45db2 1460sh_sh3e_register_virtual_type (int reg_nr)
cc17453a
EZ		 1461{
1462 if ((reg_nr >= FP0_REGNUM
e6c42fda 1463 && (reg_nr <= gdbarch_tdep (current_gdbarch)->FP_LAST_REGNUM))
cc17453a
EZ		 1464 || (reg_nr == gdbarch_tdep (current_gdbarch)->FPUL_REGNUM))
1465 return builtin_type_float;
8db62801 1466 else
cc17453a
EZ		 1467 return builtin_type_int;
1468}
1469
53116e27 1470static struct type *
fba45db2 1471sh_sh4_register_virtual_type (int reg_nr)
53116e27
EZ		 1472{
1473 if ((reg_nr >= FP0_REGNUM
e6c42fda 1474 && (reg_nr <= gdbarch_tdep (current_gdbarch)->FP_LAST_REGNUM))
53116e27
EZ		 1475 || (reg_nr == gdbarch_tdep (current_gdbarch)->FPUL_REGNUM))
1476 return builtin_type_float;
1477 else if (reg_nr >= gdbarch_tdep (current_gdbarch)->DR0_REGNUM
e6c42fda 1478 && reg_nr <= gdbarch_tdep (current_gdbarch)->DR_LAST_REGNUM)
53116e27
EZ		 1479 return builtin_type_double;
1480 else if (reg_nr >= gdbarch_tdep (current_gdbarch)->FV0_REGNUM
e6c42fda 1481 && reg_nr <= gdbarch_tdep (current_gdbarch)->FV_LAST_REGNUM)
53116e27
EZ		 1482 return sh_sh4_build_float_register_type (3);
1483 else
1484 return builtin_type_int;
1485}
1486
1487static struct type *
1488sh_sh4_build_float_register_type (int high)
1489{
1490 struct type *temp;
1491
1492 temp = create_range_type (NULL, builtin_type_int, 0, high);
1493 return create_array_type (NULL, builtin_type_float, temp);
1494}
1495
cc17453a 1496static struct type *
fba45db2 1497sh_default_register_virtual_type (int reg_nr)
cc17453a
EZ		 1498{
1499 return builtin_type_int;
1500}
1501
fb409745
EZ		 1502/* On the sh4, the DRi pseudo registers are problematic if the target
1503 is little endian. When the user writes one of those registers, for
1504 instance with 'ser var $dr0=1', we want the double to be stored
1505 like this:
1506 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
1507 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1508
1509 This corresponds to little endian byte order & big endian word
1510 order. However if we let gdb write the register w/o conversion, it
1511 will write fr0 and fr1 this way:
1512 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1513 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
1514 because it will consider fr0 and fr1 as a single LE stretch of memory.
1515
1516 To achieve what we want we must force gdb to store things in
1517 floatformat_ieee_double_littlebyte_bigword (which is defined in
1518 include/floatformat.h and libiberty/floatformat.c.
1519
1520 In case the target is big endian, there is no problem, the
1521 raw bytes will look like:
1522 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
1523 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1524
1525 The other pseudo registers (the FVs) also don't pose a problem
1526 because they are stored as 4 individual FP elements. */
1527
1528int
1529sh_sh4_register_convertible (int nr)
1530{
1531 if (TARGET_BYTE_ORDER == LITTLE_ENDIAN)
1532 return (gdbarch_tdep (current_gdbarch)->DR0_REGNUM <= nr
e6c42fda 1533 && nr <= gdbarch_tdep (current_gdbarch)->DR_LAST_REGNUM);
fb409745
EZ		 1534 else
1535 return 0;
1536}
1537
1538void
1539sh_sh4_register_convert_to_virtual (int regnum, struct type *type,
1540 char *from, char *to)
1541{
1542 if (regnum >= gdbarch_tdep (current_gdbarch)->DR0_REGNUM
e6c42fda 1543 && regnum <= gdbarch_tdep (current_gdbarch)->DR_LAST_REGNUM)
fb409745
EZ		 1544 {
1545 DOUBLEST val;
1546 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, from, &val);
1547 store_floating(to, TYPE_LENGTH(type), val);
1548 }
1549 else
1550 error("sh_register_convert_to_virtual called with non DR register number");
1551}
1552
1553void
1554sh_sh4_register_convert_to_raw (struct type *type, int regnum,
1555 char *from, char *to)
1556{
1557 if (regnum >= gdbarch_tdep (current_gdbarch)->DR0_REGNUM
e6c42fda 1558 && regnum <= gdbarch_tdep (current_gdbarch)->DR_LAST_REGNUM)
fb409745
EZ		 1559 {
1560 DOUBLEST val = extract_floating (from, TYPE_LENGTH(type));
1561 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword, &val, to);
1562 }
1563 else
1564 error("sh_register_convert_to_raw called with non DR register number");
1565}
1566
53116e27
EZ		 1567void
1568sh_fetch_pseudo_register (int reg_nr)
1569{
1570 int base_regnum, portion;
1571
1572 if (!register_cached (reg_nr))
1573 {
1574 if (reg_nr >= gdbarch_tdep (current_gdbarch)->DR0_REGNUM
e6c42fda 1575 && reg_nr <= gdbarch_tdep (current_gdbarch)->DR_LAST_REGNUM)
53116e27
EZ		 1576 {
1577 base_regnum = dr_reg_base_num (reg_nr);
1578
1579 /* Read the real regs for which this one is an alias. */
1580 for (portion = 0; portion < 2; portion++)
1581 if (!register_cached (base_regnum + portion))
1582 target_fetch_registers (base_regnum + portion);
1583 }
1584 else if (reg_nr >= gdbarch_tdep (current_gdbarch)->FV0_REGNUM
e6c42fda 1585 && reg_nr <= gdbarch_tdep (current_gdbarch)->FV_LAST_REGNUM)
53116e27
EZ		 1586 {
1587 base_regnum = fv_reg_base_num (reg_nr);
1588
1589 /* Read the real regs for which this one is an alias. */
1590 for (portion = 0; portion < 4; portion++)
1591 if (!register_cached (base_regnum + portion))
1592 target_fetch_registers (base_regnum + portion);
1593
1594 }
1595 register_valid [reg_nr] = 1;
1596 }
1597}
1598
1599void
1600sh_store_pseudo_register (int reg_nr)
1601{
1602 int base_regnum, portion;
1603
1604 if (reg_nr >= gdbarch_tdep (current_gdbarch)->DR0_REGNUM
e6c42fda 1605 && reg_nr <= gdbarch_tdep (current_gdbarch)->DR_LAST_REGNUM)
53116e27
EZ		 1606 {
1607 base_regnum = dr_reg_base_num (reg_nr);
1608
1609 /* Write the real regs for which this one is an alias. */
1610 for (portion = 0; portion < 2; portion++)
1611 {
1612 register_valid[base_regnum + portion] = 1;
1613 target_store_registers (base_regnum + portion);
1614 }
1615 }
1616 else if (reg_nr >= gdbarch_tdep (current_gdbarch)->FV0_REGNUM
e6c42fda 1617 && reg_nr <= gdbarch_tdep (current_gdbarch)->FV_LAST_REGNUM)
53116e27
EZ		 1618 {
1619 base_regnum = fv_reg_base_num (reg_nr);
1620
1621 /* Write the real regs for which this one is an alias. */
1622 for (portion = 0; portion < 4; portion++)
1623 {
1624 register_valid[base_regnum + portion] = 1;
1625 target_store_registers (base_regnum + portion);
1626 }
1627 }
1628}
1629
1630static int
1631fv_reg_base_num (int fv_regnum)
1632{
1633 int fp_regnum;
1634
1635 fp_regnum = FP0_REGNUM +
1636 (fv_regnum - gdbarch_tdep (current_gdbarch)->FV0_REGNUM) * 4;
1637 return fp_regnum;
1638}
1639
1640static int
1641dr_reg_base_num (int dr_regnum)
1642{
1643 int fp_regnum;
1644
1645 fp_regnum = FP0_REGNUM +
1646 (dr_regnum - gdbarch_tdep (current_gdbarch)->DR0_REGNUM) * 2;
1647 return fp_regnum;
1648}
1649
1650static void
1651do_fv_register_info (int fv_regnum)
1652{
1653 int first_fp_reg_num = fv_reg_base_num (fv_regnum);
1654 printf_filtered ("fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
1655 fv_regnum - gdbarch_tdep (current_gdbarch)->FV0_REGNUM,
1656 (int) read_register (first_fp_reg_num),
1657 (int) read_register (first_fp_reg_num + 1),
1658 (int) read_register (first_fp_reg_num + 2),
1659 (int) read_register (first_fp_reg_num + 3));
1660}
1661
1662static void
1663do_dr_register_info (int dr_regnum)
1664{
1665 int first_fp_reg_num = dr_reg_base_num (dr_regnum);
1666
1667 printf_filtered ("dr%d\t0x%08x%08x\n",
1668 dr_regnum - gdbarch_tdep (current_gdbarch)->DR0_REGNUM,
1669 (int) read_register (first_fp_reg_num),
1670 (int) read_register (first_fp_reg_num + 1));
1671}
1672
1673static void
1674sh_do_pseudo_register (int regnum)
1675{
1676 if (regnum < NUM_REGS || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
8e1a459b 1677 internal_error ("Invalid pseudo register number %d\n", regnum);
a38d2a54
EZ		 1678 else if (regnum >= gdbarch_tdep (current_gdbarch)->DR0_REGNUM
1679 && regnum < gdbarch_tdep (current_gdbarch)->DR_LAST_REGNUM)
53116e27 1680 do_dr_register_info (regnum);
a38d2a54
EZ		 1681 else if (regnum >= gdbarch_tdep (current_gdbarch)->FV0_REGNUM
1682 && regnum <= gdbarch_tdep (current_gdbarch)->FV_LAST_REGNUM)
53116e27
EZ		 1683 do_fv_register_info (regnum);
1684}
1685
1686
1687static void
1688sh_do_fp_register (int regnum)
1689{ /* do values for FP (float) regs */
1690 char *raw_buffer;
1691 double flt; /* double extracted from raw hex data */
1692 int inv;
1693 int j;
1694
1695 /* Allocate space for the float. */
1696 raw_buffer = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM));
1697
1698 /* Get the data in raw format. */
1699 if (read_relative_register_raw_bytes (regnum, raw_buffer))
1700 error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
1701
1702 /* Get the register as a number */
1703 flt = unpack_double (builtin_type_float, raw_buffer, &inv);
1704
1705 /* Print the name and some spaces. */
1706 fputs_filtered (REGISTER_NAME (regnum), gdb_stdout);
1707 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), gdb_stdout);
1708
1709 /* Print the value. */
1710 printf_filtered (inv ? "<invalid float>" : "%-10.9g", flt);
1711
1712 /* Print the fp register as hex. */
1713 printf_filtered ("\t(raw 0x");
1714 for (j = 0; j < REGISTER_RAW_SIZE (regnum); j++)
1715 {
1716 register int idx = TARGET_BYTE_ORDER == BIG_ENDIAN ? j
1717 : REGISTER_RAW_SIZE (regnum) - 1 - j;
1718 printf_filtered ("%02x", (unsigned char) raw_buffer[idx]);
1719 }
1720 printf_filtered (")");
1721 printf_filtered ("\n");
1722}
1723
1724static void
1725sh_do_register (int regnum)
1726{
1727 char raw_buffer[MAX_REGISTER_RAW_SIZE];
1728
1729 fputs_filtered (REGISTER_NAME (regnum), gdb_stdout);
1730 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), gdb_stdout);
1731
1732 /* Get the data in raw format. */
1733 if (read_relative_register_raw_bytes (regnum, raw_buffer))
1734 printf_filtered ("*value not available*\n");
1735
1736 val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, 0,
1737 gdb_stdout, 'x', 1, 0, Val_pretty_default);
1738 printf_filtered ("\t");
1739 val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, 0,
1740 gdb_stdout, 0, 1, 0, Val_pretty_default);
1741 printf_filtered ("\n");
1742}
1743
1744static void
1745sh_print_register (int regnum)
1746{
1747 if (regnum < 0 || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
1748 internal_error ("Invalid register number %d\n", regnum);
1749
e30839fe 1750 else if (regnum >= 0 && regnum < NUM_REGS)
53116e27
EZ		 1751 {
1752 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
1753 sh_do_fp_register (regnum); /* FP regs */
1754 else
1755 sh_do_register (regnum); /* All other regs */
1756 }
1757
1758 else if (regnum < NUM_REGS + NUM_PSEUDO_REGS)
1759 sh_do_pseudo_register (regnum);
1760}
1761
1762void
1763sh_do_registers_info (int regnum, int fpregs)
1764{
1765 if (regnum != -1) /* do one specified register */
1766 {
1767 if (*(REGISTER_NAME (regnum)) == '\0')
1768 error ("Not a valid register for the current processor type");
1769
1770 sh_print_register (regnum);
1771 }
1772 else
1773 /* do all (or most) registers */
1774 {
1775 regnum = 0;
1776 while (regnum < NUM_REGS)
1777 {
1778 /* If the register name is empty, it is undefined for this
1779 processor, so don't display anything. */
1780 if (REGISTER_NAME (regnum) == NULL
1781 || *(REGISTER_NAME (regnum)) == '\0')
1782 {
1783 regnum++;
1784 continue;
1785 }
1786
1787 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
1788 {
1789 if (fpregs)
1790 {
1791 /* true for "INFO ALL-REGISTERS" command */
1792 sh_do_fp_register (regnum); /* FP regs */
1793 regnum ++;
1794 }
1795 else
e6c42fda 1796 regnum += (gdbarch_tdep (current_gdbarch)->FP_LAST_REGNUM - FP0_REGNUM); /* skip FP regs */
53116e27
EZ		 1797 }
1798 else
1799 {
1800 sh_do_register (regnum); /* All other regs */
1801 regnum++;
1802 }
1803 }
1804
1805 if (fpregs)
1806 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
1807 {
1808 sh_do_pseudo_register (regnum);
1809 regnum++;
1810 }
1811 }
1812}
1813
1a8629c7
MS		 1814#ifdef SVR4_SHARED_LIBS
1815
1816/* Fetch (and possibly build) an appropriate link_map_offsets structure
1817 for native i386 linux targets using the struct offsets defined in
1818 link.h (but without actual reference to that file).
1819
1820 This makes it possible to access i386-linux shared libraries from
1821 a gdb that was not built on an i386-linux host (for cross debugging).
1822 */
1823
1824struct link_map_offsets *
1825sh_linux_svr4_fetch_link_map_offsets (void)
1826{
1827 static struct link_map_offsets lmo;
1828 static struct link_map_offsets *lmp = 0;
1829
1830 if (lmp == 0)
1831 {
1832 lmp = &lmo;
1833
1834 lmo.r_debug_size = 8; /* 20 not actual size but all we need */
1835
1836 lmo.r_map_offset = 4;
1837 lmo.r_map_size = 4;
1838
1839 lmo.link_map_size = 20; /* 552 not actual size but all we need */
1840
1841 lmo.l_addr_offset = 0;
1842 lmo.l_addr_size = 4;
1843
1844 lmo.l_name_offset = 4;
1845 lmo.l_name_size = 4;
1846
1847 lmo.l_next_offset = 12;
1848 lmo.l_next_size = 4;
1849
1850 lmo.l_prev_offset = 16;
1851 lmo.l_prev_size = 4;
1852 }
1853
1854 return lmp;
1855}
1856#endif /* SVR4_SHARED_LIBS */
1857
cc17453a
EZ		 1858static gdbarch_init_ftype sh_gdbarch_init;
1859
1860static struct gdbarch *
fba45db2 1861sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
cc17453a
EZ		 1862{
1863 static LONGEST sh_call_dummy_words[] = {0};
1864 struct gdbarch *gdbarch;
1865 struct gdbarch_tdep *tdep;
1866 gdbarch_register_name_ftype *sh_register_name;
1867 gdbarch_store_return_value_ftype *sh_store_return_value;
1868 gdbarch_register_virtual_type_ftype *sh_register_virtual_type;
1869
1870 /* Find a candidate among the list of pre-declared architectures. */
1871 arches = gdbarch_list_lookup_by_info (arches, &info);
1872 if (arches != NULL)
1873 return arches->gdbarch;
1874
1875 /* None found, create a new architecture from the information
1876 provided. */
1877 tdep = XMALLOC (struct gdbarch_tdep);
1878 gdbarch = gdbarch_alloc (&info, tdep);
1879
1880 /* Initialize the register numbers that are not common to all the
1881 variants to -1, if necessary thse will be overwritten in the case
1882 statement below. */
1883 tdep->FPUL_REGNUM = -1;
1884 tdep->FPSCR_REGNUM = -1;
c62a7c7b 1885 tdep->SR_REGNUM = 22;
cc17453a 1886 tdep->DSR_REGNUM = -1;
e6c42fda 1887 tdep->FP_LAST_REGNUM = -1;
cc17453a
EZ		 1888 tdep->A0G_REGNUM = -1;
1889 tdep->A0_REGNUM = -1;
1890 tdep->A1G_REGNUM = -1;
1891 tdep->A1_REGNUM = -1;
1892 tdep->M0_REGNUM = -1;
1893 tdep->M1_REGNUM = -1;
1894 tdep->X0_REGNUM = -1;
1895 tdep->X1_REGNUM = -1;
1896 tdep->Y0_REGNUM = -1;
1897 tdep->Y1_REGNUM = -1;
1898 tdep->MOD_REGNUM = -1;
1899 tdep->RS_REGNUM = -1;
1900 tdep->RE_REGNUM = -1;
1901 tdep->SSR_REGNUM = -1;
1902 tdep->SPC_REGNUM = -1;
53116e27 1903 tdep->DR0_REGNUM = -1;
e6c42fda 1904 tdep->DR_LAST_REGNUM = -1;
53116e27 1905 tdep->FV0_REGNUM = -1;
e6c42fda 1906 tdep->FV_LAST_REGNUM = -1;
a38d2a54 1907
cc17453a 1908 set_gdbarch_fp0_regnum (gdbarch, -1);
53116e27
EZ		 1909 set_gdbarch_num_pseudo_regs (gdbarch, 0);
1910 set_gdbarch_max_register_raw_size (gdbarch, 4);
1911 set_gdbarch_max_register_virtual_size (gdbarch, 4);
a38d2a54
EZ		 1912 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1913 set_gdbarch_num_regs (gdbarch, 59);
1914 set_gdbarch_sp_regnum (gdbarch, 15);
1915 set_gdbarch_fp_regnum (gdbarch, 14);
1916 set_gdbarch_pc_regnum (gdbarch, 16);
1917 set_gdbarch_register_size (gdbarch, 4);
1918 set_gdbarch_register_bytes (gdbarch, NUM_REGS * 4);
1919 set_gdbarch_fetch_pseudo_register (gdbarch, sh_fetch_pseudo_register);
1920 set_gdbarch_store_pseudo_register (gdbarch, sh_store_pseudo_register);
c5f7d19c 1921 set_gdbarch_do_registers_info (gdbarch, sh_do_registers_info);
eaf90c5d 1922 set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc);
e6c42fda 1923 print_sh_insn = gdb_print_insn_sh;
cc17453a
EZ		 1924
1925 switch (info.bfd_arch_info->mach)
8db62801 1926 {
cc17453a
EZ		 1927 case bfd_mach_sh:
1928 sh_register_name = sh_sh_register_name;
1929 sh_show_regs = sh_generic_show_regs;
1930 sh_store_return_value = sh_default_store_return_value;
1931 sh_register_virtual_type = sh_default_register_virtual_type;
1932 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 1933 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
1934 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
1935 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a
EZ		 1936 break;
1937 case bfd_mach_sh2:
1938 sh_register_name = sh_sh_register_name;
1939 sh_show_regs = sh_generic_show_regs;
1940 sh_store_return_value = sh_default_store_return_value;
1941 sh_register_virtual_type = sh_default_register_virtual_type;
1942 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 1943 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
1944 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
1945 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a
EZ		 1946 break;
1947 case bfd_mach_sh_dsp:
1948 sh_register_name = sh_sh_dsp_register_name;
1949 sh_show_regs = sh_dsp_show_regs;
1950 sh_store_return_value = sh_default_store_return_value;
1951 sh_register_virtual_type = sh_default_register_virtual_type;
1952 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 1953 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
1954 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
1955 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a
EZ		 1956 tdep->DSR_REGNUM = 24;
1957 tdep->A0G_REGNUM = 25;
1958 tdep->A0_REGNUM = 26;
1959 tdep->A1G_REGNUM = 27;
1960 tdep->A1_REGNUM = 28;
1961 tdep->M0_REGNUM = 29;
1962 tdep->M1_REGNUM = 30;
1963 tdep->X0_REGNUM = 31;
1964 tdep->X1_REGNUM = 32;
1965 tdep->Y0_REGNUM = 33;
1966 tdep->Y1_REGNUM = 34;
1967 tdep->MOD_REGNUM = 40;
1968 tdep->RS_REGNUM = 43;
1969 tdep->RE_REGNUM = 44;
1970 break;
1971 case bfd_mach_sh3:
1972 sh_register_name = sh_sh3_register_name;
1973 sh_show_regs = sh3_show_regs;
1974 sh_store_return_value = sh_default_store_return_value;
1975 sh_register_virtual_type = sh_default_register_virtual_type;
1976 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 1977 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
1978 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
1979 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a
EZ		 1980 tdep->SSR_REGNUM = 41;
1981 tdep->SPC_REGNUM = 42;
1982 break;
1983 case bfd_mach_sh3e:
1984 sh_register_name = sh_sh3e_register_name;
1985 sh_show_regs = sh3e_show_regs;
1986 sh_store_return_value = sh3e_sh4_store_return_value;
1987 sh_register_virtual_type = sh_sh3e_register_virtual_type;
1988 set_gdbarch_frame_init_saved_regs (gdbarch, sh_fp_frame_init_saved_regs);
53116e27
EZ		 1989 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
1990 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
1991 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a
EZ		 1992 set_gdbarch_fp0_regnum (gdbarch, 25);
1993 tdep->FPUL_REGNUM = 23;
1994 tdep->FPSCR_REGNUM = 24;
e6c42fda 1995 tdep->FP_LAST_REGNUM = 40;
cc17453a
EZ		 1996 tdep->SSR_REGNUM = 41;
1997 tdep->SPC_REGNUM = 42;
1998 break;
1999 case bfd_mach_sh3_dsp:
2000 sh_register_name = sh_sh3_dsp_register_name;
2001 sh_show_regs = sh3_dsp_show_regs;
2002 sh_store_return_value = sh_default_store_return_value;
2003 sh_register_virtual_type = sh_default_register_virtual_type;
2004 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 2005 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
2006 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
2007 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a
EZ		 2008 tdep->DSR_REGNUM = 24;
2009 tdep->A0G_REGNUM = 25;
2010 tdep->A0_REGNUM = 26;
2011 tdep->A1G_REGNUM = 27;
2012 tdep->A1_REGNUM = 28;
2013 tdep->M0_REGNUM = 29;
2014 tdep->M1_REGNUM = 30;
2015 tdep->X0_REGNUM = 31;
2016 tdep->X1_REGNUM = 32;
2017 tdep->Y0_REGNUM = 33;
2018 tdep->Y1_REGNUM = 34;
2019 tdep->MOD_REGNUM = 40;
2020 tdep->RS_REGNUM = 43;
2021 tdep->RE_REGNUM = 44;
2022 tdep->SSR_REGNUM = 41;
2023 tdep->SPC_REGNUM = 42;
2024 break;
2025 case bfd_mach_sh4:
53116e27
EZ		 2026 sh_register_name = sh_sh4_register_name;
2027 sh_show_regs = sh4_show_regs;
cc17453a 2028 sh_store_return_value = sh3e_sh4_store_return_value;
53116e27 2029 sh_register_virtual_type = sh_sh4_register_virtual_type;
cc17453a
EZ		 2030 set_gdbarch_frame_init_saved_regs (gdbarch, sh_fp_frame_init_saved_regs);
2031 set_gdbarch_fp0_regnum (gdbarch, 25);
53116e27
EZ		 2032 set_gdbarch_register_raw_size (gdbarch, sh_sh4_register_raw_size);
2033 set_gdbarch_register_virtual_size (gdbarch, sh_sh4_register_raw_size);
2034 set_gdbarch_register_byte (gdbarch, sh_sh4_register_byte);
2035 set_gdbarch_num_pseudo_regs (gdbarch, 12);
2036 set_gdbarch_max_register_raw_size (gdbarch, 4 * 4);
2037 set_gdbarch_max_register_virtual_size (gdbarch, 4 * 4);
fb409745
EZ		 2038 set_gdbarch_register_convert_to_raw (gdbarch, sh_sh4_register_convert_to_raw);
2039 set_gdbarch_register_convert_to_virtual (gdbarch, sh_sh4_register_convert_to_virtual);
2040 set_gdbarch_register_convertible (gdbarch, sh_sh4_register_convertible);
cc17453a
EZ		 2041 tdep->FPUL_REGNUM = 23;
2042 tdep->FPSCR_REGNUM = 24;
e6c42fda 2043 tdep->FP_LAST_REGNUM = 40;
cc17453a
EZ		 2044 tdep->SSR_REGNUM = 41;
2045 tdep->SPC_REGNUM = 42;
53116e27 2046 tdep->DR0_REGNUM = 59;
e6c42fda 2047 tdep->DR_LAST_REGNUM = 66;
53116e27 2048 tdep->FV0_REGNUM = 67;
e6c42fda 2049 tdep->FV_LAST_REGNUM = 70;
cc17453a
EZ		 2050 break;
2051 default:
2052 sh_register_name = sh_generic_register_name;
2053 sh_show_regs = sh_generic_show_regs;
2054 sh_store_return_value = sh_default_store_return_value;
2055 sh_register_virtual_type = sh_default_register_virtual_type;
2056 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
53116e27
EZ		 2057 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
2058 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
2059 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
cc17453a 2060 break;
8db62801 2061 }
cc17453a
EZ		 2062
2063 set_gdbarch_read_pc (gdbarch, generic_target_read_pc);
2064 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
2065 set_gdbarch_read_fp (gdbarch, generic_target_read_fp);
2066 set_gdbarch_write_fp (gdbarch, generic_target_write_fp);
2067 set_gdbarch_read_sp (gdbarch, generic_target_read_sp);
2068 set_gdbarch_write_sp (gdbarch, generic_target_write_sp);
2069
cc17453a 2070 set_gdbarch_register_name (gdbarch, sh_register_name);
cc17453a
EZ		 2071 set_gdbarch_register_virtual_type (gdbarch, sh_register_virtual_type);
2072
cc17453a
EZ		 2073 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2074 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2075 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2076 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2077 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2078 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
a38d2a54 2079 set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT);/*??should be 8?*/
cc17453a
EZ		 2080
2081 set_gdbarch_use_generic_dummy_frames (gdbarch, 1);
2082 set_gdbarch_call_dummy_length (gdbarch, 0);
2083 set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT);
2084 set_gdbarch_call_dummy_address (gdbarch, entry_point_address);
2085 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1); /*???*/
2086 set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0);
2087 set_gdbarch_call_dummy_start_offset (gdbarch, 0);
2088 set_gdbarch_pc_in_call_dummy (gdbarch, generic_pc_in_call_dummy);
2089 set_gdbarch_call_dummy_words (gdbarch, sh_call_dummy_words);
2090 set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (sh_call_dummy_words));
2091 set_gdbarch_call_dummy_p (gdbarch, 1);
2092 set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0);
2093 set_gdbarch_get_saved_register (gdbarch, generic_get_saved_register);
2094 set_gdbarch_fix_call_dummy (gdbarch, generic_fix_call_dummy);
2095 set_gdbarch_coerce_float_to_double (gdbarch,
2096 sh_coerce_float_to_double);
2097
2098 set_gdbarch_extract_return_value (gdbarch, sh_extract_return_value);
2099 set_gdbarch_push_arguments (gdbarch, sh_push_arguments);
2100 set_gdbarch_push_dummy_frame (gdbarch, generic_push_dummy_frame);
2101 set_gdbarch_push_return_address (gdbarch, sh_push_return_address);
2102
2103 set_gdbarch_store_struct_return (gdbarch, sh_store_struct_return);
2104 set_gdbarch_store_return_value (gdbarch, sh_store_return_value);
2105 set_gdbarch_extract_struct_value_address (gdbarch, sh_extract_struct_value_address);
2106 set_gdbarch_use_struct_convention (gdbarch, sh_use_struct_convention);
2107 set_gdbarch_init_extra_frame_info (gdbarch, sh_init_extra_frame_info);
2108 set_gdbarch_pop_frame (gdbarch, sh_pop_frame);
2109 set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
2110 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2111 set_gdbarch_decr_pc_after_break (gdbarch, 0);
2112 set_gdbarch_function_start_offset (gdbarch, 0);
cc17453a
EZ		 2113
2114 set_gdbarch_frame_args_skip (gdbarch, 0);
2115 set_gdbarch_frameless_function_invocation (gdbarch, frameless_look_for_prologue);
2116 set_gdbarch_frame_chain (gdbarch, sh_frame_chain);
2117 set_gdbarch_frame_chain_valid (gdbarch, generic_file_frame_chain_valid);
2118 set_gdbarch_frame_saved_pc (gdbarch, sh_frame_saved_pc);
2119 set_gdbarch_frame_args_address (gdbarch, sh_frame_args_address);
2120 set_gdbarch_frame_locals_address (gdbarch, sh_frame_locals_address);
2121 set_gdbarch_saved_pc_after_call (gdbarch, sh_saved_pc_after_call);
2122 set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown);
2123 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2124 set_gdbarch_ieee_float (gdbarch, 1);
a38d2a54 2125 tm_print_insn = print_sh_insn;
cc17453a
EZ		 2126
2127 return gdbarch;
8db62801
EZ		 2128}
2129
c906108c 2130void
fba45db2 2131_initialize_sh_tdep (void)
c906108c
SS		 2132{
2133 struct cmd_list_element *c;
cc17453a
EZ		 2134
2135 register_gdbarch_init (bfd_arch_sh, sh_gdbarch_init);
c906108c 2136
53116e27 2137 add_com ("regs", class_vars, sh_show_regs_command, "Print all registers");
c906108c 2138}
GDB Binutils - Deliverables
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