Commit | Line | Data |
---|---|---|
85a453d5 | 1 | /* Target-dependent code for Renesas Super-H, for GDB. |
0fd88904 | 2 | |
e2882c85 | 3 | Copyright (C) 1993-2018 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 10 | (at your option) any later version. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b | 17 | You should have received a copy of the GNU General Public License |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c | 19 | |
c378eb4e MS |
20 | /* Contributed by Steve Chamberlain |
21 | sac@cygnus.com. */ | |
c906108c SS |
22 | |
23 | #include "defs.h" | |
24 | #include "frame.h" | |
1c0159e0 CV |
25 | #include "frame-base.h" |
26 | #include "frame-unwind.h" | |
27 | #include "dwarf2-frame.h" | |
c906108c | 28 | #include "symtab.h" |
c906108c SS |
29 | #include "gdbtypes.h" |
30 | #include "gdbcmd.h" | |
31 | #include "gdbcore.h" | |
32 | #include "value.h" | |
33 | #include "dis-asm.h" | |
73c1f219 | 34 | #include "inferior.h" |
b4a20239 | 35 | #include "arch-utils.h" |
4e052eda | 36 | #include "regcache.h" |
3b2ca824 | 37 | #include "target-float.h" |
4be87837 | 38 | #include "osabi.h" |
dda63807 | 39 | #include "reggroups.h" |
c9ac0a72 | 40 | #include "regset.h" |
cb2cf4ce | 41 | #include "objfiles.h" |
c906108c | 42 | |
ab3b8126 | 43 | #include "sh-tdep.h" |
04dcf5fa | 44 | #include "sh64-tdep.h" |
ab3b8126 | 45 | |
d658f924 | 46 | #include "elf-bfd.h" |
1a8629c7 MS |
47 | #include "solib-svr4.h" |
48 | ||
55ff77ac | 49 | /* sh flags */ |
283150cd | 50 | #include "elf/sh.h" |
fa8f86ff | 51 | #include "dwarf2.h" |
c378eb4e | 52 | /* registers numbers shared with the simulator. */ |
1c922164 | 53 | #include "gdb/sim-sh.h" |
325fac50 | 54 | #include <algorithm> |
283150cd | 55 | |
c055b101 CV |
56 | /* List of "set sh ..." and "show sh ..." commands. */ |
57 | static struct cmd_list_element *setshcmdlist = NULL; | |
58 | static struct cmd_list_element *showshcmdlist = NULL; | |
59 | ||
60 | static const char sh_cc_gcc[] = "gcc"; | |
61 | static const char sh_cc_renesas[] = "renesas"; | |
40478521 | 62 | static const char *const sh_cc_enum[] = { |
c055b101 CV |
63 | sh_cc_gcc, |
64 | sh_cc_renesas, | |
65 | NULL | |
66 | }; | |
67 | ||
68 | static const char *sh_active_calling_convention = sh_cc_gcc; | |
69 | ||
da962468 | 70 | #define SH_NUM_REGS 67 |
88e04cc1 | 71 | |
1c0159e0 | 72 | struct sh_frame_cache |
cc17453a | 73 | { |
1c0159e0 CV |
74 | /* Base address. */ |
75 | CORE_ADDR base; | |
76 | LONGEST sp_offset; | |
77 | CORE_ADDR pc; | |
78 | ||
c378eb4e | 79 | /* Flag showing that a frame has been created in the prologue code. */ |
1c0159e0 CV |
80 | int uses_fp; |
81 | ||
82 | /* Saved registers. */ | |
83 | CORE_ADDR saved_regs[SH_NUM_REGS]; | |
84 | CORE_ADDR saved_sp; | |
63978407 | 85 | }; |
c906108c | 86 | |
c055b101 CV |
87 | static int |
88 | sh_is_renesas_calling_convention (struct type *func_type) | |
89 | { | |
ca193e27 TS |
90 | int val = 0; |
91 | ||
92 | if (func_type) | |
93 | { | |
94 | func_type = check_typedef (func_type); | |
95 | ||
96 | if (TYPE_CODE (func_type) == TYPE_CODE_PTR) | |
97 | func_type = check_typedef (TYPE_TARGET_TYPE (func_type)); | |
98 | ||
99 | if (TYPE_CODE (func_type) == TYPE_CODE_FUNC | |
100 | && TYPE_CALLING_CONVENTION (func_type) == DW_CC_GNU_renesas_sh) | |
101 | val = 1; | |
102 | } | |
103 | ||
104 | if (sh_active_calling_convention == sh_cc_renesas) | |
105 | val = 1; | |
106 | ||
107 | return val; | |
c055b101 CV |
108 | } |
109 | ||
fa88f677 | 110 | static const char * |
d93859e2 | 111 | sh_sh_register_name (struct gdbarch *gdbarch, int reg_nr) |
cc17453a | 112 | { |
a121b7c1 | 113 | static const char *register_names[] = { |
617daa0e CV |
114 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
115 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
116 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
117 | "", "", | |
118 | "", "", "", "", "", "", "", "", | |
119 | "", "", "", "", "", "", "", "", | |
120 | "", "", | |
121 | "", "", "", "", "", "", "", "", | |
122 | "", "", "", "", "", "", "", "", | |
da962468 | 123 | "", "", "", "", "", "", "", "", |
cc17453a EZ |
124 | }; |
125 | if (reg_nr < 0) | |
126 | return NULL; | |
127 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
128 | return NULL; | |
129 | return register_names[reg_nr]; | |
130 | } | |
131 | ||
fa88f677 | 132 | static const char * |
d93859e2 | 133 | sh_sh3_register_name (struct gdbarch *gdbarch, int reg_nr) |
cc17453a | 134 | { |
a121b7c1 | 135 | static const char *register_names[] = { |
617daa0e CV |
136 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
137 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
138 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
139 | "", "", | |
140 | "", "", "", "", "", "", "", "", | |
141 | "", "", "", "", "", "", "", "", | |
142 | "ssr", "spc", | |
cc17453a EZ |
143 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", |
144 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1" | |
da962468 | 145 | "", "", "", "", "", "", "", "", |
cc17453a EZ |
146 | }; |
147 | if (reg_nr < 0) | |
148 | return NULL; | |
149 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
150 | return NULL; | |
151 | return register_names[reg_nr]; | |
152 | } | |
153 | ||
fa88f677 | 154 | static const char * |
d93859e2 | 155 | sh_sh3e_register_name (struct gdbarch *gdbarch, int reg_nr) |
cc17453a | 156 | { |
a121b7c1 | 157 | static const char *register_names[] = { |
617daa0e CV |
158 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
159 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
160 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
cc17453a | 161 | "fpul", "fpscr", |
617daa0e CV |
162 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", |
163 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
164 | "ssr", "spc", | |
cc17453a EZ |
165 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", |
166 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", | |
da962468 | 167 | "", "", "", "", "", "", "", "", |
cc17453a EZ |
168 | }; |
169 | if (reg_nr < 0) | |
170 | return NULL; | |
171 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
172 | return NULL; | |
173 | return register_names[reg_nr]; | |
174 | } | |
175 | ||
2d188dd3 | 176 | static const char * |
d93859e2 | 177 | sh_sh2e_register_name (struct gdbarch *gdbarch, int reg_nr) |
2d188dd3 | 178 | { |
a121b7c1 | 179 | static const char *register_names[] = { |
617daa0e CV |
180 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
181 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
182 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
2d188dd3 | 183 | "fpul", "fpscr", |
617daa0e CV |
184 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", |
185 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
186 | "", "", | |
2d188dd3 NC |
187 | "", "", "", "", "", "", "", "", |
188 | "", "", "", "", "", "", "", "", | |
da962468 CV |
189 | "", "", "", "", "", "", "", "", |
190 | }; | |
191 | if (reg_nr < 0) | |
192 | return NULL; | |
193 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
194 | return NULL; | |
195 | return register_names[reg_nr]; | |
196 | } | |
197 | ||
198 | static const char * | |
d93859e2 | 199 | sh_sh2a_register_name (struct gdbarch *gdbarch, int reg_nr) |
da962468 | 200 | { |
a121b7c1 | 201 | static const char *register_names[] = { |
da962468 CV |
202 | /* general registers 0-15 */ |
203 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
204 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
205 | /* 16 - 22 */ | |
206 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
207 | /* 23, 24 */ | |
208 | "fpul", "fpscr", | |
209 | /* floating point registers 25 - 40 */ | |
210 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", | |
211 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
212 | /* 41, 42 */ | |
213 | "", "", | |
214 | /* 43 - 62. Banked registers. The bank number used is determined by | |
c378eb4e | 215 | the bank register (63). */ |
da962468 CV |
216 | "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b", |
217 | "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", | |
218 | "machb", "ivnb", "prb", "gbrb", "maclb", | |
219 | /* 63: register bank number, not a real register but used to | |
220 | communicate the register bank currently get/set. This register | |
221 | is hidden to the user, who manipulates it using the pseudo | |
222 | register called "bank" (67). See below. */ | |
223 | "", | |
224 | /* 64 - 66 */ | |
225 | "ibcr", "ibnr", "tbr", | |
226 | /* 67: register bank number, the user visible pseudo register. */ | |
227 | "bank", | |
228 | /* double precision (pseudo) 68 - 75 */ | |
229 | "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", | |
230 | }; | |
231 | if (reg_nr < 0) | |
232 | return NULL; | |
233 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
234 | return NULL; | |
235 | return register_names[reg_nr]; | |
236 | } | |
237 | ||
238 | static const char * | |
d93859e2 | 239 | sh_sh2a_nofpu_register_name (struct gdbarch *gdbarch, int reg_nr) |
da962468 | 240 | { |
a121b7c1 | 241 | static const char *register_names[] = { |
da962468 CV |
242 | /* general registers 0-15 */ |
243 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
244 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
245 | /* 16 - 22 */ | |
246 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
247 | /* 23, 24 */ | |
248 | "", "", | |
249 | /* floating point registers 25 - 40 */ | |
250 | "", "", "", "", "", "", "", "", | |
251 | "", "", "", "", "", "", "", "", | |
252 | /* 41, 42 */ | |
253 | "", "", | |
254 | /* 43 - 62. Banked registers. The bank number used is determined by | |
c378eb4e | 255 | the bank register (63). */ |
da962468 CV |
256 | "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b", |
257 | "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", | |
258 | "machb", "ivnb", "prb", "gbrb", "maclb", | |
259 | /* 63: register bank number, not a real register but used to | |
260 | communicate the register bank currently get/set. This register | |
261 | is hidden to the user, who manipulates it using the pseudo | |
262 | register called "bank" (67). See below. */ | |
263 | "", | |
264 | /* 64 - 66 */ | |
265 | "ibcr", "ibnr", "tbr", | |
266 | /* 67: register bank number, the user visible pseudo register. */ | |
267 | "bank", | |
268 | /* double precision (pseudo) 68 - 75 */ | |
269 | "", "", "", "", "", "", "", "", | |
2d188dd3 NC |
270 | }; |
271 | if (reg_nr < 0) | |
272 | return NULL; | |
273 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
274 | return NULL; | |
275 | return register_names[reg_nr]; | |
276 | } | |
277 | ||
fa88f677 | 278 | static const char * |
d93859e2 | 279 | sh_sh_dsp_register_name (struct gdbarch *gdbarch, int reg_nr) |
cc17453a | 280 | { |
a121b7c1 | 281 | static const char *register_names[] = { |
617daa0e CV |
282 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
283 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
284 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
285 | "", "dsr", | |
286 | "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1", | |
287 | "y0", "y1", "", "", "", "", "", "mod", | |
288 | "", "", | |
289 | "rs", "re", "", "", "", "", "", "", | |
290 | "", "", "", "", "", "", "", "", | |
da962468 | 291 | "", "", "", "", "", "", "", "", |
cc17453a EZ |
292 | }; |
293 | if (reg_nr < 0) | |
294 | return NULL; | |
295 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
296 | return NULL; | |
297 | return register_names[reg_nr]; | |
298 | } | |
299 | ||
fa88f677 | 300 | static const char * |
d93859e2 | 301 | sh_sh3_dsp_register_name (struct gdbarch *gdbarch, int reg_nr) |
cc17453a | 302 | { |
a121b7c1 | 303 | static const char *register_names[] = { |
617daa0e CV |
304 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
305 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
306 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
307 | "", "dsr", | |
308 | "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1", | |
309 | "y0", "y1", "", "", "", "", "", "mod", | |
310 | "ssr", "spc", | |
311 | "rs", "re", "", "", "", "", "", "", | |
026a72f8 CV |
312 | "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b", |
313 | "", "", "", "", "", "", "", "", | |
da962468 | 314 | "", "", "", "", "", "", "", "", |
cc17453a EZ |
315 | }; |
316 | if (reg_nr < 0) | |
317 | return NULL; | |
318 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
319 | return NULL; | |
320 | return register_names[reg_nr]; | |
321 | } | |
322 | ||
fa88f677 | 323 | static const char * |
d93859e2 | 324 | sh_sh4_register_name (struct gdbarch *gdbarch, int reg_nr) |
53116e27 | 325 | { |
a121b7c1 | 326 | static const char *register_names[] = { |
a38d2a54 | 327 | /* general registers 0-15 */ |
617daa0e CV |
328 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
329 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
a38d2a54 | 330 | /* 16 - 22 */ |
617daa0e | 331 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", |
a38d2a54 | 332 | /* 23, 24 */ |
53116e27 | 333 | "fpul", "fpscr", |
a38d2a54 | 334 | /* floating point registers 25 - 40 */ |
617daa0e CV |
335 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", |
336 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
a38d2a54 | 337 | /* 41, 42 */ |
617daa0e | 338 | "ssr", "spc", |
a38d2a54 | 339 | /* bank 0 43 - 50 */ |
53116e27 | 340 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", |
a38d2a54 | 341 | /* bank 1 51 - 58 */ |
53116e27 | 342 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", |
a6521d9a | 343 | /* 59 - 66 */ |
da962468 | 344 | "", "", "", "", "", "", "", "", |
c378eb4e | 345 | /* pseudo bank register. */ |
da962468 | 346 | "", |
a6521d9a | 347 | /* double precision (pseudo) 68 - 75 */ |
617daa0e | 348 | "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", |
a6521d9a | 349 | /* vectors (pseudo) 76 - 79 */ |
617daa0e | 350 | "fv0", "fv4", "fv8", "fv12", |
a6521d9a TS |
351 | /* FIXME: missing XF */ |
352 | /* FIXME: missing XD */ | |
53116e27 EZ |
353 | }; |
354 | if (reg_nr < 0) | |
355 | return NULL; | |
356 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
357 | return NULL; | |
358 | return register_names[reg_nr]; | |
359 | } | |
360 | ||
474e5826 | 361 | static const char * |
d93859e2 | 362 | sh_sh4_nofpu_register_name (struct gdbarch *gdbarch, int reg_nr) |
474e5826 | 363 | { |
a121b7c1 | 364 | static const char *register_names[] = { |
474e5826 CV |
365 | /* general registers 0-15 */ |
366 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
367 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
368 | /* 16 - 22 */ | |
369 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
370 | /* 23, 24 */ | |
371 | "", "", | |
372 | /* floating point registers 25 - 40 -- not for nofpu target */ | |
373 | "", "", "", "", "", "", "", "", | |
374 | "", "", "", "", "", "", "", "", | |
375 | /* 41, 42 */ | |
376 | "ssr", "spc", | |
377 | /* bank 0 43 - 50 */ | |
378 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", | |
379 | /* bank 1 51 - 58 */ | |
380 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", | |
a6521d9a | 381 | /* 59 - 66 */ |
da962468 | 382 | "", "", "", "", "", "", "", "", |
c378eb4e | 383 | /* pseudo bank register. */ |
da962468 | 384 | "", |
a6521d9a | 385 | /* double precision (pseudo) 68 - 75 -- not for nofpu target */ |
474e5826 | 386 | "", "", "", "", "", "", "", "", |
a6521d9a | 387 | /* vectors (pseudo) 76 - 79 -- not for nofpu target */ |
474e5826 CV |
388 | "", "", "", "", |
389 | }; | |
390 | if (reg_nr < 0) | |
391 | return NULL; | |
392 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
393 | return NULL; | |
394 | return register_names[reg_nr]; | |
395 | } | |
396 | ||
397 | static const char * | |
d93859e2 | 398 | sh_sh4al_dsp_register_name (struct gdbarch *gdbarch, int reg_nr) |
474e5826 | 399 | { |
a121b7c1 | 400 | static const char *register_names[] = { |
474e5826 CV |
401 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
402 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
403 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
404 | "", "dsr", | |
405 | "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1", | |
406 | "y0", "y1", "", "", "", "", "", "mod", | |
407 | "ssr", "spc", | |
408 | "rs", "re", "", "", "", "", "", "", | |
026a72f8 CV |
409 | "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b", |
410 | "", "", "", "", "", "", "", "", | |
da962468 | 411 | "", "", "", "", "", "", "", "", |
474e5826 CV |
412 | }; |
413 | if (reg_nr < 0) | |
414 | return NULL; | |
415 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
416 | return NULL; | |
417 | return register_names[reg_nr]; | |
418 | } | |
419 | ||
cd6c3b4f YQ |
420 | /* Implement the breakpoint_kind_from_pc gdbarch method. */ |
421 | ||
d19280ad YQ |
422 | static int |
423 | sh_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr) | |
cc17453a | 424 | { |
d19280ad YQ |
425 | return 2; |
426 | } | |
427 | ||
cd6c3b4f YQ |
428 | /* Implement the sw_breakpoint_from_kind gdbarch method. */ |
429 | ||
d19280ad YQ |
430 | static const gdb_byte * |
431 | sh_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size) | |
432 | { | |
433 | *size = kind; | |
617daa0e | 434 | |
bac718a6 UW |
435 | /* For remote stub targets, trapa #20 is used. */ |
436 | if (strcmp (target_shortname, "remote") == 0) | |
437 | { | |
438 | static unsigned char big_remote_breakpoint[] = { 0xc3, 0x20 }; | |
439 | static unsigned char little_remote_breakpoint[] = { 0x20, 0xc3 }; | |
440 | ||
67d57894 | 441 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
d19280ad | 442 | return big_remote_breakpoint; |
bac718a6 | 443 | else |
d19280ad | 444 | return little_remote_breakpoint; |
bac718a6 | 445 | } |
d19280ad YQ |
446 | else |
447 | { | |
448 | /* 0xc3c3 is trapa #c3, and it works in big and little endian | |
449 | modes. */ | |
450 | static unsigned char breakpoint[] = { 0xc3, 0xc3 }; | |
bac718a6 | 451 | |
d19280ad YQ |
452 | return breakpoint; |
453 | } | |
cc17453a | 454 | } |
c906108c SS |
455 | |
456 | /* Prologue looks like | |
1c0159e0 CV |
457 | mov.l r14,@-r15 |
458 | sts.l pr,@-r15 | |
459 | mov.l <regs>,@-r15 | |
460 | sub <room_for_loca_vars>,r15 | |
461 | mov r15,r14 | |
8db62801 | 462 | |
c378eb4e | 463 | Actually it can be more complicated than this but that's it, basically. */ |
c906108c | 464 | |
1c0159e0 CV |
465 | #define GET_SOURCE_REG(x) (((x) >> 4) & 0xf) |
466 | #define GET_TARGET_REG(x) (((x) >> 8) & 0xf) | |
467 | ||
5f883edd FF |
468 | /* JSR @Rm 0100mmmm00001011 */ |
469 | #define IS_JSR(x) (((x) & 0xf0ff) == 0x400b) | |
470 | ||
8db62801 EZ |
471 | /* STS.L PR,@-r15 0100111100100010 |
472 | r15-4-->r15, PR-->(r15) */ | |
c906108c | 473 | #define IS_STS(x) ((x) == 0x4f22) |
8db62801 | 474 | |
03131d99 CV |
475 | /* STS.L MACL,@-r15 0100111100010010 |
476 | r15-4-->r15, MACL-->(r15) */ | |
477 | #define IS_MACL_STS(x) ((x) == 0x4f12) | |
478 | ||
8db62801 EZ |
479 | /* MOV.L Rm,@-r15 00101111mmmm0110 |
480 | r15-4-->r15, Rm-->(R15) */ | |
c906108c | 481 | #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06) |
8db62801 | 482 | |
8db62801 EZ |
483 | /* MOV r15,r14 0110111011110011 |
484 | r15-->r14 */ | |
c906108c | 485 | #define IS_MOV_SP_FP(x) ((x) == 0x6ef3) |
8db62801 EZ |
486 | |
487 | /* ADD #imm,r15 01111111iiiiiiii | |
488 | r15+imm-->r15 */ | |
1c0159e0 | 489 | #define IS_ADD_IMM_SP(x) (((x) & 0xff00) == 0x7f00) |
8db62801 | 490 | |
c906108c SS |
491 | #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00) |
492 | #define IS_SHLL_R3(x) ((x) == 0x4300) | |
8db62801 EZ |
493 | |
494 | /* ADD r3,r15 0011111100111100 | |
495 | r15+r3-->r15 */ | |
c906108c | 496 | #define IS_ADD_R3SP(x) ((x) == 0x3f3c) |
8db62801 EZ |
497 | |
498 | /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011 | |
8db62801 | 499 | FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011 |
8db62801 | 500 | FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */ |
f2ea0907 | 501 | /* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to |
c378eb4e | 502 | make this entirely clear. */ |
1c0159e0 CV |
503 | /* #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) */ |
504 | #define IS_FPUSH(x) (((x) & 0xff0f) == 0xff0b) | |
505 | ||
506 | /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 4 <= m <= 7 */ | |
507 | #define IS_MOV_ARG_TO_REG(x) \ | |
508 | (((x) & 0xf00f) == 0x6003 && \ | |
509 | ((x) & 0x00f0) >= 0x0040 && \ | |
510 | ((x) & 0x00f0) <= 0x0070) | |
511 | /* MOV.L Rm,@Rn 0010nnnnmmmm0010 n = 14, 4 <= m <= 7 */ | |
512 | #define IS_MOV_ARG_TO_IND_R14(x) \ | |
513 | (((x) & 0xff0f) == 0x2e02 && \ | |
514 | ((x) & 0x00f0) >= 0x0040 && \ | |
515 | ((x) & 0x00f0) <= 0x0070) | |
516 | /* MOV.L Rm,@(disp*4,Rn) 00011110mmmmdddd n = 14, 4 <= m <= 7 */ | |
517 | #define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \ | |
518 | (((x) & 0xff00) == 0x1e00 && \ | |
519 | ((x) & 0x00f0) >= 0x0040 && \ | |
520 | ((x) & 0x00f0) <= 0x0070) | |
521 | ||
522 | /* MOV.W @(disp*2,PC),Rn 1001nnnndddddddd */ | |
523 | #define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000) | |
524 | /* MOV.L @(disp*4,PC),Rn 1101nnnndddddddd */ | |
525 | #define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000) | |
03131d99 CV |
526 | /* MOVI20 #imm20,Rn 0000nnnniiii0000 */ |
527 | #define IS_MOVI20(x) (((x) & 0xf00f) == 0x0000) | |
1c0159e0 CV |
528 | /* SUB Rn,R15 00111111nnnn1000 */ |
529 | #define IS_SUB_REG_FROM_SP(x) (((x) & 0xff0f) == 0x3f08) | |
8db62801 | 530 | |
1c0159e0 | 531 | #define FPSCR_SZ (1 << 20) |
cc17453a | 532 | |
c378eb4e | 533 | /* The following instructions are used for epilogue testing. */ |
1c0159e0 CV |
534 | #define IS_RESTORE_FP(x) ((x) == 0x6ef6) |
535 | #define IS_RTS(x) ((x) == 0x000b) | |
536 | #define IS_LDS(x) ((x) == 0x4f26) | |
03131d99 | 537 | #define IS_MACL_LDS(x) ((x) == 0x4f16) |
1c0159e0 CV |
538 | #define IS_MOV_FP_SP(x) ((x) == 0x6fe3) |
539 | #define IS_ADD_REG_TO_FP(x) (((x) & 0xff0f) == 0x3e0c) | |
540 | #define IS_ADD_IMM_FP(x) (((x) & 0xff00) == 0x7e00) | |
cc17453a | 541 | |
cc17453a | 542 | static CORE_ADDR |
e17a4113 | 543 | sh_analyze_prologue (struct gdbarch *gdbarch, |
5cbb9812 | 544 | CORE_ADDR pc, CORE_ADDR limit_pc, |
d2ca4222 | 545 | struct sh_frame_cache *cache, ULONGEST fpscr) |
617daa0e | 546 | { |
e17a4113 | 547 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1c0159e0 | 548 | ULONGEST inst; |
1c0159e0 CV |
549 | int offset; |
550 | int sav_offset = 0; | |
c906108c | 551 | int r3_val = 0; |
1c0159e0 | 552 | int reg, sav_reg = -1; |
cc17453a | 553 | |
1c0159e0 | 554 | cache->uses_fp = 0; |
5cbb9812 | 555 | for (; pc < limit_pc; pc += 2) |
cc17453a | 556 | { |
e17a4113 | 557 | inst = read_memory_unsigned_integer (pc, 2, byte_order); |
c378eb4e | 558 | /* See where the registers will be saved to. */ |
f2ea0907 | 559 | if (IS_PUSH (inst)) |
cc17453a | 560 | { |
1c0159e0 CV |
561 | cache->saved_regs[GET_SOURCE_REG (inst)] = cache->sp_offset; |
562 | cache->sp_offset += 4; | |
cc17453a | 563 | } |
f2ea0907 | 564 | else if (IS_STS (inst)) |
cc17453a | 565 | { |
1c0159e0 CV |
566 | cache->saved_regs[PR_REGNUM] = cache->sp_offset; |
567 | cache->sp_offset += 4; | |
cc17453a | 568 | } |
03131d99 CV |
569 | else if (IS_MACL_STS (inst)) |
570 | { | |
571 | cache->saved_regs[MACL_REGNUM] = cache->sp_offset; | |
572 | cache->sp_offset += 4; | |
573 | } | |
f2ea0907 | 574 | else if (IS_MOV_R3 (inst)) |
cc17453a | 575 | { |
f2ea0907 | 576 | r3_val = ((inst & 0xff) ^ 0x80) - 0x80; |
cc17453a | 577 | } |
f2ea0907 | 578 | else if (IS_SHLL_R3 (inst)) |
cc17453a EZ |
579 | { |
580 | r3_val <<= 1; | |
581 | } | |
f2ea0907 | 582 | else if (IS_ADD_R3SP (inst)) |
cc17453a | 583 | { |
1c0159e0 | 584 | cache->sp_offset += -r3_val; |
cc17453a | 585 | } |
f2ea0907 | 586 | else if (IS_ADD_IMM_SP (inst)) |
cc17453a | 587 | { |
1c0159e0 CV |
588 | offset = ((inst & 0xff) ^ 0x80) - 0x80; |
589 | cache->sp_offset -= offset; | |
c906108c | 590 | } |
1c0159e0 | 591 | else if (IS_MOVW_PCREL_TO_REG (inst)) |
617daa0e | 592 | { |
1c0159e0 CV |
593 | if (sav_reg < 0) |
594 | { | |
595 | reg = GET_TARGET_REG (inst); | |
596 | if (reg < 14) | |
597 | { | |
598 | sav_reg = reg; | |
a2b4a96c | 599 | offset = (inst & 0xff) << 1; |
1c0159e0 | 600 | sav_offset = |
e17a4113 | 601 | read_memory_integer ((pc + 4) + offset, 2, byte_order); |
1c0159e0 CV |
602 | } |
603 | } | |
c906108c | 604 | } |
1c0159e0 | 605 | else if (IS_MOVL_PCREL_TO_REG (inst)) |
617daa0e | 606 | { |
1c0159e0 CV |
607 | if (sav_reg < 0) |
608 | { | |
a2b4a96c | 609 | reg = GET_TARGET_REG (inst); |
1c0159e0 CV |
610 | if (reg < 14) |
611 | { | |
612 | sav_reg = reg; | |
a2b4a96c | 613 | offset = (inst & 0xff) << 2; |
1c0159e0 | 614 | sav_offset = |
e17a4113 UW |
615 | read_memory_integer (((pc & 0xfffffffc) + 4) + offset, |
616 | 4, byte_order); | |
1c0159e0 CV |
617 | } |
618 | } | |
c906108c | 619 | } |
5cbb9812 TS |
620 | else if (IS_MOVI20 (inst) |
621 | && (pc + 2 < limit_pc)) | |
03131d99 CV |
622 | { |
623 | if (sav_reg < 0) | |
624 | { | |
625 | reg = GET_TARGET_REG (inst); | |
626 | if (reg < 14) | |
627 | { | |
628 | sav_reg = reg; | |
629 | sav_offset = GET_SOURCE_REG (inst) << 16; | |
c378eb4e | 630 | /* MOVI20 is a 32 bit instruction! */ |
03131d99 | 631 | pc += 2; |
e17a4113 UW |
632 | sav_offset |
633 | |= read_memory_unsigned_integer (pc, 2, byte_order); | |
03131d99 CV |
634 | /* Now sav_offset contains an unsigned 20 bit value. |
635 | It must still get sign extended. */ | |
636 | if (sav_offset & 0x00080000) | |
637 | sav_offset |= 0xfff00000; | |
638 | } | |
639 | } | |
640 | } | |
1c0159e0 | 641 | else if (IS_SUB_REG_FROM_SP (inst)) |
617daa0e | 642 | { |
1c0159e0 CV |
643 | reg = GET_SOURCE_REG (inst); |
644 | if (sav_reg > 0 && reg == sav_reg) | |
645 | { | |
646 | sav_reg = -1; | |
647 | } | |
648 | cache->sp_offset += sav_offset; | |
c906108c | 649 | } |
f2ea0907 | 650 | else if (IS_FPUSH (inst)) |
c906108c | 651 | { |
d2ca4222 | 652 | if (fpscr & FPSCR_SZ) |
c906108c | 653 | { |
1c0159e0 | 654 | cache->sp_offset += 8; |
c906108c SS |
655 | } |
656 | else | |
657 | { | |
1c0159e0 | 658 | cache->sp_offset += 4; |
c906108c SS |
659 | } |
660 | } | |
f2ea0907 | 661 | else if (IS_MOV_SP_FP (inst)) |
617daa0e | 662 | { |
5cbb9812 TS |
663 | pc += 2; |
664 | /* Don't go any further than six more instructions. */ | |
325fac50 | 665 | limit_pc = std::min (limit_pc, pc + (2 * 6)); |
5cbb9812 | 666 | |
960ccd7d | 667 | cache->uses_fp = 1; |
1c0159e0 CV |
668 | /* At this point, only allow argument register moves to other |
669 | registers or argument register moves to @(X,fp) which are | |
670 | moving the register arguments onto the stack area allocated | |
671 | by a former add somenumber to SP call. Don't allow moving | |
c378eb4e | 672 | to an fp indirect address above fp + cache->sp_offset. */ |
5cbb9812 | 673 | for (; pc < limit_pc; pc += 2) |
1c0159e0 | 674 | { |
e17a4113 | 675 | inst = read_memory_integer (pc, 2, byte_order); |
1c0159e0 | 676 | if (IS_MOV_ARG_TO_IND_R14 (inst)) |
617daa0e | 677 | { |
1c0159e0 CV |
678 | reg = GET_SOURCE_REG (inst); |
679 | if (cache->sp_offset > 0) | |
617daa0e | 680 | cache->saved_regs[reg] = cache->sp_offset; |
1c0159e0 CV |
681 | } |
682 | else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst)) | |
617daa0e | 683 | { |
1c0159e0 CV |
684 | reg = GET_SOURCE_REG (inst); |
685 | offset = (inst & 0xf) * 4; | |
686 | if (cache->sp_offset > offset) | |
687 | cache->saved_regs[reg] = cache->sp_offset - offset; | |
688 | } | |
689 | else if (IS_MOV_ARG_TO_REG (inst)) | |
617daa0e | 690 | continue; |
1c0159e0 CV |
691 | else |
692 | break; | |
693 | } | |
694 | break; | |
695 | } | |
5f883edd FF |
696 | else if (IS_JSR (inst)) |
697 | { | |
698 | /* We have found a jsr that has been scheduled into the prologue. | |
699 | If we continue the scan and return a pc someplace after this, | |
700 | then setting a breakpoint on this function will cause it to | |
701 | appear to be called after the function it is calling via the | |
702 | jsr, which will be very confusing. Most likely the next | |
703 | instruction is going to be IS_MOV_SP_FP in the delay slot. If | |
c378eb4e | 704 | so, note that before returning the current pc. */ |
5cbb9812 TS |
705 | if (pc + 2 < limit_pc) |
706 | { | |
707 | inst = read_memory_integer (pc + 2, 2, byte_order); | |
708 | if (IS_MOV_SP_FP (inst)) | |
709 | cache->uses_fp = 1; | |
710 | } | |
5f883edd FF |
711 | break; |
712 | } | |
c378eb4e MS |
713 | #if 0 /* This used to just stop when it found an instruction |
714 | that was not considered part of the prologue. Now, | |
715 | we just keep going looking for likely | |
716 | instructions. */ | |
c906108c SS |
717 | else |
718 | break; | |
2bfa91ee | 719 | #endif |
c906108c SS |
720 | } |
721 | ||
1c0159e0 CV |
722 | return pc; |
723 | } | |
c906108c | 724 | |
c378eb4e | 725 | /* Skip any prologue before the guts of a function. */ |
1c0159e0 | 726 | static CORE_ADDR |
8a8bc27f | 727 | sh_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
c906108c | 728 | { |
5cbb9812 | 729 | CORE_ADDR post_prologue_pc, func_addr, func_end_addr, limit_pc; |
1c0159e0 CV |
730 | struct sh_frame_cache cache; |
731 | ||
732 | /* See if we can determine the end of the prologue via the symbol table. | |
733 | If so, then return either PC, or the PC after the prologue, whichever | |
734 | is greater. */ | |
5cbb9812 | 735 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end_addr)) |
8a8bc27f TS |
736 | { |
737 | post_prologue_pc = skip_prologue_using_sal (gdbarch, func_addr); | |
738 | if (post_prologue_pc != 0) | |
325fac50 | 739 | return std::max (pc, post_prologue_pc); |
8a8bc27f | 740 | } |
cc17453a | 741 | |
8a8bc27f TS |
742 | /* Can't determine prologue from the symbol table, need to examine |
743 | instructions. */ | |
c906108c | 744 | |
5cbb9812 TS |
745 | /* Find an upper limit on the function prologue using the debug |
746 | information. If the debug information could not be used to provide | |
747 | that bound, then use an arbitrary large number as the upper bound. */ | |
748 | limit_pc = skip_prologue_using_sal (gdbarch, pc); | |
749 | if (limit_pc == 0) | |
750 | /* Don't go any further than 28 instructions. */ | |
751 | limit_pc = pc + (2 * 28); | |
752 | ||
753 | /* Do not allow limit_pc to be past the function end, if we know | |
754 | where that end is... */ | |
755 | if (func_end_addr != 0) | |
325fac50 | 756 | limit_pc = std::min (limit_pc, func_end_addr); |
5cbb9812 | 757 | |
1c0159e0 | 758 | cache.sp_offset = -4; |
5cbb9812 | 759 | post_prologue_pc = sh_analyze_prologue (gdbarch, pc, limit_pc, &cache, 0); |
8a8bc27f TS |
760 | if (cache.uses_fp) |
761 | pc = post_prologue_pc; | |
c906108c | 762 | |
1c0159e0 CV |
763 | return pc; |
764 | } | |
765 | ||
2e952408 | 766 | /* The ABI says: |
9a5cef92 EZ |
767 | |
768 | Aggregate types not bigger than 8 bytes that have the same size and | |
769 | alignment as one of the integer scalar types are returned in the | |
770 | same registers as the integer type they match. | |
771 | ||
772 | For example, a 2-byte aligned structure with size 2 bytes has the | |
773 | same size and alignment as a short int, and will be returned in R0. | |
774 | A 4-byte aligned structure with size 8 bytes has the same size and | |
775 | alignment as a long long int, and will be returned in R0 and R1. | |
776 | ||
777 | When an aggregate type is returned in R0 and R1, R0 contains the | |
778 | first four bytes of the aggregate, and R1 contains the | |
c378eb4e | 779 | remainder. If the size of the aggregate type is not a multiple of 4 |
9a5cef92 | 780 | bytes, the aggregate is tail-padded up to a multiple of 4 |
c378eb4e | 781 | bytes. The value of the padding is undefined. For little-endian |
9a5cef92 EZ |
782 | targets the padding will appear at the most significant end of the |
783 | last element, for big-endian targets the padding appears at the | |
784 | least significant end of the last element. | |
785 | ||
c378eb4e | 786 | All other aggregate types are returned by address. The caller |
9a5cef92 | 787 | function passes the address of an area large enough to hold the |
c378eb4e | 788 | aggregate value in R2. The called function stores the result in |
7fe958be | 789 | this location. |
9a5cef92 EZ |
790 | |
791 | To reiterate, structs smaller than 8 bytes could also be returned | |
792 | in memory, if they don't pass the "same size and alignment as an | |
793 | integer type" rule. | |
794 | ||
795 | For example, in | |
796 | ||
797 | struct s { char c[3]; } wibble; | |
798 | struct s foo(void) { return wibble; } | |
799 | ||
800 | the return value from foo() will be in memory, not | |
801 | in R0, because there is no 3-byte integer type. | |
802 | ||
7fe958be EZ |
803 | Similarly, in |
804 | ||
805 | struct s { char c[2]; } wibble; | |
806 | struct s foo(void) { return wibble; } | |
807 | ||
808 | because a struct containing two chars has alignment 1, that matches | |
809 | type char, but size 2, that matches type short. There's no integer | |
810 | type that has alignment 1 and size 2, so the struct is returned in | |
c378eb4e | 811 | memory. */ |
9a5cef92 | 812 | |
1c0159e0 | 813 | static int |
c055b101 | 814 | sh_use_struct_convention (int renesas_abi, struct type *type) |
1c0159e0 CV |
815 | { |
816 | int len = TYPE_LENGTH (type); | |
817 | int nelem = TYPE_NFIELDS (type); | |
3f997a97 | 818 | |
c055b101 CV |
819 | /* The Renesas ABI returns aggregate types always on stack. */ |
820 | if (renesas_abi && (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
821 | || TYPE_CODE (type) == TYPE_CODE_UNION)) | |
822 | return 1; | |
823 | ||
3f997a97 CV |
824 | /* Non-power of 2 length types and types bigger than 8 bytes (which don't |
825 | fit in two registers anyway) use struct convention. */ | |
826 | if (len != 1 && len != 2 && len != 4 && len != 8) | |
827 | return 1; | |
828 | ||
829 | /* Scalar types and aggregate types with exactly one field are aligned | |
830 | by definition. They are returned in registers. */ | |
831 | if (nelem <= 1) | |
832 | return 0; | |
833 | ||
834 | /* If the first field in the aggregate has the same length as the entire | |
835 | aggregate type, the type is returned in registers. */ | |
836 | if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == len) | |
837 | return 0; | |
838 | ||
839 | /* If the size of the aggregate is 8 bytes and the first field is | |
840 | of size 4 bytes its alignment is equal to long long's alignment, | |
841 | so it's returned in registers. */ | |
842 | if (len == 8 && TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == 4) | |
843 | return 0; | |
844 | ||
845 | /* Otherwise use struct convention. */ | |
846 | return 1; | |
283150cd EZ |
847 | } |
848 | ||
c055b101 CV |
849 | static int |
850 | sh_use_struct_convention_nofpu (int renesas_abi, struct type *type) | |
851 | { | |
852 | /* The Renesas ABI returns long longs/doubles etc. always on stack. */ | |
853 | if (renesas_abi && TYPE_NFIELDS (type) == 0 && TYPE_LENGTH (type) >= 8) | |
854 | return 1; | |
855 | return sh_use_struct_convention (renesas_abi, type); | |
856 | } | |
857 | ||
19f59343 MS |
858 | static CORE_ADDR |
859 | sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp) | |
860 | { | |
861 | return sp & ~3; | |
862 | } | |
863 | ||
55ff77ac | 864 | /* Function: push_dummy_call (formerly push_arguments) |
c906108c SS |
865 | Setup the function arguments for calling a function in the inferior. |
866 | ||
85a453d5 | 867 | On the Renesas SH architecture, there are four registers (R4 to R7) |
c906108c SS |
868 | which are dedicated for passing function arguments. Up to the first |
869 | four arguments (depending on size) may go into these registers. | |
870 | The rest go on the stack. | |
871 | ||
6df2bf50 MS |
872 | MVS: Except on SH variants that have floating point registers. |
873 | In that case, float and double arguments are passed in the same | |
874 | manner, but using FP registers instead of GP registers. | |
875 | ||
c906108c SS |
876 | Arguments that are smaller than 4 bytes will still take up a whole |
877 | register or a whole 32-bit word on the stack, and will be | |
878 | right-justified in the register or the stack word. This includes | |
879 | chars, shorts, and small aggregate types. | |
880 | ||
881 | Arguments that are larger than 4 bytes may be split between two or | |
882 | more registers. If there are not enough registers free, an argument | |
883 | may be passed partly in a register (or registers), and partly on the | |
c378eb4e | 884 | stack. This includes doubles, long longs, and larger aggregates. |
c906108c SS |
885 | As far as I know, there is no upper limit to the size of aggregates |
886 | that will be passed in this way; in other words, the convention of | |
887 | passing a pointer to a large aggregate instead of a copy is not used. | |
888 | ||
6df2bf50 | 889 | MVS: The above appears to be true for the SH variants that do not |
55ff77ac | 890 | have an FPU, however those that have an FPU appear to copy the |
6df2bf50 MS |
891 | aggregate argument onto the stack (and not place it in registers) |
892 | if it is larger than 16 bytes (four GP registers). | |
893 | ||
c906108c SS |
894 | An exceptional case exists for struct arguments (and possibly other |
895 | aggregates such as arrays) if the size is larger than 4 bytes but | |
896 | not a multiple of 4 bytes. In this case the argument is never split | |
897 | between the registers and the stack, but instead is copied in its | |
898 | entirety onto the stack, AND also copied into as many registers as | |
899 | there is room for. In other words, space in registers permitting, | |
900 | two copies of the same argument are passed in. As far as I can tell, | |
901 | only the one on the stack is used, although that may be a function | |
902 | of the level of compiler optimization. I suspect this is a compiler | |
903 | bug. Arguments of these odd sizes are left-justified within the | |
904 | word (as opposed to arguments smaller than 4 bytes, which are | |
905 | right-justified). | |
c5aa993b | 906 | |
c906108c SS |
907 | If the function is to return an aggregate type such as a struct, it |
908 | is either returned in the normal return value register R0 (if its | |
909 | size is no greater than one byte), or else the caller must allocate | |
910 | space into which the callee will copy the return value (if the size | |
911 | is greater than one byte). In this case, a pointer to the return | |
912 | value location is passed into the callee in register R2, which does | |
913 | not displace any of the other arguments passed in via registers R4 | |
c378eb4e | 914 | to R7. */ |
c906108c | 915 | |
c378eb4e | 916 | /* Helper function to justify value in register according to endianess. */ |
948f8e3d | 917 | static const gdb_byte * |
d93859e2 | 918 | sh_justify_value_in_reg (struct gdbarch *gdbarch, struct value *val, int len) |
e5e33cd9 | 919 | { |
948f8e3d | 920 | static gdb_byte valbuf[4]; |
e5e33cd9 | 921 | |
617daa0e | 922 | memset (valbuf, 0, sizeof (valbuf)); |
e5e33cd9 CV |
923 | if (len < 4) |
924 | { | |
c378eb4e | 925 | /* value gets right-justified in the register or stack word. */ |
d93859e2 | 926 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
948f8e3d | 927 | memcpy (valbuf + (4 - len), value_contents (val), len); |
e5e33cd9 | 928 | else |
948f8e3d | 929 | memcpy (valbuf, value_contents (val), len); |
e5e33cd9 CV |
930 | return valbuf; |
931 | } | |
948f8e3d | 932 | return value_contents (val); |
617daa0e | 933 | } |
e5e33cd9 | 934 | |
c378eb4e | 935 | /* Helper function to eval number of bytes to allocate on stack. */ |
e5e33cd9 CV |
936 | static CORE_ADDR |
937 | sh_stack_allocsize (int nargs, struct value **args) | |
938 | { | |
939 | int stack_alloc = 0; | |
940 | while (nargs-- > 0) | |
4991999e | 941 | stack_alloc += ((TYPE_LENGTH (value_type (args[nargs])) + 3) & ~3); |
e5e33cd9 CV |
942 | return stack_alloc; |
943 | } | |
944 | ||
945 | /* Helper functions for getting the float arguments right. Registers usage | |
946 | depends on the ABI and the endianess. The comments should enlighten how | |
c378eb4e | 947 | it's intended to work. */ |
e5e33cd9 | 948 | |
c378eb4e | 949 | /* This array stores which of the float arg registers are already in use. */ |
e5e33cd9 CV |
950 | static int flt_argreg_array[FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM + 1]; |
951 | ||
c378eb4e | 952 | /* This function just resets the above array to "no reg used so far". */ |
e5e33cd9 CV |
953 | static void |
954 | sh_init_flt_argreg (void) | |
955 | { | |
956 | memset (flt_argreg_array, 0, sizeof flt_argreg_array); | |
957 | } | |
958 | ||
959 | /* This function returns the next register to use for float arg passing. | |
960 | It returns either a valid value between FLOAT_ARG0_REGNUM and | |
961 | FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns | |
962 | FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available. | |
963 | ||
964 | Note that register number 0 in flt_argreg_array corresponds with the | |
965 | real float register fr4. In contrast to FLOAT_ARG0_REGNUM (value is | |
966 | 29) the parity of the register number is preserved, which is important | |
c378eb4e | 967 | for the double register passing test (see the "argreg & 1" test below). */ |
e5e33cd9 | 968 | static int |
c055b101 | 969 | sh_next_flt_argreg (struct gdbarch *gdbarch, int len, struct type *func_type) |
e5e33cd9 CV |
970 | { |
971 | int argreg; | |
972 | ||
c378eb4e | 973 | /* First search for the next free register. */ |
617daa0e CV |
974 | for (argreg = 0; argreg <= FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM; |
975 | ++argreg) | |
e5e33cd9 CV |
976 | if (!flt_argreg_array[argreg]) |
977 | break; | |
978 | ||
c378eb4e | 979 | /* No register left? */ |
e5e33cd9 CV |
980 | if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM) |
981 | return FLOAT_ARGLAST_REGNUM + 1; | |
982 | ||
983 | if (len == 8) | |
984 | { | |
c378eb4e | 985 | /* Doubles are always starting in a even register number. */ |
e5e33cd9 | 986 | if (argreg & 1) |
617daa0e | 987 | { |
c055b101 CV |
988 | /* In gcc ABI, the skipped register is lost for further argument |
989 | passing now. Not so in Renesas ABI. */ | |
990 | if (!sh_is_renesas_calling_convention (func_type)) | |
991 | flt_argreg_array[argreg] = 1; | |
e5e33cd9 CV |
992 | |
993 | ++argreg; | |
994 | ||
c378eb4e | 995 | /* No register left? */ |
e5e33cd9 CV |
996 | if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM) |
997 | return FLOAT_ARGLAST_REGNUM + 1; | |
998 | } | |
c378eb4e | 999 | /* Also mark the next register as used. */ |
e5e33cd9 CV |
1000 | flt_argreg_array[argreg + 1] = 1; |
1001 | } | |
c055b101 CV |
1002 | else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE |
1003 | && !sh_is_renesas_calling_convention (func_type)) | |
e5e33cd9 | 1004 | { |
c378eb4e | 1005 | /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */ |
e5e33cd9 CV |
1006 | if (!flt_argreg_array[argreg + 1]) |
1007 | ++argreg; | |
1008 | } | |
1009 | flt_argreg_array[argreg] = 1; | |
1010 | return FLOAT_ARG0_REGNUM + argreg; | |
1011 | } | |
1012 | ||
afce3d2a CV |
1013 | /* Helper function which figures out, if a type is treated like a float type. |
1014 | ||
2e952408 | 1015 | The FPU ABIs have a special way how to treat types as float types. |
afce3d2a CV |
1016 | Structures with exactly one member, which is of type float or double, are |
1017 | treated exactly as the base types float or double: | |
1018 | ||
1019 | struct sf { | |
1020 | float f; | |
1021 | }; | |
1022 | ||
1023 | struct sd { | |
1024 | double d; | |
1025 | }; | |
1026 | ||
1027 | are handled the same way as just | |
1028 | ||
1029 | float f; | |
1030 | ||
1031 | double d; | |
1032 | ||
1033 | As a result, arguments of these struct types are pushed into floating point | |
1034 | registers exactly as floats or doubles, using the same decision algorithm. | |
1035 | ||
1036 | The same is valid if these types are used as function return types. The | |
1037 | above structs are returned in fr0 resp. fr0,fr1 instead of in r0, r0,r1 | |
1038 | or even using struct convention as it is for other structs. */ | |
1039 | ||
1040 | static int | |
1041 | sh_treat_as_flt_p (struct type *type) | |
1042 | { | |
afce3d2a CV |
1043 | /* Ordinary float types are obviously treated as float. */ |
1044 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
1045 | return 1; | |
1046 | /* Otherwise non-struct types are not treated as float. */ | |
1047 | if (TYPE_CODE (type) != TYPE_CODE_STRUCT) | |
1048 | return 0; | |
1049 | /* Otherwise structs with more than one memeber are not treated as float. */ | |
1050 | if (TYPE_NFIELDS (type) != 1) | |
1051 | return 0; | |
1052 | /* Otherwise if the type of that member is float, the whole type is | |
1053 | treated as float. */ | |
1054 | if (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) == TYPE_CODE_FLT) | |
1055 | return 1; | |
1056 | /* Otherwise it's not treated as float. */ | |
1057 | return 0; | |
1058 | } | |
1059 | ||
cc17453a | 1060 | static CORE_ADDR |
617daa0e | 1061 | sh_push_dummy_call_fpu (struct gdbarch *gdbarch, |
7d9b040b | 1062 | struct value *function, |
617daa0e | 1063 | struct regcache *regcache, |
6df2bf50 | 1064 | CORE_ADDR bp_addr, int nargs, |
617daa0e | 1065 | struct value **args, |
6df2bf50 MS |
1066 | CORE_ADDR sp, int struct_return, |
1067 | CORE_ADDR struct_addr) | |
1068 | { | |
e17a4113 | 1069 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
e5e33cd9 CV |
1070 | int stack_offset = 0; |
1071 | int argreg = ARG0_REGNUM; | |
8748518b | 1072 | int flt_argreg = 0; |
6df2bf50 | 1073 | int argnum; |
c055b101 | 1074 | struct type *func_type = value_type (function); |
6df2bf50 MS |
1075 | struct type *type; |
1076 | CORE_ADDR regval; | |
948f8e3d | 1077 | const gdb_byte *val; |
8748518b | 1078 | int len, reg_size = 0; |
afce3d2a CV |
1079 | int pass_on_stack = 0; |
1080 | int treat_as_flt; | |
c055b101 CV |
1081 | int last_reg_arg = INT_MAX; |
1082 | ||
1083 | /* The Renesas ABI expects all varargs arguments, plus the last | |
1084 | non-vararg argument to be on the stack, no matter how many | |
1085 | registers have been used so far. */ | |
1086 | if (sh_is_renesas_calling_convention (func_type) | |
876cecd0 | 1087 | && TYPE_VARARGS (func_type)) |
c055b101 | 1088 | last_reg_arg = TYPE_NFIELDS (func_type) - 2; |
6df2bf50 | 1089 | |
c378eb4e | 1090 | /* First force sp to a 4-byte alignment. */ |
6df2bf50 MS |
1091 | sp = sh_frame_align (gdbarch, sp); |
1092 | ||
c378eb4e | 1093 | /* Make room on stack for args. */ |
e5e33cd9 CV |
1094 | sp -= sh_stack_allocsize (nargs, args); |
1095 | ||
c378eb4e | 1096 | /* Initialize float argument mechanism. */ |
e5e33cd9 | 1097 | sh_init_flt_argreg (); |
6df2bf50 MS |
1098 | |
1099 | /* Now load as many as possible of the first arguments into | |
1100 | registers, and push the rest onto the stack. There are 16 bytes | |
1101 | in four registers available. Loop thru args from first to last. */ | |
e5e33cd9 | 1102 | for (argnum = 0; argnum < nargs; argnum++) |
6df2bf50 | 1103 | { |
4991999e | 1104 | type = value_type (args[argnum]); |
6df2bf50 | 1105 | len = TYPE_LENGTH (type); |
d93859e2 | 1106 | val = sh_justify_value_in_reg (gdbarch, args[argnum], len); |
e5e33cd9 CV |
1107 | |
1108 | /* Some decisions have to be made how various types are handled. | |
c378eb4e | 1109 | This also differs in different ABIs. */ |
e5e33cd9 | 1110 | pass_on_stack = 0; |
e5e33cd9 | 1111 | |
c378eb4e | 1112 | /* Find out the next register to use for a floating point value. */ |
afce3d2a CV |
1113 | treat_as_flt = sh_treat_as_flt_p (type); |
1114 | if (treat_as_flt) | |
c055b101 CV |
1115 | flt_argreg = sh_next_flt_argreg (gdbarch, len, func_type); |
1116 | /* In Renesas ABI, long longs and aggregate types are always passed | |
1117 | on stack. */ | |
1118 | else if (sh_is_renesas_calling_convention (func_type) | |
1119 | && ((TYPE_CODE (type) == TYPE_CODE_INT && len == 8) | |
1120 | || TYPE_CODE (type) == TYPE_CODE_STRUCT | |
1121 | || TYPE_CODE (type) == TYPE_CODE_UNION)) | |
1122 | pass_on_stack = 1; | |
afce3d2a CV |
1123 | /* In contrast to non-FPU CPUs, arguments are never split between |
1124 | registers and stack. If an argument doesn't fit in the remaining | |
1125 | registers it's always pushed entirely on the stack. */ | |
1126 | else if (len > ((ARGLAST_REGNUM - argreg + 1) * 4)) | |
1127 | pass_on_stack = 1; | |
48db5a3c | 1128 | |
6df2bf50 MS |
1129 | while (len > 0) |
1130 | { | |
afce3d2a CV |
1131 | if ((treat_as_flt && flt_argreg > FLOAT_ARGLAST_REGNUM) |
1132 | || (!treat_as_flt && (argreg > ARGLAST_REGNUM | |
c055b101 CV |
1133 | || pass_on_stack)) |
1134 | || argnum > last_reg_arg) | |
617daa0e | 1135 | { |
c378eb4e | 1136 | /* The data goes entirely on the stack, 4-byte aligned. */ |
e5e33cd9 CV |
1137 | reg_size = (len + 3) & ~3; |
1138 | write_memory (sp + stack_offset, val, reg_size); | |
1139 | stack_offset += reg_size; | |
6df2bf50 | 1140 | } |
afce3d2a | 1141 | else if (treat_as_flt && flt_argreg <= FLOAT_ARGLAST_REGNUM) |
6df2bf50 | 1142 | { |
e5e33cd9 CV |
1143 | /* Argument goes in a float argument register. */ |
1144 | reg_size = register_size (gdbarch, flt_argreg); | |
e17a4113 | 1145 | regval = extract_unsigned_integer (val, reg_size, byte_order); |
2e952408 CV |
1146 | /* In little endian mode, float types taking two registers |
1147 | (doubles on sh4, long doubles on sh2e, sh3e and sh4) must | |
1148 | be stored swapped in the argument registers. The below | |
1149 | code first writes the first 32 bits in the next but one | |
1150 | register, increments the val and len values accordingly | |
1151 | and then proceeds as normal by writing the second 32 bits | |
c378eb4e | 1152 | into the next register. */ |
b47193f7 | 1153 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE |
2e952408 CV |
1154 | && TYPE_LENGTH (type) == 2 * reg_size) |
1155 | { | |
1156 | regcache_cooked_write_unsigned (regcache, flt_argreg + 1, | |
1157 | regval); | |
1158 | val += reg_size; | |
1159 | len -= reg_size; | |
c378eb4e MS |
1160 | regval = extract_unsigned_integer (val, reg_size, |
1161 | byte_order); | |
2e952408 | 1162 | } |
6df2bf50 MS |
1163 | regcache_cooked_write_unsigned (regcache, flt_argreg++, regval); |
1164 | } | |
afce3d2a | 1165 | else if (!treat_as_flt && argreg <= ARGLAST_REGNUM) |
e5e33cd9 | 1166 | { |
6df2bf50 | 1167 | /* there's room in a register */ |
e5e33cd9 | 1168 | reg_size = register_size (gdbarch, argreg); |
e17a4113 | 1169 | regval = extract_unsigned_integer (val, reg_size, byte_order); |
6df2bf50 MS |
1170 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
1171 | } | |
c378eb4e MS |
1172 | /* Store the value one register at a time or in one step on |
1173 | stack. */ | |
e5e33cd9 CV |
1174 | len -= reg_size; |
1175 | val += reg_size; | |
6df2bf50 MS |
1176 | } |
1177 | } | |
1178 | ||
c055b101 CV |
1179 | if (struct_return) |
1180 | { | |
1181 | if (sh_is_renesas_calling_convention (func_type)) | |
1182 | /* If the function uses the Renesas ABI, subtract another 4 bytes from | |
1183 | the stack and store the struct return address there. */ | |
e17a4113 | 1184 | write_memory_unsigned_integer (sp -= 4, 4, byte_order, struct_addr); |
c055b101 CV |
1185 | else |
1186 | /* Using the gcc ABI, the "struct return pointer" pseudo-argument has | |
1187 | its own dedicated register. */ | |
1188 | regcache_cooked_write_unsigned (regcache, | |
1189 | STRUCT_RETURN_REGNUM, struct_addr); | |
1190 | } | |
1191 | ||
c378eb4e | 1192 | /* Store return address. */ |
55ff77ac | 1193 | regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr); |
6df2bf50 MS |
1194 | |
1195 | /* Update stack pointer. */ | |
3e8c568d | 1196 | regcache_cooked_write_unsigned (regcache, |
b47193f7 | 1197 | gdbarch_sp_regnum (gdbarch), sp); |
6df2bf50 MS |
1198 | |
1199 | return sp; | |
1200 | } | |
1201 | ||
1202 | static CORE_ADDR | |
617daa0e | 1203 | sh_push_dummy_call_nofpu (struct gdbarch *gdbarch, |
7d9b040b | 1204 | struct value *function, |
617daa0e CV |
1205 | struct regcache *regcache, |
1206 | CORE_ADDR bp_addr, | |
1207 | int nargs, struct value **args, | |
1208 | CORE_ADDR sp, int struct_return, | |
6df2bf50 | 1209 | CORE_ADDR struct_addr) |
c906108c | 1210 | { |
e17a4113 | 1211 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
e5e33cd9 CV |
1212 | int stack_offset = 0; |
1213 | int argreg = ARG0_REGNUM; | |
c906108c | 1214 | int argnum; |
c055b101 | 1215 | struct type *func_type = value_type (function); |
c906108c SS |
1216 | struct type *type; |
1217 | CORE_ADDR regval; | |
948f8e3d | 1218 | const gdb_byte *val; |
c055b101 CV |
1219 | int len, reg_size = 0; |
1220 | int pass_on_stack = 0; | |
1221 | int last_reg_arg = INT_MAX; | |
1222 | ||
1223 | /* The Renesas ABI expects all varargs arguments, plus the last | |
1224 | non-vararg argument to be on the stack, no matter how many | |
1225 | registers have been used so far. */ | |
1226 | if (sh_is_renesas_calling_convention (func_type) | |
876cecd0 | 1227 | && TYPE_VARARGS (func_type)) |
c055b101 | 1228 | last_reg_arg = TYPE_NFIELDS (func_type) - 2; |
c906108c | 1229 | |
c378eb4e | 1230 | /* First force sp to a 4-byte alignment. */ |
19f59343 | 1231 | sp = sh_frame_align (gdbarch, sp); |
c906108c | 1232 | |
c378eb4e | 1233 | /* Make room on stack for args. */ |
e5e33cd9 | 1234 | sp -= sh_stack_allocsize (nargs, args); |
c906108c | 1235 | |
c906108c SS |
1236 | /* Now load as many as possible of the first arguments into |
1237 | registers, and push the rest onto the stack. There are 16 bytes | |
1238 | in four registers available. Loop thru args from first to last. */ | |
e5e33cd9 | 1239 | for (argnum = 0; argnum < nargs; argnum++) |
617daa0e | 1240 | { |
4991999e | 1241 | type = value_type (args[argnum]); |
c5aa993b | 1242 | len = TYPE_LENGTH (type); |
d93859e2 | 1243 | val = sh_justify_value_in_reg (gdbarch, args[argnum], len); |
c906108c | 1244 | |
c055b101 | 1245 | /* Some decisions have to be made how various types are handled. |
c378eb4e | 1246 | This also differs in different ABIs. */ |
c055b101 CV |
1247 | pass_on_stack = 0; |
1248 | /* Renesas ABI pushes doubles and long longs entirely on stack. | |
1249 | Same goes for aggregate types. */ | |
1250 | if (sh_is_renesas_calling_convention (func_type) | |
1251 | && ((TYPE_CODE (type) == TYPE_CODE_INT && len >= 8) | |
1252 | || (TYPE_CODE (type) == TYPE_CODE_FLT && len >= 8) | |
1253 | || TYPE_CODE (type) == TYPE_CODE_STRUCT | |
1254 | || TYPE_CODE (type) == TYPE_CODE_UNION)) | |
1255 | pass_on_stack = 1; | |
c906108c SS |
1256 | while (len > 0) |
1257 | { | |
c055b101 CV |
1258 | if (argreg > ARGLAST_REGNUM || pass_on_stack |
1259 | || argnum > last_reg_arg) | |
617daa0e | 1260 | { |
e5e33cd9 | 1261 | /* The remainder of the data goes entirely on the stack, |
c378eb4e | 1262 | 4-byte aligned. */ |
e5e33cd9 CV |
1263 | reg_size = (len + 3) & ~3; |
1264 | write_memory (sp + stack_offset, val, reg_size); | |
617daa0e | 1265 | stack_offset += reg_size; |
c906108c | 1266 | } |
e5e33cd9 | 1267 | else if (argreg <= ARGLAST_REGNUM) |
617daa0e | 1268 | { |
c378eb4e | 1269 | /* There's room in a register. */ |
e5e33cd9 | 1270 | reg_size = register_size (gdbarch, argreg); |
e17a4113 | 1271 | regval = extract_unsigned_integer (val, reg_size, byte_order); |
48db5a3c | 1272 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
c906108c | 1273 | } |
e5e33cd9 CV |
1274 | /* Store the value reg_size bytes at a time. This means that things |
1275 | larger than reg_size bytes may go partly in registers and partly | |
c906108c | 1276 | on the stack. */ |
e5e33cd9 CV |
1277 | len -= reg_size; |
1278 | val += reg_size; | |
c906108c SS |
1279 | } |
1280 | } | |
48db5a3c | 1281 | |
c055b101 CV |
1282 | if (struct_return) |
1283 | { | |
1284 | if (sh_is_renesas_calling_convention (func_type)) | |
1285 | /* If the function uses the Renesas ABI, subtract another 4 bytes from | |
1286 | the stack and store the struct return address there. */ | |
e17a4113 | 1287 | write_memory_unsigned_integer (sp -= 4, 4, byte_order, struct_addr); |
c055b101 CV |
1288 | else |
1289 | /* Using the gcc ABI, the "struct return pointer" pseudo-argument has | |
1290 | its own dedicated register. */ | |
1291 | regcache_cooked_write_unsigned (regcache, | |
1292 | STRUCT_RETURN_REGNUM, struct_addr); | |
1293 | } | |
1294 | ||
c378eb4e | 1295 | /* Store return address. */ |
55ff77ac | 1296 | regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr); |
48db5a3c CV |
1297 | |
1298 | /* Update stack pointer. */ | |
3e8c568d | 1299 | regcache_cooked_write_unsigned (regcache, |
b47193f7 | 1300 | gdbarch_sp_regnum (gdbarch), sp); |
48db5a3c | 1301 | |
c906108c SS |
1302 | return sp; |
1303 | } | |
1304 | ||
cc17453a EZ |
1305 | /* Find a function's return value in the appropriate registers (in |
1306 | regbuf), and copy it into valbuf. Extract from an array REGBUF | |
1307 | containing the (raw) register state a function return value of type | |
1308 | TYPE, and copy that, in virtual format, into VALBUF. */ | |
1309 | static void | |
3ffc5b9b | 1310 | sh_extract_return_value_nofpu (struct type *type, struct regcache *regcache, |
948f8e3d | 1311 | gdb_byte *valbuf) |
c906108c | 1312 | { |
ac7936df | 1313 | struct gdbarch *gdbarch = regcache->arch (); |
e17a4113 | 1314 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
cc17453a | 1315 | int len = TYPE_LENGTH (type); |
617daa0e | 1316 | |
cc17453a | 1317 | if (len <= 4) |
3116c80a | 1318 | { |
48db5a3c CV |
1319 | ULONGEST c; |
1320 | ||
1321 | regcache_cooked_read_unsigned (regcache, R0_REGNUM, &c); | |
e17a4113 | 1322 | store_unsigned_integer (valbuf, len, byte_order, c); |
3116c80a | 1323 | } |
48db5a3c | 1324 | else if (len == 8) |
3116c80a | 1325 | { |
48db5a3c CV |
1326 | int i, regnum = R0_REGNUM; |
1327 | for (i = 0; i < len; i += 4) | |
948f8e3d | 1328 | regcache_raw_read (regcache, regnum++, valbuf + i); |
3116c80a EZ |
1329 | } |
1330 | else | |
8a3fe4f8 | 1331 | error (_("bad size for return value")); |
3116c80a EZ |
1332 | } |
1333 | ||
1334 | static void | |
3ffc5b9b | 1335 | sh_extract_return_value_fpu (struct type *type, struct regcache *regcache, |
948f8e3d | 1336 | gdb_byte *valbuf) |
3116c80a | 1337 | { |
ac7936df | 1338 | struct gdbarch *gdbarch = regcache->arch (); |
afce3d2a | 1339 | if (sh_treat_as_flt_p (type)) |
3116c80a | 1340 | { |
48db5a3c | 1341 | int len = TYPE_LENGTH (type); |
d93859e2 | 1342 | int i, regnum = gdbarch_fp0_regnum (gdbarch); |
48db5a3c | 1343 | for (i = 0; i < len; i += 4) |
d93859e2 | 1344 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) |
c378eb4e | 1345 | regcache_raw_read (regcache, regnum++, |
948f8e3d | 1346 | valbuf + len - 4 - i); |
2e952408 | 1347 | else |
948f8e3d | 1348 | regcache_raw_read (regcache, regnum++, valbuf + i); |
3116c80a | 1349 | } |
cc17453a | 1350 | else |
3ffc5b9b | 1351 | sh_extract_return_value_nofpu (type, regcache, valbuf); |
cc17453a | 1352 | } |
c906108c | 1353 | |
cc17453a EZ |
1354 | /* Write into appropriate registers a function return value |
1355 | of type TYPE, given in virtual format. | |
1356 | If the architecture is sh4 or sh3e, store a function's return value | |
1357 | in the R0 general register or in the FP0 floating point register, | |
c378eb4e MS |
1358 | depending on the type of the return value. In all the other cases |
1359 | the result is stored in r0, left-justified. */ | |
cc17453a | 1360 | static void |
3ffc5b9b | 1361 | sh_store_return_value_nofpu (struct type *type, struct regcache *regcache, |
948f8e3d | 1362 | const gdb_byte *valbuf) |
cc17453a | 1363 | { |
ac7936df | 1364 | struct gdbarch *gdbarch = regcache->arch (); |
e17a4113 | 1365 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
48db5a3c CV |
1366 | ULONGEST val; |
1367 | int len = TYPE_LENGTH (type); | |
d19b71be | 1368 | |
48db5a3c | 1369 | if (len <= 4) |
d19b71be | 1370 | { |
e17a4113 | 1371 | val = extract_unsigned_integer (valbuf, len, byte_order); |
48db5a3c | 1372 | regcache_cooked_write_unsigned (regcache, R0_REGNUM, val); |
d19b71be MS |
1373 | } |
1374 | else | |
48db5a3c CV |
1375 | { |
1376 | int i, regnum = R0_REGNUM; | |
1377 | for (i = 0; i < len; i += 4) | |
948f8e3d | 1378 | regcache_raw_write (regcache, regnum++, valbuf + i); |
48db5a3c | 1379 | } |
cc17453a | 1380 | } |
c906108c | 1381 | |
cc17453a | 1382 | static void |
3ffc5b9b | 1383 | sh_store_return_value_fpu (struct type *type, struct regcache *regcache, |
948f8e3d | 1384 | const gdb_byte *valbuf) |
cc17453a | 1385 | { |
ac7936df | 1386 | struct gdbarch *gdbarch = regcache->arch (); |
afce3d2a | 1387 | if (sh_treat_as_flt_p (type)) |
48db5a3c CV |
1388 | { |
1389 | int len = TYPE_LENGTH (type); | |
d93859e2 | 1390 | int i, regnum = gdbarch_fp0_regnum (gdbarch); |
48db5a3c | 1391 | for (i = 0; i < len; i += 4) |
d93859e2 | 1392 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) |
c8a3b559 | 1393 | regcache_raw_write (regcache, regnum++, |
948f8e3d | 1394 | valbuf + len - 4 - i); |
c8a3b559 | 1395 | else |
948f8e3d | 1396 | regcache_raw_write (regcache, regnum++, valbuf + i); |
48db5a3c | 1397 | } |
cc17453a | 1398 | else |
3ffc5b9b | 1399 | sh_store_return_value_nofpu (type, regcache, valbuf); |
c906108c SS |
1400 | } |
1401 | ||
c0409442 | 1402 | static enum return_value_convention |
6a3a010b | 1403 | sh_return_value_nofpu (struct gdbarch *gdbarch, struct value *function, |
c055b101 | 1404 | struct type *type, struct regcache *regcache, |
18cf8b5b | 1405 | gdb_byte *readbuf, const gdb_byte *writebuf) |
c0409442 | 1406 | { |
6a3a010b MR |
1407 | struct type *func_type = function ? value_type (function) : NULL; |
1408 | ||
c055b101 CV |
1409 | if (sh_use_struct_convention_nofpu ( |
1410 | sh_is_renesas_calling_convention (func_type), type)) | |
c0409442 CV |
1411 | return RETURN_VALUE_STRUCT_CONVENTION; |
1412 | if (writebuf) | |
3ffc5b9b | 1413 | sh_store_return_value_nofpu (type, regcache, writebuf); |
c0409442 | 1414 | else if (readbuf) |
3ffc5b9b | 1415 | sh_extract_return_value_nofpu (type, regcache, readbuf); |
c0409442 CV |
1416 | return RETURN_VALUE_REGISTER_CONVENTION; |
1417 | } | |
1418 | ||
1419 | static enum return_value_convention | |
6a3a010b | 1420 | sh_return_value_fpu (struct gdbarch *gdbarch, struct value *function, |
c055b101 | 1421 | struct type *type, struct regcache *regcache, |
18cf8b5b | 1422 | gdb_byte *readbuf, const gdb_byte *writebuf) |
c0409442 | 1423 | { |
6a3a010b MR |
1424 | struct type *func_type = function ? value_type (function) : NULL; |
1425 | ||
c055b101 CV |
1426 | if (sh_use_struct_convention ( |
1427 | sh_is_renesas_calling_convention (func_type), type)) | |
c0409442 CV |
1428 | return RETURN_VALUE_STRUCT_CONVENTION; |
1429 | if (writebuf) | |
3ffc5b9b | 1430 | sh_store_return_value_fpu (type, regcache, writebuf); |
c0409442 | 1431 | else if (readbuf) |
3ffc5b9b | 1432 | sh_extract_return_value_fpu (type, regcache, readbuf); |
c0409442 CV |
1433 | return RETURN_VALUE_REGISTER_CONVENTION; |
1434 | } | |
1435 | ||
da962468 CV |
1436 | static struct type * |
1437 | sh_sh2a_register_type (struct gdbarch *gdbarch, int reg_nr) | |
1438 | { | |
b47193f7 | 1439 | if ((reg_nr >= gdbarch_fp0_regnum (gdbarch) |
da962468 | 1440 | && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM)) |
0dfff4cb | 1441 | return builtin_type (gdbarch)->builtin_float; |
da962468 | 1442 | else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM) |
0dfff4cb | 1443 | return builtin_type (gdbarch)->builtin_double; |
da962468 | 1444 | else |
0dfff4cb | 1445 | return builtin_type (gdbarch)->builtin_int; |
da962468 CV |
1446 | } |
1447 | ||
cc17453a EZ |
1448 | /* Return the GDB type object for the "standard" data type |
1449 | of data in register N. */ | |
cc17453a | 1450 | static struct type * |
48db5a3c | 1451 | sh_sh3e_register_type (struct gdbarch *gdbarch, int reg_nr) |
cc17453a | 1452 | { |
b47193f7 | 1453 | if ((reg_nr >= gdbarch_fp0_regnum (gdbarch) |
617daa0e | 1454 | && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM)) |
0dfff4cb | 1455 | return builtin_type (gdbarch)->builtin_float; |
8db62801 | 1456 | else |
0dfff4cb | 1457 | return builtin_type (gdbarch)->builtin_int; |
cc17453a EZ |
1458 | } |
1459 | ||
7f4dbe94 | 1460 | static struct type * |
0dfff4cb | 1461 | sh_sh4_build_float_register_type (struct gdbarch *gdbarch, int high) |
7f4dbe94 | 1462 | { |
e3506a9f UW |
1463 | return lookup_array_range_type (builtin_type (gdbarch)->builtin_float, |
1464 | 0, high); | |
7f4dbe94 EZ |
1465 | } |
1466 | ||
53116e27 | 1467 | static struct type * |
48db5a3c | 1468 | sh_sh4_register_type (struct gdbarch *gdbarch, int reg_nr) |
53116e27 | 1469 | { |
b47193f7 | 1470 | if ((reg_nr >= gdbarch_fp0_regnum (gdbarch) |
617daa0e | 1471 | && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM)) |
0dfff4cb | 1472 | return builtin_type (gdbarch)->builtin_float; |
617daa0e | 1473 | else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM) |
0dfff4cb | 1474 | return builtin_type (gdbarch)->builtin_double; |
617daa0e | 1475 | else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM) |
0dfff4cb | 1476 | return sh_sh4_build_float_register_type (gdbarch, 3); |
53116e27 | 1477 | else |
0dfff4cb | 1478 | return builtin_type (gdbarch)->builtin_int; |
53116e27 EZ |
1479 | } |
1480 | ||
cc17453a | 1481 | static struct type * |
48db5a3c | 1482 | sh_default_register_type (struct gdbarch *gdbarch, int reg_nr) |
cc17453a | 1483 | { |
0dfff4cb | 1484 | return builtin_type (gdbarch)->builtin_int; |
cc17453a EZ |
1485 | } |
1486 | ||
dda63807 AS |
1487 | /* Is a register in a reggroup? |
1488 | The default code in reggroup.c doesn't identify system registers, some | |
1489 | float registers or any of the vector registers. | |
1490 | TODO: sh2a and dsp registers. */ | |
63807e1d | 1491 | static int |
dda63807 AS |
1492 | sh_register_reggroup_p (struct gdbarch *gdbarch, int regnum, |
1493 | struct reggroup *reggroup) | |
1494 | { | |
b47193f7 UW |
1495 | if (gdbarch_register_name (gdbarch, regnum) == NULL |
1496 | || *gdbarch_register_name (gdbarch, regnum) == '\0') | |
dda63807 AS |
1497 | return 0; |
1498 | ||
1499 | if (reggroup == float_reggroup | |
1500 | && (regnum == FPUL_REGNUM | |
1501 | || regnum == FPSCR_REGNUM)) | |
1502 | return 1; | |
1503 | ||
1504 | if (regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM) | |
1505 | { | |
1506 | if (reggroup == vector_reggroup || reggroup == float_reggroup) | |
1507 | return 1; | |
1508 | if (reggroup == general_reggroup) | |
1509 | return 0; | |
1510 | } | |
1511 | ||
1512 | if (regnum == VBR_REGNUM | |
1513 | || regnum == SR_REGNUM | |
1514 | || regnum == FPSCR_REGNUM | |
1515 | || regnum == SSR_REGNUM | |
1516 | || regnum == SPC_REGNUM) | |
1517 | { | |
1518 | if (reggroup == system_reggroup) | |
1519 | return 1; | |
1520 | if (reggroup == general_reggroup) | |
1521 | return 0; | |
1522 | } | |
1523 | ||
1524 | /* The default code can cope with any other registers. */ | |
1525 | return default_register_reggroup_p (gdbarch, regnum, reggroup); | |
1526 | } | |
1527 | ||
fb409745 | 1528 | /* On the sh4, the DRi pseudo registers are problematic if the target |
c378eb4e | 1529 | is little endian. When the user writes one of those registers, for |
a6521d9a | 1530 | instance with 'set var $dr0=1', we want the double to be stored |
fb409745 | 1531 | like this: |
a6521d9a TS |
1532 | fr0 = 0x00 0x00 0xf0 0x3f |
1533 | fr1 = 0x00 0x00 0x00 0x00 | |
fb409745 EZ |
1534 | |
1535 | This corresponds to little endian byte order & big endian word | |
1536 | order. However if we let gdb write the register w/o conversion, it | |
1537 | will write fr0 and fr1 this way: | |
a6521d9a TS |
1538 | fr0 = 0x00 0x00 0x00 0x00 |
1539 | fr1 = 0x00 0x00 0xf0 0x3f | |
fb409745 EZ |
1540 | because it will consider fr0 and fr1 as a single LE stretch of memory. |
1541 | ||
1542 | To achieve what we want we must force gdb to store things in | |
1543 | floatformat_ieee_double_littlebyte_bigword (which is defined in | |
1544 | include/floatformat.h and libiberty/floatformat.c. | |
1545 | ||
1546 | In case the target is big endian, there is no problem, the | |
1547 | raw bytes will look like: | |
a6521d9a TS |
1548 | fr0 = 0x3f 0xf0 0x00 0x00 |
1549 | fr1 = 0x00 0x00 0x00 0x00 | |
fb409745 EZ |
1550 | |
1551 | The other pseudo registers (the FVs) also don't pose a problem | |
c378eb4e | 1552 | because they are stored as 4 individual FP elements. */ |
fb409745 | 1553 | |
96a5a1d3 UW |
1554 | static struct type * |
1555 | sh_littlebyte_bigword_type (struct gdbarch *gdbarch) | |
1556 | { | |
1557 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1558 | ||
1559 | if (tdep->sh_littlebyte_bigword_type == NULL) | |
1560 | tdep->sh_littlebyte_bigword_type | |
1561 | = arch_float_type (gdbarch, -1, "builtin_type_sh_littlebyte_bigword", | |
1562 | floatformats_ieee_double_littlebyte_bigword); | |
1563 | ||
1564 | return tdep->sh_littlebyte_bigword_type; | |
1565 | } | |
1566 | ||
7bd872fe | 1567 | static void |
a6521d9a | 1568 | sh_register_convert_to_virtual (struct gdbarch *gdbarch, int regnum, |
948f8e3d | 1569 | struct type *type, gdb_byte *from, gdb_byte *to) |
55ff77ac | 1570 | { |
a6521d9a TS |
1571 | if (gdbarch_byte_order (gdbarch) != BFD_ENDIAN_LITTLE) |
1572 | { | |
1573 | /* It is a no-op. */ | |
1574 | memcpy (to, from, register_size (gdbarch, regnum)); | |
1575 | return; | |
1576 | } | |
1577 | ||
617daa0e | 1578 | if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM) |
3b2ca824 UW |
1579 | target_float_convert (from, sh_littlebyte_bigword_type (gdbarch), |
1580 | to, type); | |
283150cd | 1581 | else |
617daa0e CV |
1582 | error |
1583 | ("sh_register_convert_to_virtual called with non DR register number"); | |
283150cd EZ |
1584 | } |
1585 | ||
1586 | static void | |
a6521d9a | 1587 | sh_register_convert_to_raw (struct gdbarch *gdbarch, struct type *type, |
948f8e3d | 1588 | int regnum, const gdb_byte *from, gdb_byte *to) |
283150cd | 1589 | { |
a6521d9a TS |
1590 | if (gdbarch_byte_order (gdbarch) != BFD_ENDIAN_LITTLE) |
1591 | { | |
1592 | /* It is a no-op. */ | |
1593 | memcpy (to, from, register_size (gdbarch, regnum)); | |
1594 | return; | |
1595 | } | |
1596 | ||
617daa0e | 1597 | if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM) |
3b2ca824 UW |
1598 | target_float_convert (from, type, |
1599 | to, sh_littlebyte_bigword_type (gdbarch)); | |
283150cd | 1600 | else |
8a3fe4f8 | 1601 | error (_("sh_register_convert_to_raw called with non DR register number")); |
283150cd EZ |
1602 | } |
1603 | ||
c378eb4e | 1604 | /* For vectors of 4 floating point registers. */ |
1c0159e0 | 1605 | static int |
d93859e2 | 1606 | fv_reg_base_num (struct gdbarch *gdbarch, int fv_regnum) |
1c0159e0 CV |
1607 | { |
1608 | int fp_regnum; | |
1609 | ||
d93859e2 | 1610 | fp_regnum = gdbarch_fp0_regnum (gdbarch) |
3e8c568d | 1611 | + (fv_regnum - FV0_REGNUM) * 4; |
1c0159e0 CV |
1612 | return fp_regnum; |
1613 | } | |
1614 | ||
c378eb4e | 1615 | /* For double precision floating point registers, i.e 2 fp regs. */ |
1c0159e0 | 1616 | static int |
d93859e2 | 1617 | dr_reg_base_num (struct gdbarch *gdbarch, int dr_regnum) |
1c0159e0 CV |
1618 | { |
1619 | int fp_regnum; | |
1620 | ||
d93859e2 | 1621 | fp_regnum = gdbarch_fp0_regnum (gdbarch) |
3e8c568d | 1622 | + (dr_regnum - DR0_REGNUM) * 2; |
1c0159e0 CV |
1623 | return fp_regnum; |
1624 | } | |
1625 | ||
05d1431c PA |
1626 | /* Concatenate PORTIONS contiguous raw registers starting at |
1627 | BASE_REGNUM into BUFFER. */ | |
1628 | ||
1629 | static enum register_status | |
1630 | pseudo_register_read_portions (struct gdbarch *gdbarch, | |
1631 | struct regcache *regcache, | |
1632 | int portions, | |
1633 | int base_regnum, gdb_byte *buffer) | |
1634 | { | |
1635 | int portion; | |
1636 | ||
1637 | for (portion = 0; portion < portions; portion++) | |
1638 | { | |
1639 | enum register_status status; | |
1640 | gdb_byte *b; | |
1641 | ||
1642 | b = buffer + register_size (gdbarch, base_regnum) * portion; | |
1643 | status = regcache_raw_read (regcache, base_regnum + portion, b); | |
1644 | if (status != REG_VALID) | |
1645 | return status; | |
1646 | } | |
1647 | ||
1648 | return REG_VALID; | |
1649 | } | |
1650 | ||
1651 | static enum register_status | |
d8124050 | 1652 | sh_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, |
18cf8b5b | 1653 | int reg_nr, gdb_byte *buffer) |
53116e27 | 1654 | { |
05d1431c | 1655 | int base_regnum; |
05d1431c | 1656 | enum register_status status; |
53116e27 | 1657 | |
9bed62d7 | 1658 | if (reg_nr == PSEUDO_BANK_REGNUM) |
05d1431c PA |
1659 | return regcache_raw_read (regcache, BANK_REGNUM, buffer); |
1660 | else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM) | |
7bd872fe | 1661 | { |
4a8a33c8 AH |
1662 | /* Enough space for two float registers. */ |
1663 | gdb_byte temp_buffer[4 * 2]; | |
d93859e2 | 1664 | base_regnum = dr_reg_base_num (gdbarch, reg_nr); |
7bd872fe | 1665 | |
c378eb4e | 1666 | /* Build the value in the provided buffer. */ |
7bd872fe | 1667 | /* Read the real regs for which this one is an alias. */ |
05d1431c PA |
1668 | status = pseudo_register_read_portions (gdbarch, regcache, |
1669 | 2, base_regnum, temp_buffer); | |
1670 | if (status == REG_VALID) | |
1671 | { | |
1672 | /* We must pay attention to the endiannes. */ | |
a6521d9a | 1673 | sh_register_convert_to_virtual (gdbarch, reg_nr, |
05d1431c PA |
1674 | register_type (gdbarch, reg_nr), |
1675 | temp_buffer, buffer); | |
1676 | } | |
1677 | return status; | |
7bd872fe | 1678 | } |
617daa0e | 1679 | else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM) |
53116e27 | 1680 | { |
d93859e2 | 1681 | base_regnum = fv_reg_base_num (gdbarch, reg_nr); |
7bd872fe EZ |
1682 | |
1683 | /* Read the real regs for which this one is an alias. */ | |
05d1431c PA |
1684 | return pseudo_register_read_portions (gdbarch, regcache, |
1685 | 4, base_regnum, buffer); | |
53116e27 | 1686 | } |
05d1431c PA |
1687 | else |
1688 | gdb_assert_not_reached ("invalid pseudo register number"); | |
53116e27 EZ |
1689 | } |
1690 | ||
a78f21af | 1691 | static void |
d8124050 | 1692 | sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, |
18cf8b5b | 1693 | int reg_nr, const gdb_byte *buffer) |
53116e27 EZ |
1694 | { |
1695 | int base_regnum, portion; | |
1696 | ||
9bed62d7 CV |
1697 | if (reg_nr == PSEUDO_BANK_REGNUM) |
1698 | { | |
1699 | /* When the bank register is written to, the whole register bank | |
1700 | is switched and all values in the bank registers must be read | |
c378eb4e | 1701 | from the target/sim again. We're just invalidating the regcache |
9bed62d7 CV |
1702 | so that a re-read happens next time it's necessary. */ |
1703 | int bregnum; | |
1704 | ||
1705 | regcache_raw_write (regcache, BANK_REGNUM, buffer); | |
1706 | for (bregnum = R0_BANK0_REGNUM; bregnum < MACLB_REGNUM; ++bregnum) | |
9c5ea4d9 | 1707 | regcache_invalidate (regcache, bregnum); |
9bed62d7 CV |
1708 | } |
1709 | else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM) | |
53116e27 | 1710 | { |
4a8a33c8 AH |
1711 | /* Enough space for two float registers. */ |
1712 | gdb_byte temp_buffer[4 * 2]; | |
d93859e2 | 1713 | base_regnum = dr_reg_base_num (gdbarch, reg_nr); |
53116e27 | 1714 | |
c378eb4e | 1715 | /* We must pay attention to the endiannes. */ |
a6521d9a | 1716 | sh_register_convert_to_raw (gdbarch, register_type (gdbarch, reg_nr), |
b66ba949 | 1717 | reg_nr, buffer, temp_buffer); |
7bd872fe | 1718 | |
53116e27 EZ |
1719 | /* Write the real regs for which this one is an alias. */ |
1720 | for (portion = 0; portion < 2; portion++) | |
617daa0e | 1721 | regcache_raw_write (regcache, base_regnum + portion, |
0818c12a | 1722 | (temp_buffer |
617daa0e CV |
1723 | + register_size (gdbarch, |
1724 | base_regnum) * portion)); | |
53116e27 | 1725 | } |
617daa0e | 1726 | else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM) |
53116e27 | 1727 | { |
d93859e2 | 1728 | base_regnum = fv_reg_base_num (gdbarch, reg_nr); |
53116e27 EZ |
1729 | |
1730 | /* Write the real regs for which this one is an alias. */ | |
1731 | for (portion = 0; portion < 4; portion++) | |
d8124050 | 1732 | regcache_raw_write (regcache, base_regnum + portion, |
948f8e3d | 1733 | (buffer |
617daa0e CV |
1734 | + register_size (gdbarch, |
1735 | base_regnum) * portion)); | |
53116e27 EZ |
1736 | } |
1737 | } | |
1738 | ||
2f14585c | 1739 | static int |
e7faf938 | 1740 | sh_dsp_register_sim_regno (struct gdbarch *gdbarch, int nr) |
2f14585c | 1741 | { |
e7faf938 MD |
1742 | if (legacy_register_sim_regno (gdbarch, nr) < 0) |
1743 | return legacy_register_sim_regno (gdbarch, nr); | |
f2ea0907 CV |
1744 | if (nr >= DSR_REGNUM && nr <= Y1_REGNUM) |
1745 | return nr - DSR_REGNUM + SIM_SH_DSR_REGNUM; | |
1746 | if (nr == MOD_REGNUM) | |
2f14585c | 1747 | return SIM_SH_MOD_REGNUM; |
f2ea0907 | 1748 | if (nr == RS_REGNUM) |
2f14585c | 1749 | return SIM_SH_RS_REGNUM; |
f2ea0907 | 1750 | if (nr == RE_REGNUM) |
2f14585c | 1751 | return SIM_SH_RE_REGNUM; |
76cd2bd9 CV |
1752 | if (nr >= DSP_R0_BANK_REGNUM && nr <= DSP_R7_BANK_REGNUM) |
1753 | return nr - DSP_R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM; | |
2f14585c JR |
1754 | return nr; |
1755 | } | |
1c0159e0 | 1756 | |
da962468 | 1757 | static int |
e7faf938 | 1758 | sh_sh2a_register_sim_regno (struct gdbarch *gdbarch, int nr) |
da962468 CV |
1759 | { |
1760 | switch (nr) | |
1761 | { | |
1762 | case TBR_REGNUM: | |
1763 | return SIM_SH_TBR_REGNUM; | |
1764 | case IBNR_REGNUM: | |
1765 | return SIM_SH_IBNR_REGNUM; | |
1766 | case IBCR_REGNUM: | |
1767 | return SIM_SH_IBCR_REGNUM; | |
1768 | case BANK_REGNUM: | |
1769 | return SIM_SH_BANK_REGNUM; | |
1770 | case MACLB_REGNUM: | |
1771 | return SIM_SH_BANK_MACL_REGNUM; | |
1772 | case GBRB_REGNUM: | |
1773 | return SIM_SH_BANK_GBR_REGNUM; | |
1774 | case PRB_REGNUM: | |
1775 | return SIM_SH_BANK_PR_REGNUM; | |
1776 | case IVNB_REGNUM: | |
1777 | return SIM_SH_BANK_IVN_REGNUM; | |
1778 | case MACHB_REGNUM: | |
1779 | return SIM_SH_BANK_MACH_REGNUM; | |
1780 | default: | |
1781 | break; | |
1782 | } | |
e7faf938 | 1783 | return legacy_register_sim_regno (gdbarch, nr); |
da962468 CV |
1784 | } |
1785 | ||
357d3800 AS |
1786 | /* Set up the register unwinding such that call-clobbered registers are |
1787 | not displayed in frames >0 because the true value is not certain. | |
1788 | The 'undefined' registers will show up as 'not available' unless the | |
1789 | CFI says otherwise. | |
1790 | ||
1791 | This function is currently set up for SH4 and compatible only. */ | |
1792 | ||
1793 | static void | |
1794 | sh_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
aff37fc1 | 1795 | struct dwarf2_frame_state_reg *reg, |
4a4e5149 | 1796 | struct frame_info *this_frame) |
357d3800 AS |
1797 | { |
1798 | /* Mark the PC as the destination for the return address. */ | |
b47193f7 | 1799 | if (regnum == gdbarch_pc_regnum (gdbarch)) |
357d3800 AS |
1800 | reg->how = DWARF2_FRAME_REG_RA; |
1801 | ||
1802 | /* Mark the stack pointer as the call frame address. */ | |
b47193f7 | 1803 | else if (regnum == gdbarch_sp_regnum (gdbarch)) |
357d3800 AS |
1804 | reg->how = DWARF2_FRAME_REG_CFA; |
1805 | ||
1806 | /* The above was taken from the default init_reg in dwarf2-frame.c | |
1807 | while the below is SH specific. */ | |
1808 | ||
1809 | /* Caller save registers. */ | |
1810 | else if ((regnum >= R0_REGNUM && regnum <= R0_REGNUM+7) | |
1811 | || (regnum >= FR0_REGNUM && regnum <= FR0_REGNUM+11) | |
1812 | || (regnum >= DR0_REGNUM && regnum <= DR0_REGNUM+5) | |
1813 | || (regnum >= FV0_REGNUM && regnum <= FV0_REGNUM+2) | |
1814 | || (regnum == MACH_REGNUM) | |
1815 | || (regnum == MACL_REGNUM) | |
1816 | || (regnum == FPUL_REGNUM) | |
1817 | || (regnum == SR_REGNUM)) | |
1818 | reg->how = DWARF2_FRAME_REG_UNDEFINED; | |
1819 | ||
1820 | /* Callee save registers. */ | |
1821 | else if ((regnum >= R0_REGNUM+8 && regnum <= R0_REGNUM+15) | |
1822 | || (regnum >= FR0_REGNUM+12 && regnum <= FR0_REGNUM+15) | |
1823 | || (regnum >= DR0_REGNUM+6 && regnum <= DR0_REGNUM+8) | |
1824 | || (regnum == FV0_REGNUM+3)) | |
1825 | reg->how = DWARF2_FRAME_REG_SAME_VALUE; | |
1826 | ||
1827 | /* Other registers. These are not in the ABI and may or may not | |
1828 | mean anything in frames >0 so don't show them. */ | |
1829 | else if ((regnum >= R0_BANK0_REGNUM && regnum <= R0_BANK0_REGNUM+15) | |
1830 | || (regnum == GBR_REGNUM) | |
1831 | || (regnum == VBR_REGNUM) | |
1832 | || (regnum == FPSCR_REGNUM) | |
1833 | || (regnum == SSR_REGNUM) | |
1834 | || (regnum == SPC_REGNUM)) | |
1835 | reg->how = DWARF2_FRAME_REG_UNDEFINED; | |
1836 | } | |
1837 | ||
1c0159e0 CV |
1838 | static struct sh_frame_cache * |
1839 | sh_alloc_frame_cache (void) | |
1840 | { | |
1841 | struct sh_frame_cache *cache; | |
1842 | int i; | |
1843 | ||
1844 | cache = FRAME_OBSTACK_ZALLOC (struct sh_frame_cache); | |
1845 | ||
1846 | /* Base address. */ | |
1847 | cache->base = 0; | |
1848 | cache->saved_sp = 0; | |
1849 | cache->sp_offset = 0; | |
1850 | cache->pc = 0; | |
1851 | ||
1852 | /* Frameless until proven otherwise. */ | |
1853 | cache->uses_fp = 0; | |
617daa0e | 1854 | |
1c0159e0 CV |
1855 | /* Saved registers. We initialize these to -1 since zero is a valid |
1856 | offset (that's where fp is supposed to be stored). */ | |
1857 | for (i = 0; i < SH_NUM_REGS; i++) | |
1858 | { | |
1859 | cache->saved_regs[i] = -1; | |
1860 | } | |
617daa0e | 1861 | |
1c0159e0 | 1862 | return cache; |
617daa0e | 1863 | } |
1c0159e0 CV |
1864 | |
1865 | static struct sh_frame_cache * | |
94afd7a6 | 1866 | sh_frame_cache (struct frame_info *this_frame, void **this_cache) |
1c0159e0 | 1867 | { |
e17a4113 | 1868 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1c0159e0 CV |
1869 | struct sh_frame_cache *cache; |
1870 | CORE_ADDR current_pc; | |
1871 | int i; | |
1872 | ||
1873 | if (*this_cache) | |
19ba03f4 | 1874 | return (struct sh_frame_cache *) *this_cache; |
1c0159e0 CV |
1875 | |
1876 | cache = sh_alloc_frame_cache (); | |
1877 | *this_cache = cache; | |
1878 | ||
1879 | /* In principle, for normal frames, fp holds the frame pointer, | |
1880 | which holds the base address for the current stack frame. | |
1881 | However, for functions that don't need it, the frame pointer is | |
1882 | optional. For these "frameless" functions the frame pointer is | |
c378eb4e | 1883 | actually the frame pointer of the calling frame. */ |
94afd7a6 | 1884 | cache->base = get_frame_register_unsigned (this_frame, FP_REGNUM); |
1c0159e0 CV |
1885 | if (cache->base == 0) |
1886 | return cache; | |
1887 | ||
94afd7a6 UW |
1888 | cache->pc = get_frame_func (this_frame); |
1889 | current_pc = get_frame_pc (this_frame); | |
1c0159e0 | 1890 | if (cache->pc != 0) |
d2ca4222 UW |
1891 | { |
1892 | ULONGEST fpscr; | |
9fc05685 KB |
1893 | |
1894 | /* Check for the existence of the FPSCR register. If it exists, | |
1895 | fetch its value for use in prologue analysis. Passing a zero | |
1896 | value is the best choice for architecture variants upon which | |
1897 | there's no FPSCR register. */ | |
1898 | if (gdbarch_register_reggroup_p (gdbarch, FPSCR_REGNUM, all_reggroup)) | |
1899 | fpscr = get_frame_register_unsigned (this_frame, FPSCR_REGNUM); | |
1900 | else | |
1901 | fpscr = 0; | |
1902 | ||
e17a4113 | 1903 | sh_analyze_prologue (gdbarch, cache->pc, current_pc, cache, fpscr); |
d2ca4222 | 1904 | } |
617daa0e | 1905 | |
1c0159e0 CV |
1906 | if (!cache->uses_fp) |
1907 | { | |
1908 | /* We didn't find a valid frame, which means that CACHE->base | |
1909 | currently holds the frame pointer for our calling frame. If | |
1910 | we're at the start of a function, or somewhere half-way its | |
1911 | prologue, the function's frame probably hasn't been fully | |
1912 | setup yet. Try to reconstruct the base address for the stack | |
1913 | frame by looking at the stack pointer. For truly "frameless" | |
1914 | functions this might work too. */ | |
94afd7a6 | 1915 | cache->base = get_frame_register_unsigned |
e17a4113 | 1916 | (this_frame, gdbarch_sp_regnum (gdbarch)); |
1c0159e0 CV |
1917 | } |
1918 | ||
1919 | /* Now that we have the base address for the stack frame we can | |
1920 | calculate the value of sp in the calling frame. */ | |
1921 | cache->saved_sp = cache->base + cache->sp_offset; | |
1922 | ||
1923 | /* Adjust all the saved registers such that they contain addresses | |
1924 | instead of offsets. */ | |
1925 | for (i = 0; i < SH_NUM_REGS; i++) | |
1926 | if (cache->saved_regs[i] != -1) | |
1927 | cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i] - 4; | |
1928 | ||
1929 | return cache; | |
1930 | } | |
1931 | ||
94afd7a6 UW |
1932 | static struct value * |
1933 | sh_frame_prev_register (struct frame_info *this_frame, | |
1934 | void **this_cache, int regnum) | |
1c0159e0 | 1935 | { |
94afd7a6 UW |
1936 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1937 | struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache); | |
1c0159e0 CV |
1938 | |
1939 | gdb_assert (regnum >= 0); | |
1940 | ||
b47193f7 | 1941 | if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp) |
94afd7a6 | 1942 | return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp); |
1c0159e0 CV |
1943 | |
1944 | /* The PC of the previous frame is stored in the PR register of | |
1945 | the current frame. Frob regnum so that we pull the value from | |
1946 | the correct place. */ | |
b47193f7 | 1947 | if (regnum == gdbarch_pc_regnum (gdbarch)) |
1c0159e0 CV |
1948 | regnum = PR_REGNUM; |
1949 | ||
1950 | if (regnum < SH_NUM_REGS && cache->saved_regs[regnum] != -1) | |
94afd7a6 UW |
1951 | return frame_unwind_got_memory (this_frame, regnum, |
1952 | cache->saved_regs[regnum]); | |
1c0159e0 | 1953 | |
94afd7a6 | 1954 | return frame_unwind_got_register (this_frame, regnum, regnum); |
1c0159e0 CV |
1955 | } |
1956 | ||
1957 | static void | |
94afd7a6 | 1958 | sh_frame_this_id (struct frame_info *this_frame, void **this_cache, |
617daa0e CV |
1959 | struct frame_id *this_id) |
1960 | { | |
94afd7a6 | 1961 | struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache); |
1c0159e0 CV |
1962 | |
1963 | /* This marks the outermost frame. */ | |
1964 | if (cache->base == 0) | |
1965 | return; | |
1966 | ||
1967 | *this_id = frame_id_build (cache->saved_sp, cache->pc); | |
617daa0e | 1968 | } |
1c0159e0 | 1969 | |
617daa0e | 1970 | static const struct frame_unwind sh_frame_unwind = { |
1c0159e0 | 1971 | NORMAL_FRAME, |
8fbca658 | 1972 | default_frame_unwind_stop_reason, |
1c0159e0 | 1973 | sh_frame_this_id, |
94afd7a6 UW |
1974 | sh_frame_prev_register, |
1975 | NULL, | |
1976 | default_frame_sniffer | |
1c0159e0 CV |
1977 | }; |
1978 | ||
1c0159e0 CV |
1979 | static CORE_ADDR |
1980 | sh_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1981 | { | |
3e8c568d | 1982 | return frame_unwind_register_unsigned (next_frame, |
b47193f7 | 1983 | gdbarch_sp_regnum (gdbarch)); |
1c0159e0 CV |
1984 | } |
1985 | ||
1986 | static CORE_ADDR | |
1987 | sh_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1988 | { | |
3e8c568d | 1989 | return frame_unwind_register_unsigned (next_frame, |
b47193f7 | 1990 | gdbarch_pc_regnum (gdbarch)); |
1c0159e0 CV |
1991 | } |
1992 | ||
1993 | static struct frame_id | |
94afd7a6 | 1994 | sh_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
1c0159e0 | 1995 | { |
94afd7a6 UW |
1996 | CORE_ADDR sp = get_frame_register_unsigned (this_frame, |
1997 | gdbarch_sp_regnum (gdbarch)); | |
1998 | return frame_id_build (sp, get_frame_pc (this_frame)); | |
1c0159e0 CV |
1999 | } |
2000 | ||
2001 | static CORE_ADDR | |
94afd7a6 | 2002 | sh_frame_base_address (struct frame_info *this_frame, void **this_cache) |
617daa0e | 2003 | { |
94afd7a6 | 2004 | struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache); |
617daa0e | 2005 | |
1c0159e0 CV |
2006 | return cache->base; |
2007 | } | |
617daa0e CV |
2008 | |
2009 | static const struct frame_base sh_frame_base = { | |
1c0159e0 CV |
2010 | &sh_frame_unwind, |
2011 | sh_frame_base_address, | |
2012 | sh_frame_base_address, | |
2013 | sh_frame_base_address | |
617daa0e | 2014 | }; |
1c0159e0 | 2015 | |
cb2cf4ce TS |
2016 | static struct sh_frame_cache * |
2017 | sh_make_stub_cache (struct frame_info *this_frame) | |
2018 | { | |
2019 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2020 | struct sh_frame_cache *cache; | |
2021 | ||
2022 | cache = sh_alloc_frame_cache (); | |
2023 | ||
2024 | cache->saved_sp | |
2025 | = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch)); | |
2026 | ||
2027 | return cache; | |
2028 | } | |
2029 | ||
2030 | static void | |
2031 | sh_stub_this_id (struct frame_info *this_frame, void **this_cache, | |
2032 | struct frame_id *this_id) | |
2033 | { | |
2034 | struct sh_frame_cache *cache; | |
2035 | ||
2036 | if (*this_cache == NULL) | |
2037 | *this_cache = sh_make_stub_cache (this_frame); | |
19ba03f4 | 2038 | cache = (struct sh_frame_cache *) *this_cache; |
cb2cf4ce TS |
2039 | |
2040 | *this_id = frame_id_build (cache->saved_sp, get_frame_pc (this_frame)); | |
2041 | } | |
2042 | ||
2043 | static int | |
2044 | sh_stub_unwind_sniffer (const struct frame_unwind *self, | |
2045 | struct frame_info *this_frame, | |
2046 | void **this_prologue_cache) | |
2047 | { | |
2048 | CORE_ADDR addr_in_block; | |
2049 | ||
2050 | addr_in_block = get_frame_address_in_block (this_frame); | |
3e5d3a5a | 2051 | if (in_plt_section (addr_in_block)) |
cb2cf4ce TS |
2052 | return 1; |
2053 | ||
2054 | return 0; | |
2055 | } | |
2056 | ||
2057 | static const struct frame_unwind sh_stub_unwind = | |
2058 | { | |
2059 | NORMAL_FRAME, | |
2060 | default_frame_unwind_stop_reason, | |
2061 | sh_stub_this_id, | |
2062 | sh_frame_prev_register, | |
2063 | NULL, | |
2064 | sh_stub_unwind_sniffer | |
2065 | }; | |
2066 | ||
c9cf6e20 MG |
2067 | /* Implement the stack_frame_destroyed_p gdbarch method. |
2068 | ||
2069 | The epilogue is defined here as the area at the end of a function, | |
1c0159e0 | 2070 | either on the `ret' instruction itself or after an instruction which |
c378eb4e | 2071 | destroys the function's stack frame. */ |
c9cf6e20 | 2072 | |
1c0159e0 | 2073 | static int |
c9cf6e20 | 2074 | sh_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
1c0159e0 | 2075 | { |
e17a4113 | 2076 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1c0159e0 CV |
2077 | CORE_ADDR func_addr = 0, func_end = 0; |
2078 | ||
2079 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
2080 | { | |
2081 | ULONGEST inst; | |
2082 | /* The sh epilogue is max. 14 bytes long. Give another 14 bytes | |
2083 | for a nop and some fixed data (e.g. big offsets) which are | |
617daa0e | 2084 | unfortunately also treated as part of the function (which |
c378eb4e | 2085 | means, they are below func_end. */ |
1c0159e0 CV |
2086 | CORE_ADDR addr = func_end - 28; |
2087 | if (addr < func_addr + 4) | |
617daa0e | 2088 | addr = func_addr + 4; |
1c0159e0 CV |
2089 | if (pc < addr) |
2090 | return 0; | |
2091 | ||
c378eb4e | 2092 | /* First search forward until hitting an rts. */ |
1c0159e0 | 2093 | while (addr < func_end |
e17a4113 | 2094 | && !IS_RTS (read_memory_unsigned_integer (addr, 2, byte_order))) |
1c0159e0 CV |
2095 | addr += 2; |
2096 | if (addr >= func_end) | |
617daa0e | 2097 | return 0; |
1c0159e0 CV |
2098 | |
2099 | /* At this point we should find a mov.l @r15+,r14 instruction, | |
2100 | either before or after the rts. If not, then the function has | |
c378eb4e | 2101 | probably no "normal" epilogue and we bail out here. */ |
e17a4113 UW |
2102 | inst = read_memory_unsigned_integer (addr - 2, 2, byte_order); |
2103 | if (IS_RESTORE_FP (read_memory_unsigned_integer (addr - 2, 2, | |
2104 | byte_order))) | |
617daa0e | 2105 | addr -= 2; |
e17a4113 UW |
2106 | else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr + 2, 2, |
2107 | byte_order))) | |
1c0159e0 CV |
2108 | return 0; |
2109 | ||
e17a4113 | 2110 | inst = read_memory_unsigned_integer (addr - 2, 2, byte_order); |
03131d99 | 2111 | |
c378eb4e | 2112 | /* Step over possible lds.l @r15+,macl. */ |
03131d99 CV |
2113 | if (IS_MACL_LDS (inst)) |
2114 | { | |
2115 | addr -= 2; | |
e17a4113 | 2116 | inst = read_memory_unsigned_integer (addr - 2, 2, byte_order); |
03131d99 CV |
2117 | } |
2118 | ||
c378eb4e | 2119 | /* Step over possible lds.l @r15+,pr. */ |
1c0159e0 | 2120 | if (IS_LDS (inst)) |
617daa0e | 2121 | { |
1c0159e0 | 2122 | addr -= 2; |
e17a4113 | 2123 | inst = read_memory_unsigned_integer (addr - 2, 2, byte_order); |
1c0159e0 CV |
2124 | } |
2125 | ||
c378eb4e | 2126 | /* Step over possible mov r14,r15. */ |
1c0159e0 | 2127 | if (IS_MOV_FP_SP (inst)) |
617daa0e | 2128 | { |
1c0159e0 | 2129 | addr -= 2; |
e17a4113 | 2130 | inst = read_memory_unsigned_integer (addr - 2, 2, byte_order); |
1c0159e0 CV |
2131 | } |
2132 | ||
2133 | /* Now check for FP adjustments, using add #imm,r14 or add rX, r14 | |
c378eb4e | 2134 | instructions. */ |
1c0159e0 | 2135 | while (addr > func_addr + 4 |
617daa0e | 2136 | && (IS_ADD_REG_TO_FP (inst) || IS_ADD_IMM_FP (inst))) |
1c0159e0 CV |
2137 | { |
2138 | addr -= 2; | |
e17a4113 | 2139 | inst = read_memory_unsigned_integer (addr - 2, 2, byte_order); |
1c0159e0 CV |
2140 | } |
2141 | ||
03131d99 CV |
2142 | /* On SH2a check if the previous instruction was perhaps a MOVI20. |
2143 | That's allowed for the epilogue. */ | |
2144 | if ((gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a | |
2145 | || gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a_nofpu) | |
2146 | && addr > func_addr + 6 | |
e17a4113 UW |
2147 | && IS_MOVI20 (read_memory_unsigned_integer (addr - 4, 2, |
2148 | byte_order))) | |
03131d99 CV |
2149 | addr -= 4; |
2150 | ||
1c0159e0 CV |
2151 | if (pc >= addr) |
2152 | return 1; | |
2153 | } | |
2154 | return 0; | |
2155 | } | |
c9ac0a72 AS |
2156 | |
2157 | ||
2158 | /* Supply register REGNUM from the buffer specified by REGS and LEN | |
2159 | in the register set REGSET to register cache REGCACHE. | |
2160 | REGTABLE specifies where each register can be found in REGS. | |
2161 | If REGNUM is -1, do this for all registers in REGSET. */ | |
2162 | ||
2163 | void | |
2164 | sh_corefile_supply_regset (const struct regset *regset, | |
2165 | struct regcache *regcache, | |
2166 | int regnum, const void *regs, size_t len) | |
2167 | { | |
ac7936df | 2168 | struct gdbarch *gdbarch = regcache->arch (); |
c9ac0a72 AS |
2169 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2170 | const struct sh_corefile_regmap *regmap = (regset == &sh_corefile_gregset | |
2171 | ? tdep->core_gregmap | |
2172 | : tdep->core_fpregmap); | |
2173 | int i; | |
2174 | ||
2175 | for (i = 0; regmap[i].regnum != -1; i++) | |
2176 | { | |
2177 | if ((regnum == -1 || regnum == regmap[i].regnum) | |
2178 | && regmap[i].offset + 4 <= len) | |
2179 | regcache_raw_supply (regcache, regmap[i].regnum, | |
2180 | (char *)regs + regmap[i].offset); | |
2181 | } | |
2182 | } | |
2183 | ||
2184 | /* Collect register REGNUM in the register set REGSET from register cache | |
2185 | REGCACHE into the buffer specified by REGS and LEN. | |
2186 | REGTABLE specifies where each register can be found in REGS. | |
2187 | If REGNUM is -1, do this for all registers in REGSET. */ | |
2188 | ||
2189 | void | |
2190 | sh_corefile_collect_regset (const struct regset *regset, | |
2191 | const struct regcache *regcache, | |
2192 | int regnum, void *regs, size_t len) | |
2193 | { | |
ac7936df | 2194 | struct gdbarch *gdbarch = regcache->arch (); |
c9ac0a72 AS |
2195 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2196 | const struct sh_corefile_regmap *regmap = (regset == &sh_corefile_gregset | |
2197 | ? tdep->core_gregmap | |
2198 | : tdep->core_fpregmap); | |
2199 | int i; | |
2200 | ||
2201 | for (i = 0; regmap[i].regnum != -1; i++) | |
2202 | { | |
2203 | if ((regnum == -1 || regnum == regmap[i].regnum) | |
2204 | && regmap[i].offset + 4 <= len) | |
2205 | regcache_raw_collect (regcache, regmap[i].regnum, | |
2206 | (char *)regs + regmap[i].offset); | |
2207 | } | |
2208 | } | |
2209 | ||
2210 | /* The following two regsets have the same contents, so it is tempting to | |
2211 | unify them, but they are distiguished by their address, so don't. */ | |
2212 | ||
3ca7dae4 | 2213 | const struct regset sh_corefile_gregset = |
c9ac0a72 AS |
2214 | { |
2215 | NULL, | |
2216 | sh_corefile_supply_regset, | |
2217 | sh_corefile_collect_regset | |
2218 | }; | |
2219 | ||
3ca7dae4 | 2220 | static const struct regset sh_corefile_fpregset = |
c9ac0a72 AS |
2221 | { |
2222 | NULL, | |
2223 | sh_corefile_supply_regset, | |
2224 | sh_corefile_collect_regset | |
2225 | }; | |
2226 | ||
c6d41a6f AA |
2227 | static void |
2228 | sh_iterate_over_regset_sections (struct gdbarch *gdbarch, | |
2229 | iterate_over_regset_sections_cb *cb, | |
2230 | void *cb_data, | |
2231 | const struct regcache *regcache) | |
c9ac0a72 AS |
2232 | { |
2233 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2234 | ||
c6d41a6f AA |
2235 | if (tdep->core_gregmap != NULL) |
2236 | cb (".reg", tdep->sizeof_gregset, &sh_corefile_gregset, NULL, cb_data); | |
c9ac0a72 | 2237 | |
c6d41a6f AA |
2238 | if (tdep->core_fpregmap != NULL) |
2239 | cb (".reg2", tdep->sizeof_fpregset, &sh_corefile_fpregset, NULL, cb_data); | |
c9ac0a72 | 2240 | } |
18648a37 YQ |
2241 | |
2242 | /* This is the implementation of gdbarch method | |
2243 | return_in_first_hidden_param_p. */ | |
2244 | ||
2245 | static int | |
2246 | sh_return_in_first_hidden_param_p (struct gdbarch *gdbarch, | |
2247 | struct type *type) | |
2248 | { | |
2249 | return 0; | |
2250 | } | |
2251 | ||
ccf00f21 | 2252 | \f |
cc17453a EZ |
2253 | |
2254 | static struct gdbarch * | |
fba45db2 | 2255 | sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
cc17453a | 2256 | { |
cc17453a | 2257 | struct gdbarch *gdbarch; |
c9ac0a72 | 2258 | struct gdbarch_tdep *tdep; |
d658f924 | 2259 | |
2d4c29c5 TS |
2260 | /* SH5 is handled entirely in sh64-tdep.c. */ |
2261 | if (info.bfd_arch_info->mach == bfd_mach_sh5) | |
2262 | return sh64_gdbarch_init (info, arches); | |
55ff77ac | 2263 | |
4be87837 DJ |
2264 | /* If there is already a candidate, use it. */ |
2265 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
2266 | if (arches != NULL) | |
2267 | return arches->gdbarch; | |
cc17453a EZ |
2268 | |
2269 | /* None found, create a new architecture from the information | |
c378eb4e | 2270 | provided. */ |
41bf6aca | 2271 | tdep = XCNEW (struct gdbarch_tdep); |
c9ac0a72 | 2272 | gdbarch = gdbarch_alloc (&info, tdep); |
cc17453a | 2273 | |
48db5a3c CV |
2274 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); |
2275 | set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
ec920329 | 2276 | set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
48db5a3c | 2277 | set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); |
53375380 PA |
2278 | |
2279 | set_gdbarch_wchar_bit (gdbarch, 2 * TARGET_CHAR_BIT); | |
2280 | set_gdbarch_wchar_signed (gdbarch, 0); | |
2281 | ||
48db5a3c CV |
2282 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
2283 | set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
2284 | set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
a38d2a54 | 2285 | set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
48db5a3c | 2286 | |
f2ea0907 | 2287 | set_gdbarch_num_regs (gdbarch, SH_NUM_REGS); |
a38d2a54 | 2288 | set_gdbarch_sp_regnum (gdbarch, 15); |
a38d2a54 | 2289 | set_gdbarch_pc_regnum (gdbarch, 16); |
48db5a3c CV |
2290 | set_gdbarch_fp0_regnum (gdbarch, -1); |
2291 | set_gdbarch_num_pseudo_regs (gdbarch, 0); | |
2292 | ||
1c0159e0 | 2293 | set_gdbarch_register_type (gdbarch, sh_default_register_type); |
dda63807 | 2294 | set_gdbarch_register_reggroup_p (gdbarch, sh_register_reggroup_p); |
1c0159e0 | 2295 | |
04180708 YQ |
2296 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, sh_breakpoint_kind_from_pc); |
2297 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, sh_sw_breakpoint_from_kind); | |
48db5a3c | 2298 | |
2f14585c | 2299 | set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno); |
48db5a3c | 2300 | |
c0409442 | 2301 | set_gdbarch_return_value (gdbarch, sh_return_value_nofpu); |
1c0159e0 | 2302 | |
48db5a3c CV |
2303 | set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue); |
2304 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
48db5a3c | 2305 | |
1c0159e0 | 2306 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu); |
18648a37 YQ |
2307 | set_gdbarch_return_in_first_hidden_param_p (gdbarch, |
2308 | sh_return_in_first_hidden_param_p); | |
1c0159e0 | 2309 | |
48db5a3c CV |
2310 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); |
2311 | ||
19f59343 | 2312 | set_gdbarch_frame_align (gdbarch, sh_frame_align); |
1c0159e0 CV |
2313 | set_gdbarch_unwind_sp (gdbarch, sh_unwind_sp); |
2314 | set_gdbarch_unwind_pc (gdbarch, sh_unwind_pc); | |
94afd7a6 | 2315 | set_gdbarch_dummy_id (gdbarch, sh_dummy_id); |
1c0159e0 CV |
2316 | frame_base_set_default (gdbarch, &sh_frame_base); |
2317 | ||
c9cf6e20 | 2318 | set_gdbarch_stack_frame_destroyed_p (gdbarch, sh_stack_frame_destroyed_p); |
cc17453a | 2319 | |
357d3800 AS |
2320 | dwarf2_frame_set_init_reg (gdbarch, sh_dwarf2_frame_init_reg); |
2321 | ||
c6d41a6f AA |
2322 | set_gdbarch_iterate_over_regset_sections |
2323 | (gdbarch, sh_iterate_over_regset_sections); | |
c9ac0a72 | 2324 | |
cc17453a | 2325 | switch (info.bfd_arch_info->mach) |
8db62801 | 2326 | { |
cc17453a | 2327 | case bfd_mach_sh: |
48db5a3c | 2328 | set_gdbarch_register_name (gdbarch, sh_sh_register_name); |
cc17453a | 2329 | break; |
1c0159e0 | 2330 | |
cc17453a | 2331 | case bfd_mach_sh2: |
48db5a3c | 2332 | set_gdbarch_register_name (gdbarch, sh_sh_register_name); |
617daa0e | 2333 | break; |
1c0159e0 | 2334 | |
2d188dd3 | 2335 | case bfd_mach_sh2e: |
c378eb4e | 2336 | /* doubles on sh2e and sh3e are actually 4 byte. */ |
48db5a3c | 2337 | set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
f92589cb | 2338 | set_gdbarch_double_format (gdbarch, floatformats_ieee_single); |
48db5a3c CV |
2339 | |
2340 | set_gdbarch_register_name (gdbarch, sh_sh2e_register_name); | |
48db5a3c | 2341 | set_gdbarch_register_type (gdbarch, sh_sh3e_register_type); |
2d188dd3 | 2342 | set_gdbarch_fp0_regnum (gdbarch, 25); |
c0409442 | 2343 | set_gdbarch_return_value (gdbarch, sh_return_value_fpu); |
6df2bf50 | 2344 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); |
2d188dd3 | 2345 | break; |
1c0159e0 | 2346 | |
da962468 CV |
2347 | case bfd_mach_sh2a: |
2348 | set_gdbarch_register_name (gdbarch, sh_sh2a_register_name); | |
2349 | set_gdbarch_register_type (gdbarch, sh_sh2a_register_type); | |
2350 | set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno); | |
2351 | ||
2352 | set_gdbarch_fp0_regnum (gdbarch, 25); | |
2353 | set_gdbarch_num_pseudo_regs (gdbarch, 9); | |
2354 | set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read); | |
2355 | set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write); | |
c0409442 | 2356 | set_gdbarch_return_value (gdbarch, sh_return_value_fpu); |
da962468 CV |
2357 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); |
2358 | break; | |
2359 | ||
2360 | case bfd_mach_sh2a_nofpu: | |
2361 | set_gdbarch_register_name (gdbarch, sh_sh2a_nofpu_register_name); | |
2362 | set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno); | |
2363 | ||
2364 | set_gdbarch_num_pseudo_regs (gdbarch, 1); | |
2365 | set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read); | |
2366 | set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write); | |
2367 | break; | |
2368 | ||
cc17453a | 2369 | case bfd_mach_sh_dsp: |
48db5a3c | 2370 | set_gdbarch_register_name (gdbarch, sh_sh_dsp_register_name); |
2f14585c | 2371 | set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno); |
cc17453a | 2372 | break; |
1c0159e0 | 2373 | |
cc17453a | 2374 | case bfd_mach_sh3: |
4e6cbc38 AS |
2375 | case bfd_mach_sh3_nommu: |
2376 | case bfd_mach_sh2a_nofpu_or_sh3_nommu: | |
48db5a3c | 2377 | set_gdbarch_register_name (gdbarch, sh_sh3_register_name); |
cc17453a | 2378 | break; |
1c0159e0 | 2379 | |
cc17453a | 2380 | case bfd_mach_sh3e: |
4e6cbc38 | 2381 | case bfd_mach_sh2a_or_sh3e: |
c378eb4e | 2382 | /* doubles on sh2e and sh3e are actually 4 byte. */ |
48db5a3c | 2383 | set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
f92589cb | 2384 | set_gdbarch_double_format (gdbarch, floatformats_ieee_single); |
48db5a3c CV |
2385 | |
2386 | set_gdbarch_register_name (gdbarch, sh_sh3e_register_name); | |
48db5a3c | 2387 | set_gdbarch_register_type (gdbarch, sh_sh3e_register_type); |
cc17453a | 2388 | set_gdbarch_fp0_regnum (gdbarch, 25); |
c0409442 | 2389 | set_gdbarch_return_value (gdbarch, sh_return_value_fpu); |
6df2bf50 | 2390 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); |
cc17453a | 2391 | break; |
1c0159e0 | 2392 | |
cc17453a | 2393 | case bfd_mach_sh3_dsp: |
48db5a3c | 2394 | set_gdbarch_register_name (gdbarch, sh_sh3_dsp_register_name); |
48db5a3c | 2395 | set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno); |
cc17453a | 2396 | break; |
1c0159e0 | 2397 | |
cc17453a | 2398 | case bfd_mach_sh4: |
474e5826 | 2399 | case bfd_mach_sh4a: |
46e8a76b | 2400 | case bfd_mach_sh2a_or_sh4: |
48db5a3c | 2401 | set_gdbarch_register_name (gdbarch, sh_sh4_register_name); |
48db5a3c | 2402 | set_gdbarch_register_type (gdbarch, sh_sh4_register_type); |
cc17453a | 2403 | set_gdbarch_fp0_regnum (gdbarch, 25); |
da962468 | 2404 | set_gdbarch_num_pseudo_regs (gdbarch, 13); |
d8124050 AC |
2405 | set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read); |
2406 | set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write); | |
c0409442 | 2407 | set_gdbarch_return_value (gdbarch, sh_return_value_fpu); |
6df2bf50 | 2408 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); |
cc17453a | 2409 | break; |
1c0159e0 | 2410 | |
474e5826 CV |
2411 | case bfd_mach_sh4_nofpu: |
2412 | case bfd_mach_sh4a_nofpu: | |
4e6cbc38 AS |
2413 | case bfd_mach_sh4_nommu_nofpu: |
2414 | case bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu: | |
474e5826 CV |
2415 | set_gdbarch_register_name (gdbarch, sh_sh4_nofpu_register_name); |
2416 | break; | |
2417 | ||
2418 | case bfd_mach_sh4al_dsp: | |
2419 | set_gdbarch_register_name (gdbarch, sh_sh4al_dsp_register_name); | |
2420 | set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno); | |
2421 | break; | |
2422 | ||
cc17453a | 2423 | default: |
b58cbbf2 | 2424 | set_gdbarch_register_name (gdbarch, sh_sh_register_name); |
cc17453a | 2425 | break; |
8db62801 | 2426 | } |
cc17453a | 2427 | |
4be87837 DJ |
2428 | /* Hook in ABI-specific overrides, if they have been registered. */ |
2429 | gdbarch_init_osabi (info, gdbarch); | |
d658f924 | 2430 | |
94afd7a6 | 2431 | dwarf2_append_unwinders (gdbarch); |
cb2cf4ce | 2432 | frame_unwind_append_unwinder (gdbarch, &sh_stub_unwind); |
94afd7a6 | 2433 | frame_unwind_append_unwinder (gdbarch, &sh_frame_unwind); |
1c0159e0 | 2434 | |
cc17453a | 2435 | return gdbarch; |
8db62801 EZ |
2436 | } |
2437 | ||
c055b101 | 2438 | static void |
981a3fb3 | 2439 | show_sh_command (const char *args, int from_tty) |
c055b101 CV |
2440 | { |
2441 | help_list (showshcmdlist, "show sh ", all_commands, gdb_stdout); | |
2442 | } | |
2443 | ||
2444 | static void | |
981a3fb3 | 2445 | set_sh_command (const char *args, int from_tty) |
c055b101 CV |
2446 | { |
2447 | printf_unfiltered | |
2448 | ("\"set sh\" must be followed by an appropriate subcommand.\n"); | |
2449 | help_list (setshcmdlist, "set sh ", all_commands, gdb_stdout); | |
2450 | } | |
2451 | ||
c906108c | 2452 | void |
fba45db2 | 2453 | _initialize_sh_tdep (void) |
c906108c | 2454 | { |
f2ea0907 | 2455 | gdbarch_register (bfd_arch_sh, sh_gdbarch_init, NULL); |
c906108c | 2456 | |
c055b101 CV |
2457 | add_prefix_cmd ("sh", no_class, set_sh_command, "SH specific commands.", |
2458 | &setshcmdlist, "set sh ", 0, &setlist); | |
2459 | add_prefix_cmd ("sh", no_class, show_sh_command, "SH specific commands.", | |
2460 | &showshcmdlist, "show sh ", 0, &showlist); | |
2461 | ||
2462 | add_setshow_enum_cmd ("calling-convention", class_vars, sh_cc_enum, | |
2463 | &sh_active_calling_convention, | |
2464 | _("Set calling convention used when calling target " | |
2465 | "functions from GDB."), | |
2466 | _("Show calling convention used when calling target " | |
2467 | "functions from GDB."), | |
2468 | _("gcc - Use GCC calling convention (default).\n" | |
2469 | "renesas - Enforce Renesas calling convention."), | |
2470 | NULL, NULL, | |
2471 | &setshcmdlist, &showshcmdlist); | |
c906108c | 2472 | } |