Commit | Line | Data |
---|---|---|
85a453d5 | 1 | /* Target-dependent code for Renesas Super-H, for GDB. |
0fd88904 | 2 | |
e2882c85 | 3 | Copyright (C) 1993-2018 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 10 | (at your option) any later version. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b | 17 | You should have received a copy of the GNU General Public License |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c | 19 | |
c378eb4e MS |
20 | /* Contributed by Steve Chamberlain |
21 | sac@cygnus.com. */ | |
c906108c SS |
22 | |
23 | #include "defs.h" | |
24 | #include "frame.h" | |
1c0159e0 CV |
25 | #include "frame-base.h" |
26 | #include "frame-unwind.h" | |
27 | #include "dwarf2-frame.h" | |
c906108c | 28 | #include "symtab.h" |
c906108c SS |
29 | #include "gdbtypes.h" |
30 | #include "gdbcmd.h" | |
31 | #include "gdbcore.h" | |
32 | #include "value.h" | |
33 | #include "dis-asm.h" | |
73c1f219 | 34 | #include "inferior.h" |
b4a20239 | 35 | #include "arch-utils.h" |
4e052eda | 36 | #include "regcache.h" |
3b2ca824 | 37 | #include "target-float.h" |
4be87837 | 38 | #include "osabi.h" |
dda63807 | 39 | #include "reggroups.h" |
c9ac0a72 | 40 | #include "regset.h" |
cb2cf4ce | 41 | #include "objfiles.h" |
c906108c | 42 | |
ab3b8126 JT |
43 | #include "sh-tdep.h" |
44 | ||
d658f924 | 45 | #include "elf-bfd.h" |
1a8629c7 MS |
46 | #include "solib-svr4.h" |
47 | ||
55ff77ac | 48 | /* sh flags */ |
283150cd | 49 | #include "elf/sh.h" |
fa8f86ff | 50 | #include "dwarf2.h" |
c378eb4e | 51 | /* registers numbers shared with the simulator. */ |
1c922164 | 52 | #include "gdb/sim-sh.h" |
325fac50 | 53 | #include <algorithm> |
283150cd | 54 | |
c055b101 CV |
55 | /* List of "set sh ..." and "show sh ..." commands. */ |
56 | static struct cmd_list_element *setshcmdlist = NULL; | |
57 | static struct cmd_list_element *showshcmdlist = NULL; | |
58 | ||
59 | static const char sh_cc_gcc[] = "gcc"; | |
60 | static const char sh_cc_renesas[] = "renesas"; | |
40478521 | 61 | static const char *const sh_cc_enum[] = { |
c055b101 CV |
62 | sh_cc_gcc, |
63 | sh_cc_renesas, | |
64 | NULL | |
65 | }; | |
66 | ||
67 | static const char *sh_active_calling_convention = sh_cc_gcc; | |
68 | ||
da962468 | 69 | #define SH_NUM_REGS 67 |
88e04cc1 | 70 | |
1c0159e0 | 71 | struct sh_frame_cache |
cc17453a | 72 | { |
1c0159e0 CV |
73 | /* Base address. */ |
74 | CORE_ADDR base; | |
75 | LONGEST sp_offset; | |
76 | CORE_ADDR pc; | |
77 | ||
c378eb4e | 78 | /* Flag showing that a frame has been created in the prologue code. */ |
1c0159e0 CV |
79 | int uses_fp; |
80 | ||
81 | /* Saved registers. */ | |
82 | CORE_ADDR saved_regs[SH_NUM_REGS]; | |
83 | CORE_ADDR saved_sp; | |
63978407 | 84 | }; |
c906108c | 85 | |
c055b101 CV |
86 | static int |
87 | sh_is_renesas_calling_convention (struct type *func_type) | |
88 | { | |
ca193e27 TS |
89 | int val = 0; |
90 | ||
91 | if (func_type) | |
92 | { | |
93 | func_type = check_typedef (func_type); | |
94 | ||
95 | if (TYPE_CODE (func_type) == TYPE_CODE_PTR) | |
96 | func_type = check_typedef (TYPE_TARGET_TYPE (func_type)); | |
97 | ||
98 | if (TYPE_CODE (func_type) == TYPE_CODE_FUNC | |
99 | && TYPE_CALLING_CONVENTION (func_type) == DW_CC_GNU_renesas_sh) | |
100 | val = 1; | |
101 | } | |
102 | ||
103 | if (sh_active_calling_convention == sh_cc_renesas) | |
104 | val = 1; | |
105 | ||
106 | return val; | |
c055b101 CV |
107 | } |
108 | ||
fa88f677 | 109 | static const char * |
d93859e2 | 110 | sh_sh_register_name (struct gdbarch *gdbarch, int reg_nr) |
cc17453a | 111 | { |
a121b7c1 | 112 | static const char *register_names[] = { |
617daa0e CV |
113 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
114 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
115 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
116 | "", "", | |
117 | "", "", "", "", "", "", "", "", | |
118 | "", "", "", "", "", "", "", "", | |
119 | "", "", | |
120 | "", "", "", "", "", "", "", "", | |
121 | "", "", "", "", "", "", "", "", | |
da962468 | 122 | "", "", "", "", "", "", "", "", |
cc17453a EZ |
123 | }; |
124 | if (reg_nr < 0) | |
125 | return NULL; | |
126 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
127 | return NULL; | |
128 | return register_names[reg_nr]; | |
129 | } | |
130 | ||
fa88f677 | 131 | static const char * |
d93859e2 | 132 | sh_sh3_register_name (struct gdbarch *gdbarch, int reg_nr) |
cc17453a | 133 | { |
a121b7c1 | 134 | static const char *register_names[] = { |
617daa0e CV |
135 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
136 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
137 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
138 | "", "", | |
139 | "", "", "", "", "", "", "", "", | |
140 | "", "", "", "", "", "", "", "", | |
141 | "ssr", "spc", | |
cc17453a EZ |
142 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", |
143 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1" | |
da962468 | 144 | "", "", "", "", "", "", "", "", |
cc17453a EZ |
145 | }; |
146 | if (reg_nr < 0) | |
147 | return NULL; | |
148 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
149 | return NULL; | |
150 | return register_names[reg_nr]; | |
151 | } | |
152 | ||
fa88f677 | 153 | static const char * |
d93859e2 | 154 | sh_sh3e_register_name (struct gdbarch *gdbarch, int reg_nr) |
cc17453a | 155 | { |
a121b7c1 | 156 | static const char *register_names[] = { |
617daa0e CV |
157 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
158 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
159 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
cc17453a | 160 | "fpul", "fpscr", |
617daa0e CV |
161 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", |
162 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
163 | "ssr", "spc", | |
cc17453a EZ |
164 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", |
165 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", | |
da962468 | 166 | "", "", "", "", "", "", "", "", |
cc17453a EZ |
167 | }; |
168 | if (reg_nr < 0) | |
169 | return NULL; | |
170 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
171 | return NULL; | |
172 | return register_names[reg_nr]; | |
173 | } | |
174 | ||
2d188dd3 | 175 | static const char * |
d93859e2 | 176 | sh_sh2e_register_name (struct gdbarch *gdbarch, int reg_nr) |
2d188dd3 | 177 | { |
a121b7c1 | 178 | static const char *register_names[] = { |
617daa0e CV |
179 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
180 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
181 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
2d188dd3 | 182 | "fpul", "fpscr", |
617daa0e CV |
183 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", |
184 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
185 | "", "", | |
2d188dd3 NC |
186 | "", "", "", "", "", "", "", "", |
187 | "", "", "", "", "", "", "", "", | |
da962468 CV |
188 | "", "", "", "", "", "", "", "", |
189 | }; | |
190 | if (reg_nr < 0) | |
191 | return NULL; | |
192 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
193 | return NULL; | |
194 | return register_names[reg_nr]; | |
195 | } | |
196 | ||
197 | static const char * | |
d93859e2 | 198 | sh_sh2a_register_name (struct gdbarch *gdbarch, int reg_nr) |
da962468 | 199 | { |
a121b7c1 | 200 | static const char *register_names[] = { |
da962468 CV |
201 | /* general registers 0-15 */ |
202 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
203 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
204 | /* 16 - 22 */ | |
205 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
206 | /* 23, 24 */ | |
207 | "fpul", "fpscr", | |
208 | /* floating point registers 25 - 40 */ | |
209 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", | |
210 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
211 | /* 41, 42 */ | |
212 | "", "", | |
213 | /* 43 - 62. Banked registers. The bank number used is determined by | |
c378eb4e | 214 | the bank register (63). */ |
da962468 CV |
215 | "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b", |
216 | "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", | |
217 | "machb", "ivnb", "prb", "gbrb", "maclb", | |
218 | /* 63: register bank number, not a real register but used to | |
219 | communicate the register bank currently get/set. This register | |
220 | is hidden to the user, who manipulates it using the pseudo | |
221 | register called "bank" (67). See below. */ | |
222 | "", | |
223 | /* 64 - 66 */ | |
224 | "ibcr", "ibnr", "tbr", | |
225 | /* 67: register bank number, the user visible pseudo register. */ | |
226 | "bank", | |
227 | /* double precision (pseudo) 68 - 75 */ | |
228 | "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", | |
229 | }; | |
230 | if (reg_nr < 0) | |
231 | return NULL; | |
232 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
233 | return NULL; | |
234 | return register_names[reg_nr]; | |
235 | } | |
236 | ||
237 | static const char * | |
d93859e2 | 238 | sh_sh2a_nofpu_register_name (struct gdbarch *gdbarch, int reg_nr) |
da962468 | 239 | { |
a121b7c1 | 240 | static const char *register_names[] = { |
da962468 CV |
241 | /* general registers 0-15 */ |
242 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
243 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
244 | /* 16 - 22 */ | |
245 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
246 | /* 23, 24 */ | |
247 | "", "", | |
248 | /* floating point registers 25 - 40 */ | |
249 | "", "", "", "", "", "", "", "", | |
250 | "", "", "", "", "", "", "", "", | |
251 | /* 41, 42 */ | |
252 | "", "", | |
253 | /* 43 - 62. Banked registers. The bank number used is determined by | |
c378eb4e | 254 | the bank register (63). */ |
da962468 CV |
255 | "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b", |
256 | "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", | |
257 | "machb", "ivnb", "prb", "gbrb", "maclb", | |
258 | /* 63: register bank number, not a real register but used to | |
259 | communicate the register bank currently get/set. This register | |
260 | is hidden to the user, who manipulates it using the pseudo | |
261 | register called "bank" (67). See below. */ | |
262 | "", | |
263 | /* 64 - 66 */ | |
264 | "ibcr", "ibnr", "tbr", | |
265 | /* 67: register bank number, the user visible pseudo register. */ | |
266 | "bank", | |
267 | /* double precision (pseudo) 68 - 75 */ | |
268 | "", "", "", "", "", "", "", "", | |
2d188dd3 NC |
269 | }; |
270 | if (reg_nr < 0) | |
271 | return NULL; | |
272 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
273 | return NULL; | |
274 | return register_names[reg_nr]; | |
275 | } | |
276 | ||
fa88f677 | 277 | static const char * |
d93859e2 | 278 | sh_sh_dsp_register_name (struct gdbarch *gdbarch, int reg_nr) |
cc17453a | 279 | { |
a121b7c1 | 280 | static const char *register_names[] = { |
617daa0e CV |
281 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
282 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
283 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
284 | "", "dsr", | |
285 | "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1", | |
286 | "y0", "y1", "", "", "", "", "", "mod", | |
287 | "", "", | |
288 | "rs", "re", "", "", "", "", "", "", | |
289 | "", "", "", "", "", "", "", "", | |
da962468 | 290 | "", "", "", "", "", "", "", "", |
cc17453a EZ |
291 | }; |
292 | if (reg_nr < 0) | |
293 | return NULL; | |
294 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
295 | return NULL; | |
296 | return register_names[reg_nr]; | |
297 | } | |
298 | ||
fa88f677 | 299 | static const char * |
d93859e2 | 300 | sh_sh3_dsp_register_name (struct gdbarch *gdbarch, int reg_nr) |
cc17453a | 301 | { |
a121b7c1 | 302 | static const char *register_names[] = { |
617daa0e CV |
303 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
304 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
305 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
306 | "", "dsr", | |
307 | "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1", | |
308 | "y0", "y1", "", "", "", "", "", "mod", | |
309 | "ssr", "spc", | |
310 | "rs", "re", "", "", "", "", "", "", | |
026a72f8 CV |
311 | "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b", |
312 | "", "", "", "", "", "", "", "", | |
da962468 | 313 | "", "", "", "", "", "", "", "", |
cc17453a EZ |
314 | }; |
315 | if (reg_nr < 0) | |
316 | return NULL; | |
317 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
318 | return NULL; | |
319 | return register_names[reg_nr]; | |
320 | } | |
321 | ||
fa88f677 | 322 | static const char * |
d93859e2 | 323 | sh_sh4_register_name (struct gdbarch *gdbarch, int reg_nr) |
53116e27 | 324 | { |
a121b7c1 | 325 | static const char *register_names[] = { |
a38d2a54 | 326 | /* general registers 0-15 */ |
617daa0e CV |
327 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
328 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
a38d2a54 | 329 | /* 16 - 22 */ |
617daa0e | 330 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", |
a38d2a54 | 331 | /* 23, 24 */ |
53116e27 | 332 | "fpul", "fpscr", |
a38d2a54 | 333 | /* floating point registers 25 - 40 */ |
617daa0e CV |
334 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", |
335 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
a38d2a54 | 336 | /* 41, 42 */ |
617daa0e | 337 | "ssr", "spc", |
a38d2a54 | 338 | /* bank 0 43 - 50 */ |
53116e27 | 339 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", |
a38d2a54 | 340 | /* bank 1 51 - 58 */ |
53116e27 | 341 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", |
a6521d9a | 342 | /* 59 - 66 */ |
da962468 | 343 | "", "", "", "", "", "", "", "", |
c378eb4e | 344 | /* pseudo bank register. */ |
da962468 | 345 | "", |
a6521d9a | 346 | /* double precision (pseudo) 68 - 75 */ |
617daa0e | 347 | "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", |
a6521d9a | 348 | /* vectors (pseudo) 76 - 79 */ |
617daa0e | 349 | "fv0", "fv4", "fv8", "fv12", |
a6521d9a TS |
350 | /* FIXME: missing XF */ |
351 | /* FIXME: missing XD */ | |
53116e27 EZ |
352 | }; |
353 | if (reg_nr < 0) | |
354 | return NULL; | |
355 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
356 | return NULL; | |
357 | return register_names[reg_nr]; | |
358 | } | |
359 | ||
474e5826 | 360 | static const char * |
d93859e2 | 361 | sh_sh4_nofpu_register_name (struct gdbarch *gdbarch, int reg_nr) |
474e5826 | 362 | { |
a121b7c1 | 363 | static const char *register_names[] = { |
474e5826 CV |
364 | /* general registers 0-15 */ |
365 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
366 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
367 | /* 16 - 22 */ | |
368 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
369 | /* 23, 24 */ | |
370 | "", "", | |
371 | /* floating point registers 25 - 40 -- not for nofpu target */ | |
372 | "", "", "", "", "", "", "", "", | |
373 | "", "", "", "", "", "", "", "", | |
374 | /* 41, 42 */ | |
375 | "ssr", "spc", | |
376 | /* bank 0 43 - 50 */ | |
377 | "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", | |
378 | /* bank 1 51 - 58 */ | |
379 | "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", | |
a6521d9a | 380 | /* 59 - 66 */ |
da962468 | 381 | "", "", "", "", "", "", "", "", |
c378eb4e | 382 | /* pseudo bank register. */ |
da962468 | 383 | "", |
a6521d9a | 384 | /* double precision (pseudo) 68 - 75 -- not for nofpu target */ |
474e5826 | 385 | "", "", "", "", "", "", "", "", |
a6521d9a | 386 | /* vectors (pseudo) 76 - 79 -- not for nofpu target */ |
474e5826 CV |
387 | "", "", "", "", |
388 | }; | |
389 | if (reg_nr < 0) | |
390 | return NULL; | |
391 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
392 | return NULL; | |
393 | return register_names[reg_nr]; | |
394 | } | |
395 | ||
396 | static const char * | |
d93859e2 | 397 | sh_sh4al_dsp_register_name (struct gdbarch *gdbarch, int reg_nr) |
474e5826 | 398 | { |
a121b7c1 | 399 | static const char *register_names[] = { |
474e5826 CV |
400 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
401 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
402 | "pc", "pr", "gbr", "vbr", "mach", "macl", "sr", | |
403 | "", "dsr", | |
404 | "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1", | |
405 | "y0", "y1", "", "", "", "", "", "mod", | |
406 | "ssr", "spc", | |
407 | "rs", "re", "", "", "", "", "", "", | |
026a72f8 CV |
408 | "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b", |
409 | "", "", "", "", "", "", "", "", | |
da962468 | 410 | "", "", "", "", "", "", "", "", |
474e5826 CV |
411 | }; |
412 | if (reg_nr < 0) | |
413 | return NULL; | |
414 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
415 | return NULL; | |
416 | return register_names[reg_nr]; | |
417 | } | |
418 | ||
cd6c3b4f YQ |
419 | /* Implement the breakpoint_kind_from_pc gdbarch method. */ |
420 | ||
d19280ad YQ |
421 | static int |
422 | sh_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr) | |
cc17453a | 423 | { |
d19280ad YQ |
424 | return 2; |
425 | } | |
426 | ||
cd6c3b4f YQ |
427 | /* Implement the sw_breakpoint_from_kind gdbarch method. */ |
428 | ||
d19280ad YQ |
429 | static const gdb_byte * |
430 | sh_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size) | |
431 | { | |
432 | *size = kind; | |
617daa0e | 433 | |
bac718a6 UW |
434 | /* For remote stub targets, trapa #20 is used. */ |
435 | if (strcmp (target_shortname, "remote") == 0) | |
436 | { | |
437 | static unsigned char big_remote_breakpoint[] = { 0xc3, 0x20 }; | |
438 | static unsigned char little_remote_breakpoint[] = { 0x20, 0xc3 }; | |
439 | ||
67d57894 | 440 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
d19280ad | 441 | return big_remote_breakpoint; |
bac718a6 | 442 | else |
d19280ad | 443 | return little_remote_breakpoint; |
bac718a6 | 444 | } |
d19280ad YQ |
445 | else |
446 | { | |
447 | /* 0xc3c3 is trapa #c3, and it works in big and little endian | |
448 | modes. */ | |
449 | static unsigned char breakpoint[] = { 0xc3, 0xc3 }; | |
bac718a6 | 450 | |
d19280ad YQ |
451 | return breakpoint; |
452 | } | |
cc17453a | 453 | } |
c906108c SS |
454 | |
455 | /* Prologue looks like | |
1c0159e0 CV |
456 | mov.l r14,@-r15 |
457 | sts.l pr,@-r15 | |
458 | mov.l <regs>,@-r15 | |
459 | sub <room_for_loca_vars>,r15 | |
460 | mov r15,r14 | |
8db62801 | 461 | |
c378eb4e | 462 | Actually it can be more complicated than this but that's it, basically. */ |
c906108c | 463 | |
1c0159e0 CV |
464 | #define GET_SOURCE_REG(x) (((x) >> 4) & 0xf) |
465 | #define GET_TARGET_REG(x) (((x) >> 8) & 0xf) | |
466 | ||
5f883edd FF |
467 | /* JSR @Rm 0100mmmm00001011 */ |
468 | #define IS_JSR(x) (((x) & 0xf0ff) == 0x400b) | |
469 | ||
8db62801 EZ |
470 | /* STS.L PR,@-r15 0100111100100010 |
471 | r15-4-->r15, PR-->(r15) */ | |
c906108c | 472 | #define IS_STS(x) ((x) == 0x4f22) |
8db62801 | 473 | |
03131d99 CV |
474 | /* STS.L MACL,@-r15 0100111100010010 |
475 | r15-4-->r15, MACL-->(r15) */ | |
476 | #define IS_MACL_STS(x) ((x) == 0x4f12) | |
477 | ||
8db62801 EZ |
478 | /* MOV.L Rm,@-r15 00101111mmmm0110 |
479 | r15-4-->r15, Rm-->(R15) */ | |
c906108c | 480 | #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06) |
8db62801 | 481 | |
8db62801 EZ |
482 | /* MOV r15,r14 0110111011110011 |
483 | r15-->r14 */ | |
c906108c | 484 | #define IS_MOV_SP_FP(x) ((x) == 0x6ef3) |
8db62801 EZ |
485 | |
486 | /* ADD #imm,r15 01111111iiiiiiii | |
487 | r15+imm-->r15 */ | |
1c0159e0 | 488 | #define IS_ADD_IMM_SP(x) (((x) & 0xff00) == 0x7f00) |
8db62801 | 489 | |
c906108c SS |
490 | #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00) |
491 | #define IS_SHLL_R3(x) ((x) == 0x4300) | |
8db62801 EZ |
492 | |
493 | /* ADD r3,r15 0011111100111100 | |
494 | r15+r3-->r15 */ | |
c906108c | 495 | #define IS_ADD_R3SP(x) ((x) == 0x3f3c) |
8db62801 EZ |
496 | |
497 | /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011 | |
8db62801 | 498 | FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011 |
8db62801 | 499 | FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */ |
f2ea0907 | 500 | /* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to |
c378eb4e | 501 | make this entirely clear. */ |
1c0159e0 CV |
502 | /* #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) */ |
503 | #define IS_FPUSH(x) (((x) & 0xff0f) == 0xff0b) | |
504 | ||
505 | /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 4 <= m <= 7 */ | |
506 | #define IS_MOV_ARG_TO_REG(x) \ | |
507 | (((x) & 0xf00f) == 0x6003 && \ | |
508 | ((x) & 0x00f0) >= 0x0040 && \ | |
509 | ((x) & 0x00f0) <= 0x0070) | |
510 | /* MOV.L Rm,@Rn 0010nnnnmmmm0010 n = 14, 4 <= m <= 7 */ | |
511 | #define IS_MOV_ARG_TO_IND_R14(x) \ | |
512 | (((x) & 0xff0f) == 0x2e02 && \ | |
513 | ((x) & 0x00f0) >= 0x0040 && \ | |
514 | ((x) & 0x00f0) <= 0x0070) | |
515 | /* MOV.L Rm,@(disp*4,Rn) 00011110mmmmdddd n = 14, 4 <= m <= 7 */ | |
516 | #define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \ | |
517 | (((x) & 0xff00) == 0x1e00 && \ | |
518 | ((x) & 0x00f0) >= 0x0040 && \ | |
519 | ((x) & 0x00f0) <= 0x0070) | |
520 | ||
521 | /* MOV.W @(disp*2,PC),Rn 1001nnnndddddddd */ | |
522 | #define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000) | |
523 | /* MOV.L @(disp*4,PC),Rn 1101nnnndddddddd */ | |
524 | #define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000) | |
03131d99 CV |
525 | /* MOVI20 #imm20,Rn 0000nnnniiii0000 */ |
526 | #define IS_MOVI20(x) (((x) & 0xf00f) == 0x0000) | |
1c0159e0 CV |
527 | /* SUB Rn,R15 00111111nnnn1000 */ |
528 | #define IS_SUB_REG_FROM_SP(x) (((x) & 0xff0f) == 0x3f08) | |
8db62801 | 529 | |
1c0159e0 | 530 | #define FPSCR_SZ (1 << 20) |
cc17453a | 531 | |
c378eb4e | 532 | /* The following instructions are used for epilogue testing. */ |
1c0159e0 CV |
533 | #define IS_RESTORE_FP(x) ((x) == 0x6ef6) |
534 | #define IS_RTS(x) ((x) == 0x000b) | |
535 | #define IS_LDS(x) ((x) == 0x4f26) | |
03131d99 | 536 | #define IS_MACL_LDS(x) ((x) == 0x4f16) |
1c0159e0 CV |
537 | #define IS_MOV_FP_SP(x) ((x) == 0x6fe3) |
538 | #define IS_ADD_REG_TO_FP(x) (((x) & 0xff0f) == 0x3e0c) | |
539 | #define IS_ADD_IMM_FP(x) (((x) & 0xff00) == 0x7e00) | |
cc17453a | 540 | |
cc17453a | 541 | static CORE_ADDR |
e17a4113 | 542 | sh_analyze_prologue (struct gdbarch *gdbarch, |
5cbb9812 | 543 | CORE_ADDR pc, CORE_ADDR limit_pc, |
d2ca4222 | 544 | struct sh_frame_cache *cache, ULONGEST fpscr) |
617daa0e | 545 | { |
e17a4113 | 546 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1c0159e0 | 547 | ULONGEST inst; |
1c0159e0 CV |
548 | int offset; |
549 | int sav_offset = 0; | |
c906108c | 550 | int r3_val = 0; |
1c0159e0 | 551 | int reg, sav_reg = -1; |
cc17453a | 552 | |
1c0159e0 | 553 | cache->uses_fp = 0; |
5cbb9812 | 554 | for (; pc < limit_pc; pc += 2) |
cc17453a | 555 | { |
e17a4113 | 556 | inst = read_memory_unsigned_integer (pc, 2, byte_order); |
c378eb4e | 557 | /* See where the registers will be saved to. */ |
f2ea0907 | 558 | if (IS_PUSH (inst)) |
cc17453a | 559 | { |
1c0159e0 CV |
560 | cache->saved_regs[GET_SOURCE_REG (inst)] = cache->sp_offset; |
561 | cache->sp_offset += 4; | |
cc17453a | 562 | } |
f2ea0907 | 563 | else if (IS_STS (inst)) |
cc17453a | 564 | { |
1c0159e0 CV |
565 | cache->saved_regs[PR_REGNUM] = cache->sp_offset; |
566 | cache->sp_offset += 4; | |
cc17453a | 567 | } |
03131d99 CV |
568 | else if (IS_MACL_STS (inst)) |
569 | { | |
570 | cache->saved_regs[MACL_REGNUM] = cache->sp_offset; | |
571 | cache->sp_offset += 4; | |
572 | } | |
f2ea0907 | 573 | else if (IS_MOV_R3 (inst)) |
cc17453a | 574 | { |
f2ea0907 | 575 | r3_val = ((inst & 0xff) ^ 0x80) - 0x80; |
cc17453a | 576 | } |
f2ea0907 | 577 | else if (IS_SHLL_R3 (inst)) |
cc17453a EZ |
578 | { |
579 | r3_val <<= 1; | |
580 | } | |
f2ea0907 | 581 | else if (IS_ADD_R3SP (inst)) |
cc17453a | 582 | { |
1c0159e0 | 583 | cache->sp_offset += -r3_val; |
cc17453a | 584 | } |
f2ea0907 | 585 | else if (IS_ADD_IMM_SP (inst)) |
cc17453a | 586 | { |
1c0159e0 CV |
587 | offset = ((inst & 0xff) ^ 0x80) - 0x80; |
588 | cache->sp_offset -= offset; | |
c906108c | 589 | } |
1c0159e0 | 590 | else if (IS_MOVW_PCREL_TO_REG (inst)) |
617daa0e | 591 | { |
1c0159e0 CV |
592 | if (sav_reg < 0) |
593 | { | |
594 | reg = GET_TARGET_REG (inst); | |
595 | if (reg < 14) | |
596 | { | |
597 | sav_reg = reg; | |
a2b4a96c | 598 | offset = (inst & 0xff) << 1; |
1c0159e0 | 599 | sav_offset = |
e17a4113 | 600 | read_memory_integer ((pc + 4) + offset, 2, byte_order); |
1c0159e0 CV |
601 | } |
602 | } | |
c906108c | 603 | } |
1c0159e0 | 604 | else if (IS_MOVL_PCREL_TO_REG (inst)) |
617daa0e | 605 | { |
1c0159e0 CV |
606 | if (sav_reg < 0) |
607 | { | |
a2b4a96c | 608 | reg = GET_TARGET_REG (inst); |
1c0159e0 CV |
609 | if (reg < 14) |
610 | { | |
611 | sav_reg = reg; | |
a2b4a96c | 612 | offset = (inst & 0xff) << 2; |
1c0159e0 | 613 | sav_offset = |
e17a4113 UW |
614 | read_memory_integer (((pc & 0xfffffffc) + 4) + offset, |
615 | 4, byte_order); | |
1c0159e0 CV |
616 | } |
617 | } | |
c906108c | 618 | } |
5cbb9812 TS |
619 | else if (IS_MOVI20 (inst) |
620 | && (pc + 2 < limit_pc)) | |
03131d99 CV |
621 | { |
622 | if (sav_reg < 0) | |
623 | { | |
624 | reg = GET_TARGET_REG (inst); | |
625 | if (reg < 14) | |
626 | { | |
627 | sav_reg = reg; | |
628 | sav_offset = GET_SOURCE_REG (inst) << 16; | |
c378eb4e | 629 | /* MOVI20 is a 32 bit instruction! */ |
03131d99 | 630 | pc += 2; |
e17a4113 UW |
631 | sav_offset |
632 | |= read_memory_unsigned_integer (pc, 2, byte_order); | |
03131d99 CV |
633 | /* Now sav_offset contains an unsigned 20 bit value. |
634 | It must still get sign extended. */ | |
635 | if (sav_offset & 0x00080000) | |
636 | sav_offset |= 0xfff00000; | |
637 | } | |
638 | } | |
639 | } | |
1c0159e0 | 640 | else if (IS_SUB_REG_FROM_SP (inst)) |
617daa0e | 641 | { |
1c0159e0 CV |
642 | reg = GET_SOURCE_REG (inst); |
643 | if (sav_reg > 0 && reg == sav_reg) | |
644 | { | |
645 | sav_reg = -1; | |
646 | } | |
647 | cache->sp_offset += sav_offset; | |
c906108c | 648 | } |
f2ea0907 | 649 | else if (IS_FPUSH (inst)) |
c906108c | 650 | { |
d2ca4222 | 651 | if (fpscr & FPSCR_SZ) |
c906108c | 652 | { |
1c0159e0 | 653 | cache->sp_offset += 8; |
c906108c SS |
654 | } |
655 | else | |
656 | { | |
1c0159e0 | 657 | cache->sp_offset += 4; |
c906108c SS |
658 | } |
659 | } | |
f2ea0907 | 660 | else if (IS_MOV_SP_FP (inst)) |
617daa0e | 661 | { |
5cbb9812 TS |
662 | pc += 2; |
663 | /* Don't go any further than six more instructions. */ | |
325fac50 | 664 | limit_pc = std::min (limit_pc, pc + (2 * 6)); |
5cbb9812 | 665 | |
960ccd7d | 666 | cache->uses_fp = 1; |
1c0159e0 CV |
667 | /* At this point, only allow argument register moves to other |
668 | registers or argument register moves to @(X,fp) which are | |
669 | moving the register arguments onto the stack area allocated | |
670 | by a former add somenumber to SP call. Don't allow moving | |
c378eb4e | 671 | to an fp indirect address above fp + cache->sp_offset. */ |
5cbb9812 | 672 | for (; pc < limit_pc; pc += 2) |
1c0159e0 | 673 | { |
e17a4113 | 674 | inst = read_memory_integer (pc, 2, byte_order); |
1c0159e0 | 675 | if (IS_MOV_ARG_TO_IND_R14 (inst)) |
617daa0e | 676 | { |
1c0159e0 CV |
677 | reg = GET_SOURCE_REG (inst); |
678 | if (cache->sp_offset > 0) | |
617daa0e | 679 | cache->saved_regs[reg] = cache->sp_offset; |
1c0159e0 CV |
680 | } |
681 | else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst)) | |
617daa0e | 682 | { |
1c0159e0 CV |
683 | reg = GET_SOURCE_REG (inst); |
684 | offset = (inst & 0xf) * 4; | |
685 | if (cache->sp_offset > offset) | |
686 | cache->saved_regs[reg] = cache->sp_offset - offset; | |
687 | } | |
688 | else if (IS_MOV_ARG_TO_REG (inst)) | |
617daa0e | 689 | continue; |
1c0159e0 CV |
690 | else |
691 | break; | |
692 | } | |
693 | break; | |
694 | } | |
5f883edd FF |
695 | else if (IS_JSR (inst)) |
696 | { | |
697 | /* We have found a jsr that has been scheduled into the prologue. | |
698 | If we continue the scan and return a pc someplace after this, | |
699 | then setting a breakpoint on this function will cause it to | |
700 | appear to be called after the function it is calling via the | |
701 | jsr, which will be very confusing. Most likely the next | |
702 | instruction is going to be IS_MOV_SP_FP in the delay slot. If | |
c378eb4e | 703 | so, note that before returning the current pc. */ |
5cbb9812 TS |
704 | if (pc + 2 < limit_pc) |
705 | { | |
706 | inst = read_memory_integer (pc + 2, 2, byte_order); | |
707 | if (IS_MOV_SP_FP (inst)) | |
708 | cache->uses_fp = 1; | |
709 | } | |
5f883edd FF |
710 | break; |
711 | } | |
c378eb4e MS |
712 | #if 0 /* This used to just stop when it found an instruction |
713 | that was not considered part of the prologue. Now, | |
714 | we just keep going looking for likely | |
715 | instructions. */ | |
c906108c SS |
716 | else |
717 | break; | |
2bfa91ee | 718 | #endif |
c906108c SS |
719 | } |
720 | ||
1c0159e0 CV |
721 | return pc; |
722 | } | |
c906108c | 723 | |
c378eb4e | 724 | /* Skip any prologue before the guts of a function. */ |
1c0159e0 | 725 | static CORE_ADDR |
8a8bc27f | 726 | sh_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
c906108c | 727 | { |
5cbb9812 | 728 | CORE_ADDR post_prologue_pc, func_addr, func_end_addr, limit_pc; |
1c0159e0 CV |
729 | struct sh_frame_cache cache; |
730 | ||
731 | /* See if we can determine the end of the prologue via the symbol table. | |
732 | If so, then return either PC, or the PC after the prologue, whichever | |
733 | is greater. */ | |
5cbb9812 | 734 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end_addr)) |
8a8bc27f TS |
735 | { |
736 | post_prologue_pc = skip_prologue_using_sal (gdbarch, func_addr); | |
737 | if (post_prologue_pc != 0) | |
325fac50 | 738 | return std::max (pc, post_prologue_pc); |
8a8bc27f | 739 | } |
cc17453a | 740 | |
8a8bc27f TS |
741 | /* Can't determine prologue from the symbol table, need to examine |
742 | instructions. */ | |
c906108c | 743 | |
5cbb9812 TS |
744 | /* Find an upper limit on the function prologue using the debug |
745 | information. If the debug information could not be used to provide | |
746 | that bound, then use an arbitrary large number as the upper bound. */ | |
747 | limit_pc = skip_prologue_using_sal (gdbarch, pc); | |
748 | if (limit_pc == 0) | |
749 | /* Don't go any further than 28 instructions. */ | |
750 | limit_pc = pc + (2 * 28); | |
751 | ||
752 | /* Do not allow limit_pc to be past the function end, if we know | |
753 | where that end is... */ | |
754 | if (func_end_addr != 0) | |
325fac50 | 755 | limit_pc = std::min (limit_pc, func_end_addr); |
5cbb9812 | 756 | |
1c0159e0 | 757 | cache.sp_offset = -4; |
5cbb9812 | 758 | post_prologue_pc = sh_analyze_prologue (gdbarch, pc, limit_pc, &cache, 0); |
8a8bc27f TS |
759 | if (cache.uses_fp) |
760 | pc = post_prologue_pc; | |
c906108c | 761 | |
1c0159e0 CV |
762 | return pc; |
763 | } | |
764 | ||
2e952408 | 765 | /* The ABI says: |
9a5cef92 EZ |
766 | |
767 | Aggregate types not bigger than 8 bytes that have the same size and | |
768 | alignment as one of the integer scalar types are returned in the | |
769 | same registers as the integer type they match. | |
770 | ||
771 | For example, a 2-byte aligned structure with size 2 bytes has the | |
772 | same size and alignment as a short int, and will be returned in R0. | |
773 | A 4-byte aligned structure with size 8 bytes has the same size and | |
774 | alignment as a long long int, and will be returned in R0 and R1. | |
775 | ||
776 | When an aggregate type is returned in R0 and R1, R0 contains the | |
777 | first four bytes of the aggregate, and R1 contains the | |
c378eb4e | 778 | remainder. If the size of the aggregate type is not a multiple of 4 |
9a5cef92 | 779 | bytes, the aggregate is tail-padded up to a multiple of 4 |
c378eb4e | 780 | bytes. The value of the padding is undefined. For little-endian |
9a5cef92 EZ |
781 | targets the padding will appear at the most significant end of the |
782 | last element, for big-endian targets the padding appears at the | |
783 | least significant end of the last element. | |
784 | ||
c378eb4e | 785 | All other aggregate types are returned by address. The caller |
9a5cef92 | 786 | function passes the address of an area large enough to hold the |
c378eb4e | 787 | aggregate value in R2. The called function stores the result in |
7fe958be | 788 | this location. |
9a5cef92 EZ |
789 | |
790 | To reiterate, structs smaller than 8 bytes could also be returned | |
791 | in memory, if they don't pass the "same size and alignment as an | |
792 | integer type" rule. | |
793 | ||
794 | For example, in | |
795 | ||
796 | struct s { char c[3]; } wibble; | |
797 | struct s foo(void) { return wibble; } | |
798 | ||
799 | the return value from foo() will be in memory, not | |
800 | in R0, because there is no 3-byte integer type. | |
801 | ||
7fe958be EZ |
802 | Similarly, in |
803 | ||
804 | struct s { char c[2]; } wibble; | |
805 | struct s foo(void) { return wibble; } | |
806 | ||
807 | because a struct containing two chars has alignment 1, that matches | |
808 | type char, but size 2, that matches type short. There's no integer | |
809 | type that has alignment 1 and size 2, so the struct is returned in | |
c378eb4e | 810 | memory. */ |
9a5cef92 | 811 | |
1c0159e0 | 812 | static int |
c055b101 | 813 | sh_use_struct_convention (int renesas_abi, struct type *type) |
1c0159e0 CV |
814 | { |
815 | int len = TYPE_LENGTH (type); | |
816 | int nelem = TYPE_NFIELDS (type); | |
3f997a97 | 817 | |
c055b101 CV |
818 | /* The Renesas ABI returns aggregate types always on stack. */ |
819 | if (renesas_abi && (TYPE_CODE (type) == TYPE_CODE_STRUCT | |
820 | || TYPE_CODE (type) == TYPE_CODE_UNION)) | |
821 | return 1; | |
822 | ||
3f997a97 CV |
823 | /* Non-power of 2 length types and types bigger than 8 bytes (which don't |
824 | fit in two registers anyway) use struct convention. */ | |
825 | if (len != 1 && len != 2 && len != 4 && len != 8) | |
826 | return 1; | |
827 | ||
828 | /* Scalar types and aggregate types with exactly one field are aligned | |
829 | by definition. They are returned in registers. */ | |
830 | if (nelem <= 1) | |
831 | return 0; | |
832 | ||
833 | /* If the first field in the aggregate has the same length as the entire | |
834 | aggregate type, the type is returned in registers. */ | |
835 | if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == len) | |
836 | return 0; | |
837 | ||
838 | /* If the size of the aggregate is 8 bytes and the first field is | |
839 | of size 4 bytes its alignment is equal to long long's alignment, | |
840 | so it's returned in registers. */ | |
841 | if (len == 8 && TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == 4) | |
842 | return 0; | |
843 | ||
844 | /* Otherwise use struct convention. */ | |
845 | return 1; | |
283150cd EZ |
846 | } |
847 | ||
c055b101 CV |
848 | static int |
849 | sh_use_struct_convention_nofpu (int renesas_abi, struct type *type) | |
850 | { | |
851 | /* The Renesas ABI returns long longs/doubles etc. always on stack. */ | |
852 | if (renesas_abi && TYPE_NFIELDS (type) == 0 && TYPE_LENGTH (type) >= 8) | |
853 | return 1; | |
854 | return sh_use_struct_convention (renesas_abi, type); | |
855 | } | |
856 | ||
19f59343 MS |
857 | static CORE_ADDR |
858 | sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp) | |
859 | { | |
860 | return sp & ~3; | |
861 | } | |
862 | ||
55ff77ac | 863 | /* Function: push_dummy_call (formerly push_arguments) |
c906108c SS |
864 | Setup the function arguments for calling a function in the inferior. |
865 | ||
85a453d5 | 866 | On the Renesas SH architecture, there are four registers (R4 to R7) |
c906108c SS |
867 | which are dedicated for passing function arguments. Up to the first |
868 | four arguments (depending on size) may go into these registers. | |
869 | The rest go on the stack. | |
870 | ||
6df2bf50 MS |
871 | MVS: Except on SH variants that have floating point registers. |
872 | In that case, float and double arguments are passed in the same | |
873 | manner, but using FP registers instead of GP registers. | |
874 | ||
c906108c SS |
875 | Arguments that are smaller than 4 bytes will still take up a whole |
876 | register or a whole 32-bit word on the stack, and will be | |
877 | right-justified in the register or the stack word. This includes | |
878 | chars, shorts, and small aggregate types. | |
879 | ||
880 | Arguments that are larger than 4 bytes may be split between two or | |
881 | more registers. If there are not enough registers free, an argument | |
882 | may be passed partly in a register (or registers), and partly on the | |
c378eb4e | 883 | stack. This includes doubles, long longs, and larger aggregates. |
c906108c SS |
884 | As far as I know, there is no upper limit to the size of aggregates |
885 | that will be passed in this way; in other words, the convention of | |
886 | passing a pointer to a large aggregate instead of a copy is not used. | |
887 | ||
6df2bf50 | 888 | MVS: The above appears to be true for the SH variants that do not |
55ff77ac | 889 | have an FPU, however those that have an FPU appear to copy the |
6df2bf50 MS |
890 | aggregate argument onto the stack (and not place it in registers) |
891 | if it is larger than 16 bytes (four GP registers). | |
892 | ||
c906108c SS |
893 | An exceptional case exists for struct arguments (and possibly other |
894 | aggregates such as arrays) if the size is larger than 4 bytes but | |
895 | not a multiple of 4 bytes. In this case the argument is never split | |
896 | between the registers and the stack, but instead is copied in its | |
897 | entirety onto the stack, AND also copied into as many registers as | |
898 | there is room for. In other words, space in registers permitting, | |
899 | two copies of the same argument are passed in. As far as I can tell, | |
900 | only the one on the stack is used, although that may be a function | |
901 | of the level of compiler optimization. I suspect this is a compiler | |
902 | bug. Arguments of these odd sizes are left-justified within the | |
903 | word (as opposed to arguments smaller than 4 bytes, which are | |
904 | right-justified). | |
c5aa993b | 905 | |
c906108c SS |
906 | If the function is to return an aggregate type such as a struct, it |
907 | is either returned in the normal return value register R0 (if its | |
908 | size is no greater than one byte), or else the caller must allocate | |
909 | space into which the callee will copy the return value (if the size | |
910 | is greater than one byte). In this case, a pointer to the return | |
911 | value location is passed into the callee in register R2, which does | |
912 | not displace any of the other arguments passed in via registers R4 | |
c378eb4e | 913 | to R7. */ |
c906108c | 914 | |
c378eb4e | 915 | /* Helper function to justify value in register according to endianess. */ |
948f8e3d | 916 | static const gdb_byte * |
d93859e2 | 917 | sh_justify_value_in_reg (struct gdbarch *gdbarch, struct value *val, int len) |
e5e33cd9 | 918 | { |
948f8e3d | 919 | static gdb_byte valbuf[4]; |
e5e33cd9 | 920 | |
617daa0e | 921 | memset (valbuf, 0, sizeof (valbuf)); |
e5e33cd9 CV |
922 | if (len < 4) |
923 | { | |
c378eb4e | 924 | /* value gets right-justified in the register or stack word. */ |
d93859e2 | 925 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
948f8e3d | 926 | memcpy (valbuf + (4 - len), value_contents (val), len); |
e5e33cd9 | 927 | else |
948f8e3d | 928 | memcpy (valbuf, value_contents (val), len); |
e5e33cd9 CV |
929 | return valbuf; |
930 | } | |
948f8e3d | 931 | return value_contents (val); |
617daa0e | 932 | } |
e5e33cd9 | 933 | |
c378eb4e | 934 | /* Helper function to eval number of bytes to allocate on stack. */ |
e5e33cd9 CV |
935 | static CORE_ADDR |
936 | sh_stack_allocsize (int nargs, struct value **args) | |
937 | { | |
938 | int stack_alloc = 0; | |
939 | while (nargs-- > 0) | |
4991999e | 940 | stack_alloc += ((TYPE_LENGTH (value_type (args[nargs])) + 3) & ~3); |
e5e33cd9 CV |
941 | return stack_alloc; |
942 | } | |
943 | ||
944 | /* Helper functions for getting the float arguments right. Registers usage | |
945 | depends on the ABI and the endianess. The comments should enlighten how | |
c378eb4e | 946 | it's intended to work. */ |
e5e33cd9 | 947 | |
c378eb4e | 948 | /* This array stores which of the float arg registers are already in use. */ |
e5e33cd9 CV |
949 | static int flt_argreg_array[FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM + 1]; |
950 | ||
c378eb4e | 951 | /* This function just resets the above array to "no reg used so far". */ |
e5e33cd9 CV |
952 | static void |
953 | sh_init_flt_argreg (void) | |
954 | { | |
955 | memset (flt_argreg_array, 0, sizeof flt_argreg_array); | |
956 | } | |
957 | ||
958 | /* This function returns the next register to use for float arg passing. | |
959 | It returns either a valid value between FLOAT_ARG0_REGNUM and | |
960 | FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns | |
961 | FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available. | |
962 | ||
963 | Note that register number 0 in flt_argreg_array corresponds with the | |
964 | real float register fr4. In contrast to FLOAT_ARG0_REGNUM (value is | |
965 | 29) the parity of the register number is preserved, which is important | |
c378eb4e | 966 | for the double register passing test (see the "argreg & 1" test below). */ |
e5e33cd9 | 967 | static int |
c055b101 | 968 | sh_next_flt_argreg (struct gdbarch *gdbarch, int len, struct type *func_type) |
e5e33cd9 CV |
969 | { |
970 | int argreg; | |
971 | ||
c378eb4e | 972 | /* First search for the next free register. */ |
617daa0e CV |
973 | for (argreg = 0; argreg <= FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM; |
974 | ++argreg) | |
e5e33cd9 CV |
975 | if (!flt_argreg_array[argreg]) |
976 | break; | |
977 | ||
c378eb4e | 978 | /* No register left? */ |
e5e33cd9 CV |
979 | if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM) |
980 | return FLOAT_ARGLAST_REGNUM + 1; | |
981 | ||
982 | if (len == 8) | |
983 | { | |
c378eb4e | 984 | /* Doubles are always starting in a even register number. */ |
e5e33cd9 | 985 | if (argreg & 1) |
617daa0e | 986 | { |
c055b101 CV |
987 | /* In gcc ABI, the skipped register is lost for further argument |
988 | passing now. Not so in Renesas ABI. */ | |
989 | if (!sh_is_renesas_calling_convention (func_type)) | |
990 | flt_argreg_array[argreg] = 1; | |
e5e33cd9 CV |
991 | |
992 | ++argreg; | |
993 | ||
c378eb4e | 994 | /* No register left? */ |
e5e33cd9 CV |
995 | if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM) |
996 | return FLOAT_ARGLAST_REGNUM + 1; | |
997 | } | |
c378eb4e | 998 | /* Also mark the next register as used. */ |
e5e33cd9 CV |
999 | flt_argreg_array[argreg + 1] = 1; |
1000 | } | |
c055b101 CV |
1001 | else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE |
1002 | && !sh_is_renesas_calling_convention (func_type)) | |
e5e33cd9 | 1003 | { |
c378eb4e | 1004 | /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */ |
e5e33cd9 CV |
1005 | if (!flt_argreg_array[argreg + 1]) |
1006 | ++argreg; | |
1007 | } | |
1008 | flt_argreg_array[argreg] = 1; | |
1009 | return FLOAT_ARG0_REGNUM + argreg; | |
1010 | } | |
1011 | ||
afce3d2a CV |
1012 | /* Helper function which figures out, if a type is treated like a float type. |
1013 | ||
2e952408 | 1014 | The FPU ABIs have a special way how to treat types as float types. |
afce3d2a CV |
1015 | Structures with exactly one member, which is of type float or double, are |
1016 | treated exactly as the base types float or double: | |
1017 | ||
1018 | struct sf { | |
1019 | float f; | |
1020 | }; | |
1021 | ||
1022 | struct sd { | |
1023 | double d; | |
1024 | }; | |
1025 | ||
1026 | are handled the same way as just | |
1027 | ||
1028 | float f; | |
1029 | ||
1030 | double d; | |
1031 | ||
1032 | As a result, arguments of these struct types are pushed into floating point | |
1033 | registers exactly as floats or doubles, using the same decision algorithm. | |
1034 | ||
1035 | The same is valid if these types are used as function return types. The | |
1036 | above structs are returned in fr0 resp. fr0,fr1 instead of in r0, r0,r1 | |
1037 | or even using struct convention as it is for other structs. */ | |
1038 | ||
1039 | static int | |
1040 | sh_treat_as_flt_p (struct type *type) | |
1041 | { | |
afce3d2a CV |
1042 | /* Ordinary float types are obviously treated as float. */ |
1043 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
1044 | return 1; | |
1045 | /* Otherwise non-struct types are not treated as float. */ | |
1046 | if (TYPE_CODE (type) != TYPE_CODE_STRUCT) | |
1047 | return 0; | |
1048 | /* Otherwise structs with more than one memeber are not treated as float. */ | |
1049 | if (TYPE_NFIELDS (type) != 1) | |
1050 | return 0; | |
1051 | /* Otherwise if the type of that member is float, the whole type is | |
1052 | treated as float. */ | |
1053 | if (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) == TYPE_CODE_FLT) | |
1054 | return 1; | |
1055 | /* Otherwise it's not treated as float. */ | |
1056 | return 0; | |
1057 | } | |
1058 | ||
cc17453a | 1059 | static CORE_ADDR |
617daa0e | 1060 | sh_push_dummy_call_fpu (struct gdbarch *gdbarch, |
7d9b040b | 1061 | struct value *function, |
617daa0e | 1062 | struct regcache *regcache, |
6df2bf50 | 1063 | CORE_ADDR bp_addr, int nargs, |
617daa0e | 1064 | struct value **args, |
6df2bf50 MS |
1065 | CORE_ADDR sp, int struct_return, |
1066 | CORE_ADDR struct_addr) | |
1067 | { | |
e17a4113 | 1068 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
e5e33cd9 CV |
1069 | int stack_offset = 0; |
1070 | int argreg = ARG0_REGNUM; | |
8748518b | 1071 | int flt_argreg = 0; |
6df2bf50 | 1072 | int argnum; |
c055b101 | 1073 | struct type *func_type = value_type (function); |
6df2bf50 MS |
1074 | struct type *type; |
1075 | CORE_ADDR regval; | |
948f8e3d | 1076 | const gdb_byte *val; |
8748518b | 1077 | int len, reg_size = 0; |
afce3d2a CV |
1078 | int pass_on_stack = 0; |
1079 | int treat_as_flt; | |
c055b101 CV |
1080 | int last_reg_arg = INT_MAX; |
1081 | ||
1082 | /* The Renesas ABI expects all varargs arguments, plus the last | |
1083 | non-vararg argument to be on the stack, no matter how many | |
1084 | registers have been used so far. */ | |
1085 | if (sh_is_renesas_calling_convention (func_type) | |
876cecd0 | 1086 | && TYPE_VARARGS (func_type)) |
c055b101 | 1087 | last_reg_arg = TYPE_NFIELDS (func_type) - 2; |
6df2bf50 | 1088 | |
c378eb4e | 1089 | /* First force sp to a 4-byte alignment. */ |
6df2bf50 MS |
1090 | sp = sh_frame_align (gdbarch, sp); |
1091 | ||
c378eb4e | 1092 | /* Make room on stack for args. */ |
e5e33cd9 CV |
1093 | sp -= sh_stack_allocsize (nargs, args); |
1094 | ||
c378eb4e | 1095 | /* Initialize float argument mechanism. */ |
e5e33cd9 | 1096 | sh_init_flt_argreg (); |
6df2bf50 MS |
1097 | |
1098 | /* Now load as many as possible of the first arguments into | |
1099 | registers, and push the rest onto the stack. There are 16 bytes | |
1100 | in four registers available. Loop thru args from first to last. */ | |
e5e33cd9 | 1101 | for (argnum = 0; argnum < nargs; argnum++) |
6df2bf50 | 1102 | { |
4991999e | 1103 | type = value_type (args[argnum]); |
6df2bf50 | 1104 | len = TYPE_LENGTH (type); |
d93859e2 | 1105 | val = sh_justify_value_in_reg (gdbarch, args[argnum], len); |
e5e33cd9 CV |
1106 | |
1107 | /* Some decisions have to be made how various types are handled. | |
c378eb4e | 1108 | This also differs in different ABIs. */ |
e5e33cd9 | 1109 | pass_on_stack = 0; |
e5e33cd9 | 1110 | |
c378eb4e | 1111 | /* Find out the next register to use for a floating point value. */ |
afce3d2a CV |
1112 | treat_as_flt = sh_treat_as_flt_p (type); |
1113 | if (treat_as_flt) | |
c055b101 CV |
1114 | flt_argreg = sh_next_flt_argreg (gdbarch, len, func_type); |
1115 | /* In Renesas ABI, long longs and aggregate types are always passed | |
1116 | on stack. */ | |
1117 | else if (sh_is_renesas_calling_convention (func_type) | |
1118 | && ((TYPE_CODE (type) == TYPE_CODE_INT && len == 8) | |
1119 | || TYPE_CODE (type) == TYPE_CODE_STRUCT | |
1120 | || TYPE_CODE (type) == TYPE_CODE_UNION)) | |
1121 | pass_on_stack = 1; | |
afce3d2a CV |
1122 | /* In contrast to non-FPU CPUs, arguments are never split between |
1123 | registers and stack. If an argument doesn't fit in the remaining | |
1124 | registers it's always pushed entirely on the stack. */ | |
1125 | else if (len > ((ARGLAST_REGNUM - argreg + 1) * 4)) | |
1126 | pass_on_stack = 1; | |
48db5a3c | 1127 | |
6df2bf50 MS |
1128 | while (len > 0) |
1129 | { | |
afce3d2a CV |
1130 | if ((treat_as_flt && flt_argreg > FLOAT_ARGLAST_REGNUM) |
1131 | || (!treat_as_flt && (argreg > ARGLAST_REGNUM | |
c055b101 CV |
1132 | || pass_on_stack)) |
1133 | || argnum > last_reg_arg) | |
617daa0e | 1134 | { |
c378eb4e | 1135 | /* The data goes entirely on the stack, 4-byte aligned. */ |
e5e33cd9 CV |
1136 | reg_size = (len + 3) & ~3; |
1137 | write_memory (sp + stack_offset, val, reg_size); | |
1138 | stack_offset += reg_size; | |
6df2bf50 | 1139 | } |
afce3d2a | 1140 | else if (treat_as_flt && flt_argreg <= FLOAT_ARGLAST_REGNUM) |
6df2bf50 | 1141 | { |
e5e33cd9 CV |
1142 | /* Argument goes in a float argument register. */ |
1143 | reg_size = register_size (gdbarch, flt_argreg); | |
e17a4113 | 1144 | regval = extract_unsigned_integer (val, reg_size, byte_order); |
2e952408 CV |
1145 | /* In little endian mode, float types taking two registers |
1146 | (doubles on sh4, long doubles on sh2e, sh3e and sh4) must | |
1147 | be stored swapped in the argument registers. The below | |
1148 | code first writes the first 32 bits in the next but one | |
1149 | register, increments the val and len values accordingly | |
1150 | and then proceeds as normal by writing the second 32 bits | |
c378eb4e | 1151 | into the next register. */ |
b47193f7 | 1152 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE |
2e952408 CV |
1153 | && TYPE_LENGTH (type) == 2 * reg_size) |
1154 | { | |
1155 | regcache_cooked_write_unsigned (regcache, flt_argreg + 1, | |
1156 | regval); | |
1157 | val += reg_size; | |
1158 | len -= reg_size; | |
c378eb4e MS |
1159 | regval = extract_unsigned_integer (val, reg_size, |
1160 | byte_order); | |
2e952408 | 1161 | } |
6df2bf50 MS |
1162 | regcache_cooked_write_unsigned (regcache, flt_argreg++, regval); |
1163 | } | |
afce3d2a | 1164 | else if (!treat_as_flt && argreg <= ARGLAST_REGNUM) |
e5e33cd9 | 1165 | { |
6df2bf50 | 1166 | /* there's room in a register */ |
e5e33cd9 | 1167 | reg_size = register_size (gdbarch, argreg); |
e17a4113 | 1168 | regval = extract_unsigned_integer (val, reg_size, byte_order); |
6df2bf50 MS |
1169 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
1170 | } | |
c378eb4e MS |
1171 | /* Store the value one register at a time or in one step on |
1172 | stack. */ | |
e5e33cd9 CV |
1173 | len -= reg_size; |
1174 | val += reg_size; | |
6df2bf50 MS |
1175 | } |
1176 | } | |
1177 | ||
c055b101 CV |
1178 | if (struct_return) |
1179 | { | |
1180 | if (sh_is_renesas_calling_convention (func_type)) | |
1181 | /* If the function uses the Renesas ABI, subtract another 4 bytes from | |
1182 | the stack and store the struct return address there. */ | |
e17a4113 | 1183 | write_memory_unsigned_integer (sp -= 4, 4, byte_order, struct_addr); |
c055b101 CV |
1184 | else |
1185 | /* Using the gcc ABI, the "struct return pointer" pseudo-argument has | |
1186 | its own dedicated register. */ | |
1187 | regcache_cooked_write_unsigned (regcache, | |
1188 | STRUCT_RETURN_REGNUM, struct_addr); | |
1189 | } | |
1190 | ||
c378eb4e | 1191 | /* Store return address. */ |
55ff77ac | 1192 | regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr); |
6df2bf50 MS |
1193 | |
1194 | /* Update stack pointer. */ | |
3e8c568d | 1195 | regcache_cooked_write_unsigned (regcache, |
b47193f7 | 1196 | gdbarch_sp_regnum (gdbarch), sp); |
6df2bf50 MS |
1197 | |
1198 | return sp; | |
1199 | } | |
1200 | ||
1201 | static CORE_ADDR | |
617daa0e | 1202 | sh_push_dummy_call_nofpu (struct gdbarch *gdbarch, |
7d9b040b | 1203 | struct value *function, |
617daa0e CV |
1204 | struct regcache *regcache, |
1205 | CORE_ADDR bp_addr, | |
1206 | int nargs, struct value **args, | |
1207 | CORE_ADDR sp, int struct_return, | |
6df2bf50 | 1208 | CORE_ADDR struct_addr) |
c906108c | 1209 | { |
e17a4113 | 1210 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
e5e33cd9 CV |
1211 | int stack_offset = 0; |
1212 | int argreg = ARG0_REGNUM; | |
c906108c | 1213 | int argnum; |
c055b101 | 1214 | struct type *func_type = value_type (function); |
c906108c SS |
1215 | struct type *type; |
1216 | CORE_ADDR regval; | |
948f8e3d | 1217 | const gdb_byte *val; |
c055b101 CV |
1218 | int len, reg_size = 0; |
1219 | int pass_on_stack = 0; | |
1220 | int last_reg_arg = INT_MAX; | |
1221 | ||
1222 | /* The Renesas ABI expects all varargs arguments, plus the last | |
1223 | non-vararg argument to be on the stack, no matter how many | |
1224 | registers have been used so far. */ | |
1225 | if (sh_is_renesas_calling_convention (func_type) | |
876cecd0 | 1226 | && TYPE_VARARGS (func_type)) |
c055b101 | 1227 | last_reg_arg = TYPE_NFIELDS (func_type) - 2; |
c906108c | 1228 | |
c378eb4e | 1229 | /* First force sp to a 4-byte alignment. */ |
19f59343 | 1230 | sp = sh_frame_align (gdbarch, sp); |
c906108c | 1231 | |
c378eb4e | 1232 | /* Make room on stack for args. */ |
e5e33cd9 | 1233 | sp -= sh_stack_allocsize (nargs, args); |
c906108c | 1234 | |
c906108c SS |
1235 | /* Now load as many as possible of the first arguments into |
1236 | registers, and push the rest onto the stack. There are 16 bytes | |
1237 | in four registers available. Loop thru args from first to last. */ | |
e5e33cd9 | 1238 | for (argnum = 0; argnum < nargs; argnum++) |
617daa0e | 1239 | { |
4991999e | 1240 | type = value_type (args[argnum]); |
c5aa993b | 1241 | len = TYPE_LENGTH (type); |
d93859e2 | 1242 | val = sh_justify_value_in_reg (gdbarch, args[argnum], len); |
c906108c | 1243 | |
c055b101 | 1244 | /* Some decisions have to be made how various types are handled. |
c378eb4e | 1245 | This also differs in different ABIs. */ |
c055b101 CV |
1246 | pass_on_stack = 0; |
1247 | /* Renesas ABI pushes doubles and long longs entirely on stack. | |
1248 | Same goes for aggregate types. */ | |
1249 | if (sh_is_renesas_calling_convention (func_type) | |
1250 | && ((TYPE_CODE (type) == TYPE_CODE_INT && len >= 8) | |
1251 | || (TYPE_CODE (type) == TYPE_CODE_FLT && len >= 8) | |
1252 | || TYPE_CODE (type) == TYPE_CODE_STRUCT | |
1253 | || TYPE_CODE (type) == TYPE_CODE_UNION)) | |
1254 | pass_on_stack = 1; | |
c906108c SS |
1255 | while (len > 0) |
1256 | { | |
c055b101 CV |
1257 | if (argreg > ARGLAST_REGNUM || pass_on_stack |
1258 | || argnum > last_reg_arg) | |
617daa0e | 1259 | { |
e5e33cd9 | 1260 | /* The remainder of the data goes entirely on the stack, |
c378eb4e | 1261 | 4-byte aligned. */ |
e5e33cd9 CV |
1262 | reg_size = (len + 3) & ~3; |
1263 | write_memory (sp + stack_offset, val, reg_size); | |
617daa0e | 1264 | stack_offset += reg_size; |
c906108c | 1265 | } |
e5e33cd9 | 1266 | else if (argreg <= ARGLAST_REGNUM) |
617daa0e | 1267 | { |
c378eb4e | 1268 | /* There's room in a register. */ |
e5e33cd9 | 1269 | reg_size = register_size (gdbarch, argreg); |
e17a4113 | 1270 | regval = extract_unsigned_integer (val, reg_size, byte_order); |
48db5a3c | 1271 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
c906108c | 1272 | } |
e5e33cd9 CV |
1273 | /* Store the value reg_size bytes at a time. This means that things |
1274 | larger than reg_size bytes may go partly in registers and partly | |
c906108c | 1275 | on the stack. */ |
e5e33cd9 CV |
1276 | len -= reg_size; |
1277 | val += reg_size; | |
c906108c SS |
1278 | } |
1279 | } | |
48db5a3c | 1280 | |
c055b101 CV |
1281 | if (struct_return) |
1282 | { | |
1283 | if (sh_is_renesas_calling_convention (func_type)) | |
1284 | /* If the function uses the Renesas ABI, subtract another 4 bytes from | |
1285 | the stack and store the struct return address there. */ | |
e17a4113 | 1286 | write_memory_unsigned_integer (sp -= 4, 4, byte_order, struct_addr); |
c055b101 CV |
1287 | else |
1288 | /* Using the gcc ABI, the "struct return pointer" pseudo-argument has | |
1289 | its own dedicated register. */ | |
1290 | regcache_cooked_write_unsigned (regcache, | |
1291 | STRUCT_RETURN_REGNUM, struct_addr); | |
1292 | } | |
1293 | ||
c378eb4e | 1294 | /* Store return address. */ |
55ff77ac | 1295 | regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr); |
48db5a3c CV |
1296 | |
1297 | /* Update stack pointer. */ | |
3e8c568d | 1298 | regcache_cooked_write_unsigned (regcache, |
b47193f7 | 1299 | gdbarch_sp_regnum (gdbarch), sp); |
48db5a3c | 1300 | |
c906108c SS |
1301 | return sp; |
1302 | } | |
1303 | ||
cc17453a EZ |
1304 | /* Find a function's return value in the appropriate registers (in |
1305 | regbuf), and copy it into valbuf. Extract from an array REGBUF | |
1306 | containing the (raw) register state a function return value of type | |
1307 | TYPE, and copy that, in virtual format, into VALBUF. */ | |
1308 | static void | |
3ffc5b9b | 1309 | sh_extract_return_value_nofpu (struct type *type, struct regcache *regcache, |
948f8e3d | 1310 | gdb_byte *valbuf) |
c906108c | 1311 | { |
ac7936df | 1312 | struct gdbarch *gdbarch = regcache->arch (); |
e17a4113 | 1313 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
cc17453a | 1314 | int len = TYPE_LENGTH (type); |
617daa0e | 1315 | |
cc17453a | 1316 | if (len <= 4) |
3116c80a | 1317 | { |
48db5a3c CV |
1318 | ULONGEST c; |
1319 | ||
1320 | regcache_cooked_read_unsigned (regcache, R0_REGNUM, &c); | |
e17a4113 | 1321 | store_unsigned_integer (valbuf, len, byte_order, c); |
3116c80a | 1322 | } |
48db5a3c | 1323 | else if (len == 8) |
3116c80a | 1324 | { |
48db5a3c CV |
1325 | int i, regnum = R0_REGNUM; |
1326 | for (i = 0; i < len; i += 4) | |
0b883586 | 1327 | regcache->raw_read (regnum++, valbuf + i); |
3116c80a EZ |
1328 | } |
1329 | else | |
8a3fe4f8 | 1330 | error (_("bad size for return value")); |
3116c80a EZ |
1331 | } |
1332 | ||
1333 | static void | |
3ffc5b9b | 1334 | sh_extract_return_value_fpu (struct type *type, struct regcache *regcache, |
948f8e3d | 1335 | gdb_byte *valbuf) |
3116c80a | 1336 | { |
ac7936df | 1337 | struct gdbarch *gdbarch = regcache->arch (); |
afce3d2a | 1338 | if (sh_treat_as_flt_p (type)) |
3116c80a | 1339 | { |
48db5a3c | 1340 | int len = TYPE_LENGTH (type); |
d93859e2 | 1341 | int i, regnum = gdbarch_fp0_regnum (gdbarch); |
48db5a3c | 1342 | for (i = 0; i < len; i += 4) |
d93859e2 | 1343 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) |
0b883586 | 1344 | regcache->raw_read (regnum++, |
948f8e3d | 1345 | valbuf + len - 4 - i); |
2e952408 | 1346 | else |
0b883586 | 1347 | regcache->raw_read (regnum++, valbuf + i); |
3116c80a | 1348 | } |
cc17453a | 1349 | else |
3ffc5b9b | 1350 | sh_extract_return_value_nofpu (type, regcache, valbuf); |
cc17453a | 1351 | } |
c906108c | 1352 | |
cc17453a EZ |
1353 | /* Write into appropriate registers a function return value |
1354 | of type TYPE, given in virtual format. | |
1355 | If the architecture is sh4 or sh3e, store a function's return value | |
1356 | in the R0 general register or in the FP0 floating point register, | |
c378eb4e MS |
1357 | depending on the type of the return value. In all the other cases |
1358 | the result is stored in r0, left-justified. */ | |
cc17453a | 1359 | static void |
3ffc5b9b | 1360 | sh_store_return_value_nofpu (struct type *type, struct regcache *regcache, |
948f8e3d | 1361 | const gdb_byte *valbuf) |
cc17453a | 1362 | { |
ac7936df | 1363 | struct gdbarch *gdbarch = regcache->arch (); |
e17a4113 | 1364 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
48db5a3c CV |
1365 | ULONGEST val; |
1366 | int len = TYPE_LENGTH (type); | |
d19b71be | 1367 | |
48db5a3c | 1368 | if (len <= 4) |
d19b71be | 1369 | { |
e17a4113 | 1370 | val = extract_unsigned_integer (valbuf, len, byte_order); |
48db5a3c | 1371 | regcache_cooked_write_unsigned (regcache, R0_REGNUM, val); |
d19b71be MS |
1372 | } |
1373 | else | |
48db5a3c CV |
1374 | { |
1375 | int i, regnum = R0_REGNUM; | |
1376 | for (i = 0; i < len; i += 4) | |
10eaee5f | 1377 | regcache->raw_write (regnum++, valbuf + i); |
48db5a3c | 1378 | } |
cc17453a | 1379 | } |
c906108c | 1380 | |
cc17453a | 1381 | static void |
3ffc5b9b | 1382 | sh_store_return_value_fpu (struct type *type, struct regcache *regcache, |
948f8e3d | 1383 | const gdb_byte *valbuf) |
cc17453a | 1384 | { |
ac7936df | 1385 | struct gdbarch *gdbarch = regcache->arch (); |
afce3d2a | 1386 | if (sh_treat_as_flt_p (type)) |
48db5a3c CV |
1387 | { |
1388 | int len = TYPE_LENGTH (type); | |
d93859e2 | 1389 | int i, regnum = gdbarch_fp0_regnum (gdbarch); |
48db5a3c | 1390 | for (i = 0; i < len; i += 4) |
d93859e2 | 1391 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) |
10eaee5f | 1392 | regcache->raw_write (regnum++, |
948f8e3d | 1393 | valbuf + len - 4 - i); |
c8a3b559 | 1394 | else |
10eaee5f | 1395 | regcache->raw_write (regnum++, valbuf + i); |
48db5a3c | 1396 | } |
cc17453a | 1397 | else |
3ffc5b9b | 1398 | sh_store_return_value_nofpu (type, regcache, valbuf); |
c906108c SS |
1399 | } |
1400 | ||
c0409442 | 1401 | static enum return_value_convention |
6a3a010b | 1402 | sh_return_value_nofpu (struct gdbarch *gdbarch, struct value *function, |
c055b101 | 1403 | struct type *type, struct regcache *regcache, |
18cf8b5b | 1404 | gdb_byte *readbuf, const gdb_byte *writebuf) |
c0409442 | 1405 | { |
6a3a010b MR |
1406 | struct type *func_type = function ? value_type (function) : NULL; |
1407 | ||
c055b101 CV |
1408 | if (sh_use_struct_convention_nofpu ( |
1409 | sh_is_renesas_calling_convention (func_type), type)) | |
c0409442 CV |
1410 | return RETURN_VALUE_STRUCT_CONVENTION; |
1411 | if (writebuf) | |
3ffc5b9b | 1412 | sh_store_return_value_nofpu (type, regcache, writebuf); |
c0409442 | 1413 | else if (readbuf) |
3ffc5b9b | 1414 | sh_extract_return_value_nofpu (type, regcache, readbuf); |
c0409442 CV |
1415 | return RETURN_VALUE_REGISTER_CONVENTION; |
1416 | } | |
1417 | ||
1418 | static enum return_value_convention | |
6a3a010b | 1419 | sh_return_value_fpu (struct gdbarch *gdbarch, struct value *function, |
c055b101 | 1420 | struct type *type, struct regcache *regcache, |
18cf8b5b | 1421 | gdb_byte *readbuf, const gdb_byte *writebuf) |
c0409442 | 1422 | { |
6a3a010b MR |
1423 | struct type *func_type = function ? value_type (function) : NULL; |
1424 | ||
c055b101 CV |
1425 | if (sh_use_struct_convention ( |
1426 | sh_is_renesas_calling_convention (func_type), type)) | |
c0409442 CV |
1427 | return RETURN_VALUE_STRUCT_CONVENTION; |
1428 | if (writebuf) | |
3ffc5b9b | 1429 | sh_store_return_value_fpu (type, regcache, writebuf); |
c0409442 | 1430 | else if (readbuf) |
3ffc5b9b | 1431 | sh_extract_return_value_fpu (type, regcache, readbuf); |
c0409442 CV |
1432 | return RETURN_VALUE_REGISTER_CONVENTION; |
1433 | } | |
1434 | ||
da962468 CV |
1435 | static struct type * |
1436 | sh_sh2a_register_type (struct gdbarch *gdbarch, int reg_nr) | |
1437 | { | |
b47193f7 | 1438 | if ((reg_nr >= gdbarch_fp0_regnum (gdbarch) |
da962468 | 1439 | && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM)) |
0dfff4cb | 1440 | return builtin_type (gdbarch)->builtin_float; |
da962468 | 1441 | else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM) |
0dfff4cb | 1442 | return builtin_type (gdbarch)->builtin_double; |
da962468 | 1443 | else |
0dfff4cb | 1444 | return builtin_type (gdbarch)->builtin_int; |
da962468 CV |
1445 | } |
1446 | ||
cc17453a EZ |
1447 | /* Return the GDB type object for the "standard" data type |
1448 | of data in register N. */ | |
cc17453a | 1449 | static struct type * |
48db5a3c | 1450 | sh_sh3e_register_type (struct gdbarch *gdbarch, int reg_nr) |
cc17453a | 1451 | { |
b47193f7 | 1452 | if ((reg_nr >= gdbarch_fp0_regnum (gdbarch) |
617daa0e | 1453 | && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM)) |
0dfff4cb | 1454 | return builtin_type (gdbarch)->builtin_float; |
8db62801 | 1455 | else |
0dfff4cb | 1456 | return builtin_type (gdbarch)->builtin_int; |
cc17453a EZ |
1457 | } |
1458 | ||
7f4dbe94 | 1459 | static struct type * |
0dfff4cb | 1460 | sh_sh4_build_float_register_type (struct gdbarch *gdbarch, int high) |
7f4dbe94 | 1461 | { |
e3506a9f UW |
1462 | return lookup_array_range_type (builtin_type (gdbarch)->builtin_float, |
1463 | 0, high); | |
7f4dbe94 EZ |
1464 | } |
1465 | ||
53116e27 | 1466 | static struct type * |
48db5a3c | 1467 | sh_sh4_register_type (struct gdbarch *gdbarch, int reg_nr) |
53116e27 | 1468 | { |
b47193f7 | 1469 | if ((reg_nr >= gdbarch_fp0_regnum (gdbarch) |
617daa0e | 1470 | && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM)) |
0dfff4cb | 1471 | return builtin_type (gdbarch)->builtin_float; |
617daa0e | 1472 | else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM) |
0dfff4cb | 1473 | return builtin_type (gdbarch)->builtin_double; |
617daa0e | 1474 | else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM) |
0dfff4cb | 1475 | return sh_sh4_build_float_register_type (gdbarch, 3); |
53116e27 | 1476 | else |
0dfff4cb | 1477 | return builtin_type (gdbarch)->builtin_int; |
53116e27 EZ |
1478 | } |
1479 | ||
cc17453a | 1480 | static struct type * |
48db5a3c | 1481 | sh_default_register_type (struct gdbarch *gdbarch, int reg_nr) |
cc17453a | 1482 | { |
0dfff4cb | 1483 | return builtin_type (gdbarch)->builtin_int; |
cc17453a EZ |
1484 | } |
1485 | ||
dda63807 AS |
1486 | /* Is a register in a reggroup? |
1487 | The default code in reggroup.c doesn't identify system registers, some | |
1488 | float registers or any of the vector registers. | |
1489 | TODO: sh2a and dsp registers. */ | |
63807e1d | 1490 | static int |
dda63807 AS |
1491 | sh_register_reggroup_p (struct gdbarch *gdbarch, int regnum, |
1492 | struct reggroup *reggroup) | |
1493 | { | |
b47193f7 UW |
1494 | if (gdbarch_register_name (gdbarch, regnum) == NULL |
1495 | || *gdbarch_register_name (gdbarch, regnum) == '\0') | |
dda63807 AS |
1496 | return 0; |
1497 | ||
1498 | if (reggroup == float_reggroup | |
1499 | && (regnum == FPUL_REGNUM | |
1500 | || regnum == FPSCR_REGNUM)) | |
1501 | return 1; | |
1502 | ||
1503 | if (regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM) | |
1504 | { | |
1505 | if (reggroup == vector_reggroup || reggroup == float_reggroup) | |
1506 | return 1; | |
1507 | if (reggroup == general_reggroup) | |
1508 | return 0; | |
1509 | } | |
1510 | ||
1511 | if (regnum == VBR_REGNUM | |
1512 | || regnum == SR_REGNUM | |
1513 | || regnum == FPSCR_REGNUM | |
1514 | || regnum == SSR_REGNUM | |
1515 | || regnum == SPC_REGNUM) | |
1516 | { | |
1517 | if (reggroup == system_reggroup) | |
1518 | return 1; | |
1519 | if (reggroup == general_reggroup) | |
1520 | return 0; | |
1521 | } | |
1522 | ||
1523 | /* The default code can cope with any other registers. */ | |
1524 | return default_register_reggroup_p (gdbarch, regnum, reggroup); | |
1525 | } | |
1526 | ||
fb409745 | 1527 | /* On the sh4, the DRi pseudo registers are problematic if the target |
c378eb4e | 1528 | is little endian. When the user writes one of those registers, for |
a6521d9a | 1529 | instance with 'set var $dr0=1', we want the double to be stored |
fb409745 | 1530 | like this: |
a6521d9a TS |
1531 | fr0 = 0x00 0x00 0xf0 0x3f |
1532 | fr1 = 0x00 0x00 0x00 0x00 | |
fb409745 EZ |
1533 | |
1534 | This corresponds to little endian byte order & big endian word | |
1535 | order. However if we let gdb write the register w/o conversion, it | |
1536 | will write fr0 and fr1 this way: | |
a6521d9a TS |
1537 | fr0 = 0x00 0x00 0x00 0x00 |
1538 | fr1 = 0x00 0x00 0xf0 0x3f | |
fb409745 EZ |
1539 | because it will consider fr0 and fr1 as a single LE stretch of memory. |
1540 | ||
1541 | To achieve what we want we must force gdb to store things in | |
1542 | floatformat_ieee_double_littlebyte_bigword (which is defined in | |
1543 | include/floatformat.h and libiberty/floatformat.c. | |
1544 | ||
1545 | In case the target is big endian, there is no problem, the | |
1546 | raw bytes will look like: | |
a6521d9a TS |
1547 | fr0 = 0x3f 0xf0 0x00 0x00 |
1548 | fr1 = 0x00 0x00 0x00 0x00 | |
fb409745 EZ |
1549 | |
1550 | The other pseudo registers (the FVs) also don't pose a problem | |
c378eb4e | 1551 | because they are stored as 4 individual FP elements. */ |
fb409745 | 1552 | |
96a5a1d3 UW |
1553 | static struct type * |
1554 | sh_littlebyte_bigword_type (struct gdbarch *gdbarch) | |
1555 | { | |
1556 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1557 | ||
1558 | if (tdep->sh_littlebyte_bigword_type == NULL) | |
1559 | tdep->sh_littlebyte_bigword_type | |
1560 | = arch_float_type (gdbarch, -1, "builtin_type_sh_littlebyte_bigword", | |
1561 | floatformats_ieee_double_littlebyte_bigword); | |
1562 | ||
1563 | return tdep->sh_littlebyte_bigword_type; | |
1564 | } | |
1565 | ||
7bd872fe | 1566 | static void |
a6521d9a | 1567 | sh_register_convert_to_virtual (struct gdbarch *gdbarch, int regnum, |
948f8e3d | 1568 | struct type *type, gdb_byte *from, gdb_byte *to) |
55ff77ac | 1569 | { |
a6521d9a TS |
1570 | if (gdbarch_byte_order (gdbarch) != BFD_ENDIAN_LITTLE) |
1571 | { | |
1572 | /* It is a no-op. */ | |
1573 | memcpy (to, from, register_size (gdbarch, regnum)); | |
1574 | return; | |
1575 | } | |
1576 | ||
617daa0e | 1577 | if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM) |
3b2ca824 UW |
1578 | target_float_convert (from, sh_littlebyte_bigword_type (gdbarch), |
1579 | to, type); | |
283150cd | 1580 | else |
617daa0e CV |
1581 | error |
1582 | ("sh_register_convert_to_virtual called with non DR register number"); | |
283150cd EZ |
1583 | } |
1584 | ||
1585 | static void | |
a6521d9a | 1586 | sh_register_convert_to_raw (struct gdbarch *gdbarch, struct type *type, |
948f8e3d | 1587 | int regnum, const gdb_byte *from, gdb_byte *to) |
283150cd | 1588 | { |
a6521d9a TS |
1589 | if (gdbarch_byte_order (gdbarch) != BFD_ENDIAN_LITTLE) |
1590 | { | |
1591 | /* It is a no-op. */ | |
1592 | memcpy (to, from, register_size (gdbarch, regnum)); | |
1593 | return; | |
1594 | } | |
1595 | ||
617daa0e | 1596 | if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM) |
3b2ca824 UW |
1597 | target_float_convert (from, type, |
1598 | to, sh_littlebyte_bigword_type (gdbarch)); | |
283150cd | 1599 | else |
8a3fe4f8 | 1600 | error (_("sh_register_convert_to_raw called with non DR register number")); |
283150cd EZ |
1601 | } |
1602 | ||
c378eb4e | 1603 | /* For vectors of 4 floating point registers. */ |
1c0159e0 | 1604 | static int |
d93859e2 | 1605 | fv_reg_base_num (struct gdbarch *gdbarch, int fv_regnum) |
1c0159e0 CV |
1606 | { |
1607 | int fp_regnum; | |
1608 | ||
d93859e2 | 1609 | fp_regnum = gdbarch_fp0_regnum (gdbarch) |
3e8c568d | 1610 | + (fv_regnum - FV0_REGNUM) * 4; |
1c0159e0 CV |
1611 | return fp_regnum; |
1612 | } | |
1613 | ||
c378eb4e | 1614 | /* For double precision floating point registers, i.e 2 fp regs. */ |
1c0159e0 | 1615 | static int |
d93859e2 | 1616 | dr_reg_base_num (struct gdbarch *gdbarch, int dr_regnum) |
1c0159e0 CV |
1617 | { |
1618 | int fp_regnum; | |
1619 | ||
d93859e2 | 1620 | fp_regnum = gdbarch_fp0_regnum (gdbarch) |
3e8c568d | 1621 | + (dr_regnum - DR0_REGNUM) * 2; |
1c0159e0 CV |
1622 | return fp_regnum; |
1623 | } | |
1624 | ||
05d1431c PA |
1625 | /* Concatenate PORTIONS contiguous raw registers starting at |
1626 | BASE_REGNUM into BUFFER. */ | |
1627 | ||
1628 | static enum register_status | |
1629 | pseudo_register_read_portions (struct gdbarch *gdbarch, | |
849d0ba8 | 1630 | readable_regcache *regcache, |
05d1431c PA |
1631 | int portions, |
1632 | int base_regnum, gdb_byte *buffer) | |
1633 | { | |
1634 | int portion; | |
1635 | ||
1636 | for (portion = 0; portion < portions; portion++) | |
1637 | { | |
1638 | enum register_status status; | |
1639 | gdb_byte *b; | |
1640 | ||
1641 | b = buffer + register_size (gdbarch, base_regnum) * portion; | |
03f50fc8 | 1642 | status = regcache->raw_read (base_regnum + portion, b); |
05d1431c PA |
1643 | if (status != REG_VALID) |
1644 | return status; | |
1645 | } | |
1646 | ||
1647 | return REG_VALID; | |
1648 | } | |
1649 | ||
1650 | static enum register_status | |
849d0ba8 | 1651 | sh_pseudo_register_read (struct gdbarch *gdbarch, readable_regcache *regcache, |
18cf8b5b | 1652 | int reg_nr, gdb_byte *buffer) |
53116e27 | 1653 | { |
05d1431c | 1654 | int base_regnum; |
05d1431c | 1655 | enum register_status status; |
53116e27 | 1656 | |
9bed62d7 | 1657 | if (reg_nr == PSEUDO_BANK_REGNUM) |
03f50fc8 | 1658 | return regcache->raw_read (BANK_REGNUM, buffer); |
05d1431c | 1659 | else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM) |
7bd872fe | 1660 | { |
4a8a33c8 AH |
1661 | /* Enough space for two float registers. */ |
1662 | gdb_byte temp_buffer[4 * 2]; | |
d93859e2 | 1663 | base_regnum = dr_reg_base_num (gdbarch, reg_nr); |
7bd872fe | 1664 | |
c378eb4e | 1665 | /* Build the value in the provided buffer. */ |
7bd872fe | 1666 | /* Read the real regs for which this one is an alias. */ |
05d1431c PA |
1667 | status = pseudo_register_read_portions (gdbarch, regcache, |
1668 | 2, base_regnum, temp_buffer); | |
1669 | if (status == REG_VALID) | |
1670 | { | |
1671 | /* We must pay attention to the endiannes. */ | |
a6521d9a | 1672 | sh_register_convert_to_virtual (gdbarch, reg_nr, |
05d1431c PA |
1673 | register_type (gdbarch, reg_nr), |
1674 | temp_buffer, buffer); | |
1675 | } | |
1676 | return status; | |
7bd872fe | 1677 | } |
617daa0e | 1678 | else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM) |
53116e27 | 1679 | { |
d93859e2 | 1680 | base_regnum = fv_reg_base_num (gdbarch, reg_nr); |
7bd872fe EZ |
1681 | |
1682 | /* Read the real regs for which this one is an alias. */ | |
05d1431c PA |
1683 | return pseudo_register_read_portions (gdbarch, regcache, |
1684 | 4, base_regnum, buffer); | |
53116e27 | 1685 | } |
05d1431c PA |
1686 | else |
1687 | gdb_assert_not_reached ("invalid pseudo register number"); | |
53116e27 EZ |
1688 | } |
1689 | ||
a78f21af | 1690 | static void |
d8124050 | 1691 | sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, |
18cf8b5b | 1692 | int reg_nr, const gdb_byte *buffer) |
53116e27 EZ |
1693 | { |
1694 | int base_regnum, portion; | |
1695 | ||
9bed62d7 CV |
1696 | if (reg_nr == PSEUDO_BANK_REGNUM) |
1697 | { | |
1698 | /* When the bank register is written to, the whole register bank | |
1699 | is switched and all values in the bank registers must be read | |
c378eb4e | 1700 | from the target/sim again. We're just invalidating the regcache |
9bed62d7 CV |
1701 | so that a re-read happens next time it's necessary. */ |
1702 | int bregnum; | |
1703 | ||
10eaee5f | 1704 | regcache->raw_write (BANK_REGNUM, buffer); |
9bed62d7 | 1705 | for (bregnum = R0_BANK0_REGNUM; bregnum < MACLB_REGNUM; ++bregnum) |
6aa7d724 | 1706 | regcache->invalidate (bregnum); |
9bed62d7 CV |
1707 | } |
1708 | else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM) | |
53116e27 | 1709 | { |
4a8a33c8 AH |
1710 | /* Enough space for two float registers. */ |
1711 | gdb_byte temp_buffer[4 * 2]; | |
d93859e2 | 1712 | base_regnum = dr_reg_base_num (gdbarch, reg_nr); |
53116e27 | 1713 | |
c378eb4e | 1714 | /* We must pay attention to the endiannes. */ |
a6521d9a | 1715 | sh_register_convert_to_raw (gdbarch, register_type (gdbarch, reg_nr), |
b66ba949 | 1716 | reg_nr, buffer, temp_buffer); |
7bd872fe | 1717 | |
53116e27 EZ |
1718 | /* Write the real regs for which this one is an alias. */ |
1719 | for (portion = 0; portion < 2; portion++) | |
10eaee5f | 1720 | regcache->raw_write (base_regnum + portion, |
0818c12a | 1721 | (temp_buffer |
617daa0e CV |
1722 | + register_size (gdbarch, |
1723 | base_regnum) * portion)); | |
53116e27 | 1724 | } |
617daa0e | 1725 | else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM) |
53116e27 | 1726 | { |
d93859e2 | 1727 | base_regnum = fv_reg_base_num (gdbarch, reg_nr); |
53116e27 EZ |
1728 | |
1729 | /* Write the real regs for which this one is an alias. */ | |
1730 | for (portion = 0; portion < 4; portion++) | |
10eaee5f | 1731 | regcache->raw_write (base_regnum + portion, |
948f8e3d | 1732 | (buffer |
617daa0e CV |
1733 | + register_size (gdbarch, |
1734 | base_regnum) * portion)); | |
53116e27 EZ |
1735 | } |
1736 | } | |
1737 | ||
2f14585c | 1738 | static int |
e7faf938 | 1739 | sh_dsp_register_sim_regno (struct gdbarch *gdbarch, int nr) |
2f14585c | 1740 | { |
e7faf938 MD |
1741 | if (legacy_register_sim_regno (gdbarch, nr) < 0) |
1742 | return legacy_register_sim_regno (gdbarch, nr); | |
f2ea0907 CV |
1743 | if (nr >= DSR_REGNUM && nr <= Y1_REGNUM) |
1744 | return nr - DSR_REGNUM + SIM_SH_DSR_REGNUM; | |
1745 | if (nr == MOD_REGNUM) | |
2f14585c | 1746 | return SIM_SH_MOD_REGNUM; |
f2ea0907 | 1747 | if (nr == RS_REGNUM) |
2f14585c | 1748 | return SIM_SH_RS_REGNUM; |
f2ea0907 | 1749 | if (nr == RE_REGNUM) |
2f14585c | 1750 | return SIM_SH_RE_REGNUM; |
76cd2bd9 CV |
1751 | if (nr >= DSP_R0_BANK_REGNUM && nr <= DSP_R7_BANK_REGNUM) |
1752 | return nr - DSP_R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM; | |
2f14585c JR |
1753 | return nr; |
1754 | } | |
1c0159e0 | 1755 | |
da962468 | 1756 | static int |
e7faf938 | 1757 | sh_sh2a_register_sim_regno (struct gdbarch *gdbarch, int nr) |
da962468 CV |
1758 | { |
1759 | switch (nr) | |
1760 | { | |
1761 | case TBR_REGNUM: | |
1762 | return SIM_SH_TBR_REGNUM; | |
1763 | case IBNR_REGNUM: | |
1764 | return SIM_SH_IBNR_REGNUM; | |
1765 | case IBCR_REGNUM: | |
1766 | return SIM_SH_IBCR_REGNUM; | |
1767 | case BANK_REGNUM: | |
1768 | return SIM_SH_BANK_REGNUM; | |
1769 | case MACLB_REGNUM: | |
1770 | return SIM_SH_BANK_MACL_REGNUM; | |
1771 | case GBRB_REGNUM: | |
1772 | return SIM_SH_BANK_GBR_REGNUM; | |
1773 | case PRB_REGNUM: | |
1774 | return SIM_SH_BANK_PR_REGNUM; | |
1775 | case IVNB_REGNUM: | |
1776 | return SIM_SH_BANK_IVN_REGNUM; | |
1777 | case MACHB_REGNUM: | |
1778 | return SIM_SH_BANK_MACH_REGNUM; | |
1779 | default: | |
1780 | break; | |
1781 | } | |
e7faf938 | 1782 | return legacy_register_sim_regno (gdbarch, nr); |
da962468 CV |
1783 | } |
1784 | ||
357d3800 AS |
1785 | /* Set up the register unwinding such that call-clobbered registers are |
1786 | not displayed in frames >0 because the true value is not certain. | |
1787 | The 'undefined' registers will show up as 'not available' unless the | |
1788 | CFI says otherwise. | |
1789 | ||
1790 | This function is currently set up for SH4 and compatible only. */ | |
1791 | ||
1792 | static void | |
1793 | sh_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
aff37fc1 | 1794 | struct dwarf2_frame_state_reg *reg, |
4a4e5149 | 1795 | struct frame_info *this_frame) |
357d3800 AS |
1796 | { |
1797 | /* Mark the PC as the destination for the return address. */ | |
b47193f7 | 1798 | if (regnum == gdbarch_pc_regnum (gdbarch)) |
357d3800 AS |
1799 | reg->how = DWARF2_FRAME_REG_RA; |
1800 | ||
1801 | /* Mark the stack pointer as the call frame address. */ | |
b47193f7 | 1802 | else if (regnum == gdbarch_sp_regnum (gdbarch)) |
357d3800 AS |
1803 | reg->how = DWARF2_FRAME_REG_CFA; |
1804 | ||
1805 | /* The above was taken from the default init_reg in dwarf2-frame.c | |
1806 | while the below is SH specific. */ | |
1807 | ||
1808 | /* Caller save registers. */ | |
1809 | else if ((regnum >= R0_REGNUM && regnum <= R0_REGNUM+7) | |
1810 | || (regnum >= FR0_REGNUM && regnum <= FR0_REGNUM+11) | |
1811 | || (regnum >= DR0_REGNUM && regnum <= DR0_REGNUM+5) | |
1812 | || (regnum >= FV0_REGNUM && regnum <= FV0_REGNUM+2) | |
1813 | || (regnum == MACH_REGNUM) | |
1814 | || (regnum == MACL_REGNUM) | |
1815 | || (regnum == FPUL_REGNUM) | |
1816 | || (regnum == SR_REGNUM)) | |
1817 | reg->how = DWARF2_FRAME_REG_UNDEFINED; | |
1818 | ||
1819 | /* Callee save registers. */ | |
1820 | else if ((regnum >= R0_REGNUM+8 && regnum <= R0_REGNUM+15) | |
1821 | || (regnum >= FR0_REGNUM+12 && regnum <= FR0_REGNUM+15) | |
1822 | || (regnum >= DR0_REGNUM+6 && regnum <= DR0_REGNUM+8) | |
1823 | || (regnum == FV0_REGNUM+3)) | |
1824 | reg->how = DWARF2_FRAME_REG_SAME_VALUE; | |
1825 | ||
1826 | /* Other registers. These are not in the ABI and may or may not | |
1827 | mean anything in frames >0 so don't show them. */ | |
1828 | else if ((regnum >= R0_BANK0_REGNUM && regnum <= R0_BANK0_REGNUM+15) | |
1829 | || (regnum == GBR_REGNUM) | |
1830 | || (regnum == VBR_REGNUM) | |
1831 | || (regnum == FPSCR_REGNUM) | |
1832 | || (regnum == SSR_REGNUM) | |
1833 | || (regnum == SPC_REGNUM)) | |
1834 | reg->how = DWARF2_FRAME_REG_UNDEFINED; | |
1835 | } | |
1836 | ||
1c0159e0 CV |
1837 | static struct sh_frame_cache * |
1838 | sh_alloc_frame_cache (void) | |
1839 | { | |
1840 | struct sh_frame_cache *cache; | |
1841 | int i; | |
1842 | ||
1843 | cache = FRAME_OBSTACK_ZALLOC (struct sh_frame_cache); | |
1844 | ||
1845 | /* Base address. */ | |
1846 | cache->base = 0; | |
1847 | cache->saved_sp = 0; | |
1848 | cache->sp_offset = 0; | |
1849 | cache->pc = 0; | |
1850 | ||
1851 | /* Frameless until proven otherwise. */ | |
1852 | cache->uses_fp = 0; | |
617daa0e | 1853 | |
1c0159e0 CV |
1854 | /* Saved registers. We initialize these to -1 since zero is a valid |
1855 | offset (that's where fp is supposed to be stored). */ | |
1856 | for (i = 0; i < SH_NUM_REGS; i++) | |
1857 | { | |
1858 | cache->saved_regs[i] = -1; | |
1859 | } | |
617daa0e | 1860 | |
1c0159e0 | 1861 | return cache; |
617daa0e | 1862 | } |
1c0159e0 CV |
1863 | |
1864 | static struct sh_frame_cache * | |
94afd7a6 | 1865 | sh_frame_cache (struct frame_info *this_frame, void **this_cache) |
1c0159e0 | 1866 | { |
e17a4113 | 1867 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1c0159e0 CV |
1868 | struct sh_frame_cache *cache; |
1869 | CORE_ADDR current_pc; | |
1870 | int i; | |
1871 | ||
1872 | if (*this_cache) | |
19ba03f4 | 1873 | return (struct sh_frame_cache *) *this_cache; |
1c0159e0 CV |
1874 | |
1875 | cache = sh_alloc_frame_cache (); | |
1876 | *this_cache = cache; | |
1877 | ||
1878 | /* In principle, for normal frames, fp holds the frame pointer, | |
1879 | which holds the base address for the current stack frame. | |
1880 | However, for functions that don't need it, the frame pointer is | |
1881 | optional. For these "frameless" functions the frame pointer is | |
c378eb4e | 1882 | actually the frame pointer of the calling frame. */ |
94afd7a6 | 1883 | cache->base = get_frame_register_unsigned (this_frame, FP_REGNUM); |
1c0159e0 CV |
1884 | if (cache->base == 0) |
1885 | return cache; | |
1886 | ||
94afd7a6 UW |
1887 | cache->pc = get_frame_func (this_frame); |
1888 | current_pc = get_frame_pc (this_frame); | |
1c0159e0 | 1889 | if (cache->pc != 0) |
d2ca4222 UW |
1890 | { |
1891 | ULONGEST fpscr; | |
9fc05685 KB |
1892 | |
1893 | /* Check for the existence of the FPSCR register. If it exists, | |
1894 | fetch its value for use in prologue analysis. Passing a zero | |
1895 | value is the best choice for architecture variants upon which | |
1896 | there's no FPSCR register. */ | |
1897 | if (gdbarch_register_reggroup_p (gdbarch, FPSCR_REGNUM, all_reggroup)) | |
1898 | fpscr = get_frame_register_unsigned (this_frame, FPSCR_REGNUM); | |
1899 | else | |
1900 | fpscr = 0; | |
1901 | ||
e17a4113 | 1902 | sh_analyze_prologue (gdbarch, cache->pc, current_pc, cache, fpscr); |
d2ca4222 | 1903 | } |
617daa0e | 1904 | |
1c0159e0 CV |
1905 | if (!cache->uses_fp) |
1906 | { | |
1907 | /* We didn't find a valid frame, which means that CACHE->base | |
1908 | currently holds the frame pointer for our calling frame. If | |
1909 | we're at the start of a function, or somewhere half-way its | |
1910 | prologue, the function's frame probably hasn't been fully | |
1911 | setup yet. Try to reconstruct the base address for the stack | |
1912 | frame by looking at the stack pointer. For truly "frameless" | |
1913 | functions this might work too. */ | |
94afd7a6 | 1914 | cache->base = get_frame_register_unsigned |
e17a4113 | 1915 | (this_frame, gdbarch_sp_regnum (gdbarch)); |
1c0159e0 CV |
1916 | } |
1917 | ||
1918 | /* Now that we have the base address for the stack frame we can | |
1919 | calculate the value of sp in the calling frame. */ | |
1920 | cache->saved_sp = cache->base + cache->sp_offset; | |
1921 | ||
1922 | /* Adjust all the saved registers such that they contain addresses | |
1923 | instead of offsets. */ | |
1924 | for (i = 0; i < SH_NUM_REGS; i++) | |
1925 | if (cache->saved_regs[i] != -1) | |
1926 | cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i] - 4; | |
1927 | ||
1928 | return cache; | |
1929 | } | |
1930 | ||
94afd7a6 UW |
1931 | static struct value * |
1932 | sh_frame_prev_register (struct frame_info *this_frame, | |
1933 | void **this_cache, int regnum) | |
1c0159e0 | 1934 | { |
94afd7a6 UW |
1935 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1936 | struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache); | |
1c0159e0 CV |
1937 | |
1938 | gdb_assert (regnum >= 0); | |
1939 | ||
b47193f7 | 1940 | if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp) |
94afd7a6 | 1941 | return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp); |
1c0159e0 CV |
1942 | |
1943 | /* The PC of the previous frame is stored in the PR register of | |
1944 | the current frame. Frob regnum so that we pull the value from | |
1945 | the correct place. */ | |
b47193f7 | 1946 | if (regnum == gdbarch_pc_regnum (gdbarch)) |
1c0159e0 CV |
1947 | regnum = PR_REGNUM; |
1948 | ||
1949 | if (regnum < SH_NUM_REGS && cache->saved_regs[regnum] != -1) | |
94afd7a6 UW |
1950 | return frame_unwind_got_memory (this_frame, regnum, |
1951 | cache->saved_regs[regnum]); | |
1c0159e0 | 1952 | |
94afd7a6 | 1953 | return frame_unwind_got_register (this_frame, regnum, regnum); |
1c0159e0 CV |
1954 | } |
1955 | ||
1956 | static void | |
94afd7a6 | 1957 | sh_frame_this_id (struct frame_info *this_frame, void **this_cache, |
617daa0e CV |
1958 | struct frame_id *this_id) |
1959 | { | |
94afd7a6 | 1960 | struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache); |
1c0159e0 CV |
1961 | |
1962 | /* This marks the outermost frame. */ | |
1963 | if (cache->base == 0) | |
1964 | return; | |
1965 | ||
1966 | *this_id = frame_id_build (cache->saved_sp, cache->pc); | |
617daa0e | 1967 | } |
1c0159e0 | 1968 | |
617daa0e | 1969 | static const struct frame_unwind sh_frame_unwind = { |
1c0159e0 | 1970 | NORMAL_FRAME, |
8fbca658 | 1971 | default_frame_unwind_stop_reason, |
1c0159e0 | 1972 | sh_frame_this_id, |
94afd7a6 UW |
1973 | sh_frame_prev_register, |
1974 | NULL, | |
1975 | default_frame_sniffer | |
1c0159e0 CV |
1976 | }; |
1977 | ||
1c0159e0 CV |
1978 | static CORE_ADDR |
1979 | sh_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1980 | { | |
3e8c568d | 1981 | return frame_unwind_register_unsigned (next_frame, |
b47193f7 | 1982 | gdbarch_sp_regnum (gdbarch)); |
1c0159e0 CV |
1983 | } |
1984 | ||
1985 | static CORE_ADDR | |
1986 | sh_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1987 | { | |
3e8c568d | 1988 | return frame_unwind_register_unsigned (next_frame, |
b47193f7 | 1989 | gdbarch_pc_regnum (gdbarch)); |
1c0159e0 CV |
1990 | } |
1991 | ||
1992 | static struct frame_id | |
94afd7a6 | 1993 | sh_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
1c0159e0 | 1994 | { |
94afd7a6 UW |
1995 | CORE_ADDR sp = get_frame_register_unsigned (this_frame, |
1996 | gdbarch_sp_regnum (gdbarch)); | |
1997 | return frame_id_build (sp, get_frame_pc (this_frame)); | |
1c0159e0 CV |
1998 | } |
1999 | ||
2000 | static CORE_ADDR | |
94afd7a6 | 2001 | sh_frame_base_address (struct frame_info *this_frame, void **this_cache) |
617daa0e | 2002 | { |
94afd7a6 | 2003 | struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache); |
617daa0e | 2004 | |
1c0159e0 CV |
2005 | return cache->base; |
2006 | } | |
617daa0e CV |
2007 | |
2008 | static const struct frame_base sh_frame_base = { | |
1c0159e0 CV |
2009 | &sh_frame_unwind, |
2010 | sh_frame_base_address, | |
2011 | sh_frame_base_address, | |
2012 | sh_frame_base_address | |
617daa0e | 2013 | }; |
1c0159e0 | 2014 | |
cb2cf4ce TS |
2015 | static struct sh_frame_cache * |
2016 | sh_make_stub_cache (struct frame_info *this_frame) | |
2017 | { | |
2018 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2019 | struct sh_frame_cache *cache; | |
2020 | ||
2021 | cache = sh_alloc_frame_cache (); | |
2022 | ||
2023 | cache->saved_sp | |
2024 | = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch)); | |
2025 | ||
2026 | return cache; | |
2027 | } | |
2028 | ||
2029 | static void | |
2030 | sh_stub_this_id (struct frame_info *this_frame, void **this_cache, | |
2031 | struct frame_id *this_id) | |
2032 | { | |
2033 | struct sh_frame_cache *cache; | |
2034 | ||
2035 | if (*this_cache == NULL) | |
2036 | *this_cache = sh_make_stub_cache (this_frame); | |
19ba03f4 | 2037 | cache = (struct sh_frame_cache *) *this_cache; |
cb2cf4ce TS |
2038 | |
2039 | *this_id = frame_id_build (cache->saved_sp, get_frame_pc (this_frame)); | |
2040 | } | |
2041 | ||
2042 | static int | |
2043 | sh_stub_unwind_sniffer (const struct frame_unwind *self, | |
2044 | struct frame_info *this_frame, | |
2045 | void **this_prologue_cache) | |
2046 | { | |
2047 | CORE_ADDR addr_in_block; | |
2048 | ||
2049 | addr_in_block = get_frame_address_in_block (this_frame); | |
3e5d3a5a | 2050 | if (in_plt_section (addr_in_block)) |
cb2cf4ce TS |
2051 | return 1; |
2052 | ||
2053 | return 0; | |
2054 | } | |
2055 | ||
2056 | static const struct frame_unwind sh_stub_unwind = | |
2057 | { | |
2058 | NORMAL_FRAME, | |
2059 | default_frame_unwind_stop_reason, | |
2060 | sh_stub_this_id, | |
2061 | sh_frame_prev_register, | |
2062 | NULL, | |
2063 | sh_stub_unwind_sniffer | |
2064 | }; | |
2065 | ||
c9cf6e20 MG |
2066 | /* Implement the stack_frame_destroyed_p gdbarch method. |
2067 | ||
2068 | The epilogue is defined here as the area at the end of a function, | |
1c0159e0 | 2069 | either on the `ret' instruction itself or after an instruction which |
c378eb4e | 2070 | destroys the function's stack frame. */ |
c9cf6e20 | 2071 | |
1c0159e0 | 2072 | static int |
c9cf6e20 | 2073 | sh_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
1c0159e0 | 2074 | { |
e17a4113 | 2075 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1c0159e0 CV |
2076 | CORE_ADDR func_addr = 0, func_end = 0; |
2077 | ||
2078 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
2079 | { | |
2080 | ULONGEST inst; | |
2081 | /* The sh epilogue is max. 14 bytes long. Give another 14 bytes | |
2082 | for a nop and some fixed data (e.g. big offsets) which are | |
617daa0e | 2083 | unfortunately also treated as part of the function (which |
c378eb4e | 2084 | means, they are below func_end. */ |
1c0159e0 CV |
2085 | CORE_ADDR addr = func_end - 28; |
2086 | if (addr < func_addr + 4) | |
617daa0e | 2087 | addr = func_addr + 4; |
1c0159e0 CV |
2088 | if (pc < addr) |
2089 | return 0; | |
2090 | ||
c378eb4e | 2091 | /* First search forward until hitting an rts. */ |
1c0159e0 | 2092 | while (addr < func_end |
e17a4113 | 2093 | && !IS_RTS (read_memory_unsigned_integer (addr, 2, byte_order))) |
1c0159e0 CV |
2094 | addr += 2; |
2095 | if (addr >= func_end) | |
617daa0e | 2096 | return 0; |
1c0159e0 CV |
2097 | |
2098 | /* At this point we should find a mov.l @r15+,r14 instruction, | |
2099 | either before or after the rts. If not, then the function has | |
c378eb4e | 2100 | probably no "normal" epilogue and we bail out here. */ |
e17a4113 UW |
2101 | inst = read_memory_unsigned_integer (addr - 2, 2, byte_order); |
2102 | if (IS_RESTORE_FP (read_memory_unsigned_integer (addr - 2, 2, | |
2103 | byte_order))) | |
617daa0e | 2104 | addr -= 2; |
e17a4113 UW |
2105 | else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr + 2, 2, |
2106 | byte_order))) | |
1c0159e0 CV |
2107 | return 0; |
2108 | ||
e17a4113 | 2109 | inst = read_memory_unsigned_integer (addr - 2, 2, byte_order); |
03131d99 | 2110 | |
c378eb4e | 2111 | /* Step over possible lds.l @r15+,macl. */ |
03131d99 CV |
2112 | if (IS_MACL_LDS (inst)) |
2113 | { | |
2114 | addr -= 2; | |
e17a4113 | 2115 | inst = read_memory_unsigned_integer (addr - 2, 2, byte_order); |
03131d99 CV |
2116 | } |
2117 | ||
c378eb4e | 2118 | /* Step over possible lds.l @r15+,pr. */ |
1c0159e0 | 2119 | if (IS_LDS (inst)) |
617daa0e | 2120 | { |
1c0159e0 | 2121 | addr -= 2; |
e17a4113 | 2122 | inst = read_memory_unsigned_integer (addr - 2, 2, byte_order); |
1c0159e0 CV |
2123 | } |
2124 | ||
c378eb4e | 2125 | /* Step over possible mov r14,r15. */ |
1c0159e0 | 2126 | if (IS_MOV_FP_SP (inst)) |
617daa0e | 2127 | { |
1c0159e0 | 2128 | addr -= 2; |
e17a4113 | 2129 | inst = read_memory_unsigned_integer (addr - 2, 2, byte_order); |
1c0159e0 CV |
2130 | } |
2131 | ||
2132 | /* Now check for FP adjustments, using add #imm,r14 or add rX, r14 | |
c378eb4e | 2133 | instructions. */ |
1c0159e0 | 2134 | while (addr > func_addr + 4 |
617daa0e | 2135 | && (IS_ADD_REG_TO_FP (inst) || IS_ADD_IMM_FP (inst))) |
1c0159e0 CV |
2136 | { |
2137 | addr -= 2; | |
e17a4113 | 2138 | inst = read_memory_unsigned_integer (addr - 2, 2, byte_order); |
1c0159e0 CV |
2139 | } |
2140 | ||
03131d99 CV |
2141 | /* On SH2a check if the previous instruction was perhaps a MOVI20. |
2142 | That's allowed for the epilogue. */ | |
2143 | if ((gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a | |
2144 | || gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a_nofpu) | |
2145 | && addr > func_addr + 6 | |
e17a4113 UW |
2146 | && IS_MOVI20 (read_memory_unsigned_integer (addr - 4, 2, |
2147 | byte_order))) | |
03131d99 CV |
2148 | addr -= 4; |
2149 | ||
1c0159e0 CV |
2150 | if (pc >= addr) |
2151 | return 1; | |
2152 | } | |
2153 | return 0; | |
2154 | } | |
c9ac0a72 AS |
2155 | |
2156 | ||
2157 | /* Supply register REGNUM from the buffer specified by REGS and LEN | |
2158 | in the register set REGSET to register cache REGCACHE. | |
2159 | REGTABLE specifies where each register can be found in REGS. | |
2160 | If REGNUM is -1, do this for all registers in REGSET. */ | |
2161 | ||
2162 | void | |
2163 | sh_corefile_supply_regset (const struct regset *regset, | |
2164 | struct regcache *regcache, | |
2165 | int regnum, const void *regs, size_t len) | |
2166 | { | |
ac7936df | 2167 | struct gdbarch *gdbarch = regcache->arch (); |
c9ac0a72 AS |
2168 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2169 | const struct sh_corefile_regmap *regmap = (regset == &sh_corefile_gregset | |
2170 | ? tdep->core_gregmap | |
2171 | : tdep->core_fpregmap); | |
2172 | int i; | |
2173 | ||
2174 | for (i = 0; regmap[i].regnum != -1; i++) | |
2175 | { | |
2176 | if ((regnum == -1 || regnum == regmap[i].regnum) | |
2177 | && regmap[i].offset + 4 <= len) | |
73e1c03f SM |
2178 | regcache->raw_supply |
2179 | (regmap[i].regnum, (char *) regs + regmap[i].offset); | |
c9ac0a72 AS |
2180 | } |
2181 | } | |
2182 | ||
2183 | /* Collect register REGNUM in the register set REGSET from register cache | |
2184 | REGCACHE into the buffer specified by REGS and LEN. | |
2185 | REGTABLE specifies where each register can be found in REGS. | |
2186 | If REGNUM is -1, do this for all registers in REGSET. */ | |
2187 | ||
2188 | void | |
2189 | sh_corefile_collect_regset (const struct regset *regset, | |
2190 | const struct regcache *regcache, | |
2191 | int regnum, void *regs, size_t len) | |
2192 | { | |
ac7936df | 2193 | struct gdbarch *gdbarch = regcache->arch (); |
c9ac0a72 AS |
2194 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2195 | const struct sh_corefile_regmap *regmap = (regset == &sh_corefile_gregset | |
2196 | ? tdep->core_gregmap | |
2197 | : tdep->core_fpregmap); | |
2198 | int i; | |
2199 | ||
2200 | for (i = 0; regmap[i].regnum != -1; i++) | |
2201 | { | |
2202 | if ((regnum == -1 || regnum == regmap[i].regnum) | |
2203 | && regmap[i].offset + 4 <= len) | |
34a79281 | 2204 | regcache->raw_collect (regmap[i].regnum, |
c9ac0a72 AS |
2205 | (char *)regs + regmap[i].offset); |
2206 | } | |
2207 | } | |
2208 | ||
2209 | /* The following two regsets have the same contents, so it is tempting to | |
2210 | unify them, but they are distiguished by their address, so don't. */ | |
2211 | ||
3ca7dae4 | 2212 | const struct regset sh_corefile_gregset = |
c9ac0a72 AS |
2213 | { |
2214 | NULL, | |
2215 | sh_corefile_supply_regset, | |
2216 | sh_corefile_collect_regset | |
2217 | }; | |
2218 | ||
3ca7dae4 | 2219 | static const struct regset sh_corefile_fpregset = |
c9ac0a72 AS |
2220 | { |
2221 | NULL, | |
2222 | sh_corefile_supply_regset, | |
2223 | sh_corefile_collect_regset | |
2224 | }; | |
2225 | ||
c6d41a6f AA |
2226 | static void |
2227 | sh_iterate_over_regset_sections (struct gdbarch *gdbarch, | |
2228 | iterate_over_regset_sections_cb *cb, | |
2229 | void *cb_data, | |
2230 | const struct regcache *regcache) | |
c9ac0a72 AS |
2231 | { |
2232 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2233 | ||
c6d41a6f | 2234 | if (tdep->core_gregmap != NULL) |
a616bb94 AH |
2235 | cb (".reg", tdep->sizeof_gregset, tdep->sizeof_gregset, |
2236 | &sh_corefile_gregset, NULL, cb_data); | |
c9ac0a72 | 2237 | |
c6d41a6f | 2238 | if (tdep->core_fpregmap != NULL) |
a616bb94 AH |
2239 | cb (".reg2", tdep->sizeof_fpregset, tdep->sizeof_fpregset, |
2240 | &sh_corefile_fpregset, NULL, cb_data); | |
c9ac0a72 | 2241 | } |
18648a37 YQ |
2242 | |
2243 | /* This is the implementation of gdbarch method | |
2244 | return_in_first_hidden_param_p. */ | |
2245 | ||
2246 | static int | |
2247 | sh_return_in_first_hidden_param_p (struct gdbarch *gdbarch, | |
2248 | struct type *type) | |
2249 | { | |
2250 | return 0; | |
2251 | } | |
2252 | ||
ccf00f21 | 2253 | \f |
cc17453a EZ |
2254 | |
2255 | static struct gdbarch * | |
fba45db2 | 2256 | sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
cc17453a | 2257 | { |
cc17453a | 2258 | struct gdbarch *gdbarch; |
c9ac0a72 | 2259 | struct gdbarch_tdep *tdep; |
d658f924 | 2260 | |
4be87837 DJ |
2261 | /* If there is already a candidate, use it. */ |
2262 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
2263 | if (arches != NULL) | |
2264 | return arches->gdbarch; | |
cc17453a EZ |
2265 | |
2266 | /* None found, create a new architecture from the information | |
c378eb4e | 2267 | provided. */ |
41bf6aca | 2268 | tdep = XCNEW (struct gdbarch_tdep); |
c9ac0a72 | 2269 | gdbarch = gdbarch_alloc (&info, tdep); |
cc17453a | 2270 | |
48db5a3c CV |
2271 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); |
2272 | set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
ec920329 | 2273 | set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
48db5a3c | 2274 | set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); |
53375380 PA |
2275 | |
2276 | set_gdbarch_wchar_bit (gdbarch, 2 * TARGET_CHAR_BIT); | |
2277 | set_gdbarch_wchar_signed (gdbarch, 0); | |
2278 | ||
48db5a3c CV |
2279 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
2280 | set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
2281 | set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
a38d2a54 | 2282 | set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
48db5a3c | 2283 | |
f2ea0907 | 2284 | set_gdbarch_num_regs (gdbarch, SH_NUM_REGS); |
a38d2a54 | 2285 | set_gdbarch_sp_regnum (gdbarch, 15); |
a38d2a54 | 2286 | set_gdbarch_pc_regnum (gdbarch, 16); |
48db5a3c CV |
2287 | set_gdbarch_fp0_regnum (gdbarch, -1); |
2288 | set_gdbarch_num_pseudo_regs (gdbarch, 0); | |
2289 | ||
1c0159e0 | 2290 | set_gdbarch_register_type (gdbarch, sh_default_register_type); |
dda63807 | 2291 | set_gdbarch_register_reggroup_p (gdbarch, sh_register_reggroup_p); |
1c0159e0 | 2292 | |
04180708 YQ |
2293 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, sh_breakpoint_kind_from_pc); |
2294 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, sh_sw_breakpoint_from_kind); | |
48db5a3c | 2295 | |
2f14585c | 2296 | set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno); |
48db5a3c | 2297 | |
c0409442 | 2298 | set_gdbarch_return_value (gdbarch, sh_return_value_nofpu); |
1c0159e0 | 2299 | |
48db5a3c CV |
2300 | set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue); |
2301 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
48db5a3c | 2302 | |
1c0159e0 | 2303 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu); |
18648a37 YQ |
2304 | set_gdbarch_return_in_first_hidden_param_p (gdbarch, |
2305 | sh_return_in_first_hidden_param_p); | |
1c0159e0 | 2306 | |
48db5a3c CV |
2307 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); |
2308 | ||
19f59343 | 2309 | set_gdbarch_frame_align (gdbarch, sh_frame_align); |
1c0159e0 CV |
2310 | set_gdbarch_unwind_sp (gdbarch, sh_unwind_sp); |
2311 | set_gdbarch_unwind_pc (gdbarch, sh_unwind_pc); | |
94afd7a6 | 2312 | set_gdbarch_dummy_id (gdbarch, sh_dummy_id); |
1c0159e0 CV |
2313 | frame_base_set_default (gdbarch, &sh_frame_base); |
2314 | ||
c9cf6e20 | 2315 | set_gdbarch_stack_frame_destroyed_p (gdbarch, sh_stack_frame_destroyed_p); |
cc17453a | 2316 | |
357d3800 AS |
2317 | dwarf2_frame_set_init_reg (gdbarch, sh_dwarf2_frame_init_reg); |
2318 | ||
c6d41a6f AA |
2319 | set_gdbarch_iterate_over_regset_sections |
2320 | (gdbarch, sh_iterate_over_regset_sections); | |
c9ac0a72 | 2321 | |
cc17453a | 2322 | switch (info.bfd_arch_info->mach) |
8db62801 | 2323 | { |
cc17453a | 2324 | case bfd_mach_sh: |
48db5a3c | 2325 | set_gdbarch_register_name (gdbarch, sh_sh_register_name); |
cc17453a | 2326 | break; |
1c0159e0 | 2327 | |
cc17453a | 2328 | case bfd_mach_sh2: |
48db5a3c | 2329 | set_gdbarch_register_name (gdbarch, sh_sh_register_name); |
617daa0e | 2330 | break; |
1c0159e0 | 2331 | |
2d188dd3 | 2332 | case bfd_mach_sh2e: |
c378eb4e | 2333 | /* doubles on sh2e and sh3e are actually 4 byte. */ |
48db5a3c | 2334 | set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
f92589cb | 2335 | set_gdbarch_double_format (gdbarch, floatformats_ieee_single); |
48db5a3c CV |
2336 | |
2337 | set_gdbarch_register_name (gdbarch, sh_sh2e_register_name); | |
48db5a3c | 2338 | set_gdbarch_register_type (gdbarch, sh_sh3e_register_type); |
2d188dd3 | 2339 | set_gdbarch_fp0_regnum (gdbarch, 25); |
c0409442 | 2340 | set_gdbarch_return_value (gdbarch, sh_return_value_fpu); |
6df2bf50 | 2341 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); |
2d188dd3 | 2342 | break; |
1c0159e0 | 2343 | |
da962468 CV |
2344 | case bfd_mach_sh2a: |
2345 | set_gdbarch_register_name (gdbarch, sh_sh2a_register_name); | |
2346 | set_gdbarch_register_type (gdbarch, sh_sh2a_register_type); | |
2347 | set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno); | |
2348 | ||
2349 | set_gdbarch_fp0_regnum (gdbarch, 25); | |
2350 | set_gdbarch_num_pseudo_regs (gdbarch, 9); | |
2351 | set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read); | |
2352 | set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write); | |
c0409442 | 2353 | set_gdbarch_return_value (gdbarch, sh_return_value_fpu); |
da962468 CV |
2354 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); |
2355 | break; | |
2356 | ||
2357 | case bfd_mach_sh2a_nofpu: | |
2358 | set_gdbarch_register_name (gdbarch, sh_sh2a_nofpu_register_name); | |
2359 | set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno); | |
2360 | ||
2361 | set_gdbarch_num_pseudo_regs (gdbarch, 1); | |
2362 | set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read); | |
2363 | set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write); | |
2364 | break; | |
2365 | ||
cc17453a | 2366 | case bfd_mach_sh_dsp: |
48db5a3c | 2367 | set_gdbarch_register_name (gdbarch, sh_sh_dsp_register_name); |
2f14585c | 2368 | set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno); |
cc17453a | 2369 | break; |
1c0159e0 | 2370 | |
cc17453a | 2371 | case bfd_mach_sh3: |
4e6cbc38 AS |
2372 | case bfd_mach_sh3_nommu: |
2373 | case bfd_mach_sh2a_nofpu_or_sh3_nommu: | |
48db5a3c | 2374 | set_gdbarch_register_name (gdbarch, sh_sh3_register_name); |
cc17453a | 2375 | break; |
1c0159e0 | 2376 | |
cc17453a | 2377 | case bfd_mach_sh3e: |
4e6cbc38 | 2378 | case bfd_mach_sh2a_or_sh3e: |
c378eb4e | 2379 | /* doubles on sh2e and sh3e are actually 4 byte. */ |
48db5a3c | 2380 | set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
f92589cb | 2381 | set_gdbarch_double_format (gdbarch, floatformats_ieee_single); |
48db5a3c CV |
2382 | |
2383 | set_gdbarch_register_name (gdbarch, sh_sh3e_register_name); | |
48db5a3c | 2384 | set_gdbarch_register_type (gdbarch, sh_sh3e_register_type); |
cc17453a | 2385 | set_gdbarch_fp0_regnum (gdbarch, 25); |
c0409442 | 2386 | set_gdbarch_return_value (gdbarch, sh_return_value_fpu); |
6df2bf50 | 2387 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); |
cc17453a | 2388 | break; |
1c0159e0 | 2389 | |
cc17453a | 2390 | case bfd_mach_sh3_dsp: |
48db5a3c | 2391 | set_gdbarch_register_name (gdbarch, sh_sh3_dsp_register_name); |
48db5a3c | 2392 | set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno); |
cc17453a | 2393 | break; |
1c0159e0 | 2394 | |
cc17453a | 2395 | case bfd_mach_sh4: |
474e5826 | 2396 | case bfd_mach_sh4a: |
46e8a76b | 2397 | case bfd_mach_sh2a_or_sh4: |
48db5a3c | 2398 | set_gdbarch_register_name (gdbarch, sh_sh4_register_name); |
48db5a3c | 2399 | set_gdbarch_register_type (gdbarch, sh_sh4_register_type); |
cc17453a | 2400 | set_gdbarch_fp0_regnum (gdbarch, 25); |
da962468 | 2401 | set_gdbarch_num_pseudo_regs (gdbarch, 13); |
d8124050 AC |
2402 | set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read); |
2403 | set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write); | |
c0409442 | 2404 | set_gdbarch_return_value (gdbarch, sh_return_value_fpu); |
6df2bf50 | 2405 | set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu); |
cc17453a | 2406 | break; |
1c0159e0 | 2407 | |
474e5826 CV |
2408 | case bfd_mach_sh4_nofpu: |
2409 | case bfd_mach_sh4a_nofpu: | |
4e6cbc38 AS |
2410 | case bfd_mach_sh4_nommu_nofpu: |
2411 | case bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu: | |
474e5826 CV |
2412 | set_gdbarch_register_name (gdbarch, sh_sh4_nofpu_register_name); |
2413 | break; | |
2414 | ||
2415 | case bfd_mach_sh4al_dsp: | |
2416 | set_gdbarch_register_name (gdbarch, sh_sh4al_dsp_register_name); | |
2417 | set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno); | |
2418 | break; | |
2419 | ||
cc17453a | 2420 | default: |
b58cbbf2 | 2421 | set_gdbarch_register_name (gdbarch, sh_sh_register_name); |
cc17453a | 2422 | break; |
8db62801 | 2423 | } |
cc17453a | 2424 | |
4be87837 DJ |
2425 | /* Hook in ABI-specific overrides, if they have been registered. */ |
2426 | gdbarch_init_osabi (info, gdbarch); | |
d658f924 | 2427 | |
94afd7a6 | 2428 | dwarf2_append_unwinders (gdbarch); |
cb2cf4ce | 2429 | frame_unwind_append_unwinder (gdbarch, &sh_stub_unwind); |
94afd7a6 | 2430 | frame_unwind_append_unwinder (gdbarch, &sh_frame_unwind); |
1c0159e0 | 2431 | |
cc17453a | 2432 | return gdbarch; |
8db62801 EZ |
2433 | } |
2434 | ||
c055b101 | 2435 | static void |
981a3fb3 | 2436 | show_sh_command (const char *args, int from_tty) |
c055b101 CV |
2437 | { |
2438 | help_list (showshcmdlist, "show sh ", all_commands, gdb_stdout); | |
2439 | } | |
2440 | ||
2441 | static void | |
981a3fb3 | 2442 | set_sh_command (const char *args, int from_tty) |
c055b101 CV |
2443 | { |
2444 | printf_unfiltered | |
2445 | ("\"set sh\" must be followed by an appropriate subcommand.\n"); | |
2446 | help_list (setshcmdlist, "set sh ", all_commands, gdb_stdout); | |
2447 | } | |
2448 | ||
c906108c | 2449 | void |
fba45db2 | 2450 | _initialize_sh_tdep (void) |
c906108c | 2451 | { |
f2ea0907 | 2452 | gdbarch_register (bfd_arch_sh, sh_gdbarch_init, NULL); |
c906108c | 2453 | |
c055b101 CV |
2454 | add_prefix_cmd ("sh", no_class, set_sh_command, "SH specific commands.", |
2455 | &setshcmdlist, "set sh ", 0, &setlist); | |
2456 | add_prefix_cmd ("sh", no_class, show_sh_command, "SH specific commands.", | |
2457 | &showshcmdlist, "show sh ", 0, &showlist); | |
2458 | ||
2459 | add_setshow_enum_cmd ("calling-convention", class_vars, sh_cc_enum, | |
2460 | &sh_active_calling_convention, | |
2461 | _("Set calling convention used when calling target " | |
2462 | "functions from GDB."), | |
2463 | _("Show calling convention used when calling target " | |
2464 | "functions from GDB."), | |
2465 | _("gcc - Use GCC calling convention (default).\n" | |
2466 | "renesas - Enforce Renesas calling convention."), | |
2467 | NULL, NULL, | |
2468 | &setshcmdlist, &showshcmdlist); | |
c906108c | 2469 | } |