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2012-02-27 Pedro Alves <palves@redhat.com>
[deliverable/binutils-gdb.git] / gdb / sh-tdep.c
CommitLineData
85a453d5 1/* Target-dependent code for Renesas Super-H, for GDB.
0fd88904 2
0b302171 3 Copyright (C) 1993-2005, 2007-2012 Free Software Foundation, Inc.
c906108c 4
c5aa993b 5 This file is part of GDB.
c906108c 6
c5aa993b
JM		 7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
a9762ec7 9 the Free Software Foundation; either version 3 of the License, or
c5aa993b 10 (at your option) any later version.
c906108c 11
c5aa993b
JM		 12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
c906108c 16
c5aa993b 17 You should have received a copy of the GNU General Public License
a9762ec7 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
c906108c 19
c378eb4e
MS		 20/* Contributed by Steve Chamberlain
21 sac@cygnus.com. */
c906108c
SS		 22
23#include "defs.h"
24#include "frame.h"
1c0159e0
CV		 25#include "frame-base.h"
26#include "frame-unwind.h"
27#include "dwarf2-frame.h"
c906108c 28#include "symtab.h"
c906108c
SS		 29#include "gdbtypes.h"
30#include "gdbcmd.h"
31#include "gdbcore.h"
32#include "value.h"
33#include "dis-asm.h"
73c1f219 34#include "inferior.h"
c906108c 35#include "gdb_string.h"
1c0159e0 36#include "gdb_assert.h"
b4a20239 37#include "arch-utils.h"
fb409745 38#include "floatformat.h"
4e052eda 39#include "regcache.h"
d16aafd8 40#include "doublest.h"
4be87837 41#include "osabi.h"
dda63807 42#include "reggroups.h"
c9ac0a72 43#include "regset.h"
c906108c 44
ab3b8126
JT		 45#include "sh-tdep.h"
46
d658f924 47#include "elf-bfd.h"
1a8629c7
MS		 48#include "solib-svr4.h"
49
55ff77ac 50/* sh flags */
283150cd 51#include "elf/sh.h"
fa8f86ff 52#include "dwarf2.h"
c378eb4e 53/* registers numbers shared with the simulator. */
1c922164 54#include "gdb/sim-sh.h"
283150cd 55
c055b101
CV		 56/* List of "set sh ..." and "show sh ..." commands. */
57static struct cmd_list_element *setshcmdlist = NULL;
58static struct cmd_list_element *showshcmdlist = NULL;
59
60static const char sh_cc_gcc[] = "gcc";
61static const char sh_cc_renesas[] = "renesas";
40478521 62static const char *const sh_cc_enum[] = {
c055b101
CV		 63 sh_cc_gcc,
64 sh_cc_renesas,
65 NULL
66};
67
68static const char *sh_active_calling_convention = sh_cc_gcc;
69
c458d6db 70static void (*sh_show_regs) (struct frame_info *);
cc17453a 71
da962468 72#define SH_NUM_REGS 67
88e04cc1 73
1c0159e0 74struct sh_frame_cache
cc17453a 75{
1c0159e0
CV		 76 /* Base address. */
77 CORE_ADDR base;
78 LONGEST sp_offset;
79 CORE_ADDR pc;
80
c378eb4e 81 /* Flag showing that a frame has been created in the prologue code. */
1c0159e0
CV		 82 int uses_fp;
83
84 /* Saved registers. */
85 CORE_ADDR saved_regs[SH_NUM_REGS];
86 CORE_ADDR saved_sp;
63978407 87};
c906108c 88
c055b101
CV		 89static int
90sh_is_renesas_calling_convention (struct type *func_type)
91{
ca193e27
TS		 92 int val = 0;
93
94 if (func_type)
95 {
96 func_type = check_typedef (func_type);
97
98 if (TYPE_CODE (func_type) == TYPE_CODE_PTR)
99 func_type = check_typedef (TYPE_TARGET_TYPE (func_type));
100
101 if (TYPE_CODE (func_type) == TYPE_CODE_FUNC
102 && TYPE_CALLING_CONVENTION (func_type) == DW_CC_GNU_renesas_sh)
103 val = 1;
104 }
105
106 if (sh_active_calling_convention == sh_cc_renesas)
107 val = 1;
108
109 return val;
c055b101
CV		 110}
111
fa88f677 112static const char *
d93859e2 113sh_sh_register_name (struct gdbarch *gdbarch, int reg_nr)
cc17453a 114{
617daa0e
CV		 115 static char *register_names[] = {
116 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
117 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
118 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
119 "", "",
120 "", "", "", "", "", "", "", "",
121 "", "", "", "", "", "", "", "",
122 "", "",
123 "", "", "", "", "", "", "", "",
124 "", "", "", "", "", "", "", "",
da962468 125 "", "", "", "", "", "", "", "",
cc17453a
EZ		 126 };
127 if (reg_nr < 0)
128 return NULL;
129 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
130 return NULL;
131 return register_names[reg_nr];
132}
133
fa88f677 134static const char *
d93859e2 135sh_sh3_register_name (struct gdbarch *gdbarch, int reg_nr)
cc17453a 136{
617daa0e
CV		 137 static char *register_names[] = {
138 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
139 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
140 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
141 "", "",
142 "", "", "", "", "", "", "", "",
143 "", "", "", "", "", "", "", "",
144 "ssr", "spc",
cc17453a
EZ		 145 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
146 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
da962468 147 "", "", "", "", "", "", "", "",
cc17453a
EZ		 148 };
149 if (reg_nr < 0)
150 return NULL;
151 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
152 return NULL;
153 return register_names[reg_nr];
154}
155
fa88f677 156static const char *
d93859e2 157sh_sh3e_register_name (struct gdbarch *gdbarch, int reg_nr)
cc17453a 158{
617daa0e
CV		 159 static char *register_names[] = {
160 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
161 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
162 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
cc17453a 163 "fpul", "fpscr",
617daa0e
CV		 164 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
165 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
166 "ssr", "spc",
cc17453a
EZ		 167 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
168 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
da962468 169 "", "", "", "", "", "", "", "",
cc17453a
EZ		 170 };
171 if (reg_nr < 0)
172 return NULL;
173 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
174 return NULL;
175 return register_names[reg_nr];
176}
177
2d188dd3 178static const char *
d93859e2 179sh_sh2e_register_name (struct gdbarch *gdbarch, int reg_nr)
2d188dd3 180{
617daa0e
CV		 181 static char *register_names[] = {
182 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
183 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
184 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
2d188dd3 185 "fpul", "fpscr",
617daa0e
CV		 186 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
187 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
188 "", "",
2d188dd3
NC		 189 "", "", "", "", "", "", "", "",
190 "", "", "", "", "", "", "", "",
da962468
CV		 191 "", "", "", "", "", "", "", "",
192 };
193 if (reg_nr < 0)
194 return NULL;
195 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
196 return NULL;
197 return register_names[reg_nr];
198}
199
200static const char *
d93859e2 201sh_sh2a_register_name (struct gdbarch *gdbarch, int reg_nr)
da962468
CV		 202{
203 static char *register_names[] = {
204 /* general registers 0-15 */
205 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
206 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
207 /* 16 - 22 */
208 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
209 /* 23, 24 */
210 "fpul", "fpscr",
211 /* floating point registers 25 - 40 */
212 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
213 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
214 /* 41, 42 */
215 "", "",
216 /* 43 - 62. Banked registers. The bank number used is determined by
c378eb4e 217 the bank register (63). */
da962468
CV		 218 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
219 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
220 "machb", "ivnb", "prb", "gbrb", "maclb",
221 /* 63: register bank number, not a real register but used to
222 communicate the register bank currently get/set. This register
223 is hidden to the user, who manipulates it using the pseudo
224 register called "bank" (67). See below. */
225 "",
226 /* 64 - 66 */
227 "ibcr", "ibnr", "tbr",
228 /* 67: register bank number, the user visible pseudo register. */
229 "bank",
230 /* double precision (pseudo) 68 - 75 */
231 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
232 };
233 if (reg_nr < 0)
234 return NULL;
235 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
236 return NULL;
237 return register_names[reg_nr];
238}
239
240static const char *
d93859e2 241sh_sh2a_nofpu_register_name (struct gdbarch *gdbarch, int reg_nr)
da962468
CV		 242{
243 static char *register_names[] = {
244 /* general registers 0-15 */
245 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
246 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
247 /* 16 - 22 */
248 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
249 /* 23, 24 */
250 "", "",
251 /* floating point registers 25 - 40 */
252 "", "", "", "", "", "", "", "",
253 "", "", "", "", "", "", "", "",
254 /* 41, 42 */
255 "", "",
256 /* 43 - 62. Banked registers. The bank number used is determined by
c378eb4e 257 the bank register (63). */
da962468
CV		 258 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
259 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
260 "machb", "ivnb", "prb", "gbrb", "maclb",
261 /* 63: register bank number, not a real register but used to
262 communicate the register bank currently get/set. This register
263 is hidden to the user, who manipulates it using the pseudo
264 register called "bank" (67). See below. */
265 "",
266 /* 64 - 66 */
267 "ibcr", "ibnr", "tbr",
268 /* 67: register bank number, the user visible pseudo register. */
269 "bank",
270 /* double precision (pseudo) 68 - 75 */
271 "", "", "", "", "", "", "", "",
2d188dd3
NC		 272 };
273 if (reg_nr < 0)
274 return NULL;
275 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
276 return NULL;
277 return register_names[reg_nr];
278}
279
fa88f677 280static const char *
d93859e2 281sh_sh_dsp_register_name (struct gdbarch *gdbarch, int reg_nr)
cc17453a 282{
617daa0e
CV		 283 static char *register_names[] = {
284 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
285 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
286 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
287 "", "dsr",
288 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
289 "y0", "y1", "", "", "", "", "", "mod",
290 "", "",
291 "rs", "re", "", "", "", "", "", "",
292 "", "", "", "", "", "", "", "",
da962468 293 "", "", "", "", "", "", "", "",
cc17453a
EZ		 294 };
295 if (reg_nr < 0)
296 return NULL;
297 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
298 return NULL;
299 return register_names[reg_nr];
300}
301
fa88f677 302static const char *
d93859e2 303sh_sh3_dsp_register_name (struct gdbarch *gdbarch, int reg_nr)
cc17453a 304{
617daa0e
CV		 305 static char *register_names[] = {
306 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
307 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
308 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
309 "", "dsr",
310 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
311 "y0", "y1", "", "", "", "", "", "mod",
312 "ssr", "spc",
313 "rs", "re", "", "", "", "", "", "",
026a72f8
CV		 314 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
315 "", "", "", "", "", "", "", "",
da962468 316 "", "", "", "", "", "", "", "",
cc17453a
EZ		 317 };
318 if (reg_nr < 0)
319 return NULL;
320 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
321 return NULL;
322 return register_names[reg_nr];
323}
324
fa88f677 325static const char *
d93859e2 326sh_sh4_register_name (struct gdbarch *gdbarch, int reg_nr)
53116e27 327{
617daa0e 328 static char *register_names[] = {
a38d2a54 329 /* general registers 0-15 */
617daa0e
CV		 330 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
331 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
a38d2a54 332 /* 16 - 22 */
617daa0e 333 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
a38d2a54 334 /* 23, 24 */
53116e27 335 "fpul", "fpscr",
a38d2a54 336 /* floating point registers 25 - 40 */
617daa0e
CV		 337 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
338 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
a38d2a54 339 /* 41, 42 */
617daa0e 340 "ssr", "spc",
a38d2a54 341 /* bank 0 43 - 50 */
53116e27 342 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
a38d2a54 343 /* bank 1 51 - 58 */
53116e27 344 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
da962468 345 "", "", "", "", "", "", "", "",
c378eb4e 346 /* pseudo bank register. */
da962468 347 "",
a38d2a54 348 /* double precision (pseudo) 59 - 66 */
617daa0e 349 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
a38d2a54 350 /* vectors (pseudo) 67 - 70 */
617daa0e 351 "fv0", "fv4", "fv8", "fv12",
a38d2a54
EZ		 352 /* FIXME: missing XF 71 - 86 */
353 /* FIXME: missing XD 87 - 94 */
53116e27
EZ		 354 };
355 if (reg_nr < 0)
356 return NULL;
357 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
358 return NULL;
359 return register_names[reg_nr];
360}
361
474e5826 362static const char *
d93859e2 363sh_sh4_nofpu_register_name (struct gdbarch *gdbarch, int reg_nr)
474e5826
CV		 364{
365 static char *register_names[] = {
366 /* general registers 0-15 */
367 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
368 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
369 /* 16 - 22 */
370 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
371 /* 23, 24 */
372 "", "",
373 /* floating point registers 25 - 40 -- not for nofpu target */
374 "", "", "", "", "", "", "", "",
375 "", "", "", "", "", "", "", "",
376 /* 41, 42 */
377 "ssr", "spc",
378 /* bank 0 43 - 50 */
379 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
380 /* bank 1 51 - 58 */
381 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
da962468 382 "", "", "", "", "", "", "", "",
c378eb4e 383 /* pseudo bank register. */
da962468 384 "",
474e5826
CV		 385 /* double precision (pseudo) 59 - 66 -- not for nofpu target */
386 "", "", "", "", "", "", "", "",
387 /* vectors (pseudo) 67 - 70 -- not for nofpu target */
388 "", "", "", "",
389 };
390 if (reg_nr < 0)
391 return NULL;
392 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
393 return NULL;
394 return register_names[reg_nr];
395}
396
397static const char *
d93859e2 398sh_sh4al_dsp_register_name (struct gdbarch *gdbarch, int reg_nr)
474e5826
CV		 399{
400 static char *register_names[] = {
401 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
402 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
403 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
404 "", "dsr",
405 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
406 "y0", "y1", "", "", "", "", "", "mod",
407 "ssr", "spc",
408 "rs", "re", "", "", "", "", "", "",
026a72f8
CV		 409 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
410 "", "", "", "", "", "", "", "",
da962468 411 "", "", "", "", "", "", "", "",
474e5826
CV		 412 };
413 if (reg_nr < 0)
414 return NULL;
415 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
416 return NULL;
417 return register_names[reg_nr];
418}
419
3117ed25 420static const unsigned char *
67d57894 421sh_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr)
cc17453a 422{
c378eb4e 423 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes. */
617daa0e
CV		 424 static unsigned char breakpoint[] = { 0xc3, 0xc3 };
425
bac718a6
UW		 426 /* For remote stub targets, trapa #20 is used. */
427 if (strcmp (target_shortname, "remote") == 0)
428 {
429 static unsigned char big_remote_breakpoint[] = { 0xc3, 0x20 };
430 static unsigned char little_remote_breakpoint[] = { 0x20, 0xc3 };
431
67d57894 432 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
bac718a6
UW		 433 {
434 *lenptr = sizeof (big_remote_breakpoint);
435 return big_remote_breakpoint;
436 }
437 else
438 {
439 *lenptr = sizeof (little_remote_breakpoint);
440 return little_remote_breakpoint;
441 }
442 }
443
cc17453a
EZ		 444 *lenptr = sizeof (breakpoint);
445 return breakpoint;
446}
c906108c
SS		 447
448/* Prologue looks like
1c0159e0
CV		 449 mov.l r14,@-r15
450 sts.l pr,@-r15
451 mov.l <regs>,@-r15
452 sub <room_for_loca_vars>,r15
453 mov r15,r14
8db62801 454
c378eb4e 455 Actually it can be more complicated than this but that's it, basically. */
c906108c 456
1c0159e0
CV		 457#define GET_SOURCE_REG(x) (((x) >> 4) & 0xf)
458#define GET_TARGET_REG(x) (((x) >> 8) & 0xf)
459
5f883edd
FF		 460/* JSR @Rm 0100mmmm00001011 */
461#define IS_JSR(x) (((x) & 0xf0ff) == 0x400b)
462
8db62801
EZ		 463/* STS.L PR,@-r15 0100111100100010
464 r15-4-->r15, PR-->(r15) */
c906108c 465#define IS_STS(x) ((x) == 0x4f22)
8db62801 466
03131d99
CV		 467/* STS.L MACL,@-r15 0100111100010010
468 r15-4-->r15, MACL-->(r15) */
469#define IS_MACL_STS(x) ((x) == 0x4f12)
470
8db62801
EZ		 471/* MOV.L Rm,@-r15 00101111mmmm0110
472 r15-4-->r15, Rm-->(R15) */
c906108c 473#define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
8db62801 474
8db62801
EZ		 475/* MOV r15,r14 0110111011110011
476 r15-->r14 */
c906108c 477#define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
8db62801
EZ		 478
479/* ADD #imm,r15 01111111iiiiiiii
480 r15+imm-->r15 */
1c0159e0 481#define IS_ADD_IMM_SP(x) (((x) & 0xff00) == 0x7f00)
8db62801 482
c906108c
SS		 483#define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
484#define IS_SHLL_R3(x) ((x) == 0x4300)
8db62801
EZ		 485
486/* ADD r3,r15 0011111100111100
487 r15+r3-->r15 */
c906108c 488#define IS_ADD_R3SP(x) ((x) == 0x3f3c)
8db62801
EZ		 489
490/* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
8db62801 491 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
8db62801 492 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
f2ea0907 493/* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to
c378eb4e 494 make this entirely clear. */
1c0159e0
CV		 495/* #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) */
496#define IS_FPUSH(x) (((x) & 0xff0f) == 0xff0b)
497
498/* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 4 <= m <= 7 */
499#define IS_MOV_ARG_TO_REG(x) \
500 (((x) & 0xf00f) == 0x6003 && \
501 ((x) & 0x00f0) >= 0x0040 && \
502 ((x) & 0x00f0) <= 0x0070)
503/* MOV.L Rm,@Rn 0010nnnnmmmm0010 n = 14, 4 <= m <= 7 */
504#define IS_MOV_ARG_TO_IND_R14(x) \
505 (((x) & 0xff0f) == 0x2e02 && \
506 ((x) & 0x00f0) >= 0x0040 && \
507 ((x) & 0x00f0) <= 0x0070)
508/* MOV.L Rm,@(disp*4,Rn) 00011110mmmmdddd n = 14, 4 <= m <= 7 */
509#define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \
510 (((x) & 0xff00) == 0x1e00 && \
511 ((x) & 0x00f0) >= 0x0040 && \
512 ((x) & 0x00f0) <= 0x0070)
513
514/* MOV.W @(disp*2,PC),Rn 1001nnnndddddddd */
515#define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000)
516/* MOV.L @(disp*4,PC),Rn 1101nnnndddddddd */
517#define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000)
03131d99
CV		 518/* MOVI20 #imm20,Rn 0000nnnniiii0000 */
519#define IS_MOVI20(x) (((x) & 0xf00f) == 0x0000)
1c0159e0
CV		 520/* SUB Rn,R15 00111111nnnn1000 */
521#define IS_SUB_REG_FROM_SP(x) (((x) & 0xff0f) == 0x3f08)
8db62801 522
1c0159e0 523#define FPSCR_SZ (1 << 20)
cc17453a 524
c378eb4e 525/* The following instructions are used for epilogue testing. */
1c0159e0
CV		 526#define IS_RESTORE_FP(x) ((x) == 0x6ef6)
527#define IS_RTS(x) ((x) == 0x000b)
528#define IS_LDS(x) ((x) == 0x4f26)
03131d99 529#define IS_MACL_LDS(x) ((x) == 0x4f16)
1c0159e0
CV		 530#define IS_MOV_FP_SP(x) ((x) == 0x6fe3)
531#define IS_ADD_REG_TO_FP(x) (((x) & 0xff0f) == 0x3e0c)
532#define IS_ADD_IMM_FP(x) (((x) & 0xff00) == 0x7e00)
cc17453a 533
cc17453a 534static CORE_ADDR
e17a4113
UW		 535sh_analyze_prologue (struct gdbarch *gdbarch,
536 CORE_ADDR pc, CORE_ADDR current_pc,
d2ca4222 537 struct sh_frame_cache *cache, ULONGEST fpscr)
617daa0e 538{
e17a4113 539 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1c0159e0
CV		 540 ULONGEST inst;
541 CORE_ADDR opc;
542 int offset;
543 int sav_offset = 0;
c906108c 544 int r3_val = 0;
1c0159e0 545 int reg, sav_reg = -1;
cc17453a 546
1c0159e0
CV		 547 if (pc >= current_pc)
548 return current_pc;
cc17453a 549
1c0159e0 550 cache->uses_fp = 0;
cc17453a
EZ		 551 for (opc = pc + (2 * 28); pc < opc; pc += 2)
552 {
e17a4113 553 inst = read_memory_unsigned_integer (pc, 2, byte_order);
c378eb4e 554 /* See where the registers will be saved to. */
f2ea0907 555 if (IS_PUSH (inst))
cc17453a 556 {
1c0159e0
CV		 557 cache->saved_regs[GET_SOURCE_REG (inst)] = cache->sp_offset;
558 cache->sp_offset += 4;
cc17453a 559 }
f2ea0907 560 else if (IS_STS (inst))
cc17453a 561 {
1c0159e0
CV		 562 cache->saved_regs[PR_REGNUM] = cache->sp_offset;
563 cache->sp_offset += 4;
cc17453a 564 }
03131d99
CV		 565 else if (IS_MACL_STS (inst))
566 {
567 cache->saved_regs[MACL_REGNUM] = cache->sp_offset;
568 cache->sp_offset += 4;
569 }
f2ea0907 570 else if (IS_MOV_R3 (inst))
cc17453a 571 {
f2ea0907 572 r3_val = ((inst & 0xff) ^ 0x80) - 0x80;
cc17453a 573 }
f2ea0907 574 else if (IS_SHLL_R3 (inst))
cc17453a
EZ		 575 {
576 r3_val <<= 1;
577 }
f2ea0907 578 else if (IS_ADD_R3SP (inst))
cc17453a 579 {
1c0159e0 580 cache->sp_offset += -r3_val;
cc17453a 581 }
f2ea0907 582 else if (IS_ADD_IMM_SP (inst))
cc17453a 583 {
1c0159e0
CV		 584 offset = ((inst & 0xff) ^ 0x80) - 0x80;
585 cache->sp_offset -= offset;
c906108c 586 }
1c0159e0 587 else if (IS_MOVW_PCREL_TO_REG (inst))
617daa0e 588 {
1c0159e0
CV		 589 if (sav_reg < 0)
590 {
591 reg = GET_TARGET_REG (inst);
592 if (reg < 14)
593 {
594 sav_reg = reg;
a2b4a96c 595 offset = (inst & 0xff) << 1;
1c0159e0 596 sav_offset =
e17a4113 597 read_memory_integer ((pc + 4) + offset, 2, byte_order);
1c0159e0
CV		 598 }
599 }
c906108c 600 }
1c0159e0 601 else if (IS_MOVL_PCREL_TO_REG (inst))
617daa0e 602 {
1c0159e0
CV		 603 if (sav_reg < 0)
604 {
a2b4a96c 605 reg = GET_TARGET_REG (inst);
1c0159e0
CV		 606 if (reg < 14)
607 {
608 sav_reg = reg;
a2b4a96c 609 offset = (inst & 0xff) << 2;
1c0159e0 610 sav_offset =
e17a4113
UW		 611 read_memory_integer (((pc & 0xfffffffc) + 4) + offset,
612 4, byte_order);
1c0159e0
CV		 613 }
614 }
c906108c 615 }
03131d99
CV		 616 else if (IS_MOVI20 (inst))
617 {
618 if (sav_reg < 0)
619 {
620 reg = GET_TARGET_REG (inst);
621 if (reg < 14)
622 {
623 sav_reg = reg;
624 sav_offset = GET_SOURCE_REG (inst) << 16;
c378eb4e 625 /* MOVI20 is a 32 bit instruction! */
03131d99 626 pc += 2;
e17a4113
UW		 627 sav_offset
628 |= read_memory_unsigned_integer (pc, 2, byte_order);
03131d99
CV		 629 /* Now sav_offset contains an unsigned 20 bit value.
630 It must still get sign extended. */
631 if (sav_offset & 0x00080000)
632 sav_offset |= 0xfff00000;
633 }
634 }
635 }
1c0159e0 636 else if (IS_SUB_REG_FROM_SP (inst))
617daa0e 637 {
1c0159e0
CV		 638 reg = GET_SOURCE_REG (inst);
639 if (sav_reg > 0 && reg == sav_reg)
640 {
641 sav_reg = -1;
642 }
643 cache->sp_offset += sav_offset;
c906108c 644 }
f2ea0907 645 else if (IS_FPUSH (inst))
c906108c 646 {
d2ca4222 647 if (fpscr & FPSCR_SZ)
c906108c 648 {
1c0159e0 649 cache->sp_offset += 8;
c906108c
SS		 650 }
651 else
652 {
1c0159e0 653 cache->sp_offset += 4;
c906108c
SS		 654 }
655 }
f2ea0907 656 else if (IS_MOV_SP_FP (inst))
617daa0e 657 {
960ccd7d 658 cache->uses_fp = 1;
1c0159e0
CV		 659 /* At this point, only allow argument register moves to other
660 registers or argument register moves to @(X,fp) which are
661 moving the register arguments onto the stack area allocated
662 by a former add somenumber to SP call. Don't allow moving
c378eb4e 663 to an fp indirect address above fp + cache->sp_offset. */
1c0159e0
CV		 664 pc += 2;
665 for (opc = pc + 12; pc < opc; pc += 2)
666 {
e17a4113 667 inst = read_memory_integer (pc, 2, byte_order);
1c0159e0 668 if (IS_MOV_ARG_TO_IND_R14 (inst))
617daa0e 669 {
1c0159e0
CV		 670 reg = GET_SOURCE_REG (inst);
671 if (cache->sp_offset > 0)
617daa0e 672 cache->saved_regs[reg] = cache->sp_offset;
1c0159e0
CV		 673 }
674 else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst))
617daa0e 675 {
1c0159e0
CV		 676 reg = GET_SOURCE_REG (inst);
677 offset = (inst & 0xf) * 4;
678 if (cache->sp_offset > offset)
679 cache->saved_regs[reg] = cache->sp_offset - offset;
680 }
681 else if (IS_MOV_ARG_TO_REG (inst))
617daa0e 682 continue;
1c0159e0
CV		 683 else
684 break;
685 }
686 break;
687 }
5f883edd
FF		 688 else if (IS_JSR (inst))
689 {
690 /* We have found a jsr that has been scheduled into the prologue.
691 If we continue the scan and return a pc someplace after this,
692 then setting a breakpoint on this function will cause it to
693 appear to be called after the function it is calling via the
694 jsr, which will be very confusing. Most likely the next
695 instruction is going to be IS_MOV_SP_FP in the delay slot. If
c378eb4e 696 so, note that before returning the current pc. */
e17a4113 697 inst = read_memory_integer (pc + 2, 2, byte_order);
5f883edd
FF		 698 if (IS_MOV_SP_FP (inst))
699 cache->uses_fp = 1;
700 break;
701 }
c378eb4e
MS		 702#if 0 /* This used to just stop when it found an instruction
703 that was not considered part of the prologue. Now,
704 we just keep going looking for likely
705 instructions. */
c906108c
SS		 706 else
707 break;
2bfa91ee 708#endif
c906108c
SS		 709 }
710
1c0159e0
CV		 711 return pc;
712}
c906108c 713
c378eb4e 714/* Skip any prologue before the guts of a function. */
1c0159e0 715static CORE_ADDR
8a8bc27f 716sh_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
c906108c 717{
8a8bc27f 718 CORE_ADDR post_prologue_pc, func_addr;
1c0159e0
CV		 719 struct sh_frame_cache cache;
720
721 /* See if we can determine the end of the prologue via the symbol table.
722 If so, then return either PC, or the PC after the prologue, whichever
723 is greater. */
8a8bc27f
TS		 724 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
725 {
726 post_prologue_pc = skip_prologue_using_sal (gdbarch, func_addr);
727 if (post_prologue_pc != 0)
728 return max (pc, post_prologue_pc);
729 }
cc17453a 730
8a8bc27f
TS		 731 /* Can't determine prologue from the symbol table, need to examine
732 instructions. */
c906108c 733
1c0159e0 734 cache.sp_offset = -4;
8a8bc27f
TS		 735 post_prologue_pc = sh_analyze_prologue (gdbarch, pc, (CORE_ADDR) -1, &cache, 0);
736 if (cache.uses_fp)
737 pc = post_prologue_pc;
c906108c 738
1c0159e0
CV		 739 return pc;
740}
741
2e952408 742/* The ABI says:
9a5cef92
EZ		 743
744 Aggregate types not bigger than 8 bytes that have the same size and
745 alignment as one of the integer scalar types are returned in the
746 same registers as the integer type they match.
747
748 For example, a 2-byte aligned structure with size 2 bytes has the
749 same size and alignment as a short int, and will be returned in R0.
750 A 4-byte aligned structure with size 8 bytes has the same size and
751 alignment as a long long int, and will be returned in R0 and R1.
752
753 When an aggregate type is returned in R0 and R1, R0 contains the
754 first four bytes of the aggregate, and R1 contains the
c378eb4e 755 remainder. If the size of the aggregate type is not a multiple of 4
9a5cef92 756 bytes, the aggregate is tail-padded up to a multiple of 4
c378eb4e 757 bytes. The value of the padding is undefined. For little-endian
9a5cef92
EZ		 758 targets the padding will appear at the most significant end of the
759 last element, for big-endian targets the padding appears at the
760 least significant end of the last element.
761
c378eb4e 762 All other aggregate types are returned by address. The caller
9a5cef92 763 function passes the address of an area large enough to hold the
c378eb4e 764 aggregate value in R2. The called function stores the result in
7fe958be 765 this location.
9a5cef92
EZ		 766
767 To reiterate, structs smaller than 8 bytes could also be returned
768 in memory, if they don't pass the "same size and alignment as an
769 integer type" rule.
770
771 For example, in
772
773 struct s { char c[3]; } wibble;
774 struct s foo(void) { return wibble; }
775
776 the return value from foo() will be in memory, not
777 in R0, because there is no 3-byte integer type.
778
7fe958be
EZ		 779 Similarly, in
780
781 struct s { char c[2]; } wibble;
782 struct s foo(void) { return wibble; }
783
784 because a struct containing two chars has alignment 1, that matches
785 type char, but size 2, that matches type short. There's no integer
786 type that has alignment 1 and size 2, so the struct is returned in
c378eb4e 787 memory. */
9a5cef92 788
1c0159e0 789static int
c055b101 790sh_use_struct_convention (int renesas_abi, struct type *type)
1c0159e0
CV		 791{
792 int len = TYPE_LENGTH (type);
793 int nelem = TYPE_NFIELDS (type);
3f997a97 794
c055b101
CV		 795 /* The Renesas ABI returns aggregate types always on stack. */
796 if (renesas_abi && (TYPE_CODE (type) == TYPE_CODE_STRUCT
797 || TYPE_CODE (type) == TYPE_CODE_UNION))
798 return 1;
799
3f997a97
CV		 800 /* Non-power of 2 length types and types bigger than 8 bytes (which don't
801 fit in two registers anyway) use struct convention. */
802 if (len != 1 && len != 2 && len != 4 && len != 8)
803 return 1;
804
805 /* Scalar types and aggregate types with exactly one field are aligned
806 by definition. They are returned in registers. */
807 if (nelem <= 1)
808 return 0;
809
810 /* If the first field in the aggregate has the same length as the entire
811 aggregate type, the type is returned in registers. */
812 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == len)
813 return 0;
814
815 /* If the size of the aggregate is 8 bytes and the first field is
816 of size 4 bytes its alignment is equal to long long's alignment,
817 so it's returned in registers. */
818 if (len == 8 && TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == 4)
819 return 0;
820
821 /* Otherwise use struct convention. */
822 return 1;
283150cd
EZ		 823}
824
c055b101
CV		 825static int
826sh_use_struct_convention_nofpu (int renesas_abi, struct type *type)
827{
828 /* The Renesas ABI returns long longs/doubles etc. always on stack. */
829 if (renesas_abi && TYPE_NFIELDS (type) == 0 && TYPE_LENGTH (type) >= 8)
830 return 1;
831 return sh_use_struct_convention (renesas_abi, type);
832}
833
19f59343
MS		 834static CORE_ADDR
835sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
836{
837 return sp & ~3;
838}
839
55ff77ac 840/* Function: push_dummy_call (formerly push_arguments)
c906108c
SS		 841 Setup the function arguments for calling a function in the inferior.
842
85a453d5 843 On the Renesas SH architecture, there are four registers (R4 to R7)
c906108c
SS		 844 which are dedicated for passing function arguments. Up to the first
845 four arguments (depending on size) may go into these registers.
846 The rest go on the stack.
847
6df2bf50
MS		 848 MVS: Except on SH variants that have floating point registers.
849 In that case, float and double arguments are passed in the same
850 manner, but using FP registers instead of GP registers.
851
c906108c
SS		 852 Arguments that are smaller than 4 bytes will still take up a whole
853 register or a whole 32-bit word on the stack, and will be
854 right-justified in the register or the stack word. This includes
855 chars, shorts, and small aggregate types.
856
857 Arguments that are larger than 4 bytes may be split between two or
858 more registers. If there are not enough registers free, an argument
859 may be passed partly in a register (or registers), and partly on the
c378eb4e 860 stack. This includes doubles, long longs, and larger aggregates.
c906108c
SS		 861 As far as I know, there is no upper limit to the size of aggregates
862 that will be passed in this way; in other words, the convention of
863 passing a pointer to a large aggregate instead of a copy is not used.
864
6df2bf50 865 MVS: The above appears to be true for the SH variants that do not
55ff77ac 866 have an FPU, however those that have an FPU appear to copy the
6df2bf50
MS		 867 aggregate argument onto the stack (and not place it in registers)
868 if it is larger than 16 bytes (four GP registers).
869
c906108c
SS		 870 An exceptional case exists for struct arguments (and possibly other
871 aggregates such as arrays) if the size is larger than 4 bytes but
872 not a multiple of 4 bytes. In this case the argument is never split
873 between the registers and the stack, but instead is copied in its
874 entirety onto the stack, AND also copied into as many registers as
875 there is room for. In other words, space in registers permitting,
876 two copies of the same argument are passed in. As far as I can tell,
877 only the one on the stack is used, although that may be a function
878 of the level of compiler optimization. I suspect this is a compiler
879 bug. Arguments of these odd sizes are left-justified within the
880 word (as opposed to arguments smaller than 4 bytes, which are
881 right-justified).
c5aa993b 882
c906108c
SS		 883 If the function is to return an aggregate type such as a struct, it
884 is either returned in the normal return value register R0 (if its
885 size is no greater than one byte), or else the caller must allocate
886 space into which the callee will copy the return value (if the size
887 is greater than one byte). In this case, a pointer to the return
888 value location is passed into the callee in register R2, which does
889 not displace any of the other arguments passed in via registers R4
c378eb4e 890 to R7. */
c906108c 891
c378eb4e 892/* Helper function to justify value in register according to endianess. */
e5e33cd9 893static char *
d93859e2 894sh_justify_value_in_reg (struct gdbarch *gdbarch, struct value *val, int len)
e5e33cd9
CV		 895{
896 static char valbuf[4];
897
617daa0e 898 memset (valbuf, 0, sizeof (valbuf));
e5e33cd9
CV		 899 if (len < 4)
900 {
c378eb4e 901 /* value gets right-justified in the register or stack word. */
d93859e2 902 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
0fd88904 903 memcpy (valbuf + (4 - len), (char *) value_contents (val), len);
e5e33cd9 904 else
0fd88904 905 memcpy (valbuf, (char *) value_contents (val), len);
e5e33cd9
CV		 906 return valbuf;
907 }
0fd88904 908 return (char *) value_contents (val);
617daa0e 909}
e5e33cd9 910
c378eb4e 911/* Helper function to eval number of bytes to allocate on stack. */
e5e33cd9
CV		 912static CORE_ADDR
913sh_stack_allocsize (int nargs, struct value **args)
914{
915 int stack_alloc = 0;
916 while (nargs-- > 0)
4991999e 917 stack_alloc += ((TYPE_LENGTH (value_type (args[nargs])) + 3) & ~3);
e5e33cd9
CV		 918 return stack_alloc;
919}
920
921/* Helper functions for getting the float arguments right. Registers usage
922 depends on the ABI and the endianess. The comments should enlighten how
c378eb4e 923 it's intended to work. */
e5e33cd9 924
c378eb4e 925/* This array stores which of the float arg registers are already in use. */
e5e33cd9
CV		 926static int flt_argreg_array[FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM + 1];
927
c378eb4e 928/* This function just resets the above array to "no reg used so far". */
e5e33cd9
CV		 929static void
930sh_init_flt_argreg (void)
931{
932 memset (flt_argreg_array, 0, sizeof flt_argreg_array);
933}
934
935/* This function returns the next register to use for float arg passing.
936 It returns either a valid value between FLOAT_ARG0_REGNUM and
937 FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns
938 FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available.
939
940 Note that register number 0 in flt_argreg_array corresponds with the
941 real float register fr4. In contrast to FLOAT_ARG0_REGNUM (value is
942 29) the parity of the register number is preserved, which is important
c378eb4e 943 for the double register passing test (see the "argreg & 1" test below). */
e5e33cd9 944static int
c055b101 945sh_next_flt_argreg (struct gdbarch *gdbarch, int len, struct type *func_type)
e5e33cd9
CV		 946{
947 int argreg;
948
c378eb4e 949 /* First search for the next free register. */
617daa0e
CV		 950 for (argreg = 0; argreg <= FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM;
951 ++argreg)
e5e33cd9
CV		 952 if (!flt_argreg_array[argreg])
953 break;
954
c378eb4e 955 /* No register left? */
e5e33cd9
CV		 956 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
957 return FLOAT_ARGLAST_REGNUM + 1;
958
959 if (len == 8)
960 {
c378eb4e 961 /* Doubles are always starting in a even register number. */
e5e33cd9 962 if (argreg & 1)
617daa0e 963 {
c055b101
CV		 964 /* In gcc ABI, the skipped register is lost for further argument
965 passing now. Not so in Renesas ABI. */
966 if (!sh_is_renesas_calling_convention (func_type))
967 flt_argreg_array[argreg] = 1;
e5e33cd9
CV		 968
969 ++argreg;
970
c378eb4e 971 /* No register left? */
e5e33cd9
CV		 972 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
973 return FLOAT_ARGLAST_REGNUM + 1;
974 }
c378eb4e 975 /* Also mark the next register as used. */
e5e33cd9
CV		 976 flt_argreg_array[argreg + 1] = 1;
977 }
c055b101
CV		 978 else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE
979 && !sh_is_renesas_calling_convention (func_type))
e5e33cd9 980 {
c378eb4e 981 /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */
e5e33cd9
CV		 982 if (!flt_argreg_array[argreg + 1])
983 ++argreg;
984 }
985 flt_argreg_array[argreg] = 1;
986 return FLOAT_ARG0_REGNUM + argreg;
987}
988
afce3d2a
CV		 989/* Helper function which figures out, if a type is treated like a float type.
990
2e952408 991 The FPU ABIs have a special way how to treat types as float types.
afce3d2a
CV		 992 Structures with exactly one member, which is of type float or double, are
993 treated exactly as the base types float or double:
994
995 struct sf {
996 float f;
997 };
998
999 struct sd {
1000 double d;
1001 };
1002
1003 are handled the same way as just
1004
1005 float f;
1006
1007 double d;
1008
1009 As a result, arguments of these struct types are pushed into floating point
1010 registers exactly as floats or doubles, using the same decision algorithm.
1011
1012 The same is valid if these types are used as function return types. The
1013 above structs are returned in fr0 resp. fr0,fr1 instead of in r0, r0,r1
1014 or even using struct convention as it is for other structs. */
1015
1016static int
1017sh_treat_as_flt_p (struct type *type)
1018{
1019 int len = TYPE_LENGTH (type);
1020
1021 /* Ordinary float types are obviously treated as float. */
1022 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1023 return 1;
1024 /* Otherwise non-struct types are not treated as float. */
1025 if (TYPE_CODE (type) != TYPE_CODE_STRUCT)
1026 return 0;
1027 /* Otherwise structs with more than one memeber are not treated as float. */
1028 if (TYPE_NFIELDS (type) != 1)
1029 return 0;
1030 /* Otherwise if the type of that member is float, the whole type is
1031 treated as float. */
1032 if (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) == TYPE_CODE_FLT)
1033 return 1;
1034 /* Otherwise it's not treated as float. */
1035 return 0;
1036}
1037
cc17453a 1038static CORE_ADDR
617daa0e 1039sh_push_dummy_call_fpu (struct gdbarch *gdbarch,
7d9b040b 1040 struct value *function,
617daa0e 1041 struct regcache *regcache,
6df2bf50 1042 CORE_ADDR bp_addr, int nargs,
617daa0e 1043 struct value **args,
6df2bf50
MS		 1044 CORE_ADDR sp, int struct_return,
1045 CORE_ADDR struct_addr)
1046{
e17a4113 1047 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
e5e33cd9
CV		 1048 int stack_offset = 0;
1049 int argreg = ARG0_REGNUM;
8748518b 1050 int flt_argreg = 0;
6df2bf50 1051 int argnum;
c055b101 1052 struct type *func_type = value_type (function);
6df2bf50
MS		 1053 struct type *type;
1054 CORE_ADDR regval;
1055 char *val;
8748518b 1056 int len, reg_size = 0;
afce3d2a
CV		 1057 int pass_on_stack = 0;
1058 int treat_as_flt;
c055b101
CV		 1059 int last_reg_arg = INT_MAX;
1060
1061 /* The Renesas ABI expects all varargs arguments, plus the last
1062 non-vararg argument to be on the stack, no matter how many
1063 registers have been used so far. */
1064 if (sh_is_renesas_calling_convention (func_type)
876cecd0 1065 && TYPE_VARARGS (func_type))
c055b101 1066 last_reg_arg = TYPE_NFIELDS (func_type) - 2;
6df2bf50 1067
c378eb4e 1068 /* First force sp to a 4-byte alignment. */
6df2bf50
MS		 1069 sp = sh_frame_align (gdbarch, sp);
1070
c378eb4e 1071 /* Make room on stack for args. */
e5e33cd9
CV		 1072 sp -= sh_stack_allocsize (nargs, args);
1073
c378eb4e 1074 /* Initialize float argument mechanism. */
e5e33cd9 1075 sh_init_flt_argreg ();
6df2bf50
MS		 1076
1077 /* Now load as many as possible of the first arguments into
1078 registers, and push the rest onto the stack. There are 16 bytes
1079 in four registers available. Loop thru args from first to last. */
e5e33cd9 1080 for (argnum = 0; argnum < nargs; argnum++)
6df2bf50 1081 {
4991999e 1082 type = value_type (args[argnum]);
6df2bf50 1083 len = TYPE_LENGTH (type);
d93859e2 1084 val = sh_justify_value_in_reg (gdbarch, args[argnum], len);
e5e33cd9
CV		 1085
1086 /* Some decisions have to be made how various types are handled.
c378eb4e 1087 This also differs in different ABIs. */
e5e33cd9 1088 pass_on_stack = 0;
e5e33cd9 1089
c378eb4e 1090 /* Find out the next register to use for a floating point value. */
afce3d2a
CV		 1091 treat_as_flt = sh_treat_as_flt_p (type);
1092 if (treat_as_flt)
c055b101
CV		 1093 flt_argreg = sh_next_flt_argreg (gdbarch, len, func_type);
1094 /* In Renesas ABI, long longs and aggregate types are always passed
1095 on stack. */
1096 else if (sh_is_renesas_calling_convention (func_type)
1097 && ((TYPE_CODE (type) == TYPE_CODE_INT && len == 8)
1098 || TYPE_CODE (type) == TYPE_CODE_STRUCT
1099 || TYPE_CODE (type) == TYPE_CODE_UNION))
1100 pass_on_stack = 1;
afce3d2a
CV		 1101 /* In contrast to non-FPU CPUs, arguments are never split between
1102 registers and stack. If an argument doesn't fit in the remaining
1103 registers it's always pushed entirely on the stack. */
1104 else if (len > ((ARGLAST_REGNUM - argreg + 1) * 4))
1105 pass_on_stack = 1;
48db5a3c 1106
6df2bf50
MS		 1107 while (len > 0)
1108 {
afce3d2a
CV		 1109 if ((treat_as_flt && flt_argreg > FLOAT_ARGLAST_REGNUM)
1110 || (!treat_as_flt && (argreg > ARGLAST_REGNUM
c055b101
CV		 1111 || pass_on_stack))
1112 || argnum > last_reg_arg)
617daa0e 1113 {
c378eb4e 1114 /* The data goes entirely on the stack, 4-byte aligned. */
e5e33cd9
CV		 1115 reg_size = (len + 3) & ~3;
1116 write_memory (sp + stack_offset, val, reg_size);
1117 stack_offset += reg_size;
6df2bf50 1118 }
afce3d2a 1119 else if (treat_as_flt && flt_argreg <= FLOAT_ARGLAST_REGNUM)
6df2bf50 1120 {
e5e33cd9
CV		 1121 /* Argument goes in a float argument register. */
1122 reg_size = register_size (gdbarch, flt_argreg);
e17a4113 1123 regval = extract_unsigned_integer (val, reg_size, byte_order);
2e952408
CV		 1124 /* In little endian mode, float types taking two registers
1125 (doubles on sh4, long doubles on sh2e, sh3e and sh4) must
1126 be stored swapped in the argument registers. The below
1127 code first writes the first 32 bits in the next but one
1128 register, increments the val and len values accordingly
1129 and then proceeds as normal by writing the second 32 bits
c378eb4e 1130 into the next register. */
b47193f7 1131 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE
2e952408
CV		 1132 && TYPE_LENGTH (type) == 2 * reg_size)
1133 {
1134 regcache_cooked_write_unsigned (regcache, flt_argreg + 1,
1135 regval);
1136 val += reg_size;
1137 len -= reg_size;
c378eb4e
MS		 1138 regval = extract_unsigned_integer (val, reg_size,
1139 byte_order);
2e952408 1140 }
6df2bf50
MS		 1141 regcache_cooked_write_unsigned (regcache, flt_argreg++, regval);
1142 }
afce3d2a 1143 else if (!treat_as_flt && argreg <= ARGLAST_REGNUM)
e5e33cd9 1144 {
6df2bf50 1145 /* there's room in a register */
e5e33cd9 1146 reg_size = register_size (gdbarch, argreg);
e17a4113 1147 regval = extract_unsigned_integer (val, reg_size, byte_order);
6df2bf50
MS		 1148 regcache_cooked_write_unsigned (regcache, argreg++, regval);
1149 }
c378eb4e
MS		 1150 /* Store the value one register at a time or in one step on
1151 stack. */
e5e33cd9
CV		 1152 len -= reg_size;
1153 val += reg_size;
6df2bf50
MS		 1154 }
1155 }
1156
c055b101
CV		 1157 if (struct_return)
1158 {
1159 if (sh_is_renesas_calling_convention (func_type))
1160 /* If the function uses the Renesas ABI, subtract another 4 bytes from
1161 the stack and store the struct return address there. */
e17a4113 1162 write_memory_unsigned_integer (sp -= 4, 4, byte_order, struct_addr);
c055b101
CV		 1163 else
1164 /* Using the gcc ABI, the "struct return pointer" pseudo-argument has
1165 its own dedicated register. */
1166 regcache_cooked_write_unsigned (regcache,
1167 STRUCT_RETURN_REGNUM, struct_addr);
1168 }
1169
c378eb4e 1170 /* Store return address. */
55ff77ac 1171 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
6df2bf50
MS		 1172
1173 /* Update stack pointer. */
3e8c568d 1174 regcache_cooked_write_unsigned (regcache,
b47193f7 1175 gdbarch_sp_regnum (gdbarch), sp);
6df2bf50
MS		 1176
1177 return sp;
1178}
1179
1180static CORE_ADDR
617daa0e 1181sh_push_dummy_call_nofpu (struct gdbarch *gdbarch,
7d9b040b 1182 struct value *function,
617daa0e
CV		 1183 struct regcache *regcache,
1184 CORE_ADDR bp_addr,
1185 int nargs, struct value **args,
1186 CORE_ADDR sp, int struct_return,
6df2bf50 1187 CORE_ADDR struct_addr)
c906108c 1188{
e17a4113 1189 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
e5e33cd9
CV		 1190 int stack_offset = 0;
1191 int argreg = ARG0_REGNUM;
c906108c 1192 int argnum;
c055b101 1193 struct type *func_type = value_type (function);
c906108c
SS		 1194 struct type *type;
1195 CORE_ADDR regval;
1196 char *val;
c055b101
CV		 1197 int len, reg_size = 0;
1198 int pass_on_stack = 0;
1199 int last_reg_arg = INT_MAX;
1200
1201 /* The Renesas ABI expects all varargs arguments, plus the last
1202 non-vararg argument to be on the stack, no matter how many
1203 registers have been used so far. */
1204 if (sh_is_renesas_calling_convention (func_type)
876cecd0 1205 && TYPE_VARARGS (func_type))
c055b101 1206 last_reg_arg = TYPE_NFIELDS (func_type) - 2;
c906108c 1207
c378eb4e 1208 /* First force sp to a 4-byte alignment. */
19f59343 1209 sp = sh_frame_align (gdbarch, sp);
c906108c 1210
c378eb4e 1211 /* Make room on stack for args. */
e5e33cd9 1212 sp -= sh_stack_allocsize (nargs, args);
c906108c 1213
c906108c
SS		 1214 /* Now load as many as possible of the first arguments into
1215 registers, and push the rest onto the stack. There are 16 bytes
1216 in four registers available. Loop thru args from first to last. */
e5e33cd9 1217 for (argnum = 0; argnum < nargs; argnum++)
617daa0e 1218 {
4991999e 1219 type = value_type (args[argnum]);
c5aa993b 1220 len = TYPE_LENGTH (type);
d93859e2 1221 val = sh_justify_value_in_reg (gdbarch, args[argnum], len);
c906108c 1222
c055b101 1223 /* Some decisions have to be made how various types are handled.
c378eb4e 1224 This also differs in different ABIs. */
c055b101
CV		 1225 pass_on_stack = 0;
1226 /* Renesas ABI pushes doubles and long longs entirely on stack.
1227 Same goes for aggregate types. */
1228 if (sh_is_renesas_calling_convention (func_type)
1229 && ((TYPE_CODE (type) == TYPE_CODE_INT && len >= 8)
1230 || (TYPE_CODE (type) == TYPE_CODE_FLT && len >= 8)
1231 || TYPE_CODE (type) == TYPE_CODE_STRUCT
1232 || TYPE_CODE (type) == TYPE_CODE_UNION))
1233 pass_on_stack = 1;
c906108c
SS		 1234 while (len > 0)
1235 {
c055b101
CV		 1236 if (argreg > ARGLAST_REGNUM || pass_on_stack
1237 || argnum > last_reg_arg)
617daa0e 1238 {
e5e33cd9 1239 /* The remainder of the data goes entirely on the stack,
c378eb4e 1240 4-byte aligned. */
e5e33cd9
CV		 1241 reg_size = (len + 3) & ~3;
1242 write_memory (sp + stack_offset, val, reg_size);
617daa0e 1243 stack_offset += reg_size;
c906108c 1244 }
e5e33cd9 1245 else if (argreg <= ARGLAST_REGNUM)
617daa0e 1246 {
c378eb4e 1247 /* There's room in a register. */
e5e33cd9 1248 reg_size = register_size (gdbarch, argreg);
e17a4113 1249 regval = extract_unsigned_integer (val, reg_size, byte_order);
48db5a3c 1250 regcache_cooked_write_unsigned (regcache, argreg++, regval);
c906108c 1251 }
e5e33cd9
CV		 1252 /* Store the value reg_size bytes at a time. This means that things
1253 larger than reg_size bytes may go partly in registers and partly
c906108c 1254 on the stack. */
e5e33cd9
CV		 1255 len -= reg_size;
1256 val += reg_size;
c906108c
SS		 1257 }
1258 }
48db5a3c 1259
c055b101
CV		 1260 if (struct_return)
1261 {
1262 if (sh_is_renesas_calling_convention (func_type))
1263 /* If the function uses the Renesas ABI, subtract another 4 bytes from
1264 the stack and store the struct return address there. */
e17a4113 1265 write_memory_unsigned_integer (sp -= 4, 4, byte_order, struct_addr);
c055b101
CV		 1266 else
1267 /* Using the gcc ABI, the "struct return pointer" pseudo-argument has
1268 its own dedicated register. */
1269 regcache_cooked_write_unsigned (regcache,
1270 STRUCT_RETURN_REGNUM, struct_addr);
1271 }
1272
c378eb4e 1273 /* Store return address. */
55ff77ac 1274 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
48db5a3c
CV		 1275
1276 /* Update stack pointer. */
3e8c568d 1277 regcache_cooked_write_unsigned (regcache,
b47193f7 1278 gdbarch_sp_regnum (gdbarch), sp);
48db5a3c 1279
c906108c
SS		 1280 return sp;
1281}
1282
cc17453a
EZ		 1283/* Find a function's return value in the appropriate registers (in
1284 regbuf), and copy it into valbuf. Extract from an array REGBUF
1285 containing the (raw) register state a function return value of type
1286 TYPE, and copy that, in virtual format, into VALBUF. */
1287static void
3ffc5b9b
CV		 1288sh_extract_return_value_nofpu (struct type *type, struct regcache *regcache,
1289 void *valbuf)
c906108c 1290{
e17a4113
UW		 1291 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1292 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
cc17453a 1293 int len = TYPE_LENGTH (type);
3116c80a
EZ		 1294 int return_register = R0_REGNUM;
1295 int offset;
617daa0e 1296
cc17453a 1297 if (len <= 4)
3116c80a 1298 {
48db5a3c
CV		 1299 ULONGEST c;
1300
1301 regcache_cooked_read_unsigned (regcache, R0_REGNUM, &c);
e17a4113 1302 store_unsigned_integer (valbuf, len, byte_order, c);
3116c80a 1303 }
48db5a3c 1304 else if (len == 8)
3116c80a 1305 {
48db5a3c
CV		 1306 int i, regnum = R0_REGNUM;
1307 for (i = 0; i < len; i += 4)
617daa0e 1308 regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
3116c80a
EZ		 1309 }
1310 else
8a3fe4f8 1311 error (_("bad size for return value"));
3116c80a
EZ		 1312}
1313
1314static void
3ffc5b9b
CV		 1315sh_extract_return_value_fpu (struct type *type, struct regcache *regcache,
1316 void *valbuf)
3116c80a 1317{
d93859e2 1318 struct gdbarch *gdbarch = get_regcache_arch (regcache);
afce3d2a 1319 if (sh_treat_as_flt_p (type))
3116c80a 1320 {
48db5a3c 1321 int len = TYPE_LENGTH (type);
d93859e2 1322 int i, regnum = gdbarch_fp0_regnum (gdbarch);
48db5a3c 1323 for (i = 0; i < len; i += 4)
d93859e2 1324 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
c378eb4e
MS		 1325 regcache_raw_read (regcache, regnum++,
1326 (char *) valbuf + len - 4 - i);
2e952408
CV		 1327 else
1328 regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
3116c80a 1329 }
cc17453a 1330 else
3ffc5b9b 1331 sh_extract_return_value_nofpu (type, regcache, valbuf);
cc17453a 1332}
c906108c 1333
cc17453a
EZ		 1334/* Write into appropriate registers a function return value
1335 of type TYPE, given in virtual format.
1336 If the architecture is sh4 or sh3e, store a function's return value
1337 in the R0 general register or in the FP0 floating point register,
c378eb4e
MS		 1338 depending on the type of the return value. In all the other cases
1339 the result is stored in r0, left-justified. */
cc17453a 1340static void
3ffc5b9b
CV		 1341sh_store_return_value_nofpu (struct type *type, struct regcache *regcache,
1342 const void *valbuf)
cc17453a 1343{
e17a4113
UW		 1344 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1345 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
48db5a3c
CV		 1346 ULONGEST val;
1347 int len = TYPE_LENGTH (type);
d19b71be 1348
48db5a3c 1349 if (len <= 4)
d19b71be 1350 {
e17a4113 1351 val = extract_unsigned_integer (valbuf, len, byte_order);
48db5a3c 1352 regcache_cooked_write_unsigned (regcache, R0_REGNUM, val);
d19b71be
MS		 1353 }
1354 else
48db5a3c
CV		 1355 {
1356 int i, regnum = R0_REGNUM;
1357 for (i = 0; i < len; i += 4)
617daa0e 1358 regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
48db5a3c 1359 }
cc17453a 1360}
c906108c 1361
cc17453a 1362static void
3ffc5b9b
CV		 1363sh_store_return_value_fpu (struct type *type, struct regcache *regcache,
1364 const void *valbuf)
cc17453a 1365{
d93859e2 1366 struct gdbarch *gdbarch = get_regcache_arch (regcache);
afce3d2a 1367 if (sh_treat_as_flt_p (type))
48db5a3c
CV		 1368 {
1369 int len = TYPE_LENGTH (type);
d93859e2 1370 int i, regnum = gdbarch_fp0_regnum (gdbarch);
48db5a3c 1371 for (i = 0; i < len; i += 4)
d93859e2 1372 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
c8a3b559
CV		 1373 regcache_raw_write (regcache, regnum++,
1374 (char *) valbuf + len - 4 - i);
1375 else
1376 regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
48db5a3c 1377 }
cc17453a 1378 else
3ffc5b9b 1379 sh_store_return_value_nofpu (type, regcache, valbuf);
c906108c
SS		 1380}
1381
c0409442 1382static enum return_value_convention
c055b101
CV		 1383sh_return_value_nofpu (struct gdbarch *gdbarch, struct type *func_type,
1384 struct type *type, struct regcache *regcache,
18cf8b5b 1385 gdb_byte *readbuf, const gdb_byte *writebuf)
c0409442 1386{
c055b101
CV		 1387 if (sh_use_struct_convention_nofpu (
1388 sh_is_renesas_calling_convention (func_type), type))
c0409442
CV		 1389 return RETURN_VALUE_STRUCT_CONVENTION;
1390 if (writebuf)
3ffc5b9b 1391 sh_store_return_value_nofpu (type, regcache, writebuf);
c0409442 1392 else if (readbuf)
3ffc5b9b 1393 sh_extract_return_value_nofpu (type, regcache, readbuf);
c0409442
CV		 1394 return RETURN_VALUE_REGISTER_CONVENTION;
1395}
1396
1397static enum return_value_convention
c055b101
CV		 1398sh_return_value_fpu (struct gdbarch *gdbarch, struct type *func_type,
1399 struct type *type, struct regcache *regcache,
18cf8b5b 1400 gdb_byte *readbuf, const gdb_byte *writebuf)
c0409442 1401{
c055b101
CV		 1402 if (sh_use_struct_convention (
1403 sh_is_renesas_calling_convention (func_type), type))
c0409442
CV		 1404 return RETURN_VALUE_STRUCT_CONVENTION;
1405 if (writebuf)
3ffc5b9b 1406 sh_store_return_value_fpu (type, regcache, writebuf);
c0409442 1407 else if (readbuf)
3ffc5b9b 1408 sh_extract_return_value_fpu (type, regcache, readbuf);
c0409442
CV		 1409 return RETURN_VALUE_REGISTER_CONVENTION;
1410}
1411
c378eb4e 1412/* Print the registers in a form similar to the E7000. */
c906108c
SS		 1413
1414static void
c458d6db 1415sh_generic_show_regs (struct frame_info *frame)
c906108c 1416{
c458d6db
UW		 1417 printf_filtered
1418 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 1419 phex (get_frame_register_unsigned (frame,
1420 gdbarch_pc_regnum
1421 (get_frame_arch (frame))), 4),
c458d6db
UW		 1422 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1423 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1424 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
cc17453a 1425
c458d6db
UW		 1426 printf_filtered
1427 (" GBR %08lx VBR %08lx MACL %08lx\n",
1428 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1429 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1430 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
cc17453a 1431
617daa0e 1432 printf_filtered
a6b0a3f3 1433 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
c458d6db
UW		 1434 (long) get_frame_register_unsigned (frame, 0),
1435 (long) get_frame_register_unsigned (frame, 1),
1436 (long) get_frame_register_unsigned (frame, 2),
1437 (long) get_frame_register_unsigned (frame, 3),
1438 (long) get_frame_register_unsigned (frame, 4),
1439 (long) get_frame_register_unsigned (frame, 5),
1440 (long) get_frame_register_unsigned (frame, 6),
1441 (long) get_frame_register_unsigned (frame, 7));
1442 printf_filtered
1443 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1444 (long) get_frame_register_unsigned (frame, 8),
1445 (long) get_frame_register_unsigned (frame, 9),
1446 (long) get_frame_register_unsigned (frame, 10),
1447 (long) get_frame_register_unsigned (frame, 11),
1448 (long) get_frame_register_unsigned (frame, 12),
1449 (long) get_frame_register_unsigned (frame, 13),
1450 (long) get_frame_register_unsigned (frame, 14),
1451 (long) get_frame_register_unsigned (frame, 15));
cc17453a 1452}
c906108c 1453
cc17453a 1454static void
c458d6db 1455sh3_show_regs (struct frame_info *frame)
cc17453a 1456{
c458d6db
UW		 1457 printf_filtered
1458 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 1459 phex (get_frame_register_unsigned (frame,
1460 gdbarch_pc_regnum
1461 (get_frame_arch (frame))), 4),
c458d6db
UW		 1462 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1463 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1464 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1465
1466 printf_filtered
1467 (" GBR %08lx VBR %08lx MACL %08lx\n",
1468 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1469 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1470 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1471 printf_filtered
1472 (" SSR %08lx SPC %08lx\n",
1473 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1474 (long) get_frame_register_unsigned (frame, SPC_REGNUM));
c906108c 1475
617daa0e 1476 printf_filtered
a6b0a3f3 1477 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
c458d6db
UW		 1478 (long) get_frame_register_unsigned (frame, 0),
1479 (long) get_frame_register_unsigned (frame, 1),
1480 (long) get_frame_register_unsigned (frame, 2),
1481 (long) get_frame_register_unsigned (frame, 3),
1482 (long) get_frame_register_unsigned (frame, 4),
1483 (long) get_frame_register_unsigned (frame, 5),
1484 (long) get_frame_register_unsigned (frame, 6),
1485 (long) get_frame_register_unsigned (frame, 7));
1486 printf_filtered
1487 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1488 (long) get_frame_register_unsigned (frame, 8),
1489 (long) get_frame_register_unsigned (frame, 9),
1490 (long) get_frame_register_unsigned (frame, 10),
1491 (long) get_frame_register_unsigned (frame, 11),
1492 (long) get_frame_register_unsigned (frame, 12),
1493 (long) get_frame_register_unsigned (frame, 13),
1494 (long) get_frame_register_unsigned (frame, 14),
1495 (long) get_frame_register_unsigned (frame, 15));
c906108c
SS		 1496}
1497
2d188dd3 1498static void
c458d6db 1499sh2e_show_regs (struct frame_info *frame)
2d188dd3 1500{
b47193f7 1501 struct gdbarch *gdbarch = get_frame_arch (frame);
c458d6db
UW		 1502 printf_filtered
1503 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 1504 phex (get_frame_register_unsigned (frame,
1505 gdbarch_pc_regnum (gdbarch)), 4),
c458d6db
UW		 1506 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1507 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1508 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1509
1510 printf_filtered
1511 (" GBR %08lx VBR %08lx MACL %08lx\n",
1512 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1513 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1514 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1515 printf_filtered
1516 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1517 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1518 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1519 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1520 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
617daa0e
CV		 1521
1522 printf_filtered
a6b0a3f3 1523 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
c458d6db
UW		 1524 (long) get_frame_register_unsigned (frame, 0),
1525 (long) get_frame_register_unsigned (frame, 1),
1526 (long) get_frame_register_unsigned (frame, 2),
1527 (long) get_frame_register_unsigned (frame, 3),
1528 (long) get_frame_register_unsigned (frame, 4),
1529 (long) get_frame_register_unsigned (frame, 5),
1530 (long) get_frame_register_unsigned (frame, 6),
1531 (long) get_frame_register_unsigned (frame, 7));
1532 printf_filtered
1533 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1534 (long) get_frame_register_unsigned (frame, 8),
1535 (long) get_frame_register_unsigned (frame, 9),
1536 (long) get_frame_register_unsigned (frame, 10),
1537 (long) get_frame_register_unsigned (frame, 11),
1538 (long) get_frame_register_unsigned (frame, 12),
1539 (long) get_frame_register_unsigned (frame, 13),
1540 (long) get_frame_register_unsigned (frame, 14),
1541 (long) get_frame_register_unsigned (frame, 15));
1542
1543 printf_filtered
1544 ("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
3e8c568d 1545 (long) get_frame_register_unsigned
b47193f7 1546 (frame, gdbarch_fp0_regnum (gdbarch) + 0),
3e8c568d 1547 (long) get_frame_register_unsigned
b47193f7 1548 (frame, gdbarch_fp0_regnum (gdbarch) + 1),
3e8c568d 1549 (long) get_frame_register_unsigned
b47193f7 1550 (frame, gdbarch_fp0_regnum (gdbarch) + 2),
3e8c568d 1551 (long) get_frame_register_unsigned
b47193f7 1552 (frame, gdbarch_fp0_regnum (gdbarch) + 3),
3e8c568d 1553 (long) get_frame_register_unsigned
b47193f7 1554 (frame, gdbarch_fp0_regnum (gdbarch) + 4),
3e8c568d 1555 (long) get_frame_register_unsigned
b47193f7 1556 (frame, gdbarch_fp0_regnum (gdbarch) + 5),
3e8c568d 1557 (long) get_frame_register_unsigned
b47193f7 1558 (frame, gdbarch_fp0_regnum (gdbarch) + 6),
3e8c568d 1559 (long) get_frame_register_unsigned
b47193f7 1560 (frame, gdbarch_fp0_regnum (gdbarch) + 7));
c458d6db
UW		 1561 printf_filtered
1562 ("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
3e8c568d 1563 (long) get_frame_register_unsigned
b47193f7 1564 (frame, gdbarch_fp0_regnum (gdbarch) + 8),
3e8c568d 1565 (long) get_frame_register_unsigned
b47193f7 1566 (frame, gdbarch_fp0_regnum (gdbarch) + 9),
3e8c568d 1567 (long) get_frame_register_unsigned
b47193f7 1568 (frame, gdbarch_fp0_regnum (gdbarch) + 10),
3e8c568d 1569 (long) get_frame_register_unsigned
b47193f7 1570 (frame, gdbarch_fp0_regnum (gdbarch) + 11),
3e8c568d 1571 (long) get_frame_register_unsigned
b47193f7 1572 (frame, gdbarch_fp0_regnum (gdbarch) + 12),
3e8c568d 1573 (long) get_frame_register_unsigned
b47193f7 1574 (frame, gdbarch_fp0_regnum (gdbarch) + 13),
3e8c568d 1575 (long) get_frame_register_unsigned
b47193f7 1576 (frame, gdbarch_fp0_regnum (gdbarch) + 14),
3e8c568d 1577 (long) get_frame_register_unsigned
b47193f7 1578 (frame, gdbarch_fp0_regnum (gdbarch) + 15));
2d188dd3
NC		 1579}
1580
da962468 1581static void
c458d6db 1582sh2a_show_regs (struct frame_info *frame)
da962468 1583{
b47193f7 1584 struct gdbarch *gdbarch = get_frame_arch (frame);
c458d6db
UW		 1585 int pr = get_frame_register_unsigned (frame, FPSCR_REGNUM) & 0x80000;
1586
1587 printf_filtered
1588 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 1589 phex (get_frame_register_unsigned (frame,
1590 gdbarch_pc_regnum (gdbarch)), 4),
c458d6db
UW		 1591 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1592 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1593 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1594
1595 printf_filtered
1596 (" GBR %08lx VBR %08lx TBR %08lx MACL %08lx\n",
1597 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1598 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1599 (long) get_frame_register_unsigned (frame, TBR_REGNUM),
1600 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1601 printf_filtered
1602 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1603 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1604 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1605 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1606 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1607
1608 printf_filtered
1609 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1610 (long) get_frame_register_unsigned (frame, 0),
1611 (long) get_frame_register_unsigned (frame, 1),
1612 (long) get_frame_register_unsigned (frame, 2),
1613 (long) get_frame_register_unsigned (frame, 3),
1614 (long) get_frame_register_unsigned (frame, 4),
1615 (long) get_frame_register_unsigned (frame, 5),
1616 (long) get_frame_register_unsigned (frame, 6),
1617 (long) get_frame_register_unsigned (frame, 7));
1618 printf_filtered
1619 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1620 (long) get_frame_register_unsigned (frame, 8),
1621 (long) get_frame_register_unsigned (frame, 9),
1622 (long) get_frame_register_unsigned (frame, 10),
1623 (long) get_frame_register_unsigned (frame, 11),
1624 (long) get_frame_register_unsigned (frame, 12),
1625 (long) get_frame_register_unsigned (frame, 13),
1626 (long) get_frame_register_unsigned (frame, 14),
1627 (long) get_frame_register_unsigned (frame, 15));
1628
1629 printf_filtered
1630 (pr ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1631 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
3e8c568d 1632 (long) get_frame_register_unsigned
b47193f7 1633 (frame, gdbarch_fp0_regnum (gdbarch) + 0),
3e8c568d 1634 (long) get_frame_register_unsigned
b47193f7 1635 (frame, gdbarch_fp0_regnum (gdbarch) + 1),
3e8c568d 1636 (long) get_frame_register_unsigned
b47193f7 1637 (frame, gdbarch_fp0_regnum (gdbarch) + 2),
3e8c568d 1638 (long) get_frame_register_unsigned
b47193f7 1639 (frame, gdbarch_fp0_regnum (gdbarch) + 3),
3e8c568d 1640 (long) get_frame_register_unsigned
b47193f7 1641 (frame, gdbarch_fp0_regnum (gdbarch) + 4),
3e8c568d 1642 (long) get_frame_register_unsigned
b47193f7 1643 (frame, gdbarch_fp0_regnum (gdbarch) + 5),
3e8c568d 1644 (long) get_frame_register_unsigned
b47193f7 1645 (frame, gdbarch_fp0_regnum (gdbarch) + 6),
3e8c568d 1646 (long) get_frame_register_unsigned
b47193f7 1647 (frame, gdbarch_fp0_regnum (gdbarch) + 7));
c458d6db
UW		 1648 printf_filtered
1649 (pr ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1650 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
3e8c568d 1651 (long) get_frame_register_unsigned
b47193f7 1652 (frame, gdbarch_fp0_regnum (gdbarch) + 8),
3e8c568d 1653 (long) get_frame_register_unsigned
b47193f7 1654 (frame, gdbarch_fp0_regnum (gdbarch) + 9),
3e8c568d 1655 (long) get_frame_register_unsigned
b47193f7 1656 (frame, gdbarch_fp0_regnum (gdbarch) + 10),
3e8c568d 1657 (long) get_frame_register_unsigned
b47193f7 1658 (frame, gdbarch_fp0_regnum (gdbarch) + 11),
3e8c568d 1659 (long) get_frame_register_unsigned
b47193f7 1660 (frame, gdbarch_fp0_regnum (gdbarch) + 12),
3e8c568d 1661 (long) get_frame_register_unsigned
b47193f7 1662 (frame, gdbarch_fp0_regnum (gdbarch) + 13),
3e8c568d 1663 (long) get_frame_register_unsigned
b47193f7 1664 (frame, gdbarch_fp0_regnum (gdbarch) + 14),
3e8c568d 1665 (long) get_frame_register_unsigned
b47193f7 1666 (frame, gdbarch_fp0_regnum (gdbarch) + 15));
c458d6db
UW		 1667 printf_filtered
1668 ("BANK=%-3d\n", (int) get_frame_register_unsigned (frame, BANK_REGNUM));
1669 printf_filtered
1670 ("R0b-R7b %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1671 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 0),
1672 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 1),
1673 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 2),
1674 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 3),
1675 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 4),
1676 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 5),
1677 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 6),
1678 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 7));
1679 printf_filtered
1680 ("R8b-R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1681 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 8),
1682 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 9),
1683 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 10),
1684 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 11),
1685 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 12),
1686 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 13),
1687 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 14));
1688 printf_filtered
1689 ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n",
1690 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 15),
1691 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 16),
1692 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 17),
1693 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 18),
1694 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 19));
da962468
CV		 1695}
1696
1697static void
c458d6db 1698sh2a_nofpu_show_regs (struct frame_info *frame)
da962468 1699{
c458d6db
UW		 1700 int pr = get_frame_register_unsigned (frame, FPSCR_REGNUM) & 0x80000;
1701
1702 printf_filtered
1703 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 1704 phex (get_frame_register_unsigned (frame,
1705 gdbarch_pc_regnum
1706 (get_frame_arch (frame))), 4),
c458d6db
UW		 1707 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1708 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1709 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1710
1711 printf_filtered
1712 (" GBR %08lx VBR %08lx TBR %08lx MACL %08lx\n",
1713 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1714 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1715 (long) get_frame_register_unsigned (frame, TBR_REGNUM),
1716 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1717 printf_filtered
1718 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1719 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1720 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1721 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1722 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1723
1724 printf_filtered
1725 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1726 (long) get_frame_register_unsigned (frame, 0),
1727 (long) get_frame_register_unsigned (frame, 1),
1728 (long) get_frame_register_unsigned (frame, 2),
1729 (long) get_frame_register_unsigned (frame, 3),
1730 (long) get_frame_register_unsigned (frame, 4),
1731 (long) get_frame_register_unsigned (frame, 5),
1732 (long) get_frame_register_unsigned (frame, 6),
1733 (long) get_frame_register_unsigned (frame, 7));
1734 printf_filtered
1735 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1736 (long) get_frame_register_unsigned (frame, 8),
1737 (long) get_frame_register_unsigned (frame, 9),
1738 (long) get_frame_register_unsigned (frame, 10),
1739 (long) get_frame_register_unsigned (frame, 11),
1740 (long) get_frame_register_unsigned (frame, 12),
1741 (long) get_frame_register_unsigned (frame, 13),
1742 (long) get_frame_register_unsigned (frame, 14),
1743 (long) get_frame_register_unsigned (frame, 15));
1744
1745 printf_filtered
1746 ("BANK=%-3d\n", (int) get_frame_register_unsigned (frame, BANK_REGNUM));
1747 printf_filtered
1748 ("R0b-R7b %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1749 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 0),
1750 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 1),
1751 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 2),
1752 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 3),
1753 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 4),
1754 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 5),
1755 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 6),
1756 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 7));
1757 printf_filtered
1758 ("R8b-R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1759 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 8),
1760 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 9),
1761 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 10),
1762 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 11),
1763 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 12),
1764 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 13),
1765 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 14));
1766 printf_filtered
1767 ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n",
1768 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 15),
1769 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 16),
1770 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 17),
1771 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 18),
1772 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 19));
da962468
CV		 1773}
1774
cc17453a 1775static void
c458d6db 1776sh3e_show_regs (struct frame_info *frame)
cc17453a 1777{
b47193f7 1778 struct gdbarch *gdbarch = get_frame_arch (frame);
c458d6db
UW		 1779 printf_filtered
1780 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 1781 phex (get_frame_register_unsigned (frame,
1782 gdbarch_pc_regnum (gdbarch)), 4),
c458d6db
UW		 1783 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1784 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1785 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1786
1787 printf_filtered
1788 (" GBR %08lx VBR %08lx MACL %08lx\n",
1789 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1790 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1791 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1792 printf_filtered
1793 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1794 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1795 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1796 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1797 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
c906108c 1798
617daa0e 1799 printf_filtered
a6b0a3f3 1800 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
c458d6db
UW		 1801 (long) get_frame_register_unsigned (frame, 0),
1802 (long) get_frame_register_unsigned (frame, 1),
1803 (long) get_frame_register_unsigned (frame, 2),
1804 (long) get_frame_register_unsigned (frame, 3),
1805 (long) get_frame_register_unsigned (frame, 4),
1806 (long) get_frame_register_unsigned (frame, 5),
1807 (long) get_frame_register_unsigned (frame, 6),
1808 (long) get_frame_register_unsigned (frame, 7));
1809 printf_filtered
1810 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1811 (long) get_frame_register_unsigned (frame, 8),
1812 (long) get_frame_register_unsigned (frame, 9),
1813 (long) get_frame_register_unsigned (frame, 10),
1814 (long) get_frame_register_unsigned (frame, 11),
1815 (long) get_frame_register_unsigned (frame, 12),
1816 (long) get_frame_register_unsigned (frame, 13),
1817 (long) get_frame_register_unsigned (frame, 14),
1818 (long) get_frame_register_unsigned (frame, 15));
1819
1820 printf_filtered
1821 ("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
3e8c568d 1822 (long) get_frame_register_unsigned
b47193f7 1823 (frame, gdbarch_fp0_regnum (gdbarch) + 0),
3e8c568d 1824 (long) get_frame_register_unsigned
b47193f7 1825 (frame, gdbarch_fp0_regnum (gdbarch) + 1),
3e8c568d 1826 (long) get_frame_register_unsigned
b47193f7 1827 (frame, gdbarch_fp0_regnum (gdbarch) + 2),
3e8c568d 1828 (long) get_frame_register_unsigned
b47193f7 1829 (frame, gdbarch_fp0_regnum (gdbarch) + 3),
3e8c568d 1830 (long) get_frame_register_unsigned
b47193f7 1831 (frame, gdbarch_fp0_regnum (gdbarch) + 4),
3e8c568d 1832 (long) get_frame_register_unsigned
b47193f7 1833 (frame, gdbarch_fp0_regnum (gdbarch) + 5),
3e8c568d 1834 (long) get_frame_register_unsigned
b47193f7 1835 (frame, gdbarch_fp0_regnum (gdbarch) + 6),
3e8c568d 1836 (long) get_frame_register_unsigned
b47193f7 1837 (frame, gdbarch_fp0_regnum (gdbarch) + 7));
c458d6db
UW		 1838 printf_filtered
1839 ("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
3e8c568d 1840 (long) get_frame_register_unsigned
b47193f7 1841 (frame, gdbarch_fp0_regnum (gdbarch) + 8),
3e8c568d 1842 (long) get_frame_register_unsigned
b47193f7 1843 (frame, gdbarch_fp0_regnum (gdbarch) + 9),
3e8c568d 1844 (long) get_frame_register_unsigned
b47193f7 1845 (frame, gdbarch_fp0_regnum (gdbarch) + 10),
3e8c568d 1846 (long) get_frame_register_unsigned
b47193f7 1847 (frame, gdbarch_fp0_regnum (gdbarch) + 11),
3e8c568d 1848 (long) get_frame_register_unsigned
b47193f7 1849 (frame, gdbarch_fp0_regnum (gdbarch) + 12),
3e8c568d 1850 (long) get_frame_register_unsigned
b47193f7 1851 (frame, gdbarch_fp0_regnum (gdbarch) + 13),
3e8c568d 1852 (long) get_frame_register_unsigned
b47193f7 1853 (frame, gdbarch_fp0_regnum (gdbarch) + 14),
3e8c568d 1854 (long) get_frame_register_unsigned
b47193f7 1855 (frame, gdbarch_fp0_regnum (gdbarch) + 15));
cc17453a
EZ		 1856}
1857
1858static void
c458d6db 1859sh3_dsp_show_regs (struct frame_info *frame)
c906108c 1860{
c458d6db
UW		 1861 printf_filtered
1862 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 1863 phex (get_frame_register_unsigned (frame,
1864 gdbarch_pc_regnum
1865 (get_frame_arch (frame))), 4),
c458d6db
UW		 1866 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1867 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1868 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
c906108c 1869
c458d6db
UW		 1870 printf_filtered
1871 (" GBR %08lx VBR %08lx MACL %08lx\n",
1872 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1873 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1874 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
cc17453a 1875
c458d6db
UW		 1876 printf_filtered
1877 (" SSR %08lx SPC %08lx DSR %08lx\n",
1878 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1879 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1880 (long) get_frame_register_unsigned (frame, DSR_REGNUM));
617daa0e
CV		 1881
1882 printf_filtered
a6b0a3f3 1883 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
c458d6db
UW		 1884 (long) get_frame_register_unsigned (frame, 0),
1885 (long) get_frame_register_unsigned (frame, 1),
1886 (long) get_frame_register_unsigned (frame, 2),
1887 (long) get_frame_register_unsigned (frame, 3),
1888 (long) get_frame_register_unsigned (frame, 4),
1889 (long) get_frame_register_unsigned (frame, 5),
1890 (long) get_frame_register_unsigned (frame, 6),
1891 (long) get_frame_register_unsigned (frame, 7));
1892 printf_filtered
1893 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1894 (long) get_frame_register_unsigned (frame, 8),
1895 (long) get_frame_register_unsigned (frame, 9),
1896 (long) get_frame_register_unsigned (frame, 10),
1897 (long) get_frame_register_unsigned (frame, 11),
1898 (long) get_frame_register_unsigned (frame, 12),
1899 (long) get_frame_register_unsigned (frame, 13),
1900 (long) get_frame_register_unsigned (frame, 14),
1901 (long) get_frame_register_unsigned (frame, 15));
617daa0e
CV		 1902
1903 printf_filtered
1904 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
c458d6db
UW		 1905 (long) get_frame_register_unsigned (frame, A0G_REGNUM) & 0xff,
1906 (long) get_frame_register_unsigned (frame, A0_REGNUM),
1907 (long) get_frame_register_unsigned (frame, M0_REGNUM),
1908 (long) get_frame_register_unsigned (frame, X0_REGNUM),
1909 (long) get_frame_register_unsigned (frame, Y0_REGNUM),
1910 (long) get_frame_register_unsigned (frame, RS_REGNUM),
1911 (long) get_frame_register_unsigned (frame, MOD_REGNUM));
1912 printf_filtered
1913 ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1914 (long) get_frame_register_unsigned (frame, A1G_REGNUM) & 0xff,
1915 (long) get_frame_register_unsigned (frame, A1_REGNUM),
1916 (long) get_frame_register_unsigned (frame, M1_REGNUM),
1917 (long) get_frame_register_unsigned (frame, X1_REGNUM),
1918 (long) get_frame_register_unsigned (frame, Y1_REGNUM),
1919 (long) get_frame_register_unsigned (frame, RE_REGNUM));
c906108c
SS		 1920}
1921
cc17453a 1922static void
c458d6db 1923sh4_show_regs (struct frame_info *frame)
cc17453a 1924{
b47193f7 1925 struct gdbarch *gdbarch = get_frame_arch (frame);
c458d6db
UW		 1926 int pr = get_frame_register_unsigned (frame, FPSCR_REGNUM) & 0x80000;
1927
1928 printf_filtered
1929 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 1930 phex (get_frame_register_unsigned (frame,
1931 gdbarch_pc_regnum (gdbarch)), 4),
c458d6db
UW		 1932 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1933 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1934 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1935
1936 printf_filtered
1937 (" GBR %08lx VBR %08lx MACL %08lx\n",
1938 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1939 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1940 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1941 printf_filtered
1942 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1943 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1944 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1945 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1946 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1947
1948 printf_filtered
1949 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1950 (long) get_frame_register_unsigned (frame, 0),
1951 (long) get_frame_register_unsigned (frame, 1),
1952 (long) get_frame_register_unsigned (frame, 2),
1953 (long) get_frame_register_unsigned (frame, 3),
1954 (long) get_frame_register_unsigned (frame, 4),
1955 (long) get_frame_register_unsigned (frame, 5),
1956 (long) get_frame_register_unsigned (frame, 6),
1957 (long) get_frame_register_unsigned (frame, 7));
1958 printf_filtered
1959 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1960 (long) get_frame_register_unsigned (frame, 8),
1961 (long) get_frame_register_unsigned (frame, 9),
1962 (long) get_frame_register_unsigned (frame, 10),
1963 (long) get_frame_register_unsigned (frame, 11),
1964 (long) get_frame_register_unsigned (frame, 12),
1965 (long) get_frame_register_unsigned (frame, 13),
1966 (long) get_frame_register_unsigned (frame, 14),
1967 (long) get_frame_register_unsigned (frame, 15));
1968
1969 printf_filtered
1970 (pr ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1971 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
3e8c568d 1972 (long) get_frame_register_unsigned
b47193f7 1973 (frame, gdbarch_fp0_regnum (gdbarch) + 0),
3e8c568d 1974 (long) get_frame_register_unsigned
b47193f7 1975 (frame, gdbarch_fp0_regnum (gdbarch) + 1),
3e8c568d 1976 (long) get_frame_register_unsigned
b47193f7 1977 (frame, gdbarch_fp0_regnum (gdbarch) + 2),
3e8c568d 1978 (long) get_frame_register_unsigned
b47193f7 1979 (frame, gdbarch_fp0_regnum (gdbarch) + 3),
3e8c568d 1980 (long) get_frame_register_unsigned
b47193f7 1981 (frame, gdbarch_fp0_regnum (gdbarch) + 4),
3e8c568d 1982 (long) get_frame_register_unsigned
b47193f7 1983 (frame, gdbarch_fp0_regnum (gdbarch) + 5),
3e8c568d 1984 (long) get_frame_register_unsigned
b47193f7 1985 (frame, gdbarch_fp0_regnum (gdbarch) + 6),
3e8c568d 1986 (long) get_frame_register_unsigned
b47193f7 1987 (frame, gdbarch_fp0_regnum (gdbarch) + 7));
c458d6db
UW		 1988 printf_filtered
1989 (pr ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1990 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
3e8c568d 1991 (long) get_frame_register_unsigned
b47193f7 1992 (frame, gdbarch_fp0_regnum (gdbarch) + 8),
3e8c568d 1993 (long) get_frame_register_unsigned
b47193f7 1994 (frame, gdbarch_fp0_regnum (gdbarch) + 9),
3e8c568d 1995 (long) get_frame_register_unsigned
b47193f7 1996 (frame, gdbarch_fp0_regnum (gdbarch) + 10),
3e8c568d 1997 (long) get_frame_register_unsigned
b47193f7 1998 (frame, gdbarch_fp0_regnum (gdbarch) + 11),
3e8c568d 1999 (long) get_frame_register_unsigned
b47193f7 2000 (frame, gdbarch_fp0_regnum (gdbarch) + 12),
3e8c568d 2001 (long) get_frame_register_unsigned
b47193f7 2002 (frame, gdbarch_fp0_regnum (gdbarch) + 13),
3e8c568d 2003 (long) get_frame_register_unsigned
b47193f7 2004 (frame, gdbarch_fp0_regnum (gdbarch) + 14),
3e8c568d 2005 (long) get_frame_register_unsigned
b47193f7 2006 (frame, gdbarch_fp0_regnum (gdbarch) + 15));
cc17453a
EZ		 2007}
2008
474e5826 2009static void
c458d6db 2010sh4_nofpu_show_regs (struct frame_info *frame)
474e5826 2011{
c458d6db
UW		 2012 printf_filtered
2013 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 2014 phex (get_frame_register_unsigned (frame,
2015 gdbarch_pc_regnum
2016 (get_frame_arch (frame))), 4),
c458d6db
UW		 2017 (long) get_frame_register_unsigned (frame, SR_REGNUM),
2018 (long) get_frame_register_unsigned (frame, PR_REGNUM),
2019 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
2020
2021 printf_filtered
2022 (" GBR %08lx VBR %08lx MACL %08lx\n",
2023 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
2024 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
2025 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
2026 printf_filtered
2027 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
2028 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
2029 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
2030 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
2031 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
2032
2033 printf_filtered
2034 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2035 (long) get_frame_register_unsigned (frame, 0),
2036 (long) get_frame_register_unsigned (frame, 1),
2037 (long) get_frame_register_unsigned (frame, 2),
2038 (long) get_frame_register_unsigned (frame, 3),
2039 (long) get_frame_register_unsigned (frame, 4),
2040 (long) get_frame_register_unsigned (frame, 5),
2041 (long) get_frame_register_unsigned (frame, 6),
2042 (long) get_frame_register_unsigned (frame, 7));
2043 printf_filtered
2044 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2045 (long) get_frame_register_unsigned (frame, 8),
2046 (long) get_frame_register_unsigned (frame, 9),
2047 (long) get_frame_register_unsigned (frame, 10),
2048 (long) get_frame_register_unsigned (frame, 11),
2049 (long) get_frame_register_unsigned (frame, 12),
2050 (long) get_frame_register_unsigned (frame, 13),
2051 (long) get_frame_register_unsigned (frame, 14),
2052 (long) get_frame_register_unsigned (frame, 15));
474e5826
CV		 2053}
2054
cc17453a 2055static void
c458d6db 2056sh_dsp_show_regs (struct frame_info *frame)
cc17453a 2057{
c458d6db
UW		 2058 printf_filtered
2059 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
5af949e3
UW		 2060 phex (get_frame_register_unsigned (frame,
2061 gdbarch_pc_regnum
2062 (get_frame_arch (frame))), 4),
c458d6db
UW		 2063 (long) get_frame_register_unsigned (frame, SR_REGNUM),
2064 (long) get_frame_register_unsigned (frame, PR_REGNUM),
2065 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
a6b0a3f3 2066
c458d6db
UW		 2067 printf_filtered
2068 (" GBR %08lx VBR %08lx DSR %08lx MACL %08lx\n",
2069 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
2070 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
2071 (long) get_frame_register_unsigned (frame, DSR_REGNUM),
2072 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
617daa0e
CV		 2073
2074 printf_filtered
a6b0a3f3 2075 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
c458d6db
UW		 2076 (long) get_frame_register_unsigned (frame, 0),
2077 (long) get_frame_register_unsigned (frame, 1),
2078 (long) get_frame_register_unsigned (frame, 2),
2079 (long) get_frame_register_unsigned (frame, 3),
2080 (long) get_frame_register_unsigned (frame, 4),
2081 (long) get_frame_register_unsigned (frame, 5),
2082 (long) get_frame_register_unsigned (frame, 6),
2083 (long) get_frame_register_unsigned (frame, 7));
2084 printf_filtered
2085 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2086 (long) get_frame_register_unsigned (frame, 8),
2087 (long) get_frame_register_unsigned (frame, 9),
2088 (long) get_frame_register_unsigned (frame, 10),
2089 (long) get_frame_register_unsigned (frame, 11),
2090 (long) get_frame_register_unsigned (frame, 12),
2091 (long) get_frame_register_unsigned (frame, 13),
2092 (long) get_frame_register_unsigned (frame, 14),
2093 (long) get_frame_register_unsigned (frame, 15));
617daa0e
CV		 2094
2095 printf_filtered
2096 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
c458d6db
UW		 2097 (long) get_frame_register_unsigned (frame, A0G_REGNUM) & 0xff,
2098 (long) get_frame_register_unsigned (frame, A0_REGNUM),
2099 (long) get_frame_register_unsigned (frame, M0_REGNUM),
2100 (long) get_frame_register_unsigned (frame, X0_REGNUM),
2101 (long) get_frame_register_unsigned (frame, Y0_REGNUM),
2102 (long) get_frame_register_unsigned (frame, RS_REGNUM),
2103 (long) get_frame_register_unsigned (frame, MOD_REGNUM));
cc17453a 2104 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
c458d6db
UW		 2105 (long) get_frame_register_unsigned (frame, A1G_REGNUM) & 0xff,
2106 (long) get_frame_register_unsigned (frame, A1_REGNUM),
2107 (long) get_frame_register_unsigned (frame, M1_REGNUM),
2108 (long) get_frame_register_unsigned (frame, X1_REGNUM),
2109 (long) get_frame_register_unsigned (frame, Y1_REGNUM),
2110 (long) get_frame_register_unsigned (frame, RE_REGNUM));
cc17453a
EZ		 2111}
2112
a78f21af
AC		 2113static void
2114sh_show_regs_command (char *args, int from_tty)
53116e27
EZ		 2115{
2116 if (sh_show_regs)
c458d6db 2117 (*sh_show_regs) (get_current_frame ());
53116e27
EZ		 2118}
2119
da962468
CV		 2120static struct type *
2121sh_sh2a_register_type (struct gdbarch *gdbarch, int reg_nr)
2122{
b47193f7 2123 if ((reg_nr >= gdbarch_fp0_regnum (gdbarch)
da962468 2124 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
0dfff4cb 2125 return builtin_type (gdbarch)->builtin_float;
da962468 2126 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
0dfff4cb 2127 return builtin_type (gdbarch)->builtin_double;
da962468 2128 else
0dfff4cb 2129 return builtin_type (gdbarch)->builtin_int;
da962468
CV		 2130}
2131
cc17453a
EZ		 2132/* Return the GDB type object for the "standard" data type
2133 of data in register N. */
cc17453a 2134static struct type *
48db5a3c 2135sh_sh3e_register_type (struct gdbarch *gdbarch, int reg_nr)
cc17453a 2136{
b47193f7 2137 if ((reg_nr >= gdbarch_fp0_regnum (gdbarch)
617daa0e 2138 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
0dfff4cb 2139 return builtin_type (gdbarch)->builtin_float;
8db62801 2140 else
0dfff4cb 2141 return builtin_type (gdbarch)->builtin_int;
cc17453a
EZ		 2142}
2143
7f4dbe94 2144static struct type *
0dfff4cb 2145sh_sh4_build_float_register_type (struct gdbarch *gdbarch, int high)
7f4dbe94 2146{
e3506a9f
UW		 2147 return lookup_array_range_type (builtin_type (gdbarch)->builtin_float,
2148 0, high);
7f4dbe94
EZ		 2149}
2150
53116e27 2151static struct type *
48db5a3c 2152sh_sh4_register_type (struct gdbarch *gdbarch, int reg_nr)
53116e27 2153{
b47193f7 2154 if ((reg_nr >= gdbarch_fp0_regnum (gdbarch)
617daa0e 2155 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
0dfff4cb 2156 return builtin_type (gdbarch)->builtin_float;
617daa0e 2157 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
0dfff4cb 2158 return builtin_type (gdbarch)->builtin_double;
617daa0e 2159 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
0dfff4cb 2160 return sh_sh4_build_float_register_type (gdbarch, 3);
53116e27 2161 else
0dfff4cb 2162 return builtin_type (gdbarch)->builtin_int;
53116e27
EZ		 2163}
2164
cc17453a 2165static struct type *
48db5a3c 2166sh_default_register_type (struct gdbarch *gdbarch, int reg_nr)
cc17453a 2167{
0dfff4cb 2168 return builtin_type (gdbarch)->builtin_int;
cc17453a
EZ		 2169}
2170
dda63807
AS		 2171/* Is a register in a reggroup?
2172 The default code in reggroup.c doesn't identify system registers, some
2173 float registers or any of the vector registers.
2174 TODO: sh2a and dsp registers. */
63807e1d 2175static int
dda63807
AS		 2176sh_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2177 struct reggroup *reggroup)
2178{
b47193f7
UW		 2179 if (gdbarch_register_name (gdbarch, regnum) == NULL
2180 || *gdbarch_register_name (gdbarch, regnum) == '\0')
dda63807
AS		 2181 return 0;
2182
2183 if (reggroup == float_reggroup
2184 && (regnum == FPUL_REGNUM
2185 || regnum == FPSCR_REGNUM))
2186 return 1;
2187
2188 if (regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM)
2189 {
2190 if (reggroup == vector_reggroup || reggroup == float_reggroup)
2191 return 1;
2192 if (reggroup == general_reggroup)
2193 return 0;
2194 }
2195
2196 if (regnum == VBR_REGNUM
2197 || regnum == SR_REGNUM
2198 || regnum == FPSCR_REGNUM
2199 || regnum == SSR_REGNUM
2200 || regnum == SPC_REGNUM)
2201 {
2202 if (reggroup == system_reggroup)
2203 return 1;
2204 if (reggroup == general_reggroup)
2205 return 0;
2206 }
2207
2208 /* The default code can cope with any other registers. */
2209 return default_register_reggroup_p (gdbarch, regnum, reggroup);
2210}
2211
fb409745 2212/* On the sh4, the DRi pseudo registers are problematic if the target
c378eb4e 2213 is little endian. When the user writes one of those registers, for
fb409745
EZ		 2214 instance with 'ser var $dr0=1', we want the double to be stored
2215 like this:
2216 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
2217 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2218
2219 This corresponds to little endian byte order & big endian word
2220 order. However if we let gdb write the register w/o conversion, it
2221 will write fr0 and fr1 this way:
2222 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2223 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
2224 because it will consider fr0 and fr1 as a single LE stretch of memory.
2225
2226 To achieve what we want we must force gdb to store things in
2227 floatformat_ieee_double_littlebyte_bigword (which is defined in
2228 include/floatformat.h and libiberty/floatformat.c.
2229
2230 In case the target is big endian, there is no problem, the
2231 raw bytes will look like:
2232 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
2233 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2234
2235 The other pseudo registers (the FVs) also don't pose a problem
c378eb4e 2236 because they are stored as 4 individual FP elements. */
fb409745 2237
7bd872fe 2238static void
b66ba949
CV		 2239sh_register_convert_to_virtual (int regnum, struct type *type,
2240 char *from, char *to)
55ff77ac 2241{
617daa0e 2242 if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
283150cd
EZ		 2243 {
2244 DOUBLEST val;
617daa0e
CV		 2245 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
2246 from, &val);
55ff77ac 2247 store_typed_floating (to, type, val);
283150cd
EZ		 2248 }
2249 else
617daa0e
CV		 2250 error
2251 ("sh_register_convert_to_virtual called with non DR register number");
283150cd
EZ		 2252}
2253
2254static void
b66ba949
CV		 2255sh_register_convert_to_raw (struct type *type, int regnum,
2256 const void *from, void *to)
283150cd 2257{
617daa0e 2258 if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
283150cd 2259 {
48db5a3c 2260 DOUBLEST val = extract_typed_floating (from, type);
617daa0e
CV		 2261 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword,
2262 &val, to);
283150cd
EZ		 2263 }
2264 else
8a3fe4f8 2265 error (_("sh_register_convert_to_raw called with non DR register number"));
283150cd
EZ		 2266}
2267
c378eb4e 2268/* For vectors of 4 floating point registers. */
1c0159e0 2269static int
d93859e2 2270fv_reg_base_num (struct gdbarch *gdbarch, int fv_regnum)
1c0159e0
CV		 2271{
2272 int fp_regnum;
2273
d93859e2 2274 fp_regnum = gdbarch_fp0_regnum (gdbarch)
3e8c568d 2275 + (fv_regnum - FV0_REGNUM) * 4;
1c0159e0
CV		 2276 return fp_regnum;
2277}
2278
c378eb4e 2279/* For double precision floating point registers, i.e 2 fp regs. */
1c0159e0 2280static int
d93859e2 2281dr_reg_base_num (struct gdbarch *gdbarch, int dr_regnum)
1c0159e0
CV		 2282{
2283 int fp_regnum;
2284
d93859e2 2285 fp_regnum = gdbarch_fp0_regnum (gdbarch)
3e8c568d 2286 + (dr_regnum - DR0_REGNUM) * 2;
1c0159e0
CV		 2287 return fp_regnum;
2288}
2289
05d1431c
PA		 2290/* Concatenate PORTIONS contiguous raw registers starting at
2291 BASE_REGNUM into BUFFER. */
2292
2293static enum register_status
2294pseudo_register_read_portions (struct gdbarch *gdbarch,
2295 struct regcache *regcache,
2296 int portions,
2297 int base_regnum, gdb_byte *buffer)
2298{
2299 int portion;
2300
2301 for (portion = 0; portion < portions; portion++)
2302 {
2303 enum register_status status;
2304 gdb_byte *b;
2305
2306 b = buffer + register_size (gdbarch, base_regnum) * portion;
2307 status = regcache_raw_read (regcache, base_regnum + portion, b);
2308 if (status != REG_VALID)
2309 return status;
2310 }
2311
2312 return REG_VALID;
2313}
2314
2315static enum register_status
d8124050 2316sh_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
18cf8b5b 2317 int reg_nr, gdb_byte *buffer)
53116e27 2318{
05d1431c 2319 int base_regnum;
d9d9c31f 2320 char temp_buffer[MAX_REGISTER_SIZE];
05d1431c 2321 enum register_status status;
53116e27 2322
9bed62d7 2323 if (reg_nr == PSEUDO_BANK_REGNUM)
05d1431c
PA		 2324 return regcache_raw_read (regcache, BANK_REGNUM, buffer);
2325 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
7bd872fe 2326 {
d93859e2 2327 base_regnum = dr_reg_base_num (gdbarch, reg_nr);
7bd872fe 2328
c378eb4e 2329 /* Build the value in the provided buffer. */
7bd872fe 2330 /* Read the real regs for which this one is an alias. */
05d1431c
PA		 2331 status = pseudo_register_read_portions (gdbarch, regcache,
2332 2, base_regnum, temp_buffer);
2333 if (status == REG_VALID)
2334 {
2335 /* We must pay attention to the endiannes. */
2336 sh_register_convert_to_virtual (reg_nr,
2337 register_type (gdbarch, reg_nr),
2338 temp_buffer, buffer);
2339 }
2340 return status;
7bd872fe 2341 }
617daa0e 2342 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
53116e27 2343 {
d93859e2 2344 base_regnum = fv_reg_base_num (gdbarch, reg_nr);
7bd872fe
EZ		 2345
2346 /* Read the real regs for which this one is an alias. */
05d1431c
PA		 2347 return pseudo_register_read_portions (gdbarch, regcache,
2348 4, base_regnum, buffer);
53116e27 2349 }
05d1431c
PA		 2350 else
2351 gdb_assert_not_reached ("invalid pseudo register number");
53116e27
EZ		 2352}
2353
a78f21af 2354static void
d8124050 2355sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
18cf8b5b 2356 int reg_nr, const gdb_byte *buffer)
53116e27
EZ		 2357{
2358 int base_regnum, portion;
d9d9c31f 2359 char temp_buffer[MAX_REGISTER_SIZE];
53116e27 2360
9bed62d7
CV		 2361 if (reg_nr == PSEUDO_BANK_REGNUM)
2362 {
2363 /* When the bank register is written to, the whole register bank
2364 is switched and all values in the bank registers must be read
c378eb4e 2365 from the target/sim again. We're just invalidating the regcache
9bed62d7
CV		 2366 so that a re-read happens next time it's necessary. */
2367 int bregnum;
2368
2369 regcache_raw_write (regcache, BANK_REGNUM, buffer);
2370 for (bregnum = R0_BANK0_REGNUM; bregnum < MACLB_REGNUM; ++bregnum)
9c5ea4d9 2371 regcache_invalidate (regcache, bregnum);
9bed62d7
CV		 2372 }
2373 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
53116e27 2374 {
d93859e2 2375 base_regnum = dr_reg_base_num (gdbarch, reg_nr);
53116e27 2376
c378eb4e 2377 /* We must pay attention to the endiannes. */
7b9ee6a8 2378 sh_register_convert_to_raw (register_type (gdbarch, reg_nr),
b66ba949 2379 reg_nr, buffer, temp_buffer);
7bd872fe 2380
53116e27
EZ		 2381 /* Write the real regs for which this one is an alias. */
2382 for (portion = 0; portion < 2; portion++)
617daa0e 2383 regcache_raw_write (regcache, base_regnum + portion,
0818c12a 2384 (temp_buffer
617daa0e
CV		 2385 + register_size (gdbarch,
2386 base_regnum) * portion));
53116e27 2387 }
617daa0e 2388 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
53116e27 2389 {
d93859e2 2390 base_regnum = fv_reg_base_num (gdbarch, reg_nr);
53116e27
EZ		 2391
2392 /* Write the real regs for which this one is an alias. */
2393 for (portion = 0; portion < 4; portion++)
d8124050
AC		 2394 regcache_raw_write (regcache, base_regnum + portion,
2395 ((char *) buffer
617daa0e
CV		 2396 + register_size (gdbarch,
2397 base_regnum) * portion));
53116e27
EZ		 2398 }
2399}
2400
2f14585c 2401static int
e7faf938 2402sh_dsp_register_sim_regno (struct gdbarch *gdbarch, int nr)
2f14585c 2403{
e7faf938
MD		 2404 if (legacy_register_sim_regno (gdbarch, nr) < 0)
2405 return legacy_register_sim_regno (gdbarch, nr);
f2ea0907
CV		 2406 if (nr >= DSR_REGNUM && nr <= Y1_REGNUM)
2407 return nr - DSR_REGNUM + SIM_SH_DSR_REGNUM;
2408 if (nr == MOD_REGNUM)
2f14585c 2409 return SIM_SH_MOD_REGNUM;
f2ea0907 2410 if (nr == RS_REGNUM)
2f14585c 2411 return SIM_SH_RS_REGNUM;
f2ea0907 2412 if (nr == RE_REGNUM)
2f14585c 2413 return SIM_SH_RE_REGNUM;
76cd2bd9
CV		 2414 if (nr >= DSP_R0_BANK_REGNUM && nr <= DSP_R7_BANK_REGNUM)
2415 return nr - DSP_R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM;
2f14585c
JR		 2416 return nr;
2417}
1c0159e0 2418
da962468 2419static int
e7faf938 2420sh_sh2a_register_sim_regno (struct gdbarch *gdbarch, int nr)
da962468
CV		 2421{
2422 switch (nr)
2423 {
2424 case TBR_REGNUM:
2425 return SIM_SH_TBR_REGNUM;
2426 case IBNR_REGNUM:
2427 return SIM_SH_IBNR_REGNUM;
2428 case IBCR_REGNUM:
2429 return SIM_SH_IBCR_REGNUM;
2430 case BANK_REGNUM:
2431 return SIM_SH_BANK_REGNUM;
2432 case MACLB_REGNUM:
2433 return SIM_SH_BANK_MACL_REGNUM;
2434 case GBRB_REGNUM:
2435 return SIM_SH_BANK_GBR_REGNUM;
2436 case PRB_REGNUM:
2437 return SIM_SH_BANK_PR_REGNUM;
2438 case IVNB_REGNUM:
2439 return SIM_SH_BANK_IVN_REGNUM;
2440 case MACHB_REGNUM:
2441 return SIM_SH_BANK_MACH_REGNUM;
2442 default:
2443 break;
2444 }
e7faf938 2445 return legacy_register_sim_regno (gdbarch, nr);
da962468
CV		 2446}
2447
357d3800
AS		 2448/* Set up the register unwinding such that call-clobbered registers are
2449 not displayed in frames >0 because the true value is not certain.
2450 The 'undefined' registers will show up as 'not available' unless the
2451 CFI says otherwise.
2452
2453 This function is currently set up for SH4 and compatible only. */
2454
2455static void
2456sh_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
aff37fc1 2457 struct dwarf2_frame_state_reg *reg,
4a4e5149 2458 struct frame_info *this_frame)
357d3800
AS		 2459{
2460 /* Mark the PC as the destination for the return address. */
b47193f7 2461 if (regnum == gdbarch_pc_regnum (gdbarch))
357d3800
AS		 2462 reg->how = DWARF2_FRAME_REG_RA;
2463
2464 /* Mark the stack pointer as the call frame address. */
b47193f7 2465 else if (regnum == gdbarch_sp_regnum (gdbarch))
357d3800
AS		 2466 reg->how = DWARF2_FRAME_REG_CFA;
2467
2468 /* The above was taken from the default init_reg in dwarf2-frame.c
2469 while the below is SH specific. */
2470
2471 /* Caller save registers. */
2472 else if ((regnum >= R0_REGNUM && regnum <= R0_REGNUM+7)
2473 || (regnum >= FR0_REGNUM && regnum <= FR0_REGNUM+11)
2474 || (regnum >= DR0_REGNUM && regnum <= DR0_REGNUM+5)
2475 || (regnum >= FV0_REGNUM && regnum <= FV0_REGNUM+2)
2476 || (regnum == MACH_REGNUM)
2477 || (regnum == MACL_REGNUM)
2478 || (regnum == FPUL_REGNUM)
2479 || (regnum == SR_REGNUM))
2480 reg->how = DWARF2_FRAME_REG_UNDEFINED;
2481
2482 /* Callee save registers. */
2483 else if ((regnum >= R0_REGNUM+8 && regnum <= R0_REGNUM+15)
2484 || (regnum >= FR0_REGNUM+12 && regnum <= FR0_REGNUM+15)
2485 || (regnum >= DR0_REGNUM+6 && regnum <= DR0_REGNUM+8)
2486 || (regnum == FV0_REGNUM+3))
2487 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
2488
2489 /* Other registers. These are not in the ABI and may or may not
2490 mean anything in frames >0 so don't show them. */
2491 else if ((regnum >= R0_BANK0_REGNUM && regnum <= R0_BANK0_REGNUM+15)
2492 || (regnum == GBR_REGNUM)
2493 || (regnum == VBR_REGNUM)
2494 || (regnum == FPSCR_REGNUM)
2495 || (regnum == SSR_REGNUM)
2496 || (regnum == SPC_REGNUM))
2497 reg->how = DWARF2_FRAME_REG_UNDEFINED;
2498}
2499
1c0159e0
CV		 2500static struct sh_frame_cache *
2501sh_alloc_frame_cache (void)
2502{
2503 struct sh_frame_cache *cache;
2504 int i;
2505
2506 cache = FRAME_OBSTACK_ZALLOC (struct sh_frame_cache);
2507
2508 /* Base address. */
2509 cache->base = 0;
2510 cache->saved_sp = 0;
2511 cache->sp_offset = 0;
2512 cache->pc = 0;
2513
2514 /* Frameless until proven otherwise. */
2515 cache->uses_fp = 0;
617daa0e 2516
1c0159e0
CV		 2517 /* Saved registers. We initialize these to -1 since zero is a valid
2518 offset (that's where fp is supposed to be stored). */
2519 for (i = 0; i < SH_NUM_REGS; i++)
2520 {
2521 cache->saved_regs[i] = -1;
2522 }
617daa0e 2523
1c0159e0 2524 return cache;
617daa0e 2525}
1c0159e0
CV		 2526
2527static struct sh_frame_cache *
94afd7a6 2528sh_frame_cache (struct frame_info *this_frame, void **this_cache)
1c0159e0 2529{
e17a4113 2530 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1c0159e0
CV		 2531 struct sh_frame_cache *cache;
2532 CORE_ADDR current_pc;
2533 int i;
2534
2535 if (*this_cache)
2536 return *this_cache;
2537
2538 cache = sh_alloc_frame_cache ();
2539 *this_cache = cache;
2540
2541 /* In principle, for normal frames, fp holds the frame pointer,
2542 which holds the base address for the current stack frame.
2543 However, for functions that don't need it, the frame pointer is
2544 optional. For these "frameless" functions the frame pointer is
c378eb4e 2545 actually the frame pointer of the calling frame. */
94afd7a6 2546 cache->base = get_frame_register_unsigned (this_frame, FP_REGNUM);
1c0159e0
CV		 2547 if (cache->base == 0)
2548 return cache;
2549
94afd7a6
UW		 2550 cache->pc = get_frame_func (this_frame);
2551 current_pc = get_frame_pc (this_frame);
1c0159e0 2552 if (cache->pc != 0)
d2ca4222
UW		 2553 {
2554 ULONGEST fpscr;
94afd7a6 2555 fpscr = get_frame_register_unsigned (this_frame, FPSCR_REGNUM);
e17a4113 2556 sh_analyze_prologue (gdbarch, cache->pc, current_pc, cache, fpscr);
d2ca4222 2557 }
617daa0e 2558
1c0159e0
CV		 2559 if (!cache->uses_fp)
2560 {
2561 /* We didn't find a valid frame, which means that CACHE->base
2562 currently holds the frame pointer for our calling frame. If
2563 we're at the start of a function, or somewhere half-way its
2564 prologue, the function's frame probably hasn't been fully
2565 setup yet. Try to reconstruct the base address for the stack
2566 frame by looking at the stack pointer. For truly "frameless"
2567 functions this might work too. */
94afd7a6 2568 cache->base = get_frame_register_unsigned
e17a4113 2569 (this_frame, gdbarch_sp_regnum (gdbarch));
1c0159e0
CV		 2570 }
2571
2572 /* Now that we have the base address for the stack frame we can
2573 calculate the value of sp in the calling frame. */
2574 cache->saved_sp = cache->base + cache->sp_offset;
2575
2576 /* Adjust all the saved registers such that they contain addresses
2577 instead of offsets. */
2578 for (i = 0; i < SH_NUM_REGS; i++)
2579 if (cache->saved_regs[i] != -1)
2580 cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i] - 4;
2581
2582 return cache;
2583}
2584
94afd7a6
UW		 2585static struct value *
2586sh_frame_prev_register (struct frame_info *this_frame,
2587 void **this_cache, int regnum)
1c0159e0 2588{
94afd7a6
UW		 2589 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2590 struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache);
1c0159e0
CV		 2591
2592 gdb_assert (regnum >= 0);
2593
b47193f7 2594 if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp)
94afd7a6 2595 return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp);
1c0159e0
CV		 2596
2597 /* The PC of the previous frame is stored in the PR register of
2598 the current frame. Frob regnum so that we pull the value from
2599 the correct place. */
b47193f7 2600 if (regnum == gdbarch_pc_regnum (gdbarch))
1c0159e0
CV		 2601 regnum = PR_REGNUM;
2602
2603 if (regnum < SH_NUM_REGS && cache->saved_regs[regnum] != -1)
94afd7a6
UW		 2604 return frame_unwind_got_memory (this_frame, regnum,
2605 cache->saved_regs[regnum]);
1c0159e0 2606
94afd7a6 2607 return frame_unwind_got_register (this_frame, regnum, regnum);
1c0159e0
CV		 2608}
2609
2610static void
94afd7a6 2611sh_frame_this_id (struct frame_info *this_frame, void **this_cache,
617daa0e
CV		 2612 struct frame_id *this_id)
2613{
94afd7a6 2614 struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache);
1c0159e0
CV		 2615
2616 /* This marks the outermost frame. */
2617 if (cache->base == 0)
2618 return;
2619
2620 *this_id = frame_id_build (cache->saved_sp, cache->pc);
617daa0e 2621}
1c0159e0 2622
617daa0e 2623static const struct frame_unwind sh_frame_unwind = {
1c0159e0 2624 NORMAL_FRAME,
8fbca658 2625 default_frame_unwind_stop_reason,
1c0159e0 2626 sh_frame_this_id,
94afd7a6
UW		 2627 sh_frame_prev_register,
2628 NULL,
2629 default_frame_sniffer
1c0159e0
CV		 2630};
2631
1c0159e0
CV		 2632static CORE_ADDR
2633sh_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
2634{
3e8c568d 2635 return frame_unwind_register_unsigned (next_frame,
b47193f7 2636 gdbarch_sp_regnum (gdbarch));
1c0159e0
CV		 2637}
2638
2639static CORE_ADDR
2640sh_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2641{
3e8c568d 2642 return frame_unwind_register_unsigned (next_frame,
b47193f7 2643 gdbarch_pc_regnum (gdbarch));
1c0159e0
CV		 2644}
2645
2646static struct frame_id
94afd7a6 2647sh_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1c0159e0 2648{
94afd7a6
UW		 2649 CORE_ADDR sp = get_frame_register_unsigned (this_frame,
2650 gdbarch_sp_regnum (gdbarch));
2651 return frame_id_build (sp, get_frame_pc (this_frame));
1c0159e0
CV		 2652}
2653
2654static CORE_ADDR
94afd7a6 2655sh_frame_base_address (struct frame_info *this_frame, void **this_cache)
617daa0e 2656{
94afd7a6 2657 struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache);
617daa0e 2658
1c0159e0
CV		 2659 return cache->base;
2660}
617daa0e
CV		 2661
2662static const struct frame_base sh_frame_base = {
1c0159e0
CV		 2663 &sh_frame_unwind,
2664 sh_frame_base_address,
2665 sh_frame_base_address,
2666 sh_frame_base_address
617daa0e 2667};
1c0159e0
CV		 2668
2669/* The epilogue is defined here as the area at the end of a function,
2670 either on the `ret' instruction itself or after an instruction which
c378eb4e 2671 destroys the function's stack frame. */
1c0159e0
CV		 2672static int
2673sh_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
2674{
e17a4113 2675 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1c0159e0
CV		 2676 CORE_ADDR func_addr = 0, func_end = 0;
2677
2678 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
2679 {
2680 ULONGEST inst;
2681 /* The sh epilogue is max. 14 bytes long. Give another 14 bytes
2682 for a nop and some fixed data (e.g. big offsets) which are
617daa0e 2683 unfortunately also treated as part of the function (which
c378eb4e 2684 means, they are below func_end. */
1c0159e0
CV		 2685 CORE_ADDR addr = func_end - 28;
2686 if (addr < func_addr + 4)
617daa0e 2687 addr = func_addr + 4;
1c0159e0
CV		 2688 if (pc < addr)
2689 return 0;
2690
c378eb4e 2691 /* First search forward until hitting an rts. */
1c0159e0 2692 while (addr < func_end
e17a4113 2693 && !IS_RTS (read_memory_unsigned_integer (addr, 2, byte_order)))
1c0159e0
CV		 2694 addr += 2;
2695 if (addr >= func_end)
617daa0e 2696 return 0;
1c0159e0
CV		 2697
2698 /* At this point we should find a mov.l @r15+,r14 instruction,
2699 either before or after the rts. If not, then the function has
c378eb4e 2700 probably no "normal" epilogue and we bail out here. */
e17a4113
UW		 2701 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
2702 if (IS_RESTORE_FP (read_memory_unsigned_integer (addr - 2, 2,
2703 byte_order)))
617daa0e 2704 addr -= 2;
e17a4113
UW		 2705 else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr + 2, 2,
2706 byte_order)))
1c0159e0
CV		 2707 return 0;
2708
e17a4113 2709 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
03131d99 2710
c378eb4e 2711 /* Step over possible lds.l @r15+,macl. */
03131d99
CV		 2712 if (IS_MACL_LDS (inst))
2713 {
2714 addr -= 2;
e17a4113 2715 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
03131d99
CV		 2716 }
2717
c378eb4e 2718 /* Step over possible lds.l @r15+,pr. */
1c0159e0 2719 if (IS_LDS (inst))
617daa0e 2720 {
1c0159e0 2721 addr -= 2;
e17a4113 2722 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
1c0159e0
CV		 2723 }
2724
c378eb4e 2725 /* Step over possible mov r14,r15. */
1c0159e0 2726 if (IS_MOV_FP_SP (inst))
617daa0e 2727 {
1c0159e0 2728 addr -= 2;
e17a4113 2729 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
1c0159e0
CV		 2730 }
2731
2732 /* Now check for FP adjustments, using add #imm,r14 or add rX, r14
c378eb4e 2733 instructions. */
1c0159e0 2734 while (addr > func_addr + 4
617daa0e 2735 && (IS_ADD_REG_TO_FP (inst) || IS_ADD_IMM_FP (inst)))
1c0159e0
CV		 2736 {
2737 addr -= 2;
e17a4113 2738 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
1c0159e0
CV		 2739 }
2740
03131d99
CV		 2741 /* On SH2a check if the previous instruction was perhaps a MOVI20.
2742 That's allowed for the epilogue. */
2743 if ((gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a
2744 || gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a_nofpu)
2745 && addr > func_addr + 6
e17a4113
UW		 2746 && IS_MOVI20 (read_memory_unsigned_integer (addr - 4, 2,
2747 byte_order)))
03131d99
CV		 2748 addr -= 4;
2749
1c0159e0
CV		 2750 if (pc >= addr)
2751 return 1;
2752 }
2753 return 0;
2754}
c9ac0a72
AS		 2755
2756
2757/* Supply register REGNUM from the buffer specified by REGS and LEN
2758 in the register set REGSET to register cache REGCACHE.
2759 REGTABLE specifies where each register can be found in REGS.
2760 If REGNUM is -1, do this for all registers in REGSET. */
2761
2762void
2763sh_corefile_supply_regset (const struct regset *regset,
2764 struct regcache *regcache,
2765 int regnum, const void *regs, size_t len)
2766{
2767 struct gdbarch *gdbarch = get_regcache_arch (regcache);
2768 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2769 const struct sh_corefile_regmap *regmap = (regset == &sh_corefile_gregset
2770 ? tdep->core_gregmap
2771 : tdep->core_fpregmap);
2772 int i;
2773
2774 for (i = 0; regmap[i].regnum != -1; i++)
2775 {
2776 if ((regnum == -1 || regnum == regmap[i].regnum)
2777 && regmap[i].offset + 4 <= len)
2778 regcache_raw_supply (regcache, regmap[i].regnum,
2779 (char *)regs + regmap[i].offset);
2780 }
2781}
2782
2783/* Collect register REGNUM in the register set REGSET from register cache
2784 REGCACHE into the buffer specified by REGS and LEN.
2785 REGTABLE specifies where each register can be found in REGS.
2786 If REGNUM is -1, do this for all registers in REGSET. */
2787
2788void
2789sh_corefile_collect_regset (const struct regset *regset,
2790 const struct regcache *regcache,
2791 int regnum, void *regs, size_t len)
2792{
2793 struct gdbarch *gdbarch = get_regcache_arch (regcache);
2794 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2795 const struct sh_corefile_regmap *regmap = (regset == &sh_corefile_gregset
2796 ? tdep->core_gregmap
2797 : tdep->core_fpregmap);
2798 int i;
2799
2800 for (i = 0; regmap[i].regnum != -1; i++)
2801 {
2802 if ((regnum == -1 || regnum == regmap[i].regnum)
2803 && regmap[i].offset + 4 <= len)
2804 regcache_raw_collect (regcache, regmap[i].regnum,
2805 (char *)regs + regmap[i].offset);
2806 }
2807}
2808
2809/* The following two regsets have the same contents, so it is tempting to
2810 unify them, but they are distiguished by their address, so don't. */
2811
2812struct regset sh_corefile_gregset =
2813{
2814 NULL,
2815 sh_corefile_supply_regset,
2816 sh_corefile_collect_regset
2817};
2818
2819static struct regset sh_corefile_fpregset =
2820{
2821 NULL,
2822 sh_corefile_supply_regset,
2823 sh_corefile_collect_regset
2824};
2825
2826static const struct regset *
2827sh_regset_from_core_section (struct gdbarch *gdbarch, const char *sect_name,
2828 size_t sect_size)
2829{
2830 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2831
2832 if (tdep->core_gregmap && strcmp (sect_name, ".reg") == 0)
2833 return &sh_corefile_gregset;
2834
2835 if (tdep->core_fpregmap && strcmp (sect_name, ".reg2") == 0)
2836 return &sh_corefile_fpregset;
2837
2838 return NULL;
2839}
ccf00f21 2840\f
cc17453a
EZ		 2841
2842static struct gdbarch *
fba45db2 2843sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
cc17453a 2844{
cc17453a 2845 struct gdbarch *gdbarch;
c9ac0a72 2846 struct gdbarch_tdep *tdep;
d658f924 2847
55ff77ac
CV		 2848 sh_show_regs = sh_generic_show_regs;
2849 switch (info.bfd_arch_info->mach)
2850 {
617daa0e
CV		 2851 case bfd_mach_sh2e:
2852 sh_show_regs = sh2e_show_regs;
2853 break;
da962468
CV		 2854 case bfd_mach_sh2a:
2855 sh_show_regs = sh2a_show_regs;
2856 break;
2857 case bfd_mach_sh2a_nofpu:
2858 sh_show_regs = sh2a_nofpu_show_regs;
2859 break;
617daa0e
CV		 2860 case bfd_mach_sh_dsp:
2861 sh_show_regs = sh_dsp_show_regs;
2862 break;
55ff77ac 2863
617daa0e 2864 case bfd_mach_sh3:
46e8a76b
AS		 2865 case bfd_mach_sh3_nommu:
2866 case bfd_mach_sh2a_nofpu_or_sh3_nommu:
617daa0e
CV		 2867 sh_show_regs = sh3_show_regs;
2868 break;
55ff77ac 2869
617daa0e 2870 case bfd_mach_sh3e:
46e8a76b 2871 case bfd_mach_sh2a_or_sh3e:
617daa0e
CV		 2872 sh_show_regs = sh3e_show_regs;
2873 break;
55ff77ac 2874
617daa0e 2875 case bfd_mach_sh3_dsp:
474e5826 2876 case bfd_mach_sh4al_dsp:
617daa0e
CV		 2877 sh_show_regs = sh3_dsp_show_regs;
2878 break;
55ff77ac 2879
617daa0e 2880 case bfd_mach_sh4:
474e5826 2881 case bfd_mach_sh4a:
46e8a76b 2882 case bfd_mach_sh2a_or_sh4:
617daa0e
CV		 2883 sh_show_regs = sh4_show_regs;
2884 break;
55ff77ac 2885
474e5826 2886 case bfd_mach_sh4_nofpu:
46e8a76b 2887 case bfd_mach_sh4_nommu_nofpu:
474e5826 2888 case bfd_mach_sh4a_nofpu:
46e8a76b 2889 case bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu:
474e5826
CV		 2890 sh_show_regs = sh4_nofpu_show_regs;
2891 break;
2892
617daa0e
CV		 2893 case bfd_mach_sh5:
2894 sh_show_regs = sh64_show_regs;
c378eb4e 2895 /* SH5 is handled entirely in sh64-tdep.c. */
617daa0e 2896 return sh64_gdbarch_init (info, arches);
55ff77ac
CV		 2897 }
2898
4be87837
DJ		 2899 /* If there is already a candidate, use it. */
2900 arches = gdbarch_list_lookup_by_info (arches, &info);
2901 if (arches != NULL)
2902 return arches->gdbarch;
cc17453a
EZ		 2903
2904 /* None found, create a new architecture from the information
c378eb4e 2905 provided. */
c9ac0a72
AS		 2906 tdep = XZALLOC (struct gdbarch_tdep);
2907 gdbarch = gdbarch_alloc (&info, tdep);
cc17453a 2908
48db5a3c
CV		 2909 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2910 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
ec920329 2911 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
48db5a3c
CV		 2912 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2913 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2914 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2915 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
a38d2a54 2916 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
48db5a3c 2917
f2ea0907 2918 set_gdbarch_num_regs (gdbarch, SH_NUM_REGS);
a38d2a54 2919 set_gdbarch_sp_regnum (gdbarch, 15);
a38d2a54 2920 set_gdbarch_pc_regnum (gdbarch, 16);
48db5a3c
CV		 2921 set_gdbarch_fp0_regnum (gdbarch, -1);
2922 set_gdbarch_num_pseudo_regs (gdbarch, 0);
2923
1c0159e0 2924 set_gdbarch_register_type (gdbarch, sh_default_register_type);
dda63807 2925 set_gdbarch_register_reggroup_p (gdbarch, sh_register_reggroup_p);
1c0159e0 2926
eaf90c5d 2927 set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc);
48db5a3c 2928
9dae60cc 2929 set_gdbarch_print_insn (gdbarch, print_insn_sh);
2f14585c 2930 set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);
48db5a3c 2931
c0409442 2932 set_gdbarch_return_value (gdbarch, sh_return_value_nofpu);
1c0159e0 2933
48db5a3c
CV		 2934 set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
2935 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
48db5a3c 2936
1c0159e0
CV		 2937 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu);
2938
48db5a3c
CV		 2939 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2940
19f59343 2941 set_gdbarch_frame_align (gdbarch, sh_frame_align);
1c0159e0
CV		 2942 set_gdbarch_unwind_sp (gdbarch, sh_unwind_sp);
2943 set_gdbarch_unwind_pc (gdbarch, sh_unwind_pc);
94afd7a6 2944 set_gdbarch_dummy_id (gdbarch, sh_dummy_id);
1c0159e0
CV		 2945 frame_base_set_default (gdbarch, &sh_frame_base);
2946
617daa0e 2947 set_gdbarch_in_function_epilogue_p (gdbarch, sh_in_function_epilogue_p);
cc17453a 2948
357d3800
AS		 2949 dwarf2_frame_set_init_reg (gdbarch, sh_dwarf2_frame_init_reg);
2950
c9ac0a72
AS		 2951 set_gdbarch_regset_from_core_section (gdbarch, sh_regset_from_core_section);
2952
cc17453a 2953 switch (info.bfd_arch_info->mach)
8db62801 2954 {
cc17453a 2955 case bfd_mach_sh:
48db5a3c 2956 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
cc17453a 2957 break;
1c0159e0 2958
cc17453a 2959 case bfd_mach_sh2:
48db5a3c 2960 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
617daa0e 2961 break;
1c0159e0 2962
2d188dd3 2963 case bfd_mach_sh2e:
c378eb4e 2964 /* doubles on sh2e and sh3e are actually 4 byte. */
48db5a3c
CV		 2965 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2966
2967 set_gdbarch_register_name (gdbarch, sh_sh2e_register_name);
48db5a3c 2968 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
2d188dd3 2969 set_gdbarch_fp0_regnum (gdbarch, 25);
c0409442 2970 set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
6df2bf50 2971 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2d188dd3 2972 break;
1c0159e0 2973
da962468
CV		 2974 case bfd_mach_sh2a:
2975 set_gdbarch_register_name (gdbarch, sh_sh2a_register_name);
2976 set_gdbarch_register_type (gdbarch, sh_sh2a_register_type);
2977 set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno);
2978
2979 set_gdbarch_fp0_regnum (gdbarch, 25);
2980 set_gdbarch_num_pseudo_regs (gdbarch, 9);
2981 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
2982 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
c0409442 2983 set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
da962468
CV		 2984 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2985 break;
2986
2987 case bfd_mach_sh2a_nofpu:
2988 set_gdbarch_register_name (gdbarch, sh_sh2a_nofpu_register_name);
2989 set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno);
2990
2991 set_gdbarch_num_pseudo_regs (gdbarch, 1);
2992 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
2993 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
2994 break;
2995
cc17453a 2996 case bfd_mach_sh_dsp:
48db5a3c 2997 set_gdbarch_register_name (gdbarch, sh_sh_dsp_register_name);
2f14585c 2998 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
cc17453a 2999 break;
1c0159e0 3000
cc17453a 3001 case bfd_mach_sh3:
4e6cbc38
AS		 3002 case bfd_mach_sh3_nommu:
3003 case bfd_mach_sh2a_nofpu_or_sh3_nommu:
48db5a3c 3004 set_gdbarch_register_name (gdbarch, sh_sh3_register_name);
cc17453a 3005 break;
1c0159e0 3006
cc17453a 3007 case bfd_mach_sh3e:
4e6cbc38 3008 case bfd_mach_sh2a_or_sh3e:
c378eb4e 3009 /* doubles on sh2e and sh3e are actually 4 byte. */
48db5a3c
CV		 3010 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
3011
3012 set_gdbarch_register_name (gdbarch, sh_sh3e_register_name);
48db5a3c 3013 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
cc17453a 3014 set_gdbarch_fp0_regnum (gdbarch, 25);
c0409442 3015 set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
6df2bf50 3016 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
cc17453a 3017 break;
1c0159e0 3018
cc17453a 3019 case bfd_mach_sh3_dsp:
48db5a3c 3020 set_gdbarch_register_name (gdbarch, sh_sh3_dsp_register_name);
48db5a3c 3021 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
cc17453a 3022 break;
1c0159e0 3023
cc17453a 3024 case bfd_mach_sh4:
474e5826 3025 case bfd_mach_sh4a:
46e8a76b 3026 case bfd_mach_sh2a_or_sh4:
48db5a3c 3027 set_gdbarch_register_name (gdbarch, sh_sh4_register_name);
48db5a3c 3028 set_gdbarch_register_type (gdbarch, sh_sh4_register_type);
cc17453a 3029 set_gdbarch_fp0_regnum (gdbarch, 25);
da962468 3030 set_gdbarch_num_pseudo_regs (gdbarch, 13);
d8124050
AC		 3031 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
3032 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
c0409442 3033 set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
6df2bf50 3034 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
cc17453a 3035 break;
1c0159e0 3036
474e5826
CV		 3037 case bfd_mach_sh4_nofpu:
3038 case bfd_mach_sh4a_nofpu:
4e6cbc38
AS		 3039 case bfd_mach_sh4_nommu_nofpu:
3040 case bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu:
474e5826
CV		 3041 set_gdbarch_register_name (gdbarch, sh_sh4_nofpu_register_name);
3042 break;
3043
3044 case bfd_mach_sh4al_dsp:
3045 set_gdbarch_register_name (gdbarch, sh_sh4al_dsp_register_name);
3046 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
3047 break;
3048
cc17453a 3049 default:
b58cbbf2 3050 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
cc17453a 3051 break;
8db62801 3052 }
cc17453a 3053
4be87837
DJ		 3054 /* Hook in ABI-specific overrides, if they have been registered. */
3055 gdbarch_init_osabi (info, gdbarch);
d658f924 3056
94afd7a6
UW		 3057 dwarf2_append_unwinders (gdbarch);
3058 frame_unwind_append_unwinder (gdbarch, &sh_frame_unwind);
1c0159e0 3059
cc17453a 3060 return gdbarch;
8db62801
EZ		 3061}
3062
c055b101
CV		 3063static void
3064show_sh_command (char *args, int from_tty)
3065{
3066 help_list (showshcmdlist, "show sh ", all_commands, gdb_stdout);
3067}
3068
3069static void
3070set_sh_command (char *args, int from_tty)
3071{
3072 printf_unfiltered
3073 ("\"set sh\" must be followed by an appropriate subcommand.\n");
3074 help_list (setshcmdlist, "set sh ", all_commands, gdb_stdout);
3075}
3076
c378eb4e 3077extern initialize_file_ftype _initialize_sh_tdep; /* -Wmissing-prototypes */
a78f21af 3078
c906108c 3079void
fba45db2 3080_initialize_sh_tdep (void)
c906108c
SS		 3081{
3082 struct cmd_list_element *c;
617daa0e 3083
f2ea0907 3084 gdbarch_register (bfd_arch_sh, sh_gdbarch_init, NULL);
c906108c 3085
1bedd215 3086 add_com ("regs", class_vars, sh_show_regs_command, _("Print all registers"));
c055b101
CV		 3087
3088 add_prefix_cmd ("sh", no_class, set_sh_command, "SH specific commands.",
3089 &setshcmdlist, "set sh ", 0, &setlist);
3090 add_prefix_cmd ("sh", no_class, show_sh_command, "SH specific commands.",
3091 &showshcmdlist, "show sh ", 0, &showlist);
3092
3093 add_setshow_enum_cmd ("calling-convention", class_vars, sh_cc_enum,
3094 &sh_active_calling_convention,
3095 _("Set calling convention used when calling target "
3096 "functions from GDB."),
3097 _("Show calling convention used when calling target "
3098 "functions from GDB."),
3099 _("gcc - Use GCC calling convention (default).\n"
3100 "renesas - Enforce Renesas calling convention."),
3101 NULL, NULL,
3102 &setshcmdlist, &showshcmdlist);
c906108c 3103}
GDB Binutils - Deliverables
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