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85a453d5 | 1 | /* Target-dependent code for Renesas Super-H, for GDB. |
cf5b2f1b AC |
2 | |
3 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, | |
0fd88904 | 4 | 2002, 2003, 2004, 2005 Free Software Foundation, Inc. |
55ff77ac CV |
5 | |
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program; if not, write to the Free Software | |
20 | Foundation, Inc., 59 Temple Place - Suite 330, | |
21 | Boston, MA 02111-1307, USA. */ | |
22 | ||
23 | /* | |
24 | Contributed by Steve Chamberlain | |
25 | sac@cygnus.com | |
26 | */ | |
27 | ||
28 | #include "defs.h" | |
29 | #include "frame.h" | |
c30dc700 CV |
30 | #include "frame-base.h" |
31 | #include "frame-unwind.h" | |
32 | #include "dwarf2-frame.h" | |
55ff77ac | 33 | #include "symtab.h" |
55ff77ac CV |
34 | #include "gdbtypes.h" |
35 | #include "gdbcmd.h" | |
36 | #include "gdbcore.h" | |
37 | #include "value.h" | |
38 | #include "dis-asm.h" | |
39 | #include "inferior.h" | |
40 | #include "gdb_string.h" | |
c30dc700 | 41 | #include "gdb_assert.h" |
55ff77ac | 42 | #include "arch-utils.h" |
55ff77ac | 43 | #include "regcache.h" |
55ff77ac CV |
44 | #include "osabi.h" |
45 | ||
46 | #include "elf-bfd.h" | |
55ff77ac CV |
47 | |
48 | /* sh flags */ | |
49 | #include "elf/sh.h" | |
50 | /* registers numbers shared with the simulator */ | |
51 | #include "gdb/sim-sh.h" | |
52 | ||
7bb11558 | 53 | /* Information that is dependent on the processor variant. */ |
55ff77ac CV |
54 | enum sh_abi |
55 | { | |
56 | SH_ABI_UNKNOWN, | |
57 | SH_ABI_32, | |
58 | SH_ABI_64 | |
59 | }; | |
60 | ||
61 | struct gdbarch_tdep | |
62 | { | |
63 | enum sh_abi sh_abi; | |
64 | }; | |
65 | ||
c30dc700 CV |
66 | struct sh64_frame_cache |
67 | { | |
68 | /* Base address. */ | |
69 | CORE_ADDR base; | |
70 | LONGEST sp_offset; | |
71 | CORE_ADDR pc; | |
72 | ||
73 | /* Flag showing that a frame has been created in the prologue code. */ | |
74 | int uses_fp; | |
75 | ||
76 | int media_mode; | |
77 | ||
78 | /* Saved registers. */ | |
79 | CORE_ADDR saved_regs[SIM_SH64_NR_REGS]; | |
80 | CORE_ADDR saved_sp; | |
81 | }; | |
82 | ||
55ff77ac CV |
83 | /* Registers of SH5 */ |
84 | enum | |
85 | { | |
86 | R0_REGNUM = 0, | |
87 | DEFAULT_RETURN_REGNUM = 2, | |
88 | STRUCT_RETURN_REGNUM = 2, | |
89 | ARG0_REGNUM = 2, | |
90 | ARGLAST_REGNUM = 9, | |
91 | FLOAT_ARGLAST_REGNUM = 11, | |
c30dc700 | 92 | MEDIA_FP_REGNUM = 14, |
55ff77ac CV |
93 | PR_REGNUM = 18, |
94 | SR_REGNUM = 65, | |
95 | DR0_REGNUM = 141, | |
96 | DR_LAST_REGNUM = 172, | |
97 | /* FPP stands for Floating Point Pair, to avoid confusion with | |
98 | GDB's FP0_REGNUM, which is the number of the first Floating | |
99 | point register. Unfortunately on the sh5, the floating point | |
7bb11558 | 100 | registers are called FR, and the floating point pairs are called FP. */ |
55ff77ac CV |
101 | FPP0_REGNUM = 173, |
102 | FPP_LAST_REGNUM = 204, | |
103 | FV0_REGNUM = 205, | |
104 | FV_LAST_REGNUM = 220, | |
105 | R0_C_REGNUM = 221, | |
106 | R_LAST_C_REGNUM = 236, | |
107 | PC_C_REGNUM = 237, | |
108 | GBR_C_REGNUM = 238, | |
109 | MACH_C_REGNUM = 239, | |
110 | MACL_C_REGNUM = 240, | |
111 | PR_C_REGNUM = 241, | |
112 | T_C_REGNUM = 242, | |
113 | FPSCR_C_REGNUM = 243, | |
114 | FPUL_C_REGNUM = 244, | |
115 | FP0_C_REGNUM = 245, | |
116 | FP_LAST_C_REGNUM = 260, | |
117 | DR0_C_REGNUM = 261, | |
118 | DR_LAST_C_REGNUM = 268, | |
119 | FV0_C_REGNUM = 269, | |
120 | FV_LAST_C_REGNUM = 272, | |
121 | FPSCR_REGNUM = SIM_SH64_FPCSR_REGNUM, | |
122 | SSR_REGNUM = SIM_SH64_SSR_REGNUM, | |
123 | SPC_REGNUM = SIM_SH64_SPC_REGNUM, | |
124 | TR7_REGNUM = SIM_SH64_TR0_REGNUM + 7, | |
125 | FP_LAST_REGNUM = SIM_SH64_FR0_REGNUM + SIM_SH64_NR_FP_REGS - 1 | |
126 | }; | |
127 | ||
55ff77ac | 128 | static const char * |
39add00a | 129 | sh64_register_name (int reg_nr) |
55ff77ac CV |
130 | { |
131 | static char *register_names[] = | |
132 | { | |
133 | /* SH MEDIA MODE (ISA 32) */ | |
134 | /* general registers (64-bit) 0-63 */ | |
135 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
136 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
137 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
138 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", | |
139 | "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", | |
140 | "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", | |
141 | "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", | |
142 | "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", | |
143 | ||
144 | /* pc (64-bit) 64 */ | |
145 | "pc", | |
146 | ||
147 | /* status reg., saved status reg., saved pc reg. (64-bit) 65-67 */ | |
148 | "sr", "ssr", "spc", | |
149 | ||
150 | /* target registers (64-bit) 68-75*/ | |
151 | "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", | |
152 | ||
153 | /* floating point state control register (32-bit) 76 */ | |
154 | "fpscr", | |
155 | ||
156 | /* single precision floating point registers (32-bit) 77-140*/ | |
157 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", | |
158 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
159 | "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", | |
160 | "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", | |
161 | "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", | |
162 | "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", | |
163 | "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", | |
164 | "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", | |
165 | ||
166 | /* double precision registers (pseudo) 141-172 */ | |
167 | "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", | |
168 | "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", | |
169 | "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", | |
170 | "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62", | |
171 | ||
172 | /* floating point pairs (pseudo) 173-204*/ | |
173 | "fp0", "fp2", "fp4", "fp6", "fp8", "fp10", "fp12", "fp14", | |
174 | "fp16", "fp18", "fp20", "fp22", "fp24", "fp26", "fp28", "fp30", | |
175 | "fp32", "fp34", "fp36", "fp38", "fp40", "fp42", "fp44", "fp46", | |
176 | "fp48", "fp50", "fp52", "fp54", "fp56", "fp58", "fp60", "fp62", | |
177 | ||
178 | /* floating point vectors (4 floating point regs) (pseudo) 205-220*/ | |
179 | "fv0", "fv4", "fv8", "fv12", "fv16", "fv20", "fv24", "fv28", | |
180 | "fv32", "fv36", "fv40", "fv44", "fv48", "fv52", "fv56", "fv60", | |
181 | ||
182 | /* SH COMPACT MODE (ISA 16) (all pseudo) 221-272*/ | |
183 | "r0_c", "r1_c", "r2_c", "r3_c", "r4_c", "r5_c", "r6_c", "r7_c", | |
184 | "r8_c", "r9_c", "r10_c", "r11_c", "r12_c", "r13_c", "r14_c", "r15_c", | |
185 | "pc_c", | |
186 | "gbr_c", "mach_c", "macl_c", "pr_c", "t_c", | |
187 | "fpscr_c", "fpul_c", | |
188 | "fr0_c", "fr1_c", "fr2_c", "fr3_c", "fr4_c", "fr5_c", "fr6_c", "fr7_c", | |
189 | "fr8_c", "fr9_c", "fr10_c", "fr11_c", "fr12_c", "fr13_c", "fr14_c", "fr15_c", | |
190 | "dr0_c", "dr2_c", "dr4_c", "dr6_c", "dr8_c", "dr10_c", "dr12_c", "dr14_c", | |
191 | "fv0_c", "fv4_c", "fv8_c", "fv12_c", | |
192 | /* FIXME!!!! XF0 XF15, XD0 XD14 ?????*/ | |
193 | }; | |
194 | ||
195 | if (reg_nr < 0) | |
196 | return NULL; | |
197 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
198 | return NULL; | |
199 | return register_names[reg_nr]; | |
200 | } | |
201 | ||
202 | #define NUM_PSEUDO_REGS_SH_MEDIA 80 | |
203 | #define NUM_PSEUDO_REGS_SH_COMPACT 51 | |
204 | ||
205 | /* Macros and functions for setting and testing a bit in a minimal | |
206 | symbol that marks it as 32-bit function. The MSB of the minimal | |
f594e5e9 | 207 | symbol's "info" field is used for this purpose. |
55ff77ac CV |
208 | |
209 | ELF_MAKE_MSYMBOL_SPECIAL | |
210 | tests whether an ELF symbol is "special", i.e. refers | |
211 | to a 32-bit function, and sets a "special" bit in a | |
212 | minimal symbol to mark it as a 32-bit function | |
f594e5e9 | 213 | MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */ |
55ff77ac CV |
214 | |
215 | #define MSYMBOL_IS_SPECIAL(msym) \ | |
216 | (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0) | |
217 | ||
218 | static void | |
219 | sh64_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym) | |
220 | { | |
221 | if (msym == NULL) | |
222 | return; | |
223 | ||
224 | if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_SH5_ISA32) | |
225 | { | |
226 | MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) | 0x80000000); | |
227 | SYMBOL_VALUE_ADDRESS (msym) |= 1; | |
228 | } | |
229 | } | |
230 | ||
231 | /* ISA32 (shmedia) function addresses are odd (bit 0 is set). Here | |
232 | are some macros to test, set, or clear bit 0 of addresses. */ | |
233 | #define IS_ISA32_ADDR(addr) ((addr) & 1) | |
234 | #define MAKE_ISA32_ADDR(addr) ((addr) | 1) | |
235 | #define UNMAKE_ISA32_ADDR(addr) ((addr) & ~1) | |
236 | ||
237 | static int | |
238 | pc_is_isa32 (bfd_vma memaddr) | |
239 | { | |
240 | struct minimal_symbol *sym; | |
241 | ||
242 | /* If bit 0 of the address is set, assume this is a | |
7bb11558 | 243 | ISA32 (shmedia) address. */ |
55ff77ac CV |
244 | if (IS_ISA32_ADDR (memaddr)) |
245 | return 1; | |
246 | ||
247 | /* A flag indicating that this is a ISA32 function is stored by elfread.c in | |
248 | the high bit of the info field. Use this to decide if the function is | |
249 | ISA16 or ISA32. */ | |
250 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
251 | if (sym) | |
252 | return MSYMBOL_IS_SPECIAL (sym); | |
253 | else | |
254 | return 0; | |
255 | } | |
256 | ||
257 | static const unsigned char * | |
39add00a | 258 | sh64_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
55ff77ac CV |
259 | { |
260 | /* The BRK instruction for shmedia is | |
261 | 01101111 11110101 11111111 11110000 | |
262 | which translates in big endian mode to 0x6f, 0xf5, 0xff, 0xf0 | |
263 | and in little endian mode to 0xf0, 0xff, 0xf5, 0x6f */ | |
264 | ||
265 | /* The BRK instruction for shcompact is | |
266 | 00000000 00111011 | |
267 | which translates in big endian mode to 0x0, 0x3b | |
268 | and in little endian mode to 0x3b, 0x0*/ | |
269 | ||
270 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
271 | { | |
272 | if (pc_is_isa32 (*pcptr)) | |
273 | { | |
274 | static unsigned char big_breakpoint_media[] = {0x6f, 0xf5, 0xff, 0xf0}; | |
275 | *pcptr = UNMAKE_ISA32_ADDR (*pcptr); | |
276 | *lenptr = sizeof (big_breakpoint_media); | |
277 | return big_breakpoint_media; | |
278 | } | |
279 | else | |
280 | { | |
281 | static unsigned char big_breakpoint_compact[] = {0x0, 0x3b}; | |
282 | *lenptr = sizeof (big_breakpoint_compact); | |
283 | return big_breakpoint_compact; | |
284 | } | |
285 | } | |
286 | else | |
287 | { | |
288 | if (pc_is_isa32 (*pcptr)) | |
289 | { | |
290 | static unsigned char little_breakpoint_media[] = {0xf0, 0xff, 0xf5, 0x6f}; | |
291 | *pcptr = UNMAKE_ISA32_ADDR (*pcptr); | |
292 | *lenptr = sizeof (little_breakpoint_media); | |
293 | return little_breakpoint_media; | |
294 | } | |
295 | else | |
296 | { | |
297 | static unsigned char little_breakpoint_compact[] = {0x3b, 0x0}; | |
298 | *lenptr = sizeof (little_breakpoint_compact); | |
299 | return little_breakpoint_compact; | |
300 | } | |
301 | } | |
302 | } | |
303 | ||
304 | /* Prologue looks like | |
305 | [mov.l <regs>,@-r15]... | |
306 | [sts.l pr,@-r15] | |
307 | [mov.l r14,@-r15] | |
308 | [mov r15,r14] | |
309 | ||
310 | Actually it can be more complicated than this. For instance, with | |
311 | newer gcc's: | |
312 | ||
313 | mov.l r14,@-r15 | |
314 | add #-12,r15 | |
315 | mov r15,r14 | |
316 | mov r4,r1 | |
317 | mov r5,r2 | |
318 | mov.l r6,@(4,r14) | |
319 | mov.l r7,@(8,r14) | |
320 | mov.b r1,@r14 | |
321 | mov r14,r1 | |
322 | mov r14,r1 | |
323 | add #2,r1 | |
324 | mov.w r2,@r1 | |
325 | ||
326 | */ | |
327 | ||
328 | /* PTABS/L Rn, TRa 0110101111110001nnnnnnl00aaa0000 | |
329 | with l=1 and n = 18 0110101111110001010010100aaa0000 */ | |
330 | #define IS_PTABSL_R18(x) (((x) & 0xffffff8f) == 0x6bf14a00) | |
331 | ||
332 | /* STS.L PR,@-r0 0100000000100010 | |
333 | r0-4-->r0, PR-->(r0) */ | |
334 | #define IS_STS_R0(x) ((x) == 0x4022) | |
335 | ||
336 | /* STS PR, Rm 0000mmmm00101010 | |
337 | PR-->Rm */ | |
338 | #define IS_STS_PR(x) (((x) & 0xf0ff) == 0x2a) | |
339 | ||
340 | /* MOV.L Rm,@(disp,r15) 00011111mmmmdddd | |
341 | Rm-->(dispx4+r15) */ | |
342 | #define IS_MOV_TO_R15(x) (((x) & 0xff00) == 0x1f00) | |
343 | ||
344 | /* MOV.L R14,@(disp,r15) 000111111110dddd | |
345 | R14-->(dispx4+r15) */ | |
346 | #define IS_MOV_R14(x) (((x) & 0xfff0) == 0x1fe0) | |
347 | ||
348 | /* ST.Q R14, disp, R18 101011001110dddddddddd0100100000 | |
349 | R18-->(dispx8+R14) */ | |
350 | #define IS_STQ_R18_R14(x) (((x) & 0xfff003ff) == 0xace00120) | |
351 | ||
352 | /* ST.Q R15, disp, R18 101011001111dddddddddd0100100000 | |
353 | R18-->(dispx8+R15) */ | |
354 | #define IS_STQ_R18_R15(x) (((x) & 0xfff003ff) == 0xacf00120) | |
355 | ||
356 | /* ST.L R15, disp, R18 101010001111dddddddddd0100100000 | |
357 | R18-->(dispx4+R15) */ | |
358 | #define IS_STL_R18_R15(x) (((x) & 0xfff003ff) == 0xa8f00120) | |
359 | ||
360 | /* ST.Q R15, disp, R14 1010 1100 1111 dddd dddd dd00 1110 0000 | |
361 | R14-->(dispx8+R15) */ | |
362 | #define IS_STQ_R14_R15(x) (((x) & 0xfff003ff) == 0xacf000e0) | |
363 | ||
364 | /* ST.L R15, disp, R14 1010 1000 1111 dddd dddd dd00 1110 0000 | |
365 | R14-->(dispx4+R15) */ | |
366 | #define IS_STL_R14_R15(x) (((x) & 0xfff003ff) == 0xa8f000e0) | |
367 | ||
368 | /* ADDI.L R15,imm,R15 1101 0100 1111 ssss ssss ss00 1111 0000 | |
369 | R15 + imm --> R15 */ | |
370 | #define IS_ADDIL_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd4f000f0) | |
371 | ||
372 | /* ADDI R15,imm,R15 1101 0000 1111 ssss ssss ss00 1111 0000 | |
373 | R15 + imm --> R15 */ | |
374 | #define IS_ADDI_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd0f000f0) | |
375 | ||
376 | /* ADD.L R15,R63,R14 0000 0000 1111 1000 1111 1100 1110 0000 | |
377 | R15 + R63 --> R14 */ | |
378 | #define IS_ADDL_SP_FP_MEDIA(x) ((x) == 0x00f8fce0) | |
379 | ||
380 | /* ADD R15,R63,R14 0000 0000 1111 1001 1111 1100 1110 0000 | |
381 | R15 + R63 --> R14 */ | |
382 | #define IS_ADD_SP_FP_MEDIA(x) ((x) == 0x00f9fce0) | |
383 | ||
384 | #define IS_MOV_SP_FP_MEDIA(x) (IS_ADDL_SP_FP_MEDIA(x) || IS_ADD_SP_FP_MEDIA(x)) | |
385 | ||
386 | /* MOV #imm, R0 1110 0000 ssss ssss | |
387 | #imm-->R0 */ | |
388 | #define IS_MOV_R0(x) (((x) & 0xff00) == 0xe000) | |
389 | ||
390 | /* MOV.L @(disp,PC), R0 1101 0000 iiii iiii */ | |
391 | #define IS_MOVL_R0(x) (((x) & 0xff00) == 0xd000) | |
392 | ||
393 | /* ADD r15,r0 0011 0000 1111 1100 | |
394 | r15+r0-->r0 */ | |
395 | #define IS_ADD_SP_R0(x) ((x) == 0x30fc) | |
396 | ||
397 | /* MOV.L R14 @-R0 0010 0000 1110 0110 | |
398 | R14-->(R0-4), R0-4-->R0 */ | |
399 | #define IS_MOV_R14_R0(x) ((x) == 0x20e6) | |
400 | ||
401 | /* ADD Rm,R63,Rn Rm+R63-->Rn 0000 00mm mmmm 1001 1111 11nn nnnn 0000 | |
7bb11558 | 402 | where Rm is one of r2-r9 which are the argument registers. */ |
55ff77ac CV |
403 | /* FIXME: Recognize the float and double register moves too! */ |
404 | #define IS_MEDIA_IND_ARG_MOV(x) \ | |
405 | ((((x) & 0xfc0ffc0f) == 0x0009fc00) && (((x) & 0x03f00000) >= 0x00200000 && ((x) & 0x03f00000) <= 0x00900000)) | |
406 | ||
407 | /* ST.Q Rn,0,Rm Rm-->Rn+0 1010 11nn nnnn 0000 0000 00mm mmmm 0000 | |
408 | or ST.L Rn,0,Rm Rm-->Rn+0 1010 10nn nnnn 0000 0000 00mm mmmm 0000 | |
7bb11558 | 409 | where Rm is one of r2-r9 which are the argument registers. */ |
55ff77ac CV |
410 | #define IS_MEDIA_ARG_MOV(x) \ |
411 | (((((x) & 0xfc0ffc0f) == 0xac000000) || (((x) & 0xfc0ffc0f) == 0xa8000000)) \ | |
412 | && (((x) & 0x000003f0) >= 0x00000020 && ((x) & 0x000003f0) <= 0x00000090)) | |
413 | ||
414 | /* ST.B R14,0,Rn Rn-->(R14+0) 1010 0000 1110 0000 0000 00nn nnnn 0000*/ | |
415 | /* ST.W R14,0,Rn Rn-->(R14+0) 1010 0100 1110 0000 0000 00nn nnnn 0000*/ | |
416 | /* ST.L R14,0,Rn Rn-->(R14+0) 1010 1000 1110 0000 0000 00nn nnnn 0000*/ | |
417 | /* FST.S R14,0,FRn Rn-->(R14+0) 1011 0100 1110 0000 0000 00nn nnnn 0000*/ | |
418 | /* FST.D R14,0,DRn Rn-->(R14+0) 1011 1100 1110 0000 0000 00nn nnnn 0000*/ | |
419 | #define IS_MEDIA_MOV_TO_R14(x) \ | |
420 | ((((x) & 0xfffffc0f) == 0xa0e00000) \ | |
421 | || (((x) & 0xfffffc0f) == 0xa4e00000) \ | |
422 | || (((x) & 0xfffffc0f) == 0xa8e00000) \ | |
423 | || (((x) & 0xfffffc0f) == 0xb4e00000) \ | |
424 | || (((x) & 0xfffffc0f) == 0xbce00000)) | |
425 | ||
426 | /* MOV Rm, Rn Rm-->Rn 0110 nnnn mmmm 0011 | |
427 | where Rm is r2-r9 */ | |
428 | #define IS_COMPACT_IND_ARG_MOV(x) \ | |
429 | ((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0020) && (((x) & 0x00f0) <= 0x0090)) | |
430 | ||
431 | /* compact direct arg move! | |
432 | MOV.L Rn, @r14 0010 1110 mmmm 0010 */ | |
433 | #define IS_COMPACT_ARG_MOV(x) \ | |
434 | (((((x) & 0xff0f) == 0x2e02) && (((x) & 0x00f0) >= 0x0020) && ((x) & 0x00f0) <= 0x0090)) | |
435 | ||
436 | /* MOV.B Rm, @R14 0010 1110 mmmm 0000 | |
437 | MOV.W Rm, @R14 0010 1110 mmmm 0001 */ | |
438 | #define IS_COMPACT_MOV_TO_R14(x) \ | |
439 | ((((x) & 0xff0f) == 0x2e00) || (((x) & 0xff0f) == 0x2e01)) | |
440 | ||
441 | #define IS_JSR_R0(x) ((x) == 0x400b) | |
442 | #define IS_NOP(x) ((x) == 0x0009) | |
443 | ||
444 | ||
445 | /* MOV r15,r14 0110111011110011 | |
446 | r15-->r14 */ | |
447 | #define IS_MOV_SP_FP(x) ((x) == 0x6ef3) | |
448 | ||
449 | /* ADD #imm,r15 01111111iiiiiiii | |
450 | r15+imm-->r15 */ | |
451 | #define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00) | |
452 | ||
453 | /* Skip any prologue before the guts of a function */ | |
454 | ||
7bb11558 MS |
455 | /* Skip the prologue using the debug information. If this fails we'll |
456 | fall back on the 'guess' method below. */ | |
55ff77ac CV |
457 | static CORE_ADDR |
458 | after_prologue (CORE_ADDR pc) | |
459 | { | |
460 | struct symtab_and_line sal; | |
461 | CORE_ADDR func_addr, func_end; | |
462 | ||
463 | /* If we can not find the symbol in the partial symbol table, then | |
464 | there is no hope we can determine the function's start address | |
465 | with this code. */ | |
466 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
467 | return 0; | |
468 | ||
c30dc700 | 469 | |
55ff77ac CV |
470 | /* Get the line associated with FUNC_ADDR. */ |
471 | sal = find_pc_line (func_addr, 0); | |
472 | ||
473 | /* There are only two cases to consider. First, the end of the source line | |
474 | is within the function bounds. In that case we return the end of the | |
475 | source line. Second is the end of the source line extends beyond the | |
476 | bounds of the current function. We need to use the slow code to | |
477 | examine instructions in that case. */ | |
478 | if (sal.end < func_end) | |
479 | return sal.end; | |
480 | else | |
481 | return 0; | |
482 | } | |
483 | ||
484 | static CORE_ADDR | |
485 | look_for_args_moves (CORE_ADDR start_pc, int media_mode) | |
486 | { | |
487 | CORE_ADDR here, end; | |
488 | int w; | |
489 | int insn_size = (media_mode ? 4 : 2); | |
490 | ||
491 | for (here = start_pc, end = start_pc + (insn_size * 28); here < end;) | |
492 | { | |
493 | if (media_mode) | |
494 | { | |
495 | w = read_memory_integer (UNMAKE_ISA32_ADDR (here), insn_size); | |
496 | here += insn_size; | |
497 | if (IS_MEDIA_IND_ARG_MOV (w)) | |
498 | { | |
499 | /* This must be followed by a store to r14, so the argument | |
500 | is where the debug info says it is. This can happen after | |
7bb11558 | 501 | the SP has been saved, unfortunately. */ |
55ff77ac CV |
502 | |
503 | int next_insn = read_memory_integer (UNMAKE_ISA32_ADDR (here), | |
504 | insn_size); | |
505 | here += insn_size; | |
506 | if (IS_MEDIA_MOV_TO_R14 (next_insn)) | |
507 | start_pc = here; | |
508 | } | |
509 | else if (IS_MEDIA_ARG_MOV (w)) | |
510 | { | |
7bb11558 | 511 | /* These instructions store directly the argument in r14. */ |
55ff77ac CV |
512 | start_pc = here; |
513 | } | |
514 | else | |
515 | break; | |
516 | } | |
517 | else | |
518 | { | |
519 | w = read_memory_integer (here, insn_size); | |
520 | w = w & 0xffff; | |
521 | here += insn_size; | |
522 | if (IS_COMPACT_IND_ARG_MOV (w)) | |
523 | { | |
524 | /* This must be followed by a store to r14, so the argument | |
525 | is where the debug info says it is. This can happen after | |
7bb11558 | 526 | the SP has been saved, unfortunately. */ |
55ff77ac CV |
527 | |
528 | int next_insn = 0xffff & read_memory_integer (here, insn_size); | |
529 | here += insn_size; | |
530 | if (IS_COMPACT_MOV_TO_R14 (next_insn)) | |
531 | start_pc = here; | |
532 | } | |
533 | else if (IS_COMPACT_ARG_MOV (w)) | |
534 | { | |
7bb11558 | 535 | /* These instructions store directly the argument in r14. */ |
55ff77ac CV |
536 | start_pc = here; |
537 | } | |
538 | else if (IS_MOVL_R0 (w)) | |
539 | { | |
540 | /* There is a function that gcc calls to get the arguments | |
541 | passed correctly to the function. Only after this | |
542 | function call the arguments will be found at the place | |
543 | where they are supposed to be. This happens in case the | |
544 | argument has to be stored into a 64-bit register (for | |
545 | instance doubles, long longs). SHcompact doesn't have | |
546 | access to the full 64-bits, so we store the register in | |
547 | stack slot and store the address of the stack slot in | |
548 | the register, then do a call through a wrapper that | |
549 | loads the memory value into the register. A SHcompact | |
550 | callee calls an argument decoder | |
551 | (GCC_shcompact_incoming_args) that stores the 64-bit | |
552 | value in a stack slot and stores the address of the | |
553 | stack slot in the register. GCC thinks the argument is | |
554 | just passed by transparent reference, but this is only | |
555 | true after the argument decoder is called. Such a call | |
7bb11558 | 556 | needs to be considered part of the prologue. */ |
55ff77ac CV |
557 | |
558 | /* This must be followed by a JSR @r0 instruction and by | |
559 | a NOP instruction. After these, the prologue is over! */ | |
560 | ||
561 | int next_insn = 0xffff & read_memory_integer (here, insn_size); | |
562 | here += insn_size; | |
563 | if (IS_JSR_R0 (next_insn)) | |
564 | { | |
565 | next_insn = 0xffff & read_memory_integer (here, insn_size); | |
566 | here += insn_size; | |
567 | ||
568 | if (IS_NOP (next_insn)) | |
569 | start_pc = here; | |
570 | } | |
571 | } | |
572 | else | |
573 | break; | |
574 | } | |
575 | } | |
576 | ||
577 | return start_pc; | |
578 | } | |
579 | ||
580 | static CORE_ADDR | |
581 | sh64_skip_prologue_hard_way (CORE_ADDR start_pc) | |
582 | { | |
583 | CORE_ADDR here, end; | |
584 | int updated_fp = 0; | |
585 | int insn_size = 4; | |
586 | int media_mode = 1; | |
587 | ||
588 | if (!start_pc) | |
589 | return 0; | |
590 | ||
591 | if (pc_is_isa32 (start_pc) == 0) | |
592 | { | |
593 | insn_size = 2; | |
594 | media_mode = 0; | |
595 | } | |
596 | ||
597 | for (here = start_pc, end = start_pc + (insn_size * 28); here < end;) | |
598 | { | |
599 | ||
600 | if (media_mode) | |
601 | { | |
602 | int w = read_memory_integer (UNMAKE_ISA32_ADDR (here), insn_size); | |
603 | here += insn_size; | |
604 | if (IS_STQ_R18_R14 (w) || IS_STQ_R18_R15 (w) || IS_STQ_R14_R15 (w) | |
605 | || IS_STL_R14_R15 (w) || IS_STL_R18_R15 (w) | |
606 | || IS_ADDIL_SP_MEDIA (w) || IS_ADDI_SP_MEDIA (w) || IS_PTABSL_R18 (w)) | |
607 | { | |
608 | start_pc = here; | |
609 | } | |
610 | else if (IS_MOV_SP_FP (w) || IS_MOV_SP_FP_MEDIA(w)) | |
611 | { | |
612 | start_pc = here; | |
613 | updated_fp = 1; | |
614 | } | |
615 | else | |
616 | if (updated_fp) | |
617 | { | |
618 | /* Don't bail out yet, we may have arguments stored in | |
619 | registers here, according to the debug info, so that | |
7bb11558 | 620 | gdb can print the frames correctly. */ |
55ff77ac CV |
621 | start_pc = look_for_args_moves (here - insn_size, media_mode); |
622 | break; | |
623 | } | |
624 | } | |
625 | else | |
626 | { | |
627 | int w = 0xffff & read_memory_integer (here, insn_size); | |
628 | here += insn_size; | |
629 | ||
630 | if (IS_STS_R0 (w) || IS_STS_PR (w) | |
631 | || IS_MOV_TO_R15 (w) || IS_MOV_R14 (w) | |
632 | || IS_MOV_R0 (w) || IS_ADD_SP_R0 (w) || IS_MOV_R14_R0 (w)) | |
633 | { | |
634 | start_pc = here; | |
635 | } | |
636 | else if (IS_MOV_SP_FP (w)) | |
637 | { | |
638 | start_pc = here; | |
639 | updated_fp = 1; | |
640 | } | |
641 | else | |
642 | if (updated_fp) | |
643 | { | |
644 | /* Don't bail out yet, we may have arguments stored in | |
645 | registers here, according to the debug info, so that | |
7bb11558 | 646 | gdb can print the frames correctly. */ |
55ff77ac CV |
647 | start_pc = look_for_args_moves (here - insn_size, media_mode); |
648 | break; | |
649 | } | |
650 | } | |
651 | } | |
652 | ||
653 | return start_pc; | |
654 | } | |
655 | ||
656 | static CORE_ADDR | |
c30dc700 | 657 | sh64_skip_prologue (CORE_ADDR pc) |
55ff77ac CV |
658 | { |
659 | CORE_ADDR post_prologue_pc; | |
660 | ||
661 | /* See if we can determine the end of the prologue via the symbol table. | |
662 | If so, then return either PC, or the PC after the prologue, whichever | |
663 | is greater. */ | |
664 | post_prologue_pc = after_prologue (pc); | |
665 | ||
666 | /* If after_prologue returned a useful address, then use it. Else | |
7bb11558 | 667 | fall back on the instruction skipping code. */ |
55ff77ac CV |
668 | if (post_prologue_pc != 0) |
669 | return max (pc, post_prologue_pc); | |
670 | else | |
671 | return sh64_skip_prologue_hard_way (pc); | |
672 | } | |
673 | ||
55ff77ac CV |
674 | /* Should call_function allocate stack space for a struct return? */ |
675 | static int | |
c30dc700 | 676 | sh64_use_struct_convention (struct type *type) |
55ff77ac CV |
677 | { |
678 | return (TYPE_LENGTH (type) > 8); | |
679 | } | |
680 | ||
55ff77ac CV |
681 | /* Disassemble an instruction. */ |
682 | static int | |
c30dc700 | 683 | gdb_print_insn_sh64 (bfd_vma memaddr, disassemble_info *info) |
55ff77ac CV |
684 | { |
685 | info->endian = TARGET_BYTE_ORDER; | |
686 | return print_insn_sh (memaddr, info); | |
687 | } | |
688 | ||
7bb11558 | 689 | /* For vectors of 4 floating point registers. */ |
55ff77ac | 690 | static int |
c30dc700 | 691 | sh64_fv_reg_base_num (int fv_regnum) |
55ff77ac CV |
692 | { |
693 | int fp_regnum; | |
694 | ||
695 | fp_regnum = FP0_REGNUM + | |
696 | (fv_regnum - FV0_REGNUM) * 4; | |
697 | return fp_regnum; | |
698 | } | |
699 | ||
700 | /* For double precision floating point registers, i.e 2 fp regs.*/ | |
701 | static int | |
c30dc700 | 702 | sh64_dr_reg_base_num (int dr_regnum) |
55ff77ac CV |
703 | { |
704 | int fp_regnum; | |
705 | ||
706 | fp_regnum = FP0_REGNUM + | |
707 | (dr_regnum - DR0_REGNUM) * 2; | |
708 | return fp_regnum; | |
709 | } | |
710 | ||
711 | /* For pairs of floating point registers */ | |
712 | static int | |
c30dc700 | 713 | sh64_fpp_reg_base_num (int fpp_regnum) |
55ff77ac CV |
714 | { |
715 | int fp_regnum; | |
716 | ||
717 | fp_regnum = FP0_REGNUM + | |
718 | (fpp_regnum - FPP0_REGNUM) * 2; | |
719 | return fp_regnum; | |
720 | } | |
721 | ||
55ff77ac CV |
722 | /* *INDENT-OFF* */ |
723 | /* | |
724 | SH COMPACT MODE (ISA 16) (all pseudo) 221-272 | |
725 | GDB_REGNUM BASE_REGNUM | |
726 | r0_c 221 0 | |
727 | r1_c 222 1 | |
728 | r2_c 223 2 | |
729 | r3_c 224 3 | |
730 | r4_c 225 4 | |
731 | r5_c 226 5 | |
732 | r6_c 227 6 | |
733 | r7_c 228 7 | |
734 | r8_c 229 8 | |
735 | r9_c 230 9 | |
736 | r10_c 231 10 | |
737 | r11_c 232 11 | |
738 | r12_c 233 12 | |
739 | r13_c 234 13 | |
740 | r14_c 235 14 | |
741 | r15_c 236 15 | |
742 | ||
743 | pc_c 237 64 | |
744 | gbr_c 238 16 | |
745 | mach_c 239 17 | |
746 | macl_c 240 17 | |
747 | pr_c 241 18 | |
748 | t_c 242 19 | |
749 | fpscr_c 243 76 | |
750 | fpul_c 244 109 | |
751 | ||
752 | fr0_c 245 77 | |
753 | fr1_c 246 78 | |
754 | fr2_c 247 79 | |
755 | fr3_c 248 80 | |
756 | fr4_c 249 81 | |
757 | fr5_c 250 82 | |
758 | fr6_c 251 83 | |
759 | fr7_c 252 84 | |
760 | fr8_c 253 85 | |
761 | fr9_c 254 86 | |
762 | fr10_c 255 87 | |
763 | fr11_c 256 88 | |
764 | fr12_c 257 89 | |
765 | fr13_c 258 90 | |
766 | fr14_c 259 91 | |
767 | fr15_c 260 92 | |
768 | ||
769 | dr0_c 261 77 | |
770 | dr2_c 262 79 | |
771 | dr4_c 263 81 | |
772 | dr6_c 264 83 | |
773 | dr8_c 265 85 | |
774 | dr10_c 266 87 | |
775 | dr12_c 267 89 | |
776 | dr14_c 268 91 | |
777 | ||
778 | fv0_c 269 77 | |
779 | fv4_c 270 81 | |
780 | fv8_c 271 85 | |
781 | fv12_c 272 91 | |
782 | */ | |
783 | /* *INDENT-ON* */ | |
784 | static int | |
785 | sh64_compact_reg_base_num (int reg_nr) | |
786 | { | |
c30dc700 | 787 | int base_regnum = reg_nr; |
55ff77ac CV |
788 | |
789 | /* general register N maps to general register N */ | |
790 | if (reg_nr >= R0_C_REGNUM | |
791 | && reg_nr <= R_LAST_C_REGNUM) | |
792 | base_regnum = reg_nr - R0_C_REGNUM; | |
793 | ||
794 | /* floating point register N maps to floating point register N */ | |
795 | else if (reg_nr >= FP0_C_REGNUM | |
796 | && reg_nr <= FP_LAST_C_REGNUM) | |
797 | base_regnum = reg_nr - FP0_C_REGNUM + FP0_REGNUM; | |
798 | ||
799 | /* double prec register N maps to base regnum for double prec register N */ | |
800 | else if (reg_nr >= DR0_C_REGNUM | |
801 | && reg_nr <= DR_LAST_C_REGNUM) | |
c30dc700 | 802 | base_regnum = sh64_dr_reg_base_num (DR0_REGNUM + reg_nr - DR0_C_REGNUM); |
55ff77ac CV |
803 | |
804 | /* vector N maps to base regnum for vector register N */ | |
805 | else if (reg_nr >= FV0_C_REGNUM | |
806 | && reg_nr <= FV_LAST_C_REGNUM) | |
c30dc700 | 807 | base_regnum = sh64_fv_reg_base_num (FV0_REGNUM + reg_nr - FV0_C_REGNUM); |
55ff77ac CV |
808 | |
809 | else if (reg_nr == PC_C_REGNUM) | |
810 | base_regnum = PC_REGNUM; | |
811 | ||
812 | else if (reg_nr == GBR_C_REGNUM) | |
813 | base_regnum = 16; | |
814 | ||
815 | else if (reg_nr == MACH_C_REGNUM | |
816 | || reg_nr == MACL_C_REGNUM) | |
817 | base_regnum = 17; | |
818 | ||
819 | else if (reg_nr == PR_C_REGNUM) | |
c30dc700 | 820 | base_regnum = PR_REGNUM; |
55ff77ac CV |
821 | |
822 | else if (reg_nr == T_C_REGNUM) | |
823 | base_regnum = 19; | |
824 | ||
825 | else if (reg_nr == FPSCR_C_REGNUM) | |
7bb11558 | 826 | base_regnum = FPSCR_REGNUM; /*???? this register is a mess. */ |
55ff77ac CV |
827 | |
828 | else if (reg_nr == FPUL_C_REGNUM) | |
829 | base_regnum = FP0_REGNUM + 32; | |
830 | ||
831 | return base_regnum; | |
832 | } | |
833 | ||
55ff77ac CV |
834 | static int |
835 | sign_extend (int value, int bits) | |
836 | { | |
837 | value = value & ((1 << bits) - 1); | |
838 | return (value & (1 << (bits - 1)) | |
839 | ? value | (~((1 << bits) - 1)) | |
840 | : value); | |
841 | } | |
842 | ||
843 | static void | |
c30dc700 CV |
844 | sh64_analyze_prologue (struct gdbarch *gdbarch, |
845 | struct sh64_frame_cache *cache, | |
846 | CORE_ADDR func_pc, | |
847 | CORE_ADDR current_pc) | |
55ff77ac | 848 | { |
c30dc700 | 849 | int reg_nr; |
55ff77ac CV |
850 | int pc; |
851 | int opc; | |
852 | int insn; | |
853 | int r0_val = 0; | |
55ff77ac CV |
854 | int insn_size; |
855 | int gdb_register_number; | |
856 | int register_number; | |
c30dc700 | 857 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
55ff77ac | 858 | |
c30dc700 | 859 | cache->sp_offset = 0; |
55ff77ac CV |
860 | |
861 | /* Loop around examining the prologue insns until we find something | |
862 | that does not appear to be part of the prologue. But give up | |
7bb11558 | 863 | after 20 of them, since we're getting silly then. */ |
55ff77ac | 864 | |
c30dc700 | 865 | pc = func_pc; |
55ff77ac | 866 | |
c30dc700 CV |
867 | if (cache->media_mode) |
868 | insn_size = 4; | |
55ff77ac | 869 | else |
c30dc700 | 870 | insn_size = 2; |
55ff77ac | 871 | |
c30dc700 CV |
872 | opc = pc + (insn_size * 28); |
873 | if (opc > current_pc) | |
874 | opc = current_pc; | |
875 | for ( ; pc <= opc; pc += insn_size) | |
55ff77ac | 876 | { |
c30dc700 CV |
877 | insn = read_memory_integer (cache->media_mode ? UNMAKE_ISA32_ADDR (pc) |
878 | : pc, | |
55ff77ac CV |
879 | insn_size); |
880 | ||
c30dc700 | 881 | if (!cache->media_mode) |
55ff77ac CV |
882 | { |
883 | if (IS_STS_PR (insn)) | |
884 | { | |
885 | int next_insn = read_memory_integer (pc + insn_size, insn_size); | |
886 | if (IS_MOV_TO_R15 (next_insn)) | |
887 | { | |
c30dc700 CV |
888 | cache->saved_regs[PR_REGNUM] = |
889 | cache->sp_offset - ((((next_insn & 0xf) ^ 0x8) - 0x8) << 2); | |
55ff77ac CV |
890 | pc += insn_size; |
891 | } | |
892 | } | |
c30dc700 | 893 | |
55ff77ac | 894 | else if (IS_MOV_R14 (insn)) |
c30dc700 CV |
895 | cache->saved_regs[MEDIA_FP_REGNUM] = |
896 | cache->sp_offset - ((((insn & 0xf) ^ 0x8) - 0x8) << 2); | |
55ff77ac CV |
897 | |
898 | else if (IS_MOV_R0 (insn)) | |
899 | { | |
900 | /* Put in R0 the offset from SP at which to store some | |
901 | registers. We are interested in this value, because it | |
902 | will tell us where the given registers are stored within | |
903 | the frame. */ | |
904 | r0_val = ((insn & 0xff) ^ 0x80) - 0x80; | |
905 | } | |
c30dc700 | 906 | |
55ff77ac CV |
907 | else if (IS_ADD_SP_R0 (insn)) |
908 | { | |
909 | /* This instruction still prepares r0, but we don't care. | |
7bb11558 | 910 | We already have the offset in r0_val. */ |
55ff77ac | 911 | } |
c30dc700 | 912 | |
55ff77ac CV |
913 | else if (IS_STS_R0 (insn)) |
914 | { | |
915 | /* Store PR at r0_val-4 from SP. Decrement r0 by 4*/ | |
c30dc700 | 916 | cache->saved_regs[PR_REGNUM] = cache->sp_offset - (r0_val - 4); |
55ff77ac | 917 | r0_val -= 4; |
55ff77ac | 918 | } |
c30dc700 | 919 | |
55ff77ac CV |
920 | else if (IS_MOV_R14_R0 (insn)) |
921 | { | |
922 | /* Store R14 at r0_val-4 from SP. Decrement r0 by 4 */ | |
c30dc700 CV |
923 | cache->saved_regs[MEDIA_FP_REGNUM] = cache->sp_offset |
924 | - (r0_val - 4); | |
55ff77ac CV |
925 | r0_val -= 4; |
926 | } | |
927 | ||
928 | else if (IS_ADD_SP (insn)) | |
c30dc700 CV |
929 | cache->sp_offset -= ((insn & 0xff) ^ 0x80) - 0x80; |
930 | ||
55ff77ac CV |
931 | else if (IS_MOV_SP_FP (insn)) |
932 | break; | |
933 | } | |
934 | else | |
935 | { | |
c30dc700 CV |
936 | if (IS_ADDIL_SP_MEDIA (insn) || IS_ADDI_SP_MEDIA (insn)) |
937 | cache->sp_offset -= | |
938 | sign_extend ((((insn & 0xffc00) ^ 0x80000) - 0x80000) >> 10, 9); | |
55ff77ac CV |
939 | |
940 | else if (IS_STQ_R18_R15 (insn)) | |
c30dc700 CV |
941 | cache->saved_regs[PR_REGNUM] = |
942 | cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10, 9) << 3); | |
55ff77ac CV |
943 | |
944 | else if (IS_STL_R18_R15 (insn)) | |
c30dc700 CV |
945 | cache->saved_regs[PR_REGNUM] = |
946 | cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10, 9) << 2); | |
55ff77ac CV |
947 | |
948 | else if (IS_STQ_R14_R15 (insn)) | |
c30dc700 CV |
949 | cache->saved_regs[MEDIA_FP_REGNUM] = |
950 | cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10, 9) << 3); | |
55ff77ac CV |
951 | |
952 | else if (IS_STL_R14_R15 (insn)) | |
c30dc700 CV |
953 | cache->saved_regs[MEDIA_FP_REGNUM] = |
954 | cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10, 9) << 2); | |
55ff77ac CV |
955 | |
956 | else if (IS_MOV_SP_FP_MEDIA (insn)) | |
957 | break; | |
958 | } | |
959 | } | |
960 | ||
c30dc700 CV |
961 | if (cache->saved_regs[MEDIA_FP_REGNUM] >= 0) |
962 | cache->uses_fp = 1; | |
55ff77ac CV |
963 | } |
964 | ||
965 | static CORE_ADDR | |
07be497a | 966 | sh64_extract_struct_value_address (struct regcache *regcache) |
55ff77ac | 967 | { |
07be497a AC |
968 | /* FIXME: cagney/2004-01-17: Does the ABI guarantee that the return |
969 | address regster is preserved across function calls? Probably | |
970 | not, making this function wrong. */ | |
971 | ULONGEST val; | |
972 | regcache_raw_read_unsigned (regcache, STRUCT_RETURN_REGNUM, &val); | |
973 | return val; | |
55ff77ac CV |
974 | } |
975 | ||
976 | static CORE_ADDR | |
c30dc700 | 977 | sh64_frame_align (struct gdbarch *ignore, CORE_ADDR sp) |
55ff77ac | 978 | { |
c30dc700 | 979 | return sp & ~7; |
55ff77ac CV |
980 | } |
981 | ||
c30dc700 | 982 | /* Function: push_dummy_call |
55ff77ac CV |
983 | Setup the function arguments for calling a function in the inferior. |
984 | ||
85a453d5 | 985 | On the Renesas SH architecture, there are four registers (R4 to R7) |
55ff77ac CV |
986 | which are dedicated for passing function arguments. Up to the first |
987 | four arguments (depending on size) may go into these registers. | |
988 | The rest go on the stack. | |
989 | ||
990 | Arguments that are smaller than 4 bytes will still take up a whole | |
991 | register or a whole 32-bit word on the stack, and will be | |
992 | right-justified in the register or the stack word. This includes | |
993 | chars, shorts, and small aggregate types. | |
994 | ||
995 | Arguments that are larger than 4 bytes may be split between two or | |
996 | more registers. If there are not enough registers free, an argument | |
997 | may be passed partly in a register (or registers), and partly on the | |
998 | stack. This includes doubles, long longs, and larger aggregates. | |
999 | As far as I know, there is no upper limit to the size of aggregates | |
1000 | that will be passed in this way; in other words, the convention of | |
1001 | passing a pointer to a large aggregate instead of a copy is not used. | |
1002 | ||
1003 | An exceptional case exists for struct arguments (and possibly other | |
1004 | aggregates such as arrays) if the size is larger than 4 bytes but | |
1005 | not a multiple of 4 bytes. In this case the argument is never split | |
1006 | between the registers and the stack, but instead is copied in its | |
1007 | entirety onto the stack, AND also copied into as many registers as | |
1008 | there is room for. In other words, space in registers permitting, | |
1009 | two copies of the same argument are passed in. As far as I can tell, | |
1010 | only the one on the stack is used, although that may be a function | |
1011 | of the level of compiler optimization. I suspect this is a compiler | |
1012 | bug. Arguments of these odd sizes are left-justified within the | |
1013 | word (as opposed to arguments smaller than 4 bytes, which are | |
1014 | right-justified). | |
1015 | ||
1016 | If the function is to return an aggregate type such as a struct, it | |
1017 | is either returned in the normal return value register R0 (if its | |
1018 | size is no greater than one byte), or else the caller must allocate | |
1019 | space into which the callee will copy the return value (if the size | |
1020 | is greater than one byte). In this case, a pointer to the return | |
1021 | value location is passed into the callee in register R2, which does | |
1022 | not displace any of the other arguments passed in via registers R4 | |
1023 | to R7. */ | |
1024 | ||
1025 | /* R2-R9 for integer types and integer equivalent (char, pointers) and | |
1026 | non-scalar (struct, union) elements (even if the elements are | |
1027 | floats). | |
1028 | FR0-FR11 for single precision floating point (float) | |
1029 | DR0-DR10 for double precision floating point (double) | |
1030 | ||
1031 | If a float is argument number 3 (for instance) and arguments number | |
1032 | 1,2, and 4 are integer, the mapping will be: | |
1033 | arg1 -->R2, arg2 --> R3, arg3 -->FR0, arg4 --> R5. I.e. R4 is not used. | |
1034 | ||
1035 | If a float is argument number 10 (for instance) and arguments number | |
1036 | 1 through 10 are integer, the mapping will be: | |
1037 | arg1->R2, arg2->R3, arg3->R4, arg4->R5, arg5->R6, arg6->R7, arg7->R8, | |
1038 | arg8->R9, arg9->(0,SP)stack(8-byte aligned), arg10->FR0, arg11->stack(16,SP). | |
1039 | I.e. there is hole in the stack. | |
1040 | ||
1041 | Different rules apply for variable arguments functions, and for functions | |
7bb11558 | 1042 | for which the prototype is not known. */ |
55ff77ac CV |
1043 | |
1044 | static CORE_ADDR | |
c30dc700 CV |
1045 | sh64_push_dummy_call (struct gdbarch *gdbarch, |
1046 | struct value *function, | |
1047 | struct regcache *regcache, | |
1048 | CORE_ADDR bp_addr, | |
1049 | int nargs, struct value **args, | |
1050 | CORE_ADDR sp, int struct_return, | |
1051 | CORE_ADDR struct_addr) | |
55ff77ac CV |
1052 | { |
1053 | int stack_offset, stack_alloc; | |
1054 | int int_argreg; | |
1055 | int float_argreg; | |
1056 | int double_argreg; | |
1057 | int float_arg_index = 0; | |
1058 | int double_arg_index = 0; | |
1059 | int argnum; | |
1060 | struct type *type; | |
1061 | CORE_ADDR regval; | |
1062 | char *val; | |
1063 | char valbuf[8]; | |
1064 | char valbuf_tmp[8]; | |
1065 | int len; | |
1066 | int argreg_size; | |
1067 | int fp_args[12]; | |
55ff77ac CV |
1068 | |
1069 | memset (fp_args, 0, sizeof (fp_args)); | |
1070 | ||
1071 | /* first force sp to a 8-byte alignment */ | |
c30dc700 | 1072 | sp = sh64_frame_align (gdbarch, sp); |
55ff77ac CV |
1073 | |
1074 | /* The "struct return pointer" pseudo-argument has its own dedicated | |
1075 | register */ | |
1076 | ||
1077 | if (struct_return) | |
c30dc700 CV |
1078 | regcache_cooked_write_unsigned (regcache, |
1079 | STRUCT_RETURN_REGNUM, struct_addr); | |
55ff77ac CV |
1080 | |
1081 | /* Now make sure there's space on the stack */ | |
1082 | for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++) | |
4991999e | 1083 | stack_alloc += ((TYPE_LENGTH (value_type (args[argnum])) + 7) & ~7); |
55ff77ac CV |
1084 | sp -= stack_alloc; /* make room on stack for args */ |
1085 | ||
1086 | /* Now load as many as possible of the first arguments into | |
1087 | registers, and push the rest onto the stack. There are 64 bytes | |
1088 | in eight registers available. Loop thru args from first to last. */ | |
1089 | ||
1090 | int_argreg = ARG0_REGNUM; | |
1091 | float_argreg = FP0_REGNUM; | |
1092 | double_argreg = DR0_REGNUM; | |
1093 | ||
1094 | for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++) | |
1095 | { | |
4991999e | 1096 | type = value_type (args[argnum]); |
55ff77ac CV |
1097 | len = TYPE_LENGTH (type); |
1098 | memset (valbuf, 0, sizeof (valbuf)); | |
1099 | ||
1100 | if (TYPE_CODE (type) != TYPE_CODE_FLT) | |
1101 | { | |
7bb11558 | 1102 | argreg_size = register_size (current_gdbarch, int_argreg); |
55ff77ac CV |
1103 | |
1104 | if (len < argreg_size) | |
1105 | { | |
1106 | /* value gets right-justified in the register or stack word */ | |
1107 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
1108 | memcpy (valbuf + argreg_size - len, | |
0fd88904 | 1109 | (char *) value_contents (args[argnum]), len); |
55ff77ac | 1110 | else |
0fd88904 | 1111 | memcpy (valbuf, (char *) value_contents (args[argnum]), len); |
55ff77ac CV |
1112 | |
1113 | val = valbuf; | |
1114 | } | |
1115 | else | |
0fd88904 | 1116 | val = (char *) value_contents (args[argnum]); |
55ff77ac CV |
1117 | |
1118 | while (len > 0) | |
1119 | { | |
1120 | if (int_argreg > ARGLAST_REGNUM) | |
1121 | { | |
1122 | /* must go on the stack */ | |
1123 | write_memory (sp + stack_offset, val, argreg_size); | |
1124 | stack_offset += 8;/*argreg_size;*/ | |
1125 | } | |
1126 | /* NOTE WELL!!!!! This is not an "else if" clause!!! | |
1127 | That's because some *&^%$ things get passed on the stack | |
1128 | AND in the registers! */ | |
1129 | if (int_argreg <= ARGLAST_REGNUM) | |
1130 | { | |
1131 | /* there's room in a register */ | |
1132 | regval = extract_unsigned_integer (val, argreg_size); | |
c30dc700 | 1133 | regcache_cooked_write_unsigned (regcache, int_argreg, regval); |
55ff77ac CV |
1134 | } |
1135 | /* Store the value 8 bytes at a time. This means that | |
1136 | things larger than 8 bytes may go partly in registers | |
1137 | and partly on the stack. FIXME: argreg is incremented | |
7bb11558 | 1138 | before we use its size. */ |
55ff77ac CV |
1139 | len -= argreg_size; |
1140 | val += argreg_size; | |
1141 | int_argreg++; | |
1142 | } | |
1143 | } | |
1144 | else | |
1145 | { | |
0fd88904 | 1146 | val = (char *) value_contents (args[argnum]); |
55ff77ac CV |
1147 | if (len == 4) |
1148 | { | |
1149 | /* Where is it going to be stored? */ | |
1150 | while (fp_args[float_arg_index]) | |
1151 | float_arg_index ++; | |
1152 | ||
1153 | /* Now float_argreg points to the register where it | |
1154 | should be stored. Are we still within the allowed | |
1155 | register set? */ | |
1156 | if (float_arg_index <= FLOAT_ARGLAST_REGNUM) | |
1157 | { | |
1158 | /* Goes in FR0...FR11 */ | |
c30dc700 CV |
1159 | regcache_cooked_write (regcache, |
1160 | FP0_REGNUM + float_arg_index, | |
1161 | val); | |
55ff77ac | 1162 | fp_args[float_arg_index] = 1; |
7bb11558 | 1163 | /* Skip the corresponding general argument register. */ |
55ff77ac CV |
1164 | int_argreg ++; |
1165 | } | |
1166 | else | |
1167 | ; | |
1168 | /* Store it as the integers, 8 bytes at the time, if | |
7bb11558 | 1169 | necessary spilling on the stack. */ |
55ff77ac CV |
1170 | |
1171 | } | |
1172 | else if (len == 8) | |
1173 | { | |
1174 | /* Where is it going to be stored? */ | |
1175 | while (fp_args[double_arg_index]) | |
1176 | double_arg_index += 2; | |
1177 | /* Now double_argreg points to the register | |
1178 | where it should be stored. | |
1179 | Are we still within the allowed register set? */ | |
1180 | if (double_arg_index < FLOAT_ARGLAST_REGNUM) | |
1181 | { | |
1182 | /* Goes in DR0...DR10 */ | |
1183 | /* The numbering of the DRi registers is consecutive, | |
7bb11558 | 1184 | i.e. includes odd numbers. */ |
55ff77ac | 1185 | int double_register_offset = double_arg_index / 2; |
c30dc700 CV |
1186 | int regnum = DR0_REGNUM + double_register_offset; |
1187 | regcache_cooked_write (regcache, regnum, val); | |
55ff77ac CV |
1188 | fp_args[double_arg_index] = 1; |
1189 | fp_args[double_arg_index + 1] = 1; | |
7bb11558 | 1190 | /* Skip the corresponding general argument register. */ |
55ff77ac CV |
1191 | int_argreg ++; |
1192 | } | |
1193 | else | |
1194 | ; | |
1195 | /* Store it as the integers, 8 bytes at the time, if | |
7bb11558 | 1196 | necessary spilling on the stack. */ |
55ff77ac CV |
1197 | } |
1198 | } | |
1199 | } | |
c30dc700 CV |
1200 | /* Store return address. */ |
1201 | regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr); | |
55ff77ac | 1202 | |
c30dc700 CV |
1203 | /* Update stack pointer. */ |
1204 | regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp); | |
55ff77ac | 1205 | |
55ff77ac CV |
1206 | return sp; |
1207 | } | |
1208 | ||
1209 | /* Find a function's return value in the appropriate registers (in | |
1210 | regbuf), and copy it into valbuf. Extract from an array REGBUF | |
1211 | containing the (raw) register state a function return value of type | |
1212 | TYPE, and copy that, in virtual format, into VALBUF. */ | |
1213 | static void | |
c30dc700 CV |
1214 | sh64_extract_return_value (struct type *type, struct regcache *regcache, |
1215 | void *valbuf) | |
55ff77ac | 1216 | { |
55ff77ac | 1217 | int len = TYPE_LENGTH (type); |
55ff77ac CV |
1218 | |
1219 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
1220 | { | |
1221 | if (len == 4) | |
1222 | { | |
1223 | /* Return value stored in FP0_REGNUM */ | |
c30dc700 | 1224 | regcache_raw_read (regcache, FP0_REGNUM, valbuf); |
55ff77ac CV |
1225 | } |
1226 | else if (len == 8) | |
1227 | { | |
1228 | /* return value stored in DR0_REGNUM */ | |
1229 | DOUBLEST val; | |
c30dc700 | 1230 | char buf[8]; |
55ff77ac | 1231 | |
c30dc700 | 1232 | regcache_cooked_read (regcache, DR0_REGNUM, &buf); |
55ff77ac CV |
1233 | |
1234 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) | |
1235 | floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, | |
c30dc700 | 1236 | buf, &val); |
55ff77ac CV |
1237 | else |
1238 | floatformat_to_doublest (&floatformat_ieee_double_big, | |
c30dc700 | 1239 | buf, &val); |
7bb11558 | 1240 | store_typed_floating (valbuf, type, val); |
55ff77ac CV |
1241 | } |
1242 | } | |
1243 | else | |
1244 | { | |
1245 | if (len <= 8) | |
1246 | { | |
c30dc700 CV |
1247 | int offset; |
1248 | char buf[8]; | |
55ff77ac | 1249 | /* Result is in register 2. If smaller than 8 bytes, it is padded |
7bb11558 | 1250 | at the most significant end. */ |
c30dc700 CV |
1251 | regcache_raw_read (regcache, DEFAULT_RETURN_REGNUM, buf); |
1252 | ||
55ff77ac | 1253 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
c30dc700 CV |
1254 | offset = register_size (current_gdbarch, DEFAULT_RETURN_REGNUM) |
1255 | - len; | |
55ff77ac | 1256 | else |
c30dc700 CV |
1257 | offset = 0; |
1258 | memcpy (valbuf, buf + offset, len); | |
55ff77ac CV |
1259 | } |
1260 | else | |
1261 | error ("bad size for return value"); | |
1262 | } | |
1263 | } | |
1264 | ||
1265 | /* Write into appropriate registers a function return value | |
1266 | of type TYPE, given in virtual format. | |
1267 | If the architecture is sh4 or sh3e, store a function's return value | |
1268 | in the R0 general register or in the FP0 floating point register, | |
1269 | depending on the type of the return value. In all the other cases | |
7bb11558 | 1270 | the result is stored in r0, left-justified. */ |
55ff77ac CV |
1271 | |
1272 | static void | |
c30dc700 CV |
1273 | sh64_store_return_value (struct type *type, struct regcache *regcache, |
1274 | const void *valbuf) | |
55ff77ac | 1275 | { |
7bb11558 | 1276 | char buf[64]; /* more than enough... */ |
55ff77ac CV |
1277 | int len = TYPE_LENGTH (type); |
1278 | ||
1279 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
1280 | { | |
c30dc700 CV |
1281 | int i, regnum = FP0_REGNUM; |
1282 | for (i = 0; i < len; i += 4) | |
1283 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) | |
1284 | regcache_raw_write (regcache, regnum++, | |
1285 | (char *) valbuf + len - 4 - i); | |
1286 | else | |
1287 | regcache_raw_write (regcache, regnum++, (char *) valbuf + i); | |
55ff77ac CV |
1288 | } |
1289 | else | |
1290 | { | |
1291 | int return_register = DEFAULT_RETURN_REGNUM; | |
1292 | int offset = 0; | |
1293 | ||
7bb11558 | 1294 | if (len <= register_size (current_gdbarch, return_register)) |
55ff77ac | 1295 | { |
7bb11558 MS |
1296 | /* Pad with zeros. */ |
1297 | memset (buf, 0, register_size (current_gdbarch, return_register)); | |
55ff77ac | 1298 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) |
7bb11558 MS |
1299 | offset = 0; /*register_size (current_gdbarch, |
1300 | return_register) - len;*/ | |
55ff77ac | 1301 | else |
7bb11558 | 1302 | offset = register_size (current_gdbarch, return_register) - len; |
55ff77ac CV |
1303 | |
1304 | memcpy (buf + offset, valbuf, len); | |
c30dc700 | 1305 | regcache_raw_write (regcache, return_register, buf); |
55ff77ac CV |
1306 | } |
1307 | else | |
c30dc700 | 1308 | regcache_raw_write (regcache, return_register, valbuf); |
55ff77ac CV |
1309 | } |
1310 | } | |
1311 | ||
c30dc700 CV |
1312 | static enum return_value_convention |
1313 | sh64_return_value (struct gdbarch *gdbarch, struct type *type, | |
1314 | struct regcache *regcache, | |
1315 | void *readbuf, const void *writebuf) | |
1316 | { | |
1317 | if (sh64_use_struct_convention (type)) | |
1318 | return RETURN_VALUE_STRUCT_CONVENTION; | |
1319 | if (writebuf) | |
1320 | sh64_store_return_value (type, regcache, writebuf); | |
1321 | else if (readbuf) | |
1322 | sh64_extract_return_value (type, regcache, readbuf); | |
1323 | return RETURN_VALUE_REGISTER_CONVENTION; | |
1324 | } | |
1325 | ||
55ff77ac CV |
1326 | static void |
1327 | sh64_show_media_regs (void) | |
1328 | { | |
1329 | int i; | |
55ff77ac CV |
1330 | |
1331 | printf_filtered ("PC=%s SR=%016llx \n", | |
1332 | paddr (read_register (PC_REGNUM)), | |
1333 | (long long) read_register (SR_REGNUM)); | |
1334 | ||
1335 | printf_filtered ("SSR=%016llx SPC=%016llx \n", | |
1336 | (long long) read_register (SSR_REGNUM), | |
1337 | (long long) read_register (SPC_REGNUM)); | |
1338 | printf_filtered ("FPSCR=%016lx\n ", | |
1339 | (long) read_register (FPSCR_REGNUM)); | |
1340 | ||
1341 | for (i = 0; i < 64; i = i + 4) | |
1342 | printf_filtered ("\nR%d-R%d %016llx %016llx %016llx %016llx\n", | |
1343 | i, i + 3, | |
1344 | (long long) read_register (i + 0), | |
1345 | (long long) read_register (i + 1), | |
1346 | (long long) read_register (i + 2), | |
1347 | (long long) read_register (i + 3)); | |
1348 | ||
1349 | printf_filtered ("\n"); | |
1350 | ||
1351 | for (i = 0; i < 64; i = i + 8) | |
1352 | printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1353 | i, i + 7, | |
1354 | (long) read_register (FP0_REGNUM + i + 0), | |
1355 | (long) read_register (FP0_REGNUM + i + 1), | |
1356 | (long) read_register (FP0_REGNUM + i + 2), | |
1357 | (long) read_register (FP0_REGNUM + i + 3), | |
1358 | (long) read_register (FP0_REGNUM + i + 4), | |
1359 | (long) read_register (FP0_REGNUM + i + 5), | |
1360 | (long) read_register (FP0_REGNUM + i + 6), | |
1361 | (long) read_register (FP0_REGNUM + i + 7)); | |
1362 | } | |
1363 | ||
1364 | static void | |
1365 | sh64_show_compact_regs (void) | |
1366 | { | |
1367 | int i; | |
55ff77ac CV |
1368 | |
1369 | printf_filtered ("PC=%s \n", | |
1370 | paddr (read_register (PC_C_REGNUM))); | |
1371 | ||
1372 | printf_filtered ("GBR=%08lx MACH=%08lx MACL=%08lx PR=%08lx T=%08lx\n", | |
1373 | (long) read_register (GBR_C_REGNUM), | |
1374 | (long) read_register (MACH_C_REGNUM), | |
1375 | (long) read_register (MACL_C_REGNUM), | |
1376 | (long) read_register (PR_C_REGNUM), | |
1377 | (long) read_register (T_C_REGNUM)); | |
1378 | printf_filtered ("FPSCR=%08lx FPUL=%08lx\n", | |
1379 | (long) read_register (FPSCR_C_REGNUM), | |
1380 | (long) read_register (FPUL_C_REGNUM)); | |
1381 | ||
1382 | for (i = 0; i < 16; i = i + 4) | |
1383 | printf_filtered ("\nR%d-R%d %08lx %08lx %08lx %08lx\n", | |
1384 | i, i + 3, | |
1385 | (long) read_register (i + 0), | |
1386 | (long) read_register (i + 1), | |
1387 | (long) read_register (i + 2), | |
1388 | (long) read_register (i + 3)); | |
1389 | ||
1390 | printf_filtered ("\n"); | |
1391 | ||
1392 | for (i = 0; i < 16; i = i + 8) | |
1393 | printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1394 | i, i + 7, | |
1395 | (long) read_register (FP0_REGNUM + i + 0), | |
1396 | (long) read_register (FP0_REGNUM + i + 1), | |
1397 | (long) read_register (FP0_REGNUM + i + 2), | |
1398 | (long) read_register (FP0_REGNUM + i + 3), | |
1399 | (long) read_register (FP0_REGNUM + i + 4), | |
1400 | (long) read_register (FP0_REGNUM + i + 5), | |
1401 | (long) read_register (FP0_REGNUM + i + 6), | |
1402 | (long) read_register (FP0_REGNUM + i + 7)); | |
1403 | } | |
1404 | ||
7bb11558 MS |
1405 | /* FIXME!!! This only shows the registers for shmedia, excluding the |
1406 | pseudo registers. */ | |
55ff77ac CV |
1407 | void |
1408 | sh64_show_regs (void) | |
1409 | { | |
1410 | if (deprecated_selected_frame | |
1411 | && pc_is_isa32 (get_frame_pc (deprecated_selected_frame))) | |
1412 | sh64_show_media_regs (); | |
1413 | else | |
1414 | sh64_show_compact_regs (); | |
1415 | } | |
1416 | ||
1417 | /* *INDENT-OFF* */ | |
1418 | /* | |
1419 | SH MEDIA MODE (ISA 32) | |
1420 | general registers (64-bit) 0-63 | |
1421 | 0 r0, r1, r2, r3, r4, r5, r6, r7, | |
1422 | 64 r8, r9, r10, r11, r12, r13, r14, r15, | |
1423 | 128 r16, r17, r18, r19, r20, r21, r22, r23, | |
1424 | 192 r24, r25, r26, r27, r28, r29, r30, r31, | |
1425 | 256 r32, r33, r34, r35, r36, r37, r38, r39, | |
1426 | 320 r40, r41, r42, r43, r44, r45, r46, r47, | |
1427 | 384 r48, r49, r50, r51, r52, r53, r54, r55, | |
1428 | 448 r56, r57, r58, r59, r60, r61, r62, r63, | |
1429 | ||
1430 | pc (64-bit) 64 | |
1431 | 512 pc, | |
1432 | ||
1433 | status reg., saved status reg., saved pc reg. (64-bit) 65-67 | |
1434 | 520 sr, ssr, spc, | |
1435 | ||
1436 | target registers (64-bit) 68-75 | |
1437 | 544 tr0, tr1, tr2, tr3, tr4, tr5, tr6, tr7, | |
1438 | ||
1439 | floating point state control register (32-bit) 76 | |
1440 | 608 fpscr, | |
1441 | ||
1442 | single precision floating point registers (32-bit) 77-140 | |
1443 | 612 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7, | |
1444 | 644 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15, | |
1445 | 676 fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23, | |
1446 | 708 fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31, | |
1447 | 740 fr32, fr33, fr34, fr35, fr36, fr37, fr38, fr39, | |
1448 | 772 fr40, fr41, fr42, fr43, fr44, fr45, fr46, fr47, | |
1449 | 804 fr48, fr49, fr50, fr51, fr52, fr53, fr54, fr55, | |
1450 | 836 fr56, fr57, fr58, fr59, fr60, fr61, fr62, fr63, | |
1451 | ||
1452 | TOTAL SPACE FOR REGISTERS: 868 bytes | |
1453 | ||
1454 | From here on they are all pseudo registers: no memory allocated. | |
1455 | REGISTER_BYTE returns the register byte for the base register. | |
1456 | ||
1457 | double precision registers (pseudo) 141-172 | |
1458 | dr0, dr2, dr4, dr6, dr8, dr10, dr12, dr14, | |
1459 | dr16, dr18, dr20, dr22, dr24, dr26, dr28, dr30, | |
1460 | dr32, dr34, dr36, dr38, dr40, dr42, dr44, dr46, | |
1461 | dr48, dr50, dr52, dr54, dr56, dr58, dr60, dr62, | |
1462 | ||
1463 | floating point pairs (pseudo) 173-204 | |
1464 | fp0, fp2, fp4, fp6, fp8, fp10, fp12, fp14, | |
1465 | fp16, fp18, fp20, fp22, fp24, fp26, fp28, fp30, | |
1466 | fp32, fp34, fp36, fp38, fp40, fp42, fp44, fp46, | |
1467 | fp48, fp50, fp52, fp54, fp56, fp58, fp60, fp62, | |
1468 | ||
1469 | floating point vectors (4 floating point regs) (pseudo) 205-220 | |
1470 | fv0, fv4, fv8, fv12, fv16, fv20, fv24, fv28, | |
1471 | fv32, fv36, fv40, fv44, fv48, fv52, fv56, fv60, | |
1472 | ||
1473 | SH COMPACT MODE (ISA 16) (all pseudo) 221-272 | |
1474 | r0_c, r1_c, r2_c, r3_c, r4_c, r5_c, r6_c, r7_c, | |
1475 | r8_c, r9_c, r10_c, r11_c, r12_c, r13_c, r14_c, r15_c, | |
1476 | pc_c, | |
1477 | gbr_c, mach_c, macl_c, pr_c, t_c, | |
1478 | fpscr_c, fpul_c, | |
1479 | fr0_c, fr1_c, fr2_c, fr3_c, fr4_c, fr5_c, fr6_c, fr7_c, | |
1480 | fr8_c, fr9_c, fr10_c, fr11_c, fr12_c, fr13_c, fr14_c, fr15_c | |
1481 | dr0_c, dr2_c, dr4_c, dr6_c, dr8_c, dr10_c, dr12_c, dr14_c | |
1482 | fv0_c, fv4_c, fv8_c, fv12_c | |
1483 | */ | |
55ff77ac | 1484 | |
55ff77ac | 1485 | static struct type * |
39add00a | 1486 | sh64_build_float_register_type (int high) |
55ff77ac CV |
1487 | { |
1488 | struct type *temp; | |
1489 | ||
1490 | temp = create_range_type (NULL, builtin_type_int, 0, high); | |
1491 | return create_array_type (NULL, builtin_type_float, temp); | |
1492 | } | |
1493 | ||
7bb11558 MS |
1494 | /* Return the GDB type object for the "standard" data type |
1495 | of data in register REG_NR. */ | |
55ff77ac | 1496 | static struct type * |
7bb11558 | 1497 | sh64_register_type (struct gdbarch *gdbarch, int reg_nr) |
55ff77ac | 1498 | { |
55ff77ac CV |
1499 | if ((reg_nr >= FP0_REGNUM |
1500 | && reg_nr <= FP_LAST_REGNUM) | |
1501 | || (reg_nr >= FP0_C_REGNUM | |
1502 | && reg_nr <= FP_LAST_C_REGNUM)) | |
1503 | return builtin_type_float; | |
1504 | else if ((reg_nr >= DR0_REGNUM | |
1505 | && reg_nr <= DR_LAST_REGNUM) | |
1506 | || (reg_nr >= DR0_C_REGNUM | |
1507 | && reg_nr <= DR_LAST_C_REGNUM)) | |
1508 | return builtin_type_double; | |
1509 | else if (reg_nr >= FPP0_REGNUM | |
1510 | && reg_nr <= FPP_LAST_REGNUM) | |
39add00a | 1511 | return sh64_build_float_register_type (1); |
55ff77ac CV |
1512 | else if ((reg_nr >= FV0_REGNUM |
1513 | && reg_nr <= FV_LAST_REGNUM) | |
1514 | ||(reg_nr >= FV0_C_REGNUM | |
1515 | && reg_nr <= FV_LAST_C_REGNUM)) | |
39add00a | 1516 | return sh64_build_float_register_type (3); |
55ff77ac CV |
1517 | else if (reg_nr == FPSCR_REGNUM) |
1518 | return builtin_type_int; | |
1519 | else if (reg_nr >= R0_C_REGNUM | |
1520 | && reg_nr < FP0_C_REGNUM) | |
1521 | return builtin_type_int; | |
1522 | else | |
1523 | return builtin_type_long_long; | |
1524 | } | |
1525 | ||
1526 | static void | |
39add00a | 1527 | sh64_register_convert_to_virtual (int regnum, struct type *type, |
55ff77ac CV |
1528 | char *from, char *to) |
1529 | { | |
55ff77ac CV |
1530 | if (TARGET_BYTE_ORDER != BFD_ENDIAN_LITTLE) |
1531 | { | |
7bb11558 MS |
1532 | /* It is a no-op. */ |
1533 | memcpy (to, from, register_size (current_gdbarch, regnum)); | |
55ff77ac CV |
1534 | return; |
1535 | } | |
1536 | ||
1537 | if ((regnum >= DR0_REGNUM | |
1538 | && regnum <= DR_LAST_REGNUM) | |
1539 | || (regnum >= DR0_C_REGNUM | |
1540 | && regnum <= DR_LAST_C_REGNUM)) | |
1541 | { | |
1542 | DOUBLEST val; | |
7bb11558 MS |
1543 | floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, |
1544 | from, &val); | |
39add00a | 1545 | store_typed_floating (to, type, val); |
55ff77ac CV |
1546 | } |
1547 | else | |
39add00a | 1548 | error ("sh64_register_convert_to_virtual called with non DR register number"); |
55ff77ac CV |
1549 | } |
1550 | ||
1551 | static void | |
39add00a | 1552 | sh64_register_convert_to_raw (struct type *type, int regnum, |
55ff77ac CV |
1553 | const void *from, void *to) |
1554 | { | |
55ff77ac CV |
1555 | if (TARGET_BYTE_ORDER != BFD_ENDIAN_LITTLE) |
1556 | { | |
7bb11558 MS |
1557 | /* It is a no-op. */ |
1558 | memcpy (to, from, register_size (current_gdbarch, regnum)); | |
55ff77ac CV |
1559 | return; |
1560 | } | |
1561 | ||
1562 | if ((regnum >= DR0_REGNUM | |
1563 | && regnum <= DR_LAST_REGNUM) | |
1564 | || (regnum >= DR0_C_REGNUM | |
1565 | && regnum <= DR_LAST_C_REGNUM)) | |
1566 | { | |
1567 | DOUBLEST val = deprecated_extract_floating (from, TYPE_LENGTH(type)); | |
7bb11558 MS |
1568 | floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword, |
1569 | &val, to); | |
55ff77ac CV |
1570 | } |
1571 | else | |
39add00a | 1572 | error ("sh64_register_convert_to_raw called with non DR register number"); |
55ff77ac CV |
1573 | } |
1574 | ||
1575 | static void | |
1576 | sh64_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
1577 | int reg_nr, void *buffer) | |
1578 | { | |
1579 | int base_regnum; | |
1580 | int portion; | |
1581 | int offset = 0; | |
1582 | char temp_buffer[MAX_REGISTER_SIZE]; | |
55ff77ac CV |
1583 | |
1584 | if (reg_nr >= DR0_REGNUM | |
1585 | && reg_nr <= DR_LAST_REGNUM) | |
1586 | { | |
c30dc700 | 1587 | base_regnum = sh64_dr_reg_base_num (reg_nr); |
55ff77ac | 1588 | |
7bb11558 | 1589 | /* Build the value in the provided buffer. */ |
55ff77ac | 1590 | /* DR regs are double precision registers obtained by |
7bb11558 | 1591 | concatenating 2 single precision floating point registers. */ |
55ff77ac CV |
1592 | for (portion = 0; portion < 2; portion++) |
1593 | regcache_raw_read (regcache, base_regnum + portion, | |
1594 | (temp_buffer | |
7bb11558 | 1595 | + register_size (gdbarch, base_regnum) * portion)); |
55ff77ac | 1596 | |
7bb11558 | 1597 | /* We must pay attention to the endianness. */ |
39add00a MS |
1598 | sh64_register_convert_to_virtual (reg_nr, |
1599 | gdbarch_register_type (gdbarch, | |
1600 | reg_nr), | |
1601 | temp_buffer, buffer); | |
55ff77ac CV |
1602 | |
1603 | } | |
1604 | ||
1605 | else if (reg_nr >= FPP0_REGNUM | |
1606 | && reg_nr <= FPP_LAST_REGNUM) | |
1607 | { | |
c30dc700 | 1608 | base_regnum = sh64_fpp_reg_base_num (reg_nr); |
55ff77ac | 1609 | |
7bb11558 | 1610 | /* Build the value in the provided buffer. */ |
55ff77ac | 1611 | /* FPP regs are pairs of single precision registers obtained by |
7bb11558 | 1612 | concatenating 2 single precision floating point registers. */ |
55ff77ac CV |
1613 | for (portion = 0; portion < 2; portion++) |
1614 | regcache_raw_read (regcache, base_regnum + portion, | |
1615 | ((char *) buffer | |
7bb11558 | 1616 | + register_size (gdbarch, base_regnum) * portion)); |
55ff77ac CV |
1617 | } |
1618 | ||
1619 | else if (reg_nr >= FV0_REGNUM | |
1620 | && reg_nr <= FV_LAST_REGNUM) | |
1621 | { | |
c30dc700 | 1622 | base_regnum = sh64_fv_reg_base_num (reg_nr); |
55ff77ac | 1623 | |
7bb11558 | 1624 | /* Build the value in the provided buffer. */ |
55ff77ac | 1625 | /* FV regs are vectors of single precision registers obtained by |
7bb11558 | 1626 | concatenating 4 single precision floating point registers. */ |
55ff77ac CV |
1627 | for (portion = 0; portion < 4; portion++) |
1628 | regcache_raw_read (regcache, base_regnum + portion, | |
1629 | ((char *) buffer | |
7bb11558 | 1630 | + register_size (gdbarch, base_regnum) * portion)); |
55ff77ac CV |
1631 | } |
1632 | ||
1633 | /* sh compact pseudo registers. 1-to-1 with a shmedia register */ | |
1634 | else if (reg_nr >= R0_C_REGNUM | |
1635 | && reg_nr <= T_C_REGNUM) | |
1636 | { | |
1637 | base_regnum = sh64_compact_reg_base_num (reg_nr); | |
1638 | ||
7bb11558 | 1639 | /* Build the value in the provided buffer. */ |
55ff77ac CV |
1640 | regcache_raw_read (regcache, base_regnum, temp_buffer); |
1641 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
1642 | offset = 4; | |
1643 | memcpy (buffer, temp_buffer + offset, 4); /* get LOWER 32 bits only????*/ | |
1644 | } | |
1645 | ||
1646 | else if (reg_nr >= FP0_C_REGNUM | |
1647 | && reg_nr <= FP_LAST_C_REGNUM) | |
1648 | { | |
1649 | base_regnum = sh64_compact_reg_base_num (reg_nr); | |
1650 | ||
7bb11558 | 1651 | /* Build the value in the provided buffer. */ |
55ff77ac | 1652 | /* Floating point registers map 1-1 to the media fp regs, |
7bb11558 | 1653 | they have the same size and endianness. */ |
55ff77ac CV |
1654 | regcache_raw_read (regcache, base_regnum, buffer); |
1655 | } | |
1656 | ||
1657 | else if (reg_nr >= DR0_C_REGNUM | |
1658 | && reg_nr <= DR_LAST_C_REGNUM) | |
1659 | { | |
1660 | base_regnum = sh64_compact_reg_base_num (reg_nr); | |
1661 | ||
1662 | /* DR_C regs are double precision registers obtained by | |
7bb11558 | 1663 | concatenating 2 single precision floating point registers. */ |
55ff77ac CV |
1664 | for (portion = 0; portion < 2; portion++) |
1665 | regcache_raw_read (regcache, base_regnum + portion, | |
1666 | (temp_buffer | |
7bb11558 | 1667 | + register_size (gdbarch, base_regnum) * portion)); |
55ff77ac | 1668 | |
7bb11558 | 1669 | /* We must pay attention to the endianness. */ |
39add00a MS |
1670 | sh64_register_convert_to_virtual (reg_nr, |
1671 | gdbarch_register_type (gdbarch, | |
1672 | reg_nr), | |
1673 | temp_buffer, buffer); | |
55ff77ac CV |
1674 | } |
1675 | ||
1676 | else if (reg_nr >= FV0_C_REGNUM | |
1677 | && reg_nr <= FV_LAST_C_REGNUM) | |
1678 | { | |
1679 | base_regnum = sh64_compact_reg_base_num (reg_nr); | |
1680 | ||
7bb11558 | 1681 | /* Build the value in the provided buffer. */ |
55ff77ac | 1682 | /* FV_C regs are vectors of single precision registers obtained by |
7bb11558 | 1683 | concatenating 4 single precision floating point registers. */ |
55ff77ac CV |
1684 | for (portion = 0; portion < 4; portion++) |
1685 | regcache_raw_read (regcache, base_regnum + portion, | |
1686 | ((char *) buffer | |
7bb11558 | 1687 | + register_size (gdbarch, base_regnum) * portion)); |
55ff77ac CV |
1688 | } |
1689 | ||
1690 | else if (reg_nr == FPSCR_C_REGNUM) | |
1691 | { | |
1692 | int fpscr_base_regnum; | |
1693 | int sr_base_regnum; | |
1694 | unsigned int fpscr_value; | |
1695 | unsigned int sr_value; | |
1696 | unsigned int fpscr_c_value; | |
1697 | unsigned int fpscr_c_part1_value; | |
1698 | unsigned int fpscr_c_part2_value; | |
1699 | ||
1700 | fpscr_base_regnum = FPSCR_REGNUM; | |
1701 | sr_base_regnum = SR_REGNUM; | |
1702 | ||
7bb11558 | 1703 | /* Build the value in the provided buffer. */ |
55ff77ac CV |
1704 | /* FPSCR_C is a very weird register that contains sparse bits |
1705 | from the FPSCR and the SR architectural registers. | |
1706 | Specifically: */ | |
1707 | /* *INDENT-OFF* */ | |
1708 | /* | |
1709 | FPSRC_C bit | |
1710 | 0 Bit 0 of FPSCR | |
1711 | 1 reserved | |
1712 | 2-17 Bit 2-18 of FPSCR | |
1713 | 18-20 Bits 12,13,14 of SR | |
1714 | 21-31 reserved | |
1715 | */ | |
1716 | /* *INDENT-ON* */ | |
1717 | /* Get FPSCR into a local buffer */ | |
1718 | regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer); | |
7bb11558 | 1719 | /* Get value as an int. */ |
55ff77ac CV |
1720 | fpscr_value = extract_unsigned_integer (temp_buffer, 4); |
1721 | /* Get SR into a local buffer */ | |
1722 | regcache_raw_read (regcache, sr_base_regnum, temp_buffer); | |
7bb11558 | 1723 | /* Get value as an int. */ |
55ff77ac | 1724 | sr_value = extract_unsigned_integer (temp_buffer, 4); |
7bb11558 | 1725 | /* Build the new value. */ |
55ff77ac CV |
1726 | fpscr_c_part1_value = fpscr_value & 0x3fffd; |
1727 | fpscr_c_part2_value = (sr_value & 0x7000) << 6; | |
1728 | fpscr_c_value = fpscr_c_part1_value | fpscr_c_part2_value; | |
1729 | /* Store that in out buffer!!! */ | |
1730 | store_unsigned_integer (buffer, 4, fpscr_c_value); | |
7bb11558 | 1731 | /* FIXME There is surely an endianness gotcha here. */ |
55ff77ac CV |
1732 | } |
1733 | ||
1734 | else if (reg_nr == FPUL_C_REGNUM) | |
1735 | { | |
1736 | base_regnum = sh64_compact_reg_base_num (reg_nr); | |
1737 | ||
1738 | /* FPUL_C register is floating point register 32, | |
7bb11558 | 1739 | same size, same endianness. */ |
55ff77ac CV |
1740 | regcache_raw_read (regcache, base_regnum, buffer); |
1741 | } | |
1742 | } | |
1743 | ||
1744 | static void | |
1745 | sh64_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
1746 | int reg_nr, const void *buffer) | |
1747 | { | |
1748 | int base_regnum, portion; | |
1749 | int offset; | |
1750 | char temp_buffer[MAX_REGISTER_SIZE]; | |
55ff77ac CV |
1751 | |
1752 | if (reg_nr >= DR0_REGNUM | |
1753 | && reg_nr <= DR_LAST_REGNUM) | |
1754 | { | |
c30dc700 | 1755 | base_regnum = sh64_dr_reg_base_num (reg_nr); |
7bb11558 | 1756 | /* We must pay attention to the endianness. */ |
39add00a MS |
1757 | sh64_register_convert_to_raw (gdbarch_register_type (gdbarch, reg_nr), |
1758 | reg_nr, | |
1759 | buffer, temp_buffer); | |
55ff77ac CV |
1760 | |
1761 | /* Write the real regs for which this one is an alias. */ | |
1762 | for (portion = 0; portion < 2; portion++) | |
1763 | regcache_raw_write (regcache, base_regnum + portion, | |
1764 | (temp_buffer | |
7bb11558 MS |
1765 | + register_size (gdbarch, |
1766 | base_regnum) * portion)); | |
55ff77ac CV |
1767 | } |
1768 | ||
1769 | else if (reg_nr >= FPP0_REGNUM | |
1770 | && reg_nr <= FPP_LAST_REGNUM) | |
1771 | { | |
c30dc700 | 1772 | base_regnum = sh64_fpp_reg_base_num (reg_nr); |
55ff77ac CV |
1773 | |
1774 | /* Write the real regs for which this one is an alias. */ | |
1775 | for (portion = 0; portion < 2; portion++) | |
1776 | regcache_raw_write (regcache, base_regnum + portion, | |
1777 | ((char *) buffer | |
7bb11558 MS |
1778 | + register_size (gdbarch, |
1779 | base_regnum) * portion)); | |
55ff77ac CV |
1780 | } |
1781 | ||
1782 | else if (reg_nr >= FV0_REGNUM | |
1783 | && reg_nr <= FV_LAST_REGNUM) | |
1784 | { | |
c30dc700 | 1785 | base_regnum = sh64_fv_reg_base_num (reg_nr); |
55ff77ac CV |
1786 | |
1787 | /* Write the real regs for which this one is an alias. */ | |
1788 | for (portion = 0; portion < 4; portion++) | |
1789 | regcache_raw_write (regcache, base_regnum + portion, | |
1790 | ((char *) buffer | |
7bb11558 MS |
1791 | + register_size (gdbarch, |
1792 | base_regnum) * portion)); | |
55ff77ac CV |
1793 | } |
1794 | ||
1795 | /* sh compact general pseudo registers. 1-to-1 with a shmedia | |
1796 | register but only 4 bytes of it. */ | |
1797 | else if (reg_nr >= R0_C_REGNUM | |
1798 | && reg_nr <= T_C_REGNUM) | |
1799 | { | |
1800 | base_regnum = sh64_compact_reg_base_num (reg_nr); | |
7bb11558 | 1801 | /* reg_nr is 32 bit here, and base_regnum is 64 bits. */ |
55ff77ac CV |
1802 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) |
1803 | offset = 4; | |
1804 | else | |
1805 | offset = 0; | |
1806 | /* Let's read the value of the base register into a temporary | |
1807 | buffer, so that overwriting the last four bytes with the new | |
7bb11558 | 1808 | value of the pseudo will leave the upper 4 bytes unchanged. */ |
55ff77ac CV |
1809 | regcache_raw_read (regcache, base_regnum, temp_buffer); |
1810 | /* Write as an 8 byte quantity */ | |
1811 | memcpy (temp_buffer + offset, buffer, 4); | |
1812 | regcache_raw_write (regcache, base_regnum, temp_buffer); | |
1813 | } | |
1814 | ||
1815 | /* sh floating point compact pseudo registers. 1-to-1 with a shmedia | |
7bb11558 | 1816 | registers. Both are 4 bytes. */ |
55ff77ac CV |
1817 | else if (reg_nr >= FP0_C_REGNUM |
1818 | && reg_nr <= FP_LAST_C_REGNUM) | |
1819 | { | |
1820 | base_regnum = sh64_compact_reg_base_num (reg_nr); | |
1821 | regcache_raw_write (regcache, base_regnum, buffer); | |
1822 | } | |
1823 | ||
1824 | else if (reg_nr >= DR0_C_REGNUM | |
1825 | && reg_nr <= DR_LAST_C_REGNUM) | |
1826 | { | |
1827 | base_regnum = sh64_compact_reg_base_num (reg_nr); | |
1828 | for (portion = 0; portion < 2; portion++) | |
1829 | { | |
7bb11558 | 1830 | /* We must pay attention to the endianness. */ |
39add00a MS |
1831 | sh64_register_convert_to_raw (gdbarch_register_type (gdbarch, |
1832 | reg_nr), | |
1833 | reg_nr, | |
1834 | buffer, temp_buffer); | |
55ff77ac CV |
1835 | |
1836 | regcache_raw_write (regcache, base_regnum + portion, | |
1837 | (temp_buffer | |
7bb11558 MS |
1838 | + register_size (gdbarch, |
1839 | base_regnum) * portion)); | |
55ff77ac CV |
1840 | } |
1841 | } | |
1842 | ||
1843 | else if (reg_nr >= FV0_C_REGNUM | |
1844 | && reg_nr <= FV_LAST_C_REGNUM) | |
1845 | { | |
1846 | base_regnum = sh64_compact_reg_base_num (reg_nr); | |
1847 | ||
1848 | for (portion = 0; portion < 4; portion++) | |
1849 | { | |
1850 | regcache_raw_write (regcache, base_regnum + portion, | |
1851 | ((char *) buffer | |
7bb11558 MS |
1852 | + register_size (gdbarch, |
1853 | base_regnum) * portion)); | |
55ff77ac CV |
1854 | } |
1855 | } | |
1856 | ||
1857 | else if (reg_nr == FPSCR_C_REGNUM) | |
1858 | { | |
1859 | int fpscr_base_regnum; | |
1860 | int sr_base_regnum; | |
1861 | unsigned int fpscr_value; | |
1862 | unsigned int sr_value; | |
1863 | unsigned int old_fpscr_value; | |
1864 | unsigned int old_sr_value; | |
1865 | unsigned int fpscr_c_value; | |
1866 | unsigned int fpscr_mask; | |
1867 | unsigned int sr_mask; | |
1868 | ||
1869 | fpscr_base_regnum = FPSCR_REGNUM; | |
1870 | sr_base_regnum = SR_REGNUM; | |
1871 | ||
1872 | /* FPSCR_C is a very weird register that contains sparse bits | |
1873 | from the FPSCR and the SR architectural registers. | |
1874 | Specifically: */ | |
1875 | /* *INDENT-OFF* */ | |
1876 | /* | |
1877 | FPSRC_C bit | |
1878 | 0 Bit 0 of FPSCR | |
1879 | 1 reserved | |
1880 | 2-17 Bit 2-18 of FPSCR | |
1881 | 18-20 Bits 12,13,14 of SR | |
1882 | 21-31 reserved | |
1883 | */ | |
1884 | /* *INDENT-ON* */ | |
7bb11558 | 1885 | /* Get value as an int. */ |
55ff77ac CV |
1886 | fpscr_c_value = extract_unsigned_integer (buffer, 4); |
1887 | ||
7bb11558 | 1888 | /* Build the new values. */ |
55ff77ac CV |
1889 | fpscr_mask = 0x0003fffd; |
1890 | sr_mask = 0x001c0000; | |
1891 | ||
1892 | fpscr_value = fpscr_c_value & fpscr_mask; | |
1893 | sr_value = (fpscr_value & sr_mask) >> 6; | |
1894 | ||
1895 | regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer); | |
1896 | old_fpscr_value = extract_unsigned_integer (temp_buffer, 4); | |
1897 | old_fpscr_value &= 0xfffc0002; | |
1898 | fpscr_value |= old_fpscr_value; | |
1899 | store_unsigned_integer (temp_buffer, 4, fpscr_value); | |
1900 | regcache_raw_write (regcache, fpscr_base_regnum, temp_buffer); | |
1901 | ||
1902 | regcache_raw_read (regcache, sr_base_regnum, temp_buffer); | |
1903 | old_sr_value = extract_unsigned_integer (temp_buffer, 4); | |
1904 | old_sr_value &= 0xffff8fff; | |
1905 | sr_value |= old_sr_value; | |
1906 | store_unsigned_integer (temp_buffer, 4, sr_value); | |
1907 | regcache_raw_write (regcache, sr_base_regnum, temp_buffer); | |
1908 | } | |
1909 | ||
1910 | else if (reg_nr == FPUL_C_REGNUM) | |
1911 | { | |
1912 | base_regnum = sh64_compact_reg_base_num (reg_nr); | |
1913 | regcache_raw_write (regcache, base_regnum, buffer); | |
1914 | } | |
1915 | } | |
1916 | ||
55ff77ac | 1917 | /* FIXME:!! THIS SHOULD TAKE CARE OF GETTING THE RIGHT PORTION OF THE |
7bb11558 MS |
1918 | shmedia REGISTERS. */ |
1919 | /* Control registers, compact mode. */ | |
55ff77ac | 1920 | static void |
c30dc700 CV |
1921 | sh64_do_cr_c_register_info (struct ui_file *file, struct frame_info *frame, |
1922 | int cr_c_regnum) | |
55ff77ac CV |
1923 | { |
1924 | switch (cr_c_regnum) | |
1925 | { | |
c30dc700 CV |
1926 | case PC_C_REGNUM: |
1927 | fprintf_filtered (file, "pc_c\t0x%08x\n", | |
1928 | (int) get_frame_register_unsigned (frame, cr_c_regnum)); | |
55ff77ac | 1929 | break; |
c30dc700 CV |
1930 | case GBR_C_REGNUM: |
1931 | fprintf_filtered (file, "gbr_c\t0x%08x\n", | |
1932 | (int) get_frame_register_unsigned (frame, cr_c_regnum)); | |
55ff77ac | 1933 | break; |
c30dc700 CV |
1934 | case MACH_C_REGNUM: |
1935 | fprintf_filtered (file, "mach_c\t0x%08x\n", | |
1936 | (int) get_frame_register_unsigned (frame, cr_c_regnum)); | |
55ff77ac | 1937 | break; |
c30dc700 CV |
1938 | case MACL_C_REGNUM: |
1939 | fprintf_filtered (file, "macl_c\t0x%08x\n", | |
1940 | (int) get_frame_register_unsigned (frame, cr_c_regnum)); | |
55ff77ac | 1941 | break; |
c30dc700 CV |
1942 | case PR_C_REGNUM: |
1943 | fprintf_filtered (file, "pr_c\t0x%08x\n", | |
1944 | (int) get_frame_register_unsigned (frame, cr_c_regnum)); | |
55ff77ac | 1945 | break; |
c30dc700 CV |
1946 | case T_C_REGNUM: |
1947 | fprintf_filtered (file, "t_c\t0x%08x\n", | |
1948 | (int) get_frame_register_unsigned (frame, cr_c_regnum)); | |
55ff77ac | 1949 | break; |
c30dc700 CV |
1950 | case FPSCR_C_REGNUM: |
1951 | fprintf_filtered (file, "fpscr_c\t0x%08x\n", | |
1952 | (int) get_frame_register_unsigned (frame, cr_c_regnum)); | |
55ff77ac | 1953 | break; |
c30dc700 CV |
1954 | case FPUL_C_REGNUM: |
1955 | fprintf_filtered (file, "fpul_c\t0x%08x\n", | |
1956 | (int) get_frame_register_unsigned (frame, cr_c_regnum)); | |
55ff77ac CV |
1957 | break; |
1958 | } | |
1959 | } | |
1960 | ||
1961 | static void | |
c30dc700 CV |
1962 | sh64_do_fp_register (struct gdbarch *gdbarch, struct ui_file *file, |
1963 | struct frame_info *frame, int regnum) | |
55ff77ac CV |
1964 | { /* do values for FP (float) regs */ |
1965 | char *raw_buffer; | |
1966 | double flt; /* double extracted from raw hex data */ | |
1967 | int inv; | |
1968 | int j; | |
1969 | ||
7bb11558 | 1970 | /* Allocate space for the float. */ |
55ff77ac CV |
1971 | raw_buffer = (char *) alloca (register_size (gdbarch, FP0_REGNUM)); |
1972 | ||
1973 | /* Get the data in raw format. */ | |
c30dc700 | 1974 | if (!frame_register_read (frame, regnum, raw_buffer)) |
55ff77ac CV |
1975 | error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum)); |
1976 | ||
1977 | /* Get the register as a number */ | |
1978 | flt = unpack_double (builtin_type_float, raw_buffer, &inv); | |
1979 | ||
7bb11558 | 1980 | /* Print the name and some spaces. */ |
55ff77ac CV |
1981 | fputs_filtered (REGISTER_NAME (regnum), file); |
1982 | print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file); | |
1983 | ||
7bb11558 | 1984 | /* Print the value. */ |
55ff77ac CV |
1985 | if (inv) |
1986 | fprintf_filtered (file, "<invalid float>"); | |
1987 | else | |
1988 | fprintf_filtered (file, "%-10.9g", flt); | |
1989 | ||
7bb11558 | 1990 | /* Print the fp register as hex. */ |
55ff77ac CV |
1991 | fprintf_filtered (file, "\t(raw 0x"); |
1992 | for (j = 0; j < register_size (gdbarch, regnum); j++) | |
1993 | { | |
aa1ee363 | 1994 | int idx = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? j |
55ff77ac CV |
1995 | : register_size (gdbarch, regnum) - 1 - j; |
1996 | fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[idx]); | |
1997 | } | |
1998 | fprintf_filtered (file, ")"); | |
1999 | fprintf_filtered (file, "\n"); | |
2000 | } | |
2001 | ||
2002 | static void | |
c30dc700 CV |
2003 | sh64_do_pseudo_register (struct gdbarch *gdbarch, struct ui_file *file, |
2004 | struct frame_info *frame, int regnum) | |
55ff77ac | 2005 | { |
7bb11558 | 2006 | /* All the sh64-compact mode registers are pseudo registers. */ |
55ff77ac CV |
2007 | |
2008 | if (regnum < NUM_REGS | |
c30dc700 CV |
2009 | || regnum >= NUM_REGS + NUM_PSEUDO_REGS_SH_MEDIA |
2010 | + NUM_PSEUDO_REGS_SH_COMPACT) | |
55ff77ac | 2011 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 2012 | _("Invalid pseudo register number %d\n"), regnum); |
55ff77ac | 2013 | |
c30dc700 CV |
2014 | else if ((regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)) |
2015 | { | |
2016 | int fp_regnum = sh64_dr_reg_base_num (regnum); | |
2017 | fprintf_filtered (file, "dr%d\t0x%08x%08x\n", regnum - DR0_REGNUM, | |
2018 | (unsigned) get_frame_register_unsigned (frame, fp_regnum), | |
2019 | (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1)); | |
2020 | } | |
55ff77ac | 2021 | |
c30dc700 CV |
2022 | else if ((regnum >= DR0_C_REGNUM && regnum <= DR_LAST_C_REGNUM)) |
2023 | { | |
2024 | int fp_regnum = sh64_compact_reg_base_num (regnum); | |
2025 | fprintf_filtered (file, "dr%d_c\t0x%08x%08x\n", regnum - DR0_C_REGNUM, | |
2026 | (unsigned) get_frame_register_unsigned (frame, fp_regnum), | |
2027 | (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1)); | |
2028 | } | |
55ff77ac | 2029 | |
c30dc700 CV |
2030 | else if ((regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM)) |
2031 | { | |
2032 | int fp_regnum = sh64_fv_reg_base_num (regnum); | |
2033 | fprintf_filtered (file, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n", | |
2034 | regnum - FV0_REGNUM, | |
2035 | (unsigned) get_frame_register_unsigned (frame, fp_regnum), | |
2036 | (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1), | |
2037 | (unsigned) get_frame_register_unsigned (frame, fp_regnum + 2), | |
2038 | (unsigned) get_frame_register_unsigned (frame, fp_regnum + 3)); | |
2039 | } | |
55ff77ac | 2040 | |
c30dc700 CV |
2041 | else if ((regnum >= FV0_C_REGNUM && regnum <= FV_LAST_C_REGNUM)) |
2042 | { | |
2043 | int fp_regnum = sh64_compact_reg_base_num (regnum); | |
2044 | fprintf_filtered (file, "fv%d_c\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n", | |
2045 | regnum - FV0_C_REGNUM, | |
2046 | (unsigned) get_frame_register_unsigned (frame, fp_regnum), | |
2047 | (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1), | |
2048 | (unsigned) get_frame_register_unsigned (frame, fp_regnum + 2), | |
2049 | (unsigned) get_frame_register_unsigned (frame, fp_regnum + 3)); | |
2050 | } | |
2051 | ||
2052 | else if (regnum >= FPP0_REGNUM && regnum <= FPP_LAST_REGNUM) | |
2053 | { | |
2054 | int fp_regnum = sh64_fpp_reg_base_num (regnum); | |
2055 | fprintf_filtered (file, "fpp%d\t0x%08x\t0x%08x\n", regnum - FPP0_REGNUM, | |
2056 | (unsigned) get_frame_register_unsigned (frame, fp_regnum), | |
2057 | (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1)); | |
2058 | } | |
2059 | ||
2060 | else if (regnum >= R0_C_REGNUM && regnum <= R_LAST_C_REGNUM) | |
2061 | { | |
2062 | int c_regnum = sh64_compact_reg_base_num (regnum); | |
2063 | fprintf_filtered (file, "r%d_c\t0x%08x\n", regnum - R0_C_REGNUM, | |
2064 | (unsigned) get_frame_register_unsigned (frame, c_regnum)); | |
2065 | } | |
2066 | else if (regnum >= FP0_C_REGNUM && regnum <= FP_LAST_C_REGNUM) | |
7bb11558 | 2067 | /* This should work also for pseudoregs. */ |
c30dc700 CV |
2068 | sh64_do_fp_register (gdbarch, file, frame, regnum); |
2069 | else if (regnum >= PC_C_REGNUM && regnum <= FPUL_C_REGNUM) | |
2070 | sh64_do_cr_c_register_info (file, frame, regnum); | |
55ff77ac CV |
2071 | } |
2072 | ||
2073 | static void | |
c30dc700 CV |
2074 | sh64_do_register (struct gdbarch *gdbarch, struct ui_file *file, |
2075 | struct frame_info *frame, int regnum) | |
55ff77ac CV |
2076 | { |
2077 | char raw_buffer[MAX_REGISTER_SIZE]; | |
2078 | ||
2079 | fputs_filtered (REGISTER_NAME (regnum), file); | |
2080 | print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file); | |
2081 | ||
2082 | /* Get the data in raw format. */ | |
c30dc700 | 2083 | if (!frame_register_read (frame, regnum, raw_buffer)) |
55ff77ac CV |
2084 | fprintf_filtered (file, "*value not available*\n"); |
2085 | ||
2086 | val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0, | |
2087 | file, 'x', 1, 0, Val_pretty_default); | |
2088 | fprintf_filtered (file, "\t"); | |
2089 | val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0, | |
2090 | file, 0, 1, 0, Val_pretty_default); | |
2091 | fprintf_filtered (file, "\n"); | |
2092 | } | |
2093 | ||
2094 | static void | |
c30dc700 CV |
2095 | sh64_print_register (struct gdbarch *gdbarch, struct ui_file *file, |
2096 | struct frame_info *frame, int regnum) | |
55ff77ac CV |
2097 | { |
2098 | if (regnum < 0 || regnum >= NUM_REGS + NUM_PSEUDO_REGS) | |
2099 | internal_error (__FILE__, __LINE__, | |
e2e0b3e5 | 2100 | _("Invalid register number %d\n"), regnum); |
55ff77ac CV |
2101 | |
2102 | else if (regnum >= 0 && regnum < NUM_REGS) | |
2103 | { | |
2104 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT) | |
c30dc700 | 2105 | sh64_do_fp_register (gdbarch, file, frame, regnum); /* FP regs */ |
55ff77ac | 2106 | else |
c30dc700 | 2107 | sh64_do_register (gdbarch, file, frame, regnum); |
55ff77ac CV |
2108 | } |
2109 | ||
2110 | else if (regnum < NUM_REGS + NUM_PSEUDO_REGS) | |
c30dc700 | 2111 | sh64_do_pseudo_register (gdbarch, file, frame, regnum); |
55ff77ac CV |
2112 | } |
2113 | ||
2114 | static void | |
c30dc700 CV |
2115 | sh64_media_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
2116 | struct frame_info *frame, int regnum, | |
2117 | int fpregs) | |
55ff77ac CV |
2118 | { |
2119 | if (regnum != -1) /* do one specified register */ | |
2120 | { | |
2121 | if (*(REGISTER_NAME (regnum)) == '\0') | |
2122 | error ("Not a valid register for the current processor type"); | |
2123 | ||
c30dc700 | 2124 | sh64_print_register (gdbarch, file, frame, regnum); |
55ff77ac CV |
2125 | } |
2126 | else | |
2127 | /* do all (or most) registers */ | |
2128 | { | |
2129 | regnum = 0; | |
2130 | while (regnum < NUM_REGS) | |
2131 | { | |
2132 | /* If the register name is empty, it is undefined for this | |
2133 | processor, so don't display anything. */ | |
2134 | if (REGISTER_NAME (regnum) == NULL | |
2135 | || *(REGISTER_NAME (regnum)) == '\0') | |
2136 | { | |
2137 | regnum++; | |
2138 | continue; | |
2139 | } | |
2140 | ||
c30dc700 CV |
2141 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) |
2142 | == TYPE_CODE_FLT) | |
55ff77ac CV |
2143 | { |
2144 | if (fpregs) | |
2145 | { | |
2146 | /* true for "INFO ALL-REGISTERS" command */ | |
c30dc700 | 2147 | sh64_do_fp_register (gdbarch, file, frame, regnum); |
55ff77ac CV |
2148 | regnum ++; |
2149 | } | |
2150 | else | |
2151 | regnum += FP_LAST_REGNUM - FP0_REGNUM; /* skip FP regs */ | |
2152 | } | |
2153 | else | |
2154 | { | |
c30dc700 | 2155 | sh64_do_register (gdbarch, file, frame, regnum); |
55ff77ac CV |
2156 | regnum++; |
2157 | } | |
2158 | } | |
2159 | ||
2160 | if (fpregs) | |
2161 | while (regnum < NUM_REGS + NUM_PSEUDO_REGS) | |
2162 | { | |
c30dc700 | 2163 | sh64_do_pseudo_register (gdbarch, file, frame, regnum); |
55ff77ac CV |
2164 | regnum++; |
2165 | } | |
2166 | } | |
2167 | } | |
2168 | ||
2169 | static void | |
c30dc700 CV |
2170 | sh64_compact_print_registers_info (struct gdbarch *gdbarch, |
2171 | struct ui_file *file, | |
2172 | struct frame_info *frame, int regnum, | |
2173 | int fpregs) | |
55ff77ac | 2174 | { |
55ff77ac CV |
2175 | if (regnum != -1) /* do one specified register */ |
2176 | { | |
2177 | if (*(REGISTER_NAME (regnum)) == '\0') | |
2178 | error ("Not a valid register for the current processor type"); | |
2179 | ||
2180 | if (regnum >= 0 && regnum < R0_C_REGNUM) | |
2181 | error ("Not a valid register for the current processor mode."); | |
2182 | ||
c30dc700 | 2183 | sh64_print_register (gdbarch, file, frame, regnum); |
55ff77ac CV |
2184 | } |
2185 | else | |
2186 | /* do all compact registers */ | |
2187 | { | |
2188 | regnum = R0_C_REGNUM; | |
2189 | while (regnum < NUM_REGS + NUM_PSEUDO_REGS) | |
2190 | { | |
c30dc700 | 2191 | sh64_do_pseudo_register (gdbarch, file, frame, regnum); |
55ff77ac CV |
2192 | regnum++; |
2193 | } | |
2194 | } | |
2195 | } | |
2196 | ||
2197 | static void | |
c30dc700 CV |
2198 | sh64_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
2199 | struct frame_info *frame, int regnum, int fpregs) | |
55ff77ac | 2200 | { |
c30dc700 CV |
2201 | if (pc_is_isa32 (get_frame_pc (frame))) |
2202 | sh64_media_print_registers_info (gdbarch, file, frame, regnum, fpregs); | |
55ff77ac | 2203 | else |
c30dc700 | 2204 | sh64_compact_print_registers_info (gdbarch, file, frame, regnum, fpregs); |
55ff77ac CV |
2205 | } |
2206 | ||
c30dc700 CV |
2207 | static struct sh64_frame_cache * |
2208 | sh64_alloc_frame_cache (void) | |
2209 | { | |
2210 | struct sh64_frame_cache *cache; | |
2211 | int i; | |
2212 | ||
2213 | cache = FRAME_OBSTACK_ZALLOC (struct sh64_frame_cache); | |
2214 | ||
2215 | /* Base address. */ | |
2216 | cache->base = 0; | |
2217 | cache->saved_sp = 0; | |
2218 | cache->sp_offset = 0; | |
2219 | cache->pc = 0; | |
55ff77ac | 2220 | |
c30dc700 CV |
2221 | /* Frameless until proven otherwise. */ |
2222 | cache->uses_fp = 0; | |
55ff77ac | 2223 | |
c30dc700 CV |
2224 | /* Saved registers. We initialize these to -1 since zero is a valid |
2225 | offset (that's where fp is supposed to be stored). */ | |
2226 | for (i = 0; i < SIM_SH64_NR_REGS; i++) | |
2227 | { | |
2228 | cache->saved_regs[i] = -1; | |
2229 | } | |
2230 | ||
2231 | return cache; | |
2232 | } | |
2233 | ||
2234 | static struct sh64_frame_cache * | |
2235 | sh64_frame_cache (struct frame_info *next_frame, void **this_cache) | |
55ff77ac | 2236 | { |
c30dc700 CV |
2237 | struct sh64_frame_cache *cache; |
2238 | CORE_ADDR current_pc; | |
2239 | int i; | |
55ff77ac | 2240 | |
c30dc700 CV |
2241 | if (*this_cache) |
2242 | return *this_cache; | |
2243 | ||
2244 | cache = sh64_alloc_frame_cache (); | |
2245 | *this_cache = cache; | |
2246 | ||
2247 | current_pc = frame_pc_unwind (next_frame); | |
2248 | cache->media_mode = pc_is_isa32 (current_pc); | |
2249 | ||
2250 | /* In principle, for normal frames, fp holds the frame pointer, | |
2251 | which holds the base address for the current stack frame. | |
2252 | However, for functions that don't need it, the frame pointer is | |
2253 | optional. For these "frameless" functions the frame pointer is | |
2254 | actually the frame pointer of the calling frame. */ | |
2255 | cache->base = frame_unwind_register_unsigned (next_frame, MEDIA_FP_REGNUM); | |
2256 | if (cache->base == 0) | |
2257 | return cache; | |
2258 | ||
2259 | cache->pc = frame_func_unwind (next_frame); | |
2260 | if (cache->pc != 0) | |
2261 | sh64_analyze_prologue (current_gdbarch, cache, cache->pc, current_pc); | |
2262 | ||
2263 | if (!cache->uses_fp) | |
55ff77ac | 2264 | { |
c30dc700 CV |
2265 | /* We didn't find a valid frame, which means that CACHE->base |
2266 | currently holds the frame pointer for our calling frame. If | |
2267 | we're at the start of a function, or somewhere half-way its | |
2268 | prologue, the function's frame probably hasn't been fully | |
2269 | setup yet. Try to reconstruct the base address for the stack | |
2270 | frame by looking at the stack pointer. For truly "frameless" | |
2271 | functions this might work too. */ | |
2272 | cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM); | |
2273 | } | |
55ff77ac | 2274 | |
c30dc700 CV |
2275 | /* Now that we have the base address for the stack frame we can |
2276 | calculate the value of sp in the calling frame. */ | |
2277 | cache->saved_sp = cache->base + cache->sp_offset; | |
55ff77ac | 2278 | |
c30dc700 CV |
2279 | /* Adjust all the saved registers such that they contain addresses |
2280 | instead of offsets. */ | |
2281 | for (i = 0; i < SIM_SH64_NR_REGS; i++) | |
2282 | if (cache->saved_regs[i] != -1) | |
2283 | cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i]; | |
55ff77ac | 2284 | |
c30dc700 CV |
2285 | return cache; |
2286 | } | |
55ff77ac | 2287 | |
c30dc700 CV |
2288 | static void |
2289 | sh64_frame_prev_register (struct frame_info *next_frame, void **this_cache, | |
2290 | int regnum, int *optimizedp, | |
2291 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
2292 | int *realnump, void *valuep) | |
2293 | { | |
2294 | struct sh64_frame_cache *cache = sh64_frame_cache (next_frame, this_cache); | |
55ff77ac | 2295 | |
c30dc700 | 2296 | gdb_assert (regnum >= 0); |
55ff77ac | 2297 | |
c30dc700 CV |
2298 | if (regnum == SP_REGNUM && cache->saved_sp) |
2299 | { | |
2300 | *optimizedp = 0; | |
2301 | *lvalp = not_lval; | |
2302 | *addrp = 0; | |
2303 | *realnump = -1; | |
2304 | if (valuep) | |
2305 | { | |
2306 | /* Store the value. */ | |
2307 | store_unsigned_integer (valuep, | |
2308 | register_size (current_gdbarch, SP_REGNUM), | |
2309 | cache->saved_sp); | |
2310 | } | |
2311 | return; | |
2312 | } | |
2313 | ||
2314 | /* The PC of the previous frame is stored in the PR register of | |
2315 | the current frame. Frob regnum so that we pull the value from | |
2316 | the correct place. */ | |
2317 | if (regnum == PC_REGNUM) | |
2318 | regnum = PR_REGNUM; | |
2319 | ||
2320 | if (regnum < SIM_SH64_NR_REGS && cache->saved_regs[regnum] != -1) | |
2321 | { | |
2322 | int reg_size = register_size (current_gdbarch, regnum); | |
2323 | int size; | |
55ff77ac | 2324 | |
c30dc700 CV |
2325 | *optimizedp = 0; |
2326 | *lvalp = lval_memory; | |
2327 | *addrp = cache->saved_regs[regnum]; | |
2328 | *realnump = -1; | |
2329 | if (gdbarch_tdep (current_gdbarch)->sh_abi == SH_ABI_32 | |
2330 | && (regnum == MEDIA_FP_REGNUM || regnum == PR_REGNUM)) | |
2331 | size = 4; | |
2332 | else | |
2333 | size = reg_size; | |
2334 | if (valuep) | |
2335 | { | |
2336 | memset (valuep, 0, reg_size); | |
2337 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) | |
2338 | read_memory (*addrp, valuep, size); | |
2339 | else | |
2340 | read_memory (*addrp, (char *) valuep + reg_size - size, size); | |
2341 | } | |
2342 | return; | |
55ff77ac CV |
2343 | } |
2344 | ||
c30dc700 CV |
2345 | *optimizedp = 0; |
2346 | *lvalp = lval_register; | |
2347 | *addrp = 0; | |
2348 | *realnump = regnum; | |
2349 | if (valuep) | |
2350 | frame_unwind_register (next_frame, (*realnump), valuep); | |
55ff77ac | 2351 | } |
55ff77ac | 2352 | |
c30dc700 CV |
2353 | static void |
2354 | sh64_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
2355 | struct frame_id *this_id) | |
2356 | { | |
2357 | struct sh64_frame_cache *cache = sh64_frame_cache (next_frame, this_cache); | |
2358 | ||
2359 | /* This marks the outermost frame. */ | |
2360 | if (cache->base == 0) | |
2361 | return; | |
2362 | ||
2363 | *this_id = frame_id_build (cache->saved_sp, cache->pc); | |
2364 | } | |
2365 | ||
2366 | static const struct frame_unwind sh64_frame_unwind = { | |
2367 | NORMAL_FRAME, | |
2368 | sh64_frame_this_id, | |
2369 | sh64_frame_prev_register | |
2370 | }; | |
2371 | ||
2372 | static const struct frame_unwind * | |
2373 | sh64_frame_sniffer (struct frame_info *next_frame) | |
2374 | { | |
2375 | return &sh64_frame_unwind; | |
2376 | } | |
2377 | ||
2378 | static CORE_ADDR | |
2379 | sh64_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
2380 | { | |
2381 | return frame_unwind_register_unsigned (next_frame, SP_REGNUM); | |
2382 | } | |
2383 | ||
2384 | static CORE_ADDR | |
2385 | sh64_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
2386 | { | |
2387 | return frame_unwind_register_unsigned (next_frame, PC_REGNUM); | |
2388 | } | |
2389 | ||
2390 | static struct frame_id | |
2391 | sh64_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
2392 | { | |
2393 | return frame_id_build (sh64_unwind_sp (gdbarch, next_frame), | |
2394 | frame_pc_unwind (next_frame)); | |
2395 | } | |
2396 | ||
2397 | static CORE_ADDR | |
2398 | sh64_frame_base_address (struct frame_info *next_frame, void **this_cache) | |
2399 | { | |
2400 | struct sh64_frame_cache *cache = sh64_frame_cache (next_frame, this_cache); | |
2401 | ||
2402 | return cache->base; | |
2403 | } | |
2404 | ||
2405 | static const struct frame_base sh64_frame_base = { | |
2406 | &sh64_frame_unwind, | |
2407 | sh64_frame_base_address, | |
2408 | sh64_frame_base_address, | |
2409 | sh64_frame_base_address | |
2410 | }; | |
2411 | ||
55ff77ac CV |
2412 | |
2413 | struct gdbarch * | |
2414 | sh64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
2415 | { | |
55ff77ac CV |
2416 | struct gdbarch *gdbarch; |
2417 | struct gdbarch_tdep *tdep; | |
2418 | ||
2419 | /* If there is already a candidate, use it. */ | |
2420 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
2421 | if (arches != NULL) | |
2422 | return arches->gdbarch; | |
2423 | ||
2424 | /* None found, create a new architecture from the information | |
7bb11558 | 2425 | provided. */ |
55ff77ac CV |
2426 | tdep = XMALLOC (struct gdbarch_tdep); |
2427 | gdbarch = gdbarch_alloc (&info, tdep); | |
2428 | ||
55ff77ac CV |
2429 | /* Determine the ABI */ |
2430 | if (info.abfd && bfd_get_arch_size (info.abfd) == 64) | |
2431 | { | |
7bb11558 | 2432 | /* If the ABI is the 64-bit one, it can only be sh-media. */ |
55ff77ac CV |
2433 | tdep->sh_abi = SH_ABI_64; |
2434 | set_gdbarch_ptr_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
2435 | set_gdbarch_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
2436 | } | |
2437 | else | |
2438 | { | |
2439 | /* If the ABI is the 32-bit one it could be either media or | |
7bb11558 | 2440 | compact. */ |
55ff77ac CV |
2441 | tdep->sh_abi = SH_ABI_32; |
2442 | set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
2443 | set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
2444 | } | |
2445 | ||
2446 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); | |
2447 | set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
c30dc700 | 2448 | set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
55ff77ac CV |
2449 | set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); |
2450 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
2451 | set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
2452 | set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
2453 | ||
c30dc700 CV |
2454 | /* The number of real registers is the same whether we are in |
2455 | ISA16(compact) or ISA32(media). */ | |
2456 | set_gdbarch_num_regs (gdbarch, SIM_SH64_NR_REGS); | |
55ff77ac | 2457 | set_gdbarch_sp_regnum (gdbarch, 15); |
c30dc700 CV |
2458 | set_gdbarch_pc_regnum (gdbarch, 64); |
2459 | set_gdbarch_fp0_regnum (gdbarch, SIM_SH64_FR0_REGNUM); | |
2460 | set_gdbarch_num_pseudo_regs (gdbarch, NUM_PSEUDO_REGS_SH_MEDIA | |
2461 | + NUM_PSEUDO_REGS_SH_COMPACT); | |
55ff77ac | 2462 | |
c30dc700 CV |
2463 | set_gdbarch_register_name (gdbarch, sh64_register_name); |
2464 | set_gdbarch_register_type (gdbarch, sh64_register_type); | |
2465 | ||
2466 | set_gdbarch_pseudo_register_read (gdbarch, sh64_pseudo_register_read); | |
2467 | set_gdbarch_pseudo_register_write (gdbarch, sh64_pseudo_register_write); | |
2468 | ||
2469 | set_gdbarch_breakpoint_from_pc (gdbarch, sh64_breakpoint_from_pc); | |
2470 | ||
2471 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_sh64); | |
55ff77ac CV |
2472 | set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno); |
2473 | ||
2474 | set_gdbarch_write_pc (gdbarch, generic_target_write_pc); | |
2475 | ||
c30dc700 CV |
2476 | set_gdbarch_return_value (gdbarch, sh64_return_value); |
2477 | set_gdbarch_deprecated_extract_struct_value_address (gdbarch, | |
2478 | sh64_extract_struct_value_address); | |
55ff77ac | 2479 | |
c30dc700 CV |
2480 | set_gdbarch_skip_prologue (gdbarch, sh64_skip_prologue); |
2481 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
55ff77ac | 2482 | |
c30dc700 | 2483 | set_gdbarch_push_dummy_call (gdbarch, sh64_push_dummy_call); |
55ff77ac | 2484 | |
c30dc700 | 2485 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); |
55ff77ac | 2486 | |
c30dc700 CV |
2487 | set_gdbarch_frame_align (gdbarch, sh64_frame_align); |
2488 | set_gdbarch_unwind_sp (gdbarch, sh64_unwind_sp); | |
2489 | set_gdbarch_unwind_pc (gdbarch, sh64_unwind_pc); | |
2490 | set_gdbarch_unwind_dummy_id (gdbarch, sh64_unwind_dummy_id); | |
2491 | frame_base_set_default (gdbarch, &sh64_frame_base); | |
55ff77ac | 2492 | |
c30dc700 | 2493 | set_gdbarch_print_registers_info (gdbarch, sh64_print_registers_info); |
55ff77ac | 2494 | |
55ff77ac CV |
2495 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
2496 | sh64_elf_make_msymbol_special); | |
2497 | ||
2498 | /* Hook in ABI-specific overrides, if they have been registered. */ | |
2499 | gdbarch_init_osabi (info, gdbarch); | |
2500 | ||
c30dc700 CV |
2501 | frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer); |
2502 | frame_unwind_append_sniffer (gdbarch, sh64_frame_sniffer); | |
2503 | ||
55ff77ac CV |
2504 | return gdbarch; |
2505 | } |