Commit | Line | Data |
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85a453d5 | 1 | /* Target-dependent code for Renesas Super-H, for GDB. |
cf5b2f1b | 2 | |
0b302171 | 3 | Copyright (C) 1993-2005, 2007-2012 Free Software Foundation, Inc. |
55ff77ac CV |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
55ff77ac CV |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
55ff77ac | 19 | |
c378eb4e MS |
20 | /* Contributed by Steve Chamberlain |
21 | sac@cygnus.com. */ | |
55ff77ac CV |
22 | |
23 | #include "defs.h" | |
24 | #include "frame.h" | |
c30dc700 CV |
25 | #include "frame-base.h" |
26 | #include "frame-unwind.h" | |
27 | #include "dwarf2-frame.h" | |
55ff77ac | 28 | #include "symtab.h" |
55ff77ac CV |
29 | #include "gdbtypes.h" |
30 | #include "gdbcmd.h" | |
31 | #include "gdbcore.h" | |
32 | #include "value.h" | |
33 | #include "dis-asm.h" | |
34 | #include "inferior.h" | |
35 | #include "gdb_string.h" | |
c30dc700 | 36 | #include "gdb_assert.h" |
55ff77ac | 37 | #include "arch-utils.h" |
55ff77ac | 38 | #include "regcache.h" |
55ff77ac | 39 | #include "osabi.h" |
79a45b7d | 40 | #include "valprint.h" |
55ff77ac CV |
41 | |
42 | #include "elf-bfd.h" | |
55ff77ac CV |
43 | |
44 | /* sh flags */ | |
45 | #include "elf/sh.h" | |
c378eb4e | 46 | /* Register numbers shared with the simulator. */ |
55ff77ac | 47 | #include "gdb/sim-sh.h" |
d8ca156b | 48 | #include "language.h" |
55ff77ac | 49 | |
7bb11558 | 50 | /* Information that is dependent on the processor variant. */ |
55ff77ac CV |
51 | enum sh_abi |
52 | { | |
53 | SH_ABI_UNKNOWN, | |
54 | SH_ABI_32, | |
55 | SH_ABI_64 | |
56 | }; | |
57 | ||
58 | struct gdbarch_tdep | |
59 | { | |
60 | enum sh_abi sh_abi; | |
61 | }; | |
62 | ||
c30dc700 CV |
63 | struct sh64_frame_cache |
64 | { | |
65 | /* Base address. */ | |
66 | CORE_ADDR base; | |
67 | LONGEST sp_offset; | |
68 | CORE_ADDR pc; | |
69 | ||
c378eb4e | 70 | /* Flag showing that a frame has been created in the prologue code. */ |
c30dc700 CV |
71 | int uses_fp; |
72 | ||
73 | int media_mode; | |
74 | ||
75 | /* Saved registers. */ | |
76 | CORE_ADDR saved_regs[SIM_SH64_NR_REGS]; | |
77 | CORE_ADDR saved_sp; | |
78 | }; | |
79 | ||
55ff77ac CV |
80 | /* Registers of SH5 */ |
81 | enum | |
82 | { | |
83 | R0_REGNUM = 0, | |
84 | DEFAULT_RETURN_REGNUM = 2, | |
85 | STRUCT_RETURN_REGNUM = 2, | |
86 | ARG0_REGNUM = 2, | |
87 | ARGLAST_REGNUM = 9, | |
88 | FLOAT_ARGLAST_REGNUM = 11, | |
c30dc700 | 89 | MEDIA_FP_REGNUM = 14, |
55ff77ac CV |
90 | PR_REGNUM = 18, |
91 | SR_REGNUM = 65, | |
92 | DR0_REGNUM = 141, | |
93 | DR_LAST_REGNUM = 172, | |
94 | /* FPP stands for Floating Point Pair, to avoid confusion with | |
3e8c568d | 95 | GDB's gdbarch_fp0_regnum, which is the number of the first Floating |
c378eb4e | 96 | point register. Unfortunately on the sh5, the floating point |
7bb11558 | 97 | registers are called FR, and the floating point pairs are called FP. */ |
55ff77ac CV |
98 | FPP0_REGNUM = 173, |
99 | FPP_LAST_REGNUM = 204, | |
100 | FV0_REGNUM = 205, | |
101 | FV_LAST_REGNUM = 220, | |
102 | R0_C_REGNUM = 221, | |
103 | R_LAST_C_REGNUM = 236, | |
104 | PC_C_REGNUM = 237, | |
105 | GBR_C_REGNUM = 238, | |
106 | MACH_C_REGNUM = 239, | |
107 | MACL_C_REGNUM = 240, | |
108 | PR_C_REGNUM = 241, | |
109 | T_C_REGNUM = 242, | |
110 | FPSCR_C_REGNUM = 243, | |
111 | FPUL_C_REGNUM = 244, | |
112 | FP0_C_REGNUM = 245, | |
113 | FP_LAST_C_REGNUM = 260, | |
114 | DR0_C_REGNUM = 261, | |
115 | DR_LAST_C_REGNUM = 268, | |
116 | FV0_C_REGNUM = 269, | |
117 | FV_LAST_C_REGNUM = 272, | |
118 | FPSCR_REGNUM = SIM_SH64_FPCSR_REGNUM, | |
119 | SSR_REGNUM = SIM_SH64_SSR_REGNUM, | |
120 | SPC_REGNUM = SIM_SH64_SPC_REGNUM, | |
121 | TR7_REGNUM = SIM_SH64_TR0_REGNUM + 7, | |
122 | FP_LAST_REGNUM = SIM_SH64_FR0_REGNUM + SIM_SH64_NR_FP_REGS - 1 | |
123 | }; | |
124 | ||
55ff77ac | 125 | static const char * |
d93859e2 | 126 | sh64_register_name (struct gdbarch *gdbarch, int reg_nr) |
55ff77ac CV |
127 | { |
128 | static char *register_names[] = | |
129 | { | |
130 | /* SH MEDIA MODE (ISA 32) */ | |
131 | /* general registers (64-bit) 0-63 */ | |
132 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
133 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
134 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
135 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", | |
136 | "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", | |
137 | "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", | |
138 | "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", | |
139 | "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", | |
140 | ||
141 | /* pc (64-bit) 64 */ | |
142 | "pc", | |
143 | ||
144 | /* status reg., saved status reg., saved pc reg. (64-bit) 65-67 */ | |
145 | "sr", "ssr", "spc", | |
146 | ||
c378eb4e | 147 | /* target registers (64-bit) 68-75 */ |
55ff77ac CV |
148 | "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", |
149 | ||
150 | /* floating point state control register (32-bit) 76 */ | |
151 | "fpscr", | |
152 | ||
c378eb4e | 153 | /* single precision floating point registers (32-bit) 77-140 */ |
55ff77ac CV |
154 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", |
155 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
156 | "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", | |
157 | "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", | |
158 | "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", | |
159 | "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", | |
160 | "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", | |
161 | "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", | |
162 | ||
163 | /* double precision registers (pseudo) 141-172 */ | |
164 | "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", | |
165 | "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", | |
166 | "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", | |
167 | "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62", | |
168 | ||
c378eb4e | 169 | /* floating point pairs (pseudo) 173-204 */ |
55ff77ac CV |
170 | "fp0", "fp2", "fp4", "fp6", "fp8", "fp10", "fp12", "fp14", |
171 | "fp16", "fp18", "fp20", "fp22", "fp24", "fp26", "fp28", "fp30", | |
172 | "fp32", "fp34", "fp36", "fp38", "fp40", "fp42", "fp44", "fp46", | |
173 | "fp48", "fp50", "fp52", "fp54", "fp56", "fp58", "fp60", "fp62", | |
174 | ||
c378eb4e | 175 | /* floating point vectors (4 floating point regs) (pseudo) 205-220 */ |
55ff77ac CV |
176 | "fv0", "fv4", "fv8", "fv12", "fv16", "fv20", "fv24", "fv28", |
177 | "fv32", "fv36", "fv40", "fv44", "fv48", "fv52", "fv56", "fv60", | |
178 | ||
c378eb4e | 179 | /* SH COMPACT MODE (ISA 16) (all pseudo) 221-272 */ |
55ff77ac CV |
180 | "r0_c", "r1_c", "r2_c", "r3_c", "r4_c", "r5_c", "r6_c", "r7_c", |
181 | "r8_c", "r9_c", "r10_c", "r11_c", "r12_c", "r13_c", "r14_c", "r15_c", | |
182 | "pc_c", | |
183 | "gbr_c", "mach_c", "macl_c", "pr_c", "t_c", | |
184 | "fpscr_c", "fpul_c", | |
c378eb4e MS |
185 | "fr0_c", "fr1_c", "fr2_c", "fr3_c", |
186 | "fr4_c", "fr5_c", "fr6_c", "fr7_c", | |
187 | "fr8_c", "fr9_c", "fr10_c", "fr11_c", | |
188 | "fr12_c", "fr13_c", "fr14_c", "fr15_c", | |
189 | "dr0_c", "dr2_c", "dr4_c", "dr6_c", | |
190 | "dr8_c", "dr10_c", "dr12_c", "dr14_c", | |
55ff77ac | 191 | "fv0_c", "fv4_c", "fv8_c", "fv12_c", |
c378eb4e | 192 | /* FIXME!!!! XF0 XF15, XD0 XD14 ????? */ |
55ff77ac CV |
193 | }; |
194 | ||
195 | if (reg_nr < 0) | |
196 | return NULL; | |
197 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
198 | return NULL; | |
199 | return register_names[reg_nr]; | |
200 | } | |
201 | ||
202 | #define NUM_PSEUDO_REGS_SH_MEDIA 80 | |
203 | #define NUM_PSEUDO_REGS_SH_COMPACT 51 | |
204 | ||
205 | /* Macros and functions for setting and testing a bit in a minimal | |
206 | symbol that marks it as 32-bit function. The MSB of the minimal | |
f594e5e9 | 207 | symbol's "info" field is used for this purpose. |
55ff77ac | 208 | |
95f1da47 UW |
209 | gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special", |
210 | i.e. refers to a 32-bit function, and sets a "special" bit in a | |
55ff77ac | 211 | minimal symbol to mark it as a 32-bit function |
f594e5e9 | 212 | MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */ |
55ff77ac CV |
213 | |
214 | #define MSYMBOL_IS_SPECIAL(msym) \ | |
b887350f | 215 | MSYMBOL_TARGET_FLAG_1 (msym) |
55ff77ac CV |
216 | |
217 | static void | |
218 | sh64_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym) | |
219 | { | |
220 | if (msym == NULL) | |
221 | return; | |
222 | ||
223 | if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_SH5_ISA32) | |
224 | { | |
b887350f | 225 | MSYMBOL_TARGET_FLAG_1 (msym) = 1; |
55ff77ac CV |
226 | SYMBOL_VALUE_ADDRESS (msym) |= 1; |
227 | } | |
228 | } | |
229 | ||
230 | /* ISA32 (shmedia) function addresses are odd (bit 0 is set). Here | |
231 | are some macros to test, set, or clear bit 0 of addresses. */ | |
232 | #define IS_ISA32_ADDR(addr) ((addr) & 1) | |
233 | #define MAKE_ISA32_ADDR(addr) ((addr) | 1) | |
234 | #define UNMAKE_ISA32_ADDR(addr) ((addr) & ~1) | |
235 | ||
236 | static int | |
237 | pc_is_isa32 (bfd_vma memaddr) | |
238 | { | |
239 | struct minimal_symbol *sym; | |
240 | ||
241 | /* If bit 0 of the address is set, assume this is a | |
7bb11558 | 242 | ISA32 (shmedia) address. */ |
55ff77ac CV |
243 | if (IS_ISA32_ADDR (memaddr)) |
244 | return 1; | |
245 | ||
246 | /* A flag indicating that this is a ISA32 function is stored by elfread.c in | |
247 | the high bit of the info field. Use this to decide if the function is | |
248 | ISA16 or ISA32. */ | |
249 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
250 | if (sym) | |
251 | return MSYMBOL_IS_SPECIAL (sym); | |
252 | else | |
253 | return 0; | |
254 | } | |
255 | ||
256 | static const unsigned char * | |
c378eb4e MS |
257 | sh64_breakpoint_from_pc (struct gdbarch *gdbarch, |
258 | CORE_ADDR *pcptr, int *lenptr) | |
55ff77ac CV |
259 | { |
260 | /* The BRK instruction for shmedia is | |
261 | 01101111 11110101 11111111 11110000 | |
262 | which translates in big endian mode to 0x6f, 0xf5, 0xff, 0xf0 | |
263 | and in little endian mode to 0xf0, 0xff, 0xf5, 0x6f */ | |
264 | ||
265 | /* The BRK instruction for shcompact is | |
266 | 00000000 00111011 | |
267 | which translates in big endian mode to 0x0, 0x3b | |
c378eb4e | 268 | and in little endian mode to 0x3b, 0x0 */ |
55ff77ac | 269 | |
67d57894 | 270 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
55ff77ac CV |
271 | { |
272 | if (pc_is_isa32 (*pcptr)) | |
273 | { | |
c378eb4e MS |
274 | static unsigned char big_breakpoint_media[] = { |
275 | 0x6f, 0xf5, 0xff, 0xf0 | |
276 | }; | |
55ff77ac CV |
277 | *pcptr = UNMAKE_ISA32_ADDR (*pcptr); |
278 | *lenptr = sizeof (big_breakpoint_media); | |
279 | return big_breakpoint_media; | |
280 | } | |
281 | else | |
282 | { | |
283 | static unsigned char big_breakpoint_compact[] = {0x0, 0x3b}; | |
284 | *lenptr = sizeof (big_breakpoint_compact); | |
285 | return big_breakpoint_compact; | |
286 | } | |
287 | } | |
288 | else | |
289 | { | |
290 | if (pc_is_isa32 (*pcptr)) | |
291 | { | |
c378eb4e MS |
292 | static unsigned char little_breakpoint_media[] = { |
293 | 0xf0, 0xff, 0xf5, 0x6f | |
294 | }; | |
55ff77ac CV |
295 | *pcptr = UNMAKE_ISA32_ADDR (*pcptr); |
296 | *lenptr = sizeof (little_breakpoint_media); | |
297 | return little_breakpoint_media; | |
298 | } | |
299 | else | |
300 | { | |
301 | static unsigned char little_breakpoint_compact[] = {0x3b, 0x0}; | |
302 | *lenptr = sizeof (little_breakpoint_compact); | |
303 | return little_breakpoint_compact; | |
304 | } | |
305 | } | |
306 | } | |
307 | ||
308 | /* Prologue looks like | |
309 | [mov.l <regs>,@-r15]... | |
310 | [sts.l pr,@-r15] | |
311 | [mov.l r14,@-r15] | |
312 | [mov r15,r14] | |
313 | ||
314 | Actually it can be more complicated than this. For instance, with | |
315 | newer gcc's: | |
316 | ||
317 | mov.l r14,@-r15 | |
318 | add #-12,r15 | |
319 | mov r15,r14 | |
320 | mov r4,r1 | |
321 | mov r5,r2 | |
322 | mov.l r6,@(4,r14) | |
323 | mov.l r7,@(8,r14) | |
324 | mov.b r1,@r14 | |
325 | mov r14,r1 | |
326 | mov r14,r1 | |
327 | add #2,r1 | |
328 | mov.w r2,@r1 | |
329 | ||
330 | */ | |
331 | ||
332 | /* PTABS/L Rn, TRa 0110101111110001nnnnnnl00aaa0000 | |
333 | with l=1 and n = 18 0110101111110001010010100aaa0000 */ | |
334 | #define IS_PTABSL_R18(x) (((x) & 0xffffff8f) == 0x6bf14a00) | |
335 | ||
336 | /* STS.L PR,@-r0 0100000000100010 | |
337 | r0-4-->r0, PR-->(r0) */ | |
338 | #define IS_STS_R0(x) ((x) == 0x4022) | |
339 | ||
340 | /* STS PR, Rm 0000mmmm00101010 | |
341 | PR-->Rm */ | |
342 | #define IS_STS_PR(x) (((x) & 0xf0ff) == 0x2a) | |
343 | ||
344 | /* MOV.L Rm,@(disp,r15) 00011111mmmmdddd | |
345 | Rm-->(dispx4+r15) */ | |
346 | #define IS_MOV_TO_R15(x) (((x) & 0xff00) == 0x1f00) | |
347 | ||
348 | /* MOV.L R14,@(disp,r15) 000111111110dddd | |
349 | R14-->(dispx4+r15) */ | |
350 | #define IS_MOV_R14(x) (((x) & 0xfff0) == 0x1fe0) | |
351 | ||
352 | /* ST.Q R14, disp, R18 101011001110dddddddddd0100100000 | |
353 | R18-->(dispx8+R14) */ | |
354 | #define IS_STQ_R18_R14(x) (((x) & 0xfff003ff) == 0xace00120) | |
355 | ||
356 | /* ST.Q R15, disp, R18 101011001111dddddddddd0100100000 | |
357 | R18-->(dispx8+R15) */ | |
358 | #define IS_STQ_R18_R15(x) (((x) & 0xfff003ff) == 0xacf00120) | |
359 | ||
360 | /* ST.L R15, disp, R18 101010001111dddddddddd0100100000 | |
361 | R18-->(dispx4+R15) */ | |
362 | #define IS_STL_R18_R15(x) (((x) & 0xfff003ff) == 0xa8f00120) | |
363 | ||
364 | /* ST.Q R15, disp, R14 1010 1100 1111 dddd dddd dd00 1110 0000 | |
365 | R14-->(dispx8+R15) */ | |
366 | #define IS_STQ_R14_R15(x) (((x) & 0xfff003ff) == 0xacf000e0) | |
367 | ||
368 | /* ST.L R15, disp, R14 1010 1000 1111 dddd dddd dd00 1110 0000 | |
369 | R14-->(dispx4+R15) */ | |
370 | #define IS_STL_R14_R15(x) (((x) & 0xfff003ff) == 0xa8f000e0) | |
371 | ||
372 | /* ADDI.L R15,imm,R15 1101 0100 1111 ssss ssss ss00 1111 0000 | |
373 | R15 + imm --> R15 */ | |
374 | #define IS_ADDIL_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd4f000f0) | |
375 | ||
376 | /* ADDI R15,imm,R15 1101 0000 1111 ssss ssss ss00 1111 0000 | |
377 | R15 + imm --> R15 */ | |
378 | #define IS_ADDI_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd0f000f0) | |
379 | ||
380 | /* ADD.L R15,R63,R14 0000 0000 1111 1000 1111 1100 1110 0000 | |
381 | R15 + R63 --> R14 */ | |
382 | #define IS_ADDL_SP_FP_MEDIA(x) ((x) == 0x00f8fce0) | |
383 | ||
384 | /* ADD R15,R63,R14 0000 0000 1111 1001 1111 1100 1110 0000 | |
385 | R15 + R63 --> R14 */ | |
386 | #define IS_ADD_SP_FP_MEDIA(x) ((x) == 0x00f9fce0) | |
387 | ||
c378eb4e MS |
388 | #define IS_MOV_SP_FP_MEDIA(x) \ |
389 | (IS_ADDL_SP_FP_MEDIA(x) || IS_ADD_SP_FP_MEDIA(x)) | |
55ff77ac CV |
390 | |
391 | /* MOV #imm, R0 1110 0000 ssss ssss | |
392 | #imm-->R0 */ | |
393 | #define IS_MOV_R0(x) (((x) & 0xff00) == 0xe000) | |
394 | ||
395 | /* MOV.L @(disp,PC), R0 1101 0000 iiii iiii */ | |
396 | #define IS_MOVL_R0(x) (((x) & 0xff00) == 0xd000) | |
397 | ||
398 | /* ADD r15,r0 0011 0000 1111 1100 | |
399 | r15+r0-->r0 */ | |
400 | #define IS_ADD_SP_R0(x) ((x) == 0x30fc) | |
401 | ||
402 | /* MOV.L R14 @-R0 0010 0000 1110 0110 | |
403 | R14-->(R0-4), R0-4-->R0 */ | |
404 | #define IS_MOV_R14_R0(x) ((x) == 0x20e6) | |
405 | ||
406 | /* ADD Rm,R63,Rn Rm+R63-->Rn 0000 00mm mmmm 1001 1111 11nn nnnn 0000 | |
7bb11558 | 407 | where Rm is one of r2-r9 which are the argument registers. */ |
c378eb4e | 408 | /* FIXME: Recognize the float and double register moves too! */ |
55ff77ac | 409 | #define IS_MEDIA_IND_ARG_MOV(x) \ |
c378eb4e MS |
410 | ((((x) & 0xfc0ffc0f) == 0x0009fc00) \ |
411 | && (((x) & 0x03f00000) >= 0x00200000 \ | |
412 | && ((x) & 0x03f00000) <= 0x00900000)) | |
55ff77ac CV |
413 | |
414 | /* ST.Q Rn,0,Rm Rm-->Rn+0 1010 11nn nnnn 0000 0000 00mm mmmm 0000 | |
415 | or ST.L Rn,0,Rm Rm-->Rn+0 1010 10nn nnnn 0000 0000 00mm mmmm 0000 | |
7bb11558 | 416 | where Rm is one of r2-r9 which are the argument registers. */ |
55ff77ac CV |
417 | #define IS_MEDIA_ARG_MOV(x) \ |
418 | (((((x) & 0xfc0ffc0f) == 0xac000000) || (((x) & 0xfc0ffc0f) == 0xa8000000)) \ | |
419 | && (((x) & 0x000003f0) >= 0x00000020 && ((x) & 0x000003f0) <= 0x00000090)) | |
420 | ||
c378eb4e MS |
421 | /* ST.B R14,0,Rn Rn-->(R14+0) 1010 0000 1110 0000 0000 00nn nnnn 0000 */ |
422 | /* ST.W R14,0,Rn Rn-->(R14+0) 1010 0100 1110 0000 0000 00nn nnnn 0000 */ | |
423 | /* ST.L R14,0,Rn Rn-->(R14+0) 1010 1000 1110 0000 0000 00nn nnnn 0000 */ | |
424 | /* FST.S R14,0,FRn Rn-->(R14+0) 1011 0100 1110 0000 0000 00nn nnnn 0000 */ | |
425 | /* FST.D R14,0,DRn Rn-->(R14+0) 1011 1100 1110 0000 0000 00nn nnnn 0000 */ | |
55ff77ac CV |
426 | #define IS_MEDIA_MOV_TO_R14(x) \ |
427 | ((((x) & 0xfffffc0f) == 0xa0e00000) \ | |
428 | || (((x) & 0xfffffc0f) == 0xa4e00000) \ | |
429 | || (((x) & 0xfffffc0f) == 0xa8e00000) \ | |
430 | || (((x) & 0xfffffc0f) == 0xb4e00000) \ | |
431 | || (((x) & 0xfffffc0f) == 0xbce00000)) | |
432 | ||
433 | /* MOV Rm, Rn Rm-->Rn 0110 nnnn mmmm 0011 | |
434 | where Rm is r2-r9 */ | |
435 | #define IS_COMPACT_IND_ARG_MOV(x) \ | |
c378eb4e MS |
436 | ((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0020) \ |
437 | && (((x) & 0x00f0) <= 0x0090)) | |
55ff77ac CV |
438 | |
439 | /* compact direct arg move! | |
440 | MOV.L Rn, @r14 0010 1110 mmmm 0010 */ | |
441 | #define IS_COMPACT_ARG_MOV(x) \ | |
c378eb4e MS |
442 | (((((x) & 0xff0f) == 0x2e02) && (((x) & 0x00f0) >= 0x0020) \ |
443 | && ((x) & 0x00f0) <= 0x0090)) | |
55ff77ac CV |
444 | |
445 | /* MOV.B Rm, @R14 0010 1110 mmmm 0000 | |
446 | MOV.W Rm, @R14 0010 1110 mmmm 0001 */ | |
447 | #define IS_COMPACT_MOV_TO_R14(x) \ | |
448 | ((((x) & 0xff0f) == 0x2e00) || (((x) & 0xff0f) == 0x2e01)) | |
449 | ||
450 | #define IS_JSR_R0(x) ((x) == 0x400b) | |
451 | #define IS_NOP(x) ((x) == 0x0009) | |
452 | ||
453 | ||
454 | /* MOV r15,r14 0110111011110011 | |
455 | r15-->r14 */ | |
456 | #define IS_MOV_SP_FP(x) ((x) == 0x6ef3) | |
457 | ||
458 | /* ADD #imm,r15 01111111iiiiiiii | |
459 | r15+imm-->r15 */ | |
460 | #define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00) | |
461 | ||
c378eb4e | 462 | /* Skip any prologue before the guts of a function. */ |
55ff77ac | 463 | |
7bb11558 MS |
464 | /* Skip the prologue using the debug information. If this fails we'll |
465 | fall back on the 'guess' method below. */ | |
55ff77ac CV |
466 | static CORE_ADDR |
467 | after_prologue (CORE_ADDR pc) | |
468 | { | |
469 | struct symtab_and_line sal; | |
470 | CORE_ADDR func_addr, func_end; | |
471 | ||
472 | /* If we can not find the symbol in the partial symbol table, then | |
473 | there is no hope we can determine the function's start address | |
474 | with this code. */ | |
475 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
476 | return 0; | |
477 | ||
c30dc700 | 478 | |
55ff77ac CV |
479 | /* Get the line associated with FUNC_ADDR. */ |
480 | sal = find_pc_line (func_addr, 0); | |
481 | ||
482 | /* There are only two cases to consider. First, the end of the source line | |
483 | is within the function bounds. In that case we return the end of the | |
484 | source line. Second is the end of the source line extends beyond the | |
485 | bounds of the current function. We need to use the slow code to | |
486 | examine instructions in that case. */ | |
487 | if (sal.end < func_end) | |
488 | return sal.end; | |
489 | else | |
490 | return 0; | |
491 | } | |
492 | ||
493 | static CORE_ADDR | |
e17a4113 UW |
494 | look_for_args_moves (struct gdbarch *gdbarch, |
495 | CORE_ADDR start_pc, int media_mode) | |
55ff77ac | 496 | { |
e17a4113 | 497 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
55ff77ac CV |
498 | CORE_ADDR here, end; |
499 | int w; | |
500 | int insn_size = (media_mode ? 4 : 2); | |
501 | ||
502 | for (here = start_pc, end = start_pc + (insn_size * 28); here < end;) | |
503 | { | |
504 | if (media_mode) | |
505 | { | |
e17a4113 UW |
506 | w = read_memory_integer (UNMAKE_ISA32_ADDR (here), |
507 | insn_size, byte_order); | |
55ff77ac CV |
508 | here += insn_size; |
509 | if (IS_MEDIA_IND_ARG_MOV (w)) | |
510 | { | |
511 | /* This must be followed by a store to r14, so the argument | |
c378eb4e | 512 | is where the debug info says it is. This can happen after |
7bb11558 | 513 | the SP has been saved, unfortunately. */ |
55ff77ac CV |
514 | |
515 | int next_insn = read_memory_integer (UNMAKE_ISA32_ADDR (here), | |
e17a4113 | 516 | insn_size, byte_order); |
55ff77ac CV |
517 | here += insn_size; |
518 | if (IS_MEDIA_MOV_TO_R14 (next_insn)) | |
519 | start_pc = here; | |
520 | } | |
521 | else if (IS_MEDIA_ARG_MOV (w)) | |
522 | { | |
7bb11558 | 523 | /* These instructions store directly the argument in r14. */ |
55ff77ac CV |
524 | start_pc = here; |
525 | } | |
526 | else | |
527 | break; | |
528 | } | |
529 | else | |
530 | { | |
e17a4113 | 531 | w = read_memory_integer (here, insn_size, byte_order); |
55ff77ac CV |
532 | w = w & 0xffff; |
533 | here += insn_size; | |
534 | if (IS_COMPACT_IND_ARG_MOV (w)) | |
535 | { | |
536 | /* This must be followed by a store to r14, so the argument | |
c378eb4e | 537 | is where the debug info says it is. This can happen after |
7bb11558 | 538 | the SP has been saved, unfortunately. */ |
55ff77ac | 539 | |
e17a4113 UW |
540 | int next_insn = 0xffff & read_memory_integer (here, insn_size, |
541 | byte_order); | |
55ff77ac CV |
542 | here += insn_size; |
543 | if (IS_COMPACT_MOV_TO_R14 (next_insn)) | |
544 | start_pc = here; | |
545 | } | |
546 | else if (IS_COMPACT_ARG_MOV (w)) | |
547 | { | |
7bb11558 | 548 | /* These instructions store directly the argument in r14. */ |
55ff77ac CV |
549 | start_pc = here; |
550 | } | |
551 | else if (IS_MOVL_R0 (w)) | |
552 | { | |
553 | /* There is a function that gcc calls to get the arguments | |
c378eb4e | 554 | passed correctly to the function. Only after this |
55ff77ac | 555 | function call the arguments will be found at the place |
c378eb4e | 556 | where they are supposed to be. This happens in case the |
55ff77ac CV |
557 | argument has to be stored into a 64-bit register (for |
558 | instance doubles, long longs). SHcompact doesn't have | |
559 | access to the full 64-bits, so we store the register in | |
560 | stack slot and store the address of the stack slot in | |
561 | the register, then do a call through a wrapper that | |
562 | loads the memory value into the register. A SHcompact | |
563 | callee calls an argument decoder | |
564 | (GCC_shcompact_incoming_args) that stores the 64-bit | |
565 | value in a stack slot and stores the address of the | |
566 | stack slot in the register. GCC thinks the argument is | |
567 | just passed by transparent reference, but this is only | |
c378eb4e | 568 | true after the argument decoder is called. Such a call |
7bb11558 | 569 | needs to be considered part of the prologue. */ |
55ff77ac CV |
570 | |
571 | /* This must be followed by a JSR @r0 instruction and by | |
c378eb4e | 572 | a NOP instruction. After these, the prologue is over! */ |
55ff77ac | 573 | |
e17a4113 UW |
574 | int next_insn = 0xffff & read_memory_integer (here, insn_size, |
575 | byte_order); | |
55ff77ac CV |
576 | here += insn_size; |
577 | if (IS_JSR_R0 (next_insn)) | |
578 | { | |
e17a4113 UW |
579 | next_insn = 0xffff & read_memory_integer (here, insn_size, |
580 | byte_order); | |
55ff77ac CV |
581 | here += insn_size; |
582 | ||
583 | if (IS_NOP (next_insn)) | |
584 | start_pc = here; | |
585 | } | |
586 | } | |
587 | else | |
588 | break; | |
589 | } | |
590 | } | |
591 | ||
592 | return start_pc; | |
593 | } | |
594 | ||
595 | static CORE_ADDR | |
e17a4113 | 596 | sh64_skip_prologue_hard_way (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
55ff77ac | 597 | { |
e17a4113 | 598 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
55ff77ac CV |
599 | CORE_ADDR here, end; |
600 | int updated_fp = 0; | |
601 | int insn_size = 4; | |
602 | int media_mode = 1; | |
603 | ||
604 | if (!start_pc) | |
605 | return 0; | |
606 | ||
607 | if (pc_is_isa32 (start_pc) == 0) | |
608 | { | |
609 | insn_size = 2; | |
610 | media_mode = 0; | |
611 | } | |
612 | ||
613 | for (here = start_pc, end = start_pc + (insn_size * 28); here < end;) | |
614 | { | |
615 | ||
616 | if (media_mode) | |
617 | { | |
e17a4113 UW |
618 | int w = read_memory_integer (UNMAKE_ISA32_ADDR (here), |
619 | insn_size, byte_order); | |
55ff77ac CV |
620 | here += insn_size; |
621 | if (IS_STQ_R18_R14 (w) || IS_STQ_R18_R15 (w) || IS_STQ_R14_R15 (w) | |
622 | || IS_STL_R14_R15 (w) || IS_STL_R18_R15 (w) | |
c378eb4e MS |
623 | || IS_ADDIL_SP_MEDIA (w) || IS_ADDI_SP_MEDIA (w) |
624 | || IS_PTABSL_R18 (w)) | |
55ff77ac CV |
625 | { |
626 | start_pc = here; | |
627 | } | |
628 | else if (IS_MOV_SP_FP (w) || IS_MOV_SP_FP_MEDIA(w)) | |
629 | { | |
630 | start_pc = here; | |
631 | updated_fp = 1; | |
632 | } | |
633 | else | |
634 | if (updated_fp) | |
635 | { | |
636 | /* Don't bail out yet, we may have arguments stored in | |
637 | registers here, according to the debug info, so that | |
7bb11558 | 638 | gdb can print the frames correctly. */ |
e17a4113 UW |
639 | start_pc = look_for_args_moves (gdbarch, |
640 | here - insn_size, media_mode); | |
55ff77ac CV |
641 | break; |
642 | } | |
643 | } | |
644 | else | |
645 | { | |
e17a4113 | 646 | int w = 0xffff & read_memory_integer (here, insn_size, byte_order); |
55ff77ac CV |
647 | here += insn_size; |
648 | ||
649 | if (IS_STS_R0 (w) || IS_STS_PR (w) | |
650 | || IS_MOV_TO_R15 (w) || IS_MOV_R14 (w) | |
651 | || IS_MOV_R0 (w) || IS_ADD_SP_R0 (w) || IS_MOV_R14_R0 (w)) | |
652 | { | |
653 | start_pc = here; | |
654 | } | |
655 | else if (IS_MOV_SP_FP (w)) | |
656 | { | |
657 | start_pc = here; | |
658 | updated_fp = 1; | |
659 | } | |
660 | else | |
661 | if (updated_fp) | |
662 | { | |
663 | /* Don't bail out yet, we may have arguments stored in | |
664 | registers here, according to the debug info, so that | |
7bb11558 | 665 | gdb can print the frames correctly. */ |
e17a4113 UW |
666 | start_pc = look_for_args_moves (gdbarch, |
667 | here - insn_size, media_mode); | |
55ff77ac CV |
668 | break; |
669 | } | |
670 | } | |
671 | } | |
672 | ||
673 | return start_pc; | |
674 | } | |
675 | ||
676 | static CORE_ADDR | |
6093d2eb | 677 | sh64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
55ff77ac CV |
678 | { |
679 | CORE_ADDR post_prologue_pc; | |
680 | ||
681 | /* See if we can determine the end of the prologue via the symbol table. | |
682 | If so, then return either PC, or the PC after the prologue, whichever | |
683 | is greater. */ | |
684 | post_prologue_pc = after_prologue (pc); | |
685 | ||
686 | /* If after_prologue returned a useful address, then use it. Else | |
7bb11558 | 687 | fall back on the instruction skipping code. */ |
55ff77ac CV |
688 | if (post_prologue_pc != 0) |
689 | return max (pc, post_prologue_pc); | |
690 | else | |
e17a4113 | 691 | return sh64_skip_prologue_hard_way (gdbarch, pc); |
55ff77ac CV |
692 | } |
693 | ||
55ff77ac CV |
694 | /* Should call_function allocate stack space for a struct return? */ |
695 | static int | |
c30dc700 | 696 | sh64_use_struct_convention (struct type *type) |
55ff77ac CV |
697 | { |
698 | return (TYPE_LENGTH (type) > 8); | |
699 | } | |
700 | ||
7bb11558 | 701 | /* For vectors of 4 floating point registers. */ |
55ff77ac | 702 | static int |
d93859e2 | 703 | sh64_fv_reg_base_num (struct gdbarch *gdbarch, int fv_regnum) |
55ff77ac CV |
704 | { |
705 | int fp_regnum; | |
706 | ||
d93859e2 | 707 | fp_regnum = gdbarch_fp0_regnum (gdbarch) + (fv_regnum - FV0_REGNUM) * 4; |
55ff77ac CV |
708 | return fp_regnum; |
709 | } | |
710 | ||
c378eb4e | 711 | /* For double precision floating point registers, i.e 2 fp regs. */ |
55ff77ac | 712 | static int |
d93859e2 | 713 | sh64_dr_reg_base_num (struct gdbarch *gdbarch, int dr_regnum) |
55ff77ac CV |
714 | { |
715 | int fp_regnum; | |
716 | ||
d93859e2 | 717 | fp_regnum = gdbarch_fp0_regnum (gdbarch) + (dr_regnum - DR0_REGNUM) * 2; |
55ff77ac CV |
718 | return fp_regnum; |
719 | } | |
720 | ||
c378eb4e | 721 | /* For pairs of floating point registers. */ |
55ff77ac | 722 | static int |
d93859e2 | 723 | sh64_fpp_reg_base_num (struct gdbarch *gdbarch, int fpp_regnum) |
55ff77ac CV |
724 | { |
725 | int fp_regnum; | |
726 | ||
d93859e2 | 727 | fp_regnum = gdbarch_fp0_regnum (gdbarch) + (fpp_regnum - FPP0_REGNUM) * 2; |
55ff77ac CV |
728 | return fp_regnum; |
729 | } | |
730 | ||
55ff77ac CV |
731 | /* *INDENT-OFF* */ |
732 | /* | |
733 | SH COMPACT MODE (ISA 16) (all pseudo) 221-272 | |
734 | GDB_REGNUM BASE_REGNUM | |
735 | r0_c 221 0 | |
736 | r1_c 222 1 | |
737 | r2_c 223 2 | |
738 | r3_c 224 3 | |
739 | r4_c 225 4 | |
740 | r5_c 226 5 | |
741 | r6_c 227 6 | |
742 | r7_c 228 7 | |
743 | r8_c 229 8 | |
744 | r9_c 230 9 | |
745 | r10_c 231 10 | |
746 | r11_c 232 11 | |
747 | r12_c 233 12 | |
748 | r13_c 234 13 | |
749 | r14_c 235 14 | |
750 | r15_c 236 15 | |
751 | ||
752 | pc_c 237 64 | |
753 | gbr_c 238 16 | |
754 | mach_c 239 17 | |
755 | macl_c 240 17 | |
756 | pr_c 241 18 | |
757 | t_c 242 19 | |
758 | fpscr_c 243 76 | |
759 | fpul_c 244 109 | |
760 | ||
761 | fr0_c 245 77 | |
762 | fr1_c 246 78 | |
763 | fr2_c 247 79 | |
764 | fr3_c 248 80 | |
765 | fr4_c 249 81 | |
766 | fr5_c 250 82 | |
767 | fr6_c 251 83 | |
768 | fr7_c 252 84 | |
769 | fr8_c 253 85 | |
770 | fr9_c 254 86 | |
771 | fr10_c 255 87 | |
772 | fr11_c 256 88 | |
773 | fr12_c 257 89 | |
774 | fr13_c 258 90 | |
775 | fr14_c 259 91 | |
776 | fr15_c 260 92 | |
777 | ||
778 | dr0_c 261 77 | |
779 | dr2_c 262 79 | |
780 | dr4_c 263 81 | |
781 | dr6_c 264 83 | |
782 | dr8_c 265 85 | |
783 | dr10_c 266 87 | |
784 | dr12_c 267 89 | |
785 | dr14_c 268 91 | |
786 | ||
787 | fv0_c 269 77 | |
788 | fv4_c 270 81 | |
789 | fv8_c 271 85 | |
790 | fv12_c 272 91 | |
791 | */ | |
792 | /* *INDENT-ON* */ | |
793 | static int | |
d93859e2 | 794 | sh64_compact_reg_base_num (struct gdbarch *gdbarch, int reg_nr) |
55ff77ac | 795 | { |
c30dc700 | 796 | int base_regnum = reg_nr; |
55ff77ac CV |
797 | |
798 | /* general register N maps to general register N */ | |
799 | if (reg_nr >= R0_C_REGNUM | |
800 | && reg_nr <= R_LAST_C_REGNUM) | |
801 | base_regnum = reg_nr - R0_C_REGNUM; | |
802 | ||
803 | /* floating point register N maps to floating point register N */ | |
804 | else if (reg_nr >= FP0_C_REGNUM | |
805 | && reg_nr <= FP_LAST_C_REGNUM) | |
d93859e2 | 806 | base_regnum = reg_nr - FP0_C_REGNUM + gdbarch_fp0_regnum (gdbarch); |
55ff77ac CV |
807 | |
808 | /* double prec register N maps to base regnum for double prec register N */ | |
809 | else if (reg_nr >= DR0_C_REGNUM | |
810 | && reg_nr <= DR_LAST_C_REGNUM) | |
d93859e2 UW |
811 | base_regnum = sh64_dr_reg_base_num (gdbarch, |
812 | DR0_REGNUM + reg_nr - DR0_C_REGNUM); | |
55ff77ac CV |
813 | |
814 | /* vector N maps to base regnum for vector register N */ | |
815 | else if (reg_nr >= FV0_C_REGNUM | |
816 | && reg_nr <= FV_LAST_C_REGNUM) | |
d93859e2 UW |
817 | base_regnum = sh64_fv_reg_base_num (gdbarch, |
818 | FV0_REGNUM + reg_nr - FV0_C_REGNUM); | |
55ff77ac CV |
819 | |
820 | else if (reg_nr == PC_C_REGNUM) | |
d93859e2 | 821 | base_regnum = gdbarch_pc_regnum (gdbarch); |
55ff77ac CV |
822 | |
823 | else if (reg_nr == GBR_C_REGNUM) | |
824 | base_regnum = 16; | |
825 | ||
826 | else if (reg_nr == MACH_C_REGNUM | |
827 | || reg_nr == MACL_C_REGNUM) | |
828 | base_regnum = 17; | |
829 | ||
830 | else if (reg_nr == PR_C_REGNUM) | |
c30dc700 | 831 | base_regnum = PR_REGNUM; |
55ff77ac CV |
832 | |
833 | else if (reg_nr == T_C_REGNUM) | |
834 | base_regnum = 19; | |
835 | ||
836 | else if (reg_nr == FPSCR_C_REGNUM) | |
7bb11558 | 837 | base_regnum = FPSCR_REGNUM; /*???? this register is a mess. */ |
55ff77ac CV |
838 | |
839 | else if (reg_nr == FPUL_C_REGNUM) | |
d93859e2 | 840 | base_regnum = gdbarch_fp0_regnum (gdbarch) + 32; |
55ff77ac CV |
841 | |
842 | return base_regnum; | |
843 | } | |
844 | ||
55ff77ac CV |
845 | static int |
846 | sign_extend (int value, int bits) | |
847 | { | |
848 | value = value & ((1 << bits) - 1); | |
849 | return (value & (1 << (bits - 1)) | |
850 | ? value | (~((1 << bits) - 1)) | |
851 | : value); | |
852 | } | |
853 | ||
854 | static void | |
c30dc700 CV |
855 | sh64_analyze_prologue (struct gdbarch *gdbarch, |
856 | struct sh64_frame_cache *cache, | |
857 | CORE_ADDR func_pc, | |
858 | CORE_ADDR current_pc) | |
55ff77ac | 859 | { |
c30dc700 | 860 | int reg_nr; |
55ff77ac CV |
861 | int pc; |
862 | int opc; | |
863 | int insn; | |
864 | int r0_val = 0; | |
55ff77ac CV |
865 | int insn_size; |
866 | int gdb_register_number; | |
867 | int register_number; | |
c30dc700 | 868 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
e17a4113 | 869 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
55ff77ac | 870 | |
c30dc700 | 871 | cache->sp_offset = 0; |
55ff77ac CV |
872 | |
873 | /* Loop around examining the prologue insns until we find something | |
874 | that does not appear to be part of the prologue. But give up | |
7bb11558 | 875 | after 20 of them, since we're getting silly then. */ |
55ff77ac | 876 | |
c30dc700 | 877 | pc = func_pc; |
55ff77ac | 878 | |
c30dc700 CV |
879 | if (cache->media_mode) |
880 | insn_size = 4; | |
55ff77ac | 881 | else |
c30dc700 | 882 | insn_size = 2; |
55ff77ac | 883 | |
c30dc700 CV |
884 | opc = pc + (insn_size * 28); |
885 | if (opc > current_pc) | |
886 | opc = current_pc; | |
887 | for ( ; pc <= opc; pc += insn_size) | |
55ff77ac | 888 | { |
c30dc700 CV |
889 | insn = read_memory_integer (cache->media_mode ? UNMAKE_ISA32_ADDR (pc) |
890 | : pc, | |
e17a4113 | 891 | insn_size, byte_order); |
55ff77ac | 892 | |
c30dc700 | 893 | if (!cache->media_mode) |
55ff77ac CV |
894 | { |
895 | if (IS_STS_PR (insn)) | |
896 | { | |
e17a4113 UW |
897 | int next_insn = read_memory_integer (pc + insn_size, |
898 | insn_size, byte_order); | |
55ff77ac CV |
899 | if (IS_MOV_TO_R15 (next_insn)) |
900 | { | |
c378eb4e MS |
901 | cache->saved_regs[PR_REGNUM] |
902 | = cache->sp_offset - ((((next_insn & 0xf) ^ 0x8) | |
903 | - 0x8) << 2); | |
55ff77ac CV |
904 | pc += insn_size; |
905 | } | |
906 | } | |
c30dc700 | 907 | |
55ff77ac | 908 | else if (IS_MOV_R14 (insn)) |
c30dc700 CV |
909 | cache->saved_regs[MEDIA_FP_REGNUM] = |
910 | cache->sp_offset - ((((insn & 0xf) ^ 0x8) - 0x8) << 2); | |
55ff77ac CV |
911 | |
912 | else if (IS_MOV_R0 (insn)) | |
913 | { | |
914 | /* Put in R0 the offset from SP at which to store some | |
c378eb4e | 915 | registers. We are interested in this value, because it |
55ff77ac CV |
916 | will tell us where the given registers are stored within |
917 | the frame. */ | |
918 | r0_val = ((insn & 0xff) ^ 0x80) - 0x80; | |
919 | } | |
c30dc700 | 920 | |
55ff77ac CV |
921 | else if (IS_ADD_SP_R0 (insn)) |
922 | { | |
923 | /* This instruction still prepares r0, but we don't care. | |
7bb11558 | 924 | We already have the offset in r0_val. */ |
55ff77ac | 925 | } |
c30dc700 | 926 | |
55ff77ac CV |
927 | else if (IS_STS_R0 (insn)) |
928 | { | |
c378eb4e | 929 | /* Store PR at r0_val-4 from SP. Decrement r0 by 4. */ |
c30dc700 | 930 | cache->saved_regs[PR_REGNUM] = cache->sp_offset - (r0_val - 4); |
55ff77ac | 931 | r0_val -= 4; |
55ff77ac | 932 | } |
c30dc700 | 933 | |
55ff77ac CV |
934 | else if (IS_MOV_R14_R0 (insn)) |
935 | { | |
c378eb4e | 936 | /* Store R14 at r0_val-4 from SP. Decrement r0 by 4. */ |
c30dc700 CV |
937 | cache->saved_regs[MEDIA_FP_REGNUM] = cache->sp_offset |
938 | - (r0_val - 4); | |
55ff77ac CV |
939 | r0_val -= 4; |
940 | } | |
941 | ||
942 | else if (IS_ADD_SP (insn)) | |
c30dc700 CV |
943 | cache->sp_offset -= ((insn & 0xff) ^ 0x80) - 0x80; |
944 | ||
55ff77ac CV |
945 | else if (IS_MOV_SP_FP (insn)) |
946 | break; | |
947 | } | |
948 | else | |
949 | { | |
c30dc700 CV |
950 | if (IS_ADDIL_SP_MEDIA (insn) || IS_ADDI_SP_MEDIA (insn)) |
951 | cache->sp_offset -= | |
952 | sign_extend ((((insn & 0xffc00) ^ 0x80000) - 0x80000) >> 10, 9); | |
55ff77ac CV |
953 | |
954 | else if (IS_STQ_R18_R15 (insn)) | |
c378eb4e MS |
955 | cache->saved_regs[PR_REGNUM] |
956 | = cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10, | |
957 | 9) << 3); | |
55ff77ac CV |
958 | |
959 | else if (IS_STL_R18_R15 (insn)) | |
c378eb4e MS |
960 | cache->saved_regs[PR_REGNUM] |
961 | = cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10, | |
962 | 9) << 2); | |
55ff77ac CV |
963 | |
964 | else if (IS_STQ_R14_R15 (insn)) | |
c378eb4e MS |
965 | cache->saved_regs[MEDIA_FP_REGNUM] |
966 | = cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10, | |
967 | 9) << 3); | |
55ff77ac CV |
968 | |
969 | else if (IS_STL_R14_R15 (insn)) | |
c378eb4e MS |
970 | cache->saved_regs[MEDIA_FP_REGNUM] |
971 | = cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10, | |
972 | 9) << 2); | |
55ff77ac CV |
973 | |
974 | else if (IS_MOV_SP_FP_MEDIA (insn)) | |
975 | break; | |
976 | } | |
977 | } | |
978 | ||
c30dc700 CV |
979 | if (cache->saved_regs[MEDIA_FP_REGNUM] >= 0) |
980 | cache->uses_fp = 1; | |
55ff77ac CV |
981 | } |
982 | ||
55ff77ac | 983 | static CORE_ADDR |
c30dc700 | 984 | sh64_frame_align (struct gdbarch *ignore, CORE_ADDR sp) |
55ff77ac | 985 | { |
c30dc700 | 986 | return sp & ~7; |
55ff77ac CV |
987 | } |
988 | ||
c30dc700 | 989 | /* Function: push_dummy_call |
55ff77ac CV |
990 | Setup the function arguments for calling a function in the inferior. |
991 | ||
85a453d5 | 992 | On the Renesas SH architecture, there are four registers (R4 to R7) |
55ff77ac CV |
993 | which are dedicated for passing function arguments. Up to the first |
994 | four arguments (depending on size) may go into these registers. | |
995 | The rest go on the stack. | |
996 | ||
997 | Arguments that are smaller than 4 bytes will still take up a whole | |
998 | register or a whole 32-bit word on the stack, and will be | |
999 | right-justified in the register or the stack word. This includes | |
1000 | chars, shorts, and small aggregate types. | |
1001 | ||
1002 | Arguments that are larger than 4 bytes may be split between two or | |
1003 | more registers. If there are not enough registers free, an argument | |
1004 | may be passed partly in a register (or registers), and partly on the | |
c378eb4e | 1005 | stack. This includes doubles, long longs, and larger aggregates. |
55ff77ac CV |
1006 | As far as I know, there is no upper limit to the size of aggregates |
1007 | that will be passed in this way; in other words, the convention of | |
1008 | passing a pointer to a large aggregate instead of a copy is not used. | |
1009 | ||
1010 | An exceptional case exists for struct arguments (and possibly other | |
1011 | aggregates such as arrays) if the size is larger than 4 bytes but | |
1012 | not a multiple of 4 bytes. In this case the argument is never split | |
1013 | between the registers and the stack, but instead is copied in its | |
1014 | entirety onto the stack, AND also copied into as many registers as | |
1015 | there is room for. In other words, space in registers permitting, | |
1016 | two copies of the same argument are passed in. As far as I can tell, | |
1017 | only the one on the stack is used, although that may be a function | |
1018 | of the level of compiler optimization. I suspect this is a compiler | |
1019 | bug. Arguments of these odd sizes are left-justified within the | |
1020 | word (as opposed to arguments smaller than 4 bytes, which are | |
1021 | right-justified). | |
1022 | ||
1023 | If the function is to return an aggregate type such as a struct, it | |
1024 | is either returned in the normal return value register R0 (if its | |
1025 | size is no greater than one byte), or else the caller must allocate | |
1026 | space into which the callee will copy the return value (if the size | |
1027 | is greater than one byte). In this case, a pointer to the return | |
1028 | value location is passed into the callee in register R2, which does | |
1029 | not displace any of the other arguments passed in via registers R4 | |
c378eb4e | 1030 | to R7. */ |
55ff77ac CV |
1031 | |
1032 | /* R2-R9 for integer types and integer equivalent (char, pointers) and | |
1033 | non-scalar (struct, union) elements (even if the elements are | |
1034 | floats). | |
1035 | FR0-FR11 for single precision floating point (float) | |
1036 | DR0-DR10 for double precision floating point (double) | |
1037 | ||
1038 | If a float is argument number 3 (for instance) and arguments number | |
1039 | 1,2, and 4 are integer, the mapping will be: | |
c378eb4e | 1040 | arg1 -->R2, arg2 --> R3, arg3 -->FR0, arg4 --> R5. I.e. R4 is not used. |
55ff77ac CV |
1041 | |
1042 | If a float is argument number 10 (for instance) and arguments number | |
1043 | 1 through 10 are integer, the mapping will be: | |
1044 | arg1->R2, arg2->R3, arg3->R4, arg4->R5, arg5->R6, arg6->R7, arg7->R8, | |
c378eb4e MS |
1045 | arg8->R9, arg9->(0,SP)stack(8-byte aligned), arg10->FR0, |
1046 | arg11->stack(16,SP). I.e. there is hole in the stack. | |
55ff77ac CV |
1047 | |
1048 | Different rules apply for variable arguments functions, and for functions | |
7bb11558 | 1049 | for which the prototype is not known. */ |
55ff77ac CV |
1050 | |
1051 | static CORE_ADDR | |
c30dc700 CV |
1052 | sh64_push_dummy_call (struct gdbarch *gdbarch, |
1053 | struct value *function, | |
1054 | struct regcache *regcache, | |
1055 | CORE_ADDR bp_addr, | |
1056 | int nargs, struct value **args, | |
1057 | CORE_ADDR sp, int struct_return, | |
1058 | CORE_ADDR struct_addr) | |
55ff77ac | 1059 | { |
e17a4113 | 1060 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
55ff77ac CV |
1061 | int stack_offset, stack_alloc; |
1062 | int int_argreg; | |
1063 | int float_argreg; | |
1064 | int double_argreg; | |
1065 | int float_arg_index = 0; | |
1066 | int double_arg_index = 0; | |
1067 | int argnum; | |
1068 | struct type *type; | |
1069 | CORE_ADDR regval; | |
1070 | char *val; | |
1071 | char valbuf[8]; | |
1072 | char valbuf_tmp[8]; | |
1073 | int len; | |
1074 | int argreg_size; | |
1075 | int fp_args[12]; | |
55ff77ac CV |
1076 | |
1077 | memset (fp_args, 0, sizeof (fp_args)); | |
1078 | ||
c378eb4e | 1079 | /* First force sp to a 8-byte alignment. */ |
c30dc700 | 1080 | sp = sh64_frame_align (gdbarch, sp); |
55ff77ac CV |
1081 | |
1082 | /* The "struct return pointer" pseudo-argument has its own dedicated | |
c378eb4e | 1083 | register. */ |
55ff77ac CV |
1084 | |
1085 | if (struct_return) | |
c30dc700 CV |
1086 | regcache_cooked_write_unsigned (regcache, |
1087 | STRUCT_RETURN_REGNUM, struct_addr); | |
55ff77ac | 1088 | |
c378eb4e | 1089 | /* Now make sure there's space on the stack. */ |
55ff77ac | 1090 | for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++) |
4991999e | 1091 | stack_alloc += ((TYPE_LENGTH (value_type (args[argnum])) + 7) & ~7); |
c378eb4e | 1092 | sp -= stack_alloc; /* Make room on stack for args. */ |
55ff77ac CV |
1093 | |
1094 | /* Now load as many as possible of the first arguments into | |
1095 | registers, and push the rest onto the stack. There are 64 bytes | |
1096 | in eight registers available. Loop thru args from first to last. */ | |
1097 | ||
1098 | int_argreg = ARG0_REGNUM; | |
58643501 | 1099 | float_argreg = gdbarch_fp0_regnum (gdbarch); |
55ff77ac CV |
1100 | double_argreg = DR0_REGNUM; |
1101 | ||
1102 | for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++) | |
1103 | { | |
4991999e | 1104 | type = value_type (args[argnum]); |
55ff77ac CV |
1105 | len = TYPE_LENGTH (type); |
1106 | memset (valbuf, 0, sizeof (valbuf)); | |
1107 | ||
1108 | if (TYPE_CODE (type) != TYPE_CODE_FLT) | |
1109 | { | |
58643501 | 1110 | argreg_size = register_size (gdbarch, int_argreg); |
55ff77ac CV |
1111 | |
1112 | if (len < argreg_size) | |
1113 | { | |
c378eb4e | 1114 | /* value gets right-justified in the register or stack word. */ |
58643501 | 1115 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
55ff77ac | 1116 | memcpy (valbuf + argreg_size - len, |
0fd88904 | 1117 | (char *) value_contents (args[argnum]), len); |
55ff77ac | 1118 | else |
0fd88904 | 1119 | memcpy (valbuf, (char *) value_contents (args[argnum]), len); |
55ff77ac CV |
1120 | |
1121 | val = valbuf; | |
1122 | } | |
1123 | else | |
0fd88904 | 1124 | val = (char *) value_contents (args[argnum]); |
55ff77ac CV |
1125 | |
1126 | while (len > 0) | |
1127 | { | |
1128 | if (int_argreg > ARGLAST_REGNUM) | |
1129 | { | |
c378eb4e | 1130 | /* Must go on the stack. */ |
079c8cd0 CV |
1131 | write_memory (sp + stack_offset, (const bfd_byte *) val, |
1132 | argreg_size); | |
55ff77ac CV |
1133 | stack_offset += 8;/*argreg_size;*/ |
1134 | } | |
1135 | /* NOTE WELL!!!!! This is not an "else if" clause!!! | |
1136 | That's because some *&^%$ things get passed on the stack | |
1137 | AND in the registers! */ | |
1138 | if (int_argreg <= ARGLAST_REGNUM) | |
1139 | { | |
c378eb4e | 1140 | /* There's room in a register. */ |
e17a4113 UW |
1141 | regval = extract_unsigned_integer (val, argreg_size, |
1142 | byte_order); | |
c378eb4e MS |
1143 | regcache_cooked_write_unsigned (regcache, |
1144 | int_argreg, regval); | |
55ff77ac CV |
1145 | } |
1146 | /* Store the value 8 bytes at a time. This means that | |
1147 | things larger than 8 bytes may go partly in registers | |
c378eb4e | 1148 | and partly on the stack. FIXME: argreg is incremented |
7bb11558 | 1149 | before we use its size. */ |
55ff77ac CV |
1150 | len -= argreg_size; |
1151 | val += argreg_size; | |
1152 | int_argreg++; | |
1153 | } | |
1154 | } | |
1155 | else | |
1156 | { | |
0fd88904 | 1157 | val = (char *) value_contents (args[argnum]); |
55ff77ac CV |
1158 | if (len == 4) |
1159 | { | |
c378eb4e | 1160 | /* Where is it going to be stored? */ |
55ff77ac CV |
1161 | while (fp_args[float_arg_index]) |
1162 | float_arg_index ++; | |
1163 | ||
1164 | /* Now float_argreg points to the register where it | |
1165 | should be stored. Are we still within the allowed | |
c378eb4e | 1166 | register set? */ |
55ff77ac CV |
1167 | if (float_arg_index <= FLOAT_ARGLAST_REGNUM) |
1168 | { | |
1169 | /* Goes in FR0...FR11 */ | |
c30dc700 | 1170 | regcache_cooked_write (regcache, |
58643501 | 1171 | gdbarch_fp0_regnum (gdbarch) |
3e8c568d | 1172 | + float_arg_index, |
c30dc700 | 1173 | val); |
55ff77ac | 1174 | fp_args[float_arg_index] = 1; |
7bb11558 | 1175 | /* Skip the corresponding general argument register. */ |
55ff77ac CV |
1176 | int_argreg ++; |
1177 | } | |
1178 | else | |
1179 | ; | |
1180 | /* Store it as the integers, 8 bytes at the time, if | |
7bb11558 | 1181 | necessary spilling on the stack. */ |
55ff77ac CV |
1182 | |
1183 | } | |
1184 | else if (len == 8) | |
1185 | { | |
c378eb4e | 1186 | /* Where is it going to be stored? */ |
55ff77ac CV |
1187 | while (fp_args[double_arg_index]) |
1188 | double_arg_index += 2; | |
1189 | /* Now double_argreg points to the register | |
1190 | where it should be stored. | |
c378eb4e | 1191 | Are we still within the allowed register set? */ |
55ff77ac CV |
1192 | if (double_arg_index < FLOAT_ARGLAST_REGNUM) |
1193 | { | |
1194 | /* Goes in DR0...DR10 */ | |
1195 | /* The numbering of the DRi registers is consecutive, | |
7bb11558 | 1196 | i.e. includes odd numbers. */ |
55ff77ac | 1197 | int double_register_offset = double_arg_index / 2; |
c30dc700 CV |
1198 | int regnum = DR0_REGNUM + double_register_offset; |
1199 | regcache_cooked_write (regcache, regnum, val); | |
55ff77ac CV |
1200 | fp_args[double_arg_index] = 1; |
1201 | fp_args[double_arg_index + 1] = 1; | |
7bb11558 | 1202 | /* Skip the corresponding general argument register. */ |
55ff77ac CV |
1203 | int_argreg ++; |
1204 | } | |
1205 | else | |
1206 | ; | |
1207 | /* Store it as the integers, 8 bytes at the time, if | |
7bb11558 | 1208 | necessary spilling on the stack. */ |
55ff77ac CV |
1209 | } |
1210 | } | |
1211 | } | |
c378eb4e | 1212 | /* Store return address. */ |
c30dc700 | 1213 | regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr); |
55ff77ac | 1214 | |
c30dc700 | 1215 | /* Update stack pointer. */ |
3e8c568d | 1216 | regcache_cooked_write_unsigned (regcache, |
58643501 | 1217 | gdbarch_sp_regnum (gdbarch), sp); |
55ff77ac | 1218 | |
55ff77ac CV |
1219 | return sp; |
1220 | } | |
1221 | ||
1222 | /* Find a function's return value in the appropriate registers (in | |
1223 | regbuf), and copy it into valbuf. Extract from an array REGBUF | |
1224 | containing the (raw) register state a function return value of type | |
1225 | TYPE, and copy that, in virtual format, into VALBUF. */ | |
1226 | static void | |
c30dc700 CV |
1227 | sh64_extract_return_value (struct type *type, struct regcache *regcache, |
1228 | void *valbuf) | |
55ff77ac | 1229 | { |
d93859e2 | 1230 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
e17a4113 | 1231 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
55ff77ac | 1232 | int len = TYPE_LENGTH (type); |
d93859e2 | 1233 | |
55ff77ac CV |
1234 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
1235 | { | |
1236 | if (len == 4) | |
1237 | { | |
c378eb4e | 1238 | /* Return value stored in gdbarch_fp0_regnum. */ |
3e8c568d | 1239 | regcache_raw_read (regcache, |
d93859e2 | 1240 | gdbarch_fp0_regnum (gdbarch), valbuf); |
55ff77ac CV |
1241 | } |
1242 | else if (len == 8) | |
1243 | { | |
c378eb4e | 1244 | /* return value stored in DR0_REGNUM. */ |
55ff77ac | 1245 | DOUBLEST val; |
18cf8b5b | 1246 | gdb_byte buf[8]; |
55ff77ac | 1247 | |
18cf8b5b | 1248 | regcache_cooked_read (regcache, DR0_REGNUM, buf); |
55ff77ac | 1249 | |
d93859e2 | 1250 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) |
55ff77ac | 1251 | floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, |
c30dc700 | 1252 | buf, &val); |
55ff77ac CV |
1253 | else |
1254 | floatformat_to_doublest (&floatformat_ieee_double_big, | |
c30dc700 | 1255 | buf, &val); |
7bb11558 | 1256 | store_typed_floating (valbuf, type, val); |
55ff77ac CV |
1257 | } |
1258 | } | |
1259 | else | |
1260 | { | |
1261 | if (len <= 8) | |
1262 | { | |
c30dc700 CV |
1263 | int offset; |
1264 | char buf[8]; | |
c378eb4e | 1265 | /* Result is in register 2. If smaller than 8 bytes, it is padded |
7bb11558 | 1266 | at the most significant end. */ |
c30dc700 CV |
1267 | regcache_raw_read (regcache, DEFAULT_RETURN_REGNUM, buf); |
1268 | ||
d93859e2 UW |
1269 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
1270 | offset = register_size (gdbarch, DEFAULT_RETURN_REGNUM) | |
c30dc700 | 1271 | - len; |
55ff77ac | 1272 | else |
c30dc700 CV |
1273 | offset = 0; |
1274 | memcpy (valbuf, buf + offset, len); | |
55ff77ac CV |
1275 | } |
1276 | else | |
a73c6dcd | 1277 | error (_("bad size for return value")); |
55ff77ac CV |
1278 | } |
1279 | } | |
1280 | ||
1281 | /* Write into appropriate registers a function return value | |
1282 | of type TYPE, given in virtual format. | |
1283 | If the architecture is sh4 or sh3e, store a function's return value | |
1284 | in the R0 general register or in the FP0 floating point register, | |
c378eb4e | 1285 | depending on the type of the return value. In all the other cases |
7bb11558 | 1286 | the result is stored in r0, left-justified. */ |
55ff77ac CV |
1287 | |
1288 | static void | |
c30dc700 CV |
1289 | sh64_store_return_value (struct type *type, struct regcache *regcache, |
1290 | const void *valbuf) | |
55ff77ac | 1291 | { |
d93859e2 | 1292 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
7bb11558 | 1293 | char buf[64]; /* more than enough... */ |
55ff77ac CV |
1294 | int len = TYPE_LENGTH (type); |
1295 | ||
1296 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
1297 | { | |
d93859e2 | 1298 | int i, regnum = gdbarch_fp0_regnum (gdbarch); |
c30dc700 | 1299 | for (i = 0; i < len; i += 4) |
d93859e2 | 1300 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) |
c30dc700 CV |
1301 | regcache_raw_write (regcache, regnum++, |
1302 | (char *) valbuf + len - 4 - i); | |
1303 | else | |
1304 | regcache_raw_write (regcache, regnum++, (char *) valbuf + i); | |
55ff77ac CV |
1305 | } |
1306 | else | |
1307 | { | |
1308 | int return_register = DEFAULT_RETURN_REGNUM; | |
1309 | int offset = 0; | |
1310 | ||
d93859e2 | 1311 | if (len <= register_size (gdbarch, return_register)) |
55ff77ac | 1312 | { |
7bb11558 | 1313 | /* Pad with zeros. */ |
d93859e2 UW |
1314 | memset (buf, 0, register_size (gdbarch, return_register)); |
1315 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) | |
1316 | offset = 0; /*register_size (gdbarch, | |
7bb11558 | 1317 | return_register) - len;*/ |
55ff77ac | 1318 | else |
d93859e2 | 1319 | offset = register_size (gdbarch, return_register) - len; |
55ff77ac CV |
1320 | |
1321 | memcpy (buf + offset, valbuf, len); | |
c30dc700 | 1322 | regcache_raw_write (regcache, return_register, buf); |
55ff77ac CV |
1323 | } |
1324 | else | |
c30dc700 | 1325 | regcache_raw_write (regcache, return_register, valbuf); |
55ff77ac CV |
1326 | } |
1327 | } | |
1328 | ||
c30dc700 | 1329 | static enum return_value_convention |
c055b101 CV |
1330 | sh64_return_value (struct gdbarch *gdbarch, struct type *func_type, |
1331 | struct type *type, struct regcache *regcache, | |
18cf8b5b | 1332 | gdb_byte *readbuf, const gdb_byte *writebuf) |
c30dc700 CV |
1333 | { |
1334 | if (sh64_use_struct_convention (type)) | |
1335 | return RETURN_VALUE_STRUCT_CONVENTION; | |
1336 | if (writebuf) | |
1337 | sh64_store_return_value (type, regcache, writebuf); | |
1338 | else if (readbuf) | |
1339 | sh64_extract_return_value (type, regcache, readbuf); | |
1340 | return RETURN_VALUE_REGISTER_CONVENTION; | |
1341 | } | |
1342 | ||
55ff77ac | 1343 | static void |
c458d6db | 1344 | sh64_show_media_regs (struct frame_info *frame) |
55ff77ac | 1345 | { |
58643501 | 1346 | struct gdbarch *gdbarch = get_frame_arch (frame); |
55ff77ac | 1347 | int i; |
55ff77ac | 1348 | |
c458d6db | 1349 | printf_filtered |
cce7e648 | 1350 | ("PC=%s SR=%s\n", |
5af949e3 UW |
1351 | phex (get_frame_register_unsigned (frame, |
1352 | gdbarch_pc_regnum (gdbarch)), 8), | |
2244ba2e | 1353 | phex (get_frame_register_unsigned (frame, SR_REGNUM), 8)); |
55ff77ac | 1354 | |
c458d6db | 1355 | printf_filtered |
cce7e648 | 1356 | ("SSR=%s SPC=%s\n", |
2244ba2e PM |
1357 | phex (get_frame_register_unsigned (frame, SSR_REGNUM), 8), |
1358 | phex (get_frame_register_unsigned (frame, SPC_REGNUM), 8)); | |
c458d6db | 1359 | printf_filtered |
2244ba2e PM |
1360 | ("FPSCR=%s\n ", |
1361 | phex (get_frame_register_unsigned (frame, FPSCR_REGNUM), 8)); | |
55ff77ac CV |
1362 | |
1363 | for (i = 0; i < 64; i = i + 4) | |
c458d6db | 1364 | printf_filtered |
2244ba2e | 1365 | ("\nR%d-R%d %s %s %s %s\n", |
c458d6db | 1366 | i, i + 3, |
2244ba2e PM |
1367 | phex (get_frame_register_unsigned (frame, i + 0), 8), |
1368 | phex (get_frame_register_unsigned (frame, i + 1), 8), | |
1369 | phex (get_frame_register_unsigned (frame, i + 2), 8), | |
1370 | phex (get_frame_register_unsigned (frame, i + 3), 8)); | |
55ff77ac CV |
1371 | |
1372 | printf_filtered ("\n"); | |
1373 | ||
1374 | for (i = 0; i < 64; i = i + 8) | |
c458d6db UW |
1375 | printf_filtered |
1376 | ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1377 | i, i + 7, | |
3e8c568d | 1378 | (long) get_frame_register_unsigned |
58643501 | 1379 | (frame, gdbarch_fp0_regnum (gdbarch) + i + 0), |
3e8c568d | 1380 | (long) get_frame_register_unsigned |
58643501 | 1381 | (frame, gdbarch_fp0_regnum (gdbarch) + i + 1), |
3e8c568d | 1382 | (long) get_frame_register_unsigned |
58643501 | 1383 | (frame, gdbarch_fp0_regnum (gdbarch) + i + 2), |
3e8c568d | 1384 | (long) get_frame_register_unsigned |
58643501 | 1385 | (frame, gdbarch_fp0_regnum (gdbarch) + i + 3), |
3e8c568d | 1386 | (long) get_frame_register_unsigned |
58643501 | 1387 | (frame, gdbarch_fp0_regnum (gdbarch) + i + 4), |
3e8c568d | 1388 | (long) get_frame_register_unsigned |
58643501 | 1389 | (frame, gdbarch_fp0_regnum (gdbarch) + i + 5), |
3e8c568d | 1390 | (long) get_frame_register_unsigned |
58643501 | 1391 | (frame, gdbarch_fp0_regnum (gdbarch) + i + 6), |
3e8c568d | 1392 | (long) get_frame_register_unsigned |
58643501 | 1393 | (frame, gdbarch_fp0_regnum (gdbarch) + i + 7)); |
55ff77ac CV |
1394 | } |
1395 | ||
1396 | static void | |
c458d6db | 1397 | sh64_show_compact_regs (struct frame_info *frame) |
55ff77ac | 1398 | { |
58643501 | 1399 | struct gdbarch *gdbarch = get_frame_arch (frame); |
55ff77ac | 1400 | int i; |
55ff77ac | 1401 | |
c458d6db | 1402 | printf_filtered |
cce7e648 | 1403 | ("PC=%s\n", |
5af949e3 | 1404 | phex (get_frame_register_unsigned (frame, PC_C_REGNUM), 8)); |
c458d6db UW |
1405 | |
1406 | printf_filtered | |
1407 | ("GBR=%08lx MACH=%08lx MACL=%08lx PR=%08lx T=%08lx\n", | |
1408 | (long) get_frame_register_unsigned (frame, GBR_C_REGNUM), | |
1409 | (long) get_frame_register_unsigned (frame, MACH_C_REGNUM), | |
1410 | (long) get_frame_register_unsigned (frame, MACL_C_REGNUM), | |
1411 | (long) get_frame_register_unsigned (frame, PR_C_REGNUM), | |
1412 | (long) get_frame_register_unsigned (frame, T_C_REGNUM)); | |
1413 | printf_filtered | |
1414 | ("FPSCR=%08lx FPUL=%08lx\n", | |
1415 | (long) get_frame_register_unsigned (frame, FPSCR_C_REGNUM), | |
1416 | (long) get_frame_register_unsigned (frame, FPUL_C_REGNUM)); | |
55ff77ac CV |
1417 | |
1418 | for (i = 0; i < 16; i = i + 4) | |
c458d6db UW |
1419 | printf_filtered |
1420 | ("\nR%d-R%d %08lx %08lx %08lx %08lx\n", | |
1421 | i, i + 3, | |
1422 | (long) get_frame_register_unsigned (frame, i + 0), | |
1423 | (long) get_frame_register_unsigned (frame, i + 1), | |
1424 | (long) get_frame_register_unsigned (frame, i + 2), | |
1425 | (long) get_frame_register_unsigned (frame, i + 3)); | |
55ff77ac CV |
1426 | |
1427 | printf_filtered ("\n"); | |
1428 | ||
1429 | for (i = 0; i < 16; i = i + 8) | |
c458d6db UW |
1430 | printf_filtered |
1431 | ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1432 | i, i + 7, | |
3e8c568d | 1433 | (long) get_frame_register_unsigned |
58643501 | 1434 | (frame, gdbarch_fp0_regnum (gdbarch) + i + 0), |
3e8c568d | 1435 | (long) get_frame_register_unsigned |
58643501 | 1436 | (frame, gdbarch_fp0_regnum (gdbarch) + i + 1), |
3e8c568d | 1437 | (long) get_frame_register_unsigned |
58643501 | 1438 | (frame, gdbarch_fp0_regnum (gdbarch) + i + 2), |
3e8c568d | 1439 | (long) get_frame_register_unsigned |
58643501 | 1440 | (frame, gdbarch_fp0_regnum (gdbarch) + i + 3), |
3e8c568d | 1441 | (long) get_frame_register_unsigned |
58643501 | 1442 | (frame, gdbarch_fp0_regnum (gdbarch) + i + 4), |
3e8c568d | 1443 | (long) get_frame_register_unsigned |
58643501 | 1444 | (frame, gdbarch_fp0_regnum (gdbarch) + i + 5), |
3e8c568d | 1445 | (long) get_frame_register_unsigned |
58643501 | 1446 | (frame, gdbarch_fp0_regnum (gdbarch) + i + 6), |
3e8c568d | 1447 | (long) get_frame_register_unsigned |
58643501 | 1448 | (frame, gdbarch_fp0_regnum (gdbarch) + i + 7)); |
55ff77ac CV |
1449 | } |
1450 | ||
7bb11558 MS |
1451 | /* FIXME!!! This only shows the registers for shmedia, excluding the |
1452 | pseudo registers. */ | |
55ff77ac | 1453 | void |
c458d6db | 1454 | sh64_show_regs (struct frame_info *frame) |
55ff77ac | 1455 | { |
c458d6db UW |
1456 | if (pc_is_isa32 (get_frame_pc (frame))) |
1457 | sh64_show_media_regs (frame); | |
55ff77ac | 1458 | else |
c458d6db | 1459 | sh64_show_compact_regs (frame); |
55ff77ac CV |
1460 | } |
1461 | ||
1462 | /* *INDENT-OFF* */ | |
1463 | /* | |
1464 | SH MEDIA MODE (ISA 32) | |
1465 | general registers (64-bit) 0-63 | |
1466 | 0 r0, r1, r2, r3, r4, r5, r6, r7, | |
1467 | 64 r8, r9, r10, r11, r12, r13, r14, r15, | |
1468 | 128 r16, r17, r18, r19, r20, r21, r22, r23, | |
1469 | 192 r24, r25, r26, r27, r28, r29, r30, r31, | |
1470 | 256 r32, r33, r34, r35, r36, r37, r38, r39, | |
1471 | 320 r40, r41, r42, r43, r44, r45, r46, r47, | |
1472 | 384 r48, r49, r50, r51, r52, r53, r54, r55, | |
1473 | 448 r56, r57, r58, r59, r60, r61, r62, r63, | |
1474 | ||
1475 | pc (64-bit) 64 | |
1476 | 512 pc, | |
1477 | ||
1478 | status reg., saved status reg., saved pc reg. (64-bit) 65-67 | |
1479 | 520 sr, ssr, spc, | |
1480 | ||
1481 | target registers (64-bit) 68-75 | |
1482 | 544 tr0, tr1, tr2, tr3, tr4, tr5, tr6, tr7, | |
1483 | ||
1484 | floating point state control register (32-bit) 76 | |
1485 | 608 fpscr, | |
1486 | ||
1487 | single precision floating point registers (32-bit) 77-140 | |
1488 | 612 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7, | |
1489 | 644 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15, | |
1490 | 676 fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23, | |
1491 | 708 fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31, | |
1492 | 740 fr32, fr33, fr34, fr35, fr36, fr37, fr38, fr39, | |
1493 | 772 fr40, fr41, fr42, fr43, fr44, fr45, fr46, fr47, | |
1494 | 804 fr48, fr49, fr50, fr51, fr52, fr53, fr54, fr55, | |
1495 | 836 fr56, fr57, fr58, fr59, fr60, fr61, fr62, fr63, | |
1496 | ||
1497 | TOTAL SPACE FOR REGISTERS: 868 bytes | |
1498 | ||
1499 | From here on they are all pseudo registers: no memory allocated. | |
1500 | REGISTER_BYTE returns the register byte for the base register. | |
1501 | ||
1502 | double precision registers (pseudo) 141-172 | |
1503 | dr0, dr2, dr4, dr6, dr8, dr10, dr12, dr14, | |
1504 | dr16, dr18, dr20, dr22, dr24, dr26, dr28, dr30, | |
1505 | dr32, dr34, dr36, dr38, dr40, dr42, dr44, dr46, | |
1506 | dr48, dr50, dr52, dr54, dr56, dr58, dr60, dr62, | |
1507 | ||
1508 | floating point pairs (pseudo) 173-204 | |
1509 | fp0, fp2, fp4, fp6, fp8, fp10, fp12, fp14, | |
1510 | fp16, fp18, fp20, fp22, fp24, fp26, fp28, fp30, | |
1511 | fp32, fp34, fp36, fp38, fp40, fp42, fp44, fp46, | |
1512 | fp48, fp50, fp52, fp54, fp56, fp58, fp60, fp62, | |
1513 | ||
1514 | floating point vectors (4 floating point regs) (pseudo) 205-220 | |
1515 | fv0, fv4, fv8, fv12, fv16, fv20, fv24, fv28, | |
1516 | fv32, fv36, fv40, fv44, fv48, fv52, fv56, fv60, | |
1517 | ||
1518 | SH COMPACT MODE (ISA 16) (all pseudo) 221-272 | |
1519 | r0_c, r1_c, r2_c, r3_c, r4_c, r5_c, r6_c, r7_c, | |
1520 | r8_c, r9_c, r10_c, r11_c, r12_c, r13_c, r14_c, r15_c, | |
1521 | pc_c, | |
1522 | gbr_c, mach_c, macl_c, pr_c, t_c, | |
1523 | fpscr_c, fpul_c, | |
1524 | fr0_c, fr1_c, fr2_c, fr3_c, fr4_c, fr5_c, fr6_c, fr7_c, | |
1525 | fr8_c, fr9_c, fr10_c, fr11_c, fr12_c, fr13_c, fr14_c, fr15_c | |
1526 | dr0_c, dr2_c, dr4_c, dr6_c, dr8_c, dr10_c, dr12_c, dr14_c | |
1527 | fv0_c, fv4_c, fv8_c, fv12_c | |
1528 | */ | |
55ff77ac | 1529 | |
55ff77ac | 1530 | static struct type * |
0dfff4cb | 1531 | sh64_build_float_register_type (struct gdbarch *gdbarch, int high) |
55ff77ac | 1532 | { |
e3506a9f UW |
1533 | return lookup_array_range_type (builtin_type (gdbarch)->builtin_float, |
1534 | 0, high); | |
55ff77ac CV |
1535 | } |
1536 | ||
7bb11558 MS |
1537 | /* Return the GDB type object for the "standard" data type |
1538 | of data in register REG_NR. */ | |
55ff77ac | 1539 | static struct type * |
7bb11558 | 1540 | sh64_register_type (struct gdbarch *gdbarch, int reg_nr) |
55ff77ac | 1541 | { |
58643501 | 1542 | if ((reg_nr >= gdbarch_fp0_regnum (gdbarch) |
55ff77ac CV |
1543 | && reg_nr <= FP_LAST_REGNUM) |
1544 | || (reg_nr >= FP0_C_REGNUM | |
1545 | && reg_nr <= FP_LAST_C_REGNUM)) | |
0dfff4cb | 1546 | return builtin_type (gdbarch)->builtin_float; |
55ff77ac CV |
1547 | else if ((reg_nr >= DR0_REGNUM |
1548 | && reg_nr <= DR_LAST_REGNUM) | |
1549 | || (reg_nr >= DR0_C_REGNUM | |
1550 | && reg_nr <= DR_LAST_C_REGNUM)) | |
0dfff4cb | 1551 | return builtin_type (gdbarch)->builtin_double; |
55ff77ac CV |
1552 | else if (reg_nr >= FPP0_REGNUM |
1553 | && reg_nr <= FPP_LAST_REGNUM) | |
0dfff4cb | 1554 | return sh64_build_float_register_type (gdbarch, 1); |
55ff77ac CV |
1555 | else if ((reg_nr >= FV0_REGNUM |
1556 | && reg_nr <= FV_LAST_REGNUM) | |
1557 | ||(reg_nr >= FV0_C_REGNUM | |
1558 | && reg_nr <= FV_LAST_C_REGNUM)) | |
0dfff4cb | 1559 | return sh64_build_float_register_type (gdbarch, 3); |
55ff77ac | 1560 | else if (reg_nr == FPSCR_REGNUM) |
0dfff4cb | 1561 | return builtin_type (gdbarch)->builtin_int; |
55ff77ac CV |
1562 | else if (reg_nr >= R0_C_REGNUM |
1563 | && reg_nr < FP0_C_REGNUM) | |
0dfff4cb | 1564 | return builtin_type (gdbarch)->builtin_int; |
55ff77ac | 1565 | else |
0dfff4cb | 1566 | return builtin_type (gdbarch)->builtin_long_long; |
55ff77ac CV |
1567 | } |
1568 | ||
1569 | static void | |
d93859e2 UW |
1570 | sh64_register_convert_to_virtual (struct gdbarch *gdbarch, int regnum, |
1571 | struct type *type, char *from, char *to) | |
55ff77ac | 1572 | { |
d93859e2 | 1573 | if (gdbarch_byte_order (gdbarch) != BFD_ENDIAN_LITTLE) |
55ff77ac | 1574 | { |
7bb11558 | 1575 | /* It is a no-op. */ |
d93859e2 | 1576 | memcpy (to, from, register_size (gdbarch, regnum)); |
55ff77ac CV |
1577 | return; |
1578 | } | |
1579 | ||
1580 | if ((regnum >= DR0_REGNUM | |
1581 | && regnum <= DR_LAST_REGNUM) | |
1582 | || (regnum >= DR0_C_REGNUM | |
1583 | && regnum <= DR_LAST_C_REGNUM)) | |
1584 | { | |
1585 | DOUBLEST val; | |
7bb11558 MS |
1586 | floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, |
1587 | from, &val); | |
39add00a | 1588 | store_typed_floating (to, type, val); |
55ff77ac CV |
1589 | } |
1590 | else | |
a73c6dcd MS |
1591 | error (_("sh64_register_convert_to_virtual " |
1592 | "called with non DR register number")); | |
55ff77ac CV |
1593 | } |
1594 | ||
1595 | static void | |
d93859e2 UW |
1596 | sh64_register_convert_to_raw (struct gdbarch *gdbarch, struct type *type, |
1597 | int regnum, const void *from, void *to) | |
55ff77ac | 1598 | { |
d93859e2 | 1599 | if (gdbarch_byte_order (gdbarch) != BFD_ENDIAN_LITTLE) |
55ff77ac | 1600 | { |
7bb11558 | 1601 | /* It is a no-op. */ |
d93859e2 | 1602 | memcpy (to, from, register_size (gdbarch, regnum)); |
55ff77ac CV |
1603 | return; |
1604 | } | |
1605 | ||
1606 | if ((regnum >= DR0_REGNUM | |
1607 | && regnum <= DR_LAST_REGNUM) | |
1608 | || (regnum >= DR0_C_REGNUM | |
1609 | && regnum <= DR_LAST_C_REGNUM)) | |
1610 | { | |
e035e373 | 1611 | DOUBLEST val = extract_typed_floating (from, type); |
7bb11558 MS |
1612 | floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword, |
1613 | &val, to); | |
55ff77ac CV |
1614 | } |
1615 | else | |
a73c6dcd MS |
1616 | error (_("sh64_register_convert_to_raw called " |
1617 | "with non DR register number")); | |
55ff77ac CV |
1618 | } |
1619 | ||
05d1431c PA |
1620 | /* Concatenate PORTIONS contiguous raw registers starting at |
1621 | BASE_REGNUM into BUFFER. */ | |
1622 | ||
1623 | static enum register_status | |
1624 | pseudo_register_read_portions (struct gdbarch *gdbarch, | |
1625 | struct regcache *regcache, | |
1626 | int portions, | |
1627 | int base_regnum, gdb_byte *buffer) | |
1628 | { | |
1629 | int portion; | |
1630 | ||
1631 | for (portion = 0; portion < portions; portion++) | |
1632 | { | |
1633 | enum register_status status; | |
1634 | gdb_byte *b; | |
1635 | ||
1636 | b = buffer + register_size (gdbarch, base_regnum) * portion; | |
1637 | status = regcache_raw_read (regcache, base_regnum + portion, b); | |
1638 | if (status != REG_VALID) | |
1639 | return status; | |
1640 | } | |
1641 | ||
1642 | return REG_VALID; | |
1643 | } | |
1644 | ||
1645 | static enum register_status | |
55ff77ac | 1646 | sh64_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, |
18cf8b5b | 1647 | int reg_nr, gdb_byte *buffer) |
55ff77ac | 1648 | { |
e17a4113 | 1649 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
55ff77ac | 1650 | int base_regnum; |
55ff77ac CV |
1651 | int offset = 0; |
1652 | char temp_buffer[MAX_REGISTER_SIZE]; | |
05d1431c | 1653 | enum register_status status; |
55ff77ac CV |
1654 | |
1655 | if (reg_nr >= DR0_REGNUM | |
1656 | && reg_nr <= DR_LAST_REGNUM) | |
1657 | { | |
d93859e2 | 1658 | base_regnum = sh64_dr_reg_base_num (gdbarch, reg_nr); |
55ff77ac | 1659 | |
7bb11558 | 1660 | /* Build the value in the provided buffer. */ |
55ff77ac | 1661 | /* DR regs are double precision registers obtained by |
7bb11558 | 1662 | concatenating 2 single precision floating point registers. */ |
05d1431c PA |
1663 | status = pseudo_register_read_portions (gdbarch, regcache, |
1664 | 2, base_regnum, temp_buffer); | |
1665 | if (status == REG_VALID) | |
1666 | { | |
1667 | /* We must pay attention to the endianness. */ | |
1668 | sh64_register_convert_to_virtual (gdbarch, reg_nr, | |
1669 | register_type (gdbarch, reg_nr), | |
1670 | temp_buffer, buffer); | |
1671 | } | |
55ff77ac | 1672 | |
05d1431c | 1673 | return status; |
55ff77ac CV |
1674 | } |
1675 | ||
05d1431c | 1676 | else if (reg_nr >= FPP0_REGNUM |
55ff77ac CV |
1677 | && reg_nr <= FPP_LAST_REGNUM) |
1678 | { | |
d93859e2 | 1679 | base_regnum = sh64_fpp_reg_base_num (gdbarch, reg_nr); |
55ff77ac | 1680 | |
7bb11558 | 1681 | /* Build the value in the provided buffer. */ |
55ff77ac | 1682 | /* FPP regs are pairs of single precision registers obtained by |
7bb11558 | 1683 | concatenating 2 single precision floating point registers. */ |
05d1431c PA |
1684 | return pseudo_register_read_portions (gdbarch, regcache, |
1685 | 2, base_regnum, buffer); | |
55ff77ac CV |
1686 | } |
1687 | ||
1688 | else if (reg_nr >= FV0_REGNUM | |
1689 | && reg_nr <= FV_LAST_REGNUM) | |
1690 | { | |
d93859e2 | 1691 | base_regnum = sh64_fv_reg_base_num (gdbarch, reg_nr); |
55ff77ac | 1692 | |
7bb11558 | 1693 | /* Build the value in the provided buffer. */ |
55ff77ac | 1694 | /* FV regs are vectors of single precision registers obtained by |
7bb11558 | 1695 | concatenating 4 single precision floating point registers. */ |
05d1431c PA |
1696 | return pseudo_register_read_portions (gdbarch, regcache, |
1697 | 4, base_regnum, buffer); | |
55ff77ac CV |
1698 | } |
1699 | ||
c378eb4e | 1700 | /* sh compact pseudo registers. 1-to-1 with a shmedia register. */ |
55ff77ac CV |
1701 | else if (reg_nr >= R0_C_REGNUM |
1702 | && reg_nr <= T_C_REGNUM) | |
1703 | { | |
d93859e2 | 1704 | base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr); |
55ff77ac | 1705 | |
7bb11558 | 1706 | /* Build the value in the provided buffer. */ |
05d1431c PA |
1707 | status = regcache_raw_read (regcache, base_regnum, temp_buffer); |
1708 | if (status != REG_VALID) | |
1709 | return status; | |
58643501 | 1710 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
55ff77ac | 1711 | offset = 4; |
c378eb4e MS |
1712 | memcpy (buffer, |
1713 | temp_buffer + offset, 4); /* get LOWER 32 bits only???? */ | |
05d1431c | 1714 | return REG_VALID; |
55ff77ac CV |
1715 | } |
1716 | ||
1717 | else if (reg_nr >= FP0_C_REGNUM | |
1718 | && reg_nr <= FP_LAST_C_REGNUM) | |
1719 | { | |
d93859e2 | 1720 | base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr); |
55ff77ac | 1721 | |
7bb11558 | 1722 | /* Build the value in the provided buffer. */ |
55ff77ac | 1723 | /* Floating point registers map 1-1 to the media fp regs, |
7bb11558 | 1724 | they have the same size and endianness. */ |
05d1431c | 1725 | return regcache_raw_read (regcache, base_regnum, buffer); |
55ff77ac CV |
1726 | } |
1727 | ||
1728 | else if (reg_nr >= DR0_C_REGNUM | |
1729 | && reg_nr <= DR_LAST_C_REGNUM) | |
1730 | { | |
d93859e2 | 1731 | base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr); |
55ff77ac CV |
1732 | |
1733 | /* DR_C regs are double precision registers obtained by | |
7bb11558 | 1734 | concatenating 2 single precision floating point registers. */ |
05d1431c PA |
1735 | status = pseudo_register_read_portions (gdbarch, regcache, |
1736 | 2, base_regnum, temp_buffer); | |
1737 | if (status == REG_VALID) | |
1738 | { | |
1739 | /* We must pay attention to the endianness. */ | |
1740 | sh64_register_convert_to_virtual (gdbarch, reg_nr, | |
1741 | register_type (gdbarch, reg_nr), | |
1742 | temp_buffer, buffer); | |
1743 | } | |
1744 | return status; | |
55ff77ac CV |
1745 | } |
1746 | ||
1747 | else if (reg_nr >= FV0_C_REGNUM | |
1748 | && reg_nr <= FV_LAST_C_REGNUM) | |
1749 | { | |
d93859e2 | 1750 | base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr); |
55ff77ac | 1751 | |
7bb11558 | 1752 | /* Build the value in the provided buffer. */ |
55ff77ac | 1753 | /* FV_C regs are vectors of single precision registers obtained by |
7bb11558 | 1754 | concatenating 4 single precision floating point registers. */ |
05d1431c PA |
1755 | return pseudo_register_read_portions (gdbarch, regcache, |
1756 | 4, base_regnum, buffer); | |
55ff77ac CV |
1757 | } |
1758 | ||
1759 | else if (reg_nr == FPSCR_C_REGNUM) | |
1760 | { | |
1761 | int fpscr_base_regnum; | |
1762 | int sr_base_regnum; | |
1763 | unsigned int fpscr_value; | |
1764 | unsigned int sr_value; | |
1765 | unsigned int fpscr_c_value; | |
1766 | unsigned int fpscr_c_part1_value; | |
1767 | unsigned int fpscr_c_part2_value; | |
1768 | ||
1769 | fpscr_base_regnum = FPSCR_REGNUM; | |
1770 | sr_base_regnum = SR_REGNUM; | |
1771 | ||
7bb11558 | 1772 | /* Build the value in the provided buffer. */ |
55ff77ac CV |
1773 | /* FPSCR_C is a very weird register that contains sparse bits |
1774 | from the FPSCR and the SR architectural registers. | |
1775 | Specifically: */ | |
1776 | /* *INDENT-OFF* */ | |
1777 | /* | |
1778 | FPSRC_C bit | |
1779 | 0 Bit 0 of FPSCR | |
1780 | 1 reserved | |
1781 | 2-17 Bit 2-18 of FPSCR | |
1782 | 18-20 Bits 12,13,14 of SR | |
1783 | 21-31 reserved | |
1784 | */ | |
1785 | /* *INDENT-ON* */ | |
c378eb4e | 1786 | /* Get FPSCR into a local buffer. */ |
05d1431c PA |
1787 | status = regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer); |
1788 | if (status != REG_VALID) | |
1789 | return status; | |
7bb11558 | 1790 | /* Get value as an int. */ |
e17a4113 | 1791 | fpscr_value = extract_unsigned_integer (temp_buffer, 4, byte_order); |
55ff77ac | 1792 | /* Get SR into a local buffer */ |
05d1431c PA |
1793 | status = regcache_raw_read (regcache, sr_base_regnum, temp_buffer); |
1794 | if (status != REG_VALID) | |
1795 | return status; | |
7bb11558 | 1796 | /* Get value as an int. */ |
e17a4113 | 1797 | sr_value = extract_unsigned_integer (temp_buffer, 4, byte_order); |
7bb11558 | 1798 | /* Build the new value. */ |
55ff77ac CV |
1799 | fpscr_c_part1_value = fpscr_value & 0x3fffd; |
1800 | fpscr_c_part2_value = (sr_value & 0x7000) << 6; | |
1801 | fpscr_c_value = fpscr_c_part1_value | fpscr_c_part2_value; | |
c378eb4e | 1802 | /* Store that in out buffer!!! */ |
e17a4113 | 1803 | store_unsigned_integer (buffer, 4, byte_order, fpscr_c_value); |
7bb11558 | 1804 | /* FIXME There is surely an endianness gotcha here. */ |
05d1431c PA |
1805 | |
1806 | return REG_VALID; | |
55ff77ac CV |
1807 | } |
1808 | ||
1809 | else if (reg_nr == FPUL_C_REGNUM) | |
1810 | { | |
d93859e2 | 1811 | base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr); |
55ff77ac CV |
1812 | |
1813 | /* FPUL_C register is floating point register 32, | |
7bb11558 | 1814 | same size, same endianness. */ |
05d1431c | 1815 | return regcache_raw_read (regcache, base_regnum, buffer); |
55ff77ac | 1816 | } |
05d1431c PA |
1817 | else |
1818 | gdb_assert_not_reached ("invalid pseudo register number"); | |
55ff77ac CV |
1819 | } |
1820 | ||
1821 | static void | |
1822 | sh64_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
18cf8b5b | 1823 | int reg_nr, const gdb_byte *buffer) |
55ff77ac | 1824 | { |
e17a4113 | 1825 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
55ff77ac CV |
1826 | int base_regnum, portion; |
1827 | int offset; | |
1828 | char temp_buffer[MAX_REGISTER_SIZE]; | |
55ff77ac CV |
1829 | |
1830 | if (reg_nr >= DR0_REGNUM | |
1831 | && reg_nr <= DR_LAST_REGNUM) | |
1832 | { | |
d93859e2 | 1833 | base_regnum = sh64_dr_reg_base_num (gdbarch, reg_nr); |
7bb11558 | 1834 | /* We must pay attention to the endianness. */ |
d93859e2 | 1835 | sh64_register_convert_to_raw (gdbarch, register_type (gdbarch, reg_nr), |
39add00a MS |
1836 | reg_nr, |
1837 | buffer, temp_buffer); | |
55ff77ac CV |
1838 | |
1839 | /* Write the real regs for which this one is an alias. */ | |
1840 | for (portion = 0; portion < 2; portion++) | |
1841 | regcache_raw_write (regcache, base_regnum + portion, | |
1842 | (temp_buffer | |
7bb11558 MS |
1843 | + register_size (gdbarch, |
1844 | base_regnum) * portion)); | |
55ff77ac CV |
1845 | } |
1846 | ||
1847 | else if (reg_nr >= FPP0_REGNUM | |
1848 | && reg_nr <= FPP_LAST_REGNUM) | |
1849 | { | |
d93859e2 | 1850 | base_regnum = sh64_fpp_reg_base_num (gdbarch, reg_nr); |
55ff77ac CV |
1851 | |
1852 | /* Write the real regs for which this one is an alias. */ | |
1853 | for (portion = 0; portion < 2; portion++) | |
1854 | regcache_raw_write (regcache, base_regnum + portion, | |
1855 | ((char *) buffer | |
7bb11558 MS |
1856 | + register_size (gdbarch, |
1857 | base_regnum) * portion)); | |
55ff77ac CV |
1858 | } |
1859 | ||
1860 | else if (reg_nr >= FV0_REGNUM | |
1861 | && reg_nr <= FV_LAST_REGNUM) | |
1862 | { | |
d93859e2 | 1863 | base_regnum = sh64_fv_reg_base_num (gdbarch, reg_nr); |
55ff77ac CV |
1864 | |
1865 | /* Write the real regs for which this one is an alias. */ | |
1866 | for (portion = 0; portion < 4; portion++) | |
1867 | regcache_raw_write (regcache, base_regnum + portion, | |
1868 | ((char *) buffer | |
7bb11558 MS |
1869 | + register_size (gdbarch, |
1870 | base_regnum) * portion)); | |
55ff77ac CV |
1871 | } |
1872 | ||
c378eb4e | 1873 | /* sh compact general pseudo registers. 1-to-1 with a shmedia |
55ff77ac CV |
1874 | register but only 4 bytes of it. */ |
1875 | else if (reg_nr >= R0_C_REGNUM | |
1876 | && reg_nr <= T_C_REGNUM) | |
1877 | { | |
d93859e2 | 1878 | base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr); |
7bb11558 | 1879 | /* reg_nr is 32 bit here, and base_regnum is 64 bits. */ |
58643501 | 1880 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
55ff77ac CV |
1881 | offset = 4; |
1882 | else | |
1883 | offset = 0; | |
1884 | /* Let's read the value of the base register into a temporary | |
1885 | buffer, so that overwriting the last four bytes with the new | |
7bb11558 | 1886 | value of the pseudo will leave the upper 4 bytes unchanged. */ |
55ff77ac | 1887 | regcache_raw_read (regcache, base_regnum, temp_buffer); |
c378eb4e | 1888 | /* Write as an 8 byte quantity. */ |
55ff77ac CV |
1889 | memcpy (temp_buffer + offset, buffer, 4); |
1890 | regcache_raw_write (regcache, base_regnum, temp_buffer); | |
1891 | } | |
1892 | ||
c378eb4e MS |
1893 | /* sh floating point compact pseudo registers. 1-to-1 with a shmedia |
1894 | registers. Both are 4 bytes. */ | |
55ff77ac CV |
1895 | else if (reg_nr >= FP0_C_REGNUM |
1896 | && reg_nr <= FP_LAST_C_REGNUM) | |
1897 | { | |
d93859e2 | 1898 | base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr); |
55ff77ac CV |
1899 | regcache_raw_write (regcache, base_regnum, buffer); |
1900 | } | |
1901 | ||
1902 | else if (reg_nr >= DR0_C_REGNUM | |
1903 | && reg_nr <= DR_LAST_C_REGNUM) | |
1904 | { | |
d93859e2 | 1905 | base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr); |
55ff77ac CV |
1906 | for (portion = 0; portion < 2; portion++) |
1907 | { | |
7bb11558 | 1908 | /* We must pay attention to the endianness. */ |
d93859e2 UW |
1909 | sh64_register_convert_to_raw (gdbarch, |
1910 | register_type (gdbarch, reg_nr), | |
39add00a MS |
1911 | reg_nr, |
1912 | buffer, temp_buffer); | |
55ff77ac CV |
1913 | |
1914 | regcache_raw_write (regcache, base_regnum + portion, | |
1915 | (temp_buffer | |
7bb11558 MS |
1916 | + register_size (gdbarch, |
1917 | base_regnum) * portion)); | |
55ff77ac CV |
1918 | } |
1919 | } | |
1920 | ||
1921 | else if (reg_nr >= FV0_C_REGNUM | |
1922 | && reg_nr <= FV_LAST_C_REGNUM) | |
1923 | { | |
d93859e2 | 1924 | base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr); |
55ff77ac CV |
1925 | |
1926 | for (portion = 0; portion < 4; portion++) | |
1927 | { | |
1928 | regcache_raw_write (regcache, base_regnum + portion, | |
1929 | ((char *) buffer | |
7bb11558 MS |
1930 | + register_size (gdbarch, |
1931 | base_regnum) * portion)); | |
55ff77ac CV |
1932 | } |
1933 | } | |
1934 | ||
1935 | else if (reg_nr == FPSCR_C_REGNUM) | |
1936 | { | |
1937 | int fpscr_base_regnum; | |
1938 | int sr_base_regnum; | |
1939 | unsigned int fpscr_value; | |
1940 | unsigned int sr_value; | |
1941 | unsigned int old_fpscr_value; | |
1942 | unsigned int old_sr_value; | |
1943 | unsigned int fpscr_c_value; | |
1944 | unsigned int fpscr_mask; | |
1945 | unsigned int sr_mask; | |
1946 | ||
1947 | fpscr_base_regnum = FPSCR_REGNUM; | |
1948 | sr_base_regnum = SR_REGNUM; | |
1949 | ||
1950 | /* FPSCR_C is a very weird register that contains sparse bits | |
1951 | from the FPSCR and the SR architectural registers. | |
1952 | Specifically: */ | |
1953 | /* *INDENT-OFF* */ | |
1954 | /* | |
1955 | FPSRC_C bit | |
1956 | 0 Bit 0 of FPSCR | |
1957 | 1 reserved | |
1958 | 2-17 Bit 2-18 of FPSCR | |
1959 | 18-20 Bits 12,13,14 of SR | |
1960 | 21-31 reserved | |
1961 | */ | |
1962 | /* *INDENT-ON* */ | |
7bb11558 | 1963 | /* Get value as an int. */ |
e17a4113 | 1964 | fpscr_c_value = extract_unsigned_integer (buffer, 4, byte_order); |
55ff77ac | 1965 | |
7bb11558 | 1966 | /* Build the new values. */ |
55ff77ac CV |
1967 | fpscr_mask = 0x0003fffd; |
1968 | sr_mask = 0x001c0000; | |
1969 | ||
1970 | fpscr_value = fpscr_c_value & fpscr_mask; | |
1971 | sr_value = (fpscr_value & sr_mask) >> 6; | |
1972 | ||
1973 | regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer); | |
e17a4113 | 1974 | old_fpscr_value = extract_unsigned_integer (temp_buffer, 4, byte_order); |
55ff77ac CV |
1975 | old_fpscr_value &= 0xfffc0002; |
1976 | fpscr_value |= old_fpscr_value; | |
e17a4113 | 1977 | store_unsigned_integer (temp_buffer, 4, byte_order, fpscr_value); |
55ff77ac CV |
1978 | regcache_raw_write (regcache, fpscr_base_regnum, temp_buffer); |
1979 | ||
1980 | regcache_raw_read (regcache, sr_base_regnum, temp_buffer); | |
e17a4113 | 1981 | old_sr_value = extract_unsigned_integer (temp_buffer, 4, byte_order); |
55ff77ac CV |
1982 | old_sr_value &= 0xffff8fff; |
1983 | sr_value |= old_sr_value; | |
e17a4113 | 1984 | store_unsigned_integer (temp_buffer, 4, byte_order, sr_value); |
55ff77ac CV |
1985 | regcache_raw_write (regcache, sr_base_regnum, temp_buffer); |
1986 | } | |
1987 | ||
1988 | else if (reg_nr == FPUL_C_REGNUM) | |
1989 | { | |
d93859e2 | 1990 | base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr); |
55ff77ac CV |
1991 | regcache_raw_write (regcache, base_regnum, buffer); |
1992 | } | |
1993 | } | |
1994 | ||
55ff77ac | 1995 | /* FIXME:!! THIS SHOULD TAKE CARE OF GETTING THE RIGHT PORTION OF THE |
7bb11558 MS |
1996 | shmedia REGISTERS. */ |
1997 | /* Control registers, compact mode. */ | |
55ff77ac | 1998 | static void |
c30dc700 CV |
1999 | sh64_do_cr_c_register_info (struct ui_file *file, struct frame_info *frame, |
2000 | int cr_c_regnum) | |
55ff77ac CV |
2001 | { |
2002 | switch (cr_c_regnum) | |
2003 | { | |
c30dc700 CV |
2004 | case PC_C_REGNUM: |
2005 | fprintf_filtered (file, "pc_c\t0x%08x\n", | |
2006 | (int) get_frame_register_unsigned (frame, cr_c_regnum)); | |
55ff77ac | 2007 | break; |
c30dc700 CV |
2008 | case GBR_C_REGNUM: |
2009 | fprintf_filtered (file, "gbr_c\t0x%08x\n", | |
2010 | (int) get_frame_register_unsigned (frame, cr_c_regnum)); | |
55ff77ac | 2011 | break; |
c30dc700 CV |
2012 | case MACH_C_REGNUM: |
2013 | fprintf_filtered (file, "mach_c\t0x%08x\n", | |
2014 | (int) get_frame_register_unsigned (frame, cr_c_regnum)); | |
55ff77ac | 2015 | break; |
c30dc700 CV |
2016 | case MACL_C_REGNUM: |
2017 | fprintf_filtered (file, "macl_c\t0x%08x\n", | |
2018 | (int) get_frame_register_unsigned (frame, cr_c_regnum)); | |
55ff77ac | 2019 | break; |
c30dc700 CV |
2020 | case PR_C_REGNUM: |
2021 | fprintf_filtered (file, "pr_c\t0x%08x\n", | |
2022 | (int) get_frame_register_unsigned (frame, cr_c_regnum)); | |
55ff77ac | 2023 | break; |
c30dc700 CV |
2024 | case T_C_REGNUM: |
2025 | fprintf_filtered (file, "t_c\t0x%08x\n", | |
2026 | (int) get_frame_register_unsigned (frame, cr_c_regnum)); | |
55ff77ac | 2027 | break; |
c30dc700 CV |
2028 | case FPSCR_C_REGNUM: |
2029 | fprintf_filtered (file, "fpscr_c\t0x%08x\n", | |
2030 | (int) get_frame_register_unsigned (frame, cr_c_regnum)); | |
55ff77ac | 2031 | break; |
c30dc700 CV |
2032 | case FPUL_C_REGNUM: |
2033 | fprintf_filtered (file, "fpul_c\t0x%08x\n", | |
2034 | (int) get_frame_register_unsigned (frame, cr_c_regnum)); | |
55ff77ac CV |
2035 | break; |
2036 | } | |
2037 | } | |
2038 | ||
2039 | static void | |
c30dc700 CV |
2040 | sh64_do_fp_register (struct gdbarch *gdbarch, struct ui_file *file, |
2041 | struct frame_info *frame, int regnum) | |
c378eb4e | 2042 | { /* Do values for FP (float) regs. */ |
079c8cd0 | 2043 | unsigned char *raw_buffer; |
c378eb4e | 2044 | double flt; /* Double extracted from raw hex data. */ |
55ff77ac CV |
2045 | int inv; |
2046 | int j; | |
2047 | ||
7bb11558 | 2048 | /* Allocate space for the float. */ |
c378eb4e MS |
2049 | raw_buffer = (unsigned char *) |
2050 | alloca (register_size (gdbarch, gdbarch_fp0_regnum (gdbarch))); | |
55ff77ac CV |
2051 | |
2052 | /* Get the data in raw format. */ | |
c30dc700 | 2053 | if (!frame_register_read (frame, regnum, raw_buffer)) |
a73c6dcd | 2054 | error (_("can't read register %d (%s)"), |
58643501 | 2055 | regnum, gdbarch_register_name (gdbarch, regnum)); |
55ff77ac | 2056 | |
c378eb4e MS |
2057 | /* Get the register as a number. */ |
2058 | flt = unpack_double (builtin_type (gdbarch)->builtin_float, | |
2059 | raw_buffer, &inv); | |
55ff77ac | 2060 | |
7bb11558 | 2061 | /* Print the name and some spaces. */ |
58643501 | 2062 | fputs_filtered (gdbarch_register_name (gdbarch, regnum), file); |
c9f4d572 | 2063 | print_spaces_filtered (15 - strlen (gdbarch_register_name |
58643501 | 2064 | (gdbarch, regnum)), file); |
55ff77ac | 2065 | |
7bb11558 | 2066 | /* Print the value. */ |
55ff77ac CV |
2067 | if (inv) |
2068 | fprintf_filtered (file, "<invalid float>"); | |
2069 | else | |
2070 | fprintf_filtered (file, "%-10.9g", flt); | |
2071 | ||
7bb11558 | 2072 | /* Print the fp register as hex. */ |
55ff77ac CV |
2073 | fprintf_filtered (file, "\t(raw 0x"); |
2074 | for (j = 0; j < register_size (gdbarch, regnum); j++) | |
2075 | { | |
58643501 | 2076 | int idx = gdbarch_byte_order (gdbarch) |
4c6b5505 UW |
2077 | == BFD_ENDIAN_BIG ? j : register_size |
2078 | (gdbarch, regnum) - 1 - j; | |
079c8cd0 | 2079 | fprintf_filtered (file, "%02x", raw_buffer[idx]); |
55ff77ac CV |
2080 | } |
2081 | fprintf_filtered (file, ")"); | |
2082 | fprintf_filtered (file, "\n"); | |
2083 | } | |
2084 | ||
2085 | static void | |
c30dc700 CV |
2086 | sh64_do_pseudo_register (struct gdbarch *gdbarch, struct ui_file *file, |
2087 | struct frame_info *frame, int regnum) | |
55ff77ac | 2088 | { |
7bb11558 | 2089 | /* All the sh64-compact mode registers are pseudo registers. */ |
55ff77ac | 2090 | |
58643501 UW |
2091 | if (regnum < gdbarch_num_regs (gdbarch) |
2092 | || regnum >= gdbarch_num_regs (gdbarch) | |
f57d151a UW |
2093 | + NUM_PSEUDO_REGS_SH_MEDIA |
2094 | + NUM_PSEUDO_REGS_SH_COMPACT) | |
55ff77ac | 2095 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 2096 | _("Invalid pseudo register number %d\n"), regnum); |
55ff77ac | 2097 | |
c30dc700 CV |
2098 | else if ((regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)) |
2099 | { | |
d93859e2 | 2100 | int fp_regnum = sh64_dr_reg_base_num (gdbarch, regnum); |
c30dc700 CV |
2101 | fprintf_filtered (file, "dr%d\t0x%08x%08x\n", regnum - DR0_REGNUM, |
2102 | (unsigned) get_frame_register_unsigned (frame, fp_regnum), | |
2103 | (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1)); | |
2104 | } | |
55ff77ac | 2105 | |
c30dc700 CV |
2106 | else if ((regnum >= DR0_C_REGNUM && regnum <= DR_LAST_C_REGNUM)) |
2107 | { | |
d93859e2 | 2108 | int fp_regnum = sh64_compact_reg_base_num (gdbarch, regnum); |
c30dc700 CV |
2109 | fprintf_filtered (file, "dr%d_c\t0x%08x%08x\n", regnum - DR0_C_REGNUM, |
2110 | (unsigned) get_frame_register_unsigned (frame, fp_regnum), | |
2111 | (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1)); | |
2112 | } | |
55ff77ac | 2113 | |
c30dc700 CV |
2114 | else if ((regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM)) |
2115 | { | |
d93859e2 | 2116 | int fp_regnum = sh64_fv_reg_base_num (gdbarch, regnum); |
c30dc700 CV |
2117 | fprintf_filtered (file, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n", |
2118 | regnum - FV0_REGNUM, | |
2119 | (unsigned) get_frame_register_unsigned (frame, fp_regnum), | |
2120 | (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1), | |
2121 | (unsigned) get_frame_register_unsigned (frame, fp_regnum + 2), | |
2122 | (unsigned) get_frame_register_unsigned (frame, fp_regnum + 3)); | |
2123 | } | |
55ff77ac | 2124 | |
c30dc700 CV |
2125 | else if ((regnum >= FV0_C_REGNUM && regnum <= FV_LAST_C_REGNUM)) |
2126 | { | |
d93859e2 | 2127 | int fp_regnum = sh64_compact_reg_base_num (gdbarch, regnum); |
c30dc700 CV |
2128 | fprintf_filtered (file, "fv%d_c\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n", |
2129 | regnum - FV0_C_REGNUM, | |
2130 | (unsigned) get_frame_register_unsigned (frame, fp_regnum), | |
2131 | (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1), | |
2132 | (unsigned) get_frame_register_unsigned (frame, fp_regnum + 2), | |
2133 | (unsigned) get_frame_register_unsigned (frame, fp_regnum + 3)); | |
2134 | } | |
2135 | ||
2136 | else if (regnum >= FPP0_REGNUM && regnum <= FPP_LAST_REGNUM) | |
2137 | { | |
d93859e2 | 2138 | int fp_regnum = sh64_fpp_reg_base_num (gdbarch, regnum); |
c30dc700 CV |
2139 | fprintf_filtered (file, "fpp%d\t0x%08x\t0x%08x\n", regnum - FPP0_REGNUM, |
2140 | (unsigned) get_frame_register_unsigned (frame, fp_regnum), | |
2141 | (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1)); | |
2142 | } | |
2143 | ||
2144 | else if (regnum >= R0_C_REGNUM && regnum <= R_LAST_C_REGNUM) | |
2145 | { | |
d93859e2 | 2146 | int c_regnum = sh64_compact_reg_base_num (gdbarch, regnum); |
c30dc700 CV |
2147 | fprintf_filtered (file, "r%d_c\t0x%08x\n", regnum - R0_C_REGNUM, |
2148 | (unsigned) get_frame_register_unsigned (frame, c_regnum)); | |
2149 | } | |
2150 | else if (regnum >= FP0_C_REGNUM && regnum <= FP_LAST_C_REGNUM) | |
7bb11558 | 2151 | /* This should work also for pseudoregs. */ |
c30dc700 CV |
2152 | sh64_do_fp_register (gdbarch, file, frame, regnum); |
2153 | else if (regnum >= PC_C_REGNUM && regnum <= FPUL_C_REGNUM) | |
2154 | sh64_do_cr_c_register_info (file, frame, regnum); | |
55ff77ac CV |
2155 | } |
2156 | ||
2157 | static void | |
c30dc700 CV |
2158 | sh64_do_register (struct gdbarch *gdbarch, struct ui_file *file, |
2159 | struct frame_info *frame, int regnum) | |
55ff77ac | 2160 | { |
079c8cd0 | 2161 | unsigned char raw_buffer[MAX_REGISTER_SIZE]; |
79a45b7d | 2162 | struct value_print_options opts; |
55ff77ac | 2163 | |
58643501 | 2164 | fputs_filtered (gdbarch_register_name (gdbarch, regnum), file); |
c9f4d572 | 2165 | print_spaces_filtered (15 - strlen (gdbarch_register_name |
58643501 | 2166 | (gdbarch, regnum)), file); |
55ff77ac CV |
2167 | |
2168 | /* Get the data in raw format. */ | |
c30dc700 | 2169 | if (!frame_register_read (frame, regnum, raw_buffer)) |
55ff77ac | 2170 | fprintf_filtered (file, "*value not available*\n"); |
79a45b7d TT |
2171 | |
2172 | get_formatted_print_options (&opts, 'x'); | |
2173 | opts.deref_ref = 1; | |
7b9ee6a8 | 2174 | val_print (register_type (gdbarch, regnum), raw_buffer, 0, 0, |
0e03807e | 2175 | file, 0, NULL, &opts, current_language); |
55ff77ac | 2176 | fprintf_filtered (file, "\t"); |
79a45b7d TT |
2177 | get_formatted_print_options (&opts, 0); |
2178 | opts.deref_ref = 1; | |
7b9ee6a8 | 2179 | val_print (register_type (gdbarch, regnum), raw_buffer, 0, 0, |
0e03807e | 2180 | file, 0, NULL, &opts, current_language); |
55ff77ac CV |
2181 | fprintf_filtered (file, "\n"); |
2182 | } | |
2183 | ||
2184 | static void | |
c30dc700 CV |
2185 | sh64_print_register (struct gdbarch *gdbarch, struct ui_file *file, |
2186 | struct frame_info *frame, int regnum) | |
55ff77ac | 2187 | { |
58643501 UW |
2188 | if (regnum < 0 || regnum >= gdbarch_num_regs (gdbarch) |
2189 | + gdbarch_num_pseudo_regs (gdbarch)) | |
55ff77ac | 2190 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 2191 | _("Invalid register number %d\n"), regnum); |
55ff77ac | 2192 | |
58643501 | 2193 | else if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)) |
55ff77ac | 2194 | { |
7b9ee6a8 | 2195 | if (TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
c30dc700 | 2196 | sh64_do_fp_register (gdbarch, file, frame, regnum); /* FP regs */ |
55ff77ac | 2197 | else |
c30dc700 | 2198 | sh64_do_register (gdbarch, file, frame, regnum); |
55ff77ac CV |
2199 | } |
2200 | ||
58643501 UW |
2201 | else if (regnum < gdbarch_num_regs (gdbarch) |
2202 | + gdbarch_num_pseudo_regs (gdbarch)) | |
c30dc700 | 2203 | sh64_do_pseudo_register (gdbarch, file, frame, regnum); |
55ff77ac CV |
2204 | } |
2205 | ||
2206 | static void | |
c30dc700 CV |
2207 | sh64_media_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
2208 | struct frame_info *frame, int regnum, | |
2209 | int fpregs) | |
55ff77ac | 2210 | { |
c378eb4e | 2211 | if (regnum != -1) /* Do one specified register. */ |
55ff77ac | 2212 | { |
58643501 | 2213 | if (*(gdbarch_register_name (gdbarch, regnum)) == '\0') |
a73c6dcd | 2214 | error (_("Not a valid register for the current processor type")); |
55ff77ac | 2215 | |
c30dc700 | 2216 | sh64_print_register (gdbarch, file, frame, regnum); |
55ff77ac CV |
2217 | } |
2218 | else | |
c378eb4e | 2219 | /* Do all (or most) registers. */ |
55ff77ac CV |
2220 | { |
2221 | regnum = 0; | |
58643501 | 2222 | while (regnum < gdbarch_num_regs (gdbarch)) |
55ff77ac CV |
2223 | { |
2224 | /* If the register name is empty, it is undefined for this | |
2225 | processor, so don't display anything. */ | |
58643501 UW |
2226 | if (gdbarch_register_name (gdbarch, regnum) == NULL |
2227 | || *(gdbarch_register_name (gdbarch, regnum)) == '\0') | |
55ff77ac CV |
2228 | { |
2229 | regnum++; | |
2230 | continue; | |
2231 | } | |
2232 | ||
7b9ee6a8 | 2233 | if (TYPE_CODE (register_type (gdbarch, regnum)) |
c30dc700 | 2234 | == TYPE_CODE_FLT) |
55ff77ac CV |
2235 | { |
2236 | if (fpregs) | |
2237 | { | |
c378eb4e | 2238 | /* true for "INFO ALL-REGISTERS" command. */ |
c30dc700 | 2239 | sh64_do_fp_register (gdbarch, file, frame, regnum); |
55ff77ac CV |
2240 | regnum ++; |
2241 | } | |
2242 | else | |
58643501 | 2243 | regnum += FP_LAST_REGNUM - gdbarch_fp0_regnum (gdbarch); |
3e8c568d | 2244 | /* skip FP regs */ |
55ff77ac CV |
2245 | } |
2246 | else | |
2247 | { | |
c30dc700 | 2248 | sh64_do_register (gdbarch, file, frame, regnum); |
55ff77ac CV |
2249 | regnum++; |
2250 | } | |
2251 | } | |
2252 | ||
2253 | if (fpregs) | |
58643501 UW |
2254 | while (regnum < gdbarch_num_regs (gdbarch) |
2255 | + gdbarch_num_pseudo_regs (gdbarch)) | |
55ff77ac | 2256 | { |
c30dc700 | 2257 | sh64_do_pseudo_register (gdbarch, file, frame, regnum); |
55ff77ac CV |
2258 | regnum++; |
2259 | } | |
2260 | } | |
2261 | } | |
2262 | ||
2263 | static void | |
c30dc700 CV |
2264 | sh64_compact_print_registers_info (struct gdbarch *gdbarch, |
2265 | struct ui_file *file, | |
2266 | struct frame_info *frame, int regnum, | |
2267 | int fpregs) | |
55ff77ac | 2268 | { |
c378eb4e | 2269 | if (regnum != -1) /* Do one specified register. */ |
55ff77ac | 2270 | { |
58643501 | 2271 | if (*(gdbarch_register_name (gdbarch, regnum)) == '\0') |
a73c6dcd | 2272 | error (_("Not a valid register for the current processor type")); |
55ff77ac CV |
2273 | |
2274 | if (regnum >= 0 && regnum < R0_C_REGNUM) | |
a73c6dcd | 2275 | error (_("Not a valid register for the current processor mode.")); |
55ff77ac | 2276 | |
c30dc700 | 2277 | sh64_print_register (gdbarch, file, frame, regnum); |
55ff77ac CV |
2278 | } |
2279 | else | |
c378eb4e | 2280 | /* Do all compact registers. */ |
55ff77ac CV |
2281 | { |
2282 | regnum = R0_C_REGNUM; | |
58643501 UW |
2283 | while (regnum < gdbarch_num_regs (gdbarch) |
2284 | + gdbarch_num_pseudo_regs (gdbarch)) | |
55ff77ac | 2285 | { |
c30dc700 | 2286 | sh64_do_pseudo_register (gdbarch, file, frame, regnum); |
55ff77ac CV |
2287 | regnum++; |
2288 | } | |
2289 | } | |
2290 | } | |
2291 | ||
2292 | static void | |
c30dc700 CV |
2293 | sh64_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
2294 | struct frame_info *frame, int regnum, int fpregs) | |
55ff77ac | 2295 | { |
c30dc700 CV |
2296 | if (pc_is_isa32 (get_frame_pc (frame))) |
2297 | sh64_media_print_registers_info (gdbarch, file, frame, regnum, fpregs); | |
55ff77ac | 2298 | else |
c30dc700 | 2299 | sh64_compact_print_registers_info (gdbarch, file, frame, regnum, fpregs); |
55ff77ac CV |
2300 | } |
2301 | ||
c30dc700 CV |
2302 | static struct sh64_frame_cache * |
2303 | sh64_alloc_frame_cache (void) | |
2304 | { | |
2305 | struct sh64_frame_cache *cache; | |
2306 | int i; | |
2307 | ||
2308 | cache = FRAME_OBSTACK_ZALLOC (struct sh64_frame_cache); | |
2309 | ||
2310 | /* Base address. */ | |
2311 | cache->base = 0; | |
2312 | cache->saved_sp = 0; | |
2313 | cache->sp_offset = 0; | |
2314 | cache->pc = 0; | |
55ff77ac | 2315 | |
c30dc700 CV |
2316 | /* Frameless until proven otherwise. */ |
2317 | cache->uses_fp = 0; | |
55ff77ac | 2318 | |
c30dc700 CV |
2319 | /* Saved registers. We initialize these to -1 since zero is a valid |
2320 | offset (that's where fp is supposed to be stored). */ | |
2321 | for (i = 0; i < SIM_SH64_NR_REGS; i++) | |
2322 | { | |
2323 | cache->saved_regs[i] = -1; | |
2324 | } | |
2325 | ||
2326 | return cache; | |
2327 | } | |
2328 | ||
2329 | static struct sh64_frame_cache * | |
94afd7a6 | 2330 | sh64_frame_cache (struct frame_info *this_frame, void **this_cache) |
55ff77ac | 2331 | { |
58643501 | 2332 | struct gdbarch *gdbarch; |
c30dc700 CV |
2333 | struct sh64_frame_cache *cache; |
2334 | CORE_ADDR current_pc; | |
2335 | int i; | |
55ff77ac | 2336 | |
c30dc700 CV |
2337 | if (*this_cache) |
2338 | return *this_cache; | |
2339 | ||
94afd7a6 | 2340 | gdbarch = get_frame_arch (this_frame); |
c30dc700 CV |
2341 | cache = sh64_alloc_frame_cache (); |
2342 | *this_cache = cache; | |
2343 | ||
94afd7a6 | 2344 | current_pc = get_frame_pc (this_frame); |
c30dc700 CV |
2345 | cache->media_mode = pc_is_isa32 (current_pc); |
2346 | ||
2347 | /* In principle, for normal frames, fp holds the frame pointer, | |
2348 | which holds the base address for the current stack frame. | |
2349 | However, for functions that don't need it, the frame pointer is | |
2350 | optional. For these "frameless" functions the frame pointer is | |
c378eb4e | 2351 | actually the frame pointer of the calling frame. */ |
94afd7a6 | 2352 | cache->base = get_frame_register_unsigned (this_frame, MEDIA_FP_REGNUM); |
c30dc700 CV |
2353 | if (cache->base == 0) |
2354 | return cache; | |
2355 | ||
94afd7a6 | 2356 | cache->pc = get_frame_func (this_frame); |
c30dc700 | 2357 | if (cache->pc != 0) |
58643501 | 2358 | sh64_analyze_prologue (gdbarch, cache, cache->pc, current_pc); |
c30dc700 CV |
2359 | |
2360 | if (!cache->uses_fp) | |
55ff77ac | 2361 | { |
c30dc700 CV |
2362 | /* We didn't find a valid frame, which means that CACHE->base |
2363 | currently holds the frame pointer for our calling frame. If | |
2364 | we're at the start of a function, or somewhere half-way its | |
2365 | prologue, the function's frame probably hasn't been fully | |
2366 | setup yet. Try to reconstruct the base address for the stack | |
2367 | frame by looking at the stack pointer. For truly "frameless" | |
2368 | functions this might work too. */ | |
94afd7a6 UW |
2369 | cache->base = get_frame_register_unsigned |
2370 | (this_frame, gdbarch_sp_regnum (gdbarch)); | |
c30dc700 | 2371 | } |
55ff77ac | 2372 | |
c30dc700 CV |
2373 | /* Now that we have the base address for the stack frame we can |
2374 | calculate the value of sp in the calling frame. */ | |
2375 | cache->saved_sp = cache->base + cache->sp_offset; | |
55ff77ac | 2376 | |
c30dc700 CV |
2377 | /* Adjust all the saved registers such that they contain addresses |
2378 | instead of offsets. */ | |
2379 | for (i = 0; i < SIM_SH64_NR_REGS; i++) | |
2380 | if (cache->saved_regs[i] != -1) | |
2381 | cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i]; | |
55ff77ac | 2382 | |
c30dc700 CV |
2383 | return cache; |
2384 | } | |
55ff77ac | 2385 | |
94afd7a6 UW |
2386 | static struct value * |
2387 | sh64_frame_prev_register (struct frame_info *this_frame, | |
2388 | void **this_cache, int regnum) | |
c30dc700 | 2389 | { |
94afd7a6 UW |
2390 | struct sh64_frame_cache *cache = sh64_frame_cache (this_frame, this_cache); |
2391 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
e17a4113 | 2392 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
55ff77ac | 2393 | |
c30dc700 | 2394 | gdb_assert (regnum >= 0); |
55ff77ac | 2395 | |
58643501 | 2396 | if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp) |
94afd7a6 | 2397 | frame_unwind_got_constant (this_frame, regnum, cache->saved_sp); |
c30dc700 CV |
2398 | |
2399 | /* The PC of the previous frame is stored in the PR register of | |
2400 | the current frame. Frob regnum so that we pull the value from | |
2401 | the correct place. */ | |
58643501 | 2402 | if (regnum == gdbarch_pc_regnum (gdbarch)) |
c30dc700 CV |
2403 | regnum = PR_REGNUM; |
2404 | ||
2405 | if (regnum < SIM_SH64_NR_REGS && cache->saved_regs[regnum] != -1) | |
2406 | { | |
58643501 | 2407 | if (gdbarch_tdep (gdbarch)->sh_abi == SH_ABI_32 |
c30dc700 | 2408 | && (regnum == MEDIA_FP_REGNUM || regnum == PR_REGNUM)) |
c30dc700 | 2409 | { |
94afd7a6 | 2410 | CORE_ADDR val; |
e17a4113 UW |
2411 | val = read_memory_unsigned_integer (cache->saved_regs[regnum], |
2412 | 4, byte_order); | |
94afd7a6 | 2413 | return frame_unwind_got_constant (this_frame, regnum, val); |
c30dc700 | 2414 | } |
94afd7a6 UW |
2415 | |
2416 | return frame_unwind_got_memory (this_frame, regnum, | |
2417 | cache->saved_regs[regnum]); | |
55ff77ac CV |
2418 | } |
2419 | ||
94afd7a6 | 2420 | return frame_unwind_got_register (this_frame, regnum, regnum); |
55ff77ac | 2421 | } |
55ff77ac | 2422 | |
c30dc700 | 2423 | static void |
94afd7a6 | 2424 | sh64_frame_this_id (struct frame_info *this_frame, void **this_cache, |
c30dc700 CV |
2425 | struct frame_id *this_id) |
2426 | { | |
94afd7a6 | 2427 | struct sh64_frame_cache *cache = sh64_frame_cache (this_frame, this_cache); |
c30dc700 CV |
2428 | |
2429 | /* This marks the outermost frame. */ | |
2430 | if (cache->base == 0) | |
2431 | return; | |
2432 | ||
2433 | *this_id = frame_id_build (cache->saved_sp, cache->pc); | |
2434 | } | |
2435 | ||
2436 | static const struct frame_unwind sh64_frame_unwind = { | |
2437 | NORMAL_FRAME, | |
8fbca658 | 2438 | default_frame_unwind_stop_reason, |
c30dc700 | 2439 | sh64_frame_this_id, |
94afd7a6 UW |
2440 | sh64_frame_prev_register, |
2441 | NULL, | |
2442 | default_frame_sniffer | |
c30dc700 CV |
2443 | }; |
2444 | ||
c30dc700 CV |
2445 | static CORE_ADDR |
2446 | sh64_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
2447 | { | |
3e8c568d | 2448 | return frame_unwind_register_unsigned (next_frame, |
58643501 | 2449 | gdbarch_sp_regnum (gdbarch)); |
c30dc700 CV |
2450 | } |
2451 | ||
2452 | static CORE_ADDR | |
2453 | sh64_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
2454 | { | |
3e8c568d | 2455 | return frame_unwind_register_unsigned (next_frame, |
58643501 | 2456 | gdbarch_pc_regnum (gdbarch)); |
c30dc700 CV |
2457 | } |
2458 | ||
2459 | static struct frame_id | |
94afd7a6 | 2460 | sh64_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
c30dc700 | 2461 | { |
94afd7a6 UW |
2462 | CORE_ADDR sp = get_frame_register_unsigned (this_frame, |
2463 | gdbarch_sp_regnum (gdbarch)); | |
2464 | return frame_id_build (sp, get_frame_pc (this_frame)); | |
c30dc700 CV |
2465 | } |
2466 | ||
2467 | static CORE_ADDR | |
94afd7a6 | 2468 | sh64_frame_base_address (struct frame_info *this_frame, void **this_cache) |
c30dc700 | 2469 | { |
94afd7a6 | 2470 | struct sh64_frame_cache *cache = sh64_frame_cache (this_frame, this_cache); |
c30dc700 CV |
2471 | |
2472 | return cache->base; | |
2473 | } | |
2474 | ||
2475 | static const struct frame_base sh64_frame_base = { | |
2476 | &sh64_frame_unwind, | |
2477 | sh64_frame_base_address, | |
2478 | sh64_frame_base_address, | |
2479 | sh64_frame_base_address | |
2480 | }; | |
2481 | ||
55ff77ac CV |
2482 | |
2483 | struct gdbarch * | |
2484 | sh64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
2485 | { | |
55ff77ac CV |
2486 | struct gdbarch *gdbarch; |
2487 | struct gdbarch_tdep *tdep; | |
2488 | ||
2489 | /* If there is already a candidate, use it. */ | |
2490 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
2491 | if (arches != NULL) | |
2492 | return arches->gdbarch; | |
2493 | ||
2494 | /* None found, create a new architecture from the information | |
7bb11558 | 2495 | provided. */ |
55ff77ac CV |
2496 | tdep = XMALLOC (struct gdbarch_tdep); |
2497 | gdbarch = gdbarch_alloc (&info, tdep); | |
2498 | ||
55ff77ac CV |
2499 | /* Determine the ABI */ |
2500 | if (info.abfd && bfd_get_arch_size (info.abfd) == 64) | |
2501 | { | |
7bb11558 | 2502 | /* If the ABI is the 64-bit one, it can only be sh-media. */ |
55ff77ac CV |
2503 | tdep->sh_abi = SH_ABI_64; |
2504 | set_gdbarch_ptr_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
2505 | set_gdbarch_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
2506 | } | |
2507 | else | |
2508 | { | |
2509 | /* If the ABI is the 32-bit one it could be either media or | |
7bb11558 | 2510 | compact. */ |
55ff77ac CV |
2511 | tdep->sh_abi = SH_ABI_32; |
2512 | set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
2513 | set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
2514 | } | |
2515 | ||
2516 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); | |
2517 | set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
c30dc700 | 2518 | set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
55ff77ac CV |
2519 | set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); |
2520 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
2521 | set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
2522 | set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
2523 | ||
c30dc700 CV |
2524 | /* The number of real registers is the same whether we are in |
2525 | ISA16(compact) or ISA32(media). */ | |
2526 | set_gdbarch_num_regs (gdbarch, SIM_SH64_NR_REGS); | |
55ff77ac | 2527 | set_gdbarch_sp_regnum (gdbarch, 15); |
c30dc700 CV |
2528 | set_gdbarch_pc_regnum (gdbarch, 64); |
2529 | set_gdbarch_fp0_regnum (gdbarch, SIM_SH64_FR0_REGNUM); | |
2530 | set_gdbarch_num_pseudo_regs (gdbarch, NUM_PSEUDO_REGS_SH_MEDIA | |
2531 | + NUM_PSEUDO_REGS_SH_COMPACT); | |
55ff77ac | 2532 | |
c30dc700 CV |
2533 | set_gdbarch_register_name (gdbarch, sh64_register_name); |
2534 | set_gdbarch_register_type (gdbarch, sh64_register_type); | |
2535 | ||
2536 | set_gdbarch_pseudo_register_read (gdbarch, sh64_pseudo_register_read); | |
2537 | set_gdbarch_pseudo_register_write (gdbarch, sh64_pseudo_register_write); | |
2538 | ||
2539 | set_gdbarch_breakpoint_from_pc (gdbarch, sh64_breakpoint_from_pc); | |
2540 | ||
9dae60cc | 2541 | set_gdbarch_print_insn (gdbarch, print_insn_sh); |
55ff77ac CV |
2542 | set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno); |
2543 | ||
c30dc700 | 2544 | set_gdbarch_return_value (gdbarch, sh64_return_value); |
55ff77ac | 2545 | |
c30dc700 CV |
2546 | set_gdbarch_skip_prologue (gdbarch, sh64_skip_prologue); |
2547 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
55ff77ac | 2548 | |
c30dc700 | 2549 | set_gdbarch_push_dummy_call (gdbarch, sh64_push_dummy_call); |
55ff77ac | 2550 | |
c30dc700 | 2551 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); |
55ff77ac | 2552 | |
c30dc700 CV |
2553 | set_gdbarch_frame_align (gdbarch, sh64_frame_align); |
2554 | set_gdbarch_unwind_sp (gdbarch, sh64_unwind_sp); | |
2555 | set_gdbarch_unwind_pc (gdbarch, sh64_unwind_pc); | |
94afd7a6 | 2556 | set_gdbarch_dummy_id (gdbarch, sh64_dummy_id); |
c30dc700 | 2557 | frame_base_set_default (gdbarch, &sh64_frame_base); |
55ff77ac | 2558 | |
c30dc700 | 2559 | set_gdbarch_print_registers_info (gdbarch, sh64_print_registers_info); |
55ff77ac | 2560 | |
55ff77ac CV |
2561 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
2562 | sh64_elf_make_msymbol_special); | |
2563 | ||
2564 | /* Hook in ABI-specific overrides, if they have been registered. */ | |
2565 | gdbarch_init_osabi (info, gdbarch); | |
2566 | ||
94afd7a6 UW |
2567 | dwarf2_append_unwinders (gdbarch); |
2568 | frame_unwind_append_unwinder (gdbarch, &sh64_frame_unwind); | |
c30dc700 | 2569 | |
55ff77ac CV |
2570 | return gdbarch; |
2571 | } |