Commit | Line | Data |
---|---|---|
85a453d5 | 1 | /* Target-dependent code for Renesas Super-H, for GDB. |
cf5b2f1b | 2 | |
32d0add0 | 3 | Copyright (C) 1993-2015 Free Software Foundation, Inc. |
55ff77ac CV |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
55ff77ac CV |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
55ff77ac | 19 | |
c378eb4e MS |
20 | /* Contributed by Steve Chamberlain |
21 | sac@cygnus.com. */ | |
55ff77ac CV |
22 | |
23 | #include "defs.h" | |
24 | #include "frame.h" | |
c30dc700 CV |
25 | #include "frame-base.h" |
26 | #include "frame-unwind.h" | |
27 | #include "dwarf2-frame.h" | |
55ff77ac | 28 | #include "symtab.h" |
55ff77ac CV |
29 | #include "gdbtypes.h" |
30 | #include "gdbcmd.h" | |
31 | #include "gdbcore.h" | |
32 | #include "value.h" | |
33 | #include "dis-asm.h" | |
34 | #include "inferior.h" | |
55ff77ac | 35 | #include "arch-utils.h" |
55ff77ac | 36 | #include "regcache.h" |
55ff77ac | 37 | #include "osabi.h" |
79a45b7d | 38 | #include "valprint.h" |
55ff77ac CV |
39 | |
40 | #include "elf-bfd.h" | |
55ff77ac CV |
41 | |
42 | /* sh flags */ | |
43 | #include "elf/sh.h" | |
c378eb4e | 44 | /* Register numbers shared with the simulator. */ |
55ff77ac | 45 | #include "gdb/sim-sh.h" |
d8ca156b | 46 | #include "language.h" |
04dcf5fa | 47 | #include "sh64-tdep.h" |
55ff77ac | 48 | |
7bb11558 | 49 | /* Information that is dependent on the processor variant. */ |
55ff77ac CV |
50 | enum sh_abi |
51 | { | |
52 | SH_ABI_UNKNOWN, | |
53 | SH_ABI_32, | |
54 | SH_ABI_64 | |
55 | }; | |
56 | ||
57 | struct gdbarch_tdep | |
58 | { | |
59 | enum sh_abi sh_abi; | |
60 | }; | |
61 | ||
c30dc700 CV |
62 | struct sh64_frame_cache |
63 | { | |
64 | /* Base address. */ | |
65 | CORE_ADDR base; | |
66 | LONGEST sp_offset; | |
67 | CORE_ADDR pc; | |
68 | ||
c378eb4e | 69 | /* Flag showing that a frame has been created in the prologue code. */ |
c30dc700 CV |
70 | int uses_fp; |
71 | ||
72 | int media_mode; | |
73 | ||
74 | /* Saved registers. */ | |
75 | CORE_ADDR saved_regs[SIM_SH64_NR_REGS]; | |
76 | CORE_ADDR saved_sp; | |
77 | }; | |
78 | ||
55ff77ac CV |
79 | /* Registers of SH5 */ |
80 | enum | |
81 | { | |
82 | R0_REGNUM = 0, | |
83 | DEFAULT_RETURN_REGNUM = 2, | |
84 | STRUCT_RETURN_REGNUM = 2, | |
85 | ARG0_REGNUM = 2, | |
86 | ARGLAST_REGNUM = 9, | |
87 | FLOAT_ARGLAST_REGNUM = 11, | |
c30dc700 | 88 | MEDIA_FP_REGNUM = 14, |
55ff77ac CV |
89 | PR_REGNUM = 18, |
90 | SR_REGNUM = 65, | |
91 | DR0_REGNUM = 141, | |
92 | DR_LAST_REGNUM = 172, | |
93 | /* FPP stands for Floating Point Pair, to avoid confusion with | |
3e8c568d | 94 | GDB's gdbarch_fp0_regnum, which is the number of the first Floating |
c378eb4e | 95 | point register. Unfortunately on the sh5, the floating point |
7bb11558 | 96 | registers are called FR, and the floating point pairs are called FP. */ |
55ff77ac CV |
97 | FPP0_REGNUM = 173, |
98 | FPP_LAST_REGNUM = 204, | |
99 | FV0_REGNUM = 205, | |
100 | FV_LAST_REGNUM = 220, | |
101 | R0_C_REGNUM = 221, | |
102 | R_LAST_C_REGNUM = 236, | |
103 | PC_C_REGNUM = 237, | |
104 | GBR_C_REGNUM = 238, | |
105 | MACH_C_REGNUM = 239, | |
106 | MACL_C_REGNUM = 240, | |
107 | PR_C_REGNUM = 241, | |
108 | T_C_REGNUM = 242, | |
109 | FPSCR_C_REGNUM = 243, | |
110 | FPUL_C_REGNUM = 244, | |
111 | FP0_C_REGNUM = 245, | |
112 | FP_LAST_C_REGNUM = 260, | |
113 | DR0_C_REGNUM = 261, | |
114 | DR_LAST_C_REGNUM = 268, | |
115 | FV0_C_REGNUM = 269, | |
116 | FV_LAST_C_REGNUM = 272, | |
117 | FPSCR_REGNUM = SIM_SH64_FPCSR_REGNUM, | |
118 | SSR_REGNUM = SIM_SH64_SSR_REGNUM, | |
119 | SPC_REGNUM = SIM_SH64_SPC_REGNUM, | |
120 | TR7_REGNUM = SIM_SH64_TR0_REGNUM + 7, | |
121 | FP_LAST_REGNUM = SIM_SH64_FR0_REGNUM + SIM_SH64_NR_FP_REGS - 1 | |
122 | }; | |
123 | ||
55ff77ac | 124 | static const char * |
d93859e2 | 125 | sh64_register_name (struct gdbarch *gdbarch, int reg_nr) |
55ff77ac CV |
126 | { |
127 | static char *register_names[] = | |
128 | { | |
129 | /* SH MEDIA MODE (ISA 32) */ | |
130 | /* general registers (64-bit) 0-63 */ | |
131 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
132 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
133 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
134 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", | |
135 | "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", | |
136 | "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", | |
137 | "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", | |
138 | "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", | |
139 | ||
140 | /* pc (64-bit) 64 */ | |
141 | "pc", | |
142 | ||
143 | /* status reg., saved status reg., saved pc reg. (64-bit) 65-67 */ | |
144 | "sr", "ssr", "spc", | |
145 | ||
c378eb4e | 146 | /* target registers (64-bit) 68-75 */ |
55ff77ac CV |
147 | "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", |
148 | ||
149 | /* floating point state control register (32-bit) 76 */ | |
150 | "fpscr", | |
151 | ||
c378eb4e | 152 | /* single precision floating point registers (32-bit) 77-140 */ |
55ff77ac CV |
153 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", |
154 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
155 | "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", | |
156 | "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", | |
157 | "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", | |
158 | "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", | |
159 | "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", | |
160 | "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", | |
161 | ||
162 | /* double precision registers (pseudo) 141-172 */ | |
163 | "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", | |
164 | "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", | |
165 | "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", | |
166 | "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62", | |
167 | ||
c378eb4e | 168 | /* floating point pairs (pseudo) 173-204 */ |
55ff77ac CV |
169 | "fp0", "fp2", "fp4", "fp6", "fp8", "fp10", "fp12", "fp14", |
170 | "fp16", "fp18", "fp20", "fp22", "fp24", "fp26", "fp28", "fp30", | |
171 | "fp32", "fp34", "fp36", "fp38", "fp40", "fp42", "fp44", "fp46", | |
172 | "fp48", "fp50", "fp52", "fp54", "fp56", "fp58", "fp60", "fp62", | |
173 | ||
c378eb4e | 174 | /* floating point vectors (4 floating point regs) (pseudo) 205-220 */ |
55ff77ac CV |
175 | "fv0", "fv4", "fv8", "fv12", "fv16", "fv20", "fv24", "fv28", |
176 | "fv32", "fv36", "fv40", "fv44", "fv48", "fv52", "fv56", "fv60", | |
177 | ||
c378eb4e | 178 | /* SH COMPACT MODE (ISA 16) (all pseudo) 221-272 */ |
55ff77ac CV |
179 | "r0_c", "r1_c", "r2_c", "r3_c", "r4_c", "r5_c", "r6_c", "r7_c", |
180 | "r8_c", "r9_c", "r10_c", "r11_c", "r12_c", "r13_c", "r14_c", "r15_c", | |
181 | "pc_c", | |
182 | "gbr_c", "mach_c", "macl_c", "pr_c", "t_c", | |
183 | "fpscr_c", "fpul_c", | |
c378eb4e MS |
184 | "fr0_c", "fr1_c", "fr2_c", "fr3_c", |
185 | "fr4_c", "fr5_c", "fr6_c", "fr7_c", | |
186 | "fr8_c", "fr9_c", "fr10_c", "fr11_c", | |
187 | "fr12_c", "fr13_c", "fr14_c", "fr15_c", | |
188 | "dr0_c", "dr2_c", "dr4_c", "dr6_c", | |
189 | "dr8_c", "dr10_c", "dr12_c", "dr14_c", | |
55ff77ac | 190 | "fv0_c", "fv4_c", "fv8_c", "fv12_c", |
c378eb4e | 191 | /* FIXME!!!! XF0 XF15, XD0 XD14 ????? */ |
55ff77ac CV |
192 | }; |
193 | ||
194 | if (reg_nr < 0) | |
195 | return NULL; | |
196 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
197 | return NULL; | |
198 | return register_names[reg_nr]; | |
199 | } | |
200 | ||
201 | #define NUM_PSEUDO_REGS_SH_MEDIA 80 | |
202 | #define NUM_PSEUDO_REGS_SH_COMPACT 51 | |
203 | ||
204 | /* Macros and functions for setting and testing a bit in a minimal | |
205 | symbol that marks it as 32-bit function. The MSB of the minimal | |
f594e5e9 | 206 | symbol's "info" field is used for this purpose. |
55ff77ac | 207 | |
95f1da47 UW |
208 | gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special", |
209 | i.e. refers to a 32-bit function, and sets a "special" bit in a | |
55ff77ac | 210 | minimal symbol to mark it as a 32-bit function |
f594e5e9 | 211 | MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */ |
55ff77ac CV |
212 | |
213 | #define MSYMBOL_IS_SPECIAL(msym) \ | |
b887350f | 214 | MSYMBOL_TARGET_FLAG_1 (msym) |
55ff77ac CV |
215 | |
216 | static void | |
217 | sh64_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym) | |
218 | { | |
219 | if (msym == NULL) | |
220 | return; | |
221 | ||
222 | if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_SH5_ISA32) | |
223 | { | |
b887350f | 224 | MSYMBOL_TARGET_FLAG_1 (msym) = 1; |
77e371c0 | 225 | SET_MSYMBOL_VALUE_ADDRESS (msym, MSYMBOL_VALUE_RAW_ADDRESS (msym) | 1); |
55ff77ac CV |
226 | } |
227 | } | |
228 | ||
229 | /* ISA32 (shmedia) function addresses are odd (bit 0 is set). Here | |
230 | are some macros to test, set, or clear bit 0 of addresses. */ | |
231 | #define IS_ISA32_ADDR(addr) ((addr) & 1) | |
232 | #define MAKE_ISA32_ADDR(addr) ((addr) | 1) | |
233 | #define UNMAKE_ISA32_ADDR(addr) ((addr) & ~1) | |
234 | ||
235 | static int | |
236 | pc_is_isa32 (bfd_vma memaddr) | |
237 | { | |
7cbd4a93 | 238 | struct bound_minimal_symbol sym; |
55ff77ac CV |
239 | |
240 | /* If bit 0 of the address is set, assume this is a | |
7bb11558 | 241 | ISA32 (shmedia) address. */ |
55ff77ac CV |
242 | if (IS_ISA32_ADDR (memaddr)) |
243 | return 1; | |
244 | ||
245 | /* A flag indicating that this is a ISA32 function is stored by elfread.c in | |
246 | the high bit of the info field. Use this to decide if the function is | |
247 | ISA16 or ISA32. */ | |
248 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
7cbd4a93 TT |
249 | if (sym.minsym) |
250 | return MSYMBOL_IS_SPECIAL (sym.minsym); | |
55ff77ac CV |
251 | else |
252 | return 0; | |
253 | } | |
254 | ||
255 | static const unsigned char * | |
c378eb4e MS |
256 | sh64_breakpoint_from_pc (struct gdbarch *gdbarch, |
257 | CORE_ADDR *pcptr, int *lenptr) | |
55ff77ac CV |
258 | { |
259 | /* The BRK instruction for shmedia is | |
260 | 01101111 11110101 11111111 11110000 | |
261 | which translates in big endian mode to 0x6f, 0xf5, 0xff, 0xf0 | |
262 | and in little endian mode to 0xf0, 0xff, 0xf5, 0x6f */ | |
263 | ||
264 | /* The BRK instruction for shcompact is | |
265 | 00000000 00111011 | |
266 | which translates in big endian mode to 0x0, 0x3b | |
c378eb4e | 267 | and in little endian mode to 0x3b, 0x0 */ |
55ff77ac | 268 | |
67d57894 | 269 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
55ff77ac CV |
270 | { |
271 | if (pc_is_isa32 (*pcptr)) | |
272 | { | |
c378eb4e MS |
273 | static unsigned char big_breakpoint_media[] = { |
274 | 0x6f, 0xf5, 0xff, 0xf0 | |
275 | }; | |
55ff77ac CV |
276 | *pcptr = UNMAKE_ISA32_ADDR (*pcptr); |
277 | *lenptr = sizeof (big_breakpoint_media); | |
278 | return big_breakpoint_media; | |
279 | } | |
280 | else | |
281 | { | |
282 | static unsigned char big_breakpoint_compact[] = {0x0, 0x3b}; | |
283 | *lenptr = sizeof (big_breakpoint_compact); | |
284 | return big_breakpoint_compact; | |
285 | } | |
286 | } | |
287 | else | |
288 | { | |
289 | if (pc_is_isa32 (*pcptr)) | |
290 | { | |
c378eb4e MS |
291 | static unsigned char little_breakpoint_media[] = { |
292 | 0xf0, 0xff, 0xf5, 0x6f | |
293 | }; | |
55ff77ac CV |
294 | *pcptr = UNMAKE_ISA32_ADDR (*pcptr); |
295 | *lenptr = sizeof (little_breakpoint_media); | |
296 | return little_breakpoint_media; | |
297 | } | |
298 | else | |
299 | { | |
300 | static unsigned char little_breakpoint_compact[] = {0x3b, 0x0}; | |
301 | *lenptr = sizeof (little_breakpoint_compact); | |
302 | return little_breakpoint_compact; | |
303 | } | |
304 | } | |
305 | } | |
306 | ||
307 | /* Prologue looks like | |
308 | [mov.l <regs>,@-r15]... | |
309 | [sts.l pr,@-r15] | |
310 | [mov.l r14,@-r15] | |
311 | [mov r15,r14] | |
312 | ||
313 | Actually it can be more complicated than this. For instance, with | |
314 | newer gcc's: | |
315 | ||
316 | mov.l r14,@-r15 | |
317 | add #-12,r15 | |
318 | mov r15,r14 | |
319 | mov r4,r1 | |
320 | mov r5,r2 | |
321 | mov.l r6,@(4,r14) | |
322 | mov.l r7,@(8,r14) | |
323 | mov.b r1,@r14 | |
324 | mov r14,r1 | |
325 | mov r14,r1 | |
326 | add #2,r1 | |
327 | mov.w r2,@r1 | |
328 | ||
329 | */ | |
330 | ||
331 | /* PTABS/L Rn, TRa 0110101111110001nnnnnnl00aaa0000 | |
332 | with l=1 and n = 18 0110101111110001010010100aaa0000 */ | |
333 | #define IS_PTABSL_R18(x) (((x) & 0xffffff8f) == 0x6bf14a00) | |
334 | ||
335 | /* STS.L PR,@-r0 0100000000100010 | |
336 | r0-4-->r0, PR-->(r0) */ | |
337 | #define IS_STS_R0(x) ((x) == 0x4022) | |
338 | ||
339 | /* STS PR, Rm 0000mmmm00101010 | |
340 | PR-->Rm */ | |
341 | #define IS_STS_PR(x) (((x) & 0xf0ff) == 0x2a) | |
342 | ||
343 | /* MOV.L Rm,@(disp,r15) 00011111mmmmdddd | |
344 | Rm-->(dispx4+r15) */ | |
345 | #define IS_MOV_TO_R15(x) (((x) & 0xff00) == 0x1f00) | |
346 | ||
347 | /* MOV.L R14,@(disp,r15) 000111111110dddd | |
348 | R14-->(dispx4+r15) */ | |
349 | #define IS_MOV_R14(x) (((x) & 0xfff0) == 0x1fe0) | |
350 | ||
351 | /* ST.Q R14, disp, R18 101011001110dddddddddd0100100000 | |
352 | R18-->(dispx8+R14) */ | |
353 | #define IS_STQ_R18_R14(x) (((x) & 0xfff003ff) == 0xace00120) | |
354 | ||
355 | /* ST.Q R15, disp, R18 101011001111dddddddddd0100100000 | |
356 | R18-->(dispx8+R15) */ | |
357 | #define IS_STQ_R18_R15(x) (((x) & 0xfff003ff) == 0xacf00120) | |
358 | ||
359 | /* ST.L R15, disp, R18 101010001111dddddddddd0100100000 | |
360 | R18-->(dispx4+R15) */ | |
361 | #define IS_STL_R18_R15(x) (((x) & 0xfff003ff) == 0xa8f00120) | |
362 | ||
363 | /* ST.Q R15, disp, R14 1010 1100 1111 dddd dddd dd00 1110 0000 | |
364 | R14-->(dispx8+R15) */ | |
365 | #define IS_STQ_R14_R15(x) (((x) & 0xfff003ff) == 0xacf000e0) | |
366 | ||
367 | /* ST.L R15, disp, R14 1010 1000 1111 dddd dddd dd00 1110 0000 | |
368 | R14-->(dispx4+R15) */ | |
369 | #define IS_STL_R14_R15(x) (((x) & 0xfff003ff) == 0xa8f000e0) | |
370 | ||
371 | /* ADDI.L R15,imm,R15 1101 0100 1111 ssss ssss ss00 1111 0000 | |
372 | R15 + imm --> R15 */ | |
373 | #define IS_ADDIL_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd4f000f0) | |
374 | ||
375 | /* ADDI R15,imm,R15 1101 0000 1111 ssss ssss ss00 1111 0000 | |
376 | R15 + imm --> R15 */ | |
377 | #define IS_ADDI_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd0f000f0) | |
378 | ||
379 | /* ADD.L R15,R63,R14 0000 0000 1111 1000 1111 1100 1110 0000 | |
380 | R15 + R63 --> R14 */ | |
381 | #define IS_ADDL_SP_FP_MEDIA(x) ((x) == 0x00f8fce0) | |
382 | ||
383 | /* ADD R15,R63,R14 0000 0000 1111 1001 1111 1100 1110 0000 | |
384 | R15 + R63 --> R14 */ | |
385 | #define IS_ADD_SP_FP_MEDIA(x) ((x) == 0x00f9fce0) | |
386 | ||
c378eb4e MS |
387 | #define IS_MOV_SP_FP_MEDIA(x) \ |
388 | (IS_ADDL_SP_FP_MEDIA(x) || IS_ADD_SP_FP_MEDIA(x)) | |
55ff77ac CV |
389 | |
390 | /* MOV #imm, R0 1110 0000 ssss ssss | |
391 | #imm-->R0 */ | |
392 | #define IS_MOV_R0(x) (((x) & 0xff00) == 0xe000) | |
393 | ||
394 | /* MOV.L @(disp,PC), R0 1101 0000 iiii iiii */ | |
395 | #define IS_MOVL_R0(x) (((x) & 0xff00) == 0xd000) | |
396 | ||
397 | /* ADD r15,r0 0011 0000 1111 1100 | |
398 | r15+r0-->r0 */ | |
399 | #define IS_ADD_SP_R0(x) ((x) == 0x30fc) | |
400 | ||
401 | /* MOV.L R14 @-R0 0010 0000 1110 0110 | |
402 | R14-->(R0-4), R0-4-->R0 */ | |
403 | #define IS_MOV_R14_R0(x) ((x) == 0x20e6) | |
404 | ||
405 | /* ADD Rm,R63,Rn Rm+R63-->Rn 0000 00mm mmmm 1001 1111 11nn nnnn 0000 | |
7bb11558 | 406 | where Rm is one of r2-r9 which are the argument registers. */ |
c378eb4e | 407 | /* FIXME: Recognize the float and double register moves too! */ |
55ff77ac | 408 | #define IS_MEDIA_IND_ARG_MOV(x) \ |
c378eb4e MS |
409 | ((((x) & 0xfc0ffc0f) == 0x0009fc00) \ |
410 | && (((x) & 0x03f00000) >= 0x00200000 \ | |
411 | && ((x) & 0x03f00000) <= 0x00900000)) | |
55ff77ac CV |
412 | |
413 | /* ST.Q Rn,0,Rm Rm-->Rn+0 1010 11nn nnnn 0000 0000 00mm mmmm 0000 | |
414 | or ST.L Rn,0,Rm Rm-->Rn+0 1010 10nn nnnn 0000 0000 00mm mmmm 0000 | |
7bb11558 | 415 | where Rm is one of r2-r9 which are the argument registers. */ |
55ff77ac CV |
416 | #define IS_MEDIA_ARG_MOV(x) \ |
417 | (((((x) & 0xfc0ffc0f) == 0xac000000) || (((x) & 0xfc0ffc0f) == 0xa8000000)) \ | |
418 | && (((x) & 0x000003f0) >= 0x00000020 && ((x) & 0x000003f0) <= 0x00000090)) | |
419 | ||
c378eb4e MS |
420 | /* ST.B R14,0,Rn Rn-->(R14+0) 1010 0000 1110 0000 0000 00nn nnnn 0000 */ |
421 | /* ST.W R14,0,Rn Rn-->(R14+0) 1010 0100 1110 0000 0000 00nn nnnn 0000 */ | |
422 | /* ST.L R14,0,Rn Rn-->(R14+0) 1010 1000 1110 0000 0000 00nn nnnn 0000 */ | |
423 | /* FST.S R14,0,FRn Rn-->(R14+0) 1011 0100 1110 0000 0000 00nn nnnn 0000 */ | |
424 | /* FST.D R14,0,DRn Rn-->(R14+0) 1011 1100 1110 0000 0000 00nn nnnn 0000 */ | |
55ff77ac CV |
425 | #define IS_MEDIA_MOV_TO_R14(x) \ |
426 | ((((x) & 0xfffffc0f) == 0xa0e00000) \ | |
427 | || (((x) & 0xfffffc0f) == 0xa4e00000) \ | |
428 | || (((x) & 0xfffffc0f) == 0xa8e00000) \ | |
429 | || (((x) & 0xfffffc0f) == 0xb4e00000) \ | |
430 | || (((x) & 0xfffffc0f) == 0xbce00000)) | |
431 | ||
432 | /* MOV Rm, Rn Rm-->Rn 0110 nnnn mmmm 0011 | |
433 | where Rm is r2-r9 */ | |
434 | #define IS_COMPACT_IND_ARG_MOV(x) \ | |
c378eb4e MS |
435 | ((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0020) \ |
436 | && (((x) & 0x00f0) <= 0x0090)) | |
55ff77ac CV |
437 | |
438 | /* compact direct arg move! | |
439 | MOV.L Rn, @r14 0010 1110 mmmm 0010 */ | |
440 | #define IS_COMPACT_ARG_MOV(x) \ | |
c378eb4e MS |
441 | (((((x) & 0xff0f) == 0x2e02) && (((x) & 0x00f0) >= 0x0020) \ |
442 | && ((x) & 0x00f0) <= 0x0090)) | |
55ff77ac CV |
443 | |
444 | /* MOV.B Rm, @R14 0010 1110 mmmm 0000 | |
445 | MOV.W Rm, @R14 0010 1110 mmmm 0001 */ | |
446 | #define IS_COMPACT_MOV_TO_R14(x) \ | |
447 | ((((x) & 0xff0f) == 0x2e00) || (((x) & 0xff0f) == 0x2e01)) | |
448 | ||
449 | #define IS_JSR_R0(x) ((x) == 0x400b) | |
450 | #define IS_NOP(x) ((x) == 0x0009) | |
451 | ||
452 | ||
453 | /* MOV r15,r14 0110111011110011 | |
454 | r15-->r14 */ | |
455 | #define IS_MOV_SP_FP(x) ((x) == 0x6ef3) | |
456 | ||
457 | /* ADD #imm,r15 01111111iiiiiiii | |
458 | r15+imm-->r15 */ | |
459 | #define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00) | |
460 | ||
c378eb4e | 461 | /* Skip any prologue before the guts of a function. */ |
55ff77ac | 462 | |
7bb11558 MS |
463 | /* Skip the prologue using the debug information. If this fails we'll |
464 | fall back on the 'guess' method below. */ | |
55ff77ac CV |
465 | static CORE_ADDR |
466 | after_prologue (CORE_ADDR pc) | |
467 | { | |
468 | struct symtab_and_line sal; | |
469 | CORE_ADDR func_addr, func_end; | |
470 | ||
471 | /* If we can not find the symbol in the partial symbol table, then | |
472 | there is no hope we can determine the function's start address | |
473 | with this code. */ | |
474 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
475 | return 0; | |
476 | ||
c30dc700 | 477 | |
55ff77ac CV |
478 | /* Get the line associated with FUNC_ADDR. */ |
479 | sal = find_pc_line (func_addr, 0); | |
480 | ||
481 | /* There are only two cases to consider. First, the end of the source line | |
482 | is within the function bounds. In that case we return the end of the | |
483 | source line. Second is the end of the source line extends beyond the | |
484 | bounds of the current function. We need to use the slow code to | |
485 | examine instructions in that case. */ | |
486 | if (sal.end < func_end) | |
487 | return sal.end; | |
488 | else | |
489 | return 0; | |
490 | } | |
491 | ||
492 | static CORE_ADDR | |
e17a4113 UW |
493 | look_for_args_moves (struct gdbarch *gdbarch, |
494 | CORE_ADDR start_pc, int media_mode) | |
55ff77ac | 495 | { |
e17a4113 | 496 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
55ff77ac CV |
497 | CORE_ADDR here, end; |
498 | int w; | |
499 | int insn_size = (media_mode ? 4 : 2); | |
500 | ||
501 | for (here = start_pc, end = start_pc + (insn_size * 28); here < end;) | |
502 | { | |
503 | if (media_mode) | |
504 | { | |
e17a4113 UW |
505 | w = read_memory_integer (UNMAKE_ISA32_ADDR (here), |
506 | insn_size, byte_order); | |
55ff77ac CV |
507 | here += insn_size; |
508 | if (IS_MEDIA_IND_ARG_MOV (w)) | |
509 | { | |
510 | /* This must be followed by a store to r14, so the argument | |
c378eb4e | 511 | is where the debug info says it is. This can happen after |
7bb11558 | 512 | the SP has been saved, unfortunately. */ |
55ff77ac CV |
513 | |
514 | int next_insn = read_memory_integer (UNMAKE_ISA32_ADDR (here), | |
e17a4113 | 515 | insn_size, byte_order); |
55ff77ac CV |
516 | here += insn_size; |
517 | if (IS_MEDIA_MOV_TO_R14 (next_insn)) | |
518 | start_pc = here; | |
519 | } | |
520 | else if (IS_MEDIA_ARG_MOV (w)) | |
521 | { | |
7bb11558 | 522 | /* These instructions store directly the argument in r14. */ |
55ff77ac CV |
523 | start_pc = here; |
524 | } | |
525 | else | |
526 | break; | |
527 | } | |
528 | else | |
529 | { | |
e17a4113 | 530 | w = read_memory_integer (here, insn_size, byte_order); |
55ff77ac CV |
531 | w = w & 0xffff; |
532 | here += insn_size; | |
533 | if (IS_COMPACT_IND_ARG_MOV (w)) | |
534 | { | |
535 | /* This must be followed by a store to r14, so the argument | |
c378eb4e | 536 | is where the debug info says it is. This can happen after |
7bb11558 | 537 | the SP has been saved, unfortunately. */ |
55ff77ac | 538 | |
e17a4113 UW |
539 | int next_insn = 0xffff & read_memory_integer (here, insn_size, |
540 | byte_order); | |
55ff77ac CV |
541 | here += insn_size; |
542 | if (IS_COMPACT_MOV_TO_R14 (next_insn)) | |
543 | start_pc = here; | |
544 | } | |
545 | else if (IS_COMPACT_ARG_MOV (w)) | |
546 | { | |
7bb11558 | 547 | /* These instructions store directly the argument in r14. */ |
55ff77ac CV |
548 | start_pc = here; |
549 | } | |
550 | else if (IS_MOVL_R0 (w)) | |
551 | { | |
552 | /* There is a function that gcc calls to get the arguments | |
c378eb4e | 553 | passed correctly to the function. Only after this |
55ff77ac | 554 | function call the arguments will be found at the place |
c378eb4e | 555 | where they are supposed to be. This happens in case the |
55ff77ac CV |
556 | argument has to be stored into a 64-bit register (for |
557 | instance doubles, long longs). SHcompact doesn't have | |
558 | access to the full 64-bits, so we store the register in | |
559 | stack slot and store the address of the stack slot in | |
560 | the register, then do a call through a wrapper that | |
561 | loads the memory value into the register. A SHcompact | |
562 | callee calls an argument decoder | |
563 | (GCC_shcompact_incoming_args) that stores the 64-bit | |
564 | value in a stack slot and stores the address of the | |
565 | stack slot in the register. GCC thinks the argument is | |
566 | just passed by transparent reference, but this is only | |
c378eb4e | 567 | true after the argument decoder is called. Such a call |
7bb11558 | 568 | needs to be considered part of the prologue. */ |
55ff77ac CV |
569 | |
570 | /* This must be followed by a JSR @r0 instruction and by | |
c378eb4e | 571 | a NOP instruction. After these, the prologue is over! */ |
55ff77ac | 572 | |
e17a4113 UW |
573 | int next_insn = 0xffff & read_memory_integer (here, insn_size, |
574 | byte_order); | |
55ff77ac CV |
575 | here += insn_size; |
576 | if (IS_JSR_R0 (next_insn)) | |
577 | { | |
e17a4113 UW |
578 | next_insn = 0xffff & read_memory_integer (here, insn_size, |
579 | byte_order); | |
55ff77ac CV |
580 | here += insn_size; |
581 | ||
582 | if (IS_NOP (next_insn)) | |
583 | start_pc = here; | |
584 | } | |
585 | } | |
586 | else | |
587 | break; | |
588 | } | |
589 | } | |
590 | ||
591 | return start_pc; | |
592 | } | |
593 | ||
594 | static CORE_ADDR | |
e17a4113 | 595 | sh64_skip_prologue_hard_way (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
55ff77ac | 596 | { |
e17a4113 | 597 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
55ff77ac CV |
598 | CORE_ADDR here, end; |
599 | int updated_fp = 0; | |
600 | int insn_size = 4; | |
601 | int media_mode = 1; | |
602 | ||
603 | if (!start_pc) | |
604 | return 0; | |
605 | ||
606 | if (pc_is_isa32 (start_pc) == 0) | |
607 | { | |
608 | insn_size = 2; | |
609 | media_mode = 0; | |
610 | } | |
611 | ||
612 | for (here = start_pc, end = start_pc + (insn_size * 28); here < end;) | |
613 | { | |
614 | ||
615 | if (media_mode) | |
616 | { | |
e17a4113 UW |
617 | int w = read_memory_integer (UNMAKE_ISA32_ADDR (here), |
618 | insn_size, byte_order); | |
55ff77ac CV |
619 | here += insn_size; |
620 | if (IS_STQ_R18_R14 (w) || IS_STQ_R18_R15 (w) || IS_STQ_R14_R15 (w) | |
621 | || IS_STL_R14_R15 (w) || IS_STL_R18_R15 (w) | |
c378eb4e MS |
622 | || IS_ADDIL_SP_MEDIA (w) || IS_ADDI_SP_MEDIA (w) |
623 | || IS_PTABSL_R18 (w)) | |
55ff77ac CV |
624 | { |
625 | start_pc = here; | |
626 | } | |
627 | else if (IS_MOV_SP_FP (w) || IS_MOV_SP_FP_MEDIA(w)) | |
628 | { | |
629 | start_pc = here; | |
630 | updated_fp = 1; | |
631 | } | |
632 | else | |
633 | if (updated_fp) | |
634 | { | |
635 | /* Don't bail out yet, we may have arguments stored in | |
636 | registers here, according to the debug info, so that | |
7bb11558 | 637 | gdb can print the frames correctly. */ |
e17a4113 UW |
638 | start_pc = look_for_args_moves (gdbarch, |
639 | here - insn_size, media_mode); | |
55ff77ac CV |
640 | break; |
641 | } | |
642 | } | |
643 | else | |
644 | { | |
e17a4113 | 645 | int w = 0xffff & read_memory_integer (here, insn_size, byte_order); |
55ff77ac CV |
646 | here += insn_size; |
647 | ||
648 | if (IS_STS_R0 (w) || IS_STS_PR (w) | |
649 | || IS_MOV_TO_R15 (w) || IS_MOV_R14 (w) | |
650 | || IS_MOV_R0 (w) || IS_ADD_SP_R0 (w) || IS_MOV_R14_R0 (w)) | |
651 | { | |
652 | start_pc = here; | |
653 | } | |
654 | else if (IS_MOV_SP_FP (w)) | |
655 | { | |
656 | start_pc = here; | |
657 | updated_fp = 1; | |
658 | } | |
659 | else | |
660 | if (updated_fp) | |
661 | { | |
662 | /* Don't bail out yet, we may have arguments stored in | |
663 | registers here, according to the debug info, so that | |
7bb11558 | 664 | gdb can print the frames correctly. */ |
e17a4113 UW |
665 | start_pc = look_for_args_moves (gdbarch, |
666 | here - insn_size, media_mode); | |
55ff77ac CV |
667 | break; |
668 | } | |
669 | } | |
670 | } | |
671 | ||
672 | return start_pc; | |
673 | } | |
674 | ||
675 | static CORE_ADDR | |
6093d2eb | 676 | sh64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
55ff77ac CV |
677 | { |
678 | CORE_ADDR post_prologue_pc; | |
679 | ||
680 | /* See if we can determine the end of the prologue via the symbol table. | |
681 | If so, then return either PC, or the PC after the prologue, whichever | |
682 | is greater. */ | |
683 | post_prologue_pc = after_prologue (pc); | |
684 | ||
685 | /* If after_prologue returned a useful address, then use it. Else | |
7bb11558 | 686 | fall back on the instruction skipping code. */ |
55ff77ac CV |
687 | if (post_prologue_pc != 0) |
688 | return max (pc, post_prologue_pc); | |
689 | else | |
e17a4113 | 690 | return sh64_skip_prologue_hard_way (gdbarch, pc); |
55ff77ac CV |
691 | } |
692 | ||
55ff77ac CV |
693 | /* Should call_function allocate stack space for a struct return? */ |
694 | static int | |
c30dc700 | 695 | sh64_use_struct_convention (struct type *type) |
55ff77ac CV |
696 | { |
697 | return (TYPE_LENGTH (type) > 8); | |
698 | } | |
699 | ||
7bb11558 | 700 | /* For vectors of 4 floating point registers. */ |
55ff77ac | 701 | static int |
d93859e2 | 702 | sh64_fv_reg_base_num (struct gdbarch *gdbarch, int fv_regnum) |
55ff77ac CV |
703 | { |
704 | int fp_regnum; | |
705 | ||
d93859e2 | 706 | fp_regnum = gdbarch_fp0_regnum (gdbarch) + (fv_regnum - FV0_REGNUM) * 4; |
55ff77ac CV |
707 | return fp_regnum; |
708 | } | |
709 | ||
c378eb4e | 710 | /* For double precision floating point registers, i.e 2 fp regs. */ |
55ff77ac | 711 | static int |
d93859e2 | 712 | sh64_dr_reg_base_num (struct gdbarch *gdbarch, int dr_regnum) |
55ff77ac CV |
713 | { |
714 | int fp_regnum; | |
715 | ||
d93859e2 | 716 | fp_regnum = gdbarch_fp0_regnum (gdbarch) + (dr_regnum - DR0_REGNUM) * 2; |
55ff77ac CV |
717 | return fp_regnum; |
718 | } | |
719 | ||
c378eb4e | 720 | /* For pairs of floating point registers. */ |
55ff77ac | 721 | static int |
d93859e2 | 722 | sh64_fpp_reg_base_num (struct gdbarch *gdbarch, int fpp_regnum) |
55ff77ac CV |
723 | { |
724 | int fp_regnum; | |
725 | ||
d93859e2 | 726 | fp_regnum = gdbarch_fp0_regnum (gdbarch) + (fpp_regnum - FPP0_REGNUM) * 2; |
55ff77ac CV |
727 | return fp_regnum; |
728 | } | |
729 | ||
55ff77ac CV |
730 | /* *INDENT-OFF* */ |
731 | /* | |
732 | SH COMPACT MODE (ISA 16) (all pseudo) 221-272 | |
733 | GDB_REGNUM BASE_REGNUM | |
734 | r0_c 221 0 | |
735 | r1_c 222 1 | |
736 | r2_c 223 2 | |
737 | r3_c 224 3 | |
738 | r4_c 225 4 | |
739 | r5_c 226 5 | |
740 | r6_c 227 6 | |
741 | r7_c 228 7 | |
742 | r8_c 229 8 | |
743 | r9_c 230 9 | |
744 | r10_c 231 10 | |
745 | r11_c 232 11 | |
746 | r12_c 233 12 | |
747 | r13_c 234 13 | |
748 | r14_c 235 14 | |
749 | r15_c 236 15 | |
750 | ||
751 | pc_c 237 64 | |
752 | gbr_c 238 16 | |
753 | mach_c 239 17 | |
754 | macl_c 240 17 | |
755 | pr_c 241 18 | |
756 | t_c 242 19 | |
757 | fpscr_c 243 76 | |
758 | fpul_c 244 109 | |
759 | ||
760 | fr0_c 245 77 | |
761 | fr1_c 246 78 | |
762 | fr2_c 247 79 | |
763 | fr3_c 248 80 | |
764 | fr4_c 249 81 | |
765 | fr5_c 250 82 | |
766 | fr6_c 251 83 | |
767 | fr7_c 252 84 | |
768 | fr8_c 253 85 | |
769 | fr9_c 254 86 | |
770 | fr10_c 255 87 | |
771 | fr11_c 256 88 | |
772 | fr12_c 257 89 | |
773 | fr13_c 258 90 | |
774 | fr14_c 259 91 | |
775 | fr15_c 260 92 | |
776 | ||
777 | dr0_c 261 77 | |
778 | dr2_c 262 79 | |
779 | dr4_c 263 81 | |
780 | dr6_c 264 83 | |
781 | dr8_c 265 85 | |
782 | dr10_c 266 87 | |
783 | dr12_c 267 89 | |
784 | dr14_c 268 91 | |
785 | ||
786 | fv0_c 269 77 | |
787 | fv4_c 270 81 | |
788 | fv8_c 271 85 | |
789 | fv12_c 272 91 | |
790 | */ | |
791 | /* *INDENT-ON* */ | |
792 | static int | |
d93859e2 | 793 | sh64_compact_reg_base_num (struct gdbarch *gdbarch, int reg_nr) |
55ff77ac | 794 | { |
c30dc700 | 795 | int base_regnum = reg_nr; |
55ff77ac CV |
796 | |
797 | /* general register N maps to general register N */ | |
798 | if (reg_nr >= R0_C_REGNUM | |
799 | && reg_nr <= R_LAST_C_REGNUM) | |
800 | base_regnum = reg_nr - R0_C_REGNUM; | |
801 | ||
802 | /* floating point register N maps to floating point register N */ | |
803 | else if (reg_nr >= FP0_C_REGNUM | |
804 | && reg_nr <= FP_LAST_C_REGNUM) | |
d93859e2 | 805 | base_regnum = reg_nr - FP0_C_REGNUM + gdbarch_fp0_regnum (gdbarch); |
55ff77ac CV |
806 | |
807 | /* double prec register N maps to base regnum for double prec register N */ | |
808 | else if (reg_nr >= DR0_C_REGNUM | |
809 | && reg_nr <= DR_LAST_C_REGNUM) | |
d93859e2 UW |
810 | base_regnum = sh64_dr_reg_base_num (gdbarch, |
811 | DR0_REGNUM + reg_nr - DR0_C_REGNUM); | |
55ff77ac CV |
812 | |
813 | /* vector N maps to base regnum for vector register N */ | |
814 | else if (reg_nr >= FV0_C_REGNUM | |
815 | && reg_nr <= FV_LAST_C_REGNUM) | |
d93859e2 UW |
816 | base_regnum = sh64_fv_reg_base_num (gdbarch, |
817 | FV0_REGNUM + reg_nr - FV0_C_REGNUM); | |
55ff77ac CV |
818 | |
819 | else if (reg_nr == PC_C_REGNUM) | |
d93859e2 | 820 | base_regnum = gdbarch_pc_regnum (gdbarch); |
55ff77ac CV |
821 | |
822 | else if (reg_nr == GBR_C_REGNUM) | |
823 | base_regnum = 16; | |
824 | ||
825 | else if (reg_nr == MACH_C_REGNUM | |
826 | || reg_nr == MACL_C_REGNUM) | |
827 | base_regnum = 17; | |
828 | ||
829 | else if (reg_nr == PR_C_REGNUM) | |
c30dc700 | 830 | base_regnum = PR_REGNUM; |
55ff77ac CV |
831 | |
832 | else if (reg_nr == T_C_REGNUM) | |
833 | base_regnum = 19; | |
834 | ||
835 | else if (reg_nr == FPSCR_C_REGNUM) | |
7bb11558 | 836 | base_regnum = FPSCR_REGNUM; /*???? this register is a mess. */ |
55ff77ac CV |
837 | |
838 | else if (reg_nr == FPUL_C_REGNUM) | |
d93859e2 | 839 | base_regnum = gdbarch_fp0_regnum (gdbarch) + 32; |
55ff77ac CV |
840 | |
841 | return base_regnum; | |
842 | } | |
843 | ||
55ff77ac CV |
844 | static int |
845 | sign_extend (int value, int bits) | |
846 | { | |
847 | value = value & ((1 << bits) - 1); | |
848 | return (value & (1 << (bits - 1)) | |
849 | ? value | (~((1 << bits) - 1)) | |
850 | : value); | |
851 | } | |
852 | ||
853 | static void | |
c30dc700 CV |
854 | sh64_analyze_prologue (struct gdbarch *gdbarch, |
855 | struct sh64_frame_cache *cache, | |
856 | CORE_ADDR func_pc, | |
857 | CORE_ADDR current_pc) | |
55ff77ac | 858 | { |
55ff77ac CV |
859 | int pc; |
860 | int opc; | |
861 | int insn; | |
862 | int r0_val = 0; | |
55ff77ac CV |
863 | int insn_size; |
864 | int gdb_register_number; | |
865 | int register_number; | |
c30dc700 | 866 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
e17a4113 | 867 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
55ff77ac | 868 | |
c30dc700 | 869 | cache->sp_offset = 0; |
55ff77ac CV |
870 | |
871 | /* Loop around examining the prologue insns until we find something | |
872 | that does not appear to be part of the prologue. But give up | |
7bb11558 | 873 | after 20 of them, since we're getting silly then. */ |
55ff77ac | 874 | |
c30dc700 | 875 | pc = func_pc; |
55ff77ac | 876 | |
c30dc700 CV |
877 | if (cache->media_mode) |
878 | insn_size = 4; | |
55ff77ac | 879 | else |
c30dc700 | 880 | insn_size = 2; |
55ff77ac | 881 | |
c30dc700 CV |
882 | opc = pc + (insn_size * 28); |
883 | if (opc > current_pc) | |
884 | opc = current_pc; | |
885 | for ( ; pc <= opc; pc += insn_size) | |
55ff77ac | 886 | { |
c30dc700 CV |
887 | insn = read_memory_integer (cache->media_mode ? UNMAKE_ISA32_ADDR (pc) |
888 | : pc, | |
e17a4113 | 889 | insn_size, byte_order); |
55ff77ac | 890 | |
c30dc700 | 891 | if (!cache->media_mode) |
55ff77ac CV |
892 | { |
893 | if (IS_STS_PR (insn)) | |
894 | { | |
e17a4113 UW |
895 | int next_insn = read_memory_integer (pc + insn_size, |
896 | insn_size, byte_order); | |
55ff77ac CV |
897 | if (IS_MOV_TO_R15 (next_insn)) |
898 | { | |
c378eb4e MS |
899 | cache->saved_regs[PR_REGNUM] |
900 | = cache->sp_offset - ((((next_insn & 0xf) ^ 0x8) | |
901 | - 0x8) << 2); | |
55ff77ac CV |
902 | pc += insn_size; |
903 | } | |
904 | } | |
c30dc700 | 905 | |
55ff77ac | 906 | else if (IS_MOV_R14 (insn)) |
c30dc700 CV |
907 | cache->saved_regs[MEDIA_FP_REGNUM] = |
908 | cache->sp_offset - ((((insn & 0xf) ^ 0x8) - 0x8) << 2); | |
55ff77ac CV |
909 | |
910 | else if (IS_MOV_R0 (insn)) | |
911 | { | |
912 | /* Put in R0 the offset from SP at which to store some | |
c378eb4e | 913 | registers. We are interested in this value, because it |
55ff77ac CV |
914 | will tell us where the given registers are stored within |
915 | the frame. */ | |
916 | r0_val = ((insn & 0xff) ^ 0x80) - 0x80; | |
917 | } | |
c30dc700 | 918 | |
55ff77ac CV |
919 | else if (IS_ADD_SP_R0 (insn)) |
920 | { | |
921 | /* This instruction still prepares r0, but we don't care. | |
7bb11558 | 922 | We already have the offset in r0_val. */ |
55ff77ac | 923 | } |
c30dc700 | 924 | |
55ff77ac CV |
925 | else if (IS_STS_R0 (insn)) |
926 | { | |
c378eb4e | 927 | /* Store PR at r0_val-4 from SP. Decrement r0 by 4. */ |
c30dc700 | 928 | cache->saved_regs[PR_REGNUM] = cache->sp_offset - (r0_val - 4); |
55ff77ac | 929 | r0_val -= 4; |
55ff77ac | 930 | } |
c30dc700 | 931 | |
55ff77ac CV |
932 | else if (IS_MOV_R14_R0 (insn)) |
933 | { | |
c378eb4e | 934 | /* Store R14 at r0_val-4 from SP. Decrement r0 by 4. */ |
c30dc700 CV |
935 | cache->saved_regs[MEDIA_FP_REGNUM] = cache->sp_offset |
936 | - (r0_val - 4); | |
55ff77ac CV |
937 | r0_val -= 4; |
938 | } | |
939 | ||
940 | else if (IS_ADD_SP (insn)) | |
c30dc700 CV |
941 | cache->sp_offset -= ((insn & 0xff) ^ 0x80) - 0x80; |
942 | ||
55ff77ac CV |
943 | else if (IS_MOV_SP_FP (insn)) |
944 | break; | |
945 | } | |
946 | else | |
947 | { | |
c30dc700 CV |
948 | if (IS_ADDIL_SP_MEDIA (insn) || IS_ADDI_SP_MEDIA (insn)) |
949 | cache->sp_offset -= | |
950 | sign_extend ((((insn & 0xffc00) ^ 0x80000) - 0x80000) >> 10, 9); | |
55ff77ac CV |
951 | |
952 | else if (IS_STQ_R18_R15 (insn)) | |
c378eb4e MS |
953 | cache->saved_regs[PR_REGNUM] |
954 | = cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10, | |
955 | 9) << 3); | |
55ff77ac CV |
956 | |
957 | else if (IS_STL_R18_R15 (insn)) | |
c378eb4e MS |
958 | cache->saved_regs[PR_REGNUM] |
959 | = cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10, | |
960 | 9) << 2); | |
55ff77ac CV |
961 | |
962 | else if (IS_STQ_R14_R15 (insn)) | |
c378eb4e MS |
963 | cache->saved_regs[MEDIA_FP_REGNUM] |
964 | = cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10, | |
965 | 9) << 3); | |
55ff77ac CV |
966 | |
967 | else if (IS_STL_R14_R15 (insn)) | |
c378eb4e MS |
968 | cache->saved_regs[MEDIA_FP_REGNUM] |
969 | = cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10, | |
970 | 9) << 2); | |
55ff77ac CV |
971 | |
972 | else if (IS_MOV_SP_FP_MEDIA (insn)) | |
973 | break; | |
974 | } | |
975 | } | |
976 | ||
c30dc700 CV |
977 | if (cache->saved_regs[MEDIA_FP_REGNUM] >= 0) |
978 | cache->uses_fp = 1; | |
55ff77ac CV |
979 | } |
980 | ||
55ff77ac | 981 | static CORE_ADDR |
c30dc700 | 982 | sh64_frame_align (struct gdbarch *ignore, CORE_ADDR sp) |
55ff77ac | 983 | { |
c30dc700 | 984 | return sp & ~7; |
55ff77ac CV |
985 | } |
986 | ||
c30dc700 | 987 | /* Function: push_dummy_call |
55ff77ac CV |
988 | Setup the function arguments for calling a function in the inferior. |
989 | ||
85a453d5 | 990 | On the Renesas SH architecture, there are four registers (R4 to R7) |
55ff77ac CV |
991 | which are dedicated for passing function arguments. Up to the first |
992 | four arguments (depending on size) may go into these registers. | |
993 | The rest go on the stack. | |
994 | ||
995 | Arguments that are smaller than 4 bytes will still take up a whole | |
996 | register or a whole 32-bit word on the stack, and will be | |
997 | right-justified in the register or the stack word. This includes | |
998 | chars, shorts, and small aggregate types. | |
999 | ||
1000 | Arguments that are larger than 4 bytes may be split between two or | |
1001 | more registers. If there are not enough registers free, an argument | |
1002 | may be passed partly in a register (or registers), and partly on the | |
c378eb4e | 1003 | stack. This includes doubles, long longs, and larger aggregates. |
55ff77ac CV |
1004 | As far as I know, there is no upper limit to the size of aggregates |
1005 | that will be passed in this way; in other words, the convention of | |
1006 | passing a pointer to a large aggregate instead of a copy is not used. | |
1007 | ||
1008 | An exceptional case exists for struct arguments (and possibly other | |
1009 | aggregates such as arrays) if the size is larger than 4 bytes but | |
1010 | not a multiple of 4 bytes. In this case the argument is never split | |
1011 | between the registers and the stack, but instead is copied in its | |
1012 | entirety onto the stack, AND also copied into as many registers as | |
1013 | there is room for. In other words, space in registers permitting, | |
1014 | two copies of the same argument are passed in. As far as I can tell, | |
1015 | only the one on the stack is used, although that may be a function | |
1016 | of the level of compiler optimization. I suspect this is a compiler | |
1017 | bug. Arguments of these odd sizes are left-justified within the | |
1018 | word (as opposed to arguments smaller than 4 bytes, which are | |
1019 | right-justified). | |
1020 | ||
1021 | If the function is to return an aggregate type such as a struct, it | |
1022 | is either returned in the normal return value register R0 (if its | |
1023 | size is no greater than one byte), or else the caller must allocate | |
1024 | space into which the callee will copy the return value (if the size | |
1025 | is greater than one byte). In this case, a pointer to the return | |
1026 | value location is passed into the callee in register R2, which does | |
1027 | not displace any of the other arguments passed in via registers R4 | |
c378eb4e | 1028 | to R7. */ |
55ff77ac CV |
1029 | |
1030 | /* R2-R9 for integer types and integer equivalent (char, pointers) and | |
1031 | non-scalar (struct, union) elements (even if the elements are | |
1032 | floats). | |
1033 | FR0-FR11 for single precision floating point (float) | |
1034 | DR0-DR10 for double precision floating point (double) | |
1035 | ||
1036 | If a float is argument number 3 (for instance) and arguments number | |
1037 | 1,2, and 4 are integer, the mapping will be: | |
c378eb4e | 1038 | arg1 -->R2, arg2 --> R3, arg3 -->FR0, arg4 --> R5. I.e. R4 is not used. |
55ff77ac CV |
1039 | |
1040 | If a float is argument number 10 (for instance) and arguments number | |
1041 | 1 through 10 are integer, the mapping will be: | |
1042 | arg1->R2, arg2->R3, arg3->R4, arg4->R5, arg5->R6, arg6->R7, arg7->R8, | |
c378eb4e MS |
1043 | arg8->R9, arg9->(0,SP)stack(8-byte aligned), arg10->FR0, |
1044 | arg11->stack(16,SP). I.e. there is hole in the stack. | |
55ff77ac CV |
1045 | |
1046 | Different rules apply for variable arguments functions, and for functions | |
7bb11558 | 1047 | for which the prototype is not known. */ |
55ff77ac CV |
1048 | |
1049 | static CORE_ADDR | |
c30dc700 CV |
1050 | sh64_push_dummy_call (struct gdbarch *gdbarch, |
1051 | struct value *function, | |
1052 | struct regcache *regcache, | |
1053 | CORE_ADDR bp_addr, | |
1054 | int nargs, struct value **args, | |
1055 | CORE_ADDR sp, int struct_return, | |
1056 | CORE_ADDR struct_addr) | |
55ff77ac | 1057 | { |
e17a4113 | 1058 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
55ff77ac CV |
1059 | int stack_offset, stack_alloc; |
1060 | int int_argreg; | |
1061 | int float_argreg; | |
1062 | int double_argreg; | |
1063 | int float_arg_index = 0; | |
1064 | int double_arg_index = 0; | |
1065 | int argnum; | |
1066 | struct type *type; | |
1067 | CORE_ADDR regval; | |
948f8e3d PA |
1068 | const gdb_byte *val; |
1069 | gdb_byte valbuf[8]; | |
55ff77ac CV |
1070 | int len; |
1071 | int argreg_size; | |
1072 | int fp_args[12]; | |
55ff77ac CV |
1073 | |
1074 | memset (fp_args, 0, sizeof (fp_args)); | |
1075 | ||
c378eb4e | 1076 | /* First force sp to a 8-byte alignment. */ |
c30dc700 | 1077 | sp = sh64_frame_align (gdbarch, sp); |
55ff77ac CV |
1078 | |
1079 | /* The "struct return pointer" pseudo-argument has its own dedicated | |
c378eb4e | 1080 | register. */ |
55ff77ac CV |
1081 | |
1082 | if (struct_return) | |
c30dc700 CV |
1083 | regcache_cooked_write_unsigned (regcache, |
1084 | STRUCT_RETURN_REGNUM, struct_addr); | |
55ff77ac | 1085 | |
c378eb4e | 1086 | /* Now make sure there's space on the stack. */ |
55ff77ac | 1087 | for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++) |
4991999e | 1088 | stack_alloc += ((TYPE_LENGTH (value_type (args[argnum])) + 7) & ~7); |
c378eb4e | 1089 | sp -= stack_alloc; /* Make room on stack for args. */ |
55ff77ac CV |
1090 | |
1091 | /* Now load as many as possible of the first arguments into | |
1092 | registers, and push the rest onto the stack. There are 64 bytes | |
1093 | in eight registers available. Loop thru args from first to last. */ | |
1094 | ||
1095 | int_argreg = ARG0_REGNUM; | |
58643501 | 1096 | float_argreg = gdbarch_fp0_regnum (gdbarch); |
55ff77ac CV |
1097 | double_argreg = DR0_REGNUM; |
1098 | ||
1099 | for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++) | |
1100 | { | |
4991999e | 1101 | type = value_type (args[argnum]); |
55ff77ac CV |
1102 | len = TYPE_LENGTH (type); |
1103 | memset (valbuf, 0, sizeof (valbuf)); | |
1104 | ||
1105 | if (TYPE_CODE (type) != TYPE_CODE_FLT) | |
1106 | { | |
58643501 | 1107 | argreg_size = register_size (gdbarch, int_argreg); |
55ff77ac CV |
1108 | |
1109 | if (len < argreg_size) | |
1110 | { | |
c378eb4e | 1111 | /* value gets right-justified in the register or stack word. */ |
58643501 | 1112 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
55ff77ac | 1113 | memcpy (valbuf + argreg_size - len, |
948f8e3d | 1114 | value_contents (args[argnum]), len); |
55ff77ac | 1115 | else |
948f8e3d | 1116 | memcpy (valbuf, value_contents (args[argnum]), len); |
55ff77ac CV |
1117 | |
1118 | val = valbuf; | |
1119 | } | |
1120 | else | |
948f8e3d | 1121 | val = value_contents (args[argnum]); |
55ff77ac CV |
1122 | |
1123 | while (len > 0) | |
1124 | { | |
1125 | if (int_argreg > ARGLAST_REGNUM) | |
1126 | { | |
c378eb4e | 1127 | /* Must go on the stack. */ |
948f8e3d | 1128 | write_memory (sp + stack_offset, val, argreg_size); |
55ff77ac CV |
1129 | stack_offset += 8;/*argreg_size;*/ |
1130 | } | |
1131 | /* NOTE WELL!!!!! This is not an "else if" clause!!! | |
1132 | That's because some *&^%$ things get passed on the stack | |
1133 | AND in the registers! */ | |
1134 | if (int_argreg <= ARGLAST_REGNUM) | |
1135 | { | |
c378eb4e | 1136 | /* There's room in a register. */ |
e17a4113 UW |
1137 | regval = extract_unsigned_integer (val, argreg_size, |
1138 | byte_order); | |
c378eb4e MS |
1139 | regcache_cooked_write_unsigned (regcache, |
1140 | int_argreg, regval); | |
55ff77ac CV |
1141 | } |
1142 | /* Store the value 8 bytes at a time. This means that | |
1143 | things larger than 8 bytes may go partly in registers | |
c378eb4e | 1144 | and partly on the stack. FIXME: argreg is incremented |
7bb11558 | 1145 | before we use its size. */ |
55ff77ac CV |
1146 | len -= argreg_size; |
1147 | val += argreg_size; | |
1148 | int_argreg++; | |
1149 | } | |
1150 | } | |
1151 | else | |
1152 | { | |
948f8e3d | 1153 | val = value_contents (args[argnum]); |
55ff77ac CV |
1154 | if (len == 4) |
1155 | { | |
c378eb4e | 1156 | /* Where is it going to be stored? */ |
55ff77ac CV |
1157 | while (fp_args[float_arg_index]) |
1158 | float_arg_index ++; | |
1159 | ||
1160 | /* Now float_argreg points to the register where it | |
1161 | should be stored. Are we still within the allowed | |
c378eb4e | 1162 | register set? */ |
55ff77ac CV |
1163 | if (float_arg_index <= FLOAT_ARGLAST_REGNUM) |
1164 | { | |
1165 | /* Goes in FR0...FR11 */ | |
c30dc700 | 1166 | regcache_cooked_write (regcache, |
58643501 | 1167 | gdbarch_fp0_regnum (gdbarch) |
3e8c568d | 1168 | + float_arg_index, |
c30dc700 | 1169 | val); |
55ff77ac | 1170 | fp_args[float_arg_index] = 1; |
7bb11558 | 1171 | /* Skip the corresponding general argument register. */ |
55ff77ac CV |
1172 | int_argreg ++; |
1173 | } | |
1174 | else | |
d4fb63e1 TT |
1175 | { |
1176 | /* Store it as the integers, 8 bytes at the time, if | |
1177 | necessary spilling on the stack. */ | |
1178 | } | |
55ff77ac CV |
1179 | } |
1180 | else if (len == 8) | |
1181 | { | |
c378eb4e | 1182 | /* Where is it going to be stored? */ |
55ff77ac CV |
1183 | while (fp_args[double_arg_index]) |
1184 | double_arg_index += 2; | |
1185 | /* Now double_argreg points to the register | |
1186 | where it should be stored. | |
c378eb4e | 1187 | Are we still within the allowed register set? */ |
55ff77ac CV |
1188 | if (double_arg_index < FLOAT_ARGLAST_REGNUM) |
1189 | { | |
1190 | /* Goes in DR0...DR10 */ | |
1191 | /* The numbering of the DRi registers is consecutive, | |
7bb11558 | 1192 | i.e. includes odd numbers. */ |
55ff77ac | 1193 | int double_register_offset = double_arg_index / 2; |
c30dc700 CV |
1194 | int regnum = DR0_REGNUM + double_register_offset; |
1195 | regcache_cooked_write (regcache, regnum, val); | |
55ff77ac CV |
1196 | fp_args[double_arg_index] = 1; |
1197 | fp_args[double_arg_index + 1] = 1; | |
7bb11558 | 1198 | /* Skip the corresponding general argument register. */ |
55ff77ac CV |
1199 | int_argreg ++; |
1200 | } | |
1201 | else | |
d4fb63e1 TT |
1202 | { |
1203 | /* Store it as the integers, 8 bytes at the time, if | |
1204 | necessary spilling on the stack. */ | |
1205 | } | |
55ff77ac CV |
1206 | } |
1207 | } | |
1208 | } | |
c378eb4e | 1209 | /* Store return address. */ |
c30dc700 | 1210 | regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr); |
55ff77ac | 1211 | |
c30dc700 | 1212 | /* Update stack pointer. */ |
3e8c568d | 1213 | regcache_cooked_write_unsigned (regcache, |
58643501 | 1214 | gdbarch_sp_regnum (gdbarch), sp); |
55ff77ac | 1215 | |
55ff77ac CV |
1216 | return sp; |
1217 | } | |
1218 | ||
1219 | /* Find a function's return value in the appropriate registers (in | |
1220 | regbuf), and copy it into valbuf. Extract from an array REGBUF | |
1221 | containing the (raw) register state a function return value of type | |
1222 | TYPE, and copy that, in virtual format, into VALBUF. */ | |
1223 | static void | |
c30dc700 CV |
1224 | sh64_extract_return_value (struct type *type, struct regcache *regcache, |
1225 | void *valbuf) | |
55ff77ac | 1226 | { |
d93859e2 | 1227 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
e17a4113 | 1228 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
55ff77ac | 1229 | int len = TYPE_LENGTH (type); |
d93859e2 | 1230 | |
55ff77ac CV |
1231 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
1232 | { | |
1233 | if (len == 4) | |
1234 | { | |
c378eb4e | 1235 | /* Return value stored in gdbarch_fp0_regnum. */ |
3e8c568d | 1236 | regcache_raw_read (regcache, |
d93859e2 | 1237 | gdbarch_fp0_regnum (gdbarch), valbuf); |
55ff77ac CV |
1238 | } |
1239 | else if (len == 8) | |
1240 | { | |
c378eb4e | 1241 | /* return value stored in DR0_REGNUM. */ |
55ff77ac | 1242 | DOUBLEST val; |
18cf8b5b | 1243 | gdb_byte buf[8]; |
55ff77ac | 1244 | |
18cf8b5b | 1245 | regcache_cooked_read (regcache, DR0_REGNUM, buf); |
55ff77ac | 1246 | |
d93859e2 | 1247 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) |
55ff77ac | 1248 | floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, |
c30dc700 | 1249 | buf, &val); |
55ff77ac CV |
1250 | else |
1251 | floatformat_to_doublest (&floatformat_ieee_double_big, | |
c30dc700 | 1252 | buf, &val); |
7bb11558 | 1253 | store_typed_floating (valbuf, type, val); |
55ff77ac CV |
1254 | } |
1255 | } | |
1256 | else | |
1257 | { | |
1258 | if (len <= 8) | |
1259 | { | |
c30dc700 | 1260 | int offset; |
e362b510 | 1261 | gdb_byte buf[8]; |
c378eb4e | 1262 | /* Result is in register 2. If smaller than 8 bytes, it is padded |
7bb11558 | 1263 | at the most significant end. */ |
c30dc700 CV |
1264 | regcache_raw_read (regcache, DEFAULT_RETURN_REGNUM, buf); |
1265 | ||
d93859e2 UW |
1266 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
1267 | offset = register_size (gdbarch, DEFAULT_RETURN_REGNUM) | |
c30dc700 | 1268 | - len; |
55ff77ac | 1269 | else |
c30dc700 CV |
1270 | offset = 0; |
1271 | memcpy (valbuf, buf + offset, len); | |
55ff77ac CV |
1272 | } |
1273 | else | |
a73c6dcd | 1274 | error (_("bad size for return value")); |
55ff77ac CV |
1275 | } |
1276 | } | |
1277 | ||
1278 | /* Write into appropriate registers a function return value | |
1279 | of type TYPE, given in virtual format. | |
1280 | If the architecture is sh4 or sh3e, store a function's return value | |
1281 | in the R0 general register or in the FP0 floating point register, | |
c378eb4e | 1282 | depending on the type of the return value. In all the other cases |
7bb11558 | 1283 | the result is stored in r0, left-justified. */ |
55ff77ac CV |
1284 | |
1285 | static void | |
c30dc700 | 1286 | sh64_store_return_value (struct type *type, struct regcache *regcache, |
948f8e3d | 1287 | const gdb_byte *valbuf) |
55ff77ac | 1288 | { |
d93859e2 | 1289 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
e362b510 | 1290 | gdb_byte buf[64]; /* more than enough... */ |
55ff77ac CV |
1291 | int len = TYPE_LENGTH (type); |
1292 | ||
1293 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
1294 | { | |
d93859e2 | 1295 | int i, regnum = gdbarch_fp0_regnum (gdbarch); |
c30dc700 | 1296 | for (i = 0; i < len; i += 4) |
d93859e2 | 1297 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) |
c30dc700 | 1298 | regcache_raw_write (regcache, regnum++, |
948f8e3d | 1299 | valbuf + len - 4 - i); |
c30dc700 | 1300 | else |
948f8e3d | 1301 | regcache_raw_write (regcache, regnum++, valbuf + i); |
55ff77ac CV |
1302 | } |
1303 | else | |
1304 | { | |
1305 | int return_register = DEFAULT_RETURN_REGNUM; | |
1306 | int offset = 0; | |
1307 | ||
d93859e2 | 1308 | if (len <= register_size (gdbarch, return_register)) |
55ff77ac | 1309 | { |
7bb11558 | 1310 | /* Pad with zeros. */ |
d93859e2 UW |
1311 | memset (buf, 0, register_size (gdbarch, return_register)); |
1312 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) | |
1313 | offset = 0; /*register_size (gdbarch, | |
7bb11558 | 1314 | return_register) - len;*/ |
55ff77ac | 1315 | else |
d93859e2 | 1316 | offset = register_size (gdbarch, return_register) - len; |
55ff77ac CV |
1317 | |
1318 | memcpy (buf + offset, valbuf, len); | |
c30dc700 | 1319 | regcache_raw_write (regcache, return_register, buf); |
55ff77ac CV |
1320 | } |
1321 | else | |
c30dc700 | 1322 | regcache_raw_write (regcache, return_register, valbuf); |
55ff77ac CV |
1323 | } |
1324 | } | |
1325 | ||
c30dc700 | 1326 | static enum return_value_convention |
6a3a010b | 1327 | sh64_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 | 1328 | struct type *type, struct regcache *regcache, |
18cf8b5b | 1329 | gdb_byte *readbuf, const gdb_byte *writebuf) |
c30dc700 CV |
1330 | { |
1331 | if (sh64_use_struct_convention (type)) | |
1332 | return RETURN_VALUE_STRUCT_CONVENTION; | |
1333 | if (writebuf) | |
1334 | sh64_store_return_value (type, regcache, writebuf); | |
1335 | else if (readbuf) | |
1336 | sh64_extract_return_value (type, regcache, readbuf); | |
1337 | return RETURN_VALUE_REGISTER_CONVENTION; | |
1338 | } | |
1339 | ||
55ff77ac CV |
1340 | /* *INDENT-OFF* */ |
1341 | /* | |
1342 | SH MEDIA MODE (ISA 32) | |
1343 | general registers (64-bit) 0-63 | |
1344 | 0 r0, r1, r2, r3, r4, r5, r6, r7, | |
1345 | 64 r8, r9, r10, r11, r12, r13, r14, r15, | |
1346 | 128 r16, r17, r18, r19, r20, r21, r22, r23, | |
1347 | 192 r24, r25, r26, r27, r28, r29, r30, r31, | |
1348 | 256 r32, r33, r34, r35, r36, r37, r38, r39, | |
1349 | 320 r40, r41, r42, r43, r44, r45, r46, r47, | |
1350 | 384 r48, r49, r50, r51, r52, r53, r54, r55, | |
1351 | 448 r56, r57, r58, r59, r60, r61, r62, r63, | |
1352 | ||
1353 | pc (64-bit) 64 | |
1354 | 512 pc, | |
1355 | ||
1356 | status reg., saved status reg., saved pc reg. (64-bit) 65-67 | |
1357 | 520 sr, ssr, spc, | |
1358 | ||
1359 | target registers (64-bit) 68-75 | |
1360 | 544 tr0, tr1, tr2, tr3, tr4, tr5, tr6, tr7, | |
1361 | ||
1362 | floating point state control register (32-bit) 76 | |
1363 | 608 fpscr, | |
1364 | ||
1365 | single precision floating point registers (32-bit) 77-140 | |
1366 | 612 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7, | |
1367 | 644 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15, | |
1368 | 676 fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23, | |
1369 | 708 fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31, | |
1370 | 740 fr32, fr33, fr34, fr35, fr36, fr37, fr38, fr39, | |
1371 | 772 fr40, fr41, fr42, fr43, fr44, fr45, fr46, fr47, | |
1372 | 804 fr48, fr49, fr50, fr51, fr52, fr53, fr54, fr55, | |
1373 | 836 fr56, fr57, fr58, fr59, fr60, fr61, fr62, fr63, | |
1374 | ||
1375 | TOTAL SPACE FOR REGISTERS: 868 bytes | |
1376 | ||
1377 | From here on they are all pseudo registers: no memory allocated. | |
1378 | REGISTER_BYTE returns the register byte for the base register. | |
1379 | ||
1380 | double precision registers (pseudo) 141-172 | |
1381 | dr0, dr2, dr4, dr6, dr8, dr10, dr12, dr14, | |
1382 | dr16, dr18, dr20, dr22, dr24, dr26, dr28, dr30, | |
1383 | dr32, dr34, dr36, dr38, dr40, dr42, dr44, dr46, | |
1384 | dr48, dr50, dr52, dr54, dr56, dr58, dr60, dr62, | |
1385 | ||
1386 | floating point pairs (pseudo) 173-204 | |
1387 | fp0, fp2, fp4, fp6, fp8, fp10, fp12, fp14, | |
1388 | fp16, fp18, fp20, fp22, fp24, fp26, fp28, fp30, | |
1389 | fp32, fp34, fp36, fp38, fp40, fp42, fp44, fp46, | |
1390 | fp48, fp50, fp52, fp54, fp56, fp58, fp60, fp62, | |
1391 | ||
1392 | floating point vectors (4 floating point regs) (pseudo) 205-220 | |
1393 | fv0, fv4, fv8, fv12, fv16, fv20, fv24, fv28, | |
1394 | fv32, fv36, fv40, fv44, fv48, fv52, fv56, fv60, | |
1395 | ||
1396 | SH COMPACT MODE (ISA 16) (all pseudo) 221-272 | |
1397 | r0_c, r1_c, r2_c, r3_c, r4_c, r5_c, r6_c, r7_c, | |
1398 | r8_c, r9_c, r10_c, r11_c, r12_c, r13_c, r14_c, r15_c, | |
1399 | pc_c, | |
1400 | gbr_c, mach_c, macl_c, pr_c, t_c, | |
1401 | fpscr_c, fpul_c, | |
1402 | fr0_c, fr1_c, fr2_c, fr3_c, fr4_c, fr5_c, fr6_c, fr7_c, | |
1403 | fr8_c, fr9_c, fr10_c, fr11_c, fr12_c, fr13_c, fr14_c, fr15_c | |
1404 | dr0_c, dr2_c, dr4_c, dr6_c, dr8_c, dr10_c, dr12_c, dr14_c | |
1405 | fv0_c, fv4_c, fv8_c, fv12_c | |
1406 | */ | |
55ff77ac | 1407 | |
55ff77ac | 1408 | static struct type * |
0dfff4cb | 1409 | sh64_build_float_register_type (struct gdbarch *gdbarch, int high) |
55ff77ac | 1410 | { |
e3506a9f UW |
1411 | return lookup_array_range_type (builtin_type (gdbarch)->builtin_float, |
1412 | 0, high); | |
55ff77ac CV |
1413 | } |
1414 | ||
7bb11558 MS |
1415 | /* Return the GDB type object for the "standard" data type |
1416 | of data in register REG_NR. */ | |
55ff77ac | 1417 | static struct type * |
7bb11558 | 1418 | sh64_register_type (struct gdbarch *gdbarch, int reg_nr) |
55ff77ac | 1419 | { |
58643501 | 1420 | if ((reg_nr >= gdbarch_fp0_regnum (gdbarch) |
55ff77ac CV |
1421 | && reg_nr <= FP_LAST_REGNUM) |
1422 | || (reg_nr >= FP0_C_REGNUM | |
1423 | && reg_nr <= FP_LAST_C_REGNUM)) | |
0dfff4cb | 1424 | return builtin_type (gdbarch)->builtin_float; |
55ff77ac CV |
1425 | else if ((reg_nr >= DR0_REGNUM |
1426 | && reg_nr <= DR_LAST_REGNUM) | |
1427 | || (reg_nr >= DR0_C_REGNUM | |
1428 | && reg_nr <= DR_LAST_C_REGNUM)) | |
0dfff4cb | 1429 | return builtin_type (gdbarch)->builtin_double; |
55ff77ac CV |
1430 | else if (reg_nr >= FPP0_REGNUM |
1431 | && reg_nr <= FPP_LAST_REGNUM) | |
0dfff4cb | 1432 | return sh64_build_float_register_type (gdbarch, 1); |
55ff77ac CV |
1433 | else if ((reg_nr >= FV0_REGNUM |
1434 | && reg_nr <= FV_LAST_REGNUM) | |
1435 | ||(reg_nr >= FV0_C_REGNUM | |
1436 | && reg_nr <= FV_LAST_C_REGNUM)) | |
0dfff4cb | 1437 | return sh64_build_float_register_type (gdbarch, 3); |
55ff77ac | 1438 | else if (reg_nr == FPSCR_REGNUM) |
0dfff4cb | 1439 | return builtin_type (gdbarch)->builtin_int; |
55ff77ac CV |
1440 | else if (reg_nr >= R0_C_REGNUM |
1441 | && reg_nr < FP0_C_REGNUM) | |
0dfff4cb | 1442 | return builtin_type (gdbarch)->builtin_int; |
55ff77ac | 1443 | else |
0dfff4cb | 1444 | return builtin_type (gdbarch)->builtin_long_long; |
55ff77ac CV |
1445 | } |
1446 | ||
1447 | static void | |
d93859e2 | 1448 | sh64_register_convert_to_virtual (struct gdbarch *gdbarch, int regnum, |
948f8e3d | 1449 | struct type *type, gdb_byte *from, gdb_byte *to) |
55ff77ac | 1450 | { |
d93859e2 | 1451 | if (gdbarch_byte_order (gdbarch) != BFD_ENDIAN_LITTLE) |
55ff77ac | 1452 | { |
7bb11558 | 1453 | /* It is a no-op. */ |
d93859e2 | 1454 | memcpy (to, from, register_size (gdbarch, regnum)); |
55ff77ac CV |
1455 | return; |
1456 | } | |
1457 | ||
1458 | if ((regnum >= DR0_REGNUM | |
1459 | && regnum <= DR_LAST_REGNUM) | |
1460 | || (regnum >= DR0_C_REGNUM | |
1461 | && regnum <= DR_LAST_C_REGNUM)) | |
1462 | { | |
1463 | DOUBLEST val; | |
7bb11558 MS |
1464 | floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, |
1465 | from, &val); | |
39add00a | 1466 | store_typed_floating (to, type, val); |
55ff77ac CV |
1467 | } |
1468 | else | |
a73c6dcd MS |
1469 | error (_("sh64_register_convert_to_virtual " |
1470 | "called with non DR register number")); | |
55ff77ac CV |
1471 | } |
1472 | ||
1473 | static void | |
d93859e2 UW |
1474 | sh64_register_convert_to_raw (struct gdbarch *gdbarch, struct type *type, |
1475 | int regnum, const void *from, void *to) | |
55ff77ac | 1476 | { |
d93859e2 | 1477 | if (gdbarch_byte_order (gdbarch) != BFD_ENDIAN_LITTLE) |
55ff77ac | 1478 | { |
7bb11558 | 1479 | /* It is a no-op. */ |
d93859e2 | 1480 | memcpy (to, from, register_size (gdbarch, regnum)); |
55ff77ac CV |
1481 | return; |
1482 | } | |
1483 | ||
1484 | if ((regnum >= DR0_REGNUM | |
1485 | && regnum <= DR_LAST_REGNUM) | |
1486 | || (regnum >= DR0_C_REGNUM | |
1487 | && regnum <= DR_LAST_C_REGNUM)) | |
1488 | { | |
e035e373 | 1489 | DOUBLEST val = extract_typed_floating (from, type); |
7bb11558 MS |
1490 | floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword, |
1491 | &val, to); | |
55ff77ac CV |
1492 | } |
1493 | else | |
a73c6dcd MS |
1494 | error (_("sh64_register_convert_to_raw called " |
1495 | "with non DR register number")); | |
55ff77ac CV |
1496 | } |
1497 | ||
05d1431c PA |
1498 | /* Concatenate PORTIONS contiguous raw registers starting at |
1499 | BASE_REGNUM into BUFFER. */ | |
1500 | ||
1501 | static enum register_status | |
1502 | pseudo_register_read_portions (struct gdbarch *gdbarch, | |
1503 | struct regcache *regcache, | |
1504 | int portions, | |
1505 | int base_regnum, gdb_byte *buffer) | |
1506 | { | |
1507 | int portion; | |
1508 | ||
1509 | for (portion = 0; portion < portions; portion++) | |
1510 | { | |
1511 | enum register_status status; | |
1512 | gdb_byte *b; | |
1513 | ||
1514 | b = buffer + register_size (gdbarch, base_regnum) * portion; | |
1515 | status = regcache_raw_read (regcache, base_regnum + portion, b); | |
1516 | if (status != REG_VALID) | |
1517 | return status; | |
1518 | } | |
1519 | ||
1520 | return REG_VALID; | |
1521 | } | |
1522 | ||
1523 | static enum register_status | |
55ff77ac | 1524 | sh64_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, |
18cf8b5b | 1525 | int reg_nr, gdb_byte *buffer) |
55ff77ac | 1526 | { |
e17a4113 | 1527 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
55ff77ac | 1528 | int base_regnum; |
55ff77ac | 1529 | int offset = 0; |
948f8e3d | 1530 | gdb_byte temp_buffer[MAX_REGISTER_SIZE]; |
05d1431c | 1531 | enum register_status status; |
55ff77ac CV |
1532 | |
1533 | if (reg_nr >= DR0_REGNUM | |
1534 | && reg_nr <= DR_LAST_REGNUM) | |
1535 | { | |
d93859e2 | 1536 | base_regnum = sh64_dr_reg_base_num (gdbarch, reg_nr); |
55ff77ac | 1537 | |
7bb11558 | 1538 | /* Build the value in the provided buffer. */ |
55ff77ac | 1539 | /* DR regs are double precision registers obtained by |
7bb11558 | 1540 | concatenating 2 single precision floating point registers. */ |
05d1431c PA |
1541 | status = pseudo_register_read_portions (gdbarch, regcache, |
1542 | 2, base_regnum, temp_buffer); | |
1543 | if (status == REG_VALID) | |
1544 | { | |
1545 | /* We must pay attention to the endianness. */ | |
1546 | sh64_register_convert_to_virtual (gdbarch, reg_nr, | |
1547 | register_type (gdbarch, reg_nr), | |
1548 | temp_buffer, buffer); | |
1549 | } | |
55ff77ac | 1550 | |
05d1431c | 1551 | return status; |
55ff77ac CV |
1552 | } |
1553 | ||
05d1431c | 1554 | else if (reg_nr >= FPP0_REGNUM |
55ff77ac CV |
1555 | && reg_nr <= FPP_LAST_REGNUM) |
1556 | { | |
d93859e2 | 1557 | base_regnum = sh64_fpp_reg_base_num (gdbarch, reg_nr); |
55ff77ac | 1558 | |
7bb11558 | 1559 | /* Build the value in the provided buffer. */ |
55ff77ac | 1560 | /* FPP regs are pairs of single precision registers obtained by |
7bb11558 | 1561 | concatenating 2 single precision floating point registers. */ |
05d1431c PA |
1562 | return pseudo_register_read_portions (gdbarch, regcache, |
1563 | 2, base_regnum, buffer); | |
55ff77ac CV |
1564 | } |
1565 | ||
1566 | else if (reg_nr >= FV0_REGNUM | |
1567 | && reg_nr <= FV_LAST_REGNUM) | |
1568 | { | |
d93859e2 | 1569 | base_regnum = sh64_fv_reg_base_num (gdbarch, reg_nr); |
55ff77ac | 1570 | |
7bb11558 | 1571 | /* Build the value in the provided buffer. */ |
55ff77ac | 1572 | /* FV regs are vectors of single precision registers obtained by |
7bb11558 | 1573 | concatenating 4 single precision floating point registers. */ |
05d1431c PA |
1574 | return pseudo_register_read_portions (gdbarch, regcache, |
1575 | 4, base_regnum, buffer); | |
55ff77ac CV |
1576 | } |
1577 | ||
c378eb4e | 1578 | /* sh compact pseudo registers. 1-to-1 with a shmedia register. */ |
55ff77ac CV |
1579 | else if (reg_nr >= R0_C_REGNUM |
1580 | && reg_nr <= T_C_REGNUM) | |
1581 | { | |
d93859e2 | 1582 | base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr); |
55ff77ac | 1583 | |
7bb11558 | 1584 | /* Build the value in the provided buffer. */ |
05d1431c PA |
1585 | status = regcache_raw_read (regcache, base_regnum, temp_buffer); |
1586 | if (status != REG_VALID) | |
1587 | return status; | |
58643501 | 1588 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
55ff77ac | 1589 | offset = 4; |
c378eb4e MS |
1590 | memcpy (buffer, |
1591 | temp_buffer + offset, 4); /* get LOWER 32 bits only???? */ | |
05d1431c | 1592 | return REG_VALID; |
55ff77ac CV |
1593 | } |
1594 | ||
1595 | else if (reg_nr >= FP0_C_REGNUM | |
1596 | && reg_nr <= FP_LAST_C_REGNUM) | |
1597 | { | |
d93859e2 | 1598 | base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr); |
55ff77ac | 1599 | |
7bb11558 | 1600 | /* Build the value in the provided buffer. */ |
55ff77ac | 1601 | /* Floating point registers map 1-1 to the media fp regs, |
7bb11558 | 1602 | they have the same size and endianness. */ |
05d1431c | 1603 | return regcache_raw_read (regcache, base_regnum, buffer); |
55ff77ac CV |
1604 | } |
1605 | ||
1606 | else if (reg_nr >= DR0_C_REGNUM | |
1607 | && reg_nr <= DR_LAST_C_REGNUM) | |
1608 | { | |
d93859e2 | 1609 | base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr); |
55ff77ac CV |
1610 | |
1611 | /* DR_C regs are double precision registers obtained by | |
7bb11558 | 1612 | concatenating 2 single precision floating point registers. */ |
05d1431c PA |
1613 | status = pseudo_register_read_portions (gdbarch, regcache, |
1614 | 2, base_regnum, temp_buffer); | |
1615 | if (status == REG_VALID) | |
1616 | { | |
1617 | /* We must pay attention to the endianness. */ | |
1618 | sh64_register_convert_to_virtual (gdbarch, reg_nr, | |
1619 | register_type (gdbarch, reg_nr), | |
1620 | temp_buffer, buffer); | |
1621 | } | |
1622 | return status; | |
55ff77ac CV |
1623 | } |
1624 | ||
1625 | else if (reg_nr >= FV0_C_REGNUM | |
1626 | && reg_nr <= FV_LAST_C_REGNUM) | |
1627 | { | |
d93859e2 | 1628 | base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr); |
55ff77ac | 1629 | |
7bb11558 | 1630 | /* Build the value in the provided buffer. */ |
55ff77ac | 1631 | /* FV_C regs are vectors of single precision registers obtained by |
7bb11558 | 1632 | concatenating 4 single precision floating point registers. */ |
05d1431c PA |
1633 | return pseudo_register_read_portions (gdbarch, regcache, |
1634 | 4, base_regnum, buffer); | |
55ff77ac CV |
1635 | } |
1636 | ||
1637 | else if (reg_nr == FPSCR_C_REGNUM) | |
1638 | { | |
1639 | int fpscr_base_regnum; | |
1640 | int sr_base_regnum; | |
1641 | unsigned int fpscr_value; | |
1642 | unsigned int sr_value; | |
1643 | unsigned int fpscr_c_value; | |
1644 | unsigned int fpscr_c_part1_value; | |
1645 | unsigned int fpscr_c_part2_value; | |
1646 | ||
1647 | fpscr_base_regnum = FPSCR_REGNUM; | |
1648 | sr_base_regnum = SR_REGNUM; | |
1649 | ||
7bb11558 | 1650 | /* Build the value in the provided buffer. */ |
55ff77ac CV |
1651 | /* FPSCR_C is a very weird register that contains sparse bits |
1652 | from the FPSCR and the SR architectural registers. | |
1653 | Specifically: */ | |
1654 | /* *INDENT-OFF* */ | |
1655 | /* | |
1656 | FPSRC_C bit | |
1657 | 0 Bit 0 of FPSCR | |
1658 | 1 reserved | |
1659 | 2-17 Bit 2-18 of FPSCR | |
1660 | 18-20 Bits 12,13,14 of SR | |
1661 | 21-31 reserved | |
1662 | */ | |
1663 | /* *INDENT-ON* */ | |
c378eb4e | 1664 | /* Get FPSCR into a local buffer. */ |
05d1431c PA |
1665 | status = regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer); |
1666 | if (status != REG_VALID) | |
1667 | return status; | |
7bb11558 | 1668 | /* Get value as an int. */ |
e17a4113 | 1669 | fpscr_value = extract_unsigned_integer (temp_buffer, 4, byte_order); |
55ff77ac | 1670 | /* Get SR into a local buffer */ |
05d1431c PA |
1671 | status = regcache_raw_read (regcache, sr_base_regnum, temp_buffer); |
1672 | if (status != REG_VALID) | |
1673 | return status; | |
7bb11558 | 1674 | /* Get value as an int. */ |
e17a4113 | 1675 | sr_value = extract_unsigned_integer (temp_buffer, 4, byte_order); |
7bb11558 | 1676 | /* Build the new value. */ |
55ff77ac CV |
1677 | fpscr_c_part1_value = fpscr_value & 0x3fffd; |
1678 | fpscr_c_part2_value = (sr_value & 0x7000) << 6; | |
1679 | fpscr_c_value = fpscr_c_part1_value | fpscr_c_part2_value; | |
c378eb4e | 1680 | /* Store that in out buffer!!! */ |
e17a4113 | 1681 | store_unsigned_integer (buffer, 4, byte_order, fpscr_c_value); |
7bb11558 | 1682 | /* FIXME There is surely an endianness gotcha here. */ |
05d1431c PA |
1683 | |
1684 | return REG_VALID; | |
55ff77ac CV |
1685 | } |
1686 | ||
1687 | else if (reg_nr == FPUL_C_REGNUM) | |
1688 | { | |
d93859e2 | 1689 | base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr); |
55ff77ac CV |
1690 | |
1691 | /* FPUL_C register is floating point register 32, | |
7bb11558 | 1692 | same size, same endianness. */ |
05d1431c | 1693 | return regcache_raw_read (regcache, base_regnum, buffer); |
55ff77ac | 1694 | } |
05d1431c PA |
1695 | else |
1696 | gdb_assert_not_reached ("invalid pseudo register number"); | |
55ff77ac CV |
1697 | } |
1698 | ||
1699 | static void | |
1700 | sh64_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
18cf8b5b | 1701 | int reg_nr, const gdb_byte *buffer) |
55ff77ac | 1702 | { |
e17a4113 | 1703 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
55ff77ac CV |
1704 | int base_regnum, portion; |
1705 | int offset; | |
948f8e3d | 1706 | gdb_byte temp_buffer[MAX_REGISTER_SIZE]; |
55ff77ac CV |
1707 | |
1708 | if (reg_nr >= DR0_REGNUM | |
1709 | && reg_nr <= DR_LAST_REGNUM) | |
1710 | { | |
d93859e2 | 1711 | base_regnum = sh64_dr_reg_base_num (gdbarch, reg_nr); |
7bb11558 | 1712 | /* We must pay attention to the endianness. */ |
d93859e2 | 1713 | sh64_register_convert_to_raw (gdbarch, register_type (gdbarch, reg_nr), |
39add00a MS |
1714 | reg_nr, |
1715 | buffer, temp_buffer); | |
55ff77ac CV |
1716 | |
1717 | /* Write the real regs for which this one is an alias. */ | |
1718 | for (portion = 0; portion < 2; portion++) | |
1719 | regcache_raw_write (regcache, base_regnum + portion, | |
1720 | (temp_buffer | |
948f8e3d | 1721 | + register_size (gdbarch, |
7bb11558 | 1722 | base_regnum) * portion)); |
55ff77ac CV |
1723 | } |
1724 | ||
1725 | else if (reg_nr >= FPP0_REGNUM | |
1726 | && reg_nr <= FPP_LAST_REGNUM) | |
1727 | { | |
d93859e2 | 1728 | base_regnum = sh64_fpp_reg_base_num (gdbarch, reg_nr); |
55ff77ac CV |
1729 | |
1730 | /* Write the real regs for which this one is an alias. */ | |
1731 | for (portion = 0; portion < 2; portion++) | |
1732 | regcache_raw_write (regcache, base_regnum + portion, | |
948f8e3d PA |
1733 | (buffer + register_size (gdbarch, |
1734 | base_regnum) * portion)); | |
55ff77ac CV |
1735 | } |
1736 | ||
1737 | else if (reg_nr >= FV0_REGNUM | |
1738 | && reg_nr <= FV_LAST_REGNUM) | |
1739 | { | |
d93859e2 | 1740 | base_regnum = sh64_fv_reg_base_num (gdbarch, reg_nr); |
55ff77ac CV |
1741 | |
1742 | /* Write the real regs for which this one is an alias. */ | |
1743 | for (portion = 0; portion < 4; portion++) | |
1744 | regcache_raw_write (regcache, base_regnum + portion, | |
948f8e3d PA |
1745 | (buffer + register_size (gdbarch, |
1746 | base_regnum) * portion)); | |
55ff77ac CV |
1747 | } |
1748 | ||
c378eb4e | 1749 | /* sh compact general pseudo registers. 1-to-1 with a shmedia |
55ff77ac CV |
1750 | register but only 4 bytes of it. */ |
1751 | else if (reg_nr >= R0_C_REGNUM | |
1752 | && reg_nr <= T_C_REGNUM) | |
1753 | { | |
d93859e2 | 1754 | base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr); |
7bb11558 | 1755 | /* reg_nr is 32 bit here, and base_regnum is 64 bits. */ |
58643501 | 1756 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
55ff77ac CV |
1757 | offset = 4; |
1758 | else | |
1759 | offset = 0; | |
1760 | /* Let's read the value of the base register into a temporary | |
1761 | buffer, so that overwriting the last four bytes with the new | |
7bb11558 | 1762 | value of the pseudo will leave the upper 4 bytes unchanged. */ |
55ff77ac | 1763 | regcache_raw_read (regcache, base_regnum, temp_buffer); |
c378eb4e | 1764 | /* Write as an 8 byte quantity. */ |
55ff77ac CV |
1765 | memcpy (temp_buffer + offset, buffer, 4); |
1766 | regcache_raw_write (regcache, base_regnum, temp_buffer); | |
1767 | } | |
1768 | ||
c378eb4e MS |
1769 | /* sh floating point compact pseudo registers. 1-to-1 with a shmedia |
1770 | registers. Both are 4 bytes. */ | |
55ff77ac CV |
1771 | else if (reg_nr >= FP0_C_REGNUM |
1772 | && reg_nr <= FP_LAST_C_REGNUM) | |
1773 | { | |
d93859e2 | 1774 | base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr); |
55ff77ac CV |
1775 | regcache_raw_write (regcache, base_regnum, buffer); |
1776 | } | |
1777 | ||
1778 | else if (reg_nr >= DR0_C_REGNUM | |
1779 | && reg_nr <= DR_LAST_C_REGNUM) | |
1780 | { | |
d93859e2 | 1781 | base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr); |
55ff77ac CV |
1782 | for (portion = 0; portion < 2; portion++) |
1783 | { | |
7bb11558 | 1784 | /* We must pay attention to the endianness. */ |
d93859e2 UW |
1785 | sh64_register_convert_to_raw (gdbarch, |
1786 | register_type (gdbarch, reg_nr), | |
39add00a MS |
1787 | reg_nr, |
1788 | buffer, temp_buffer); | |
55ff77ac CV |
1789 | |
1790 | regcache_raw_write (regcache, base_regnum + portion, | |
1791 | (temp_buffer | |
7bb11558 MS |
1792 | + register_size (gdbarch, |
1793 | base_regnum) * portion)); | |
55ff77ac CV |
1794 | } |
1795 | } | |
1796 | ||
1797 | else if (reg_nr >= FV0_C_REGNUM | |
1798 | && reg_nr <= FV_LAST_C_REGNUM) | |
1799 | { | |
d93859e2 | 1800 | base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr); |
55ff77ac CV |
1801 | |
1802 | for (portion = 0; portion < 4; portion++) | |
1803 | { | |
1804 | regcache_raw_write (regcache, base_regnum + portion, | |
948f8e3d | 1805 | (buffer |
7bb11558 MS |
1806 | + register_size (gdbarch, |
1807 | base_regnum) * portion)); | |
55ff77ac CV |
1808 | } |
1809 | } | |
1810 | ||
1811 | else if (reg_nr == FPSCR_C_REGNUM) | |
1812 | { | |
1813 | int fpscr_base_regnum; | |
1814 | int sr_base_regnum; | |
1815 | unsigned int fpscr_value; | |
1816 | unsigned int sr_value; | |
1817 | unsigned int old_fpscr_value; | |
1818 | unsigned int old_sr_value; | |
1819 | unsigned int fpscr_c_value; | |
1820 | unsigned int fpscr_mask; | |
1821 | unsigned int sr_mask; | |
1822 | ||
1823 | fpscr_base_regnum = FPSCR_REGNUM; | |
1824 | sr_base_regnum = SR_REGNUM; | |
1825 | ||
1826 | /* FPSCR_C is a very weird register that contains sparse bits | |
1827 | from the FPSCR and the SR architectural registers. | |
1828 | Specifically: */ | |
1829 | /* *INDENT-OFF* */ | |
1830 | /* | |
1831 | FPSRC_C bit | |
1832 | 0 Bit 0 of FPSCR | |
1833 | 1 reserved | |
1834 | 2-17 Bit 2-18 of FPSCR | |
1835 | 18-20 Bits 12,13,14 of SR | |
1836 | 21-31 reserved | |
1837 | */ | |
1838 | /* *INDENT-ON* */ | |
7bb11558 | 1839 | /* Get value as an int. */ |
e17a4113 | 1840 | fpscr_c_value = extract_unsigned_integer (buffer, 4, byte_order); |
55ff77ac | 1841 | |
7bb11558 | 1842 | /* Build the new values. */ |
55ff77ac CV |
1843 | fpscr_mask = 0x0003fffd; |
1844 | sr_mask = 0x001c0000; | |
1845 | ||
1846 | fpscr_value = fpscr_c_value & fpscr_mask; | |
1847 | sr_value = (fpscr_value & sr_mask) >> 6; | |
1848 | ||
1849 | regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer); | |
e17a4113 | 1850 | old_fpscr_value = extract_unsigned_integer (temp_buffer, 4, byte_order); |
55ff77ac CV |
1851 | old_fpscr_value &= 0xfffc0002; |
1852 | fpscr_value |= old_fpscr_value; | |
e17a4113 | 1853 | store_unsigned_integer (temp_buffer, 4, byte_order, fpscr_value); |
55ff77ac CV |
1854 | regcache_raw_write (regcache, fpscr_base_regnum, temp_buffer); |
1855 | ||
1856 | regcache_raw_read (regcache, sr_base_regnum, temp_buffer); | |
e17a4113 | 1857 | old_sr_value = extract_unsigned_integer (temp_buffer, 4, byte_order); |
55ff77ac CV |
1858 | old_sr_value &= 0xffff8fff; |
1859 | sr_value |= old_sr_value; | |
e17a4113 | 1860 | store_unsigned_integer (temp_buffer, 4, byte_order, sr_value); |
55ff77ac CV |
1861 | regcache_raw_write (regcache, sr_base_regnum, temp_buffer); |
1862 | } | |
1863 | ||
1864 | else if (reg_nr == FPUL_C_REGNUM) | |
1865 | { | |
d93859e2 | 1866 | base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr); |
55ff77ac CV |
1867 | regcache_raw_write (regcache, base_regnum, buffer); |
1868 | } | |
1869 | } | |
1870 | ||
55ff77ac | 1871 | /* FIXME:!! THIS SHOULD TAKE CARE OF GETTING THE RIGHT PORTION OF THE |
7bb11558 MS |
1872 | shmedia REGISTERS. */ |
1873 | /* Control registers, compact mode. */ | |
55ff77ac | 1874 | static void |
c30dc700 CV |
1875 | sh64_do_cr_c_register_info (struct ui_file *file, struct frame_info *frame, |
1876 | int cr_c_regnum) | |
55ff77ac CV |
1877 | { |
1878 | switch (cr_c_regnum) | |
1879 | { | |
c30dc700 CV |
1880 | case PC_C_REGNUM: |
1881 | fprintf_filtered (file, "pc_c\t0x%08x\n", | |
1882 | (int) get_frame_register_unsigned (frame, cr_c_regnum)); | |
55ff77ac | 1883 | break; |
c30dc700 CV |
1884 | case GBR_C_REGNUM: |
1885 | fprintf_filtered (file, "gbr_c\t0x%08x\n", | |
1886 | (int) get_frame_register_unsigned (frame, cr_c_regnum)); | |
55ff77ac | 1887 | break; |
c30dc700 CV |
1888 | case MACH_C_REGNUM: |
1889 | fprintf_filtered (file, "mach_c\t0x%08x\n", | |
1890 | (int) get_frame_register_unsigned (frame, cr_c_regnum)); | |
55ff77ac | 1891 | break; |
c30dc700 CV |
1892 | case MACL_C_REGNUM: |
1893 | fprintf_filtered (file, "macl_c\t0x%08x\n", | |
1894 | (int) get_frame_register_unsigned (frame, cr_c_regnum)); | |
55ff77ac | 1895 | break; |
c30dc700 CV |
1896 | case PR_C_REGNUM: |
1897 | fprintf_filtered (file, "pr_c\t0x%08x\n", | |
1898 | (int) get_frame_register_unsigned (frame, cr_c_regnum)); | |
55ff77ac | 1899 | break; |
c30dc700 CV |
1900 | case T_C_REGNUM: |
1901 | fprintf_filtered (file, "t_c\t0x%08x\n", | |
1902 | (int) get_frame_register_unsigned (frame, cr_c_regnum)); | |
55ff77ac | 1903 | break; |
c30dc700 CV |
1904 | case FPSCR_C_REGNUM: |
1905 | fprintf_filtered (file, "fpscr_c\t0x%08x\n", | |
1906 | (int) get_frame_register_unsigned (frame, cr_c_regnum)); | |
55ff77ac | 1907 | break; |
c30dc700 CV |
1908 | case FPUL_C_REGNUM: |
1909 | fprintf_filtered (file, "fpul_c\t0x%08x\n", | |
1910 | (int) get_frame_register_unsigned (frame, cr_c_regnum)); | |
55ff77ac CV |
1911 | break; |
1912 | } | |
1913 | } | |
1914 | ||
1915 | static void | |
c30dc700 CV |
1916 | sh64_do_fp_register (struct gdbarch *gdbarch, struct ui_file *file, |
1917 | struct frame_info *frame, int regnum) | |
c378eb4e | 1918 | { /* Do values for FP (float) regs. */ |
079c8cd0 | 1919 | unsigned char *raw_buffer; |
c378eb4e | 1920 | double flt; /* Double extracted from raw hex data. */ |
55ff77ac CV |
1921 | int inv; |
1922 | int j; | |
1923 | ||
7bb11558 | 1924 | /* Allocate space for the float. */ |
c378eb4e MS |
1925 | raw_buffer = (unsigned char *) |
1926 | alloca (register_size (gdbarch, gdbarch_fp0_regnum (gdbarch))); | |
55ff77ac CV |
1927 | |
1928 | /* Get the data in raw format. */ | |
ca9d61b9 | 1929 | if (!deprecated_frame_register_read (frame, regnum, raw_buffer)) |
a73c6dcd | 1930 | error (_("can't read register %d (%s)"), |
58643501 | 1931 | regnum, gdbarch_register_name (gdbarch, regnum)); |
55ff77ac | 1932 | |
c378eb4e MS |
1933 | /* Get the register as a number. */ |
1934 | flt = unpack_double (builtin_type (gdbarch)->builtin_float, | |
1935 | raw_buffer, &inv); | |
55ff77ac | 1936 | |
7bb11558 | 1937 | /* Print the name and some spaces. */ |
58643501 | 1938 | fputs_filtered (gdbarch_register_name (gdbarch, regnum), file); |
c9f4d572 | 1939 | print_spaces_filtered (15 - strlen (gdbarch_register_name |
58643501 | 1940 | (gdbarch, regnum)), file); |
55ff77ac | 1941 | |
7bb11558 | 1942 | /* Print the value. */ |
55ff77ac CV |
1943 | if (inv) |
1944 | fprintf_filtered (file, "<invalid float>"); | |
1945 | else | |
1946 | fprintf_filtered (file, "%-10.9g", flt); | |
1947 | ||
7bb11558 | 1948 | /* Print the fp register as hex. */ |
2cc762b5 AB |
1949 | fprintf_filtered (file, "\t(raw "); |
1950 | print_hex_chars (file, raw_buffer, | |
1951 | register_size (gdbarch, regnum), | |
1952 | gdbarch_byte_order (gdbarch)); | |
55ff77ac CV |
1953 | fprintf_filtered (file, ")"); |
1954 | fprintf_filtered (file, "\n"); | |
1955 | } | |
1956 | ||
1957 | static void | |
c30dc700 CV |
1958 | sh64_do_pseudo_register (struct gdbarch *gdbarch, struct ui_file *file, |
1959 | struct frame_info *frame, int regnum) | |
55ff77ac | 1960 | { |
7bb11558 | 1961 | /* All the sh64-compact mode registers are pseudo registers. */ |
55ff77ac | 1962 | |
58643501 UW |
1963 | if (regnum < gdbarch_num_regs (gdbarch) |
1964 | || regnum >= gdbarch_num_regs (gdbarch) | |
f57d151a UW |
1965 | + NUM_PSEUDO_REGS_SH_MEDIA |
1966 | + NUM_PSEUDO_REGS_SH_COMPACT) | |
55ff77ac | 1967 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 1968 | _("Invalid pseudo register number %d\n"), regnum); |
55ff77ac | 1969 | |
c30dc700 CV |
1970 | else if ((regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)) |
1971 | { | |
d93859e2 | 1972 | int fp_regnum = sh64_dr_reg_base_num (gdbarch, regnum); |
c30dc700 CV |
1973 | fprintf_filtered (file, "dr%d\t0x%08x%08x\n", regnum - DR0_REGNUM, |
1974 | (unsigned) get_frame_register_unsigned (frame, fp_regnum), | |
1975 | (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1)); | |
1976 | } | |
55ff77ac | 1977 | |
c30dc700 CV |
1978 | else if ((regnum >= DR0_C_REGNUM && regnum <= DR_LAST_C_REGNUM)) |
1979 | { | |
d93859e2 | 1980 | int fp_regnum = sh64_compact_reg_base_num (gdbarch, regnum); |
c30dc700 CV |
1981 | fprintf_filtered (file, "dr%d_c\t0x%08x%08x\n", regnum - DR0_C_REGNUM, |
1982 | (unsigned) get_frame_register_unsigned (frame, fp_regnum), | |
1983 | (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1)); | |
1984 | } | |
55ff77ac | 1985 | |
c30dc700 CV |
1986 | else if ((regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM)) |
1987 | { | |
d93859e2 | 1988 | int fp_regnum = sh64_fv_reg_base_num (gdbarch, regnum); |
c30dc700 CV |
1989 | fprintf_filtered (file, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n", |
1990 | regnum - FV0_REGNUM, | |
1991 | (unsigned) get_frame_register_unsigned (frame, fp_regnum), | |
1992 | (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1), | |
1993 | (unsigned) get_frame_register_unsigned (frame, fp_regnum + 2), | |
1994 | (unsigned) get_frame_register_unsigned (frame, fp_regnum + 3)); | |
1995 | } | |
55ff77ac | 1996 | |
c30dc700 CV |
1997 | else if ((regnum >= FV0_C_REGNUM && regnum <= FV_LAST_C_REGNUM)) |
1998 | { | |
d93859e2 | 1999 | int fp_regnum = sh64_compact_reg_base_num (gdbarch, regnum); |
c30dc700 CV |
2000 | fprintf_filtered (file, "fv%d_c\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n", |
2001 | regnum - FV0_C_REGNUM, | |
2002 | (unsigned) get_frame_register_unsigned (frame, fp_regnum), | |
2003 | (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1), | |
2004 | (unsigned) get_frame_register_unsigned (frame, fp_regnum + 2), | |
2005 | (unsigned) get_frame_register_unsigned (frame, fp_regnum + 3)); | |
2006 | } | |
2007 | ||
2008 | else if (regnum >= FPP0_REGNUM && regnum <= FPP_LAST_REGNUM) | |
2009 | { | |
d93859e2 | 2010 | int fp_regnum = sh64_fpp_reg_base_num (gdbarch, regnum); |
c30dc700 CV |
2011 | fprintf_filtered (file, "fpp%d\t0x%08x\t0x%08x\n", regnum - FPP0_REGNUM, |
2012 | (unsigned) get_frame_register_unsigned (frame, fp_regnum), | |
2013 | (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1)); | |
2014 | } | |
2015 | ||
2016 | else if (regnum >= R0_C_REGNUM && regnum <= R_LAST_C_REGNUM) | |
2017 | { | |
d93859e2 | 2018 | int c_regnum = sh64_compact_reg_base_num (gdbarch, regnum); |
c30dc700 CV |
2019 | fprintf_filtered (file, "r%d_c\t0x%08x\n", regnum - R0_C_REGNUM, |
2020 | (unsigned) get_frame_register_unsigned (frame, c_regnum)); | |
2021 | } | |
2022 | else if (regnum >= FP0_C_REGNUM && regnum <= FP_LAST_C_REGNUM) | |
7bb11558 | 2023 | /* This should work also for pseudoregs. */ |
c30dc700 CV |
2024 | sh64_do_fp_register (gdbarch, file, frame, regnum); |
2025 | else if (regnum >= PC_C_REGNUM && regnum <= FPUL_C_REGNUM) | |
2026 | sh64_do_cr_c_register_info (file, frame, regnum); | |
55ff77ac CV |
2027 | } |
2028 | ||
2029 | static void | |
c30dc700 CV |
2030 | sh64_do_register (struct gdbarch *gdbarch, struct ui_file *file, |
2031 | struct frame_info *frame, int regnum) | |
55ff77ac | 2032 | { |
079c8cd0 | 2033 | unsigned char raw_buffer[MAX_REGISTER_SIZE]; |
79a45b7d | 2034 | struct value_print_options opts; |
55ff77ac | 2035 | |
58643501 | 2036 | fputs_filtered (gdbarch_register_name (gdbarch, regnum), file); |
c9f4d572 | 2037 | print_spaces_filtered (15 - strlen (gdbarch_register_name |
58643501 | 2038 | (gdbarch, regnum)), file); |
55ff77ac CV |
2039 | |
2040 | /* Get the data in raw format. */ | |
ca9d61b9 | 2041 | if (!deprecated_frame_register_read (frame, regnum, raw_buffer)) |
47061676 AB |
2042 | { |
2043 | fprintf_filtered (file, "*value not available*\n"); | |
2044 | return; | |
2045 | } | |
79a45b7d TT |
2046 | |
2047 | get_formatted_print_options (&opts, 'x'); | |
2048 | opts.deref_ref = 1; | |
7b9ee6a8 | 2049 | val_print (register_type (gdbarch, regnum), raw_buffer, 0, 0, |
0e03807e | 2050 | file, 0, NULL, &opts, current_language); |
55ff77ac | 2051 | fprintf_filtered (file, "\t"); |
79a45b7d TT |
2052 | get_formatted_print_options (&opts, 0); |
2053 | opts.deref_ref = 1; | |
7b9ee6a8 | 2054 | val_print (register_type (gdbarch, regnum), raw_buffer, 0, 0, |
0e03807e | 2055 | file, 0, NULL, &opts, current_language); |
55ff77ac CV |
2056 | fprintf_filtered (file, "\n"); |
2057 | } | |
2058 | ||
2059 | static void | |
c30dc700 CV |
2060 | sh64_print_register (struct gdbarch *gdbarch, struct ui_file *file, |
2061 | struct frame_info *frame, int regnum) | |
55ff77ac | 2062 | { |
58643501 UW |
2063 | if (regnum < 0 || regnum >= gdbarch_num_regs (gdbarch) |
2064 | + gdbarch_num_pseudo_regs (gdbarch)) | |
55ff77ac | 2065 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 2066 | _("Invalid register number %d\n"), regnum); |
55ff77ac | 2067 | |
58643501 | 2068 | else if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)) |
55ff77ac | 2069 | { |
7b9ee6a8 | 2070 | if (TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
c30dc700 | 2071 | sh64_do_fp_register (gdbarch, file, frame, regnum); /* FP regs */ |
55ff77ac | 2072 | else |
c30dc700 | 2073 | sh64_do_register (gdbarch, file, frame, regnum); |
55ff77ac CV |
2074 | } |
2075 | ||
58643501 UW |
2076 | else if (regnum < gdbarch_num_regs (gdbarch) |
2077 | + gdbarch_num_pseudo_regs (gdbarch)) | |
c30dc700 | 2078 | sh64_do_pseudo_register (gdbarch, file, frame, regnum); |
55ff77ac CV |
2079 | } |
2080 | ||
2081 | static void | |
c30dc700 CV |
2082 | sh64_media_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
2083 | struct frame_info *frame, int regnum, | |
2084 | int fpregs) | |
55ff77ac | 2085 | { |
c378eb4e | 2086 | if (regnum != -1) /* Do one specified register. */ |
55ff77ac | 2087 | { |
58643501 | 2088 | if (*(gdbarch_register_name (gdbarch, regnum)) == '\0') |
a73c6dcd | 2089 | error (_("Not a valid register for the current processor type")); |
55ff77ac | 2090 | |
c30dc700 | 2091 | sh64_print_register (gdbarch, file, frame, regnum); |
55ff77ac CV |
2092 | } |
2093 | else | |
c378eb4e | 2094 | /* Do all (or most) registers. */ |
55ff77ac CV |
2095 | { |
2096 | regnum = 0; | |
58643501 | 2097 | while (regnum < gdbarch_num_regs (gdbarch)) |
55ff77ac CV |
2098 | { |
2099 | /* If the register name is empty, it is undefined for this | |
2100 | processor, so don't display anything. */ | |
58643501 UW |
2101 | if (gdbarch_register_name (gdbarch, regnum) == NULL |
2102 | || *(gdbarch_register_name (gdbarch, regnum)) == '\0') | |
55ff77ac CV |
2103 | { |
2104 | regnum++; | |
2105 | continue; | |
2106 | } | |
2107 | ||
7b9ee6a8 | 2108 | if (TYPE_CODE (register_type (gdbarch, regnum)) |
c30dc700 | 2109 | == TYPE_CODE_FLT) |
55ff77ac CV |
2110 | { |
2111 | if (fpregs) | |
2112 | { | |
c378eb4e | 2113 | /* true for "INFO ALL-REGISTERS" command. */ |
c30dc700 | 2114 | sh64_do_fp_register (gdbarch, file, frame, regnum); |
55ff77ac CV |
2115 | regnum ++; |
2116 | } | |
2117 | else | |
58643501 | 2118 | regnum += FP_LAST_REGNUM - gdbarch_fp0_regnum (gdbarch); |
3e8c568d | 2119 | /* skip FP regs */ |
55ff77ac CV |
2120 | } |
2121 | else | |
2122 | { | |
c30dc700 | 2123 | sh64_do_register (gdbarch, file, frame, regnum); |
55ff77ac CV |
2124 | regnum++; |
2125 | } | |
2126 | } | |
2127 | ||
2128 | if (fpregs) | |
58643501 UW |
2129 | while (regnum < gdbarch_num_regs (gdbarch) |
2130 | + gdbarch_num_pseudo_regs (gdbarch)) | |
55ff77ac | 2131 | { |
c30dc700 | 2132 | sh64_do_pseudo_register (gdbarch, file, frame, regnum); |
55ff77ac CV |
2133 | regnum++; |
2134 | } | |
2135 | } | |
2136 | } | |
2137 | ||
2138 | static void | |
c30dc700 CV |
2139 | sh64_compact_print_registers_info (struct gdbarch *gdbarch, |
2140 | struct ui_file *file, | |
2141 | struct frame_info *frame, int regnum, | |
2142 | int fpregs) | |
55ff77ac | 2143 | { |
c378eb4e | 2144 | if (regnum != -1) /* Do one specified register. */ |
55ff77ac | 2145 | { |
58643501 | 2146 | if (*(gdbarch_register_name (gdbarch, regnum)) == '\0') |
a73c6dcd | 2147 | error (_("Not a valid register for the current processor type")); |
55ff77ac CV |
2148 | |
2149 | if (regnum >= 0 && regnum < R0_C_REGNUM) | |
a73c6dcd | 2150 | error (_("Not a valid register for the current processor mode.")); |
55ff77ac | 2151 | |
c30dc700 | 2152 | sh64_print_register (gdbarch, file, frame, regnum); |
55ff77ac CV |
2153 | } |
2154 | else | |
c378eb4e | 2155 | /* Do all compact registers. */ |
55ff77ac CV |
2156 | { |
2157 | regnum = R0_C_REGNUM; | |
58643501 UW |
2158 | while (regnum < gdbarch_num_regs (gdbarch) |
2159 | + gdbarch_num_pseudo_regs (gdbarch)) | |
55ff77ac | 2160 | { |
c30dc700 | 2161 | sh64_do_pseudo_register (gdbarch, file, frame, regnum); |
55ff77ac CV |
2162 | regnum++; |
2163 | } | |
2164 | } | |
2165 | } | |
2166 | ||
2167 | static void | |
c30dc700 CV |
2168 | sh64_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
2169 | struct frame_info *frame, int regnum, int fpregs) | |
55ff77ac | 2170 | { |
c30dc700 CV |
2171 | if (pc_is_isa32 (get_frame_pc (frame))) |
2172 | sh64_media_print_registers_info (gdbarch, file, frame, regnum, fpregs); | |
55ff77ac | 2173 | else |
c30dc700 | 2174 | sh64_compact_print_registers_info (gdbarch, file, frame, regnum, fpregs); |
55ff77ac CV |
2175 | } |
2176 | ||
c30dc700 CV |
2177 | static struct sh64_frame_cache * |
2178 | sh64_alloc_frame_cache (void) | |
2179 | { | |
2180 | struct sh64_frame_cache *cache; | |
2181 | int i; | |
2182 | ||
2183 | cache = FRAME_OBSTACK_ZALLOC (struct sh64_frame_cache); | |
2184 | ||
2185 | /* Base address. */ | |
2186 | cache->base = 0; | |
2187 | cache->saved_sp = 0; | |
2188 | cache->sp_offset = 0; | |
2189 | cache->pc = 0; | |
55ff77ac | 2190 | |
c30dc700 CV |
2191 | /* Frameless until proven otherwise. */ |
2192 | cache->uses_fp = 0; | |
55ff77ac | 2193 | |
c30dc700 CV |
2194 | /* Saved registers. We initialize these to -1 since zero is a valid |
2195 | offset (that's where fp is supposed to be stored). */ | |
2196 | for (i = 0; i < SIM_SH64_NR_REGS; i++) | |
2197 | { | |
2198 | cache->saved_regs[i] = -1; | |
2199 | } | |
2200 | ||
2201 | return cache; | |
2202 | } | |
2203 | ||
2204 | static struct sh64_frame_cache * | |
94afd7a6 | 2205 | sh64_frame_cache (struct frame_info *this_frame, void **this_cache) |
55ff77ac | 2206 | { |
58643501 | 2207 | struct gdbarch *gdbarch; |
c30dc700 CV |
2208 | struct sh64_frame_cache *cache; |
2209 | CORE_ADDR current_pc; | |
2210 | int i; | |
55ff77ac | 2211 | |
c30dc700 CV |
2212 | if (*this_cache) |
2213 | return *this_cache; | |
2214 | ||
94afd7a6 | 2215 | gdbarch = get_frame_arch (this_frame); |
c30dc700 CV |
2216 | cache = sh64_alloc_frame_cache (); |
2217 | *this_cache = cache; | |
2218 | ||
94afd7a6 | 2219 | current_pc = get_frame_pc (this_frame); |
c30dc700 CV |
2220 | cache->media_mode = pc_is_isa32 (current_pc); |
2221 | ||
2222 | /* In principle, for normal frames, fp holds the frame pointer, | |
2223 | which holds the base address for the current stack frame. | |
2224 | However, for functions that don't need it, the frame pointer is | |
2225 | optional. For these "frameless" functions the frame pointer is | |
c378eb4e | 2226 | actually the frame pointer of the calling frame. */ |
94afd7a6 | 2227 | cache->base = get_frame_register_unsigned (this_frame, MEDIA_FP_REGNUM); |
c30dc700 CV |
2228 | if (cache->base == 0) |
2229 | return cache; | |
2230 | ||
94afd7a6 | 2231 | cache->pc = get_frame_func (this_frame); |
c30dc700 | 2232 | if (cache->pc != 0) |
58643501 | 2233 | sh64_analyze_prologue (gdbarch, cache, cache->pc, current_pc); |
c30dc700 CV |
2234 | |
2235 | if (!cache->uses_fp) | |
55ff77ac | 2236 | { |
c30dc700 CV |
2237 | /* We didn't find a valid frame, which means that CACHE->base |
2238 | currently holds the frame pointer for our calling frame. If | |
2239 | we're at the start of a function, or somewhere half-way its | |
2240 | prologue, the function's frame probably hasn't been fully | |
2241 | setup yet. Try to reconstruct the base address for the stack | |
2242 | frame by looking at the stack pointer. For truly "frameless" | |
2243 | functions this might work too. */ | |
94afd7a6 UW |
2244 | cache->base = get_frame_register_unsigned |
2245 | (this_frame, gdbarch_sp_regnum (gdbarch)); | |
c30dc700 | 2246 | } |
55ff77ac | 2247 | |
c30dc700 CV |
2248 | /* Now that we have the base address for the stack frame we can |
2249 | calculate the value of sp in the calling frame. */ | |
2250 | cache->saved_sp = cache->base + cache->sp_offset; | |
55ff77ac | 2251 | |
c30dc700 CV |
2252 | /* Adjust all the saved registers such that they contain addresses |
2253 | instead of offsets. */ | |
2254 | for (i = 0; i < SIM_SH64_NR_REGS; i++) | |
2255 | if (cache->saved_regs[i] != -1) | |
2256 | cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i]; | |
55ff77ac | 2257 | |
c30dc700 CV |
2258 | return cache; |
2259 | } | |
55ff77ac | 2260 | |
94afd7a6 UW |
2261 | static struct value * |
2262 | sh64_frame_prev_register (struct frame_info *this_frame, | |
2263 | void **this_cache, int regnum) | |
c30dc700 | 2264 | { |
94afd7a6 UW |
2265 | struct sh64_frame_cache *cache = sh64_frame_cache (this_frame, this_cache); |
2266 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
e17a4113 | 2267 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
55ff77ac | 2268 | |
c30dc700 | 2269 | gdb_assert (regnum >= 0); |
55ff77ac | 2270 | |
58643501 | 2271 | if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp) |
94afd7a6 | 2272 | frame_unwind_got_constant (this_frame, regnum, cache->saved_sp); |
c30dc700 CV |
2273 | |
2274 | /* The PC of the previous frame is stored in the PR register of | |
2275 | the current frame. Frob regnum so that we pull the value from | |
2276 | the correct place. */ | |
58643501 | 2277 | if (regnum == gdbarch_pc_regnum (gdbarch)) |
c30dc700 CV |
2278 | regnum = PR_REGNUM; |
2279 | ||
2280 | if (regnum < SIM_SH64_NR_REGS && cache->saved_regs[regnum] != -1) | |
2281 | { | |
58643501 | 2282 | if (gdbarch_tdep (gdbarch)->sh_abi == SH_ABI_32 |
c30dc700 | 2283 | && (regnum == MEDIA_FP_REGNUM || regnum == PR_REGNUM)) |
c30dc700 | 2284 | { |
94afd7a6 | 2285 | CORE_ADDR val; |
e17a4113 UW |
2286 | val = read_memory_unsigned_integer (cache->saved_regs[regnum], |
2287 | 4, byte_order); | |
94afd7a6 | 2288 | return frame_unwind_got_constant (this_frame, regnum, val); |
c30dc700 | 2289 | } |
94afd7a6 UW |
2290 | |
2291 | return frame_unwind_got_memory (this_frame, regnum, | |
2292 | cache->saved_regs[regnum]); | |
55ff77ac CV |
2293 | } |
2294 | ||
94afd7a6 | 2295 | return frame_unwind_got_register (this_frame, regnum, regnum); |
55ff77ac | 2296 | } |
55ff77ac | 2297 | |
c30dc700 | 2298 | static void |
94afd7a6 | 2299 | sh64_frame_this_id (struct frame_info *this_frame, void **this_cache, |
c30dc700 CV |
2300 | struct frame_id *this_id) |
2301 | { | |
94afd7a6 | 2302 | struct sh64_frame_cache *cache = sh64_frame_cache (this_frame, this_cache); |
c30dc700 CV |
2303 | |
2304 | /* This marks the outermost frame. */ | |
2305 | if (cache->base == 0) | |
2306 | return; | |
2307 | ||
2308 | *this_id = frame_id_build (cache->saved_sp, cache->pc); | |
2309 | } | |
2310 | ||
2311 | static const struct frame_unwind sh64_frame_unwind = { | |
2312 | NORMAL_FRAME, | |
8fbca658 | 2313 | default_frame_unwind_stop_reason, |
c30dc700 | 2314 | sh64_frame_this_id, |
94afd7a6 UW |
2315 | sh64_frame_prev_register, |
2316 | NULL, | |
2317 | default_frame_sniffer | |
c30dc700 CV |
2318 | }; |
2319 | ||
c30dc700 CV |
2320 | static CORE_ADDR |
2321 | sh64_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
2322 | { | |
3e8c568d | 2323 | return frame_unwind_register_unsigned (next_frame, |
58643501 | 2324 | gdbarch_sp_regnum (gdbarch)); |
c30dc700 CV |
2325 | } |
2326 | ||
2327 | static CORE_ADDR | |
2328 | sh64_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
2329 | { | |
3e8c568d | 2330 | return frame_unwind_register_unsigned (next_frame, |
58643501 | 2331 | gdbarch_pc_regnum (gdbarch)); |
c30dc700 CV |
2332 | } |
2333 | ||
2334 | static struct frame_id | |
94afd7a6 | 2335 | sh64_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
c30dc700 | 2336 | { |
94afd7a6 UW |
2337 | CORE_ADDR sp = get_frame_register_unsigned (this_frame, |
2338 | gdbarch_sp_regnum (gdbarch)); | |
2339 | return frame_id_build (sp, get_frame_pc (this_frame)); | |
c30dc700 CV |
2340 | } |
2341 | ||
2342 | static CORE_ADDR | |
94afd7a6 | 2343 | sh64_frame_base_address (struct frame_info *this_frame, void **this_cache) |
c30dc700 | 2344 | { |
94afd7a6 | 2345 | struct sh64_frame_cache *cache = sh64_frame_cache (this_frame, this_cache); |
c30dc700 CV |
2346 | |
2347 | return cache->base; | |
2348 | } | |
2349 | ||
2350 | static const struct frame_base sh64_frame_base = { | |
2351 | &sh64_frame_unwind, | |
2352 | sh64_frame_base_address, | |
2353 | sh64_frame_base_address, | |
2354 | sh64_frame_base_address | |
2355 | }; | |
2356 | ||
55ff77ac CV |
2357 | |
2358 | struct gdbarch * | |
2359 | sh64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
2360 | { | |
55ff77ac CV |
2361 | struct gdbarch *gdbarch; |
2362 | struct gdbarch_tdep *tdep; | |
2363 | ||
2364 | /* If there is already a candidate, use it. */ | |
2365 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
2366 | if (arches != NULL) | |
2367 | return arches->gdbarch; | |
2368 | ||
2369 | /* None found, create a new architecture from the information | |
7bb11558 | 2370 | provided. */ |
70ba0933 | 2371 | tdep = XNEW (struct gdbarch_tdep); |
55ff77ac CV |
2372 | gdbarch = gdbarch_alloc (&info, tdep); |
2373 | ||
55ff77ac CV |
2374 | /* Determine the ABI */ |
2375 | if (info.abfd && bfd_get_arch_size (info.abfd) == 64) | |
2376 | { | |
7bb11558 | 2377 | /* If the ABI is the 64-bit one, it can only be sh-media. */ |
55ff77ac CV |
2378 | tdep->sh_abi = SH_ABI_64; |
2379 | set_gdbarch_ptr_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
2380 | set_gdbarch_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
2381 | } | |
2382 | else | |
2383 | { | |
2384 | /* If the ABI is the 32-bit one it could be either media or | |
7bb11558 | 2385 | compact. */ |
55ff77ac CV |
2386 | tdep->sh_abi = SH_ABI_32; |
2387 | set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
2388 | set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
2389 | } | |
2390 | ||
2391 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); | |
2392 | set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
c30dc700 | 2393 | set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
55ff77ac CV |
2394 | set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); |
2395 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
2396 | set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
2397 | set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
2398 | ||
c30dc700 CV |
2399 | /* The number of real registers is the same whether we are in |
2400 | ISA16(compact) or ISA32(media). */ | |
2401 | set_gdbarch_num_regs (gdbarch, SIM_SH64_NR_REGS); | |
55ff77ac | 2402 | set_gdbarch_sp_regnum (gdbarch, 15); |
c30dc700 CV |
2403 | set_gdbarch_pc_regnum (gdbarch, 64); |
2404 | set_gdbarch_fp0_regnum (gdbarch, SIM_SH64_FR0_REGNUM); | |
2405 | set_gdbarch_num_pseudo_regs (gdbarch, NUM_PSEUDO_REGS_SH_MEDIA | |
2406 | + NUM_PSEUDO_REGS_SH_COMPACT); | |
55ff77ac | 2407 | |
c30dc700 CV |
2408 | set_gdbarch_register_name (gdbarch, sh64_register_name); |
2409 | set_gdbarch_register_type (gdbarch, sh64_register_type); | |
2410 | ||
2411 | set_gdbarch_pseudo_register_read (gdbarch, sh64_pseudo_register_read); | |
2412 | set_gdbarch_pseudo_register_write (gdbarch, sh64_pseudo_register_write); | |
2413 | ||
2414 | set_gdbarch_breakpoint_from_pc (gdbarch, sh64_breakpoint_from_pc); | |
2415 | ||
9dae60cc | 2416 | set_gdbarch_print_insn (gdbarch, print_insn_sh); |
55ff77ac CV |
2417 | set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno); |
2418 | ||
c30dc700 | 2419 | set_gdbarch_return_value (gdbarch, sh64_return_value); |
55ff77ac | 2420 | |
c30dc700 CV |
2421 | set_gdbarch_skip_prologue (gdbarch, sh64_skip_prologue); |
2422 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
55ff77ac | 2423 | |
c30dc700 | 2424 | set_gdbarch_push_dummy_call (gdbarch, sh64_push_dummy_call); |
55ff77ac | 2425 | |
c30dc700 | 2426 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); |
55ff77ac | 2427 | |
c30dc700 CV |
2428 | set_gdbarch_frame_align (gdbarch, sh64_frame_align); |
2429 | set_gdbarch_unwind_sp (gdbarch, sh64_unwind_sp); | |
2430 | set_gdbarch_unwind_pc (gdbarch, sh64_unwind_pc); | |
94afd7a6 | 2431 | set_gdbarch_dummy_id (gdbarch, sh64_dummy_id); |
c30dc700 | 2432 | frame_base_set_default (gdbarch, &sh64_frame_base); |
55ff77ac | 2433 | |
c30dc700 | 2434 | set_gdbarch_print_registers_info (gdbarch, sh64_print_registers_info); |
55ff77ac | 2435 | |
55ff77ac CV |
2436 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
2437 | sh64_elf_make_msymbol_special); | |
2438 | ||
2439 | /* Hook in ABI-specific overrides, if they have been registered. */ | |
2440 | gdbarch_init_osabi (info, gdbarch); | |
2441 | ||
94afd7a6 UW |
2442 | dwarf2_append_unwinders (gdbarch); |
2443 | frame_unwind_append_unwinder (gdbarch, &sh64_frame_unwind); | |
c30dc700 | 2444 | |
55ff77ac CV |
2445 | return gdbarch; |
2446 | } |