Commit | Line | Data |
---|---|---|
85a453d5 | 1 | /* Target-dependent code for Renesas Super-H, for GDB. |
cf5b2f1b | 2 | |
61baf725 | 3 | Copyright (C) 1993-2017 Free Software Foundation, Inc. |
55ff77ac CV |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
55ff77ac CV |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
55ff77ac | 19 | |
c378eb4e MS |
20 | /* Contributed by Steve Chamberlain |
21 | sac@cygnus.com. */ | |
55ff77ac CV |
22 | |
23 | #include "defs.h" | |
24 | #include "frame.h" | |
c30dc700 CV |
25 | #include "frame-base.h" |
26 | #include "frame-unwind.h" | |
27 | #include "dwarf2-frame.h" | |
55ff77ac | 28 | #include "symtab.h" |
55ff77ac CV |
29 | #include "gdbtypes.h" |
30 | #include "gdbcmd.h" | |
31 | #include "gdbcore.h" | |
32 | #include "value.h" | |
33 | #include "dis-asm.h" | |
34 | #include "inferior.h" | |
55ff77ac | 35 | #include "arch-utils.h" |
55ff77ac | 36 | #include "regcache.h" |
55ff77ac | 37 | #include "osabi.h" |
79a45b7d | 38 | #include "valprint.h" |
55ff77ac CV |
39 | |
40 | #include "elf-bfd.h" | |
55ff77ac CV |
41 | |
42 | /* sh flags */ | |
43 | #include "elf/sh.h" | |
c378eb4e | 44 | /* Register numbers shared with the simulator. */ |
55ff77ac | 45 | #include "gdb/sim-sh.h" |
d8ca156b | 46 | #include "language.h" |
04dcf5fa | 47 | #include "sh64-tdep.h" |
325fac50 | 48 | #include <algorithm> |
55ff77ac | 49 | |
7bb11558 | 50 | /* Information that is dependent on the processor variant. */ |
55ff77ac CV |
51 | enum sh_abi |
52 | { | |
53 | SH_ABI_UNKNOWN, | |
54 | SH_ABI_32, | |
55 | SH_ABI_64 | |
56 | }; | |
57 | ||
58 | struct gdbarch_tdep | |
59 | { | |
60 | enum sh_abi sh_abi; | |
96a5a1d3 UW |
61 | /* ISA-specific data types. */ |
62 | struct type *sh_littlebyte_bigword_type; | |
55ff77ac CV |
63 | }; |
64 | ||
96a5a1d3 UW |
65 | struct type * |
66 | sh64_littlebyte_bigword_type (struct gdbarch *gdbarch) | |
67 | { | |
68 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
69 | ||
70 | if (tdep->sh_littlebyte_bigword_type == NULL) | |
71 | tdep->sh_littlebyte_bigword_type | |
72 | = arch_float_type (gdbarch, -1, "builtin_type_sh_littlebyte_bigword", | |
73 | floatformats_ieee_double_littlebyte_bigword); | |
74 | ||
75 | return tdep->sh_littlebyte_bigword_type; | |
76 | } | |
77 | ||
c30dc700 CV |
78 | struct sh64_frame_cache |
79 | { | |
80 | /* Base address. */ | |
81 | CORE_ADDR base; | |
82 | LONGEST sp_offset; | |
83 | CORE_ADDR pc; | |
84 | ||
c378eb4e | 85 | /* Flag showing that a frame has been created in the prologue code. */ |
c30dc700 CV |
86 | int uses_fp; |
87 | ||
88 | int media_mode; | |
89 | ||
90 | /* Saved registers. */ | |
91 | CORE_ADDR saved_regs[SIM_SH64_NR_REGS]; | |
92 | CORE_ADDR saved_sp; | |
93 | }; | |
94 | ||
55ff77ac CV |
95 | /* Registers of SH5 */ |
96 | enum | |
97 | { | |
98 | R0_REGNUM = 0, | |
99 | DEFAULT_RETURN_REGNUM = 2, | |
100 | STRUCT_RETURN_REGNUM = 2, | |
101 | ARG0_REGNUM = 2, | |
102 | ARGLAST_REGNUM = 9, | |
103 | FLOAT_ARGLAST_REGNUM = 11, | |
c30dc700 | 104 | MEDIA_FP_REGNUM = 14, |
55ff77ac CV |
105 | PR_REGNUM = 18, |
106 | SR_REGNUM = 65, | |
107 | DR0_REGNUM = 141, | |
108 | DR_LAST_REGNUM = 172, | |
109 | /* FPP stands for Floating Point Pair, to avoid confusion with | |
3e8c568d | 110 | GDB's gdbarch_fp0_regnum, which is the number of the first Floating |
c378eb4e | 111 | point register. Unfortunately on the sh5, the floating point |
7bb11558 | 112 | registers are called FR, and the floating point pairs are called FP. */ |
55ff77ac CV |
113 | FPP0_REGNUM = 173, |
114 | FPP_LAST_REGNUM = 204, | |
115 | FV0_REGNUM = 205, | |
116 | FV_LAST_REGNUM = 220, | |
117 | R0_C_REGNUM = 221, | |
118 | R_LAST_C_REGNUM = 236, | |
119 | PC_C_REGNUM = 237, | |
120 | GBR_C_REGNUM = 238, | |
121 | MACH_C_REGNUM = 239, | |
122 | MACL_C_REGNUM = 240, | |
123 | PR_C_REGNUM = 241, | |
124 | T_C_REGNUM = 242, | |
125 | FPSCR_C_REGNUM = 243, | |
126 | FPUL_C_REGNUM = 244, | |
127 | FP0_C_REGNUM = 245, | |
128 | FP_LAST_C_REGNUM = 260, | |
129 | DR0_C_REGNUM = 261, | |
130 | DR_LAST_C_REGNUM = 268, | |
131 | FV0_C_REGNUM = 269, | |
132 | FV_LAST_C_REGNUM = 272, | |
133 | FPSCR_REGNUM = SIM_SH64_FPCSR_REGNUM, | |
134 | SSR_REGNUM = SIM_SH64_SSR_REGNUM, | |
135 | SPC_REGNUM = SIM_SH64_SPC_REGNUM, | |
136 | TR7_REGNUM = SIM_SH64_TR0_REGNUM + 7, | |
137 | FP_LAST_REGNUM = SIM_SH64_FR0_REGNUM + SIM_SH64_NR_FP_REGS - 1 | |
138 | }; | |
139 | ||
55ff77ac | 140 | static const char * |
d93859e2 | 141 | sh64_register_name (struct gdbarch *gdbarch, int reg_nr) |
55ff77ac | 142 | { |
a121b7c1 | 143 | static const char *register_names[] = |
55ff77ac CV |
144 | { |
145 | /* SH MEDIA MODE (ISA 32) */ | |
146 | /* general registers (64-bit) 0-63 */ | |
147 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
148 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
149 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
150 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", | |
151 | "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", | |
152 | "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", | |
153 | "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", | |
154 | "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", | |
155 | ||
156 | /* pc (64-bit) 64 */ | |
157 | "pc", | |
158 | ||
159 | /* status reg., saved status reg., saved pc reg. (64-bit) 65-67 */ | |
160 | "sr", "ssr", "spc", | |
161 | ||
c378eb4e | 162 | /* target registers (64-bit) 68-75 */ |
55ff77ac CV |
163 | "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", |
164 | ||
165 | /* floating point state control register (32-bit) 76 */ | |
166 | "fpscr", | |
167 | ||
c378eb4e | 168 | /* single precision floating point registers (32-bit) 77-140 */ |
55ff77ac CV |
169 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", |
170 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
171 | "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", | |
172 | "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", | |
173 | "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", | |
174 | "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", | |
175 | "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", | |
176 | "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", | |
177 | ||
178 | /* double precision registers (pseudo) 141-172 */ | |
179 | "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", | |
180 | "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", | |
181 | "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", | |
182 | "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62", | |
183 | ||
c378eb4e | 184 | /* floating point pairs (pseudo) 173-204 */ |
55ff77ac CV |
185 | "fp0", "fp2", "fp4", "fp6", "fp8", "fp10", "fp12", "fp14", |
186 | "fp16", "fp18", "fp20", "fp22", "fp24", "fp26", "fp28", "fp30", | |
187 | "fp32", "fp34", "fp36", "fp38", "fp40", "fp42", "fp44", "fp46", | |
188 | "fp48", "fp50", "fp52", "fp54", "fp56", "fp58", "fp60", "fp62", | |
189 | ||
c378eb4e | 190 | /* floating point vectors (4 floating point regs) (pseudo) 205-220 */ |
55ff77ac CV |
191 | "fv0", "fv4", "fv8", "fv12", "fv16", "fv20", "fv24", "fv28", |
192 | "fv32", "fv36", "fv40", "fv44", "fv48", "fv52", "fv56", "fv60", | |
193 | ||
c378eb4e | 194 | /* SH COMPACT MODE (ISA 16) (all pseudo) 221-272 */ |
55ff77ac CV |
195 | "r0_c", "r1_c", "r2_c", "r3_c", "r4_c", "r5_c", "r6_c", "r7_c", |
196 | "r8_c", "r9_c", "r10_c", "r11_c", "r12_c", "r13_c", "r14_c", "r15_c", | |
197 | "pc_c", | |
198 | "gbr_c", "mach_c", "macl_c", "pr_c", "t_c", | |
199 | "fpscr_c", "fpul_c", | |
c378eb4e MS |
200 | "fr0_c", "fr1_c", "fr2_c", "fr3_c", |
201 | "fr4_c", "fr5_c", "fr6_c", "fr7_c", | |
202 | "fr8_c", "fr9_c", "fr10_c", "fr11_c", | |
203 | "fr12_c", "fr13_c", "fr14_c", "fr15_c", | |
204 | "dr0_c", "dr2_c", "dr4_c", "dr6_c", | |
205 | "dr8_c", "dr10_c", "dr12_c", "dr14_c", | |
55ff77ac | 206 | "fv0_c", "fv4_c", "fv8_c", "fv12_c", |
c378eb4e | 207 | /* FIXME!!!! XF0 XF15, XD0 XD14 ????? */ |
55ff77ac CV |
208 | }; |
209 | ||
210 | if (reg_nr < 0) | |
211 | return NULL; | |
212 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
213 | return NULL; | |
214 | return register_names[reg_nr]; | |
215 | } | |
216 | ||
217 | #define NUM_PSEUDO_REGS_SH_MEDIA 80 | |
218 | #define NUM_PSEUDO_REGS_SH_COMPACT 51 | |
219 | ||
220 | /* Macros and functions for setting and testing a bit in a minimal | |
221 | symbol that marks it as 32-bit function. The MSB of the minimal | |
f594e5e9 | 222 | symbol's "info" field is used for this purpose. |
55ff77ac | 223 | |
95f1da47 UW |
224 | gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special", |
225 | i.e. refers to a 32-bit function, and sets a "special" bit in a | |
55ff77ac | 226 | minimal symbol to mark it as a 32-bit function |
f594e5e9 | 227 | MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */ |
55ff77ac CV |
228 | |
229 | #define MSYMBOL_IS_SPECIAL(msym) \ | |
b887350f | 230 | MSYMBOL_TARGET_FLAG_1 (msym) |
55ff77ac CV |
231 | |
232 | static void | |
233 | sh64_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym) | |
234 | { | |
235 | if (msym == NULL) | |
236 | return; | |
237 | ||
238 | if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_SH5_ISA32) | |
239 | { | |
b887350f | 240 | MSYMBOL_TARGET_FLAG_1 (msym) = 1; |
77e371c0 | 241 | SET_MSYMBOL_VALUE_ADDRESS (msym, MSYMBOL_VALUE_RAW_ADDRESS (msym) | 1); |
55ff77ac CV |
242 | } |
243 | } | |
244 | ||
245 | /* ISA32 (shmedia) function addresses are odd (bit 0 is set). Here | |
246 | are some macros to test, set, or clear bit 0 of addresses. */ | |
247 | #define IS_ISA32_ADDR(addr) ((addr) & 1) | |
248 | #define MAKE_ISA32_ADDR(addr) ((addr) | 1) | |
249 | #define UNMAKE_ISA32_ADDR(addr) ((addr) & ~1) | |
250 | ||
251 | static int | |
252 | pc_is_isa32 (bfd_vma memaddr) | |
253 | { | |
7cbd4a93 | 254 | struct bound_minimal_symbol sym; |
55ff77ac CV |
255 | |
256 | /* If bit 0 of the address is set, assume this is a | |
7bb11558 | 257 | ISA32 (shmedia) address. */ |
55ff77ac CV |
258 | if (IS_ISA32_ADDR (memaddr)) |
259 | return 1; | |
260 | ||
261 | /* A flag indicating that this is a ISA32 function is stored by elfread.c in | |
262 | the high bit of the info field. Use this to decide if the function is | |
263 | ISA16 or ISA32. */ | |
264 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
7cbd4a93 TT |
265 | if (sym.minsym) |
266 | return MSYMBOL_IS_SPECIAL (sym.minsym); | |
55ff77ac CV |
267 | else |
268 | return 0; | |
269 | } | |
270 | ||
d19280ad YQ |
271 | static int |
272 | sh64_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr) | |
55ff77ac | 273 | { |
d19280ad YQ |
274 | if (pc_is_isa32 (*pcptr)) |
275 | { | |
276 | *pcptr = UNMAKE_ISA32_ADDR (*pcptr); | |
277 | return 4; | |
278 | } | |
279 | else | |
280 | return 2; | |
281 | } | |
282 | ||
283 | static const gdb_byte * | |
284 | sh64_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size) | |
285 | { | |
286 | *size = kind; | |
287 | ||
288 | /* The BRK instruction for shmedia is | |
55ff77ac CV |
289 | 01101111 11110101 11111111 11110000 |
290 | which translates in big endian mode to 0x6f, 0xf5, 0xff, 0xf0 | |
291 | and in little endian mode to 0xf0, 0xff, 0xf5, 0x6f */ | |
292 | ||
293 | /* The BRK instruction for shcompact is | |
294 | 00000000 00111011 | |
295 | which translates in big endian mode to 0x0, 0x3b | |
c378eb4e | 296 | and in little endian mode to 0x3b, 0x0 */ |
55ff77ac | 297 | |
d19280ad | 298 | if (kind == 4) |
55ff77ac | 299 | { |
d19280ad YQ |
300 | static unsigned char big_breakpoint_media[] = { |
301 | 0x6f, 0xf5, 0xff, 0xf0 | |
302 | }; | |
303 | static unsigned char little_breakpoint_media[] = { | |
304 | 0xf0, 0xff, 0xf5, 0x6f | |
305 | }; | |
306 | ||
307 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
308 | return big_breakpoint_media; | |
55ff77ac | 309 | else |
d19280ad | 310 | return little_breakpoint_media; |
55ff77ac CV |
311 | } |
312 | else | |
313 | { | |
d19280ad YQ |
314 | static unsigned char big_breakpoint_compact[] = {0x0, 0x3b}; |
315 | static unsigned char little_breakpoint_compact[] = {0x3b, 0x0}; | |
316 | ||
317 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
318 | return big_breakpoint_compact; | |
55ff77ac | 319 | else |
d19280ad | 320 | return little_breakpoint_compact; |
55ff77ac CV |
321 | } |
322 | } | |
323 | ||
324 | /* Prologue looks like | |
325 | [mov.l <regs>,@-r15]... | |
326 | [sts.l pr,@-r15] | |
327 | [mov.l r14,@-r15] | |
328 | [mov r15,r14] | |
329 | ||
330 | Actually it can be more complicated than this. For instance, with | |
331 | newer gcc's: | |
332 | ||
333 | mov.l r14,@-r15 | |
334 | add #-12,r15 | |
335 | mov r15,r14 | |
336 | mov r4,r1 | |
337 | mov r5,r2 | |
338 | mov.l r6,@(4,r14) | |
339 | mov.l r7,@(8,r14) | |
340 | mov.b r1,@r14 | |
341 | mov r14,r1 | |
342 | mov r14,r1 | |
343 | add #2,r1 | |
344 | mov.w r2,@r1 | |
345 | ||
346 | */ | |
347 | ||
348 | /* PTABS/L Rn, TRa 0110101111110001nnnnnnl00aaa0000 | |
349 | with l=1 and n = 18 0110101111110001010010100aaa0000 */ | |
350 | #define IS_PTABSL_R18(x) (((x) & 0xffffff8f) == 0x6bf14a00) | |
351 | ||
352 | /* STS.L PR,@-r0 0100000000100010 | |
353 | r0-4-->r0, PR-->(r0) */ | |
354 | #define IS_STS_R0(x) ((x) == 0x4022) | |
355 | ||
356 | /* STS PR, Rm 0000mmmm00101010 | |
357 | PR-->Rm */ | |
358 | #define IS_STS_PR(x) (((x) & 0xf0ff) == 0x2a) | |
359 | ||
360 | /* MOV.L Rm,@(disp,r15) 00011111mmmmdddd | |
361 | Rm-->(dispx4+r15) */ | |
362 | #define IS_MOV_TO_R15(x) (((x) & 0xff00) == 0x1f00) | |
363 | ||
364 | /* MOV.L R14,@(disp,r15) 000111111110dddd | |
365 | R14-->(dispx4+r15) */ | |
366 | #define IS_MOV_R14(x) (((x) & 0xfff0) == 0x1fe0) | |
367 | ||
368 | /* ST.Q R14, disp, R18 101011001110dddddddddd0100100000 | |
369 | R18-->(dispx8+R14) */ | |
370 | #define IS_STQ_R18_R14(x) (((x) & 0xfff003ff) == 0xace00120) | |
371 | ||
372 | /* ST.Q R15, disp, R18 101011001111dddddddddd0100100000 | |
373 | R18-->(dispx8+R15) */ | |
374 | #define IS_STQ_R18_R15(x) (((x) & 0xfff003ff) == 0xacf00120) | |
375 | ||
376 | /* ST.L R15, disp, R18 101010001111dddddddddd0100100000 | |
377 | R18-->(dispx4+R15) */ | |
378 | #define IS_STL_R18_R15(x) (((x) & 0xfff003ff) == 0xa8f00120) | |
379 | ||
380 | /* ST.Q R15, disp, R14 1010 1100 1111 dddd dddd dd00 1110 0000 | |
381 | R14-->(dispx8+R15) */ | |
382 | #define IS_STQ_R14_R15(x) (((x) & 0xfff003ff) == 0xacf000e0) | |
383 | ||
384 | /* ST.L R15, disp, R14 1010 1000 1111 dddd dddd dd00 1110 0000 | |
385 | R14-->(dispx4+R15) */ | |
386 | #define IS_STL_R14_R15(x) (((x) & 0xfff003ff) == 0xa8f000e0) | |
387 | ||
388 | /* ADDI.L R15,imm,R15 1101 0100 1111 ssss ssss ss00 1111 0000 | |
389 | R15 + imm --> R15 */ | |
390 | #define IS_ADDIL_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd4f000f0) | |
391 | ||
392 | /* ADDI R15,imm,R15 1101 0000 1111 ssss ssss ss00 1111 0000 | |
393 | R15 + imm --> R15 */ | |
394 | #define IS_ADDI_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd0f000f0) | |
395 | ||
396 | /* ADD.L R15,R63,R14 0000 0000 1111 1000 1111 1100 1110 0000 | |
397 | R15 + R63 --> R14 */ | |
398 | #define IS_ADDL_SP_FP_MEDIA(x) ((x) == 0x00f8fce0) | |
399 | ||
400 | /* ADD R15,R63,R14 0000 0000 1111 1001 1111 1100 1110 0000 | |
401 | R15 + R63 --> R14 */ | |
402 | #define IS_ADD_SP_FP_MEDIA(x) ((x) == 0x00f9fce0) | |
403 | ||
c378eb4e MS |
404 | #define IS_MOV_SP_FP_MEDIA(x) \ |
405 | (IS_ADDL_SP_FP_MEDIA(x) || IS_ADD_SP_FP_MEDIA(x)) | |
55ff77ac CV |
406 | |
407 | /* MOV #imm, R0 1110 0000 ssss ssss | |
408 | #imm-->R0 */ | |
409 | #define IS_MOV_R0(x) (((x) & 0xff00) == 0xe000) | |
410 | ||
411 | /* MOV.L @(disp,PC), R0 1101 0000 iiii iiii */ | |
412 | #define IS_MOVL_R0(x) (((x) & 0xff00) == 0xd000) | |
413 | ||
414 | /* ADD r15,r0 0011 0000 1111 1100 | |
415 | r15+r0-->r0 */ | |
416 | #define IS_ADD_SP_R0(x) ((x) == 0x30fc) | |
417 | ||
418 | /* MOV.L R14 @-R0 0010 0000 1110 0110 | |
419 | R14-->(R0-4), R0-4-->R0 */ | |
420 | #define IS_MOV_R14_R0(x) ((x) == 0x20e6) | |
421 | ||
422 | /* ADD Rm,R63,Rn Rm+R63-->Rn 0000 00mm mmmm 1001 1111 11nn nnnn 0000 | |
7bb11558 | 423 | where Rm is one of r2-r9 which are the argument registers. */ |
c378eb4e | 424 | /* FIXME: Recognize the float and double register moves too! */ |
55ff77ac | 425 | #define IS_MEDIA_IND_ARG_MOV(x) \ |
c378eb4e MS |
426 | ((((x) & 0xfc0ffc0f) == 0x0009fc00) \ |
427 | && (((x) & 0x03f00000) >= 0x00200000 \ | |
428 | && ((x) & 0x03f00000) <= 0x00900000)) | |
55ff77ac CV |
429 | |
430 | /* ST.Q Rn,0,Rm Rm-->Rn+0 1010 11nn nnnn 0000 0000 00mm mmmm 0000 | |
431 | or ST.L Rn,0,Rm Rm-->Rn+0 1010 10nn nnnn 0000 0000 00mm mmmm 0000 | |
7bb11558 | 432 | where Rm is one of r2-r9 which are the argument registers. */ |
55ff77ac CV |
433 | #define IS_MEDIA_ARG_MOV(x) \ |
434 | (((((x) & 0xfc0ffc0f) == 0xac000000) || (((x) & 0xfc0ffc0f) == 0xa8000000)) \ | |
435 | && (((x) & 0x000003f0) >= 0x00000020 && ((x) & 0x000003f0) <= 0x00000090)) | |
436 | ||
c378eb4e MS |
437 | /* ST.B R14,0,Rn Rn-->(R14+0) 1010 0000 1110 0000 0000 00nn nnnn 0000 */ |
438 | /* ST.W R14,0,Rn Rn-->(R14+0) 1010 0100 1110 0000 0000 00nn nnnn 0000 */ | |
439 | /* ST.L R14,0,Rn Rn-->(R14+0) 1010 1000 1110 0000 0000 00nn nnnn 0000 */ | |
440 | /* FST.S R14,0,FRn Rn-->(R14+0) 1011 0100 1110 0000 0000 00nn nnnn 0000 */ | |
441 | /* FST.D R14,0,DRn Rn-->(R14+0) 1011 1100 1110 0000 0000 00nn nnnn 0000 */ | |
55ff77ac CV |
442 | #define IS_MEDIA_MOV_TO_R14(x) \ |
443 | ((((x) & 0xfffffc0f) == 0xa0e00000) \ | |
444 | || (((x) & 0xfffffc0f) == 0xa4e00000) \ | |
445 | || (((x) & 0xfffffc0f) == 0xa8e00000) \ | |
446 | || (((x) & 0xfffffc0f) == 0xb4e00000) \ | |
447 | || (((x) & 0xfffffc0f) == 0xbce00000)) | |
448 | ||
449 | /* MOV Rm, Rn Rm-->Rn 0110 nnnn mmmm 0011 | |
450 | where Rm is r2-r9 */ | |
451 | #define IS_COMPACT_IND_ARG_MOV(x) \ | |
c378eb4e MS |
452 | ((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0020) \ |
453 | && (((x) & 0x00f0) <= 0x0090)) | |
55ff77ac CV |
454 | |
455 | /* compact direct arg move! | |
456 | MOV.L Rn, @r14 0010 1110 mmmm 0010 */ | |
457 | #define IS_COMPACT_ARG_MOV(x) \ | |
c378eb4e MS |
458 | (((((x) & 0xff0f) == 0x2e02) && (((x) & 0x00f0) >= 0x0020) \ |
459 | && ((x) & 0x00f0) <= 0x0090)) | |
55ff77ac CV |
460 | |
461 | /* MOV.B Rm, @R14 0010 1110 mmmm 0000 | |
462 | MOV.W Rm, @R14 0010 1110 mmmm 0001 */ | |
463 | #define IS_COMPACT_MOV_TO_R14(x) \ | |
464 | ((((x) & 0xff0f) == 0x2e00) || (((x) & 0xff0f) == 0x2e01)) | |
465 | ||
466 | #define IS_JSR_R0(x) ((x) == 0x400b) | |
467 | #define IS_NOP(x) ((x) == 0x0009) | |
468 | ||
469 | ||
470 | /* MOV r15,r14 0110111011110011 | |
471 | r15-->r14 */ | |
472 | #define IS_MOV_SP_FP(x) ((x) == 0x6ef3) | |
473 | ||
474 | /* ADD #imm,r15 01111111iiiiiiii | |
475 | r15+imm-->r15 */ | |
476 | #define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00) | |
477 | ||
c378eb4e | 478 | /* Skip any prologue before the guts of a function. */ |
55ff77ac | 479 | |
7bb11558 MS |
480 | /* Skip the prologue using the debug information. If this fails we'll |
481 | fall back on the 'guess' method below. */ | |
55ff77ac CV |
482 | static CORE_ADDR |
483 | after_prologue (CORE_ADDR pc) | |
484 | { | |
485 | struct symtab_and_line sal; | |
486 | CORE_ADDR func_addr, func_end; | |
487 | ||
488 | /* If we can not find the symbol in the partial symbol table, then | |
489 | there is no hope we can determine the function's start address | |
490 | with this code. */ | |
491 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
492 | return 0; | |
493 | ||
c30dc700 | 494 | |
55ff77ac CV |
495 | /* Get the line associated with FUNC_ADDR. */ |
496 | sal = find_pc_line (func_addr, 0); | |
497 | ||
498 | /* There are only two cases to consider. First, the end of the source line | |
499 | is within the function bounds. In that case we return the end of the | |
500 | source line. Second is the end of the source line extends beyond the | |
501 | bounds of the current function. We need to use the slow code to | |
502 | examine instructions in that case. */ | |
503 | if (sal.end < func_end) | |
504 | return sal.end; | |
505 | else | |
506 | return 0; | |
507 | } | |
508 | ||
509 | static CORE_ADDR | |
e17a4113 UW |
510 | look_for_args_moves (struct gdbarch *gdbarch, |
511 | CORE_ADDR start_pc, int media_mode) | |
55ff77ac | 512 | { |
e17a4113 | 513 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
55ff77ac CV |
514 | CORE_ADDR here, end; |
515 | int w; | |
516 | int insn_size = (media_mode ? 4 : 2); | |
517 | ||
518 | for (here = start_pc, end = start_pc + (insn_size * 28); here < end;) | |
519 | { | |
520 | if (media_mode) | |
521 | { | |
e17a4113 UW |
522 | w = read_memory_integer (UNMAKE_ISA32_ADDR (here), |
523 | insn_size, byte_order); | |
55ff77ac CV |
524 | here += insn_size; |
525 | if (IS_MEDIA_IND_ARG_MOV (w)) | |
526 | { | |
527 | /* This must be followed by a store to r14, so the argument | |
c378eb4e | 528 | is where the debug info says it is. This can happen after |
7bb11558 | 529 | the SP has been saved, unfortunately. */ |
55ff77ac CV |
530 | |
531 | int next_insn = read_memory_integer (UNMAKE_ISA32_ADDR (here), | |
e17a4113 | 532 | insn_size, byte_order); |
55ff77ac CV |
533 | here += insn_size; |
534 | if (IS_MEDIA_MOV_TO_R14 (next_insn)) | |
535 | start_pc = here; | |
536 | } | |
537 | else if (IS_MEDIA_ARG_MOV (w)) | |
538 | { | |
7bb11558 | 539 | /* These instructions store directly the argument in r14. */ |
55ff77ac CV |
540 | start_pc = here; |
541 | } | |
542 | else | |
543 | break; | |
544 | } | |
545 | else | |
546 | { | |
e17a4113 | 547 | w = read_memory_integer (here, insn_size, byte_order); |
55ff77ac CV |
548 | w = w & 0xffff; |
549 | here += insn_size; | |
550 | if (IS_COMPACT_IND_ARG_MOV (w)) | |
551 | { | |
552 | /* This must be followed by a store to r14, so the argument | |
c378eb4e | 553 | is where the debug info says it is. This can happen after |
7bb11558 | 554 | the SP has been saved, unfortunately. */ |
55ff77ac | 555 | |
e17a4113 UW |
556 | int next_insn = 0xffff & read_memory_integer (here, insn_size, |
557 | byte_order); | |
55ff77ac CV |
558 | here += insn_size; |
559 | if (IS_COMPACT_MOV_TO_R14 (next_insn)) | |
560 | start_pc = here; | |
561 | } | |
562 | else if (IS_COMPACT_ARG_MOV (w)) | |
563 | { | |
7bb11558 | 564 | /* These instructions store directly the argument in r14. */ |
55ff77ac CV |
565 | start_pc = here; |
566 | } | |
567 | else if (IS_MOVL_R0 (w)) | |
568 | { | |
569 | /* There is a function that gcc calls to get the arguments | |
c378eb4e | 570 | passed correctly to the function. Only after this |
55ff77ac | 571 | function call the arguments will be found at the place |
c378eb4e | 572 | where they are supposed to be. This happens in case the |
55ff77ac CV |
573 | argument has to be stored into a 64-bit register (for |
574 | instance doubles, long longs). SHcompact doesn't have | |
575 | access to the full 64-bits, so we store the register in | |
576 | stack slot and store the address of the stack slot in | |
577 | the register, then do a call through a wrapper that | |
578 | loads the memory value into the register. A SHcompact | |
579 | callee calls an argument decoder | |
580 | (GCC_shcompact_incoming_args) that stores the 64-bit | |
581 | value in a stack slot and stores the address of the | |
582 | stack slot in the register. GCC thinks the argument is | |
583 | just passed by transparent reference, but this is only | |
c378eb4e | 584 | true after the argument decoder is called. Such a call |
7bb11558 | 585 | needs to be considered part of the prologue. */ |
55ff77ac CV |
586 | |
587 | /* This must be followed by a JSR @r0 instruction and by | |
c378eb4e | 588 | a NOP instruction. After these, the prologue is over! */ |
55ff77ac | 589 | |
e17a4113 UW |
590 | int next_insn = 0xffff & read_memory_integer (here, insn_size, |
591 | byte_order); | |
55ff77ac CV |
592 | here += insn_size; |
593 | if (IS_JSR_R0 (next_insn)) | |
594 | { | |
e17a4113 UW |
595 | next_insn = 0xffff & read_memory_integer (here, insn_size, |
596 | byte_order); | |
55ff77ac CV |
597 | here += insn_size; |
598 | ||
599 | if (IS_NOP (next_insn)) | |
600 | start_pc = here; | |
601 | } | |
602 | } | |
603 | else | |
604 | break; | |
605 | } | |
606 | } | |
607 | ||
608 | return start_pc; | |
609 | } | |
610 | ||
611 | static CORE_ADDR | |
e17a4113 | 612 | sh64_skip_prologue_hard_way (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
55ff77ac | 613 | { |
e17a4113 | 614 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
55ff77ac CV |
615 | CORE_ADDR here, end; |
616 | int updated_fp = 0; | |
617 | int insn_size = 4; | |
618 | int media_mode = 1; | |
619 | ||
620 | if (!start_pc) | |
621 | return 0; | |
622 | ||
623 | if (pc_is_isa32 (start_pc) == 0) | |
624 | { | |
625 | insn_size = 2; | |
626 | media_mode = 0; | |
627 | } | |
628 | ||
629 | for (here = start_pc, end = start_pc + (insn_size * 28); here < end;) | |
630 | { | |
631 | ||
632 | if (media_mode) | |
633 | { | |
e17a4113 UW |
634 | int w = read_memory_integer (UNMAKE_ISA32_ADDR (here), |
635 | insn_size, byte_order); | |
55ff77ac CV |
636 | here += insn_size; |
637 | if (IS_STQ_R18_R14 (w) || IS_STQ_R18_R15 (w) || IS_STQ_R14_R15 (w) | |
638 | || IS_STL_R14_R15 (w) || IS_STL_R18_R15 (w) | |
c378eb4e MS |
639 | || IS_ADDIL_SP_MEDIA (w) || IS_ADDI_SP_MEDIA (w) |
640 | || IS_PTABSL_R18 (w)) | |
55ff77ac CV |
641 | { |
642 | start_pc = here; | |
643 | } | |
644 | else if (IS_MOV_SP_FP (w) || IS_MOV_SP_FP_MEDIA(w)) | |
645 | { | |
646 | start_pc = here; | |
647 | updated_fp = 1; | |
648 | } | |
649 | else | |
650 | if (updated_fp) | |
651 | { | |
652 | /* Don't bail out yet, we may have arguments stored in | |
653 | registers here, according to the debug info, so that | |
7bb11558 | 654 | gdb can print the frames correctly. */ |
e17a4113 UW |
655 | start_pc = look_for_args_moves (gdbarch, |
656 | here - insn_size, media_mode); | |
55ff77ac CV |
657 | break; |
658 | } | |
659 | } | |
660 | else | |
661 | { | |
e17a4113 | 662 | int w = 0xffff & read_memory_integer (here, insn_size, byte_order); |
55ff77ac CV |
663 | here += insn_size; |
664 | ||
665 | if (IS_STS_R0 (w) || IS_STS_PR (w) | |
666 | || IS_MOV_TO_R15 (w) || IS_MOV_R14 (w) | |
667 | || IS_MOV_R0 (w) || IS_ADD_SP_R0 (w) || IS_MOV_R14_R0 (w)) | |
668 | { | |
669 | start_pc = here; | |
670 | } | |
671 | else if (IS_MOV_SP_FP (w)) | |
672 | { | |
673 | start_pc = here; | |
674 | updated_fp = 1; | |
675 | } | |
676 | else | |
677 | if (updated_fp) | |
678 | { | |
679 | /* Don't bail out yet, we may have arguments stored in | |
680 | registers here, according to the debug info, so that | |
7bb11558 | 681 | gdb can print the frames correctly. */ |
e17a4113 UW |
682 | start_pc = look_for_args_moves (gdbarch, |
683 | here - insn_size, media_mode); | |
55ff77ac CV |
684 | break; |
685 | } | |
686 | } | |
687 | } | |
688 | ||
689 | return start_pc; | |
690 | } | |
691 | ||
692 | static CORE_ADDR | |
6093d2eb | 693 | sh64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
55ff77ac CV |
694 | { |
695 | CORE_ADDR post_prologue_pc; | |
696 | ||
697 | /* See if we can determine the end of the prologue via the symbol table. | |
698 | If so, then return either PC, or the PC after the prologue, whichever | |
699 | is greater. */ | |
700 | post_prologue_pc = after_prologue (pc); | |
701 | ||
702 | /* If after_prologue returned a useful address, then use it. Else | |
7bb11558 | 703 | fall back on the instruction skipping code. */ |
55ff77ac | 704 | if (post_prologue_pc != 0) |
325fac50 | 705 | return std::max (pc, post_prologue_pc); |
55ff77ac | 706 | else |
e17a4113 | 707 | return sh64_skip_prologue_hard_way (gdbarch, pc); |
55ff77ac CV |
708 | } |
709 | ||
55ff77ac CV |
710 | /* Should call_function allocate stack space for a struct return? */ |
711 | static int | |
c30dc700 | 712 | sh64_use_struct_convention (struct type *type) |
55ff77ac CV |
713 | { |
714 | return (TYPE_LENGTH (type) > 8); | |
715 | } | |
716 | ||
7bb11558 | 717 | /* For vectors of 4 floating point registers. */ |
55ff77ac | 718 | static int |
d93859e2 | 719 | sh64_fv_reg_base_num (struct gdbarch *gdbarch, int fv_regnum) |
55ff77ac CV |
720 | { |
721 | int fp_regnum; | |
722 | ||
d93859e2 | 723 | fp_regnum = gdbarch_fp0_regnum (gdbarch) + (fv_regnum - FV0_REGNUM) * 4; |
55ff77ac CV |
724 | return fp_regnum; |
725 | } | |
726 | ||
c378eb4e | 727 | /* For double precision floating point registers, i.e 2 fp regs. */ |
55ff77ac | 728 | static int |
d93859e2 | 729 | sh64_dr_reg_base_num (struct gdbarch *gdbarch, int dr_regnum) |
55ff77ac CV |
730 | { |
731 | int fp_regnum; | |
732 | ||
d93859e2 | 733 | fp_regnum = gdbarch_fp0_regnum (gdbarch) + (dr_regnum - DR0_REGNUM) * 2; |
55ff77ac CV |
734 | return fp_regnum; |
735 | } | |
736 | ||
c378eb4e | 737 | /* For pairs of floating point registers. */ |
55ff77ac | 738 | static int |
d93859e2 | 739 | sh64_fpp_reg_base_num (struct gdbarch *gdbarch, int fpp_regnum) |
55ff77ac CV |
740 | { |
741 | int fp_regnum; | |
742 | ||
d93859e2 | 743 | fp_regnum = gdbarch_fp0_regnum (gdbarch) + (fpp_regnum - FPP0_REGNUM) * 2; |
55ff77ac CV |
744 | return fp_regnum; |
745 | } | |
746 | ||
55ff77ac CV |
747 | /* *INDENT-OFF* */ |
748 | /* | |
749 | SH COMPACT MODE (ISA 16) (all pseudo) 221-272 | |
750 | GDB_REGNUM BASE_REGNUM | |
751 | r0_c 221 0 | |
752 | r1_c 222 1 | |
753 | r2_c 223 2 | |
754 | r3_c 224 3 | |
755 | r4_c 225 4 | |
756 | r5_c 226 5 | |
757 | r6_c 227 6 | |
758 | r7_c 228 7 | |
759 | r8_c 229 8 | |
760 | r9_c 230 9 | |
761 | r10_c 231 10 | |
762 | r11_c 232 11 | |
763 | r12_c 233 12 | |
764 | r13_c 234 13 | |
765 | r14_c 235 14 | |
766 | r15_c 236 15 | |
767 | ||
768 | pc_c 237 64 | |
769 | gbr_c 238 16 | |
770 | mach_c 239 17 | |
771 | macl_c 240 17 | |
772 | pr_c 241 18 | |
773 | t_c 242 19 | |
774 | fpscr_c 243 76 | |
775 | fpul_c 244 109 | |
776 | ||
777 | fr0_c 245 77 | |
778 | fr1_c 246 78 | |
779 | fr2_c 247 79 | |
780 | fr3_c 248 80 | |
781 | fr4_c 249 81 | |
782 | fr5_c 250 82 | |
783 | fr6_c 251 83 | |
784 | fr7_c 252 84 | |
785 | fr8_c 253 85 | |
786 | fr9_c 254 86 | |
787 | fr10_c 255 87 | |
788 | fr11_c 256 88 | |
789 | fr12_c 257 89 | |
790 | fr13_c 258 90 | |
791 | fr14_c 259 91 | |
792 | fr15_c 260 92 | |
793 | ||
794 | dr0_c 261 77 | |
795 | dr2_c 262 79 | |
796 | dr4_c 263 81 | |
797 | dr6_c 264 83 | |
798 | dr8_c 265 85 | |
799 | dr10_c 266 87 | |
800 | dr12_c 267 89 | |
801 | dr14_c 268 91 | |
802 | ||
803 | fv0_c 269 77 | |
804 | fv4_c 270 81 | |
805 | fv8_c 271 85 | |
806 | fv12_c 272 91 | |
807 | */ | |
808 | /* *INDENT-ON* */ | |
809 | static int | |
d93859e2 | 810 | sh64_compact_reg_base_num (struct gdbarch *gdbarch, int reg_nr) |
55ff77ac | 811 | { |
c30dc700 | 812 | int base_regnum = reg_nr; |
55ff77ac CV |
813 | |
814 | /* general register N maps to general register N */ | |
815 | if (reg_nr >= R0_C_REGNUM | |
816 | && reg_nr <= R_LAST_C_REGNUM) | |
817 | base_regnum = reg_nr - R0_C_REGNUM; | |
818 | ||
819 | /* floating point register N maps to floating point register N */ | |
820 | else if (reg_nr >= FP0_C_REGNUM | |
821 | && reg_nr <= FP_LAST_C_REGNUM) | |
d93859e2 | 822 | base_regnum = reg_nr - FP0_C_REGNUM + gdbarch_fp0_regnum (gdbarch); |
55ff77ac CV |
823 | |
824 | /* double prec register N maps to base regnum for double prec register N */ | |
825 | else if (reg_nr >= DR0_C_REGNUM | |
826 | && reg_nr <= DR_LAST_C_REGNUM) | |
d93859e2 UW |
827 | base_regnum = sh64_dr_reg_base_num (gdbarch, |
828 | DR0_REGNUM + reg_nr - DR0_C_REGNUM); | |
55ff77ac CV |
829 | |
830 | /* vector N maps to base regnum for vector register N */ | |
831 | else if (reg_nr >= FV0_C_REGNUM | |
832 | && reg_nr <= FV_LAST_C_REGNUM) | |
d93859e2 UW |
833 | base_regnum = sh64_fv_reg_base_num (gdbarch, |
834 | FV0_REGNUM + reg_nr - FV0_C_REGNUM); | |
55ff77ac CV |
835 | |
836 | else if (reg_nr == PC_C_REGNUM) | |
d93859e2 | 837 | base_regnum = gdbarch_pc_regnum (gdbarch); |
55ff77ac CV |
838 | |
839 | else if (reg_nr == GBR_C_REGNUM) | |
840 | base_regnum = 16; | |
841 | ||
842 | else if (reg_nr == MACH_C_REGNUM | |
843 | || reg_nr == MACL_C_REGNUM) | |
844 | base_regnum = 17; | |
845 | ||
846 | else if (reg_nr == PR_C_REGNUM) | |
c30dc700 | 847 | base_regnum = PR_REGNUM; |
55ff77ac CV |
848 | |
849 | else if (reg_nr == T_C_REGNUM) | |
850 | base_regnum = 19; | |
851 | ||
852 | else if (reg_nr == FPSCR_C_REGNUM) | |
7bb11558 | 853 | base_regnum = FPSCR_REGNUM; /*???? this register is a mess. */ |
55ff77ac CV |
854 | |
855 | else if (reg_nr == FPUL_C_REGNUM) | |
d93859e2 | 856 | base_regnum = gdbarch_fp0_regnum (gdbarch) + 32; |
55ff77ac CV |
857 | |
858 | return base_regnum; | |
859 | } | |
860 | ||
55ff77ac CV |
861 | static int |
862 | sign_extend (int value, int bits) | |
863 | { | |
864 | value = value & ((1 << bits) - 1); | |
865 | return (value & (1 << (bits - 1)) | |
866 | ? value | (~((1 << bits) - 1)) | |
867 | : value); | |
868 | } | |
869 | ||
870 | static void | |
c30dc700 CV |
871 | sh64_analyze_prologue (struct gdbarch *gdbarch, |
872 | struct sh64_frame_cache *cache, | |
873 | CORE_ADDR func_pc, | |
874 | CORE_ADDR current_pc) | |
55ff77ac | 875 | { |
55ff77ac CV |
876 | int pc; |
877 | int opc; | |
878 | int insn; | |
879 | int r0_val = 0; | |
55ff77ac | 880 | int insn_size; |
e17a4113 | 881 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
55ff77ac | 882 | |
c30dc700 | 883 | cache->sp_offset = 0; |
55ff77ac CV |
884 | |
885 | /* Loop around examining the prologue insns until we find something | |
886 | that does not appear to be part of the prologue. But give up | |
7bb11558 | 887 | after 20 of them, since we're getting silly then. */ |
55ff77ac | 888 | |
c30dc700 | 889 | pc = func_pc; |
55ff77ac | 890 | |
c30dc700 CV |
891 | if (cache->media_mode) |
892 | insn_size = 4; | |
55ff77ac | 893 | else |
c30dc700 | 894 | insn_size = 2; |
55ff77ac | 895 | |
c30dc700 CV |
896 | opc = pc + (insn_size * 28); |
897 | if (opc > current_pc) | |
898 | opc = current_pc; | |
899 | for ( ; pc <= opc; pc += insn_size) | |
55ff77ac | 900 | { |
c30dc700 CV |
901 | insn = read_memory_integer (cache->media_mode ? UNMAKE_ISA32_ADDR (pc) |
902 | : pc, | |
e17a4113 | 903 | insn_size, byte_order); |
55ff77ac | 904 | |
c30dc700 | 905 | if (!cache->media_mode) |
55ff77ac CV |
906 | { |
907 | if (IS_STS_PR (insn)) | |
908 | { | |
e17a4113 UW |
909 | int next_insn = read_memory_integer (pc + insn_size, |
910 | insn_size, byte_order); | |
55ff77ac CV |
911 | if (IS_MOV_TO_R15 (next_insn)) |
912 | { | |
c378eb4e MS |
913 | cache->saved_regs[PR_REGNUM] |
914 | = cache->sp_offset - ((((next_insn & 0xf) ^ 0x8) | |
915 | - 0x8) << 2); | |
55ff77ac CV |
916 | pc += insn_size; |
917 | } | |
918 | } | |
c30dc700 | 919 | |
55ff77ac | 920 | else if (IS_MOV_R14 (insn)) |
9ca10714 JB |
921 | { |
922 | cache->saved_regs[MEDIA_FP_REGNUM] = | |
923 | cache->sp_offset - ((((insn & 0xf) ^ 0x8) - 0x8) << 2); | |
924 | cache->uses_fp = 1; | |
925 | } | |
55ff77ac CV |
926 | |
927 | else if (IS_MOV_R0 (insn)) | |
928 | { | |
929 | /* Put in R0 the offset from SP at which to store some | |
c378eb4e | 930 | registers. We are interested in this value, because it |
55ff77ac CV |
931 | will tell us where the given registers are stored within |
932 | the frame. */ | |
933 | r0_val = ((insn & 0xff) ^ 0x80) - 0x80; | |
934 | } | |
c30dc700 | 935 | |
55ff77ac CV |
936 | else if (IS_ADD_SP_R0 (insn)) |
937 | { | |
938 | /* This instruction still prepares r0, but we don't care. | |
7bb11558 | 939 | We already have the offset in r0_val. */ |
55ff77ac | 940 | } |
c30dc700 | 941 | |
55ff77ac CV |
942 | else if (IS_STS_R0 (insn)) |
943 | { | |
c378eb4e | 944 | /* Store PR at r0_val-4 from SP. Decrement r0 by 4. */ |
c30dc700 | 945 | cache->saved_regs[PR_REGNUM] = cache->sp_offset - (r0_val - 4); |
55ff77ac | 946 | r0_val -= 4; |
55ff77ac | 947 | } |
c30dc700 | 948 | |
55ff77ac CV |
949 | else if (IS_MOV_R14_R0 (insn)) |
950 | { | |
c378eb4e | 951 | /* Store R14 at r0_val-4 from SP. Decrement r0 by 4. */ |
c30dc700 CV |
952 | cache->saved_regs[MEDIA_FP_REGNUM] = cache->sp_offset |
953 | - (r0_val - 4); | |
9ca10714 | 954 | cache->uses_fp = 1; |
55ff77ac CV |
955 | r0_val -= 4; |
956 | } | |
957 | ||
958 | else if (IS_ADD_SP (insn)) | |
c30dc700 CV |
959 | cache->sp_offset -= ((insn & 0xff) ^ 0x80) - 0x80; |
960 | ||
55ff77ac CV |
961 | else if (IS_MOV_SP_FP (insn)) |
962 | break; | |
963 | } | |
964 | else | |
965 | { | |
c30dc700 CV |
966 | if (IS_ADDIL_SP_MEDIA (insn) || IS_ADDI_SP_MEDIA (insn)) |
967 | cache->sp_offset -= | |
968 | sign_extend ((((insn & 0xffc00) ^ 0x80000) - 0x80000) >> 10, 9); | |
55ff77ac CV |
969 | |
970 | else if (IS_STQ_R18_R15 (insn)) | |
c378eb4e MS |
971 | cache->saved_regs[PR_REGNUM] |
972 | = cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10, | |
973 | 9) << 3); | |
55ff77ac CV |
974 | |
975 | else if (IS_STL_R18_R15 (insn)) | |
c378eb4e MS |
976 | cache->saved_regs[PR_REGNUM] |
977 | = cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10, | |
978 | 9) << 2); | |
55ff77ac CV |
979 | |
980 | else if (IS_STQ_R14_R15 (insn)) | |
9ca10714 JB |
981 | { |
982 | cache->saved_regs[MEDIA_FP_REGNUM] | |
983 | = cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10, | |
984 | 9) << 3); | |
985 | cache->uses_fp = 1; | |
986 | } | |
55ff77ac CV |
987 | |
988 | else if (IS_STL_R14_R15 (insn)) | |
9ca10714 JB |
989 | { |
990 | cache->saved_regs[MEDIA_FP_REGNUM] | |
991 | = cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10, | |
992 | 9) << 2); | |
993 | cache->uses_fp = 1; | |
994 | } | |
55ff77ac CV |
995 | |
996 | else if (IS_MOV_SP_FP_MEDIA (insn)) | |
997 | break; | |
998 | } | |
999 | } | |
55ff77ac CV |
1000 | } |
1001 | ||
55ff77ac | 1002 | static CORE_ADDR |
c30dc700 | 1003 | sh64_frame_align (struct gdbarch *ignore, CORE_ADDR sp) |
55ff77ac | 1004 | { |
c30dc700 | 1005 | return sp & ~7; |
55ff77ac CV |
1006 | } |
1007 | ||
c30dc700 | 1008 | /* Function: push_dummy_call |
55ff77ac CV |
1009 | Setup the function arguments for calling a function in the inferior. |
1010 | ||
85a453d5 | 1011 | On the Renesas SH architecture, there are four registers (R4 to R7) |
55ff77ac CV |
1012 | which are dedicated for passing function arguments. Up to the first |
1013 | four arguments (depending on size) may go into these registers. | |
1014 | The rest go on the stack. | |
1015 | ||
1016 | Arguments that are smaller than 4 bytes will still take up a whole | |
1017 | register or a whole 32-bit word on the stack, and will be | |
1018 | right-justified in the register or the stack word. This includes | |
1019 | chars, shorts, and small aggregate types. | |
1020 | ||
1021 | Arguments that are larger than 4 bytes may be split between two or | |
1022 | more registers. If there are not enough registers free, an argument | |
1023 | may be passed partly in a register (or registers), and partly on the | |
c378eb4e | 1024 | stack. This includes doubles, long longs, and larger aggregates. |
55ff77ac CV |
1025 | As far as I know, there is no upper limit to the size of aggregates |
1026 | that will be passed in this way; in other words, the convention of | |
1027 | passing a pointer to a large aggregate instead of a copy is not used. | |
1028 | ||
1029 | An exceptional case exists for struct arguments (and possibly other | |
1030 | aggregates such as arrays) if the size is larger than 4 bytes but | |
1031 | not a multiple of 4 bytes. In this case the argument is never split | |
1032 | between the registers and the stack, but instead is copied in its | |
1033 | entirety onto the stack, AND also copied into as many registers as | |
1034 | there is room for. In other words, space in registers permitting, | |
1035 | two copies of the same argument are passed in. As far as I can tell, | |
1036 | only the one on the stack is used, although that may be a function | |
1037 | of the level of compiler optimization. I suspect this is a compiler | |
1038 | bug. Arguments of these odd sizes are left-justified within the | |
1039 | word (as opposed to arguments smaller than 4 bytes, which are | |
1040 | right-justified). | |
1041 | ||
1042 | If the function is to return an aggregate type such as a struct, it | |
1043 | is either returned in the normal return value register R0 (if its | |
1044 | size is no greater than one byte), or else the caller must allocate | |
1045 | space into which the callee will copy the return value (if the size | |
1046 | is greater than one byte). In this case, a pointer to the return | |
1047 | value location is passed into the callee in register R2, which does | |
1048 | not displace any of the other arguments passed in via registers R4 | |
c378eb4e | 1049 | to R7. */ |
55ff77ac CV |
1050 | |
1051 | /* R2-R9 for integer types and integer equivalent (char, pointers) and | |
1052 | non-scalar (struct, union) elements (even if the elements are | |
1053 | floats). | |
1054 | FR0-FR11 for single precision floating point (float) | |
1055 | DR0-DR10 for double precision floating point (double) | |
1056 | ||
1057 | If a float is argument number 3 (for instance) and arguments number | |
1058 | 1,2, and 4 are integer, the mapping will be: | |
c378eb4e | 1059 | arg1 -->R2, arg2 --> R3, arg3 -->FR0, arg4 --> R5. I.e. R4 is not used. |
55ff77ac CV |
1060 | |
1061 | If a float is argument number 10 (for instance) and arguments number | |
1062 | 1 through 10 are integer, the mapping will be: | |
1063 | arg1->R2, arg2->R3, arg3->R4, arg4->R5, arg5->R6, arg6->R7, arg7->R8, | |
c378eb4e MS |
1064 | arg8->R9, arg9->(0,SP)stack(8-byte aligned), arg10->FR0, |
1065 | arg11->stack(16,SP). I.e. there is hole in the stack. | |
55ff77ac CV |
1066 | |
1067 | Different rules apply for variable arguments functions, and for functions | |
7bb11558 | 1068 | for which the prototype is not known. */ |
55ff77ac CV |
1069 | |
1070 | static CORE_ADDR | |
c30dc700 CV |
1071 | sh64_push_dummy_call (struct gdbarch *gdbarch, |
1072 | struct value *function, | |
1073 | struct regcache *regcache, | |
1074 | CORE_ADDR bp_addr, | |
1075 | int nargs, struct value **args, | |
1076 | CORE_ADDR sp, int struct_return, | |
1077 | CORE_ADDR struct_addr) | |
55ff77ac | 1078 | { |
e17a4113 | 1079 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
55ff77ac CV |
1080 | int stack_offset, stack_alloc; |
1081 | int int_argreg; | |
55ff77ac CV |
1082 | int float_arg_index = 0; |
1083 | int double_arg_index = 0; | |
1084 | int argnum; | |
1085 | struct type *type; | |
1086 | CORE_ADDR regval; | |
948f8e3d PA |
1087 | const gdb_byte *val; |
1088 | gdb_byte valbuf[8]; | |
55ff77ac CV |
1089 | int len; |
1090 | int argreg_size; | |
1091 | int fp_args[12]; | |
55ff77ac CV |
1092 | |
1093 | memset (fp_args, 0, sizeof (fp_args)); | |
1094 | ||
c378eb4e | 1095 | /* First force sp to a 8-byte alignment. */ |
c30dc700 | 1096 | sp = sh64_frame_align (gdbarch, sp); |
55ff77ac CV |
1097 | |
1098 | /* The "struct return pointer" pseudo-argument has its own dedicated | |
c378eb4e | 1099 | register. */ |
55ff77ac CV |
1100 | |
1101 | if (struct_return) | |
c30dc700 CV |
1102 | regcache_cooked_write_unsigned (regcache, |
1103 | STRUCT_RETURN_REGNUM, struct_addr); | |
55ff77ac | 1104 | |
c378eb4e | 1105 | /* Now make sure there's space on the stack. */ |
55ff77ac | 1106 | for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++) |
4991999e | 1107 | stack_alloc += ((TYPE_LENGTH (value_type (args[argnum])) + 7) & ~7); |
c378eb4e | 1108 | sp -= stack_alloc; /* Make room on stack for args. */ |
55ff77ac CV |
1109 | |
1110 | /* Now load as many as possible of the first arguments into | |
1111 | registers, and push the rest onto the stack. There are 64 bytes | |
1112 | in eight registers available. Loop thru args from first to last. */ | |
1113 | ||
1114 | int_argreg = ARG0_REGNUM; | |
55ff77ac CV |
1115 | |
1116 | for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++) | |
1117 | { | |
4991999e | 1118 | type = value_type (args[argnum]); |
55ff77ac CV |
1119 | len = TYPE_LENGTH (type); |
1120 | memset (valbuf, 0, sizeof (valbuf)); | |
1121 | ||
1122 | if (TYPE_CODE (type) != TYPE_CODE_FLT) | |
1123 | { | |
58643501 | 1124 | argreg_size = register_size (gdbarch, int_argreg); |
55ff77ac CV |
1125 | |
1126 | if (len < argreg_size) | |
1127 | { | |
c378eb4e | 1128 | /* value gets right-justified in the register or stack word. */ |
58643501 | 1129 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
55ff77ac | 1130 | memcpy (valbuf + argreg_size - len, |
948f8e3d | 1131 | value_contents (args[argnum]), len); |
55ff77ac | 1132 | else |
948f8e3d | 1133 | memcpy (valbuf, value_contents (args[argnum]), len); |
55ff77ac CV |
1134 | |
1135 | val = valbuf; | |
1136 | } | |
1137 | else | |
948f8e3d | 1138 | val = value_contents (args[argnum]); |
55ff77ac CV |
1139 | |
1140 | while (len > 0) | |
1141 | { | |
1142 | if (int_argreg > ARGLAST_REGNUM) | |
1143 | { | |
c378eb4e | 1144 | /* Must go on the stack. */ |
948f8e3d | 1145 | write_memory (sp + stack_offset, val, argreg_size); |
55ff77ac CV |
1146 | stack_offset += 8;/*argreg_size;*/ |
1147 | } | |
1148 | /* NOTE WELL!!!!! This is not an "else if" clause!!! | |
1149 | That's because some *&^%$ things get passed on the stack | |
1150 | AND in the registers! */ | |
1151 | if (int_argreg <= ARGLAST_REGNUM) | |
1152 | { | |
c378eb4e | 1153 | /* There's room in a register. */ |
e17a4113 UW |
1154 | regval = extract_unsigned_integer (val, argreg_size, |
1155 | byte_order); | |
c378eb4e MS |
1156 | regcache_cooked_write_unsigned (regcache, |
1157 | int_argreg, regval); | |
55ff77ac CV |
1158 | } |
1159 | /* Store the value 8 bytes at a time. This means that | |
1160 | things larger than 8 bytes may go partly in registers | |
c378eb4e | 1161 | and partly on the stack. FIXME: argreg is incremented |
7bb11558 | 1162 | before we use its size. */ |
55ff77ac CV |
1163 | len -= argreg_size; |
1164 | val += argreg_size; | |
1165 | int_argreg++; | |
1166 | } | |
1167 | } | |
1168 | else | |
1169 | { | |
948f8e3d | 1170 | val = value_contents (args[argnum]); |
55ff77ac CV |
1171 | if (len == 4) |
1172 | { | |
c378eb4e | 1173 | /* Where is it going to be stored? */ |
55ff77ac CV |
1174 | while (fp_args[float_arg_index]) |
1175 | float_arg_index ++; | |
1176 | ||
1177 | /* Now float_argreg points to the register where it | |
1178 | should be stored. Are we still within the allowed | |
c378eb4e | 1179 | register set? */ |
55ff77ac CV |
1180 | if (float_arg_index <= FLOAT_ARGLAST_REGNUM) |
1181 | { | |
1182 | /* Goes in FR0...FR11 */ | |
c30dc700 | 1183 | regcache_cooked_write (regcache, |
58643501 | 1184 | gdbarch_fp0_regnum (gdbarch) |
3e8c568d | 1185 | + float_arg_index, |
c30dc700 | 1186 | val); |
55ff77ac | 1187 | fp_args[float_arg_index] = 1; |
7bb11558 | 1188 | /* Skip the corresponding general argument register. */ |
55ff77ac CV |
1189 | int_argreg ++; |
1190 | } | |
1191 | else | |
d4fb63e1 TT |
1192 | { |
1193 | /* Store it as the integers, 8 bytes at the time, if | |
1194 | necessary spilling on the stack. */ | |
1195 | } | |
55ff77ac CV |
1196 | } |
1197 | else if (len == 8) | |
1198 | { | |
c378eb4e | 1199 | /* Where is it going to be stored? */ |
55ff77ac CV |
1200 | while (fp_args[double_arg_index]) |
1201 | double_arg_index += 2; | |
1202 | /* Now double_argreg points to the register | |
1203 | where it should be stored. | |
c378eb4e | 1204 | Are we still within the allowed register set? */ |
55ff77ac CV |
1205 | if (double_arg_index < FLOAT_ARGLAST_REGNUM) |
1206 | { | |
1207 | /* Goes in DR0...DR10 */ | |
1208 | /* The numbering of the DRi registers is consecutive, | |
7bb11558 | 1209 | i.e. includes odd numbers. */ |
55ff77ac | 1210 | int double_register_offset = double_arg_index / 2; |
c30dc700 CV |
1211 | int regnum = DR0_REGNUM + double_register_offset; |
1212 | regcache_cooked_write (regcache, regnum, val); | |
55ff77ac CV |
1213 | fp_args[double_arg_index] = 1; |
1214 | fp_args[double_arg_index + 1] = 1; | |
7bb11558 | 1215 | /* Skip the corresponding general argument register. */ |
55ff77ac CV |
1216 | int_argreg ++; |
1217 | } | |
1218 | else | |
d4fb63e1 TT |
1219 | { |
1220 | /* Store it as the integers, 8 bytes at the time, if | |
1221 | necessary spilling on the stack. */ | |
1222 | } | |
55ff77ac CV |
1223 | } |
1224 | } | |
1225 | } | |
c378eb4e | 1226 | /* Store return address. */ |
c30dc700 | 1227 | regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr); |
55ff77ac | 1228 | |
c30dc700 | 1229 | /* Update stack pointer. */ |
3e8c568d | 1230 | regcache_cooked_write_unsigned (regcache, |
58643501 | 1231 | gdbarch_sp_regnum (gdbarch), sp); |
55ff77ac | 1232 | |
55ff77ac CV |
1233 | return sp; |
1234 | } | |
1235 | ||
1236 | /* Find a function's return value in the appropriate registers (in | |
1237 | regbuf), and copy it into valbuf. Extract from an array REGBUF | |
1238 | containing the (raw) register state a function return value of type | |
1239 | TYPE, and copy that, in virtual format, into VALBUF. */ | |
1240 | static void | |
c30dc700 | 1241 | sh64_extract_return_value (struct type *type, struct regcache *regcache, |
7c543f7b | 1242 | gdb_byte *valbuf) |
55ff77ac | 1243 | { |
ac7936df | 1244 | struct gdbarch *gdbarch = regcache->arch (); |
55ff77ac | 1245 | int len = TYPE_LENGTH (type); |
d93859e2 | 1246 | |
55ff77ac CV |
1247 | if (TYPE_CODE (type) == TYPE_CODE_FLT) |
1248 | { | |
1249 | if (len == 4) | |
1250 | { | |
c378eb4e | 1251 | /* Return value stored in gdbarch_fp0_regnum. */ |
3e8c568d | 1252 | regcache_raw_read (regcache, |
d93859e2 | 1253 | gdbarch_fp0_regnum (gdbarch), valbuf); |
55ff77ac CV |
1254 | } |
1255 | else if (len == 8) | |
1256 | { | |
c378eb4e | 1257 | /* return value stored in DR0_REGNUM. */ |
18cf8b5b | 1258 | gdb_byte buf[8]; |
18cf8b5b | 1259 | regcache_cooked_read (regcache, DR0_REGNUM, buf); |
55ff77ac | 1260 | |
96a5a1d3 UW |
1261 | convert_typed_floating (buf, sh64_littlebyte_bigword_type (gdbarch), |
1262 | valbuf, type); | |
55ff77ac CV |
1263 | } |
1264 | } | |
1265 | else | |
1266 | { | |
1267 | if (len <= 8) | |
1268 | { | |
c30dc700 | 1269 | int offset; |
e362b510 | 1270 | gdb_byte buf[8]; |
c378eb4e | 1271 | /* Result is in register 2. If smaller than 8 bytes, it is padded |
7bb11558 | 1272 | at the most significant end. */ |
c30dc700 CV |
1273 | regcache_raw_read (regcache, DEFAULT_RETURN_REGNUM, buf); |
1274 | ||
d93859e2 UW |
1275 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
1276 | offset = register_size (gdbarch, DEFAULT_RETURN_REGNUM) | |
c30dc700 | 1277 | - len; |
55ff77ac | 1278 | else |
c30dc700 CV |
1279 | offset = 0; |
1280 | memcpy (valbuf, buf + offset, len); | |
55ff77ac CV |
1281 | } |
1282 | else | |
a73c6dcd | 1283 | error (_("bad size for return value")); |
55ff77ac CV |
1284 | } |
1285 | } | |
1286 | ||
1287 | /* Write into appropriate registers a function return value | |
1288 | of type TYPE, given in virtual format. | |
1289 | If the architecture is sh4 or sh3e, store a function's return value | |
1290 | in the R0 general register or in the FP0 floating point register, | |
c378eb4e | 1291 | depending on the type of the return value. In all the other cases |
7bb11558 | 1292 | the result is stored in r0, left-justified. */ |
55ff77ac CV |
1293 | |
1294 | static void | |
c30dc700 | 1295 | sh64_store_return_value (struct type *type, struct regcache *regcache, |
948f8e3d | 1296 | const gdb_byte *valbuf) |
55ff77ac | 1297 | { |
ac7936df | 1298 | struct gdbarch *gdbarch = regcache->arch (); |
e362b510 | 1299 | gdb_byte buf[64]; /* more than enough... */ |
55ff77ac CV |
1300 | int len = TYPE_LENGTH (type); |
1301 | ||
1302 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
1303 | { | |
d93859e2 | 1304 | int i, regnum = gdbarch_fp0_regnum (gdbarch); |
c30dc700 | 1305 | for (i = 0; i < len; i += 4) |
d93859e2 | 1306 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) |
c30dc700 | 1307 | regcache_raw_write (regcache, regnum++, |
948f8e3d | 1308 | valbuf + len - 4 - i); |
c30dc700 | 1309 | else |
948f8e3d | 1310 | regcache_raw_write (regcache, regnum++, valbuf + i); |
55ff77ac CV |
1311 | } |
1312 | else | |
1313 | { | |
1314 | int return_register = DEFAULT_RETURN_REGNUM; | |
1315 | int offset = 0; | |
1316 | ||
d93859e2 | 1317 | if (len <= register_size (gdbarch, return_register)) |
55ff77ac | 1318 | { |
7bb11558 | 1319 | /* Pad with zeros. */ |
d93859e2 UW |
1320 | memset (buf, 0, register_size (gdbarch, return_register)); |
1321 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE) | |
1322 | offset = 0; /*register_size (gdbarch, | |
7bb11558 | 1323 | return_register) - len;*/ |
55ff77ac | 1324 | else |
d93859e2 | 1325 | offset = register_size (gdbarch, return_register) - len; |
55ff77ac CV |
1326 | |
1327 | memcpy (buf + offset, valbuf, len); | |
c30dc700 | 1328 | regcache_raw_write (regcache, return_register, buf); |
55ff77ac CV |
1329 | } |
1330 | else | |
c30dc700 | 1331 | regcache_raw_write (regcache, return_register, valbuf); |
55ff77ac CV |
1332 | } |
1333 | } | |
1334 | ||
c30dc700 | 1335 | static enum return_value_convention |
6a3a010b | 1336 | sh64_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 | 1337 | struct type *type, struct regcache *regcache, |
18cf8b5b | 1338 | gdb_byte *readbuf, const gdb_byte *writebuf) |
c30dc700 CV |
1339 | { |
1340 | if (sh64_use_struct_convention (type)) | |
1341 | return RETURN_VALUE_STRUCT_CONVENTION; | |
1342 | if (writebuf) | |
1343 | sh64_store_return_value (type, regcache, writebuf); | |
1344 | else if (readbuf) | |
1345 | sh64_extract_return_value (type, regcache, readbuf); | |
1346 | return RETURN_VALUE_REGISTER_CONVENTION; | |
1347 | } | |
1348 | ||
55ff77ac CV |
1349 | /* *INDENT-OFF* */ |
1350 | /* | |
1351 | SH MEDIA MODE (ISA 32) | |
1352 | general registers (64-bit) 0-63 | |
1353 | 0 r0, r1, r2, r3, r4, r5, r6, r7, | |
1354 | 64 r8, r9, r10, r11, r12, r13, r14, r15, | |
1355 | 128 r16, r17, r18, r19, r20, r21, r22, r23, | |
1356 | 192 r24, r25, r26, r27, r28, r29, r30, r31, | |
1357 | 256 r32, r33, r34, r35, r36, r37, r38, r39, | |
1358 | 320 r40, r41, r42, r43, r44, r45, r46, r47, | |
1359 | 384 r48, r49, r50, r51, r52, r53, r54, r55, | |
1360 | 448 r56, r57, r58, r59, r60, r61, r62, r63, | |
1361 | ||
1362 | pc (64-bit) 64 | |
1363 | 512 pc, | |
1364 | ||
1365 | status reg., saved status reg., saved pc reg. (64-bit) 65-67 | |
1366 | 520 sr, ssr, spc, | |
1367 | ||
1368 | target registers (64-bit) 68-75 | |
1369 | 544 tr0, tr1, tr2, tr3, tr4, tr5, tr6, tr7, | |
1370 | ||
1371 | floating point state control register (32-bit) 76 | |
1372 | 608 fpscr, | |
1373 | ||
1374 | single precision floating point registers (32-bit) 77-140 | |
1375 | 612 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7, | |
1376 | 644 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15, | |
1377 | 676 fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23, | |
1378 | 708 fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31, | |
1379 | 740 fr32, fr33, fr34, fr35, fr36, fr37, fr38, fr39, | |
1380 | 772 fr40, fr41, fr42, fr43, fr44, fr45, fr46, fr47, | |
1381 | 804 fr48, fr49, fr50, fr51, fr52, fr53, fr54, fr55, | |
1382 | 836 fr56, fr57, fr58, fr59, fr60, fr61, fr62, fr63, | |
1383 | ||
1384 | TOTAL SPACE FOR REGISTERS: 868 bytes | |
1385 | ||
1386 | From here on they are all pseudo registers: no memory allocated. | |
1387 | REGISTER_BYTE returns the register byte for the base register. | |
1388 | ||
1389 | double precision registers (pseudo) 141-172 | |
1390 | dr0, dr2, dr4, dr6, dr8, dr10, dr12, dr14, | |
1391 | dr16, dr18, dr20, dr22, dr24, dr26, dr28, dr30, | |
1392 | dr32, dr34, dr36, dr38, dr40, dr42, dr44, dr46, | |
1393 | dr48, dr50, dr52, dr54, dr56, dr58, dr60, dr62, | |
1394 | ||
1395 | floating point pairs (pseudo) 173-204 | |
1396 | fp0, fp2, fp4, fp6, fp8, fp10, fp12, fp14, | |
1397 | fp16, fp18, fp20, fp22, fp24, fp26, fp28, fp30, | |
1398 | fp32, fp34, fp36, fp38, fp40, fp42, fp44, fp46, | |
1399 | fp48, fp50, fp52, fp54, fp56, fp58, fp60, fp62, | |
1400 | ||
1401 | floating point vectors (4 floating point regs) (pseudo) 205-220 | |
1402 | fv0, fv4, fv8, fv12, fv16, fv20, fv24, fv28, | |
1403 | fv32, fv36, fv40, fv44, fv48, fv52, fv56, fv60, | |
1404 | ||
1405 | SH COMPACT MODE (ISA 16) (all pseudo) 221-272 | |
1406 | r0_c, r1_c, r2_c, r3_c, r4_c, r5_c, r6_c, r7_c, | |
1407 | r8_c, r9_c, r10_c, r11_c, r12_c, r13_c, r14_c, r15_c, | |
1408 | pc_c, | |
1409 | gbr_c, mach_c, macl_c, pr_c, t_c, | |
1410 | fpscr_c, fpul_c, | |
1411 | fr0_c, fr1_c, fr2_c, fr3_c, fr4_c, fr5_c, fr6_c, fr7_c, | |
1412 | fr8_c, fr9_c, fr10_c, fr11_c, fr12_c, fr13_c, fr14_c, fr15_c | |
1413 | dr0_c, dr2_c, dr4_c, dr6_c, dr8_c, dr10_c, dr12_c, dr14_c | |
1414 | fv0_c, fv4_c, fv8_c, fv12_c | |
1415 | */ | |
55ff77ac | 1416 | |
55ff77ac | 1417 | static struct type * |
0dfff4cb | 1418 | sh64_build_float_register_type (struct gdbarch *gdbarch, int high) |
55ff77ac | 1419 | { |
e3506a9f UW |
1420 | return lookup_array_range_type (builtin_type (gdbarch)->builtin_float, |
1421 | 0, high); | |
55ff77ac CV |
1422 | } |
1423 | ||
7bb11558 MS |
1424 | /* Return the GDB type object for the "standard" data type |
1425 | of data in register REG_NR. */ | |
55ff77ac | 1426 | static struct type * |
7bb11558 | 1427 | sh64_register_type (struct gdbarch *gdbarch, int reg_nr) |
55ff77ac | 1428 | { |
58643501 | 1429 | if ((reg_nr >= gdbarch_fp0_regnum (gdbarch) |
55ff77ac CV |
1430 | && reg_nr <= FP_LAST_REGNUM) |
1431 | || (reg_nr >= FP0_C_REGNUM | |
1432 | && reg_nr <= FP_LAST_C_REGNUM)) | |
0dfff4cb | 1433 | return builtin_type (gdbarch)->builtin_float; |
55ff77ac CV |
1434 | else if ((reg_nr >= DR0_REGNUM |
1435 | && reg_nr <= DR_LAST_REGNUM) | |
1436 | || (reg_nr >= DR0_C_REGNUM | |
1437 | && reg_nr <= DR_LAST_C_REGNUM)) | |
0dfff4cb | 1438 | return builtin_type (gdbarch)->builtin_double; |
55ff77ac CV |
1439 | else if (reg_nr >= FPP0_REGNUM |
1440 | && reg_nr <= FPP_LAST_REGNUM) | |
0dfff4cb | 1441 | return sh64_build_float_register_type (gdbarch, 1); |
55ff77ac CV |
1442 | else if ((reg_nr >= FV0_REGNUM |
1443 | && reg_nr <= FV_LAST_REGNUM) | |
1444 | ||(reg_nr >= FV0_C_REGNUM | |
1445 | && reg_nr <= FV_LAST_C_REGNUM)) | |
0dfff4cb | 1446 | return sh64_build_float_register_type (gdbarch, 3); |
55ff77ac | 1447 | else if (reg_nr == FPSCR_REGNUM) |
0dfff4cb | 1448 | return builtin_type (gdbarch)->builtin_int; |
55ff77ac CV |
1449 | else if (reg_nr >= R0_C_REGNUM |
1450 | && reg_nr < FP0_C_REGNUM) | |
0dfff4cb | 1451 | return builtin_type (gdbarch)->builtin_int; |
55ff77ac | 1452 | else |
0dfff4cb | 1453 | return builtin_type (gdbarch)->builtin_long_long; |
55ff77ac CV |
1454 | } |
1455 | ||
1456 | static void | |
d93859e2 | 1457 | sh64_register_convert_to_virtual (struct gdbarch *gdbarch, int regnum, |
948f8e3d | 1458 | struct type *type, gdb_byte *from, gdb_byte *to) |
55ff77ac | 1459 | { |
d93859e2 | 1460 | if (gdbarch_byte_order (gdbarch) != BFD_ENDIAN_LITTLE) |
55ff77ac | 1461 | { |
7bb11558 | 1462 | /* It is a no-op. */ |
d93859e2 | 1463 | memcpy (to, from, register_size (gdbarch, regnum)); |
55ff77ac CV |
1464 | return; |
1465 | } | |
1466 | ||
1467 | if ((regnum >= DR0_REGNUM | |
1468 | && regnum <= DR_LAST_REGNUM) | |
1469 | || (regnum >= DR0_C_REGNUM | |
1470 | && regnum <= DR_LAST_C_REGNUM)) | |
96a5a1d3 UW |
1471 | convert_typed_floating (from, sh64_littlebyte_bigword_type (gdbarch), |
1472 | to, type); | |
55ff77ac | 1473 | else |
a73c6dcd MS |
1474 | error (_("sh64_register_convert_to_virtual " |
1475 | "called with non DR register number")); | |
55ff77ac CV |
1476 | } |
1477 | ||
1478 | static void | |
d93859e2 UW |
1479 | sh64_register_convert_to_raw (struct gdbarch *gdbarch, struct type *type, |
1480 | int regnum, const void *from, void *to) | |
55ff77ac | 1481 | { |
d93859e2 | 1482 | if (gdbarch_byte_order (gdbarch) != BFD_ENDIAN_LITTLE) |
55ff77ac | 1483 | { |
7bb11558 | 1484 | /* It is a no-op. */ |
d93859e2 | 1485 | memcpy (to, from, register_size (gdbarch, regnum)); |
55ff77ac CV |
1486 | return; |
1487 | } | |
1488 | ||
1489 | if ((regnum >= DR0_REGNUM | |
1490 | && regnum <= DR_LAST_REGNUM) | |
1491 | || (regnum >= DR0_C_REGNUM | |
1492 | && regnum <= DR_LAST_C_REGNUM)) | |
96a5a1d3 UW |
1493 | convert_typed_floating (from, type, |
1494 | to, sh64_littlebyte_bigword_type (gdbarch)); | |
55ff77ac | 1495 | else |
a73c6dcd MS |
1496 | error (_("sh64_register_convert_to_raw called " |
1497 | "with non DR register number")); | |
55ff77ac CV |
1498 | } |
1499 | ||
05d1431c PA |
1500 | /* Concatenate PORTIONS contiguous raw registers starting at |
1501 | BASE_REGNUM into BUFFER. */ | |
1502 | ||
1503 | static enum register_status | |
1504 | pseudo_register_read_portions (struct gdbarch *gdbarch, | |
1505 | struct regcache *regcache, | |
1506 | int portions, | |
1507 | int base_regnum, gdb_byte *buffer) | |
1508 | { | |
1509 | int portion; | |
1510 | ||
1511 | for (portion = 0; portion < portions; portion++) | |
1512 | { | |
1513 | enum register_status status; | |
1514 | gdb_byte *b; | |
1515 | ||
1516 | b = buffer + register_size (gdbarch, base_regnum) * portion; | |
1517 | status = regcache_raw_read (regcache, base_regnum + portion, b); | |
1518 | if (status != REG_VALID) | |
1519 | return status; | |
1520 | } | |
1521 | ||
1522 | return REG_VALID; | |
1523 | } | |
1524 | ||
1525 | static enum register_status | |
55ff77ac | 1526 | sh64_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, |
18cf8b5b | 1527 | int reg_nr, gdb_byte *buffer) |
55ff77ac | 1528 | { |
e17a4113 | 1529 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
55ff77ac | 1530 | int base_regnum; |
55ff77ac | 1531 | int offset = 0; |
05d1431c | 1532 | enum register_status status; |
55ff77ac CV |
1533 | |
1534 | if (reg_nr >= DR0_REGNUM | |
1535 | && reg_nr <= DR_LAST_REGNUM) | |
1536 | { | |
4a8a33c8 | 1537 | gdb_byte temp_buffer[8]; |
d93859e2 | 1538 | base_regnum = sh64_dr_reg_base_num (gdbarch, reg_nr); |
55ff77ac | 1539 | |
7bb11558 | 1540 | /* Build the value in the provided buffer. */ |
55ff77ac | 1541 | /* DR regs are double precision registers obtained by |
7bb11558 | 1542 | concatenating 2 single precision floating point registers. */ |
05d1431c PA |
1543 | status = pseudo_register_read_portions (gdbarch, regcache, |
1544 | 2, base_regnum, temp_buffer); | |
1545 | if (status == REG_VALID) | |
1546 | { | |
1547 | /* We must pay attention to the endianness. */ | |
1548 | sh64_register_convert_to_virtual (gdbarch, reg_nr, | |
1549 | register_type (gdbarch, reg_nr), | |
1550 | temp_buffer, buffer); | |
1551 | } | |
55ff77ac | 1552 | |
05d1431c | 1553 | return status; |
55ff77ac CV |
1554 | } |
1555 | ||
05d1431c | 1556 | else if (reg_nr >= FPP0_REGNUM |
55ff77ac CV |
1557 | && reg_nr <= FPP_LAST_REGNUM) |
1558 | { | |
d93859e2 | 1559 | base_regnum = sh64_fpp_reg_base_num (gdbarch, reg_nr); |
55ff77ac | 1560 | |
7bb11558 | 1561 | /* Build the value in the provided buffer. */ |
55ff77ac | 1562 | /* FPP regs are pairs of single precision registers obtained by |
7bb11558 | 1563 | concatenating 2 single precision floating point registers. */ |
05d1431c PA |
1564 | return pseudo_register_read_portions (gdbarch, regcache, |
1565 | 2, base_regnum, buffer); | |
55ff77ac CV |
1566 | } |
1567 | ||
1568 | else if (reg_nr >= FV0_REGNUM | |
1569 | && reg_nr <= FV_LAST_REGNUM) | |
1570 | { | |
d93859e2 | 1571 | base_regnum = sh64_fv_reg_base_num (gdbarch, reg_nr); |
55ff77ac | 1572 | |
7bb11558 | 1573 | /* Build the value in the provided buffer. */ |
55ff77ac | 1574 | /* FV regs are vectors of single precision registers obtained by |
7bb11558 | 1575 | concatenating 4 single precision floating point registers. */ |
05d1431c PA |
1576 | return pseudo_register_read_portions (gdbarch, regcache, |
1577 | 4, base_regnum, buffer); | |
55ff77ac CV |
1578 | } |
1579 | ||
c378eb4e | 1580 | /* sh compact pseudo registers. 1-to-1 with a shmedia register. */ |
55ff77ac CV |
1581 | else if (reg_nr >= R0_C_REGNUM |
1582 | && reg_nr <= T_C_REGNUM) | |
1583 | { | |
4a8a33c8 | 1584 | gdb_byte temp_buffer[8]; |
d93859e2 | 1585 | base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr); |
55ff77ac | 1586 | |
7bb11558 | 1587 | /* Build the value in the provided buffer. */ |
05d1431c PA |
1588 | status = regcache_raw_read (regcache, base_regnum, temp_buffer); |
1589 | if (status != REG_VALID) | |
1590 | return status; | |
58643501 | 1591 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
55ff77ac | 1592 | offset = 4; |
c378eb4e MS |
1593 | memcpy (buffer, |
1594 | temp_buffer + offset, 4); /* get LOWER 32 bits only???? */ | |
05d1431c | 1595 | return REG_VALID; |
55ff77ac CV |
1596 | } |
1597 | ||
1598 | else if (reg_nr >= FP0_C_REGNUM | |
1599 | && reg_nr <= FP_LAST_C_REGNUM) | |
1600 | { | |
d93859e2 | 1601 | base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr); |
55ff77ac | 1602 | |
7bb11558 | 1603 | /* Build the value in the provided buffer. */ |
55ff77ac | 1604 | /* Floating point registers map 1-1 to the media fp regs, |
7bb11558 | 1605 | they have the same size and endianness. */ |
05d1431c | 1606 | return regcache_raw_read (regcache, base_regnum, buffer); |
55ff77ac CV |
1607 | } |
1608 | ||
1609 | else if (reg_nr >= DR0_C_REGNUM | |
1610 | && reg_nr <= DR_LAST_C_REGNUM) | |
1611 | { | |
4a8a33c8 | 1612 | gdb_byte temp_buffer[8]; |
d93859e2 | 1613 | base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr); |
55ff77ac CV |
1614 | |
1615 | /* DR_C regs are double precision registers obtained by | |
7bb11558 | 1616 | concatenating 2 single precision floating point registers. */ |
05d1431c PA |
1617 | status = pseudo_register_read_portions (gdbarch, regcache, |
1618 | 2, base_regnum, temp_buffer); | |
1619 | if (status == REG_VALID) | |
1620 | { | |
1621 | /* We must pay attention to the endianness. */ | |
1622 | sh64_register_convert_to_virtual (gdbarch, reg_nr, | |
1623 | register_type (gdbarch, reg_nr), | |
1624 | temp_buffer, buffer); | |
1625 | } | |
1626 | return status; | |
55ff77ac CV |
1627 | } |
1628 | ||
1629 | else if (reg_nr >= FV0_C_REGNUM | |
1630 | && reg_nr <= FV_LAST_C_REGNUM) | |
1631 | { | |
d93859e2 | 1632 | base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr); |
55ff77ac | 1633 | |
7bb11558 | 1634 | /* Build the value in the provided buffer. */ |
55ff77ac | 1635 | /* FV_C regs are vectors of single precision registers obtained by |
7bb11558 | 1636 | concatenating 4 single precision floating point registers. */ |
05d1431c PA |
1637 | return pseudo_register_read_portions (gdbarch, regcache, |
1638 | 4, base_regnum, buffer); | |
55ff77ac CV |
1639 | } |
1640 | ||
1641 | else if (reg_nr == FPSCR_C_REGNUM) | |
1642 | { | |
1643 | int fpscr_base_regnum; | |
1644 | int sr_base_regnum; | |
4a8a33c8 AH |
1645 | ULONGEST fpscr_value; |
1646 | ULONGEST sr_value; | |
55ff77ac CV |
1647 | unsigned int fpscr_c_value; |
1648 | unsigned int fpscr_c_part1_value; | |
1649 | unsigned int fpscr_c_part2_value; | |
1650 | ||
1651 | fpscr_base_regnum = FPSCR_REGNUM; | |
1652 | sr_base_regnum = SR_REGNUM; | |
1653 | ||
7bb11558 | 1654 | /* Build the value in the provided buffer. */ |
55ff77ac CV |
1655 | /* FPSCR_C is a very weird register that contains sparse bits |
1656 | from the FPSCR and the SR architectural registers. | |
1657 | Specifically: */ | |
1658 | /* *INDENT-OFF* */ | |
1659 | /* | |
1660 | FPSRC_C bit | |
1661 | 0 Bit 0 of FPSCR | |
1662 | 1 reserved | |
1663 | 2-17 Bit 2-18 of FPSCR | |
1664 | 18-20 Bits 12,13,14 of SR | |
1665 | 21-31 reserved | |
1666 | */ | |
1667 | /* *INDENT-ON* */ | |
4a8a33c8 | 1668 | /* Get FPSCR as an int. */ |
6f98355c | 1669 | status = regcache->raw_read (fpscr_base_regnum, &fpscr_value); |
05d1431c PA |
1670 | if (status != REG_VALID) |
1671 | return status; | |
4a8a33c8 | 1672 | /* Get SR as an int. */ |
6f98355c | 1673 | status = regcache->raw_read (sr_base_regnum, &sr_value); |
05d1431c PA |
1674 | if (status != REG_VALID) |
1675 | return status; | |
7bb11558 | 1676 | /* Build the new value. */ |
55ff77ac CV |
1677 | fpscr_c_part1_value = fpscr_value & 0x3fffd; |
1678 | fpscr_c_part2_value = (sr_value & 0x7000) << 6; | |
1679 | fpscr_c_value = fpscr_c_part1_value | fpscr_c_part2_value; | |
c378eb4e | 1680 | /* Store that in out buffer!!! */ |
e17a4113 | 1681 | store_unsigned_integer (buffer, 4, byte_order, fpscr_c_value); |
7bb11558 | 1682 | /* FIXME There is surely an endianness gotcha here. */ |
05d1431c PA |
1683 | |
1684 | return REG_VALID; | |
55ff77ac CV |
1685 | } |
1686 | ||
1687 | else if (reg_nr == FPUL_C_REGNUM) | |
1688 | { | |
d93859e2 | 1689 | base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr); |
55ff77ac CV |
1690 | |
1691 | /* FPUL_C register is floating point register 32, | |
7bb11558 | 1692 | same size, same endianness. */ |
05d1431c | 1693 | return regcache_raw_read (regcache, base_regnum, buffer); |
55ff77ac | 1694 | } |
05d1431c PA |
1695 | else |
1696 | gdb_assert_not_reached ("invalid pseudo register number"); | |
55ff77ac CV |
1697 | } |
1698 | ||
1699 | static void | |
1700 | sh64_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
18cf8b5b | 1701 | int reg_nr, const gdb_byte *buffer) |
55ff77ac | 1702 | { |
e17a4113 | 1703 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
55ff77ac CV |
1704 | int base_regnum, portion; |
1705 | int offset; | |
55ff77ac CV |
1706 | |
1707 | if (reg_nr >= DR0_REGNUM | |
1708 | && reg_nr <= DR_LAST_REGNUM) | |
1709 | { | |
4a8a33c8 | 1710 | gdb_byte temp_buffer[8]; |
d93859e2 | 1711 | base_regnum = sh64_dr_reg_base_num (gdbarch, reg_nr); |
7bb11558 | 1712 | /* We must pay attention to the endianness. */ |
d93859e2 | 1713 | sh64_register_convert_to_raw (gdbarch, register_type (gdbarch, reg_nr), |
39add00a MS |
1714 | reg_nr, |
1715 | buffer, temp_buffer); | |
55ff77ac CV |
1716 | |
1717 | /* Write the real regs for which this one is an alias. */ | |
1718 | for (portion = 0; portion < 2; portion++) | |
1719 | regcache_raw_write (regcache, base_regnum + portion, | |
1720 | (temp_buffer | |
948f8e3d | 1721 | + register_size (gdbarch, |
7bb11558 | 1722 | base_regnum) * portion)); |
55ff77ac CV |
1723 | } |
1724 | ||
1725 | else if (reg_nr >= FPP0_REGNUM | |
1726 | && reg_nr <= FPP_LAST_REGNUM) | |
1727 | { | |
d93859e2 | 1728 | base_regnum = sh64_fpp_reg_base_num (gdbarch, reg_nr); |
55ff77ac CV |
1729 | |
1730 | /* Write the real regs for which this one is an alias. */ | |
1731 | for (portion = 0; portion < 2; portion++) | |
1732 | regcache_raw_write (regcache, base_regnum + portion, | |
948f8e3d PA |
1733 | (buffer + register_size (gdbarch, |
1734 | base_regnum) * portion)); | |
55ff77ac CV |
1735 | } |
1736 | ||
1737 | else if (reg_nr >= FV0_REGNUM | |
1738 | && reg_nr <= FV_LAST_REGNUM) | |
1739 | { | |
d93859e2 | 1740 | base_regnum = sh64_fv_reg_base_num (gdbarch, reg_nr); |
55ff77ac CV |
1741 | |
1742 | /* Write the real regs for which this one is an alias. */ | |
1743 | for (portion = 0; portion < 4; portion++) | |
1744 | regcache_raw_write (regcache, base_regnum + portion, | |
948f8e3d PA |
1745 | (buffer + register_size (gdbarch, |
1746 | base_regnum) * portion)); | |
55ff77ac CV |
1747 | } |
1748 | ||
c378eb4e | 1749 | /* sh compact general pseudo registers. 1-to-1 with a shmedia |
55ff77ac CV |
1750 | register but only 4 bytes of it. */ |
1751 | else if (reg_nr >= R0_C_REGNUM | |
1752 | && reg_nr <= T_C_REGNUM) | |
1753 | { | |
4a8a33c8 | 1754 | gdb_byte temp_buffer[8]; |
d93859e2 | 1755 | base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr); |
7bb11558 | 1756 | /* reg_nr is 32 bit here, and base_regnum is 64 bits. */ |
58643501 | 1757 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
55ff77ac CV |
1758 | offset = 4; |
1759 | else | |
1760 | offset = 0; | |
1761 | /* Let's read the value of the base register into a temporary | |
1762 | buffer, so that overwriting the last four bytes with the new | |
7bb11558 | 1763 | value of the pseudo will leave the upper 4 bytes unchanged. */ |
55ff77ac | 1764 | regcache_raw_read (regcache, base_regnum, temp_buffer); |
c378eb4e | 1765 | /* Write as an 8 byte quantity. */ |
55ff77ac CV |
1766 | memcpy (temp_buffer + offset, buffer, 4); |
1767 | regcache_raw_write (regcache, base_regnum, temp_buffer); | |
1768 | } | |
1769 | ||
c378eb4e MS |
1770 | /* sh floating point compact pseudo registers. 1-to-1 with a shmedia |
1771 | registers. Both are 4 bytes. */ | |
55ff77ac CV |
1772 | else if (reg_nr >= FP0_C_REGNUM |
1773 | && reg_nr <= FP_LAST_C_REGNUM) | |
1774 | { | |
d93859e2 | 1775 | base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr); |
55ff77ac CV |
1776 | regcache_raw_write (regcache, base_regnum, buffer); |
1777 | } | |
1778 | ||
1779 | else if (reg_nr >= DR0_C_REGNUM | |
1780 | && reg_nr <= DR_LAST_C_REGNUM) | |
1781 | { | |
4a8a33c8 | 1782 | gdb_byte temp_buffer[8]; |
d93859e2 | 1783 | base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr); |
55ff77ac CV |
1784 | for (portion = 0; portion < 2; portion++) |
1785 | { | |
7bb11558 | 1786 | /* We must pay attention to the endianness. */ |
d93859e2 UW |
1787 | sh64_register_convert_to_raw (gdbarch, |
1788 | register_type (gdbarch, reg_nr), | |
39add00a MS |
1789 | reg_nr, |
1790 | buffer, temp_buffer); | |
55ff77ac CV |
1791 | |
1792 | regcache_raw_write (regcache, base_regnum + portion, | |
1793 | (temp_buffer | |
7bb11558 MS |
1794 | + register_size (gdbarch, |
1795 | base_regnum) * portion)); | |
55ff77ac CV |
1796 | } |
1797 | } | |
1798 | ||
1799 | else if (reg_nr >= FV0_C_REGNUM | |
1800 | && reg_nr <= FV_LAST_C_REGNUM) | |
1801 | { | |
d93859e2 | 1802 | base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr); |
55ff77ac CV |
1803 | |
1804 | for (portion = 0; portion < 4; portion++) | |
1805 | { | |
1806 | regcache_raw_write (regcache, base_regnum + portion, | |
948f8e3d | 1807 | (buffer |
7bb11558 MS |
1808 | + register_size (gdbarch, |
1809 | base_regnum) * portion)); | |
55ff77ac CV |
1810 | } |
1811 | } | |
1812 | ||
1813 | else if (reg_nr == FPSCR_C_REGNUM) | |
1814 | { | |
1815 | int fpscr_base_regnum; | |
1816 | int sr_base_regnum; | |
4a8a33c8 AH |
1817 | ULONGEST fpscr_value; |
1818 | ULONGEST sr_value; | |
1819 | ULONGEST old_fpscr_value; | |
1820 | ULONGEST old_sr_value; | |
55ff77ac CV |
1821 | unsigned int fpscr_c_value; |
1822 | unsigned int fpscr_mask; | |
1823 | unsigned int sr_mask; | |
1824 | ||
1825 | fpscr_base_regnum = FPSCR_REGNUM; | |
1826 | sr_base_regnum = SR_REGNUM; | |
1827 | ||
1828 | /* FPSCR_C is a very weird register that contains sparse bits | |
1829 | from the FPSCR and the SR architectural registers. | |
1830 | Specifically: */ | |
1831 | /* *INDENT-OFF* */ | |
1832 | /* | |
1833 | FPSRC_C bit | |
1834 | 0 Bit 0 of FPSCR | |
1835 | 1 reserved | |
1836 | 2-17 Bit 2-18 of FPSCR | |
1837 | 18-20 Bits 12,13,14 of SR | |
1838 | 21-31 reserved | |
1839 | */ | |
1840 | /* *INDENT-ON* */ | |
7bb11558 | 1841 | /* Get value as an int. */ |
e17a4113 | 1842 | fpscr_c_value = extract_unsigned_integer (buffer, 4, byte_order); |
55ff77ac | 1843 | |
7bb11558 | 1844 | /* Build the new values. */ |
55ff77ac CV |
1845 | fpscr_mask = 0x0003fffd; |
1846 | sr_mask = 0x001c0000; | |
1847 | ||
1848 | fpscr_value = fpscr_c_value & fpscr_mask; | |
1849 | sr_value = (fpscr_value & sr_mask) >> 6; | |
1850 | ||
6f98355c | 1851 | regcache->raw_read (fpscr_base_regnum, &old_fpscr_value); |
55ff77ac CV |
1852 | old_fpscr_value &= 0xfffc0002; |
1853 | fpscr_value |= old_fpscr_value; | |
6f98355c | 1854 | regcache->raw_write (fpscr_base_regnum, fpscr_value); |
4a8a33c8 | 1855 | |
6f98355c | 1856 | regcache->raw_read (sr_base_regnum, &old_sr_value); |
55ff77ac CV |
1857 | old_sr_value &= 0xffff8fff; |
1858 | sr_value |= old_sr_value; | |
6f98355c | 1859 | regcache->raw_write (sr_base_regnum, sr_value); |
55ff77ac CV |
1860 | } |
1861 | ||
1862 | else if (reg_nr == FPUL_C_REGNUM) | |
1863 | { | |
d93859e2 | 1864 | base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr); |
55ff77ac CV |
1865 | regcache_raw_write (regcache, base_regnum, buffer); |
1866 | } | |
1867 | } | |
1868 | ||
55ff77ac | 1869 | /* FIXME:!! THIS SHOULD TAKE CARE OF GETTING THE RIGHT PORTION OF THE |
7bb11558 MS |
1870 | shmedia REGISTERS. */ |
1871 | /* Control registers, compact mode. */ | |
55ff77ac | 1872 | static void |
c30dc700 CV |
1873 | sh64_do_cr_c_register_info (struct ui_file *file, struct frame_info *frame, |
1874 | int cr_c_regnum) | |
55ff77ac CV |
1875 | { |
1876 | switch (cr_c_regnum) | |
1877 | { | |
c30dc700 CV |
1878 | case PC_C_REGNUM: |
1879 | fprintf_filtered (file, "pc_c\t0x%08x\n", | |
1880 | (int) get_frame_register_unsigned (frame, cr_c_regnum)); | |
55ff77ac | 1881 | break; |
c30dc700 CV |
1882 | case GBR_C_REGNUM: |
1883 | fprintf_filtered (file, "gbr_c\t0x%08x\n", | |
1884 | (int) get_frame_register_unsigned (frame, cr_c_regnum)); | |
55ff77ac | 1885 | break; |
c30dc700 CV |
1886 | case MACH_C_REGNUM: |
1887 | fprintf_filtered (file, "mach_c\t0x%08x\n", | |
1888 | (int) get_frame_register_unsigned (frame, cr_c_regnum)); | |
55ff77ac | 1889 | break; |
c30dc700 CV |
1890 | case MACL_C_REGNUM: |
1891 | fprintf_filtered (file, "macl_c\t0x%08x\n", | |
1892 | (int) get_frame_register_unsigned (frame, cr_c_regnum)); | |
55ff77ac | 1893 | break; |
c30dc700 CV |
1894 | case PR_C_REGNUM: |
1895 | fprintf_filtered (file, "pr_c\t0x%08x\n", | |
1896 | (int) get_frame_register_unsigned (frame, cr_c_regnum)); | |
55ff77ac | 1897 | break; |
c30dc700 CV |
1898 | case T_C_REGNUM: |
1899 | fprintf_filtered (file, "t_c\t0x%08x\n", | |
1900 | (int) get_frame_register_unsigned (frame, cr_c_regnum)); | |
55ff77ac | 1901 | break; |
c30dc700 CV |
1902 | case FPSCR_C_REGNUM: |
1903 | fprintf_filtered (file, "fpscr_c\t0x%08x\n", | |
1904 | (int) get_frame_register_unsigned (frame, cr_c_regnum)); | |
55ff77ac | 1905 | break; |
c30dc700 CV |
1906 | case FPUL_C_REGNUM: |
1907 | fprintf_filtered (file, "fpul_c\t0x%08x\n", | |
1908 | (int) get_frame_register_unsigned (frame, cr_c_regnum)); | |
55ff77ac CV |
1909 | break; |
1910 | } | |
1911 | } | |
1912 | ||
1913 | static void | |
c30dc700 CV |
1914 | sh64_do_fp_register (struct gdbarch *gdbarch, struct ui_file *file, |
1915 | struct frame_info *frame, int regnum) | |
c378eb4e | 1916 | { /* Do values for FP (float) regs. */ |
079c8cd0 | 1917 | unsigned char *raw_buffer; |
55ff77ac | 1918 | |
7bb11558 | 1919 | /* Allocate space for the float. */ |
c378eb4e MS |
1920 | raw_buffer = (unsigned char *) |
1921 | alloca (register_size (gdbarch, gdbarch_fp0_regnum (gdbarch))); | |
55ff77ac CV |
1922 | |
1923 | /* Get the data in raw format. */ | |
ca9d61b9 | 1924 | if (!deprecated_frame_register_read (frame, regnum, raw_buffer)) |
a73c6dcd | 1925 | error (_("can't read register %d (%s)"), |
58643501 | 1926 | regnum, gdbarch_register_name (gdbarch, regnum)); |
55ff77ac | 1927 | |
7bb11558 | 1928 | /* Print the name and some spaces. */ |
58643501 | 1929 | fputs_filtered (gdbarch_register_name (gdbarch, regnum), file); |
c9f4d572 | 1930 | print_spaces_filtered (15 - strlen (gdbarch_register_name |
58643501 | 1931 | (gdbarch, regnum)), file); |
55ff77ac | 1932 | |
7bb11558 | 1933 | /* Print the value. */ |
8ba0dd51 UW |
1934 | const struct floatformat *fmt |
1935 | = floatformat_from_type (builtin_type (gdbarch)->builtin_float); | |
1936 | std::string str = floatformat_to_string (fmt, raw_buffer, "%-10.9g"); | |
1937 | fprintf_filtered (file, "%s", str.c_str ()); | |
55ff77ac | 1938 | |
7bb11558 | 1939 | /* Print the fp register as hex. */ |
2cc762b5 AB |
1940 | fprintf_filtered (file, "\t(raw "); |
1941 | print_hex_chars (file, raw_buffer, | |
1942 | register_size (gdbarch, regnum), | |
30a25466 | 1943 | gdbarch_byte_order (gdbarch), true); |
55ff77ac CV |
1944 | fprintf_filtered (file, ")"); |
1945 | fprintf_filtered (file, "\n"); | |
1946 | } | |
1947 | ||
1948 | static void | |
c30dc700 CV |
1949 | sh64_do_pseudo_register (struct gdbarch *gdbarch, struct ui_file *file, |
1950 | struct frame_info *frame, int regnum) | |
55ff77ac | 1951 | { |
7bb11558 | 1952 | /* All the sh64-compact mode registers are pseudo registers. */ |
55ff77ac | 1953 | |
58643501 UW |
1954 | if (regnum < gdbarch_num_regs (gdbarch) |
1955 | || regnum >= gdbarch_num_regs (gdbarch) | |
f57d151a UW |
1956 | + NUM_PSEUDO_REGS_SH_MEDIA |
1957 | + NUM_PSEUDO_REGS_SH_COMPACT) | |
55ff77ac | 1958 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 1959 | _("Invalid pseudo register number %d\n"), regnum); |
55ff77ac | 1960 | |
c30dc700 CV |
1961 | else if ((regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)) |
1962 | { | |
d93859e2 | 1963 | int fp_regnum = sh64_dr_reg_base_num (gdbarch, regnum); |
c30dc700 CV |
1964 | fprintf_filtered (file, "dr%d\t0x%08x%08x\n", regnum - DR0_REGNUM, |
1965 | (unsigned) get_frame_register_unsigned (frame, fp_regnum), | |
1966 | (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1)); | |
1967 | } | |
55ff77ac | 1968 | |
c30dc700 CV |
1969 | else if ((regnum >= DR0_C_REGNUM && regnum <= DR_LAST_C_REGNUM)) |
1970 | { | |
d93859e2 | 1971 | int fp_regnum = sh64_compact_reg_base_num (gdbarch, regnum); |
c30dc700 CV |
1972 | fprintf_filtered (file, "dr%d_c\t0x%08x%08x\n", regnum - DR0_C_REGNUM, |
1973 | (unsigned) get_frame_register_unsigned (frame, fp_regnum), | |
1974 | (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1)); | |
1975 | } | |
55ff77ac | 1976 | |
c30dc700 CV |
1977 | else if ((regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM)) |
1978 | { | |
d93859e2 | 1979 | int fp_regnum = sh64_fv_reg_base_num (gdbarch, regnum); |
c30dc700 CV |
1980 | fprintf_filtered (file, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n", |
1981 | regnum - FV0_REGNUM, | |
1982 | (unsigned) get_frame_register_unsigned (frame, fp_regnum), | |
1983 | (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1), | |
1984 | (unsigned) get_frame_register_unsigned (frame, fp_regnum + 2), | |
1985 | (unsigned) get_frame_register_unsigned (frame, fp_regnum + 3)); | |
1986 | } | |
55ff77ac | 1987 | |
c30dc700 CV |
1988 | else if ((regnum >= FV0_C_REGNUM && regnum <= FV_LAST_C_REGNUM)) |
1989 | { | |
d93859e2 | 1990 | int fp_regnum = sh64_compact_reg_base_num (gdbarch, regnum); |
c30dc700 CV |
1991 | fprintf_filtered (file, "fv%d_c\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n", |
1992 | regnum - FV0_C_REGNUM, | |
1993 | (unsigned) get_frame_register_unsigned (frame, fp_regnum), | |
1994 | (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1), | |
1995 | (unsigned) get_frame_register_unsigned (frame, fp_regnum + 2), | |
1996 | (unsigned) get_frame_register_unsigned (frame, fp_regnum + 3)); | |
1997 | } | |
1998 | ||
1999 | else if (regnum >= FPP0_REGNUM && regnum <= FPP_LAST_REGNUM) | |
2000 | { | |
d93859e2 | 2001 | int fp_regnum = sh64_fpp_reg_base_num (gdbarch, regnum); |
c30dc700 CV |
2002 | fprintf_filtered (file, "fpp%d\t0x%08x\t0x%08x\n", regnum - FPP0_REGNUM, |
2003 | (unsigned) get_frame_register_unsigned (frame, fp_regnum), | |
2004 | (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1)); | |
2005 | } | |
2006 | ||
2007 | else if (regnum >= R0_C_REGNUM && regnum <= R_LAST_C_REGNUM) | |
2008 | { | |
d93859e2 | 2009 | int c_regnum = sh64_compact_reg_base_num (gdbarch, regnum); |
c30dc700 CV |
2010 | fprintf_filtered (file, "r%d_c\t0x%08x\n", regnum - R0_C_REGNUM, |
2011 | (unsigned) get_frame_register_unsigned (frame, c_regnum)); | |
2012 | } | |
2013 | else if (regnum >= FP0_C_REGNUM && regnum <= FP_LAST_C_REGNUM) | |
7bb11558 | 2014 | /* This should work also for pseudoregs. */ |
c30dc700 CV |
2015 | sh64_do_fp_register (gdbarch, file, frame, regnum); |
2016 | else if (regnum >= PC_C_REGNUM && regnum <= FPUL_C_REGNUM) | |
2017 | sh64_do_cr_c_register_info (file, frame, regnum); | |
55ff77ac CV |
2018 | } |
2019 | ||
2020 | static void | |
c30dc700 CV |
2021 | sh64_do_register (struct gdbarch *gdbarch, struct ui_file *file, |
2022 | struct frame_info *frame, int regnum) | |
55ff77ac | 2023 | { |
79a45b7d | 2024 | struct value_print_options opts; |
cc977dc7 | 2025 | struct value *val; |
55ff77ac | 2026 | |
58643501 | 2027 | fputs_filtered (gdbarch_register_name (gdbarch, regnum), file); |
c9f4d572 | 2028 | print_spaces_filtered (15 - strlen (gdbarch_register_name |
58643501 | 2029 | (gdbarch, regnum)), file); |
55ff77ac CV |
2030 | |
2031 | /* Get the data in raw format. */ | |
cc977dc7 YQ |
2032 | val = get_frame_register_value (frame, regnum); |
2033 | if (value_optimized_out (val) || !value_entirely_available (val)) | |
47061676 AB |
2034 | { |
2035 | fprintf_filtered (file, "*value not available*\n"); | |
2036 | return; | |
2037 | } | |
79a45b7d TT |
2038 | |
2039 | get_formatted_print_options (&opts, 'x'); | |
2040 | opts.deref_ref = 1; | |
cc977dc7 | 2041 | val_print (register_type (gdbarch, regnum), |
e8b24d9f | 2042 | 0, 0, |
cc977dc7 | 2043 | file, 0, val, &opts, current_language); |
55ff77ac | 2044 | fprintf_filtered (file, "\t"); |
79a45b7d TT |
2045 | get_formatted_print_options (&opts, 0); |
2046 | opts.deref_ref = 1; | |
cc977dc7 | 2047 | val_print (register_type (gdbarch, regnum), |
e8b24d9f | 2048 | 0, 0, |
cc977dc7 | 2049 | file, 0, val, &opts, current_language); |
55ff77ac CV |
2050 | fprintf_filtered (file, "\n"); |
2051 | } | |
2052 | ||
2053 | static void | |
c30dc700 CV |
2054 | sh64_print_register (struct gdbarch *gdbarch, struct ui_file *file, |
2055 | struct frame_info *frame, int regnum) | |
55ff77ac | 2056 | { |
58643501 UW |
2057 | if (regnum < 0 || regnum >= gdbarch_num_regs (gdbarch) |
2058 | + gdbarch_num_pseudo_regs (gdbarch)) | |
55ff77ac | 2059 | internal_error (__FILE__, __LINE__, |
e2e0b3e5 | 2060 | _("Invalid register number %d\n"), regnum); |
55ff77ac | 2061 | |
58643501 | 2062 | else if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)) |
55ff77ac | 2063 | { |
7b9ee6a8 | 2064 | if (TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT) |
c30dc700 | 2065 | sh64_do_fp_register (gdbarch, file, frame, regnum); /* FP regs */ |
55ff77ac | 2066 | else |
c30dc700 | 2067 | sh64_do_register (gdbarch, file, frame, regnum); |
55ff77ac CV |
2068 | } |
2069 | ||
58643501 UW |
2070 | else if (regnum < gdbarch_num_regs (gdbarch) |
2071 | + gdbarch_num_pseudo_regs (gdbarch)) | |
c30dc700 | 2072 | sh64_do_pseudo_register (gdbarch, file, frame, regnum); |
55ff77ac CV |
2073 | } |
2074 | ||
2075 | static void | |
c30dc700 CV |
2076 | sh64_media_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
2077 | struct frame_info *frame, int regnum, | |
2078 | int fpregs) | |
55ff77ac | 2079 | { |
c378eb4e | 2080 | if (regnum != -1) /* Do one specified register. */ |
55ff77ac | 2081 | { |
58643501 | 2082 | if (*(gdbarch_register_name (gdbarch, regnum)) == '\0') |
a73c6dcd | 2083 | error (_("Not a valid register for the current processor type")); |
55ff77ac | 2084 | |
c30dc700 | 2085 | sh64_print_register (gdbarch, file, frame, regnum); |
55ff77ac CV |
2086 | } |
2087 | else | |
c378eb4e | 2088 | /* Do all (or most) registers. */ |
55ff77ac CV |
2089 | { |
2090 | regnum = 0; | |
58643501 | 2091 | while (regnum < gdbarch_num_regs (gdbarch)) |
55ff77ac CV |
2092 | { |
2093 | /* If the register name is empty, it is undefined for this | |
2094 | processor, so don't display anything. */ | |
58643501 UW |
2095 | if (gdbarch_register_name (gdbarch, regnum) == NULL |
2096 | || *(gdbarch_register_name (gdbarch, regnum)) == '\0') | |
55ff77ac CV |
2097 | { |
2098 | regnum++; | |
2099 | continue; | |
2100 | } | |
2101 | ||
7b9ee6a8 | 2102 | if (TYPE_CODE (register_type (gdbarch, regnum)) |
c30dc700 | 2103 | == TYPE_CODE_FLT) |
55ff77ac CV |
2104 | { |
2105 | if (fpregs) | |
2106 | { | |
c378eb4e | 2107 | /* true for "INFO ALL-REGISTERS" command. */ |
c30dc700 | 2108 | sh64_do_fp_register (gdbarch, file, frame, regnum); |
55ff77ac CV |
2109 | regnum ++; |
2110 | } | |
2111 | else | |
58643501 | 2112 | regnum += FP_LAST_REGNUM - gdbarch_fp0_regnum (gdbarch); |
3e8c568d | 2113 | /* skip FP regs */ |
55ff77ac CV |
2114 | } |
2115 | else | |
2116 | { | |
c30dc700 | 2117 | sh64_do_register (gdbarch, file, frame, regnum); |
55ff77ac CV |
2118 | regnum++; |
2119 | } | |
2120 | } | |
2121 | ||
2122 | if (fpregs) | |
58643501 UW |
2123 | while (regnum < gdbarch_num_regs (gdbarch) |
2124 | + gdbarch_num_pseudo_regs (gdbarch)) | |
55ff77ac | 2125 | { |
c30dc700 | 2126 | sh64_do_pseudo_register (gdbarch, file, frame, regnum); |
55ff77ac CV |
2127 | regnum++; |
2128 | } | |
2129 | } | |
2130 | } | |
2131 | ||
2132 | static void | |
c30dc700 CV |
2133 | sh64_compact_print_registers_info (struct gdbarch *gdbarch, |
2134 | struct ui_file *file, | |
2135 | struct frame_info *frame, int regnum, | |
2136 | int fpregs) | |
55ff77ac | 2137 | { |
c378eb4e | 2138 | if (regnum != -1) /* Do one specified register. */ |
55ff77ac | 2139 | { |
58643501 | 2140 | if (*(gdbarch_register_name (gdbarch, regnum)) == '\0') |
a73c6dcd | 2141 | error (_("Not a valid register for the current processor type")); |
55ff77ac CV |
2142 | |
2143 | if (regnum >= 0 && regnum < R0_C_REGNUM) | |
a73c6dcd | 2144 | error (_("Not a valid register for the current processor mode.")); |
55ff77ac | 2145 | |
c30dc700 | 2146 | sh64_print_register (gdbarch, file, frame, regnum); |
55ff77ac CV |
2147 | } |
2148 | else | |
c378eb4e | 2149 | /* Do all compact registers. */ |
55ff77ac CV |
2150 | { |
2151 | regnum = R0_C_REGNUM; | |
58643501 UW |
2152 | while (regnum < gdbarch_num_regs (gdbarch) |
2153 | + gdbarch_num_pseudo_regs (gdbarch)) | |
55ff77ac | 2154 | { |
c30dc700 | 2155 | sh64_do_pseudo_register (gdbarch, file, frame, regnum); |
55ff77ac CV |
2156 | regnum++; |
2157 | } | |
2158 | } | |
2159 | } | |
2160 | ||
2161 | static void | |
c30dc700 CV |
2162 | sh64_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
2163 | struct frame_info *frame, int regnum, int fpregs) | |
55ff77ac | 2164 | { |
c30dc700 CV |
2165 | if (pc_is_isa32 (get_frame_pc (frame))) |
2166 | sh64_media_print_registers_info (gdbarch, file, frame, regnum, fpregs); | |
55ff77ac | 2167 | else |
c30dc700 | 2168 | sh64_compact_print_registers_info (gdbarch, file, frame, regnum, fpregs); |
55ff77ac CV |
2169 | } |
2170 | ||
c30dc700 CV |
2171 | static struct sh64_frame_cache * |
2172 | sh64_alloc_frame_cache (void) | |
2173 | { | |
2174 | struct sh64_frame_cache *cache; | |
2175 | int i; | |
2176 | ||
2177 | cache = FRAME_OBSTACK_ZALLOC (struct sh64_frame_cache); | |
2178 | ||
2179 | /* Base address. */ | |
2180 | cache->base = 0; | |
2181 | cache->saved_sp = 0; | |
2182 | cache->sp_offset = 0; | |
2183 | cache->pc = 0; | |
55ff77ac | 2184 | |
c30dc700 CV |
2185 | /* Frameless until proven otherwise. */ |
2186 | cache->uses_fp = 0; | |
55ff77ac | 2187 | |
c30dc700 CV |
2188 | /* Saved registers. We initialize these to -1 since zero is a valid |
2189 | offset (that's where fp is supposed to be stored). */ | |
2190 | for (i = 0; i < SIM_SH64_NR_REGS; i++) | |
2191 | { | |
2192 | cache->saved_regs[i] = -1; | |
2193 | } | |
2194 | ||
2195 | return cache; | |
2196 | } | |
2197 | ||
2198 | static struct sh64_frame_cache * | |
94afd7a6 | 2199 | sh64_frame_cache (struct frame_info *this_frame, void **this_cache) |
55ff77ac | 2200 | { |
58643501 | 2201 | struct gdbarch *gdbarch; |
c30dc700 CV |
2202 | struct sh64_frame_cache *cache; |
2203 | CORE_ADDR current_pc; | |
2204 | int i; | |
55ff77ac | 2205 | |
c30dc700 | 2206 | if (*this_cache) |
19ba03f4 | 2207 | return (struct sh64_frame_cache *) *this_cache; |
c30dc700 | 2208 | |
94afd7a6 | 2209 | gdbarch = get_frame_arch (this_frame); |
c30dc700 CV |
2210 | cache = sh64_alloc_frame_cache (); |
2211 | *this_cache = cache; | |
2212 | ||
94afd7a6 | 2213 | current_pc = get_frame_pc (this_frame); |
c30dc700 CV |
2214 | cache->media_mode = pc_is_isa32 (current_pc); |
2215 | ||
2216 | /* In principle, for normal frames, fp holds the frame pointer, | |
2217 | which holds the base address for the current stack frame. | |
2218 | However, for functions that don't need it, the frame pointer is | |
2219 | optional. For these "frameless" functions the frame pointer is | |
c378eb4e | 2220 | actually the frame pointer of the calling frame. */ |
94afd7a6 | 2221 | cache->base = get_frame_register_unsigned (this_frame, MEDIA_FP_REGNUM); |
c30dc700 CV |
2222 | if (cache->base == 0) |
2223 | return cache; | |
2224 | ||
94afd7a6 | 2225 | cache->pc = get_frame_func (this_frame); |
c30dc700 | 2226 | if (cache->pc != 0) |
58643501 | 2227 | sh64_analyze_prologue (gdbarch, cache, cache->pc, current_pc); |
c30dc700 CV |
2228 | |
2229 | if (!cache->uses_fp) | |
55ff77ac | 2230 | { |
c30dc700 CV |
2231 | /* We didn't find a valid frame, which means that CACHE->base |
2232 | currently holds the frame pointer for our calling frame. If | |
2233 | we're at the start of a function, or somewhere half-way its | |
2234 | prologue, the function's frame probably hasn't been fully | |
2235 | setup yet. Try to reconstruct the base address for the stack | |
2236 | frame by looking at the stack pointer. For truly "frameless" | |
2237 | functions this might work too. */ | |
94afd7a6 UW |
2238 | cache->base = get_frame_register_unsigned |
2239 | (this_frame, gdbarch_sp_regnum (gdbarch)); | |
c30dc700 | 2240 | } |
55ff77ac | 2241 | |
c30dc700 CV |
2242 | /* Now that we have the base address for the stack frame we can |
2243 | calculate the value of sp in the calling frame. */ | |
2244 | cache->saved_sp = cache->base + cache->sp_offset; | |
55ff77ac | 2245 | |
c30dc700 CV |
2246 | /* Adjust all the saved registers such that they contain addresses |
2247 | instead of offsets. */ | |
2248 | for (i = 0; i < SIM_SH64_NR_REGS; i++) | |
2249 | if (cache->saved_regs[i] != -1) | |
2250 | cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i]; | |
55ff77ac | 2251 | |
c30dc700 CV |
2252 | return cache; |
2253 | } | |
55ff77ac | 2254 | |
94afd7a6 UW |
2255 | static struct value * |
2256 | sh64_frame_prev_register (struct frame_info *this_frame, | |
2257 | void **this_cache, int regnum) | |
c30dc700 | 2258 | { |
94afd7a6 UW |
2259 | struct sh64_frame_cache *cache = sh64_frame_cache (this_frame, this_cache); |
2260 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
e17a4113 | 2261 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
55ff77ac | 2262 | |
c30dc700 | 2263 | gdb_assert (regnum >= 0); |
55ff77ac | 2264 | |
58643501 | 2265 | if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp) |
94afd7a6 | 2266 | frame_unwind_got_constant (this_frame, regnum, cache->saved_sp); |
c30dc700 CV |
2267 | |
2268 | /* The PC of the previous frame is stored in the PR register of | |
2269 | the current frame. Frob regnum so that we pull the value from | |
2270 | the correct place. */ | |
58643501 | 2271 | if (regnum == gdbarch_pc_regnum (gdbarch)) |
c30dc700 CV |
2272 | regnum = PR_REGNUM; |
2273 | ||
2274 | if (regnum < SIM_SH64_NR_REGS && cache->saved_regs[regnum] != -1) | |
2275 | { | |
58643501 | 2276 | if (gdbarch_tdep (gdbarch)->sh_abi == SH_ABI_32 |
c30dc700 | 2277 | && (regnum == MEDIA_FP_REGNUM || regnum == PR_REGNUM)) |
c30dc700 | 2278 | { |
94afd7a6 | 2279 | CORE_ADDR val; |
e17a4113 UW |
2280 | val = read_memory_unsigned_integer (cache->saved_regs[regnum], |
2281 | 4, byte_order); | |
94afd7a6 | 2282 | return frame_unwind_got_constant (this_frame, regnum, val); |
c30dc700 | 2283 | } |
94afd7a6 UW |
2284 | |
2285 | return frame_unwind_got_memory (this_frame, regnum, | |
2286 | cache->saved_regs[regnum]); | |
55ff77ac CV |
2287 | } |
2288 | ||
94afd7a6 | 2289 | return frame_unwind_got_register (this_frame, regnum, regnum); |
55ff77ac | 2290 | } |
55ff77ac | 2291 | |
c30dc700 | 2292 | static void |
94afd7a6 | 2293 | sh64_frame_this_id (struct frame_info *this_frame, void **this_cache, |
c30dc700 CV |
2294 | struct frame_id *this_id) |
2295 | { | |
94afd7a6 | 2296 | struct sh64_frame_cache *cache = sh64_frame_cache (this_frame, this_cache); |
c30dc700 CV |
2297 | |
2298 | /* This marks the outermost frame. */ | |
2299 | if (cache->base == 0) | |
2300 | return; | |
2301 | ||
2302 | *this_id = frame_id_build (cache->saved_sp, cache->pc); | |
2303 | } | |
2304 | ||
2305 | static const struct frame_unwind sh64_frame_unwind = { | |
2306 | NORMAL_FRAME, | |
8fbca658 | 2307 | default_frame_unwind_stop_reason, |
c30dc700 | 2308 | sh64_frame_this_id, |
94afd7a6 UW |
2309 | sh64_frame_prev_register, |
2310 | NULL, | |
2311 | default_frame_sniffer | |
c30dc700 CV |
2312 | }; |
2313 | ||
c30dc700 CV |
2314 | static CORE_ADDR |
2315 | sh64_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
2316 | { | |
3e8c568d | 2317 | return frame_unwind_register_unsigned (next_frame, |
58643501 | 2318 | gdbarch_sp_regnum (gdbarch)); |
c30dc700 CV |
2319 | } |
2320 | ||
2321 | static CORE_ADDR | |
2322 | sh64_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
2323 | { | |
3e8c568d | 2324 | return frame_unwind_register_unsigned (next_frame, |
58643501 | 2325 | gdbarch_pc_regnum (gdbarch)); |
c30dc700 CV |
2326 | } |
2327 | ||
2328 | static struct frame_id | |
94afd7a6 | 2329 | sh64_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
c30dc700 | 2330 | { |
94afd7a6 UW |
2331 | CORE_ADDR sp = get_frame_register_unsigned (this_frame, |
2332 | gdbarch_sp_regnum (gdbarch)); | |
2333 | return frame_id_build (sp, get_frame_pc (this_frame)); | |
c30dc700 CV |
2334 | } |
2335 | ||
2336 | static CORE_ADDR | |
94afd7a6 | 2337 | sh64_frame_base_address (struct frame_info *this_frame, void **this_cache) |
c30dc700 | 2338 | { |
94afd7a6 | 2339 | struct sh64_frame_cache *cache = sh64_frame_cache (this_frame, this_cache); |
c30dc700 CV |
2340 | |
2341 | return cache->base; | |
2342 | } | |
2343 | ||
2344 | static const struct frame_base sh64_frame_base = { | |
2345 | &sh64_frame_unwind, | |
2346 | sh64_frame_base_address, | |
2347 | sh64_frame_base_address, | |
2348 | sh64_frame_base_address | |
2349 | }; | |
2350 | ||
55ff77ac CV |
2351 | |
2352 | struct gdbarch * | |
2353 | sh64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
2354 | { | |
55ff77ac CV |
2355 | struct gdbarch *gdbarch; |
2356 | struct gdbarch_tdep *tdep; | |
2357 | ||
2358 | /* If there is already a candidate, use it. */ | |
2359 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
2360 | if (arches != NULL) | |
2361 | return arches->gdbarch; | |
2362 | ||
2363 | /* None found, create a new architecture from the information | |
7bb11558 | 2364 | provided. */ |
cdd238da | 2365 | tdep = XCNEW (struct gdbarch_tdep); |
55ff77ac CV |
2366 | gdbarch = gdbarch_alloc (&info, tdep); |
2367 | ||
55ff77ac CV |
2368 | /* Determine the ABI */ |
2369 | if (info.abfd && bfd_get_arch_size (info.abfd) == 64) | |
2370 | { | |
7bb11558 | 2371 | /* If the ABI is the 64-bit one, it can only be sh-media. */ |
55ff77ac CV |
2372 | tdep->sh_abi = SH_ABI_64; |
2373 | set_gdbarch_ptr_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
2374 | set_gdbarch_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
2375 | } | |
2376 | else | |
2377 | { | |
2378 | /* If the ABI is the 32-bit one it could be either media or | |
7bb11558 | 2379 | compact. */ |
55ff77ac CV |
2380 | tdep->sh_abi = SH_ABI_32; |
2381 | set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
2382 | set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
2383 | } | |
2384 | ||
2385 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); | |
2386 | set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
c30dc700 | 2387 | set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); |
55ff77ac CV |
2388 | set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); |
2389 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
2390 | set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
2391 | set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
2392 | ||
c30dc700 CV |
2393 | /* The number of real registers is the same whether we are in |
2394 | ISA16(compact) or ISA32(media). */ | |
2395 | set_gdbarch_num_regs (gdbarch, SIM_SH64_NR_REGS); | |
55ff77ac | 2396 | set_gdbarch_sp_regnum (gdbarch, 15); |
c30dc700 CV |
2397 | set_gdbarch_pc_regnum (gdbarch, 64); |
2398 | set_gdbarch_fp0_regnum (gdbarch, SIM_SH64_FR0_REGNUM); | |
2399 | set_gdbarch_num_pseudo_regs (gdbarch, NUM_PSEUDO_REGS_SH_MEDIA | |
2400 | + NUM_PSEUDO_REGS_SH_COMPACT); | |
55ff77ac | 2401 | |
c30dc700 CV |
2402 | set_gdbarch_register_name (gdbarch, sh64_register_name); |
2403 | set_gdbarch_register_type (gdbarch, sh64_register_type); | |
2404 | ||
2405 | set_gdbarch_pseudo_register_read (gdbarch, sh64_pseudo_register_read); | |
2406 | set_gdbarch_pseudo_register_write (gdbarch, sh64_pseudo_register_write); | |
2407 | ||
04180708 YQ |
2408 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, sh64_breakpoint_kind_from_pc); |
2409 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, sh64_sw_breakpoint_from_kind); | |
55ff77ac CV |
2410 | set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno); |
2411 | ||
c30dc700 | 2412 | set_gdbarch_return_value (gdbarch, sh64_return_value); |
55ff77ac | 2413 | |
c30dc700 CV |
2414 | set_gdbarch_skip_prologue (gdbarch, sh64_skip_prologue); |
2415 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
55ff77ac | 2416 | |
c30dc700 | 2417 | set_gdbarch_push_dummy_call (gdbarch, sh64_push_dummy_call); |
55ff77ac | 2418 | |
c30dc700 | 2419 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); |
55ff77ac | 2420 | |
c30dc700 CV |
2421 | set_gdbarch_frame_align (gdbarch, sh64_frame_align); |
2422 | set_gdbarch_unwind_sp (gdbarch, sh64_unwind_sp); | |
2423 | set_gdbarch_unwind_pc (gdbarch, sh64_unwind_pc); | |
94afd7a6 | 2424 | set_gdbarch_dummy_id (gdbarch, sh64_dummy_id); |
c30dc700 | 2425 | frame_base_set_default (gdbarch, &sh64_frame_base); |
55ff77ac | 2426 | |
c30dc700 | 2427 | set_gdbarch_print_registers_info (gdbarch, sh64_print_registers_info); |
55ff77ac | 2428 | |
55ff77ac CV |
2429 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
2430 | sh64_elf_make_msymbol_special); | |
2431 | ||
2432 | /* Hook in ABI-specific overrides, if they have been registered. */ | |
2433 | gdbarch_init_osabi (info, gdbarch); | |
2434 | ||
94afd7a6 UW |
2435 | dwarf2_append_unwinders (gdbarch); |
2436 | frame_unwind_append_unwinder (gdbarch, &sh64_frame_unwind); | |
c30dc700 | 2437 | |
55ff77ac CV |
2438 | return gdbarch; |
2439 | } |