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55ff77ac CV |
1 | /* Target-dependent code for Hitachi Super-H, for GDB. |
2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 | |
3 | Free Software Foundation, Inc. | |
4 | ||
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
21 | ||
22 | /* | |
23 | Contributed by Steve Chamberlain | |
24 | sac@cygnus.com | |
25 | */ | |
26 | ||
27 | #include "defs.h" | |
28 | #include "frame.h" | |
29 | #include "symtab.h" | |
30 | #include "symfile.h" | |
31 | #include "gdbtypes.h" | |
32 | #include "gdbcmd.h" | |
33 | #include "gdbcore.h" | |
34 | #include "value.h" | |
35 | #include "dis-asm.h" | |
36 | #include "inferior.h" | |
37 | #include "gdb_string.h" | |
38 | #include "arch-utils.h" | |
39 | #include "floatformat.h" | |
40 | #include "regcache.h" | |
41 | #include "doublest.h" | |
42 | #include "osabi.h" | |
43 | ||
44 | #include "elf-bfd.h" | |
45 | #include "solib-svr4.h" | |
46 | ||
47 | /* sh flags */ | |
48 | #include "elf/sh.h" | |
49 | /* registers numbers shared with the simulator */ | |
50 | #include "gdb/sim-sh.h" | |
51 | ||
52 | /* Information that is dependent on the processor variant. */ | |
53 | enum sh_abi | |
54 | { | |
55 | SH_ABI_UNKNOWN, | |
56 | SH_ABI_32, | |
57 | SH_ABI_64 | |
58 | }; | |
59 | ||
60 | struct gdbarch_tdep | |
61 | { | |
62 | enum sh_abi sh_abi; | |
63 | }; | |
64 | ||
65 | /* Registers of SH5 */ | |
66 | enum | |
67 | { | |
68 | R0_REGNUM = 0, | |
69 | DEFAULT_RETURN_REGNUM = 2, | |
70 | STRUCT_RETURN_REGNUM = 2, | |
71 | ARG0_REGNUM = 2, | |
72 | ARGLAST_REGNUM = 9, | |
73 | FLOAT_ARGLAST_REGNUM = 11, | |
74 | PR_REGNUM = 18, | |
75 | SR_REGNUM = 65, | |
76 | DR0_REGNUM = 141, | |
77 | DR_LAST_REGNUM = 172, | |
78 | /* FPP stands for Floating Point Pair, to avoid confusion with | |
79 | GDB's FP0_REGNUM, which is the number of the first Floating | |
80 | point register. Unfortunately on the sh5, the floating point | |
81 | registers are called FR, and the floating point pairs are called FP. */ | |
82 | FPP0_REGNUM = 173, | |
83 | FPP_LAST_REGNUM = 204, | |
84 | FV0_REGNUM = 205, | |
85 | FV_LAST_REGNUM = 220, | |
86 | R0_C_REGNUM = 221, | |
87 | R_LAST_C_REGNUM = 236, | |
88 | PC_C_REGNUM = 237, | |
89 | GBR_C_REGNUM = 238, | |
90 | MACH_C_REGNUM = 239, | |
91 | MACL_C_REGNUM = 240, | |
92 | PR_C_REGNUM = 241, | |
93 | T_C_REGNUM = 242, | |
94 | FPSCR_C_REGNUM = 243, | |
95 | FPUL_C_REGNUM = 244, | |
96 | FP0_C_REGNUM = 245, | |
97 | FP_LAST_C_REGNUM = 260, | |
98 | DR0_C_REGNUM = 261, | |
99 | DR_LAST_C_REGNUM = 268, | |
100 | FV0_C_REGNUM = 269, | |
101 | FV_LAST_C_REGNUM = 272, | |
102 | FPSCR_REGNUM = SIM_SH64_FPCSR_REGNUM, | |
103 | SSR_REGNUM = SIM_SH64_SSR_REGNUM, | |
104 | SPC_REGNUM = SIM_SH64_SPC_REGNUM, | |
105 | TR7_REGNUM = SIM_SH64_TR0_REGNUM + 7, | |
106 | FP_LAST_REGNUM = SIM_SH64_FR0_REGNUM + SIM_SH64_NR_FP_REGS - 1 | |
107 | }; | |
108 | ||
109 | ||
110 | /* Define other aspects of the stack frame. | |
111 | we keep a copy of the worked out return pc lying around, since it | |
112 | is a useful bit of info */ | |
113 | ||
114 | struct frame_extra_info | |
115 | { | |
116 | CORE_ADDR return_pc; | |
117 | int leaf_function; | |
118 | int f_offset; | |
119 | }; | |
120 | ||
121 | static const char * | |
122 | sh_sh64_register_name (int reg_nr) | |
123 | { | |
124 | static char *register_names[] = | |
125 | { | |
126 | /* SH MEDIA MODE (ISA 32) */ | |
127 | /* general registers (64-bit) 0-63 */ | |
128 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
129 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
130 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
131 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", | |
132 | "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", | |
133 | "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", | |
134 | "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", | |
135 | "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", | |
136 | ||
137 | /* pc (64-bit) 64 */ | |
138 | "pc", | |
139 | ||
140 | /* status reg., saved status reg., saved pc reg. (64-bit) 65-67 */ | |
141 | "sr", "ssr", "spc", | |
142 | ||
143 | /* target registers (64-bit) 68-75*/ | |
144 | "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", | |
145 | ||
146 | /* floating point state control register (32-bit) 76 */ | |
147 | "fpscr", | |
148 | ||
149 | /* single precision floating point registers (32-bit) 77-140*/ | |
150 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", | |
151 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
152 | "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", | |
153 | "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", | |
154 | "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", | |
155 | "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", | |
156 | "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", | |
157 | "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", | |
158 | ||
159 | /* double precision registers (pseudo) 141-172 */ | |
160 | "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", | |
161 | "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", | |
162 | "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", | |
163 | "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62", | |
164 | ||
165 | /* floating point pairs (pseudo) 173-204*/ | |
166 | "fp0", "fp2", "fp4", "fp6", "fp8", "fp10", "fp12", "fp14", | |
167 | "fp16", "fp18", "fp20", "fp22", "fp24", "fp26", "fp28", "fp30", | |
168 | "fp32", "fp34", "fp36", "fp38", "fp40", "fp42", "fp44", "fp46", | |
169 | "fp48", "fp50", "fp52", "fp54", "fp56", "fp58", "fp60", "fp62", | |
170 | ||
171 | /* floating point vectors (4 floating point regs) (pseudo) 205-220*/ | |
172 | "fv0", "fv4", "fv8", "fv12", "fv16", "fv20", "fv24", "fv28", | |
173 | "fv32", "fv36", "fv40", "fv44", "fv48", "fv52", "fv56", "fv60", | |
174 | ||
175 | /* SH COMPACT MODE (ISA 16) (all pseudo) 221-272*/ | |
176 | "r0_c", "r1_c", "r2_c", "r3_c", "r4_c", "r5_c", "r6_c", "r7_c", | |
177 | "r8_c", "r9_c", "r10_c", "r11_c", "r12_c", "r13_c", "r14_c", "r15_c", | |
178 | "pc_c", | |
179 | "gbr_c", "mach_c", "macl_c", "pr_c", "t_c", | |
180 | "fpscr_c", "fpul_c", | |
181 | "fr0_c", "fr1_c", "fr2_c", "fr3_c", "fr4_c", "fr5_c", "fr6_c", "fr7_c", | |
182 | "fr8_c", "fr9_c", "fr10_c", "fr11_c", "fr12_c", "fr13_c", "fr14_c", "fr15_c", | |
183 | "dr0_c", "dr2_c", "dr4_c", "dr6_c", "dr8_c", "dr10_c", "dr12_c", "dr14_c", | |
184 | "fv0_c", "fv4_c", "fv8_c", "fv12_c", | |
185 | /* FIXME!!!! XF0 XF15, XD0 XD14 ?????*/ | |
186 | }; | |
187 | ||
188 | if (reg_nr < 0) | |
189 | return NULL; | |
190 | if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) | |
191 | return NULL; | |
192 | return register_names[reg_nr]; | |
193 | } | |
194 | ||
195 | #define NUM_PSEUDO_REGS_SH_MEDIA 80 | |
196 | #define NUM_PSEUDO_REGS_SH_COMPACT 51 | |
197 | ||
198 | /* Macros and functions for setting and testing a bit in a minimal | |
199 | symbol that marks it as 32-bit function. The MSB of the minimal | |
200 | symbol's "info" field is used for this purpose. This field is | |
201 | already being used to store the symbol size, so the assumption is | |
202 | that the symbol size cannot exceed 2^31. | |
203 | ||
204 | ELF_MAKE_MSYMBOL_SPECIAL | |
205 | tests whether an ELF symbol is "special", i.e. refers | |
206 | to a 32-bit function, and sets a "special" bit in a | |
207 | minimal symbol to mark it as a 32-bit function | |
208 | MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol | |
209 | MSYMBOL_SIZE returns the size of the minimal symbol, i.e. | |
210 | the "info" field with the "special" bit masked out */ | |
211 | ||
212 | #define MSYMBOL_IS_SPECIAL(msym) \ | |
213 | (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0) | |
214 | ||
215 | static void | |
216 | sh64_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym) | |
217 | { | |
218 | if (msym == NULL) | |
219 | return; | |
220 | ||
221 | if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_SH5_ISA32) | |
222 | { | |
223 | MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) | 0x80000000); | |
224 | SYMBOL_VALUE_ADDRESS (msym) |= 1; | |
225 | } | |
226 | } | |
227 | ||
228 | /* ISA32 (shmedia) function addresses are odd (bit 0 is set). Here | |
229 | are some macros to test, set, or clear bit 0 of addresses. */ | |
230 | #define IS_ISA32_ADDR(addr) ((addr) & 1) | |
231 | #define MAKE_ISA32_ADDR(addr) ((addr) | 1) | |
232 | #define UNMAKE_ISA32_ADDR(addr) ((addr) & ~1) | |
233 | ||
234 | static int | |
235 | pc_is_isa32 (bfd_vma memaddr) | |
236 | { | |
237 | struct minimal_symbol *sym; | |
238 | ||
239 | /* If bit 0 of the address is set, assume this is a | |
240 | ISA32 (shmedia) address. */ | |
241 | if (IS_ISA32_ADDR (memaddr)) | |
242 | return 1; | |
243 | ||
244 | /* A flag indicating that this is a ISA32 function is stored by elfread.c in | |
245 | the high bit of the info field. Use this to decide if the function is | |
246 | ISA16 or ISA32. */ | |
247 | sym = lookup_minimal_symbol_by_pc (memaddr); | |
248 | if (sym) | |
249 | return MSYMBOL_IS_SPECIAL (sym); | |
250 | else | |
251 | return 0; | |
252 | } | |
253 | ||
254 | static const unsigned char * | |
255 | sh_sh64_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) | |
256 | { | |
257 | /* The BRK instruction for shmedia is | |
258 | 01101111 11110101 11111111 11110000 | |
259 | which translates in big endian mode to 0x6f, 0xf5, 0xff, 0xf0 | |
260 | and in little endian mode to 0xf0, 0xff, 0xf5, 0x6f */ | |
261 | ||
262 | /* The BRK instruction for shcompact is | |
263 | 00000000 00111011 | |
264 | which translates in big endian mode to 0x0, 0x3b | |
265 | and in little endian mode to 0x3b, 0x0*/ | |
266 | ||
267 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
268 | { | |
269 | if (pc_is_isa32 (*pcptr)) | |
270 | { | |
271 | static unsigned char big_breakpoint_media[] = {0x6f, 0xf5, 0xff, 0xf0}; | |
272 | *pcptr = UNMAKE_ISA32_ADDR (*pcptr); | |
273 | *lenptr = sizeof (big_breakpoint_media); | |
274 | return big_breakpoint_media; | |
275 | } | |
276 | else | |
277 | { | |
278 | static unsigned char big_breakpoint_compact[] = {0x0, 0x3b}; | |
279 | *lenptr = sizeof (big_breakpoint_compact); | |
280 | return big_breakpoint_compact; | |
281 | } | |
282 | } | |
283 | else | |
284 | { | |
285 | if (pc_is_isa32 (*pcptr)) | |
286 | { | |
287 | static unsigned char little_breakpoint_media[] = {0xf0, 0xff, 0xf5, 0x6f}; | |
288 | *pcptr = UNMAKE_ISA32_ADDR (*pcptr); | |
289 | *lenptr = sizeof (little_breakpoint_media); | |
290 | return little_breakpoint_media; | |
291 | } | |
292 | else | |
293 | { | |
294 | static unsigned char little_breakpoint_compact[] = {0x3b, 0x0}; | |
295 | *lenptr = sizeof (little_breakpoint_compact); | |
296 | return little_breakpoint_compact; | |
297 | } | |
298 | } | |
299 | } | |
300 | ||
301 | /* Prologue looks like | |
302 | [mov.l <regs>,@-r15]... | |
303 | [sts.l pr,@-r15] | |
304 | [mov.l r14,@-r15] | |
305 | [mov r15,r14] | |
306 | ||
307 | Actually it can be more complicated than this. For instance, with | |
308 | newer gcc's: | |
309 | ||
310 | mov.l r14,@-r15 | |
311 | add #-12,r15 | |
312 | mov r15,r14 | |
313 | mov r4,r1 | |
314 | mov r5,r2 | |
315 | mov.l r6,@(4,r14) | |
316 | mov.l r7,@(8,r14) | |
317 | mov.b r1,@r14 | |
318 | mov r14,r1 | |
319 | mov r14,r1 | |
320 | add #2,r1 | |
321 | mov.w r2,@r1 | |
322 | ||
323 | */ | |
324 | ||
325 | /* PTABS/L Rn, TRa 0110101111110001nnnnnnl00aaa0000 | |
326 | with l=1 and n = 18 0110101111110001010010100aaa0000 */ | |
327 | #define IS_PTABSL_R18(x) (((x) & 0xffffff8f) == 0x6bf14a00) | |
328 | ||
329 | /* STS.L PR,@-r0 0100000000100010 | |
330 | r0-4-->r0, PR-->(r0) */ | |
331 | #define IS_STS_R0(x) ((x) == 0x4022) | |
332 | ||
333 | /* STS PR, Rm 0000mmmm00101010 | |
334 | PR-->Rm */ | |
335 | #define IS_STS_PR(x) (((x) & 0xf0ff) == 0x2a) | |
336 | ||
337 | /* MOV.L Rm,@(disp,r15) 00011111mmmmdddd | |
338 | Rm-->(dispx4+r15) */ | |
339 | #define IS_MOV_TO_R15(x) (((x) & 0xff00) == 0x1f00) | |
340 | ||
341 | /* MOV.L R14,@(disp,r15) 000111111110dddd | |
342 | R14-->(dispx4+r15) */ | |
343 | #define IS_MOV_R14(x) (((x) & 0xfff0) == 0x1fe0) | |
344 | ||
345 | /* ST.Q R14, disp, R18 101011001110dddddddddd0100100000 | |
346 | R18-->(dispx8+R14) */ | |
347 | #define IS_STQ_R18_R14(x) (((x) & 0xfff003ff) == 0xace00120) | |
348 | ||
349 | /* ST.Q R15, disp, R18 101011001111dddddddddd0100100000 | |
350 | R18-->(dispx8+R15) */ | |
351 | #define IS_STQ_R18_R15(x) (((x) & 0xfff003ff) == 0xacf00120) | |
352 | ||
353 | /* ST.L R15, disp, R18 101010001111dddddddddd0100100000 | |
354 | R18-->(dispx4+R15) */ | |
355 | #define IS_STL_R18_R15(x) (((x) & 0xfff003ff) == 0xa8f00120) | |
356 | ||
357 | /* ST.Q R15, disp, R14 1010 1100 1111 dddd dddd dd00 1110 0000 | |
358 | R14-->(dispx8+R15) */ | |
359 | #define IS_STQ_R14_R15(x) (((x) & 0xfff003ff) == 0xacf000e0) | |
360 | ||
361 | /* ST.L R15, disp, R14 1010 1000 1111 dddd dddd dd00 1110 0000 | |
362 | R14-->(dispx4+R15) */ | |
363 | #define IS_STL_R14_R15(x) (((x) & 0xfff003ff) == 0xa8f000e0) | |
364 | ||
365 | /* ADDI.L R15,imm,R15 1101 0100 1111 ssss ssss ss00 1111 0000 | |
366 | R15 + imm --> R15 */ | |
367 | #define IS_ADDIL_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd4f000f0) | |
368 | ||
369 | /* ADDI R15,imm,R15 1101 0000 1111 ssss ssss ss00 1111 0000 | |
370 | R15 + imm --> R15 */ | |
371 | #define IS_ADDI_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd0f000f0) | |
372 | ||
373 | /* ADD.L R15,R63,R14 0000 0000 1111 1000 1111 1100 1110 0000 | |
374 | R15 + R63 --> R14 */ | |
375 | #define IS_ADDL_SP_FP_MEDIA(x) ((x) == 0x00f8fce0) | |
376 | ||
377 | /* ADD R15,R63,R14 0000 0000 1111 1001 1111 1100 1110 0000 | |
378 | R15 + R63 --> R14 */ | |
379 | #define IS_ADD_SP_FP_MEDIA(x) ((x) == 0x00f9fce0) | |
380 | ||
381 | #define IS_MOV_SP_FP_MEDIA(x) (IS_ADDL_SP_FP_MEDIA(x) || IS_ADD_SP_FP_MEDIA(x)) | |
382 | ||
383 | /* MOV #imm, R0 1110 0000 ssss ssss | |
384 | #imm-->R0 */ | |
385 | #define IS_MOV_R0(x) (((x) & 0xff00) == 0xe000) | |
386 | ||
387 | /* MOV.L @(disp,PC), R0 1101 0000 iiii iiii */ | |
388 | #define IS_MOVL_R0(x) (((x) & 0xff00) == 0xd000) | |
389 | ||
390 | /* ADD r15,r0 0011 0000 1111 1100 | |
391 | r15+r0-->r0 */ | |
392 | #define IS_ADD_SP_R0(x) ((x) == 0x30fc) | |
393 | ||
394 | /* MOV.L R14 @-R0 0010 0000 1110 0110 | |
395 | R14-->(R0-4), R0-4-->R0 */ | |
396 | #define IS_MOV_R14_R0(x) ((x) == 0x20e6) | |
397 | ||
398 | /* ADD Rm,R63,Rn Rm+R63-->Rn 0000 00mm mmmm 1001 1111 11nn nnnn 0000 | |
399 | where Rm is one of r2-r9 which are the argument registers. */ | |
400 | /* FIXME: Recognize the float and double register moves too! */ | |
401 | #define IS_MEDIA_IND_ARG_MOV(x) \ | |
402 | ((((x) & 0xfc0ffc0f) == 0x0009fc00) && (((x) & 0x03f00000) >= 0x00200000 && ((x) & 0x03f00000) <= 0x00900000)) | |
403 | ||
404 | /* ST.Q Rn,0,Rm Rm-->Rn+0 1010 11nn nnnn 0000 0000 00mm mmmm 0000 | |
405 | or ST.L Rn,0,Rm Rm-->Rn+0 1010 10nn nnnn 0000 0000 00mm mmmm 0000 | |
406 | where Rm is one of r2-r9 which are the argument registers. */ | |
407 | #define IS_MEDIA_ARG_MOV(x) \ | |
408 | (((((x) & 0xfc0ffc0f) == 0xac000000) || (((x) & 0xfc0ffc0f) == 0xa8000000)) \ | |
409 | && (((x) & 0x000003f0) >= 0x00000020 && ((x) & 0x000003f0) <= 0x00000090)) | |
410 | ||
411 | /* ST.B R14,0,Rn Rn-->(R14+0) 1010 0000 1110 0000 0000 00nn nnnn 0000*/ | |
412 | /* ST.W R14,0,Rn Rn-->(R14+0) 1010 0100 1110 0000 0000 00nn nnnn 0000*/ | |
413 | /* ST.L R14,0,Rn Rn-->(R14+0) 1010 1000 1110 0000 0000 00nn nnnn 0000*/ | |
414 | /* FST.S R14,0,FRn Rn-->(R14+0) 1011 0100 1110 0000 0000 00nn nnnn 0000*/ | |
415 | /* FST.D R14,0,DRn Rn-->(R14+0) 1011 1100 1110 0000 0000 00nn nnnn 0000*/ | |
416 | #define IS_MEDIA_MOV_TO_R14(x) \ | |
417 | ((((x) & 0xfffffc0f) == 0xa0e00000) \ | |
418 | || (((x) & 0xfffffc0f) == 0xa4e00000) \ | |
419 | || (((x) & 0xfffffc0f) == 0xa8e00000) \ | |
420 | || (((x) & 0xfffffc0f) == 0xb4e00000) \ | |
421 | || (((x) & 0xfffffc0f) == 0xbce00000)) | |
422 | ||
423 | /* MOV Rm, Rn Rm-->Rn 0110 nnnn mmmm 0011 | |
424 | where Rm is r2-r9 */ | |
425 | #define IS_COMPACT_IND_ARG_MOV(x) \ | |
426 | ((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0020) && (((x) & 0x00f0) <= 0x0090)) | |
427 | ||
428 | /* compact direct arg move! | |
429 | MOV.L Rn, @r14 0010 1110 mmmm 0010 */ | |
430 | #define IS_COMPACT_ARG_MOV(x) \ | |
431 | (((((x) & 0xff0f) == 0x2e02) && (((x) & 0x00f0) >= 0x0020) && ((x) & 0x00f0) <= 0x0090)) | |
432 | ||
433 | /* MOV.B Rm, @R14 0010 1110 mmmm 0000 | |
434 | MOV.W Rm, @R14 0010 1110 mmmm 0001 */ | |
435 | #define IS_COMPACT_MOV_TO_R14(x) \ | |
436 | ((((x) & 0xff0f) == 0x2e00) || (((x) & 0xff0f) == 0x2e01)) | |
437 | ||
438 | #define IS_JSR_R0(x) ((x) == 0x400b) | |
439 | #define IS_NOP(x) ((x) == 0x0009) | |
440 | ||
441 | ||
442 | /* MOV r15,r14 0110111011110011 | |
443 | r15-->r14 */ | |
444 | #define IS_MOV_SP_FP(x) ((x) == 0x6ef3) | |
445 | ||
446 | /* ADD #imm,r15 01111111iiiiiiii | |
447 | r15+imm-->r15 */ | |
448 | #define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00) | |
449 | ||
450 | /* Skip any prologue before the guts of a function */ | |
451 | ||
452 | /* Skip the prologue using the debug information. If this fails we'll | |
453 | fall back on the 'guess' method below. */ | |
454 | static CORE_ADDR | |
455 | after_prologue (CORE_ADDR pc) | |
456 | { | |
457 | struct symtab_and_line sal; | |
458 | CORE_ADDR func_addr, func_end; | |
459 | ||
460 | /* If we can not find the symbol in the partial symbol table, then | |
461 | there is no hope we can determine the function's start address | |
462 | with this code. */ | |
463 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
464 | return 0; | |
465 | ||
466 | /* Get the line associated with FUNC_ADDR. */ | |
467 | sal = find_pc_line (func_addr, 0); | |
468 | ||
469 | /* There are only two cases to consider. First, the end of the source line | |
470 | is within the function bounds. In that case we return the end of the | |
471 | source line. Second is the end of the source line extends beyond the | |
472 | bounds of the current function. We need to use the slow code to | |
473 | examine instructions in that case. */ | |
474 | if (sal.end < func_end) | |
475 | return sal.end; | |
476 | else | |
477 | return 0; | |
478 | } | |
479 | ||
480 | static CORE_ADDR | |
481 | look_for_args_moves (CORE_ADDR start_pc, int media_mode) | |
482 | { | |
483 | CORE_ADDR here, end; | |
484 | int w; | |
485 | int insn_size = (media_mode ? 4 : 2); | |
486 | ||
487 | for (here = start_pc, end = start_pc + (insn_size * 28); here < end;) | |
488 | { | |
489 | if (media_mode) | |
490 | { | |
491 | w = read_memory_integer (UNMAKE_ISA32_ADDR (here), insn_size); | |
492 | here += insn_size; | |
493 | if (IS_MEDIA_IND_ARG_MOV (w)) | |
494 | { | |
495 | /* This must be followed by a store to r14, so the argument | |
496 | is where the debug info says it is. This can happen after | |
497 | the SP has been saved, unfortunately. */ | |
498 | ||
499 | int next_insn = read_memory_integer (UNMAKE_ISA32_ADDR (here), | |
500 | insn_size); | |
501 | here += insn_size; | |
502 | if (IS_MEDIA_MOV_TO_R14 (next_insn)) | |
503 | start_pc = here; | |
504 | } | |
505 | else if (IS_MEDIA_ARG_MOV (w)) | |
506 | { | |
507 | /* These instructions store directly the argument in r14. */ | |
508 | start_pc = here; | |
509 | } | |
510 | else | |
511 | break; | |
512 | } | |
513 | else | |
514 | { | |
515 | w = read_memory_integer (here, insn_size); | |
516 | w = w & 0xffff; | |
517 | here += insn_size; | |
518 | if (IS_COMPACT_IND_ARG_MOV (w)) | |
519 | { | |
520 | /* This must be followed by a store to r14, so the argument | |
521 | is where the debug info says it is. This can happen after | |
522 | the SP has been saved, unfortunately. */ | |
523 | ||
524 | int next_insn = 0xffff & read_memory_integer (here, insn_size); | |
525 | here += insn_size; | |
526 | if (IS_COMPACT_MOV_TO_R14 (next_insn)) | |
527 | start_pc = here; | |
528 | } | |
529 | else if (IS_COMPACT_ARG_MOV (w)) | |
530 | { | |
531 | /* These instructions store directly the argument in r14. */ | |
532 | start_pc = here; | |
533 | } | |
534 | else if (IS_MOVL_R0 (w)) | |
535 | { | |
536 | /* There is a function that gcc calls to get the arguments | |
537 | passed correctly to the function. Only after this | |
538 | function call the arguments will be found at the place | |
539 | where they are supposed to be. This happens in case the | |
540 | argument has to be stored into a 64-bit register (for | |
541 | instance doubles, long longs). SHcompact doesn't have | |
542 | access to the full 64-bits, so we store the register in | |
543 | stack slot and store the address of the stack slot in | |
544 | the register, then do a call through a wrapper that | |
545 | loads the memory value into the register. A SHcompact | |
546 | callee calls an argument decoder | |
547 | (GCC_shcompact_incoming_args) that stores the 64-bit | |
548 | value in a stack slot and stores the address of the | |
549 | stack slot in the register. GCC thinks the argument is | |
550 | just passed by transparent reference, but this is only | |
551 | true after the argument decoder is called. Such a call | |
552 | needs to be considered part of the prologue. */ | |
553 | ||
554 | /* This must be followed by a JSR @r0 instruction and by | |
555 | a NOP instruction. After these, the prologue is over! */ | |
556 | ||
557 | int next_insn = 0xffff & read_memory_integer (here, insn_size); | |
558 | here += insn_size; | |
559 | if (IS_JSR_R0 (next_insn)) | |
560 | { | |
561 | next_insn = 0xffff & read_memory_integer (here, insn_size); | |
562 | here += insn_size; | |
563 | ||
564 | if (IS_NOP (next_insn)) | |
565 | start_pc = here; | |
566 | } | |
567 | } | |
568 | else | |
569 | break; | |
570 | } | |
571 | } | |
572 | ||
573 | return start_pc; | |
574 | } | |
575 | ||
576 | static CORE_ADDR | |
577 | sh64_skip_prologue_hard_way (CORE_ADDR start_pc) | |
578 | { | |
579 | CORE_ADDR here, end; | |
580 | int updated_fp = 0; | |
581 | int insn_size = 4; | |
582 | int media_mode = 1; | |
583 | ||
584 | if (!start_pc) | |
585 | return 0; | |
586 | ||
587 | if (pc_is_isa32 (start_pc) == 0) | |
588 | { | |
589 | insn_size = 2; | |
590 | media_mode = 0; | |
591 | } | |
592 | ||
593 | for (here = start_pc, end = start_pc + (insn_size * 28); here < end;) | |
594 | { | |
595 | ||
596 | if (media_mode) | |
597 | { | |
598 | int w = read_memory_integer (UNMAKE_ISA32_ADDR (here), insn_size); | |
599 | here += insn_size; | |
600 | if (IS_STQ_R18_R14 (w) || IS_STQ_R18_R15 (w) || IS_STQ_R14_R15 (w) | |
601 | || IS_STL_R14_R15 (w) || IS_STL_R18_R15 (w) | |
602 | || IS_ADDIL_SP_MEDIA (w) || IS_ADDI_SP_MEDIA (w) || IS_PTABSL_R18 (w)) | |
603 | { | |
604 | start_pc = here; | |
605 | } | |
606 | else if (IS_MOV_SP_FP (w) || IS_MOV_SP_FP_MEDIA(w)) | |
607 | { | |
608 | start_pc = here; | |
609 | updated_fp = 1; | |
610 | } | |
611 | else | |
612 | if (updated_fp) | |
613 | { | |
614 | /* Don't bail out yet, we may have arguments stored in | |
615 | registers here, according to the debug info, so that | |
616 | gdb can print the frames correctly. */ | |
617 | start_pc = look_for_args_moves (here - insn_size, media_mode); | |
618 | break; | |
619 | } | |
620 | } | |
621 | else | |
622 | { | |
623 | int w = 0xffff & read_memory_integer (here, insn_size); | |
624 | here += insn_size; | |
625 | ||
626 | if (IS_STS_R0 (w) || IS_STS_PR (w) | |
627 | || IS_MOV_TO_R15 (w) || IS_MOV_R14 (w) | |
628 | || IS_MOV_R0 (w) || IS_ADD_SP_R0 (w) || IS_MOV_R14_R0 (w)) | |
629 | { | |
630 | start_pc = here; | |
631 | } | |
632 | else if (IS_MOV_SP_FP (w)) | |
633 | { | |
634 | start_pc = here; | |
635 | updated_fp = 1; | |
636 | } | |
637 | else | |
638 | if (updated_fp) | |
639 | { | |
640 | /* Don't bail out yet, we may have arguments stored in | |
641 | registers here, according to the debug info, so that | |
642 | gdb can print the frames correctly. */ | |
643 | start_pc = look_for_args_moves (here - insn_size, media_mode); | |
644 | break; | |
645 | } | |
646 | } | |
647 | } | |
648 | ||
649 | return start_pc; | |
650 | } | |
651 | ||
652 | static CORE_ADDR | |
653 | sh_skip_prologue (CORE_ADDR pc) | |
654 | { | |
655 | CORE_ADDR post_prologue_pc; | |
656 | ||
657 | /* See if we can determine the end of the prologue via the symbol table. | |
658 | If so, then return either PC, or the PC after the prologue, whichever | |
659 | is greater. */ | |
660 | post_prologue_pc = after_prologue (pc); | |
661 | ||
662 | /* If after_prologue returned a useful address, then use it. Else | |
663 | fall back on the instruction skipping code. */ | |
664 | if (post_prologue_pc != 0) | |
665 | return max (pc, post_prologue_pc); | |
666 | else | |
667 | return sh64_skip_prologue_hard_way (pc); | |
668 | } | |
669 | ||
670 | /* Immediately after a function call, return the saved pc. | |
671 | Can't always go through the frames for this because on some machines | |
672 | the new frame is not set up until the new function executes | |
673 | some instructions. | |
674 | ||
675 | The return address is the value saved in the PR register + 4 */ | |
676 | static CORE_ADDR | |
677 | sh_saved_pc_after_call (struct frame_info *frame) | |
678 | { | |
679 | return (ADDR_BITS_REMOVE (read_register (PR_REGNUM))); | |
680 | } | |
681 | ||
682 | /* Should call_function allocate stack space for a struct return? */ | |
683 | static int | |
684 | sh64_use_struct_convention (int gcc_p, struct type *type) | |
685 | { | |
686 | return (TYPE_LENGTH (type) > 8); | |
687 | } | |
688 | ||
689 | /* Store the address of the place in which to copy the structure the | |
690 | subroutine will return. This is called from call_function. | |
691 | ||
692 | We store structs through a pointer passed in R2 */ | |
693 | static void | |
694 | sh64_store_struct_return (CORE_ADDR addr, CORE_ADDR sp) | |
695 | { | |
696 | write_register (STRUCT_RETURN_REGNUM, (addr)); | |
697 | } | |
698 | ||
699 | /* Disassemble an instruction. */ | |
700 | static int | |
701 | gdb_print_insn_sh (bfd_vma memaddr, disassemble_info *info) | |
702 | { | |
703 | info->endian = TARGET_BYTE_ORDER; | |
704 | return print_insn_sh (memaddr, info); | |
705 | } | |
706 | ||
707 | /* Given a register number RN as it appears in an assembly | |
708 | instruction, find the corresponding register number in the GDB | |
709 | scheme. */ | |
710 | static int | |
711 | translate_insn_rn (int rn, int media_mode) | |
712 | { | |
713 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
714 | ||
715 | /* FIXME: this assumes that the number rn is for a not pseudo | |
716 | register only. */ | |
717 | if (media_mode) | |
718 | return rn; | |
719 | else | |
720 | { | |
721 | /* These registers don't have a corresponding compact one. */ | |
722 | /* FIXME: This is probably not enough. */ | |
723 | #if 0 | |
724 | if ((rn >= 16 && rn <= 63) || (rn >= 93 && rn <= 140)) | |
725 | return rn; | |
726 | #endif | |
727 | if (rn >= 0 && rn <= R0_C_REGNUM) | |
728 | return R0_C_REGNUM + rn; | |
729 | else | |
730 | return rn; | |
731 | } | |
732 | } | |
733 | ||
734 | /* Given a GDB frame, determine the address of the calling function's | |
735 | frame. This will be used to create a new GDB frame struct, and | |
736 | then DEPRECATED_INIT_EXTRA_FRAME_INFO and DEPRECATED_INIT_FRAME_PC | |
737 | will be called for the new frame. | |
738 | ||
739 | For us, the frame address is its stack pointer value, so we look up | |
740 | the function prologue to determine the caller's sp value, and return it. */ | |
741 | static CORE_ADDR | |
742 | sh64_frame_chain (struct frame_info *frame) | |
743 | { | |
744 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), | |
745 | get_frame_base (frame), | |
746 | get_frame_base (frame))) | |
747 | return get_frame_base (frame); /* dummy frame same as caller's frame */ | |
748 | if (get_frame_pc (frame) && !inside_entry_file (get_frame_pc (frame))) | |
749 | { | |
750 | int media_mode = pc_is_isa32 (get_frame_pc (frame)); | |
751 | int size; | |
752 | if (gdbarch_tdep (current_gdbarch)->sh_abi == SH_ABI_32) | |
753 | size = 4; | |
754 | else | |
755 | size = REGISTER_RAW_SIZE (translate_insn_rn (DEPRECATED_FP_REGNUM, media_mode)); | |
756 | return read_memory_integer (get_frame_base (frame) | |
757 | + get_frame_extra_info (frame)->f_offset, | |
758 | size); | |
759 | } | |
760 | else | |
761 | return 0; | |
762 | } | |
763 | ||
764 | static CORE_ADDR | |
765 | sh64_get_saved_pr (struct frame_info *fi, int pr_regnum) | |
766 | { | |
767 | int media_mode = 0; | |
768 | ||
769 | for (; fi; fi = get_next_frame (fi)) | |
770 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), get_frame_base (fi), | |
771 | get_frame_base (fi))) | |
772 | /* When the caller requests PR from the dummy frame, we return PC because | |
773 | that's where the previous routine appears to have done a call from. */ | |
774 | return deprecated_read_register_dummy (get_frame_pc (fi), | |
775 | get_frame_base (fi), pr_regnum); | |
776 | else | |
777 | { | |
778 | DEPRECATED_FRAME_INIT_SAVED_REGS (fi); | |
779 | if (!get_frame_pc (fi)) | |
780 | return 0; | |
781 | ||
782 | media_mode = pc_is_isa32 (get_frame_pc (fi)); | |
783 | ||
784 | if (get_frame_saved_regs (fi)[pr_regnum] != 0) | |
785 | { | |
786 | int gdb_reg_num = translate_insn_rn (pr_regnum, media_mode); | |
787 | int size = ((gdbarch_tdep (current_gdbarch)->sh_abi == SH_ABI_32) | |
788 | ? 4 | |
789 | : REGISTER_RAW_SIZE (gdb_reg_num)); | |
790 | return read_memory_integer (get_frame_saved_regs (fi)[pr_regnum], size); | |
791 | } | |
792 | } | |
793 | return read_register (pr_regnum); | |
794 | } | |
795 | ||
796 | /* For vectors of 4 floating point registers. */ | |
797 | static int | |
798 | fv_reg_base_num (int fv_regnum) | |
799 | { | |
800 | int fp_regnum; | |
801 | ||
802 | fp_regnum = FP0_REGNUM + | |
803 | (fv_regnum - FV0_REGNUM) * 4; | |
804 | return fp_regnum; | |
805 | } | |
806 | ||
807 | /* For double precision floating point registers, i.e 2 fp regs.*/ | |
808 | static int | |
809 | dr_reg_base_num (int dr_regnum) | |
810 | { | |
811 | int fp_regnum; | |
812 | ||
813 | fp_regnum = FP0_REGNUM + | |
814 | (dr_regnum - DR0_REGNUM) * 2; | |
815 | return fp_regnum; | |
816 | } | |
817 | ||
818 | /* For pairs of floating point registers */ | |
819 | static int | |
820 | fpp_reg_base_num (int fpp_regnum) | |
821 | { | |
822 | int fp_regnum; | |
823 | ||
824 | fp_regnum = FP0_REGNUM + | |
825 | (fpp_regnum - FPP0_REGNUM) * 2; | |
826 | return fp_regnum; | |
827 | } | |
828 | ||
829 | static int | |
830 | is_media_pseudo (int rn) | |
831 | { | |
832 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
833 | ||
834 | return (rn >= DR0_REGNUM | |
835 | && rn <= FV_LAST_REGNUM); | |
836 | } | |
837 | ||
838 | static int | |
839 | sh64_get_gdb_regnum (int gcc_regnum, CORE_ADDR pc) | |
840 | { | |
841 | return translate_insn_rn (gcc_regnum, pc_is_isa32 (pc)); | |
842 | } | |
843 | ||
844 | static int | |
845 | sh64_media_reg_base_num (int reg_nr) | |
846 | { | |
847 | int base_regnum = -1; | |
848 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
849 | ||
850 | if (reg_nr >= DR0_REGNUM | |
851 | && reg_nr <= DR_LAST_REGNUM) | |
852 | base_regnum = dr_reg_base_num (reg_nr); | |
853 | ||
854 | else if (reg_nr >= FPP0_REGNUM | |
855 | && reg_nr <= FPP_LAST_REGNUM) | |
856 | base_regnum = fpp_reg_base_num (reg_nr); | |
857 | ||
858 | else if (reg_nr >= FV0_REGNUM | |
859 | && reg_nr <= FV_LAST_REGNUM) | |
860 | base_regnum = fv_reg_base_num (reg_nr); | |
861 | ||
862 | return base_regnum; | |
863 | } | |
864 | ||
865 | /* *INDENT-OFF* */ | |
866 | /* | |
867 | SH COMPACT MODE (ISA 16) (all pseudo) 221-272 | |
868 | GDB_REGNUM BASE_REGNUM | |
869 | r0_c 221 0 | |
870 | r1_c 222 1 | |
871 | r2_c 223 2 | |
872 | r3_c 224 3 | |
873 | r4_c 225 4 | |
874 | r5_c 226 5 | |
875 | r6_c 227 6 | |
876 | r7_c 228 7 | |
877 | r8_c 229 8 | |
878 | r9_c 230 9 | |
879 | r10_c 231 10 | |
880 | r11_c 232 11 | |
881 | r12_c 233 12 | |
882 | r13_c 234 13 | |
883 | r14_c 235 14 | |
884 | r15_c 236 15 | |
885 | ||
886 | pc_c 237 64 | |
887 | gbr_c 238 16 | |
888 | mach_c 239 17 | |
889 | macl_c 240 17 | |
890 | pr_c 241 18 | |
891 | t_c 242 19 | |
892 | fpscr_c 243 76 | |
893 | fpul_c 244 109 | |
894 | ||
895 | fr0_c 245 77 | |
896 | fr1_c 246 78 | |
897 | fr2_c 247 79 | |
898 | fr3_c 248 80 | |
899 | fr4_c 249 81 | |
900 | fr5_c 250 82 | |
901 | fr6_c 251 83 | |
902 | fr7_c 252 84 | |
903 | fr8_c 253 85 | |
904 | fr9_c 254 86 | |
905 | fr10_c 255 87 | |
906 | fr11_c 256 88 | |
907 | fr12_c 257 89 | |
908 | fr13_c 258 90 | |
909 | fr14_c 259 91 | |
910 | fr15_c 260 92 | |
911 | ||
912 | dr0_c 261 77 | |
913 | dr2_c 262 79 | |
914 | dr4_c 263 81 | |
915 | dr6_c 264 83 | |
916 | dr8_c 265 85 | |
917 | dr10_c 266 87 | |
918 | dr12_c 267 89 | |
919 | dr14_c 268 91 | |
920 | ||
921 | fv0_c 269 77 | |
922 | fv4_c 270 81 | |
923 | fv8_c 271 85 | |
924 | fv12_c 272 91 | |
925 | */ | |
926 | /* *INDENT-ON* */ | |
927 | static int | |
928 | sh64_compact_reg_base_num (int reg_nr) | |
929 | { | |
930 | int base_regnum = -1; | |
931 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
932 | ||
933 | /* general register N maps to general register N */ | |
934 | if (reg_nr >= R0_C_REGNUM | |
935 | && reg_nr <= R_LAST_C_REGNUM) | |
936 | base_regnum = reg_nr - R0_C_REGNUM; | |
937 | ||
938 | /* floating point register N maps to floating point register N */ | |
939 | else if (reg_nr >= FP0_C_REGNUM | |
940 | && reg_nr <= FP_LAST_C_REGNUM) | |
941 | base_regnum = reg_nr - FP0_C_REGNUM + FP0_REGNUM; | |
942 | ||
943 | /* double prec register N maps to base regnum for double prec register N */ | |
944 | else if (reg_nr >= DR0_C_REGNUM | |
945 | && reg_nr <= DR_LAST_C_REGNUM) | |
946 | base_regnum = dr_reg_base_num (DR0_REGNUM | |
947 | + reg_nr - DR0_C_REGNUM); | |
948 | ||
949 | /* vector N maps to base regnum for vector register N */ | |
950 | else if (reg_nr >= FV0_C_REGNUM | |
951 | && reg_nr <= FV_LAST_C_REGNUM) | |
952 | base_regnum = fv_reg_base_num (FV0_REGNUM | |
953 | + reg_nr - FV0_C_REGNUM); | |
954 | ||
955 | else if (reg_nr == PC_C_REGNUM) | |
956 | base_regnum = PC_REGNUM; | |
957 | ||
958 | else if (reg_nr == GBR_C_REGNUM) | |
959 | base_regnum = 16; | |
960 | ||
961 | else if (reg_nr == MACH_C_REGNUM | |
962 | || reg_nr == MACL_C_REGNUM) | |
963 | base_regnum = 17; | |
964 | ||
965 | else if (reg_nr == PR_C_REGNUM) | |
966 | base_regnum = 18; | |
967 | ||
968 | else if (reg_nr == T_C_REGNUM) | |
969 | base_regnum = 19; | |
970 | ||
971 | else if (reg_nr == FPSCR_C_REGNUM) | |
972 | base_regnum = FPSCR_REGNUM; /*???? this register is a mess. */ | |
973 | ||
974 | else if (reg_nr == FPUL_C_REGNUM) | |
975 | base_regnum = FP0_REGNUM + 32; | |
976 | ||
977 | return base_regnum; | |
978 | } | |
979 | ||
980 | /* Given a register number RN (according to the gdb scheme) , return | |
981 | its corresponding architectural register. In media mode, only a | |
982 | subset of the registers is pseudo registers. For compact mode, all | |
983 | the registers are pseudo. */ | |
984 | static int | |
985 | translate_rn_to_arch_reg_num (int rn, int media_mode) | |
986 | { | |
987 | ||
988 | if (media_mode) | |
989 | { | |
990 | if (!is_media_pseudo (rn)) | |
991 | return rn; | |
992 | else | |
993 | return sh64_media_reg_base_num (rn); | |
994 | } | |
995 | else | |
996 | /* All compact registers are pseudo. */ | |
997 | return sh64_compact_reg_base_num (rn); | |
998 | } | |
999 | ||
1000 | static int | |
1001 | sign_extend (int value, int bits) | |
1002 | { | |
1003 | value = value & ((1 << bits) - 1); | |
1004 | return (value & (1 << (bits - 1)) | |
1005 | ? value | (~((1 << bits) - 1)) | |
1006 | : value); | |
1007 | } | |
1008 | ||
1009 | static void | |
1010 | sh64_nofp_frame_init_saved_regs (struct frame_info *fi) | |
1011 | { | |
1012 | int *where = (int *) alloca ((NUM_REGS + NUM_PSEUDO_REGS) * sizeof (int)); | |
1013 | int rn; | |
1014 | int have_fp = 0; | |
1015 | int fp_regnum; | |
1016 | int sp_regnum; | |
1017 | int depth; | |
1018 | int pc; | |
1019 | int opc; | |
1020 | int insn; | |
1021 | int r0_val = 0; | |
1022 | int media_mode = 0; | |
1023 | int insn_size; | |
1024 | int gdb_register_number; | |
1025 | int register_number; | |
1026 | char *dummy_regs = deprecated_generic_find_dummy_frame (get_frame_pc (fi), get_frame_base (fi)); | |
1027 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
1028 | ||
1029 | if (get_frame_saved_regs (fi) == NULL) | |
1030 | frame_saved_regs_zalloc (fi); | |
1031 | else | |
1032 | memset (get_frame_saved_regs (fi), 0, SIZEOF_FRAME_SAVED_REGS); | |
1033 | ||
1034 | if (dummy_regs) | |
1035 | { | |
1036 | /* DANGER! This is ONLY going to work if the char buffer format of | |
1037 | the saved registers is byte-for-byte identical to the | |
1038 | CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */ | |
1039 | memcpy (get_frame_saved_regs (fi), dummy_regs, SIZEOF_FRAME_SAVED_REGS); | |
1040 | return; | |
1041 | } | |
1042 | ||
1043 | get_frame_extra_info (fi)->leaf_function = 1; | |
1044 | get_frame_extra_info (fi)->f_offset = 0; | |
1045 | ||
1046 | for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++) | |
1047 | where[rn] = -1; | |
1048 | ||
1049 | depth = 0; | |
1050 | ||
1051 | /* Loop around examining the prologue insns until we find something | |
1052 | that does not appear to be part of the prologue. But give up | |
1053 | after 20 of them, since we're getting silly then. */ | |
1054 | ||
1055 | pc = get_frame_func (fi); | |
1056 | if (!pc) | |
1057 | { | |
1058 | deprecated_update_frame_pc_hack (fi, 0); | |
1059 | return; | |
1060 | } | |
1061 | ||
1062 | if (pc_is_isa32 (pc)) | |
1063 | { | |
1064 | media_mode = 1; | |
1065 | insn_size = 4; | |
1066 | } | |
1067 | else | |
1068 | { | |
1069 | media_mode = 0; | |
1070 | insn_size = 2; | |
1071 | } | |
1072 | ||
1073 | /* The frame pointer register is general register 14 in shmedia and | |
1074 | shcompact modes. In sh compact it is a pseudo register. Same goes | |
1075 | for the stack pointer register, which is register 15. */ | |
1076 | fp_regnum = translate_insn_rn (DEPRECATED_FP_REGNUM, media_mode); | |
1077 | sp_regnum = translate_insn_rn (SP_REGNUM, media_mode); | |
1078 | ||
1079 | for (opc = pc + (insn_size * 28); pc < opc; pc += insn_size) | |
1080 | { | |
1081 | insn = read_memory_integer (media_mode ? UNMAKE_ISA32_ADDR (pc) : pc, | |
1082 | insn_size); | |
1083 | ||
1084 | if (media_mode == 0) | |
1085 | { | |
1086 | if (IS_STS_PR (insn)) | |
1087 | { | |
1088 | int next_insn = read_memory_integer (pc + insn_size, insn_size); | |
1089 | if (IS_MOV_TO_R15 (next_insn)) | |
1090 | { | |
1091 | int reg_nr = PR_C_REGNUM; | |
1092 | ||
1093 | where[reg_nr] = depth - ((((next_insn & 0xf) ^ 0x8) - 0x8) << 2); | |
1094 | get_frame_extra_info (fi)->leaf_function = 0; | |
1095 | pc += insn_size; | |
1096 | } | |
1097 | } | |
1098 | else if (IS_MOV_R14 (insn)) | |
1099 | { | |
1100 | where[fp_regnum] = depth - ((((insn & 0xf) ^ 0x8) - 0x8) << 2); | |
1101 | } | |
1102 | ||
1103 | else if (IS_MOV_R0 (insn)) | |
1104 | { | |
1105 | /* Put in R0 the offset from SP at which to store some | |
1106 | registers. We are interested in this value, because it | |
1107 | will tell us where the given registers are stored within | |
1108 | the frame. */ | |
1109 | r0_val = ((insn & 0xff) ^ 0x80) - 0x80; | |
1110 | } | |
1111 | else if (IS_ADD_SP_R0 (insn)) | |
1112 | { | |
1113 | /* This instruction still prepares r0, but we don't care. | |
1114 | We already have the offset in r0_val. */ | |
1115 | } | |
1116 | else if (IS_STS_R0 (insn)) | |
1117 | { | |
1118 | /* Store PR at r0_val-4 from SP. Decrement r0 by 4*/ | |
1119 | int reg_nr = PR_C_REGNUM; | |
1120 | where[reg_nr] = depth - (r0_val - 4); | |
1121 | r0_val -= 4; | |
1122 | get_frame_extra_info (fi)->leaf_function = 0; | |
1123 | } | |
1124 | else if (IS_MOV_R14_R0 (insn)) | |
1125 | { | |
1126 | /* Store R14 at r0_val-4 from SP. Decrement r0 by 4 */ | |
1127 | where[fp_regnum] = depth - (r0_val - 4); | |
1128 | r0_val -= 4; | |
1129 | } | |
1130 | ||
1131 | else if (IS_ADD_SP (insn)) | |
1132 | { | |
1133 | depth -= ((insn & 0xff) ^ 0x80) - 0x80; | |
1134 | } | |
1135 | else if (IS_MOV_SP_FP (insn)) | |
1136 | break; | |
1137 | } | |
1138 | else | |
1139 | { | |
1140 | if (IS_ADDIL_SP_MEDIA (insn) | |
1141 | || IS_ADDI_SP_MEDIA (insn)) | |
1142 | { | |
1143 | depth -= sign_extend ((((insn & 0xffc00) ^ 0x80000) - 0x80000) >> 10, 9); | |
1144 | } | |
1145 | ||
1146 | else if (IS_STQ_R18_R15 (insn)) | |
1147 | { | |
1148 | where[PR_REGNUM] = | |
1149 | depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 3); | |
1150 | get_frame_extra_info (fi)->leaf_function = 0; | |
1151 | } | |
1152 | ||
1153 | else if (IS_STL_R18_R15 (insn)) | |
1154 | { | |
1155 | where[PR_REGNUM] = | |
1156 | depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 2); | |
1157 | get_frame_extra_info (fi)->leaf_function = 0; | |
1158 | } | |
1159 | ||
1160 | else if (IS_STQ_R14_R15 (insn)) | |
1161 | { | |
1162 | where[fp_regnum] = depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 3); | |
1163 | } | |
1164 | ||
1165 | else if (IS_STL_R14_R15 (insn)) | |
1166 | { | |
1167 | where[fp_regnum] = depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 2); | |
1168 | } | |
1169 | ||
1170 | else if (IS_MOV_SP_FP_MEDIA (insn)) | |
1171 | break; | |
1172 | } | |
1173 | } | |
1174 | ||
1175 | /* Now we know how deep things are, we can work out their addresses. */ | |
1176 | for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++) | |
1177 | { | |
1178 | register_number = translate_rn_to_arch_reg_num (rn, media_mode); | |
1179 | ||
1180 | if (where[rn] >= 0) | |
1181 | { | |
1182 | if (rn == fp_regnum) | |
1183 | have_fp = 1; | |
1184 | ||
1185 | /* Watch out! saved_regs is only for the real registers, and | |
1186 | doesn't include space for the pseudo registers. */ | |
1187 | get_frame_saved_regs (fi)[register_number]= get_frame_base (fi) - where[rn] + depth; | |
1188 | ||
1189 | } | |
1190 | else | |
1191 | get_frame_saved_regs (fi)[register_number] = 0; | |
1192 | } | |
1193 | ||
1194 | if (have_fp) | |
1195 | { | |
1196 | /* SP_REGNUM is 15. For shmedia 15 is the real register. For | |
1197 | shcompact 15 is the arch register corresponding to the pseudo | |
1198 | register r15 which still is the SP register. */ | |
1199 | /* The place on the stack where fp is stored contains the sp of | |
1200 | the caller. */ | |
1201 | /* Again, saved_registers contains only space for the real | |
1202 | registers, so we store in DEPRECATED_FP_REGNUM position. */ | |
1203 | int size; | |
1204 | if (tdep->sh_abi == SH_ABI_32) | |
1205 | size = 4; | |
1206 | else | |
1207 | size = REGISTER_RAW_SIZE (fp_regnum); | |
1208 | get_frame_saved_regs (fi)[sp_regnum] = read_memory_integer (get_frame_saved_regs (fi)[fp_regnum], size); | |
1209 | } | |
1210 | else | |
1211 | get_frame_saved_regs (fi)[sp_regnum] = get_frame_base (fi); | |
1212 | ||
1213 | get_frame_extra_info (fi)->f_offset = depth - where[fp_regnum]; | |
1214 | } | |
1215 | ||
1216 | /* Initialize the extra info saved in a FRAME */ | |
1217 | static void | |
1218 | sh64_init_extra_frame_info (int fromleaf, struct frame_info *fi) | |
1219 | { | |
1220 | int media_mode = pc_is_isa32 (get_frame_pc (fi)); | |
1221 | ||
1222 | frame_extra_info_zalloc (fi, sizeof (struct frame_extra_info)); | |
1223 | ||
1224 | if (get_next_frame (fi)) | |
1225 | deprecated_update_frame_pc_hack (fi, DEPRECATED_FRAME_SAVED_PC (get_next_frame (fi))); | |
1226 | ||
1227 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), get_frame_base (fi), | |
1228 | get_frame_base (fi))) | |
1229 | { | |
1230 | /* We need to setup fi->frame here because call_function_by_hand | |
1231 | gets it wrong by assuming it's always FP. */ | |
1232 | deprecated_update_frame_base_hack (fi, deprecated_read_register_dummy (get_frame_pc (fi), get_frame_base (fi), SP_REGNUM)); | |
1233 | get_frame_extra_info (fi)->return_pc = | |
1234 | deprecated_read_register_dummy (get_frame_pc (fi), | |
1235 | get_frame_base (fi), PC_REGNUM); | |
1236 | get_frame_extra_info (fi)->f_offset = -(DEPRECATED_CALL_DUMMY_LENGTH + 4); | |
1237 | get_frame_extra_info (fi)->leaf_function = 0; | |
1238 | return; | |
1239 | } | |
1240 | else | |
1241 | { | |
1242 | DEPRECATED_FRAME_INIT_SAVED_REGS (fi); | |
1243 | get_frame_extra_info (fi)->return_pc = | |
1244 | sh64_get_saved_pr (fi, PR_REGNUM); | |
1245 | } | |
1246 | } | |
1247 | ||
1248 | static void | |
1249 | sh64_get_saved_register (char *raw_buffer, int *optimized, CORE_ADDR *addrp, | |
1250 | struct frame_info *frame, int regnum, | |
1251 | enum lval_type *lval) | |
1252 | { | |
1253 | int media_mode; | |
1254 | int live_regnum = regnum; | |
1255 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
1256 | ||
1257 | if (!target_has_registers) | |
1258 | error ("No registers."); | |
1259 | ||
1260 | /* Normal systems don't optimize out things with register numbers. */ | |
1261 | if (optimized != NULL) | |
1262 | *optimized = 0; | |
1263 | ||
1264 | if (addrp) /* default assumption: not found in memory */ | |
1265 | *addrp = 0; | |
1266 | ||
1267 | if (raw_buffer) | |
1268 | memset (raw_buffer, 0, sizeof (raw_buffer)); | |
1269 | ||
1270 | /* We must do this here, before the following while loop changes | |
1271 | frame, and makes it NULL. If this is a media register number, | |
1272 | but we are in compact mode, it will become the corresponding | |
1273 | compact pseudo register. If there is no corresponding compact | |
1274 | pseudo-register what do we do?*/ | |
1275 | media_mode = pc_is_isa32 (get_frame_pc (frame)); | |
1276 | live_regnum = translate_insn_rn (regnum, media_mode); | |
1277 | ||
1278 | /* Note: since the current frame's registers could only have been | |
1279 | saved by frames INTERIOR TO the current frame, we skip examining | |
1280 | the current frame itself: otherwise, we would be getting the | |
1281 | previous frame's registers which were saved by the current frame. */ | |
1282 | ||
1283 | while (frame && ((frame = get_next_frame (frame)) != NULL)) | |
1284 | { | |
1285 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), | |
1286 | get_frame_base (frame), | |
1287 | get_frame_base (frame))) | |
1288 | { | |
1289 | if (lval) /* found it in a CALL_DUMMY frame */ | |
1290 | *lval = not_lval; | |
1291 | if (raw_buffer) | |
1292 | memcpy (raw_buffer, | |
1293 | (deprecated_generic_find_dummy_frame (get_frame_pc (frame), get_frame_base (frame)) | |
1294 | + REGISTER_BYTE (regnum)), | |
1295 | REGISTER_RAW_SIZE (regnum)); | |
1296 | return; | |
1297 | } | |
1298 | ||
1299 | DEPRECATED_FRAME_INIT_SAVED_REGS (frame); | |
1300 | if (get_frame_saved_regs (frame) != NULL | |
1301 | && get_frame_saved_regs (frame)[regnum] != 0) | |
1302 | { | |
1303 | if (lval) /* found it saved on the stack */ | |
1304 | *lval = lval_memory; | |
1305 | if (regnum == SP_REGNUM) | |
1306 | { | |
1307 | if (raw_buffer) /* SP register treated specially */ | |
1308 | store_unsigned_integer (raw_buffer, REGISTER_RAW_SIZE (regnum), | |
1309 | get_frame_saved_regs (frame)[regnum]); | |
1310 | } | |
1311 | else | |
1312 | { /* any other register */ | |
1313 | ||
1314 | if (addrp) | |
1315 | *addrp = get_frame_saved_regs (frame)[regnum]; | |
1316 | if (raw_buffer) | |
1317 | { | |
1318 | int size; | |
1319 | if (tdep->sh_abi == SH_ABI_32 | |
1320 | && (live_regnum == DEPRECATED_FP_REGNUM | |
1321 | || live_regnum == PR_REGNUM)) | |
1322 | size = 4; | |
1323 | else | |
1324 | size = REGISTER_RAW_SIZE (live_regnum); | |
1325 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) | |
1326 | read_memory (get_frame_saved_regs (frame)[regnum], raw_buffer, size); | |
1327 | else | |
1328 | read_memory (get_frame_saved_regs (frame)[regnum], | |
1329 | raw_buffer | |
1330 | + REGISTER_RAW_SIZE (live_regnum) | |
1331 | - size, | |
1332 | size); | |
1333 | } | |
1334 | } | |
1335 | return; | |
1336 | } | |
1337 | } | |
1338 | ||
1339 | /* If we get thru the loop to this point, it means the register was | |
1340 | not saved in any frame. Return the actual live-register value. */ | |
1341 | ||
1342 | if (lval) /* found it in a live register */ | |
1343 | *lval = lval_register; | |
1344 | if (addrp) | |
1345 | *addrp = REGISTER_BYTE (live_regnum); | |
1346 | if (raw_buffer) | |
1347 | deprecated_read_register_gen (live_regnum, raw_buffer); | |
1348 | } | |
1349 | ||
1350 | static CORE_ADDR | |
1351 | sh64_extract_struct_value_address (char *regbuf) | |
1352 | { | |
1353 | return (extract_unsigned_integer ((regbuf + REGISTER_BYTE (STRUCT_RETURN_REGNUM)), | |
1354 | REGISTER_RAW_SIZE (STRUCT_RETURN_REGNUM))); | |
1355 | } | |
1356 | ||
1357 | static CORE_ADDR | |
1358 | sh_frame_saved_pc (struct frame_info *frame) | |
1359 | { | |
1360 | return (get_frame_extra_info (frame)->return_pc); | |
1361 | } | |
1362 | ||
1363 | /* Discard from the stack the innermost frame, restoring all saved registers. | |
1364 | Used in the 'return' command. */ | |
1365 | static void | |
1366 | sh64_pop_frame (void) | |
1367 | { | |
1368 | register struct frame_info *frame = get_current_frame (); | |
1369 | register CORE_ADDR fp; | |
1370 | register int regnum; | |
1371 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
1372 | ||
1373 | int media_mode = pc_is_isa32 (get_frame_pc (frame)); | |
1374 | ||
1375 | if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), | |
1376 | get_frame_base (frame), | |
1377 | get_frame_base (frame))) | |
1378 | generic_pop_dummy_frame (); | |
1379 | else | |
1380 | { | |
1381 | fp = get_frame_base (frame); | |
1382 | DEPRECATED_FRAME_INIT_SAVED_REGS (frame); | |
1383 | ||
1384 | /* Copy regs from where they were saved in the frame */ | |
1385 | for (regnum = 0; regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++) | |
1386 | if (get_frame_saved_regs (frame)[regnum]) | |
1387 | { | |
1388 | int size; | |
1389 | if (tdep->sh_abi == SH_ABI_32 | |
1390 | && (regnum == DEPRECATED_FP_REGNUM | |
1391 | || regnum == PR_REGNUM)) | |
1392 | size = 4; | |
1393 | else | |
1394 | size = REGISTER_RAW_SIZE (translate_insn_rn (regnum, | |
1395 | media_mode)); | |
1396 | write_register (regnum, | |
1397 | read_memory_integer (get_frame_saved_regs (frame)[regnum], | |
1398 | size)); | |
1399 | } | |
1400 | ||
1401 | write_register (PC_REGNUM, get_frame_extra_info (frame)->return_pc); | |
1402 | write_register (SP_REGNUM, fp + 8); | |
1403 | } | |
1404 | flush_cached_frames (); | |
1405 | } | |
1406 | ||
1407 | static CORE_ADDR | |
1408 | sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp) | |
1409 | { | |
1410 | return sp & ~3; | |
1411 | } | |
1412 | ||
1413 | /* Function: push_arguments | |
1414 | Setup the function arguments for calling a function in the inferior. | |
1415 | ||
1416 | On the Hitachi SH architecture, there are four registers (R4 to R7) | |
1417 | which are dedicated for passing function arguments. Up to the first | |
1418 | four arguments (depending on size) may go into these registers. | |
1419 | The rest go on the stack. | |
1420 | ||
1421 | Arguments that are smaller than 4 bytes will still take up a whole | |
1422 | register or a whole 32-bit word on the stack, and will be | |
1423 | right-justified in the register or the stack word. This includes | |
1424 | chars, shorts, and small aggregate types. | |
1425 | ||
1426 | Arguments that are larger than 4 bytes may be split between two or | |
1427 | more registers. If there are not enough registers free, an argument | |
1428 | may be passed partly in a register (or registers), and partly on the | |
1429 | stack. This includes doubles, long longs, and larger aggregates. | |
1430 | As far as I know, there is no upper limit to the size of aggregates | |
1431 | that will be passed in this way; in other words, the convention of | |
1432 | passing a pointer to a large aggregate instead of a copy is not used. | |
1433 | ||
1434 | An exceptional case exists for struct arguments (and possibly other | |
1435 | aggregates such as arrays) if the size is larger than 4 bytes but | |
1436 | not a multiple of 4 bytes. In this case the argument is never split | |
1437 | between the registers and the stack, but instead is copied in its | |
1438 | entirety onto the stack, AND also copied into as many registers as | |
1439 | there is room for. In other words, space in registers permitting, | |
1440 | two copies of the same argument are passed in. As far as I can tell, | |
1441 | only the one on the stack is used, although that may be a function | |
1442 | of the level of compiler optimization. I suspect this is a compiler | |
1443 | bug. Arguments of these odd sizes are left-justified within the | |
1444 | word (as opposed to arguments smaller than 4 bytes, which are | |
1445 | right-justified). | |
1446 | ||
1447 | If the function is to return an aggregate type such as a struct, it | |
1448 | is either returned in the normal return value register R0 (if its | |
1449 | size is no greater than one byte), or else the caller must allocate | |
1450 | space into which the callee will copy the return value (if the size | |
1451 | is greater than one byte). In this case, a pointer to the return | |
1452 | value location is passed into the callee in register R2, which does | |
1453 | not displace any of the other arguments passed in via registers R4 | |
1454 | to R7. */ | |
1455 | ||
1456 | /* R2-R9 for integer types and integer equivalent (char, pointers) and | |
1457 | non-scalar (struct, union) elements (even if the elements are | |
1458 | floats). | |
1459 | FR0-FR11 for single precision floating point (float) | |
1460 | DR0-DR10 for double precision floating point (double) | |
1461 | ||
1462 | If a float is argument number 3 (for instance) and arguments number | |
1463 | 1,2, and 4 are integer, the mapping will be: | |
1464 | arg1 -->R2, arg2 --> R3, arg3 -->FR0, arg4 --> R5. I.e. R4 is not used. | |
1465 | ||
1466 | If a float is argument number 10 (for instance) and arguments number | |
1467 | 1 through 10 are integer, the mapping will be: | |
1468 | arg1->R2, arg2->R3, arg3->R4, arg4->R5, arg5->R6, arg6->R7, arg7->R8, | |
1469 | arg8->R9, arg9->(0,SP)stack(8-byte aligned), arg10->FR0, arg11->stack(16,SP). | |
1470 | I.e. there is hole in the stack. | |
1471 | ||
1472 | Different rules apply for variable arguments functions, and for functions | |
1473 | for which the prototype is not known. */ | |
1474 | ||
1475 | static CORE_ADDR | |
1476 | sh64_push_arguments (int nargs, struct value **args, CORE_ADDR sp, | |
1477 | int struct_return, CORE_ADDR struct_addr) | |
1478 | { | |
1479 | int stack_offset, stack_alloc; | |
1480 | int int_argreg; | |
1481 | int float_argreg; | |
1482 | int double_argreg; | |
1483 | int float_arg_index = 0; | |
1484 | int double_arg_index = 0; | |
1485 | int argnum; | |
1486 | struct type *type; | |
1487 | CORE_ADDR regval; | |
1488 | char *val; | |
1489 | char valbuf[8]; | |
1490 | char valbuf_tmp[8]; | |
1491 | int len; | |
1492 | int argreg_size; | |
1493 | int fp_args[12]; | |
1494 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
1495 | ||
1496 | memset (fp_args, 0, sizeof (fp_args)); | |
1497 | ||
1498 | /* first force sp to a 8-byte alignment */ | |
1499 | sp = sp & ~7; | |
1500 | ||
1501 | /* The "struct return pointer" pseudo-argument has its own dedicated | |
1502 | register */ | |
1503 | ||
1504 | if (struct_return) | |
1505 | write_register (STRUCT_RETURN_REGNUM, struct_addr); | |
1506 | ||
1507 | /* Now make sure there's space on the stack */ | |
1508 | for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++) | |
1509 | stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 7) & ~7); | |
1510 | sp -= stack_alloc; /* make room on stack for args */ | |
1511 | ||
1512 | /* Now load as many as possible of the first arguments into | |
1513 | registers, and push the rest onto the stack. There are 64 bytes | |
1514 | in eight registers available. Loop thru args from first to last. */ | |
1515 | ||
1516 | int_argreg = ARG0_REGNUM; | |
1517 | float_argreg = FP0_REGNUM; | |
1518 | double_argreg = DR0_REGNUM; | |
1519 | ||
1520 | for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++) | |
1521 | { | |
1522 | type = VALUE_TYPE (args[argnum]); | |
1523 | len = TYPE_LENGTH (type); | |
1524 | memset (valbuf, 0, sizeof (valbuf)); | |
1525 | ||
1526 | if (TYPE_CODE (type) != TYPE_CODE_FLT) | |
1527 | { | |
1528 | argreg_size = REGISTER_RAW_SIZE (int_argreg); | |
1529 | ||
1530 | if (len < argreg_size) | |
1531 | { | |
1532 | /* value gets right-justified in the register or stack word */ | |
1533 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
1534 | memcpy (valbuf + argreg_size - len, | |
1535 | (char *) VALUE_CONTENTS (args[argnum]), len); | |
1536 | else | |
1537 | memcpy (valbuf, (char *) VALUE_CONTENTS (args[argnum]), len); | |
1538 | ||
1539 | val = valbuf; | |
1540 | } | |
1541 | else | |
1542 | val = (char *) VALUE_CONTENTS (args[argnum]); | |
1543 | ||
1544 | while (len > 0) | |
1545 | { | |
1546 | if (int_argreg > ARGLAST_REGNUM) | |
1547 | { | |
1548 | /* must go on the stack */ | |
1549 | write_memory (sp + stack_offset, val, argreg_size); | |
1550 | stack_offset += 8;/*argreg_size;*/ | |
1551 | } | |
1552 | /* NOTE WELL!!!!! This is not an "else if" clause!!! | |
1553 | That's because some *&^%$ things get passed on the stack | |
1554 | AND in the registers! */ | |
1555 | if (int_argreg <= ARGLAST_REGNUM) | |
1556 | { | |
1557 | /* there's room in a register */ | |
1558 | regval = extract_unsigned_integer (val, argreg_size); | |
1559 | write_register (int_argreg, regval); | |
1560 | } | |
1561 | /* Store the value 8 bytes at a time. This means that | |
1562 | things larger than 8 bytes may go partly in registers | |
1563 | and partly on the stack. FIXME: argreg is incremented | |
1564 | before we use its size. */ | |
1565 | len -= argreg_size; | |
1566 | val += argreg_size; | |
1567 | int_argreg++; | |
1568 | } | |
1569 | } | |
1570 | else | |
1571 | { | |
1572 | val = (char *) VALUE_CONTENTS (args[argnum]); | |
1573 | if (len == 4) | |
1574 | { | |
1575 | /* Where is it going to be stored? */ | |
1576 | while (fp_args[float_arg_index]) | |
1577 | float_arg_index ++; | |
1578 | ||
1579 | /* Now float_argreg points to the register where it | |
1580 | should be stored. Are we still within the allowed | |
1581 | register set? */ | |
1582 | if (float_arg_index <= FLOAT_ARGLAST_REGNUM) | |
1583 | { | |
1584 | /* Goes in FR0...FR11 */ | |
1585 | deprecated_write_register_gen (FP0_REGNUM + float_arg_index, | |
1586 | val); | |
1587 | fp_args[float_arg_index] = 1; | |
1588 | /* Skip the corresponding general argument register. */ | |
1589 | int_argreg ++; | |
1590 | } | |
1591 | else | |
1592 | ; | |
1593 | /* Store it as the integers, 8 bytes at the time, if | |
1594 | necessary spilling on the stack. */ | |
1595 | ||
1596 | } | |
1597 | else if (len == 8) | |
1598 | { | |
1599 | /* Where is it going to be stored? */ | |
1600 | while (fp_args[double_arg_index]) | |
1601 | double_arg_index += 2; | |
1602 | /* Now double_argreg points to the register | |
1603 | where it should be stored. | |
1604 | Are we still within the allowed register set? */ | |
1605 | if (double_arg_index < FLOAT_ARGLAST_REGNUM) | |
1606 | { | |
1607 | /* Goes in DR0...DR10 */ | |
1608 | /* The numbering of the DRi registers is consecutive, | |
1609 | i.e. includes odd numbers. */ | |
1610 | int double_register_offset = double_arg_index / 2; | |
1611 | int regnum = DR0_REGNUM + | |
1612 | double_register_offset; | |
1613 | #if 0 | |
1614 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) | |
1615 | { | |
1616 | memset (valbuf_tmp, 0, sizeof (valbuf_tmp)); | |
1617 | DEPRECATED_REGISTER_CONVERT_TO_VIRTUAL (regnum, | |
1618 | type, val, | |
1619 | valbuf_tmp); | |
1620 | val = valbuf_tmp; | |
1621 | } | |
1622 | #endif | |
1623 | /* Note: must use write_register_gen here instead | |
1624 | of regcache_raw_write, because | |
1625 | regcache_raw_write works only for real | |
1626 | registers, not pseudo. write_register_gen will | |
1627 | call the gdbarch function to do register | |
1628 | writes, and that will properly know how to deal | |
1629 | with pseudoregs. */ | |
1630 | deprecated_write_register_gen (regnum, val); | |
1631 | fp_args[double_arg_index] = 1; | |
1632 | fp_args[double_arg_index + 1] = 1; | |
1633 | /* Skip the corresponding general argument register. */ | |
1634 | int_argreg ++; | |
1635 | } | |
1636 | else | |
1637 | ; | |
1638 | /* Store it as the integers, 8 bytes at the time, if | |
1639 | necessary spilling on the stack. */ | |
1640 | } | |
1641 | } | |
1642 | } | |
1643 | return sp; | |
1644 | } | |
1645 | ||
1646 | /* Function: push_return_address (pc) | |
1647 | Set up the return address for the inferior function call. | |
1648 | Needed for targets where we don't actually execute a JSR/BSR instruction */ | |
1649 | ||
1650 | static CORE_ADDR | |
1651 | sh64_push_return_address (CORE_ADDR pc, CORE_ADDR sp) | |
1652 | { | |
e8a7b686 | 1653 | write_register (PR_REGNUM, entry_point_address ()); |
55ff77ac CV |
1654 | return sp; |
1655 | } | |
1656 | ||
1657 | /* Find a function's return value in the appropriate registers (in | |
1658 | regbuf), and copy it into valbuf. Extract from an array REGBUF | |
1659 | containing the (raw) register state a function return value of type | |
1660 | TYPE, and copy that, in virtual format, into VALBUF. */ | |
1661 | static void | |
1662 | sh64_extract_return_value (struct type *type, char *regbuf, char *valbuf) | |
1663 | { | |
1664 | int offset; | |
1665 | int return_register; | |
1666 | int len = TYPE_LENGTH (type); | |
1667 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
1668 | ||
1669 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
1670 | { | |
1671 | if (len == 4) | |
1672 | { | |
1673 | /* Return value stored in FP0_REGNUM */ | |
1674 | return_register = FP0_REGNUM; | |
1675 | offset = REGISTER_BYTE (return_register); | |
1676 | memcpy (valbuf, (char *) regbuf + offset, len); | |
1677 | } | |
1678 | else if (len == 8) | |
1679 | { | |
1680 | /* return value stored in DR0_REGNUM */ | |
1681 | DOUBLEST val; | |
1682 | ||
1683 | return_register = DR0_REGNUM; | |
1684 | offset = REGISTER_BYTE (return_register); | |
1685 | ||
1686 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) | |
1687 | floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, | |
1688 | (char *) regbuf + offset, &val); | |
1689 | else | |
1690 | floatformat_to_doublest (&floatformat_ieee_double_big, | |
1691 | (char *) regbuf + offset, &val); | |
1692 | deprecated_store_floating (valbuf, len, val); | |
1693 | } | |
1694 | } | |
1695 | else | |
1696 | { | |
1697 | if (len <= 8) | |
1698 | { | |
1699 | /* Result is in register 2. If smaller than 8 bytes, it is padded | |
1700 | at the most significant end. */ | |
1701 | return_register = DEFAULT_RETURN_REGNUM; | |
1702 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
1703 | offset = REGISTER_BYTE (return_register) + | |
1704 | REGISTER_RAW_SIZE (return_register) - len; | |
1705 | else | |
1706 | offset = REGISTER_BYTE (return_register); | |
1707 | memcpy (valbuf, (char *) regbuf + offset, len); | |
1708 | } | |
1709 | else | |
1710 | error ("bad size for return value"); | |
1711 | } | |
1712 | } | |
1713 | ||
1714 | /* Write into appropriate registers a function return value | |
1715 | of type TYPE, given in virtual format. | |
1716 | If the architecture is sh4 or sh3e, store a function's return value | |
1717 | in the R0 general register or in the FP0 floating point register, | |
1718 | depending on the type of the return value. In all the other cases | |
1719 | the result is stored in r0, left-justified. */ | |
1720 | ||
1721 | static void | |
1722 | sh64_store_return_value (struct type *type, char *valbuf) | |
1723 | { | |
1724 | char buf[64]; /* more than enough... */ | |
1725 | int len = TYPE_LENGTH (type); | |
1726 | ||
1727 | if (TYPE_CODE (type) == TYPE_CODE_FLT) | |
1728 | { | |
1729 | if (len == 4) | |
1730 | { | |
1731 | /* Return value stored in FP0_REGNUM */ | |
1732 | deprecated_write_register_gen (FP0_REGNUM, valbuf); | |
1733 | } | |
1734 | if (len == 8) | |
1735 | { | |
1736 | /* return value stored in DR0_REGNUM */ | |
1737 | /* FIXME: Implement */ | |
1738 | } | |
1739 | } | |
1740 | else | |
1741 | { | |
1742 | int return_register = DEFAULT_RETURN_REGNUM; | |
1743 | int offset = 0; | |
1744 | ||
1745 | if (len <= REGISTER_RAW_SIZE (return_register)) | |
1746 | { | |
1747 | /* Pad with zeros. */ | |
1748 | memset (buf, 0, REGISTER_RAW_SIZE (return_register)); | |
1749 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) | |
1750 | offset = 0; /*REGISTER_RAW_SIZE (return_register) - len;*/ | |
1751 | else | |
1752 | offset = REGISTER_RAW_SIZE (return_register) - len; | |
1753 | ||
1754 | memcpy (buf + offset, valbuf, len); | |
1755 | deprecated_write_register_gen (return_register, buf); | |
1756 | } | |
1757 | else | |
1758 | deprecated_write_register_gen (return_register, valbuf); | |
1759 | } | |
1760 | } | |
1761 | ||
1762 | static void | |
1763 | sh64_show_media_regs (void) | |
1764 | { | |
1765 | int i; | |
1766 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
1767 | ||
1768 | printf_filtered ("PC=%s SR=%016llx \n", | |
1769 | paddr (read_register (PC_REGNUM)), | |
1770 | (long long) read_register (SR_REGNUM)); | |
1771 | ||
1772 | printf_filtered ("SSR=%016llx SPC=%016llx \n", | |
1773 | (long long) read_register (SSR_REGNUM), | |
1774 | (long long) read_register (SPC_REGNUM)); | |
1775 | printf_filtered ("FPSCR=%016lx\n ", | |
1776 | (long) read_register (FPSCR_REGNUM)); | |
1777 | ||
1778 | for (i = 0; i < 64; i = i + 4) | |
1779 | printf_filtered ("\nR%d-R%d %016llx %016llx %016llx %016llx\n", | |
1780 | i, i + 3, | |
1781 | (long long) read_register (i + 0), | |
1782 | (long long) read_register (i + 1), | |
1783 | (long long) read_register (i + 2), | |
1784 | (long long) read_register (i + 3)); | |
1785 | ||
1786 | printf_filtered ("\n"); | |
1787 | ||
1788 | for (i = 0; i < 64; i = i + 8) | |
1789 | printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1790 | i, i + 7, | |
1791 | (long) read_register (FP0_REGNUM + i + 0), | |
1792 | (long) read_register (FP0_REGNUM + i + 1), | |
1793 | (long) read_register (FP0_REGNUM + i + 2), | |
1794 | (long) read_register (FP0_REGNUM + i + 3), | |
1795 | (long) read_register (FP0_REGNUM + i + 4), | |
1796 | (long) read_register (FP0_REGNUM + i + 5), | |
1797 | (long) read_register (FP0_REGNUM + i + 6), | |
1798 | (long) read_register (FP0_REGNUM + i + 7)); | |
1799 | } | |
1800 | ||
1801 | static void | |
1802 | sh64_show_compact_regs (void) | |
1803 | { | |
1804 | int i; | |
1805 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
1806 | ||
1807 | printf_filtered ("PC=%s \n", | |
1808 | paddr (read_register (PC_C_REGNUM))); | |
1809 | ||
1810 | printf_filtered ("GBR=%08lx MACH=%08lx MACL=%08lx PR=%08lx T=%08lx\n", | |
1811 | (long) read_register (GBR_C_REGNUM), | |
1812 | (long) read_register (MACH_C_REGNUM), | |
1813 | (long) read_register (MACL_C_REGNUM), | |
1814 | (long) read_register (PR_C_REGNUM), | |
1815 | (long) read_register (T_C_REGNUM)); | |
1816 | printf_filtered ("FPSCR=%08lx FPUL=%08lx\n", | |
1817 | (long) read_register (FPSCR_C_REGNUM), | |
1818 | (long) read_register (FPUL_C_REGNUM)); | |
1819 | ||
1820 | for (i = 0; i < 16; i = i + 4) | |
1821 | printf_filtered ("\nR%d-R%d %08lx %08lx %08lx %08lx\n", | |
1822 | i, i + 3, | |
1823 | (long) read_register (i + 0), | |
1824 | (long) read_register (i + 1), | |
1825 | (long) read_register (i + 2), | |
1826 | (long) read_register (i + 3)); | |
1827 | ||
1828 | printf_filtered ("\n"); | |
1829 | ||
1830 | for (i = 0; i < 16; i = i + 8) | |
1831 | printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n", | |
1832 | i, i + 7, | |
1833 | (long) read_register (FP0_REGNUM + i + 0), | |
1834 | (long) read_register (FP0_REGNUM + i + 1), | |
1835 | (long) read_register (FP0_REGNUM + i + 2), | |
1836 | (long) read_register (FP0_REGNUM + i + 3), | |
1837 | (long) read_register (FP0_REGNUM + i + 4), | |
1838 | (long) read_register (FP0_REGNUM + i + 5), | |
1839 | (long) read_register (FP0_REGNUM + i + 6), | |
1840 | (long) read_register (FP0_REGNUM + i + 7)); | |
1841 | } | |
1842 | ||
1843 | /*FIXME!!! This only shows the registers for shmedia, excluding the | |
1844 | pseudo registers. */ | |
1845 | void | |
1846 | sh64_show_regs (void) | |
1847 | { | |
1848 | if (deprecated_selected_frame | |
1849 | && pc_is_isa32 (get_frame_pc (deprecated_selected_frame))) | |
1850 | sh64_show_media_regs (); | |
1851 | else | |
1852 | sh64_show_compact_regs (); | |
1853 | } | |
1854 | ||
1855 | /* *INDENT-OFF* */ | |
1856 | /* | |
1857 | SH MEDIA MODE (ISA 32) | |
1858 | general registers (64-bit) 0-63 | |
1859 | 0 r0, r1, r2, r3, r4, r5, r6, r7, | |
1860 | 64 r8, r9, r10, r11, r12, r13, r14, r15, | |
1861 | 128 r16, r17, r18, r19, r20, r21, r22, r23, | |
1862 | 192 r24, r25, r26, r27, r28, r29, r30, r31, | |
1863 | 256 r32, r33, r34, r35, r36, r37, r38, r39, | |
1864 | 320 r40, r41, r42, r43, r44, r45, r46, r47, | |
1865 | 384 r48, r49, r50, r51, r52, r53, r54, r55, | |
1866 | 448 r56, r57, r58, r59, r60, r61, r62, r63, | |
1867 | ||
1868 | pc (64-bit) 64 | |
1869 | 512 pc, | |
1870 | ||
1871 | status reg., saved status reg., saved pc reg. (64-bit) 65-67 | |
1872 | 520 sr, ssr, spc, | |
1873 | ||
1874 | target registers (64-bit) 68-75 | |
1875 | 544 tr0, tr1, tr2, tr3, tr4, tr5, tr6, tr7, | |
1876 | ||
1877 | floating point state control register (32-bit) 76 | |
1878 | 608 fpscr, | |
1879 | ||
1880 | single precision floating point registers (32-bit) 77-140 | |
1881 | 612 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7, | |
1882 | 644 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15, | |
1883 | 676 fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23, | |
1884 | 708 fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31, | |
1885 | 740 fr32, fr33, fr34, fr35, fr36, fr37, fr38, fr39, | |
1886 | 772 fr40, fr41, fr42, fr43, fr44, fr45, fr46, fr47, | |
1887 | 804 fr48, fr49, fr50, fr51, fr52, fr53, fr54, fr55, | |
1888 | 836 fr56, fr57, fr58, fr59, fr60, fr61, fr62, fr63, | |
1889 | ||
1890 | TOTAL SPACE FOR REGISTERS: 868 bytes | |
1891 | ||
1892 | From here on they are all pseudo registers: no memory allocated. | |
1893 | REGISTER_BYTE returns the register byte for the base register. | |
1894 | ||
1895 | double precision registers (pseudo) 141-172 | |
1896 | dr0, dr2, dr4, dr6, dr8, dr10, dr12, dr14, | |
1897 | dr16, dr18, dr20, dr22, dr24, dr26, dr28, dr30, | |
1898 | dr32, dr34, dr36, dr38, dr40, dr42, dr44, dr46, | |
1899 | dr48, dr50, dr52, dr54, dr56, dr58, dr60, dr62, | |
1900 | ||
1901 | floating point pairs (pseudo) 173-204 | |
1902 | fp0, fp2, fp4, fp6, fp8, fp10, fp12, fp14, | |
1903 | fp16, fp18, fp20, fp22, fp24, fp26, fp28, fp30, | |
1904 | fp32, fp34, fp36, fp38, fp40, fp42, fp44, fp46, | |
1905 | fp48, fp50, fp52, fp54, fp56, fp58, fp60, fp62, | |
1906 | ||
1907 | floating point vectors (4 floating point regs) (pseudo) 205-220 | |
1908 | fv0, fv4, fv8, fv12, fv16, fv20, fv24, fv28, | |
1909 | fv32, fv36, fv40, fv44, fv48, fv52, fv56, fv60, | |
1910 | ||
1911 | SH COMPACT MODE (ISA 16) (all pseudo) 221-272 | |
1912 | r0_c, r1_c, r2_c, r3_c, r4_c, r5_c, r6_c, r7_c, | |
1913 | r8_c, r9_c, r10_c, r11_c, r12_c, r13_c, r14_c, r15_c, | |
1914 | pc_c, | |
1915 | gbr_c, mach_c, macl_c, pr_c, t_c, | |
1916 | fpscr_c, fpul_c, | |
1917 | fr0_c, fr1_c, fr2_c, fr3_c, fr4_c, fr5_c, fr6_c, fr7_c, | |
1918 | fr8_c, fr9_c, fr10_c, fr11_c, fr12_c, fr13_c, fr14_c, fr15_c | |
1919 | dr0_c, dr2_c, dr4_c, dr6_c, dr8_c, dr10_c, dr12_c, dr14_c | |
1920 | fv0_c, fv4_c, fv8_c, fv12_c | |
1921 | */ | |
1922 | /* *INDENT-ON* */ | |
1923 | static int | |
1924 | sh_sh64_register_byte (int reg_nr) | |
1925 | { | |
1926 | int base_regnum = -1; | |
1927 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
1928 | ||
1929 | /* If it is a pseudo register, get the number of the first floating | |
1930 | point register that is part of it. */ | |
1931 | if (reg_nr >= DR0_REGNUM | |
1932 | && reg_nr <= DR_LAST_REGNUM) | |
1933 | base_regnum = dr_reg_base_num (reg_nr); | |
1934 | ||
1935 | else if (reg_nr >= FPP0_REGNUM | |
1936 | && reg_nr <= FPP_LAST_REGNUM) | |
1937 | base_regnum = fpp_reg_base_num (reg_nr); | |
1938 | ||
1939 | else if (reg_nr >= FV0_REGNUM | |
1940 | && reg_nr <= FV_LAST_REGNUM) | |
1941 | base_regnum = fv_reg_base_num (reg_nr); | |
1942 | ||
1943 | /* sh compact pseudo register. FPSCR is a pathological case, need to | |
1944 | treat it as special. */ | |
1945 | else if ((reg_nr >= R0_C_REGNUM | |
1946 | && reg_nr <= FV_LAST_C_REGNUM) | |
1947 | && reg_nr != FPSCR_C_REGNUM) | |
1948 | base_regnum = sh64_compact_reg_base_num (reg_nr); | |
1949 | ||
1950 | /* Now return the offset in bytes within the register cache. */ | |
1951 | /* sh media pseudo register, i.e. any of DR, FFP, FV registers. */ | |
1952 | if (reg_nr >= DR0_REGNUM | |
1953 | && reg_nr <= FV_LAST_REGNUM) | |
1954 | return (base_regnum - FP0_REGNUM + 1) * 4 | |
1955 | + (TR7_REGNUM + 1) * 8; | |
1956 | ||
1957 | /* sh compact pseudo register: general register */ | |
1958 | if ((reg_nr >= R0_C_REGNUM | |
1959 | && reg_nr <= R_LAST_C_REGNUM)) | |
1960 | return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
1961 | ? base_regnum * 8 + 4 | |
1962 | : base_regnum * 8); | |
1963 | ||
1964 | /* sh compact pseudo register: */ | |
1965 | if (reg_nr == PC_C_REGNUM | |
1966 | || reg_nr == GBR_C_REGNUM | |
1967 | || reg_nr == MACL_C_REGNUM | |
1968 | || reg_nr == PR_C_REGNUM) | |
1969 | return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG | |
1970 | ? base_regnum * 8 + 4 | |
1971 | : base_regnum * 8); | |
1972 | ||
1973 | if (reg_nr == MACH_C_REGNUM) | |
1974 | return base_regnum * 8; | |
1975 | ||
1976 | if (reg_nr == T_C_REGNUM) | |
1977 | return base_regnum * 8; /* FIXME??? how do we get bit 0? Do we have to? */ | |
1978 | ||
1979 | /* sh compact pseudo register: floating point register */ | |
1980 | else if (reg_nr >= FP0_C_REGNUM | |
1981 | && reg_nr <= FV_LAST_C_REGNUM) | |
1982 | return (base_regnum - FP0_REGNUM) * 4 | |
1983 | + (TR7_REGNUM + 1) * 8 + 4; | |
1984 | ||
1985 | else if (reg_nr == FPSCR_C_REGNUM) | |
1986 | /* This is complicated, for now return the beginning of the | |
1987 | architectural FPSCR register. */ | |
1988 | return (TR7_REGNUM + 1) * 8; | |
1989 | ||
1990 | else if (reg_nr == FPUL_C_REGNUM) | |
1991 | return ((base_regnum - FP0_REGNUM) * 4 + | |
1992 | (TR7_REGNUM + 1) * 8 + 4); | |
1993 | ||
1994 | /* It is not a pseudo register. */ | |
1995 | /* It is a 64 bit register. */ | |
1996 | else if (reg_nr <= TR7_REGNUM) | |
1997 | return reg_nr * 8; | |
1998 | ||
1999 | /* It is a 32 bit register. */ | |
2000 | else if (reg_nr == FPSCR_REGNUM) | |
2001 | return (FPSCR_REGNUM * 8); | |
2002 | ||
2003 | /* It is floating point 32-bit register */ | |
2004 | else | |
2005 | return ((TR7_REGNUM + 1) * 8 | |
2006 | + (reg_nr - FP0_REGNUM + 1) * 4); | |
2007 | } | |
2008 | ||
2009 | static int | |
2010 | sh_sh64_register_raw_size (int reg_nr) | |
2011 | { | |
2012 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2013 | ||
2014 | if ((reg_nr >= DR0_REGNUM | |
2015 | && reg_nr <= DR_LAST_REGNUM) | |
2016 | || (reg_nr >= FPP0_REGNUM | |
2017 | && reg_nr <= FPP_LAST_REGNUM) | |
2018 | || (reg_nr >= DR0_C_REGNUM | |
2019 | && reg_nr <= DR_LAST_C_REGNUM) | |
2020 | || (reg_nr <= TR7_REGNUM)) | |
2021 | return 8; | |
2022 | ||
2023 | else if ((reg_nr >= FV0_REGNUM | |
2024 | && reg_nr <= FV_LAST_REGNUM) | |
2025 | || (reg_nr >= FV0_C_REGNUM | |
2026 | && reg_nr <= FV_LAST_C_REGNUM)) | |
2027 | return 16; | |
2028 | ||
2029 | else /* this covers also the 32-bit SH compact registers. */ | |
2030 | return 4; | |
2031 | } | |
2032 | ||
2033 | /* ??????? FIXME */ | |
2034 | static int | |
2035 | sh_sh64_register_virtual_size (int reg_nr) | |
2036 | { | |
2037 | if (reg_nr >= FP0_REGNUM | |
2038 | && reg_nr <= FP_LAST_REGNUM) | |
2039 | return 4; | |
2040 | else | |
2041 | return 8; | |
2042 | } | |
2043 | ||
2044 | static struct type * | |
2045 | sh_sh64_build_float_register_type (int high) | |
2046 | { | |
2047 | struct type *temp; | |
2048 | ||
2049 | temp = create_range_type (NULL, builtin_type_int, 0, high); | |
2050 | return create_array_type (NULL, builtin_type_float, temp); | |
2051 | } | |
2052 | ||
2053 | static struct type * | |
2054 | sh_sh64_register_virtual_type (int reg_nr) | |
2055 | { | |
2056 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2057 | ||
2058 | if ((reg_nr >= FP0_REGNUM | |
2059 | && reg_nr <= FP_LAST_REGNUM) | |
2060 | || (reg_nr >= FP0_C_REGNUM | |
2061 | && reg_nr <= FP_LAST_C_REGNUM)) | |
2062 | return builtin_type_float; | |
2063 | else if ((reg_nr >= DR0_REGNUM | |
2064 | && reg_nr <= DR_LAST_REGNUM) | |
2065 | || (reg_nr >= DR0_C_REGNUM | |
2066 | && reg_nr <= DR_LAST_C_REGNUM)) | |
2067 | return builtin_type_double; | |
2068 | else if (reg_nr >= FPP0_REGNUM | |
2069 | && reg_nr <= FPP_LAST_REGNUM) | |
2070 | return sh_sh64_build_float_register_type (1); | |
2071 | else if ((reg_nr >= FV0_REGNUM | |
2072 | && reg_nr <= FV_LAST_REGNUM) | |
2073 | ||(reg_nr >= FV0_C_REGNUM | |
2074 | && reg_nr <= FV_LAST_C_REGNUM)) | |
2075 | return sh_sh64_build_float_register_type (3); | |
2076 | else if (reg_nr == FPSCR_REGNUM) | |
2077 | return builtin_type_int; | |
2078 | else if (reg_nr >= R0_C_REGNUM | |
2079 | && reg_nr < FP0_C_REGNUM) | |
2080 | return builtin_type_int; | |
2081 | else | |
2082 | return builtin_type_long_long; | |
2083 | } | |
2084 | ||
2085 | static void | |
2086 | sh_sh64_register_convert_to_virtual (int regnum, struct type *type, | |
2087 | char *from, char *to) | |
2088 | { | |
2089 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2090 | ||
2091 | if (TARGET_BYTE_ORDER != BFD_ENDIAN_LITTLE) | |
2092 | { | |
2093 | /* It is a no-op. */ | |
2094 | memcpy (to, from, REGISTER_RAW_SIZE (regnum)); | |
2095 | return; | |
2096 | } | |
2097 | ||
2098 | if ((regnum >= DR0_REGNUM | |
2099 | && regnum <= DR_LAST_REGNUM) | |
2100 | || (regnum >= DR0_C_REGNUM | |
2101 | && regnum <= DR_LAST_C_REGNUM)) | |
2102 | { | |
2103 | DOUBLEST val; | |
2104 | floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, from, &val); | |
2105 | deprecated_store_floating(to, TYPE_LENGTH(type), val); | |
2106 | } | |
2107 | else | |
2108 | error("sh_register_convert_to_virtual called with non DR register number"); | |
2109 | } | |
2110 | ||
2111 | static void | |
2112 | sh_sh64_register_convert_to_raw (struct type *type, int regnum, | |
2113 | const void *from, void *to) | |
2114 | { | |
2115 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2116 | ||
2117 | if (TARGET_BYTE_ORDER != BFD_ENDIAN_LITTLE) | |
2118 | { | |
2119 | /* It is a no-op. */ | |
2120 | memcpy (to, from, REGISTER_RAW_SIZE (regnum)); | |
2121 | return; | |
2122 | } | |
2123 | ||
2124 | if ((regnum >= DR0_REGNUM | |
2125 | && regnum <= DR_LAST_REGNUM) | |
2126 | || (regnum >= DR0_C_REGNUM | |
2127 | && regnum <= DR_LAST_C_REGNUM)) | |
2128 | { | |
2129 | DOUBLEST val = deprecated_extract_floating (from, TYPE_LENGTH(type)); | |
2130 | floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword, &val, to); | |
2131 | } | |
2132 | else | |
2133 | error("sh_register_convert_to_raw called with non DR register number"); | |
2134 | } | |
2135 | ||
2136 | static void | |
2137 | sh64_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, | |
2138 | int reg_nr, void *buffer) | |
2139 | { | |
2140 | int base_regnum; | |
2141 | int portion; | |
2142 | int offset = 0; | |
2143 | char temp_buffer[MAX_REGISTER_SIZE]; | |
2144 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2145 | ||
2146 | if (reg_nr >= DR0_REGNUM | |
2147 | && reg_nr <= DR_LAST_REGNUM) | |
2148 | { | |
2149 | base_regnum = dr_reg_base_num (reg_nr); | |
2150 | ||
2151 | /* Build the value in the provided buffer. */ | |
2152 | /* DR regs are double precision registers obtained by | |
2153 | concatenating 2 single precision floating point registers. */ | |
2154 | for (portion = 0; portion < 2; portion++) | |
2155 | regcache_raw_read (regcache, base_regnum + portion, | |
2156 | (temp_buffer | |
2157 | + REGISTER_RAW_SIZE (base_regnum) * portion)); | |
2158 | ||
2159 | /* We must pay attention to the endiannes. */ | |
2160 | sh_sh64_register_convert_to_virtual (reg_nr, REGISTER_VIRTUAL_TYPE (reg_nr), | |
2161 | temp_buffer, buffer); | |
2162 | ||
2163 | } | |
2164 | ||
2165 | else if (reg_nr >= FPP0_REGNUM | |
2166 | && reg_nr <= FPP_LAST_REGNUM) | |
2167 | { | |
2168 | base_regnum = fpp_reg_base_num (reg_nr); | |
2169 | ||
2170 | /* Build the value in the provided buffer. */ | |
2171 | /* FPP regs are pairs of single precision registers obtained by | |
2172 | concatenating 2 single precision floating point registers. */ | |
2173 | for (portion = 0; portion < 2; portion++) | |
2174 | regcache_raw_read (regcache, base_regnum + portion, | |
2175 | ((char *) buffer | |
2176 | + REGISTER_RAW_SIZE (base_regnum) * portion)); | |
2177 | } | |
2178 | ||
2179 | else if (reg_nr >= FV0_REGNUM | |
2180 | && reg_nr <= FV_LAST_REGNUM) | |
2181 | { | |
2182 | base_regnum = fv_reg_base_num (reg_nr); | |
2183 | ||
2184 | /* Build the value in the provided buffer. */ | |
2185 | /* FV regs are vectors of single precision registers obtained by | |
2186 | concatenating 4 single precision floating point registers. */ | |
2187 | for (portion = 0; portion < 4; portion++) | |
2188 | regcache_raw_read (regcache, base_regnum + portion, | |
2189 | ((char *) buffer | |
2190 | + REGISTER_RAW_SIZE (base_regnum) * portion)); | |
2191 | } | |
2192 | ||
2193 | /* sh compact pseudo registers. 1-to-1 with a shmedia register */ | |
2194 | else if (reg_nr >= R0_C_REGNUM | |
2195 | && reg_nr <= T_C_REGNUM) | |
2196 | { | |
2197 | base_regnum = sh64_compact_reg_base_num (reg_nr); | |
2198 | ||
2199 | /* Build the value in the provided buffer. */ | |
2200 | regcache_raw_read (regcache, base_regnum, temp_buffer); | |
2201 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
2202 | offset = 4; | |
2203 | memcpy (buffer, temp_buffer + offset, 4); /* get LOWER 32 bits only????*/ | |
2204 | } | |
2205 | ||
2206 | else if (reg_nr >= FP0_C_REGNUM | |
2207 | && reg_nr <= FP_LAST_C_REGNUM) | |
2208 | { | |
2209 | base_regnum = sh64_compact_reg_base_num (reg_nr); | |
2210 | ||
2211 | /* Build the value in the provided buffer. */ | |
2212 | /* Floating point registers map 1-1 to the media fp regs, | |
2213 | they have the same size and endienness. */ | |
2214 | regcache_raw_read (regcache, base_regnum, buffer); | |
2215 | } | |
2216 | ||
2217 | else if (reg_nr >= DR0_C_REGNUM | |
2218 | && reg_nr <= DR_LAST_C_REGNUM) | |
2219 | { | |
2220 | base_regnum = sh64_compact_reg_base_num (reg_nr); | |
2221 | ||
2222 | /* DR_C regs are double precision registers obtained by | |
2223 | concatenating 2 single precision floating point registers. */ | |
2224 | for (portion = 0; portion < 2; portion++) | |
2225 | regcache_raw_read (regcache, base_regnum + portion, | |
2226 | (temp_buffer | |
2227 | + REGISTER_RAW_SIZE (base_regnum) * portion)); | |
2228 | ||
2229 | /* We must pay attention to the endiannes. */ | |
2230 | sh_sh64_register_convert_to_virtual (reg_nr, REGISTER_VIRTUAL_TYPE (reg_nr), | |
2231 | temp_buffer, buffer); | |
2232 | } | |
2233 | ||
2234 | else if (reg_nr >= FV0_C_REGNUM | |
2235 | && reg_nr <= FV_LAST_C_REGNUM) | |
2236 | { | |
2237 | base_regnum = sh64_compact_reg_base_num (reg_nr); | |
2238 | ||
2239 | /* Build the value in the provided buffer. */ | |
2240 | /* FV_C regs are vectors of single precision registers obtained by | |
2241 | concatenating 4 single precision floating point registers. */ | |
2242 | for (portion = 0; portion < 4; portion++) | |
2243 | regcache_raw_read (regcache, base_regnum + portion, | |
2244 | ((char *) buffer | |
2245 | + REGISTER_RAW_SIZE (base_regnum) * portion)); | |
2246 | } | |
2247 | ||
2248 | else if (reg_nr == FPSCR_C_REGNUM) | |
2249 | { | |
2250 | int fpscr_base_regnum; | |
2251 | int sr_base_regnum; | |
2252 | unsigned int fpscr_value; | |
2253 | unsigned int sr_value; | |
2254 | unsigned int fpscr_c_value; | |
2255 | unsigned int fpscr_c_part1_value; | |
2256 | unsigned int fpscr_c_part2_value; | |
2257 | ||
2258 | fpscr_base_regnum = FPSCR_REGNUM; | |
2259 | sr_base_regnum = SR_REGNUM; | |
2260 | ||
2261 | /* Build the value in the provided buffer. */ | |
2262 | /* FPSCR_C is a very weird register that contains sparse bits | |
2263 | from the FPSCR and the SR architectural registers. | |
2264 | Specifically: */ | |
2265 | /* *INDENT-OFF* */ | |
2266 | /* | |
2267 | FPSRC_C bit | |
2268 | 0 Bit 0 of FPSCR | |
2269 | 1 reserved | |
2270 | 2-17 Bit 2-18 of FPSCR | |
2271 | 18-20 Bits 12,13,14 of SR | |
2272 | 21-31 reserved | |
2273 | */ | |
2274 | /* *INDENT-ON* */ | |
2275 | /* Get FPSCR into a local buffer */ | |
2276 | regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer); | |
2277 | /* Get value as an int. */ | |
2278 | fpscr_value = extract_unsigned_integer (temp_buffer, 4); | |
2279 | /* Get SR into a local buffer */ | |
2280 | regcache_raw_read (regcache, sr_base_regnum, temp_buffer); | |
2281 | /* Get value as an int. */ | |
2282 | sr_value = extract_unsigned_integer (temp_buffer, 4); | |
2283 | /* Build the new value. */ | |
2284 | fpscr_c_part1_value = fpscr_value & 0x3fffd; | |
2285 | fpscr_c_part2_value = (sr_value & 0x7000) << 6; | |
2286 | fpscr_c_value = fpscr_c_part1_value | fpscr_c_part2_value; | |
2287 | /* Store that in out buffer!!! */ | |
2288 | store_unsigned_integer (buffer, 4, fpscr_c_value); | |
2289 | /* FIXME There is surely an endianness gotcha here. */ | |
2290 | } | |
2291 | ||
2292 | else if (reg_nr == FPUL_C_REGNUM) | |
2293 | { | |
2294 | base_regnum = sh64_compact_reg_base_num (reg_nr); | |
2295 | ||
2296 | /* FPUL_C register is floating point register 32, | |
2297 | same size, same endianness. */ | |
2298 | regcache_raw_read (regcache, base_regnum, buffer); | |
2299 | } | |
2300 | } | |
2301 | ||
2302 | static void | |
2303 | sh64_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
2304 | int reg_nr, const void *buffer) | |
2305 | { | |
2306 | int base_regnum, portion; | |
2307 | int offset; | |
2308 | char temp_buffer[MAX_REGISTER_SIZE]; | |
2309 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2310 | ||
2311 | if (reg_nr >= DR0_REGNUM | |
2312 | && reg_nr <= DR_LAST_REGNUM) | |
2313 | { | |
2314 | base_regnum = dr_reg_base_num (reg_nr); | |
2315 | /* We must pay attention to the endiannes. */ | |
2316 | sh_sh64_register_convert_to_raw (REGISTER_VIRTUAL_TYPE (reg_nr), reg_nr, | |
2317 | buffer, temp_buffer); | |
2318 | ||
2319 | ||
2320 | /* Write the real regs for which this one is an alias. */ | |
2321 | for (portion = 0; portion < 2; portion++) | |
2322 | regcache_raw_write (regcache, base_regnum + portion, | |
2323 | (temp_buffer | |
2324 | + REGISTER_RAW_SIZE (base_regnum) * portion)); | |
2325 | } | |
2326 | ||
2327 | else if (reg_nr >= FPP0_REGNUM | |
2328 | && reg_nr <= FPP_LAST_REGNUM) | |
2329 | { | |
2330 | base_regnum = fpp_reg_base_num (reg_nr); | |
2331 | ||
2332 | /* Write the real regs for which this one is an alias. */ | |
2333 | for (portion = 0; portion < 2; portion++) | |
2334 | regcache_raw_write (regcache, base_regnum + portion, | |
2335 | ((char *) buffer | |
2336 | + REGISTER_RAW_SIZE (base_regnum) * portion)); | |
2337 | } | |
2338 | ||
2339 | else if (reg_nr >= FV0_REGNUM | |
2340 | && reg_nr <= FV_LAST_REGNUM) | |
2341 | { | |
2342 | base_regnum = fv_reg_base_num (reg_nr); | |
2343 | ||
2344 | /* Write the real regs for which this one is an alias. */ | |
2345 | for (portion = 0; portion < 4; portion++) | |
2346 | regcache_raw_write (regcache, base_regnum + portion, | |
2347 | ((char *) buffer | |
2348 | + REGISTER_RAW_SIZE (base_regnum) * portion)); | |
2349 | } | |
2350 | ||
2351 | /* sh compact general pseudo registers. 1-to-1 with a shmedia | |
2352 | register but only 4 bytes of it. */ | |
2353 | else if (reg_nr >= R0_C_REGNUM | |
2354 | && reg_nr <= T_C_REGNUM) | |
2355 | { | |
2356 | base_regnum = sh64_compact_reg_base_num (reg_nr); | |
2357 | /* reg_nr is 32 bit here, and base_regnum is 64 bits. */ | |
2358 | if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) | |
2359 | offset = 4; | |
2360 | else | |
2361 | offset = 0; | |
2362 | /* Let's read the value of the base register into a temporary | |
2363 | buffer, so that overwriting the last four bytes with the new | |
2364 | value of the pseudo will leave the upper 4 bytes unchanged. */ | |
2365 | regcache_raw_read (regcache, base_regnum, temp_buffer); | |
2366 | /* Write as an 8 byte quantity */ | |
2367 | memcpy (temp_buffer + offset, buffer, 4); | |
2368 | regcache_raw_write (regcache, base_regnum, temp_buffer); | |
2369 | } | |
2370 | ||
2371 | /* sh floating point compact pseudo registers. 1-to-1 with a shmedia | |
2372 | registers. Both are 4 bytes. */ | |
2373 | else if (reg_nr >= FP0_C_REGNUM | |
2374 | && reg_nr <= FP_LAST_C_REGNUM) | |
2375 | { | |
2376 | base_regnum = sh64_compact_reg_base_num (reg_nr); | |
2377 | regcache_raw_write (regcache, base_regnum, buffer); | |
2378 | } | |
2379 | ||
2380 | else if (reg_nr >= DR0_C_REGNUM | |
2381 | && reg_nr <= DR_LAST_C_REGNUM) | |
2382 | { | |
2383 | base_regnum = sh64_compact_reg_base_num (reg_nr); | |
2384 | for (portion = 0; portion < 2; portion++) | |
2385 | { | |
2386 | /* We must pay attention to the endiannes. */ | |
2387 | sh_sh64_register_convert_to_raw (REGISTER_VIRTUAL_TYPE (reg_nr), reg_nr, | |
2388 | buffer, temp_buffer); | |
2389 | ||
2390 | regcache_raw_write (regcache, base_regnum + portion, | |
2391 | (temp_buffer | |
2392 | + REGISTER_RAW_SIZE (base_regnum) * portion)); | |
2393 | } | |
2394 | } | |
2395 | ||
2396 | else if (reg_nr >= FV0_C_REGNUM | |
2397 | && reg_nr <= FV_LAST_C_REGNUM) | |
2398 | { | |
2399 | base_regnum = sh64_compact_reg_base_num (reg_nr); | |
2400 | ||
2401 | for (portion = 0; portion < 4; portion++) | |
2402 | { | |
2403 | regcache_raw_write (regcache, base_regnum + portion, | |
2404 | ((char *) buffer | |
2405 | + REGISTER_RAW_SIZE (base_regnum) * portion)); | |
2406 | } | |
2407 | } | |
2408 | ||
2409 | else if (reg_nr == FPSCR_C_REGNUM) | |
2410 | { | |
2411 | int fpscr_base_regnum; | |
2412 | int sr_base_regnum; | |
2413 | unsigned int fpscr_value; | |
2414 | unsigned int sr_value; | |
2415 | unsigned int old_fpscr_value; | |
2416 | unsigned int old_sr_value; | |
2417 | unsigned int fpscr_c_value; | |
2418 | unsigned int fpscr_mask; | |
2419 | unsigned int sr_mask; | |
2420 | ||
2421 | fpscr_base_regnum = FPSCR_REGNUM; | |
2422 | sr_base_regnum = SR_REGNUM; | |
2423 | ||
2424 | /* FPSCR_C is a very weird register that contains sparse bits | |
2425 | from the FPSCR and the SR architectural registers. | |
2426 | Specifically: */ | |
2427 | /* *INDENT-OFF* */ | |
2428 | /* | |
2429 | FPSRC_C bit | |
2430 | 0 Bit 0 of FPSCR | |
2431 | 1 reserved | |
2432 | 2-17 Bit 2-18 of FPSCR | |
2433 | 18-20 Bits 12,13,14 of SR | |
2434 | 21-31 reserved | |
2435 | */ | |
2436 | /* *INDENT-ON* */ | |
2437 | /* Get value as an int. */ | |
2438 | fpscr_c_value = extract_unsigned_integer (buffer, 4); | |
2439 | ||
2440 | /* Build the new values. */ | |
2441 | fpscr_mask = 0x0003fffd; | |
2442 | sr_mask = 0x001c0000; | |
2443 | ||
2444 | fpscr_value = fpscr_c_value & fpscr_mask; | |
2445 | sr_value = (fpscr_value & sr_mask) >> 6; | |
2446 | ||
2447 | regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer); | |
2448 | old_fpscr_value = extract_unsigned_integer (temp_buffer, 4); | |
2449 | old_fpscr_value &= 0xfffc0002; | |
2450 | fpscr_value |= old_fpscr_value; | |
2451 | store_unsigned_integer (temp_buffer, 4, fpscr_value); | |
2452 | regcache_raw_write (regcache, fpscr_base_regnum, temp_buffer); | |
2453 | ||
2454 | regcache_raw_read (regcache, sr_base_regnum, temp_buffer); | |
2455 | old_sr_value = extract_unsigned_integer (temp_buffer, 4); | |
2456 | old_sr_value &= 0xffff8fff; | |
2457 | sr_value |= old_sr_value; | |
2458 | store_unsigned_integer (temp_buffer, 4, sr_value); | |
2459 | regcache_raw_write (regcache, sr_base_regnum, temp_buffer); | |
2460 | } | |
2461 | ||
2462 | else if (reg_nr == FPUL_C_REGNUM) | |
2463 | { | |
2464 | base_regnum = sh64_compact_reg_base_num (reg_nr); | |
2465 | regcache_raw_write (regcache, base_regnum, buffer); | |
2466 | } | |
2467 | } | |
2468 | ||
2469 | /* Floating point vector of 4 float registers. */ | |
2470 | static void | |
2471 | do_fv_register_info (struct gdbarch *gdbarch, struct ui_file *file, | |
2472 | int fv_regnum) | |
2473 | { | |
2474 | int first_fp_reg_num = fv_reg_base_num (fv_regnum); | |
2475 | fprintf_filtered (file, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n", | |
2476 | fv_regnum - FV0_REGNUM, | |
2477 | (int) read_register (first_fp_reg_num), | |
2478 | (int) read_register (first_fp_reg_num + 1), | |
2479 | (int) read_register (first_fp_reg_num + 2), | |
2480 | (int) read_register (first_fp_reg_num + 3)); | |
2481 | } | |
2482 | ||
2483 | /* Floating point vector of 4 float registers, compact mode. */ | |
2484 | static void | |
2485 | do_fv_c_register_info (int fv_regnum) | |
2486 | { | |
2487 | int first_fp_reg_num = sh64_compact_reg_base_num (fv_regnum); | |
2488 | printf_filtered ("fv%d_c\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n", | |
2489 | fv_regnum - FV0_C_REGNUM, | |
2490 | (int) read_register (first_fp_reg_num), | |
2491 | (int) read_register (first_fp_reg_num + 1), | |
2492 | (int) read_register (first_fp_reg_num + 2), | |
2493 | (int) read_register (first_fp_reg_num + 3)); | |
2494 | } | |
2495 | ||
2496 | /* Pairs of single regs. The DR are instead double precision | |
2497 | registers. */ | |
2498 | static void | |
2499 | do_fpp_register_info (int fpp_regnum) | |
2500 | { | |
2501 | int first_fp_reg_num = fpp_reg_base_num (fpp_regnum); | |
2502 | ||
2503 | printf_filtered ("fpp%d\t0x%08x\t0x%08x\n", | |
2504 | fpp_regnum - FPP0_REGNUM, | |
2505 | (int) read_register (first_fp_reg_num), | |
2506 | (int) read_register (first_fp_reg_num + 1)); | |
2507 | } | |
2508 | ||
2509 | /* Double precision registers. */ | |
2510 | static void | |
2511 | do_dr_register_info (struct gdbarch *gdbarch, struct ui_file *file, | |
2512 | int dr_regnum) | |
2513 | { | |
2514 | int first_fp_reg_num = dr_reg_base_num (dr_regnum); | |
2515 | ||
2516 | fprintf_filtered (file, "dr%d\t0x%08x%08x\n", | |
2517 | dr_regnum - DR0_REGNUM, | |
2518 | (int) read_register (first_fp_reg_num), | |
2519 | (int) read_register (first_fp_reg_num + 1)); | |
2520 | } | |
2521 | ||
2522 | /* Double precision registers, compact mode. */ | |
2523 | static void | |
2524 | do_dr_c_register_info (int dr_regnum) | |
2525 | { | |
2526 | int first_fp_reg_num = sh64_compact_reg_base_num (dr_regnum); | |
2527 | ||
2528 | printf_filtered ("dr%d_c\t0x%08x%08x\n", | |
2529 | dr_regnum - DR0_C_REGNUM, | |
2530 | (int) read_register (first_fp_reg_num), | |
2531 | (int) read_register (first_fp_reg_num +1)); | |
2532 | } | |
2533 | ||
2534 | /* General register in compact mode. */ | |
2535 | static void | |
2536 | do_r_c_register_info (int r_c_regnum) | |
2537 | { | |
2538 | int regnum = sh64_compact_reg_base_num (r_c_regnum); | |
2539 | ||
2540 | printf_filtered ("r%d_c\t0x%08x\n", | |
2541 | r_c_regnum - R0_C_REGNUM, | |
2542 | /*FIXME!!!*/ (int) read_register (regnum)); | |
2543 | } | |
2544 | ||
2545 | /* FIXME:!! THIS SHOULD TAKE CARE OF GETTING THE RIGHT PORTION OF THE | |
2546 | shmedia REGISTERS. */ | |
2547 | /* Control registers, compact mode. */ | |
2548 | static void | |
2549 | do_cr_c_register_info (int cr_c_regnum) | |
2550 | { | |
2551 | switch (cr_c_regnum) | |
2552 | { | |
2553 | case 237: printf_filtered ("pc_c\t0x%08x\n", (int) read_register (cr_c_regnum)); | |
2554 | break; | |
2555 | case 238: printf_filtered ("gbr_c\t0x%08x\n", (int) read_register (cr_c_regnum)); | |
2556 | break; | |
2557 | case 239: printf_filtered ("mach_c\t0x%08x\n", (int) read_register (cr_c_regnum)); | |
2558 | break; | |
2559 | case 240: printf_filtered ("macl_c\t0x%08x\n", (int) read_register (cr_c_regnum)); | |
2560 | break; | |
2561 | case 241: printf_filtered ("pr_c\t0x%08x\n", (int) read_register (cr_c_regnum)); | |
2562 | break; | |
2563 | case 242: printf_filtered ("t_c\t0x%08x\n", (int) read_register (cr_c_regnum)); | |
2564 | break; | |
2565 | case 243: printf_filtered ("fpscr_c\t0x%08x\n", (int) read_register (cr_c_regnum)); | |
2566 | break; | |
2567 | case 244: printf_filtered ("fpul_c\t0x%08x\n", (int)read_register (cr_c_regnum)); | |
2568 | break; | |
2569 | } | |
2570 | } | |
2571 | ||
2572 | static void | |
2573 | sh_do_fp_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum) | |
2574 | { /* do values for FP (float) regs */ | |
2575 | char *raw_buffer; | |
2576 | double flt; /* double extracted from raw hex data */ | |
2577 | int inv; | |
2578 | int j; | |
2579 | ||
2580 | /* Allocate space for the float. */ | |
2581 | raw_buffer = (char *) alloca (register_size (gdbarch, FP0_REGNUM)); | |
2582 | ||
2583 | /* Get the data in raw format. */ | |
2584 | if (!frame_register_read (get_selected_frame (), regnum, raw_buffer)) | |
2585 | error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum)); | |
2586 | ||
2587 | /* Get the register as a number */ | |
2588 | flt = unpack_double (builtin_type_float, raw_buffer, &inv); | |
2589 | ||
2590 | /* Print the name and some spaces. */ | |
2591 | fputs_filtered (REGISTER_NAME (regnum), file); | |
2592 | print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file); | |
2593 | ||
2594 | /* Print the value. */ | |
2595 | if (inv) | |
2596 | fprintf_filtered (file, "<invalid float>"); | |
2597 | else | |
2598 | fprintf_filtered (file, "%-10.9g", flt); | |
2599 | ||
2600 | /* Print the fp register as hex. */ | |
2601 | fprintf_filtered (file, "\t(raw 0x"); | |
2602 | for (j = 0; j < register_size (gdbarch, regnum); j++) | |
2603 | { | |
2604 | register int idx = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? j | |
2605 | : register_size (gdbarch, regnum) - 1 - j; | |
2606 | fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[idx]); | |
2607 | } | |
2608 | fprintf_filtered (file, ")"); | |
2609 | fprintf_filtered (file, "\n"); | |
2610 | } | |
2611 | ||
2612 | static void | |
2613 | sh64_do_pseudo_register (int regnum) | |
2614 | { | |
2615 | /* All the sh64-compact mode registers are pseudo registers. */ | |
2616 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2617 | ||
2618 | if (regnum < NUM_REGS | |
2619 | || regnum >= NUM_REGS + NUM_PSEUDO_REGS_SH_MEDIA + NUM_PSEUDO_REGS_SH_COMPACT) | |
2620 | internal_error (__FILE__, __LINE__, | |
2621 | "Invalid pseudo register number %d\n", regnum); | |
2622 | ||
2623 | else if ((regnum >= DR0_REGNUM | |
2624 | && regnum <= DR_LAST_REGNUM)) | |
2625 | do_dr_register_info (current_gdbarch, gdb_stdout, regnum); | |
2626 | ||
2627 | else if ((regnum >= DR0_C_REGNUM | |
2628 | && regnum <= DR_LAST_C_REGNUM)) | |
2629 | do_dr_c_register_info (regnum); | |
2630 | ||
2631 | else if ((regnum >= FV0_REGNUM | |
2632 | && regnum <= FV_LAST_REGNUM)) | |
2633 | do_fv_register_info (current_gdbarch, gdb_stdout, regnum); | |
2634 | ||
2635 | else if ((regnum >= FV0_C_REGNUM | |
2636 | && regnum <= FV_LAST_C_REGNUM)) | |
2637 | do_fv_c_register_info (regnum); | |
2638 | ||
2639 | else if (regnum >= FPP0_REGNUM | |
2640 | && regnum <= FPP_LAST_REGNUM) | |
2641 | do_fpp_register_info (regnum); | |
2642 | ||
2643 | else if (regnum >= R0_C_REGNUM | |
2644 | && regnum <= R_LAST_C_REGNUM) | |
2645 | do_r_c_register_info (regnum); /* FIXME, this function will not print the right format */ | |
2646 | ||
2647 | else if (regnum >= FP0_C_REGNUM | |
2648 | && regnum <= FP_LAST_C_REGNUM) | |
2649 | sh_do_fp_register (current_gdbarch, gdb_stdout, regnum); /* this should work also for pseudoregs */ | |
2650 | ||
2651 | else if (regnum >= PC_C_REGNUM | |
2652 | && regnum <= FPUL_C_REGNUM) | |
2653 | do_cr_c_register_info (regnum); | |
2654 | ||
2655 | } | |
2656 | ||
2657 | static void | |
2658 | sh_do_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum) | |
2659 | { | |
2660 | char raw_buffer[MAX_REGISTER_SIZE]; | |
2661 | ||
2662 | fputs_filtered (REGISTER_NAME (regnum), file); | |
2663 | print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file); | |
2664 | ||
2665 | /* Get the data in raw format. */ | |
2666 | if (!frame_register_read (get_selected_frame (), regnum, raw_buffer)) | |
2667 | fprintf_filtered (file, "*value not available*\n"); | |
2668 | ||
2669 | val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0, | |
2670 | file, 'x', 1, 0, Val_pretty_default); | |
2671 | fprintf_filtered (file, "\t"); | |
2672 | val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0, | |
2673 | file, 0, 1, 0, Val_pretty_default); | |
2674 | fprintf_filtered (file, "\n"); | |
2675 | } | |
2676 | ||
2677 | static void | |
2678 | sh_print_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum) | |
2679 | { | |
2680 | if (regnum < 0 || regnum >= NUM_REGS + NUM_PSEUDO_REGS) | |
2681 | internal_error (__FILE__, __LINE__, | |
2682 | "Invalid register number %d\n", regnum); | |
2683 | ||
2684 | else if (regnum >= 0 && regnum < NUM_REGS) | |
2685 | { | |
2686 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT) | |
2687 | sh_do_fp_register (gdbarch, file, regnum); /* FP regs */ | |
2688 | else | |
2689 | sh_do_register (gdbarch, file, regnum); /* All other regs */ | |
2690 | } | |
2691 | ||
2692 | else if (regnum < NUM_REGS + NUM_PSEUDO_REGS) | |
2693 | sh64_do_pseudo_register (regnum); | |
2694 | } | |
2695 | ||
2696 | static void | |
2697 | sh_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, | |
2698 | struct frame_info *frame, int regnum, int fpregs) | |
2699 | { | |
2700 | if (regnum != -1) /* do one specified register */ | |
2701 | { | |
2702 | if (*(REGISTER_NAME (regnum)) == '\0') | |
2703 | error ("Not a valid register for the current processor type"); | |
2704 | ||
2705 | sh_print_register (gdbarch, file, regnum); | |
2706 | } | |
2707 | else | |
2708 | /* do all (or most) registers */ | |
2709 | { | |
2710 | regnum = 0; | |
2711 | while (regnum < NUM_REGS) | |
2712 | { | |
2713 | /* If the register name is empty, it is undefined for this | |
2714 | processor, so don't display anything. */ | |
2715 | if (REGISTER_NAME (regnum) == NULL | |
2716 | || *(REGISTER_NAME (regnum)) == '\0') | |
2717 | { | |
2718 | regnum++; | |
2719 | continue; | |
2720 | } | |
2721 | ||
2722 | if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT) | |
2723 | { | |
2724 | if (fpregs) | |
2725 | { | |
2726 | /* true for "INFO ALL-REGISTERS" command */ | |
2727 | sh_do_fp_register (gdbarch, file, regnum); /* FP regs */ | |
2728 | regnum ++; | |
2729 | } | |
2730 | else | |
2731 | regnum += FP_LAST_REGNUM - FP0_REGNUM; /* skip FP regs */ | |
2732 | } | |
2733 | else | |
2734 | { | |
2735 | sh_do_register (gdbarch, file, regnum); /* All other regs */ | |
2736 | regnum++; | |
2737 | } | |
2738 | } | |
2739 | ||
2740 | if (fpregs) | |
2741 | while (regnum < NUM_REGS + NUM_PSEUDO_REGS) | |
2742 | { | |
2743 | sh64_do_pseudo_register (regnum); | |
2744 | regnum++; | |
2745 | } | |
2746 | } | |
2747 | } | |
2748 | ||
2749 | static void | |
2750 | sh_compact_do_registers_info (int regnum, int fpregs) | |
2751 | { | |
2752 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
2753 | if (regnum != -1) /* do one specified register */ | |
2754 | { | |
2755 | if (*(REGISTER_NAME (regnum)) == '\0') | |
2756 | error ("Not a valid register for the current processor type"); | |
2757 | ||
2758 | if (regnum >= 0 && regnum < R0_C_REGNUM) | |
2759 | error ("Not a valid register for the current processor mode."); | |
2760 | ||
2761 | sh_print_register (current_gdbarch, gdb_stdout, regnum); | |
2762 | } | |
2763 | else | |
2764 | /* do all compact registers */ | |
2765 | { | |
2766 | regnum = R0_C_REGNUM; | |
2767 | while (regnum < NUM_REGS + NUM_PSEUDO_REGS) | |
2768 | { | |
2769 | sh64_do_pseudo_register (regnum); | |
2770 | regnum++; | |
2771 | } | |
2772 | } | |
2773 | } | |
2774 | ||
2775 | static void | |
2776 | sh64_do_registers_info (int regnum, int fpregs) | |
2777 | { | |
2778 | if (pc_is_isa32 (get_frame_pc (deprecated_selected_frame))) | |
2779 | sh_print_registers_info (current_gdbarch, gdb_stdout, | |
2780 | deprecated_selected_frame, regnum, fpregs); | |
2781 | else | |
2782 | sh_compact_do_registers_info (regnum, fpregs); | |
2783 | } | |
2784 | ||
2785 | #ifdef SVR4_SHARED_LIBS | |
2786 | ||
2787 | /* Fetch (and possibly build) an appropriate link_map_offsets structure | |
2788 | for native i386 linux targets using the struct offsets defined in | |
2789 | link.h (but without actual reference to that file). | |
2790 | ||
2791 | This makes it possible to access i386-linux shared libraries from | |
2792 | a gdb that was not built on an i386-linux host (for cross debugging). | |
2793 | */ | |
2794 | ||
2795 | struct link_map_offsets * | |
2796 | sh_linux_svr4_fetch_link_map_offsets (void) | |
2797 | { | |
2798 | static struct link_map_offsets lmo; | |
2799 | static struct link_map_offsets *lmp = 0; | |
2800 | ||
2801 | if (lmp == 0) | |
2802 | { | |
2803 | lmp = &lmo; | |
2804 | ||
2805 | lmo.r_debug_size = 8; /* 20 not actual size but all we need */ | |
2806 | ||
2807 | lmo.r_map_offset = 4; | |
2808 | lmo.r_map_size = 4; | |
2809 | ||
2810 | lmo.link_map_size = 20; /* 552 not actual size but all we need */ | |
2811 | ||
2812 | lmo.l_addr_offset = 0; | |
2813 | lmo.l_addr_size = 4; | |
2814 | ||
2815 | lmo.l_name_offset = 4; | |
2816 | lmo.l_name_size = 4; | |
2817 | ||
2818 | lmo.l_next_offset = 12; | |
2819 | lmo.l_next_size = 4; | |
2820 | ||
2821 | lmo.l_prev_offset = 16; | |
2822 | lmo.l_prev_size = 4; | |
2823 | } | |
2824 | ||
2825 | return lmp; | |
2826 | } | |
2827 | #endif /* SVR4_SHARED_LIBS */ | |
2828 | ||
2829 | gdbarch_init_ftype sh64_gdbarch_init; | |
2830 | ||
2831 | struct gdbarch * | |
2832 | sh64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
2833 | { | |
2834 | static LONGEST sh64_call_dummy_words[] = {0}; | |
2835 | struct gdbarch *gdbarch; | |
2836 | struct gdbarch_tdep *tdep; | |
2837 | ||
2838 | /* If there is already a candidate, use it. */ | |
2839 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
2840 | if (arches != NULL) | |
2841 | return arches->gdbarch; | |
2842 | ||
2843 | /* None found, create a new architecture from the information | |
2844 | provided. */ | |
2845 | tdep = XMALLOC (struct gdbarch_tdep); | |
2846 | gdbarch = gdbarch_alloc (&info, tdep); | |
2847 | ||
2848 | /* NOTE: cagney/2002-12-06: This can be deleted when this arch is | |
2849 | ready to unwind the PC first (see frame.c:get_prev_frame()). */ | |
2850 | set_gdbarch_deprecated_init_frame_pc (gdbarch, init_frame_pc_default); | |
2851 | ||
2852 | /* Determine the ABI */ | |
2853 | if (info.abfd && bfd_get_arch_size (info.abfd) == 64) | |
2854 | { | |
2855 | /* If the ABI is the 64-bit one, it can only be sh-media. */ | |
2856 | tdep->sh_abi = SH_ABI_64; | |
2857 | set_gdbarch_ptr_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
2858 | set_gdbarch_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
2859 | } | |
2860 | else | |
2861 | { | |
2862 | /* If the ABI is the 32-bit one it could be either media or | |
2863 | compact. */ | |
2864 | tdep->sh_abi = SH_ABI_32; | |
2865 | set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
2866 | set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
2867 | } | |
2868 | ||
2869 | set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); | |
2870 | set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
2871 | set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
2872 | set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); | |
2873 | set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
2874 | set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); | |
2875 | ||
2876 | set_gdbarch_sp_regnum (gdbarch, 15); | |
2877 | set_gdbarch_deprecated_fp_regnum (gdbarch, 14); | |
2878 | ||
2879 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_sh); | |
2880 | set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno); | |
2881 | ||
2882 | set_gdbarch_write_pc (gdbarch, generic_target_write_pc); | |
2883 | ||
2884 | set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue); | |
2885 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
2886 | set_gdbarch_decr_pc_after_break (gdbarch, 0); | |
2887 | set_gdbarch_function_start_offset (gdbarch, 0); | |
2888 | ||
2889 | set_gdbarch_frame_args_skip (gdbarch, 0); | |
2890 | set_gdbarch_frameless_function_invocation (gdbarch, frameless_look_for_prologue); | |
2891 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); | |
2892 | ||
2893 | set_gdbarch_deprecated_frame_saved_pc (gdbarch, sh_frame_saved_pc); | |
2894 | set_gdbarch_deprecated_saved_pc_after_call (gdbarch, sh_saved_pc_after_call); | |
2895 | set_gdbarch_frame_align (gdbarch, sh_frame_align); | |
2896 | ||
2897 | set_gdbarch_num_pseudo_regs (gdbarch, NUM_PSEUDO_REGS_SH_MEDIA + NUM_PSEUDO_REGS_SH_COMPACT); | |
2898 | set_gdbarch_fp0_regnum (gdbarch, SIM_SH64_FR0_REGNUM); | |
2899 | set_gdbarch_pc_regnum (gdbarch, 64); | |
2900 | ||
2901 | /* the number of real registers is the same whether we are in | |
2902 | ISA16(compact) or ISA32(media). */ | |
2903 | set_gdbarch_num_regs (gdbarch, SIM_SH64_NR_REGS); | |
2904 | set_gdbarch_deprecated_register_size (gdbarch, 8); /*????*/ | |
2905 | set_gdbarch_deprecated_register_bytes (gdbarch, | |
2906 | ((SIM_SH64_NR_FP_REGS + 1) * 4) | |
2907 | + (SIM_SH64_NR_REGS - SIM_SH64_NR_FP_REGS -1) * 8); | |
2908 | ||
2909 | set_gdbarch_register_name (gdbarch, sh_sh64_register_name); | |
2910 | set_gdbarch_deprecated_register_virtual_type (gdbarch, sh_sh64_register_virtual_type); | |
2911 | set_gdbarch_deprecated_store_return_value (gdbarch, sh64_store_return_value); | |
2912 | set_gdbarch_deprecated_register_raw_size (gdbarch, sh_sh64_register_raw_size); | |
2913 | set_gdbarch_deprecated_register_virtual_size (gdbarch, sh_sh64_register_raw_size); | |
2914 | set_gdbarch_deprecated_register_byte (gdbarch, sh_sh64_register_byte); | |
2915 | /* This seems awfully wrong!*/ | |
2916 | /*set_gdbarch_deprecated_max_register_raw_size (gdbarch, 8);*/ | |
2917 | /* should include the size of the pseudo regs. */ | |
2918 | set_gdbarch_deprecated_max_register_raw_size (gdbarch, 4 * 4); | |
2919 | /* Or should that go in the virtual_size? */ | |
2920 | /*set_gdbarch_deprecated_max_register_virtual_size (gdbarch, 8);*/ | |
2921 | set_gdbarch_deprecated_max_register_virtual_size (gdbarch, 4 * 4); | |
2922 | set_gdbarch_pseudo_register_read (gdbarch, sh64_pseudo_register_read); | |
2923 | set_gdbarch_pseudo_register_write (gdbarch, sh64_pseudo_register_write); | |
2924 | ||
2925 | set_gdbarch_deprecated_do_registers_info (gdbarch, sh64_do_registers_info); | |
2926 | set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh64_nofp_frame_init_saved_regs); | |
2927 | set_gdbarch_breakpoint_from_pc (gdbarch, sh_sh64_breakpoint_from_pc); | |
2928 | set_gdbarch_deprecated_call_dummy_words (gdbarch, sh64_call_dummy_words); | |
2929 | set_gdbarch_deprecated_sizeof_call_dummy_words (gdbarch, sizeof (sh64_call_dummy_words)); | |
2930 | ||
2931 | set_gdbarch_deprecated_init_extra_frame_info (gdbarch, sh64_init_extra_frame_info); | |
2932 | set_gdbarch_deprecated_frame_chain (gdbarch, sh64_frame_chain); | |
2933 | set_gdbarch_deprecated_get_saved_register (gdbarch, sh64_get_saved_register); | |
2934 | set_gdbarch_deprecated_extract_return_value (gdbarch, sh64_extract_return_value); | |
2935 | set_gdbarch_deprecated_push_arguments (gdbarch, sh64_push_arguments); | |
2936 | set_gdbarch_deprecated_push_return_address (gdbarch, sh64_push_return_address); | |
2937 | set_gdbarch_deprecated_dummy_write_sp (gdbarch, deprecated_write_sp); | |
2938 | set_gdbarch_deprecated_store_struct_return (gdbarch, sh64_store_struct_return); | |
2939 | set_gdbarch_deprecated_extract_struct_value_address (gdbarch, sh64_extract_struct_value_address); | |
2940 | set_gdbarch_use_struct_convention (gdbarch, sh64_use_struct_convention); | |
2941 | set_gdbarch_deprecated_pop_frame (gdbarch, sh64_pop_frame); | |
2942 | set_gdbarch_elf_make_msymbol_special (gdbarch, | |
2943 | sh64_elf_make_msymbol_special); | |
2944 | ||
2945 | /* Hook in ABI-specific overrides, if they have been registered. */ | |
2946 | gdbarch_init_osabi (info, gdbarch); | |
2947 | ||
2948 | return gdbarch; | |
2949 | } |