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2003-11-12 Michael Snyder <msnyder@redhat.com>
[deliverable/binutils-gdb.git] / gdb / sh64-tdep.c
CommitLineData
85a453d5 1/* Target-dependent code for Renesas Super-H, for GDB.
55ff77ac
CV		 2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
21
22/*
23 Contributed by Steve Chamberlain
24 sac@cygnus.com
25 */
26
27#include "defs.h"
28#include "frame.h"
29#include "symtab.h"
30#include "symfile.h"
31#include "gdbtypes.h"
32#include "gdbcmd.h"
33#include "gdbcore.h"
34#include "value.h"
35#include "dis-asm.h"
36#include "inferior.h"
37#include "gdb_string.h"
38#include "arch-utils.h"
39#include "floatformat.h"
40#include "regcache.h"
41#include "doublest.h"
42#include "osabi.h"
43
44#include "elf-bfd.h"
45#include "solib-svr4.h"
46
47/* sh flags */
48#include "elf/sh.h"
49/* registers numbers shared with the simulator */
50#include "gdb/sim-sh.h"
51
7bb11558 52/* Information that is dependent on the processor variant. */
55ff77ac
CV		 53enum sh_abi
54 {
55 SH_ABI_UNKNOWN,
56 SH_ABI_32,
57 SH_ABI_64
58 };
59
60struct gdbarch_tdep
61 {
62 enum sh_abi sh_abi;
63 };
64
65/* Registers of SH5 */
66enum
67 {
68 R0_REGNUM = 0,
69 DEFAULT_RETURN_REGNUM = 2,
70 STRUCT_RETURN_REGNUM = 2,
71 ARG0_REGNUM = 2,
72 ARGLAST_REGNUM = 9,
73 FLOAT_ARGLAST_REGNUM = 11,
74 PR_REGNUM = 18,
75 SR_REGNUM = 65,
76 DR0_REGNUM = 141,
77 DR_LAST_REGNUM = 172,
78 /* FPP stands for Floating Point Pair, to avoid confusion with
79 GDB's FP0_REGNUM, which is the number of the first Floating
80 point register. Unfortunately on the sh5, the floating point
7bb11558 81 registers are called FR, and the floating point pairs are called FP. */
55ff77ac
CV		 82 FPP0_REGNUM = 173,
83 FPP_LAST_REGNUM = 204,
84 FV0_REGNUM = 205,
85 FV_LAST_REGNUM = 220,
86 R0_C_REGNUM = 221,
87 R_LAST_C_REGNUM = 236,
88 PC_C_REGNUM = 237,
89 GBR_C_REGNUM = 238,
90 MACH_C_REGNUM = 239,
91 MACL_C_REGNUM = 240,
92 PR_C_REGNUM = 241,
93 T_C_REGNUM = 242,
94 FPSCR_C_REGNUM = 243,
95 FPUL_C_REGNUM = 244,
96 FP0_C_REGNUM = 245,
97 FP_LAST_C_REGNUM = 260,
98 DR0_C_REGNUM = 261,
99 DR_LAST_C_REGNUM = 268,
100 FV0_C_REGNUM = 269,
101 FV_LAST_C_REGNUM = 272,
102 FPSCR_REGNUM = SIM_SH64_FPCSR_REGNUM,
103 SSR_REGNUM = SIM_SH64_SSR_REGNUM,
104 SPC_REGNUM = SIM_SH64_SPC_REGNUM,
105 TR7_REGNUM = SIM_SH64_TR0_REGNUM + 7,
106 FP_LAST_REGNUM = SIM_SH64_FR0_REGNUM + SIM_SH64_NR_FP_REGS - 1
107 };
108
109
110/* Define other aspects of the stack frame.
111 we keep a copy of the worked out return pc lying around, since it
112 is a useful bit of info */
113
114struct frame_extra_info
115{
116 CORE_ADDR return_pc;
117 int leaf_function;
118 int f_offset;
119};
120
121static const char *
122sh_sh64_register_name (int reg_nr)
123{
124 static char *register_names[] =
125 {
126 /* SH MEDIA MODE (ISA 32) */
127 /* general registers (64-bit) 0-63 */
128 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
129 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
130 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
131 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
132 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
133 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
134 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
135 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
136
137 /* pc (64-bit) 64 */
138 "pc",
139
140 /* status reg., saved status reg., saved pc reg. (64-bit) 65-67 */
141 "sr", "ssr", "spc",
142
143 /* target registers (64-bit) 68-75*/
144 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7",
145
146 /* floating point state control register (32-bit) 76 */
147 "fpscr",
148
149 /* single precision floating point registers (32-bit) 77-140*/
150 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
151 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
152 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23",
153 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31",
154 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39",
155 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47",
156 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55",
157 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63",
158
159 /* double precision registers (pseudo) 141-172 */
160 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
161 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30",
162 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46",
163 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62",
164
165 /* floating point pairs (pseudo) 173-204*/
166 "fp0", "fp2", "fp4", "fp6", "fp8", "fp10", "fp12", "fp14",
167 "fp16", "fp18", "fp20", "fp22", "fp24", "fp26", "fp28", "fp30",
168 "fp32", "fp34", "fp36", "fp38", "fp40", "fp42", "fp44", "fp46",
169 "fp48", "fp50", "fp52", "fp54", "fp56", "fp58", "fp60", "fp62",
170
171 /* floating point vectors (4 floating point regs) (pseudo) 205-220*/
172 "fv0", "fv4", "fv8", "fv12", "fv16", "fv20", "fv24", "fv28",
173 "fv32", "fv36", "fv40", "fv44", "fv48", "fv52", "fv56", "fv60",
174
175 /* SH COMPACT MODE (ISA 16) (all pseudo) 221-272*/
176 "r0_c", "r1_c", "r2_c", "r3_c", "r4_c", "r5_c", "r6_c", "r7_c",
177 "r8_c", "r9_c", "r10_c", "r11_c", "r12_c", "r13_c", "r14_c", "r15_c",
178 "pc_c",
179 "gbr_c", "mach_c", "macl_c", "pr_c", "t_c",
180 "fpscr_c", "fpul_c",
181 "fr0_c", "fr1_c", "fr2_c", "fr3_c", "fr4_c", "fr5_c", "fr6_c", "fr7_c",
182 "fr8_c", "fr9_c", "fr10_c", "fr11_c", "fr12_c", "fr13_c", "fr14_c", "fr15_c",
183 "dr0_c", "dr2_c", "dr4_c", "dr6_c", "dr8_c", "dr10_c", "dr12_c", "dr14_c",
184 "fv0_c", "fv4_c", "fv8_c", "fv12_c",
185 /* FIXME!!!! XF0 XF15, XD0 XD14 ?????*/
186 };
187
188 if (reg_nr < 0)
189 return NULL;
190 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
191 return NULL;
192 return register_names[reg_nr];
193}
194
195#define NUM_PSEUDO_REGS_SH_MEDIA 80
196#define NUM_PSEUDO_REGS_SH_COMPACT 51
197
198/* Macros and functions for setting and testing a bit in a minimal
199 symbol that marks it as 32-bit function. The MSB of the minimal
f594e5e9 200 symbol's "info" field is used for this purpose.
55ff77ac
CV		 201
202 ELF_MAKE_MSYMBOL_SPECIAL
203 tests whether an ELF symbol is "special", i.e. refers
204 to a 32-bit function, and sets a "special" bit in a
205 minimal symbol to mark it as a 32-bit function
f594e5e9 206 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
55ff77ac
CV		 207
208#define MSYMBOL_IS_SPECIAL(msym) \
209 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
210
211static void
212sh64_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym)
213{
214 if (msym == NULL)
215 return;
216
217 if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_SH5_ISA32)
218 {
219 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) | 0x80000000);
220 SYMBOL_VALUE_ADDRESS (msym) |= 1;
221 }
222}
223
224/* ISA32 (shmedia) function addresses are odd (bit 0 is set). Here
225 are some macros to test, set, or clear bit 0 of addresses. */
226#define IS_ISA32_ADDR(addr) ((addr) & 1)
227#define MAKE_ISA32_ADDR(addr) ((addr) | 1)
228#define UNMAKE_ISA32_ADDR(addr) ((addr) & ~1)
229
230static int
231pc_is_isa32 (bfd_vma memaddr)
232{
233 struct minimal_symbol *sym;
234
235 /* If bit 0 of the address is set, assume this is a
7bb11558 236 ISA32 (shmedia) address. */
55ff77ac
CV		 237 if (IS_ISA32_ADDR (memaddr))
238 return 1;
239
240 /* A flag indicating that this is a ISA32 function is stored by elfread.c in
241 the high bit of the info field. Use this to decide if the function is
242 ISA16 or ISA32. */
243 sym = lookup_minimal_symbol_by_pc (memaddr);
244 if (sym)
245 return MSYMBOL_IS_SPECIAL (sym);
246 else
247 return 0;
248}
249
250static const unsigned char *
251sh_sh64_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
252{
253 /* The BRK instruction for shmedia is
254 01101111 11110101 11111111 11110000
255 which translates in big endian mode to 0x6f, 0xf5, 0xff, 0xf0
256 and in little endian mode to 0xf0, 0xff, 0xf5, 0x6f */
257
258 /* The BRK instruction for shcompact is
259 00000000 00111011
260 which translates in big endian mode to 0x0, 0x3b
261 and in little endian mode to 0x3b, 0x0*/
262
263 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
264 {
265 if (pc_is_isa32 (*pcptr))
266 {
267 static unsigned char big_breakpoint_media[] = {0x6f, 0xf5, 0xff, 0xf0};
268 *pcptr = UNMAKE_ISA32_ADDR (*pcptr);
269 *lenptr = sizeof (big_breakpoint_media);
270 return big_breakpoint_media;
271 }
272 else
273 {
274 static unsigned char big_breakpoint_compact[] = {0x0, 0x3b};
275 *lenptr = sizeof (big_breakpoint_compact);
276 return big_breakpoint_compact;
277 }
278 }
279 else
280 {
281 if (pc_is_isa32 (*pcptr))
282 {
283 static unsigned char little_breakpoint_media[] = {0xf0, 0xff, 0xf5, 0x6f};
284 *pcptr = UNMAKE_ISA32_ADDR (*pcptr);
285 *lenptr = sizeof (little_breakpoint_media);
286 return little_breakpoint_media;
287 }
288 else
289 {
290 static unsigned char little_breakpoint_compact[] = {0x3b, 0x0};
291 *lenptr = sizeof (little_breakpoint_compact);
292 return little_breakpoint_compact;
293 }
294 }
295}
296
297/* Prologue looks like
298 [mov.l <regs>,@-r15]...
299 [sts.l pr,@-r15]
300 [mov.l r14,@-r15]
301 [mov r15,r14]
302
303 Actually it can be more complicated than this. For instance, with
304 newer gcc's:
305
306 mov.l r14,@-r15
307 add #-12,r15
308 mov r15,r14
309 mov r4,r1
310 mov r5,r2
311 mov.l r6,@(4,r14)
312 mov.l r7,@(8,r14)
313 mov.b r1,@r14
314 mov r14,r1
315 mov r14,r1
316 add #2,r1
317 mov.w r2,@r1
318
319 */
320
321/* PTABS/L Rn, TRa 0110101111110001nnnnnnl00aaa0000
322 with l=1 and n = 18 0110101111110001010010100aaa0000 */
323#define IS_PTABSL_R18(x) (((x) & 0xffffff8f) == 0x6bf14a00)
324
325/* STS.L PR,@-r0 0100000000100010
326 r0-4-->r0, PR-->(r0) */
327#define IS_STS_R0(x) ((x) == 0x4022)
328
329/* STS PR, Rm 0000mmmm00101010
330 PR-->Rm */
331#define IS_STS_PR(x) (((x) & 0xf0ff) == 0x2a)
332
333/* MOV.L Rm,@(disp,r15) 00011111mmmmdddd
334 Rm-->(dispx4+r15) */
335#define IS_MOV_TO_R15(x) (((x) & 0xff00) == 0x1f00)
336
337/* MOV.L R14,@(disp,r15) 000111111110dddd
338 R14-->(dispx4+r15) */
339#define IS_MOV_R14(x) (((x) & 0xfff0) == 0x1fe0)
340
341/* ST.Q R14, disp, R18 101011001110dddddddddd0100100000
342 R18-->(dispx8+R14) */
343#define IS_STQ_R18_R14(x) (((x) & 0xfff003ff) == 0xace00120)
344
345/* ST.Q R15, disp, R18 101011001111dddddddddd0100100000
346 R18-->(dispx8+R15) */
347#define IS_STQ_R18_R15(x) (((x) & 0xfff003ff) == 0xacf00120)
348
349/* ST.L R15, disp, R18 101010001111dddddddddd0100100000
350 R18-->(dispx4+R15) */
351#define IS_STL_R18_R15(x) (((x) & 0xfff003ff) == 0xa8f00120)
352
353/* ST.Q R15, disp, R14 1010 1100 1111 dddd dddd dd00 1110 0000
354 R14-->(dispx8+R15) */
355#define IS_STQ_R14_R15(x) (((x) & 0xfff003ff) == 0xacf000e0)
356
357/* ST.L R15, disp, R14 1010 1000 1111 dddd dddd dd00 1110 0000
358 R14-->(dispx4+R15) */
359#define IS_STL_R14_R15(x) (((x) & 0xfff003ff) == 0xa8f000e0)
360
361/* ADDI.L R15,imm,R15 1101 0100 1111 ssss ssss ss00 1111 0000
362 R15 + imm --> R15 */
363#define IS_ADDIL_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd4f000f0)
364
365/* ADDI R15,imm,R15 1101 0000 1111 ssss ssss ss00 1111 0000
366 R15 + imm --> R15 */
367#define IS_ADDI_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd0f000f0)
368
369/* ADD.L R15,R63,R14 0000 0000 1111 1000 1111 1100 1110 0000
370 R15 + R63 --> R14 */
371#define IS_ADDL_SP_FP_MEDIA(x) ((x) == 0x00f8fce0)
372
373/* ADD R15,R63,R14 0000 0000 1111 1001 1111 1100 1110 0000
374 R15 + R63 --> R14 */
375#define IS_ADD_SP_FP_MEDIA(x) ((x) == 0x00f9fce0)
376
377#define IS_MOV_SP_FP_MEDIA(x) (IS_ADDL_SP_FP_MEDIA(x) || IS_ADD_SP_FP_MEDIA(x))
378
379/* MOV #imm, R0 1110 0000 ssss ssss
380 #imm-->R0 */
381#define IS_MOV_R0(x) (((x) & 0xff00) == 0xe000)
382
383/* MOV.L @(disp,PC), R0 1101 0000 iiii iiii */
384#define IS_MOVL_R0(x) (((x) & 0xff00) == 0xd000)
385
386/* ADD r15,r0 0011 0000 1111 1100
387 r15+r0-->r0 */
388#define IS_ADD_SP_R0(x) ((x) == 0x30fc)
389
390/* MOV.L R14 @-R0 0010 0000 1110 0110
391 R14-->(R0-4), R0-4-->R0 */
392#define IS_MOV_R14_R0(x) ((x) == 0x20e6)
393
394/* ADD Rm,R63,Rn Rm+R63-->Rn 0000 00mm mmmm 1001 1111 11nn nnnn 0000
7bb11558 395 where Rm is one of r2-r9 which are the argument registers. */
55ff77ac
CV		 396/* FIXME: Recognize the float and double register moves too! */
397#define IS_MEDIA_IND_ARG_MOV(x) \
398((((x) & 0xfc0ffc0f) == 0x0009fc00) && (((x) & 0x03f00000) >= 0x00200000 && ((x) & 0x03f00000) <= 0x00900000))
399
400/* ST.Q Rn,0,Rm Rm-->Rn+0 1010 11nn nnnn 0000 0000 00mm mmmm 0000
401 or ST.L Rn,0,Rm Rm-->Rn+0 1010 10nn nnnn 0000 0000 00mm mmmm 0000
7bb11558 402 where Rm is one of r2-r9 which are the argument registers. */
55ff77ac
CV		 403#define IS_MEDIA_ARG_MOV(x) \
404(((((x) & 0xfc0ffc0f) == 0xac000000) || (((x) & 0xfc0ffc0f) == 0xa8000000)) \
405 && (((x) & 0x000003f0) >= 0x00000020 && ((x) & 0x000003f0) <= 0x00000090))
406
407/* ST.B R14,0,Rn Rn-->(R14+0) 1010 0000 1110 0000 0000 00nn nnnn 0000*/
408/* ST.W R14,0,Rn Rn-->(R14+0) 1010 0100 1110 0000 0000 00nn nnnn 0000*/
409/* ST.L R14,0,Rn Rn-->(R14+0) 1010 1000 1110 0000 0000 00nn nnnn 0000*/
410/* FST.S R14,0,FRn Rn-->(R14+0) 1011 0100 1110 0000 0000 00nn nnnn 0000*/
411/* FST.D R14,0,DRn Rn-->(R14+0) 1011 1100 1110 0000 0000 00nn nnnn 0000*/
412#define IS_MEDIA_MOV_TO_R14(x) \
413((((x) & 0xfffffc0f) == 0xa0e00000) \
414|| (((x) & 0xfffffc0f) == 0xa4e00000) \
415|| (((x) & 0xfffffc0f) == 0xa8e00000) \
416|| (((x) & 0xfffffc0f) == 0xb4e00000) \
417|| (((x) & 0xfffffc0f) == 0xbce00000))
418
419/* MOV Rm, Rn Rm-->Rn 0110 nnnn mmmm 0011
420 where Rm is r2-r9 */
421#define IS_COMPACT_IND_ARG_MOV(x) \
422((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0020) && (((x) & 0x00f0) <= 0x0090))
423
424/* compact direct arg move!
425 MOV.L Rn, @r14 0010 1110 mmmm 0010 */
426#define IS_COMPACT_ARG_MOV(x) \
427(((((x) & 0xff0f) == 0x2e02) && (((x) & 0x00f0) >= 0x0020) && ((x) & 0x00f0) <= 0x0090))
428
429/* MOV.B Rm, @R14 0010 1110 mmmm 0000
430 MOV.W Rm, @R14 0010 1110 mmmm 0001 */
431#define IS_COMPACT_MOV_TO_R14(x) \
432((((x) & 0xff0f) == 0x2e00) || (((x) & 0xff0f) == 0x2e01))
433
434#define IS_JSR_R0(x) ((x) == 0x400b)
435#define IS_NOP(x) ((x) == 0x0009)
436
437
438/* MOV r15,r14 0110111011110011
439 r15-->r14 */
440#define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
441
442/* ADD #imm,r15 01111111iiiiiiii
443 r15+imm-->r15 */
444#define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00)
445
446/* Skip any prologue before the guts of a function */
447
7bb11558
MS		 448/* Skip the prologue using the debug information. If this fails we'll
449 fall back on the 'guess' method below. */
55ff77ac
CV		 450static CORE_ADDR
451after_prologue (CORE_ADDR pc)
452{
453 struct symtab_and_line sal;
454 CORE_ADDR func_addr, func_end;
455
456 /* If we can not find the symbol in the partial symbol table, then
457 there is no hope we can determine the function's start address
458 with this code. */
459 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
460 return 0;
461
462 /* Get the line associated with FUNC_ADDR. */
463 sal = find_pc_line (func_addr, 0);
464
465 /* There are only two cases to consider. First, the end of the source line
466 is within the function bounds. In that case we return the end of the
467 source line. Second is the end of the source line extends beyond the
468 bounds of the current function. We need to use the slow code to
469 examine instructions in that case. */
470 if (sal.end < func_end)
471 return sal.end;
472 else
473 return 0;
474}
475
476static CORE_ADDR
477look_for_args_moves (CORE_ADDR start_pc, int media_mode)
478{
479 CORE_ADDR here, end;
480 int w;
481 int insn_size = (media_mode ? 4 : 2);
482
483 for (here = start_pc, end = start_pc + (insn_size * 28); here < end;)
484 {
485 if (media_mode)
486 {
487 w = read_memory_integer (UNMAKE_ISA32_ADDR (here), insn_size);
488 here += insn_size;
489 if (IS_MEDIA_IND_ARG_MOV (w))
490 {
491 /* This must be followed by a store to r14, so the argument
492 is where the debug info says it is. This can happen after
7bb11558 493 the SP has been saved, unfortunately. */
55ff77ac
CV		 494
495 int next_insn = read_memory_integer (UNMAKE_ISA32_ADDR (here),
496 insn_size);
497 here += insn_size;
498 if (IS_MEDIA_MOV_TO_R14 (next_insn))
499 start_pc = here;
500 }
501 else if (IS_MEDIA_ARG_MOV (w))
502 {
7bb11558 503 /* These instructions store directly the argument in r14. */
55ff77ac
CV		 504 start_pc = here;
505 }
506 else
507 break;
508 }
509 else
510 {
511 w = read_memory_integer (here, insn_size);
512 w = w & 0xffff;
513 here += insn_size;
514 if (IS_COMPACT_IND_ARG_MOV (w))
515 {
516 /* This must be followed by a store to r14, so the argument
517 is where the debug info says it is. This can happen after
7bb11558 518 the SP has been saved, unfortunately. */
55ff77ac
CV		 519
520 int next_insn = 0xffff & read_memory_integer (here, insn_size);
521 here += insn_size;
522 if (IS_COMPACT_MOV_TO_R14 (next_insn))
523 start_pc = here;
524 }
525 else if (IS_COMPACT_ARG_MOV (w))
526 {
7bb11558 527 /* These instructions store directly the argument in r14. */
55ff77ac
CV		 528 start_pc = here;
529 }
530 else if (IS_MOVL_R0 (w))
531 {
532 /* There is a function that gcc calls to get the arguments
533 passed correctly to the function. Only after this
534 function call the arguments will be found at the place
535 where they are supposed to be. This happens in case the
536 argument has to be stored into a 64-bit register (for
537 instance doubles, long longs). SHcompact doesn't have
538 access to the full 64-bits, so we store the register in
539 stack slot and store the address of the stack slot in
540 the register, then do a call through a wrapper that
541 loads the memory value into the register. A SHcompact
542 callee calls an argument decoder
543 (GCC_shcompact_incoming_args) that stores the 64-bit
544 value in a stack slot and stores the address of the
545 stack slot in the register. GCC thinks the argument is
546 just passed by transparent reference, but this is only
547 true after the argument decoder is called. Such a call
7bb11558 548 needs to be considered part of the prologue. */
55ff77ac
CV		 549
550 /* This must be followed by a JSR @r0 instruction and by
551 a NOP instruction. After these, the prologue is over! */
552
553 int next_insn = 0xffff & read_memory_integer (here, insn_size);
554 here += insn_size;
555 if (IS_JSR_R0 (next_insn))
556 {
557 next_insn = 0xffff & read_memory_integer (here, insn_size);
558 here += insn_size;
559
560 if (IS_NOP (next_insn))
561 start_pc = here;
562 }
563 }
564 else
565 break;
566 }
567 }
568
569 return start_pc;
570}
571
572static CORE_ADDR
573sh64_skip_prologue_hard_way (CORE_ADDR start_pc)
574{
575 CORE_ADDR here, end;
576 int updated_fp = 0;
577 int insn_size = 4;
578 int media_mode = 1;
579
580 if (!start_pc)
581 return 0;
582
583 if (pc_is_isa32 (start_pc) == 0)
584 {
585 insn_size = 2;
586 media_mode = 0;
587 }
588
589 for (here = start_pc, end = start_pc + (insn_size * 28); here < end;)
590 {
591
592 if (media_mode)
593 {
594 int w = read_memory_integer (UNMAKE_ISA32_ADDR (here), insn_size);
595 here += insn_size;
596 if (IS_STQ_R18_R14 (w) || IS_STQ_R18_R15 (w) || IS_STQ_R14_R15 (w)
597 || IS_STL_R14_R15 (w) || IS_STL_R18_R15 (w)
598 || IS_ADDIL_SP_MEDIA (w) || IS_ADDI_SP_MEDIA (w) || IS_PTABSL_R18 (w))
599 {
600 start_pc = here;
601 }
602 else if (IS_MOV_SP_FP (w) || IS_MOV_SP_FP_MEDIA(w))
603 {
604 start_pc = here;
605 updated_fp = 1;
606 }
607 else
608 if (updated_fp)
609 {
610 /* Don't bail out yet, we may have arguments stored in
611 registers here, according to the debug info, so that
7bb11558 612 gdb can print the frames correctly. */
55ff77ac
CV		 613 start_pc = look_for_args_moves (here - insn_size, media_mode);
614 break;
615 }
616 }
617 else
618 {
619 int w = 0xffff & read_memory_integer (here, insn_size);
620 here += insn_size;
621
622 if (IS_STS_R0 (w) || IS_STS_PR (w)
623 || IS_MOV_TO_R15 (w) || IS_MOV_R14 (w)
624 || IS_MOV_R0 (w) || IS_ADD_SP_R0 (w) || IS_MOV_R14_R0 (w))
625 {
626 start_pc = here;
627 }
628 else if (IS_MOV_SP_FP (w))
629 {
630 start_pc = here;
631 updated_fp = 1;
632 }
633 else
634 if (updated_fp)
635 {
636 /* Don't bail out yet, we may have arguments stored in
637 registers here, according to the debug info, so that
7bb11558 638 gdb can print the frames correctly. */
55ff77ac
CV		 639 start_pc = look_for_args_moves (here - insn_size, media_mode);
640 break;
641 }
642 }
643 }
644
645 return start_pc;
646}
647
648static CORE_ADDR
649sh_skip_prologue (CORE_ADDR pc)
650{
651 CORE_ADDR post_prologue_pc;
652
653 /* See if we can determine the end of the prologue via the symbol table.
654 If so, then return either PC, or the PC after the prologue, whichever
655 is greater. */
656 post_prologue_pc = after_prologue (pc);
657
658 /* If after_prologue returned a useful address, then use it. Else
7bb11558 659 fall back on the instruction skipping code. */
55ff77ac
CV		 660 if (post_prologue_pc != 0)
661 return max (pc, post_prologue_pc);
662 else
663 return sh64_skip_prologue_hard_way (pc);
664}
665
666/* Immediately after a function call, return the saved pc.
667 Can't always go through the frames for this because on some machines
668 the new frame is not set up until the new function executes
669 some instructions.
670
671 The return address is the value saved in the PR register + 4 */
672static CORE_ADDR
673sh_saved_pc_after_call (struct frame_info *frame)
674{
675 return (ADDR_BITS_REMOVE (read_register (PR_REGNUM)));
676}
677
678/* Should call_function allocate stack space for a struct return? */
679static int
680sh64_use_struct_convention (int gcc_p, struct type *type)
681{
682 return (TYPE_LENGTH (type) > 8);
683}
684
685/* Store the address of the place in which to copy the structure the
686 subroutine will return. This is called from call_function.
687
688 We store structs through a pointer passed in R2 */
689static void
690sh64_store_struct_return (CORE_ADDR addr, CORE_ADDR sp)
691{
692 write_register (STRUCT_RETURN_REGNUM, (addr));
693}
694
695/* Disassemble an instruction. */
696static int
697gdb_print_insn_sh (bfd_vma memaddr, disassemble_info *info)
698{
699 info->endian = TARGET_BYTE_ORDER;
700 return print_insn_sh (memaddr, info);
701}
702
703/* Given a register number RN as it appears in an assembly
704 instruction, find the corresponding register number in the GDB
7bb11558 705 scheme. */
55ff77ac
CV		 706static int
707translate_insn_rn (int rn, int media_mode)
708{
7bb11558 709 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
55ff77ac
CV		 710
711 /* FIXME: this assumes that the number rn is for a not pseudo
7bb11558 712 register only. */
55ff77ac
CV		 713 if (media_mode)
714 return rn;
715 else
716 {
7bb11558
MS		 717 /* These registers don't have a corresponding compact one. */
718 /* FIXME: This is probably not enough. */
55ff77ac
CV		 719#if 0
720 if ((rn >= 16 && rn <= 63) || (rn >= 93 && rn <= 140))
721 return rn;
722#endif
723 if (rn >= 0 && rn <= R0_C_REGNUM)
724 return R0_C_REGNUM + rn;
725 else
726 return rn;
727 }
728}
729
730/* Given a GDB frame, determine the address of the calling function's
731 frame. This will be used to create a new GDB frame struct, and
732 then DEPRECATED_INIT_EXTRA_FRAME_INFO and DEPRECATED_INIT_FRAME_PC
733 will be called for the new frame.
734
735 For us, the frame address is its stack pointer value, so we look up
736 the function prologue to determine the caller's sp value, and return it. */
737static CORE_ADDR
738sh64_frame_chain (struct frame_info *frame)
739{
740 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame),
741 get_frame_base (frame),
742 get_frame_base (frame)))
7bb11558 743 return get_frame_base (frame); /* dummy frame same as caller's frame */
627b3ba2
AC		 744 if (get_frame_pc (frame)
745 && !deprecated_inside_entry_file (get_frame_pc (frame)))
55ff77ac
CV		 746 {
747 int media_mode = pc_is_isa32 (get_frame_pc (frame));
748 int size;
749 if (gdbarch_tdep (current_gdbarch)->sh_abi == SH_ABI_32)
750 size = 4;
751 else
7bb11558
MS		 752 size = register_size (current_gdbarch,
753 translate_insn_rn (DEPRECATED_FP_REGNUM,
754 media_mode));
55ff77ac
CV		 755 return read_memory_integer (get_frame_base (frame)
756 + get_frame_extra_info (frame)->f_offset,
757 size);
758 }
759 else
760 return 0;
761}
762
763static CORE_ADDR
764sh64_get_saved_pr (struct frame_info *fi, int pr_regnum)
765{
766 int media_mode = 0;
767
768 for (; fi; fi = get_next_frame (fi))
769 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), get_frame_base (fi),
770 get_frame_base (fi)))
7bb11558
MS		 771 /* When the caller requests PR from the dummy frame, we return
772 PC because that's where the previous routine appears to have
773 done a call from. */
55ff77ac
CV		 774 return deprecated_read_register_dummy (get_frame_pc (fi),
775 get_frame_base (fi), pr_regnum);
776 else
777 {
778 DEPRECATED_FRAME_INIT_SAVED_REGS (fi);
779 if (!get_frame_pc (fi))
780 return 0;
781
782 media_mode = pc_is_isa32 (get_frame_pc (fi));
783
1b1d3794 784 if (deprecated_get_frame_saved_regs (fi)[pr_regnum] != 0)
55ff77ac
CV		 785 {
786 int gdb_reg_num = translate_insn_rn (pr_regnum, media_mode);
787 int size = ((gdbarch_tdep (current_gdbarch)->sh_abi == SH_ABI_32)
788 ? 4
7bb11558 789 : register_size (current_gdbarch, gdb_reg_num));
1b1d3794 790 return read_memory_integer (deprecated_get_frame_saved_regs (fi)[pr_regnum], size);
55ff77ac
CV		 791 }
792 }
793 return read_register (pr_regnum);
794}
795
7bb11558 796/* For vectors of 4 floating point registers. */
55ff77ac
CV		 797static int
798fv_reg_base_num (int fv_regnum)
799{
800 int fp_regnum;
801
802 fp_regnum = FP0_REGNUM +
803 (fv_regnum - FV0_REGNUM) * 4;
804 return fp_regnum;
805}
806
807/* For double precision floating point registers, i.e 2 fp regs.*/
808static int
809dr_reg_base_num (int dr_regnum)
810{
811 int fp_regnum;
812
813 fp_regnum = FP0_REGNUM +
814 (dr_regnum - DR0_REGNUM) * 2;
815 return fp_regnum;
816}
817
818/* For pairs of floating point registers */
819static int
820fpp_reg_base_num (int fpp_regnum)
821{
822 int fp_regnum;
823
824 fp_regnum = FP0_REGNUM +
825 (fpp_regnum - FPP0_REGNUM) * 2;
826 return fp_regnum;
827}
828
829static int
830is_media_pseudo (int rn)
831{
7bb11558 832 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
55ff77ac
CV		 833
834 return (rn >= DR0_REGNUM
835 && rn <= FV_LAST_REGNUM);
836}
837
838static int
839sh64_get_gdb_regnum (int gcc_regnum, CORE_ADDR pc)
840{
841 return translate_insn_rn (gcc_regnum, pc_is_isa32 (pc));
842}
843
844static int
845sh64_media_reg_base_num (int reg_nr)
846{
847 int base_regnum = -1;
7bb11558 848 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
55ff77ac
CV		 849
850 if (reg_nr >= DR0_REGNUM
851 && reg_nr <= DR_LAST_REGNUM)
852 base_regnum = dr_reg_base_num (reg_nr);
853
854 else if (reg_nr >= FPP0_REGNUM
855 && reg_nr <= FPP_LAST_REGNUM)
856 base_regnum = fpp_reg_base_num (reg_nr);
857
858 else if (reg_nr >= FV0_REGNUM
859 && reg_nr <= FV_LAST_REGNUM)
860 base_regnum = fv_reg_base_num (reg_nr);
861
862 return base_regnum;
863}
864
865/* *INDENT-OFF* */
866/*
867 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
868 GDB_REGNUM BASE_REGNUM
869 r0_c 221 0
870 r1_c 222 1
871 r2_c 223 2
872 r3_c 224 3
873 r4_c 225 4
874 r5_c 226 5
875 r6_c 227 6
876 r7_c 228 7
877 r8_c 229 8
878 r9_c 230 9
879 r10_c 231 10
880 r11_c 232 11
881 r12_c 233 12
882 r13_c 234 13
883 r14_c 235 14
884 r15_c 236 15
885
886 pc_c 237 64
887 gbr_c 238 16
888 mach_c 239 17
889 macl_c 240 17
890 pr_c 241 18
891 t_c 242 19
892 fpscr_c 243 76
893 fpul_c 244 109
894
895 fr0_c 245 77
896 fr1_c 246 78
897 fr2_c 247 79
898 fr3_c 248 80
899 fr4_c 249 81
900 fr5_c 250 82
901 fr6_c 251 83
902 fr7_c 252 84
903 fr8_c 253 85
904 fr9_c 254 86
905 fr10_c 255 87
906 fr11_c 256 88
907 fr12_c 257 89
908 fr13_c 258 90
909 fr14_c 259 91
910 fr15_c 260 92
911
912 dr0_c 261 77
913 dr2_c 262 79
914 dr4_c 263 81
915 dr6_c 264 83
916 dr8_c 265 85
917 dr10_c 266 87
918 dr12_c 267 89
919 dr14_c 268 91
920
921 fv0_c 269 77
922 fv4_c 270 81
923 fv8_c 271 85
924 fv12_c 272 91
925*/
926/* *INDENT-ON* */
927static int
928sh64_compact_reg_base_num (int reg_nr)
929{
930 int base_regnum = -1;
7bb11558 931 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
55ff77ac
CV		 932
933 /* general register N maps to general register N */
934 if (reg_nr >= R0_C_REGNUM
935 && reg_nr <= R_LAST_C_REGNUM)
936 base_regnum = reg_nr - R0_C_REGNUM;
937
938 /* floating point register N maps to floating point register N */
939 else if (reg_nr >= FP0_C_REGNUM
940 && reg_nr <= FP_LAST_C_REGNUM)
941 base_regnum = reg_nr - FP0_C_REGNUM + FP0_REGNUM;
942
943 /* double prec register N maps to base regnum for double prec register N */
944 else if (reg_nr >= DR0_C_REGNUM
945 && reg_nr <= DR_LAST_C_REGNUM)
946 base_regnum = dr_reg_base_num (DR0_REGNUM
947 + reg_nr - DR0_C_REGNUM);
948
949 /* vector N maps to base regnum for vector register N */
950 else if (reg_nr >= FV0_C_REGNUM
951 && reg_nr <= FV_LAST_C_REGNUM)
952 base_regnum = fv_reg_base_num (FV0_REGNUM
953 + reg_nr - FV0_C_REGNUM);
954
955 else if (reg_nr == PC_C_REGNUM)
956 base_regnum = PC_REGNUM;
957
958 else if (reg_nr == GBR_C_REGNUM)
959 base_regnum = 16;
960
961 else if (reg_nr == MACH_C_REGNUM
962 || reg_nr == MACL_C_REGNUM)
963 base_regnum = 17;
964
965 else if (reg_nr == PR_C_REGNUM)
966 base_regnum = 18;
967
968 else if (reg_nr == T_C_REGNUM)
969 base_regnum = 19;
970
971 else if (reg_nr == FPSCR_C_REGNUM)
7bb11558 972 base_regnum = FPSCR_REGNUM; /*???? this register is a mess. */
55ff77ac
CV		 973
974 else if (reg_nr == FPUL_C_REGNUM)
975 base_regnum = FP0_REGNUM + 32;
976
977 return base_regnum;
978}
979
980/* Given a register number RN (according to the gdb scheme) , return
981 its corresponding architectural register. In media mode, only a
982 subset of the registers is pseudo registers. For compact mode, all
7bb11558 983 the registers are pseudo. */
55ff77ac
CV		 984static int
985translate_rn_to_arch_reg_num (int rn, int media_mode)
986{
987
988 if (media_mode)
989 {
990 if (!is_media_pseudo (rn))
991 return rn;
992 else
993 return sh64_media_reg_base_num (rn);
994 }
995 else
7bb11558 996 /* All compact registers are pseudo. */
55ff77ac
CV		 997 return sh64_compact_reg_base_num (rn);
998}
999
1000static int
1001sign_extend (int value, int bits)
1002{
1003 value = value & ((1 << bits) - 1);
1004 return (value & (1 << (bits - 1))
1005 ? value | (~((1 << bits) - 1))
1006 : value);
1007}
1008
1009static void
1010sh64_nofp_frame_init_saved_regs (struct frame_info *fi)
1011{
1012 int *where = (int *) alloca ((NUM_REGS + NUM_PSEUDO_REGS) * sizeof (int));
1013 int rn;
1014 int have_fp = 0;
1015 int fp_regnum;
1016 int sp_regnum;
1017 int depth;
1018 int pc;
1019 int opc;
1020 int insn;
1021 int r0_val = 0;
1022 int media_mode = 0;
1023 int insn_size;
1024 int gdb_register_number;
1025 int register_number;
1026 char *dummy_regs = deprecated_generic_find_dummy_frame (get_frame_pc (fi), get_frame_base (fi));
7bb11558 1027 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
55ff77ac 1028
1b1d3794 1029 if (deprecated_get_frame_saved_regs (fi) == NULL)
55ff77ac
CV		 1030 frame_saved_regs_zalloc (fi);
1031 else
1b1d3794 1032 memset (deprecated_get_frame_saved_regs (fi), 0, SIZEOF_FRAME_SAVED_REGS);
55ff77ac
CV		 1033
1034 if (dummy_regs)
1035 {
1036 /* DANGER! This is ONLY going to work if the char buffer format of
1037 the saved registers is byte-for-byte identical to the
1038 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
1b1d3794 1039 memcpy (deprecated_get_frame_saved_regs (fi), dummy_regs, SIZEOF_FRAME_SAVED_REGS);
55ff77ac
CV		 1040 return;
1041 }
1042
1043 get_frame_extra_info (fi)->leaf_function = 1;
1044 get_frame_extra_info (fi)->f_offset = 0;
1045
1046 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
1047 where[rn] = -1;
1048
1049 depth = 0;
1050
1051 /* Loop around examining the prologue insns until we find something
1052 that does not appear to be part of the prologue. But give up
7bb11558 1053 after 20 of them, since we're getting silly then. */
55ff77ac
CV		 1054
1055 pc = get_frame_func (fi);
1056 if (!pc)
1057 {
1058 deprecated_update_frame_pc_hack (fi, 0);
1059 return;
1060 }
1061
1062 if (pc_is_isa32 (pc))
1063 {
1064 media_mode = 1;
1065 insn_size = 4;
1066 }
1067 else
1068 {
1069 media_mode = 0;
1070 insn_size = 2;
1071 }
1072
1073 /* The frame pointer register is general register 14 in shmedia and
1074 shcompact modes. In sh compact it is a pseudo register. Same goes
7bb11558 1075 for the stack pointer register, which is register 15. */
55ff77ac
CV		 1076 fp_regnum = translate_insn_rn (DEPRECATED_FP_REGNUM, media_mode);
1077 sp_regnum = translate_insn_rn (SP_REGNUM, media_mode);
1078
1079 for (opc = pc + (insn_size * 28); pc < opc; pc += insn_size)
1080 {
1081 insn = read_memory_integer (media_mode ? UNMAKE_ISA32_ADDR (pc) : pc,
1082 insn_size);
1083
1084 if (media_mode == 0)
1085 {
1086 if (IS_STS_PR (insn))
1087 {
1088 int next_insn = read_memory_integer (pc + insn_size, insn_size);
1089 if (IS_MOV_TO_R15 (next_insn))
1090 {
1091 int reg_nr = PR_C_REGNUM;
1092
1093 where[reg_nr] = depth - ((((next_insn & 0xf) ^ 0x8) - 0x8) << 2);
1094 get_frame_extra_info (fi)->leaf_function = 0;
1095 pc += insn_size;
1096 }
1097 }
1098 else if (IS_MOV_R14 (insn))
1099 {
1100 where[fp_regnum] = depth - ((((insn & 0xf) ^ 0x8) - 0x8) << 2);
1101 }
1102
1103 else if (IS_MOV_R0 (insn))
1104 {
1105 /* Put in R0 the offset from SP at which to store some
1106 registers. We are interested in this value, because it
1107 will tell us where the given registers are stored within
1108 the frame. */
1109 r0_val = ((insn & 0xff) ^ 0x80) - 0x80;
1110 }
1111 else if (IS_ADD_SP_R0 (insn))
1112 {
1113 /* This instruction still prepares r0, but we don't care.
7bb11558 1114 We already have the offset in r0_val. */
55ff77ac
CV		 1115 }
1116 else if (IS_STS_R0 (insn))
1117 {
1118 /* Store PR at r0_val-4 from SP. Decrement r0 by 4*/
1119 int reg_nr = PR_C_REGNUM;
1120 where[reg_nr] = depth - (r0_val - 4);
1121 r0_val -= 4;
1122 get_frame_extra_info (fi)->leaf_function = 0;
1123 }
1124 else if (IS_MOV_R14_R0 (insn))
1125 {
1126 /* Store R14 at r0_val-4 from SP. Decrement r0 by 4 */
1127 where[fp_regnum] = depth - (r0_val - 4);
1128 r0_val -= 4;
1129 }
1130
1131 else if (IS_ADD_SP (insn))
1132 {
1133 depth -= ((insn & 0xff) ^ 0x80) - 0x80;
1134 }
1135 else if (IS_MOV_SP_FP (insn))
1136 break;
1137 }
1138 else
1139 {
1140 if (IS_ADDIL_SP_MEDIA (insn)
1141 || IS_ADDI_SP_MEDIA (insn))
1142 {
1143 depth -= sign_extend ((((insn & 0xffc00) ^ 0x80000) - 0x80000) >> 10, 9);
1144 }
1145
1146 else if (IS_STQ_R18_R15 (insn))
1147 {
1148 where[PR_REGNUM] =
1149 depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 3);
1150 get_frame_extra_info (fi)->leaf_function = 0;
1151 }
1152
1153 else if (IS_STL_R18_R15 (insn))
1154 {
1155 where[PR_REGNUM] =
1156 depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 2);
1157 get_frame_extra_info (fi)->leaf_function = 0;
1158 }
1159
1160 else if (IS_STQ_R14_R15 (insn))
1161 {
1162 where[fp_regnum] = depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 3);
1163 }
1164
1165 else if (IS_STL_R14_R15 (insn))
1166 {
1167 where[fp_regnum] = depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 2);
1168 }
1169
1170 else if (IS_MOV_SP_FP_MEDIA (insn))
1171 break;
1172 }
1173 }
1174
7bb11558 1175 /* Now we know how deep things are, we can work out their addresses. */
55ff77ac
CV		 1176 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
1177 {
1178 register_number = translate_rn_to_arch_reg_num (rn, media_mode);
1179
1180 if (where[rn] >= 0)
1181 {
1182 if (rn == fp_regnum)
1183 have_fp = 1;
1184
1185 /* Watch out! saved_regs is only for the real registers, and
7bb11558
MS		 1186 doesn't include space for the pseudo registers. */
1187 deprecated_get_frame_saved_regs (fi)[register_number]
1188 = get_frame_base (fi) - where[rn] + depth;
55ff77ac
CV		 1189 }
1190 else
7bb11558 1191 deprecated_get_frame_saved_regs (fi)[register_number] = 0;
55ff77ac
CV		 1192 }
1193
1194 if (have_fp)
1195 {
1196 /* SP_REGNUM is 15. For shmedia 15 is the real register. For
1197 shcompact 15 is the arch register corresponding to the pseudo
7bb11558 1198 register r15 which still is the SP register. */
55ff77ac 1199 /* The place on the stack where fp is stored contains the sp of
7bb11558 1200 the caller. */
55ff77ac
CV		 1201 /* Again, saved_registers contains only space for the real
1202 registers, so we store in DEPRECATED_FP_REGNUM position. */
1203 int size;
1204 if (tdep->sh_abi == SH_ABI_32)
1205 size = 4;
1206 else
7bb11558
MS		 1207 size = register_size (current_gdbarch, fp_regnum);
1208 deprecated_get_frame_saved_regs (fi)[sp_regnum]
1209 = read_memory_integer (deprecated_get_frame_saved_regs (fi)[fp_regnum],
1210 size);
55ff77ac
CV		 1211 }
1212 else
1b1d3794 1213 deprecated_get_frame_saved_regs (fi)[sp_regnum] = get_frame_base (fi);
55ff77ac 1214
7bb11558 1215 get_frame_extra_info (fi)->f_offset = depth - where[fp_regnum];
55ff77ac
CV		 1216}
1217
1218/* Initialize the extra info saved in a FRAME */
1219static void
1220sh64_init_extra_frame_info (int fromleaf, struct frame_info *fi)
1221{
1222 int media_mode = pc_is_isa32 (get_frame_pc (fi));
1223
1224 frame_extra_info_zalloc (fi, sizeof (struct frame_extra_info));
1225
1226 if (get_next_frame (fi))
1227 deprecated_update_frame_pc_hack (fi, DEPRECATED_FRAME_SAVED_PC (get_next_frame (fi)));
1228
1229 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), get_frame_base (fi),
1230 get_frame_base (fi)))
1231 {
1232 /* We need to setup fi->frame here because call_function_by_hand
1233 gets it wrong by assuming it's always FP. */
1234 deprecated_update_frame_base_hack (fi, deprecated_read_register_dummy (get_frame_pc (fi), get_frame_base (fi), SP_REGNUM));
1235 get_frame_extra_info (fi)->return_pc =
1236 deprecated_read_register_dummy (get_frame_pc (fi),
1237 get_frame_base (fi), PC_REGNUM);
1238 get_frame_extra_info (fi)->f_offset = -(DEPRECATED_CALL_DUMMY_LENGTH + 4);
1239 get_frame_extra_info (fi)->leaf_function = 0;
1240 return;
1241 }
1242 else
1243 {
1244 DEPRECATED_FRAME_INIT_SAVED_REGS (fi);
1245 get_frame_extra_info (fi)->return_pc =
1246 sh64_get_saved_pr (fi, PR_REGNUM);
1247 }
1248}
1249
1250static void
1251sh64_get_saved_register (char *raw_buffer, int *optimized, CORE_ADDR *addrp,
1252 struct frame_info *frame, int regnum,
1253 enum lval_type *lval)
1254{
1255 int media_mode;
1256 int live_regnum = regnum;
7bb11558 1257 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
55ff77ac
CV		 1258
1259 if (!target_has_registers)
1260 error ("No registers.");
1261
1262 /* Normal systems don't optimize out things with register numbers. */
1263 if (optimized != NULL)
1264 *optimized = 0;
1265
1266 if (addrp) /* default assumption: not found in memory */
1267 *addrp = 0;
1268
1269 if (raw_buffer)
1270 memset (raw_buffer, 0, sizeof (raw_buffer));
1271
1272 /* We must do this here, before the following while loop changes
1273 frame, and makes it NULL. If this is a media register number,
1274 but we are in compact mode, it will become the corresponding
1275 compact pseudo register. If there is no corresponding compact
1276 pseudo-register what do we do?*/
1277 media_mode = pc_is_isa32 (get_frame_pc (frame));
1278 live_regnum = translate_insn_rn (regnum, media_mode);
1279
1280 /* Note: since the current frame's registers could only have been
1281 saved by frames INTERIOR TO the current frame, we skip examining
1282 the current frame itself: otherwise, we would be getting the
1283 previous frame's registers which were saved by the current frame. */
1284
1285 while (frame && ((frame = get_next_frame (frame)) != NULL))
1286 {
1287 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame),
1288 get_frame_base (frame),
1289 get_frame_base (frame)))
1290 {
1291 if (lval) /* found it in a CALL_DUMMY frame */
1292 *lval = not_lval;
1293 if (raw_buffer)
1294 memcpy (raw_buffer,
1295 (deprecated_generic_find_dummy_frame (get_frame_pc (frame), get_frame_base (frame))
62700349 1296 + DEPRECATED_REGISTER_BYTE (regnum)),
7bb11558 1297 register_size (current_gdbarch, regnum));
55ff77ac
CV		 1298 return;
1299 }
1300
1301 DEPRECATED_FRAME_INIT_SAVED_REGS (frame);
1b1d3794
AC		 1302 if (deprecated_get_frame_saved_regs (frame) != NULL
1303 && deprecated_get_frame_saved_regs (frame)[regnum] != 0)
55ff77ac
CV		 1304 {
1305 if (lval) /* found it saved on the stack */
1306 *lval = lval_memory;
1307 if (regnum == SP_REGNUM)
1308 {
1309 if (raw_buffer) /* SP register treated specially */
7bb11558
MS		 1310 store_unsigned_integer (raw_buffer,
1311 register_size (current_gdbarch,
1312 regnum),
1b1d3794 1313 deprecated_get_frame_saved_regs (frame)[regnum]);
55ff77ac
CV		 1314 }
1315 else
1316 { /* any other register */
1317
1318 if (addrp)
1b1d3794 1319 *addrp = deprecated_get_frame_saved_regs (frame)[regnum];
55ff77ac
CV		 1320 if (raw_buffer)
1321 {
1322 int size;
1323 if (tdep->sh_abi == SH_ABI_32
1324 && (live_regnum == DEPRECATED_FP_REGNUM
1325 || live_regnum == PR_REGNUM))
1326 size = 4;
1327 else
7bb11558 1328 size = register_size (current_gdbarch, live_regnum);
55ff77ac 1329 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
1b1d3794 1330 read_memory (deprecated_get_frame_saved_regs (frame)[regnum], raw_buffer, size);
55ff77ac 1331 else
1b1d3794 1332 read_memory (deprecated_get_frame_saved_regs (frame)[regnum],
55ff77ac 1333 raw_buffer
7bb11558 1334 + register_size (current_gdbarch, live_regnum)
55ff77ac
CV		 1335 - size,
1336 size);
1337 }
1338 }
1339 return;
1340 }
1341 }
1342
1343 /* If we get thru the loop to this point, it means the register was
1344 not saved in any frame. Return the actual live-register value. */
1345
1346 if (lval) /* found it in a live register */
1347 *lval = lval_register;
1348 if (addrp)
62700349 1349 *addrp = DEPRECATED_REGISTER_BYTE (live_regnum);
55ff77ac
CV		 1350 if (raw_buffer)
1351 deprecated_read_register_gen (live_regnum, raw_buffer);
1352}
1353
1354static CORE_ADDR
1355sh64_extract_struct_value_address (char *regbuf)
1356{
62700349 1357 return (extract_unsigned_integer ((regbuf + DEPRECATED_REGISTER_BYTE (STRUCT_RETURN_REGNUM)),
7bb11558
MS		 1358 register_size (current_gdbarch,
1359 STRUCT_RETURN_REGNUM)));
55ff77ac
CV		 1360}
1361
1362static CORE_ADDR
1363sh_frame_saved_pc (struct frame_info *frame)
1364{
1365 return (get_frame_extra_info (frame)->return_pc);
1366}
1367
1368/* Discard from the stack the innermost frame, restoring all saved registers.
7bb11558 1369 Used in the 'return' command. */
55ff77ac
CV		 1370static void
1371sh64_pop_frame (void)
1372{
52f0bd74
AC		 1373 struct frame_info *frame = get_current_frame ();
1374 CORE_ADDR fp;
1375 int regnum;
7bb11558 1376 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
55ff77ac
CV		 1377
1378 int media_mode = pc_is_isa32 (get_frame_pc (frame));
1379
1380 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame),
1381 get_frame_base (frame),
1382 get_frame_base (frame)))
1383 generic_pop_dummy_frame ();
1384 else
1385 {
1386 fp = get_frame_base (frame);
1387 DEPRECATED_FRAME_INIT_SAVED_REGS (frame);
1388
1389 /* Copy regs from where they were saved in the frame */
1390 for (regnum = 0; regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++)
1b1d3794 1391 if (deprecated_get_frame_saved_regs (frame)[regnum])
55ff77ac
CV		 1392 {
1393 int size;
1394 if (tdep->sh_abi == SH_ABI_32
1395 && (regnum == DEPRECATED_FP_REGNUM
1396 || regnum == PR_REGNUM))
1397 size = 4;
1398 else
7bb11558
MS		 1399 size = register_size (current_gdbarch,
1400 translate_insn_rn (regnum, media_mode));
55ff77ac 1401 write_register (regnum,
1b1d3794 1402 read_memory_integer (deprecated_get_frame_saved_regs (frame)[regnum],
55ff77ac
CV		 1403 size));
1404 }
1405
1406 write_register (PC_REGNUM, get_frame_extra_info (frame)->return_pc);
1407 write_register (SP_REGNUM, fp + 8);
1408 }
1409 flush_cached_frames ();
1410}
1411
1412static CORE_ADDR
1413sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
1414{
1415 return sp & ~3;
1416}
1417
1418/* Function: push_arguments
1419 Setup the function arguments for calling a function in the inferior.
1420
85a453d5 1421 On the Renesas SH architecture, there are four registers (R4 to R7)
55ff77ac
CV		 1422 which are dedicated for passing function arguments. Up to the first
1423 four arguments (depending on size) may go into these registers.
1424 The rest go on the stack.
1425
1426 Arguments that are smaller than 4 bytes will still take up a whole
1427 register or a whole 32-bit word on the stack, and will be
1428 right-justified in the register or the stack word. This includes
1429 chars, shorts, and small aggregate types.
1430
1431 Arguments that are larger than 4 bytes may be split between two or
1432 more registers. If there are not enough registers free, an argument
1433 may be passed partly in a register (or registers), and partly on the
1434 stack. This includes doubles, long longs, and larger aggregates.
1435 As far as I know, there is no upper limit to the size of aggregates
1436 that will be passed in this way; in other words, the convention of
1437 passing a pointer to a large aggregate instead of a copy is not used.
1438
1439 An exceptional case exists for struct arguments (and possibly other
1440 aggregates such as arrays) if the size is larger than 4 bytes but
1441 not a multiple of 4 bytes. In this case the argument is never split
1442 between the registers and the stack, but instead is copied in its
1443 entirety onto the stack, AND also copied into as many registers as
1444 there is room for. In other words, space in registers permitting,
1445 two copies of the same argument are passed in. As far as I can tell,
1446 only the one on the stack is used, although that may be a function
1447 of the level of compiler optimization. I suspect this is a compiler
1448 bug. Arguments of these odd sizes are left-justified within the
1449 word (as opposed to arguments smaller than 4 bytes, which are
1450 right-justified).
1451
1452 If the function is to return an aggregate type such as a struct, it
1453 is either returned in the normal return value register R0 (if its
1454 size is no greater than one byte), or else the caller must allocate
1455 space into which the callee will copy the return value (if the size
1456 is greater than one byte). In this case, a pointer to the return
1457 value location is passed into the callee in register R2, which does
1458 not displace any of the other arguments passed in via registers R4
1459 to R7. */
1460
1461/* R2-R9 for integer types and integer equivalent (char, pointers) and
1462 non-scalar (struct, union) elements (even if the elements are
1463 floats).
1464 FR0-FR11 for single precision floating point (float)
1465 DR0-DR10 for double precision floating point (double)
1466
1467 If a float is argument number 3 (for instance) and arguments number
1468 1,2, and 4 are integer, the mapping will be:
1469 arg1 -->R2, arg2 --> R3, arg3 -->FR0, arg4 --> R5. I.e. R4 is not used.
1470
1471 If a float is argument number 10 (for instance) and arguments number
1472 1 through 10 are integer, the mapping will be:
1473 arg1->R2, arg2->R3, arg3->R4, arg4->R5, arg5->R6, arg6->R7, arg7->R8,
1474 arg8->R9, arg9->(0,SP)stack(8-byte aligned), arg10->FR0, arg11->stack(16,SP).
1475 I.e. there is hole in the stack.
1476
1477 Different rules apply for variable arguments functions, and for functions
7bb11558 1478 for which the prototype is not known. */
55ff77ac
CV		 1479
1480static CORE_ADDR
1481sh64_push_arguments (int nargs, struct value **args, CORE_ADDR sp,
1482 int struct_return, CORE_ADDR struct_addr)
1483{
1484 int stack_offset, stack_alloc;
1485 int int_argreg;
1486 int float_argreg;
1487 int double_argreg;
1488 int float_arg_index = 0;
1489 int double_arg_index = 0;
1490 int argnum;
1491 struct type *type;
1492 CORE_ADDR regval;
1493 char *val;
1494 char valbuf[8];
1495 char valbuf_tmp[8];
1496 int len;
1497 int argreg_size;
1498 int fp_args[12];
7bb11558 1499 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
55ff77ac
CV		 1500
1501 memset (fp_args, 0, sizeof (fp_args));
1502
1503 /* first force sp to a 8-byte alignment */
1504 sp = sp & ~7;
1505
1506 /* The "struct return pointer" pseudo-argument has its own dedicated
1507 register */
1508
1509 if (struct_return)
1510 write_register (STRUCT_RETURN_REGNUM, struct_addr);
1511
1512 /* Now make sure there's space on the stack */
1513 for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++)
1514 stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 7) & ~7);
1515 sp -= stack_alloc; /* make room on stack for args */
1516
1517 /* Now load as many as possible of the first arguments into
1518 registers, and push the rest onto the stack. There are 64 bytes
1519 in eight registers available. Loop thru args from first to last. */
1520
1521 int_argreg = ARG0_REGNUM;
1522 float_argreg = FP0_REGNUM;
1523 double_argreg = DR0_REGNUM;
1524
1525 for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
1526 {
1527 type = VALUE_TYPE (args[argnum]);
1528 len = TYPE_LENGTH (type);
1529 memset (valbuf, 0, sizeof (valbuf));
1530
1531 if (TYPE_CODE (type) != TYPE_CODE_FLT)
1532 {
7bb11558 1533 argreg_size = register_size (current_gdbarch, int_argreg);
55ff77ac
CV		 1534
1535 if (len < argreg_size)
1536 {
1537 /* value gets right-justified in the register or stack word */
1538 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1539 memcpy (valbuf + argreg_size - len,
1540 (char *) VALUE_CONTENTS (args[argnum]), len);
1541 else
1542 memcpy (valbuf, (char *) VALUE_CONTENTS (args[argnum]), len);
1543
1544 val = valbuf;
1545 }
1546 else
1547 val = (char *) VALUE_CONTENTS (args[argnum]);
1548
1549 while (len > 0)
1550 {
1551 if (int_argreg > ARGLAST_REGNUM)
1552 {
1553 /* must go on the stack */
1554 write_memory (sp + stack_offset, val, argreg_size);
1555 stack_offset += 8;/*argreg_size;*/
1556 }
1557 /* NOTE WELL!!!!! This is not an "else if" clause!!!
1558 That's because some *&^%$ things get passed on the stack
1559 AND in the registers! */
1560 if (int_argreg <= ARGLAST_REGNUM)
1561 {
1562 /* there's room in a register */
1563 regval = extract_unsigned_integer (val, argreg_size);
1564 write_register (int_argreg, regval);
1565 }
1566 /* Store the value 8 bytes at a time. This means that
1567 things larger than 8 bytes may go partly in registers
1568 and partly on the stack. FIXME: argreg is incremented
7bb11558 1569 before we use its size. */
55ff77ac
CV		 1570 len -= argreg_size;
1571 val += argreg_size;
1572 int_argreg++;
1573 }
1574 }
1575 else
1576 {
1577 val = (char *) VALUE_CONTENTS (args[argnum]);
1578 if (len == 4)
1579 {
1580 /* Where is it going to be stored? */
1581 while (fp_args[float_arg_index])
1582 float_arg_index ++;
1583
1584 /* Now float_argreg points to the register where it
1585 should be stored. Are we still within the allowed
1586 register set? */
1587 if (float_arg_index <= FLOAT_ARGLAST_REGNUM)
1588 {
1589 /* Goes in FR0...FR11 */
1590 deprecated_write_register_gen (FP0_REGNUM + float_arg_index,
1591 val);
1592 fp_args[float_arg_index] = 1;
7bb11558 1593 /* Skip the corresponding general argument register. */
55ff77ac
CV		 1594 int_argreg ++;
1595 }
1596 else
1597 ;
1598 /* Store it as the integers, 8 bytes at the time, if
7bb11558 1599 necessary spilling on the stack. */
55ff77ac
CV		 1600
1601 }
1602 else if (len == 8)
1603 {
1604 /* Where is it going to be stored? */
1605 while (fp_args[double_arg_index])
1606 double_arg_index += 2;
1607 /* Now double_argreg points to the register
1608 where it should be stored.
1609 Are we still within the allowed register set? */
1610 if (double_arg_index < FLOAT_ARGLAST_REGNUM)
1611 {
1612 /* Goes in DR0...DR10 */
1613 /* The numbering of the DRi registers is consecutive,
7bb11558 1614 i.e. includes odd numbers. */
55ff77ac
CV		 1615 int double_register_offset = double_arg_index / 2;
1616 int regnum = DR0_REGNUM +
1617 double_register_offset;
1618#if 0
1619 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
1620 {
1621 memset (valbuf_tmp, 0, sizeof (valbuf_tmp));
1622 DEPRECATED_REGISTER_CONVERT_TO_VIRTUAL (regnum,
1623 type, val,
1624 valbuf_tmp);
1625 val = valbuf_tmp;
1626 }
1627#endif
1628 /* Note: must use write_register_gen here instead
1629 of regcache_raw_write, because
1630 regcache_raw_write works only for real
1631 registers, not pseudo. write_register_gen will
1632 call the gdbarch function to do register
1633 writes, and that will properly know how to deal
7bb11558 1634 with pseudoregs. */
55ff77ac
CV		 1635 deprecated_write_register_gen (regnum, val);
1636 fp_args[double_arg_index] = 1;
1637 fp_args[double_arg_index + 1] = 1;
7bb11558 1638 /* Skip the corresponding general argument register. */
55ff77ac
CV		 1639 int_argreg ++;
1640 }
1641 else
1642 ;
1643 /* Store it as the integers, 8 bytes at the time, if
7bb11558 1644 necessary spilling on the stack. */
55ff77ac
CV		 1645 }
1646 }
1647 }
1648 return sp;
1649}
1650
1651/* Function: push_return_address (pc)
1652 Set up the return address for the inferior function call.
1653 Needed for targets where we don't actually execute a JSR/BSR instruction */
1654
1655static CORE_ADDR
1656sh64_push_return_address (CORE_ADDR pc, CORE_ADDR sp)
1657{
e8a7b686 1658 write_register (PR_REGNUM, entry_point_address ());
55ff77ac
CV		 1659 return sp;
1660}
1661
1662/* Find a function's return value in the appropriate registers (in
1663 regbuf), and copy it into valbuf. Extract from an array REGBUF
1664 containing the (raw) register state a function return value of type
1665 TYPE, and copy that, in virtual format, into VALBUF. */
1666static void
1667sh64_extract_return_value (struct type *type, char *regbuf, char *valbuf)
1668{
1669 int offset;
1670 int return_register;
1671 int len = TYPE_LENGTH (type);
7bb11558 1672 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
55ff77ac
CV		 1673
1674 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1675 {
1676 if (len == 4)
1677 {
1678 /* Return value stored in FP0_REGNUM */
1679 return_register = FP0_REGNUM;
62700349 1680 offset = DEPRECATED_REGISTER_BYTE (return_register);
7bb11558 1681 memcpy (valbuf, (char *) regbuf + offset, len);
55ff77ac
CV		 1682 }
1683 else if (len == 8)
1684 {
1685 /* return value stored in DR0_REGNUM */
1686 DOUBLEST val;
1687
1688 return_register = DR0_REGNUM;
62700349 1689 offset = DEPRECATED_REGISTER_BYTE (return_register);
55ff77ac
CV		 1690
1691 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
1692 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
1693 (char *) regbuf + offset, &val);
1694 else
1695 floatformat_to_doublest (&floatformat_ieee_double_big,
1696 (char *) regbuf + offset, &val);
7bb11558 1697 store_typed_floating (valbuf, type, val);
55ff77ac
CV		 1698 }
1699 }
1700 else
1701 {
1702 if (len <= 8)
1703 {
1704 /* Result is in register 2. If smaller than 8 bytes, it is padded
7bb11558 1705 at the most significant end. */
55ff77ac
CV		 1706 return_register = DEFAULT_RETURN_REGNUM;
1707 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
62700349 1708 offset = DEPRECATED_REGISTER_BYTE (return_register) +
7bb11558 1709 register_size (current_gdbarch, return_register) - len;
55ff77ac 1710 else
62700349 1711 offset = DEPRECATED_REGISTER_BYTE (return_register);
55ff77ac
CV		 1712 memcpy (valbuf, (char *) regbuf + offset, len);
1713 }
1714 else
1715 error ("bad size for return value");
1716 }
1717}
1718
1719/* Write into appropriate registers a function return value
1720 of type TYPE, given in virtual format.
1721 If the architecture is sh4 or sh3e, store a function's return value
1722 in the R0 general register or in the FP0 floating point register,
1723 depending on the type of the return value. In all the other cases
7bb11558 1724 the result is stored in r0, left-justified. */
55ff77ac
CV		 1725
1726static void
1727sh64_store_return_value (struct type *type, char *valbuf)
1728{
7bb11558 1729 char buf[64]; /* more than enough... */
55ff77ac
CV		 1730 int len = TYPE_LENGTH (type);
1731
1732 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1733 {
1734 if (len == 4)
1735 {
1736 /* Return value stored in FP0_REGNUM */
1737 deprecated_write_register_gen (FP0_REGNUM, valbuf);
1738 }
1739 if (len == 8)
1740 {
1741 /* return value stored in DR0_REGNUM */
1742 /* FIXME: Implement */
1743 }
1744 }
1745 else
1746 {
1747 int return_register = DEFAULT_RETURN_REGNUM;
1748 int offset = 0;
1749
7bb11558 1750 if (len <= register_size (current_gdbarch, return_register))
55ff77ac 1751 {
7bb11558
MS		 1752 /* Pad with zeros. */
1753 memset (buf, 0, register_size (current_gdbarch, return_register));
55ff77ac 1754 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
7bb11558
MS		 1755 offset = 0; /*register_size (current_gdbarch,
1756 return_register) - len;*/
55ff77ac 1757 else
7bb11558 1758 offset = register_size (current_gdbarch, return_register) - len;
55ff77ac
CV		 1759
1760 memcpy (buf + offset, valbuf, len);
1761 deprecated_write_register_gen (return_register, buf);
1762 }
1763 else
1764 deprecated_write_register_gen (return_register, valbuf);
1765 }
1766}
1767
1768static void
1769sh64_show_media_regs (void)
1770{
1771 int i;
7bb11558 1772 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
55ff77ac
CV		 1773
1774 printf_filtered ("PC=%s SR=%016llx \n",
1775 paddr (read_register (PC_REGNUM)),
1776 (long long) read_register (SR_REGNUM));
1777
1778 printf_filtered ("SSR=%016llx SPC=%016llx \n",
1779 (long long) read_register (SSR_REGNUM),
1780 (long long) read_register (SPC_REGNUM));
1781 printf_filtered ("FPSCR=%016lx\n ",
1782 (long) read_register (FPSCR_REGNUM));
1783
1784 for (i = 0; i < 64; i = i + 4)
1785 printf_filtered ("\nR%d-R%d %016llx %016llx %016llx %016llx\n",
1786 i, i + 3,
1787 (long long) read_register (i + 0),
1788 (long long) read_register (i + 1),
1789 (long long) read_register (i + 2),
1790 (long long) read_register (i + 3));
1791
1792 printf_filtered ("\n");
1793
1794 for (i = 0; i < 64; i = i + 8)
1795 printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1796 i, i + 7,
1797 (long) read_register (FP0_REGNUM + i + 0),
1798 (long) read_register (FP0_REGNUM + i + 1),
1799 (long) read_register (FP0_REGNUM + i + 2),
1800 (long) read_register (FP0_REGNUM + i + 3),
1801 (long) read_register (FP0_REGNUM + i + 4),
1802 (long) read_register (FP0_REGNUM + i + 5),
1803 (long) read_register (FP0_REGNUM + i + 6),
1804 (long) read_register (FP0_REGNUM + i + 7));
1805}
1806
1807static void
1808sh64_show_compact_regs (void)
1809{
1810 int i;
7bb11558 1811 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
55ff77ac
CV		 1812
1813 printf_filtered ("PC=%s \n",
1814 paddr (read_register (PC_C_REGNUM)));
1815
1816 printf_filtered ("GBR=%08lx MACH=%08lx MACL=%08lx PR=%08lx T=%08lx\n",
1817 (long) read_register (GBR_C_REGNUM),
1818 (long) read_register (MACH_C_REGNUM),
1819 (long) read_register (MACL_C_REGNUM),
1820 (long) read_register (PR_C_REGNUM),
1821 (long) read_register (T_C_REGNUM));
1822 printf_filtered ("FPSCR=%08lx FPUL=%08lx\n",
1823 (long) read_register (FPSCR_C_REGNUM),
1824 (long) read_register (FPUL_C_REGNUM));
1825
1826 for (i = 0; i < 16; i = i + 4)
1827 printf_filtered ("\nR%d-R%d %08lx %08lx %08lx %08lx\n",
1828 i, i + 3,
1829 (long) read_register (i + 0),
1830 (long) read_register (i + 1),
1831 (long) read_register (i + 2),
1832 (long) read_register (i + 3));
1833
1834 printf_filtered ("\n");
1835
1836 for (i = 0; i < 16; i = i + 8)
1837 printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1838 i, i + 7,
1839 (long) read_register (FP0_REGNUM + i + 0),
1840 (long) read_register (FP0_REGNUM + i + 1),
1841 (long) read_register (FP0_REGNUM + i + 2),
1842 (long) read_register (FP0_REGNUM + i + 3),
1843 (long) read_register (FP0_REGNUM + i + 4),
1844 (long) read_register (FP0_REGNUM + i + 5),
1845 (long) read_register (FP0_REGNUM + i + 6),
1846 (long) read_register (FP0_REGNUM + i + 7));
1847}
1848
7bb11558
MS		 1849/* FIXME!!! This only shows the registers for shmedia, excluding the
1850 pseudo registers. */
55ff77ac
CV		 1851void
1852sh64_show_regs (void)
1853{
1854 if (deprecated_selected_frame
1855 && pc_is_isa32 (get_frame_pc (deprecated_selected_frame)))
1856 sh64_show_media_regs ();
1857 else
1858 sh64_show_compact_regs ();
1859}
1860
1861/* *INDENT-OFF* */
1862/*
1863 SH MEDIA MODE (ISA 32)
1864 general registers (64-bit) 0-63
18650 r0, r1, r2, r3, r4, r5, r6, r7,
186664 r8, r9, r10, r11, r12, r13, r14, r15,
1867128 r16, r17, r18, r19, r20, r21, r22, r23,
1868192 r24, r25, r26, r27, r28, r29, r30, r31,
1869256 r32, r33, r34, r35, r36, r37, r38, r39,
1870320 r40, r41, r42, r43, r44, r45, r46, r47,
1871384 r48, r49, r50, r51, r52, r53, r54, r55,
1872448 r56, r57, r58, r59, r60, r61, r62, r63,
1873
1874 pc (64-bit) 64
1875512 pc,
1876
1877 status reg., saved status reg., saved pc reg. (64-bit) 65-67
1878520 sr, ssr, spc,
1879
1880 target registers (64-bit) 68-75
1881544 tr0, tr1, tr2, tr3, tr4, tr5, tr6, tr7,
1882
1883 floating point state control register (32-bit) 76
1884608 fpscr,
1885
1886 single precision floating point registers (32-bit) 77-140
1887612 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
1888644 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15,
1889676 fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23,
1890708 fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31,
1891740 fr32, fr33, fr34, fr35, fr36, fr37, fr38, fr39,
1892772 fr40, fr41, fr42, fr43, fr44, fr45, fr46, fr47,
1893804 fr48, fr49, fr50, fr51, fr52, fr53, fr54, fr55,
1894836 fr56, fr57, fr58, fr59, fr60, fr61, fr62, fr63,
1895
1896TOTAL SPACE FOR REGISTERS: 868 bytes
1897
1898From here on they are all pseudo registers: no memory allocated.
1899REGISTER_BYTE returns the register byte for the base register.
1900
1901 double precision registers (pseudo) 141-172
1902 dr0, dr2, dr4, dr6, dr8, dr10, dr12, dr14,
1903 dr16, dr18, dr20, dr22, dr24, dr26, dr28, dr30,
1904 dr32, dr34, dr36, dr38, dr40, dr42, dr44, dr46,
1905 dr48, dr50, dr52, dr54, dr56, dr58, dr60, dr62,
1906
1907 floating point pairs (pseudo) 173-204
1908 fp0, fp2, fp4, fp6, fp8, fp10, fp12, fp14,
1909 fp16, fp18, fp20, fp22, fp24, fp26, fp28, fp30,
1910 fp32, fp34, fp36, fp38, fp40, fp42, fp44, fp46,
1911 fp48, fp50, fp52, fp54, fp56, fp58, fp60, fp62,
1912
1913 floating point vectors (4 floating point regs) (pseudo) 205-220
1914 fv0, fv4, fv8, fv12, fv16, fv20, fv24, fv28,
1915 fv32, fv36, fv40, fv44, fv48, fv52, fv56, fv60,
1916
1917 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
1918 r0_c, r1_c, r2_c, r3_c, r4_c, r5_c, r6_c, r7_c,
1919 r8_c, r9_c, r10_c, r11_c, r12_c, r13_c, r14_c, r15_c,
1920 pc_c,
1921 gbr_c, mach_c, macl_c, pr_c, t_c,
1922 fpscr_c, fpul_c,
1923 fr0_c, fr1_c, fr2_c, fr3_c, fr4_c, fr5_c, fr6_c, fr7_c,
1924 fr8_c, fr9_c, fr10_c, fr11_c, fr12_c, fr13_c, fr14_c, fr15_c
1925 dr0_c, dr2_c, dr4_c, dr6_c, dr8_c, dr10_c, dr12_c, dr14_c
1926 fv0_c, fv4_c, fv8_c, fv12_c
1927*/
1928/* *INDENT-ON* */
1929static int
1930sh_sh64_register_byte (int reg_nr)
1931{
1932 int base_regnum = -1;
7bb11558 1933 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
55ff77ac
CV		 1934
1935 /* If it is a pseudo register, get the number of the first floating
7bb11558 1936 point register that is part of it. */
55ff77ac
CV		 1937 if (reg_nr >= DR0_REGNUM
1938 && reg_nr <= DR_LAST_REGNUM)
1939 base_regnum = dr_reg_base_num (reg_nr);
1940
1941 else if (reg_nr >= FPP0_REGNUM
1942 && reg_nr <= FPP_LAST_REGNUM)
1943 base_regnum = fpp_reg_base_num (reg_nr);
1944
1945 else if (reg_nr >= FV0_REGNUM
1946 && reg_nr <= FV_LAST_REGNUM)
1947 base_regnum = fv_reg_base_num (reg_nr);
1948
1949 /* sh compact pseudo register. FPSCR is a pathological case, need to
7bb11558 1950 treat it as special. */
55ff77ac
CV		 1951 else if ((reg_nr >= R0_C_REGNUM
1952 && reg_nr <= FV_LAST_C_REGNUM)
1953 && reg_nr != FPSCR_C_REGNUM)
1954 base_regnum = sh64_compact_reg_base_num (reg_nr);
1955
7bb11558
MS		 1956 /* Now return the offset in bytes within the register cache. */
1957 /* sh media pseudo register, i.e. any of DR, FFP, FV registers. */
55ff77ac
CV		 1958 if (reg_nr >= DR0_REGNUM
1959 && reg_nr <= FV_LAST_REGNUM)
1960 return (base_regnum - FP0_REGNUM + 1) * 4
1961 + (TR7_REGNUM + 1) * 8;
1962
1963 /* sh compact pseudo register: general register */
1964 if ((reg_nr >= R0_C_REGNUM
1965 && reg_nr <= R_LAST_C_REGNUM))
1966 return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
1967 ? base_regnum * 8 + 4
1968 : base_regnum * 8);
1969
1970 /* sh compact pseudo register: */
1971 if (reg_nr == PC_C_REGNUM
1972 || reg_nr == GBR_C_REGNUM
1973 || reg_nr == MACL_C_REGNUM
1974 || reg_nr == PR_C_REGNUM)
1975 return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
1976 ? base_regnum * 8 + 4
1977 : base_regnum * 8);
1978
1979 if (reg_nr == MACH_C_REGNUM)
1980 return base_regnum * 8;
1981
1982 if (reg_nr == T_C_REGNUM)
1983 return base_regnum * 8; /* FIXME??? how do we get bit 0? Do we have to? */
1984
1985 /* sh compact pseudo register: floating point register */
1986 else if (reg_nr >= FP0_C_REGNUM
1987 && reg_nr <= FV_LAST_C_REGNUM)
1988 return (base_regnum - FP0_REGNUM) * 4
1989 + (TR7_REGNUM + 1) * 8 + 4;
1990
1991 else if (reg_nr == FPSCR_C_REGNUM)
1992 /* This is complicated, for now return the beginning of the
7bb11558 1993 architectural FPSCR register. */
55ff77ac
CV		 1994 return (TR7_REGNUM + 1) * 8;
1995
1996 else if (reg_nr == FPUL_C_REGNUM)
1997 return ((base_regnum - FP0_REGNUM) * 4 +
1998 (TR7_REGNUM + 1) * 8 + 4);
1999
7bb11558
MS		 2000 /* It is not a pseudo register. */
2001 /* It is a 64 bit register. */
55ff77ac
CV		 2002 else if (reg_nr <= TR7_REGNUM)
2003 return reg_nr * 8;
2004
7bb11558 2005 /* It is a 32 bit register. */
55ff77ac
CV		 2006 else if (reg_nr == FPSCR_REGNUM)
2007 return (FPSCR_REGNUM * 8);
2008
2009 /* It is floating point 32-bit register */
2010 else
2011 return ((TR7_REGNUM + 1) * 8
2012 + (reg_nr - FP0_REGNUM + 1) * 4);
2013}
2014
55ff77ac
CV		 2015static struct type *
2016sh_sh64_build_float_register_type (int high)
2017{
2018 struct type *temp;
2019
2020 temp = create_range_type (NULL, builtin_type_int, 0, high);
2021 return create_array_type (NULL, builtin_type_float, temp);
2022}
2023
7bb11558
MS		 2024/* Return the GDB type object for the "standard" data type
2025 of data in register REG_NR. */
55ff77ac 2026static struct type *
7bb11558 2027sh64_register_type (struct gdbarch *gdbarch, int reg_nr)
55ff77ac 2028{
7bb11558 2029 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
55ff77ac
CV		 2030
2031 if ((reg_nr >= FP0_REGNUM
2032 && reg_nr <= FP_LAST_REGNUM)
2033 || (reg_nr >= FP0_C_REGNUM
2034 && reg_nr <= FP_LAST_C_REGNUM))
2035 return builtin_type_float;
2036 else if ((reg_nr >= DR0_REGNUM
2037 && reg_nr <= DR_LAST_REGNUM)
2038 || (reg_nr >= DR0_C_REGNUM
2039 && reg_nr <= DR_LAST_C_REGNUM))
2040 return builtin_type_double;
2041 else if (reg_nr >= FPP0_REGNUM
2042 && reg_nr <= FPP_LAST_REGNUM)
2043 return sh_sh64_build_float_register_type (1);
2044 else if ((reg_nr >= FV0_REGNUM
2045 && reg_nr <= FV_LAST_REGNUM)
2046 ||(reg_nr >= FV0_C_REGNUM
2047 && reg_nr <= FV_LAST_C_REGNUM))
2048 return sh_sh64_build_float_register_type (3);
2049 else if (reg_nr == FPSCR_REGNUM)
2050 return builtin_type_int;
2051 else if (reg_nr >= R0_C_REGNUM
2052 && reg_nr < FP0_C_REGNUM)
2053 return builtin_type_int;
2054 else
2055 return builtin_type_long_long;
2056}
2057
2058static void
2059sh_sh64_register_convert_to_virtual (int regnum, struct type *type,
2060 char *from, char *to)
2061{
7bb11558 2062 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
55ff77ac
CV		 2063
2064 if (TARGET_BYTE_ORDER != BFD_ENDIAN_LITTLE)
2065 {
7bb11558
MS		 2066 /* It is a no-op. */
2067 memcpy (to, from, register_size (current_gdbarch, regnum));
55ff77ac
CV		 2068 return;
2069 }
2070
2071 if ((regnum >= DR0_REGNUM
2072 && regnum <= DR_LAST_REGNUM)
2073 || (regnum >= DR0_C_REGNUM
2074 && regnum <= DR_LAST_C_REGNUM))
2075 {
2076 DOUBLEST val;
7bb11558
MS		 2077 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
2078 from, &val);
2079 store_typed_floating(to, type, val);
55ff77ac
CV		 2080 }
2081 else
7bb11558 2082 error("sh64_register_convert_to_virtual called with non DR register number");
55ff77ac
CV		 2083}
2084
2085static void
2086sh_sh64_register_convert_to_raw (struct type *type, int regnum,
2087 const void *from, void *to)
2088{
7bb11558 2089 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
55ff77ac
CV		 2090
2091 if (TARGET_BYTE_ORDER != BFD_ENDIAN_LITTLE)
2092 {
7bb11558
MS		 2093 /* It is a no-op. */
2094 memcpy (to, from, register_size (current_gdbarch, regnum));
55ff77ac
CV		 2095 return;
2096 }
2097
2098 if ((regnum >= DR0_REGNUM
2099 && regnum <= DR_LAST_REGNUM)
2100 || (regnum >= DR0_C_REGNUM
2101 && regnum <= DR_LAST_C_REGNUM))
2102 {
2103 DOUBLEST val = deprecated_extract_floating (from, TYPE_LENGTH(type));
7bb11558
MS		 2104 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword,
2105 &val, to);
55ff77ac
CV		 2106 }
2107 else
7bb11558 2108 error("sh64_register_convert_to_raw called with non DR register number");
55ff77ac
CV		 2109}
2110
2111static void
2112sh64_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2113 int reg_nr, void *buffer)
2114{
2115 int base_regnum;
2116 int portion;
2117 int offset = 0;
2118 char temp_buffer[MAX_REGISTER_SIZE];
7bb11558 2119 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
55ff77ac
CV		 2120
2121 if (reg_nr >= DR0_REGNUM
2122 && reg_nr <= DR_LAST_REGNUM)
2123 {
2124 base_regnum = dr_reg_base_num (reg_nr);
2125
7bb11558 2126 /* Build the value in the provided buffer. */
55ff77ac 2127 /* DR regs are double precision registers obtained by
7bb11558 2128 concatenating 2 single precision floating point registers. */
55ff77ac
CV		 2129 for (portion = 0; portion < 2; portion++)
2130 regcache_raw_read (regcache, base_regnum + portion,
2131 (temp_buffer
7bb11558 2132 + register_size (gdbarch, base_regnum) * portion));
55ff77ac 2133
7bb11558
MS		 2134 /* We must pay attention to the endianness. */
2135 sh_sh64_register_convert_to_virtual (reg_nr,
2136 gdbarch_register_type (gdbarch,
2137 reg_nr),
55ff77ac
CV		 2138 temp_buffer, buffer);
2139
2140 }
2141
2142 else if (reg_nr >= FPP0_REGNUM
2143 && reg_nr <= FPP_LAST_REGNUM)
2144 {
2145 base_regnum = fpp_reg_base_num (reg_nr);
2146
7bb11558 2147 /* Build the value in the provided buffer. */
55ff77ac 2148 /* FPP regs are pairs of single precision registers obtained by
7bb11558 2149 concatenating 2 single precision floating point registers. */
55ff77ac
CV		 2150 for (portion = 0; portion < 2; portion++)
2151 regcache_raw_read (regcache, base_regnum + portion,
2152 ((char *) buffer
7bb11558 2153 + register_size (gdbarch, base_regnum) * portion));
55ff77ac
CV		 2154 }
2155
2156 else if (reg_nr >= FV0_REGNUM
2157 && reg_nr <= FV_LAST_REGNUM)
2158 {
2159 base_regnum = fv_reg_base_num (reg_nr);
2160
7bb11558 2161 /* Build the value in the provided buffer. */
55ff77ac 2162 /* FV regs are vectors of single precision registers obtained by
7bb11558 2163 concatenating 4 single precision floating point registers. */
55ff77ac
CV		 2164 for (portion = 0; portion < 4; portion++)
2165 regcache_raw_read (regcache, base_regnum + portion,
2166 ((char *) buffer
7bb11558 2167 + register_size (gdbarch, base_regnum) * portion));
55ff77ac
CV		 2168 }
2169
2170 /* sh compact pseudo registers. 1-to-1 with a shmedia register */
2171 else if (reg_nr >= R0_C_REGNUM
2172 && reg_nr <= T_C_REGNUM)
2173 {
2174 base_regnum = sh64_compact_reg_base_num (reg_nr);
2175
7bb11558 2176 /* Build the value in the provided buffer. */
55ff77ac
CV		 2177 regcache_raw_read (regcache, base_regnum, temp_buffer);
2178 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2179 offset = 4;
2180 memcpy (buffer, temp_buffer + offset, 4); /* get LOWER 32 bits only????*/
2181 }
2182
2183 else if (reg_nr >= FP0_C_REGNUM
2184 && reg_nr <= FP_LAST_C_REGNUM)
2185 {
2186 base_regnum = sh64_compact_reg_base_num (reg_nr);
2187
7bb11558 2188 /* Build the value in the provided buffer. */
55ff77ac 2189 /* Floating point registers map 1-1 to the media fp regs,
7bb11558 2190 they have the same size and endianness. */
55ff77ac
CV		 2191 regcache_raw_read (regcache, base_regnum, buffer);
2192 }
2193
2194 else if (reg_nr >= DR0_C_REGNUM
2195 && reg_nr <= DR_LAST_C_REGNUM)
2196 {
2197 base_regnum = sh64_compact_reg_base_num (reg_nr);
2198
2199 /* DR_C regs are double precision registers obtained by
7bb11558 2200 concatenating 2 single precision floating point registers. */
55ff77ac
CV		 2201 for (portion = 0; portion < 2; portion++)
2202 regcache_raw_read (regcache, base_regnum + portion,
2203 (temp_buffer
7bb11558 2204 + register_size (gdbarch, base_regnum) * portion));
55ff77ac 2205
7bb11558
MS		 2206 /* We must pay attention to the endianness. */
2207 sh_sh64_register_convert_to_virtual (reg_nr,
2208 gdbarch_register_type (gdbarch,
2209 reg_nr),
55ff77ac
CV		 2210 temp_buffer, buffer);
2211 }
2212
2213 else if (reg_nr >= FV0_C_REGNUM
2214 && reg_nr <= FV_LAST_C_REGNUM)
2215 {
2216 base_regnum = sh64_compact_reg_base_num (reg_nr);
2217
7bb11558 2218 /* Build the value in the provided buffer. */
55ff77ac 2219 /* FV_C regs are vectors of single precision registers obtained by
7bb11558 2220 concatenating 4 single precision floating point registers. */
55ff77ac
CV		 2221 for (portion = 0; portion < 4; portion++)
2222 regcache_raw_read (regcache, base_regnum + portion,
2223 ((char *) buffer
7bb11558 2224 + register_size (gdbarch, base_regnum) * portion));
55ff77ac
CV		 2225 }
2226
2227 else if (reg_nr == FPSCR_C_REGNUM)
2228 {
2229 int fpscr_base_regnum;
2230 int sr_base_regnum;
2231 unsigned int fpscr_value;
2232 unsigned int sr_value;
2233 unsigned int fpscr_c_value;
2234 unsigned int fpscr_c_part1_value;
2235 unsigned int fpscr_c_part2_value;
2236
2237 fpscr_base_regnum = FPSCR_REGNUM;
2238 sr_base_regnum = SR_REGNUM;
2239
7bb11558 2240 /* Build the value in the provided buffer. */
55ff77ac
CV		 2241 /* FPSCR_C is a very weird register that contains sparse bits
2242 from the FPSCR and the SR architectural registers.
2243 Specifically: */
2244 /* *INDENT-OFF* */
2245 /*
2246 FPSRC_C bit
2247 0 Bit 0 of FPSCR
2248 1 reserved
2249 2-17 Bit 2-18 of FPSCR
2250 18-20 Bits 12,13,14 of SR
2251 21-31 reserved
2252 */
2253 /* *INDENT-ON* */
2254 /* Get FPSCR into a local buffer */
2255 regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer);
7bb11558 2256 /* Get value as an int. */
55ff77ac
CV		 2257 fpscr_value = extract_unsigned_integer (temp_buffer, 4);
2258 /* Get SR into a local buffer */
2259 regcache_raw_read (regcache, sr_base_regnum, temp_buffer);
7bb11558 2260 /* Get value as an int. */
55ff77ac 2261 sr_value = extract_unsigned_integer (temp_buffer, 4);
7bb11558 2262 /* Build the new value. */
55ff77ac
CV		 2263 fpscr_c_part1_value = fpscr_value & 0x3fffd;
2264 fpscr_c_part2_value = (sr_value & 0x7000) << 6;
2265 fpscr_c_value = fpscr_c_part1_value | fpscr_c_part2_value;
2266 /* Store that in out buffer!!! */
2267 store_unsigned_integer (buffer, 4, fpscr_c_value);
7bb11558 2268 /* FIXME There is surely an endianness gotcha here. */
55ff77ac
CV		 2269 }
2270
2271 else if (reg_nr == FPUL_C_REGNUM)
2272 {
2273 base_regnum = sh64_compact_reg_base_num (reg_nr);
2274
2275 /* FPUL_C register is floating point register 32,
7bb11558 2276 same size, same endianness. */
55ff77ac
CV		 2277 regcache_raw_read (regcache, base_regnum, buffer);
2278 }
2279}
2280
2281static void
2282sh64_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2283 int reg_nr, const void *buffer)
2284{
2285 int base_regnum, portion;
2286 int offset;
2287 char temp_buffer[MAX_REGISTER_SIZE];
2288 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2289
2290 if (reg_nr >= DR0_REGNUM
2291 && reg_nr <= DR_LAST_REGNUM)
2292 {
2293 base_regnum = dr_reg_base_num (reg_nr);
7bb11558
MS		 2294 /* We must pay attention to the endianness. */
2295 sh_sh64_register_convert_to_raw (gdbarch_register_type (gdbarch,
2296 reg_nr), reg_nr,
55ff77ac
CV		 2297 buffer, temp_buffer);
2298
2299
2300 /* Write the real regs for which this one is an alias. */
2301 for (portion = 0; portion < 2; portion++)
2302 regcache_raw_write (regcache, base_regnum + portion,
2303 (temp_buffer
7bb11558
MS		 2304 + register_size (gdbarch,
2305 base_regnum) * portion));
55ff77ac
CV		 2306 }
2307
2308 else if (reg_nr >= FPP0_REGNUM
2309 && reg_nr <= FPP_LAST_REGNUM)
2310 {
2311 base_regnum = fpp_reg_base_num (reg_nr);
2312
2313 /* Write the real regs for which this one is an alias. */
2314 for (portion = 0; portion < 2; portion++)
2315 regcache_raw_write (regcache, base_regnum + portion,
2316 ((char *) buffer
7bb11558
MS		 2317 + register_size (gdbarch,
2318 base_regnum) * portion));
55ff77ac
CV		 2319 }
2320
2321 else if (reg_nr >= FV0_REGNUM
2322 && reg_nr <= FV_LAST_REGNUM)
2323 {
2324 base_regnum = fv_reg_base_num (reg_nr);
2325
2326 /* Write the real regs for which this one is an alias. */
2327 for (portion = 0; portion < 4; portion++)
2328 regcache_raw_write (regcache, base_regnum + portion,
2329 ((char *) buffer
7bb11558
MS		 2330 + register_size (gdbarch,
2331 base_regnum) * portion));
55ff77ac
CV		 2332 }
2333
2334 /* sh compact general pseudo registers. 1-to-1 with a shmedia
2335 register but only 4 bytes of it. */
2336 else if (reg_nr >= R0_C_REGNUM
2337 && reg_nr <= T_C_REGNUM)
2338 {
2339 base_regnum = sh64_compact_reg_base_num (reg_nr);
7bb11558 2340 /* reg_nr is 32 bit here, and base_regnum is 64 bits. */
55ff77ac
CV		 2341 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2342 offset = 4;
2343 else
2344 offset = 0;
2345 /* Let's read the value of the base register into a temporary
2346 buffer, so that overwriting the last four bytes with the new
7bb11558 2347 value of the pseudo will leave the upper 4 bytes unchanged. */
55ff77ac
CV		 2348 regcache_raw_read (regcache, base_regnum, temp_buffer);
2349 /* Write as an 8 byte quantity */
2350 memcpy (temp_buffer + offset, buffer, 4);
2351 regcache_raw_write (regcache, base_regnum, temp_buffer);
2352 }
2353
2354 /* sh floating point compact pseudo registers. 1-to-1 with a shmedia
7bb11558 2355 registers. Both are 4 bytes. */
55ff77ac
CV		 2356 else if (reg_nr >= FP0_C_REGNUM
2357 && reg_nr <= FP_LAST_C_REGNUM)
2358 {
2359 base_regnum = sh64_compact_reg_base_num (reg_nr);
2360 regcache_raw_write (regcache, base_regnum, buffer);
2361 }
2362
2363 else if (reg_nr >= DR0_C_REGNUM
2364 && reg_nr <= DR_LAST_C_REGNUM)
2365 {
2366 base_regnum = sh64_compact_reg_base_num (reg_nr);
2367 for (portion = 0; portion < 2; portion++)
2368 {
7bb11558
MS		 2369 /* We must pay attention to the endianness. */
2370 sh_sh64_register_convert_to_raw (gdbarch_register_type (gdbarch,
2371 reg_nr),
2372 reg_nr,
55ff77ac
CV		 2373 buffer, temp_buffer);
2374
2375 regcache_raw_write (regcache, base_regnum + portion,
2376 (temp_buffer
7bb11558
MS		 2377 + register_size (gdbarch,
2378 base_regnum) * portion));
55ff77ac
CV		 2379 }
2380 }
2381
2382 else if (reg_nr >= FV0_C_REGNUM
2383 && reg_nr <= FV_LAST_C_REGNUM)
2384 {
2385 base_regnum = sh64_compact_reg_base_num (reg_nr);
2386
2387 for (portion = 0; portion < 4; portion++)
2388 {
2389 regcache_raw_write (regcache, base_regnum + portion,
2390 ((char *) buffer
7bb11558
MS		 2391 + register_size (gdbarch,
2392 base_regnum) * portion));
55ff77ac
CV		 2393 }
2394 }
2395
2396 else if (reg_nr == FPSCR_C_REGNUM)
2397 {
2398 int fpscr_base_regnum;
2399 int sr_base_regnum;
2400 unsigned int fpscr_value;
2401 unsigned int sr_value;
2402 unsigned int old_fpscr_value;
2403 unsigned int old_sr_value;
2404 unsigned int fpscr_c_value;
2405 unsigned int fpscr_mask;
2406 unsigned int sr_mask;
2407
2408 fpscr_base_regnum = FPSCR_REGNUM;
2409 sr_base_regnum = SR_REGNUM;
2410
2411 /* FPSCR_C is a very weird register that contains sparse bits
2412 from the FPSCR and the SR architectural registers.
2413 Specifically: */
2414 /* *INDENT-OFF* */
2415 /*
2416 FPSRC_C bit
2417 0 Bit 0 of FPSCR
2418 1 reserved
2419 2-17 Bit 2-18 of FPSCR
2420 18-20 Bits 12,13,14 of SR
2421 21-31 reserved
2422 */
2423 /* *INDENT-ON* */
7bb11558 2424 /* Get value as an int. */
55ff77ac
CV		 2425 fpscr_c_value = extract_unsigned_integer (buffer, 4);
2426
7bb11558 2427 /* Build the new values. */
55ff77ac
CV		 2428 fpscr_mask = 0x0003fffd;
2429 sr_mask = 0x001c0000;
2430
2431 fpscr_value = fpscr_c_value & fpscr_mask;
2432 sr_value = (fpscr_value & sr_mask) >> 6;
2433
2434 regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer);
2435 old_fpscr_value = extract_unsigned_integer (temp_buffer, 4);
2436 old_fpscr_value &= 0xfffc0002;
2437 fpscr_value |= old_fpscr_value;
2438 store_unsigned_integer (temp_buffer, 4, fpscr_value);
2439 regcache_raw_write (regcache, fpscr_base_regnum, temp_buffer);
2440
2441 regcache_raw_read (regcache, sr_base_regnum, temp_buffer);
2442 old_sr_value = extract_unsigned_integer (temp_buffer, 4);
2443 old_sr_value &= 0xffff8fff;
2444 sr_value |= old_sr_value;
2445 store_unsigned_integer (temp_buffer, 4, sr_value);
2446 regcache_raw_write (regcache, sr_base_regnum, temp_buffer);
2447 }
2448
2449 else if (reg_nr == FPUL_C_REGNUM)
2450 {
2451 base_regnum = sh64_compact_reg_base_num (reg_nr);
2452 regcache_raw_write (regcache, base_regnum, buffer);
2453 }
2454}
2455
7bb11558 2456/* Floating point vector of 4 float registers. */
55ff77ac
CV		 2457static void
2458do_fv_register_info (struct gdbarch *gdbarch, struct ui_file *file,
2459 int fv_regnum)
2460{
2461 int first_fp_reg_num = fv_reg_base_num (fv_regnum);
2462 fprintf_filtered (file, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
2463 fv_regnum - FV0_REGNUM,
2464 (int) read_register (first_fp_reg_num),
2465 (int) read_register (first_fp_reg_num + 1),
2466 (int) read_register (first_fp_reg_num + 2),
2467 (int) read_register (first_fp_reg_num + 3));
2468}
2469
7bb11558 2470/* Floating point vector of 4 float registers, compact mode. */
55ff77ac
CV		 2471static void
2472do_fv_c_register_info (int fv_regnum)
2473{
2474 int first_fp_reg_num = sh64_compact_reg_base_num (fv_regnum);
2475 printf_filtered ("fv%d_c\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
2476 fv_regnum - FV0_C_REGNUM,
2477 (int) read_register (first_fp_reg_num),
2478 (int) read_register (first_fp_reg_num + 1),
2479 (int) read_register (first_fp_reg_num + 2),
2480 (int) read_register (first_fp_reg_num + 3));
2481}
2482
2483/* Pairs of single regs. The DR are instead double precision
7bb11558 2484 registers. */
55ff77ac
CV		 2485static void
2486do_fpp_register_info (int fpp_regnum)
2487{
2488 int first_fp_reg_num = fpp_reg_base_num (fpp_regnum);
2489
2490 printf_filtered ("fpp%d\t0x%08x\t0x%08x\n",
2491 fpp_regnum - FPP0_REGNUM,
2492 (int) read_register (first_fp_reg_num),
2493 (int) read_register (first_fp_reg_num + 1));
2494}
2495
7bb11558 2496/* Double precision registers. */
55ff77ac
CV		 2497static void
2498do_dr_register_info (struct gdbarch *gdbarch, struct ui_file *file,
2499 int dr_regnum)
2500{
2501 int first_fp_reg_num = dr_reg_base_num (dr_regnum);
2502
2503 fprintf_filtered (file, "dr%d\t0x%08x%08x\n",
2504 dr_regnum - DR0_REGNUM,
2505 (int) read_register (first_fp_reg_num),
2506 (int) read_register (first_fp_reg_num + 1));
2507}
2508
7bb11558 2509/* Double precision registers, compact mode. */
55ff77ac
CV		 2510static void
2511do_dr_c_register_info (int dr_regnum)
2512{
2513 int first_fp_reg_num = sh64_compact_reg_base_num (dr_regnum);
2514
2515 printf_filtered ("dr%d_c\t0x%08x%08x\n",
2516 dr_regnum - DR0_C_REGNUM,
2517 (int) read_register (first_fp_reg_num),
2518 (int) read_register (first_fp_reg_num +1));
2519}
2520
7bb11558 2521/* General register in compact mode. */
55ff77ac
CV		 2522static void
2523do_r_c_register_info (int r_c_regnum)
2524{
2525 int regnum = sh64_compact_reg_base_num (r_c_regnum);
2526
2527 printf_filtered ("r%d_c\t0x%08x\n",
2528 r_c_regnum - R0_C_REGNUM,
2529 /*FIXME!!!*/ (int) read_register (regnum));
2530}
2531
2532/* FIXME:!! THIS SHOULD TAKE CARE OF GETTING THE RIGHT PORTION OF THE
7bb11558
MS		 2533 shmedia REGISTERS. */
2534/* Control registers, compact mode. */
55ff77ac
CV		 2535static void
2536do_cr_c_register_info (int cr_c_regnum)
2537{
2538 switch (cr_c_regnum)
2539 {
2540 case 237: printf_filtered ("pc_c\t0x%08x\n", (int) read_register (cr_c_regnum));
2541 break;
2542 case 238: printf_filtered ("gbr_c\t0x%08x\n", (int) read_register (cr_c_regnum));
2543 break;
2544 case 239: printf_filtered ("mach_c\t0x%08x\n", (int) read_register (cr_c_regnum));
2545 break;
2546 case 240: printf_filtered ("macl_c\t0x%08x\n", (int) read_register (cr_c_regnum));
2547 break;
2548 case 241: printf_filtered ("pr_c\t0x%08x\n", (int) read_register (cr_c_regnum));
2549 break;
2550 case 242: printf_filtered ("t_c\t0x%08x\n", (int) read_register (cr_c_regnum));
2551 break;
2552 case 243: printf_filtered ("fpscr_c\t0x%08x\n", (int) read_register (cr_c_regnum));
2553 break;
2554 case 244: printf_filtered ("fpul_c\t0x%08x\n", (int)read_register (cr_c_regnum));
2555 break;
2556 }
2557}
2558
2559static void
2560sh_do_fp_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
2561{ /* do values for FP (float) regs */
2562 char *raw_buffer;
2563 double flt; /* double extracted from raw hex data */
2564 int inv;
2565 int j;
2566
7bb11558 2567 /* Allocate space for the float. */
55ff77ac
CV		 2568 raw_buffer = (char *) alloca (register_size (gdbarch, FP0_REGNUM));
2569
2570 /* Get the data in raw format. */
2571 if (!frame_register_read (get_selected_frame (), regnum, raw_buffer))
2572 error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
2573
2574 /* Get the register as a number */
2575 flt = unpack_double (builtin_type_float, raw_buffer, &inv);
2576
7bb11558 2577 /* Print the name and some spaces. */
55ff77ac
CV		 2578 fputs_filtered (REGISTER_NAME (regnum), file);
2579 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file);
2580
7bb11558 2581 /* Print the value. */
55ff77ac
CV		 2582 if (inv)
2583 fprintf_filtered (file, "<invalid float>");
2584 else
2585 fprintf_filtered (file, "%-10.9g", flt);
2586
7bb11558 2587 /* Print the fp register as hex. */
55ff77ac
CV		 2588 fprintf_filtered (file, "\t(raw 0x");
2589 for (j = 0; j < register_size (gdbarch, regnum); j++)
2590 {
aa1ee363 2591 int idx = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? j
55ff77ac
CV		 2592 : register_size (gdbarch, regnum) - 1 - j;
2593 fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[idx]);
2594 }
2595 fprintf_filtered (file, ")");
2596 fprintf_filtered (file, "\n");
2597}
2598
2599static void
2600sh64_do_pseudo_register (int regnum)
2601{
7bb11558
MS		 2602 /* All the sh64-compact mode registers are pseudo registers. */
2603 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
55ff77ac
CV		 2604
2605 if (regnum < NUM_REGS
2606 || regnum >= NUM_REGS + NUM_PSEUDO_REGS_SH_MEDIA + NUM_PSEUDO_REGS_SH_COMPACT)
2607 internal_error (__FILE__, __LINE__,
2608 "Invalid pseudo register number %d\n", regnum);
2609
2610 else if ((regnum >= DR0_REGNUM
2611 && regnum <= DR_LAST_REGNUM))
2612 do_dr_register_info (current_gdbarch, gdb_stdout, regnum);
2613
2614 else if ((regnum >= DR0_C_REGNUM
2615 && regnum <= DR_LAST_C_REGNUM))
2616 do_dr_c_register_info (regnum);
2617
2618 else if ((regnum >= FV0_REGNUM
2619 && regnum <= FV_LAST_REGNUM))
2620 do_fv_register_info (current_gdbarch, gdb_stdout, regnum);
2621
2622 else if ((regnum >= FV0_C_REGNUM
2623 && regnum <= FV_LAST_C_REGNUM))
2624 do_fv_c_register_info (regnum);
2625
2626 else if (regnum >= FPP0_REGNUM
2627 && regnum <= FPP_LAST_REGNUM)
2628 do_fpp_register_info (regnum);
2629
2630 else if (regnum >= R0_C_REGNUM
2631 && regnum <= R_LAST_C_REGNUM)
7bb11558
MS		 2632 /* FIXME, this function will not print the right format. */
2633 do_r_c_register_info (regnum);
55ff77ac
CV		 2634 else if (regnum >= FP0_C_REGNUM
2635 && regnum <= FP_LAST_C_REGNUM)
7bb11558
MS		 2636 /* This should work also for pseudoregs. */
2637 sh_do_fp_register (current_gdbarch, gdb_stdout, regnum);
55ff77ac
CV		 2638 else if (regnum >= PC_C_REGNUM
2639 && regnum <= FPUL_C_REGNUM)
2640 do_cr_c_register_info (regnum);
55ff77ac
CV		 2641}
2642
2643static void
2644sh_do_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
2645{
2646 char raw_buffer[MAX_REGISTER_SIZE];
2647
2648 fputs_filtered (REGISTER_NAME (regnum), file);
2649 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file);
2650
2651 /* Get the data in raw format. */
2652 if (!frame_register_read (get_selected_frame (), regnum, raw_buffer))
2653 fprintf_filtered (file, "*value not available*\n");
2654
2655 val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0,
2656 file, 'x', 1, 0, Val_pretty_default);
2657 fprintf_filtered (file, "\t");
2658 val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0,
2659 file, 0, 1, 0, Val_pretty_default);
2660 fprintf_filtered (file, "\n");
2661}
2662
2663static void
2664sh_print_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
2665{
2666 if (regnum < 0 || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
2667 internal_error (__FILE__, __LINE__,
2668 "Invalid register number %d\n", regnum);
2669
2670 else if (regnum >= 0 && regnum < NUM_REGS)
2671 {
2672 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT)
2673 sh_do_fp_register (gdbarch, file, regnum); /* FP regs */
2674 else
2675 sh_do_register (gdbarch, file, regnum); /* All other regs */
2676 }
2677
2678 else if (regnum < NUM_REGS + NUM_PSEUDO_REGS)
2679 sh64_do_pseudo_register (regnum);
2680}
2681
2682static void
2683sh_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
2684 struct frame_info *frame, int regnum, int fpregs)
2685{
2686 if (regnum != -1) /* do one specified register */
2687 {
2688 if (*(REGISTER_NAME (regnum)) == '\0')
2689 error ("Not a valid register for the current processor type");
2690
2691 sh_print_register (gdbarch, file, regnum);
2692 }
2693 else
2694 /* do all (or most) registers */
2695 {
2696 regnum = 0;
2697 while (regnum < NUM_REGS)
2698 {
2699 /* If the register name is empty, it is undefined for this
2700 processor, so don't display anything. */
2701 if (REGISTER_NAME (regnum) == NULL
2702 || *(REGISTER_NAME (regnum)) == '\0')
2703 {
2704 regnum++;
2705 continue;
2706 }
2707
2708 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT)
2709 {
2710 if (fpregs)
2711 {
2712 /* true for "INFO ALL-REGISTERS" command */
2713 sh_do_fp_register (gdbarch, file, regnum); /* FP regs */
2714 regnum ++;
2715 }
2716 else
2717 regnum += FP_LAST_REGNUM - FP0_REGNUM; /* skip FP regs */
2718 }
2719 else
2720 {
2721 sh_do_register (gdbarch, file, regnum); /* All other regs */
2722 regnum++;
2723 }
2724 }
2725
2726 if (fpregs)
2727 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
2728 {
2729 sh64_do_pseudo_register (regnum);
2730 regnum++;
2731 }
2732 }
2733}
2734
2735static void
2736sh_compact_do_registers_info (int regnum, int fpregs)
2737{
7bb11558 2738 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
55ff77ac
CV		 2739 if (regnum != -1) /* do one specified register */
2740 {
2741 if (*(REGISTER_NAME (regnum)) == '\0')
2742 error ("Not a valid register for the current processor type");
2743
2744 if (regnum >= 0 && regnum < R0_C_REGNUM)
2745 error ("Not a valid register for the current processor mode.");
2746
2747 sh_print_register (current_gdbarch, gdb_stdout, regnum);
2748 }
2749 else
2750 /* do all compact registers */
2751 {
2752 regnum = R0_C_REGNUM;
2753 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
2754 {
2755 sh64_do_pseudo_register (regnum);
2756 regnum++;
2757 }
2758 }
2759}
2760
2761static void
2762sh64_do_registers_info (int regnum, int fpregs)
2763{
2764 if (pc_is_isa32 (get_frame_pc (deprecated_selected_frame)))
2765 sh_print_registers_info (current_gdbarch, gdb_stdout,
2766 deprecated_selected_frame, regnum, fpregs);
2767 else
7bb11558 2768 sh_compact_do_registers_info (regnum, fpregs);
55ff77ac
CV		 2769}
2770
2771#ifdef SVR4_SHARED_LIBS
2772
2773/* Fetch (and possibly build) an appropriate link_map_offsets structure
2774 for native i386 linux targets using the struct offsets defined in
2775 link.h (but without actual reference to that file).
2776
2777 This makes it possible to access i386-linux shared libraries from
2778 a gdb that was not built on an i386-linux host (for cross debugging).
2779 */
2780
2781struct link_map_offsets *
2782sh_linux_svr4_fetch_link_map_offsets (void)
2783{
2784 static struct link_map_offsets lmo;
2785 static struct link_map_offsets *lmp = 0;
2786
2787 if (lmp == 0)
2788 {
2789 lmp = &lmo;
2790
2791 lmo.r_debug_size = 8; /* 20 not actual size but all we need */
2792
2793 lmo.r_map_offset = 4;
2794 lmo.r_map_size = 4;
2795
2796 lmo.link_map_size = 20; /* 552 not actual size but all we need */
2797
2798 lmo.l_addr_offset = 0;
2799 lmo.l_addr_size = 4;
2800
2801 lmo.l_name_offset = 4;
2802 lmo.l_name_size = 4;
2803
2804 lmo.l_next_offset = 12;
2805 lmo.l_next_size = 4;
2806
2807 lmo.l_prev_offset = 16;
2808 lmo.l_prev_size = 4;
2809 }
2810
2811 return lmp;
2812}
2813#endif /* SVR4_SHARED_LIBS */
2814
2815gdbarch_init_ftype sh64_gdbarch_init;
2816
2817struct gdbarch *
2818sh64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2819{
2820 static LONGEST sh64_call_dummy_words[] = {0};
2821 struct gdbarch *gdbarch;
2822 struct gdbarch_tdep *tdep;
2823
2824 /* If there is already a candidate, use it. */
2825 arches = gdbarch_list_lookup_by_info (arches, &info);
2826 if (arches != NULL)
2827 return arches->gdbarch;
2828
2829 /* None found, create a new architecture from the information
7bb11558 2830 provided. */
55ff77ac
CV		 2831 tdep = XMALLOC (struct gdbarch_tdep);
2832 gdbarch = gdbarch_alloc (&info, tdep);
2833
2834 /* NOTE: cagney/2002-12-06: This can be deleted when this arch is
2835 ready to unwind the PC first (see frame.c:get_prev_frame()). */
0968aa8c 2836 set_gdbarch_deprecated_init_frame_pc (gdbarch, deprecated_init_frame_pc_default);
55ff77ac
CV		 2837
2838 /* Determine the ABI */
2839 if (info.abfd && bfd_get_arch_size (info.abfd) == 64)
2840 {
7bb11558 2841 /* If the ABI is the 64-bit one, it can only be sh-media. */
55ff77ac
CV		 2842 tdep->sh_abi = SH_ABI_64;
2843 set_gdbarch_ptr_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2844 set_gdbarch_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2845 }
2846 else
2847 {
2848 /* If the ABI is the 32-bit one it could be either media or
7bb11558 2849 compact. */
55ff77ac
CV		 2850 tdep->sh_abi = SH_ABI_32;
2851 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2852 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2853 }
2854
2855 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2856 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2857 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2858 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2859 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2860 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2861
2862 set_gdbarch_sp_regnum (gdbarch, 15);
2863 set_gdbarch_deprecated_fp_regnum (gdbarch, 14);
2864
2865 set_gdbarch_print_insn (gdbarch, gdb_print_insn_sh);
2866 set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);
2867
2868 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
2869
2870 set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
2871 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2872 set_gdbarch_decr_pc_after_break (gdbarch, 0);
2873 set_gdbarch_function_start_offset (gdbarch, 0);
2874
2875 set_gdbarch_frame_args_skip (gdbarch, 0);
2876 set_gdbarch_frameless_function_invocation (gdbarch, frameless_look_for_prologue);
2877 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2878
2879 set_gdbarch_deprecated_frame_saved_pc (gdbarch, sh_frame_saved_pc);
2880 set_gdbarch_deprecated_saved_pc_after_call (gdbarch, sh_saved_pc_after_call);
2881 set_gdbarch_frame_align (gdbarch, sh_frame_align);
2882
2883 set_gdbarch_num_pseudo_regs (gdbarch, NUM_PSEUDO_REGS_SH_MEDIA + NUM_PSEUDO_REGS_SH_COMPACT);
2884 set_gdbarch_fp0_regnum (gdbarch, SIM_SH64_FR0_REGNUM);
2885 set_gdbarch_pc_regnum (gdbarch, 64);
2886
7bb11558
MS		 2887 /* The number of real registers is the same whether we are in
2888 ISA16(compact) or ISA32(media). */
55ff77ac 2889 set_gdbarch_num_regs (gdbarch, SIM_SH64_NR_REGS);
55ff77ac
CV		 2890 set_gdbarch_deprecated_register_bytes (gdbarch,
2891 ((SIM_SH64_NR_FP_REGS + 1) * 4)
2892 + (SIM_SH64_NR_REGS - SIM_SH64_NR_FP_REGS -1) * 8);
2893
2894 set_gdbarch_register_name (gdbarch, sh_sh64_register_name);
7bb11558 2895 set_gdbarch_register_type (gdbarch, sh64_register_type);
55ff77ac 2896 set_gdbarch_deprecated_store_return_value (gdbarch, sh64_store_return_value);
55ff77ac 2897 set_gdbarch_deprecated_register_byte (gdbarch, sh_sh64_register_byte);
55ff77ac
CV		 2898 set_gdbarch_pseudo_register_read (gdbarch, sh64_pseudo_register_read);
2899 set_gdbarch_pseudo_register_write (gdbarch, sh64_pseudo_register_write);
2900
2901 set_gdbarch_deprecated_do_registers_info (gdbarch, sh64_do_registers_info);
2902 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh64_nofp_frame_init_saved_regs);
2903 set_gdbarch_breakpoint_from_pc (gdbarch, sh_sh64_breakpoint_from_pc);
2904 set_gdbarch_deprecated_call_dummy_words (gdbarch, sh64_call_dummy_words);
2905 set_gdbarch_deprecated_sizeof_call_dummy_words (gdbarch, sizeof (sh64_call_dummy_words));
2906
2907 set_gdbarch_deprecated_init_extra_frame_info (gdbarch, sh64_init_extra_frame_info);
2908 set_gdbarch_deprecated_frame_chain (gdbarch, sh64_frame_chain);
2909 set_gdbarch_deprecated_get_saved_register (gdbarch, sh64_get_saved_register);
2910 set_gdbarch_deprecated_extract_return_value (gdbarch, sh64_extract_return_value);
2911 set_gdbarch_deprecated_push_arguments (gdbarch, sh64_push_arguments);
2912 set_gdbarch_deprecated_push_return_address (gdbarch, sh64_push_return_address);
2913 set_gdbarch_deprecated_dummy_write_sp (gdbarch, deprecated_write_sp);
2914 set_gdbarch_deprecated_store_struct_return (gdbarch, sh64_store_struct_return);
2915 set_gdbarch_deprecated_extract_struct_value_address (gdbarch, sh64_extract_struct_value_address);
2916 set_gdbarch_use_struct_convention (gdbarch, sh64_use_struct_convention);
2917 set_gdbarch_deprecated_pop_frame (gdbarch, sh64_pop_frame);
2918 set_gdbarch_elf_make_msymbol_special (gdbarch,
2919 sh64_elf_make_msymbol_special);
2920
2921 /* Hook in ABI-specific overrides, if they have been registered. */
2922 gdbarch_init_osabi (info, gdbarch);
2923
2924 return gdbarch;
2925}
GDB Binutils - Deliverables
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