[deliverable/binutils-gdb.git] / gdb / sparc-nat.c

/* Functions specific to running gdb native on a SPARC running SunOS4.
   Copyright 1989, 1992, 1993, 1994, 1996 Free Software Foundation, Inc.

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 2 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program; if not, write to the Free Software
   Foundation, Inc., 59 Temple Place - Suite 330,
   Boston, MA 02111-1307, USA.  */

#include "defs.h"
#include "inferior.h"
#include "target.h"
#include "gdbcore.h"

#include <signal.h>
#include <sys/ptrace.h>
#include <sys/wait.h>
#ifdef __linux__
#include <asm/reg.h>
#else
#include <machine/reg.h>
#endif
#include <sys/user.h>

/* We don't store all registers immediately when requested, since they
   get sent over in large chunks anyway.  Instead, we accumulate most
   of the changes and send them over once.  "deferred_stores" keeps
   track of which sets of registers we have locally-changed copies of,
   so we only need send the groups that have changed.  */

#define	INT_REGS	1
#define	STACK_REGS	2
#define	FP_REGS		4

static void fetch_core_registers (char *, unsigned int, int, CORE_ADDR);

/* Fetch one or more registers from the inferior.  REGNO == -1 to get
   them all.  We actually fetch more than requested, when convenient,
   marking them as valid so we won't fetch them again.  */

void
fetch_inferior_registers (int regno)
{
  struct regs inferior_registers;
  struct fp_status inferior_fp_registers;
  int i;

  /* We should never be called with deferred stores, because a prerequisite
     for writing regs is to have fetched them all (PREPARE_TO_STORE), sigh.  */
  if (deferred_stores)
    abort ();

  DO_DEFERRED_STORES;

  /* Global and Out regs are fetched directly, as well as the control
     registers.  If we're getting one of the in or local regs,
     and the stack pointer has not yet been fetched,
     we have to do that first, since they're found in memory relative
     to the stack pointer.  */
  if (regno < O7_REGNUM		/* including -1 */
      || regno >= Y_REGNUM
      || (!register_valid[SP_REGNUM] && regno < I7_REGNUM))
    {
      if (0 != ptrace (PTRACE_GETREGS, inferior_pid,
		       (PTRACE_ARG3_TYPE) & inferior_registers, 0))
	perror ("ptrace_getregs");

      registers[REGISTER_BYTE (0)] = 0;
      memcpy (&registers[REGISTER_BYTE (1)], &inferior_registers.r_g1,
	      15 * REGISTER_RAW_SIZE (G0_REGNUM));
      *(int *) &registers[REGISTER_BYTE (PS_REGNUM)] = inferior_registers.r_ps;
      *(int *) &registers[REGISTER_BYTE (PC_REGNUM)] = inferior_registers.r_pc;
      *(int *) &registers[REGISTER_BYTE (NPC_REGNUM)] = inferior_registers.r_npc;
      *(int *) &registers[REGISTER_BYTE (Y_REGNUM)] = inferior_registers.r_y;

      for (i = G0_REGNUM; i <= O7_REGNUM; i++)
	register_valid[i] = 1;
      register_valid[Y_REGNUM] = 1;
      register_valid[PS_REGNUM] = 1;
      register_valid[PC_REGNUM] = 1;
      register_valid[NPC_REGNUM] = 1;
      /* If we don't set these valid, read_register_bytes() rereads
         all the regs every time it is called!  FIXME.  */
      register_valid[WIM_REGNUM] = 1;	/* Not true yet, FIXME */
      register_valid[TBR_REGNUM] = 1;	/* Not true yet, FIXME */
      register_valid[CPS_REGNUM] = 1;	/* Not true yet, FIXME */
    }

  /* Floating point registers */
  if (regno == -1 ||
      regno == FPS_REGNUM ||
      (regno >= FP0_REGNUM && regno <= FP0_REGNUM + 31))
    {
      if (0 != ptrace (PTRACE_GETFPREGS, inferior_pid,
		       (PTRACE_ARG3_TYPE) & inferior_fp_registers,
		       0))
	perror ("ptrace_getfpregs");
      memcpy (&registers[REGISTER_BYTE (FP0_REGNUM)], &inferior_fp_registers,
	      sizeof inferior_fp_registers.fpu_fr);
      memcpy (&registers[REGISTER_BYTE (FPS_REGNUM)],
	      &inferior_fp_registers.Fpu_fsr,
	      sizeof (FPU_FSR_TYPE));
      for (i = FP0_REGNUM; i <= FP0_REGNUM + 31; i++)
	register_valid[i] = 1;
      register_valid[FPS_REGNUM] = 1;
    }

  /* These regs are saved on the stack by the kernel.  Only read them
     all (16 ptrace calls!) if we really need them.  */
  if (regno == -1)
    {
      target_read_memory (*(CORE_ADDR *) & registers[REGISTER_BYTE (SP_REGNUM)],
			  &registers[REGISTER_BYTE (L0_REGNUM)],
			  16 * REGISTER_RAW_SIZE (L0_REGNUM));
      for (i = L0_REGNUM; i <= I7_REGNUM; i++)
	register_valid[i] = 1;
    }
  else if (regno >= L0_REGNUM && regno <= I7_REGNUM)
    {
      CORE_ADDR sp = *(CORE_ADDR *) & registers[REGISTER_BYTE (SP_REGNUM)];
      i = REGISTER_BYTE (regno);
      if (register_valid[regno])
	printf_unfiltered ("register %d valid and read\n", regno);
      target_read_memory (sp + i - REGISTER_BYTE (L0_REGNUM),
			  &registers[i], REGISTER_RAW_SIZE (regno));
      register_valid[regno] = 1;
    }
}

/* Store our register values back into the inferior.
   If REGNO is -1, do this for all registers.
   Otherwise, REGNO specifies which register (so we can save time).  */

void
store_inferior_registers (int regno)
{
  struct regs inferior_registers;
  struct fp_status inferior_fp_registers;
  int wanna_store = INT_REGS + STACK_REGS + FP_REGS;

  /* First decide which pieces of machine-state we need to modify.  
     Default for regno == -1 case is all pieces.  */
  if (regno >= 0)
    if (FP0_REGNUM <= regno && regno < FP0_REGNUM + 32)
      {
	wanna_store = FP_REGS;
      }
    else
      {
	if (regno == SP_REGNUM)
	  wanna_store = INT_REGS + STACK_REGS;
	else if (regno < L0_REGNUM || regno > I7_REGNUM)
	  wanna_store = INT_REGS;
	else if (regno == FPS_REGNUM)
	  wanna_store = FP_REGS;
	else
	  wanna_store = STACK_REGS;
      }

  /* See if we're forcing the stores to happen now, or deferring. */
  if (regno == -2)
    {
      wanna_store = deferred_stores;
      deferred_stores = 0;
    }
  else
    {
      if (wanna_store == STACK_REGS)
	{
	  /* Fall through and just store one stack reg.  If we deferred
	     it, we'd have to store them all, or remember more info.  */
	}
      else
	{
	  deferred_stores |= wanna_store;
	  return;
	}
    }

  if (wanna_store & STACK_REGS)
    {
      CORE_ADDR sp = *(CORE_ADDR *) & registers[REGISTER_BYTE (SP_REGNUM)];

      if (regno < 0 || regno == SP_REGNUM)
	{
	  if (!register_valid[L0_REGNUM + 5])
	    abort ();
	  target_write_memory (sp,
			       &registers[REGISTER_BYTE (L0_REGNUM)],
			       16 * REGISTER_RAW_SIZE (L0_REGNUM));
	}
      else
	{
	  if (!register_valid[regno])
	    abort ();
	  target_write_memory (sp + REGISTER_BYTE (regno) - REGISTER_BYTE (L0_REGNUM),
			       &registers[REGISTER_BYTE (regno)],
			       REGISTER_RAW_SIZE (regno));
	}

    }

  if (wanna_store & INT_REGS)
    {
      if (!register_valid[G1_REGNUM])
	abort ();

      memcpy (&inferior_registers.r_g1, &registers[REGISTER_BYTE (G1_REGNUM)],
	      15 * REGISTER_RAW_SIZE (G1_REGNUM));

      inferior_registers.r_ps =
	*(int *) &registers[REGISTER_BYTE (PS_REGNUM)];
      inferior_registers.r_pc =
	*(int *) &registers[REGISTER_BYTE (PC_REGNUM)];
      inferior_registers.r_npc =
	*(int *) &registers[REGISTER_BYTE (NPC_REGNUM)];
      inferior_registers.r_y =
	*(int *) &registers[REGISTER_BYTE (Y_REGNUM)];

      if (0 != ptrace (PTRACE_SETREGS, inferior_pid,
		       (PTRACE_ARG3_TYPE) & inferior_registers, 0))
	perror ("ptrace_setregs");
    }

  if (wanna_store & FP_REGS)
    {
      if (!register_valid[FP0_REGNUM + 9])
	abort ();
      memcpy (&inferior_fp_registers, &registers[REGISTER_BYTE (FP0_REGNUM)],
	      sizeof inferior_fp_registers.fpu_fr);
      memcpy (&inferior_fp_registers.Fpu_fsr,
	      &registers[REGISTER_BYTE (FPS_REGNUM)], sizeof (FPU_FSR_TYPE));
      if (0 !=
	  ptrace (PTRACE_SETFPREGS, inferior_pid,
		  (PTRACE_ARG3_TYPE) & inferior_fp_registers, 0))
	perror ("ptrace_setfpregs");
    }
}


static void
fetch_core_registers (core_reg_sect, core_reg_size, which, ignore)
     char *core_reg_sect;
     unsigned core_reg_size;
     int which;
     CORE_ADDR ignore;		/* reg addr, unused in this version */
{

  if (which == 0)
    {

      /* Integer registers */

#define gregs ((struct regs *)core_reg_sect)
      /* G0 *always* holds 0.  */
      *(int *) &registers[REGISTER_BYTE (0)] = 0;

      /* The globals and output registers.  */
      memcpy (&registers[REGISTER_BYTE (G1_REGNUM)], &gregs->r_g1,
	      15 * REGISTER_RAW_SIZE (G1_REGNUM));
      *(int *) &registers[REGISTER_BYTE (PS_REGNUM)] = gregs->r_ps;
      *(int *) &registers[REGISTER_BYTE (PC_REGNUM)] = gregs->r_pc;
      *(int *) &registers[REGISTER_BYTE (NPC_REGNUM)] = gregs->r_npc;
      *(int *) &registers[REGISTER_BYTE (Y_REGNUM)] = gregs->r_y;

      /* My best guess at where to get the locals and input
         registers is exactly where they usually are, right above
         the stack pointer.  If the core dump was caused by a bus error
         from blowing away the stack pointer (as is possible) then this
         won't work, but it's worth the try. */
      {
	int sp;

	sp = *(int *) &registers[REGISTER_BYTE (SP_REGNUM)];
	if (0 != target_read_memory (sp, &registers[REGISTER_BYTE (L0_REGNUM)],
				     16 * REGISTER_RAW_SIZE (L0_REGNUM)))
	  {
	    /* fprintf_unfiltered so user can still use gdb */
	    fprintf_unfiltered (gdb_stderr,
		"Couldn't read input and local registers from core file\n");
	  }
      }
    }
  else if (which == 2)
    {

      /* Floating point registers */

#define fpuregs  ((struct fpu *) core_reg_sect)
      if (core_reg_size >= sizeof (struct fpu))
	{
	  memcpy (&registers[REGISTER_BYTE (FP0_REGNUM)], fpuregs->fpu_regs,
		  sizeof (fpuregs->fpu_regs));
	  memcpy (&registers[REGISTER_BYTE (FPS_REGNUM)], &fpuregs->fpu_fsr,
		  sizeof (FPU_FSR_TYPE));
	}
      else
	fprintf_unfiltered (gdb_stderr, "Couldn't read float regs from core file\n");
    }
}

int
kernel_u_size (void)
{
  return (sizeof (struct user));
}
\f

/* Register that we are able to handle sparc core file formats.
   FIXME: is this really bfd_target_unknown_flavour? */

static struct core_fns sparc_core_fns =
{
  bfd_target_unknown_flavour,		/* core_flavour */
  default_check_format,			/* check_format */
  default_core_sniffer,			/* core_sniffer */
  fetch_core_registers,			/* core_read_registers */
  NULL					/* next */
};

void
_initialize_core_sparc (void)
{
  add_core_fns (&sparc_core_fns);
}
Commit	Line	Data
c906108c SS	1	/* Functions specific to running gdb native on a SPARC running SunOS4.
	2	Copyright 1989, 1992, 1993, 1994, 1996 Free Software Foundation, Inc.
	3
c5aa993b	4	This file is part of GDB.
c906108c	5
c5aa993b JM	6	This program is free software; you can redistribute it and/or modify
	7	it under the terms of the GNU General Public License as published by
	8	the Free Software Foundation; either version 2 of the License, or
	9	(at your option) any later version.
c906108c	10
c5aa993b JM	11	This program is distributed in the hope that it will be useful,
	12	but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	GNU General Public License for more details.
c906108c	15
c5aa993b JM	16	You should have received a copy of the GNU General Public License
	17	along with this program; if not, write to the Free Software
	18	Foundation, Inc., 59 Temple Place - Suite 330,
	19	Boston, MA 02111-1307, USA. */
c906108c SS	20
	21	#include "defs.h"
	22	#include "inferior.h"
	23	#include "target.h"
	24	#include "gdbcore.h"
	25
	26	#include <signal.h>
	27	#include <sys/ptrace.h>
	28	#include <sys/wait.h>
	29	#ifdef __linux__
	30	#include <asm/reg.h>
	31	#else
	32	#include <machine/reg.h>
	33	#endif
	34	#include <sys/user.h>
	35
	36	/* We don't store all registers immediately when requested, since they
	37	get sent over in large chunks anyway. Instead, we accumulate most
	38	of the changes and send them over once. "deferred_stores" keeps
	39	track of which sets of registers we have locally-changed copies of,
	40	so we only need send the groups that have changed. */
	41
	42	#define INT_REGS 1
	43	#define STACK_REGS 2
	44	#define FP_REGS 4
	45
a14ed312	46	static void fetch_core_registers (char *, unsigned int, int, CORE_ADDR);
c906108c SS	47
	48	/* Fetch one or more registers from the inferior. REGNO == -1 to get
	49	them all. We actually fetch more than requested, when convenient,
	50	marking them as valid so we won't fetch them again. */
	51
	52	void
fba45db2	53	fetch_inferior_registers (int regno)
c906108c SS	54	{
	55	struct regs inferior_registers;
	56	struct fp_status inferior_fp_registers;
	57	int i;
	58
	59	/* We should never be called with deferred stores, because a prerequisite
	60	for writing regs is to have fetched them all (PREPARE_TO_STORE), sigh. */
c5aa993b JM	61	if (deferred_stores)
c5aa993b JM	62	abort ();
c906108c SS	63
	64	DO_DEFERRED_STORES;
	65
	66	/* Global and Out regs are fetched directly, as well as the control
	67	registers. If we're getting one of the in or local regs,
	68	and the stack pointer has not yet been fetched,
	69	we have to do that first, since they're found in memory relative
	70	to the stack pointer. */
c5aa993b	71	if (regno < O7_REGNUM /* including -1 */
c906108c SS	72	\|\| regno >= Y_REGNUM
	73	\|\| (!register_valid[SP_REGNUM] && regno < I7_REGNUM))
	74	{
	75	if (0 != ptrace (PTRACE_GETREGS, inferior_pid,
c5aa993b JM	76	(PTRACE_ARG3_TYPE) & inferior_registers, 0))
	77	perror ("ptrace_getregs");
	78
c906108c SS	79	registers[REGISTER_BYTE (0)] = 0;
	80	memcpy (&registers[REGISTER_BYTE (1)], &inferior_registers.r_g1,
	81	15 * REGISTER_RAW_SIZE (G0_REGNUM));
c5aa993b JM	82	(int ) &registers[REGISTER_BYTE (PS_REGNUM)] = inferior_registers.r_ps;
	83	(int ) &registers[REGISTER_BYTE (PC_REGNUM)] = inferior_registers.r_pc;
	84	(int ) &registers[REGISTER_BYTE (NPC_REGNUM)] = inferior_registers.r_npc;
	85	(int ) &registers[REGISTER_BYTE (Y_REGNUM)] = inferior_registers.r_y;
c906108c SS	86
	87	for (i = G0_REGNUM; i <= O7_REGNUM; i++)
	88	register_valid[i] = 1;
	89	register_valid[Y_REGNUM] = 1;
	90	register_valid[PS_REGNUM] = 1;
	91	register_valid[PC_REGNUM] = 1;
	92	register_valid[NPC_REGNUM] = 1;
	93	/* If we don't set these valid, read_register_bytes() rereads
c5aa993b	94	all the regs every time it is called! FIXME. */
c906108c SS	95	register_valid[WIM_REGNUM] = 1; /* Not true yet, FIXME */
	96	register_valid[TBR_REGNUM] = 1; /* Not true yet, FIXME */
	97	register_valid[CPS_REGNUM] = 1; /* Not true yet, FIXME */
	98	}
	99
	100	/* Floating point registers */
	101	if (regno == -1 \|\|
	102	regno == FPS_REGNUM \|\|
	103	(regno >= FP0_REGNUM && regno <= FP0_REGNUM + 31))
	104	{
	105	if (0 != ptrace (PTRACE_GETFPREGS, inferior_pid,
c5aa993b	106	(PTRACE_ARG3_TYPE) & inferior_fp_registers,
c906108c	107	0))
c5aa993b	108	perror ("ptrace_getfpregs");
c906108c SS	109	memcpy (&registers[REGISTER_BYTE (FP0_REGNUM)], &inferior_fp_registers,
	110	sizeof inferior_fp_registers.fpu_fr);
	111	memcpy (&registers[REGISTER_BYTE (FPS_REGNUM)],
c5aa993b JM	112	&inferior_fp_registers.Fpu_fsr,
	113	sizeof (FPU_FSR_TYPE));
	114	for (i = FP0_REGNUM; i <= FP0_REGNUM + 31; i++)
c906108c SS	115	register_valid[i] = 1;
	116	register_valid[FPS_REGNUM] = 1;
	117	}
	118
	119	/* These regs are saved on the stack by the kernel. Only read them
	120	all (16 ptrace calls!) if we really need them. */
	121	if (regno == -1)
	122	{
c5aa993b JM	123	target_read_memory ((CORE_ADDR ) & registers[REGISTER_BYTE (SP_REGNUM)],
	124	&registers[REGISTER_BYTE (L0_REGNUM)],
	125	16 * REGISTER_RAW_SIZE (L0_REGNUM));
c906108c SS	126	for (i = L0_REGNUM; i <= I7_REGNUM; i++)
	127	register_valid[i] = 1;
	128	}
	129	else if (regno >= L0_REGNUM && regno <= I7_REGNUM)
	130	{
c5aa993b	131	CORE_ADDR sp = (CORE_ADDR ) & registers[REGISTER_BYTE (SP_REGNUM)];
c906108c SS	132	i = REGISTER_BYTE (regno);
c906108c SS	133	if (register_valid[regno])
c5aa993b	134	printf_unfiltered ("register %d valid and read\n", regno);
c906108c SS	135	target_read_memory (sp + i - REGISTER_BYTE (L0_REGNUM),
	136	&registers[i], REGISTER_RAW_SIZE (regno));
	137	register_valid[regno] = 1;
	138	}
	139	}
	140
	141	/* Store our register values back into the inferior.
	142	If REGNO is -1, do this for all registers.
	143	Otherwise, REGNO specifies which register (so we can save time). */
	144
	145	void
fba45db2	146	store_inferior_registers (int regno)
c906108c SS	147	{
	148	struct regs inferior_registers;
	149	struct fp_status inferior_fp_registers;
	150	int wanna_store = INT_REGS + STACK_REGS + FP_REGS;
	151
	152	/* First decide which pieces of machine-state we need to modify.
	153	Default for regno == -1 case is all pieces. */
	154	if (regno >= 0)
	155	if (FP0_REGNUM <= regno && regno < FP0_REGNUM + 32)
	156	{
	157	wanna_store = FP_REGS;
	158	}
c5aa993b	159	else
c906108c SS	160	{
	161	if (regno == SP_REGNUM)
	162	wanna_store = INT_REGS + STACK_REGS;
	163	else if (regno < L0_REGNUM \|\| regno > I7_REGNUM)
	164	wanna_store = INT_REGS;
	165	else if (regno == FPS_REGNUM)
	166	wanna_store = FP_REGS;
	167	else
	168	wanna_store = STACK_REGS;
	169	}
	170
	171	/* See if we're forcing the stores to happen now, or deferring. */
	172	if (regno == -2)
	173	{
	174	wanna_store = deferred_stores;
	175	deferred_stores = 0;
	176	}
	177	else
	178	{
	179	if (wanna_store == STACK_REGS)
	180	{
	181	/* Fall through and just store one stack reg. If we deferred
	182	it, we'd have to store them all, or remember more info. */
	183	}
	184	else
	185	{
	186	deferred_stores \|= wanna_store;
	187	return;
	188	}
	189	}
	190
	191	if (wanna_store & STACK_REGS)
	192	{
c5aa993b	193	CORE_ADDR sp = (CORE_ADDR ) & registers[REGISTER_BYTE (SP_REGNUM)];
c906108c SS	194
	195	if (regno < 0 \|\| regno == SP_REGNUM)
	196	{
c5aa993b JM	197	if (!register_valid[L0_REGNUM + 5])
	198	abort ();
	199	target_write_memory (sp,
c906108c	200	&registers[REGISTER_BYTE (L0_REGNUM)],
c5aa993b	201	16 * REGISTER_RAW_SIZE (L0_REGNUM));
c906108c SS	202	}
	203	else
	204	{
c5aa993b JM	205	if (!register_valid[regno])
c5aa993b JM	206	abort ();
c906108c SS	207	target_write_memory (sp + REGISTER_BYTE (regno) - REGISTER_BYTE (L0_REGNUM),
	208	&registers[REGISTER_BYTE (regno)],
	209	REGISTER_RAW_SIZE (regno));
	210	}
c5aa993b	211
c906108c SS	212	}
	213
	214	if (wanna_store & INT_REGS)
	215	{
c5aa993b JM	216	if (!register_valid[G1_REGNUM])
c5aa993b JM	217	abort ();
c906108c SS	218
	219	memcpy (&inferior_registers.r_g1, &registers[REGISTER_BYTE (G1_REGNUM)],
	220	15 * REGISTER_RAW_SIZE (G1_REGNUM));
	221
	222	inferior_registers.r_ps =
c5aa993b	223	(int ) &registers[REGISTER_BYTE (PS_REGNUM)];
c906108c	224	inferior_registers.r_pc =
c5aa993b	225	(int ) &registers[REGISTER_BYTE (PC_REGNUM)];
c906108c	226	inferior_registers.r_npc =
c5aa993b	227	(int ) &registers[REGISTER_BYTE (NPC_REGNUM)];
c906108c	228	inferior_registers.r_y =
c5aa993b	229	(int ) &registers[REGISTER_BYTE (Y_REGNUM)];
c906108c SS	230
c906108c SS	231	if (0 != ptrace (PTRACE_SETREGS, inferior_pid,
c5aa993b JM	232	(PTRACE_ARG3_TYPE) & inferior_registers, 0))
c5aa993b JM	233	perror ("ptrace_setregs");
c906108c SS	234	}
	235
	236	if (wanna_store & FP_REGS)
	237	{
c5aa993b JM	238	if (!register_valid[FP0_REGNUM + 9])
c5aa993b JM	239	abort ();
c906108c SS	240	memcpy (&inferior_fp_registers, &registers[REGISTER_BYTE (FP0_REGNUM)],
c906108c SS	241	sizeof inferior_fp_registers.fpu_fr);
c5aa993b	242	memcpy (&inferior_fp_registers.Fpu_fsr,
c906108c SS	243	&registers[REGISTER_BYTE (FPS_REGNUM)], sizeof (FPU_FSR_TYPE));
c906108c SS	244	if (0 !=
c5aa993b JM	245	ptrace (PTRACE_SETFPREGS, inferior_pid,
	246	(PTRACE_ARG3_TYPE) & inferior_fp_registers, 0))
	247	perror ("ptrace_setfpregs");
c906108c SS	248	}
	249	}
	250
	251
	252	static void
	253	fetch_core_registers (core_reg_sect, core_reg_size, which, ignore)
c5aa993b JM	254	char *core_reg_sect;
	255	unsigned core_reg_size;
	256	int which;
	257	CORE_ADDR ignore; /* reg addr, unused in this version */
c906108c SS	258	{
c906108c SS	259
c5aa993b JM	260	if (which == 0)
c5aa993b JM	261	{
c906108c	262
c5aa993b	263	/* Integer registers */
c906108c SS	264
c906108c SS	265	#define gregs ((struct regs *)core_reg_sect)
c5aa993b JM	266	/* G0 always holds 0. */
c5aa993b JM	267	(int ) &registers[REGISTER_BYTE (0)] = 0;
c906108c	268
c5aa993b JM	269	/* The globals and output registers. */
	270	memcpy (&registers[REGISTER_BYTE (G1_REGNUM)], &gregs->r_g1,
	271	15 * REGISTER_RAW_SIZE (G1_REGNUM));
	272	(int ) &registers[REGISTER_BYTE (PS_REGNUM)] = gregs->r_ps;
	273	(int ) &registers[REGISTER_BYTE (PC_REGNUM)] = gregs->r_pc;
	274	(int ) &registers[REGISTER_BYTE (NPC_REGNUM)] = gregs->r_npc;
	275	(int ) &registers[REGISTER_BYTE (Y_REGNUM)] = gregs->r_y;
	276
	277	/* My best guess at where to get the locals and input
	278	registers is exactly where they usually are, right above
	279	the stack pointer. If the core dump was caused by a bus error
	280	from blowing away the stack pointer (as is possible) then this
	281	won't work, but it's worth the try. */
	282	{
	283	int sp;
	284
	285	sp = (int ) &registers[REGISTER_BYTE (SP_REGNUM)];
	286	if (0 != target_read_memory (sp, &registers[REGISTER_BYTE (L0_REGNUM)],
	287	16 * REGISTER_RAW_SIZE (L0_REGNUM)))
	288	{
	289	/* fprintf_unfiltered so user can still use gdb */
	290	fprintf_unfiltered (gdb_stderr,
	291	"Couldn't read input and local registers from core file\n");
	292	}
	293	}
c906108c	294	}
c5aa993b JM	295	else if (which == 2)
c5aa993b JM	296	{
c906108c	297
c5aa993b	298	/* Floating point registers */
c906108c SS	299
c906108c SS	300	#define fpuregs ((struct fpu *) core_reg_sect)
c5aa993b JM	301	if (core_reg_size >= sizeof (struct fpu))
	302	{
	303	memcpy (&registers[REGISTER_BYTE (FP0_REGNUM)], fpuregs->fpu_regs,
	304	sizeof (fpuregs->fpu_regs));
	305	memcpy (&registers[REGISTER_BYTE (FPS_REGNUM)], &fpuregs->fpu_fsr,
	306	sizeof (FPU_FSR_TYPE));
	307	}
	308	else
	309	fprintf_unfiltered (gdb_stderr, "Couldn't read float regs from core file\n");
	310	}
c906108c SS	311	}
	312
	313	int
fba45db2	314	kernel_u_size (void)
c906108c SS	315	{
	316	return (sizeof (struct user));
	317	}
c906108c	318	\f
c5aa993b	319
c906108c SS	320	/* Register that we are able to handle sparc core file formats.
	321	FIXME: is this really bfd_target_unknown_flavour? */
	322
	323	static struct core_fns sparc_core_fns =
	324	{
2acceee2 JM	325	bfd_target_unknown_flavour, /* core_flavour */
	326	default_check_format, /* check_format */
	327	default_core_sniffer, /* core_sniffer */
	328	fetch_core_registers, /* core_read_registers */
	329	NULL /* next */
c906108c SS	330	};
	331
	332	void
fba45db2	333	_initialize_core_sparc (void)
c906108c SS	334	{
	335	add_core_fns (&sparc_core_fns);
	336	}