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c906108c | 1 | /* Functions specific to running gdb native on a SPARC running SunOS4. |
4e052eda AC |
2 | Copyright 1989, 1992, 1993, 1994, 1996, 2001 Free Software |
3 | Foundation, Inc. | |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b JM |
17 | You should have received a copy of the GNU General Public License |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
21 | |
22 | #include "defs.h" | |
23 | #include "inferior.h" | |
24 | #include "target.h" | |
25 | #include "gdbcore.h" | |
4e052eda AC |
26 | #include "sparc-nat.c" |
27 | #include "regcache.h" | |
c906108c SS |
28 | |
29 | #include <signal.h> | |
30 | #include <sys/ptrace.h> | |
31 | #include <sys/wait.h> | |
32 | #ifdef __linux__ | |
33 | #include <asm/reg.h> | |
34 | #else | |
35 | #include <machine/reg.h> | |
36 | #endif | |
37 | #include <sys/user.h> | |
38 | ||
39 | /* We don't store all registers immediately when requested, since they | |
40 | get sent over in large chunks anyway. Instead, we accumulate most | |
41 | of the changes and send them over once. "deferred_stores" keeps | |
42 | track of which sets of registers we have locally-changed copies of, | |
43 | so we only need send the groups that have changed. */ | |
44 | ||
45 | #define INT_REGS 1 | |
46 | #define STACK_REGS 2 | |
47 | #define FP_REGS 4 | |
48 | ||
a14ed312 | 49 | static void fetch_core_registers (char *, unsigned int, int, CORE_ADDR); |
c906108c SS |
50 | |
51 | /* Fetch one or more registers from the inferior. REGNO == -1 to get | |
52 | them all. We actually fetch more than requested, when convenient, | |
53 | marking them as valid so we won't fetch them again. */ | |
54 | ||
55 | void | |
fba45db2 | 56 | fetch_inferior_registers (int regno) |
c906108c SS |
57 | { |
58 | struct regs inferior_registers; | |
59 | struct fp_status inferior_fp_registers; | |
60 | int i; | |
61 | ||
62 | /* We should never be called with deferred stores, because a prerequisite | |
63 | for writing regs is to have fetched them all (PREPARE_TO_STORE), sigh. */ | |
c5aa993b | 64 | if (deferred_stores) |
e1e9e218 | 65 | internal_error (__FILE__, __LINE__, "failed internal consistency check"); |
c906108c SS |
66 | |
67 | DO_DEFERRED_STORES; | |
68 | ||
69 | /* Global and Out regs are fetched directly, as well as the control | |
70 | registers. If we're getting one of the in or local regs, | |
71 | and the stack pointer has not yet been fetched, | |
72 | we have to do that first, since they're found in memory relative | |
73 | to the stack pointer. */ | |
c5aa993b | 74 | if (regno < O7_REGNUM /* including -1 */ |
c906108c SS |
75 | || regno >= Y_REGNUM |
76 | || (!register_valid[SP_REGNUM] && regno < I7_REGNUM)) | |
77 | { | |
78 | if (0 != ptrace (PTRACE_GETREGS, inferior_pid, | |
c5aa993b JM |
79 | (PTRACE_ARG3_TYPE) & inferior_registers, 0)) |
80 | perror ("ptrace_getregs"); | |
81 | ||
c906108c SS |
82 | registers[REGISTER_BYTE (0)] = 0; |
83 | memcpy (®isters[REGISTER_BYTE (1)], &inferior_registers.r_g1, | |
84 | 15 * REGISTER_RAW_SIZE (G0_REGNUM)); | |
c5aa993b JM |
85 | *(int *) ®isters[REGISTER_BYTE (PS_REGNUM)] = inferior_registers.r_ps; |
86 | *(int *) ®isters[REGISTER_BYTE (PC_REGNUM)] = inferior_registers.r_pc; | |
87 | *(int *) ®isters[REGISTER_BYTE (NPC_REGNUM)] = inferior_registers.r_npc; | |
88 | *(int *) ®isters[REGISTER_BYTE (Y_REGNUM)] = inferior_registers.r_y; | |
c906108c SS |
89 | |
90 | for (i = G0_REGNUM; i <= O7_REGNUM; i++) | |
91 | register_valid[i] = 1; | |
92 | register_valid[Y_REGNUM] = 1; | |
93 | register_valid[PS_REGNUM] = 1; | |
94 | register_valid[PC_REGNUM] = 1; | |
95 | register_valid[NPC_REGNUM] = 1; | |
96 | /* If we don't set these valid, read_register_bytes() rereads | |
c5aa993b | 97 | all the regs every time it is called! FIXME. */ |
c906108c SS |
98 | register_valid[WIM_REGNUM] = 1; /* Not true yet, FIXME */ |
99 | register_valid[TBR_REGNUM] = 1; /* Not true yet, FIXME */ | |
100 | register_valid[CPS_REGNUM] = 1; /* Not true yet, FIXME */ | |
101 | } | |
102 | ||
103 | /* Floating point registers */ | |
104 | if (regno == -1 || | |
105 | regno == FPS_REGNUM || | |
106 | (regno >= FP0_REGNUM && regno <= FP0_REGNUM + 31)) | |
107 | { | |
108 | if (0 != ptrace (PTRACE_GETFPREGS, inferior_pid, | |
c5aa993b | 109 | (PTRACE_ARG3_TYPE) & inferior_fp_registers, |
c906108c | 110 | 0)) |
c5aa993b | 111 | perror ("ptrace_getfpregs"); |
c906108c SS |
112 | memcpy (®isters[REGISTER_BYTE (FP0_REGNUM)], &inferior_fp_registers, |
113 | sizeof inferior_fp_registers.fpu_fr); | |
114 | memcpy (®isters[REGISTER_BYTE (FPS_REGNUM)], | |
c5aa993b JM |
115 | &inferior_fp_registers.Fpu_fsr, |
116 | sizeof (FPU_FSR_TYPE)); | |
117 | for (i = FP0_REGNUM; i <= FP0_REGNUM + 31; i++) | |
c906108c SS |
118 | register_valid[i] = 1; |
119 | register_valid[FPS_REGNUM] = 1; | |
120 | } | |
121 | ||
122 | /* These regs are saved on the stack by the kernel. Only read them | |
123 | all (16 ptrace calls!) if we really need them. */ | |
124 | if (regno == -1) | |
125 | { | |
c5aa993b JM |
126 | target_read_memory (*(CORE_ADDR *) & registers[REGISTER_BYTE (SP_REGNUM)], |
127 | ®isters[REGISTER_BYTE (L0_REGNUM)], | |
128 | 16 * REGISTER_RAW_SIZE (L0_REGNUM)); | |
c906108c SS |
129 | for (i = L0_REGNUM; i <= I7_REGNUM; i++) |
130 | register_valid[i] = 1; | |
131 | } | |
132 | else if (regno >= L0_REGNUM && regno <= I7_REGNUM) | |
133 | { | |
c5aa993b | 134 | CORE_ADDR sp = *(CORE_ADDR *) & registers[REGISTER_BYTE (SP_REGNUM)]; |
c906108c SS |
135 | i = REGISTER_BYTE (regno); |
136 | if (register_valid[regno]) | |
c5aa993b | 137 | printf_unfiltered ("register %d valid and read\n", regno); |
c906108c SS |
138 | target_read_memory (sp + i - REGISTER_BYTE (L0_REGNUM), |
139 | ®isters[i], REGISTER_RAW_SIZE (regno)); | |
140 | register_valid[regno] = 1; | |
141 | } | |
142 | } | |
143 | ||
144 | /* Store our register values back into the inferior. | |
145 | If REGNO is -1, do this for all registers. | |
146 | Otherwise, REGNO specifies which register (so we can save time). */ | |
147 | ||
148 | void | |
fba45db2 | 149 | store_inferior_registers (int regno) |
c906108c SS |
150 | { |
151 | struct regs inferior_registers; | |
152 | struct fp_status inferior_fp_registers; | |
153 | int wanna_store = INT_REGS + STACK_REGS + FP_REGS; | |
154 | ||
155 | /* First decide which pieces of machine-state we need to modify. | |
156 | Default for regno == -1 case is all pieces. */ | |
157 | if (regno >= 0) | |
158 | if (FP0_REGNUM <= regno && regno < FP0_REGNUM + 32) | |
159 | { | |
160 | wanna_store = FP_REGS; | |
161 | } | |
c5aa993b | 162 | else |
c906108c SS |
163 | { |
164 | if (regno == SP_REGNUM) | |
165 | wanna_store = INT_REGS + STACK_REGS; | |
166 | else if (regno < L0_REGNUM || regno > I7_REGNUM) | |
167 | wanna_store = INT_REGS; | |
168 | else if (regno == FPS_REGNUM) | |
169 | wanna_store = FP_REGS; | |
170 | else | |
171 | wanna_store = STACK_REGS; | |
172 | } | |
173 | ||
174 | /* See if we're forcing the stores to happen now, or deferring. */ | |
175 | if (regno == -2) | |
176 | { | |
177 | wanna_store = deferred_stores; | |
178 | deferred_stores = 0; | |
179 | } | |
180 | else | |
181 | { | |
182 | if (wanna_store == STACK_REGS) | |
183 | { | |
184 | /* Fall through and just store one stack reg. If we deferred | |
185 | it, we'd have to store them all, or remember more info. */ | |
186 | } | |
187 | else | |
188 | { | |
189 | deferred_stores |= wanna_store; | |
190 | return; | |
191 | } | |
192 | } | |
193 | ||
194 | if (wanna_store & STACK_REGS) | |
195 | { | |
c5aa993b | 196 | CORE_ADDR sp = *(CORE_ADDR *) & registers[REGISTER_BYTE (SP_REGNUM)]; |
c906108c SS |
197 | |
198 | if (regno < 0 || regno == SP_REGNUM) | |
199 | { | |
c5aa993b | 200 | if (!register_valid[L0_REGNUM + 5]) |
e1e9e218 | 201 | internal_error (__FILE__, __LINE__, "failed internal consistency check"); |
c5aa993b | 202 | target_write_memory (sp, |
c906108c | 203 | ®isters[REGISTER_BYTE (L0_REGNUM)], |
c5aa993b | 204 | 16 * REGISTER_RAW_SIZE (L0_REGNUM)); |
c906108c SS |
205 | } |
206 | else | |
207 | { | |
c5aa993b | 208 | if (!register_valid[regno]) |
e1e9e218 | 209 | internal_error (__FILE__, __LINE__, "failed internal consistency check"); |
c906108c SS |
210 | target_write_memory (sp + REGISTER_BYTE (regno) - REGISTER_BYTE (L0_REGNUM), |
211 | ®isters[REGISTER_BYTE (regno)], | |
212 | REGISTER_RAW_SIZE (regno)); | |
213 | } | |
c5aa993b | 214 | |
c906108c SS |
215 | } |
216 | ||
217 | if (wanna_store & INT_REGS) | |
218 | { | |
c5aa993b | 219 | if (!register_valid[G1_REGNUM]) |
e1e9e218 | 220 | internal_error (__FILE__, __LINE__, "failed internal consistency check"); |
c906108c SS |
221 | |
222 | memcpy (&inferior_registers.r_g1, ®isters[REGISTER_BYTE (G1_REGNUM)], | |
223 | 15 * REGISTER_RAW_SIZE (G1_REGNUM)); | |
224 | ||
225 | inferior_registers.r_ps = | |
c5aa993b | 226 | *(int *) ®isters[REGISTER_BYTE (PS_REGNUM)]; |
c906108c | 227 | inferior_registers.r_pc = |
c5aa993b | 228 | *(int *) ®isters[REGISTER_BYTE (PC_REGNUM)]; |
c906108c | 229 | inferior_registers.r_npc = |
c5aa993b | 230 | *(int *) ®isters[REGISTER_BYTE (NPC_REGNUM)]; |
c906108c | 231 | inferior_registers.r_y = |
c5aa993b | 232 | *(int *) ®isters[REGISTER_BYTE (Y_REGNUM)]; |
c906108c SS |
233 | |
234 | if (0 != ptrace (PTRACE_SETREGS, inferior_pid, | |
c5aa993b JM |
235 | (PTRACE_ARG3_TYPE) & inferior_registers, 0)) |
236 | perror ("ptrace_setregs"); | |
c906108c SS |
237 | } |
238 | ||
239 | if (wanna_store & FP_REGS) | |
240 | { | |
c5aa993b | 241 | if (!register_valid[FP0_REGNUM + 9]) |
e1e9e218 | 242 | internal_error (__FILE__, __LINE__, "failed internal consistency check"); |
c906108c SS |
243 | memcpy (&inferior_fp_registers, ®isters[REGISTER_BYTE (FP0_REGNUM)], |
244 | sizeof inferior_fp_registers.fpu_fr); | |
c5aa993b | 245 | memcpy (&inferior_fp_registers.Fpu_fsr, |
c906108c SS |
246 | ®isters[REGISTER_BYTE (FPS_REGNUM)], sizeof (FPU_FSR_TYPE)); |
247 | if (0 != | |
c5aa993b JM |
248 | ptrace (PTRACE_SETFPREGS, inferior_pid, |
249 | (PTRACE_ARG3_TYPE) & inferior_fp_registers, 0)) | |
250 | perror ("ptrace_setfpregs"); | |
c906108c SS |
251 | } |
252 | } | |
253 | ||
c67b4c45 KB |
254 | /* Provide registers to GDB from a core file. |
255 | ||
256 | CORE_REG_SECT points to an array of bytes, which are the contents | |
257 | of a `note' from a core file which BFD thinks might contain | |
258 | register contents. CORE_REG_SIZE is its size. | |
259 | ||
260 | WHICH says which register set corelow suspects this is: | |
261 | 0 --- the general-purpose register set | |
262 | 2 --- the floating-point register set | |
263 | ||
264 | IGNORE is unused. */ | |
c906108c SS |
265 | |
266 | static void | |
c67b4c45 KB |
267 | fetch_core_registers (char *core_reg_sect, unsigned core_reg_size, |
268 | int which, CORE_ADDR ignore) | |
c906108c SS |
269 | { |
270 | ||
c5aa993b JM |
271 | if (which == 0) |
272 | { | |
c906108c | 273 | |
c5aa993b | 274 | /* Integer registers */ |
c906108c SS |
275 | |
276 | #define gregs ((struct regs *)core_reg_sect) | |
c5aa993b JM |
277 | /* G0 *always* holds 0. */ |
278 | *(int *) ®isters[REGISTER_BYTE (0)] = 0; | |
c906108c | 279 | |
c5aa993b JM |
280 | /* The globals and output registers. */ |
281 | memcpy (®isters[REGISTER_BYTE (G1_REGNUM)], &gregs->r_g1, | |
282 | 15 * REGISTER_RAW_SIZE (G1_REGNUM)); | |
283 | *(int *) ®isters[REGISTER_BYTE (PS_REGNUM)] = gregs->r_ps; | |
284 | *(int *) ®isters[REGISTER_BYTE (PC_REGNUM)] = gregs->r_pc; | |
285 | *(int *) ®isters[REGISTER_BYTE (NPC_REGNUM)] = gregs->r_npc; | |
286 | *(int *) ®isters[REGISTER_BYTE (Y_REGNUM)] = gregs->r_y; | |
287 | ||
288 | /* My best guess at where to get the locals and input | |
289 | registers is exactly where they usually are, right above | |
290 | the stack pointer. If the core dump was caused by a bus error | |
291 | from blowing away the stack pointer (as is possible) then this | |
292 | won't work, but it's worth the try. */ | |
293 | { | |
294 | int sp; | |
295 | ||
296 | sp = *(int *) ®isters[REGISTER_BYTE (SP_REGNUM)]; | |
297 | if (0 != target_read_memory (sp, ®isters[REGISTER_BYTE (L0_REGNUM)], | |
298 | 16 * REGISTER_RAW_SIZE (L0_REGNUM))) | |
299 | { | |
300 | /* fprintf_unfiltered so user can still use gdb */ | |
301 | fprintf_unfiltered (gdb_stderr, | |
302 | "Couldn't read input and local registers from core file\n"); | |
303 | } | |
304 | } | |
c906108c | 305 | } |
c5aa993b JM |
306 | else if (which == 2) |
307 | { | |
c906108c | 308 | |
c5aa993b | 309 | /* Floating point registers */ |
c906108c SS |
310 | |
311 | #define fpuregs ((struct fpu *) core_reg_sect) | |
c5aa993b JM |
312 | if (core_reg_size >= sizeof (struct fpu)) |
313 | { | |
314 | memcpy (®isters[REGISTER_BYTE (FP0_REGNUM)], fpuregs->fpu_regs, | |
315 | sizeof (fpuregs->fpu_regs)); | |
316 | memcpy (®isters[REGISTER_BYTE (FPS_REGNUM)], &fpuregs->fpu_fsr, | |
317 | sizeof (FPU_FSR_TYPE)); | |
318 | } | |
319 | else | |
320 | fprintf_unfiltered (gdb_stderr, "Couldn't read float regs from core file\n"); | |
321 | } | |
c906108c SS |
322 | } |
323 | ||
324 | int | |
fba45db2 | 325 | kernel_u_size (void) |
c906108c SS |
326 | { |
327 | return (sizeof (struct user)); | |
328 | } | |
c906108c | 329 | \f |
c5aa993b | 330 | |
c906108c SS |
331 | /* Register that we are able to handle sparc core file formats. |
332 | FIXME: is this really bfd_target_unknown_flavour? */ | |
333 | ||
334 | static struct core_fns sparc_core_fns = | |
335 | { | |
2acceee2 JM |
336 | bfd_target_unknown_flavour, /* core_flavour */ |
337 | default_check_format, /* check_format */ | |
338 | default_core_sniffer, /* core_sniffer */ | |
339 | fetch_core_registers, /* core_read_registers */ | |
340 | NULL /* next */ | |
c906108c SS |
341 | }; |
342 | ||
343 | void | |
fba45db2 | 344 | _initialize_core_sparc (void) |
c906108c SS |
345 | { |
346 | add_core_fns (&sparc_core_fns); | |
347 | } |