Commit | Line | Data |
---|---|---|
386c036b | 1 | /* Target-dependent code for SPARC. |
cda5a58a | 2 | |
6aba47ca | 3 | Copyright (C) 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b JM |
17 | You should have received a copy of the GNU General Public License |
18 | along with this program; if not, write to the Free Software | |
197e01b6 EZ |
19 | Foundation, Inc., 51 Franklin Street, Fifth Floor, |
20 | Boston, MA 02110-1301, USA. */ | |
c906108c | 21 | |
c906108c | 22 | #include "defs.h" |
5af923b0 | 23 | #include "arch-utils.h" |
386c036b | 24 | #include "dis-asm.h" |
f5a9b87d | 25 | #include "dwarf2-frame.h" |
386c036b | 26 | #include "floatformat.h" |
c906108c | 27 | #include "frame.h" |
386c036b MK |
28 | #include "frame-base.h" |
29 | #include "frame-unwind.h" | |
30 | #include "gdbcore.h" | |
31 | #include "gdbtypes.h" | |
c906108c | 32 | #include "inferior.h" |
386c036b MK |
33 | #include "symtab.h" |
34 | #include "objfiles.h" | |
35 | #include "osabi.h" | |
36 | #include "regcache.h" | |
c906108c SS |
37 | #include "target.h" |
38 | #include "value.h" | |
c906108c | 39 | |
43bd9a9e | 40 | #include "gdb_assert.h" |
386c036b | 41 | #include "gdb_string.h" |
c906108c | 42 | |
386c036b | 43 | #include "sparc-tdep.h" |
c906108c | 44 | |
a54124c5 MK |
45 | struct regset; |
46 | ||
9eb42ed1 MK |
47 | /* This file implements the SPARC 32-bit ABI as defined by the section |
48 | "Low-Level System Information" of the SPARC Compliance Definition | |
49 | (SCD) 2.4.1, which is the 32-bit System V psABI for SPARC. The SCD | |
f2e7c15d | 50 | lists changes with respect to the original 32-bit psABI as defined |
9eb42ed1 | 51 | in the "System V ABI, SPARC Processor Supplement". |
386c036b MK |
52 | |
53 | Note that if we talk about SunOS, we mean SunOS 4.x, which was | |
54 | BSD-based, which is sometimes (retroactively?) referred to as | |
55 | Solaris 1.x. If we talk about Solaris we mean Solaris 2.x and | |
56 | above (Solaris 7, 8 and 9 are nothing but Solaris 2.7, 2.8 and 2.9 | |
57 | suffering from severe version number inflation). Solaris 2.x is | |
58 | also known as SunOS 5.x, since that's what uname(1) says. Solaris | |
59 | 2.x is SVR4-based. */ | |
60 | ||
61 | /* Please use the sparc32_-prefix for 32-bit specific code, the | |
62 | sparc64_-prefix for 64-bit specific code and the sparc_-prefix for | |
63 | code that can handle both. The 64-bit specific code lives in | |
64 | sparc64-tdep.c; don't add any here. */ | |
65 | ||
66 | /* The SPARC Floating-Point Quad-Precision format is similar to | |
67 | big-endian IA-64 Quad-recision format. */ | |
68 | #define floatformat_sparc_quad floatformat_ia64_quad_big | |
69 | ||
70 | /* The stack pointer is offset from the stack frame by a BIAS of 2047 | |
71 | (0x7ff) for 64-bit code. BIAS is likely to be defined on SPARC | |
72 | hosts, so undefine it first. */ | |
73 | #undef BIAS | |
74 | #define BIAS 2047 | |
75 | ||
76 | /* Macros to extract fields from SPARC instructions. */ | |
c906108c SS |
77 | #define X_OP(i) (((i) >> 30) & 0x3) |
78 | #define X_RD(i) (((i) >> 25) & 0x1f) | |
79 | #define X_A(i) (((i) >> 29) & 1) | |
80 | #define X_COND(i) (((i) >> 25) & 0xf) | |
81 | #define X_OP2(i) (((i) >> 22) & 0x7) | |
82 | #define X_IMM22(i) ((i) & 0x3fffff) | |
83 | #define X_OP3(i) (((i) >> 19) & 0x3f) | |
075ccec8 | 84 | #define X_RS1(i) (((i) >> 14) & 0x1f) |
c906108c | 85 | #define X_I(i) (((i) >> 13) & 1) |
c906108c | 86 | /* Sign extension macros. */ |
c906108c | 87 | #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000) |
c906108c | 88 | #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000) |
075ccec8 | 89 | #define X_SIMM13(i) ((((i) & 0x1fff) ^ 0x1000) - 0x1000) |
c906108c | 90 | |
386c036b MK |
91 | /* Fetch the instruction at PC. Instructions are always big-endian |
92 | even if the processor operates in little-endian mode. */ | |
93 | ||
94 | unsigned long | |
95 | sparc_fetch_instruction (CORE_ADDR pc) | |
c906108c | 96 | { |
e1613aba | 97 | gdb_byte buf[4]; |
386c036b MK |
98 | unsigned long insn; |
99 | int i; | |
100 | ||
690668cc | 101 | /* If we can't read the instruction at PC, return zero. */ |
b5bf31df | 102 | if (read_memory_nobpt (pc, buf, sizeof (buf))) |
690668cc | 103 | return 0; |
c906108c | 104 | |
386c036b MK |
105 | insn = 0; |
106 | for (i = 0; i < sizeof (buf); i++) | |
107 | insn = (insn << 8) | buf[i]; | |
108 | return insn; | |
109 | } | |
42cdca6c MK |
110 | \f |
111 | ||
5465445a JB |
112 | /* Return non-zero if the instruction corresponding to PC is an "unimp" |
113 | instruction. */ | |
114 | ||
115 | static int | |
116 | sparc_is_unimp_insn (CORE_ADDR pc) | |
117 | { | |
118 | const unsigned long insn = sparc_fetch_instruction (pc); | |
119 | ||
120 | return ((insn & 0xc1c00000) == 0); | |
121 | } | |
122 | ||
42cdca6c MK |
123 | /* OpenBSD/sparc includes StackGhost, which according to the author's |
124 | website http://stackghost.cerias.purdue.edu "... transparently and | |
125 | automatically protects applications' stack frames; more | |
126 | specifically, it guards the return pointers. The protection | |
127 | mechanisms require no application source or binary modification and | |
128 | imposes only a negligible performance penalty." | |
129 | ||
130 | The same website provides the following description of how | |
131 | StackGhost works: | |
132 | ||
133 | "StackGhost interfaces with the kernel trap handler that would | |
134 | normally write out registers to the stack and the handler that | |
135 | would read them back in. By XORing a cookie into the | |
136 | return-address saved in the user stack when it is actually written | |
137 | to the stack, and then XOR it out when the return-address is pulled | |
138 | from the stack, StackGhost can cause attacker corrupted return | |
139 | pointers to behave in a manner the attacker cannot predict. | |
140 | StackGhost can also use several unused bits in the return pointer | |
141 | to detect a smashed return pointer and abort the process." | |
142 | ||
143 | For GDB this means that whenever we're reading %i7 from a stack | |
144 | frame's window save area, we'll have to XOR the cookie. | |
145 | ||
146 | More information on StackGuard can be found on in: | |
147 | ||
148 | Mike Frantzen and Mike Shuey. "StackGhost: Hardware Facilitated | |
149 | Stack Protection." 2001. Published in USENIX Security Symposium | |
150 | '01. */ | |
151 | ||
152 | /* Fetch StackGhost Per-Process XOR cookie. */ | |
153 | ||
154 | ULONGEST | |
155 | sparc_fetch_wcookie (void) | |
156 | { | |
baf92889 | 157 | struct target_ops *ops = ¤t_target; |
e1613aba | 158 | gdb_byte buf[8]; |
baf92889 MK |
159 | int len; |
160 | ||
13547ab6 | 161 | len = target_read (ops, TARGET_OBJECT_WCOOKIE, NULL, buf, 0, 8); |
baf92889 MK |
162 | if (len == -1) |
163 | return 0; | |
42cdca6c | 164 | |
baf92889 MK |
165 | /* We should have either an 32-bit or an 64-bit cookie. */ |
166 | gdb_assert (len == 4 || len == 8); | |
167 | ||
168 | return extract_unsigned_integer (buf, len); | |
169 | } | |
386c036b | 170 | \f |
baf92889 | 171 | |
386c036b | 172 | /* Return the contents if register REGNUM as an address. */ |
c906108c | 173 | |
c893be75 | 174 | CORE_ADDR |
386c036b MK |
175 | sparc_address_from_register (int regnum) |
176 | { | |
177 | ULONGEST addr; | |
c906108c | 178 | |
386c036b MK |
179 | regcache_cooked_read_unsigned (current_regcache, regnum, &addr); |
180 | return addr; | |
181 | } | |
182 | \f | |
c906108c | 183 | |
386c036b MK |
184 | /* The functions on this page are intended to be used to classify |
185 | function arguments. */ | |
c906108c | 186 | |
386c036b | 187 | /* Check whether TYPE is "Integral or Pointer". */ |
c906108c | 188 | |
386c036b MK |
189 | static int |
190 | sparc_integral_or_pointer_p (const struct type *type) | |
c906108c | 191 | { |
80ad1639 MK |
192 | int len = TYPE_LENGTH (type); |
193 | ||
386c036b | 194 | switch (TYPE_CODE (type)) |
c906108c | 195 | { |
386c036b MK |
196 | case TYPE_CODE_INT: |
197 | case TYPE_CODE_BOOL: | |
198 | case TYPE_CODE_CHAR: | |
199 | case TYPE_CODE_ENUM: | |
200 | case TYPE_CODE_RANGE: | |
80ad1639 MK |
201 | /* We have byte, half-word, word and extended-word/doubleword |
202 | integral types. The doubleword is an extension to the | |
203 | original 32-bit ABI by the SCD 2.4.x. */ | |
204 | return (len == 1 || len == 2 || len == 4 || len == 8); | |
386c036b MK |
205 | case TYPE_CODE_PTR: |
206 | case TYPE_CODE_REF: | |
80ad1639 MK |
207 | /* Allow either 32-bit or 64-bit pointers. */ |
208 | return (len == 4 || len == 8); | |
386c036b MK |
209 | default: |
210 | break; | |
211 | } | |
c906108c | 212 | |
386c036b MK |
213 | return 0; |
214 | } | |
c906108c | 215 | |
386c036b | 216 | /* Check whether TYPE is "Floating". */ |
c906108c | 217 | |
386c036b MK |
218 | static int |
219 | sparc_floating_p (const struct type *type) | |
220 | { | |
221 | switch (TYPE_CODE (type)) | |
c906108c | 222 | { |
386c036b MK |
223 | case TYPE_CODE_FLT: |
224 | { | |
225 | int len = TYPE_LENGTH (type); | |
226 | return (len == 4 || len == 8 || len == 16); | |
227 | } | |
228 | default: | |
229 | break; | |
230 | } | |
231 | ||
232 | return 0; | |
233 | } | |
c906108c | 234 | |
386c036b | 235 | /* Check whether TYPE is "Structure or Union". */ |
c906108c | 236 | |
386c036b MK |
237 | static int |
238 | sparc_structure_or_union_p (const struct type *type) | |
239 | { | |
240 | switch (TYPE_CODE (type)) | |
241 | { | |
242 | case TYPE_CODE_STRUCT: | |
243 | case TYPE_CODE_UNION: | |
244 | return 1; | |
245 | default: | |
246 | break; | |
c906108c | 247 | } |
386c036b MK |
248 | |
249 | return 0; | |
c906108c | 250 | } |
386c036b MK |
251 | |
252 | /* Register information. */ | |
253 | ||
254 | static const char *sparc32_register_names[] = | |
5af923b0 | 255 | { |
386c036b MK |
256 | "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", |
257 | "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", | |
258 | "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", | |
259 | "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7", | |
260 | ||
261 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
262 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
263 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
264 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
265 | ||
266 | "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr" | |
5af923b0 MS |
267 | }; |
268 | ||
386c036b MK |
269 | /* Total number of registers. */ |
270 | #define SPARC32_NUM_REGS ARRAY_SIZE (sparc32_register_names) | |
c906108c | 271 | |
386c036b MK |
272 | /* We provide the aliases %d0..%d30 for the floating registers as |
273 | "psuedo" registers. */ | |
274 | ||
275 | static const char *sparc32_pseudo_register_names[] = | |
276 | { | |
277 | "d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14", | |
278 | "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30" | |
279 | }; | |
280 | ||
281 | /* Total number of pseudo registers. */ | |
282 | #define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names) | |
283 | ||
284 | /* Return the name of register REGNUM. */ | |
285 | ||
286 | static const char * | |
287 | sparc32_register_name (int regnum) | |
288 | { | |
289 | if (regnum >= 0 && regnum < SPARC32_NUM_REGS) | |
290 | return sparc32_register_names[regnum]; | |
291 | ||
292 | if (regnum < SPARC32_NUM_REGS + SPARC32_NUM_PSEUDO_REGS) | |
293 | return sparc32_pseudo_register_names[regnum - SPARC32_NUM_REGS]; | |
294 | ||
295 | return NULL; | |
296 | } | |
2d457077 MK |
297 | \f |
298 | ||
299 | /* Type for %psr. */ | |
300 | struct type *sparc_psr_type; | |
301 | ||
302 | /* Type for %fsr. */ | |
303 | struct type *sparc_fsr_type; | |
304 | ||
305 | /* Construct types for ISA-specific registers. */ | |
306 | ||
307 | static void | |
308 | sparc_init_types (void) | |
309 | { | |
310 | struct type *type; | |
311 | ||
312 | type = init_flags_type ("builtin_type_sparc_psr", 4); | |
313 | append_flags_type_flag (type, 5, "ET"); | |
314 | append_flags_type_flag (type, 6, "PS"); | |
315 | append_flags_type_flag (type, 7, "S"); | |
316 | append_flags_type_flag (type, 12, "EF"); | |
317 | append_flags_type_flag (type, 13, "EC"); | |
318 | sparc_psr_type = type; | |
319 | ||
320 | type = init_flags_type ("builtin_type_sparc_fsr", 4); | |
321 | append_flags_type_flag (type, 0, "NXA"); | |
322 | append_flags_type_flag (type, 1, "DZA"); | |
323 | append_flags_type_flag (type, 2, "UFA"); | |
324 | append_flags_type_flag (type, 3, "OFA"); | |
325 | append_flags_type_flag (type, 4, "NVA"); | |
326 | append_flags_type_flag (type, 5, "NXC"); | |
327 | append_flags_type_flag (type, 6, "DZC"); | |
328 | append_flags_type_flag (type, 7, "UFC"); | |
329 | append_flags_type_flag (type, 8, "OFC"); | |
330 | append_flags_type_flag (type, 9, "NVC"); | |
331 | append_flags_type_flag (type, 22, "NS"); | |
332 | append_flags_type_flag (type, 23, "NXM"); | |
333 | append_flags_type_flag (type, 24, "DZM"); | |
334 | append_flags_type_flag (type, 25, "UFM"); | |
335 | append_flags_type_flag (type, 26, "OFM"); | |
336 | append_flags_type_flag (type, 27, "NVM"); | |
337 | sparc_fsr_type = type; | |
338 | } | |
386c036b MK |
339 | |
340 | /* Return the GDB type object for the "standard" data type of data in | |
341 | register REGNUM. */ | |
342 | ||
343 | static struct type * | |
344 | sparc32_register_type (struct gdbarch *gdbarch, int regnum) | |
345 | { | |
346 | if (regnum >= SPARC_F0_REGNUM && regnum <= SPARC_F31_REGNUM) | |
347 | return builtin_type_float; | |
348 | ||
349 | if (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM) | |
350 | return builtin_type_double; | |
351 | ||
352 | if (regnum == SPARC_SP_REGNUM || regnum == SPARC_FP_REGNUM) | |
353 | return builtin_type_void_data_ptr; | |
354 | ||
355 | if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM) | |
356 | return builtin_type_void_func_ptr; | |
357 | ||
2d457077 MK |
358 | if (regnum == SPARC32_PSR_REGNUM) |
359 | return sparc_psr_type; | |
360 | ||
361 | if (regnum == SPARC32_FSR_REGNUM) | |
362 | return sparc_fsr_type; | |
363 | ||
386c036b MK |
364 | return builtin_type_int32; |
365 | } | |
366 | ||
367 | static void | |
368 | sparc32_pseudo_register_read (struct gdbarch *gdbarch, | |
369 | struct regcache *regcache, | |
e1613aba | 370 | int regnum, gdb_byte *buf) |
386c036b MK |
371 | { |
372 | gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM); | |
373 | ||
374 | regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM); | |
375 | regcache_raw_read (regcache, regnum, buf); | |
e1613aba | 376 | regcache_raw_read (regcache, regnum + 1, buf + 4); |
386c036b MK |
377 | } |
378 | ||
379 | static void | |
380 | sparc32_pseudo_register_write (struct gdbarch *gdbarch, | |
381 | struct regcache *regcache, | |
e1613aba | 382 | int regnum, const gdb_byte *buf) |
386c036b MK |
383 | { |
384 | gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM); | |
385 | ||
386 | regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM); | |
387 | regcache_raw_write (regcache, regnum, buf); | |
e1613aba | 388 | regcache_raw_write (regcache, regnum + 1, buf + 4); |
386c036b MK |
389 | } |
390 | \f | |
391 | ||
392 | static CORE_ADDR | |
393 | sparc32_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, | |
394 | CORE_ADDR funcaddr, int using_gcc, | |
395 | struct value **args, int nargs, | |
396 | struct type *value_type, | |
397 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr) | |
c906108c | 398 | { |
386c036b MK |
399 | *bp_addr = sp - 4; |
400 | *real_pc = funcaddr; | |
401 | ||
402 | if (using_struct_return (value_type, using_gcc)) | |
c906108c | 403 | { |
e1613aba | 404 | gdb_byte buf[4]; |
386c036b MK |
405 | |
406 | /* This is an UNIMP instruction. */ | |
407 | store_unsigned_integer (buf, 4, TYPE_LENGTH (value_type) & 0x1fff); | |
408 | write_memory (sp - 8, buf, 4); | |
409 | return sp - 8; | |
c906108c SS |
410 | } |
411 | ||
386c036b MK |
412 | return sp - 4; |
413 | } | |
414 | ||
415 | static CORE_ADDR | |
416 | sparc32_store_arguments (struct regcache *regcache, int nargs, | |
417 | struct value **args, CORE_ADDR sp, | |
418 | int struct_return, CORE_ADDR struct_addr) | |
419 | { | |
420 | /* Number of words in the "parameter array". */ | |
421 | int num_elements = 0; | |
422 | int element = 0; | |
423 | int i; | |
424 | ||
425 | for (i = 0; i < nargs; i++) | |
c906108c | 426 | { |
4991999e | 427 | struct type *type = value_type (args[i]); |
386c036b MK |
428 | int len = TYPE_LENGTH (type); |
429 | ||
430 | if (sparc_structure_or_union_p (type) | |
431 | || (sparc_floating_p (type) && len == 16)) | |
c906108c | 432 | { |
386c036b MK |
433 | /* Structure, Union and Quad-Precision Arguments. */ |
434 | sp -= len; | |
435 | ||
436 | /* Use doubleword alignment for these values. That's always | |
437 | correct, and wasting a few bytes shouldn't be a problem. */ | |
438 | sp &= ~0x7; | |
439 | ||
0fd88904 | 440 | write_memory (sp, value_contents (args[i]), len); |
386c036b MK |
441 | args[i] = value_from_pointer (lookup_pointer_type (type), sp); |
442 | num_elements++; | |
443 | } | |
444 | else if (sparc_floating_p (type)) | |
445 | { | |
446 | /* Floating arguments. */ | |
447 | gdb_assert (len == 4 || len == 8); | |
448 | num_elements += (len / 4); | |
c906108c | 449 | } |
c5aa993b JM |
450 | else |
451 | { | |
386c036b MK |
452 | /* Integral and pointer arguments. */ |
453 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
454 | ||
455 | if (len < 4) | |
456 | args[i] = value_cast (builtin_type_int32, args[i]); | |
457 | num_elements += ((len + 3) / 4); | |
c5aa993b | 458 | } |
c906108c | 459 | } |
c906108c | 460 | |
386c036b MK |
461 | /* Always allocate at least six words. */ |
462 | sp -= max (6, num_elements) * 4; | |
c906108c | 463 | |
386c036b MK |
464 | /* The psABI says that "Software convention requires space for the |
465 | struct/union return value pointer, even if the word is unused." */ | |
466 | sp -= 4; | |
c906108c | 467 | |
386c036b MK |
468 | /* The psABI says that "Although software convention and the |
469 | operating system require every stack frame to be doubleword | |
470 | aligned." */ | |
471 | sp &= ~0x7; | |
c906108c | 472 | |
386c036b | 473 | for (i = 0; i < nargs; i++) |
c906108c | 474 | { |
0fd88904 | 475 | const bfd_byte *valbuf = value_contents (args[i]); |
4991999e | 476 | struct type *type = value_type (args[i]); |
386c036b | 477 | int len = TYPE_LENGTH (type); |
c906108c | 478 | |
386c036b | 479 | gdb_assert (len == 4 || len == 8); |
c906108c | 480 | |
386c036b MK |
481 | if (element < 6) |
482 | { | |
483 | int regnum = SPARC_O0_REGNUM + element; | |
c906108c | 484 | |
386c036b MK |
485 | regcache_cooked_write (regcache, regnum, valbuf); |
486 | if (len > 4 && element < 5) | |
487 | regcache_cooked_write (regcache, regnum + 1, valbuf + 4); | |
488 | } | |
5af923b0 | 489 | |
386c036b MK |
490 | /* Always store the argument in memory. */ |
491 | write_memory (sp + 4 + element * 4, valbuf, len); | |
492 | element += len / 4; | |
493 | } | |
c906108c | 494 | |
386c036b | 495 | gdb_assert (element == num_elements); |
c906108c | 496 | |
386c036b | 497 | if (struct_return) |
c906108c | 498 | { |
e1613aba | 499 | gdb_byte buf[4]; |
c906108c | 500 | |
386c036b MK |
501 | store_unsigned_integer (buf, 4, struct_addr); |
502 | write_memory (sp, buf, 4); | |
503 | } | |
c906108c | 504 | |
386c036b | 505 | return sp; |
c906108c SS |
506 | } |
507 | ||
386c036b | 508 | static CORE_ADDR |
7d9b040b | 509 | sparc32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
386c036b MK |
510 | struct regcache *regcache, CORE_ADDR bp_addr, |
511 | int nargs, struct value **args, CORE_ADDR sp, | |
512 | int struct_return, CORE_ADDR struct_addr) | |
c906108c | 513 | { |
386c036b MK |
514 | CORE_ADDR call_pc = (struct_return ? (bp_addr - 12) : (bp_addr - 8)); |
515 | ||
516 | /* Set return address. */ | |
517 | regcache_cooked_write_unsigned (regcache, SPARC_O7_REGNUM, call_pc); | |
518 | ||
519 | /* Set up function arguments. */ | |
520 | sp = sparc32_store_arguments (regcache, nargs, args, sp, | |
521 | struct_return, struct_addr); | |
522 | ||
523 | /* Allocate the 16-word window save area. */ | |
524 | sp -= 16 * 4; | |
c906108c | 525 | |
386c036b MK |
526 | /* Stack should be doubleword aligned at this point. */ |
527 | gdb_assert (sp % 8 == 0); | |
c906108c | 528 | |
386c036b MK |
529 | /* Finally, update the stack pointer. */ |
530 | regcache_cooked_write_unsigned (regcache, SPARC_SP_REGNUM, sp); | |
531 | ||
532 | return sp; | |
533 | } | |
534 | \f | |
c906108c | 535 | |
386c036b MK |
536 | /* Use the program counter to determine the contents and size of a |
537 | breakpoint instruction. Return a pointer to a string of bytes that | |
538 | encode a breakpoint instruction, store the length of the string in | |
539 | *LEN and optionally adjust *PC to point to the correct memory | |
540 | location for inserting the breakpoint. */ | |
541 | ||
e1613aba | 542 | static const gdb_byte * |
386c036b MK |
543 | sparc_breakpoint_from_pc (CORE_ADDR *pc, int *len) |
544 | { | |
864a1a37 | 545 | static const gdb_byte break_insn[] = { 0x91, 0xd0, 0x20, 0x01 }; |
c5aa993b | 546 | |
386c036b MK |
547 | *len = sizeof (break_insn); |
548 | return break_insn; | |
c906108c | 549 | } |
386c036b | 550 | \f |
c906108c | 551 | |
386c036b | 552 | /* Allocate and initialize a frame cache. */ |
c906108c | 553 | |
386c036b MK |
554 | static struct sparc_frame_cache * |
555 | sparc_alloc_frame_cache (void) | |
556 | { | |
557 | struct sparc_frame_cache *cache; | |
558 | int i; | |
c906108c | 559 | |
386c036b | 560 | cache = FRAME_OBSTACK_ZALLOC (struct sparc_frame_cache); |
c906108c | 561 | |
386c036b MK |
562 | /* Base address. */ |
563 | cache->base = 0; | |
564 | cache->pc = 0; | |
c906108c | 565 | |
386c036b MK |
566 | /* Frameless until proven otherwise. */ |
567 | cache->frameless_p = 1; | |
568 | ||
569 | cache->struct_return_p = 0; | |
570 | ||
571 | return cache; | |
572 | } | |
573 | ||
574 | CORE_ADDR | |
575 | sparc_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc, | |
576 | struct sparc_frame_cache *cache) | |
c906108c | 577 | { |
386c036b MK |
578 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
579 | unsigned long insn; | |
580 | int offset = 0; | |
c906108c | 581 | int dest = -1; |
c906108c | 582 | |
386c036b MK |
583 | if (current_pc <= pc) |
584 | return current_pc; | |
585 | ||
586 | /* We have to handle to "Procedure Linkage Table" (PLT) special. On | |
587 | SPARC the linker usually defines a symbol (typically | |
588 | _PROCEDURE_LINKAGE_TABLE_) at the start of the .plt section. | |
589 | This symbol makes us end up here with PC pointing at the start of | |
590 | the PLT and CURRENT_PC probably pointing at a PLT entry. If we | |
591 | would do our normal prologue analysis, we would probably conclude | |
592 | that we've got a frame when in reality we don't, since the | |
593 | dynamic linker patches up the first PLT with some code that | |
594 | starts with a SAVE instruction. Patch up PC such that it points | |
595 | at the start of our PLT entry. */ | |
596 | if (tdep->plt_entry_size > 0 && in_plt_section (current_pc, NULL)) | |
597 | pc = current_pc - ((current_pc - pc) % tdep->plt_entry_size); | |
c906108c | 598 | |
386c036b MK |
599 | insn = sparc_fetch_instruction (pc); |
600 | ||
601 | /* Recognize a SETHI insn and record its destination. */ | |
602 | if (X_OP (insn) == 0 && X_OP2 (insn) == 0x04) | |
c906108c SS |
603 | { |
604 | dest = X_RD (insn); | |
386c036b MK |
605 | offset += 4; |
606 | ||
607 | insn = sparc_fetch_instruction (pc + 4); | |
c906108c SS |
608 | } |
609 | ||
386c036b MK |
610 | /* Allow for an arithmetic operation on DEST or %g1. */ |
611 | if (X_OP (insn) == 2 && X_I (insn) | |
c906108c SS |
612 | && (X_RD (insn) == 1 || X_RD (insn) == dest)) |
613 | { | |
386c036b | 614 | offset += 4; |
c906108c | 615 | |
386c036b | 616 | insn = sparc_fetch_instruction (pc + 8); |
c906108c | 617 | } |
c906108c | 618 | |
386c036b MK |
619 | /* Check for the SAVE instruction that sets up the frame. */ |
620 | if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3c) | |
c906108c | 621 | { |
386c036b MK |
622 | cache->frameless_p = 0; |
623 | return pc + offset + 4; | |
c906108c SS |
624 | } |
625 | ||
626 | return pc; | |
627 | } | |
628 | ||
386c036b MK |
629 | static CORE_ADDR |
630 | sparc_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
631 | { | |
632 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
633 | return frame_unwind_register_unsigned (next_frame, tdep->pc_regnum); | |
634 | } | |
635 | ||
636 | /* Return PC of first real instruction of the function starting at | |
637 | START_PC. */ | |
f510d44e | 638 | |
386c036b MK |
639 | static CORE_ADDR |
640 | sparc32_skip_prologue (CORE_ADDR start_pc) | |
c906108c | 641 | { |
f510d44e DM |
642 | struct symtab_and_line sal; |
643 | CORE_ADDR func_start, func_end; | |
386c036b | 644 | struct sparc_frame_cache cache; |
f510d44e DM |
645 | |
646 | /* This is the preferred method, find the end of the prologue by | |
647 | using the debugging information. */ | |
648 | if (find_pc_partial_function (start_pc, NULL, &func_start, &func_end)) | |
649 | { | |
650 | sal = find_pc_line (func_start, 0); | |
651 | ||
652 | if (sal.end < func_end | |
653 | && start_pc <= sal.end) | |
654 | return sal.end; | |
655 | } | |
656 | ||
075ccec8 MK |
657 | start_pc = sparc_analyze_prologue (start_pc, 0xffffffffUL, &cache); |
658 | ||
659 | /* The psABI says that "Although the first 6 words of arguments | |
660 | reside in registers, the standard stack frame reserves space for | |
661 | them.". It also suggests that a function may use that space to | |
662 | "write incoming arguments 0 to 5" into that space, and that's | |
663 | indeed what GCC seems to be doing. In that case GCC will | |
664 | generate debug information that points to the stack slots instead | |
665 | of the registers, so we should consider the instructions that | |
666 | write out these incoming arguments onto the stack. Of course we | |
667 | only need to do this if we have a stack frame. */ | |
668 | ||
669 | while (!cache.frameless_p) | |
670 | { | |
671 | unsigned long insn = sparc_fetch_instruction (start_pc); | |
672 | ||
673 | /* Recognize instructions that store incoming arguments in | |
674 | %i0...%i5 into the corresponding stack slot. */ | |
675 | if (X_OP (insn) == 3 && (X_OP3 (insn) & 0x3c) == 0x04 && X_I (insn) | |
676 | && (X_RD (insn) >= 24 && X_RD (insn) <= 29) && X_RS1 (insn) == 30 | |
677 | && X_SIMM13 (insn) == 68 + (X_RD (insn) - 24) * 4) | |
678 | { | |
679 | start_pc += 4; | |
680 | continue; | |
681 | } | |
682 | ||
683 | break; | |
684 | } | |
685 | ||
686 | return start_pc; | |
c906108c SS |
687 | } |
688 | ||
386c036b | 689 | /* Normal frames. */ |
9319a2fe | 690 | |
386c036b MK |
691 | struct sparc_frame_cache * |
692 | sparc_frame_cache (struct frame_info *next_frame, void **this_cache) | |
9319a2fe | 693 | { |
386c036b | 694 | struct sparc_frame_cache *cache; |
9319a2fe | 695 | |
386c036b MK |
696 | if (*this_cache) |
697 | return *this_cache; | |
c906108c | 698 | |
386c036b MK |
699 | cache = sparc_alloc_frame_cache (); |
700 | *this_cache = cache; | |
c906108c | 701 | |
386c036b MK |
702 | cache->pc = frame_func_unwind (next_frame); |
703 | if (cache->pc != 0) | |
c906108c | 704 | { |
386c036b MK |
705 | CORE_ADDR addr_in_block = frame_unwind_address_in_block (next_frame); |
706 | sparc_analyze_prologue (cache->pc, addr_in_block, cache); | |
c906108c | 707 | } |
386c036b MK |
708 | |
709 | if (cache->frameless_p) | |
c906108c | 710 | { |
cbeae229 MK |
711 | /* This function is frameless, so %fp (%i6) holds the frame |
712 | pointer for our calling frame. Use %sp (%o6) as this frame's | |
713 | base address. */ | |
714 | cache->base = | |
715 | frame_unwind_register_unsigned (next_frame, SPARC_SP_REGNUM); | |
716 | } | |
717 | else | |
718 | { | |
719 | /* For normal frames, %fp (%i6) holds the frame pointer, the | |
720 | base address for the current stack frame. */ | |
721 | cache->base = | |
722 | frame_unwind_register_unsigned (next_frame, SPARC_FP_REGNUM); | |
c906108c | 723 | } |
c906108c | 724 | |
5b2d44a0 MK |
725 | if (cache->base & 1) |
726 | cache->base += BIAS; | |
727 | ||
386c036b | 728 | return cache; |
c906108c | 729 | } |
c906108c | 730 | |
aff37fc1 DM |
731 | static int |
732 | sparc32_struct_return_from_sym (struct symbol *sym) | |
733 | { | |
734 | struct type *type = check_typedef (SYMBOL_TYPE (sym)); | |
735 | enum type_code code = TYPE_CODE (type); | |
736 | ||
737 | if (code == TYPE_CODE_FUNC || code == TYPE_CODE_METHOD) | |
738 | { | |
739 | type = check_typedef (TYPE_TARGET_TYPE (type)); | |
740 | if (sparc_structure_or_union_p (type) | |
741 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)) | |
742 | return 1; | |
743 | } | |
744 | ||
745 | return 0; | |
746 | } | |
747 | ||
386c036b MK |
748 | struct sparc_frame_cache * |
749 | sparc32_frame_cache (struct frame_info *next_frame, void **this_cache) | |
c906108c | 750 | { |
386c036b MK |
751 | struct sparc_frame_cache *cache; |
752 | struct symbol *sym; | |
c906108c | 753 | |
386c036b MK |
754 | if (*this_cache) |
755 | return *this_cache; | |
c906108c | 756 | |
386c036b | 757 | cache = sparc_frame_cache (next_frame, this_cache); |
c906108c | 758 | |
386c036b MK |
759 | sym = find_pc_function (cache->pc); |
760 | if (sym) | |
c906108c | 761 | { |
aff37fc1 | 762 | cache->struct_return_p = sparc32_struct_return_from_sym (sym); |
c906108c | 763 | } |
5465445a JB |
764 | else |
765 | { | |
766 | /* There is no debugging information for this function to | |
767 | help us determine whether this function returns a struct | |
768 | or not. So we rely on another heuristic which is to check | |
769 | the instruction at the return address and see if this is | |
770 | an "unimp" instruction. If it is, then it is a struct-return | |
771 | function. */ | |
772 | CORE_ADDR pc; | |
773 | int regnum = cache->frameless_p ? SPARC_O7_REGNUM : SPARC_I7_REGNUM; | |
774 | ||
775 | pc = frame_unwind_register_unsigned (next_frame, regnum) + 8; | |
776 | if (sparc_is_unimp_insn (pc)) | |
777 | cache->struct_return_p = 1; | |
778 | } | |
c906108c | 779 | |
386c036b MK |
780 | return cache; |
781 | } | |
782 | ||
783 | static void | |
784 | sparc32_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
785 | struct frame_id *this_id) | |
786 | { | |
787 | struct sparc_frame_cache *cache = | |
788 | sparc32_frame_cache (next_frame, this_cache); | |
789 | ||
790 | /* This marks the outermost frame. */ | |
791 | if (cache->base == 0) | |
792 | return; | |
793 | ||
794 | (*this_id) = frame_id_build (cache->base, cache->pc); | |
795 | } | |
c906108c | 796 | |
386c036b MK |
797 | static void |
798 | sparc32_frame_prev_register (struct frame_info *next_frame, void **this_cache, | |
799 | int regnum, int *optimizedp, | |
800 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
47ef841b | 801 | int *realnump, gdb_byte *valuep) |
386c036b MK |
802 | { |
803 | struct sparc_frame_cache *cache = | |
804 | sparc32_frame_cache (next_frame, this_cache); | |
c906108c | 805 | |
386c036b | 806 | if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM) |
c906108c | 807 | { |
386c036b MK |
808 | *optimizedp = 0; |
809 | *lvalp = not_lval; | |
810 | *addrp = 0; | |
811 | *realnump = -1; | |
812 | if (valuep) | |
c906108c | 813 | { |
386c036b MK |
814 | CORE_ADDR pc = (regnum == SPARC32_NPC_REGNUM) ? 4 : 0; |
815 | ||
816 | /* If this functions has a Structure, Union or | |
817 | Quad-Precision return value, we have to skip the UNIMP | |
818 | instruction that encodes the size of the structure. */ | |
819 | if (cache->struct_return_p) | |
820 | pc += 4; | |
821 | ||
822 | regnum = cache->frameless_p ? SPARC_O7_REGNUM : SPARC_I7_REGNUM; | |
823 | pc += frame_unwind_register_unsigned (next_frame, regnum) + 8; | |
824 | store_unsigned_integer (valuep, 4, pc); | |
c906108c | 825 | } |
c906108c SS |
826 | return; |
827 | } | |
828 | ||
42cdca6c MK |
829 | /* Handle StackGhost. */ |
830 | { | |
831 | ULONGEST wcookie = sparc_fetch_wcookie (); | |
832 | ||
833 | if (wcookie != 0 && !cache->frameless_p && regnum == SPARC_I7_REGNUM) | |
834 | { | |
835 | *optimizedp = 0; | |
836 | *lvalp = not_lval; | |
837 | *addrp = 0; | |
838 | *realnump = -1; | |
839 | if (valuep) | |
840 | { | |
841 | CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4; | |
7d34766b | 842 | ULONGEST i7; |
42cdca6c MK |
843 | |
844 | /* Read the value in from memory. */ | |
7d34766b MK |
845 | i7 = get_frame_memory_unsigned (next_frame, addr, 4); |
846 | store_unsigned_integer (valuep, 4, i7 ^ wcookie); | |
42cdca6c MK |
847 | } |
848 | return; | |
849 | } | |
850 | } | |
851 | ||
386c036b MK |
852 | /* The previous frame's `local' and `in' registers have been saved |
853 | in the register save area. */ | |
854 | if (!cache->frameless_p | |
855 | && regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) | |
c906108c | 856 | { |
386c036b MK |
857 | *optimizedp = 0; |
858 | *lvalp = lval_memory; | |
859 | *addrp = cache->base + (regnum - SPARC_L0_REGNUM) * 4; | |
860 | *realnump = -1; | |
861 | if (valuep) | |
c906108c | 862 | { |
386c036b MK |
863 | struct gdbarch *gdbarch = get_frame_arch (next_frame); |
864 | ||
865 | /* Read the value in from memory. */ | |
866 | read_memory (*addrp, valuep, register_size (gdbarch, regnum)); | |
c906108c | 867 | } |
386c036b MK |
868 | return; |
869 | } | |
c906108c | 870 | |
386c036b MK |
871 | /* The previous frame's `out' registers are accessable as the |
872 | current frame's `in' registers. */ | |
873 | if (!cache->frameless_p | |
874 | && regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O7_REGNUM) | |
875 | regnum += (SPARC_I0_REGNUM - SPARC_O0_REGNUM); | |
5af923b0 | 876 | |
00b25ff3 AC |
877 | *optimizedp = 0; |
878 | *lvalp = lval_register; | |
879 | *addrp = 0; | |
880 | *realnump = regnum; | |
881 | if (valuep) | |
882 | frame_unwind_register (next_frame, (*realnump), valuep); | |
386c036b | 883 | } |
c906108c | 884 | |
386c036b MK |
885 | static const struct frame_unwind sparc32_frame_unwind = |
886 | { | |
887 | NORMAL_FRAME, | |
888 | sparc32_frame_this_id, | |
889 | sparc32_frame_prev_register | |
890 | }; | |
891 | ||
892 | static const struct frame_unwind * | |
893 | sparc32_frame_sniffer (struct frame_info *next_frame) | |
894 | { | |
895 | return &sparc32_frame_unwind; | |
c906108c | 896 | } |
386c036b | 897 | \f |
c906108c | 898 | |
386c036b MK |
899 | static CORE_ADDR |
900 | sparc32_frame_base_address (struct frame_info *next_frame, void **this_cache) | |
901 | { | |
902 | struct sparc_frame_cache *cache = | |
903 | sparc32_frame_cache (next_frame, this_cache); | |
c906108c | 904 | |
386c036b MK |
905 | return cache->base; |
906 | } | |
c906108c | 907 | |
386c036b MK |
908 | static const struct frame_base sparc32_frame_base = |
909 | { | |
910 | &sparc32_frame_unwind, | |
911 | sparc32_frame_base_address, | |
912 | sparc32_frame_base_address, | |
913 | sparc32_frame_base_address | |
914 | }; | |
c906108c | 915 | |
386c036b MK |
916 | static struct frame_id |
917 | sparc_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
918 | { | |
919 | CORE_ADDR sp; | |
5af923b0 | 920 | |
386c036b | 921 | sp = frame_unwind_register_unsigned (next_frame, SPARC_SP_REGNUM); |
5b2d44a0 MK |
922 | if (sp & 1) |
923 | sp += BIAS; | |
386c036b MK |
924 | return frame_id_build (sp, frame_pc_unwind (next_frame)); |
925 | } | |
926 | \f | |
c906108c | 927 | |
386c036b MK |
928 | /* Extract from an array REGBUF containing the (raw) register state, a |
929 | function return value of TYPE, and copy that into VALBUF. */ | |
5af923b0 | 930 | |
386c036b MK |
931 | static void |
932 | sparc32_extract_return_value (struct type *type, struct regcache *regcache, | |
e1613aba | 933 | gdb_byte *valbuf) |
386c036b MK |
934 | { |
935 | int len = TYPE_LENGTH (type); | |
e1613aba | 936 | gdb_byte buf[8]; |
c906108c | 937 | |
386c036b MK |
938 | gdb_assert (!sparc_structure_or_union_p (type)); |
939 | gdb_assert (!(sparc_floating_p (type) && len == 16)); | |
c906108c | 940 | |
386c036b | 941 | if (sparc_floating_p (type)) |
5af923b0 | 942 | { |
386c036b MK |
943 | /* Floating return values. */ |
944 | regcache_cooked_read (regcache, SPARC_F0_REGNUM, buf); | |
945 | if (len > 4) | |
946 | regcache_cooked_read (regcache, SPARC_F1_REGNUM, buf + 4); | |
947 | memcpy (valbuf, buf, len); | |
5af923b0 MS |
948 | } |
949 | else | |
950 | { | |
386c036b MK |
951 | /* Integral and pointer return values. */ |
952 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
c906108c | 953 | |
386c036b MK |
954 | regcache_cooked_read (regcache, SPARC_O0_REGNUM, buf); |
955 | if (len > 4) | |
956 | { | |
957 | regcache_cooked_read (regcache, SPARC_O1_REGNUM, buf + 4); | |
958 | gdb_assert (len == 8); | |
959 | memcpy (valbuf, buf, 8); | |
960 | } | |
961 | else | |
962 | { | |
963 | /* Just stripping off any unused bytes should preserve the | |
964 | signed-ness just fine. */ | |
965 | memcpy (valbuf, buf + 4 - len, len); | |
966 | } | |
967 | } | |
968 | } | |
c906108c | 969 | |
386c036b MK |
970 | /* Write into the appropriate registers a function return value stored |
971 | in VALBUF of type TYPE. */ | |
c906108c | 972 | |
386c036b MK |
973 | static void |
974 | sparc32_store_return_value (struct type *type, struct regcache *regcache, | |
e1613aba | 975 | const gdb_byte *valbuf) |
386c036b MK |
976 | { |
977 | int len = TYPE_LENGTH (type); | |
e1613aba | 978 | gdb_byte buf[8]; |
c906108c | 979 | |
386c036b MK |
980 | gdb_assert (!sparc_structure_or_union_p (type)); |
981 | gdb_assert (!(sparc_floating_p (type) && len == 16)); | |
c906108c | 982 | |
386c036b MK |
983 | if (sparc_floating_p (type)) |
984 | { | |
985 | /* Floating return values. */ | |
986 | memcpy (buf, valbuf, len); | |
987 | regcache_cooked_write (regcache, SPARC_F0_REGNUM, buf); | |
988 | if (len > 4) | |
989 | regcache_cooked_write (regcache, SPARC_F1_REGNUM, buf + 4); | |
990 | } | |
991 | else | |
c906108c | 992 | { |
386c036b MK |
993 | /* Integral and pointer return values. */ |
994 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
995 | ||
996 | if (len > 4) | |
2757dd86 | 997 | { |
386c036b MK |
998 | gdb_assert (len == 8); |
999 | memcpy (buf, valbuf, 8); | |
1000 | regcache_cooked_write (regcache, SPARC_O1_REGNUM, buf + 4); | |
2757dd86 AC |
1001 | } |
1002 | else | |
1003 | { | |
386c036b MK |
1004 | /* ??? Do we need to do any sign-extension here? */ |
1005 | memcpy (buf + 4 - len, valbuf, len); | |
2757dd86 | 1006 | } |
386c036b | 1007 | regcache_cooked_write (regcache, SPARC_O0_REGNUM, buf); |
c906108c SS |
1008 | } |
1009 | } | |
1010 | ||
b9d4c5ed MK |
1011 | static enum return_value_convention |
1012 | sparc32_return_value (struct gdbarch *gdbarch, struct type *type, | |
e1613aba MK |
1013 | struct regcache *regcache, gdb_byte *readbuf, |
1014 | const gdb_byte *writebuf) | |
b9d4c5ed | 1015 | { |
0a8f48b9 MK |
1016 | /* The psABI says that "...every stack frame reserves the word at |
1017 | %fp+64. If a function returns a structure, union, or | |
1018 | quad-precision value, this word should hold the address of the | |
1019 | object into which the return value should be copied." This | |
1020 | guarantees that we can always find the return value, not just | |
1021 | before the function returns. */ | |
1022 | ||
b9d4c5ed MK |
1023 | if (sparc_structure_or_union_p (type) |
1024 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)) | |
0a8f48b9 MK |
1025 | { |
1026 | if (readbuf) | |
1027 | { | |
1028 | ULONGEST sp; | |
1029 | CORE_ADDR addr; | |
1030 | ||
1031 | regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); | |
1032 | addr = read_memory_unsigned_integer (sp + 64, 4); | |
1033 | read_memory (addr, readbuf, TYPE_LENGTH (type)); | |
1034 | } | |
1035 | ||
1036 | return RETURN_VALUE_ABI_PRESERVES_ADDRESS; | |
1037 | } | |
b9d4c5ed MK |
1038 | |
1039 | if (readbuf) | |
1040 | sparc32_extract_return_value (type, regcache, readbuf); | |
1041 | if (writebuf) | |
1042 | sparc32_store_return_value (type, regcache, writebuf); | |
1043 | ||
1044 | return RETURN_VALUE_REGISTER_CONVENTION; | |
1045 | } | |
1046 | ||
386c036b MK |
1047 | static int |
1048 | sparc32_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type) | |
c906108c | 1049 | { |
386c036b MK |
1050 | return (sparc_structure_or_union_p (type) |
1051 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)); | |
1052 | } | |
c906108c | 1053 | |
aff37fc1 DM |
1054 | static int |
1055 | sparc32_dwarf2_struct_return_p (struct frame_info *next_frame) | |
1056 | { | |
1057 | CORE_ADDR pc = frame_unwind_address_in_block (next_frame); | |
1058 | struct symbol *sym = find_pc_function (pc); | |
1059 | ||
1060 | if (sym) | |
1061 | return sparc32_struct_return_from_sym (sym); | |
1062 | return 0; | |
1063 | } | |
1064 | ||
f5a9b87d DM |
1065 | static void |
1066 | sparc32_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
aff37fc1 DM |
1067 | struct dwarf2_frame_state_reg *reg, |
1068 | struct frame_info *next_frame) | |
f5a9b87d | 1069 | { |
aff37fc1 DM |
1070 | int off; |
1071 | ||
f5a9b87d DM |
1072 | switch (regnum) |
1073 | { | |
1074 | case SPARC_G0_REGNUM: | |
1075 | /* Since %g0 is always zero, there is no point in saving it, and | |
1076 | people will be inclined omit it from the CFI. Make sure we | |
1077 | don't warn about that. */ | |
1078 | reg->how = DWARF2_FRAME_REG_SAME_VALUE; | |
1079 | break; | |
1080 | case SPARC_SP_REGNUM: | |
1081 | reg->how = DWARF2_FRAME_REG_CFA; | |
1082 | break; | |
1083 | case SPARC32_PC_REGNUM: | |
f5a9b87d DM |
1084 | case SPARC32_NPC_REGNUM: |
1085 | reg->how = DWARF2_FRAME_REG_RA_OFFSET; | |
aff37fc1 DM |
1086 | off = 8; |
1087 | if (sparc32_dwarf2_struct_return_p (next_frame)) | |
1088 | off += 4; | |
1089 | if (regnum == SPARC32_NPC_REGNUM) | |
1090 | off += 4; | |
1091 | reg->loc.offset = off; | |
f5a9b87d DM |
1092 | break; |
1093 | } | |
1094 | } | |
1095 | ||
386c036b MK |
1096 | \f |
1097 | /* The SPARC Architecture doesn't have hardware single-step support, | |
1098 | and most operating systems don't implement it either, so we provide | |
1099 | software single-step mechanism. */ | |
c906108c | 1100 | |
386c036b | 1101 | static CORE_ADDR |
c893be75 MK |
1102 | sparc_analyze_control_transfer (struct gdbarch *arch, |
1103 | CORE_ADDR pc, CORE_ADDR *npc) | |
386c036b MK |
1104 | { |
1105 | unsigned long insn = sparc_fetch_instruction (pc); | |
1106 | int conditional_p = X_COND (insn) & 0x7; | |
1107 | int branch_p = 0; | |
1108 | long offset = 0; /* Must be signed for sign-extend. */ | |
c906108c | 1109 | |
386c036b | 1110 | if (X_OP (insn) == 0 && X_OP2 (insn) == 3 && (insn & 0x1000000) == 0) |
c906108c | 1111 | { |
386c036b MK |
1112 | /* Branch on Integer Register with Prediction (BPr). */ |
1113 | branch_p = 1; | |
1114 | conditional_p = 1; | |
c906108c | 1115 | } |
386c036b | 1116 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 6) |
c906108c | 1117 | { |
386c036b MK |
1118 | /* Branch on Floating-Point Condition Codes (FBfcc). */ |
1119 | branch_p = 1; | |
1120 | offset = 4 * X_DISP22 (insn); | |
c906108c | 1121 | } |
386c036b MK |
1122 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 5) |
1123 | { | |
1124 | /* Branch on Floating-Point Condition Codes with Prediction | |
1125 | (FBPfcc). */ | |
1126 | branch_p = 1; | |
1127 | offset = 4 * X_DISP19 (insn); | |
1128 | } | |
1129 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 2) | |
1130 | { | |
1131 | /* Branch on Integer Condition Codes (Bicc). */ | |
1132 | branch_p = 1; | |
1133 | offset = 4 * X_DISP22 (insn); | |
1134 | } | |
1135 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 1) | |
c906108c | 1136 | { |
386c036b MK |
1137 | /* Branch on Integer Condition Codes with Prediction (BPcc). */ |
1138 | branch_p = 1; | |
1139 | offset = 4 * X_DISP19 (insn); | |
c906108c | 1140 | } |
c893be75 MK |
1141 | else if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3a) |
1142 | { | |
1143 | /* Trap instruction (TRAP). */ | |
1144 | return gdbarch_tdep (arch)->step_trap (insn); | |
1145 | } | |
386c036b MK |
1146 | |
1147 | /* FIXME: Handle DONE and RETRY instructions. */ | |
1148 | ||
386c036b | 1149 | if (branch_p) |
c906108c | 1150 | { |
386c036b | 1151 | if (conditional_p) |
c906108c | 1152 | { |
386c036b MK |
1153 | /* For conditional branches, return nPC + 4 iff the annul |
1154 | bit is 1. */ | |
1155 | return (X_A (insn) ? *npc + 4 : 0); | |
c906108c SS |
1156 | } |
1157 | else | |
1158 | { | |
386c036b MK |
1159 | /* For unconditional branches, return the target if its |
1160 | specified condition is "always" and return nPC + 4 if the | |
1161 | condition is "never". If the annul bit is 1, set *NPC to | |
1162 | zero. */ | |
1163 | if (X_COND (insn) == 0x0) | |
1164 | pc = *npc, offset = 4; | |
1165 | if (X_A (insn)) | |
1166 | *npc = 0; | |
1167 | ||
1168 | gdb_assert (offset != 0); | |
1169 | return pc + offset; | |
c906108c SS |
1170 | } |
1171 | } | |
386c036b MK |
1172 | |
1173 | return 0; | |
c906108c SS |
1174 | } |
1175 | ||
c893be75 MK |
1176 | static CORE_ADDR |
1177 | sparc_step_trap (unsigned long insn) | |
1178 | { | |
1179 | return 0; | |
1180 | } | |
1181 | ||
386c036b MK |
1182 | void |
1183 | sparc_software_single_step (enum target_signal sig, int insert_breakpoints_p) | |
1184 | { | |
c893be75 MK |
1185 | struct gdbarch *arch = current_gdbarch; |
1186 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); | |
8181d85f | 1187 | CORE_ADDR npc, nnpc; |
c906108c | 1188 | |
386c036b MK |
1189 | if (insert_breakpoints_p) |
1190 | { | |
8c3900e4 | 1191 | CORE_ADDR pc, orig_npc; |
c906108c | 1192 | |
386c036b | 1193 | pc = sparc_address_from_register (tdep->pc_regnum); |
8c3900e4 | 1194 | orig_npc = npc = sparc_address_from_register (tdep->npc_regnum); |
c906108c | 1195 | |
386c036b | 1196 | /* Analyze the instruction at PC. */ |
c893be75 | 1197 | nnpc = sparc_analyze_control_transfer (arch, pc, &npc); |
386c036b | 1198 | if (npc != 0) |
8181d85f DJ |
1199 | insert_single_step_breakpoint (npc); |
1200 | ||
386c036b | 1201 | if (nnpc != 0) |
8181d85f | 1202 | insert_single_step_breakpoint (nnpc); |
c906108c | 1203 | |
386c036b | 1204 | /* Assert that we have set at least one breakpoint, and that |
8c3900e4 DJ |
1205 | they're not set at the same spot - unless we're going |
1206 | from here straight to NULL, i.e. a call or jump to 0. */ | |
1207 | gdb_assert (npc != 0 || nnpc != 0 || orig_npc == 0); | |
1208 | gdb_assert (nnpc != npc || orig_npc == 0); | |
60054393 | 1209 | } |
386c036b | 1210 | else |
8181d85f | 1211 | remove_single_step_breakpoints (); |
386c036b MK |
1212 | } |
1213 | ||
1214 | static void | |
1215 | sparc_write_pc (CORE_ADDR pc, ptid_t ptid) | |
1216 | { | |
1217 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
1218 | ||
1219 | write_register_pid (tdep->pc_regnum, pc, ptid); | |
1220 | write_register_pid (tdep->npc_regnum, pc + 4, ptid); | |
1221 | } | |
1222 | \f | |
1223 | /* Unglobalize NAME. */ | |
1224 | ||
1225 | char * | |
1226 | sparc_stabs_unglobalize_name (char *name) | |
1227 | { | |
1228 | /* The Sun compilers (Sun ONE Studio, Forte Developer, Sun WorkShop, | |
1229 | SunPRO) convert file static variables into global values, a | |
1230 | process known as globalization. In order to do this, the | |
1231 | compiler will create a unique prefix and prepend it to each file | |
1232 | static variable. For static variables within a function, this | |
1233 | globalization prefix is followed by the function name (nested | |
1234 | static variables within a function are supposed to generate a | |
1235 | warning message, and are left alone). The procedure is | |
1236 | documented in the Stabs Interface Manual, which is distrubuted | |
1237 | with the compilers, although version 4.0 of the manual seems to | |
1238 | be incorrect in some places, at least for SPARC. The | |
1239 | globalization prefix is encoded into an N_OPT stab, with the form | |
1240 | "G=<prefix>". The globalization prefix always seems to start | |
1241 | with a dollar sign '$'; a dot '.' is used as a seperator. So we | |
1242 | simply strip everything up until the last dot. */ | |
c906108c | 1243 | |
386c036b | 1244 | if (name[0] == '$') |
c906108c | 1245 | { |
386c036b MK |
1246 | char *p = strrchr (name, '.'); |
1247 | if (p) | |
1248 | return p + 1; | |
c906108c | 1249 | } |
c906108c | 1250 | |
386c036b MK |
1251 | return name; |
1252 | } | |
1253 | \f | |
5af923b0 | 1254 | |
a54124c5 MK |
1255 | /* Return the appropriate register set for the core section identified |
1256 | by SECT_NAME and SECT_SIZE. */ | |
1257 | ||
1258 | const struct regset * | |
1259 | sparc_regset_from_core_section (struct gdbarch *gdbarch, | |
1260 | const char *sect_name, size_t sect_size) | |
1261 | { | |
1262 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1263 | ||
c558d81a | 1264 | if (strcmp (sect_name, ".reg") == 0 && sect_size >= tdep->sizeof_gregset) |
a54124c5 MK |
1265 | return tdep->gregset; |
1266 | ||
c558d81a | 1267 | if (strcmp (sect_name, ".reg2") == 0 && sect_size >= tdep->sizeof_fpregset) |
a54124c5 MK |
1268 | return tdep->fpregset; |
1269 | ||
1270 | return NULL; | |
1271 | } | |
1272 | \f | |
1273 | ||
386c036b MK |
1274 | static struct gdbarch * |
1275 | sparc32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
1276 | { | |
1277 | struct gdbarch_tdep *tdep; | |
1278 | struct gdbarch *gdbarch; | |
c906108c | 1279 | |
386c036b MK |
1280 | /* If there is already a candidate, use it. */ |
1281 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
1282 | if (arches != NULL) | |
1283 | return arches->gdbarch; | |
c906108c | 1284 | |
386c036b MK |
1285 | /* Allocate space for the new architecture. */ |
1286 | tdep = XMALLOC (struct gdbarch_tdep); | |
1287 | gdbarch = gdbarch_alloc (&info, tdep); | |
5af923b0 | 1288 | |
386c036b MK |
1289 | tdep->pc_regnum = SPARC32_PC_REGNUM; |
1290 | tdep->npc_regnum = SPARC32_NPC_REGNUM; | |
a54124c5 | 1291 | tdep->gregset = NULL; |
c558d81a | 1292 | tdep->sizeof_gregset = 0; |
a54124c5 | 1293 | tdep->fpregset = NULL; |
c558d81a | 1294 | tdep->sizeof_fpregset = 0; |
386c036b | 1295 | tdep->plt_entry_size = 0; |
c893be75 | 1296 | tdep->step_trap = sparc_step_trap; |
386c036b MK |
1297 | |
1298 | set_gdbarch_long_double_bit (gdbarch, 128); | |
1299 | set_gdbarch_long_double_format (gdbarch, &floatformat_sparc_quad); | |
1300 | ||
1301 | set_gdbarch_num_regs (gdbarch, SPARC32_NUM_REGS); | |
1302 | set_gdbarch_register_name (gdbarch, sparc32_register_name); | |
1303 | set_gdbarch_register_type (gdbarch, sparc32_register_type); | |
1304 | set_gdbarch_num_pseudo_regs (gdbarch, SPARC32_NUM_PSEUDO_REGS); | |
1305 | set_gdbarch_pseudo_register_read (gdbarch, sparc32_pseudo_register_read); | |
1306 | set_gdbarch_pseudo_register_write (gdbarch, sparc32_pseudo_register_write); | |
1307 | ||
1308 | /* Register numbers of various important registers. */ | |
1309 | set_gdbarch_sp_regnum (gdbarch, SPARC_SP_REGNUM); /* %sp */ | |
1310 | set_gdbarch_pc_regnum (gdbarch, SPARC32_PC_REGNUM); /* %pc */ | |
1311 | set_gdbarch_fp0_regnum (gdbarch, SPARC_F0_REGNUM); /* %f0 */ | |
1312 | ||
1313 | /* Call dummy code. */ | |
1314 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); | |
1315 | set_gdbarch_push_dummy_code (gdbarch, sparc32_push_dummy_code); | |
1316 | set_gdbarch_push_dummy_call (gdbarch, sparc32_push_dummy_call); | |
1317 | ||
b9d4c5ed | 1318 | set_gdbarch_return_value (gdbarch, sparc32_return_value); |
386c036b MK |
1319 | set_gdbarch_stabs_argument_has_addr |
1320 | (gdbarch, sparc32_stabs_argument_has_addr); | |
1321 | ||
1322 | set_gdbarch_skip_prologue (gdbarch, sparc32_skip_prologue); | |
1323 | ||
1324 | /* Stack grows downward. */ | |
1325 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
c906108c | 1326 | |
386c036b | 1327 | set_gdbarch_breakpoint_from_pc (gdbarch, sparc_breakpoint_from_pc); |
c906108c | 1328 | |
386c036b | 1329 | set_gdbarch_frame_args_skip (gdbarch, 8); |
5af923b0 | 1330 | |
386c036b | 1331 | set_gdbarch_print_insn (gdbarch, print_insn_sparc); |
c906108c | 1332 | |
386c036b MK |
1333 | set_gdbarch_software_single_step (gdbarch, sparc_software_single_step); |
1334 | set_gdbarch_write_pc (gdbarch, sparc_write_pc); | |
c906108c | 1335 | |
386c036b | 1336 | set_gdbarch_unwind_dummy_id (gdbarch, sparc_unwind_dummy_id); |
c906108c | 1337 | |
386c036b | 1338 | set_gdbarch_unwind_pc (gdbarch, sparc_unwind_pc); |
c906108c | 1339 | |
386c036b MK |
1340 | frame_base_set_default (gdbarch, &sparc32_frame_base); |
1341 | ||
f5a9b87d DM |
1342 | /* Hook in the DWARF CFI frame unwinder. */ |
1343 | dwarf2_frame_set_init_reg (gdbarch, sparc32_dwarf2_frame_init_reg); | |
1344 | /* FIXME: kettenis/20050423: Don't enable the unwinder until the | |
1345 | StackGhost issues have been resolved. */ | |
1346 | ||
b2a0b9b2 DM |
1347 | /* Hook in ABI-specific overrides, if they have been registered. */ |
1348 | gdbarch_init_osabi (info, gdbarch); | |
1349 | ||
386c036b | 1350 | frame_unwind_append_sniffer (gdbarch, sparc32_frame_sniffer); |
c906108c | 1351 | |
a54124c5 | 1352 | /* If we have register sets, enable the generic core file support. */ |
4c72d57a | 1353 | if (tdep->gregset) |
a54124c5 MK |
1354 | set_gdbarch_regset_from_core_section (gdbarch, |
1355 | sparc_regset_from_core_section); | |
1356 | ||
386c036b MK |
1357 | return gdbarch; |
1358 | } | |
1359 | \f | |
1360 | /* Helper functions for dealing with register windows. */ | |
1361 | ||
1362 | void | |
1363 | sparc_supply_rwindow (struct regcache *regcache, CORE_ADDR sp, int regnum) | |
c906108c | 1364 | { |
386c036b | 1365 | int offset = 0; |
e1613aba | 1366 | gdb_byte buf[8]; |
386c036b MK |
1367 | int i; |
1368 | ||
1369 | if (sp & 1) | |
1370 | { | |
1371 | /* Registers are 64-bit. */ | |
1372 | sp += BIAS; | |
c906108c | 1373 | |
386c036b MK |
1374 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1375 | { | |
1376 | if (regnum == i || regnum == -1) | |
1377 | { | |
1378 | target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8); | |
f700a364 MK |
1379 | |
1380 | /* Handle StackGhost. */ | |
1381 | if (i == SPARC_I7_REGNUM) | |
1382 | { | |
1383 | ULONGEST wcookie = sparc_fetch_wcookie (); | |
1384 | ULONGEST i7 = extract_unsigned_integer (buf + offset, 8); | |
1385 | ||
1386 | store_unsigned_integer (buf + offset, 8, i7 ^ wcookie); | |
1387 | } | |
1388 | ||
386c036b MK |
1389 | regcache_raw_supply (regcache, i, buf); |
1390 | } | |
1391 | } | |
1392 | } | |
1393 | else | |
c906108c | 1394 | { |
386c036b MK |
1395 | /* Registers are 32-bit. Toss any sign-extension of the stack |
1396 | pointer. */ | |
1397 | sp &= 0xffffffffUL; | |
c906108c | 1398 | |
386c036b MK |
1399 | /* Clear out the top half of the temporary buffer, and put the |
1400 | register value in the bottom half if we're in 64-bit mode. */ | |
1401 | if (gdbarch_ptr_bit (current_gdbarch) == 64) | |
c906108c | 1402 | { |
386c036b MK |
1403 | memset (buf, 0, 4); |
1404 | offset = 4; | |
1405 | } | |
c906108c | 1406 | |
386c036b MK |
1407 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1408 | { | |
1409 | if (regnum == i || regnum == -1) | |
1410 | { | |
1411 | target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 4), | |
1412 | buf + offset, 4); | |
42cdca6c MK |
1413 | |
1414 | /* Handle StackGhost. */ | |
1415 | if (i == SPARC_I7_REGNUM) | |
1416 | { | |
1417 | ULONGEST wcookie = sparc_fetch_wcookie (); | |
7d34766b | 1418 | ULONGEST i7 = extract_unsigned_integer (buf + offset, 4); |
42cdca6c | 1419 | |
7d34766b | 1420 | store_unsigned_integer (buf + offset, 4, i7 ^ wcookie); |
42cdca6c MK |
1421 | } |
1422 | ||
386c036b MK |
1423 | regcache_raw_supply (regcache, i, buf); |
1424 | } | |
c906108c SS |
1425 | } |
1426 | } | |
c906108c | 1427 | } |
c906108c SS |
1428 | |
1429 | void | |
386c036b MK |
1430 | sparc_collect_rwindow (const struct regcache *regcache, |
1431 | CORE_ADDR sp, int regnum) | |
c906108c | 1432 | { |
386c036b | 1433 | int offset = 0; |
e1613aba | 1434 | gdb_byte buf[8]; |
386c036b | 1435 | int i; |
5af923b0 | 1436 | |
386c036b | 1437 | if (sp & 1) |
5af923b0 | 1438 | { |
386c036b MK |
1439 | /* Registers are 64-bit. */ |
1440 | sp += BIAS; | |
c906108c | 1441 | |
386c036b MK |
1442 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1443 | { | |
1444 | if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i) | |
1445 | { | |
1446 | regcache_raw_collect (regcache, i, buf); | |
f700a364 MK |
1447 | |
1448 | /* Handle StackGhost. */ | |
1449 | if (i == SPARC_I7_REGNUM) | |
1450 | { | |
1451 | ULONGEST wcookie = sparc_fetch_wcookie (); | |
1452 | ULONGEST i7 = extract_unsigned_integer (buf + offset, 8); | |
1453 | ||
1454 | store_unsigned_integer (buf, 8, i7 ^ wcookie); | |
1455 | } | |
1456 | ||
386c036b MK |
1457 | target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8); |
1458 | } | |
1459 | } | |
5af923b0 MS |
1460 | } |
1461 | else | |
1462 | { | |
386c036b MK |
1463 | /* Registers are 32-bit. Toss any sign-extension of the stack |
1464 | pointer. */ | |
1465 | sp &= 0xffffffffUL; | |
1466 | ||
1467 | /* Only use the bottom half if we're in 64-bit mode. */ | |
1468 | if (gdbarch_ptr_bit (current_gdbarch) == 64) | |
1469 | offset = 4; | |
1470 | ||
1471 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
1472 | { | |
1473 | if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i) | |
1474 | { | |
1475 | regcache_raw_collect (regcache, i, buf); | |
42cdca6c MK |
1476 | |
1477 | /* Handle StackGhost. */ | |
1478 | if (i == SPARC_I7_REGNUM) | |
1479 | { | |
1480 | ULONGEST wcookie = sparc_fetch_wcookie (); | |
7d34766b | 1481 | ULONGEST i7 = extract_unsigned_integer (buf + offset, 4); |
42cdca6c | 1482 | |
7d34766b | 1483 | store_unsigned_integer (buf + offset, 4, i7 ^ wcookie); |
42cdca6c MK |
1484 | } |
1485 | ||
386c036b MK |
1486 | target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 4), |
1487 | buf + offset, 4); | |
1488 | } | |
1489 | } | |
5af923b0 | 1490 | } |
c906108c SS |
1491 | } |
1492 | ||
386c036b MK |
1493 | /* Helper functions for dealing with register sets. */ |
1494 | ||
c906108c | 1495 | void |
386c036b MK |
1496 | sparc32_supply_gregset (const struct sparc_gregset *gregset, |
1497 | struct regcache *regcache, | |
1498 | int regnum, const void *gregs) | |
c906108c | 1499 | { |
e1613aba | 1500 | const gdb_byte *regs = gregs; |
386c036b | 1501 | int i; |
5af923b0 | 1502 | |
386c036b MK |
1503 | if (regnum == SPARC32_PSR_REGNUM || regnum == -1) |
1504 | regcache_raw_supply (regcache, SPARC32_PSR_REGNUM, | |
1505 | regs + gregset->r_psr_offset); | |
c906108c | 1506 | |
386c036b MK |
1507 | if (regnum == SPARC32_PC_REGNUM || regnum == -1) |
1508 | regcache_raw_supply (regcache, SPARC32_PC_REGNUM, | |
1509 | regs + gregset->r_pc_offset); | |
5af923b0 | 1510 | |
386c036b MK |
1511 | if (regnum == SPARC32_NPC_REGNUM || regnum == -1) |
1512 | regcache_raw_supply (regcache, SPARC32_NPC_REGNUM, | |
1513 | regs + gregset->r_npc_offset); | |
5af923b0 | 1514 | |
386c036b MK |
1515 | if (regnum == SPARC32_Y_REGNUM || regnum == -1) |
1516 | regcache_raw_supply (regcache, SPARC32_Y_REGNUM, | |
1517 | regs + gregset->r_y_offset); | |
5af923b0 | 1518 | |
386c036b MK |
1519 | if (regnum == SPARC_G0_REGNUM || regnum == -1) |
1520 | regcache_raw_supply (regcache, SPARC_G0_REGNUM, NULL); | |
5af923b0 | 1521 | |
386c036b | 1522 | if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1) |
c906108c | 1523 | { |
386c036b MK |
1524 | int offset = gregset->r_g1_offset; |
1525 | ||
1526 | for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++) | |
1527 | { | |
1528 | if (regnum == i || regnum == -1) | |
1529 | regcache_raw_supply (regcache, i, regs + offset); | |
1530 | offset += 4; | |
1531 | } | |
c906108c | 1532 | } |
386c036b MK |
1533 | |
1534 | if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1) | |
c906108c | 1535 | { |
386c036b MK |
1536 | /* Not all of the register set variants include Locals and |
1537 | Inputs. For those that don't, we read them off the stack. */ | |
1538 | if (gregset->r_l0_offset == -1) | |
1539 | { | |
1540 | ULONGEST sp; | |
1541 | ||
1542 | regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); | |
1543 | sparc_supply_rwindow (regcache, sp, regnum); | |
1544 | } | |
1545 | else | |
1546 | { | |
1547 | int offset = gregset->r_l0_offset; | |
1548 | ||
1549 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
1550 | { | |
1551 | if (regnum == i || regnum == -1) | |
1552 | regcache_raw_supply (regcache, i, regs + offset); | |
1553 | offset += 4; | |
1554 | } | |
1555 | } | |
c906108c SS |
1556 | } |
1557 | } | |
1558 | ||
c5aa993b | 1559 | void |
386c036b MK |
1560 | sparc32_collect_gregset (const struct sparc_gregset *gregset, |
1561 | const struct regcache *regcache, | |
1562 | int regnum, void *gregs) | |
c906108c | 1563 | { |
e1613aba | 1564 | gdb_byte *regs = gregs; |
386c036b | 1565 | int i; |
c5aa993b | 1566 | |
386c036b MK |
1567 | if (regnum == SPARC32_PSR_REGNUM || regnum == -1) |
1568 | regcache_raw_collect (regcache, SPARC32_PSR_REGNUM, | |
1569 | regs + gregset->r_psr_offset); | |
60054393 | 1570 | |
386c036b MK |
1571 | if (regnum == SPARC32_PC_REGNUM || regnum == -1) |
1572 | regcache_raw_collect (regcache, SPARC32_PC_REGNUM, | |
1573 | regs + gregset->r_pc_offset); | |
1574 | ||
1575 | if (regnum == SPARC32_NPC_REGNUM || regnum == -1) | |
1576 | regcache_raw_collect (regcache, SPARC32_NPC_REGNUM, | |
1577 | regs + gregset->r_npc_offset); | |
5af923b0 | 1578 | |
386c036b MK |
1579 | if (regnum == SPARC32_Y_REGNUM || regnum == -1) |
1580 | regcache_raw_collect (regcache, SPARC32_Y_REGNUM, | |
1581 | regs + gregset->r_y_offset); | |
1582 | ||
1583 | if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1) | |
5af923b0 | 1584 | { |
386c036b MK |
1585 | int offset = gregset->r_g1_offset; |
1586 | ||
1587 | /* %g0 is always zero. */ | |
1588 | for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++) | |
1589 | { | |
1590 | if (regnum == i || regnum == -1) | |
1591 | regcache_raw_collect (regcache, i, regs + offset); | |
1592 | offset += 4; | |
1593 | } | |
5af923b0 | 1594 | } |
386c036b MK |
1595 | |
1596 | if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1) | |
5af923b0 | 1597 | { |
386c036b MK |
1598 | /* Not all of the register set variants include Locals and |
1599 | Inputs. For those that don't, we read them off the stack. */ | |
1600 | if (gregset->r_l0_offset != -1) | |
1601 | { | |
1602 | int offset = gregset->r_l0_offset; | |
1603 | ||
1604 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
1605 | { | |
1606 | if (regnum == i || regnum == -1) | |
1607 | regcache_raw_collect (regcache, i, regs + offset); | |
1608 | offset += 4; | |
1609 | } | |
1610 | } | |
5af923b0 | 1611 | } |
c906108c SS |
1612 | } |
1613 | ||
c906108c | 1614 | void |
386c036b MK |
1615 | sparc32_supply_fpregset (struct regcache *regcache, |
1616 | int regnum, const void *fpregs) | |
c906108c | 1617 | { |
e1613aba | 1618 | const gdb_byte *regs = fpregs; |
386c036b | 1619 | int i; |
60054393 | 1620 | |
386c036b | 1621 | for (i = 0; i < 32; i++) |
c906108c | 1622 | { |
386c036b MK |
1623 | if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1) |
1624 | regcache_raw_supply (regcache, SPARC_F0_REGNUM + i, regs + (i * 4)); | |
c906108c | 1625 | } |
5af923b0 | 1626 | |
386c036b MK |
1627 | if (regnum == SPARC32_FSR_REGNUM || regnum == -1) |
1628 | regcache_raw_supply (regcache, SPARC32_FSR_REGNUM, regs + (32 * 4) + 4); | |
c906108c SS |
1629 | } |
1630 | ||
386c036b MK |
1631 | void |
1632 | sparc32_collect_fpregset (const struct regcache *regcache, | |
1633 | int regnum, void *fpregs) | |
c906108c | 1634 | { |
e1613aba | 1635 | gdb_byte *regs = fpregs; |
386c036b | 1636 | int i; |
c906108c | 1637 | |
386c036b MK |
1638 | for (i = 0; i < 32; i++) |
1639 | { | |
1640 | if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1) | |
1641 | regcache_raw_collect (regcache, SPARC_F0_REGNUM + i, regs + (i * 4)); | |
1642 | } | |
c906108c | 1643 | |
386c036b MK |
1644 | if (regnum == SPARC32_FSR_REGNUM || regnum == -1) |
1645 | regcache_raw_collect (regcache, SPARC32_FSR_REGNUM, regs + (32 * 4) + 4); | |
c906108c | 1646 | } |
c906108c | 1647 | \f |
c906108c | 1648 | |
386c036b | 1649 | /* SunOS 4. */ |
c906108c | 1650 | |
386c036b MK |
1651 | /* From <machine/reg.h>. */ |
1652 | const struct sparc_gregset sparc32_sunos4_gregset = | |
c906108c | 1653 | { |
386c036b MK |
1654 | 0 * 4, /* %psr */ |
1655 | 1 * 4, /* %pc */ | |
1656 | 2 * 4, /* %npc */ | |
1657 | 3 * 4, /* %y */ | |
1658 | -1, /* %wim */ | |
1659 | -1, /* %tbr */ | |
1660 | 4 * 4, /* %g1 */ | |
1661 | -1 /* %l0 */ | |
1662 | }; | |
1663 | \f | |
c906108c | 1664 | |
386c036b MK |
1665 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
1666 | void _initialize_sparc_tdep (void); | |
c906108c SS |
1667 | |
1668 | void | |
386c036b | 1669 | _initialize_sparc_tdep (void) |
c906108c | 1670 | { |
386c036b | 1671 | register_gdbarch_init (bfd_arch_sparc, sparc32_gdbarch_init); |
2d457077 MK |
1672 | |
1673 | /* Initialize the SPARC-specific register types. */ | |
1674 | sparc_init_types(); | |
ef3cf062 | 1675 | } |