Commit | Line | Data |
---|---|---|
386c036b | 1 | /* Target-dependent code for SPARC. |
cda5a58a | 2 | |
6aba47ca | 3 | Copyright (C) 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b JM |
17 | You should have received a copy of the GNU General Public License |
18 | along with this program; if not, write to the Free Software | |
197e01b6 EZ |
19 | Foundation, Inc., 51 Franklin Street, Fifth Floor, |
20 | Boston, MA 02110-1301, USA. */ | |
c906108c | 21 | |
c906108c | 22 | #include "defs.h" |
5af923b0 | 23 | #include "arch-utils.h" |
386c036b | 24 | #include "dis-asm.h" |
f5a9b87d | 25 | #include "dwarf2-frame.h" |
386c036b | 26 | #include "floatformat.h" |
c906108c | 27 | #include "frame.h" |
386c036b MK |
28 | #include "frame-base.h" |
29 | #include "frame-unwind.h" | |
30 | #include "gdbcore.h" | |
31 | #include "gdbtypes.h" | |
c906108c | 32 | #include "inferior.h" |
386c036b MK |
33 | #include "symtab.h" |
34 | #include "objfiles.h" | |
35 | #include "osabi.h" | |
36 | #include "regcache.h" | |
c906108c SS |
37 | #include "target.h" |
38 | #include "value.h" | |
c906108c | 39 | |
43bd9a9e | 40 | #include "gdb_assert.h" |
386c036b | 41 | #include "gdb_string.h" |
c906108c | 42 | |
386c036b | 43 | #include "sparc-tdep.h" |
c906108c | 44 | |
a54124c5 MK |
45 | struct regset; |
46 | ||
9eb42ed1 MK |
47 | /* This file implements the SPARC 32-bit ABI as defined by the section |
48 | "Low-Level System Information" of the SPARC Compliance Definition | |
49 | (SCD) 2.4.1, which is the 32-bit System V psABI for SPARC. The SCD | |
f2e7c15d | 50 | lists changes with respect to the original 32-bit psABI as defined |
9eb42ed1 | 51 | in the "System V ABI, SPARC Processor Supplement". |
386c036b MK |
52 | |
53 | Note that if we talk about SunOS, we mean SunOS 4.x, which was | |
54 | BSD-based, which is sometimes (retroactively?) referred to as | |
55 | Solaris 1.x. If we talk about Solaris we mean Solaris 2.x and | |
56 | above (Solaris 7, 8 and 9 are nothing but Solaris 2.7, 2.8 and 2.9 | |
57 | suffering from severe version number inflation). Solaris 2.x is | |
58 | also known as SunOS 5.x, since that's what uname(1) says. Solaris | |
59 | 2.x is SVR4-based. */ | |
60 | ||
61 | /* Please use the sparc32_-prefix for 32-bit specific code, the | |
62 | sparc64_-prefix for 64-bit specific code and the sparc_-prefix for | |
63 | code that can handle both. The 64-bit specific code lives in | |
64 | sparc64-tdep.c; don't add any here. */ | |
65 | ||
66 | /* The SPARC Floating-Point Quad-Precision format is similar to | |
67 | big-endian IA-64 Quad-recision format. */ | |
8da61cc4 | 68 | #define floatformats_sparc_quad floatformats_ia64_quad |
386c036b MK |
69 | |
70 | /* The stack pointer is offset from the stack frame by a BIAS of 2047 | |
71 | (0x7ff) for 64-bit code. BIAS is likely to be defined on SPARC | |
72 | hosts, so undefine it first. */ | |
73 | #undef BIAS | |
74 | #define BIAS 2047 | |
75 | ||
76 | /* Macros to extract fields from SPARC instructions. */ | |
c906108c SS |
77 | #define X_OP(i) (((i) >> 30) & 0x3) |
78 | #define X_RD(i) (((i) >> 25) & 0x1f) | |
79 | #define X_A(i) (((i) >> 29) & 1) | |
80 | #define X_COND(i) (((i) >> 25) & 0xf) | |
81 | #define X_OP2(i) (((i) >> 22) & 0x7) | |
82 | #define X_IMM22(i) ((i) & 0x3fffff) | |
83 | #define X_OP3(i) (((i) >> 19) & 0x3f) | |
075ccec8 | 84 | #define X_RS1(i) (((i) >> 14) & 0x1f) |
b0b92586 | 85 | #define X_RS2(i) ((i) & 0x1f) |
c906108c | 86 | #define X_I(i) (((i) >> 13) & 1) |
c906108c | 87 | /* Sign extension macros. */ |
c906108c | 88 | #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000) |
c906108c | 89 | #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000) |
075ccec8 | 90 | #define X_SIMM13(i) ((((i) & 0x1fff) ^ 0x1000) - 0x1000) |
c906108c | 91 | |
386c036b MK |
92 | /* Fetch the instruction at PC. Instructions are always big-endian |
93 | even if the processor operates in little-endian mode. */ | |
94 | ||
95 | unsigned long | |
96 | sparc_fetch_instruction (CORE_ADDR pc) | |
c906108c | 97 | { |
e1613aba | 98 | gdb_byte buf[4]; |
386c036b MK |
99 | unsigned long insn; |
100 | int i; | |
101 | ||
690668cc | 102 | /* If we can't read the instruction at PC, return zero. */ |
b5bf31df | 103 | if (read_memory_nobpt (pc, buf, sizeof (buf))) |
690668cc | 104 | return 0; |
c906108c | 105 | |
386c036b MK |
106 | insn = 0; |
107 | for (i = 0; i < sizeof (buf); i++) | |
108 | insn = (insn << 8) | buf[i]; | |
109 | return insn; | |
110 | } | |
42cdca6c MK |
111 | \f |
112 | ||
5465445a JB |
113 | /* Return non-zero if the instruction corresponding to PC is an "unimp" |
114 | instruction. */ | |
115 | ||
116 | static int | |
117 | sparc_is_unimp_insn (CORE_ADDR pc) | |
118 | { | |
119 | const unsigned long insn = sparc_fetch_instruction (pc); | |
120 | ||
121 | return ((insn & 0xc1c00000) == 0); | |
122 | } | |
123 | ||
42cdca6c MK |
124 | /* OpenBSD/sparc includes StackGhost, which according to the author's |
125 | website http://stackghost.cerias.purdue.edu "... transparently and | |
126 | automatically protects applications' stack frames; more | |
127 | specifically, it guards the return pointers. The protection | |
128 | mechanisms require no application source or binary modification and | |
129 | imposes only a negligible performance penalty." | |
130 | ||
131 | The same website provides the following description of how | |
132 | StackGhost works: | |
133 | ||
134 | "StackGhost interfaces with the kernel trap handler that would | |
135 | normally write out registers to the stack and the handler that | |
136 | would read them back in. By XORing a cookie into the | |
137 | return-address saved in the user stack when it is actually written | |
138 | to the stack, and then XOR it out when the return-address is pulled | |
139 | from the stack, StackGhost can cause attacker corrupted return | |
140 | pointers to behave in a manner the attacker cannot predict. | |
141 | StackGhost can also use several unused bits in the return pointer | |
142 | to detect a smashed return pointer and abort the process." | |
143 | ||
144 | For GDB this means that whenever we're reading %i7 from a stack | |
145 | frame's window save area, we'll have to XOR the cookie. | |
146 | ||
147 | More information on StackGuard can be found on in: | |
148 | ||
149 | Mike Frantzen and Mike Shuey. "StackGhost: Hardware Facilitated | |
150 | Stack Protection." 2001. Published in USENIX Security Symposium | |
151 | '01. */ | |
152 | ||
153 | /* Fetch StackGhost Per-Process XOR cookie. */ | |
154 | ||
155 | ULONGEST | |
156 | sparc_fetch_wcookie (void) | |
157 | { | |
baf92889 | 158 | struct target_ops *ops = ¤t_target; |
e1613aba | 159 | gdb_byte buf[8]; |
baf92889 MK |
160 | int len; |
161 | ||
13547ab6 | 162 | len = target_read (ops, TARGET_OBJECT_WCOOKIE, NULL, buf, 0, 8); |
baf92889 MK |
163 | if (len == -1) |
164 | return 0; | |
42cdca6c | 165 | |
baf92889 MK |
166 | /* We should have either an 32-bit or an 64-bit cookie. */ |
167 | gdb_assert (len == 4 || len == 8); | |
168 | ||
169 | return extract_unsigned_integer (buf, len); | |
170 | } | |
386c036b | 171 | \f |
baf92889 | 172 | |
386c036b | 173 | /* Return the contents if register REGNUM as an address. */ |
c906108c | 174 | |
c893be75 | 175 | CORE_ADDR |
386c036b MK |
176 | sparc_address_from_register (int regnum) |
177 | { | |
178 | ULONGEST addr; | |
c906108c | 179 | |
386c036b MK |
180 | regcache_cooked_read_unsigned (current_regcache, regnum, &addr); |
181 | return addr; | |
182 | } | |
183 | \f | |
c906108c | 184 | |
386c036b MK |
185 | /* The functions on this page are intended to be used to classify |
186 | function arguments. */ | |
c906108c | 187 | |
386c036b | 188 | /* Check whether TYPE is "Integral or Pointer". */ |
c906108c | 189 | |
386c036b MK |
190 | static int |
191 | sparc_integral_or_pointer_p (const struct type *type) | |
c906108c | 192 | { |
80ad1639 MK |
193 | int len = TYPE_LENGTH (type); |
194 | ||
386c036b | 195 | switch (TYPE_CODE (type)) |
c906108c | 196 | { |
386c036b MK |
197 | case TYPE_CODE_INT: |
198 | case TYPE_CODE_BOOL: | |
199 | case TYPE_CODE_CHAR: | |
200 | case TYPE_CODE_ENUM: | |
201 | case TYPE_CODE_RANGE: | |
80ad1639 MK |
202 | /* We have byte, half-word, word and extended-word/doubleword |
203 | integral types. The doubleword is an extension to the | |
204 | original 32-bit ABI by the SCD 2.4.x. */ | |
205 | return (len == 1 || len == 2 || len == 4 || len == 8); | |
386c036b MK |
206 | case TYPE_CODE_PTR: |
207 | case TYPE_CODE_REF: | |
80ad1639 MK |
208 | /* Allow either 32-bit or 64-bit pointers. */ |
209 | return (len == 4 || len == 8); | |
386c036b MK |
210 | default: |
211 | break; | |
212 | } | |
c906108c | 213 | |
386c036b MK |
214 | return 0; |
215 | } | |
c906108c | 216 | |
386c036b | 217 | /* Check whether TYPE is "Floating". */ |
c906108c | 218 | |
386c036b MK |
219 | static int |
220 | sparc_floating_p (const struct type *type) | |
221 | { | |
222 | switch (TYPE_CODE (type)) | |
c906108c | 223 | { |
386c036b MK |
224 | case TYPE_CODE_FLT: |
225 | { | |
226 | int len = TYPE_LENGTH (type); | |
227 | return (len == 4 || len == 8 || len == 16); | |
228 | } | |
229 | default: | |
230 | break; | |
231 | } | |
232 | ||
233 | return 0; | |
234 | } | |
c906108c | 235 | |
386c036b | 236 | /* Check whether TYPE is "Structure or Union". */ |
c906108c | 237 | |
386c036b MK |
238 | static int |
239 | sparc_structure_or_union_p (const struct type *type) | |
240 | { | |
241 | switch (TYPE_CODE (type)) | |
242 | { | |
243 | case TYPE_CODE_STRUCT: | |
244 | case TYPE_CODE_UNION: | |
245 | return 1; | |
246 | default: | |
247 | break; | |
c906108c | 248 | } |
386c036b MK |
249 | |
250 | return 0; | |
c906108c | 251 | } |
386c036b MK |
252 | |
253 | /* Register information. */ | |
254 | ||
255 | static const char *sparc32_register_names[] = | |
5af923b0 | 256 | { |
386c036b MK |
257 | "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", |
258 | "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", | |
259 | "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", | |
260 | "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7", | |
261 | ||
262 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
263 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
264 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
265 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
266 | ||
267 | "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr" | |
5af923b0 MS |
268 | }; |
269 | ||
386c036b MK |
270 | /* Total number of registers. */ |
271 | #define SPARC32_NUM_REGS ARRAY_SIZE (sparc32_register_names) | |
c906108c | 272 | |
386c036b MK |
273 | /* We provide the aliases %d0..%d30 for the floating registers as |
274 | "psuedo" registers. */ | |
275 | ||
276 | static const char *sparc32_pseudo_register_names[] = | |
277 | { | |
278 | "d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14", | |
279 | "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30" | |
280 | }; | |
281 | ||
282 | /* Total number of pseudo registers. */ | |
283 | #define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names) | |
284 | ||
285 | /* Return the name of register REGNUM. */ | |
286 | ||
287 | static const char * | |
288 | sparc32_register_name (int regnum) | |
289 | { | |
290 | if (regnum >= 0 && regnum < SPARC32_NUM_REGS) | |
291 | return sparc32_register_names[regnum]; | |
292 | ||
293 | if (regnum < SPARC32_NUM_REGS + SPARC32_NUM_PSEUDO_REGS) | |
294 | return sparc32_pseudo_register_names[regnum - SPARC32_NUM_REGS]; | |
295 | ||
296 | return NULL; | |
297 | } | |
2d457077 MK |
298 | \f |
299 | ||
300 | /* Type for %psr. */ | |
301 | struct type *sparc_psr_type; | |
302 | ||
303 | /* Type for %fsr. */ | |
304 | struct type *sparc_fsr_type; | |
305 | ||
306 | /* Construct types for ISA-specific registers. */ | |
307 | ||
308 | static void | |
309 | sparc_init_types (void) | |
310 | { | |
311 | struct type *type; | |
312 | ||
313 | type = init_flags_type ("builtin_type_sparc_psr", 4); | |
314 | append_flags_type_flag (type, 5, "ET"); | |
315 | append_flags_type_flag (type, 6, "PS"); | |
316 | append_flags_type_flag (type, 7, "S"); | |
317 | append_flags_type_flag (type, 12, "EF"); | |
318 | append_flags_type_flag (type, 13, "EC"); | |
319 | sparc_psr_type = type; | |
320 | ||
321 | type = init_flags_type ("builtin_type_sparc_fsr", 4); | |
322 | append_flags_type_flag (type, 0, "NXA"); | |
323 | append_flags_type_flag (type, 1, "DZA"); | |
324 | append_flags_type_flag (type, 2, "UFA"); | |
325 | append_flags_type_flag (type, 3, "OFA"); | |
326 | append_flags_type_flag (type, 4, "NVA"); | |
327 | append_flags_type_flag (type, 5, "NXC"); | |
328 | append_flags_type_flag (type, 6, "DZC"); | |
329 | append_flags_type_flag (type, 7, "UFC"); | |
330 | append_flags_type_flag (type, 8, "OFC"); | |
331 | append_flags_type_flag (type, 9, "NVC"); | |
332 | append_flags_type_flag (type, 22, "NS"); | |
333 | append_flags_type_flag (type, 23, "NXM"); | |
334 | append_flags_type_flag (type, 24, "DZM"); | |
335 | append_flags_type_flag (type, 25, "UFM"); | |
336 | append_flags_type_flag (type, 26, "OFM"); | |
337 | append_flags_type_flag (type, 27, "NVM"); | |
338 | sparc_fsr_type = type; | |
339 | } | |
386c036b MK |
340 | |
341 | /* Return the GDB type object for the "standard" data type of data in | |
342 | register REGNUM. */ | |
343 | ||
344 | static struct type * | |
345 | sparc32_register_type (struct gdbarch *gdbarch, int regnum) | |
346 | { | |
347 | if (regnum >= SPARC_F0_REGNUM && regnum <= SPARC_F31_REGNUM) | |
348 | return builtin_type_float; | |
349 | ||
350 | if (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM) | |
351 | return builtin_type_double; | |
352 | ||
353 | if (regnum == SPARC_SP_REGNUM || regnum == SPARC_FP_REGNUM) | |
354 | return builtin_type_void_data_ptr; | |
355 | ||
356 | if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM) | |
357 | return builtin_type_void_func_ptr; | |
358 | ||
2d457077 MK |
359 | if (regnum == SPARC32_PSR_REGNUM) |
360 | return sparc_psr_type; | |
361 | ||
362 | if (regnum == SPARC32_FSR_REGNUM) | |
363 | return sparc_fsr_type; | |
364 | ||
386c036b MK |
365 | return builtin_type_int32; |
366 | } | |
367 | ||
368 | static void | |
369 | sparc32_pseudo_register_read (struct gdbarch *gdbarch, | |
370 | struct regcache *regcache, | |
e1613aba | 371 | int regnum, gdb_byte *buf) |
386c036b MK |
372 | { |
373 | gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM); | |
374 | ||
375 | regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM); | |
376 | regcache_raw_read (regcache, regnum, buf); | |
e1613aba | 377 | regcache_raw_read (regcache, regnum + 1, buf + 4); |
386c036b MK |
378 | } |
379 | ||
380 | static void | |
381 | sparc32_pseudo_register_write (struct gdbarch *gdbarch, | |
382 | struct regcache *regcache, | |
e1613aba | 383 | int regnum, const gdb_byte *buf) |
386c036b MK |
384 | { |
385 | gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM); | |
386 | ||
387 | regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM); | |
388 | regcache_raw_write (regcache, regnum, buf); | |
e1613aba | 389 | regcache_raw_write (regcache, regnum + 1, buf + 4); |
386c036b MK |
390 | } |
391 | \f | |
392 | ||
393 | static CORE_ADDR | |
394 | sparc32_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, | |
395 | CORE_ADDR funcaddr, int using_gcc, | |
396 | struct value **args, int nargs, | |
397 | struct type *value_type, | |
398 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr) | |
c906108c | 399 | { |
386c036b MK |
400 | *bp_addr = sp - 4; |
401 | *real_pc = funcaddr; | |
402 | ||
403 | if (using_struct_return (value_type, using_gcc)) | |
c906108c | 404 | { |
e1613aba | 405 | gdb_byte buf[4]; |
386c036b MK |
406 | |
407 | /* This is an UNIMP instruction. */ | |
408 | store_unsigned_integer (buf, 4, TYPE_LENGTH (value_type) & 0x1fff); | |
409 | write_memory (sp - 8, buf, 4); | |
410 | return sp - 8; | |
c906108c SS |
411 | } |
412 | ||
386c036b MK |
413 | return sp - 4; |
414 | } | |
415 | ||
416 | static CORE_ADDR | |
417 | sparc32_store_arguments (struct regcache *regcache, int nargs, | |
418 | struct value **args, CORE_ADDR sp, | |
419 | int struct_return, CORE_ADDR struct_addr) | |
420 | { | |
421 | /* Number of words in the "parameter array". */ | |
422 | int num_elements = 0; | |
423 | int element = 0; | |
424 | int i; | |
425 | ||
426 | for (i = 0; i < nargs; i++) | |
c906108c | 427 | { |
4991999e | 428 | struct type *type = value_type (args[i]); |
386c036b MK |
429 | int len = TYPE_LENGTH (type); |
430 | ||
431 | if (sparc_structure_or_union_p (type) | |
432 | || (sparc_floating_p (type) && len == 16)) | |
c906108c | 433 | { |
386c036b MK |
434 | /* Structure, Union and Quad-Precision Arguments. */ |
435 | sp -= len; | |
436 | ||
437 | /* Use doubleword alignment for these values. That's always | |
438 | correct, and wasting a few bytes shouldn't be a problem. */ | |
439 | sp &= ~0x7; | |
440 | ||
0fd88904 | 441 | write_memory (sp, value_contents (args[i]), len); |
386c036b MK |
442 | args[i] = value_from_pointer (lookup_pointer_type (type), sp); |
443 | num_elements++; | |
444 | } | |
445 | else if (sparc_floating_p (type)) | |
446 | { | |
447 | /* Floating arguments. */ | |
448 | gdb_assert (len == 4 || len == 8); | |
449 | num_elements += (len / 4); | |
c906108c | 450 | } |
c5aa993b JM |
451 | else |
452 | { | |
386c036b MK |
453 | /* Integral and pointer arguments. */ |
454 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
455 | ||
456 | if (len < 4) | |
457 | args[i] = value_cast (builtin_type_int32, args[i]); | |
458 | num_elements += ((len + 3) / 4); | |
c5aa993b | 459 | } |
c906108c | 460 | } |
c906108c | 461 | |
386c036b MK |
462 | /* Always allocate at least six words. */ |
463 | sp -= max (6, num_elements) * 4; | |
c906108c | 464 | |
386c036b MK |
465 | /* The psABI says that "Software convention requires space for the |
466 | struct/union return value pointer, even if the word is unused." */ | |
467 | sp -= 4; | |
c906108c | 468 | |
386c036b MK |
469 | /* The psABI says that "Although software convention and the |
470 | operating system require every stack frame to be doubleword | |
471 | aligned." */ | |
472 | sp &= ~0x7; | |
c906108c | 473 | |
386c036b | 474 | for (i = 0; i < nargs; i++) |
c906108c | 475 | { |
0fd88904 | 476 | const bfd_byte *valbuf = value_contents (args[i]); |
4991999e | 477 | struct type *type = value_type (args[i]); |
386c036b | 478 | int len = TYPE_LENGTH (type); |
c906108c | 479 | |
386c036b | 480 | gdb_assert (len == 4 || len == 8); |
c906108c | 481 | |
386c036b MK |
482 | if (element < 6) |
483 | { | |
484 | int regnum = SPARC_O0_REGNUM + element; | |
c906108c | 485 | |
386c036b MK |
486 | regcache_cooked_write (regcache, regnum, valbuf); |
487 | if (len > 4 && element < 5) | |
488 | regcache_cooked_write (regcache, regnum + 1, valbuf + 4); | |
489 | } | |
5af923b0 | 490 | |
386c036b MK |
491 | /* Always store the argument in memory. */ |
492 | write_memory (sp + 4 + element * 4, valbuf, len); | |
493 | element += len / 4; | |
494 | } | |
c906108c | 495 | |
386c036b | 496 | gdb_assert (element == num_elements); |
c906108c | 497 | |
386c036b | 498 | if (struct_return) |
c906108c | 499 | { |
e1613aba | 500 | gdb_byte buf[4]; |
c906108c | 501 | |
386c036b MK |
502 | store_unsigned_integer (buf, 4, struct_addr); |
503 | write_memory (sp, buf, 4); | |
504 | } | |
c906108c | 505 | |
386c036b | 506 | return sp; |
c906108c SS |
507 | } |
508 | ||
386c036b | 509 | static CORE_ADDR |
7d9b040b | 510 | sparc32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
386c036b MK |
511 | struct regcache *regcache, CORE_ADDR bp_addr, |
512 | int nargs, struct value **args, CORE_ADDR sp, | |
513 | int struct_return, CORE_ADDR struct_addr) | |
c906108c | 514 | { |
386c036b MK |
515 | CORE_ADDR call_pc = (struct_return ? (bp_addr - 12) : (bp_addr - 8)); |
516 | ||
517 | /* Set return address. */ | |
518 | regcache_cooked_write_unsigned (regcache, SPARC_O7_REGNUM, call_pc); | |
519 | ||
520 | /* Set up function arguments. */ | |
521 | sp = sparc32_store_arguments (regcache, nargs, args, sp, | |
522 | struct_return, struct_addr); | |
523 | ||
524 | /* Allocate the 16-word window save area. */ | |
525 | sp -= 16 * 4; | |
c906108c | 526 | |
386c036b MK |
527 | /* Stack should be doubleword aligned at this point. */ |
528 | gdb_assert (sp % 8 == 0); | |
c906108c | 529 | |
386c036b MK |
530 | /* Finally, update the stack pointer. */ |
531 | regcache_cooked_write_unsigned (regcache, SPARC_SP_REGNUM, sp); | |
532 | ||
533 | return sp; | |
534 | } | |
535 | \f | |
c906108c | 536 | |
386c036b MK |
537 | /* Use the program counter to determine the contents and size of a |
538 | breakpoint instruction. Return a pointer to a string of bytes that | |
539 | encode a breakpoint instruction, store the length of the string in | |
540 | *LEN and optionally adjust *PC to point to the correct memory | |
541 | location for inserting the breakpoint. */ | |
542 | ||
e1613aba | 543 | static const gdb_byte * |
386c036b MK |
544 | sparc_breakpoint_from_pc (CORE_ADDR *pc, int *len) |
545 | { | |
864a1a37 | 546 | static const gdb_byte break_insn[] = { 0x91, 0xd0, 0x20, 0x01 }; |
c5aa993b | 547 | |
386c036b MK |
548 | *len = sizeof (break_insn); |
549 | return break_insn; | |
c906108c | 550 | } |
386c036b | 551 | \f |
c906108c | 552 | |
386c036b | 553 | /* Allocate and initialize a frame cache. */ |
c906108c | 554 | |
386c036b MK |
555 | static struct sparc_frame_cache * |
556 | sparc_alloc_frame_cache (void) | |
557 | { | |
558 | struct sparc_frame_cache *cache; | |
559 | int i; | |
c906108c | 560 | |
386c036b | 561 | cache = FRAME_OBSTACK_ZALLOC (struct sparc_frame_cache); |
c906108c | 562 | |
386c036b MK |
563 | /* Base address. */ |
564 | cache->base = 0; | |
565 | cache->pc = 0; | |
c906108c | 566 | |
386c036b MK |
567 | /* Frameless until proven otherwise. */ |
568 | cache->frameless_p = 1; | |
569 | ||
570 | cache->struct_return_p = 0; | |
571 | ||
572 | return cache; | |
573 | } | |
574 | ||
b0b92586 JB |
575 | /* GCC generates several well-known sequences of instructions at the begining |
576 | of each function prologue when compiling with -fstack-check. If one of | |
577 | such sequences starts at START_PC, then return the address of the | |
578 | instruction immediately past this sequence. Otherwise, return START_PC. */ | |
579 | ||
580 | static CORE_ADDR | |
581 | sparc_skip_stack_check (const CORE_ADDR start_pc) | |
582 | { | |
583 | CORE_ADDR pc = start_pc; | |
584 | unsigned long insn; | |
585 | int offset_stack_checking_sequence = 0; | |
586 | ||
587 | /* With GCC, all stack checking sequences begin with the same two | |
588 | instructions. */ | |
589 | ||
590 | /* sethi <some immediate>,%g1 */ | |
591 | insn = sparc_fetch_instruction (pc); | |
592 | pc = pc + 4; | |
593 | if (!(X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 1)) | |
594 | return start_pc; | |
595 | ||
596 | /* sub %sp, %g1, %g1 */ | |
597 | insn = sparc_fetch_instruction (pc); | |
598 | pc = pc + 4; | |
599 | if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn) | |
600 | && X_RD (insn) == 1 && X_RS1 (insn) == 14 && X_RS2 (insn) == 1)) | |
601 | return start_pc; | |
602 | ||
603 | insn = sparc_fetch_instruction (pc); | |
604 | pc = pc + 4; | |
605 | ||
606 | /* First possible sequence: | |
607 | [first two instructions above] | |
608 | clr [%g1 - some immediate] */ | |
609 | ||
610 | /* clr [%g1 - some immediate] */ | |
611 | if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) | |
612 | && X_RS1 (insn) == 1 && X_RD (insn) == 0) | |
613 | { | |
614 | /* Valid stack-check sequence, return the new PC. */ | |
615 | return pc; | |
616 | } | |
617 | ||
618 | /* Second possible sequence: A small number of probes. | |
619 | [first two instructions above] | |
620 | clr [%g1] | |
621 | add %g1, -<some immediate>, %g1 | |
622 | clr [%g1] | |
623 | [repeat the two instructions above any (small) number of times] | |
624 | clr [%g1 - some immediate] */ | |
625 | ||
626 | /* clr [%g1] */ | |
627 | else if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn) | |
628 | && X_RS1 (insn) == 1 && X_RD (insn) == 0) | |
629 | { | |
630 | while (1) | |
631 | { | |
632 | /* add %g1, -<some immediate>, %g1 */ | |
633 | insn = sparc_fetch_instruction (pc); | |
634 | pc = pc + 4; | |
635 | if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn) | |
636 | && X_RS1 (insn) == 1 && X_RD (insn) == 1)) | |
637 | break; | |
638 | ||
639 | /* clr [%g1] */ | |
640 | insn = sparc_fetch_instruction (pc); | |
641 | pc = pc + 4; | |
642 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn) | |
643 | && X_RD (insn) == 0 && X_RS1 (insn) == 1)) | |
644 | return start_pc; | |
645 | } | |
646 | ||
647 | /* clr [%g1 - some immediate] */ | |
648 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) | |
649 | && X_RS1 (insn) == 1 && X_RD (insn) == 0)) | |
650 | return start_pc; | |
651 | ||
652 | /* We found a valid stack-check sequence, return the new PC. */ | |
653 | return pc; | |
654 | } | |
655 | ||
656 | /* Third sequence: A probing loop. | |
657 | [first two instructions above] | |
658 | sethi <some immediate>, %g4 | |
659 | sub %g1, %g4, %g4 | |
660 | cmp %g1, %g4 | |
661 | be <disp> | |
662 | add %g1, -<some immediate>, %g1 | |
663 | ba <disp> | |
664 | clr [%g1] | |
665 | clr [%g4 - some immediate] */ | |
666 | ||
667 | /* sethi <some immediate>, %g4 */ | |
668 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 4) | |
669 | { | |
670 | /* sub %g1, %g4, %g4 */ | |
671 | insn = sparc_fetch_instruction (pc); | |
672 | pc = pc + 4; | |
673 | if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn) | |
674 | && X_RD (insn) == 4 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4)) | |
675 | return start_pc; | |
676 | ||
677 | /* cmp %g1, %g4 */ | |
678 | insn = sparc_fetch_instruction (pc); | |
679 | pc = pc + 4; | |
680 | if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x14 && !X_I(insn) | |
681 | && X_RD (insn) == 0 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4)) | |
682 | return start_pc; | |
683 | ||
684 | /* be <disp> */ | |
685 | insn = sparc_fetch_instruction (pc); | |
686 | pc = pc + 4; | |
687 | if (!(X_OP (insn) == 0 && X_COND (insn) == 0x1)) | |
688 | return start_pc; | |
689 | ||
690 | /* add %g1, -<some immediate>, %g1 */ | |
691 | insn = sparc_fetch_instruction (pc); | |
692 | pc = pc + 4; | |
693 | if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn) | |
694 | && X_RS1 (insn) == 1 && X_RD (insn) == 1)) | |
695 | return start_pc; | |
696 | ||
697 | /* ba <disp> */ | |
698 | insn = sparc_fetch_instruction (pc); | |
699 | pc = pc + 4; | |
700 | if (!(X_OP (insn) == 0 && X_COND (insn) == 0x8)) | |
701 | return start_pc; | |
702 | ||
703 | /* clr [%g1] */ | |
704 | insn = sparc_fetch_instruction (pc); | |
705 | pc = pc + 4; | |
706 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn) | |
707 | && X_RD (insn) == 0 && X_RS1 (insn) == 1)) | |
708 | return start_pc; | |
709 | ||
710 | /* clr [%g4 - some immediate] */ | |
711 | insn = sparc_fetch_instruction (pc); | |
712 | pc = pc + 4; | |
713 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) | |
714 | && X_RS1 (insn) == 4 && X_RD (insn) == 0)) | |
715 | return start_pc; | |
716 | ||
717 | /* We found a valid stack-check sequence, return the new PC. */ | |
718 | return pc; | |
719 | } | |
720 | ||
721 | /* No stack check code in our prologue, return the start_pc. */ | |
722 | return start_pc; | |
723 | } | |
724 | ||
386c036b MK |
725 | CORE_ADDR |
726 | sparc_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc, | |
727 | struct sparc_frame_cache *cache) | |
c906108c | 728 | { |
386c036b MK |
729 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); |
730 | unsigned long insn; | |
731 | int offset = 0; | |
c906108c | 732 | int dest = -1; |
c906108c | 733 | |
b0b92586 JB |
734 | pc = sparc_skip_stack_check (pc); |
735 | ||
386c036b MK |
736 | if (current_pc <= pc) |
737 | return current_pc; | |
738 | ||
739 | /* We have to handle to "Procedure Linkage Table" (PLT) special. On | |
740 | SPARC the linker usually defines a symbol (typically | |
741 | _PROCEDURE_LINKAGE_TABLE_) at the start of the .plt section. | |
742 | This symbol makes us end up here with PC pointing at the start of | |
743 | the PLT and CURRENT_PC probably pointing at a PLT entry. If we | |
744 | would do our normal prologue analysis, we would probably conclude | |
745 | that we've got a frame when in reality we don't, since the | |
746 | dynamic linker patches up the first PLT with some code that | |
747 | starts with a SAVE instruction. Patch up PC such that it points | |
748 | at the start of our PLT entry. */ | |
749 | if (tdep->plt_entry_size > 0 && in_plt_section (current_pc, NULL)) | |
750 | pc = current_pc - ((current_pc - pc) % tdep->plt_entry_size); | |
c906108c | 751 | |
386c036b MK |
752 | insn = sparc_fetch_instruction (pc); |
753 | ||
754 | /* Recognize a SETHI insn and record its destination. */ | |
755 | if (X_OP (insn) == 0 && X_OP2 (insn) == 0x04) | |
c906108c SS |
756 | { |
757 | dest = X_RD (insn); | |
386c036b MK |
758 | offset += 4; |
759 | ||
760 | insn = sparc_fetch_instruction (pc + 4); | |
c906108c SS |
761 | } |
762 | ||
386c036b MK |
763 | /* Allow for an arithmetic operation on DEST or %g1. */ |
764 | if (X_OP (insn) == 2 && X_I (insn) | |
c906108c SS |
765 | && (X_RD (insn) == 1 || X_RD (insn) == dest)) |
766 | { | |
386c036b | 767 | offset += 4; |
c906108c | 768 | |
386c036b | 769 | insn = sparc_fetch_instruction (pc + 8); |
c906108c | 770 | } |
c906108c | 771 | |
386c036b MK |
772 | /* Check for the SAVE instruction that sets up the frame. */ |
773 | if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3c) | |
c906108c | 774 | { |
386c036b MK |
775 | cache->frameless_p = 0; |
776 | return pc + offset + 4; | |
c906108c SS |
777 | } |
778 | ||
779 | return pc; | |
780 | } | |
781 | ||
386c036b MK |
782 | static CORE_ADDR |
783 | sparc_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
784 | { | |
785 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
786 | return frame_unwind_register_unsigned (next_frame, tdep->pc_regnum); | |
787 | } | |
788 | ||
789 | /* Return PC of first real instruction of the function starting at | |
790 | START_PC. */ | |
f510d44e | 791 | |
386c036b MK |
792 | static CORE_ADDR |
793 | sparc32_skip_prologue (CORE_ADDR start_pc) | |
c906108c | 794 | { |
f510d44e DM |
795 | struct symtab_and_line sal; |
796 | CORE_ADDR func_start, func_end; | |
386c036b | 797 | struct sparc_frame_cache cache; |
f510d44e DM |
798 | |
799 | /* This is the preferred method, find the end of the prologue by | |
800 | using the debugging information. */ | |
801 | if (find_pc_partial_function (start_pc, NULL, &func_start, &func_end)) | |
802 | { | |
803 | sal = find_pc_line (func_start, 0); | |
804 | ||
805 | if (sal.end < func_end | |
806 | && start_pc <= sal.end) | |
807 | return sal.end; | |
808 | } | |
809 | ||
075ccec8 MK |
810 | start_pc = sparc_analyze_prologue (start_pc, 0xffffffffUL, &cache); |
811 | ||
812 | /* The psABI says that "Although the first 6 words of arguments | |
813 | reside in registers, the standard stack frame reserves space for | |
814 | them.". It also suggests that a function may use that space to | |
815 | "write incoming arguments 0 to 5" into that space, and that's | |
816 | indeed what GCC seems to be doing. In that case GCC will | |
817 | generate debug information that points to the stack slots instead | |
818 | of the registers, so we should consider the instructions that | |
819 | write out these incoming arguments onto the stack. Of course we | |
820 | only need to do this if we have a stack frame. */ | |
821 | ||
822 | while (!cache.frameless_p) | |
823 | { | |
824 | unsigned long insn = sparc_fetch_instruction (start_pc); | |
825 | ||
826 | /* Recognize instructions that store incoming arguments in | |
827 | %i0...%i5 into the corresponding stack slot. */ | |
828 | if (X_OP (insn) == 3 && (X_OP3 (insn) & 0x3c) == 0x04 && X_I (insn) | |
829 | && (X_RD (insn) >= 24 && X_RD (insn) <= 29) && X_RS1 (insn) == 30 | |
830 | && X_SIMM13 (insn) == 68 + (X_RD (insn) - 24) * 4) | |
831 | { | |
832 | start_pc += 4; | |
833 | continue; | |
834 | } | |
835 | ||
836 | break; | |
837 | } | |
838 | ||
839 | return start_pc; | |
c906108c SS |
840 | } |
841 | ||
386c036b | 842 | /* Normal frames. */ |
9319a2fe | 843 | |
386c036b MK |
844 | struct sparc_frame_cache * |
845 | sparc_frame_cache (struct frame_info *next_frame, void **this_cache) | |
9319a2fe | 846 | { |
386c036b | 847 | struct sparc_frame_cache *cache; |
9319a2fe | 848 | |
386c036b MK |
849 | if (*this_cache) |
850 | return *this_cache; | |
c906108c | 851 | |
386c036b MK |
852 | cache = sparc_alloc_frame_cache (); |
853 | *this_cache = cache; | |
c906108c | 854 | |
93d42b30 | 855 | cache->pc = frame_func_unwind (next_frame, NORMAL_FRAME); |
386c036b | 856 | if (cache->pc != 0) |
93d42b30 | 857 | sparc_analyze_prologue (cache->pc, frame_pc_unwind (next_frame), cache); |
386c036b MK |
858 | |
859 | if (cache->frameless_p) | |
c906108c | 860 | { |
cbeae229 MK |
861 | /* This function is frameless, so %fp (%i6) holds the frame |
862 | pointer for our calling frame. Use %sp (%o6) as this frame's | |
863 | base address. */ | |
864 | cache->base = | |
865 | frame_unwind_register_unsigned (next_frame, SPARC_SP_REGNUM); | |
866 | } | |
867 | else | |
868 | { | |
869 | /* For normal frames, %fp (%i6) holds the frame pointer, the | |
870 | base address for the current stack frame. */ | |
871 | cache->base = | |
872 | frame_unwind_register_unsigned (next_frame, SPARC_FP_REGNUM); | |
c906108c | 873 | } |
c906108c | 874 | |
5b2d44a0 MK |
875 | if (cache->base & 1) |
876 | cache->base += BIAS; | |
877 | ||
386c036b | 878 | return cache; |
c906108c | 879 | } |
c906108c | 880 | |
aff37fc1 DM |
881 | static int |
882 | sparc32_struct_return_from_sym (struct symbol *sym) | |
883 | { | |
884 | struct type *type = check_typedef (SYMBOL_TYPE (sym)); | |
885 | enum type_code code = TYPE_CODE (type); | |
886 | ||
887 | if (code == TYPE_CODE_FUNC || code == TYPE_CODE_METHOD) | |
888 | { | |
889 | type = check_typedef (TYPE_TARGET_TYPE (type)); | |
890 | if (sparc_structure_or_union_p (type) | |
891 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)) | |
892 | return 1; | |
893 | } | |
894 | ||
895 | return 0; | |
896 | } | |
897 | ||
386c036b MK |
898 | struct sparc_frame_cache * |
899 | sparc32_frame_cache (struct frame_info *next_frame, void **this_cache) | |
c906108c | 900 | { |
386c036b MK |
901 | struct sparc_frame_cache *cache; |
902 | struct symbol *sym; | |
c906108c | 903 | |
386c036b MK |
904 | if (*this_cache) |
905 | return *this_cache; | |
c906108c | 906 | |
386c036b | 907 | cache = sparc_frame_cache (next_frame, this_cache); |
c906108c | 908 | |
386c036b MK |
909 | sym = find_pc_function (cache->pc); |
910 | if (sym) | |
c906108c | 911 | { |
aff37fc1 | 912 | cache->struct_return_p = sparc32_struct_return_from_sym (sym); |
c906108c | 913 | } |
5465445a JB |
914 | else |
915 | { | |
916 | /* There is no debugging information for this function to | |
917 | help us determine whether this function returns a struct | |
918 | or not. So we rely on another heuristic which is to check | |
919 | the instruction at the return address and see if this is | |
920 | an "unimp" instruction. If it is, then it is a struct-return | |
921 | function. */ | |
922 | CORE_ADDR pc; | |
923 | int regnum = cache->frameless_p ? SPARC_O7_REGNUM : SPARC_I7_REGNUM; | |
924 | ||
925 | pc = frame_unwind_register_unsigned (next_frame, regnum) + 8; | |
926 | if (sparc_is_unimp_insn (pc)) | |
927 | cache->struct_return_p = 1; | |
928 | } | |
c906108c | 929 | |
386c036b MK |
930 | return cache; |
931 | } | |
932 | ||
933 | static void | |
934 | sparc32_frame_this_id (struct frame_info *next_frame, void **this_cache, | |
935 | struct frame_id *this_id) | |
936 | { | |
937 | struct sparc_frame_cache *cache = | |
938 | sparc32_frame_cache (next_frame, this_cache); | |
939 | ||
940 | /* This marks the outermost frame. */ | |
941 | if (cache->base == 0) | |
942 | return; | |
943 | ||
944 | (*this_id) = frame_id_build (cache->base, cache->pc); | |
945 | } | |
c906108c | 946 | |
386c036b MK |
947 | static void |
948 | sparc32_frame_prev_register (struct frame_info *next_frame, void **this_cache, | |
949 | int regnum, int *optimizedp, | |
950 | enum lval_type *lvalp, CORE_ADDR *addrp, | |
47ef841b | 951 | int *realnump, gdb_byte *valuep) |
386c036b MK |
952 | { |
953 | struct sparc_frame_cache *cache = | |
954 | sparc32_frame_cache (next_frame, this_cache); | |
c906108c | 955 | |
386c036b | 956 | if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM) |
c906108c | 957 | { |
386c036b MK |
958 | *optimizedp = 0; |
959 | *lvalp = not_lval; | |
960 | *addrp = 0; | |
961 | *realnump = -1; | |
962 | if (valuep) | |
c906108c | 963 | { |
386c036b MK |
964 | CORE_ADDR pc = (regnum == SPARC32_NPC_REGNUM) ? 4 : 0; |
965 | ||
966 | /* If this functions has a Structure, Union or | |
967 | Quad-Precision return value, we have to skip the UNIMP | |
968 | instruction that encodes the size of the structure. */ | |
969 | if (cache->struct_return_p) | |
970 | pc += 4; | |
971 | ||
972 | regnum = cache->frameless_p ? SPARC_O7_REGNUM : SPARC_I7_REGNUM; | |
973 | pc += frame_unwind_register_unsigned (next_frame, regnum) + 8; | |
974 | store_unsigned_integer (valuep, 4, pc); | |
c906108c | 975 | } |
c906108c SS |
976 | return; |
977 | } | |
978 | ||
42cdca6c MK |
979 | /* Handle StackGhost. */ |
980 | { | |
981 | ULONGEST wcookie = sparc_fetch_wcookie (); | |
982 | ||
983 | if (wcookie != 0 && !cache->frameless_p && regnum == SPARC_I7_REGNUM) | |
984 | { | |
985 | *optimizedp = 0; | |
986 | *lvalp = not_lval; | |
987 | *addrp = 0; | |
988 | *realnump = -1; | |
989 | if (valuep) | |
990 | { | |
991 | CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4; | |
7d34766b | 992 | ULONGEST i7; |
42cdca6c MK |
993 | |
994 | /* Read the value in from memory. */ | |
7d34766b MK |
995 | i7 = get_frame_memory_unsigned (next_frame, addr, 4); |
996 | store_unsigned_integer (valuep, 4, i7 ^ wcookie); | |
42cdca6c MK |
997 | } |
998 | return; | |
999 | } | |
1000 | } | |
1001 | ||
386c036b MK |
1002 | /* The previous frame's `local' and `in' registers have been saved |
1003 | in the register save area. */ | |
1004 | if (!cache->frameless_p | |
1005 | && regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) | |
c906108c | 1006 | { |
386c036b MK |
1007 | *optimizedp = 0; |
1008 | *lvalp = lval_memory; | |
1009 | *addrp = cache->base + (regnum - SPARC_L0_REGNUM) * 4; | |
1010 | *realnump = -1; | |
1011 | if (valuep) | |
c906108c | 1012 | { |
386c036b MK |
1013 | struct gdbarch *gdbarch = get_frame_arch (next_frame); |
1014 | ||
1015 | /* Read the value in from memory. */ | |
1016 | read_memory (*addrp, valuep, register_size (gdbarch, regnum)); | |
c906108c | 1017 | } |
386c036b MK |
1018 | return; |
1019 | } | |
c906108c | 1020 | |
386c036b MK |
1021 | /* The previous frame's `out' registers are accessable as the |
1022 | current frame's `in' registers. */ | |
1023 | if (!cache->frameless_p | |
1024 | && regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O7_REGNUM) | |
1025 | regnum += (SPARC_I0_REGNUM - SPARC_O0_REGNUM); | |
5af923b0 | 1026 | |
00b25ff3 AC |
1027 | *optimizedp = 0; |
1028 | *lvalp = lval_register; | |
1029 | *addrp = 0; | |
1030 | *realnump = regnum; | |
1031 | if (valuep) | |
1032 | frame_unwind_register (next_frame, (*realnump), valuep); | |
386c036b | 1033 | } |
c906108c | 1034 | |
386c036b MK |
1035 | static const struct frame_unwind sparc32_frame_unwind = |
1036 | { | |
1037 | NORMAL_FRAME, | |
1038 | sparc32_frame_this_id, | |
1039 | sparc32_frame_prev_register | |
1040 | }; | |
1041 | ||
1042 | static const struct frame_unwind * | |
1043 | sparc32_frame_sniffer (struct frame_info *next_frame) | |
1044 | { | |
1045 | return &sparc32_frame_unwind; | |
c906108c | 1046 | } |
386c036b | 1047 | \f |
c906108c | 1048 | |
386c036b MK |
1049 | static CORE_ADDR |
1050 | sparc32_frame_base_address (struct frame_info *next_frame, void **this_cache) | |
1051 | { | |
1052 | struct sparc_frame_cache *cache = | |
1053 | sparc32_frame_cache (next_frame, this_cache); | |
c906108c | 1054 | |
386c036b MK |
1055 | return cache->base; |
1056 | } | |
c906108c | 1057 | |
386c036b MK |
1058 | static const struct frame_base sparc32_frame_base = |
1059 | { | |
1060 | &sparc32_frame_unwind, | |
1061 | sparc32_frame_base_address, | |
1062 | sparc32_frame_base_address, | |
1063 | sparc32_frame_base_address | |
1064 | }; | |
c906108c | 1065 | |
386c036b MK |
1066 | static struct frame_id |
1067 | sparc_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
1068 | { | |
1069 | CORE_ADDR sp; | |
5af923b0 | 1070 | |
386c036b | 1071 | sp = frame_unwind_register_unsigned (next_frame, SPARC_SP_REGNUM); |
5b2d44a0 MK |
1072 | if (sp & 1) |
1073 | sp += BIAS; | |
386c036b MK |
1074 | return frame_id_build (sp, frame_pc_unwind (next_frame)); |
1075 | } | |
1076 | \f | |
c906108c | 1077 | |
386c036b MK |
1078 | /* Extract from an array REGBUF containing the (raw) register state, a |
1079 | function return value of TYPE, and copy that into VALBUF. */ | |
5af923b0 | 1080 | |
386c036b MK |
1081 | static void |
1082 | sparc32_extract_return_value (struct type *type, struct regcache *regcache, | |
e1613aba | 1083 | gdb_byte *valbuf) |
386c036b MK |
1084 | { |
1085 | int len = TYPE_LENGTH (type); | |
e1613aba | 1086 | gdb_byte buf[8]; |
c906108c | 1087 | |
386c036b MK |
1088 | gdb_assert (!sparc_structure_or_union_p (type)); |
1089 | gdb_assert (!(sparc_floating_p (type) && len == 16)); | |
c906108c | 1090 | |
386c036b | 1091 | if (sparc_floating_p (type)) |
5af923b0 | 1092 | { |
386c036b MK |
1093 | /* Floating return values. */ |
1094 | regcache_cooked_read (regcache, SPARC_F0_REGNUM, buf); | |
1095 | if (len > 4) | |
1096 | regcache_cooked_read (regcache, SPARC_F1_REGNUM, buf + 4); | |
1097 | memcpy (valbuf, buf, len); | |
5af923b0 MS |
1098 | } |
1099 | else | |
1100 | { | |
386c036b MK |
1101 | /* Integral and pointer return values. */ |
1102 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
c906108c | 1103 | |
386c036b MK |
1104 | regcache_cooked_read (regcache, SPARC_O0_REGNUM, buf); |
1105 | if (len > 4) | |
1106 | { | |
1107 | regcache_cooked_read (regcache, SPARC_O1_REGNUM, buf + 4); | |
1108 | gdb_assert (len == 8); | |
1109 | memcpy (valbuf, buf, 8); | |
1110 | } | |
1111 | else | |
1112 | { | |
1113 | /* Just stripping off any unused bytes should preserve the | |
1114 | signed-ness just fine. */ | |
1115 | memcpy (valbuf, buf + 4 - len, len); | |
1116 | } | |
1117 | } | |
1118 | } | |
c906108c | 1119 | |
386c036b MK |
1120 | /* Write into the appropriate registers a function return value stored |
1121 | in VALBUF of type TYPE. */ | |
c906108c | 1122 | |
386c036b MK |
1123 | static void |
1124 | sparc32_store_return_value (struct type *type, struct regcache *regcache, | |
e1613aba | 1125 | const gdb_byte *valbuf) |
386c036b MK |
1126 | { |
1127 | int len = TYPE_LENGTH (type); | |
e1613aba | 1128 | gdb_byte buf[8]; |
c906108c | 1129 | |
386c036b MK |
1130 | gdb_assert (!sparc_structure_or_union_p (type)); |
1131 | gdb_assert (!(sparc_floating_p (type) && len == 16)); | |
c906108c | 1132 | |
386c036b MK |
1133 | if (sparc_floating_p (type)) |
1134 | { | |
1135 | /* Floating return values. */ | |
1136 | memcpy (buf, valbuf, len); | |
1137 | regcache_cooked_write (regcache, SPARC_F0_REGNUM, buf); | |
1138 | if (len > 4) | |
1139 | regcache_cooked_write (regcache, SPARC_F1_REGNUM, buf + 4); | |
1140 | } | |
1141 | else | |
c906108c | 1142 | { |
386c036b MK |
1143 | /* Integral and pointer return values. */ |
1144 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
1145 | ||
1146 | if (len > 4) | |
2757dd86 | 1147 | { |
386c036b MK |
1148 | gdb_assert (len == 8); |
1149 | memcpy (buf, valbuf, 8); | |
1150 | regcache_cooked_write (regcache, SPARC_O1_REGNUM, buf + 4); | |
2757dd86 AC |
1151 | } |
1152 | else | |
1153 | { | |
386c036b MK |
1154 | /* ??? Do we need to do any sign-extension here? */ |
1155 | memcpy (buf + 4 - len, valbuf, len); | |
2757dd86 | 1156 | } |
386c036b | 1157 | regcache_cooked_write (regcache, SPARC_O0_REGNUM, buf); |
c906108c SS |
1158 | } |
1159 | } | |
1160 | ||
b9d4c5ed MK |
1161 | static enum return_value_convention |
1162 | sparc32_return_value (struct gdbarch *gdbarch, struct type *type, | |
e1613aba MK |
1163 | struct regcache *regcache, gdb_byte *readbuf, |
1164 | const gdb_byte *writebuf) | |
b9d4c5ed | 1165 | { |
0a8f48b9 MK |
1166 | /* The psABI says that "...every stack frame reserves the word at |
1167 | %fp+64. If a function returns a structure, union, or | |
1168 | quad-precision value, this word should hold the address of the | |
1169 | object into which the return value should be copied." This | |
1170 | guarantees that we can always find the return value, not just | |
1171 | before the function returns. */ | |
1172 | ||
b9d4c5ed MK |
1173 | if (sparc_structure_or_union_p (type) |
1174 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)) | |
0a8f48b9 MK |
1175 | { |
1176 | if (readbuf) | |
1177 | { | |
1178 | ULONGEST sp; | |
1179 | CORE_ADDR addr; | |
1180 | ||
1181 | regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); | |
1182 | addr = read_memory_unsigned_integer (sp + 64, 4); | |
1183 | read_memory (addr, readbuf, TYPE_LENGTH (type)); | |
1184 | } | |
1185 | ||
1186 | return RETURN_VALUE_ABI_PRESERVES_ADDRESS; | |
1187 | } | |
b9d4c5ed MK |
1188 | |
1189 | if (readbuf) | |
1190 | sparc32_extract_return_value (type, regcache, readbuf); | |
1191 | if (writebuf) | |
1192 | sparc32_store_return_value (type, regcache, writebuf); | |
1193 | ||
1194 | return RETURN_VALUE_REGISTER_CONVENTION; | |
1195 | } | |
1196 | ||
386c036b MK |
1197 | static int |
1198 | sparc32_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type) | |
c906108c | 1199 | { |
386c036b MK |
1200 | return (sparc_structure_or_union_p (type) |
1201 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)); | |
1202 | } | |
c906108c | 1203 | |
aff37fc1 DM |
1204 | static int |
1205 | sparc32_dwarf2_struct_return_p (struct frame_info *next_frame) | |
1206 | { | |
93d42b30 | 1207 | CORE_ADDR pc = frame_unwind_address_in_block (next_frame, NORMAL_FRAME); |
aff37fc1 DM |
1208 | struct symbol *sym = find_pc_function (pc); |
1209 | ||
1210 | if (sym) | |
1211 | return sparc32_struct_return_from_sym (sym); | |
1212 | return 0; | |
1213 | } | |
1214 | ||
f5a9b87d DM |
1215 | static void |
1216 | sparc32_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
aff37fc1 DM |
1217 | struct dwarf2_frame_state_reg *reg, |
1218 | struct frame_info *next_frame) | |
f5a9b87d | 1219 | { |
aff37fc1 DM |
1220 | int off; |
1221 | ||
f5a9b87d DM |
1222 | switch (regnum) |
1223 | { | |
1224 | case SPARC_G0_REGNUM: | |
1225 | /* Since %g0 is always zero, there is no point in saving it, and | |
1226 | people will be inclined omit it from the CFI. Make sure we | |
1227 | don't warn about that. */ | |
1228 | reg->how = DWARF2_FRAME_REG_SAME_VALUE; | |
1229 | break; | |
1230 | case SPARC_SP_REGNUM: | |
1231 | reg->how = DWARF2_FRAME_REG_CFA; | |
1232 | break; | |
1233 | case SPARC32_PC_REGNUM: | |
f5a9b87d DM |
1234 | case SPARC32_NPC_REGNUM: |
1235 | reg->how = DWARF2_FRAME_REG_RA_OFFSET; | |
aff37fc1 DM |
1236 | off = 8; |
1237 | if (sparc32_dwarf2_struct_return_p (next_frame)) | |
1238 | off += 4; | |
1239 | if (regnum == SPARC32_NPC_REGNUM) | |
1240 | off += 4; | |
1241 | reg->loc.offset = off; | |
f5a9b87d DM |
1242 | break; |
1243 | } | |
1244 | } | |
1245 | ||
386c036b MK |
1246 | \f |
1247 | /* The SPARC Architecture doesn't have hardware single-step support, | |
1248 | and most operating systems don't implement it either, so we provide | |
1249 | software single-step mechanism. */ | |
c906108c | 1250 | |
386c036b | 1251 | static CORE_ADDR |
c893be75 MK |
1252 | sparc_analyze_control_transfer (struct gdbarch *arch, |
1253 | CORE_ADDR pc, CORE_ADDR *npc) | |
386c036b MK |
1254 | { |
1255 | unsigned long insn = sparc_fetch_instruction (pc); | |
1256 | int conditional_p = X_COND (insn) & 0x7; | |
1257 | int branch_p = 0; | |
1258 | long offset = 0; /* Must be signed for sign-extend. */ | |
c906108c | 1259 | |
386c036b | 1260 | if (X_OP (insn) == 0 && X_OP2 (insn) == 3 && (insn & 0x1000000) == 0) |
c906108c | 1261 | { |
386c036b MK |
1262 | /* Branch on Integer Register with Prediction (BPr). */ |
1263 | branch_p = 1; | |
1264 | conditional_p = 1; | |
c906108c | 1265 | } |
386c036b | 1266 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 6) |
c906108c | 1267 | { |
386c036b MK |
1268 | /* Branch on Floating-Point Condition Codes (FBfcc). */ |
1269 | branch_p = 1; | |
1270 | offset = 4 * X_DISP22 (insn); | |
c906108c | 1271 | } |
386c036b MK |
1272 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 5) |
1273 | { | |
1274 | /* Branch on Floating-Point Condition Codes with Prediction | |
1275 | (FBPfcc). */ | |
1276 | branch_p = 1; | |
1277 | offset = 4 * X_DISP19 (insn); | |
1278 | } | |
1279 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 2) | |
1280 | { | |
1281 | /* Branch on Integer Condition Codes (Bicc). */ | |
1282 | branch_p = 1; | |
1283 | offset = 4 * X_DISP22 (insn); | |
1284 | } | |
1285 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 1) | |
c906108c | 1286 | { |
386c036b MK |
1287 | /* Branch on Integer Condition Codes with Prediction (BPcc). */ |
1288 | branch_p = 1; | |
1289 | offset = 4 * X_DISP19 (insn); | |
c906108c | 1290 | } |
c893be75 MK |
1291 | else if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3a) |
1292 | { | |
1293 | /* Trap instruction (TRAP). */ | |
1294 | return gdbarch_tdep (arch)->step_trap (insn); | |
1295 | } | |
386c036b MK |
1296 | |
1297 | /* FIXME: Handle DONE and RETRY instructions. */ | |
1298 | ||
386c036b | 1299 | if (branch_p) |
c906108c | 1300 | { |
386c036b | 1301 | if (conditional_p) |
c906108c | 1302 | { |
386c036b MK |
1303 | /* For conditional branches, return nPC + 4 iff the annul |
1304 | bit is 1. */ | |
1305 | return (X_A (insn) ? *npc + 4 : 0); | |
c906108c SS |
1306 | } |
1307 | else | |
1308 | { | |
386c036b MK |
1309 | /* For unconditional branches, return the target if its |
1310 | specified condition is "always" and return nPC + 4 if the | |
1311 | condition is "never". If the annul bit is 1, set *NPC to | |
1312 | zero. */ | |
1313 | if (X_COND (insn) == 0x0) | |
1314 | pc = *npc, offset = 4; | |
1315 | if (X_A (insn)) | |
1316 | *npc = 0; | |
1317 | ||
1318 | gdb_assert (offset != 0); | |
1319 | return pc + offset; | |
c906108c SS |
1320 | } |
1321 | } | |
386c036b MK |
1322 | |
1323 | return 0; | |
c906108c SS |
1324 | } |
1325 | ||
c893be75 MK |
1326 | static CORE_ADDR |
1327 | sparc_step_trap (unsigned long insn) | |
1328 | { | |
1329 | return 0; | |
1330 | } | |
1331 | ||
e6590a1b | 1332 | int |
e0cd558a | 1333 | sparc_software_single_step (struct regcache *regcache) |
386c036b | 1334 | { |
c893be75 MK |
1335 | struct gdbarch *arch = current_gdbarch; |
1336 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); | |
8181d85f | 1337 | CORE_ADDR npc, nnpc; |
c906108c | 1338 | |
e0cd558a | 1339 | CORE_ADDR pc, orig_npc; |
c906108c | 1340 | |
e0cd558a UW |
1341 | pc = sparc_address_from_register (tdep->pc_regnum); |
1342 | orig_npc = npc = sparc_address_from_register (tdep->npc_regnum); | |
c906108c | 1343 | |
e0cd558a UW |
1344 | /* Analyze the instruction at PC. */ |
1345 | nnpc = sparc_analyze_control_transfer (arch, pc, &npc); | |
1346 | if (npc != 0) | |
1347 | insert_single_step_breakpoint (npc); | |
8181d85f | 1348 | |
e0cd558a UW |
1349 | if (nnpc != 0) |
1350 | insert_single_step_breakpoint (nnpc); | |
c906108c | 1351 | |
e0cd558a UW |
1352 | /* Assert that we have set at least one breakpoint, and that |
1353 | they're not set at the same spot - unless we're going | |
1354 | from here straight to NULL, i.e. a call or jump to 0. */ | |
1355 | gdb_assert (npc != 0 || nnpc != 0 || orig_npc == 0); | |
1356 | gdb_assert (nnpc != npc || orig_npc == 0); | |
e6590a1b UW |
1357 | |
1358 | return 1; | |
386c036b MK |
1359 | } |
1360 | ||
1361 | static void | |
1362 | sparc_write_pc (CORE_ADDR pc, ptid_t ptid) | |
1363 | { | |
1364 | struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); | |
1365 | ||
1366 | write_register_pid (tdep->pc_regnum, pc, ptid); | |
1367 | write_register_pid (tdep->npc_regnum, pc + 4, ptid); | |
1368 | } | |
1369 | \f | |
1370 | /* Unglobalize NAME. */ | |
1371 | ||
1372 | char * | |
1373 | sparc_stabs_unglobalize_name (char *name) | |
1374 | { | |
1375 | /* The Sun compilers (Sun ONE Studio, Forte Developer, Sun WorkShop, | |
1376 | SunPRO) convert file static variables into global values, a | |
1377 | process known as globalization. In order to do this, the | |
1378 | compiler will create a unique prefix and prepend it to each file | |
1379 | static variable. For static variables within a function, this | |
1380 | globalization prefix is followed by the function name (nested | |
1381 | static variables within a function are supposed to generate a | |
1382 | warning message, and are left alone). The procedure is | |
1383 | documented in the Stabs Interface Manual, which is distrubuted | |
1384 | with the compilers, although version 4.0 of the manual seems to | |
1385 | be incorrect in some places, at least for SPARC. The | |
1386 | globalization prefix is encoded into an N_OPT stab, with the form | |
1387 | "G=<prefix>". The globalization prefix always seems to start | |
1388 | with a dollar sign '$'; a dot '.' is used as a seperator. So we | |
1389 | simply strip everything up until the last dot. */ | |
c906108c | 1390 | |
386c036b | 1391 | if (name[0] == '$') |
c906108c | 1392 | { |
386c036b MK |
1393 | char *p = strrchr (name, '.'); |
1394 | if (p) | |
1395 | return p + 1; | |
c906108c | 1396 | } |
c906108c | 1397 | |
386c036b MK |
1398 | return name; |
1399 | } | |
1400 | \f | |
5af923b0 | 1401 | |
a54124c5 MK |
1402 | /* Return the appropriate register set for the core section identified |
1403 | by SECT_NAME and SECT_SIZE. */ | |
1404 | ||
1405 | const struct regset * | |
1406 | sparc_regset_from_core_section (struct gdbarch *gdbarch, | |
1407 | const char *sect_name, size_t sect_size) | |
1408 | { | |
1409 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1410 | ||
c558d81a | 1411 | if (strcmp (sect_name, ".reg") == 0 && sect_size >= tdep->sizeof_gregset) |
a54124c5 MK |
1412 | return tdep->gregset; |
1413 | ||
c558d81a | 1414 | if (strcmp (sect_name, ".reg2") == 0 && sect_size >= tdep->sizeof_fpregset) |
a54124c5 MK |
1415 | return tdep->fpregset; |
1416 | ||
1417 | return NULL; | |
1418 | } | |
1419 | \f | |
1420 | ||
386c036b MK |
1421 | static struct gdbarch * |
1422 | sparc32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
1423 | { | |
1424 | struct gdbarch_tdep *tdep; | |
1425 | struct gdbarch *gdbarch; | |
c906108c | 1426 | |
386c036b MK |
1427 | /* If there is already a candidate, use it. */ |
1428 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
1429 | if (arches != NULL) | |
1430 | return arches->gdbarch; | |
c906108c | 1431 | |
386c036b MK |
1432 | /* Allocate space for the new architecture. */ |
1433 | tdep = XMALLOC (struct gdbarch_tdep); | |
1434 | gdbarch = gdbarch_alloc (&info, tdep); | |
5af923b0 | 1435 | |
386c036b MK |
1436 | tdep->pc_regnum = SPARC32_PC_REGNUM; |
1437 | tdep->npc_regnum = SPARC32_NPC_REGNUM; | |
a54124c5 | 1438 | tdep->gregset = NULL; |
c558d81a | 1439 | tdep->sizeof_gregset = 0; |
a54124c5 | 1440 | tdep->fpregset = NULL; |
c558d81a | 1441 | tdep->sizeof_fpregset = 0; |
386c036b | 1442 | tdep->plt_entry_size = 0; |
c893be75 | 1443 | tdep->step_trap = sparc_step_trap; |
386c036b MK |
1444 | |
1445 | set_gdbarch_long_double_bit (gdbarch, 128); | |
8da61cc4 | 1446 | set_gdbarch_long_double_format (gdbarch, floatformats_sparc_quad); |
386c036b MK |
1447 | |
1448 | set_gdbarch_num_regs (gdbarch, SPARC32_NUM_REGS); | |
1449 | set_gdbarch_register_name (gdbarch, sparc32_register_name); | |
1450 | set_gdbarch_register_type (gdbarch, sparc32_register_type); | |
1451 | set_gdbarch_num_pseudo_regs (gdbarch, SPARC32_NUM_PSEUDO_REGS); | |
1452 | set_gdbarch_pseudo_register_read (gdbarch, sparc32_pseudo_register_read); | |
1453 | set_gdbarch_pseudo_register_write (gdbarch, sparc32_pseudo_register_write); | |
1454 | ||
1455 | /* Register numbers of various important registers. */ | |
1456 | set_gdbarch_sp_regnum (gdbarch, SPARC_SP_REGNUM); /* %sp */ | |
1457 | set_gdbarch_pc_regnum (gdbarch, SPARC32_PC_REGNUM); /* %pc */ | |
1458 | set_gdbarch_fp0_regnum (gdbarch, SPARC_F0_REGNUM); /* %f0 */ | |
1459 | ||
1460 | /* Call dummy code. */ | |
1461 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); | |
1462 | set_gdbarch_push_dummy_code (gdbarch, sparc32_push_dummy_code); | |
1463 | set_gdbarch_push_dummy_call (gdbarch, sparc32_push_dummy_call); | |
1464 | ||
b9d4c5ed | 1465 | set_gdbarch_return_value (gdbarch, sparc32_return_value); |
386c036b MK |
1466 | set_gdbarch_stabs_argument_has_addr |
1467 | (gdbarch, sparc32_stabs_argument_has_addr); | |
1468 | ||
1469 | set_gdbarch_skip_prologue (gdbarch, sparc32_skip_prologue); | |
1470 | ||
1471 | /* Stack grows downward. */ | |
1472 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
c906108c | 1473 | |
386c036b | 1474 | set_gdbarch_breakpoint_from_pc (gdbarch, sparc_breakpoint_from_pc); |
c906108c | 1475 | |
386c036b | 1476 | set_gdbarch_frame_args_skip (gdbarch, 8); |
5af923b0 | 1477 | |
386c036b | 1478 | set_gdbarch_print_insn (gdbarch, print_insn_sparc); |
c906108c | 1479 | |
386c036b MK |
1480 | set_gdbarch_software_single_step (gdbarch, sparc_software_single_step); |
1481 | set_gdbarch_write_pc (gdbarch, sparc_write_pc); | |
c906108c | 1482 | |
386c036b | 1483 | set_gdbarch_unwind_dummy_id (gdbarch, sparc_unwind_dummy_id); |
c906108c | 1484 | |
386c036b | 1485 | set_gdbarch_unwind_pc (gdbarch, sparc_unwind_pc); |
c906108c | 1486 | |
386c036b MK |
1487 | frame_base_set_default (gdbarch, &sparc32_frame_base); |
1488 | ||
f5a9b87d DM |
1489 | /* Hook in the DWARF CFI frame unwinder. */ |
1490 | dwarf2_frame_set_init_reg (gdbarch, sparc32_dwarf2_frame_init_reg); | |
1491 | /* FIXME: kettenis/20050423: Don't enable the unwinder until the | |
1492 | StackGhost issues have been resolved. */ | |
1493 | ||
b2a0b9b2 DM |
1494 | /* Hook in ABI-specific overrides, if they have been registered. */ |
1495 | gdbarch_init_osabi (info, gdbarch); | |
1496 | ||
386c036b | 1497 | frame_unwind_append_sniffer (gdbarch, sparc32_frame_sniffer); |
c906108c | 1498 | |
a54124c5 | 1499 | /* If we have register sets, enable the generic core file support. */ |
4c72d57a | 1500 | if (tdep->gregset) |
a54124c5 MK |
1501 | set_gdbarch_regset_from_core_section (gdbarch, |
1502 | sparc_regset_from_core_section); | |
1503 | ||
386c036b MK |
1504 | return gdbarch; |
1505 | } | |
1506 | \f | |
1507 | /* Helper functions for dealing with register windows. */ | |
1508 | ||
1509 | void | |
1510 | sparc_supply_rwindow (struct regcache *regcache, CORE_ADDR sp, int regnum) | |
c906108c | 1511 | { |
386c036b | 1512 | int offset = 0; |
e1613aba | 1513 | gdb_byte buf[8]; |
386c036b MK |
1514 | int i; |
1515 | ||
1516 | if (sp & 1) | |
1517 | { | |
1518 | /* Registers are 64-bit. */ | |
1519 | sp += BIAS; | |
c906108c | 1520 | |
386c036b MK |
1521 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1522 | { | |
1523 | if (regnum == i || regnum == -1) | |
1524 | { | |
1525 | target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8); | |
f700a364 MK |
1526 | |
1527 | /* Handle StackGhost. */ | |
1528 | if (i == SPARC_I7_REGNUM) | |
1529 | { | |
1530 | ULONGEST wcookie = sparc_fetch_wcookie (); | |
1531 | ULONGEST i7 = extract_unsigned_integer (buf + offset, 8); | |
1532 | ||
1533 | store_unsigned_integer (buf + offset, 8, i7 ^ wcookie); | |
1534 | } | |
1535 | ||
386c036b MK |
1536 | regcache_raw_supply (regcache, i, buf); |
1537 | } | |
1538 | } | |
1539 | } | |
1540 | else | |
c906108c | 1541 | { |
386c036b MK |
1542 | /* Registers are 32-bit. Toss any sign-extension of the stack |
1543 | pointer. */ | |
1544 | sp &= 0xffffffffUL; | |
c906108c | 1545 | |
386c036b MK |
1546 | /* Clear out the top half of the temporary buffer, and put the |
1547 | register value in the bottom half if we're in 64-bit mode. */ | |
1548 | if (gdbarch_ptr_bit (current_gdbarch) == 64) | |
c906108c | 1549 | { |
386c036b MK |
1550 | memset (buf, 0, 4); |
1551 | offset = 4; | |
1552 | } | |
c906108c | 1553 | |
386c036b MK |
1554 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1555 | { | |
1556 | if (regnum == i || regnum == -1) | |
1557 | { | |
1558 | target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 4), | |
1559 | buf + offset, 4); | |
42cdca6c MK |
1560 | |
1561 | /* Handle StackGhost. */ | |
1562 | if (i == SPARC_I7_REGNUM) | |
1563 | { | |
1564 | ULONGEST wcookie = sparc_fetch_wcookie (); | |
7d34766b | 1565 | ULONGEST i7 = extract_unsigned_integer (buf + offset, 4); |
42cdca6c | 1566 | |
7d34766b | 1567 | store_unsigned_integer (buf + offset, 4, i7 ^ wcookie); |
42cdca6c MK |
1568 | } |
1569 | ||
386c036b MK |
1570 | regcache_raw_supply (regcache, i, buf); |
1571 | } | |
c906108c SS |
1572 | } |
1573 | } | |
c906108c | 1574 | } |
c906108c SS |
1575 | |
1576 | void | |
386c036b MK |
1577 | sparc_collect_rwindow (const struct regcache *regcache, |
1578 | CORE_ADDR sp, int regnum) | |
c906108c | 1579 | { |
386c036b | 1580 | int offset = 0; |
e1613aba | 1581 | gdb_byte buf[8]; |
386c036b | 1582 | int i; |
5af923b0 | 1583 | |
386c036b | 1584 | if (sp & 1) |
5af923b0 | 1585 | { |
386c036b MK |
1586 | /* Registers are 64-bit. */ |
1587 | sp += BIAS; | |
c906108c | 1588 | |
386c036b MK |
1589 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1590 | { | |
1591 | if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i) | |
1592 | { | |
1593 | regcache_raw_collect (regcache, i, buf); | |
f700a364 MK |
1594 | |
1595 | /* Handle StackGhost. */ | |
1596 | if (i == SPARC_I7_REGNUM) | |
1597 | { | |
1598 | ULONGEST wcookie = sparc_fetch_wcookie (); | |
1599 | ULONGEST i7 = extract_unsigned_integer (buf + offset, 8); | |
1600 | ||
1601 | store_unsigned_integer (buf, 8, i7 ^ wcookie); | |
1602 | } | |
1603 | ||
386c036b MK |
1604 | target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8); |
1605 | } | |
1606 | } | |
5af923b0 MS |
1607 | } |
1608 | else | |
1609 | { | |
386c036b MK |
1610 | /* Registers are 32-bit. Toss any sign-extension of the stack |
1611 | pointer. */ | |
1612 | sp &= 0xffffffffUL; | |
1613 | ||
1614 | /* Only use the bottom half if we're in 64-bit mode. */ | |
1615 | if (gdbarch_ptr_bit (current_gdbarch) == 64) | |
1616 | offset = 4; | |
1617 | ||
1618 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
1619 | { | |
1620 | if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i) | |
1621 | { | |
1622 | regcache_raw_collect (regcache, i, buf); | |
42cdca6c MK |
1623 | |
1624 | /* Handle StackGhost. */ | |
1625 | if (i == SPARC_I7_REGNUM) | |
1626 | { | |
1627 | ULONGEST wcookie = sparc_fetch_wcookie (); | |
7d34766b | 1628 | ULONGEST i7 = extract_unsigned_integer (buf + offset, 4); |
42cdca6c | 1629 | |
7d34766b | 1630 | store_unsigned_integer (buf + offset, 4, i7 ^ wcookie); |
42cdca6c MK |
1631 | } |
1632 | ||
386c036b MK |
1633 | target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 4), |
1634 | buf + offset, 4); | |
1635 | } | |
1636 | } | |
5af923b0 | 1637 | } |
c906108c SS |
1638 | } |
1639 | ||
386c036b MK |
1640 | /* Helper functions for dealing with register sets. */ |
1641 | ||
c906108c | 1642 | void |
386c036b MK |
1643 | sparc32_supply_gregset (const struct sparc_gregset *gregset, |
1644 | struct regcache *regcache, | |
1645 | int regnum, const void *gregs) | |
c906108c | 1646 | { |
e1613aba | 1647 | const gdb_byte *regs = gregs; |
386c036b | 1648 | int i; |
5af923b0 | 1649 | |
386c036b MK |
1650 | if (regnum == SPARC32_PSR_REGNUM || regnum == -1) |
1651 | regcache_raw_supply (regcache, SPARC32_PSR_REGNUM, | |
1652 | regs + gregset->r_psr_offset); | |
c906108c | 1653 | |
386c036b MK |
1654 | if (regnum == SPARC32_PC_REGNUM || regnum == -1) |
1655 | regcache_raw_supply (regcache, SPARC32_PC_REGNUM, | |
1656 | regs + gregset->r_pc_offset); | |
5af923b0 | 1657 | |
386c036b MK |
1658 | if (regnum == SPARC32_NPC_REGNUM || regnum == -1) |
1659 | regcache_raw_supply (regcache, SPARC32_NPC_REGNUM, | |
1660 | regs + gregset->r_npc_offset); | |
5af923b0 | 1661 | |
386c036b MK |
1662 | if (regnum == SPARC32_Y_REGNUM || regnum == -1) |
1663 | regcache_raw_supply (regcache, SPARC32_Y_REGNUM, | |
1664 | regs + gregset->r_y_offset); | |
5af923b0 | 1665 | |
386c036b MK |
1666 | if (regnum == SPARC_G0_REGNUM || regnum == -1) |
1667 | regcache_raw_supply (regcache, SPARC_G0_REGNUM, NULL); | |
5af923b0 | 1668 | |
386c036b | 1669 | if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1) |
c906108c | 1670 | { |
386c036b MK |
1671 | int offset = gregset->r_g1_offset; |
1672 | ||
1673 | for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++) | |
1674 | { | |
1675 | if (regnum == i || regnum == -1) | |
1676 | regcache_raw_supply (regcache, i, regs + offset); | |
1677 | offset += 4; | |
1678 | } | |
c906108c | 1679 | } |
386c036b MK |
1680 | |
1681 | if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1) | |
c906108c | 1682 | { |
386c036b MK |
1683 | /* Not all of the register set variants include Locals and |
1684 | Inputs. For those that don't, we read them off the stack. */ | |
1685 | if (gregset->r_l0_offset == -1) | |
1686 | { | |
1687 | ULONGEST sp; | |
1688 | ||
1689 | regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); | |
1690 | sparc_supply_rwindow (regcache, sp, regnum); | |
1691 | } | |
1692 | else | |
1693 | { | |
1694 | int offset = gregset->r_l0_offset; | |
1695 | ||
1696 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
1697 | { | |
1698 | if (regnum == i || regnum == -1) | |
1699 | regcache_raw_supply (regcache, i, regs + offset); | |
1700 | offset += 4; | |
1701 | } | |
1702 | } | |
c906108c SS |
1703 | } |
1704 | } | |
1705 | ||
c5aa993b | 1706 | void |
386c036b MK |
1707 | sparc32_collect_gregset (const struct sparc_gregset *gregset, |
1708 | const struct regcache *regcache, | |
1709 | int regnum, void *gregs) | |
c906108c | 1710 | { |
e1613aba | 1711 | gdb_byte *regs = gregs; |
386c036b | 1712 | int i; |
c5aa993b | 1713 | |
386c036b MK |
1714 | if (regnum == SPARC32_PSR_REGNUM || regnum == -1) |
1715 | regcache_raw_collect (regcache, SPARC32_PSR_REGNUM, | |
1716 | regs + gregset->r_psr_offset); | |
60054393 | 1717 | |
386c036b MK |
1718 | if (regnum == SPARC32_PC_REGNUM || regnum == -1) |
1719 | regcache_raw_collect (regcache, SPARC32_PC_REGNUM, | |
1720 | regs + gregset->r_pc_offset); | |
1721 | ||
1722 | if (regnum == SPARC32_NPC_REGNUM || regnum == -1) | |
1723 | regcache_raw_collect (regcache, SPARC32_NPC_REGNUM, | |
1724 | regs + gregset->r_npc_offset); | |
5af923b0 | 1725 | |
386c036b MK |
1726 | if (regnum == SPARC32_Y_REGNUM || regnum == -1) |
1727 | regcache_raw_collect (regcache, SPARC32_Y_REGNUM, | |
1728 | regs + gregset->r_y_offset); | |
1729 | ||
1730 | if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1) | |
5af923b0 | 1731 | { |
386c036b MK |
1732 | int offset = gregset->r_g1_offset; |
1733 | ||
1734 | /* %g0 is always zero. */ | |
1735 | for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++) | |
1736 | { | |
1737 | if (regnum == i || regnum == -1) | |
1738 | regcache_raw_collect (regcache, i, regs + offset); | |
1739 | offset += 4; | |
1740 | } | |
5af923b0 | 1741 | } |
386c036b MK |
1742 | |
1743 | if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1) | |
5af923b0 | 1744 | { |
386c036b MK |
1745 | /* Not all of the register set variants include Locals and |
1746 | Inputs. For those that don't, we read them off the stack. */ | |
1747 | if (gregset->r_l0_offset != -1) | |
1748 | { | |
1749 | int offset = gregset->r_l0_offset; | |
1750 | ||
1751 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
1752 | { | |
1753 | if (regnum == i || regnum == -1) | |
1754 | regcache_raw_collect (regcache, i, regs + offset); | |
1755 | offset += 4; | |
1756 | } | |
1757 | } | |
5af923b0 | 1758 | } |
c906108c SS |
1759 | } |
1760 | ||
c906108c | 1761 | void |
386c036b MK |
1762 | sparc32_supply_fpregset (struct regcache *regcache, |
1763 | int regnum, const void *fpregs) | |
c906108c | 1764 | { |
e1613aba | 1765 | const gdb_byte *regs = fpregs; |
386c036b | 1766 | int i; |
60054393 | 1767 | |
386c036b | 1768 | for (i = 0; i < 32; i++) |
c906108c | 1769 | { |
386c036b MK |
1770 | if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1) |
1771 | regcache_raw_supply (regcache, SPARC_F0_REGNUM + i, regs + (i * 4)); | |
c906108c | 1772 | } |
5af923b0 | 1773 | |
386c036b MK |
1774 | if (regnum == SPARC32_FSR_REGNUM || regnum == -1) |
1775 | regcache_raw_supply (regcache, SPARC32_FSR_REGNUM, regs + (32 * 4) + 4); | |
c906108c SS |
1776 | } |
1777 | ||
386c036b MK |
1778 | void |
1779 | sparc32_collect_fpregset (const struct regcache *regcache, | |
1780 | int regnum, void *fpregs) | |
c906108c | 1781 | { |
e1613aba | 1782 | gdb_byte *regs = fpregs; |
386c036b | 1783 | int i; |
c906108c | 1784 | |
386c036b MK |
1785 | for (i = 0; i < 32; i++) |
1786 | { | |
1787 | if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1) | |
1788 | regcache_raw_collect (regcache, SPARC_F0_REGNUM + i, regs + (i * 4)); | |
1789 | } | |
c906108c | 1790 | |
386c036b MK |
1791 | if (regnum == SPARC32_FSR_REGNUM || regnum == -1) |
1792 | regcache_raw_collect (regcache, SPARC32_FSR_REGNUM, regs + (32 * 4) + 4); | |
c906108c | 1793 | } |
c906108c | 1794 | \f |
c906108c | 1795 | |
386c036b | 1796 | /* SunOS 4. */ |
c906108c | 1797 | |
386c036b MK |
1798 | /* From <machine/reg.h>. */ |
1799 | const struct sparc_gregset sparc32_sunos4_gregset = | |
c906108c | 1800 | { |
386c036b MK |
1801 | 0 * 4, /* %psr */ |
1802 | 1 * 4, /* %pc */ | |
1803 | 2 * 4, /* %npc */ | |
1804 | 3 * 4, /* %y */ | |
1805 | -1, /* %wim */ | |
1806 | -1, /* %tbr */ | |
1807 | 4 * 4, /* %g1 */ | |
1808 | -1 /* %l0 */ | |
1809 | }; | |
1810 | \f | |
c906108c | 1811 | |
386c036b MK |
1812 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
1813 | void _initialize_sparc_tdep (void); | |
c906108c SS |
1814 | |
1815 | void | |
386c036b | 1816 | _initialize_sparc_tdep (void) |
c906108c | 1817 | { |
386c036b | 1818 | register_gdbarch_init (bfd_arch_sparc, sparc32_gdbarch_init); |
2d457077 MK |
1819 | |
1820 | /* Initialize the SPARC-specific register types. */ | |
1821 | sparc_init_types(); | |
ef3cf062 | 1822 | } |