Commit | Line | Data |
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386c036b | 1 | /* Target-dependent code for SPARC. |
cda5a58a | 2 | |
0fb0cc75 | 3 | Copyright (C) 2003, 2004, 2005, 2006, 2007, 2008, 2009 |
9b254dd1 | 4 | Free Software Foundation, Inc. |
c906108c | 5 | |
c5aa993b | 6 | This file is part of GDB. |
c906108c | 7 | |
c5aa993b JM |
8 | This program is free software; you can redistribute it and/or modify |
9 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 10 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 11 | (at your option) any later version. |
c906108c | 12 | |
c5aa993b JM |
13 | This program is distributed in the hope that it will be useful, |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
c906108c | 17 | |
c5aa993b | 18 | You should have received a copy of the GNU General Public License |
a9762ec7 | 19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c | 20 | |
c906108c | 21 | #include "defs.h" |
5af923b0 | 22 | #include "arch-utils.h" |
386c036b | 23 | #include "dis-asm.h" |
f5a9b87d | 24 | #include "dwarf2-frame.h" |
386c036b | 25 | #include "floatformat.h" |
c906108c | 26 | #include "frame.h" |
386c036b MK |
27 | #include "frame-base.h" |
28 | #include "frame-unwind.h" | |
29 | #include "gdbcore.h" | |
30 | #include "gdbtypes.h" | |
c906108c | 31 | #include "inferior.h" |
386c036b MK |
32 | #include "symtab.h" |
33 | #include "objfiles.h" | |
34 | #include "osabi.h" | |
35 | #include "regcache.h" | |
c906108c SS |
36 | #include "target.h" |
37 | #include "value.h" | |
c906108c | 38 | |
43bd9a9e | 39 | #include "gdb_assert.h" |
386c036b | 40 | #include "gdb_string.h" |
c906108c | 41 | |
386c036b | 42 | #include "sparc-tdep.h" |
c906108c | 43 | |
a54124c5 MK |
44 | struct regset; |
45 | ||
9eb42ed1 MK |
46 | /* This file implements the SPARC 32-bit ABI as defined by the section |
47 | "Low-Level System Information" of the SPARC Compliance Definition | |
48 | (SCD) 2.4.1, which is the 32-bit System V psABI for SPARC. The SCD | |
f2e7c15d | 49 | lists changes with respect to the original 32-bit psABI as defined |
9eb42ed1 | 50 | in the "System V ABI, SPARC Processor Supplement". |
386c036b MK |
51 | |
52 | Note that if we talk about SunOS, we mean SunOS 4.x, which was | |
53 | BSD-based, which is sometimes (retroactively?) referred to as | |
54 | Solaris 1.x. If we talk about Solaris we mean Solaris 2.x and | |
55 | above (Solaris 7, 8 and 9 are nothing but Solaris 2.7, 2.8 and 2.9 | |
56 | suffering from severe version number inflation). Solaris 2.x is | |
57 | also known as SunOS 5.x, since that's what uname(1) says. Solaris | |
58 | 2.x is SVR4-based. */ | |
59 | ||
60 | /* Please use the sparc32_-prefix for 32-bit specific code, the | |
61 | sparc64_-prefix for 64-bit specific code and the sparc_-prefix for | |
62 | code that can handle both. The 64-bit specific code lives in | |
63 | sparc64-tdep.c; don't add any here. */ | |
64 | ||
65 | /* The SPARC Floating-Point Quad-Precision format is similar to | |
66 | big-endian IA-64 Quad-recision format. */ | |
8da61cc4 | 67 | #define floatformats_sparc_quad floatformats_ia64_quad |
386c036b MK |
68 | |
69 | /* The stack pointer is offset from the stack frame by a BIAS of 2047 | |
70 | (0x7ff) for 64-bit code. BIAS is likely to be defined on SPARC | |
71 | hosts, so undefine it first. */ | |
72 | #undef BIAS | |
73 | #define BIAS 2047 | |
74 | ||
75 | /* Macros to extract fields from SPARC instructions. */ | |
c906108c SS |
76 | #define X_OP(i) (((i) >> 30) & 0x3) |
77 | #define X_RD(i) (((i) >> 25) & 0x1f) | |
78 | #define X_A(i) (((i) >> 29) & 1) | |
79 | #define X_COND(i) (((i) >> 25) & 0xf) | |
80 | #define X_OP2(i) (((i) >> 22) & 0x7) | |
81 | #define X_IMM22(i) ((i) & 0x3fffff) | |
82 | #define X_OP3(i) (((i) >> 19) & 0x3f) | |
075ccec8 | 83 | #define X_RS1(i) (((i) >> 14) & 0x1f) |
b0b92586 | 84 | #define X_RS2(i) ((i) & 0x1f) |
c906108c | 85 | #define X_I(i) (((i) >> 13) & 1) |
c906108c | 86 | /* Sign extension macros. */ |
c906108c | 87 | #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000) |
c906108c | 88 | #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000) |
075ccec8 | 89 | #define X_SIMM13(i) ((((i) & 0x1fff) ^ 0x1000) - 0x1000) |
c906108c | 90 | |
386c036b MK |
91 | /* Fetch the instruction at PC. Instructions are always big-endian |
92 | even if the processor operates in little-endian mode. */ | |
93 | ||
94 | unsigned long | |
95 | sparc_fetch_instruction (CORE_ADDR pc) | |
c906108c | 96 | { |
e1613aba | 97 | gdb_byte buf[4]; |
386c036b MK |
98 | unsigned long insn; |
99 | int i; | |
100 | ||
690668cc | 101 | /* If we can't read the instruction at PC, return zero. */ |
8defab1a | 102 | if (target_read_memory (pc, buf, sizeof (buf))) |
690668cc | 103 | return 0; |
c906108c | 104 | |
386c036b MK |
105 | insn = 0; |
106 | for (i = 0; i < sizeof (buf); i++) | |
107 | insn = (insn << 8) | buf[i]; | |
108 | return insn; | |
109 | } | |
42cdca6c MK |
110 | \f |
111 | ||
5465445a JB |
112 | /* Return non-zero if the instruction corresponding to PC is an "unimp" |
113 | instruction. */ | |
114 | ||
115 | static int | |
116 | sparc_is_unimp_insn (CORE_ADDR pc) | |
117 | { | |
118 | const unsigned long insn = sparc_fetch_instruction (pc); | |
119 | ||
120 | return ((insn & 0xc1c00000) == 0); | |
121 | } | |
122 | ||
42cdca6c MK |
123 | /* OpenBSD/sparc includes StackGhost, which according to the author's |
124 | website http://stackghost.cerias.purdue.edu "... transparently and | |
125 | automatically protects applications' stack frames; more | |
126 | specifically, it guards the return pointers. The protection | |
127 | mechanisms require no application source or binary modification and | |
128 | imposes only a negligible performance penalty." | |
129 | ||
130 | The same website provides the following description of how | |
131 | StackGhost works: | |
132 | ||
133 | "StackGhost interfaces with the kernel trap handler that would | |
134 | normally write out registers to the stack and the handler that | |
135 | would read them back in. By XORing a cookie into the | |
136 | return-address saved in the user stack when it is actually written | |
137 | to the stack, and then XOR it out when the return-address is pulled | |
138 | from the stack, StackGhost can cause attacker corrupted return | |
139 | pointers to behave in a manner the attacker cannot predict. | |
140 | StackGhost can also use several unused bits in the return pointer | |
141 | to detect a smashed return pointer and abort the process." | |
142 | ||
143 | For GDB this means that whenever we're reading %i7 from a stack | |
144 | frame's window save area, we'll have to XOR the cookie. | |
145 | ||
146 | More information on StackGuard can be found on in: | |
147 | ||
148 | Mike Frantzen and Mike Shuey. "StackGhost: Hardware Facilitated | |
149 | Stack Protection." 2001. Published in USENIX Security Symposium | |
150 | '01. */ | |
151 | ||
152 | /* Fetch StackGhost Per-Process XOR cookie. */ | |
153 | ||
154 | ULONGEST | |
e17a4113 | 155 | sparc_fetch_wcookie (struct gdbarch *gdbarch) |
42cdca6c | 156 | { |
e17a4113 | 157 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
baf92889 | 158 | struct target_ops *ops = ¤t_target; |
e1613aba | 159 | gdb_byte buf[8]; |
baf92889 MK |
160 | int len; |
161 | ||
13547ab6 | 162 | len = target_read (ops, TARGET_OBJECT_WCOOKIE, NULL, buf, 0, 8); |
baf92889 MK |
163 | if (len == -1) |
164 | return 0; | |
42cdca6c | 165 | |
baf92889 MK |
166 | /* We should have either an 32-bit or an 64-bit cookie. */ |
167 | gdb_assert (len == 4 || len == 8); | |
168 | ||
e17a4113 | 169 | return extract_unsigned_integer (buf, len, byte_order); |
baf92889 | 170 | } |
386c036b | 171 | \f |
baf92889 | 172 | |
386c036b MK |
173 | /* The functions on this page are intended to be used to classify |
174 | function arguments. */ | |
c906108c | 175 | |
386c036b | 176 | /* Check whether TYPE is "Integral or Pointer". */ |
c906108c | 177 | |
386c036b MK |
178 | static int |
179 | sparc_integral_or_pointer_p (const struct type *type) | |
c906108c | 180 | { |
80ad1639 MK |
181 | int len = TYPE_LENGTH (type); |
182 | ||
386c036b | 183 | switch (TYPE_CODE (type)) |
c906108c | 184 | { |
386c036b MK |
185 | case TYPE_CODE_INT: |
186 | case TYPE_CODE_BOOL: | |
187 | case TYPE_CODE_CHAR: | |
188 | case TYPE_CODE_ENUM: | |
189 | case TYPE_CODE_RANGE: | |
80ad1639 MK |
190 | /* We have byte, half-word, word and extended-word/doubleword |
191 | integral types. The doubleword is an extension to the | |
192 | original 32-bit ABI by the SCD 2.4.x. */ | |
193 | return (len == 1 || len == 2 || len == 4 || len == 8); | |
386c036b MK |
194 | case TYPE_CODE_PTR: |
195 | case TYPE_CODE_REF: | |
80ad1639 MK |
196 | /* Allow either 32-bit or 64-bit pointers. */ |
197 | return (len == 4 || len == 8); | |
386c036b MK |
198 | default: |
199 | break; | |
200 | } | |
c906108c | 201 | |
386c036b MK |
202 | return 0; |
203 | } | |
c906108c | 204 | |
386c036b | 205 | /* Check whether TYPE is "Floating". */ |
c906108c | 206 | |
386c036b MK |
207 | static int |
208 | sparc_floating_p (const struct type *type) | |
209 | { | |
210 | switch (TYPE_CODE (type)) | |
c906108c | 211 | { |
386c036b MK |
212 | case TYPE_CODE_FLT: |
213 | { | |
214 | int len = TYPE_LENGTH (type); | |
215 | return (len == 4 || len == 8 || len == 16); | |
216 | } | |
217 | default: | |
218 | break; | |
219 | } | |
220 | ||
221 | return 0; | |
222 | } | |
c906108c | 223 | |
386c036b | 224 | /* Check whether TYPE is "Structure or Union". */ |
c906108c | 225 | |
386c036b MK |
226 | static int |
227 | sparc_structure_or_union_p (const struct type *type) | |
228 | { | |
229 | switch (TYPE_CODE (type)) | |
230 | { | |
231 | case TYPE_CODE_STRUCT: | |
232 | case TYPE_CODE_UNION: | |
233 | return 1; | |
234 | default: | |
235 | break; | |
c906108c | 236 | } |
386c036b MK |
237 | |
238 | return 0; | |
c906108c | 239 | } |
386c036b MK |
240 | |
241 | /* Register information. */ | |
242 | ||
243 | static const char *sparc32_register_names[] = | |
5af923b0 | 244 | { |
386c036b MK |
245 | "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", |
246 | "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", | |
247 | "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", | |
248 | "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7", | |
249 | ||
250 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
251 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
252 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
253 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
254 | ||
255 | "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr" | |
5af923b0 MS |
256 | }; |
257 | ||
386c036b MK |
258 | /* Total number of registers. */ |
259 | #define SPARC32_NUM_REGS ARRAY_SIZE (sparc32_register_names) | |
c906108c | 260 | |
386c036b MK |
261 | /* We provide the aliases %d0..%d30 for the floating registers as |
262 | "psuedo" registers. */ | |
263 | ||
264 | static const char *sparc32_pseudo_register_names[] = | |
265 | { | |
266 | "d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14", | |
267 | "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30" | |
268 | }; | |
269 | ||
270 | /* Total number of pseudo registers. */ | |
271 | #define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names) | |
272 | ||
273 | /* Return the name of register REGNUM. */ | |
274 | ||
275 | static const char * | |
d93859e2 | 276 | sparc32_register_name (struct gdbarch *gdbarch, int regnum) |
386c036b MK |
277 | { |
278 | if (regnum >= 0 && regnum < SPARC32_NUM_REGS) | |
279 | return sparc32_register_names[regnum]; | |
280 | ||
281 | if (regnum < SPARC32_NUM_REGS + SPARC32_NUM_PSEUDO_REGS) | |
282 | return sparc32_pseudo_register_names[regnum - SPARC32_NUM_REGS]; | |
283 | ||
284 | return NULL; | |
285 | } | |
2d457077 | 286 | \f |
209bd28e | 287 | /* Construct types for ISA-specific registers. */ |
2d457077 | 288 | |
209bd28e UW |
289 | static struct type * |
290 | sparc_psr_type (struct gdbarch *gdbarch) | |
291 | { | |
292 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2d457077 | 293 | |
209bd28e UW |
294 | if (!tdep->sparc_psr_type) |
295 | { | |
296 | struct type *type; | |
2d457077 | 297 | |
e9bb382b | 298 | type = arch_flags_type (gdbarch, "builtin_type_sparc_psr", 4); |
209bd28e UW |
299 | append_flags_type_flag (type, 5, "ET"); |
300 | append_flags_type_flag (type, 6, "PS"); | |
301 | append_flags_type_flag (type, 7, "S"); | |
302 | append_flags_type_flag (type, 12, "EF"); | |
303 | append_flags_type_flag (type, 13, "EC"); | |
2d457077 | 304 | |
209bd28e UW |
305 | tdep->sparc_psr_type = type; |
306 | } | |
307 | ||
308 | return tdep->sparc_psr_type; | |
309 | } | |
310 | ||
311 | static struct type * | |
312 | sparc_fsr_type (struct gdbarch *gdbarch) | |
2d457077 | 313 | { |
209bd28e UW |
314 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
315 | ||
316 | if (!tdep->sparc_fsr_type) | |
317 | { | |
318 | struct type *type; | |
319 | ||
e9bb382b | 320 | type = arch_flags_type (gdbarch, "builtin_type_sparc_fsr", 4); |
209bd28e UW |
321 | append_flags_type_flag (type, 0, "NXA"); |
322 | append_flags_type_flag (type, 1, "DZA"); | |
323 | append_flags_type_flag (type, 2, "UFA"); | |
324 | append_flags_type_flag (type, 3, "OFA"); | |
325 | append_flags_type_flag (type, 4, "NVA"); | |
326 | append_flags_type_flag (type, 5, "NXC"); | |
327 | append_flags_type_flag (type, 6, "DZC"); | |
328 | append_flags_type_flag (type, 7, "UFC"); | |
329 | append_flags_type_flag (type, 8, "OFC"); | |
330 | append_flags_type_flag (type, 9, "NVC"); | |
331 | append_flags_type_flag (type, 22, "NS"); | |
332 | append_flags_type_flag (type, 23, "NXM"); | |
333 | append_flags_type_flag (type, 24, "DZM"); | |
334 | append_flags_type_flag (type, 25, "UFM"); | |
335 | append_flags_type_flag (type, 26, "OFM"); | |
336 | append_flags_type_flag (type, 27, "NVM"); | |
337 | ||
338 | tdep->sparc_fsr_type = type; | |
339 | } | |
340 | ||
341 | return tdep->sparc_fsr_type; | |
2d457077 | 342 | } |
386c036b MK |
343 | |
344 | /* Return the GDB type object for the "standard" data type of data in | |
345 | register REGNUM. */ | |
346 | ||
347 | static struct type * | |
348 | sparc32_register_type (struct gdbarch *gdbarch, int regnum) | |
349 | { | |
350 | if (regnum >= SPARC_F0_REGNUM && regnum <= SPARC_F31_REGNUM) | |
0dfff4cb | 351 | return builtin_type (gdbarch)->builtin_float; |
386c036b MK |
352 | |
353 | if (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM) | |
0dfff4cb | 354 | return builtin_type (gdbarch)->builtin_double; |
386c036b MK |
355 | |
356 | if (regnum == SPARC_SP_REGNUM || regnum == SPARC_FP_REGNUM) | |
0dfff4cb | 357 | return builtin_type (gdbarch)->builtin_data_ptr; |
386c036b MK |
358 | |
359 | if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM) | |
0dfff4cb | 360 | return builtin_type (gdbarch)->builtin_func_ptr; |
386c036b | 361 | |
2d457077 | 362 | if (regnum == SPARC32_PSR_REGNUM) |
209bd28e | 363 | return sparc_psr_type (gdbarch); |
2d457077 MK |
364 | |
365 | if (regnum == SPARC32_FSR_REGNUM) | |
209bd28e | 366 | return sparc_fsr_type (gdbarch); |
2d457077 | 367 | |
df4df182 | 368 | return builtin_type (gdbarch)->builtin_int32; |
386c036b MK |
369 | } |
370 | ||
371 | static void | |
372 | sparc32_pseudo_register_read (struct gdbarch *gdbarch, | |
373 | struct regcache *regcache, | |
e1613aba | 374 | int regnum, gdb_byte *buf) |
386c036b MK |
375 | { |
376 | gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM); | |
377 | ||
378 | regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM); | |
379 | regcache_raw_read (regcache, regnum, buf); | |
e1613aba | 380 | regcache_raw_read (regcache, regnum + 1, buf + 4); |
386c036b MK |
381 | } |
382 | ||
383 | static void | |
384 | sparc32_pseudo_register_write (struct gdbarch *gdbarch, | |
385 | struct regcache *regcache, | |
e1613aba | 386 | int regnum, const gdb_byte *buf) |
386c036b MK |
387 | { |
388 | gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM); | |
389 | ||
390 | regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM); | |
391 | regcache_raw_write (regcache, regnum, buf); | |
e1613aba | 392 | regcache_raw_write (regcache, regnum + 1, buf + 4); |
386c036b MK |
393 | } |
394 | \f | |
395 | ||
396 | static CORE_ADDR | |
397 | sparc32_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, | |
82585c72 | 398 | CORE_ADDR funcaddr, |
386c036b MK |
399 | struct value **args, int nargs, |
400 | struct type *value_type, | |
e4fd649a UW |
401 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr, |
402 | struct regcache *regcache) | |
c906108c | 403 | { |
e17a4113 UW |
404 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
405 | ||
386c036b MK |
406 | *bp_addr = sp - 4; |
407 | *real_pc = funcaddr; | |
408 | ||
d80b854b | 409 | if (using_struct_return (gdbarch, NULL, value_type)) |
c906108c | 410 | { |
e1613aba | 411 | gdb_byte buf[4]; |
386c036b MK |
412 | |
413 | /* This is an UNIMP instruction. */ | |
e17a4113 UW |
414 | store_unsigned_integer (buf, 4, byte_order, |
415 | TYPE_LENGTH (value_type) & 0x1fff); | |
386c036b MK |
416 | write_memory (sp - 8, buf, 4); |
417 | return sp - 8; | |
c906108c SS |
418 | } |
419 | ||
386c036b MK |
420 | return sp - 4; |
421 | } | |
422 | ||
423 | static CORE_ADDR | |
424 | sparc32_store_arguments (struct regcache *regcache, int nargs, | |
425 | struct value **args, CORE_ADDR sp, | |
426 | int struct_return, CORE_ADDR struct_addr) | |
427 | { | |
df4df182 | 428 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
e17a4113 | 429 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
386c036b MK |
430 | /* Number of words in the "parameter array". */ |
431 | int num_elements = 0; | |
432 | int element = 0; | |
433 | int i; | |
434 | ||
435 | for (i = 0; i < nargs; i++) | |
c906108c | 436 | { |
4991999e | 437 | struct type *type = value_type (args[i]); |
386c036b MK |
438 | int len = TYPE_LENGTH (type); |
439 | ||
440 | if (sparc_structure_or_union_p (type) | |
441 | || (sparc_floating_p (type) && len == 16)) | |
c906108c | 442 | { |
386c036b MK |
443 | /* Structure, Union and Quad-Precision Arguments. */ |
444 | sp -= len; | |
445 | ||
446 | /* Use doubleword alignment for these values. That's always | |
447 | correct, and wasting a few bytes shouldn't be a problem. */ | |
448 | sp &= ~0x7; | |
449 | ||
0fd88904 | 450 | write_memory (sp, value_contents (args[i]), len); |
386c036b MK |
451 | args[i] = value_from_pointer (lookup_pointer_type (type), sp); |
452 | num_elements++; | |
453 | } | |
454 | else if (sparc_floating_p (type)) | |
455 | { | |
456 | /* Floating arguments. */ | |
457 | gdb_assert (len == 4 || len == 8); | |
458 | num_elements += (len / 4); | |
c906108c | 459 | } |
c5aa993b JM |
460 | else |
461 | { | |
386c036b MK |
462 | /* Integral and pointer arguments. */ |
463 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
464 | ||
465 | if (len < 4) | |
df4df182 UW |
466 | args[i] = value_cast (builtin_type (gdbarch)->builtin_int32, |
467 | args[i]); | |
386c036b | 468 | num_elements += ((len + 3) / 4); |
c5aa993b | 469 | } |
c906108c | 470 | } |
c906108c | 471 | |
386c036b MK |
472 | /* Always allocate at least six words. */ |
473 | sp -= max (6, num_elements) * 4; | |
c906108c | 474 | |
386c036b MK |
475 | /* The psABI says that "Software convention requires space for the |
476 | struct/union return value pointer, even if the word is unused." */ | |
477 | sp -= 4; | |
c906108c | 478 | |
386c036b MK |
479 | /* The psABI says that "Although software convention and the |
480 | operating system require every stack frame to be doubleword | |
481 | aligned." */ | |
482 | sp &= ~0x7; | |
c906108c | 483 | |
386c036b | 484 | for (i = 0; i < nargs; i++) |
c906108c | 485 | { |
0fd88904 | 486 | const bfd_byte *valbuf = value_contents (args[i]); |
4991999e | 487 | struct type *type = value_type (args[i]); |
386c036b | 488 | int len = TYPE_LENGTH (type); |
c906108c | 489 | |
386c036b | 490 | gdb_assert (len == 4 || len == 8); |
c906108c | 491 | |
386c036b MK |
492 | if (element < 6) |
493 | { | |
494 | int regnum = SPARC_O0_REGNUM + element; | |
c906108c | 495 | |
386c036b MK |
496 | regcache_cooked_write (regcache, regnum, valbuf); |
497 | if (len > 4 && element < 5) | |
498 | regcache_cooked_write (regcache, regnum + 1, valbuf + 4); | |
499 | } | |
5af923b0 | 500 | |
386c036b MK |
501 | /* Always store the argument in memory. */ |
502 | write_memory (sp + 4 + element * 4, valbuf, len); | |
503 | element += len / 4; | |
504 | } | |
c906108c | 505 | |
386c036b | 506 | gdb_assert (element == num_elements); |
c906108c | 507 | |
386c036b | 508 | if (struct_return) |
c906108c | 509 | { |
e1613aba | 510 | gdb_byte buf[4]; |
c906108c | 511 | |
e17a4113 | 512 | store_unsigned_integer (buf, 4, byte_order, struct_addr); |
386c036b MK |
513 | write_memory (sp, buf, 4); |
514 | } | |
c906108c | 515 | |
386c036b | 516 | return sp; |
c906108c SS |
517 | } |
518 | ||
386c036b | 519 | static CORE_ADDR |
7d9b040b | 520 | sparc32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
386c036b MK |
521 | struct regcache *regcache, CORE_ADDR bp_addr, |
522 | int nargs, struct value **args, CORE_ADDR sp, | |
523 | int struct_return, CORE_ADDR struct_addr) | |
c906108c | 524 | { |
386c036b MK |
525 | CORE_ADDR call_pc = (struct_return ? (bp_addr - 12) : (bp_addr - 8)); |
526 | ||
527 | /* Set return address. */ | |
528 | regcache_cooked_write_unsigned (regcache, SPARC_O7_REGNUM, call_pc); | |
529 | ||
530 | /* Set up function arguments. */ | |
531 | sp = sparc32_store_arguments (regcache, nargs, args, sp, | |
532 | struct_return, struct_addr); | |
533 | ||
534 | /* Allocate the 16-word window save area. */ | |
535 | sp -= 16 * 4; | |
c906108c | 536 | |
386c036b MK |
537 | /* Stack should be doubleword aligned at this point. */ |
538 | gdb_assert (sp % 8 == 0); | |
c906108c | 539 | |
386c036b MK |
540 | /* Finally, update the stack pointer. */ |
541 | regcache_cooked_write_unsigned (regcache, SPARC_SP_REGNUM, sp); | |
542 | ||
543 | return sp; | |
544 | } | |
545 | \f | |
c906108c | 546 | |
386c036b MK |
547 | /* Use the program counter to determine the contents and size of a |
548 | breakpoint instruction. Return a pointer to a string of bytes that | |
549 | encode a breakpoint instruction, store the length of the string in | |
550 | *LEN and optionally adjust *PC to point to the correct memory | |
551 | location for inserting the breakpoint. */ | |
552 | ||
e1613aba | 553 | static const gdb_byte * |
67d57894 | 554 | sparc_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len) |
386c036b | 555 | { |
864a1a37 | 556 | static const gdb_byte break_insn[] = { 0x91, 0xd0, 0x20, 0x01 }; |
c5aa993b | 557 | |
386c036b MK |
558 | *len = sizeof (break_insn); |
559 | return break_insn; | |
c906108c | 560 | } |
386c036b | 561 | \f |
c906108c | 562 | |
386c036b | 563 | /* Allocate and initialize a frame cache. */ |
c906108c | 564 | |
386c036b MK |
565 | static struct sparc_frame_cache * |
566 | sparc_alloc_frame_cache (void) | |
567 | { | |
568 | struct sparc_frame_cache *cache; | |
569 | int i; | |
c906108c | 570 | |
386c036b | 571 | cache = FRAME_OBSTACK_ZALLOC (struct sparc_frame_cache); |
c906108c | 572 | |
386c036b MK |
573 | /* Base address. */ |
574 | cache->base = 0; | |
575 | cache->pc = 0; | |
c906108c | 576 | |
386c036b MK |
577 | /* Frameless until proven otherwise. */ |
578 | cache->frameless_p = 1; | |
579 | ||
580 | cache->struct_return_p = 0; | |
581 | ||
582 | return cache; | |
583 | } | |
584 | ||
b0b92586 JB |
585 | /* GCC generates several well-known sequences of instructions at the begining |
586 | of each function prologue when compiling with -fstack-check. If one of | |
587 | such sequences starts at START_PC, then return the address of the | |
588 | instruction immediately past this sequence. Otherwise, return START_PC. */ | |
589 | ||
590 | static CORE_ADDR | |
591 | sparc_skip_stack_check (const CORE_ADDR start_pc) | |
592 | { | |
593 | CORE_ADDR pc = start_pc; | |
594 | unsigned long insn; | |
595 | int offset_stack_checking_sequence = 0; | |
596 | ||
597 | /* With GCC, all stack checking sequences begin with the same two | |
598 | instructions. */ | |
599 | ||
600 | /* sethi <some immediate>,%g1 */ | |
601 | insn = sparc_fetch_instruction (pc); | |
602 | pc = pc + 4; | |
603 | if (!(X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 1)) | |
604 | return start_pc; | |
605 | ||
606 | /* sub %sp, %g1, %g1 */ | |
607 | insn = sparc_fetch_instruction (pc); | |
608 | pc = pc + 4; | |
609 | if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn) | |
610 | && X_RD (insn) == 1 && X_RS1 (insn) == 14 && X_RS2 (insn) == 1)) | |
611 | return start_pc; | |
612 | ||
613 | insn = sparc_fetch_instruction (pc); | |
614 | pc = pc + 4; | |
615 | ||
616 | /* First possible sequence: | |
617 | [first two instructions above] | |
618 | clr [%g1 - some immediate] */ | |
619 | ||
620 | /* clr [%g1 - some immediate] */ | |
621 | if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) | |
622 | && X_RS1 (insn) == 1 && X_RD (insn) == 0) | |
623 | { | |
624 | /* Valid stack-check sequence, return the new PC. */ | |
625 | return pc; | |
626 | } | |
627 | ||
628 | /* Second possible sequence: A small number of probes. | |
629 | [first two instructions above] | |
630 | clr [%g1] | |
631 | add %g1, -<some immediate>, %g1 | |
632 | clr [%g1] | |
633 | [repeat the two instructions above any (small) number of times] | |
634 | clr [%g1 - some immediate] */ | |
635 | ||
636 | /* clr [%g1] */ | |
637 | else if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn) | |
638 | && X_RS1 (insn) == 1 && X_RD (insn) == 0) | |
639 | { | |
640 | while (1) | |
641 | { | |
642 | /* add %g1, -<some immediate>, %g1 */ | |
643 | insn = sparc_fetch_instruction (pc); | |
644 | pc = pc + 4; | |
645 | if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn) | |
646 | && X_RS1 (insn) == 1 && X_RD (insn) == 1)) | |
647 | break; | |
648 | ||
649 | /* clr [%g1] */ | |
650 | insn = sparc_fetch_instruction (pc); | |
651 | pc = pc + 4; | |
652 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn) | |
653 | && X_RD (insn) == 0 && X_RS1 (insn) == 1)) | |
654 | return start_pc; | |
655 | } | |
656 | ||
657 | /* clr [%g1 - some immediate] */ | |
658 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) | |
659 | && X_RS1 (insn) == 1 && X_RD (insn) == 0)) | |
660 | return start_pc; | |
661 | ||
662 | /* We found a valid stack-check sequence, return the new PC. */ | |
663 | return pc; | |
664 | } | |
665 | ||
666 | /* Third sequence: A probing loop. | |
667 | [first two instructions above] | |
668 | sethi <some immediate>, %g4 | |
669 | sub %g1, %g4, %g4 | |
670 | cmp %g1, %g4 | |
671 | be <disp> | |
672 | add %g1, -<some immediate>, %g1 | |
673 | ba <disp> | |
674 | clr [%g1] | |
675 | clr [%g4 - some immediate] */ | |
676 | ||
677 | /* sethi <some immediate>, %g4 */ | |
678 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 4) | |
679 | { | |
680 | /* sub %g1, %g4, %g4 */ | |
681 | insn = sparc_fetch_instruction (pc); | |
682 | pc = pc + 4; | |
683 | if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn) | |
684 | && X_RD (insn) == 4 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4)) | |
685 | return start_pc; | |
686 | ||
687 | /* cmp %g1, %g4 */ | |
688 | insn = sparc_fetch_instruction (pc); | |
689 | pc = pc + 4; | |
690 | if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x14 && !X_I(insn) | |
691 | && X_RD (insn) == 0 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4)) | |
692 | return start_pc; | |
693 | ||
694 | /* be <disp> */ | |
695 | insn = sparc_fetch_instruction (pc); | |
696 | pc = pc + 4; | |
697 | if (!(X_OP (insn) == 0 && X_COND (insn) == 0x1)) | |
698 | return start_pc; | |
699 | ||
700 | /* add %g1, -<some immediate>, %g1 */ | |
701 | insn = sparc_fetch_instruction (pc); | |
702 | pc = pc + 4; | |
703 | if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn) | |
704 | && X_RS1 (insn) == 1 && X_RD (insn) == 1)) | |
705 | return start_pc; | |
706 | ||
707 | /* ba <disp> */ | |
708 | insn = sparc_fetch_instruction (pc); | |
709 | pc = pc + 4; | |
710 | if (!(X_OP (insn) == 0 && X_COND (insn) == 0x8)) | |
711 | return start_pc; | |
712 | ||
713 | /* clr [%g1] */ | |
714 | insn = sparc_fetch_instruction (pc); | |
715 | pc = pc + 4; | |
716 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn) | |
717 | && X_RD (insn) == 0 && X_RS1 (insn) == 1)) | |
718 | return start_pc; | |
719 | ||
720 | /* clr [%g4 - some immediate] */ | |
721 | insn = sparc_fetch_instruction (pc); | |
722 | pc = pc + 4; | |
723 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) | |
724 | && X_RS1 (insn) == 4 && X_RD (insn) == 0)) | |
725 | return start_pc; | |
726 | ||
727 | /* We found a valid stack-check sequence, return the new PC. */ | |
728 | return pc; | |
729 | } | |
730 | ||
731 | /* No stack check code in our prologue, return the start_pc. */ | |
732 | return start_pc; | |
733 | } | |
734 | ||
386c036b | 735 | CORE_ADDR |
be8626e0 MD |
736 | sparc_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, |
737 | CORE_ADDR current_pc, struct sparc_frame_cache *cache) | |
c906108c | 738 | { |
be8626e0 | 739 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
386c036b MK |
740 | unsigned long insn; |
741 | int offset = 0; | |
c906108c | 742 | int dest = -1; |
c906108c | 743 | |
b0b92586 JB |
744 | pc = sparc_skip_stack_check (pc); |
745 | ||
386c036b MK |
746 | if (current_pc <= pc) |
747 | return current_pc; | |
748 | ||
749 | /* We have to handle to "Procedure Linkage Table" (PLT) special. On | |
750 | SPARC the linker usually defines a symbol (typically | |
751 | _PROCEDURE_LINKAGE_TABLE_) at the start of the .plt section. | |
752 | This symbol makes us end up here with PC pointing at the start of | |
753 | the PLT and CURRENT_PC probably pointing at a PLT entry. If we | |
754 | would do our normal prologue analysis, we would probably conclude | |
755 | that we've got a frame when in reality we don't, since the | |
756 | dynamic linker patches up the first PLT with some code that | |
757 | starts with a SAVE instruction. Patch up PC such that it points | |
758 | at the start of our PLT entry. */ | |
759 | if (tdep->plt_entry_size > 0 && in_plt_section (current_pc, NULL)) | |
760 | pc = current_pc - ((current_pc - pc) % tdep->plt_entry_size); | |
c906108c | 761 | |
386c036b MK |
762 | insn = sparc_fetch_instruction (pc); |
763 | ||
764 | /* Recognize a SETHI insn and record its destination. */ | |
765 | if (X_OP (insn) == 0 && X_OP2 (insn) == 0x04) | |
c906108c SS |
766 | { |
767 | dest = X_RD (insn); | |
386c036b MK |
768 | offset += 4; |
769 | ||
770 | insn = sparc_fetch_instruction (pc + 4); | |
c906108c SS |
771 | } |
772 | ||
386c036b MK |
773 | /* Allow for an arithmetic operation on DEST or %g1. */ |
774 | if (X_OP (insn) == 2 && X_I (insn) | |
c906108c SS |
775 | && (X_RD (insn) == 1 || X_RD (insn) == dest)) |
776 | { | |
386c036b | 777 | offset += 4; |
c906108c | 778 | |
386c036b | 779 | insn = sparc_fetch_instruction (pc + 8); |
c906108c | 780 | } |
c906108c | 781 | |
386c036b MK |
782 | /* Check for the SAVE instruction that sets up the frame. */ |
783 | if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3c) | |
c906108c | 784 | { |
386c036b MK |
785 | cache->frameless_p = 0; |
786 | return pc + offset + 4; | |
c906108c SS |
787 | } |
788 | ||
789 | return pc; | |
790 | } | |
791 | ||
386c036b | 792 | static CORE_ADDR |
236369e7 | 793 | sparc_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame) |
386c036b MK |
794 | { |
795 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
236369e7 | 796 | return frame_unwind_register_unsigned (this_frame, tdep->pc_regnum); |
386c036b MK |
797 | } |
798 | ||
799 | /* Return PC of first real instruction of the function starting at | |
800 | START_PC. */ | |
f510d44e | 801 | |
386c036b | 802 | static CORE_ADDR |
6093d2eb | 803 | sparc32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
c906108c | 804 | { |
f510d44e DM |
805 | struct symtab_and_line sal; |
806 | CORE_ADDR func_start, func_end; | |
386c036b | 807 | struct sparc_frame_cache cache; |
f510d44e DM |
808 | |
809 | /* This is the preferred method, find the end of the prologue by | |
810 | using the debugging information. */ | |
811 | if (find_pc_partial_function (start_pc, NULL, &func_start, &func_end)) | |
812 | { | |
813 | sal = find_pc_line (func_start, 0); | |
814 | ||
815 | if (sal.end < func_end | |
816 | && start_pc <= sal.end) | |
817 | return sal.end; | |
818 | } | |
819 | ||
be8626e0 | 820 | start_pc = sparc_analyze_prologue (gdbarch, start_pc, 0xffffffffUL, &cache); |
075ccec8 MK |
821 | |
822 | /* The psABI says that "Although the first 6 words of arguments | |
823 | reside in registers, the standard stack frame reserves space for | |
824 | them.". It also suggests that a function may use that space to | |
825 | "write incoming arguments 0 to 5" into that space, and that's | |
826 | indeed what GCC seems to be doing. In that case GCC will | |
827 | generate debug information that points to the stack slots instead | |
828 | of the registers, so we should consider the instructions that | |
829 | write out these incoming arguments onto the stack. Of course we | |
830 | only need to do this if we have a stack frame. */ | |
831 | ||
832 | while (!cache.frameless_p) | |
833 | { | |
834 | unsigned long insn = sparc_fetch_instruction (start_pc); | |
835 | ||
836 | /* Recognize instructions that store incoming arguments in | |
837 | %i0...%i5 into the corresponding stack slot. */ | |
838 | if (X_OP (insn) == 3 && (X_OP3 (insn) & 0x3c) == 0x04 && X_I (insn) | |
839 | && (X_RD (insn) >= 24 && X_RD (insn) <= 29) && X_RS1 (insn) == 30 | |
840 | && X_SIMM13 (insn) == 68 + (X_RD (insn) - 24) * 4) | |
841 | { | |
842 | start_pc += 4; | |
843 | continue; | |
844 | } | |
845 | ||
846 | break; | |
847 | } | |
848 | ||
849 | return start_pc; | |
c906108c SS |
850 | } |
851 | ||
386c036b | 852 | /* Normal frames. */ |
9319a2fe | 853 | |
386c036b | 854 | struct sparc_frame_cache * |
236369e7 | 855 | sparc_frame_cache (struct frame_info *this_frame, void **this_cache) |
9319a2fe | 856 | { |
386c036b | 857 | struct sparc_frame_cache *cache; |
9319a2fe | 858 | |
386c036b MK |
859 | if (*this_cache) |
860 | return *this_cache; | |
c906108c | 861 | |
386c036b MK |
862 | cache = sparc_alloc_frame_cache (); |
863 | *this_cache = cache; | |
c906108c | 864 | |
236369e7 | 865 | cache->pc = get_frame_func (this_frame); |
386c036b | 866 | if (cache->pc != 0) |
236369e7 JB |
867 | sparc_analyze_prologue (get_frame_arch (this_frame), cache->pc, |
868 | get_frame_pc (this_frame), cache); | |
386c036b MK |
869 | |
870 | if (cache->frameless_p) | |
c906108c | 871 | { |
cbeae229 MK |
872 | /* This function is frameless, so %fp (%i6) holds the frame |
873 | pointer for our calling frame. Use %sp (%o6) as this frame's | |
874 | base address. */ | |
875 | cache->base = | |
236369e7 | 876 | get_frame_register_unsigned (this_frame, SPARC_SP_REGNUM); |
cbeae229 MK |
877 | } |
878 | else | |
879 | { | |
880 | /* For normal frames, %fp (%i6) holds the frame pointer, the | |
881 | base address for the current stack frame. */ | |
882 | cache->base = | |
236369e7 | 883 | get_frame_register_unsigned (this_frame, SPARC_FP_REGNUM); |
c906108c | 884 | } |
c906108c | 885 | |
5b2d44a0 MK |
886 | if (cache->base & 1) |
887 | cache->base += BIAS; | |
888 | ||
386c036b | 889 | return cache; |
c906108c | 890 | } |
c906108c | 891 | |
aff37fc1 DM |
892 | static int |
893 | sparc32_struct_return_from_sym (struct symbol *sym) | |
894 | { | |
895 | struct type *type = check_typedef (SYMBOL_TYPE (sym)); | |
896 | enum type_code code = TYPE_CODE (type); | |
897 | ||
898 | if (code == TYPE_CODE_FUNC || code == TYPE_CODE_METHOD) | |
899 | { | |
900 | type = check_typedef (TYPE_TARGET_TYPE (type)); | |
901 | if (sparc_structure_or_union_p (type) | |
902 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)) | |
903 | return 1; | |
904 | } | |
905 | ||
906 | return 0; | |
907 | } | |
908 | ||
386c036b | 909 | struct sparc_frame_cache * |
236369e7 | 910 | sparc32_frame_cache (struct frame_info *this_frame, void **this_cache) |
c906108c | 911 | { |
386c036b MK |
912 | struct sparc_frame_cache *cache; |
913 | struct symbol *sym; | |
c906108c | 914 | |
386c036b MK |
915 | if (*this_cache) |
916 | return *this_cache; | |
c906108c | 917 | |
236369e7 | 918 | cache = sparc_frame_cache (this_frame, this_cache); |
c906108c | 919 | |
386c036b MK |
920 | sym = find_pc_function (cache->pc); |
921 | if (sym) | |
c906108c | 922 | { |
aff37fc1 | 923 | cache->struct_return_p = sparc32_struct_return_from_sym (sym); |
c906108c | 924 | } |
5465445a JB |
925 | else |
926 | { | |
927 | /* There is no debugging information for this function to | |
928 | help us determine whether this function returns a struct | |
929 | or not. So we rely on another heuristic which is to check | |
930 | the instruction at the return address and see if this is | |
931 | an "unimp" instruction. If it is, then it is a struct-return | |
932 | function. */ | |
933 | CORE_ADDR pc; | |
934 | int regnum = cache->frameless_p ? SPARC_O7_REGNUM : SPARC_I7_REGNUM; | |
935 | ||
236369e7 | 936 | pc = get_frame_register_unsigned (this_frame, regnum) + 8; |
5465445a JB |
937 | if (sparc_is_unimp_insn (pc)) |
938 | cache->struct_return_p = 1; | |
939 | } | |
c906108c | 940 | |
386c036b MK |
941 | return cache; |
942 | } | |
943 | ||
944 | static void | |
236369e7 | 945 | sparc32_frame_this_id (struct frame_info *this_frame, void **this_cache, |
386c036b MK |
946 | struct frame_id *this_id) |
947 | { | |
948 | struct sparc_frame_cache *cache = | |
236369e7 | 949 | sparc32_frame_cache (this_frame, this_cache); |
386c036b MK |
950 | |
951 | /* This marks the outermost frame. */ | |
952 | if (cache->base == 0) | |
953 | return; | |
954 | ||
955 | (*this_id) = frame_id_build (cache->base, cache->pc); | |
956 | } | |
c906108c | 957 | |
236369e7 JB |
958 | static struct value * |
959 | sparc32_frame_prev_register (struct frame_info *this_frame, | |
960 | void **this_cache, int regnum) | |
386c036b | 961 | { |
e17a4113 | 962 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
386c036b | 963 | struct sparc_frame_cache *cache = |
236369e7 | 964 | sparc32_frame_cache (this_frame, this_cache); |
c906108c | 965 | |
386c036b | 966 | if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM) |
c906108c | 967 | { |
236369e7 | 968 | CORE_ADDR pc = (regnum == SPARC32_NPC_REGNUM) ? 4 : 0; |
386c036b | 969 | |
236369e7 JB |
970 | /* If this functions has a Structure, Union or Quad-Precision |
971 | return value, we have to skip the UNIMP instruction that encodes | |
972 | the size of the structure. */ | |
973 | if (cache->struct_return_p) | |
974 | pc += 4; | |
386c036b | 975 | |
236369e7 JB |
976 | regnum = cache->frameless_p ? SPARC_O7_REGNUM : SPARC_I7_REGNUM; |
977 | pc += get_frame_register_unsigned (this_frame, regnum) + 8; | |
978 | return frame_unwind_got_constant (this_frame, regnum, pc); | |
c906108c SS |
979 | } |
980 | ||
42cdca6c MK |
981 | /* Handle StackGhost. */ |
982 | { | |
e17a4113 | 983 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
42cdca6c MK |
984 | |
985 | if (wcookie != 0 && !cache->frameless_p && regnum == SPARC_I7_REGNUM) | |
986 | { | |
236369e7 JB |
987 | CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4; |
988 | ULONGEST i7; | |
989 | ||
990 | /* Read the value in from memory. */ | |
991 | i7 = get_frame_memory_unsigned (this_frame, addr, 4); | |
992 | return frame_unwind_got_constant (this_frame, regnum, i7 ^ wcookie); | |
42cdca6c MK |
993 | } |
994 | } | |
995 | ||
386c036b MK |
996 | /* The previous frame's `local' and `in' registers have been saved |
997 | in the register save area. */ | |
998 | if (!cache->frameless_p | |
999 | && regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) | |
c906108c | 1000 | { |
236369e7 | 1001 | CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4; |
386c036b | 1002 | |
236369e7 | 1003 | return frame_unwind_got_memory (this_frame, regnum, addr); |
386c036b | 1004 | } |
c906108c | 1005 | |
236369e7 | 1006 | /* The previous frame's `out' registers are accessible as the |
386c036b MK |
1007 | current frame's `in' registers. */ |
1008 | if (!cache->frameless_p | |
1009 | && regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O7_REGNUM) | |
1010 | regnum += (SPARC_I0_REGNUM - SPARC_O0_REGNUM); | |
5af923b0 | 1011 | |
236369e7 | 1012 | return frame_unwind_got_register (this_frame, regnum, regnum); |
386c036b | 1013 | } |
c906108c | 1014 | |
386c036b MK |
1015 | static const struct frame_unwind sparc32_frame_unwind = |
1016 | { | |
1017 | NORMAL_FRAME, | |
1018 | sparc32_frame_this_id, | |
236369e7 JB |
1019 | sparc32_frame_prev_register, |
1020 | NULL, | |
1021 | default_frame_sniffer | |
386c036b | 1022 | }; |
386c036b | 1023 | \f |
c906108c | 1024 | |
386c036b | 1025 | static CORE_ADDR |
236369e7 | 1026 | sparc32_frame_base_address (struct frame_info *this_frame, void **this_cache) |
386c036b MK |
1027 | { |
1028 | struct sparc_frame_cache *cache = | |
236369e7 | 1029 | sparc32_frame_cache (this_frame, this_cache); |
c906108c | 1030 | |
386c036b MK |
1031 | return cache->base; |
1032 | } | |
c906108c | 1033 | |
386c036b MK |
1034 | static const struct frame_base sparc32_frame_base = |
1035 | { | |
1036 | &sparc32_frame_unwind, | |
1037 | sparc32_frame_base_address, | |
1038 | sparc32_frame_base_address, | |
1039 | sparc32_frame_base_address | |
1040 | }; | |
c906108c | 1041 | |
386c036b | 1042 | static struct frame_id |
236369e7 | 1043 | sparc_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
386c036b MK |
1044 | { |
1045 | CORE_ADDR sp; | |
5af923b0 | 1046 | |
236369e7 | 1047 | sp = get_frame_register_unsigned (this_frame, SPARC_SP_REGNUM); |
5b2d44a0 MK |
1048 | if (sp & 1) |
1049 | sp += BIAS; | |
236369e7 | 1050 | return frame_id_build (sp, get_frame_pc (this_frame)); |
386c036b MK |
1051 | } |
1052 | \f | |
c906108c | 1053 | |
3923a2b2 MK |
1054 | /* Extract a function return value of TYPE from REGCACHE, and copy |
1055 | that into VALBUF. */ | |
5af923b0 | 1056 | |
386c036b MK |
1057 | static void |
1058 | sparc32_extract_return_value (struct type *type, struct regcache *regcache, | |
e1613aba | 1059 | gdb_byte *valbuf) |
386c036b MK |
1060 | { |
1061 | int len = TYPE_LENGTH (type); | |
e1613aba | 1062 | gdb_byte buf[8]; |
c906108c | 1063 | |
386c036b MK |
1064 | gdb_assert (!sparc_structure_or_union_p (type)); |
1065 | gdb_assert (!(sparc_floating_p (type) && len == 16)); | |
c906108c | 1066 | |
386c036b | 1067 | if (sparc_floating_p (type)) |
5af923b0 | 1068 | { |
386c036b MK |
1069 | /* Floating return values. */ |
1070 | regcache_cooked_read (regcache, SPARC_F0_REGNUM, buf); | |
1071 | if (len > 4) | |
1072 | regcache_cooked_read (regcache, SPARC_F1_REGNUM, buf + 4); | |
1073 | memcpy (valbuf, buf, len); | |
5af923b0 MS |
1074 | } |
1075 | else | |
1076 | { | |
386c036b MK |
1077 | /* Integral and pointer return values. */ |
1078 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
c906108c | 1079 | |
386c036b MK |
1080 | regcache_cooked_read (regcache, SPARC_O0_REGNUM, buf); |
1081 | if (len > 4) | |
1082 | { | |
1083 | regcache_cooked_read (regcache, SPARC_O1_REGNUM, buf + 4); | |
1084 | gdb_assert (len == 8); | |
1085 | memcpy (valbuf, buf, 8); | |
1086 | } | |
1087 | else | |
1088 | { | |
1089 | /* Just stripping off any unused bytes should preserve the | |
1090 | signed-ness just fine. */ | |
1091 | memcpy (valbuf, buf + 4 - len, len); | |
1092 | } | |
1093 | } | |
1094 | } | |
c906108c | 1095 | |
3923a2b2 MK |
1096 | /* Store the function return value of type TYPE from VALBUF into |
1097 | REGCACHE. */ | |
c906108c | 1098 | |
386c036b MK |
1099 | static void |
1100 | sparc32_store_return_value (struct type *type, struct regcache *regcache, | |
e1613aba | 1101 | const gdb_byte *valbuf) |
386c036b MK |
1102 | { |
1103 | int len = TYPE_LENGTH (type); | |
e1613aba | 1104 | gdb_byte buf[8]; |
c906108c | 1105 | |
386c036b MK |
1106 | gdb_assert (!sparc_structure_or_union_p (type)); |
1107 | gdb_assert (!(sparc_floating_p (type) && len == 16)); | |
c906108c | 1108 | |
386c036b MK |
1109 | if (sparc_floating_p (type)) |
1110 | { | |
1111 | /* Floating return values. */ | |
1112 | memcpy (buf, valbuf, len); | |
1113 | regcache_cooked_write (regcache, SPARC_F0_REGNUM, buf); | |
1114 | if (len > 4) | |
1115 | regcache_cooked_write (regcache, SPARC_F1_REGNUM, buf + 4); | |
1116 | } | |
1117 | else | |
c906108c | 1118 | { |
386c036b MK |
1119 | /* Integral and pointer return values. */ |
1120 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
1121 | ||
1122 | if (len > 4) | |
2757dd86 | 1123 | { |
386c036b MK |
1124 | gdb_assert (len == 8); |
1125 | memcpy (buf, valbuf, 8); | |
1126 | regcache_cooked_write (regcache, SPARC_O1_REGNUM, buf + 4); | |
2757dd86 AC |
1127 | } |
1128 | else | |
1129 | { | |
386c036b MK |
1130 | /* ??? Do we need to do any sign-extension here? */ |
1131 | memcpy (buf + 4 - len, valbuf, len); | |
2757dd86 | 1132 | } |
386c036b | 1133 | regcache_cooked_write (regcache, SPARC_O0_REGNUM, buf); |
c906108c SS |
1134 | } |
1135 | } | |
1136 | ||
b9d4c5ed | 1137 | static enum return_value_convention |
c055b101 CV |
1138 | sparc32_return_value (struct gdbarch *gdbarch, struct type *func_type, |
1139 | struct type *type, struct regcache *regcache, | |
1140 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
b9d4c5ed | 1141 | { |
e17a4113 UW |
1142 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1143 | ||
0a8f48b9 MK |
1144 | /* The psABI says that "...every stack frame reserves the word at |
1145 | %fp+64. If a function returns a structure, union, or | |
1146 | quad-precision value, this word should hold the address of the | |
1147 | object into which the return value should be copied." This | |
1148 | guarantees that we can always find the return value, not just | |
1149 | before the function returns. */ | |
1150 | ||
b9d4c5ed MK |
1151 | if (sparc_structure_or_union_p (type) |
1152 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)) | |
0a8f48b9 MK |
1153 | { |
1154 | if (readbuf) | |
1155 | { | |
1156 | ULONGEST sp; | |
1157 | CORE_ADDR addr; | |
1158 | ||
1159 | regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); | |
e17a4113 | 1160 | addr = read_memory_unsigned_integer (sp + 64, 4, byte_order); |
0a8f48b9 MK |
1161 | read_memory (addr, readbuf, TYPE_LENGTH (type)); |
1162 | } | |
1163 | ||
1164 | return RETURN_VALUE_ABI_PRESERVES_ADDRESS; | |
1165 | } | |
b9d4c5ed MK |
1166 | |
1167 | if (readbuf) | |
1168 | sparc32_extract_return_value (type, regcache, readbuf); | |
1169 | if (writebuf) | |
1170 | sparc32_store_return_value (type, regcache, writebuf); | |
1171 | ||
1172 | return RETURN_VALUE_REGISTER_CONVENTION; | |
1173 | } | |
1174 | ||
386c036b MK |
1175 | static int |
1176 | sparc32_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type) | |
c906108c | 1177 | { |
386c036b MK |
1178 | return (sparc_structure_or_union_p (type) |
1179 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)); | |
1180 | } | |
c906108c | 1181 | |
aff37fc1 | 1182 | static int |
4a4e5149 | 1183 | sparc32_dwarf2_struct_return_p (struct frame_info *this_frame) |
aff37fc1 | 1184 | { |
236369e7 | 1185 | CORE_ADDR pc = get_frame_address_in_block (this_frame); |
aff37fc1 DM |
1186 | struct symbol *sym = find_pc_function (pc); |
1187 | ||
1188 | if (sym) | |
1189 | return sparc32_struct_return_from_sym (sym); | |
1190 | return 0; | |
1191 | } | |
1192 | ||
f5a9b87d DM |
1193 | static void |
1194 | sparc32_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
aff37fc1 | 1195 | struct dwarf2_frame_state_reg *reg, |
4a4e5149 | 1196 | struct frame_info *this_frame) |
f5a9b87d | 1197 | { |
aff37fc1 DM |
1198 | int off; |
1199 | ||
f5a9b87d DM |
1200 | switch (regnum) |
1201 | { | |
1202 | case SPARC_G0_REGNUM: | |
1203 | /* Since %g0 is always zero, there is no point in saving it, and | |
1204 | people will be inclined omit it from the CFI. Make sure we | |
1205 | don't warn about that. */ | |
1206 | reg->how = DWARF2_FRAME_REG_SAME_VALUE; | |
1207 | break; | |
1208 | case SPARC_SP_REGNUM: | |
1209 | reg->how = DWARF2_FRAME_REG_CFA; | |
1210 | break; | |
1211 | case SPARC32_PC_REGNUM: | |
f5a9b87d DM |
1212 | case SPARC32_NPC_REGNUM: |
1213 | reg->how = DWARF2_FRAME_REG_RA_OFFSET; | |
aff37fc1 | 1214 | off = 8; |
4a4e5149 | 1215 | if (sparc32_dwarf2_struct_return_p (this_frame)) |
aff37fc1 DM |
1216 | off += 4; |
1217 | if (regnum == SPARC32_NPC_REGNUM) | |
1218 | off += 4; | |
1219 | reg->loc.offset = off; | |
f5a9b87d DM |
1220 | break; |
1221 | } | |
1222 | } | |
1223 | ||
386c036b MK |
1224 | \f |
1225 | /* The SPARC Architecture doesn't have hardware single-step support, | |
1226 | and most operating systems don't implement it either, so we provide | |
1227 | software single-step mechanism. */ | |
c906108c | 1228 | |
386c036b | 1229 | static CORE_ADDR |
0b1b3e42 | 1230 | sparc_analyze_control_transfer (struct frame_info *frame, |
c893be75 | 1231 | CORE_ADDR pc, CORE_ADDR *npc) |
386c036b MK |
1232 | { |
1233 | unsigned long insn = sparc_fetch_instruction (pc); | |
1234 | int conditional_p = X_COND (insn) & 0x7; | |
1235 | int branch_p = 0; | |
1236 | long offset = 0; /* Must be signed for sign-extend. */ | |
c906108c | 1237 | |
386c036b | 1238 | if (X_OP (insn) == 0 && X_OP2 (insn) == 3 && (insn & 0x1000000) == 0) |
c906108c | 1239 | { |
386c036b MK |
1240 | /* Branch on Integer Register with Prediction (BPr). */ |
1241 | branch_p = 1; | |
1242 | conditional_p = 1; | |
c906108c | 1243 | } |
386c036b | 1244 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 6) |
c906108c | 1245 | { |
386c036b MK |
1246 | /* Branch on Floating-Point Condition Codes (FBfcc). */ |
1247 | branch_p = 1; | |
1248 | offset = 4 * X_DISP22 (insn); | |
c906108c | 1249 | } |
386c036b MK |
1250 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 5) |
1251 | { | |
1252 | /* Branch on Floating-Point Condition Codes with Prediction | |
1253 | (FBPfcc). */ | |
1254 | branch_p = 1; | |
1255 | offset = 4 * X_DISP19 (insn); | |
1256 | } | |
1257 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 2) | |
1258 | { | |
1259 | /* Branch on Integer Condition Codes (Bicc). */ | |
1260 | branch_p = 1; | |
1261 | offset = 4 * X_DISP22 (insn); | |
1262 | } | |
1263 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 1) | |
c906108c | 1264 | { |
386c036b MK |
1265 | /* Branch on Integer Condition Codes with Prediction (BPcc). */ |
1266 | branch_p = 1; | |
1267 | offset = 4 * X_DISP19 (insn); | |
c906108c | 1268 | } |
c893be75 MK |
1269 | else if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3a) |
1270 | { | |
1271 | /* Trap instruction (TRAP). */ | |
0b1b3e42 | 1272 | return gdbarch_tdep (get_frame_arch (frame))->step_trap (frame, insn); |
c893be75 | 1273 | } |
386c036b MK |
1274 | |
1275 | /* FIXME: Handle DONE and RETRY instructions. */ | |
1276 | ||
386c036b | 1277 | if (branch_p) |
c906108c | 1278 | { |
386c036b | 1279 | if (conditional_p) |
c906108c | 1280 | { |
386c036b MK |
1281 | /* For conditional branches, return nPC + 4 iff the annul |
1282 | bit is 1. */ | |
1283 | return (X_A (insn) ? *npc + 4 : 0); | |
c906108c SS |
1284 | } |
1285 | else | |
1286 | { | |
386c036b MK |
1287 | /* For unconditional branches, return the target if its |
1288 | specified condition is "always" and return nPC + 4 if the | |
1289 | condition is "never". If the annul bit is 1, set *NPC to | |
1290 | zero. */ | |
1291 | if (X_COND (insn) == 0x0) | |
1292 | pc = *npc, offset = 4; | |
1293 | if (X_A (insn)) | |
1294 | *npc = 0; | |
1295 | ||
1296 | gdb_assert (offset != 0); | |
1297 | return pc + offset; | |
c906108c SS |
1298 | } |
1299 | } | |
386c036b MK |
1300 | |
1301 | return 0; | |
c906108c SS |
1302 | } |
1303 | ||
c893be75 | 1304 | static CORE_ADDR |
0b1b3e42 | 1305 | sparc_step_trap (struct frame_info *frame, unsigned long insn) |
c893be75 MK |
1306 | { |
1307 | return 0; | |
1308 | } | |
1309 | ||
e6590a1b | 1310 | int |
0b1b3e42 | 1311 | sparc_software_single_step (struct frame_info *frame) |
386c036b | 1312 | { |
0b1b3e42 | 1313 | struct gdbarch *arch = get_frame_arch (frame); |
c893be75 | 1314 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); |
6c95b8df | 1315 | struct address_space *aspace = get_frame_address_space (frame); |
8181d85f | 1316 | CORE_ADDR npc, nnpc; |
c906108c | 1317 | |
e0cd558a | 1318 | CORE_ADDR pc, orig_npc; |
c906108c | 1319 | |
0b1b3e42 UW |
1320 | pc = get_frame_register_unsigned (frame, tdep->pc_regnum); |
1321 | orig_npc = npc = get_frame_register_unsigned (frame, tdep->npc_regnum); | |
c906108c | 1322 | |
e0cd558a | 1323 | /* Analyze the instruction at PC. */ |
0b1b3e42 | 1324 | nnpc = sparc_analyze_control_transfer (frame, pc, &npc); |
e0cd558a | 1325 | if (npc != 0) |
6c95b8df | 1326 | insert_single_step_breakpoint (arch, aspace, npc); |
8181d85f | 1327 | |
e0cd558a | 1328 | if (nnpc != 0) |
6c95b8df | 1329 | insert_single_step_breakpoint (arch, aspace, nnpc); |
c906108c | 1330 | |
e0cd558a UW |
1331 | /* Assert that we have set at least one breakpoint, and that |
1332 | they're not set at the same spot - unless we're going | |
1333 | from here straight to NULL, i.e. a call or jump to 0. */ | |
1334 | gdb_assert (npc != 0 || nnpc != 0 || orig_npc == 0); | |
1335 | gdb_assert (nnpc != npc || orig_npc == 0); | |
e6590a1b UW |
1336 | |
1337 | return 1; | |
386c036b MK |
1338 | } |
1339 | ||
1340 | static void | |
61a1198a | 1341 | sparc_write_pc (struct regcache *regcache, CORE_ADDR pc) |
386c036b | 1342 | { |
61a1198a | 1343 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); |
386c036b | 1344 | |
61a1198a UW |
1345 | regcache_cooked_write_unsigned (regcache, tdep->pc_regnum, pc); |
1346 | regcache_cooked_write_unsigned (regcache, tdep->npc_regnum, pc + 4); | |
386c036b MK |
1347 | } |
1348 | \f | |
5af923b0 | 1349 | |
a54124c5 MK |
1350 | /* Return the appropriate register set for the core section identified |
1351 | by SECT_NAME and SECT_SIZE. */ | |
1352 | ||
63807e1d | 1353 | static const struct regset * |
a54124c5 MK |
1354 | sparc_regset_from_core_section (struct gdbarch *gdbarch, |
1355 | const char *sect_name, size_t sect_size) | |
1356 | { | |
1357 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1358 | ||
c558d81a | 1359 | if (strcmp (sect_name, ".reg") == 0 && sect_size >= tdep->sizeof_gregset) |
a54124c5 MK |
1360 | return tdep->gregset; |
1361 | ||
c558d81a | 1362 | if (strcmp (sect_name, ".reg2") == 0 && sect_size >= tdep->sizeof_fpregset) |
a54124c5 MK |
1363 | return tdep->fpregset; |
1364 | ||
1365 | return NULL; | |
1366 | } | |
1367 | \f | |
1368 | ||
386c036b MK |
1369 | static struct gdbarch * |
1370 | sparc32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
1371 | { | |
1372 | struct gdbarch_tdep *tdep; | |
1373 | struct gdbarch *gdbarch; | |
c906108c | 1374 | |
386c036b MK |
1375 | /* If there is already a candidate, use it. */ |
1376 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
1377 | if (arches != NULL) | |
1378 | return arches->gdbarch; | |
c906108c | 1379 | |
386c036b | 1380 | /* Allocate space for the new architecture. */ |
1390fcc2 | 1381 | tdep = XZALLOC (struct gdbarch_tdep); |
386c036b | 1382 | gdbarch = gdbarch_alloc (&info, tdep); |
5af923b0 | 1383 | |
386c036b MK |
1384 | tdep->pc_regnum = SPARC32_PC_REGNUM; |
1385 | tdep->npc_regnum = SPARC32_NPC_REGNUM; | |
c893be75 | 1386 | tdep->step_trap = sparc_step_trap; |
386c036b MK |
1387 | |
1388 | set_gdbarch_long_double_bit (gdbarch, 128); | |
8da61cc4 | 1389 | set_gdbarch_long_double_format (gdbarch, floatformats_sparc_quad); |
386c036b MK |
1390 | |
1391 | set_gdbarch_num_regs (gdbarch, SPARC32_NUM_REGS); | |
1392 | set_gdbarch_register_name (gdbarch, sparc32_register_name); | |
1393 | set_gdbarch_register_type (gdbarch, sparc32_register_type); | |
1394 | set_gdbarch_num_pseudo_regs (gdbarch, SPARC32_NUM_PSEUDO_REGS); | |
1395 | set_gdbarch_pseudo_register_read (gdbarch, sparc32_pseudo_register_read); | |
1396 | set_gdbarch_pseudo_register_write (gdbarch, sparc32_pseudo_register_write); | |
1397 | ||
1398 | /* Register numbers of various important registers. */ | |
1399 | set_gdbarch_sp_regnum (gdbarch, SPARC_SP_REGNUM); /* %sp */ | |
1400 | set_gdbarch_pc_regnum (gdbarch, SPARC32_PC_REGNUM); /* %pc */ | |
1401 | set_gdbarch_fp0_regnum (gdbarch, SPARC_F0_REGNUM); /* %f0 */ | |
1402 | ||
1403 | /* Call dummy code. */ | |
1404 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); | |
1405 | set_gdbarch_push_dummy_code (gdbarch, sparc32_push_dummy_code); | |
1406 | set_gdbarch_push_dummy_call (gdbarch, sparc32_push_dummy_call); | |
1407 | ||
b9d4c5ed | 1408 | set_gdbarch_return_value (gdbarch, sparc32_return_value); |
386c036b MK |
1409 | set_gdbarch_stabs_argument_has_addr |
1410 | (gdbarch, sparc32_stabs_argument_has_addr); | |
1411 | ||
1412 | set_gdbarch_skip_prologue (gdbarch, sparc32_skip_prologue); | |
1413 | ||
1414 | /* Stack grows downward. */ | |
1415 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
c906108c | 1416 | |
386c036b | 1417 | set_gdbarch_breakpoint_from_pc (gdbarch, sparc_breakpoint_from_pc); |
c906108c | 1418 | |
386c036b | 1419 | set_gdbarch_frame_args_skip (gdbarch, 8); |
5af923b0 | 1420 | |
386c036b | 1421 | set_gdbarch_print_insn (gdbarch, print_insn_sparc); |
c906108c | 1422 | |
386c036b MK |
1423 | set_gdbarch_software_single_step (gdbarch, sparc_software_single_step); |
1424 | set_gdbarch_write_pc (gdbarch, sparc_write_pc); | |
c906108c | 1425 | |
236369e7 | 1426 | set_gdbarch_dummy_id (gdbarch, sparc_dummy_id); |
c906108c | 1427 | |
386c036b | 1428 | set_gdbarch_unwind_pc (gdbarch, sparc_unwind_pc); |
c906108c | 1429 | |
386c036b MK |
1430 | frame_base_set_default (gdbarch, &sparc32_frame_base); |
1431 | ||
f5a9b87d DM |
1432 | /* Hook in the DWARF CFI frame unwinder. */ |
1433 | dwarf2_frame_set_init_reg (gdbarch, sparc32_dwarf2_frame_init_reg); | |
1434 | /* FIXME: kettenis/20050423: Don't enable the unwinder until the | |
1435 | StackGhost issues have been resolved. */ | |
1436 | ||
b2a0b9b2 DM |
1437 | /* Hook in ABI-specific overrides, if they have been registered. */ |
1438 | gdbarch_init_osabi (info, gdbarch); | |
1439 | ||
236369e7 | 1440 | frame_unwind_append_unwinder (gdbarch, &sparc32_frame_unwind); |
c906108c | 1441 | |
a54124c5 | 1442 | /* If we have register sets, enable the generic core file support. */ |
4c72d57a | 1443 | if (tdep->gregset) |
a54124c5 MK |
1444 | set_gdbarch_regset_from_core_section (gdbarch, |
1445 | sparc_regset_from_core_section); | |
1446 | ||
386c036b MK |
1447 | return gdbarch; |
1448 | } | |
1449 | \f | |
1450 | /* Helper functions for dealing with register windows. */ | |
1451 | ||
1452 | void | |
1453 | sparc_supply_rwindow (struct regcache *regcache, CORE_ADDR sp, int regnum) | |
c906108c | 1454 | { |
e17a4113 UW |
1455 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
1456 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
386c036b | 1457 | int offset = 0; |
e1613aba | 1458 | gdb_byte buf[8]; |
386c036b MK |
1459 | int i; |
1460 | ||
1461 | if (sp & 1) | |
1462 | { | |
1463 | /* Registers are 64-bit. */ | |
1464 | sp += BIAS; | |
c906108c | 1465 | |
386c036b MK |
1466 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1467 | { | |
1468 | if (regnum == i || regnum == -1) | |
1469 | { | |
1470 | target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8); | |
f700a364 MK |
1471 | |
1472 | /* Handle StackGhost. */ | |
1473 | if (i == SPARC_I7_REGNUM) | |
1474 | { | |
e17a4113 UW |
1475 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
1476 | ULONGEST i7; | |
f700a364 | 1477 | |
e17a4113 UW |
1478 | i7 = extract_unsigned_integer (buf + offset, 8, byte_order); |
1479 | store_unsigned_integer (buf + offset, 8, byte_order, | |
1480 | i7 ^ wcookie); | |
f700a364 MK |
1481 | } |
1482 | ||
386c036b MK |
1483 | regcache_raw_supply (regcache, i, buf); |
1484 | } | |
1485 | } | |
1486 | } | |
1487 | else | |
c906108c | 1488 | { |
386c036b MK |
1489 | /* Registers are 32-bit. Toss any sign-extension of the stack |
1490 | pointer. */ | |
1491 | sp &= 0xffffffffUL; | |
c906108c | 1492 | |
386c036b MK |
1493 | /* Clear out the top half of the temporary buffer, and put the |
1494 | register value in the bottom half if we're in 64-bit mode. */ | |
e6d4f032 | 1495 | if (gdbarch_ptr_bit (get_regcache_arch (regcache)) == 64) |
c906108c | 1496 | { |
386c036b MK |
1497 | memset (buf, 0, 4); |
1498 | offset = 4; | |
1499 | } | |
c906108c | 1500 | |
386c036b MK |
1501 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1502 | { | |
1503 | if (regnum == i || regnum == -1) | |
1504 | { | |
1505 | target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 4), | |
1506 | buf + offset, 4); | |
42cdca6c MK |
1507 | |
1508 | /* Handle StackGhost. */ | |
1509 | if (i == SPARC_I7_REGNUM) | |
1510 | { | |
e17a4113 UW |
1511 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
1512 | ULONGEST i7; | |
42cdca6c | 1513 | |
e17a4113 UW |
1514 | i7 = extract_unsigned_integer (buf + offset, 4, byte_order); |
1515 | store_unsigned_integer (buf + offset, 4, byte_order, | |
1516 | i7 ^ wcookie); | |
42cdca6c MK |
1517 | } |
1518 | ||
386c036b MK |
1519 | regcache_raw_supply (regcache, i, buf); |
1520 | } | |
c906108c SS |
1521 | } |
1522 | } | |
c906108c | 1523 | } |
c906108c SS |
1524 | |
1525 | void | |
386c036b MK |
1526 | sparc_collect_rwindow (const struct regcache *regcache, |
1527 | CORE_ADDR sp, int regnum) | |
c906108c | 1528 | { |
e17a4113 UW |
1529 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
1530 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
386c036b | 1531 | int offset = 0; |
e1613aba | 1532 | gdb_byte buf[8]; |
386c036b | 1533 | int i; |
5af923b0 | 1534 | |
386c036b | 1535 | if (sp & 1) |
5af923b0 | 1536 | { |
386c036b MK |
1537 | /* Registers are 64-bit. */ |
1538 | sp += BIAS; | |
c906108c | 1539 | |
386c036b MK |
1540 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1541 | { | |
1542 | if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i) | |
1543 | { | |
1544 | regcache_raw_collect (regcache, i, buf); | |
f700a364 MK |
1545 | |
1546 | /* Handle StackGhost. */ | |
1547 | if (i == SPARC_I7_REGNUM) | |
1548 | { | |
e17a4113 UW |
1549 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
1550 | ULONGEST i7; | |
f700a364 | 1551 | |
e17a4113 UW |
1552 | i7 = extract_unsigned_integer (buf + offset, 8, byte_order); |
1553 | store_unsigned_integer (buf, 8, byte_order, i7 ^ wcookie); | |
f700a364 MK |
1554 | } |
1555 | ||
386c036b MK |
1556 | target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8); |
1557 | } | |
1558 | } | |
5af923b0 MS |
1559 | } |
1560 | else | |
1561 | { | |
386c036b MK |
1562 | /* Registers are 32-bit. Toss any sign-extension of the stack |
1563 | pointer. */ | |
1564 | sp &= 0xffffffffUL; | |
1565 | ||
1566 | /* Only use the bottom half if we're in 64-bit mode. */ | |
e6d4f032 | 1567 | if (gdbarch_ptr_bit (get_regcache_arch (regcache)) == 64) |
386c036b MK |
1568 | offset = 4; |
1569 | ||
1570 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
1571 | { | |
1572 | if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i) | |
1573 | { | |
1574 | regcache_raw_collect (regcache, i, buf); | |
42cdca6c MK |
1575 | |
1576 | /* Handle StackGhost. */ | |
1577 | if (i == SPARC_I7_REGNUM) | |
1578 | { | |
e17a4113 UW |
1579 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
1580 | ULONGEST i7; | |
42cdca6c | 1581 | |
e17a4113 UW |
1582 | i7 = extract_unsigned_integer (buf + offset, 4, byte_order); |
1583 | store_unsigned_integer (buf + offset, 4, byte_order, | |
1584 | i7 ^ wcookie); | |
42cdca6c MK |
1585 | } |
1586 | ||
386c036b MK |
1587 | target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 4), |
1588 | buf + offset, 4); | |
1589 | } | |
1590 | } | |
5af923b0 | 1591 | } |
c906108c SS |
1592 | } |
1593 | ||
386c036b MK |
1594 | /* Helper functions for dealing with register sets. */ |
1595 | ||
c906108c | 1596 | void |
386c036b MK |
1597 | sparc32_supply_gregset (const struct sparc_gregset *gregset, |
1598 | struct regcache *regcache, | |
1599 | int regnum, const void *gregs) | |
c906108c | 1600 | { |
e1613aba | 1601 | const gdb_byte *regs = gregs; |
386c036b | 1602 | int i; |
5af923b0 | 1603 | |
386c036b MK |
1604 | if (regnum == SPARC32_PSR_REGNUM || regnum == -1) |
1605 | regcache_raw_supply (regcache, SPARC32_PSR_REGNUM, | |
1606 | regs + gregset->r_psr_offset); | |
c906108c | 1607 | |
386c036b MK |
1608 | if (regnum == SPARC32_PC_REGNUM || regnum == -1) |
1609 | regcache_raw_supply (regcache, SPARC32_PC_REGNUM, | |
1610 | regs + gregset->r_pc_offset); | |
5af923b0 | 1611 | |
386c036b MK |
1612 | if (regnum == SPARC32_NPC_REGNUM || regnum == -1) |
1613 | regcache_raw_supply (regcache, SPARC32_NPC_REGNUM, | |
1614 | regs + gregset->r_npc_offset); | |
5af923b0 | 1615 | |
386c036b MK |
1616 | if (regnum == SPARC32_Y_REGNUM || regnum == -1) |
1617 | regcache_raw_supply (regcache, SPARC32_Y_REGNUM, | |
1618 | regs + gregset->r_y_offset); | |
5af923b0 | 1619 | |
386c036b MK |
1620 | if (regnum == SPARC_G0_REGNUM || regnum == -1) |
1621 | regcache_raw_supply (regcache, SPARC_G0_REGNUM, NULL); | |
5af923b0 | 1622 | |
386c036b | 1623 | if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1) |
c906108c | 1624 | { |
386c036b MK |
1625 | int offset = gregset->r_g1_offset; |
1626 | ||
1627 | for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++) | |
1628 | { | |
1629 | if (regnum == i || regnum == -1) | |
1630 | regcache_raw_supply (regcache, i, regs + offset); | |
1631 | offset += 4; | |
1632 | } | |
c906108c | 1633 | } |
386c036b MK |
1634 | |
1635 | if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1) | |
c906108c | 1636 | { |
386c036b MK |
1637 | /* Not all of the register set variants include Locals and |
1638 | Inputs. For those that don't, we read them off the stack. */ | |
1639 | if (gregset->r_l0_offset == -1) | |
1640 | { | |
1641 | ULONGEST sp; | |
1642 | ||
1643 | regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); | |
1644 | sparc_supply_rwindow (regcache, sp, regnum); | |
1645 | } | |
1646 | else | |
1647 | { | |
1648 | int offset = gregset->r_l0_offset; | |
1649 | ||
1650 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
1651 | { | |
1652 | if (regnum == i || regnum == -1) | |
1653 | regcache_raw_supply (regcache, i, regs + offset); | |
1654 | offset += 4; | |
1655 | } | |
1656 | } | |
c906108c SS |
1657 | } |
1658 | } | |
1659 | ||
c5aa993b | 1660 | void |
386c036b MK |
1661 | sparc32_collect_gregset (const struct sparc_gregset *gregset, |
1662 | const struct regcache *regcache, | |
1663 | int regnum, void *gregs) | |
c906108c | 1664 | { |
e1613aba | 1665 | gdb_byte *regs = gregs; |
386c036b | 1666 | int i; |
c5aa993b | 1667 | |
386c036b MK |
1668 | if (regnum == SPARC32_PSR_REGNUM || regnum == -1) |
1669 | regcache_raw_collect (regcache, SPARC32_PSR_REGNUM, | |
1670 | regs + gregset->r_psr_offset); | |
60054393 | 1671 | |
386c036b MK |
1672 | if (regnum == SPARC32_PC_REGNUM || regnum == -1) |
1673 | regcache_raw_collect (regcache, SPARC32_PC_REGNUM, | |
1674 | regs + gregset->r_pc_offset); | |
1675 | ||
1676 | if (regnum == SPARC32_NPC_REGNUM || regnum == -1) | |
1677 | regcache_raw_collect (regcache, SPARC32_NPC_REGNUM, | |
1678 | regs + gregset->r_npc_offset); | |
5af923b0 | 1679 | |
386c036b MK |
1680 | if (regnum == SPARC32_Y_REGNUM || regnum == -1) |
1681 | regcache_raw_collect (regcache, SPARC32_Y_REGNUM, | |
1682 | regs + gregset->r_y_offset); | |
1683 | ||
1684 | if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1) | |
5af923b0 | 1685 | { |
386c036b MK |
1686 | int offset = gregset->r_g1_offset; |
1687 | ||
1688 | /* %g0 is always zero. */ | |
1689 | for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++) | |
1690 | { | |
1691 | if (regnum == i || regnum == -1) | |
1692 | regcache_raw_collect (regcache, i, regs + offset); | |
1693 | offset += 4; | |
1694 | } | |
5af923b0 | 1695 | } |
386c036b MK |
1696 | |
1697 | if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1) | |
5af923b0 | 1698 | { |
386c036b MK |
1699 | /* Not all of the register set variants include Locals and |
1700 | Inputs. For those that don't, we read them off the stack. */ | |
1701 | if (gregset->r_l0_offset != -1) | |
1702 | { | |
1703 | int offset = gregset->r_l0_offset; | |
1704 | ||
1705 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
1706 | { | |
1707 | if (regnum == i || regnum == -1) | |
1708 | regcache_raw_collect (regcache, i, regs + offset); | |
1709 | offset += 4; | |
1710 | } | |
1711 | } | |
5af923b0 | 1712 | } |
c906108c SS |
1713 | } |
1714 | ||
c906108c | 1715 | void |
386c036b MK |
1716 | sparc32_supply_fpregset (struct regcache *regcache, |
1717 | int regnum, const void *fpregs) | |
c906108c | 1718 | { |
e1613aba | 1719 | const gdb_byte *regs = fpregs; |
386c036b | 1720 | int i; |
60054393 | 1721 | |
386c036b | 1722 | for (i = 0; i < 32; i++) |
c906108c | 1723 | { |
386c036b MK |
1724 | if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1) |
1725 | regcache_raw_supply (regcache, SPARC_F0_REGNUM + i, regs + (i * 4)); | |
c906108c | 1726 | } |
5af923b0 | 1727 | |
386c036b MK |
1728 | if (regnum == SPARC32_FSR_REGNUM || regnum == -1) |
1729 | regcache_raw_supply (regcache, SPARC32_FSR_REGNUM, regs + (32 * 4) + 4); | |
c906108c SS |
1730 | } |
1731 | ||
386c036b MK |
1732 | void |
1733 | sparc32_collect_fpregset (const struct regcache *regcache, | |
1734 | int regnum, void *fpregs) | |
c906108c | 1735 | { |
e1613aba | 1736 | gdb_byte *regs = fpregs; |
386c036b | 1737 | int i; |
c906108c | 1738 | |
386c036b MK |
1739 | for (i = 0; i < 32; i++) |
1740 | { | |
1741 | if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1) | |
1742 | regcache_raw_collect (regcache, SPARC_F0_REGNUM + i, regs + (i * 4)); | |
1743 | } | |
c906108c | 1744 | |
386c036b MK |
1745 | if (regnum == SPARC32_FSR_REGNUM || regnum == -1) |
1746 | regcache_raw_collect (regcache, SPARC32_FSR_REGNUM, regs + (32 * 4) + 4); | |
c906108c | 1747 | } |
c906108c | 1748 | \f |
c906108c | 1749 | |
386c036b | 1750 | /* SunOS 4. */ |
c906108c | 1751 | |
386c036b MK |
1752 | /* From <machine/reg.h>. */ |
1753 | const struct sparc_gregset sparc32_sunos4_gregset = | |
c906108c | 1754 | { |
386c036b MK |
1755 | 0 * 4, /* %psr */ |
1756 | 1 * 4, /* %pc */ | |
1757 | 2 * 4, /* %npc */ | |
1758 | 3 * 4, /* %y */ | |
1759 | -1, /* %wim */ | |
1760 | -1, /* %tbr */ | |
1761 | 4 * 4, /* %g1 */ | |
1762 | -1 /* %l0 */ | |
1763 | }; | |
1764 | \f | |
c906108c | 1765 | |
386c036b MK |
1766 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
1767 | void _initialize_sparc_tdep (void); | |
c906108c SS |
1768 | |
1769 | void | |
386c036b | 1770 | _initialize_sparc_tdep (void) |
c906108c | 1771 | { |
386c036b | 1772 | register_gdbarch_init (bfd_arch_sparc, sparc32_gdbarch_init); |
ef3cf062 | 1773 | } |