Commit | Line | Data |
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386c036b | 1 | /* Target-dependent code for SPARC. |
cda5a58a | 2 | |
0b302171 | 3 | Copyright (C) 2003-2012 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 10 | (at your option) any later version. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b | 17 | You should have received a copy of the GNU General Public License |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c | 19 | |
c906108c | 20 | #include "defs.h" |
5af923b0 | 21 | #include "arch-utils.h" |
386c036b | 22 | #include "dis-asm.h" |
f5a9b87d | 23 | #include "dwarf2-frame.h" |
386c036b | 24 | #include "floatformat.h" |
c906108c | 25 | #include "frame.h" |
386c036b MK |
26 | #include "frame-base.h" |
27 | #include "frame-unwind.h" | |
28 | #include "gdbcore.h" | |
29 | #include "gdbtypes.h" | |
c906108c | 30 | #include "inferior.h" |
386c036b MK |
31 | #include "symtab.h" |
32 | #include "objfiles.h" | |
33 | #include "osabi.h" | |
34 | #include "regcache.h" | |
c906108c SS |
35 | #include "target.h" |
36 | #include "value.h" | |
c906108c | 37 | |
43bd9a9e | 38 | #include "gdb_assert.h" |
386c036b | 39 | #include "gdb_string.h" |
c906108c | 40 | |
386c036b | 41 | #include "sparc-tdep.h" |
c906108c | 42 | |
a54124c5 MK |
43 | struct regset; |
44 | ||
9eb42ed1 MK |
45 | /* This file implements the SPARC 32-bit ABI as defined by the section |
46 | "Low-Level System Information" of the SPARC Compliance Definition | |
47 | (SCD) 2.4.1, which is the 32-bit System V psABI for SPARC. The SCD | |
f2e7c15d | 48 | lists changes with respect to the original 32-bit psABI as defined |
9eb42ed1 | 49 | in the "System V ABI, SPARC Processor Supplement". |
386c036b MK |
50 | |
51 | Note that if we talk about SunOS, we mean SunOS 4.x, which was | |
52 | BSD-based, which is sometimes (retroactively?) referred to as | |
53 | Solaris 1.x. If we talk about Solaris we mean Solaris 2.x and | |
54 | above (Solaris 7, 8 and 9 are nothing but Solaris 2.7, 2.8 and 2.9 | |
55 | suffering from severe version number inflation). Solaris 2.x is | |
56 | also known as SunOS 5.x, since that's what uname(1) says. Solaris | |
57 | 2.x is SVR4-based. */ | |
58 | ||
59 | /* Please use the sparc32_-prefix for 32-bit specific code, the | |
60 | sparc64_-prefix for 64-bit specific code and the sparc_-prefix for | |
61 | code that can handle both. The 64-bit specific code lives in | |
62 | sparc64-tdep.c; don't add any here. */ | |
63 | ||
64 | /* The SPARC Floating-Point Quad-Precision format is similar to | |
7a58cce8 | 65 | big-endian IA-64 Quad-Precision format. */ |
8da61cc4 | 66 | #define floatformats_sparc_quad floatformats_ia64_quad |
386c036b MK |
67 | |
68 | /* The stack pointer is offset from the stack frame by a BIAS of 2047 | |
69 | (0x7ff) for 64-bit code. BIAS is likely to be defined on SPARC | |
70 | hosts, so undefine it first. */ | |
71 | #undef BIAS | |
72 | #define BIAS 2047 | |
73 | ||
74 | /* Macros to extract fields from SPARC instructions. */ | |
c906108c SS |
75 | #define X_OP(i) (((i) >> 30) & 0x3) |
76 | #define X_RD(i) (((i) >> 25) & 0x1f) | |
77 | #define X_A(i) (((i) >> 29) & 1) | |
78 | #define X_COND(i) (((i) >> 25) & 0xf) | |
79 | #define X_OP2(i) (((i) >> 22) & 0x7) | |
80 | #define X_IMM22(i) ((i) & 0x3fffff) | |
81 | #define X_OP3(i) (((i) >> 19) & 0x3f) | |
075ccec8 | 82 | #define X_RS1(i) (((i) >> 14) & 0x1f) |
b0b92586 | 83 | #define X_RS2(i) ((i) & 0x1f) |
c906108c | 84 | #define X_I(i) (((i) >> 13) & 1) |
c906108c | 85 | /* Sign extension macros. */ |
c906108c | 86 | #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000) |
c906108c | 87 | #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000) |
075ccec8 | 88 | #define X_SIMM13(i) ((((i) & 0x1fff) ^ 0x1000) - 0x1000) |
c906108c | 89 | |
386c036b MK |
90 | /* Fetch the instruction at PC. Instructions are always big-endian |
91 | even if the processor operates in little-endian mode. */ | |
92 | ||
93 | unsigned long | |
94 | sparc_fetch_instruction (CORE_ADDR pc) | |
c906108c | 95 | { |
e1613aba | 96 | gdb_byte buf[4]; |
386c036b MK |
97 | unsigned long insn; |
98 | int i; | |
99 | ||
690668cc | 100 | /* If we can't read the instruction at PC, return zero. */ |
8defab1a | 101 | if (target_read_memory (pc, buf, sizeof (buf))) |
690668cc | 102 | return 0; |
c906108c | 103 | |
386c036b MK |
104 | insn = 0; |
105 | for (i = 0; i < sizeof (buf); i++) | |
106 | insn = (insn << 8) | buf[i]; | |
107 | return insn; | |
108 | } | |
42cdca6c MK |
109 | \f |
110 | ||
5465445a JB |
111 | /* Return non-zero if the instruction corresponding to PC is an "unimp" |
112 | instruction. */ | |
113 | ||
114 | static int | |
115 | sparc_is_unimp_insn (CORE_ADDR pc) | |
116 | { | |
117 | const unsigned long insn = sparc_fetch_instruction (pc); | |
118 | ||
119 | return ((insn & 0xc1c00000) == 0); | |
120 | } | |
121 | ||
42cdca6c MK |
122 | /* OpenBSD/sparc includes StackGhost, which according to the author's |
123 | website http://stackghost.cerias.purdue.edu "... transparently and | |
124 | automatically protects applications' stack frames; more | |
125 | specifically, it guards the return pointers. The protection | |
126 | mechanisms require no application source or binary modification and | |
127 | imposes only a negligible performance penalty." | |
128 | ||
129 | The same website provides the following description of how | |
130 | StackGhost works: | |
131 | ||
132 | "StackGhost interfaces with the kernel trap handler that would | |
133 | normally write out registers to the stack and the handler that | |
134 | would read them back in. By XORing a cookie into the | |
135 | return-address saved in the user stack when it is actually written | |
136 | to the stack, and then XOR it out when the return-address is pulled | |
137 | from the stack, StackGhost can cause attacker corrupted return | |
138 | pointers to behave in a manner the attacker cannot predict. | |
139 | StackGhost can also use several unused bits in the return pointer | |
140 | to detect a smashed return pointer and abort the process." | |
141 | ||
142 | For GDB this means that whenever we're reading %i7 from a stack | |
143 | frame's window save area, we'll have to XOR the cookie. | |
144 | ||
145 | More information on StackGuard can be found on in: | |
146 | ||
c378eb4e | 147 | Mike Frantzen and Mike Shuey. "StackGhost: Hardware Facilitated |
42cdca6c MK |
148 | Stack Protection." 2001. Published in USENIX Security Symposium |
149 | '01. */ | |
150 | ||
151 | /* Fetch StackGhost Per-Process XOR cookie. */ | |
152 | ||
153 | ULONGEST | |
e17a4113 | 154 | sparc_fetch_wcookie (struct gdbarch *gdbarch) |
42cdca6c | 155 | { |
e17a4113 | 156 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
baf92889 | 157 | struct target_ops *ops = ¤t_target; |
e1613aba | 158 | gdb_byte buf[8]; |
baf92889 MK |
159 | int len; |
160 | ||
13547ab6 | 161 | len = target_read (ops, TARGET_OBJECT_WCOOKIE, NULL, buf, 0, 8); |
baf92889 MK |
162 | if (len == -1) |
163 | return 0; | |
42cdca6c | 164 | |
baf92889 MK |
165 | /* We should have either an 32-bit or an 64-bit cookie. */ |
166 | gdb_assert (len == 4 || len == 8); | |
167 | ||
e17a4113 | 168 | return extract_unsigned_integer (buf, len, byte_order); |
baf92889 | 169 | } |
386c036b | 170 | \f |
baf92889 | 171 | |
386c036b MK |
172 | /* The functions on this page are intended to be used to classify |
173 | function arguments. */ | |
c906108c | 174 | |
386c036b | 175 | /* Check whether TYPE is "Integral or Pointer". */ |
c906108c | 176 | |
386c036b MK |
177 | static int |
178 | sparc_integral_or_pointer_p (const struct type *type) | |
c906108c | 179 | { |
80ad1639 MK |
180 | int len = TYPE_LENGTH (type); |
181 | ||
386c036b | 182 | switch (TYPE_CODE (type)) |
c906108c | 183 | { |
386c036b MK |
184 | case TYPE_CODE_INT: |
185 | case TYPE_CODE_BOOL: | |
186 | case TYPE_CODE_CHAR: | |
187 | case TYPE_CODE_ENUM: | |
188 | case TYPE_CODE_RANGE: | |
80ad1639 MK |
189 | /* We have byte, half-word, word and extended-word/doubleword |
190 | integral types. The doubleword is an extension to the | |
191 | original 32-bit ABI by the SCD 2.4.x. */ | |
192 | return (len == 1 || len == 2 || len == 4 || len == 8); | |
386c036b MK |
193 | case TYPE_CODE_PTR: |
194 | case TYPE_CODE_REF: | |
80ad1639 MK |
195 | /* Allow either 32-bit or 64-bit pointers. */ |
196 | return (len == 4 || len == 8); | |
386c036b MK |
197 | default: |
198 | break; | |
199 | } | |
c906108c | 200 | |
386c036b MK |
201 | return 0; |
202 | } | |
c906108c | 203 | |
386c036b | 204 | /* Check whether TYPE is "Floating". */ |
c906108c | 205 | |
386c036b MK |
206 | static int |
207 | sparc_floating_p (const struct type *type) | |
208 | { | |
209 | switch (TYPE_CODE (type)) | |
c906108c | 210 | { |
386c036b MK |
211 | case TYPE_CODE_FLT: |
212 | { | |
213 | int len = TYPE_LENGTH (type); | |
214 | return (len == 4 || len == 8 || len == 16); | |
215 | } | |
216 | default: | |
217 | break; | |
218 | } | |
219 | ||
220 | return 0; | |
221 | } | |
c906108c | 222 | |
fe10a582 DM |
223 | /* Check whether TYPE is "Complex Floating". */ |
224 | ||
225 | static int | |
226 | sparc_complex_floating_p (const struct type *type) | |
227 | { | |
228 | switch (TYPE_CODE (type)) | |
229 | { | |
230 | case TYPE_CODE_COMPLEX: | |
231 | { | |
232 | int len = TYPE_LENGTH (type); | |
233 | return (len == 8 || len == 16 || len == 32); | |
234 | } | |
235 | default: | |
236 | break; | |
237 | } | |
238 | ||
239 | return 0; | |
240 | } | |
241 | ||
0497f5b0 JB |
242 | /* Check whether TYPE is "Structure or Union". |
243 | ||
244 | In terms of Ada subprogram calls, arrays are treated the same as | |
245 | struct and union types. So this function also returns non-zero | |
246 | for array types. */ | |
c906108c | 247 | |
386c036b MK |
248 | static int |
249 | sparc_structure_or_union_p (const struct type *type) | |
250 | { | |
251 | switch (TYPE_CODE (type)) | |
252 | { | |
253 | case TYPE_CODE_STRUCT: | |
254 | case TYPE_CODE_UNION: | |
0497f5b0 | 255 | case TYPE_CODE_ARRAY: |
386c036b MK |
256 | return 1; |
257 | default: | |
258 | break; | |
c906108c | 259 | } |
386c036b MK |
260 | |
261 | return 0; | |
c906108c | 262 | } |
386c036b MK |
263 | |
264 | /* Register information. */ | |
265 | ||
266 | static const char *sparc32_register_names[] = | |
5af923b0 | 267 | { |
386c036b MK |
268 | "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", |
269 | "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7", | |
270 | "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", | |
271 | "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7", | |
272 | ||
273 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
274 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
275 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
276 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
277 | ||
278 | "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr" | |
5af923b0 MS |
279 | }; |
280 | ||
386c036b MK |
281 | /* Total number of registers. */ |
282 | #define SPARC32_NUM_REGS ARRAY_SIZE (sparc32_register_names) | |
c906108c | 283 | |
386c036b MK |
284 | /* We provide the aliases %d0..%d30 for the floating registers as |
285 | "psuedo" registers. */ | |
286 | ||
287 | static const char *sparc32_pseudo_register_names[] = | |
288 | { | |
289 | "d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14", | |
290 | "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30" | |
291 | }; | |
292 | ||
293 | /* Total number of pseudo registers. */ | |
294 | #define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names) | |
295 | ||
296 | /* Return the name of register REGNUM. */ | |
297 | ||
298 | static const char * | |
d93859e2 | 299 | sparc32_register_name (struct gdbarch *gdbarch, int regnum) |
386c036b MK |
300 | { |
301 | if (regnum >= 0 && regnum < SPARC32_NUM_REGS) | |
302 | return sparc32_register_names[regnum]; | |
303 | ||
304 | if (regnum < SPARC32_NUM_REGS + SPARC32_NUM_PSEUDO_REGS) | |
305 | return sparc32_pseudo_register_names[regnum - SPARC32_NUM_REGS]; | |
306 | ||
307 | return NULL; | |
308 | } | |
2d457077 | 309 | \f |
209bd28e | 310 | /* Construct types for ISA-specific registers. */ |
2d457077 | 311 | |
209bd28e UW |
312 | static struct type * |
313 | sparc_psr_type (struct gdbarch *gdbarch) | |
314 | { | |
315 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2d457077 | 316 | |
209bd28e UW |
317 | if (!tdep->sparc_psr_type) |
318 | { | |
319 | struct type *type; | |
2d457077 | 320 | |
e9bb382b | 321 | type = arch_flags_type (gdbarch, "builtin_type_sparc_psr", 4); |
209bd28e UW |
322 | append_flags_type_flag (type, 5, "ET"); |
323 | append_flags_type_flag (type, 6, "PS"); | |
324 | append_flags_type_flag (type, 7, "S"); | |
325 | append_flags_type_flag (type, 12, "EF"); | |
326 | append_flags_type_flag (type, 13, "EC"); | |
2d457077 | 327 | |
209bd28e UW |
328 | tdep->sparc_psr_type = type; |
329 | } | |
330 | ||
331 | return tdep->sparc_psr_type; | |
332 | } | |
333 | ||
334 | static struct type * | |
335 | sparc_fsr_type (struct gdbarch *gdbarch) | |
2d457077 | 336 | { |
209bd28e UW |
337 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
338 | ||
339 | if (!tdep->sparc_fsr_type) | |
340 | { | |
341 | struct type *type; | |
342 | ||
e9bb382b | 343 | type = arch_flags_type (gdbarch, "builtin_type_sparc_fsr", 4); |
209bd28e UW |
344 | append_flags_type_flag (type, 0, "NXA"); |
345 | append_flags_type_flag (type, 1, "DZA"); | |
346 | append_flags_type_flag (type, 2, "UFA"); | |
347 | append_flags_type_flag (type, 3, "OFA"); | |
348 | append_flags_type_flag (type, 4, "NVA"); | |
349 | append_flags_type_flag (type, 5, "NXC"); | |
350 | append_flags_type_flag (type, 6, "DZC"); | |
351 | append_flags_type_flag (type, 7, "UFC"); | |
352 | append_flags_type_flag (type, 8, "OFC"); | |
353 | append_flags_type_flag (type, 9, "NVC"); | |
354 | append_flags_type_flag (type, 22, "NS"); | |
355 | append_flags_type_flag (type, 23, "NXM"); | |
356 | append_flags_type_flag (type, 24, "DZM"); | |
357 | append_flags_type_flag (type, 25, "UFM"); | |
358 | append_flags_type_flag (type, 26, "OFM"); | |
359 | append_flags_type_flag (type, 27, "NVM"); | |
360 | ||
361 | tdep->sparc_fsr_type = type; | |
362 | } | |
363 | ||
364 | return tdep->sparc_fsr_type; | |
2d457077 | 365 | } |
386c036b MK |
366 | |
367 | /* Return the GDB type object for the "standard" data type of data in | |
c378eb4e | 368 | register REGNUM. */ |
386c036b MK |
369 | |
370 | static struct type * | |
371 | sparc32_register_type (struct gdbarch *gdbarch, int regnum) | |
372 | { | |
373 | if (regnum >= SPARC_F0_REGNUM && regnum <= SPARC_F31_REGNUM) | |
0dfff4cb | 374 | return builtin_type (gdbarch)->builtin_float; |
386c036b MK |
375 | |
376 | if (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM) | |
0dfff4cb | 377 | return builtin_type (gdbarch)->builtin_double; |
386c036b MK |
378 | |
379 | if (regnum == SPARC_SP_REGNUM || regnum == SPARC_FP_REGNUM) | |
0dfff4cb | 380 | return builtin_type (gdbarch)->builtin_data_ptr; |
386c036b MK |
381 | |
382 | if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM) | |
0dfff4cb | 383 | return builtin_type (gdbarch)->builtin_func_ptr; |
386c036b | 384 | |
2d457077 | 385 | if (regnum == SPARC32_PSR_REGNUM) |
209bd28e | 386 | return sparc_psr_type (gdbarch); |
2d457077 MK |
387 | |
388 | if (regnum == SPARC32_FSR_REGNUM) | |
209bd28e | 389 | return sparc_fsr_type (gdbarch); |
2d457077 | 390 | |
df4df182 | 391 | return builtin_type (gdbarch)->builtin_int32; |
386c036b MK |
392 | } |
393 | ||
05d1431c | 394 | static enum register_status |
386c036b MK |
395 | sparc32_pseudo_register_read (struct gdbarch *gdbarch, |
396 | struct regcache *regcache, | |
e1613aba | 397 | int regnum, gdb_byte *buf) |
386c036b | 398 | { |
05d1431c PA |
399 | enum register_status status; |
400 | ||
386c036b MK |
401 | gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM); |
402 | ||
403 | regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM); | |
05d1431c PA |
404 | status = regcache_raw_read (regcache, regnum, buf); |
405 | if (status == REG_VALID) | |
406 | status = regcache_raw_read (regcache, regnum + 1, buf + 4); | |
407 | return status; | |
386c036b MK |
408 | } |
409 | ||
410 | static void | |
411 | sparc32_pseudo_register_write (struct gdbarch *gdbarch, | |
412 | struct regcache *regcache, | |
e1613aba | 413 | int regnum, const gdb_byte *buf) |
386c036b MK |
414 | { |
415 | gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM); | |
416 | ||
417 | regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM); | |
418 | regcache_raw_write (regcache, regnum, buf); | |
e1613aba | 419 | regcache_raw_write (regcache, regnum + 1, buf + 4); |
386c036b MK |
420 | } |
421 | \f | |
422 | ||
49a45ecf JB |
423 | static CORE_ADDR |
424 | sparc32_frame_align (struct gdbarch *gdbarch, CORE_ADDR address) | |
425 | { | |
426 | /* The ABI requires double-word alignment. */ | |
427 | return address & ~0x7; | |
428 | } | |
429 | ||
386c036b MK |
430 | static CORE_ADDR |
431 | sparc32_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, | |
82585c72 | 432 | CORE_ADDR funcaddr, |
386c036b MK |
433 | struct value **args, int nargs, |
434 | struct type *value_type, | |
e4fd649a UW |
435 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr, |
436 | struct regcache *regcache) | |
c906108c | 437 | { |
e17a4113 UW |
438 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
439 | ||
386c036b MK |
440 | *bp_addr = sp - 4; |
441 | *real_pc = funcaddr; | |
442 | ||
d80b854b | 443 | if (using_struct_return (gdbarch, NULL, value_type)) |
c906108c | 444 | { |
e1613aba | 445 | gdb_byte buf[4]; |
386c036b MK |
446 | |
447 | /* This is an UNIMP instruction. */ | |
e17a4113 UW |
448 | store_unsigned_integer (buf, 4, byte_order, |
449 | TYPE_LENGTH (value_type) & 0x1fff); | |
386c036b MK |
450 | write_memory (sp - 8, buf, 4); |
451 | return sp - 8; | |
c906108c SS |
452 | } |
453 | ||
386c036b MK |
454 | return sp - 4; |
455 | } | |
456 | ||
457 | static CORE_ADDR | |
458 | sparc32_store_arguments (struct regcache *regcache, int nargs, | |
459 | struct value **args, CORE_ADDR sp, | |
460 | int struct_return, CORE_ADDR struct_addr) | |
461 | { | |
df4df182 | 462 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
e17a4113 | 463 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
386c036b MK |
464 | /* Number of words in the "parameter array". */ |
465 | int num_elements = 0; | |
466 | int element = 0; | |
467 | int i; | |
468 | ||
469 | for (i = 0; i < nargs; i++) | |
c906108c | 470 | { |
4991999e | 471 | struct type *type = value_type (args[i]); |
386c036b MK |
472 | int len = TYPE_LENGTH (type); |
473 | ||
474 | if (sparc_structure_or_union_p (type) | |
fe10a582 DM |
475 | || (sparc_floating_p (type) && len == 16) |
476 | || sparc_complex_floating_p (type)) | |
c906108c | 477 | { |
386c036b MK |
478 | /* Structure, Union and Quad-Precision Arguments. */ |
479 | sp -= len; | |
480 | ||
481 | /* Use doubleword alignment for these values. That's always | |
482 | correct, and wasting a few bytes shouldn't be a problem. */ | |
483 | sp &= ~0x7; | |
484 | ||
0fd88904 | 485 | write_memory (sp, value_contents (args[i]), len); |
386c036b MK |
486 | args[i] = value_from_pointer (lookup_pointer_type (type), sp); |
487 | num_elements++; | |
488 | } | |
489 | else if (sparc_floating_p (type)) | |
490 | { | |
491 | /* Floating arguments. */ | |
492 | gdb_assert (len == 4 || len == 8); | |
493 | num_elements += (len / 4); | |
c906108c | 494 | } |
c5aa993b JM |
495 | else |
496 | { | |
386c036b MK |
497 | /* Integral and pointer arguments. */ |
498 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
499 | ||
500 | if (len < 4) | |
df4df182 UW |
501 | args[i] = value_cast (builtin_type (gdbarch)->builtin_int32, |
502 | args[i]); | |
386c036b | 503 | num_elements += ((len + 3) / 4); |
c5aa993b | 504 | } |
c906108c | 505 | } |
c906108c | 506 | |
386c036b MK |
507 | /* Always allocate at least six words. */ |
508 | sp -= max (6, num_elements) * 4; | |
c906108c | 509 | |
386c036b MK |
510 | /* The psABI says that "Software convention requires space for the |
511 | struct/union return value pointer, even if the word is unused." */ | |
512 | sp -= 4; | |
c906108c | 513 | |
386c036b MK |
514 | /* The psABI says that "Although software convention and the |
515 | operating system require every stack frame to be doubleword | |
516 | aligned." */ | |
517 | sp &= ~0x7; | |
c906108c | 518 | |
386c036b | 519 | for (i = 0; i < nargs; i++) |
c906108c | 520 | { |
0fd88904 | 521 | const bfd_byte *valbuf = value_contents (args[i]); |
4991999e | 522 | struct type *type = value_type (args[i]); |
386c036b | 523 | int len = TYPE_LENGTH (type); |
c906108c | 524 | |
386c036b | 525 | gdb_assert (len == 4 || len == 8); |
c906108c | 526 | |
386c036b MK |
527 | if (element < 6) |
528 | { | |
529 | int regnum = SPARC_O0_REGNUM + element; | |
c906108c | 530 | |
386c036b MK |
531 | regcache_cooked_write (regcache, regnum, valbuf); |
532 | if (len > 4 && element < 5) | |
533 | regcache_cooked_write (regcache, regnum + 1, valbuf + 4); | |
534 | } | |
5af923b0 | 535 | |
386c036b MK |
536 | /* Always store the argument in memory. */ |
537 | write_memory (sp + 4 + element * 4, valbuf, len); | |
538 | element += len / 4; | |
539 | } | |
c906108c | 540 | |
386c036b | 541 | gdb_assert (element == num_elements); |
c906108c | 542 | |
386c036b | 543 | if (struct_return) |
c906108c | 544 | { |
e1613aba | 545 | gdb_byte buf[4]; |
c906108c | 546 | |
e17a4113 | 547 | store_unsigned_integer (buf, 4, byte_order, struct_addr); |
386c036b MK |
548 | write_memory (sp, buf, 4); |
549 | } | |
c906108c | 550 | |
386c036b | 551 | return sp; |
c906108c SS |
552 | } |
553 | ||
386c036b | 554 | static CORE_ADDR |
7d9b040b | 555 | sparc32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
386c036b MK |
556 | struct regcache *regcache, CORE_ADDR bp_addr, |
557 | int nargs, struct value **args, CORE_ADDR sp, | |
558 | int struct_return, CORE_ADDR struct_addr) | |
c906108c | 559 | { |
386c036b MK |
560 | CORE_ADDR call_pc = (struct_return ? (bp_addr - 12) : (bp_addr - 8)); |
561 | ||
562 | /* Set return address. */ | |
563 | regcache_cooked_write_unsigned (regcache, SPARC_O7_REGNUM, call_pc); | |
564 | ||
565 | /* Set up function arguments. */ | |
566 | sp = sparc32_store_arguments (regcache, nargs, args, sp, | |
567 | struct_return, struct_addr); | |
568 | ||
569 | /* Allocate the 16-word window save area. */ | |
570 | sp -= 16 * 4; | |
c906108c | 571 | |
386c036b MK |
572 | /* Stack should be doubleword aligned at this point. */ |
573 | gdb_assert (sp % 8 == 0); | |
c906108c | 574 | |
386c036b MK |
575 | /* Finally, update the stack pointer. */ |
576 | regcache_cooked_write_unsigned (regcache, SPARC_SP_REGNUM, sp); | |
577 | ||
578 | return sp; | |
579 | } | |
580 | \f | |
c906108c | 581 | |
386c036b MK |
582 | /* Use the program counter to determine the contents and size of a |
583 | breakpoint instruction. Return a pointer to a string of bytes that | |
584 | encode a breakpoint instruction, store the length of the string in | |
585 | *LEN and optionally adjust *PC to point to the correct memory | |
586 | location for inserting the breakpoint. */ | |
587 | ||
e1613aba | 588 | static const gdb_byte * |
67d57894 | 589 | sparc_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len) |
386c036b | 590 | { |
864a1a37 | 591 | static const gdb_byte break_insn[] = { 0x91, 0xd0, 0x20, 0x01 }; |
c5aa993b | 592 | |
386c036b MK |
593 | *len = sizeof (break_insn); |
594 | return break_insn; | |
c906108c | 595 | } |
386c036b | 596 | \f |
c906108c | 597 | |
386c036b | 598 | /* Allocate and initialize a frame cache. */ |
c906108c | 599 | |
386c036b MK |
600 | static struct sparc_frame_cache * |
601 | sparc_alloc_frame_cache (void) | |
602 | { | |
603 | struct sparc_frame_cache *cache; | |
604 | int i; | |
c906108c | 605 | |
386c036b | 606 | cache = FRAME_OBSTACK_ZALLOC (struct sparc_frame_cache); |
c906108c | 607 | |
386c036b MK |
608 | /* Base address. */ |
609 | cache->base = 0; | |
610 | cache->pc = 0; | |
c906108c | 611 | |
386c036b MK |
612 | /* Frameless until proven otherwise. */ |
613 | cache->frameless_p = 1; | |
369c397b JB |
614 | cache->frame_offset = 0; |
615 | cache->saved_regs_mask = 0; | |
616 | cache->copied_regs_mask = 0; | |
386c036b MK |
617 | cache->struct_return_p = 0; |
618 | ||
619 | return cache; | |
620 | } | |
621 | ||
b0b92586 JB |
622 | /* GCC generates several well-known sequences of instructions at the begining |
623 | of each function prologue when compiling with -fstack-check. If one of | |
624 | such sequences starts at START_PC, then return the address of the | |
625 | instruction immediately past this sequence. Otherwise, return START_PC. */ | |
626 | ||
627 | static CORE_ADDR | |
628 | sparc_skip_stack_check (const CORE_ADDR start_pc) | |
629 | { | |
630 | CORE_ADDR pc = start_pc; | |
631 | unsigned long insn; | |
632 | int offset_stack_checking_sequence = 0; | |
2067c8d4 | 633 | int probing_loop = 0; |
b0b92586 JB |
634 | |
635 | /* With GCC, all stack checking sequences begin with the same two | |
2067c8d4 | 636 | instructions, plus an optional one in the case of a probing loop: |
b0b92586 | 637 | |
2067c8d4 JG |
638 | sethi <some immediate>, %g1 |
639 | sub %sp, %g1, %g1 | |
640 | ||
641 | or: | |
642 | ||
643 | sethi <some immediate>, %g1 | |
644 | sethi <some immediate>, %g4 | |
645 | sub %sp, %g1, %g1 | |
646 | ||
647 | or: | |
648 | ||
649 | sethi <some immediate>, %g1 | |
650 | sub %sp, %g1, %g1 | |
651 | sethi <some immediate>, %g4 | |
652 | ||
653 | If the optional instruction is found (setting g4), assume that a | |
654 | probing loop will follow. */ | |
655 | ||
656 | /* sethi <some immediate>, %g1 */ | |
b0b92586 JB |
657 | insn = sparc_fetch_instruction (pc); |
658 | pc = pc + 4; | |
659 | if (!(X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 1)) | |
660 | return start_pc; | |
661 | ||
2067c8d4 | 662 | /* optional: sethi <some immediate>, %g4 */ |
b0b92586 JB |
663 | insn = sparc_fetch_instruction (pc); |
664 | pc = pc + 4; | |
2067c8d4 JG |
665 | if (X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 4) |
666 | { | |
667 | probing_loop = 1; | |
668 | insn = sparc_fetch_instruction (pc); | |
669 | pc = pc + 4; | |
670 | } | |
671 | ||
672 | /* sub %sp, %g1, %g1 */ | |
b0b92586 JB |
673 | if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn) |
674 | && X_RD (insn) == 1 && X_RS1 (insn) == 14 && X_RS2 (insn) == 1)) | |
675 | return start_pc; | |
676 | ||
677 | insn = sparc_fetch_instruction (pc); | |
678 | pc = pc + 4; | |
679 | ||
2067c8d4 JG |
680 | /* optional: sethi <some immediate>, %g4 */ |
681 | if (X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 4) | |
682 | { | |
683 | probing_loop = 1; | |
684 | insn = sparc_fetch_instruction (pc); | |
685 | pc = pc + 4; | |
686 | } | |
687 | ||
b0b92586 JB |
688 | /* First possible sequence: |
689 | [first two instructions above] | |
690 | clr [%g1 - some immediate] */ | |
691 | ||
692 | /* clr [%g1 - some immediate] */ | |
693 | if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) | |
694 | && X_RS1 (insn) == 1 && X_RD (insn) == 0) | |
695 | { | |
696 | /* Valid stack-check sequence, return the new PC. */ | |
697 | return pc; | |
698 | } | |
699 | ||
700 | /* Second possible sequence: A small number of probes. | |
701 | [first two instructions above] | |
702 | clr [%g1] | |
703 | add %g1, -<some immediate>, %g1 | |
704 | clr [%g1] | |
705 | [repeat the two instructions above any (small) number of times] | |
706 | clr [%g1 - some immediate] */ | |
707 | ||
708 | /* clr [%g1] */ | |
709 | else if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn) | |
710 | && X_RS1 (insn) == 1 && X_RD (insn) == 0) | |
711 | { | |
712 | while (1) | |
713 | { | |
714 | /* add %g1, -<some immediate>, %g1 */ | |
715 | insn = sparc_fetch_instruction (pc); | |
716 | pc = pc + 4; | |
717 | if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn) | |
718 | && X_RS1 (insn) == 1 && X_RD (insn) == 1)) | |
719 | break; | |
720 | ||
721 | /* clr [%g1] */ | |
722 | insn = sparc_fetch_instruction (pc); | |
723 | pc = pc + 4; | |
724 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn) | |
725 | && X_RD (insn) == 0 && X_RS1 (insn) == 1)) | |
726 | return start_pc; | |
727 | } | |
728 | ||
729 | /* clr [%g1 - some immediate] */ | |
730 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) | |
731 | && X_RS1 (insn) == 1 && X_RD (insn) == 0)) | |
732 | return start_pc; | |
733 | ||
734 | /* We found a valid stack-check sequence, return the new PC. */ | |
735 | return pc; | |
736 | } | |
737 | ||
738 | /* Third sequence: A probing loop. | |
2067c8d4 | 739 | [first three instructions above] |
b0b92586 JB |
740 | sub %g1, %g4, %g4 |
741 | cmp %g1, %g4 | |
742 | be <disp> | |
743 | add %g1, -<some immediate>, %g1 | |
744 | ba <disp> | |
745 | clr [%g1] | |
2067c8d4 JG |
746 | |
747 | And an optional last probe for the remainder: | |
748 | ||
b0b92586 JB |
749 | clr [%g4 - some immediate] */ |
750 | ||
2067c8d4 | 751 | if (probing_loop) |
b0b92586 JB |
752 | { |
753 | /* sub %g1, %g4, %g4 */ | |
b0b92586 JB |
754 | if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn) |
755 | && X_RD (insn) == 4 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4)) | |
756 | return start_pc; | |
757 | ||
758 | /* cmp %g1, %g4 */ | |
759 | insn = sparc_fetch_instruction (pc); | |
760 | pc = pc + 4; | |
761 | if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x14 && !X_I(insn) | |
762 | && X_RD (insn) == 0 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4)) | |
763 | return start_pc; | |
764 | ||
765 | /* be <disp> */ | |
766 | insn = sparc_fetch_instruction (pc); | |
767 | pc = pc + 4; | |
768 | if (!(X_OP (insn) == 0 && X_COND (insn) == 0x1)) | |
769 | return start_pc; | |
770 | ||
771 | /* add %g1, -<some immediate>, %g1 */ | |
772 | insn = sparc_fetch_instruction (pc); | |
773 | pc = pc + 4; | |
774 | if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn) | |
775 | && X_RS1 (insn) == 1 && X_RD (insn) == 1)) | |
776 | return start_pc; | |
777 | ||
778 | /* ba <disp> */ | |
779 | insn = sparc_fetch_instruction (pc); | |
780 | pc = pc + 4; | |
781 | if (!(X_OP (insn) == 0 && X_COND (insn) == 0x8)) | |
782 | return start_pc; | |
783 | ||
2067c8d4 | 784 | /* clr [%g1] (st %g0, [%g1] or st %g0, [%g1+0]) */ |
b0b92586 JB |
785 | insn = sparc_fetch_instruction (pc); |
786 | pc = pc + 4; | |
2067c8d4 JG |
787 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 |
788 | && X_RD (insn) == 0 && X_RS1 (insn) == 1 | |
789 | && (!X_I(insn) || X_SIMM13 (insn) == 0))) | |
b0b92586 JB |
790 | return start_pc; |
791 | ||
2067c8d4 JG |
792 | /* We found a valid stack-check sequence, return the new PC. */ |
793 | ||
794 | /* optional: clr [%g4 - some immediate] */ | |
b0b92586 JB |
795 | insn = sparc_fetch_instruction (pc); |
796 | pc = pc + 4; | |
797 | if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) | |
798 | && X_RS1 (insn) == 4 && X_RD (insn) == 0)) | |
2067c8d4 JG |
799 | return pc - 4; |
800 | else | |
801 | return pc; | |
b0b92586 JB |
802 | } |
803 | ||
804 | /* No stack check code in our prologue, return the start_pc. */ | |
805 | return start_pc; | |
806 | } | |
807 | ||
369c397b JB |
808 | /* Record the effect of a SAVE instruction on CACHE. */ |
809 | ||
810 | void | |
811 | sparc_record_save_insn (struct sparc_frame_cache *cache) | |
812 | { | |
813 | /* The frame is set up. */ | |
814 | cache->frameless_p = 0; | |
815 | ||
816 | /* The frame pointer contains the CFA. */ | |
817 | cache->frame_offset = 0; | |
818 | ||
819 | /* The `local' and `in' registers are all saved. */ | |
820 | cache->saved_regs_mask = 0xffff; | |
821 | ||
822 | /* The `out' registers are all renamed. */ | |
823 | cache->copied_regs_mask = 0xff; | |
824 | } | |
825 | ||
826 | /* Do a full analysis of the prologue at PC and update CACHE accordingly. | |
827 | Bail out early if CURRENT_PC is reached. Return the address where | |
828 | the analysis stopped. | |
829 | ||
830 | We handle both the traditional register window model and the single | |
831 | register window (aka flat) model. */ | |
832 | ||
386c036b | 833 | CORE_ADDR |
be8626e0 MD |
834 | sparc_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, |
835 | CORE_ADDR current_pc, struct sparc_frame_cache *cache) | |
c906108c | 836 | { |
be8626e0 | 837 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
386c036b MK |
838 | unsigned long insn; |
839 | int offset = 0; | |
c906108c | 840 | int dest = -1; |
c906108c | 841 | |
b0b92586 JB |
842 | pc = sparc_skip_stack_check (pc); |
843 | ||
386c036b MK |
844 | if (current_pc <= pc) |
845 | return current_pc; | |
846 | ||
847 | /* We have to handle to "Procedure Linkage Table" (PLT) special. On | |
848 | SPARC the linker usually defines a symbol (typically | |
849 | _PROCEDURE_LINKAGE_TABLE_) at the start of the .plt section. | |
850 | This symbol makes us end up here with PC pointing at the start of | |
851 | the PLT and CURRENT_PC probably pointing at a PLT entry. If we | |
852 | would do our normal prologue analysis, we would probably conclude | |
853 | that we've got a frame when in reality we don't, since the | |
854 | dynamic linker patches up the first PLT with some code that | |
855 | starts with a SAVE instruction. Patch up PC such that it points | |
856 | at the start of our PLT entry. */ | |
857 | if (tdep->plt_entry_size > 0 && in_plt_section (current_pc, NULL)) | |
858 | pc = current_pc - ((current_pc - pc) % tdep->plt_entry_size); | |
c906108c | 859 | |
386c036b MK |
860 | insn = sparc_fetch_instruction (pc); |
861 | ||
369c397b JB |
862 | /* Recognize store insns and record their sources. */ |
863 | while (X_OP (insn) == 3 | |
864 | && (X_OP3 (insn) == 0x4 /* stw */ | |
865 | || X_OP3 (insn) == 0x7 /* std */ | |
866 | || X_OP3 (insn) == 0xe) /* stx */ | |
867 | && X_RS1 (insn) == SPARC_SP_REGNUM) | |
868 | { | |
869 | int regnum = X_RD (insn); | |
870 | ||
871 | /* Recognize stores into the corresponding stack slots. */ | |
872 | if (regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM | |
873 | && ((X_I (insn) | |
874 | && X_SIMM13 (insn) == (X_OP3 (insn) == 0xe | |
875 | ? (regnum - SPARC_L0_REGNUM) * 8 + BIAS | |
876 | : (regnum - SPARC_L0_REGNUM) * 4)) | |
877 | || (!X_I (insn) && regnum == SPARC_L0_REGNUM))) | |
878 | { | |
879 | cache->saved_regs_mask |= (1 << (regnum - SPARC_L0_REGNUM)); | |
880 | if (X_OP3 (insn) == 0x7) | |
881 | cache->saved_regs_mask |= (1 << (regnum + 1 - SPARC_L0_REGNUM)); | |
882 | } | |
883 | ||
884 | offset += 4; | |
885 | ||
886 | insn = sparc_fetch_instruction (pc + offset); | |
887 | } | |
888 | ||
386c036b MK |
889 | /* Recognize a SETHI insn and record its destination. */ |
890 | if (X_OP (insn) == 0 && X_OP2 (insn) == 0x04) | |
c906108c SS |
891 | { |
892 | dest = X_RD (insn); | |
386c036b MK |
893 | offset += 4; |
894 | ||
369c397b | 895 | insn = sparc_fetch_instruction (pc + offset); |
c906108c SS |
896 | } |
897 | ||
386c036b MK |
898 | /* Allow for an arithmetic operation on DEST or %g1. */ |
899 | if (X_OP (insn) == 2 && X_I (insn) | |
c906108c SS |
900 | && (X_RD (insn) == 1 || X_RD (insn) == dest)) |
901 | { | |
386c036b | 902 | offset += 4; |
c906108c | 903 | |
369c397b | 904 | insn = sparc_fetch_instruction (pc + offset); |
c906108c | 905 | } |
c906108c | 906 | |
386c036b MK |
907 | /* Check for the SAVE instruction that sets up the frame. */ |
908 | if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3c) | |
c906108c | 909 | { |
369c397b JB |
910 | sparc_record_save_insn (cache); |
911 | offset += 4; | |
912 | return pc + offset; | |
913 | } | |
914 | ||
915 | /* Check for an arithmetic operation on %sp. */ | |
916 | if (X_OP (insn) == 2 | |
917 | && (X_OP3 (insn) == 0 || X_OP3 (insn) == 0x4) | |
918 | && X_RS1 (insn) == SPARC_SP_REGNUM | |
919 | && X_RD (insn) == SPARC_SP_REGNUM) | |
920 | { | |
921 | if (X_I (insn)) | |
922 | { | |
923 | cache->frame_offset = X_SIMM13 (insn); | |
924 | if (X_OP3 (insn) == 0) | |
925 | cache->frame_offset = -cache->frame_offset; | |
926 | } | |
927 | offset += 4; | |
928 | ||
929 | insn = sparc_fetch_instruction (pc + offset); | |
930 | ||
931 | /* Check for an arithmetic operation that sets up the frame. */ | |
932 | if (X_OP (insn) == 2 | |
933 | && (X_OP3 (insn) == 0 || X_OP3 (insn) == 0x4) | |
934 | && X_RS1 (insn) == SPARC_SP_REGNUM | |
935 | && X_RD (insn) == SPARC_FP_REGNUM) | |
936 | { | |
937 | cache->frameless_p = 0; | |
938 | cache->frame_offset = 0; | |
939 | /* We could check that the amount subtracted to %sp above is the | |
940 | same as the one added here, but this seems superfluous. */ | |
941 | cache->copied_regs_mask |= 0x40; | |
942 | offset += 4; | |
943 | ||
944 | insn = sparc_fetch_instruction (pc + offset); | |
945 | } | |
946 | ||
947 | /* Check for a move (or) operation that copies the return register. */ | |
948 | if (X_OP (insn) == 2 | |
949 | && X_OP3 (insn) == 0x2 | |
950 | && !X_I (insn) | |
951 | && X_RS1 (insn) == SPARC_G0_REGNUM | |
952 | && X_RS2 (insn) == SPARC_O7_REGNUM | |
953 | && X_RD (insn) == SPARC_I7_REGNUM) | |
954 | { | |
955 | cache->copied_regs_mask |= 0x80; | |
956 | offset += 4; | |
957 | } | |
958 | ||
959 | return pc + offset; | |
c906108c SS |
960 | } |
961 | ||
962 | return pc; | |
963 | } | |
964 | ||
386c036b | 965 | static CORE_ADDR |
236369e7 | 966 | sparc_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame) |
386c036b MK |
967 | { |
968 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
236369e7 | 969 | return frame_unwind_register_unsigned (this_frame, tdep->pc_regnum); |
386c036b MK |
970 | } |
971 | ||
972 | /* Return PC of first real instruction of the function starting at | |
973 | START_PC. */ | |
f510d44e | 974 | |
386c036b | 975 | static CORE_ADDR |
6093d2eb | 976 | sparc32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
c906108c | 977 | { |
f510d44e DM |
978 | struct symtab_and_line sal; |
979 | CORE_ADDR func_start, func_end; | |
386c036b | 980 | struct sparc_frame_cache cache; |
f510d44e DM |
981 | |
982 | /* This is the preferred method, find the end of the prologue by | |
983 | using the debugging information. */ | |
984 | if (find_pc_partial_function (start_pc, NULL, &func_start, &func_end)) | |
985 | { | |
986 | sal = find_pc_line (func_start, 0); | |
987 | ||
988 | if (sal.end < func_end | |
989 | && start_pc <= sal.end) | |
990 | return sal.end; | |
991 | } | |
992 | ||
be8626e0 | 993 | start_pc = sparc_analyze_prologue (gdbarch, start_pc, 0xffffffffUL, &cache); |
075ccec8 MK |
994 | |
995 | /* The psABI says that "Although the first 6 words of arguments | |
996 | reside in registers, the standard stack frame reserves space for | |
997 | them.". It also suggests that a function may use that space to | |
998 | "write incoming arguments 0 to 5" into that space, and that's | |
999 | indeed what GCC seems to be doing. In that case GCC will | |
1000 | generate debug information that points to the stack slots instead | |
1001 | of the registers, so we should consider the instructions that | |
369c397b | 1002 | write out these incoming arguments onto the stack. */ |
075ccec8 | 1003 | |
369c397b | 1004 | while (1) |
075ccec8 MK |
1005 | { |
1006 | unsigned long insn = sparc_fetch_instruction (start_pc); | |
1007 | ||
369c397b JB |
1008 | /* Recognize instructions that store incoming arguments into the |
1009 | corresponding stack slots. */ | |
1010 | if (X_OP (insn) == 3 && (X_OP3 (insn) & 0x3c) == 0x04 | |
1011 | && X_I (insn) && X_RS1 (insn) == SPARC_FP_REGNUM) | |
075ccec8 | 1012 | { |
369c397b JB |
1013 | int regnum = X_RD (insn); |
1014 | ||
1015 | /* Case of arguments still in %o[0..5]. */ | |
1016 | if (regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O5_REGNUM | |
1017 | && !(cache.copied_regs_mask & (1 << (regnum - SPARC_O0_REGNUM))) | |
1018 | && X_SIMM13 (insn) == 68 + (regnum - SPARC_O0_REGNUM) * 4) | |
1019 | { | |
1020 | start_pc += 4; | |
1021 | continue; | |
1022 | } | |
1023 | ||
1024 | /* Case of arguments copied into %i[0..5]. */ | |
1025 | if (regnum >= SPARC_I0_REGNUM && regnum <= SPARC_I5_REGNUM | |
1026 | && (cache.copied_regs_mask & (1 << (regnum - SPARC_I0_REGNUM))) | |
1027 | && X_SIMM13 (insn) == 68 + (regnum - SPARC_I0_REGNUM) * 4) | |
1028 | { | |
1029 | start_pc += 4; | |
1030 | continue; | |
1031 | } | |
075ccec8 MK |
1032 | } |
1033 | ||
1034 | break; | |
1035 | } | |
1036 | ||
1037 | return start_pc; | |
c906108c SS |
1038 | } |
1039 | ||
386c036b | 1040 | /* Normal frames. */ |
9319a2fe | 1041 | |
386c036b | 1042 | struct sparc_frame_cache * |
236369e7 | 1043 | sparc_frame_cache (struct frame_info *this_frame, void **this_cache) |
9319a2fe | 1044 | { |
386c036b | 1045 | struct sparc_frame_cache *cache; |
9319a2fe | 1046 | |
386c036b MK |
1047 | if (*this_cache) |
1048 | return *this_cache; | |
c906108c | 1049 | |
386c036b MK |
1050 | cache = sparc_alloc_frame_cache (); |
1051 | *this_cache = cache; | |
c906108c | 1052 | |
236369e7 | 1053 | cache->pc = get_frame_func (this_frame); |
386c036b | 1054 | if (cache->pc != 0) |
236369e7 JB |
1055 | sparc_analyze_prologue (get_frame_arch (this_frame), cache->pc, |
1056 | get_frame_pc (this_frame), cache); | |
386c036b MK |
1057 | |
1058 | if (cache->frameless_p) | |
c906108c | 1059 | { |
cbeae229 MK |
1060 | /* This function is frameless, so %fp (%i6) holds the frame |
1061 | pointer for our calling frame. Use %sp (%o6) as this frame's | |
1062 | base address. */ | |
1063 | cache->base = | |
236369e7 | 1064 | get_frame_register_unsigned (this_frame, SPARC_SP_REGNUM); |
cbeae229 MK |
1065 | } |
1066 | else | |
1067 | { | |
1068 | /* For normal frames, %fp (%i6) holds the frame pointer, the | |
1069 | base address for the current stack frame. */ | |
1070 | cache->base = | |
236369e7 | 1071 | get_frame_register_unsigned (this_frame, SPARC_FP_REGNUM); |
c906108c | 1072 | } |
c906108c | 1073 | |
369c397b JB |
1074 | cache->base += cache->frame_offset; |
1075 | ||
5b2d44a0 MK |
1076 | if (cache->base & 1) |
1077 | cache->base += BIAS; | |
1078 | ||
386c036b | 1079 | return cache; |
c906108c | 1080 | } |
c906108c | 1081 | |
aff37fc1 DM |
1082 | static int |
1083 | sparc32_struct_return_from_sym (struct symbol *sym) | |
1084 | { | |
1085 | struct type *type = check_typedef (SYMBOL_TYPE (sym)); | |
1086 | enum type_code code = TYPE_CODE (type); | |
1087 | ||
1088 | if (code == TYPE_CODE_FUNC || code == TYPE_CODE_METHOD) | |
1089 | { | |
1090 | type = check_typedef (TYPE_TARGET_TYPE (type)); | |
1091 | if (sparc_structure_or_union_p (type) | |
1092 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)) | |
1093 | return 1; | |
1094 | } | |
1095 | ||
1096 | return 0; | |
1097 | } | |
1098 | ||
386c036b | 1099 | struct sparc_frame_cache * |
236369e7 | 1100 | sparc32_frame_cache (struct frame_info *this_frame, void **this_cache) |
c906108c | 1101 | { |
386c036b MK |
1102 | struct sparc_frame_cache *cache; |
1103 | struct symbol *sym; | |
c906108c | 1104 | |
386c036b MK |
1105 | if (*this_cache) |
1106 | return *this_cache; | |
c906108c | 1107 | |
236369e7 | 1108 | cache = sparc_frame_cache (this_frame, this_cache); |
c906108c | 1109 | |
386c036b MK |
1110 | sym = find_pc_function (cache->pc); |
1111 | if (sym) | |
c906108c | 1112 | { |
aff37fc1 | 1113 | cache->struct_return_p = sparc32_struct_return_from_sym (sym); |
c906108c | 1114 | } |
5465445a JB |
1115 | else |
1116 | { | |
1117 | /* There is no debugging information for this function to | |
1118 | help us determine whether this function returns a struct | |
1119 | or not. So we rely on another heuristic which is to check | |
1120 | the instruction at the return address and see if this is | |
1121 | an "unimp" instruction. If it is, then it is a struct-return | |
1122 | function. */ | |
1123 | CORE_ADDR pc; | |
369c397b JB |
1124 | int regnum = |
1125 | (cache->copied_regs_mask & 0x80) ? SPARC_I7_REGNUM : SPARC_O7_REGNUM; | |
5465445a | 1126 | |
236369e7 | 1127 | pc = get_frame_register_unsigned (this_frame, regnum) + 8; |
5465445a JB |
1128 | if (sparc_is_unimp_insn (pc)) |
1129 | cache->struct_return_p = 1; | |
1130 | } | |
c906108c | 1131 | |
386c036b MK |
1132 | return cache; |
1133 | } | |
1134 | ||
1135 | static void | |
236369e7 | 1136 | sparc32_frame_this_id (struct frame_info *this_frame, void **this_cache, |
386c036b MK |
1137 | struct frame_id *this_id) |
1138 | { | |
1139 | struct sparc_frame_cache *cache = | |
236369e7 | 1140 | sparc32_frame_cache (this_frame, this_cache); |
386c036b MK |
1141 | |
1142 | /* This marks the outermost frame. */ | |
1143 | if (cache->base == 0) | |
1144 | return; | |
1145 | ||
1146 | (*this_id) = frame_id_build (cache->base, cache->pc); | |
1147 | } | |
c906108c | 1148 | |
236369e7 JB |
1149 | static struct value * |
1150 | sparc32_frame_prev_register (struct frame_info *this_frame, | |
1151 | void **this_cache, int regnum) | |
386c036b | 1152 | { |
e17a4113 | 1153 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
386c036b | 1154 | struct sparc_frame_cache *cache = |
236369e7 | 1155 | sparc32_frame_cache (this_frame, this_cache); |
c906108c | 1156 | |
386c036b | 1157 | if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM) |
c906108c | 1158 | { |
236369e7 | 1159 | CORE_ADDR pc = (regnum == SPARC32_NPC_REGNUM) ? 4 : 0; |
386c036b | 1160 | |
236369e7 JB |
1161 | /* If this functions has a Structure, Union or Quad-Precision |
1162 | return value, we have to skip the UNIMP instruction that encodes | |
1163 | the size of the structure. */ | |
1164 | if (cache->struct_return_p) | |
1165 | pc += 4; | |
386c036b | 1166 | |
369c397b JB |
1167 | regnum = |
1168 | (cache->copied_regs_mask & 0x80) ? SPARC_I7_REGNUM : SPARC_O7_REGNUM; | |
236369e7 JB |
1169 | pc += get_frame_register_unsigned (this_frame, regnum) + 8; |
1170 | return frame_unwind_got_constant (this_frame, regnum, pc); | |
c906108c SS |
1171 | } |
1172 | ||
42cdca6c MK |
1173 | /* Handle StackGhost. */ |
1174 | { | |
e17a4113 | 1175 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
42cdca6c MK |
1176 | |
1177 | if (wcookie != 0 && !cache->frameless_p && regnum == SPARC_I7_REGNUM) | |
1178 | { | |
236369e7 JB |
1179 | CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4; |
1180 | ULONGEST i7; | |
1181 | ||
1182 | /* Read the value in from memory. */ | |
1183 | i7 = get_frame_memory_unsigned (this_frame, addr, 4); | |
1184 | return frame_unwind_got_constant (this_frame, regnum, i7 ^ wcookie); | |
42cdca6c MK |
1185 | } |
1186 | } | |
1187 | ||
369c397b | 1188 | /* The previous frame's `local' and `in' registers may have been saved |
386c036b | 1189 | in the register save area. */ |
369c397b JB |
1190 | if (regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM |
1191 | && (cache->saved_regs_mask & (1 << (regnum - SPARC_L0_REGNUM)))) | |
c906108c | 1192 | { |
236369e7 | 1193 | CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4; |
386c036b | 1194 | |
236369e7 | 1195 | return frame_unwind_got_memory (this_frame, regnum, addr); |
386c036b | 1196 | } |
c906108c | 1197 | |
369c397b JB |
1198 | /* The previous frame's `out' registers may be accessible as the current |
1199 | frame's `in' registers. */ | |
1200 | if (regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O7_REGNUM | |
1201 | && (cache->copied_regs_mask & (1 << (regnum - SPARC_O0_REGNUM)))) | |
386c036b | 1202 | regnum += (SPARC_I0_REGNUM - SPARC_O0_REGNUM); |
5af923b0 | 1203 | |
236369e7 | 1204 | return frame_unwind_got_register (this_frame, regnum, regnum); |
386c036b | 1205 | } |
c906108c | 1206 | |
386c036b MK |
1207 | static const struct frame_unwind sparc32_frame_unwind = |
1208 | { | |
1209 | NORMAL_FRAME, | |
8fbca658 | 1210 | default_frame_unwind_stop_reason, |
386c036b | 1211 | sparc32_frame_this_id, |
236369e7 JB |
1212 | sparc32_frame_prev_register, |
1213 | NULL, | |
1214 | default_frame_sniffer | |
386c036b | 1215 | }; |
386c036b | 1216 | \f |
c906108c | 1217 | |
386c036b | 1218 | static CORE_ADDR |
236369e7 | 1219 | sparc32_frame_base_address (struct frame_info *this_frame, void **this_cache) |
386c036b MK |
1220 | { |
1221 | struct sparc_frame_cache *cache = | |
236369e7 | 1222 | sparc32_frame_cache (this_frame, this_cache); |
c906108c | 1223 | |
386c036b MK |
1224 | return cache->base; |
1225 | } | |
c906108c | 1226 | |
386c036b MK |
1227 | static const struct frame_base sparc32_frame_base = |
1228 | { | |
1229 | &sparc32_frame_unwind, | |
1230 | sparc32_frame_base_address, | |
1231 | sparc32_frame_base_address, | |
1232 | sparc32_frame_base_address | |
1233 | }; | |
c906108c | 1234 | |
386c036b | 1235 | static struct frame_id |
236369e7 | 1236 | sparc_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
386c036b MK |
1237 | { |
1238 | CORE_ADDR sp; | |
5af923b0 | 1239 | |
236369e7 | 1240 | sp = get_frame_register_unsigned (this_frame, SPARC_SP_REGNUM); |
5b2d44a0 MK |
1241 | if (sp & 1) |
1242 | sp += BIAS; | |
236369e7 | 1243 | return frame_id_build (sp, get_frame_pc (this_frame)); |
386c036b MK |
1244 | } |
1245 | \f | |
c906108c | 1246 | |
3923a2b2 MK |
1247 | /* Extract a function return value of TYPE from REGCACHE, and copy |
1248 | that into VALBUF. */ | |
5af923b0 | 1249 | |
386c036b MK |
1250 | static void |
1251 | sparc32_extract_return_value (struct type *type, struct regcache *regcache, | |
e1613aba | 1252 | gdb_byte *valbuf) |
386c036b MK |
1253 | { |
1254 | int len = TYPE_LENGTH (type); | |
fe10a582 | 1255 | gdb_byte buf[32]; |
c906108c | 1256 | |
386c036b MK |
1257 | gdb_assert (!sparc_structure_or_union_p (type)); |
1258 | gdb_assert (!(sparc_floating_p (type) && len == 16)); | |
c906108c | 1259 | |
fe10a582 | 1260 | if (sparc_floating_p (type) || sparc_complex_floating_p (type)) |
5af923b0 | 1261 | { |
386c036b MK |
1262 | /* Floating return values. */ |
1263 | regcache_cooked_read (regcache, SPARC_F0_REGNUM, buf); | |
1264 | if (len > 4) | |
1265 | regcache_cooked_read (regcache, SPARC_F1_REGNUM, buf + 4); | |
fe10a582 DM |
1266 | if (len > 8) |
1267 | { | |
1268 | regcache_cooked_read (regcache, SPARC_F2_REGNUM, buf + 8); | |
1269 | regcache_cooked_read (regcache, SPARC_F3_REGNUM, buf + 12); | |
1270 | } | |
1271 | if (len > 16) | |
1272 | { | |
1273 | regcache_cooked_read (regcache, SPARC_F4_REGNUM, buf + 16); | |
1274 | regcache_cooked_read (regcache, SPARC_F5_REGNUM, buf + 20); | |
1275 | regcache_cooked_read (regcache, SPARC_F6_REGNUM, buf + 24); | |
1276 | regcache_cooked_read (regcache, SPARC_F7_REGNUM, buf + 28); | |
1277 | } | |
386c036b | 1278 | memcpy (valbuf, buf, len); |
5af923b0 MS |
1279 | } |
1280 | else | |
1281 | { | |
386c036b MK |
1282 | /* Integral and pointer return values. */ |
1283 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
c906108c | 1284 | |
386c036b MK |
1285 | regcache_cooked_read (regcache, SPARC_O0_REGNUM, buf); |
1286 | if (len > 4) | |
1287 | { | |
1288 | regcache_cooked_read (regcache, SPARC_O1_REGNUM, buf + 4); | |
1289 | gdb_assert (len == 8); | |
1290 | memcpy (valbuf, buf, 8); | |
1291 | } | |
1292 | else | |
1293 | { | |
1294 | /* Just stripping off any unused bytes should preserve the | |
1295 | signed-ness just fine. */ | |
1296 | memcpy (valbuf, buf + 4 - len, len); | |
1297 | } | |
1298 | } | |
1299 | } | |
c906108c | 1300 | |
3923a2b2 MK |
1301 | /* Store the function return value of type TYPE from VALBUF into |
1302 | REGCACHE. */ | |
c906108c | 1303 | |
386c036b MK |
1304 | static void |
1305 | sparc32_store_return_value (struct type *type, struct regcache *regcache, | |
e1613aba | 1306 | const gdb_byte *valbuf) |
386c036b MK |
1307 | { |
1308 | int len = TYPE_LENGTH (type); | |
e1613aba | 1309 | gdb_byte buf[8]; |
c906108c | 1310 | |
386c036b MK |
1311 | gdb_assert (!sparc_structure_or_union_p (type)); |
1312 | gdb_assert (!(sparc_floating_p (type) && len == 16)); | |
a9789a6b | 1313 | gdb_assert (len <= 8); |
c906108c | 1314 | |
fe10a582 | 1315 | if (sparc_floating_p (type) || sparc_complex_floating_p (type)) |
386c036b MK |
1316 | { |
1317 | /* Floating return values. */ | |
1318 | memcpy (buf, valbuf, len); | |
1319 | regcache_cooked_write (regcache, SPARC_F0_REGNUM, buf); | |
1320 | if (len > 4) | |
1321 | regcache_cooked_write (regcache, SPARC_F1_REGNUM, buf + 4); | |
fe10a582 DM |
1322 | if (len > 8) |
1323 | { | |
1324 | regcache_cooked_write (regcache, SPARC_F2_REGNUM, buf + 8); | |
1325 | regcache_cooked_write (regcache, SPARC_F3_REGNUM, buf + 12); | |
1326 | } | |
1327 | if (len > 16) | |
1328 | { | |
1329 | regcache_cooked_write (regcache, SPARC_F4_REGNUM, buf + 16); | |
1330 | regcache_cooked_write (regcache, SPARC_F5_REGNUM, buf + 20); | |
1331 | regcache_cooked_write (regcache, SPARC_F6_REGNUM, buf + 24); | |
1332 | regcache_cooked_write (regcache, SPARC_F7_REGNUM, buf + 28); | |
1333 | } | |
386c036b MK |
1334 | } |
1335 | else | |
c906108c | 1336 | { |
386c036b MK |
1337 | /* Integral and pointer return values. */ |
1338 | gdb_assert (sparc_integral_or_pointer_p (type)); | |
1339 | ||
1340 | if (len > 4) | |
2757dd86 | 1341 | { |
386c036b MK |
1342 | gdb_assert (len == 8); |
1343 | memcpy (buf, valbuf, 8); | |
1344 | regcache_cooked_write (regcache, SPARC_O1_REGNUM, buf + 4); | |
2757dd86 AC |
1345 | } |
1346 | else | |
1347 | { | |
386c036b MK |
1348 | /* ??? Do we need to do any sign-extension here? */ |
1349 | memcpy (buf + 4 - len, valbuf, len); | |
2757dd86 | 1350 | } |
386c036b | 1351 | regcache_cooked_write (regcache, SPARC_O0_REGNUM, buf); |
c906108c SS |
1352 | } |
1353 | } | |
1354 | ||
b9d4c5ed | 1355 | static enum return_value_convention |
c055b101 CV |
1356 | sparc32_return_value (struct gdbarch *gdbarch, struct type *func_type, |
1357 | struct type *type, struct regcache *regcache, | |
1358 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
b9d4c5ed | 1359 | { |
e17a4113 UW |
1360 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1361 | ||
0a8f48b9 MK |
1362 | /* The psABI says that "...every stack frame reserves the word at |
1363 | %fp+64. If a function returns a structure, union, or | |
1364 | quad-precision value, this word should hold the address of the | |
1365 | object into which the return value should be copied." This | |
1366 | guarantees that we can always find the return value, not just | |
1367 | before the function returns. */ | |
1368 | ||
b9d4c5ed MK |
1369 | if (sparc_structure_or_union_p (type) |
1370 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)) | |
0a8f48b9 MK |
1371 | { |
1372 | if (readbuf) | |
1373 | { | |
1374 | ULONGEST sp; | |
1375 | CORE_ADDR addr; | |
1376 | ||
1377 | regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); | |
e17a4113 | 1378 | addr = read_memory_unsigned_integer (sp + 64, 4, byte_order); |
0a8f48b9 MK |
1379 | read_memory (addr, readbuf, TYPE_LENGTH (type)); |
1380 | } | |
1381 | ||
1382 | return RETURN_VALUE_ABI_PRESERVES_ADDRESS; | |
1383 | } | |
b9d4c5ed MK |
1384 | |
1385 | if (readbuf) | |
1386 | sparc32_extract_return_value (type, regcache, readbuf); | |
1387 | if (writebuf) | |
1388 | sparc32_store_return_value (type, regcache, writebuf); | |
1389 | ||
1390 | return RETURN_VALUE_REGISTER_CONVENTION; | |
1391 | } | |
1392 | ||
386c036b MK |
1393 | static int |
1394 | sparc32_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type) | |
c906108c | 1395 | { |
386c036b | 1396 | return (sparc_structure_or_union_p (type) |
fe10a582 DM |
1397 | || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16) |
1398 | || sparc_complex_floating_p (type)); | |
386c036b | 1399 | } |
c906108c | 1400 | |
aff37fc1 | 1401 | static int |
4a4e5149 | 1402 | sparc32_dwarf2_struct_return_p (struct frame_info *this_frame) |
aff37fc1 | 1403 | { |
236369e7 | 1404 | CORE_ADDR pc = get_frame_address_in_block (this_frame); |
aff37fc1 DM |
1405 | struct symbol *sym = find_pc_function (pc); |
1406 | ||
1407 | if (sym) | |
1408 | return sparc32_struct_return_from_sym (sym); | |
1409 | return 0; | |
1410 | } | |
1411 | ||
f5a9b87d DM |
1412 | static void |
1413 | sparc32_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
aff37fc1 | 1414 | struct dwarf2_frame_state_reg *reg, |
4a4e5149 | 1415 | struct frame_info *this_frame) |
f5a9b87d | 1416 | { |
aff37fc1 DM |
1417 | int off; |
1418 | ||
f5a9b87d DM |
1419 | switch (regnum) |
1420 | { | |
1421 | case SPARC_G0_REGNUM: | |
1422 | /* Since %g0 is always zero, there is no point in saving it, and | |
1423 | people will be inclined omit it from the CFI. Make sure we | |
1424 | don't warn about that. */ | |
1425 | reg->how = DWARF2_FRAME_REG_SAME_VALUE; | |
1426 | break; | |
1427 | case SPARC_SP_REGNUM: | |
1428 | reg->how = DWARF2_FRAME_REG_CFA; | |
1429 | break; | |
1430 | case SPARC32_PC_REGNUM: | |
f5a9b87d DM |
1431 | case SPARC32_NPC_REGNUM: |
1432 | reg->how = DWARF2_FRAME_REG_RA_OFFSET; | |
aff37fc1 | 1433 | off = 8; |
4a4e5149 | 1434 | if (sparc32_dwarf2_struct_return_p (this_frame)) |
aff37fc1 DM |
1435 | off += 4; |
1436 | if (regnum == SPARC32_NPC_REGNUM) | |
1437 | off += 4; | |
1438 | reg->loc.offset = off; | |
f5a9b87d DM |
1439 | break; |
1440 | } | |
1441 | } | |
1442 | ||
386c036b MK |
1443 | \f |
1444 | /* The SPARC Architecture doesn't have hardware single-step support, | |
1445 | and most operating systems don't implement it either, so we provide | |
1446 | software single-step mechanism. */ | |
c906108c | 1447 | |
386c036b | 1448 | static CORE_ADDR |
0b1b3e42 | 1449 | sparc_analyze_control_transfer (struct frame_info *frame, |
c893be75 | 1450 | CORE_ADDR pc, CORE_ADDR *npc) |
386c036b MK |
1451 | { |
1452 | unsigned long insn = sparc_fetch_instruction (pc); | |
1453 | int conditional_p = X_COND (insn) & 0x7; | |
1454 | int branch_p = 0; | |
1455 | long offset = 0; /* Must be signed for sign-extend. */ | |
c906108c | 1456 | |
386c036b | 1457 | if (X_OP (insn) == 0 && X_OP2 (insn) == 3 && (insn & 0x1000000) == 0) |
c906108c | 1458 | { |
386c036b MK |
1459 | /* Branch on Integer Register with Prediction (BPr). */ |
1460 | branch_p = 1; | |
1461 | conditional_p = 1; | |
c906108c | 1462 | } |
386c036b | 1463 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 6) |
c906108c | 1464 | { |
386c036b MK |
1465 | /* Branch on Floating-Point Condition Codes (FBfcc). */ |
1466 | branch_p = 1; | |
1467 | offset = 4 * X_DISP22 (insn); | |
c906108c | 1468 | } |
386c036b MK |
1469 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 5) |
1470 | { | |
1471 | /* Branch on Floating-Point Condition Codes with Prediction | |
1472 | (FBPfcc). */ | |
1473 | branch_p = 1; | |
1474 | offset = 4 * X_DISP19 (insn); | |
1475 | } | |
1476 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 2) | |
1477 | { | |
1478 | /* Branch on Integer Condition Codes (Bicc). */ | |
1479 | branch_p = 1; | |
1480 | offset = 4 * X_DISP22 (insn); | |
1481 | } | |
1482 | else if (X_OP (insn) == 0 && X_OP2 (insn) == 1) | |
c906108c | 1483 | { |
386c036b MK |
1484 | /* Branch on Integer Condition Codes with Prediction (BPcc). */ |
1485 | branch_p = 1; | |
1486 | offset = 4 * X_DISP19 (insn); | |
c906108c | 1487 | } |
c893be75 MK |
1488 | else if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3a) |
1489 | { | |
1490 | /* Trap instruction (TRAP). */ | |
0b1b3e42 | 1491 | return gdbarch_tdep (get_frame_arch (frame))->step_trap (frame, insn); |
c893be75 | 1492 | } |
386c036b MK |
1493 | |
1494 | /* FIXME: Handle DONE and RETRY instructions. */ | |
1495 | ||
386c036b | 1496 | if (branch_p) |
c906108c | 1497 | { |
386c036b | 1498 | if (conditional_p) |
c906108c | 1499 | { |
386c036b MK |
1500 | /* For conditional branches, return nPC + 4 iff the annul |
1501 | bit is 1. */ | |
1502 | return (X_A (insn) ? *npc + 4 : 0); | |
c906108c SS |
1503 | } |
1504 | else | |
1505 | { | |
386c036b MK |
1506 | /* For unconditional branches, return the target if its |
1507 | specified condition is "always" and return nPC + 4 if the | |
1508 | condition is "never". If the annul bit is 1, set *NPC to | |
1509 | zero. */ | |
1510 | if (X_COND (insn) == 0x0) | |
1511 | pc = *npc, offset = 4; | |
1512 | if (X_A (insn)) | |
1513 | *npc = 0; | |
1514 | ||
1515 | gdb_assert (offset != 0); | |
1516 | return pc + offset; | |
c906108c SS |
1517 | } |
1518 | } | |
386c036b MK |
1519 | |
1520 | return 0; | |
c906108c SS |
1521 | } |
1522 | ||
c893be75 | 1523 | static CORE_ADDR |
0b1b3e42 | 1524 | sparc_step_trap (struct frame_info *frame, unsigned long insn) |
c893be75 MK |
1525 | { |
1526 | return 0; | |
1527 | } | |
1528 | ||
e6590a1b | 1529 | int |
0b1b3e42 | 1530 | sparc_software_single_step (struct frame_info *frame) |
386c036b | 1531 | { |
0b1b3e42 | 1532 | struct gdbarch *arch = get_frame_arch (frame); |
c893be75 | 1533 | struct gdbarch_tdep *tdep = gdbarch_tdep (arch); |
6c95b8df | 1534 | struct address_space *aspace = get_frame_address_space (frame); |
8181d85f | 1535 | CORE_ADDR npc, nnpc; |
c906108c | 1536 | |
e0cd558a | 1537 | CORE_ADDR pc, orig_npc; |
c906108c | 1538 | |
0b1b3e42 UW |
1539 | pc = get_frame_register_unsigned (frame, tdep->pc_regnum); |
1540 | orig_npc = npc = get_frame_register_unsigned (frame, tdep->npc_regnum); | |
c906108c | 1541 | |
e0cd558a | 1542 | /* Analyze the instruction at PC. */ |
0b1b3e42 | 1543 | nnpc = sparc_analyze_control_transfer (frame, pc, &npc); |
e0cd558a | 1544 | if (npc != 0) |
6c95b8df | 1545 | insert_single_step_breakpoint (arch, aspace, npc); |
8181d85f | 1546 | |
e0cd558a | 1547 | if (nnpc != 0) |
6c95b8df | 1548 | insert_single_step_breakpoint (arch, aspace, nnpc); |
c906108c | 1549 | |
e0cd558a UW |
1550 | /* Assert that we have set at least one breakpoint, and that |
1551 | they're not set at the same spot - unless we're going | |
1552 | from here straight to NULL, i.e. a call or jump to 0. */ | |
1553 | gdb_assert (npc != 0 || nnpc != 0 || orig_npc == 0); | |
1554 | gdb_assert (nnpc != npc || orig_npc == 0); | |
e6590a1b UW |
1555 | |
1556 | return 1; | |
386c036b MK |
1557 | } |
1558 | ||
1559 | static void | |
61a1198a | 1560 | sparc_write_pc (struct regcache *regcache, CORE_ADDR pc) |
386c036b | 1561 | { |
61a1198a | 1562 | struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache)); |
386c036b | 1563 | |
61a1198a UW |
1564 | regcache_cooked_write_unsigned (regcache, tdep->pc_regnum, pc); |
1565 | regcache_cooked_write_unsigned (regcache, tdep->npc_regnum, pc + 4); | |
386c036b MK |
1566 | } |
1567 | \f | |
5af923b0 | 1568 | |
a54124c5 MK |
1569 | /* Return the appropriate register set for the core section identified |
1570 | by SECT_NAME and SECT_SIZE. */ | |
1571 | ||
63807e1d | 1572 | static const struct regset * |
a54124c5 MK |
1573 | sparc_regset_from_core_section (struct gdbarch *gdbarch, |
1574 | const char *sect_name, size_t sect_size) | |
1575 | { | |
1576 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
1577 | ||
c558d81a | 1578 | if (strcmp (sect_name, ".reg") == 0 && sect_size >= tdep->sizeof_gregset) |
a54124c5 MK |
1579 | return tdep->gregset; |
1580 | ||
c558d81a | 1581 | if (strcmp (sect_name, ".reg2") == 0 && sect_size >= tdep->sizeof_fpregset) |
a54124c5 MK |
1582 | return tdep->fpregset; |
1583 | ||
1584 | return NULL; | |
1585 | } | |
1586 | \f | |
1587 | ||
386c036b MK |
1588 | static struct gdbarch * |
1589 | sparc32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
1590 | { | |
1591 | struct gdbarch_tdep *tdep; | |
1592 | struct gdbarch *gdbarch; | |
c906108c | 1593 | |
386c036b MK |
1594 | /* If there is already a candidate, use it. */ |
1595 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
1596 | if (arches != NULL) | |
1597 | return arches->gdbarch; | |
c906108c | 1598 | |
386c036b | 1599 | /* Allocate space for the new architecture. */ |
1390fcc2 | 1600 | tdep = XZALLOC (struct gdbarch_tdep); |
386c036b | 1601 | gdbarch = gdbarch_alloc (&info, tdep); |
5af923b0 | 1602 | |
386c036b MK |
1603 | tdep->pc_regnum = SPARC32_PC_REGNUM; |
1604 | tdep->npc_regnum = SPARC32_NPC_REGNUM; | |
c893be75 | 1605 | tdep->step_trap = sparc_step_trap; |
386c036b MK |
1606 | |
1607 | set_gdbarch_long_double_bit (gdbarch, 128); | |
8da61cc4 | 1608 | set_gdbarch_long_double_format (gdbarch, floatformats_sparc_quad); |
386c036b MK |
1609 | |
1610 | set_gdbarch_num_regs (gdbarch, SPARC32_NUM_REGS); | |
1611 | set_gdbarch_register_name (gdbarch, sparc32_register_name); | |
1612 | set_gdbarch_register_type (gdbarch, sparc32_register_type); | |
1613 | set_gdbarch_num_pseudo_regs (gdbarch, SPARC32_NUM_PSEUDO_REGS); | |
1614 | set_gdbarch_pseudo_register_read (gdbarch, sparc32_pseudo_register_read); | |
1615 | set_gdbarch_pseudo_register_write (gdbarch, sparc32_pseudo_register_write); | |
1616 | ||
1617 | /* Register numbers of various important registers. */ | |
1618 | set_gdbarch_sp_regnum (gdbarch, SPARC_SP_REGNUM); /* %sp */ | |
1619 | set_gdbarch_pc_regnum (gdbarch, SPARC32_PC_REGNUM); /* %pc */ | |
1620 | set_gdbarch_fp0_regnum (gdbarch, SPARC_F0_REGNUM); /* %f0 */ | |
1621 | ||
1622 | /* Call dummy code. */ | |
49a45ecf | 1623 | set_gdbarch_frame_align (gdbarch, sparc32_frame_align); |
386c036b MK |
1624 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); |
1625 | set_gdbarch_push_dummy_code (gdbarch, sparc32_push_dummy_code); | |
1626 | set_gdbarch_push_dummy_call (gdbarch, sparc32_push_dummy_call); | |
1627 | ||
b9d4c5ed | 1628 | set_gdbarch_return_value (gdbarch, sparc32_return_value); |
386c036b MK |
1629 | set_gdbarch_stabs_argument_has_addr |
1630 | (gdbarch, sparc32_stabs_argument_has_addr); | |
1631 | ||
1632 | set_gdbarch_skip_prologue (gdbarch, sparc32_skip_prologue); | |
1633 | ||
1634 | /* Stack grows downward. */ | |
1635 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
c906108c | 1636 | |
386c036b | 1637 | set_gdbarch_breakpoint_from_pc (gdbarch, sparc_breakpoint_from_pc); |
c906108c | 1638 | |
386c036b | 1639 | set_gdbarch_frame_args_skip (gdbarch, 8); |
5af923b0 | 1640 | |
386c036b | 1641 | set_gdbarch_print_insn (gdbarch, print_insn_sparc); |
c906108c | 1642 | |
386c036b MK |
1643 | set_gdbarch_software_single_step (gdbarch, sparc_software_single_step); |
1644 | set_gdbarch_write_pc (gdbarch, sparc_write_pc); | |
c906108c | 1645 | |
236369e7 | 1646 | set_gdbarch_dummy_id (gdbarch, sparc_dummy_id); |
c906108c | 1647 | |
386c036b | 1648 | set_gdbarch_unwind_pc (gdbarch, sparc_unwind_pc); |
c906108c | 1649 | |
386c036b MK |
1650 | frame_base_set_default (gdbarch, &sparc32_frame_base); |
1651 | ||
f5a9b87d DM |
1652 | /* Hook in the DWARF CFI frame unwinder. */ |
1653 | dwarf2_frame_set_init_reg (gdbarch, sparc32_dwarf2_frame_init_reg); | |
1654 | /* FIXME: kettenis/20050423: Don't enable the unwinder until the | |
1655 | StackGhost issues have been resolved. */ | |
1656 | ||
b2a0b9b2 DM |
1657 | /* Hook in ABI-specific overrides, if they have been registered. */ |
1658 | gdbarch_init_osabi (info, gdbarch); | |
1659 | ||
236369e7 | 1660 | frame_unwind_append_unwinder (gdbarch, &sparc32_frame_unwind); |
c906108c | 1661 | |
a54124c5 | 1662 | /* If we have register sets, enable the generic core file support. */ |
4c72d57a | 1663 | if (tdep->gregset) |
a54124c5 MK |
1664 | set_gdbarch_regset_from_core_section (gdbarch, |
1665 | sparc_regset_from_core_section); | |
1666 | ||
386c036b MK |
1667 | return gdbarch; |
1668 | } | |
1669 | \f | |
1670 | /* Helper functions for dealing with register windows. */ | |
1671 | ||
1672 | void | |
1673 | sparc_supply_rwindow (struct regcache *regcache, CORE_ADDR sp, int regnum) | |
c906108c | 1674 | { |
e17a4113 UW |
1675 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
1676 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
386c036b | 1677 | int offset = 0; |
e1613aba | 1678 | gdb_byte buf[8]; |
386c036b MK |
1679 | int i; |
1680 | ||
1681 | if (sp & 1) | |
1682 | { | |
1683 | /* Registers are 64-bit. */ | |
1684 | sp += BIAS; | |
c906108c | 1685 | |
386c036b MK |
1686 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1687 | { | |
1688 | if (regnum == i || regnum == -1) | |
1689 | { | |
1690 | target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8); | |
f700a364 MK |
1691 | |
1692 | /* Handle StackGhost. */ | |
1693 | if (i == SPARC_I7_REGNUM) | |
1694 | { | |
e17a4113 UW |
1695 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
1696 | ULONGEST i7; | |
f700a364 | 1697 | |
e17a4113 UW |
1698 | i7 = extract_unsigned_integer (buf + offset, 8, byte_order); |
1699 | store_unsigned_integer (buf + offset, 8, byte_order, | |
1700 | i7 ^ wcookie); | |
f700a364 MK |
1701 | } |
1702 | ||
386c036b MK |
1703 | regcache_raw_supply (regcache, i, buf); |
1704 | } | |
1705 | } | |
1706 | } | |
1707 | else | |
c906108c | 1708 | { |
386c036b MK |
1709 | /* Registers are 32-bit. Toss any sign-extension of the stack |
1710 | pointer. */ | |
1711 | sp &= 0xffffffffUL; | |
c906108c | 1712 | |
386c036b MK |
1713 | /* Clear out the top half of the temporary buffer, and put the |
1714 | register value in the bottom half if we're in 64-bit mode. */ | |
e6d4f032 | 1715 | if (gdbarch_ptr_bit (get_regcache_arch (regcache)) == 64) |
c906108c | 1716 | { |
386c036b MK |
1717 | memset (buf, 0, 4); |
1718 | offset = 4; | |
1719 | } | |
c906108c | 1720 | |
386c036b MK |
1721 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1722 | { | |
1723 | if (regnum == i || regnum == -1) | |
1724 | { | |
1725 | target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 4), | |
1726 | buf + offset, 4); | |
42cdca6c MK |
1727 | |
1728 | /* Handle StackGhost. */ | |
1729 | if (i == SPARC_I7_REGNUM) | |
1730 | { | |
e17a4113 UW |
1731 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
1732 | ULONGEST i7; | |
42cdca6c | 1733 | |
e17a4113 UW |
1734 | i7 = extract_unsigned_integer (buf + offset, 4, byte_order); |
1735 | store_unsigned_integer (buf + offset, 4, byte_order, | |
1736 | i7 ^ wcookie); | |
42cdca6c MK |
1737 | } |
1738 | ||
386c036b MK |
1739 | regcache_raw_supply (regcache, i, buf); |
1740 | } | |
c906108c SS |
1741 | } |
1742 | } | |
c906108c | 1743 | } |
c906108c SS |
1744 | |
1745 | void | |
386c036b MK |
1746 | sparc_collect_rwindow (const struct regcache *regcache, |
1747 | CORE_ADDR sp, int regnum) | |
c906108c | 1748 | { |
e17a4113 UW |
1749 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
1750 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
386c036b | 1751 | int offset = 0; |
e1613aba | 1752 | gdb_byte buf[8]; |
386c036b | 1753 | int i; |
5af923b0 | 1754 | |
386c036b | 1755 | if (sp & 1) |
5af923b0 | 1756 | { |
386c036b MK |
1757 | /* Registers are 64-bit. */ |
1758 | sp += BIAS; | |
c906108c | 1759 | |
386c036b MK |
1760 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) |
1761 | { | |
1762 | if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i) | |
1763 | { | |
1764 | regcache_raw_collect (regcache, i, buf); | |
f700a364 MK |
1765 | |
1766 | /* Handle StackGhost. */ | |
1767 | if (i == SPARC_I7_REGNUM) | |
1768 | { | |
e17a4113 UW |
1769 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
1770 | ULONGEST i7; | |
f700a364 | 1771 | |
e17a4113 UW |
1772 | i7 = extract_unsigned_integer (buf + offset, 8, byte_order); |
1773 | store_unsigned_integer (buf, 8, byte_order, i7 ^ wcookie); | |
f700a364 MK |
1774 | } |
1775 | ||
386c036b MK |
1776 | target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8); |
1777 | } | |
1778 | } | |
5af923b0 MS |
1779 | } |
1780 | else | |
1781 | { | |
386c036b MK |
1782 | /* Registers are 32-bit. Toss any sign-extension of the stack |
1783 | pointer. */ | |
1784 | sp &= 0xffffffffUL; | |
1785 | ||
1786 | /* Only use the bottom half if we're in 64-bit mode. */ | |
e6d4f032 | 1787 | if (gdbarch_ptr_bit (get_regcache_arch (regcache)) == 64) |
386c036b MK |
1788 | offset = 4; |
1789 | ||
1790 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
1791 | { | |
1792 | if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i) | |
1793 | { | |
1794 | regcache_raw_collect (regcache, i, buf); | |
42cdca6c MK |
1795 | |
1796 | /* Handle StackGhost. */ | |
1797 | if (i == SPARC_I7_REGNUM) | |
1798 | { | |
e17a4113 UW |
1799 | ULONGEST wcookie = sparc_fetch_wcookie (gdbarch); |
1800 | ULONGEST i7; | |
42cdca6c | 1801 | |
e17a4113 UW |
1802 | i7 = extract_unsigned_integer (buf + offset, 4, byte_order); |
1803 | store_unsigned_integer (buf + offset, 4, byte_order, | |
1804 | i7 ^ wcookie); | |
42cdca6c MK |
1805 | } |
1806 | ||
386c036b MK |
1807 | target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 4), |
1808 | buf + offset, 4); | |
1809 | } | |
1810 | } | |
5af923b0 | 1811 | } |
c906108c SS |
1812 | } |
1813 | ||
386c036b MK |
1814 | /* Helper functions for dealing with register sets. */ |
1815 | ||
c906108c | 1816 | void |
386c036b MK |
1817 | sparc32_supply_gregset (const struct sparc_gregset *gregset, |
1818 | struct regcache *regcache, | |
1819 | int regnum, const void *gregs) | |
c906108c | 1820 | { |
e1613aba | 1821 | const gdb_byte *regs = gregs; |
22e74ef9 | 1822 | gdb_byte zero[4] = { 0 }; |
386c036b | 1823 | int i; |
5af923b0 | 1824 | |
386c036b MK |
1825 | if (regnum == SPARC32_PSR_REGNUM || regnum == -1) |
1826 | regcache_raw_supply (regcache, SPARC32_PSR_REGNUM, | |
1827 | regs + gregset->r_psr_offset); | |
c906108c | 1828 | |
386c036b MK |
1829 | if (regnum == SPARC32_PC_REGNUM || regnum == -1) |
1830 | regcache_raw_supply (regcache, SPARC32_PC_REGNUM, | |
1831 | regs + gregset->r_pc_offset); | |
5af923b0 | 1832 | |
386c036b MK |
1833 | if (regnum == SPARC32_NPC_REGNUM || regnum == -1) |
1834 | regcache_raw_supply (regcache, SPARC32_NPC_REGNUM, | |
1835 | regs + gregset->r_npc_offset); | |
5af923b0 | 1836 | |
386c036b MK |
1837 | if (regnum == SPARC32_Y_REGNUM || regnum == -1) |
1838 | regcache_raw_supply (regcache, SPARC32_Y_REGNUM, | |
1839 | regs + gregset->r_y_offset); | |
5af923b0 | 1840 | |
386c036b | 1841 | if (regnum == SPARC_G0_REGNUM || regnum == -1) |
22e74ef9 | 1842 | regcache_raw_supply (regcache, SPARC_G0_REGNUM, &zero); |
5af923b0 | 1843 | |
386c036b | 1844 | if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1) |
c906108c | 1845 | { |
386c036b MK |
1846 | int offset = gregset->r_g1_offset; |
1847 | ||
1848 | for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++) | |
1849 | { | |
1850 | if (regnum == i || regnum == -1) | |
1851 | regcache_raw_supply (regcache, i, regs + offset); | |
1852 | offset += 4; | |
1853 | } | |
c906108c | 1854 | } |
386c036b MK |
1855 | |
1856 | if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1) | |
c906108c | 1857 | { |
386c036b MK |
1858 | /* Not all of the register set variants include Locals and |
1859 | Inputs. For those that don't, we read them off the stack. */ | |
1860 | if (gregset->r_l0_offset == -1) | |
1861 | { | |
1862 | ULONGEST sp; | |
1863 | ||
1864 | regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp); | |
1865 | sparc_supply_rwindow (regcache, sp, regnum); | |
1866 | } | |
1867 | else | |
1868 | { | |
1869 | int offset = gregset->r_l0_offset; | |
1870 | ||
1871 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
1872 | { | |
1873 | if (regnum == i || regnum == -1) | |
1874 | regcache_raw_supply (regcache, i, regs + offset); | |
1875 | offset += 4; | |
1876 | } | |
1877 | } | |
c906108c SS |
1878 | } |
1879 | } | |
1880 | ||
c5aa993b | 1881 | void |
386c036b MK |
1882 | sparc32_collect_gregset (const struct sparc_gregset *gregset, |
1883 | const struct regcache *regcache, | |
1884 | int regnum, void *gregs) | |
c906108c | 1885 | { |
e1613aba | 1886 | gdb_byte *regs = gregs; |
386c036b | 1887 | int i; |
c5aa993b | 1888 | |
386c036b MK |
1889 | if (regnum == SPARC32_PSR_REGNUM || regnum == -1) |
1890 | regcache_raw_collect (regcache, SPARC32_PSR_REGNUM, | |
1891 | regs + gregset->r_psr_offset); | |
60054393 | 1892 | |
386c036b MK |
1893 | if (regnum == SPARC32_PC_REGNUM || regnum == -1) |
1894 | regcache_raw_collect (regcache, SPARC32_PC_REGNUM, | |
1895 | regs + gregset->r_pc_offset); | |
1896 | ||
1897 | if (regnum == SPARC32_NPC_REGNUM || regnum == -1) | |
1898 | regcache_raw_collect (regcache, SPARC32_NPC_REGNUM, | |
1899 | regs + gregset->r_npc_offset); | |
5af923b0 | 1900 | |
386c036b MK |
1901 | if (regnum == SPARC32_Y_REGNUM || regnum == -1) |
1902 | regcache_raw_collect (regcache, SPARC32_Y_REGNUM, | |
1903 | regs + gregset->r_y_offset); | |
1904 | ||
1905 | if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1) | |
5af923b0 | 1906 | { |
386c036b MK |
1907 | int offset = gregset->r_g1_offset; |
1908 | ||
1909 | /* %g0 is always zero. */ | |
1910 | for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++) | |
1911 | { | |
1912 | if (regnum == i || regnum == -1) | |
1913 | regcache_raw_collect (regcache, i, regs + offset); | |
1914 | offset += 4; | |
1915 | } | |
5af923b0 | 1916 | } |
386c036b MK |
1917 | |
1918 | if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1) | |
5af923b0 | 1919 | { |
386c036b MK |
1920 | /* Not all of the register set variants include Locals and |
1921 | Inputs. For those that don't, we read them off the stack. */ | |
1922 | if (gregset->r_l0_offset != -1) | |
1923 | { | |
1924 | int offset = gregset->r_l0_offset; | |
1925 | ||
1926 | for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++) | |
1927 | { | |
1928 | if (regnum == i || regnum == -1) | |
1929 | regcache_raw_collect (regcache, i, regs + offset); | |
1930 | offset += 4; | |
1931 | } | |
1932 | } | |
5af923b0 | 1933 | } |
c906108c SS |
1934 | } |
1935 | ||
c906108c | 1936 | void |
386c036b MK |
1937 | sparc32_supply_fpregset (struct regcache *regcache, |
1938 | int regnum, const void *fpregs) | |
c906108c | 1939 | { |
e1613aba | 1940 | const gdb_byte *regs = fpregs; |
386c036b | 1941 | int i; |
60054393 | 1942 | |
386c036b | 1943 | for (i = 0; i < 32; i++) |
c906108c | 1944 | { |
386c036b MK |
1945 | if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1) |
1946 | regcache_raw_supply (regcache, SPARC_F0_REGNUM + i, regs + (i * 4)); | |
c906108c | 1947 | } |
5af923b0 | 1948 | |
386c036b MK |
1949 | if (regnum == SPARC32_FSR_REGNUM || regnum == -1) |
1950 | regcache_raw_supply (regcache, SPARC32_FSR_REGNUM, regs + (32 * 4) + 4); | |
c906108c SS |
1951 | } |
1952 | ||
386c036b MK |
1953 | void |
1954 | sparc32_collect_fpregset (const struct regcache *regcache, | |
1955 | int regnum, void *fpregs) | |
c906108c | 1956 | { |
e1613aba | 1957 | gdb_byte *regs = fpregs; |
386c036b | 1958 | int i; |
c906108c | 1959 | |
386c036b MK |
1960 | for (i = 0; i < 32; i++) |
1961 | { | |
1962 | if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1) | |
1963 | regcache_raw_collect (regcache, SPARC_F0_REGNUM + i, regs + (i * 4)); | |
1964 | } | |
c906108c | 1965 | |
386c036b MK |
1966 | if (regnum == SPARC32_FSR_REGNUM || regnum == -1) |
1967 | regcache_raw_collect (regcache, SPARC32_FSR_REGNUM, regs + (32 * 4) + 4); | |
c906108c | 1968 | } |
c906108c | 1969 | \f |
c906108c | 1970 | |
386c036b | 1971 | /* SunOS 4. */ |
c906108c | 1972 | |
386c036b MK |
1973 | /* From <machine/reg.h>. */ |
1974 | const struct sparc_gregset sparc32_sunos4_gregset = | |
c906108c | 1975 | { |
386c036b MK |
1976 | 0 * 4, /* %psr */ |
1977 | 1 * 4, /* %pc */ | |
1978 | 2 * 4, /* %npc */ | |
1979 | 3 * 4, /* %y */ | |
1980 | -1, /* %wim */ | |
1981 | -1, /* %tbr */ | |
1982 | 4 * 4, /* %g1 */ | |
1983 | -1 /* %l0 */ | |
1984 | }; | |
1985 | \f | |
c906108c | 1986 | |
386c036b MK |
1987 | /* Provide a prototype to silence -Wmissing-prototypes. */ |
1988 | void _initialize_sparc_tdep (void); | |
c906108c SS |
1989 | |
1990 | void | |
386c036b | 1991 | _initialize_sparc_tdep (void) |
c906108c | 1992 | { |
386c036b | 1993 | register_gdbarch_init (bfd_arch_sparc, sparc32_gdbarch_init); |
ef3cf062 | 1994 | } |